1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
244 static int meabi_flags
= EABI_DEFAULT
;
246 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
249 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
254 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
259 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
260 symbolS
* GOT_symbol
;
263 /* 0: assemble for ARM,
264 1: assemble for Thumb,
265 2: assemble for Thumb even though target CPU does not support thumb
267 static int thumb_mode
= 0;
268 /* A value distinct from the possible values for thumb_mode that we
269 can use to record whether thumb_mode has been copied into the
270 tc_frag_data field of a frag. */
271 #define MODE_RECORDED (1 << 4)
273 /* Specifies the intrinsic IT insn behavior mode. */
274 enum implicit_it_mode
276 IMPLICIT_IT_MODE_NEVER
= 0x00,
277 IMPLICIT_IT_MODE_ARM
= 0x01,
278 IMPLICIT_IT_MODE_THUMB
= 0x02,
279 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
281 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
283 /* If unified_syntax is true, we are processing the new unified
284 ARM/Thumb syntax. Important differences from the old ARM mode:
286 - Immediate operands do not require a # prefix.
287 - Conditional affixes always appear at the end of the
288 instruction. (For backward compatibility, those instructions
289 that formerly had them in the middle, continue to accept them
291 - The IT instruction may appear, and if it does is validated
292 against subsequent conditional affixes. It does not generate
295 Important differences from the old Thumb mode:
297 - Immediate operands do not require a # prefix.
298 - Most of the V6T2 instructions are only available in unified mode.
299 - The .N and .W suffixes are recognized and honored (it is an error
300 if they cannot be honored).
301 - All instructions set the flags if and only if they have an 's' affix.
302 - Conditional affixes may be used. They are validated against
303 preceding IT instructions. Unlike ARM mode, you cannot use a
304 conditional affix except in the scope of an IT instruction. */
306 static bfd_boolean unified_syntax
= FALSE
;
321 enum neon_el_type type
;
325 #define NEON_MAX_TYPE_ELS 4
329 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
333 enum it_instruction_type
338 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
339 if inside, should be the last one. */
340 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
341 i.e. BKPT and NOP. */
342 IT_INSN
/* The IT insn has been parsed. */
348 unsigned long instruction
;
352 /* "uncond_value" is set to the value in place of the conditional field in
353 unconditional versions of the instruction, or -1 if nothing is
356 struct neon_type vectype
;
357 /* This does not indicate an actual NEON instruction, only that
358 the mnemonic accepts neon-style type suffixes. */
360 /* Set to the opcode if the instruction needs relaxation.
361 Zero if the instruction is not relaxed. */
365 bfd_reloc_code_real_type type
;
370 enum it_instruction_type it_insn_type
;
376 struct neon_type_el vectype
;
377 unsigned present
: 1; /* Operand present. */
378 unsigned isreg
: 1; /* Operand was a register. */
379 unsigned immisreg
: 1; /* .imm field is a second register. */
380 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
381 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
382 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
383 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
384 instructions. This allows us to disambiguate ARM <-> vector insns. */
385 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
386 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
387 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
388 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
389 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
390 unsigned writeback
: 1; /* Operand has trailing ! */
391 unsigned preind
: 1; /* Preindexed address. */
392 unsigned postind
: 1; /* Postindexed address. */
393 unsigned negative
: 1; /* Index register was negated. */
394 unsigned shifted
: 1; /* Shift applied to operation. */
395 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
399 static struct arm_it inst
;
401 #define NUM_FLOAT_VALS 8
403 const char * fp_const
[] =
405 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
408 /* Number of littlenums required to hold an extended precision number. */
409 #define MAX_LITTLENUMS 6
411 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
421 #define CP_T_X 0x00008000
422 #define CP_T_Y 0x00400000
424 #define CONDS_BIT 0x00100000
425 #define LOAD_BIT 0x00100000
427 #define DOUBLE_LOAD_FLAG 0x00000001
431 const char * template_name
;
435 #define COND_ALWAYS 0xE
439 const char * template_name
;
443 struct asm_barrier_opt
445 const char * template_name
;
449 /* The bit that distinguishes CPSR and SPSR. */
450 #define SPSR_BIT (1 << 22)
452 /* The individual PSR flag bits. */
453 #define PSR_c (1 << 16)
454 #define PSR_x (1 << 17)
455 #define PSR_s (1 << 18)
456 #define PSR_f (1 << 19)
461 bfd_reloc_code_real_type reloc
;
466 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
467 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
472 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
475 /* Bits for DEFINED field in neon_typed_alias. */
476 #define NTA_HASTYPE 1
477 #define NTA_HASINDEX 2
479 struct neon_typed_alias
481 unsigned char defined
;
483 struct neon_type_el eltype
;
486 /* ARM register categories. This includes coprocessor numbers and various
487 architecture extensions' registers. */
514 /* Structure for a hash table entry for a register.
515 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
516 information which states whether a vector type or index is specified (for a
517 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
523 unsigned char builtin
;
524 struct neon_typed_alias
* neon
;
527 /* Diagnostics used when we don't get a register of the expected type. */
528 const char * const reg_expected_msgs
[] =
530 N_("ARM register expected"),
531 N_("bad or missing co-processor number"),
532 N_("co-processor register expected"),
533 N_("FPA register expected"),
534 N_("VFP single precision register expected"),
535 N_("VFP/Neon double precision register expected"),
536 N_("Neon quad precision register expected"),
537 N_("VFP single or double precision register expected"),
538 N_("Neon double or quad precision register expected"),
539 N_("VFP single, double or Neon quad precision register expected"),
540 N_("VFP system register expected"),
541 N_("Maverick MVF register expected"),
542 N_("Maverick MVD register expected"),
543 N_("Maverick MVFX register expected"),
544 N_("Maverick MVDX register expected"),
545 N_("Maverick MVAX register expected"),
546 N_("Maverick DSPSC register expected"),
547 N_("iWMMXt data register expected"),
548 N_("iWMMXt control register expected"),
549 N_("iWMMXt scalar register expected"),
550 N_("XScale accumulator register expected"),
553 /* Some well known registers that we refer to directly elsewhere. */
558 /* ARM instructions take 4bytes in the object file, Thumb instructions
564 /* Basic string to match. */
565 const char * template_name
;
567 /* Parameters to instruction. */
568 unsigned int operands
[8];
570 /* Conditional tag - see opcode_lookup. */
571 unsigned int tag
: 4;
573 /* Basic instruction code. */
574 unsigned int avalue
: 28;
576 /* Thumb-format instruction code. */
579 /* Which architecture variant provides this instruction. */
580 const arm_feature_set
* avariant
;
581 const arm_feature_set
* tvariant
;
583 /* Function to call to encode instruction in ARM format. */
584 void (* aencode
) (void);
586 /* Function to call to encode instruction in Thumb format. */
587 void (* tencode
) (void);
590 /* Defines for various bits that we will want to toggle. */
591 #define INST_IMMEDIATE 0x02000000
592 #define OFFSET_REG 0x02000000
593 #define HWOFFSET_IMM 0x00400000
594 #define SHIFT_BY_REG 0x00000010
595 #define PRE_INDEX 0x01000000
596 #define INDEX_UP 0x00800000
597 #define WRITE_BACK 0x00200000
598 #define LDM_TYPE_2_OR_3 0x00400000
599 #define CPSI_MMOD 0x00020000
601 #define LITERAL_MASK 0xf000f000
602 #define OPCODE_MASK 0xfe1fffff
603 #define V4_STR_BIT 0x00000020
605 #define T2_SUBS_PC_LR 0xf3de8f00
607 #define DATA_OP_SHIFT 21
609 #define T2_OPCODE_MASK 0xfe1fffff
610 #define T2_DATA_OP_SHIFT 21
612 /* Codes to distinguish the arithmetic instructions. */
623 #define OPCODE_CMP 10
624 #define OPCODE_CMN 11
625 #define OPCODE_ORR 12
626 #define OPCODE_MOV 13
627 #define OPCODE_BIC 14
628 #define OPCODE_MVN 15
630 #define T2_OPCODE_AND 0
631 #define T2_OPCODE_BIC 1
632 #define T2_OPCODE_ORR 2
633 #define T2_OPCODE_ORN 3
634 #define T2_OPCODE_EOR 4
635 #define T2_OPCODE_ADD 8
636 #define T2_OPCODE_ADC 10
637 #define T2_OPCODE_SBC 11
638 #define T2_OPCODE_SUB 13
639 #define T2_OPCODE_RSB 14
641 #define T_OPCODE_MUL 0x4340
642 #define T_OPCODE_TST 0x4200
643 #define T_OPCODE_CMN 0x42c0
644 #define T_OPCODE_NEG 0x4240
645 #define T_OPCODE_MVN 0x43c0
647 #define T_OPCODE_ADD_R3 0x1800
648 #define T_OPCODE_SUB_R3 0x1a00
649 #define T_OPCODE_ADD_HI 0x4400
650 #define T_OPCODE_ADD_ST 0xb000
651 #define T_OPCODE_SUB_ST 0xb080
652 #define T_OPCODE_ADD_SP 0xa800
653 #define T_OPCODE_ADD_PC 0xa000
654 #define T_OPCODE_ADD_I8 0x3000
655 #define T_OPCODE_SUB_I8 0x3800
656 #define T_OPCODE_ADD_I3 0x1c00
657 #define T_OPCODE_SUB_I3 0x1e00
659 #define T_OPCODE_ASR_R 0x4100
660 #define T_OPCODE_LSL_R 0x4080
661 #define T_OPCODE_LSR_R 0x40c0
662 #define T_OPCODE_ROR_R 0x41c0
663 #define T_OPCODE_ASR_I 0x1000
664 #define T_OPCODE_LSL_I 0x0000
665 #define T_OPCODE_LSR_I 0x0800
667 #define T_OPCODE_MOV_I8 0x2000
668 #define T_OPCODE_CMP_I8 0x2800
669 #define T_OPCODE_CMP_LR 0x4280
670 #define T_OPCODE_MOV_HR 0x4600
671 #define T_OPCODE_CMP_HR 0x4500
673 #define T_OPCODE_LDR_PC 0x4800
674 #define T_OPCODE_LDR_SP 0x9800
675 #define T_OPCODE_STR_SP 0x9000
676 #define T_OPCODE_LDR_IW 0x6800
677 #define T_OPCODE_STR_IW 0x6000
678 #define T_OPCODE_LDR_IH 0x8800
679 #define T_OPCODE_STR_IH 0x8000
680 #define T_OPCODE_LDR_IB 0x7800
681 #define T_OPCODE_STR_IB 0x7000
682 #define T_OPCODE_LDR_RW 0x5800
683 #define T_OPCODE_STR_RW 0x5000
684 #define T_OPCODE_LDR_RH 0x5a00
685 #define T_OPCODE_STR_RH 0x5200
686 #define T_OPCODE_LDR_RB 0x5c00
687 #define T_OPCODE_STR_RB 0x5400
689 #define T_OPCODE_PUSH 0xb400
690 #define T_OPCODE_POP 0xbc00
692 #define T_OPCODE_BRANCH 0xe000
694 #define THUMB_SIZE 2 /* Size of thumb instruction. */
695 #define THUMB_PP_PC_LR 0x0100
696 #define THUMB_LOAD_BIT 0x0800
697 #define THUMB2_LOAD_BIT 0x00100000
699 #define BAD_ARGS _("bad arguments to instruction")
700 #define BAD_SP _("r13 not allowed here")
701 #define BAD_PC _("r15 not allowed here")
702 #define BAD_COND _("instruction cannot be conditional")
703 #define BAD_OVERLAP _("registers may not be the same")
704 #define BAD_HIREG _("lo register required")
705 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
706 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
707 #define BAD_BRANCH _("branch must be last instruction in IT block")
708 #define BAD_NOT_IT _("instruction not allowed in IT block")
709 #define BAD_FPU _("selected FPU does not support instruction")
710 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
711 #define BAD_IT_COND _("incorrect condition in IT block")
712 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
713 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
714 #define BAD_PC_ADDRESSING \
715 _("cannot use register index with PC-relative addressing")
716 #define BAD_PC_WRITEBACK \
717 _("cannot use writeback with PC-relative addressing")
719 static struct hash_control
* arm_ops_hsh
;
720 static struct hash_control
* arm_cond_hsh
;
721 static struct hash_control
* arm_shift_hsh
;
722 static struct hash_control
* arm_psr_hsh
;
723 static struct hash_control
* arm_v7m_psr_hsh
;
724 static struct hash_control
* arm_reg_hsh
;
725 static struct hash_control
* arm_reloc_hsh
;
726 static struct hash_control
* arm_barrier_opt_hsh
;
728 /* Stuff needed to resolve the label ambiguity
737 symbolS
* last_label_seen
;
738 static int label_is_thumb_function_name
= FALSE
;
740 /* Literal pool structure. Held on a per-section
741 and per-sub-section basis. */
743 #define MAX_LITERAL_POOL_SIZE 1024
744 typedef struct literal_pool
746 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
747 unsigned int next_free_entry
;
752 struct literal_pool
* next
;
755 /* Pointer to a linked list of literal pools. */
756 literal_pool
* list_of_pools
= NULL
;
759 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
761 static struct current_it now_it
;
765 now_it_compatible (int cond
)
767 return (cond
& ~1) == (now_it
.cc
& ~1);
771 conditional_insn (void)
773 return inst
.cond
!= COND_ALWAYS
;
776 static int in_it_block (void);
778 static int handle_it_state (void);
780 static void force_automatic_it_block_close (void);
782 static void it_fsm_post_encode (void);
784 #define set_it_insn_type(type) \
787 inst.it_insn_type = type; \
788 if (handle_it_state () == FAIL) \
793 #define set_it_insn_type_nonvoid(type, failret) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_last() \
805 if (inst.cond == COND_ALWAYS) \
806 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
808 set_it_insn_type (INSIDE_IT_LAST_INSN); \
814 /* This array holds the chars that always start a comment. If the
815 pre-processor is disabled, these aren't very useful. */
816 const char comment_chars
[] = "@";
818 /* This array holds the chars that only start a comment at the beginning of
819 a line. If the line seems to have the form '# 123 filename'
820 .line and .file directives will appear in the pre-processed output. */
821 /* Note that input_file.c hand checks for '#' at the beginning of the
822 first line of the input file. This is because the compiler outputs
823 #NO_APP at the beginning of its output. */
824 /* Also note that comments like this one will always work. */
825 const char line_comment_chars
[] = "#";
827 const char line_separator_chars
[] = ";";
829 /* Chars that can be used to separate mant
830 from exp in floating point numbers. */
831 const char EXP_CHARS
[] = "eE";
833 /* Chars that mean this number is a floating point constant. */
837 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
839 /* Prefix characters that indicate the start of an immediate
841 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
843 /* Separator character handling. */
845 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
848 skip_past_char (char ** str
, char c
)
859 #define skip_past_comma(str) skip_past_char (str, ',')
861 /* Arithmetic expressions (possibly involving symbols). */
863 /* Return TRUE if anything in the expression is a bignum. */
866 walk_no_bignums (symbolS
* sp
)
868 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
871 if (symbol_get_value_expression (sp
)->X_add_symbol
)
873 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
874 || (symbol_get_value_expression (sp
)->X_op_symbol
875 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
881 static int in_my_get_expression
= 0;
883 /* Third argument to my_get_expression. */
884 #define GE_NO_PREFIX 0
885 #define GE_IMM_PREFIX 1
886 #define GE_OPT_PREFIX 2
887 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
888 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
889 #define GE_OPT_PREFIX_BIG 3
892 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
897 /* In unified syntax, all prefixes are optional. */
899 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
904 case GE_NO_PREFIX
: break;
906 if (!is_immediate_prefix (**str
))
908 inst
.error
= _("immediate expression requires a # prefix");
914 case GE_OPT_PREFIX_BIG
:
915 if (is_immediate_prefix (**str
))
921 memset (ep
, 0, sizeof (expressionS
));
923 save_in
= input_line_pointer
;
924 input_line_pointer
= *str
;
925 in_my_get_expression
= 1;
926 seg
= expression (ep
);
927 in_my_get_expression
= 0;
929 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
931 /* We found a bad or missing expression in md_operand(). */
932 *str
= input_line_pointer
;
933 input_line_pointer
= save_in
;
934 if (inst
.error
== NULL
)
935 inst
.error
= (ep
->X_op
== O_absent
936 ? _("missing expression") :_("bad expression"));
941 if (seg
!= absolute_section
942 && seg
!= text_section
943 && seg
!= data_section
944 && seg
!= bss_section
945 && seg
!= undefined_section
)
947 inst
.error
= _("bad segment");
948 *str
= input_line_pointer
;
949 input_line_pointer
= save_in
;
956 /* Get rid of any bignums now, so that we don't generate an error for which
957 we can't establish a line number later on. Big numbers are never valid
958 in instructions, which is where this routine is always called. */
959 if (prefix_mode
!= GE_OPT_PREFIX_BIG
960 && (ep
->X_op
== O_big
962 && (walk_no_bignums (ep
->X_add_symbol
)
964 && walk_no_bignums (ep
->X_op_symbol
))))))
966 inst
.error
= _("invalid constant");
967 *str
= input_line_pointer
;
968 input_line_pointer
= save_in
;
972 *str
= input_line_pointer
;
973 input_line_pointer
= save_in
;
977 /* Turn a string in input_line_pointer into a floating point constant
978 of type TYPE, and store the appropriate bytes in *LITP. The number
979 of LITTLENUMS emitted is stored in *SIZEP. An error message is
980 returned, or NULL on OK.
982 Note that fp constants aren't represent in the normal way on the ARM.
983 In big endian mode, things are as expected. However, in little endian
984 mode fp constants are big-endian word-wise, and little-endian byte-wise
985 within the words. For example, (double) 1.1 in big endian mode is
986 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
987 the byte sequence 99 99 f1 3f 9a 99 99 99.
989 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
992 md_atof (int type
, char * litP
, int * sizeP
)
995 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1027 return _("Unrecognized or unsupported floating point constant");
1030 t
= atof_ieee (input_line_pointer
, type
, words
);
1032 input_line_pointer
= t
;
1033 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1035 if (target_big_endian
)
1037 for (i
= 0; i
< prec
; i
++)
1039 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1040 litP
+= sizeof (LITTLENUM_TYPE
);
1045 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1046 for (i
= prec
- 1; i
>= 0; i
--)
1048 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1049 litP
+= sizeof (LITTLENUM_TYPE
);
1052 /* For a 4 byte float the order of elements in `words' is 1 0.
1053 For an 8 byte float the order is 1 0 3 2. */
1054 for (i
= 0; i
< prec
; i
+= 2)
1056 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1057 sizeof (LITTLENUM_TYPE
));
1058 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1059 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1060 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1067 /* We handle all bad expressions here, so that we can report the faulty
1068 instruction in the error message. */
1070 md_operand (expressionS
* exp
)
1072 if (in_my_get_expression
)
1073 exp
->X_op
= O_illegal
;
1076 /* Immediate values. */
1078 /* Generic immediate-value read function for use in directives.
1079 Accepts anything that 'expression' can fold to a constant.
1080 *val receives the number. */
1083 immediate_for_directive (int *val
)
1086 exp
.X_op
= O_illegal
;
1088 if (is_immediate_prefix (*input_line_pointer
))
1090 input_line_pointer
++;
1094 if (exp
.X_op
!= O_constant
)
1096 as_bad (_("expected #constant"));
1097 ignore_rest_of_line ();
1100 *val
= exp
.X_add_number
;
1105 /* Register parsing. */
1107 /* Generic register parser. CCP points to what should be the
1108 beginning of a register name. If it is indeed a valid register
1109 name, advance CCP over it and return the reg_entry structure;
1110 otherwise return NULL. Does not issue diagnostics. */
1112 static struct reg_entry
*
1113 arm_reg_parse_multi (char **ccp
)
1117 struct reg_entry
*reg
;
1119 #ifdef REGISTER_PREFIX
1120 if (*start
!= REGISTER_PREFIX
)
1124 #ifdef OPTIONAL_REGISTER_PREFIX
1125 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1130 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1135 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1137 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1147 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1148 enum arm_reg_type type
)
1150 /* Alternative syntaxes are accepted for a few register classes. */
1157 /* Generic coprocessor register names are allowed for these. */
1158 if (reg
&& reg
->type
== REG_TYPE_CN
)
1163 /* For backward compatibility, a bare number is valid here. */
1165 unsigned long processor
= strtoul (start
, ccp
, 10);
1166 if (*ccp
!= start
&& processor
<= 15)
1170 case REG_TYPE_MMXWC
:
1171 /* WC includes WCG. ??? I'm not sure this is true for all
1172 instructions that take WC registers. */
1173 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1184 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1185 return value is the register number or FAIL. */
1188 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1191 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1194 /* Do not allow a scalar (reg+index) to parse as a register. */
1195 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1198 if (reg
&& reg
->type
== type
)
1201 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1208 /* Parse a Neon type specifier. *STR should point at the leading '.'
1209 character. Does no verification at this stage that the type fits the opcode
1216 Can all be legally parsed by this function.
1218 Fills in neon_type struct pointer with parsed information, and updates STR
1219 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1220 type, FAIL if not. */
1223 parse_neon_type (struct neon_type
*type
, char **str
)
1230 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1232 enum neon_el_type thistype
= NT_untyped
;
1233 unsigned thissize
= -1u;
1240 /* Just a size without an explicit type. */
1244 switch (TOLOWER (*ptr
))
1246 case 'i': thistype
= NT_integer
; break;
1247 case 'f': thistype
= NT_float
; break;
1248 case 'p': thistype
= NT_poly
; break;
1249 case 's': thistype
= NT_signed
; break;
1250 case 'u': thistype
= NT_unsigned
; break;
1252 thistype
= NT_float
;
1257 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1263 /* .f is an abbreviation for .f32. */
1264 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1269 thissize
= strtoul (ptr
, &ptr
, 10);
1271 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1274 as_bad (_("bad size %d in type specifier"), thissize
);
1282 type
->el
[type
->elems
].type
= thistype
;
1283 type
->el
[type
->elems
].size
= thissize
;
1288 /* Empty/missing type is not a successful parse. */
1289 if (type
->elems
== 0)
1297 /* Errors may be set multiple times during parsing or bit encoding
1298 (particularly in the Neon bits), but usually the earliest error which is set
1299 will be the most meaningful. Avoid overwriting it with later (cascading)
1300 errors by calling this function. */
1303 first_error (const char *err
)
1309 /* Parse a single type, e.g. ".s32", leading period included. */
1311 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1314 struct neon_type optype
;
1318 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1320 if (optype
.elems
== 1)
1321 *vectype
= optype
.el
[0];
1324 first_error (_("only one type should be specified for operand"));
1330 first_error (_("vector type expected"));
1342 /* Special meanings for indices (which have a range of 0-7), which will fit into
1345 #define NEON_ALL_LANES 15
1346 #define NEON_INTERLEAVE_LANES 14
1348 /* Parse either a register or a scalar, with an optional type. Return the
1349 register number, and optionally fill in the actual type of the register
1350 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1351 type/index information in *TYPEINFO. */
1354 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1355 enum arm_reg_type
*rtype
,
1356 struct neon_typed_alias
*typeinfo
)
1359 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1360 struct neon_typed_alias atype
;
1361 struct neon_type_el parsetype
;
1365 atype
.eltype
.type
= NT_invtype
;
1366 atype
.eltype
.size
= -1;
1368 /* Try alternate syntax for some types of register. Note these are mutually
1369 exclusive with the Neon syntax extensions. */
1372 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1380 /* Undo polymorphism when a set of register types may be accepted. */
1381 if ((type
== REG_TYPE_NDQ
1382 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1383 || (type
== REG_TYPE_VFSD
1384 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1385 || (type
== REG_TYPE_NSDQ
1386 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1387 || reg
->type
== REG_TYPE_NQ
))
1388 || (type
== REG_TYPE_MMXWC
1389 && (reg
->type
== REG_TYPE_MMXWCG
)))
1390 type
= (enum arm_reg_type
) reg
->type
;
1392 if (type
!= reg
->type
)
1398 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1400 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1402 first_error (_("can't redefine type for operand"));
1405 atype
.defined
|= NTA_HASTYPE
;
1406 atype
.eltype
= parsetype
;
1409 if (skip_past_char (&str
, '[') == SUCCESS
)
1411 if (type
!= REG_TYPE_VFD
)
1413 first_error (_("only D registers may be indexed"));
1417 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1419 first_error (_("can't change index for operand"));
1423 atype
.defined
|= NTA_HASINDEX
;
1425 if (skip_past_char (&str
, ']') == SUCCESS
)
1426 atype
.index
= NEON_ALL_LANES
;
1431 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1433 if (exp
.X_op
!= O_constant
)
1435 first_error (_("constant expression required"));
1439 if (skip_past_char (&str
, ']') == FAIL
)
1442 atype
.index
= exp
.X_add_number
;
1457 /* Like arm_reg_parse, but allow allow the following extra features:
1458 - If RTYPE is non-zero, return the (possibly restricted) type of the
1459 register (e.g. Neon double or quad reg when either has been requested).
1460 - If this is a Neon vector type with additional type information, fill
1461 in the struct pointed to by VECTYPE (if non-NULL).
1462 This function will fault on encountering a scalar. */
1465 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1466 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1468 struct neon_typed_alias atype
;
1470 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1475 /* Do not allow a scalar (reg+index) to parse as a register. */
1476 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1478 first_error (_("register operand expected, but got scalar"));
1483 *vectype
= atype
.eltype
;
1490 #define NEON_SCALAR_REG(X) ((X) >> 4)
1491 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1493 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1494 have enough information to be able to do a good job bounds-checking. So, we
1495 just do easy checks here, and do further checks later. */
1498 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1502 struct neon_typed_alias atype
;
1504 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1506 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1509 if (atype
.index
== NEON_ALL_LANES
)
1511 first_error (_("scalar must have an index"));
1514 else if (atype
.index
>= 64 / elsize
)
1516 first_error (_("scalar index out of range"));
1521 *type
= atype
.eltype
;
1525 return reg
* 16 + atype
.index
;
1528 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1531 parse_reg_list (char ** strp
)
1533 char * str
= * strp
;
1537 /* We come back here if we get ranges concatenated by '+' or '|'. */
1552 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1554 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1564 first_error (_("bad range in register list"));
1568 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1570 if (range
& (1 << i
))
1572 (_("Warning: duplicated register (r%d) in register list"),
1580 if (range
& (1 << reg
))
1581 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1583 else if (reg
<= cur_reg
)
1584 as_tsktsk (_("Warning: register range not in ascending order"));
1589 while (skip_past_comma (&str
) != FAIL
1590 || (in_range
= 1, *str
++ == '-'));
1595 first_error (_("missing `}'"));
1603 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1606 if (exp
.X_op
== O_constant
)
1608 if (exp
.X_add_number
1609 != (exp
.X_add_number
& 0x0000ffff))
1611 inst
.error
= _("invalid register mask");
1615 if ((range
& exp
.X_add_number
) != 0)
1617 int regno
= range
& exp
.X_add_number
;
1620 regno
= (1 << regno
) - 1;
1622 (_("Warning: duplicated register (r%d) in register list"),
1626 range
|= exp
.X_add_number
;
1630 if (inst
.reloc
.type
!= 0)
1632 inst
.error
= _("expression too complex");
1636 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1637 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1638 inst
.reloc
.pc_rel
= 0;
1642 if (*str
== '|' || *str
== '+')
1648 while (another_range
);
1654 /* Types of registers in a list. */
1663 /* Parse a VFP register list. If the string is invalid return FAIL.
1664 Otherwise return the number of registers, and set PBASE to the first
1665 register. Parses registers of type ETYPE.
1666 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1667 - Q registers can be used to specify pairs of D registers
1668 - { } can be omitted from around a singleton register list
1669 FIXME: This is not implemented, as it would require backtracking in
1672 This could be done (the meaning isn't really ambiguous), but doesn't
1673 fit in well with the current parsing framework.
1674 - 32 D registers may be used (also true for VFPv3).
1675 FIXME: Types are ignored in these register lists, which is probably a
1679 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1684 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1688 unsigned long mask
= 0;
1693 inst
.error
= _("expecting {");
1702 regtype
= REG_TYPE_VFS
;
1707 regtype
= REG_TYPE_VFD
;
1710 case REGLIST_NEON_D
:
1711 regtype
= REG_TYPE_NDQ
;
1715 if (etype
!= REGLIST_VFP_S
)
1717 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1718 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1722 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1725 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1732 base_reg
= max_regs
;
1736 int setmask
= 1, addregs
= 1;
1738 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1740 if (new_base
== FAIL
)
1742 first_error (_(reg_expected_msgs
[regtype
]));
1746 if (new_base
>= max_regs
)
1748 first_error (_("register out of range in list"));
1752 /* Note: a value of 2 * n is returned for the register Q<n>. */
1753 if (regtype
== REG_TYPE_NQ
)
1759 if (new_base
< base_reg
)
1760 base_reg
= new_base
;
1762 if (mask
& (setmask
<< new_base
))
1764 first_error (_("invalid register list"));
1768 if ((mask
>> new_base
) != 0 && ! warned
)
1770 as_tsktsk (_("register list not in ascending order"));
1774 mask
|= setmask
<< new_base
;
1777 if (*str
== '-') /* We have the start of a range expression */
1783 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1786 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1790 if (high_range
>= max_regs
)
1792 first_error (_("register out of range in list"));
1796 if (regtype
== REG_TYPE_NQ
)
1797 high_range
= high_range
+ 1;
1799 if (high_range
<= new_base
)
1801 inst
.error
= _("register range not in ascending order");
1805 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1807 if (mask
& (setmask
<< new_base
))
1809 inst
.error
= _("invalid register list");
1813 mask
|= setmask
<< new_base
;
1818 while (skip_past_comma (&str
) != FAIL
);
1822 /* Sanity check -- should have raised a parse error above. */
1823 if (count
== 0 || count
> max_regs
)
1828 /* Final test -- the registers must be consecutive. */
1830 for (i
= 0; i
< count
; i
++)
1832 if ((mask
& (1u << i
)) == 0)
1834 inst
.error
= _("non-contiguous register range");
1844 /* True if two alias types are the same. */
1847 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1855 if (a
->defined
!= b
->defined
)
1858 if ((a
->defined
& NTA_HASTYPE
) != 0
1859 && (a
->eltype
.type
!= b
->eltype
.type
1860 || a
->eltype
.size
!= b
->eltype
.size
))
1863 if ((a
->defined
& NTA_HASINDEX
) != 0
1864 && (a
->index
!= b
->index
))
1870 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1871 The base register is put in *PBASE.
1872 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1874 The register stride (minus one) is put in bit 4 of the return value.
1875 Bits [6:5] encode the list length (minus one).
1876 The type of the list elements is put in *ELTYPE, if non-NULL. */
1878 #define NEON_LANE(X) ((X) & 0xf)
1879 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1880 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1883 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1884 struct neon_type_el
*eltype
)
1891 int leading_brace
= 0;
1892 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1893 const char *const incr_error
= _("register stride must be 1 or 2");
1894 const char *const type_error
= _("mismatched element/structure types in list");
1895 struct neon_typed_alias firsttype
;
1897 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1902 struct neon_typed_alias atype
;
1903 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1907 first_error (_(reg_expected_msgs
[rtype
]));
1914 if (rtype
== REG_TYPE_NQ
)
1920 else if (reg_incr
== -1)
1922 reg_incr
= getreg
- base_reg
;
1923 if (reg_incr
< 1 || reg_incr
> 2)
1925 first_error (_(incr_error
));
1929 else if (getreg
!= base_reg
+ reg_incr
* count
)
1931 first_error (_(incr_error
));
1935 if (! neon_alias_types_same (&atype
, &firsttype
))
1937 first_error (_(type_error
));
1941 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1945 struct neon_typed_alias htype
;
1946 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1948 lane
= NEON_INTERLEAVE_LANES
;
1949 else if (lane
!= NEON_INTERLEAVE_LANES
)
1951 first_error (_(type_error
));
1956 else if (reg_incr
!= 1)
1958 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1962 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1965 first_error (_(reg_expected_msgs
[rtype
]));
1968 if (! neon_alias_types_same (&htype
, &firsttype
))
1970 first_error (_(type_error
));
1973 count
+= hireg
+ dregs
- getreg
;
1977 /* If we're using Q registers, we can't use [] or [n] syntax. */
1978 if (rtype
== REG_TYPE_NQ
)
1984 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1988 else if (lane
!= atype
.index
)
1990 first_error (_(type_error
));
1994 else if (lane
== -1)
1995 lane
= NEON_INTERLEAVE_LANES
;
1996 else if (lane
!= NEON_INTERLEAVE_LANES
)
1998 first_error (_(type_error
));
2003 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2005 /* No lane set by [x]. We must be interleaving structures. */
2007 lane
= NEON_INTERLEAVE_LANES
;
2010 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2011 || (count
> 1 && reg_incr
== -1))
2013 first_error (_("error parsing element/structure list"));
2017 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2019 first_error (_("expected }"));
2027 *eltype
= firsttype
.eltype
;
2032 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2035 /* Parse an explicit relocation suffix on an expression. This is
2036 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2037 arm_reloc_hsh contains no entries, so this function can only
2038 succeed if there is no () after the word. Returns -1 on error,
2039 BFD_RELOC_UNUSED if there wasn't any suffix. */
2041 parse_reloc (char **str
)
2043 struct reloc_entry
*r
;
2047 return BFD_RELOC_UNUSED
;
2052 while (*q
&& *q
!= ')' && *q
!= ',')
2057 if ((r
= (struct reloc_entry
*)
2058 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2065 /* Directives: register aliases. */
2067 static struct reg_entry
*
2068 insert_reg_alias (char *str
, unsigned number
, int type
)
2070 struct reg_entry
*new_reg
;
2073 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2075 if (new_reg
->builtin
)
2076 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2078 /* Only warn about a redefinition if it's not defined as the
2080 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2081 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2086 name
= xstrdup (str
);
2087 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2089 new_reg
->name
= name
;
2090 new_reg
->number
= number
;
2091 new_reg
->type
= type
;
2092 new_reg
->builtin
= FALSE
;
2093 new_reg
->neon
= NULL
;
2095 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2102 insert_neon_reg_alias (char *str
, int number
, int type
,
2103 struct neon_typed_alias
*atype
)
2105 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2109 first_error (_("attempt to redefine typed alias"));
2115 reg
->neon
= (struct neon_typed_alias
*)
2116 xmalloc (sizeof (struct neon_typed_alias
));
2117 *reg
->neon
= *atype
;
2121 /* Look for the .req directive. This is of the form:
2123 new_register_name .req existing_register_name
2125 If we find one, or if it looks sufficiently like one that we want to
2126 handle any error here, return TRUE. Otherwise return FALSE. */
2129 create_register_alias (char * newname
, char *p
)
2131 struct reg_entry
*old
;
2132 char *oldname
, *nbuf
;
2135 /* The input scrubber ensures that whitespace after the mnemonic is
2136 collapsed to single spaces. */
2138 if (strncmp (oldname
, " .req ", 6) != 0)
2142 if (*oldname
== '\0')
2145 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2148 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2152 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2153 the desired alias name, and p points to its end. If not, then
2154 the desired alias name is in the global original_case_string. */
2155 #ifdef TC_CASE_SENSITIVE
2158 newname
= original_case_string
;
2159 nlen
= strlen (newname
);
2162 nbuf
= (char *) alloca (nlen
+ 1);
2163 memcpy (nbuf
, newname
, nlen
);
2166 /* Create aliases under the new name as stated; an all-lowercase
2167 version of the new name; and an all-uppercase version of the new
2169 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2171 for (p
= nbuf
; *p
; p
++)
2174 if (strncmp (nbuf
, newname
, nlen
))
2176 /* If this attempt to create an additional alias fails, do not bother
2177 trying to create the all-lower case alias. We will fail and issue
2178 a second, duplicate error message. This situation arises when the
2179 programmer does something like:
2182 The second .req creates the "Foo" alias but then fails to create
2183 the artificial FOO alias because it has already been created by the
2185 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2189 for (p
= nbuf
; *p
; p
++)
2192 if (strncmp (nbuf
, newname
, nlen
))
2193 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2199 /* Create a Neon typed/indexed register alias using directives, e.g.:
2204 These typed registers can be used instead of the types specified after the
2205 Neon mnemonic, so long as all operands given have types. Types can also be
2206 specified directly, e.g.:
2207 vadd d0.s32, d1.s32, d2.s32 */
2210 create_neon_reg_alias (char *newname
, char *p
)
2212 enum arm_reg_type basetype
;
2213 struct reg_entry
*basereg
;
2214 struct reg_entry mybasereg
;
2215 struct neon_type ntype
;
2216 struct neon_typed_alias typeinfo
;
2217 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2220 typeinfo
.defined
= 0;
2221 typeinfo
.eltype
.type
= NT_invtype
;
2222 typeinfo
.eltype
.size
= -1;
2223 typeinfo
.index
= -1;
2227 if (strncmp (p
, " .dn ", 5) == 0)
2228 basetype
= REG_TYPE_VFD
;
2229 else if (strncmp (p
, " .qn ", 5) == 0)
2230 basetype
= REG_TYPE_NQ
;
2239 basereg
= arm_reg_parse_multi (&p
);
2241 if (basereg
&& basereg
->type
!= basetype
)
2243 as_bad (_("bad type for register"));
2247 if (basereg
== NULL
)
2250 /* Try parsing as an integer. */
2251 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2252 if (exp
.X_op
!= O_constant
)
2254 as_bad (_("expression must be constant"));
2257 basereg
= &mybasereg
;
2258 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2264 typeinfo
= *basereg
->neon
;
2266 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2268 /* We got a type. */
2269 if (typeinfo
.defined
& NTA_HASTYPE
)
2271 as_bad (_("can't redefine the type of a register alias"));
2275 typeinfo
.defined
|= NTA_HASTYPE
;
2276 if (ntype
.elems
!= 1)
2278 as_bad (_("you must specify a single type only"));
2281 typeinfo
.eltype
= ntype
.el
[0];
2284 if (skip_past_char (&p
, '[') == SUCCESS
)
2287 /* We got a scalar index. */
2289 if (typeinfo
.defined
& NTA_HASINDEX
)
2291 as_bad (_("can't redefine the index of a scalar alias"));
2295 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2297 if (exp
.X_op
!= O_constant
)
2299 as_bad (_("scalar index must be constant"));
2303 typeinfo
.defined
|= NTA_HASINDEX
;
2304 typeinfo
.index
= exp
.X_add_number
;
2306 if (skip_past_char (&p
, ']') == FAIL
)
2308 as_bad (_("expecting ]"));
2313 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2314 the desired alias name, and p points to its end. If not, then
2315 the desired alias name is in the global original_case_string. */
2316 #ifdef TC_CASE_SENSITIVE
2317 namelen
= nameend
- newname
;
2319 newname
= original_case_string
;
2320 namelen
= strlen (newname
);
2323 namebuf
= (char *) alloca (namelen
+ 1);
2324 strncpy (namebuf
, newname
, namelen
);
2325 namebuf
[namelen
] = '\0';
2327 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2328 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2330 /* Insert name in all uppercase. */
2331 for (p
= namebuf
; *p
; p
++)
2334 if (strncmp (namebuf
, newname
, namelen
))
2335 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2336 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2338 /* Insert name in all lowercase. */
2339 for (p
= namebuf
; *p
; p
++)
2342 if (strncmp (namebuf
, newname
, namelen
))
2343 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2344 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2349 /* Should never be called, as .req goes between the alias and the
2350 register name, not at the beginning of the line. */
2353 s_req (int a ATTRIBUTE_UNUSED
)
2355 as_bad (_("invalid syntax for .req directive"));
2359 s_dn (int a ATTRIBUTE_UNUSED
)
2361 as_bad (_("invalid syntax for .dn directive"));
2365 s_qn (int a ATTRIBUTE_UNUSED
)
2367 as_bad (_("invalid syntax for .qn directive"));
2370 /* The .unreq directive deletes an alias which was previously defined
2371 by .req. For example:
2377 s_unreq (int a ATTRIBUTE_UNUSED
)
2382 name
= input_line_pointer
;
2384 while (*input_line_pointer
!= 0
2385 && *input_line_pointer
!= ' '
2386 && *input_line_pointer
!= '\n')
2387 ++input_line_pointer
;
2389 saved_char
= *input_line_pointer
;
2390 *input_line_pointer
= 0;
2393 as_bad (_("invalid syntax for .unreq directive"));
2396 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2400 as_bad (_("unknown register alias '%s'"), name
);
2401 else if (reg
->builtin
)
2402 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2409 hash_delete (arm_reg_hsh
, name
, FALSE
);
2410 free ((char *) reg
->name
);
2415 /* Also locate the all upper case and all lower case versions.
2416 Do not complain if we cannot find one or the other as it
2417 was probably deleted above. */
2419 nbuf
= strdup (name
);
2420 for (p
= nbuf
; *p
; p
++)
2422 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2425 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2426 free ((char *) reg
->name
);
2432 for (p
= nbuf
; *p
; p
++)
2434 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2437 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2438 free ((char *) reg
->name
);
2448 *input_line_pointer
= saved_char
;
2449 demand_empty_rest_of_line ();
2452 /* Directives: Instruction set selection. */
2455 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2456 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2457 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2458 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2460 /* Create a new mapping symbol for the transition to STATE. */
2463 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2466 const char * symname
;
2473 type
= BSF_NO_FLAGS
;
2477 type
= BSF_NO_FLAGS
;
2481 type
= BSF_NO_FLAGS
;
2487 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2488 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2493 THUMB_SET_FUNC (symbolP
, 0);
2494 ARM_SET_THUMB (symbolP
, 0);
2495 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2499 THUMB_SET_FUNC (symbolP
, 1);
2500 ARM_SET_THUMB (symbolP
, 1);
2501 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2509 /* Save the mapping symbols for future reference. Also check that
2510 we do not place two mapping symbols at the same offset within a
2511 frag. We'll handle overlap between frags in
2512 check_mapping_symbols.
2514 If .fill or other data filling directive generates zero sized data,
2515 the mapping symbol for the following code will have the same value
2516 as the one generated for the data filling directive. In this case,
2517 we replace the old symbol with the new one at the same address. */
2520 if (frag
->tc_frag_data
.first_map
!= NULL
)
2522 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2523 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2525 frag
->tc_frag_data
.first_map
= symbolP
;
2527 if (frag
->tc_frag_data
.last_map
!= NULL
)
2529 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2530 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2531 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2533 frag
->tc_frag_data
.last_map
= symbolP
;
2536 /* We must sometimes convert a region marked as code to data during
2537 code alignment, if an odd number of bytes have to be padded. The
2538 code mapping symbol is pushed to an aligned address. */
2541 insert_data_mapping_symbol (enum mstate state
,
2542 valueT value
, fragS
*frag
, offsetT bytes
)
2544 /* If there was already a mapping symbol, remove it. */
2545 if (frag
->tc_frag_data
.last_map
!= NULL
2546 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2548 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2552 know (frag
->tc_frag_data
.first_map
== symp
);
2553 frag
->tc_frag_data
.first_map
= NULL
;
2555 frag
->tc_frag_data
.last_map
= NULL
;
2556 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2559 make_mapping_symbol (MAP_DATA
, value
, frag
);
2560 make_mapping_symbol (state
, value
+ bytes
, frag
);
2563 static void mapping_state_2 (enum mstate state
, int max_chars
);
2565 /* Set the mapping state to STATE. Only call this when about to
2566 emit some STATE bytes to the file. */
2569 mapping_state (enum mstate state
)
2571 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2573 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2575 if (mapstate
== state
)
2576 /* The mapping symbol has already been emitted.
2577 There is nothing else to do. */
2579 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2580 /* This case will be evaluated later in the next else. */
2582 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2583 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2585 /* Only add the symbol if the offset is > 0:
2586 if we're at the first frag, check it's size > 0;
2587 if we're not at the first frag, then for sure
2588 the offset is > 0. */
2589 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2590 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2593 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2596 mapping_state_2 (state
, 0);
2600 /* Same as mapping_state, but MAX_CHARS bytes have already been
2601 allocated. Put the mapping symbol that far back. */
2604 mapping_state_2 (enum mstate state
, int max_chars
)
2606 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2608 if (!SEG_NORMAL (now_seg
))
2611 if (mapstate
== state
)
2612 /* The mapping symbol has already been emitted.
2613 There is nothing else to do. */
2616 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2617 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2620 #define mapping_state(x) ((void)0)
2621 #define mapping_state_2(x, y) ((void)0)
2624 /* Find the real, Thumb encoded start of a Thumb function. */
2628 find_real_start (symbolS
* symbolP
)
2631 const char * name
= S_GET_NAME (symbolP
);
2632 symbolS
* new_target
;
2634 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2635 #define STUB_NAME ".real_start_of"
2640 /* The compiler may generate BL instructions to local labels because
2641 it needs to perform a branch to a far away location. These labels
2642 do not have a corresponding ".real_start_of" label. We check
2643 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2644 the ".real_start_of" convention for nonlocal branches. */
2645 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2648 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2649 new_target
= symbol_find (real_start
);
2651 if (new_target
== NULL
)
2653 as_warn (_("Failed to find real start of function: %s\n"), name
);
2654 new_target
= symbolP
;
2662 opcode_select (int width
)
2669 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2670 as_bad (_("selected processor does not support THUMB opcodes"));
2673 /* No need to force the alignment, since we will have been
2674 coming from ARM mode, which is word-aligned. */
2675 record_alignment (now_seg
, 1);
2682 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2683 as_bad (_("selected processor does not support ARM opcodes"));
2688 frag_align (2, 0, 0);
2690 record_alignment (now_seg
, 1);
2695 as_bad (_("invalid instruction size selected (%d)"), width
);
2700 s_arm (int ignore ATTRIBUTE_UNUSED
)
2703 demand_empty_rest_of_line ();
2707 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2710 demand_empty_rest_of_line ();
2714 s_code (int unused ATTRIBUTE_UNUSED
)
2718 temp
= get_absolute_expression ();
2723 opcode_select (temp
);
2727 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2732 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2734 /* If we are not already in thumb mode go into it, EVEN if
2735 the target processor does not support thumb instructions.
2736 This is used by gcc/config/arm/lib1funcs.asm for example
2737 to compile interworking support functions even if the
2738 target processor should not support interworking. */
2742 record_alignment (now_seg
, 1);
2745 demand_empty_rest_of_line ();
2749 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2753 /* The following label is the name/address of the start of a Thumb function.
2754 We need to know this for the interworking support. */
2755 label_is_thumb_function_name
= TRUE
;
2758 /* Perform a .set directive, but also mark the alias as
2759 being a thumb function. */
2762 s_thumb_set (int equiv
)
2764 /* XXX the following is a duplicate of the code for s_set() in read.c
2765 We cannot just call that code as we need to get at the symbol that
2772 /* Especial apologies for the random logic:
2773 This just grew, and could be parsed much more simply!
2775 name
= input_line_pointer
;
2776 delim
= get_symbol_end ();
2777 end_name
= input_line_pointer
;
2780 if (*input_line_pointer
!= ',')
2783 as_bad (_("expected comma after name \"%s\""), name
);
2785 ignore_rest_of_line ();
2789 input_line_pointer
++;
2792 if (name
[0] == '.' && name
[1] == '\0')
2794 /* XXX - this should not happen to .thumb_set. */
2798 if ((symbolP
= symbol_find (name
)) == NULL
2799 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2802 /* When doing symbol listings, play games with dummy fragments living
2803 outside the normal fragment chain to record the file and line info
2805 if (listing
& LISTING_SYMBOLS
)
2807 extern struct list_info_struct
* listing_tail
;
2808 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2810 memset (dummy_frag
, 0, sizeof (fragS
));
2811 dummy_frag
->fr_type
= rs_fill
;
2812 dummy_frag
->line
= listing_tail
;
2813 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2814 dummy_frag
->fr_symbol
= symbolP
;
2818 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2821 /* "set" symbols are local unless otherwise specified. */
2822 SF_SET_LOCAL (symbolP
);
2823 #endif /* OBJ_COFF */
2824 } /* Make a new symbol. */
2826 symbol_table_insert (symbolP
);
2831 && S_IS_DEFINED (symbolP
)
2832 && S_GET_SEGMENT (symbolP
) != reg_section
)
2833 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2835 pseudo_set (symbolP
);
2837 demand_empty_rest_of_line ();
2839 /* XXX Now we come to the Thumb specific bit of code. */
2841 THUMB_SET_FUNC (symbolP
, 1);
2842 ARM_SET_THUMB (symbolP
, 1);
2843 #if defined OBJ_ELF || defined OBJ_COFF
2844 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2848 /* Directives: Mode selection. */
2850 /* .syntax [unified|divided] - choose the new unified syntax
2851 (same for Arm and Thumb encoding, modulo slight differences in what
2852 can be represented) or the old divergent syntax for each mode. */
2854 s_syntax (int unused ATTRIBUTE_UNUSED
)
2858 name
= input_line_pointer
;
2859 delim
= get_symbol_end ();
2861 if (!strcasecmp (name
, "unified"))
2862 unified_syntax
= TRUE
;
2863 else if (!strcasecmp (name
, "divided"))
2864 unified_syntax
= FALSE
;
2867 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2870 *input_line_pointer
= delim
;
2871 demand_empty_rest_of_line ();
2874 /* Directives: sectioning and alignment. */
2876 /* Same as s_align_ptwo but align 0 => align 2. */
2879 s_align (int unused ATTRIBUTE_UNUSED
)
2884 long max_alignment
= 15;
2886 temp
= get_absolute_expression ();
2887 if (temp
> max_alignment
)
2888 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2891 as_bad (_("alignment negative. 0 assumed."));
2895 if (*input_line_pointer
== ',')
2897 input_line_pointer
++;
2898 temp_fill
= get_absolute_expression ();
2910 /* Only make a frag if we HAVE to. */
2911 if (temp
&& !need_pass_2
)
2913 if (!fill_p
&& subseg_text_p (now_seg
))
2914 frag_align_code (temp
, 0);
2916 frag_align (temp
, (int) temp_fill
, 0);
2918 demand_empty_rest_of_line ();
2920 record_alignment (now_seg
, temp
);
2924 s_bss (int ignore ATTRIBUTE_UNUSED
)
2926 /* We don't support putting frags in the BSS segment, we fake it by
2927 marking in_bss, then looking at s_skip for clues. */
2928 subseg_set (bss_section
, 0);
2929 demand_empty_rest_of_line ();
2931 #ifdef md_elf_section_change_hook
2932 md_elf_section_change_hook ();
2937 s_even (int ignore ATTRIBUTE_UNUSED
)
2939 /* Never make frag if expect extra pass. */
2941 frag_align (1, 0, 0);
2943 record_alignment (now_seg
, 1);
2945 demand_empty_rest_of_line ();
2948 /* Directives: Literal pools. */
2950 static literal_pool
*
2951 find_literal_pool (void)
2953 literal_pool
* pool
;
2955 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2957 if (pool
->section
== now_seg
2958 && pool
->sub_section
== now_subseg
)
2965 static literal_pool
*
2966 find_or_make_literal_pool (void)
2968 /* Next literal pool ID number. */
2969 static unsigned int latest_pool_num
= 1;
2970 literal_pool
* pool
;
2972 pool
= find_literal_pool ();
2976 /* Create a new pool. */
2977 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2981 pool
->next_free_entry
= 0;
2982 pool
->section
= now_seg
;
2983 pool
->sub_section
= now_subseg
;
2984 pool
->next
= list_of_pools
;
2985 pool
->symbol
= NULL
;
2987 /* Add it to the list. */
2988 list_of_pools
= pool
;
2991 /* New pools, and emptied pools, will have a NULL symbol. */
2992 if (pool
->symbol
== NULL
)
2994 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2995 (valueT
) 0, &zero_address_frag
);
2996 pool
->id
= latest_pool_num
++;
3003 /* Add the literal in the global 'inst'
3004 structure to the relevant literal pool. */
3007 add_to_lit_pool (void)
3009 literal_pool
* pool
;
3012 pool
= find_or_make_literal_pool ();
3014 /* Check if this literal value is already in the pool. */
3015 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3017 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3018 && (inst
.reloc
.exp
.X_op
== O_constant
)
3019 && (pool
->literals
[entry
].X_add_number
3020 == inst
.reloc
.exp
.X_add_number
)
3021 && (pool
->literals
[entry
].X_unsigned
3022 == inst
.reloc
.exp
.X_unsigned
))
3025 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3026 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3027 && (pool
->literals
[entry
].X_add_number
3028 == inst
.reloc
.exp
.X_add_number
)
3029 && (pool
->literals
[entry
].X_add_symbol
3030 == inst
.reloc
.exp
.X_add_symbol
)
3031 && (pool
->literals
[entry
].X_op_symbol
3032 == inst
.reloc
.exp
.X_op_symbol
))
3036 /* Do we need to create a new entry? */
3037 if (entry
== pool
->next_free_entry
)
3039 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3041 inst
.error
= _("literal pool overflow");
3045 pool
->literals
[entry
] = inst
.reloc
.exp
;
3046 pool
->next_free_entry
+= 1;
3049 inst
.reloc
.exp
.X_op
= O_symbol
;
3050 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3051 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3056 /* Can't use symbol_new here, so have to create a symbol and then at
3057 a later date assign it a value. Thats what these functions do. */
3060 symbol_locate (symbolS
* symbolP
,
3061 const char * name
, /* It is copied, the caller can modify. */
3062 segT segment
, /* Segment identifier (SEG_<something>). */
3063 valueT valu
, /* Symbol value. */
3064 fragS
* frag
) /* Associated fragment. */
3066 unsigned int name_length
;
3067 char * preserved_copy_of_name
;
3069 name_length
= strlen (name
) + 1; /* +1 for \0. */
3070 obstack_grow (¬es
, name
, name_length
);
3071 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3073 #ifdef tc_canonicalize_symbol_name
3074 preserved_copy_of_name
=
3075 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3078 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3080 S_SET_SEGMENT (symbolP
, segment
);
3081 S_SET_VALUE (symbolP
, valu
);
3082 symbol_clear_list_pointers (symbolP
);
3084 symbol_set_frag (symbolP
, frag
);
3086 /* Link to end of symbol chain. */
3088 extern int symbol_table_frozen
;
3090 if (symbol_table_frozen
)
3094 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3096 obj_symbol_new_hook (symbolP
);
3098 #ifdef tc_symbol_new_hook
3099 tc_symbol_new_hook (symbolP
);
3103 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3104 #endif /* DEBUG_SYMS */
3109 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3112 literal_pool
* pool
;
3115 pool
= find_literal_pool ();
3117 || pool
->symbol
== NULL
3118 || pool
->next_free_entry
== 0)
3121 mapping_state (MAP_DATA
);
3123 /* Align pool as you have word accesses.
3124 Only make a frag if we have to. */
3126 frag_align (2, 0, 0);
3128 record_alignment (now_seg
, 2);
3130 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3132 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3133 (valueT
) frag_now_fix (), frag_now
);
3134 symbol_table_insert (pool
->symbol
);
3136 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3138 #if defined OBJ_COFF || defined OBJ_ELF
3139 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3142 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3143 /* First output the expression in the instruction to the pool. */
3144 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3146 /* Mark the pool as empty. */
3147 pool
->next_free_entry
= 0;
3148 pool
->symbol
= NULL
;
3152 /* Forward declarations for functions below, in the MD interface
3154 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3155 static valueT
create_unwind_entry (int);
3156 static void start_unwind_section (const segT
, int);
3157 static void add_unwind_opcode (valueT
, int);
3158 static void flush_pending_unwind (void);
3160 /* Directives: Data. */
3163 s_arm_elf_cons (int nbytes
)
3167 #ifdef md_flush_pending_output
3168 md_flush_pending_output ();
3171 if (is_it_end_of_statement ())
3173 demand_empty_rest_of_line ();
3177 #ifdef md_cons_align
3178 md_cons_align (nbytes
);
3181 mapping_state (MAP_DATA
);
3185 char *base
= input_line_pointer
;
3189 if (exp
.X_op
!= O_symbol
)
3190 emit_expr (&exp
, (unsigned int) nbytes
);
3193 char *before_reloc
= input_line_pointer
;
3194 reloc
= parse_reloc (&input_line_pointer
);
3197 as_bad (_("unrecognized relocation suffix"));
3198 ignore_rest_of_line ();
3201 else if (reloc
== BFD_RELOC_UNUSED
)
3202 emit_expr (&exp
, (unsigned int) nbytes
);
3205 reloc_howto_type
*howto
= (reloc_howto_type
*)
3206 bfd_reloc_type_lookup (stdoutput
,
3207 (bfd_reloc_code_real_type
) reloc
);
3208 int size
= bfd_get_reloc_size (howto
);
3210 if (reloc
== BFD_RELOC_ARM_PLT32
)
3212 as_bad (_("(plt) is only valid on branch targets"));
3213 reloc
= BFD_RELOC_UNUSED
;
3218 as_bad (_("%s relocations do not fit in %d bytes"),
3219 howto
->name
, nbytes
);
3222 /* We've parsed an expression stopping at O_symbol.
3223 But there may be more expression left now that we
3224 have parsed the relocation marker. Parse it again.
3225 XXX Surely there is a cleaner way to do this. */
3226 char *p
= input_line_pointer
;
3228 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3229 memcpy (save_buf
, base
, input_line_pointer
- base
);
3230 memmove (base
+ (input_line_pointer
- before_reloc
),
3231 base
, before_reloc
- base
);
3233 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3235 memcpy (base
, save_buf
, p
- base
);
3237 offset
= nbytes
- size
;
3238 p
= frag_more ((int) nbytes
);
3239 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3240 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3245 while (*input_line_pointer
++ == ',');
3247 /* Put terminator back into stream. */
3248 input_line_pointer
--;
3249 demand_empty_rest_of_line ();
3252 /* Emit an expression containing a 32-bit thumb instruction.
3253 Implementation based on put_thumb32_insn. */
3256 emit_thumb32_expr (expressionS
* exp
)
3258 expressionS exp_high
= *exp
;
3260 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3261 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3262 exp
->X_add_number
&= 0xffff;
3263 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3266 /* Guess the instruction size based on the opcode. */
3269 thumb_insn_size (int opcode
)
3271 if ((unsigned int) opcode
< 0xe800u
)
3273 else if ((unsigned int) opcode
>= 0xe8000000u
)
3280 emit_insn (expressionS
*exp
, int nbytes
)
3284 if (exp
->X_op
== O_constant
)
3289 size
= thumb_insn_size (exp
->X_add_number
);
3293 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3295 as_bad (_(".inst.n operand too big. "\
3296 "Use .inst.w instead"));
3301 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3302 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3304 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3306 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3307 emit_thumb32_expr (exp
);
3309 emit_expr (exp
, (unsigned int) size
);
3311 it_fsm_post_encode ();
3315 as_bad (_("cannot determine Thumb instruction size. " \
3316 "Use .inst.n/.inst.w instead"));
3319 as_bad (_("constant expression required"));
3324 /* Like s_arm_elf_cons but do not use md_cons_align and
3325 set the mapping state to MAP_ARM/MAP_THUMB. */
3328 s_arm_elf_inst (int nbytes
)
3330 if (is_it_end_of_statement ())
3332 demand_empty_rest_of_line ();
3336 /* Calling mapping_state () here will not change ARM/THUMB,
3337 but will ensure not to be in DATA state. */
3340 mapping_state (MAP_THUMB
);
3345 as_bad (_("width suffixes are invalid in ARM mode"));
3346 ignore_rest_of_line ();
3352 mapping_state (MAP_ARM
);
3361 if (! emit_insn (& exp
, nbytes
))
3363 ignore_rest_of_line ();
3367 while (*input_line_pointer
++ == ',');
3369 /* Put terminator back into stream. */
3370 input_line_pointer
--;
3371 demand_empty_rest_of_line ();
3374 /* Parse a .rel31 directive. */
3377 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3384 if (*input_line_pointer
== '1')
3385 highbit
= 0x80000000;
3386 else if (*input_line_pointer
!= '0')
3387 as_bad (_("expected 0 or 1"));
3389 input_line_pointer
++;
3390 if (*input_line_pointer
!= ',')
3391 as_bad (_("missing comma"));
3392 input_line_pointer
++;
3394 #ifdef md_flush_pending_output
3395 md_flush_pending_output ();
3398 #ifdef md_cons_align
3402 mapping_state (MAP_DATA
);
3407 md_number_to_chars (p
, highbit
, 4);
3408 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3409 BFD_RELOC_ARM_PREL31
);
3411 demand_empty_rest_of_line ();
3414 /* Directives: AEABI stack-unwind tables. */
3416 /* Parse an unwind_fnstart directive. Simply records the current location. */
3419 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3421 demand_empty_rest_of_line ();
3422 if (unwind
.proc_start
)
3424 as_bad (_("duplicate .fnstart directive"));
3428 /* Mark the start of the function. */
3429 unwind
.proc_start
= expr_build_dot ();
3431 /* Reset the rest of the unwind info. */
3432 unwind
.opcode_count
= 0;
3433 unwind
.table_entry
= NULL
;
3434 unwind
.personality_routine
= NULL
;
3435 unwind
.personality_index
= -1;
3436 unwind
.frame_size
= 0;
3437 unwind
.fp_offset
= 0;
3438 unwind
.fp_reg
= REG_SP
;
3440 unwind
.sp_restored
= 0;
3444 /* Parse a handlerdata directive. Creates the exception handling table entry
3445 for the function. */
3448 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3450 demand_empty_rest_of_line ();
3451 if (!unwind
.proc_start
)
3452 as_bad (MISSING_FNSTART
);
3454 if (unwind
.table_entry
)
3455 as_bad (_("duplicate .handlerdata directive"));
3457 create_unwind_entry (1);
3460 /* Parse an unwind_fnend directive. Generates the index table entry. */
3463 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3468 unsigned int marked_pr_dependency
;
3470 demand_empty_rest_of_line ();
3472 if (!unwind
.proc_start
)
3474 as_bad (_(".fnend directive without .fnstart"));
3478 /* Add eh table entry. */
3479 if (unwind
.table_entry
== NULL
)
3480 val
= create_unwind_entry (0);
3484 /* Add index table entry. This is two words. */
3485 start_unwind_section (unwind
.saved_seg
, 1);
3486 frag_align (2, 0, 0);
3487 record_alignment (now_seg
, 2);
3489 ptr
= frag_more (8);
3490 where
= frag_now_fix () - 8;
3492 /* Self relative offset of the function start. */
3493 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3494 BFD_RELOC_ARM_PREL31
);
3496 /* Indicate dependency on EHABI-defined personality routines to the
3497 linker, if it hasn't been done already. */
3498 marked_pr_dependency
3499 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3500 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3501 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3503 static const char *const name
[] =
3505 "__aeabi_unwind_cpp_pr0",
3506 "__aeabi_unwind_cpp_pr1",
3507 "__aeabi_unwind_cpp_pr2"
3509 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3510 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3511 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3512 |= 1 << unwind
.personality_index
;
3516 /* Inline exception table entry. */
3517 md_number_to_chars (ptr
+ 4, val
, 4);
3519 /* Self relative offset of the table entry. */
3520 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3521 BFD_RELOC_ARM_PREL31
);
3523 /* Restore the original section. */
3524 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3526 unwind
.proc_start
= NULL
;
3530 /* Parse an unwind_cantunwind directive. */
3533 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3535 demand_empty_rest_of_line ();
3536 if (!unwind
.proc_start
)
3537 as_bad (MISSING_FNSTART
);
3539 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3540 as_bad (_("personality routine specified for cantunwind frame"));
3542 unwind
.personality_index
= -2;
3546 /* Parse a personalityindex directive. */
3549 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3553 if (!unwind
.proc_start
)
3554 as_bad (MISSING_FNSTART
);
3556 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3557 as_bad (_("duplicate .personalityindex directive"));
3561 if (exp
.X_op
!= O_constant
3562 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3564 as_bad (_("bad personality routine number"));
3565 ignore_rest_of_line ();
3569 unwind
.personality_index
= exp
.X_add_number
;
3571 demand_empty_rest_of_line ();
3575 /* Parse a personality directive. */
3578 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3582 if (!unwind
.proc_start
)
3583 as_bad (MISSING_FNSTART
);
3585 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3586 as_bad (_("duplicate .personality directive"));
3588 name
= input_line_pointer
;
3589 c
= get_symbol_end ();
3590 p
= input_line_pointer
;
3591 unwind
.personality_routine
= symbol_find_or_make (name
);
3593 demand_empty_rest_of_line ();
3597 /* Parse a directive saving core registers. */
3600 s_arm_unwind_save_core (void)
3606 range
= parse_reg_list (&input_line_pointer
);
3609 as_bad (_("expected register list"));
3610 ignore_rest_of_line ();
3614 demand_empty_rest_of_line ();
3616 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3617 into .unwind_save {..., sp...}. We aren't bothered about the value of
3618 ip because it is clobbered by calls. */
3619 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3620 && (range
& 0x3000) == 0x1000)
3622 unwind
.opcode_count
--;
3623 unwind
.sp_restored
= 0;
3624 range
= (range
| 0x2000) & ~0x1000;
3625 unwind
.pending_offset
= 0;
3631 /* See if we can use the short opcodes. These pop a block of up to 8
3632 registers starting with r4, plus maybe r14. */
3633 for (n
= 0; n
< 8; n
++)
3635 /* Break at the first non-saved register. */
3636 if ((range
& (1 << (n
+ 4))) == 0)
3639 /* See if there are any other bits set. */
3640 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3642 /* Use the long form. */
3643 op
= 0x8000 | ((range
>> 4) & 0xfff);
3644 add_unwind_opcode (op
, 2);
3648 /* Use the short form. */
3650 op
= 0xa8; /* Pop r14. */
3652 op
= 0xa0; /* Do not pop r14. */
3654 add_unwind_opcode (op
, 1);
3661 op
= 0xb100 | (range
& 0xf);
3662 add_unwind_opcode (op
, 2);
3665 /* Record the number of bytes pushed. */
3666 for (n
= 0; n
< 16; n
++)
3668 if (range
& (1 << n
))
3669 unwind
.frame_size
+= 4;
3674 /* Parse a directive saving FPA registers. */
3677 s_arm_unwind_save_fpa (int reg
)
3683 /* Get Number of registers to transfer. */
3684 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3687 exp
.X_op
= O_illegal
;
3689 if (exp
.X_op
!= O_constant
)
3691 as_bad (_("expected , <constant>"));
3692 ignore_rest_of_line ();
3696 num_regs
= exp
.X_add_number
;
3698 if (num_regs
< 1 || num_regs
> 4)
3700 as_bad (_("number of registers must be in the range [1:4]"));
3701 ignore_rest_of_line ();
3705 demand_empty_rest_of_line ();
3710 op
= 0xb4 | (num_regs
- 1);
3711 add_unwind_opcode (op
, 1);
3716 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3717 add_unwind_opcode (op
, 2);
3719 unwind
.frame_size
+= num_regs
* 12;
3723 /* Parse a directive saving VFP registers for ARMv6 and above. */
3726 s_arm_unwind_save_vfp_armv6 (void)
3731 int num_vfpv3_regs
= 0;
3732 int num_regs_below_16
;
3734 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3737 as_bad (_("expected register list"));
3738 ignore_rest_of_line ();
3742 demand_empty_rest_of_line ();
3744 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3745 than FSTMX/FLDMX-style ones). */
3747 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3749 num_vfpv3_regs
= count
;
3750 else if (start
+ count
> 16)
3751 num_vfpv3_regs
= start
+ count
- 16;
3753 if (num_vfpv3_regs
> 0)
3755 int start_offset
= start
> 16 ? start
- 16 : 0;
3756 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3757 add_unwind_opcode (op
, 2);
3760 /* Generate opcode for registers numbered in the range 0 .. 15. */
3761 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3762 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3763 if (num_regs_below_16
> 0)
3765 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3766 add_unwind_opcode (op
, 2);
3769 unwind
.frame_size
+= count
* 8;
3773 /* Parse a directive saving VFP registers for pre-ARMv6. */
3776 s_arm_unwind_save_vfp (void)
3782 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3785 as_bad (_("expected register list"));
3786 ignore_rest_of_line ();
3790 demand_empty_rest_of_line ();
3795 op
= 0xb8 | (count
- 1);
3796 add_unwind_opcode (op
, 1);
3801 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3802 add_unwind_opcode (op
, 2);
3804 unwind
.frame_size
+= count
* 8 + 4;
3808 /* Parse a directive saving iWMMXt data registers. */
3811 s_arm_unwind_save_mmxwr (void)
3819 if (*input_line_pointer
== '{')
3820 input_line_pointer
++;
3824 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3828 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3833 as_tsktsk (_("register list not in ascending order"));
3836 if (*input_line_pointer
== '-')
3838 input_line_pointer
++;
3839 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3842 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3845 else if (reg
>= hi_reg
)
3847 as_bad (_("bad register range"));
3850 for (; reg
< hi_reg
; reg
++)
3854 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3856 if (*input_line_pointer
== '}')
3857 input_line_pointer
++;
3859 demand_empty_rest_of_line ();
3861 /* Generate any deferred opcodes because we're going to be looking at
3863 flush_pending_unwind ();
3865 for (i
= 0; i
< 16; i
++)
3867 if (mask
& (1 << i
))
3868 unwind
.frame_size
+= 8;
3871 /* Attempt to combine with a previous opcode. We do this because gcc
3872 likes to output separate unwind directives for a single block of
3874 if (unwind
.opcode_count
> 0)
3876 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3877 if ((i
& 0xf8) == 0xc0)
3880 /* Only merge if the blocks are contiguous. */
3883 if ((mask
& 0xfe00) == (1 << 9))
3885 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3886 unwind
.opcode_count
--;
3889 else if (i
== 6 && unwind
.opcode_count
>= 2)
3891 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3895 op
= 0xffff << (reg
- 1);
3897 && ((mask
& op
) == (1u << (reg
- 1))))
3899 op
= (1 << (reg
+ i
+ 1)) - 1;
3900 op
&= ~((1 << reg
) - 1);
3902 unwind
.opcode_count
-= 2;
3909 /* We want to generate opcodes in the order the registers have been
3910 saved, ie. descending order. */
3911 for (reg
= 15; reg
>= -1; reg
--)
3913 /* Save registers in blocks. */
3915 || !(mask
& (1 << reg
)))
3917 /* We found an unsaved reg. Generate opcodes to save the
3924 op
= 0xc0 | (hi_reg
- 10);
3925 add_unwind_opcode (op
, 1);
3930 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3931 add_unwind_opcode (op
, 2);
3940 ignore_rest_of_line ();
3944 s_arm_unwind_save_mmxwcg (void)
3951 if (*input_line_pointer
== '{')
3952 input_line_pointer
++;
3956 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3960 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3966 as_tsktsk (_("register list not in ascending order"));
3969 if (*input_line_pointer
== '-')
3971 input_line_pointer
++;
3972 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3975 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3978 else if (reg
>= hi_reg
)
3980 as_bad (_("bad register range"));
3983 for (; reg
< hi_reg
; reg
++)
3987 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3989 if (*input_line_pointer
== '}')
3990 input_line_pointer
++;
3992 demand_empty_rest_of_line ();
3994 /* Generate any deferred opcodes because we're going to be looking at
3996 flush_pending_unwind ();
3998 for (reg
= 0; reg
< 16; reg
++)
4000 if (mask
& (1 << reg
))
4001 unwind
.frame_size
+= 4;
4004 add_unwind_opcode (op
, 2);
4007 ignore_rest_of_line ();
4011 /* Parse an unwind_save directive.
4012 If the argument is non-zero, this is a .vsave directive. */
4015 s_arm_unwind_save (int arch_v6
)
4018 struct reg_entry
*reg
;
4019 bfd_boolean had_brace
= FALSE
;
4021 if (!unwind
.proc_start
)
4022 as_bad (MISSING_FNSTART
);
4024 /* Figure out what sort of save we have. */
4025 peek
= input_line_pointer
;
4033 reg
= arm_reg_parse_multi (&peek
);
4037 as_bad (_("register expected"));
4038 ignore_rest_of_line ();
4047 as_bad (_("FPA .unwind_save does not take a register list"));
4048 ignore_rest_of_line ();
4051 input_line_pointer
= peek
;
4052 s_arm_unwind_save_fpa (reg
->number
);
4055 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4058 s_arm_unwind_save_vfp_armv6 ();
4060 s_arm_unwind_save_vfp ();
4062 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4063 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4066 as_bad (_(".unwind_save does not support this kind of register"));
4067 ignore_rest_of_line ();
4072 /* Parse an unwind_movsp directive. */
4075 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4081 if (!unwind
.proc_start
)
4082 as_bad (MISSING_FNSTART
);
4084 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4087 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4088 ignore_rest_of_line ();
4092 /* Optional constant. */
4093 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4095 if (immediate_for_directive (&offset
) == FAIL
)
4101 demand_empty_rest_of_line ();
4103 if (reg
== REG_SP
|| reg
== REG_PC
)
4105 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4109 if (unwind
.fp_reg
!= REG_SP
)
4110 as_bad (_("unexpected .unwind_movsp directive"));
4112 /* Generate opcode to restore the value. */
4114 add_unwind_opcode (op
, 1);
4116 /* Record the information for later. */
4117 unwind
.fp_reg
= reg
;
4118 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4119 unwind
.sp_restored
= 1;
4122 /* Parse an unwind_pad directive. */
4125 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4129 if (!unwind
.proc_start
)
4130 as_bad (MISSING_FNSTART
);
4132 if (immediate_for_directive (&offset
) == FAIL
)
4137 as_bad (_("stack increment must be multiple of 4"));
4138 ignore_rest_of_line ();
4142 /* Don't generate any opcodes, just record the details for later. */
4143 unwind
.frame_size
+= offset
;
4144 unwind
.pending_offset
+= offset
;
4146 demand_empty_rest_of_line ();
4149 /* Parse an unwind_setfp directive. */
4152 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4158 if (!unwind
.proc_start
)
4159 as_bad (MISSING_FNSTART
);
4161 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4162 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4165 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4167 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4169 as_bad (_("expected <reg>, <reg>"));
4170 ignore_rest_of_line ();
4174 /* Optional constant. */
4175 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4177 if (immediate_for_directive (&offset
) == FAIL
)
4183 demand_empty_rest_of_line ();
4185 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4187 as_bad (_("register must be either sp or set by a previous"
4188 "unwind_movsp directive"));
4192 /* Don't generate any opcodes, just record the information for later. */
4193 unwind
.fp_reg
= fp_reg
;
4195 if (sp_reg
== REG_SP
)
4196 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4198 unwind
.fp_offset
-= offset
;
4201 /* Parse an unwind_raw directive. */
4204 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4207 /* This is an arbitrary limit. */
4208 unsigned char op
[16];
4211 if (!unwind
.proc_start
)
4212 as_bad (MISSING_FNSTART
);
4215 if (exp
.X_op
== O_constant
4216 && skip_past_comma (&input_line_pointer
) != FAIL
)
4218 unwind
.frame_size
+= exp
.X_add_number
;
4222 exp
.X_op
= O_illegal
;
4224 if (exp
.X_op
!= O_constant
)
4226 as_bad (_("expected <offset>, <opcode>"));
4227 ignore_rest_of_line ();
4233 /* Parse the opcode. */
4238 as_bad (_("unwind opcode too long"));
4239 ignore_rest_of_line ();
4241 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4243 as_bad (_("invalid unwind opcode"));
4244 ignore_rest_of_line ();
4247 op
[count
++] = exp
.X_add_number
;
4249 /* Parse the next byte. */
4250 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4256 /* Add the opcode bytes in reverse order. */
4258 add_unwind_opcode (op
[count
], 1);
4260 demand_empty_rest_of_line ();
4264 /* Parse a .eabi_attribute directive. */
4267 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4269 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4271 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4272 attributes_set_explicitly
[tag
] = 1;
4274 #endif /* OBJ_ELF */
4276 static void s_arm_arch (int);
4277 static void s_arm_object_arch (int);
4278 static void s_arm_cpu (int);
4279 static void s_arm_fpu (int);
4280 static void s_arm_arch_extension (int);
4285 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4292 if (exp
.X_op
== O_symbol
)
4293 exp
.X_op
= O_secrel
;
4295 emit_expr (&exp
, 4);
4297 while (*input_line_pointer
++ == ',');
4299 input_line_pointer
--;
4300 demand_empty_rest_of_line ();
4304 /* This table describes all the machine specific pseudo-ops the assembler
4305 has to support. The fields are:
4306 pseudo-op name without dot
4307 function to call to execute this pseudo-op
4308 Integer arg to pass to the function. */
4310 const pseudo_typeS md_pseudo_table
[] =
4312 /* Never called because '.req' does not start a line. */
4313 { "req", s_req
, 0 },
4314 /* Following two are likewise never called. */
4317 { "unreq", s_unreq
, 0 },
4318 { "bss", s_bss
, 0 },
4319 { "align", s_align
, 0 },
4320 { "arm", s_arm
, 0 },
4321 { "thumb", s_thumb
, 0 },
4322 { "code", s_code
, 0 },
4323 { "force_thumb", s_force_thumb
, 0 },
4324 { "thumb_func", s_thumb_func
, 0 },
4325 { "thumb_set", s_thumb_set
, 0 },
4326 { "even", s_even
, 0 },
4327 { "ltorg", s_ltorg
, 0 },
4328 { "pool", s_ltorg
, 0 },
4329 { "syntax", s_syntax
, 0 },
4330 { "cpu", s_arm_cpu
, 0 },
4331 { "arch", s_arm_arch
, 0 },
4332 { "object_arch", s_arm_object_arch
, 0 },
4333 { "fpu", s_arm_fpu
, 0 },
4334 { "arch_extension", s_arm_arch_extension
, 0 },
4336 { "word", s_arm_elf_cons
, 4 },
4337 { "long", s_arm_elf_cons
, 4 },
4338 { "inst.n", s_arm_elf_inst
, 2 },
4339 { "inst.w", s_arm_elf_inst
, 4 },
4340 { "inst", s_arm_elf_inst
, 0 },
4341 { "rel31", s_arm_rel31
, 0 },
4342 { "fnstart", s_arm_unwind_fnstart
, 0 },
4343 { "fnend", s_arm_unwind_fnend
, 0 },
4344 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4345 { "personality", s_arm_unwind_personality
, 0 },
4346 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4347 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4348 { "save", s_arm_unwind_save
, 0 },
4349 { "vsave", s_arm_unwind_save
, 1 },
4350 { "movsp", s_arm_unwind_movsp
, 0 },
4351 { "pad", s_arm_unwind_pad
, 0 },
4352 { "setfp", s_arm_unwind_setfp
, 0 },
4353 { "unwind_raw", s_arm_unwind_raw
, 0 },
4354 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4358 /* These are used for dwarf. */
4362 /* These are used for dwarf2. */
4363 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4364 { "loc", dwarf2_directive_loc
, 0 },
4365 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4367 { "extend", float_cons
, 'x' },
4368 { "ldouble", float_cons
, 'x' },
4369 { "packed", float_cons
, 'p' },
4371 {"secrel32", pe_directive_secrel
, 0},
4376 /* Parser functions used exclusively in instruction operands. */
4378 /* Generic immediate-value read function for use in insn parsing.
4379 STR points to the beginning of the immediate (the leading #);
4380 VAL receives the value; if the value is outside [MIN, MAX]
4381 issue an error. PREFIX_OPT is true if the immediate prefix is
4385 parse_immediate (char **str
, int *val
, int min
, int max
,
4386 bfd_boolean prefix_opt
)
4389 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4390 if (exp
.X_op
!= O_constant
)
4392 inst
.error
= _("constant expression required");
4396 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4398 inst
.error
= _("immediate value out of range");
4402 *val
= exp
.X_add_number
;
4406 /* Less-generic immediate-value read function with the possibility of loading a
4407 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4408 instructions. Puts the result directly in inst.operands[i]. */
4411 parse_big_immediate (char **str
, int i
)
4416 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4418 if (exp
.X_op
== O_constant
)
4420 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4421 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4422 O_constant. We have to be careful not to break compilation for
4423 32-bit X_add_number, though. */
4424 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4426 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4427 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4428 inst
.operands
[i
].regisimm
= 1;
4431 else if (exp
.X_op
== O_big
4432 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4434 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4436 /* Bignums have their least significant bits in
4437 generic_bignum[0]. Make sure we put 32 bits in imm and
4438 32 bits in reg, in a (hopefully) portable way. */
4439 gas_assert (parts
!= 0);
4441 /* Make sure that the number is not too big.
4442 PR 11972: Bignums can now be sign-extended to the
4443 size of a .octa so check that the out of range bits
4444 are all zero or all one. */
4445 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4447 LITTLENUM_TYPE m
= -1;
4449 if (generic_bignum
[parts
* 2] != 0
4450 && generic_bignum
[parts
* 2] != m
)
4453 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4454 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4458 inst
.operands
[i
].imm
= 0;
4459 for (j
= 0; j
< parts
; j
++, idx
++)
4460 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4461 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4462 inst
.operands
[i
].reg
= 0;
4463 for (j
= 0; j
< parts
; j
++, idx
++)
4464 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4465 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4466 inst
.operands
[i
].regisimm
= 1;
4476 /* Returns the pseudo-register number of an FPA immediate constant,
4477 or FAIL if there isn't a valid constant here. */
4480 parse_fpa_immediate (char ** str
)
4482 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4488 /* First try and match exact strings, this is to guarantee
4489 that some formats will work even for cross assembly. */
4491 for (i
= 0; fp_const
[i
]; i
++)
4493 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4497 *str
+= strlen (fp_const
[i
]);
4498 if (is_end_of_line
[(unsigned char) **str
])
4504 /* Just because we didn't get a match doesn't mean that the constant
4505 isn't valid, just that it is in a format that we don't
4506 automatically recognize. Try parsing it with the standard
4507 expression routines. */
4509 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4511 /* Look for a raw floating point number. */
4512 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4513 && is_end_of_line
[(unsigned char) *save_in
])
4515 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4517 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4519 if (words
[j
] != fp_values
[i
][j
])
4523 if (j
== MAX_LITTLENUMS
)
4531 /* Try and parse a more complex expression, this will probably fail
4532 unless the code uses a floating point prefix (eg "0f"). */
4533 save_in
= input_line_pointer
;
4534 input_line_pointer
= *str
;
4535 if (expression (&exp
) == absolute_section
4536 && exp
.X_op
== O_big
4537 && exp
.X_add_number
< 0)
4539 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4541 if (gen_to_words (words
, 5, (long) 15) == 0)
4543 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4545 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4547 if (words
[j
] != fp_values
[i
][j
])
4551 if (j
== MAX_LITTLENUMS
)
4553 *str
= input_line_pointer
;
4554 input_line_pointer
= save_in
;
4561 *str
= input_line_pointer
;
4562 input_line_pointer
= save_in
;
4563 inst
.error
= _("invalid FPA immediate expression");
4567 /* Returns 1 if a number has "quarter-precision" float format
4568 0baBbbbbbc defgh000 00000000 00000000. */
4571 is_quarter_float (unsigned imm
)
4573 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4574 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4577 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4578 0baBbbbbbc defgh000 00000000 00000000.
4579 The zero and minus-zero cases need special handling, since they can't be
4580 encoded in the "quarter-precision" float format, but can nonetheless be
4581 loaded as integer constants. */
4584 parse_qfloat_immediate (char **ccp
, int *immed
)
4588 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4589 int found_fpchar
= 0;
4591 skip_past_char (&str
, '#');
4593 /* We must not accidentally parse an integer as a floating-point number. Make
4594 sure that the value we parse is not an integer by checking for special
4595 characters '.' or 'e'.
4596 FIXME: This is a horrible hack, but doing better is tricky because type
4597 information isn't in a very usable state at parse time. */
4599 skip_whitespace (fpnum
);
4601 if (strncmp (fpnum
, "0x", 2) == 0)
4605 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4606 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4616 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4618 unsigned fpword
= 0;
4621 /* Our FP word must be 32 bits (single-precision FP). */
4622 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4624 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4628 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4641 /* Shift operands. */
4644 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4647 struct asm_shift_name
4650 enum shift_kind kind
;
4653 /* Third argument to parse_shift. */
4654 enum parse_shift_mode
4656 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4657 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4658 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4659 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4660 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4663 /* Parse a <shift> specifier on an ARM data processing instruction.
4664 This has three forms:
4666 (LSL|LSR|ASL|ASR|ROR) Rs
4667 (LSL|LSR|ASL|ASR|ROR) #imm
4670 Note that ASL is assimilated to LSL in the instruction encoding, and
4671 RRX to ROR #0 (which cannot be written as such). */
4674 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4676 const struct asm_shift_name
*shift_name
;
4677 enum shift_kind shift
;
4682 for (p
= *str
; ISALPHA (*p
); p
++)
4687 inst
.error
= _("shift expression expected");
4691 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4694 if (shift_name
== NULL
)
4696 inst
.error
= _("shift expression expected");
4700 shift
= shift_name
->kind
;
4704 case NO_SHIFT_RESTRICT
:
4705 case SHIFT_IMMEDIATE
: break;
4707 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4708 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4710 inst
.error
= _("'LSL' or 'ASR' required");
4715 case SHIFT_LSL_IMMEDIATE
:
4716 if (shift
!= SHIFT_LSL
)
4718 inst
.error
= _("'LSL' required");
4723 case SHIFT_ASR_IMMEDIATE
:
4724 if (shift
!= SHIFT_ASR
)
4726 inst
.error
= _("'ASR' required");
4734 if (shift
!= SHIFT_RRX
)
4736 /* Whitespace can appear here if the next thing is a bare digit. */
4737 skip_whitespace (p
);
4739 if (mode
== NO_SHIFT_RESTRICT
4740 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4742 inst
.operands
[i
].imm
= reg
;
4743 inst
.operands
[i
].immisreg
= 1;
4745 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4748 inst
.operands
[i
].shift_kind
= shift
;
4749 inst
.operands
[i
].shifted
= 1;
4754 /* Parse a <shifter_operand> for an ARM data processing instruction:
4757 #<immediate>, <rotate>
4761 where <shift> is defined by parse_shift above, and <rotate> is a
4762 multiple of 2 between 0 and 30. Validation of immediate operands
4763 is deferred to md_apply_fix. */
4766 parse_shifter_operand (char **str
, int i
)
4771 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4773 inst
.operands
[i
].reg
= value
;
4774 inst
.operands
[i
].isreg
= 1;
4776 /* parse_shift will override this if appropriate */
4777 inst
.reloc
.exp
.X_op
= O_constant
;
4778 inst
.reloc
.exp
.X_add_number
= 0;
4780 if (skip_past_comma (str
) == FAIL
)
4783 /* Shift operation on register. */
4784 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4787 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4790 if (skip_past_comma (str
) == SUCCESS
)
4792 /* #x, y -- ie explicit rotation by Y. */
4793 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4796 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4798 inst
.error
= _("constant expression expected");
4802 value
= exp
.X_add_number
;
4803 if (value
< 0 || value
> 30 || value
% 2 != 0)
4805 inst
.error
= _("invalid rotation");
4808 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4810 inst
.error
= _("invalid constant");
4814 /* Convert to decoded value. md_apply_fix will put it back. */
4815 inst
.reloc
.exp
.X_add_number
4816 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4817 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4820 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4821 inst
.reloc
.pc_rel
= 0;
4825 /* Group relocation information. Each entry in the table contains the
4826 textual name of the relocation as may appear in assembler source
4827 and must end with a colon.
4828 Along with this textual name are the relocation codes to be used if
4829 the corresponding instruction is an ALU instruction (ADD or SUB only),
4830 an LDR, an LDRS, or an LDC. */
4832 struct group_reloc_table_entry
4843 /* Varieties of non-ALU group relocation. */
4850 static struct group_reloc_table_entry group_reloc_table
[] =
4851 { /* Program counter relative: */
4853 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4858 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4859 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4860 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4861 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4863 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4868 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4869 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4870 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4871 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4873 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4874 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4875 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4876 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4877 /* Section base relative */
4879 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4884 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4885 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4886 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4887 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4889 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4894 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4895 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4896 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4897 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4899 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4900 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4901 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4902 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4904 /* Given the address of a pointer pointing to the textual name of a group
4905 relocation as may appear in assembler source, attempt to find its details
4906 in group_reloc_table. The pointer will be updated to the character after
4907 the trailing colon. On failure, FAIL will be returned; SUCCESS
4908 otherwise. On success, *entry will be updated to point at the relevant
4909 group_reloc_table entry. */
4912 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4915 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4917 int length
= strlen (group_reloc_table
[i
].name
);
4919 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4920 && (*str
)[length
] == ':')
4922 *out
= &group_reloc_table
[i
];
4923 *str
+= (length
+ 1);
4931 /* Parse a <shifter_operand> for an ARM data processing instruction
4932 (as for parse_shifter_operand) where group relocations are allowed:
4935 #<immediate>, <rotate>
4936 #:<group_reloc>:<expression>
4940 where <group_reloc> is one of the strings defined in group_reloc_table.
4941 The hashes are optional.
4943 Everything else is as for parse_shifter_operand. */
4945 static parse_operand_result
4946 parse_shifter_operand_group_reloc (char **str
, int i
)
4948 /* Determine if we have the sequence of characters #: or just :
4949 coming next. If we do, then we check for a group relocation.
4950 If we don't, punt the whole lot to parse_shifter_operand. */
4952 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4953 || (*str
)[0] == ':')
4955 struct group_reloc_table_entry
*entry
;
4957 if ((*str
)[0] == '#')
4962 /* Try to parse a group relocation. Anything else is an error. */
4963 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4965 inst
.error
= _("unknown group relocation");
4966 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4969 /* We now have the group relocation table entry corresponding to
4970 the name in the assembler source. Next, we parse the expression. */
4971 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4972 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4974 /* Record the relocation type (always the ALU variant here). */
4975 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4976 gas_assert (inst
.reloc
.type
!= 0);
4978 return PARSE_OPERAND_SUCCESS
;
4981 return parse_shifter_operand (str
, i
) == SUCCESS
4982 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4984 /* Never reached. */
4987 /* Parse a Neon alignment expression. Information is written to
4988 inst.operands[i]. We assume the initial ':' has been skipped.
4990 align .imm = align << 8, .immisalign=1, .preind=0 */
4991 static parse_operand_result
4992 parse_neon_alignment (char **str
, int i
)
4997 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4999 if (exp
.X_op
!= O_constant
)
5001 inst
.error
= _("alignment must be constant");
5002 return PARSE_OPERAND_FAIL
;
5005 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5006 inst
.operands
[i
].immisalign
= 1;
5007 /* Alignments are not pre-indexes. */
5008 inst
.operands
[i
].preind
= 0;
5011 return PARSE_OPERAND_SUCCESS
;
5014 /* Parse all forms of an ARM address expression. Information is written
5015 to inst.operands[i] and/or inst.reloc.
5017 Preindexed addressing (.preind=1):
5019 [Rn, #offset] .reg=Rn .reloc.exp=offset
5020 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5021 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5022 .shift_kind=shift .reloc.exp=shift_imm
5024 These three may have a trailing ! which causes .writeback to be set also.
5026 Postindexed addressing (.postind=1, .writeback=1):
5028 [Rn], #offset .reg=Rn .reloc.exp=offset
5029 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5030 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5031 .shift_kind=shift .reloc.exp=shift_imm
5033 Unindexed addressing (.preind=0, .postind=0):
5035 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5039 [Rn]{!} shorthand for [Rn,#0]{!}
5040 =immediate .isreg=0 .reloc.exp=immediate
5041 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5043 It is the caller's responsibility to check for addressing modes not
5044 supported by the instruction, and to set inst.reloc.type. */
5046 static parse_operand_result
5047 parse_address_main (char **str
, int i
, int group_relocations
,
5048 group_reloc_type group_type
)
5053 if (skip_past_char (&p
, '[') == FAIL
)
5055 if (skip_past_char (&p
, '=') == FAIL
)
5057 /* Bare address - translate to PC-relative offset. */
5058 inst
.reloc
.pc_rel
= 1;
5059 inst
.operands
[i
].reg
= REG_PC
;
5060 inst
.operands
[i
].isreg
= 1;
5061 inst
.operands
[i
].preind
= 1;
5063 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5065 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5066 return PARSE_OPERAND_FAIL
;
5069 return PARSE_OPERAND_SUCCESS
;
5072 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5074 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5075 return PARSE_OPERAND_FAIL
;
5077 inst
.operands
[i
].reg
= reg
;
5078 inst
.operands
[i
].isreg
= 1;
5080 if (skip_past_comma (&p
) == SUCCESS
)
5082 inst
.operands
[i
].preind
= 1;
5085 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5087 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5089 inst
.operands
[i
].imm
= reg
;
5090 inst
.operands
[i
].immisreg
= 1;
5092 if (skip_past_comma (&p
) == SUCCESS
)
5093 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5094 return PARSE_OPERAND_FAIL
;
5096 else if (skip_past_char (&p
, ':') == SUCCESS
)
5098 /* FIXME: '@' should be used here, but it's filtered out by generic
5099 code before we get to see it here. This may be subject to
5101 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5103 if (result
!= PARSE_OPERAND_SUCCESS
)
5108 if (inst
.operands
[i
].negative
)
5110 inst
.operands
[i
].negative
= 0;
5114 if (group_relocations
5115 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5117 struct group_reloc_table_entry
*entry
;
5119 /* Skip over the #: or : sequence. */
5125 /* Try to parse a group relocation. Anything else is an
5127 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5129 inst
.error
= _("unknown group relocation");
5130 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5133 /* We now have the group relocation table entry corresponding to
5134 the name in the assembler source. Next, we parse the
5136 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5137 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5139 /* Record the relocation type. */
5143 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5147 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5151 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5158 if (inst
.reloc
.type
== 0)
5160 inst
.error
= _("this group relocation is not allowed on this instruction");
5161 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5165 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5166 return PARSE_OPERAND_FAIL
;
5169 else if (skip_past_char (&p
, ':') == SUCCESS
)
5171 /* FIXME: '@' should be used here, but it's filtered out by generic code
5172 before we get to see it here. This may be subject to change. */
5173 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5175 if (result
!= PARSE_OPERAND_SUCCESS
)
5179 if (skip_past_char (&p
, ']') == FAIL
)
5181 inst
.error
= _("']' expected");
5182 return PARSE_OPERAND_FAIL
;
5185 if (skip_past_char (&p
, '!') == SUCCESS
)
5186 inst
.operands
[i
].writeback
= 1;
5188 else if (skip_past_comma (&p
) == SUCCESS
)
5190 if (skip_past_char (&p
, '{') == SUCCESS
)
5192 /* [Rn], {expr} - unindexed, with option */
5193 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5194 0, 255, TRUE
) == FAIL
)
5195 return PARSE_OPERAND_FAIL
;
5197 if (skip_past_char (&p
, '}') == FAIL
)
5199 inst
.error
= _("'}' expected at end of 'option' field");
5200 return PARSE_OPERAND_FAIL
;
5202 if (inst
.operands
[i
].preind
)
5204 inst
.error
= _("cannot combine index with option");
5205 return PARSE_OPERAND_FAIL
;
5208 return PARSE_OPERAND_SUCCESS
;
5212 inst
.operands
[i
].postind
= 1;
5213 inst
.operands
[i
].writeback
= 1;
5215 if (inst
.operands
[i
].preind
)
5217 inst
.error
= _("cannot combine pre- and post-indexing");
5218 return PARSE_OPERAND_FAIL
;
5222 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5224 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5226 /* We might be using the immediate for alignment already. If we
5227 are, OR the register number into the low-order bits. */
5228 if (inst
.operands
[i
].immisalign
)
5229 inst
.operands
[i
].imm
|= reg
;
5231 inst
.operands
[i
].imm
= reg
;
5232 inst
.operands
[i
].immisreg
= 1;
5234 if (skip_past_comma (&p
) == SUCCESS
)
5235 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5236 return PARSE_OPERAND_FAIL
;
5240 if (inst
.operands
[i
].negative
)
5242 inst
.operands
[i
].negative
= 0;
5245 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5246 return PARSE_OPERAND_FAIL
;
5251 /* If at this point neither .preind nor .postind is set, we have a
5252 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5253 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5255 inst
.operands
[i
].preind
= 1;
5256 inst
.reloc
.exp
.X_op
= O_constant
;
5257 inst
.reloc
.exp
.X_add_number
= 0;
5260 return PARSE_OPERAND_SUCCESS
;
5264 parse_address (char **str
, int i
)
5266 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5270 static parse_operand_result
5271 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5273 return parse_address_main (str
, i
, 1, type
);
5276 /* Parse an operand for a MOVW or MOVT instruction. */
5278 parse_half (char **str
)
5283 skip_past_char (&p
, '#');
5284 if (strncasecmp (p
, ":lower16:", 9) == 0)
5285 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5286 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5287 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5289 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5292 skip_whitespace (p
);
5295 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5298 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5300 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5302 inst
.error
= _("constant expression expected");
5305 if (inst
.reloc
.exp
.X_add_number
< 0
5306 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5308 inst
.error
= _("immediate value out of range");
5316 /* Miscellaneous. */
5318 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5319 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5321 parse_psr (char **str
)
5324 unsigned long psr_field
;
5325 const struct asm_psr
*psr
;
5328 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5329 feature for ease of use and backwards compatibility. */
5331 if (strncasecmp (p
, "SPSR", 4) == 0)
5332 psr_field
= SPSR_BIT
;
5333 else if (strncasecmp (p
, "CPSR", 4) == 0
5334 || (strncasecmp (p
, "APSR", 4) == 0
5335 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
)))
5342 while (ISALNUM (*p
) || *p
== '_');
5344 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5356 /* A suffix follows. */
5362 while (ISALNUM (*p
) || *p
== '_');
5364 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5369 psr_field
|= psr
->field
;
5374 goto error
; /* Garbage after "[CS]PSR". */
5376 psr_field
|= (PSR_c
| PSR_f
);
5382 inst
.error
= _("flag for {c}psr instruction expected");
5386 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5387 value suitable for splatting into the AIF field of the instruction. */
5390 parse_cps_flags (char **str
)
5399 case '\0': case ',':
5402 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5403 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5404 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5407 inst
.error
= _("unrecognized CPS flag");
5412 if (saw_a_flag
== 0)
5414 inst
.error
= _("missing CPS flags");
5422 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5423 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5426 parse_endian_specifier (char **str
)
5431 if (strncasecmp (s
, "BE", 2))
5433 else if (strncasecmp (s
, "LE", 2))
5437 inst
.error
= _("valid endian specifiers are be or le");
5441 if (ISALNUM (s
[2]) || s
[2] == '_')
5443 inst
.error
= _("valid endian specifiers are be or le");
5448 return little_endian
;
5451 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5452 value suitable for poking into the rotate field of an sxt or sxta
5453 instruction, or FAIL on error. */
5456 parse_ror (char **str
)
5461 if (strncasecmp (s
, "ROR", 3) == 0)
5465 inst
.error
= _("missing rotation field after comma");
5469 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5474 case 0: *str
= s
; return 0x0;
5475 case 8: *str
= s
; return 0x1;
5476 case 16: *str
= s
; return 0x2;
5477 case 24: *str
= s
; return 0x3;
5480 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5485 /* Parse a conditional code (from conds[] below). The value returned is in the
5486 range 0 .. 14, or FAIL. */
5488 parse_cond (char **str
)
5491 const struct asm_cond
*c
;
5493 /* Condition codes are always 2 characters, so matching up to
5494 3 characters is sufficient. */
5499 while (ISALPHA (*q
) && n
< 3)
5501 cond
[n
] = TOLOWER (*q
);
5506 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5509 inst
.error
= _("condition required");
5517 /* Parse an option for a barrier instruction. Returns the encoding for the
5520 parse_barrier (char **str
)
5523 const struct asm_barrier_opt
*o
;
5526 while (ISALPHA (*q
))
5529 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5538 /* Parse the operands of a table branch instruction. Similar to a memory
5541 parse_tb (char **str
)
5546 if (skip_past_char (&p
, '[') == FAIL
)
5548 inst
.error
= _("'[' expected");
5552 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5554 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5557 inst
.operands
[0].reg
= reg
;
5559 if (skip_past_comma (&p
) == FAIL
)
5561 inst
.error
= _("',' expected");
5565 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5567 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5570 inst
.operands
[0].imm
= reg
;
5572 if (skip_past_comma (&p
) == SUCCESS
)
5574 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5576 if (inst
.reloc
.exp
.X_add_number
!= 1)
5578 inst
.error
= _("invalid shift");
5581 inst
.operands
[0].shifted
= 1;
5584 if (skip_past_char (&p
, ']') == FAIL
)
5586 inst
.error
= _("']' expected");
5593 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5594 information on the types the operands can take and how they are encoded.
5595 Up to four operands may be read; this function handles setting the
5596 ".present" field for each read operand itself.
5597 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5598 else returns FAIL. */
5601 parse_neon_mov (char **str
, int *which_operand
)
5603 int i
= *which_operand
, val
;
5604 enum arm_reg_type rtype
;
5606 struct neon_type_el optype
;
5608 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5610 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5611 inst
.operands
[i
].reg
= val
;
5612 inst
.operands
[i
].isscalar
= 1;
5613 inst
.operands
[i
].vectype
= optype
;
5614 inst
.operands
[i
++].present
= 1;
5616 if (skip_past_comma (&ptr
) == FAIL
)
5619 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5622 inst
.operands
[i
].reg
= val
;
5623 inst
.operands
[i
].isreg
= 1;
5624 inst
.operands
[i
].present
= 1;
5626 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5629 /* Cases 0, 1, 2, 3, 5 (D only). */
5630 if (skip_past_comma (&ptr
) == FAIL
)
5633 inst
.operands
[i
].reg
= val
;
5634 inst
.operands
[i
].isreg
= 1;
5635 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5636 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5637 inst
.operands
[i
].isvec
= 1;
5638 inst
.operands
[i
].vectype
= optype
;
5639 inst
.operands
[i
++].present
= 1;
5641 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5643 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5644 Case 13: VMOV <Sd>, <Rm> */
5645 inst
.operands
[i
].reg
= val
;
5646 inst
.operands
[i
].isreg
= 1;
5647 inst
.operands
[i
].present
= 1;
5649 if (rtype
== REG_TYPE_NQ
)
5651 first_error (_("can't use Neon quad register here"));
5654 else if (rtype
!= REG_TYPE_VFS
)
5657 if (skip_past_comma (&ptr
) == FAIL
)
5659 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5661 inst
.operands
[i
].reg
= val
;
5662 inst
.operands
[i
].isreg
= 1;
5663 inst
.operands
[i
].present
= 1;
5666 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5669 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5670 Case 1: VMOV<c><q> <Dd>, <Dm>
5671 Case 8: VMOV.F32 <Sd>, <Sm>
5672 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5674 inst
.operands
[i
].reg
= val
;
5675 inst
.operands
[i
].isreg
= 1;
5676 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5677 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5678 inst
.operands
[i
].isvec
= 1;
5679 inst
.operands
[i
].vectype
= optype
;
5680 inst
.operands
[i
].present
= 1;
5682 if (skip_past_comma (&ptr
) == SUCCESS
)
5687 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5690 inst
.operands
[i
].reg
= val
;
5691 inst
.operands
[i
].isreg
= 1;
5692 inst
.operands
[i
++].present
= 1;
5694 if (skip_past_comma (&ptr
) == FAIL
)
5697 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5700 inst
.operands
[i
].reg
= val
;
5701 inst
.operands
[i
].isreg
= 1;
5702 inst
.operands
[i
++].present
= 1;
5705 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5706 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5707 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5708 Case 10: VMOV.F32 <Sd>, #<imm>
5709 Case 11: VMOV.F64 <Dd>, #<imm> */
5710 inst
.operands
[i
].immisfloat
= 1;
5711 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5712 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5713 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5717 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5721 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5724 inst
.operands
[i
].reg
= val
;
5725 inst
.operands
[i
].isreg
= 1;
5726 inst
.operands
[i
++].present
= 1;
5728 if (skip_past_comma (&ptr
) == FAIL
)
5731 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5733 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5734 inst
.operands
[i
].reg
= val
;
5735 inst
.operands
[i
].isscalar
= 1;
5736 inst
.operands
[i
].present
= 1;
5737 inst
.operands
[i
].vectype
= optype
;
5739 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5741 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5742 inst
.operands
[i
].reg
= val
;
5743 inst
.operands
[i
].isreg
= 1;
5744 inst
.operands
[i
++].present
= 1;
5746 if (skip_past_comma (&ptr
) == FAIL
)
5749 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5752 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5756 inst
.operands
[i
].reg
= val
;
5757 inst
.operands
[i
].isreg
= 1;
5758 inst
.operands
[i
].isvec
= 1;
5759 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5760 inst
.operands
[i
].vectype
= optype
;
5761 inst
.operands
[i
].present
= 1;
5763 if (rtype
== REG_TYPE_VFS
)
5767 if (skip_past_comma (&ptr
) == FAIL
)
5769 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5772 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5775 inst
.operands
[i
].reg
= val
;
5776 inst
.operands
[i
].isreg
= 1;
5777 inst
.operands
[i
].isvec
= 1;
5778 inst
.operands
[i
].issingle
= 1;
5779 inst
.operands
[i
].vectype
= optype
;
5780 inst
.operands
[i
].present
= 1;
5783 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5787 inst
.operands
[i
].reg
= val
;
5788 inst
.operands
[i
].isreg
= 1;
5789 inst
.operands
[i
].isvec
= 1;
5790 inst
.operands
[i
].issingle
= 1;
5791 inst
.operands
[i
].vectype
= optype
;
5792 inst
.operands
[i
++].present
= 1;
5797 first_error (_("parse error"));
5801 /* Successfully parsed the operands. Update args. */
5807 first_error (_("expected comma"));
5811 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5815 /* Use this macro when the operand constraints are different
5816 for ARM and THUMB (e.g. ldrd). */
5817 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5818 ((arm_operand) | ((thumb_operand) << 16))
5820 /* Matcher codes for parse_operands. */
5821 enum operand_parse_code
5823 OP_stop
, /* end of line */
5825 OP_RR
, /* ARM register */
5826 OP_RRnpc
, /* ARM register, not r15 */
5827 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5828 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5829 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5830 optional trailing ! */
5831 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5832 OP_RCP
, /* Coprocessor number */
5833 OP_RCN
, /* Coprocessor register */
5834 OP_RF
, /* FPA register */
5835 OP_RVS
, /* VFP single precision register */
5836 OP_RVD
, /* VFP double precision register (0..15) */
5837 OP_RND
, /* Neon double precision register (0..31) */
5838 OP_RNQ
, /* Neon quad precision register */
5839 OP_RVSD
, /* VFP single or double precision register */
5840 OP_RNDQ
, /* Neon double or quad precision register */
5841 OP_RNSDQ
, /* Neon single, double or quad precision register */
5842 OP_RNSC
, /* Neon scalar D[X] */
5843 OP_RVC
, /* VFP control register */
5844 OP_RMF
, /* Maverick F register */
5845 OP_RMD
, /* Maverick D register */
5846 OP_RMFX
, /* Maverick FX register */
5847 OP_RMDX
, /* Maverick DX register */
5848 OP_RMAX
, /* Maverick AX register */
5849 OP_RMDS
, /* Maverick DSPSC register */
5850 OP_RIWR
, /* iWMMXt wR register */
5851 OP_RIWC
, /* iWMMXt wC register */
5852 OP_RIWG
, /* iWMMXt wCG register */
5853 OP_RXA
, /* XScale accumulator register */
5855 OP_REGLST
, /* ARM register list */
5856 OP_VRSLST
, /* VFP single-precision register list */
5857 OP_VRDLST
, /* VFP double-precision register list */
5858 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5859 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5860 OP_NSTRLST
, /* Neon element/structure list */
5862 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5863 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5864 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5865 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5866 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5867 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5868 OP_VMOV
, /* Neon VMOV operands. */
5869 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5870 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5871 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5873 OP_I0
, /* immediate zero */
5874 OP_I7
, /* immediate value 0 .. 7 */
5875 OP_I15
, /* 0 .. 15 */
5876 OP_I16
, /* 1 .. 16 */
5877 OP_I16z
, /* 0 .. 16 */
5878 OP_I31
, /* 0 .. 31 */
5879 OP_I31w
, /* 0 .. 31, optional trailing ! */
5880 OP_I32
, /* 1 .. 32 */
5881 OP_I32z
, /* 0 .. 32 */
5882 OP_I63
, /* 0 .. 63 */
5883 OP_I63s
, /* -64 .. 63 */
5884 OP_I64
, /* 1 .. 64 */
5885 OP_I64z
, /* 0 .. 64 */
5886 OP_I255
, /* 0 .. 255 */
5888 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5889 OP_I7b
, /* 0 .. 7 */
5890 OP_I15b
, /* 0 .. 15 */
5891 OP_I31b
, /* 0 .. 31 */
5893 OP_SH
, /* shifter operand */
5894 OP_SHG
, /* shifter operand with possible group relocation */
5895 OP_ADDR
, /* Memory address expression (any mode) */
5896 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5897 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5898 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5899 OP_EXP
, /* arbitrary expression */
5900 OP_EXPi
, /* same, with optional immediate prefix */
5901 OP_EXPr
, /* same, with optional relocation suffix */
5902 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5904 OP_CPSF
, /* CPS flags */
5905 OP_ENDI
, /* Endianness specifier */
5906 OP_PSR
, /* CPSR/SPSR mask for msr */
5907 OP_COND
, /* conditional code */
5908 OP_TB
, /* Table branch. */
5910 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5911 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5913 OP_RRnpc_I0
, /* ARM register or literal 0 */
5914 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5915 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5916 OP_RF_IF
, /* FPA register or immediate */
5917 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5918 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5920 /* Optional operands. */
5921 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5922 OP_oI31b
, /* 0 .. 31 */
5923 OP_oI32b
, /* 1 .. 32 */
5924 OP_oIffffb
, /* 0 .. 65535 */
5925 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5927 OP_oRR
, /* ARM register */
5928 OP_oRRnpc
, /* ARM register, not the PC */
5929 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5930 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5931 OP_oRND
, /* Optional Neon double precision register */
5932 OP_oRNQ
, /* Optional Neon quad precision register */
5933 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5934 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5935 OP_oSHll
, /* LSL immediate */
5936 OP_oSHar
, /* ASR immediate */
5937 OP_oSHllar
, /* LSL or ASR immediate */
5938 OP_oROR
, /* ROR 0/8/16/24 */
5939 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5941 /* Some pre-defined mixed (ARM/THUMB) operands. */
5942 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5943 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5944 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5946 OP_FIRST_OPTIONAL
= OP_oI7b
5949 /* Generic instruction operand parser. This does no encoding and no
5950 semantic validation; it merely squirrels values away in the inst
5951 structure. Returns SUCCESS or FAIL depending on whether the
5952 specified grammar matched. */
5954 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5956 unsigned const int *upat
= pattern
;
5957 char *backtrack_pos
= 0;
5958 const char *backtrack_error
= 0;
5959 int i
, val
, backtrack_index
= 0;
5960 enum arm_reg_type rtype
;
5961 parse_operand_result result
;
5962 unsigned int op_parse_code
;
5964 #define po_char_or_fail(chr) \
5967 if (skip_past_char (&str, chr) == FAIL) \
5972 #define po_reg_or_fail(regtype) \
5975 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5976 & inst.operands[i].vectype); \
5979 first_error (_(reg_expected_msgs[regtype])); \
5982 inst.operands[i].reg = val; \
5983 inst.operands[i].isreg = 1; \
5984 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5985 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5986 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5987 || rtype == REG_TYPE_VFD \
5988 || rtype == REG_TYPE_NQ); \
5992 #define po_reg_or_goto(regtype, label) \
5995 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5996 & inst.operands[i].vectype); \
6000 inst.operands[i].reg = val; \
6001 inst.operands[i].isreg = 1; \
6002 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6003 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6004 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6005 || rtype == REG_TYPE_VFD \
6006 || rtype == REG_TYPE_NQ); \
6010 #define po_imm_or_fail(min, max, popt) \
6013 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6015 inst.operands[i].imm = val; \
6019 #define po_scalar_or_goto(elsz, label) \
6022 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6025 inst.operands[i].reg = val; \
6026 inst.operands[i].isscalar = 1; \
6030 #define po_misc_or_fail(expr) \
6038 #define po_misc_or_fail_no_backtrack(expr) \
6042 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6043 backtrack_pos = 0; \
6044 if (result != PARSE_OPERAND_SUCCESS) \
6049 #define po_barrier_or_imm(str) \
6052 val = parse_barrier (&str); \
6055 if (ISALPHA (*str)) \
6062 if ((inst.instruction & 0xf0) == 0x60 \
6065 /* ISB can only take SY as an option. */ \
6066 inst.error = _("invalid barrier type"); \
6073 skip_whitespace (str
);
6075 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6077 op_parse_code
= upat
[i
];
6078 if (op_parse_code
>= 1<<16)
6079 op_parse_code
= thumb
? (op_parse_code
>> 16)
6080 : (op_parse_code
& ((1<<16)-1));
6082 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6084 /* Remember where we are in case we need to backtrack. */
6085 gas_assert (!backtrack_pos
);
6086 backtrack_pos
= str
;
6087 backtrack_error
= inst
.error
;
6088 backtrack_index
= i
;
6091 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6092 po_char_or_fail (',');
6094 switch (op_parse_code
)
6102 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6103 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6104 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6105 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6106 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6107 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6109 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6111 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6113 /* Also accept generic coprocessor regs for unknown registers. */
6115 po_reg_or_fail (REG_TYPE_CN
);
6117 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6118 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6119 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6120 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6121 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6122 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6123 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6124 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6125 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6126 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6128 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6130 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6131 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6133 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6135 /* Neon scalar. Using an element size of 8 means that some invalid
6136 scalars are accepted here, so deal with those in later code. */
6137 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6141 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6144 po_imm_or_fail (0, 0, TRUE
);
6149 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6154 po_scalar_or_goto (8, try_rr
);
6157 po_reg_or_fail (REG_TYPE_RN
);
6163 po_scalar_or_goto (8, try_nsdq
);
6166 po_reg_or_fail (REG_TYPE_NSDQ
);
6172 po_scalar_or_goto (8, try_ndq
);
6175 po_reg_or_fail (REG_TYPE_NDQ
);
6181 po_scalar_or_goto (8, try_vfd
);
6184 po_reg_or_fail (REG_TYPE_VFD
);
6189 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6190 not careful then bad things might happen. */
6191 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6196 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6199 /* There's a possibility of getting a 64-bit immediate here, so
6200 we need special handling. */
6201 if (parse_big_immediate (&str
, i
) == FAIL
)
6203 inst
.error
= _("immediate value is out of range");
6211 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6214 po_imm_or_fail (0, 63, TRUE
);
6219 po_char_or_fail ('[');
6220 po_reg_or_fail (REG_TYPE_RN
);
6221 po_char_or_fail (']');
6227 po_reg_or_fail (REG_TYPE_RN
);
6228 if (skip_past_char (&str
, '!') == SUCCESS
)
6229 inst
.operands
[i
].writeback
= 1;
6233 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6234 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6235 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6236 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6237 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6238 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6239 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6240 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6241 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6242 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6243 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6244 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6246 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6248 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6249 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6251 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6252 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6253 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6255 /* Immediate variants */
6257 po_char_or_fail ('{');
6258 po_imm_or_fail (0, 255, TRUE
);
6259 po_char_or_fail ('}');
6263 /* The expression parser chokes on a trailing !, so we have
6264 to find it first and zap it. */
6267 while (*s
&& *s
!= ',')
6272 inst
.operands
[i
].writeback
= 1;
6274 po_imm_or_fail (0, 31, TRUE
);
6282 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6287 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6292 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6294 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6296 val
= parse_reloc (&str
);
6299 inst
.error
= _("unrecognized relocation suffix");
6302 else if (val
!= BFD_RELOC_UNUSED
)
6304 inst
.operands
[i
].imm
= val
;
6305 inst
.operands
[i
].hasreloc
= 1;
6310 /* Operand for MOVW or MOVT. */
6312 po_misc_or_fail (parse_half (&str
));
6315 /* Register or expression. */
6316 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6317 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6319 /* Register or immediate. */
6320 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6321 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6323 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6325 if (!is_immediate_prefix (*str
))
6328 val
= parse_fpa_immediate (&str
);
6331 /* FPA immediates are encoded as registers 8-15.
6332 parse_fpa_immediate has already applied the offset. */
6333 inst
.operands
[i
].reg
= val
;
6334 inst
.operands
[i
].isreg
= 1;
6337 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6338 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6340 /* Two kinds of register. */
6343 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6345 || (rege
->type
!= REG_TYPE_MMXWR
6346 && rege
->type
!= REG_TYPE_MMXWC
6347 && rege
->type
!= REG_TYPE_MMXWCG
))
6349 inst
.error
= _("iWMMXt data or control register expected");
6352 inst
.operands
[i
].reg
= rege
->number
;
6353 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6359 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6361 || (rege
->type
!= REG_TYPE_MMXWC
6362 && rege
->type
!= REG_TYPE_MMXWCG
))
6364 inst
.error
= _("iWMMXt control register expected");
6367 inst
.operands
[i
].reg
= rege
->number
;
6368 inst
.operands
[i
].isreg
= 1;
6373 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6374 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6375 case OP_oROR
: val
= parse_ror (&str
); break;
6376 case OP_PSR
: val
= parse_psr (&str
); break;
6377 case OP_COND
: val
= parse_cond (&str
); break;
6378 case OP_oBARRIER_I15
:
6379 po_barrier_or_imm (str
); break;
6381 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6386 po_reg_or_goto (REG_TYPE_VFC
, try_banked_reg
);
6387 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6390 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6391 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6393 inst
.error
= _("Banked registers are not available with this "
6399 val
= parse_psr (&str
);
6403 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6406 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6408 if (strncasecmp (str
, "APSR_", 5) == 0)
6415 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6416 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6417 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6418 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6419 default: found
= 16;
6423 inst
.operands
[i
].isvec
= 1;
6424 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6425 inst
.operands
[i
].reg
= REG_PC
;
6432 po_misc_or_fail (parse_tb (&str
));
6435 /* Register lists. */
6437 val
= parse_reg_list (&str
);
6440 inst
.operands
[1].writeback
= 1;
6446 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6450 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6454 /* Allow Q registers too. */
6455 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6460 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6462 inst
.operands
[i
].issingle
= 1;
6467 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6472 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6473 &inst
.operands
[i
].vectype
);
6476 /* Addressing modes */
6478 po_misc_or_fail (parse_address (&str
, i
));
6482 po_misc_or_fail_no_backtrack (
6483 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6487 po_misc_or_fail_no_backtrack (
6488 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6492 po_misc_or_fail_no_backtrack (
6493 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6497 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6501 po_misc_or_fail_no_backtrack (
6502 parse_shifter_operand_group_reloc (&str
, i
));
6506 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6510 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6514 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6518 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6521 /* Various value-based sanity checks and shared operations. We
6522 do not signal immediate failures for the register constraints;
6523 this allows a syntax error to take precedence. */
6524 switch (op_parse_code
)
6532 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6533 inst
.error
= BAD_PC
;
6538 if (inst
.operands
[i
].isreg
)
6540 if (inst
.operands
[i
].reg
== REG_PC
)
6541 inst
.error
= BAD_PC
;
6542 else if (inst
.operands
[i
].reg
== REG_SP
)
6543 inst
.error
= BAD_SP
;
6548 if (inst
.operands
[i
].isreg
6549 && inst
.operands
[i
].reg
== REG_PC
6550 && (inst
.operands
[i
].writeback
|| thumb
))
6551 inst
.error
= BAD_PC
;
6560 case OP_oBARRIER_I15
:
6569 inst
.operands
[i
].imm
= val
;
6576 /* If we get here, this operand was successfully parsed. */
6577 inst
.operands
[i
].present
= 1;
6581 inst
.error
= BAD_ARGS
;
6586 /* The parse routine should already have set inst.error, but set a
6587 default here just in case. */
6589 inst
.error
= _("syntax error");
6593 /* Do not backtrack over a trailing optional argument that
6594 absorbed some text. We will only fail again, with the
6595 'garbage following instruction' error message, which is
6596 probably less helpful than the current one. */
6597 if (backtrack_index
== i
&& backtrack_pos
!= str
6598 && upat
[i
+1] == OP_stop
)
6601 inst
.error
= _("syntax error");
6605 /* Try again, skipping the optional argument at backtrack_pos. */
6606 str
= backtrack_pos
;
6607 inst
.error
= backtrack_error
;
6608 inst
.operands
[backtrack_index
].present
= 0;
6609 i
= backtrack_index
;
6613 /* Check that we have parsed all the arguments. */
6614 if (*str
!= '\0' && !inst
.error
)
6615 inst
.error
= _("garbage following instruction");
6617 return inst
.error
? FAIL
: SUCCESS
;
6620 #undef po_char_or_fail
6621 #undef po_reg_or_fail
6622 #undef po_reg_or_goto
6623 #undef po_imm_or_fail
6624 #undef po_scalar_or_fail
6625 #undef po_barrier_or_imm
6627 /* Shorthand macro for instruction encoding functions issuing errors. */
6628 #define constraint(expr, err) \
6639 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6640 instructions are unpredictable if these registers are used. This
6641 is the BadReg predicate in ARM's Thumb-2 documentation. */
6642 #define reject_bad_reg(reg) \
6644 if (reg == REG_SP || reg == REG_PC) \
6646 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6651 /* If REG is R13 (the stack pointer), warn that its use is
6653 #define warn_deprecated_sp(reg) \
6655 if (warn_on_deprecated && reg == REG_SP) \
6656 as_warn (_("use of r13 is deprecated")); \
6659 /* Functions for operand encoding. ARM, then Thumb. */
6661 #define rotate_left(v, n) (v << n | v >> (32 - n))
6663 /* If VAL can be encoded in the immediate field of an ARM instruction,
6664 return the encoded form. Otherwise, return FAIL. */
6667 encode_arm_immediate (unsigned int val
)
6671 for (i
= 0; i
< 32; i
+= 2)
6672 if ((a
= rotate_left (val
, i
)) <= 0xff)
6673 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6678 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6679 return the encoded form. Otherwise, return FAIL. */
6681 encode_thumb32_immediate (unsigned int val
)
6688 for (i
= 1; i
<= 24; i
++)
6691 if ((val
& ~(0xff << i
)) == 0)
6692 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6696 if (val
== ((a
<< 16) | a
))
6698 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6702 if (val
== ((a
<< 16) | a
))
6703 return 0x200 | (a
>> 8);
6707 /* Encode a VFP SP or DP register number into inst.instruction. */
6710 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6712 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6715 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6718 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6721 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6726 first_error (_("D register out of range for selected VFP version"));
6734 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6738 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6742 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6746 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6750 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6754 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6762 /* Encode a <shift> in an ARM-format instruction. The immediate,
6763 if any, is handled by md_apply_fix. */
6765 encode_arm_shift (int i
)
6767 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6768 inst
.instruction
|= SHIFT_ROR
<< 5;
6771 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6772 if (inst
.operands
[i
].immisreg
)
6774 inst
.instruction
|= SHIFT_BY_REG
;
6775 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6778 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6783 encode_arm_shifter_operand (int i
)
6785 if (inst
.operands
[i
].isreg
)
6787 inst
.instruction
|= inst
.operands
[i
].reg
;
6788 encode_arm_shift (i
);
6791 inst
.instruction
|= INST_IMMEDIATE
;
6794 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6796 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6798 gas_assert (inst
.operands
[i
].isreg
);
6799 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6801 if (inst
.operands
[i
].preind
)
6805 inst
.error
= _("instruction does not accept preindexed addressing");
6808 inst
.instruction
|= PRE_INDEX
;
6809 if (inst
.operands
[i
].writeback
)
6810 inst
.instruction
|= WRITE_BACK
;
6813 else if (inst
.operands
[i
].postind
)
6815 gas_assert (inst
.operands
[i
].writeback
);
6817 inst
.instruction
|= WRITE_BACK
;
6819 else /* unindexed - only for coprocessor */
6821 inst
.error
= _("instruction does not accept unindexed addressing");
6825 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6826 && (((inst
.instruction
& 0x000f0000) >> 16)
6827 == ((inst
.instruction
& 0x0000f000) >> 12)))
6828 as_warn ((inst
.instruction
& LOAD_BIT
)
6829 ? _("destination register same as write-back base")
6830 : _("source register same as write-back base"));
6833 /* inst.operands[i] was set up by parse_address. Encode it into an
6834 ARM-format mode 2 load or store instruction. If is_t is true,
6835 reject forms that cannot be used with a T instruction (i.e. not
6838 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6840 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6842 encode_arm_addr_mode_common (i
, is_t
);
6844 if (inst
.operands
[i
].immisreg
)
6846 constraint ((inst
.operands
[i
].imm
== REG_PC
6847 || (is_pc
&& inst
.operands
[i
].writeback
)),
6849 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6850 inst
.instruction
|= inst
.operands
[i
].imm
;
6851 if (!inst
.operands
[i
].negative
)
6852 inst
.instruction
|= INDEX_UP
;
6853 if (inst
.operands
[i
].shifted
)
6855 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6856 inst
.instruction
|= SHIFT_ROR
<< 5;
6859 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6860 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6864 else /* immediate offset in inst.reloc */
6866 if (is_pc
&& !inst
.reloc
.pc_rel
)
6868 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6870 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6871 cannot use PC in addressing.
6872 PC cannot be used in writeback addressing, either. */
6873 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6876 /* Use of PC in str is deprecated for ARMv7. */
6877 if (warn_on_deprecated
6879 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6880 as_warn (_("use of PC in this instruction is deprecated"));
6883 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6884 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6888 /* inst.operands[i] was set up by parse_address. Encode it into an
6889 ARM-format mode 3 load or store instruction. Reject forms that
6890 cannot be used with such instructions. If is_t is true, reject
6891 forms that cannot be used with a T instruction (i.e. not
6894 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6896 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6898 inst
.error
= _("instruction does not accept scaled register index");
6902 encode_arm_addr_mode_common (i
, is_t
);
6904 if (inst
.operands
[i
].immisreg
)
6906 constraint ((inst
.operands
[i
].imm
== REG_PC
6907 || inst
.operands
[i
].reg
== REG_PC
),
6909 inst
.instruction
|= inst
.operands
[i
].imm
;
6910 if (!inst
.operands
[i
].negative
)
6911 inst
.instruction
|= INDEX_UP
;
6913 else /* immediate offset in inst.reloc */
6915 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6916 && inst
.operands
[i
].writeback
),
6918 inst
.instruction
|= HWOFFSET_IMM
;
6919 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6920 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6924 /* inst.operands[i] was set up by parse_address. Encode it into an
6925 ARM-format instruction. Reject all forms which cannot be encoded
6926 into a coprocessor load/store instruction. If wb_ok is false,
6927 reject use of writeback; if unind_ok is false, reject use of
6928 unindexed addressing. If reloc_override is not 0, use it instead
6929 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6930 (in which case it is preserved). */
6933 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6935 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6937 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6939 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6941 gas_assert (!inst
.operands
[i
].writeback
);
6944 inst
.error
= _("instruction does not support unindexed addressing");
6947 inst
.instruction
|= inst
.operands
[i
].imm
;
6948 inst
.instruction
|= INDEX_UP
;
6952 if (inst
.operands
[i
].preind
)
6953 inst
.instruction
|= PRE_INDEX
;
6955 if (inst
.operands
[i
].writeback
)
6957 if (inst
.operands
[i
].reg
== REG_PC
)
6959 inst
.error
= _("pc may not be used with write-back");
6964 inst
.error
= _("instruction does not support writeback");
6967 inst
.instruction
|= WRITE_BACK
;
6971 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6972 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6973 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6974 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6977 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6979 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6985 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6986 Determine whether it can be performed with a move instruction; if
6987 it can, convert inst.instruction to that move instruction and
6988 return TRUE; if it can't, convert inst.instruction to a literal-pool
6989 load and return FALSE. If this is not a valid thing to do in the
6990 current context, set inst.error and return TRUE.
6992 inst.operands[i] describes the destination register. */
6995 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7000 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7004 if ((inst
.instruction
& tbit
) == 0)
7006 inst
.error
= _("invalid pseudo operation");
7009 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7011 inst
.error
= _("constant expression expected");
7014 if (inst
.reloc
.exp
.X_op
== O_constant
)
7018 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7020 /* This can be done with a mov(1) instruction. */
7021 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7022 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7028 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7031 /* This can be done with a mov instruction. */
7032 inst
.instruction
&= LITERAL_MASK
;
7033 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7034 inst
.instruction
|= value
& 0xfff;
7038 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7041 /* This can be done with a mvn instruction. */
7042 inst
.instruction
&= LITERAL_MASK
;
7043 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7044 inst
.instruction
|= value
& 0xfff;
7050 if (add_to_lit_pool () == FAIL
)
7052 inst
.error
= _("literal pool insertion failed");
7055 inst
.operands
[1].reg
= REG_PC
;
7056 inst
.operands
[1].isreg
= 1;
7057 inst
.operands
[1].preind
= 1;
7058 inst
.reloc
.pc_rel
= 1;
7059 inst
.reloc
.type
= (thumb_p
7060 ? BFD_RELOC_ARM_THUMB_OFFSET
7062 ? BFD_RELOC_ARM_HWLITERAL
7063 : BFD_RELOC_ARM_LITERAL
));
7067 /* Functions for instruction encoding, sorted by sub-architecture.
7068 First some generics; their names are taken from the conventional
7069 bit positions for register arguments in ARM format instructions. */
7079 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7085 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7086 inst
.instruction
|= inst
.operands
[1].reg
;
7092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7093 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7099 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7100 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7106 unsigned Rn
= inst
.operands
[2].reg
;
7107 /* Enforce restrictions on SWP instruction. */
7108 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7110 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7111 _("Rn must not overlap other operands"));
7113 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7114 if (warn_on_deprecated
7115 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7116 as_warn (_("swp{b} use is deprecated for this architecture"));
7119 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7120 inst
.instruction
|= inst
.operands
[1].reg
;
7121 inst
.instruction
|= Rn
<< 16;
7127 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7128 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7129 inst
.instruction
|= inst
.operands
[2].reg
;
7135 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7136 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7137 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7138 || inst
.reloc
.exp
.X_add_number
!= 0),
7140 inst
.instruction
|= inst
.operands
[0].reg
;
7141 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7142 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7148 inst
.instruction
|= inst
.operands
[0].imm
;
7154 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7155 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7158 /* ARM instructions, in alphabetical order by function name (except
7159 that wrapper functions appear immediately after the function they
7162 /* This is a pseudo-op of the form "adr rd, label" to be converted
7163 into a relative address of the form "add rd, pc, #label-.-8". */
7168 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7170 /* Frag hacking will turn this into a sub instruction if the offset turns
7171 out to be negative. */
7172 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7173 inst
.reloc
.pc_rel
= 1;
7174 inst
.reloc
.exp
.X_add_number
-= 8;
7177 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7178 into a relative address of the form:
7179 add rd, pc, #low(label-.-8)"
7180 add rd, rd, #high(label-.-8)" */
7185 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7187 /* Frag hacking will turn this into a sub instruction if the offset turns
7188 out to be negative. */
7189 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7190 inst
.reloc
.pc_rel
= 1;
7191 inst
.size
= INSN_SIZE
* 2;
7192 inst
.reloc
.exp
.X_add_number
-= 8;
7198 if (!inst
.operands
[1].present
)
7199 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7200 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7201 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7202 encode_arm_shifter_operand (2);
7208 if (inst
.operands
[0].present
)
7210 constraint ((inst
.instruction
& 0xf0) != 0x40
7211 && inst
.operands
[0].imm
> 0xf
7212 && inst
.operands
[0].imm
< 0x0,
7213 _("bad barrier type"));
7214 inst
.instruction
|= inst
.operands
[0].imm
;
7217 inst
.instruction
|= 0xf;
7223 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7224 constraint (msb
> 32, _("bit-field extends past end of register"));
7225 /* The instruction encoding stores the LSB and MSB,
7226 not the LSB and width. */
7227 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7228 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7229 inst
.instruction
|= (msb
- 1) << 16;
7237 /* #0 in second position is alternative syntax for bfc, which is
7238 the same instruction but with REG_PC in the Rm field. */
7239 if (!inst
.operands
[1].isreg
)
7240 inst
.operands
[1].reg
= REG_PC
;
7242 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7243 constraint (msb
> 32, _("bit-field extends past end of register"));
7244 /* The instruction encoding stores the LSB and MSB,
7245 not the LSB and width. */
7246 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7247 inst
.instruction
|= inst
.operands
[1].reg
;
7248 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7249 inst
.instruction
|= (msb
- 1) << 16;
7255 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7256 _("bit-field extends past end of register"));
7257 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7258 inst
.instruction
|= inst
.operands
[1].reg
;
7259 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7260 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7263 /* ARM V5 breakpoint instruction (argument parse)
7264 BKPT <16 bit unsigned immediate>
7265 Instruction is not conditional.
7266 The bit pattern given in insns[] has the COND_ALWAYS condition,
7267 and it is an error if the caller tried to override that. */
7272 /* Top 12 of 16 bits to bits 19:8. */
7273 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7275 /* Bottom 4 of 16 bits to bits 3:0. */
7276 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7280 encode_branch (int default_reloc
)
7282 if (inst
.operands
[0].hasreloc
)
7284 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7285 _("the only suffix valid here is '(plt)'"));
7286 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7289 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7290 inst
.reloc
.pc_rel
= 1;
7297 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7298 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7301 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7308 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7310 if (inst
.cond
== COND_ALWAYS
)
7311 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7313 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7317 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7320 /* ARM V5 branch-link-exchange instruction (argument parse)
7321 BLX <target_addr> ie BLX(1)
7322 BLX{<condition>} <Rm> ie BLX(2)
7323 Unfortunately, there are two different opcodes for this mnemonic.
7324 So, the insns[].value is not used, and the code here zaps values
7325 into inst.instruction.
7326 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7331 if (inst
.operands
[0].isreg
)
7333 /* Arg is a register; the opcode provided by insns[] is correct.
7334 It is not illegal to do "blx pc", just useless. */
7335 if (inst
.operands
[0].reg
== REG_PC
)
7336 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7338 inst
.instruction
|= inst
.operands
[0].reg
;
7342 /* Arg is an address; this instruction cannot be executed
7343 conditionally, and the opcode must be adjusted.
7344 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7345 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7346 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7347 inst
.instruction
= 0xfa000000;
7348 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7355 bfd_boolean want_reloc
;
7357 if (inst
.operands
[0].reg
== REG_PC
)
7358 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7360 inst
.instruction
|= inst
.operands
[0].reg
;
7361 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7362 it is for ARMv4t or earlier. */
7363 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7364 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7368 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7373 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7377 /* ARM v5TEJ. Jump to Jazelle code. */
7382 if (inst
.operands
[0].reg
== REG_PC
)
7383 as_tsktsk (_("use of r15 in bxj is not really useful"));
7385 inst
.instruction
|= inst
.operands
[0].reg
;
7388 /* Co-processor data operation:
7389 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7390 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7394 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7395 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7396 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7397 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7398 inst
.instruction
|= inst
.operands
[4].reg
;
7399 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7405 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7406 encode_arm_shifter_operand (1);
7409 /* Transfer between coprocessor and ARM registers.
7410 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7415 No special properties. */
7422 Rd
= inst
.operands
[2].reg
;
7425 if (inst
.instruction
== 0xee000010
7426 || inst
.instruction
== 0xfe000010)
7428 reject_bad_reg (Rd
);
7431 constraint (Rd
== REG_SP
, BAD_SP
);
7436 if (inst
.instruction
== 0xe000010)
7437 constraint (Rd
== REG_PC
, BAD_PC
);
7441 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7442 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7443 inst
.instruction
|= Rd
<< 12;
7444 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7445 inst
.instruction
|= inst
.operands
[4].reg
;
7446 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7449 /* Transfer between coprocessor register and pair of ARM registers.
7450 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7455 Two XScale instructions are special cases of these:
7457 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7458 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7460 Result unpredictable if Rd or Rn is R15. */
7467 Rd
= inst
.operands
[2].reg
;
7468 Rn
= inst
.operands
[3].reg
;
7472 reject_bad_reg (Rd
);
7473 reject_bad_reg (Rn
);
7477 constraint (Rd
== REG_PC
, BAD_PC
);
7478 constraint (Rn
== REG_PC
, BAD_PC
);
7481 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7482 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7483 inst
.instruction
|= Rd
<< 12;
7484 inst
.instruction
|= Rn
<< 16;
7485 inst
.instruction
|= inst
.operands
[4].reg
;
7491 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7492 if (inst
.operands
[1].present
)
7494 inst
.instruction
|= CPSI_MMOD
;
7495 inst
.instruction
|= inst
.operands
[1].imm
;
7502 inst
.instruction
|= inst
.operands
[0].imm
;
7508 unsigned Rd
, Rn
, Rm
;
7510 Rd
= inst
.operands
[0].reg
;
7511 Rn
= (inst
.operands
[1].present
7512 ? inst
.operands
[1].reg
: Rd
);
7513 Rm
= inst
.operands
[2].reg
;
7515 constraint ((Rd
== REG_PC
), BAD_PC
);
7516 constraint ((Rn
== REG_PC
), BAD_PC
);
7517 constraint ((Rm
== REG_PC
), BAD_PC
);
7519 inst
.instruction
|= Rd
<< 16;
7520 inst
.instruction
|= Rn
<< 0;
7521 inst
.instruction
|= Rm
<< 8;
7527 /* There is no IT instruction in ARM mode. We
7528 process it to do the validation as if in
7529 thumb mode, just in case the code gets
7530 assembled for thumb using the unified syntax. */
7535 set_it_insn_type (IT_INSN
);
7536 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7537 now_it
.cc
= inst
.operands
[0].imm
;
7544 int base_reg
= inst
.operands
[0].reg
;
7545 int range
= inst
.operands
[1].imm
;
7547 inst
.instruction
|= base_reg
<< 16;
7548 inst
.instruction
|= range
;
7550 if (inst
.operands
[1].writeback
)
7551 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7553 if (inst
.operands
[0].writeback
)
7555 inst
.instruction
|= WRITE_BACK
;
7556 /* Check for unpredictable uses of writeback. */
7557 if (inst
.instruction
& LOAD_BIT
)
7559 /* Not allowed in LDM type 2. */
7560 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7561 && ((range
& (1 << REG_PC
)) == 0))
7562 as_warn (_("writeback of base register is UNPREDICTABLE"));
7563 /* Only allowed if base reg not in list for other types. */
7564 else if (range
& (1 << base_reg
))
7565 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7569 /* Not allowed for type 2. */
7570 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7571 as_warn (_("writeback of base register is UNPREDICTABLE"));
7572 /* Only allowed if base reg not in list, or first in list. */
7573 else if ((range
& (1 << base_reg
))
7574 && (range
& ((1 << base_reg
) - 1)))
7575 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7580 /* ARMv5TE load-consecutive (argument parse)
7589 constraint (inst
.operands
[0].reg
% 2 != 0,
7590 _("first destination register must be even"));
7591 constraint (inst
.operands
[1].present
7592 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7593 _("can only load two consecutive registers"));
7594 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7595 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7597 if (!inst
.operands
[1].present
)
7598 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7600 if (inst
.instruction
& LOAD_BIT
)
7602 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7603 register and the first register written; we have to diagnose
7604 overlap between the base and the second register written here. */
7606 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7607 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7608 as_warn (_("base register written back, and overlaps "
7609 "second destination register"));
7611 /* For an index-register load, the index register must not overlap the
7612 destination (even if not write-back). */
7613 else if (inst
.operands
[2].immisreg
7614 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7615 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7616 as_warn (_("index register overlaps destination register"));
7619 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7620 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7626 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7627 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7628 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7629 || inst
.operands
[1].negative
7630 /* This can arise if the programmer has written
7632 or if they have mistakenly used a register name as the last
7635 It is very difficult to distinguish between these two cases
7636 because "rX" might actually be a label. ie the register
7637 name has been occluded by a symbol of the same name. So we
7638 just generate a general 'bad addressing mode' type error
7639 message and leave it up to the programmer to discover the
7640 true cause and fix their mistake. */
7641 || (inst
.operands
[1].reg
== REG_PC
),
7644 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7645 || inst
.reloc
.exp
.X_add_number
!= 0,
7646 _("offset must be zero in ARM encoding"));
7648 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7650 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7651 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7652 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7658 constraint (inst
.operands
[0].reg
% 2 != 0,
7659 _("even register required"));
7660 constraint (inst
.operands
[1].present
7661 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7662 _("can only load two consecutive registers"));
7663 /* If op 1 were present and equal to PC, this function wouldn't
7664 have been called in the first place. */
7665 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7667 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7668 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7674 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7675 if (!inst
.operands
[1].isreg
)
7676 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7678 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7684 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7686 if (inst
.operands
[1].preind
)
7688 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7689 || inst
.reloc
.exp
.X_add_number
!= 0,
7690 _("this instruction requires a post-indexed address"));
7692 inst
.operands
[1].preind
= 0;
7693 inst
.operands
[1].postind
= 1;
7694 inst
.operands
[1].writeback
= 1;
7696 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7697 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7700 /* Halfword and signed-byte load/store operations. */
7705 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7706 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7707 if (!inst
.operands
[1].isreg
)
7708 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7710 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7716 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7718 if (inst
.operands
[1].preind
)
7720 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7721 || inst
.reloc
.exp
.X_add_number
!= 0,
7722 _("this instruction requires a post-indexed address"));
7724 inst
.operands
[1].preind
= 0;
7725 inst
.operands
[1].postind
= 1;
7726 inst
.operands
[1].writeback
= 1;
7728 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7729 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7732 /* Co-processor register load/store.
7733 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7737 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7738 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7739 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7745 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7746 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7747 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7748 && !(inst
.instruction
& 0x00400000))
7749 as_tsktsk (_("Rd and Rm should be different in mla"));
7751 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7752 inst
.instruction
|= inst
.operands
[1].reg
;
7753 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7754 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7760 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7761 encode_arm_shifter_operand (1);
7764 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7771 top
= (inst
.instruction
& 0x00400000) != 0;
7772 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7773 _(":lower16: not allowed this instruction"));
7774 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7775 _(":upper16: not allowed instruction"));
7776 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7777 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7779 imm
= inst
.reloc
.exp
.X_add_number
;
7780 /* The value is in two pieces: 0:11, 16:19. */
7781 inst
.instruction
|= (imm
& 0x00000fff);
7782 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7786 static void do_vfp_nsyn_opcode (const char *);
7789 do_vfp_nsyn_mrs (void)
7791 if (inst
.operands
[0].isvec
)
7793 if (inst
.operands
[1].reg
!= 1)
7794 first_error (_("operand 1 must be FPSCR"));
7795 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7796 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7797 do_vfp_nsyn_opcode ("fmstat");
7799 else if (inst
.operands
[1].isvec
)
7800 do_vfp_nsyn_opcode ("fmrx");
7808 do_vfp_nsyn_msr (void)
7810 if (inst
.operands
[0].isvec
)
7811 do_vfp_nsyn_opcode ("fmxr");
7821 unsigned Rt
= inst
.operands
[0].reg
;
7823 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7825 inst
.error
= BAD_SP
;
7829 /* APSR_ sets isvec. All other refs to PC are illegal. */
7830 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7832 inst
.error
= BAD_PC
;
7836 if (inst
.operands
[1].reg
!= 1)
7837 first_error (_("operand 1 must be FPSCR"));
7839 inst
.instruction
|= (Rt
<< 12);
7845 unsigned Rt
= inst
.operands
[1].reg
;
7848 reject_bad_reg (Rt
);
7849 else if (Rt
== REG_PC
)
7851 inst
.error
= BAD_PC
;
7855 if (inst
.operands
[0].reg
!= 1)
7856 first_error (_("operand 0 must be FPSCR"));
7858 inst
.instruction
|= (Rt
<< 12);
7866 if (do_vfp_nsyn_mrs () == SUCCESS
)
7869 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7870 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7872 if (inst
.operands
[1].isreg
)
7874 br
= inst
.operands
[1].reg
;
7875 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
7876 as_bad (_("bad register for mrs"));
7880 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7881 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7883 _("'CPSR' or 'SPSR' expected"));
7884 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
7887 inst
.instruction
|= br
;
7890 /* Two possible forms:
7891 "{C|S}PSR_<field>, Rm",
7892 "{C|S}PSR_f, #expression". */
7897 if (do_vfp_nsyn_msr () == SUCCESS
)
7900 inst
.instruction
|= inst
.operands
[0].imm
;
7901 if (inst
.operands
[1].isreg
)
7902 inst
.instruction
|= inst
.operands
[1].reg
;
7905 inst
.instruction
|= INST_IMMEDIATE
;
7906 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7907 inst
.reloc
.pc_rel
= 0;
7914 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7916 if (!inst
.operands
[2].present
)
7917 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7918 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7919 inst
.instruction
|= inst
.operands
[1].reg
;
7920 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7922 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7923 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7924 as_tsktsk (_("Rd and Rm should be different in mul"));
7927 /* Long Multiply Parser
7928 UMULL RdLo, RdHi, Rm, Rs
7929 SMULL RdLo, RdHi, Rm, Rs
7930 UMLAL RdLo, RdHi, Rm, Rs
7931 SMLAL RdLo, RdHi, Rm, Rs. */
7936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7937 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7938 inst
.instruction
|= inst
.operands
[2].reg
;
7939 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7941 /* rdhi and rdlo must be different. */
7942 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7943 as_tsktsk (_("rdhi and rdlo must be different"));
7945 /* rdhi, rdlo and rm must all be different before armv6. */
7946 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7947 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7948 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7949 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7955 if (inst
.operands
[0].present
7956 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7958 /* Architectural NOP hints are CPSR sets with no bits selected. */
7959 inst
.instruction
&= 0xf0000000;
7960 inst
.instruction
|= 0x0320f000;
7961 if (inst
.operands
[0].present
)
7962 inst
.instruction
|= inst
.operands
[0].imm
;
7966 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7967 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7968 Condition defaults to COND_ALWAYS.
7969 Error if Rd, Rn or Rm are R15. */
7974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7975 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7976 inst
.instruction
|= inst
.operands
[2].reg
;
7977 if (inst
.operands
[3].present
)
7978 encode_arm_shift (3);
7981 /* ARM V6 PKHTB (Argument Parse). */
7986 if (!inst
.operands
[3].present
)
7988 /* If the shift specifier is omitted, turn the instruction
7989 into pkhbt rd, rm, rn. */
7990 inst
.instruction
&= 0xfff00010;
7991 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7992 inst
.instruction
|= inst
.operands
[1].reg
;
7993 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7998 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7999 inst
.instruction
|= inst
.operands
[2].reg
;
8000 encode_arm_shift (3);
8004 /* ARMv5TE: Preload-Cache
8005 MP Extensions: Preload for write
8009 Syntactically, like LDR with B=1, W=0, L=1. */
8014 constraint (!inst
.operands
[0].isreg
,
8015 _("'[' expected after PLD mnemonic"));
8016 constraint (inst
.operands
[0].postind
,
8017 _("post-indexed expression used in preload instruction"));
8018 constraint (inst
.operands
[0].writeback
,
8019 _("writeback used in preload instruction"));
8020 constraint (!inst
.operands
[0].preind
,
8021 _("unindexed addressing used in preload instruction"));
8022 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8025 /* ARMv7: PLI <addr_mode> */
8029 constraint (!inst
.operands
[0].isreg
,
8030 _("'[' expected after PLI mnemonic"));
8031 constraint (inst
.operands
[0].postind
,
8032 _("post-indexed expression used in preload instruction"));
8033 constraint (inst
.operands
[0].writeback
,
8034 _("writeback used in preload instruction"));
8035 constraint (!inst
.operands
[0].preind
,
8036 _("unindexed addressing used in preload instruction"));
8037 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8038 inst
.instruction
&= ~PRE_INDEX
;
8044 inst
.operands
[1] = inst
.operands
[0];
8045 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8046 inst
.operands
[0].isreg
= 1;
8047 inst
.operands
[0].writeback
= 1;
8048 inst
.operands
[0].reg
= REG_SP
;
8052 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8053 word at the specified address and the following word
8055 Unconditionally executed.
8056 Error if Rn is R15. */
8061 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8062 if (inst
.operands
[0].writeback
)
8063 inst
.instruction
|= WRITE_BACK
;
8066 /* ARM V6 ssat (argument parse). */
8071 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8072 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8073 inst
.instruction
|= inst
.operands
[2].reg
;
8075 if (inst
.operands
[3].present
)
8076 encode_arm_shift (3);
8079 /* ARM V6 usat (argument parse). */
8084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8085 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8086 inst
.instruction
|= inst
.operands
[2].reg
;
8088 if (inst
.operands
[3].present
)
8089 encode_arm_shift (3);
8092 /* ARM V6 ssat16 (argument parse). */
8097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8098 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8099 inst
.instruction
|= inst
.operands
[2].reg
;
8105 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8106 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8107 inst
.instruction
|= inst
.operands
[2].reg
;
8110 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8111 preserving the other bits.
8113 setend <endian_specifier>, where <endian_specifier> is either
8119 if (inst
.operands
[0].imm
)
8120 inst
.instruction
|= 0x200;
8126 unsigned int Rm
= (inst
.operands
[1].present
8127 ? inst
.operands
[1].reg
8128 : inst
.operands
[0].reg
);
8130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8131 inst
.instruction
|= Rm
;
8132 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8134 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8135 inst
.instruction
|= SHIFT_BY_REG
;
8138 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8144 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8145 inst
.reloc
.pc_rel
= 0;
8151 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8152 inst
.reloc
.pc_rel
= 0;
8158 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8159 inst
.reloc
.pc_rel
= 0;
8162 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8163 SMLAxy{cond} Rd,Rm,Rs,Rn
8164 SMLAWy{cond} Rd,Rm,Rs,Rn
8165 Error if any register is R15. */
8170 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8171 inst
.instruction
|= inst
.operands
[1].reg
;
8172 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8173 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8176 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8177 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8178 Error if any register is R15.
8179 Warning if Rdlo == Rdhi. */
8184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8185 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8186 inst
.instruction
|= inst
.operands
[2].reg
;
8187 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8189 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8190 as_tsktsk (_("rdhi and rdlo must be different"));
8193 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8194 SMULxy{cond} Rd,Rm,Rs
8195 Error if any register is R15. */
8200 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8201 inst
.instruction
|= inst
.operands
[1].reg
;
8202 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8205 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8206 the same for both ARM and Thumb-2. */
8213 if (inst
.operands
[0].present
)
8215 reg
= inst
.operands
[0].reg
;
8216 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8221 inst
.instruction
|= reg
<< 16;
8222 inst
.instruction
|= inst
.operands
[1].imm
;
8223 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8224 inst
.instruction
|= WRITE_BACK
;
8227 /* ARM V6 strex (argument parse). */
8232 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8233 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8234 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8235 || inst
.operands
[2].negative
8236 /* See comment in do_ldrex(). */
8237 || (inst
.operands
[2].reg
== REG_PC
),
8240 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8241 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8243 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8244 || inst
.reloc
.exp
.X_add_number
!= 0,
8245 _("offset must be zero in ARM encoding"));
8247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8248 inst
.instruction
|= inst
.operands
[1].reg
;
8249 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8250 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8256 constraint (inst
.operands
[1].reg
% 2 != 0,
8257 _("even register required"));
8258 constraint (inst
.operands
[2].present
8259 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8260 _("can only store two consecutive registers"));
8261 /* If op 2 were present and equal to PC, this function wouldn't
8262 have been called in the first place. */
8263 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8265 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8266 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8267 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8270 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8271 inst
.instruction
|= inst
.operands
[1].reg
;
8272 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8275 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8276 extends it to 32-bits, and adds the result to a value in another
8277 register. You can specify a rotation by 0, 8, 16, or 24 bits
8278 before extracting the 16-bit value.
8279 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8280 Condition defaults to COND_ALWAYS.
8281 Error if any register uses R15. */
8286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8287 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8288 inst
.instruction
|= inst
.operands
[2].reg
;
8289 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8294 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8295 Condition defaults to COND_ALWAYS.
8296 Error if any register uses R15. */
8301 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8302 inst
.instruction
|= inst
.operands
[1].reg
;
8303 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8306 /* VFP instructions. In a logical order: SP variant first, monad
8307 before dyad, arithmetic then move then load/store. */
8310 do_vfp_sp_monadic (void)
8312 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8313 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8317 do_vfp_sp_dyadic (void)
8319 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8320 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8321 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8325 do_vfp_sp_compare_z (void)
8327 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8331 do_vfp_dp_sp_cvt (void)
8333 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8334 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8338 do_vfp_sp_dp_cvt (void)
8340 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8341 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8345 do_vfp_reg_from_sp (void)
8347 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8348 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8352 do_vfp_reg2_from_sp2 (void)
8354 constraint (inst
.operands
[2].imm
!= 2,
8355 _("only two consecutive VFP SP registers allowed here"));
8356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8357 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8358 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8362 do_vfp_sp_from_reg (void)
8364 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8365 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8369 do_vfp_sp2_from_reg2 (void)
8371 constraint (inst
.operands
[0].imm
!= 2,
8372 _("only two consecutive VFP SP registers allowed here"));
8373 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8374 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8375 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8379 do_vfp_sp_ldst (void)
8381 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8382 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8386 do_vfp_dp_ldst (void)
8388 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8389 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8394 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8396 if (inst
.operands
[0].writeback
)
8397 inst
.instruction
|= WRITE_BACK
;
8399 constraint (ldstm_type
!= VFP_LDSTMIA
,
8400 _("this addressing mode requires base-register writeback"));
8401 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8402 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8403 inst
.instruction
|= inst
.operands
[1].imm
;
8407 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8411 if (inst
.operands
[0].writeback
)
8412 inst
.instruction
|= WRITE_BACK
;
8414 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8415 _("this addressing mode requires base-register writeback"));
8417 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8418 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8420 count
= inst
.operands
[1].imm
<< 1;
8421 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8424 inst
.instruction
|= count
;
8428 do_vfp_sp_ldstmia (void)
8430 vfp_sp_ldstm (VFP_LDSTMIA
);
8434 do_vfp_sp_ldstmdb (void)
8436 vfp_sp_ldstm (VFP_LDSTMDB
);
8440 do_vfp_dp_ldstmia (void)
8442 vfp_dp_ldstm (VFP_LDSTMIA
);
8446 do_vfp_dp_ldstmdb (void)
8448 vfp_dp_ldstm (VFP_LDSTMDB
);
8452 do_vfp_xp_ldstmia (void)
8454 vfp_dp_ldstm (VFP_LDSTMIAX
);
8458 do_vfp_xp_ldstmdb (void)
8460 vfp_dp_ldstm (VFP_LDSTMDBX
);
8464 do_vfp_dp_rd_rm (void)
8466 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8467 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8471 do_vfp_dp_rn_rd (void)
8473 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8474 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8478 do_vfp_dp_rd_rn (void)
8480 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8481 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8485 do_vfp_dp_rd_rn_rm (void)
8487 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8488 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8489 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8495 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8499 do_vfp_dp_rm_rd_rn (void)
8501 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8502 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8503 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8506 /* VFPv3 instructions. */
8508 do_vfp_sp_const (void)
8510 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8511 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8512 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8516 do_vfp_dp_const (void)
8518 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8519 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8520 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8524 vfp_conv (int srcsize
)
8526 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8527 inst
.instruction
|= (immbits
& 1) << 5;
8528 inst
.instruction
|= (immbits
>> 1);
8532 do_vfp_sp_conv_16 (void)
8534 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8539 do_vfp_dp_conv_16 (void)
8541 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8546 do_vfp_sp_conv_32 (void)
8548 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8553 do_vfp_dp_conv_32 (void)
8555 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8559 /* FPA instructions. Also in a logical order. */
8564 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8565 inst
.instruction
|= inst
.operands
[1].reg
;
8569 do_fpa_ldmstm (void)
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8572 switch (inst
.operands
[1].imm
)
8574 case 1: inst
.instruction
|= CP_T_X
; break;
8575 case 2: inst
.instruction
|= CP_T_Y
; break;
8576 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8581 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8583 /* The instruction specified "ea" or "fd", so we can only accept
8584 [Rn]{!}. The instruction does not really support stacking or
8585 unstacking, so we have to emulate these by setting appropriate
8586 bits and offsets. */
8587 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8588 || inst
.reloc
.exp
.X_add_number
!= 0,
8589 _("this instruction does not support indexing"));
8591 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8592 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8594 if (!(inst
.instruction
& INDEX_UP
))
8595 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8597 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8599 inst
.operands
[2].preind
= 0;
8600 inst
.operands
[2].postind
= 1;
8604 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8607 /* iWMMXt instructions: strictly in alphabetical order. */
8610 do_iwmmxt_tandorc (void)
8612 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8616 do_iwmmxt_textrc (void)
8618 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8619 inst
.instruction
|= inst
.operands
[1].imm
;
8623 do_iwmmxt_textrm (void)
8625 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8626 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8627 inst
.instruction
|= inst
.operands
[2].imm
;
8631 do_iwmmxt_tinsr (void)
8633 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8634 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8635 inst
.instruction
|= inst
.operands
[2].imm
;
8639 do_iwmmxt_tmia (void)
8641 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8642 inst
.instruction
|= inst
.operands
[1].reg
;
8643 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8647 do_iwmmxt_waligni (void)
8649 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8650 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8651 inst
.instruction
|= inst
.operands
[2].reg
;
8652 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8656 do_iwmmxt_wmerge (void)
8658 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8659 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8660 inst
.instruction
|= inst
.operands
[2].reg
;
8661 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8665 do_iwmmxt_wmov (void)
8667 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8668 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8669 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8670 inst
.instruction
|= inst
.operands
[1].reg
;
8674 do_iwmmxt_wldstbh (void)
8677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8679 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8681 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8682 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8686 do_iwmmxt_wldstw (void)
8688 /* RIWR_RIWC clears .isreg for a control register. */
8689 if (!inst
.operands
[0].isreg
)
8691 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8692 inst
.instruction
|= 0xf0000000;
8695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8696 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8700 do_iwmmxt_wldstd (void)
8702 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8704 && inst
.operands
[1].immisreg
)
8706 inst
.instruction
&= ~0x1a000ff;
8707 inst
.instruction
|= (0xf << 28);
8708 if (inst
.operands
[1].preind
)
8709 inst
.instruction
|= PRE_INDEX
;
8710 if (!inst
.operands
[1].negative
)
8711 inst
.instruction
|= INDEX_UP
;
8712 if (inst
.operands
[1].writeback
)
8713 inst
.instruction
|= WRITE_BACK
;
8714 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8715 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8716 inst
.instruction
|= inst
.operands
[1].imm
;
8719 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8723 do_iwmmxt_wshufh (void)
8725 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8726 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8727 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8728 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8732 do_iwmmxt_wzero (void)
8734 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8735 inst
.instruction
|= inst
.operands
[0].reg
;
8736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8737 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8741 do_iwmmxt_wrwrwr_or_imm5 (void)
8743 if (inst
.operands
[2].isreg
)
8746 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8747 _("immediate operand requires iWMMXt2"));
8749 if (inst
.operands
[2].imm
== 0)
8751 switch ((inst
.instruction
>> 20) & 0xf)
8757 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8758 inst
.operands
[2].imm
= 16;
8759 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8765 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8766 inst
.operands
[2].imm
= 32;
8767 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8774 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8776 wrn
= (inst
.instruction
>> 16) & 0xf;
8777 inst
.instruction
&= 0xff0fff0f;
8778 inst
.instruction
|= wrn
;
8779 /* Bail out here; the instruction is now assembled. */
8784 /* Map 32 -> 0, etc. */
8785 inst
.operands
[2].imm
&= 0x1f;
8786 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8790 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8791 operations first, then control, shift, and load/store. */
8793 /* Insns like "foo X,Y,Z". */
8796 do_mav_triple (void)
8798 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8799 inst
.instruction
|= inst
.operands
[1].reg
;
8800 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8803 /* Insns like "foo W,X,Y,Z".
8804 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8809 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8810 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8811 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8812 inst
.instruction
|= inst
.operands
[3].reg
;
8815 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8819 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8822 /* Maverick shift immediate instructions.
8823 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8824 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8829 int imm
= inst
.operands
[2].imm
;
8831 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8832 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8834 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8835 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8836 Bit 4 should be 0. */
8837 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8839 inst
.instruction
|= imm
;
8842 /* XScale instructions. Also sorted arithmetic before move. */
8844 /* Xscale multiply-accumulate (argument parse)
8847 MIAxycc acc0,Rm,Rs. */
8852 inst
.instruction
|= inst
.operands
[1].reg
;
8853 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8856 /* Xscale move-accumulator-register (argument parse)
8858 MARcc acc0,RdLo,RdHi. */
8863 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8864 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8867 /* Xscale move-register-accumulator (argument parse)
8869 MRAcc RdLo,RdHi,acc0. */
8874 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8876 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8879 /* Encoding functions relevant only to Thumb. */
8881 /* inst.operands[i] is a shifted-register operand; encode
8882 it into inst.instruction in the format used by Thumb32. */
8885 encode_thumb32_shifted_operand (int i
)
8887 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8888 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8890 constraint (inst
.operands
[i
].immisreg
,
8891 _("shift by register not allowed in thumb mode"));
8892 inst
.instruction
|= inst
.operands
[i
].reg
;
8893 if (shift
== SHIFT_RRX
)
8894 inst
.instruction
|= SHIFT_ROR
<< 4;
8897 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8898 _("expression too complex"));
8900 constraint (value
> 32
8901 || (value
== 32 && (shift
== SHIFT_LSL
8902 || shift
== SHIFT_ROR
)),
8903 _("shift expression is too large"));
8907 else if (value
== 32)
8910 inst
.instruction
|= shift
<< 4;
8911 inst
.instruction
|= (value
& 0x1c) << 10;
8912 inst
.instruction
|= (value
& 0x03) << 6;
8917 /* inst.operands[i] was set up by parse_address. Encode it into a
8918 Thumb32 format load or store instruction. Reject forms that cannot
8919 be used with such instructions. If is_t is true, reject forms that
8920 cannot be used with a T instruction; if is_d is true, reject forms
8921 that cannot be used with a D instruction. If it is a store insn,
8925 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8927 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8929 constraint (!inst
.operands
[i
].isreg
,
8930 _("Instruction does not support =N addresses"));
8932 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8933 if (inst
.operands
[i
].immisreg
)
8935 constraint (is_pc
, BAD_PC_ADDRESSING
);
8936 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8937 constraint (inst
.operands
[i
].negative
,
8938 _("Thumb does not support negative register indexing"));
8939 constraint (inst
.operands
[i
].postind
,
8940 _("Thumb does not support register post-indexing"));
8941 constraint (inst
.operands
[i
].writeback
,
8942 _("Thumb does not support register indexing with writeback"));
8943 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8944 _("Thumb supports only LSL in shifted register indexing"));
8946 inst
.instruction
|= inst
.operands
[i
].imm
;
8947 if (inst
.operands
[i
].shifted
)
8949 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8950 _("expression too complex"));
8951 constraint (inst
.reloc
.exp
.X_add_number
< 0
8952 || inst
.reloc
.exp
.X_add_number
> 3,
8953 _("shift out of range"));
8954 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8956 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8958 else if (inst
.operands
[i
].preind
)
8960 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8961 constraint (is_t
&& inst
.operands
[i
].writeback
,
8962 _("cannot use writeback with this instruction"));
8963 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8964 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8968 inst
.instruction
|= 0x01000000;
8969 if (inst
.operands
[i
].writeback
)
8970 inst
.instruction
|= 0x00200000;
8974 inst
.instruction
|= 0x00000c00;
8975 if (inst
.operands
[i
].writeback
)
8976 inst
.instruction
|= 0x00000100;
8978 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8980 else if (inst
.operands
[i
].postind
)
8982 gas_assert (inst
.operands
[i
].writeback
);
8983 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8984 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8987 inst
.instruction
|= 0x00200000;
8989 inst
.instruction
|= 0x00000900;
8990 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8992 else /* unindexed - only for coprocessor */
8993 inst
.error
= _("instruction does not accept unindexed addressing");
8996 /* Table of Thumb instructions which exist in both 16- and 32-bit
8997 encodings (the latter only in post-V6T2 cores). The index is the
8998 value used in the insns table below. When there is more than one
8999 possible 16-bit encoding for the instruction, this table always
9001 Also contains several pseudo-instructions used during relaxation. */
9002 #define T16_32_TAB \
9003 X(_adc, 4140, eb400000), \
9004 X(_adcs, 4140, eb500000), \
9005 X(_add, 1c00, eb000000), \
9006 X(_adds, 1c00, eb100000), \
9007 X(_addi, 0000, f1000000), \
9008 X(_addis, 0000, f1100000), \
9009 X(_add_pc,000f, f20f0000), \
9010 X(_add_sp,000d, f10d0000), \
9011 X(_adr, 000f, f20f0000), \
9012 X(_and, 4000, ea000000), \
9013 X(_ands, 4000, ea100000), \
9014 X(_asr, 1000, fa40f000), \
9015 X(_asrs, 1000, fa50f000), \
9016 X(_b, e000, f000b000), \
9017 X(_bcond, d000, f0008000), \
9018 X(_bic, 4380, ea200000), \
9019 X(_bics, 4380, ea300000), \
9020 X(_cmn, 42c0, eb100f00), \
9021 X(_cmp, 2800, ebb00f00), \
9022 X(_cpsie, b660, f3af8400), \
9023 X(_cpsid, b670, f3af8600), \
9024 X(_cpy, 4600, ea4f0000), \
9025 X(_dec_sp,80dd, f1ad0d00), \
9026 X(_eor, 4040, ea800000), \
9027 X(_eors, 4040, ea900000), \
9028 X(_inc_sp,00dd, f10d0d00), \
9029 X(_ldmia, c800, e8900000), \
9030 X(_ldr, 6800, f8500000), \
9031 X(_ldrb, 7800, f8100000), \
9032 X(_ldrh, 8800, f8300000), \
9033 X(_ldrsb, 5600, f9100000), \
9034 X(_ldrsh, 5e00, f9300000), \
9035 X(_ldr_pc,4800, f85f0000), \
9036 X(_ldr_pc2,4800, f85f0000), \
9037 X(_ldr_sp,9800, f85d0000), \
9038 X(_lsl, 0000, fa00f000), \
9039 X(_lsls, 0000, fa10f000), \
9040 X(_lsr, 0800, fa20f000), \
9041 X(_lsrs, 0800, fa30f000), \
9042 X(_mov, 2000, ea4f0000), \
9043 X(_movs, 2000, ea5f0000), \
9044 X(_mul, 4340, fb00f000), \
9045 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9046 X(_mvn, 43c0, ea6f0000), \
9047 X(_mvns, 43c0, ea7f0000), \
9048 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9049 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9050 X(_orr, 4300, ea400000), \
9051 X(_orrs, 4300, ea500000), \
9052 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9053 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9054 X(_rev, ba00, fa90f080), \
9055 X(_rev16, ba40, fa90f090), \
9056 X(_revsh, bac0, fa90f0b0), \
9057 X(_ror, 41c0, fa60f000), \
9058 X(_rors, 41c0, fa70f000), \
9059 X(_sbc, 4180, eb600000), \
9060 X(_sbcs, 4180, eb700000), \
9061 X(_stmia, c000, e8800000), \
9062 X(_str, 6000, f8400000), \
9063 X(_strb, 7000, f8000000), \
9064 X(_strh, 8000, f8200000), \
9065 X(_str_sp,9000, f84d0000), \
9066 X(_sub, 1e00, eba00000), \
9067 X(_subs, 1e00, ebb00000), \
9068 X(_subi, 8000, f1a00000), \
9069 X(_subis, 8000, f1b00000), \
9070 X(_sxtb, b240, fa4ff080), \
9071 X(_sxth, b200, fa0ff080), \
9072 X(_tst, 4200, ea100f00), \
9073 X(_uxtb, b2c0, fa5ff080), \
9074 X(_uxth, b280, fa1ff080), \
9075 X(_nop, bf00, f3af8000), \
9076 X(_yield, bf10, f3af8001), \
9077 X(_wfe, bf20, f3af8002), \
9078 X(_wfi, bf30, f3af8003), \
9079 X(_sev, bf40, f3af8004),
9081 /* To catch errors in encoding functions, the codes are all offset by
9082 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9083 as 16-bit instructions. */
9084 #define X(a,b,c) T_MNEM##a
9085 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9088 #define X(a,b,c) 0x##b
9089 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9090 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9093 #define X(a,b,c) 0x##c
9094 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9095 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9096 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9100 /* Thumb instruction encoders, in alphabetical order. */
9105 do_t_add_sub_w (void)
9109 Rd
= inst
.operands
[0].reg
;
9110 Rn
= inst
.operands
[1].reg
;
9112 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9113 is the SP-{plus,minus}-immediate form of the instruction. */
9115 constraint (Rd
== REG_PC
, BAD_PC
);
9117 reject_bad_reg (Rd
);
9119 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9120 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9123 /* Parse an add or subtract instruction. We get here with inst.instruction
9124 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9131 Rd
= inst
.operands
[0].reg
;
9132 Rs
= (inst
.operands
[1].present
9133 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9134 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9137 set_it_insn_type_last ();
9145 flags
= (inst
.instruction
== T_MNEM_adds
9146 || inst
.instruction
== T_MNEM_subs
);
9148 narrow
= !in_it_block ();
9150 narrow
= in_it_block ();
9151 if (!inst
.operands
[2].isreg
)
9155 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9157 add
= (inst
.instruction
== T_MNEM_add
9158 || inst
.instruction
== T_MNEM_adds
);
9160 if (inst
.size_req
!= 4)
9162 /* Attempt to use a narrow opcode, with relaxation if
9164 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9165 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9166 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9167 opcode
= T_MNEM_add_sp
;
9168 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9169 opcode
= T_MNEM_add_pc
;
9170 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9173 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9175 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9179 inst
.instruction
= THUMB_OP16(opcode
);
9180 inst
.instruction
|= (Rd
<< 4) | Rs
;
9181 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9182 if (inst
.size_req
!= 2)
9183 inst
.relax
= opcode
;
9186 constraint (inst
.size_req
== 2, BAD_HIREG
);
9188 if (inst
.size_req
== 4
9189 || (inst
.size_req
!= 2 && !opcode
))
9193 constraint (add
, BAD_PC
);
9194 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9195 _("only SUBS PC, LR, #const allowed"));
9196 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9197 _("expression too complex"));
9198 constraint (inst
.reloc
.exp
.X_add_number
< 0
9199 || inst
.reloc
.exp
.X_add_number
> 0xff,
9200 _("immediate value out of range"));
9201 inst
.instruction
= T2_SUBS_PC_LR
9202 | inst
.reloc
.exp
.X_add_number
;
9203 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9206 else if (Rs
== REG_PC
)
9208 /* Always use addw/subw. */
9209 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9210 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9214 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9215 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9218 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9220 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9222 inst
.instruction
|= Rd
<< 8;
9223 inst
.instruction
|= Rs
<< 16;
9228 Rn
= inst
.operands
[2].reg
;
9229 /* See if we can do this with a 16-bit instruction. */
9230 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9232 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9237 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9238 || inst
.instruction
== T_MNEM_add
)
9241 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9245 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9247 /* Thumb-1 cores (except v6-M) require at least one high
9248 register in a narrow non flag setting add. */
9249 if (Rd
> 7 || Rn
> 7
9250 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9251 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9258 inst
.instruction
= T_OPCODE_ADD_HI
;
9259 inst
.instruction
|= (Rd
& 8) << 4;
9260 inst
.instruction
|= (Rd
& 7);
9261 inst
.instruction
|= Rn
<< 3;
9267 constraint (Rd
== REG_PC
, BAD_PC
);
9268 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9269 constraint (Rs
== REG_PC
, BAD_PC
);
9270 reject_bad_reg (Rn
);
9272 /* If we get here, it can't be done in 16 bits. */
9273 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9274 _("shift must be constant"));
9275 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9276 inst
.instruction
|= Rd
<< 8;
9277 inst
.instruction
|= Rs
<< 16;
9278 encode_thumb32_shifted_operand (2);
9283 constraint (inst
.instruction
== T_MNEM_adds
9284 || inst
.instruction
== T_MNEM_subs
,
9287 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9289 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9290 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9293 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9295 inst
.instruction
|= (Rd
<< 4) | Rs
;
9296 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9300 Rn
= inst
.operands
[2].reg
;
9301 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9303 /* We now have Rd, Rs, and Rn set to registers. */
9304 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9306 /* Can't do this for SUB. */
9307 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9308 inst
.instruction
= T_OPCODE_ADD_HI
;
9309 inst
.instruction
|= (Rd
& 8) << 4;
9310 inst
.instruction
|= (Rd
& 7);
9312 inst
.instruction
|= Rn
<< 3;
9314 inst
.instruction
|= Rs
<< 3;
9316 constraint (1, _("dest must overlap one source register"));
9320 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9321 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9322 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9332 Rd
= inst
.operands
[0].reg
;
9333 reject_bad_reg (Rd
);
9335 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9337 /* Defer to section relaxation. */
9338 inst
.relax
= inst
.instruction
;
9339 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9340 inst
.instruction
|= Rd
<< 4;
9342 else if (unified_syntax
&& inst
.size_req
!= 2)
9344 /* Generate a 32-bit opcode. */
9345 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9346 inst
.instruction
|= Rd
<< 8;
9347 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9348 inst
.reloc
.pc_rel
= 1;
9352 /* Generate a 16-bit opcode. */
9353 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9354 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9355 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9356 inst
.reloc
.pc_rel
= 1;
9358 inst
.instruction
|= Rd
<< 4;
9362 /* Arithmetic instructions for which there is just one 16-bit
9363 instruction encoding, and it allows only two low registers.
9364 For maximal compatibility with ARM syntax, we allow three register
9365 operands even when Thumb-32 instructions are not available, as long
9366 as the first two are identical. For instance, both "sbc r0,r1" and
9367 "sbc r0,r0,r1" are allowed. */
9373 Rd
= inst
.operands
[0].reg
;
9374 Rs
= (inst
.operands
[1].present
9375 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9376 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9377 Rn
= inst
.operands
[2].reg
;
9379 reject_bad_reg (Rd
);
9380 reject_bad_reg (Rs
);
9381 if (inst
.operands
[2].isreg
)
9382 reject_bad_reg (Rn
);
9386 if (!inst
.operands
[2].isreg
)
9388 /* For an immediate, we always generate a 32-bit opcode;
9389 section relaxation will shrink it later if possible. */
9390 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9391 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9392 inst
.instruction
|= Rd
<< 8;
9393 inst
.instruction
|= Rs
<< 16;
9394 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9400 /* See if we can do this with a 16-bit instruction. */
9401 if (THUMB_SETS_FLAGS (inst
.instruction
))
9402 narrow
= !in_it_block ();
9404 narrow
= in_it_block ();
9406 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9408 if (inst
.operands
[2].shifted
)
9410 if (inst
.size_req
== 4)
9416 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9417 inst
.instruction
|= Rd
;
9418 inst
.instruction
|= Rn
<< 3;
9422 /* If we get here, it can't be done in 16 bits. */
9423 constraint (inst
.operands
[2].shifted
9424 && inst
.operands
[2].immisreg
,
9425 _("shift must be constant"));
9426 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9427 inst
.instruction
|= Rd
<< 8;
9428 inst
.instruction
|= Rs
<< 16;
9429 encode_thumb32_shifted_operand (2);
9434 /* On its face this is a lie - the instruction does set the
9435 flags. However, the only supported mnemonic in this mode
9437 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9439 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9440 _("unshifted register required"));
9441 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9442 constraint (Rd
!= Rs
,
9443 _("dest and source1 must be the same register"));
9445 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9446 inst
.instruction
|= Rd
;
9447 inst
.instruction
|= Rn
<< 3;
9451 /* Similarly, but for instructions where the arithmetic operation is
9452 commutative, so we can allow either of them to be different from
9453 the destination operand in a 16-bit instruction. For instance, all
9454 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9461 Rd
= inst
.operands
[0].reg
;
9462 Rs
= (inst
.operands
[1].present
9463 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9464 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9465 Rn
= inst
.operands
[2].reg
;
9467 reject_bad_reg (Rd
);
9468 reject_bad_reg (Rs
);
9469 if (inst
.operands
[2].isreg
)
9470 reject_bad_reg (Rn
);
9474 if (!inst
.operands
[2].isreg
)
9476 /* For an immediate, we always generate a 32-bit opcode;
9477 section relaxation will shrink it later if possible. */
9478 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9479 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9480 inst
.instruction
|= Rd
<< 8;
9481 inst
.instruction
|= Rs
<< 16;
9482 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9488 /* See if we can do this with a 16-bit instruction. */
9489 if (THUMB_SETS_FLAGS (inst
.instruction
))
9490 narrow
= !in_it_block ();
9492 narrow
= in_it_block ();
9494 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9496 if (inst
.operands
[2].shifted
)
9498 if (inst
.size_req
== 4)
9505 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9506 inst
.instruction
|= Rd
;
9507 inst
.instruction
|= Rn
<< 3;
9512 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9513 inst
.instruction
|= Rd
;
9514 inst
.instruction
|= Rs
<< 3;
9519 /* If we get here, it can't be done in 16 bits. */
9520 constraint (inst
.operands
[2].shifted
9521 && inst
.operands
[2].immisreg
,
9522 _("shift must be constant"));
9523 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9524 inst
.instruction
|= Rd
<< 8;
9525 inst
.instruction
|= Rs
<< 16;
9526 encode_thumb32_shifted_operand (2);
9531 /* On its face this is a lie - the instruction does set the
9532 flags. However, the only supported mnemonic in this mode
9534 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9536 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9537 _("unshifted register required"));
9538 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9540 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9541 inst
.instruction
|= Rd
;
9544 inst
.instruction
|= Rn
<< 3;
9546 inst
.instruction
|= Rs
<< 3;
9548 constraint (1, _("dest must overlap one source register"));
9555 if (inst
.operands
[0].present
)
9557 constraint ((inst
.instruction
& 0xf0) != 0x40
9558 && inst
.operands
[0].imm
> 0xf
9559 && inst
.operands
[0].imm
< 0x0,
9560 _("bad barrier type"));
9561 inst
.instruction
|= inst
.operands
[0].imm
;
9564 inst
.instruction
|= 0xf;
9571 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9572 constraint (msb
> 32, _("bit-field extends past end of register"));
9573 /* The instruction encoding stores the LSB and MSB,
9574 not the LSB and width. */
9575 Rd
= inst
.operands
[0].reg
;
9576 reject_bad_reg (Rd
);
9577 inst
.instruction
|= Rd
<< 8;
9578 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9579 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9580 inst
.instruction
|= msb
- 1;
9589 Rd
= inst
.operands
[0].reg
;
9590 reject_bad_reg (Rd
);
9592 /* #0 in second position is alternative syntax for bfc, which is
9593 the same instruction but with REG_PC in the Rm field. */
9594 if (!inst
.operands
[1].isreg
)
9598 Rn
= inst
.operands
[1].reg
;
9599 reject_bad_reg (Rn
);
9602 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9603 constraint (msb
> 32, _("bit-field extends past end of register"));
9604 /* The instruction encoding stores the LSB and MSB,
9605 not the LSB and width. */
9606 inst
.instruction
|= Rd
<< 8;
9607 inst
.instruction
|= Rn
<< 16;
9608 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9609 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9610 inst
.instruction
|= msb
- 1;
9618 Rd
= inst
.operands
[0].reg
;
9619 Rn
= inst
.operands
[1].reg
;
9621 reject_bad_reg (Rd
);
9622 reject_bad_reg (Rn
);
9624 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9625 _("bit-field extends past end of register"));
9626 inst
.instruction
|= Rd
<< 8;
9627 inst
.instruction
|= Rn
<< 16;
9628 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9629 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9630 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9633 /* ARM V5 Thumb BLX (argument parse)
9634 BLX <target_addr> which is BLX(1)
9635 BLX <Rm> which is BLX(2)
9636 Unfortunately, there are two different opcodes for this mnemonic.
9637 So, the insns[].value is not used, and the code here zaps values
9638 into inst.instruction.
9640 ??? How to take advantage of the additional two bits of displacement
9641 available in Thumb32 mode? Need new relocation? */
9646 set_it_insn_type_last ();
9648 if (inst
.operands
[0].isreg
)
9650 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9651 /* We have a register, so this is BLX(2). */
9652 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9656 /* No register. This must be BLX(1). */
9657 inst
.instruction
= 0xf000e800;
9658 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9659 inst
.reloc
.pc_rel
= 1;
9671 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9675 /* Conditional branches inside IT blocks are encoded as unconditional
9682 if (cond
!= COND_ALWAYS
)
9683 opcode
= T_MNEM_bcond
;
9685 opcode
= inst
.instruction
;
9688 && (inst
.size_req
== 4
9689 || (inst
.size_req
!= 2 && inst
.operands
[0].hasreloc
)))
9691 inst
.instruction
= THUMB_OP32(opcode
);
9692 if (cond
== COND_ALWAYS
)
9693 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9696 gas_assert (cond
!= 0xF);
9697 inst
.instruction
|= cond
<< 22;
9698 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9703 inst
.instruction
= THUMB_OP16(opcode
);
9704 if (cond
== COND_ALWAYS
)
9705 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9708 inst
.instruction
|= cond
<< 8;
9709 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9711 /* Allow section relaxation. */
9712 if (unified_syntax
&& inst
.size_req
!= 2)
9713 inst
.relax
= opcode
;
9715 inst
.reloc
.type
= reloc
;
9716 inst
.reloc
.pc_rel
= 1;
9722 constraint (inst
.cond
!= COND_ALWAYS
,
9723 _("instruction is always unconditional"));
9724 if (inst
.operands
[0].present
)
9726 constraint (inst
.operands
[0].imm
> 255,
9727 _("immediate value out of range"));
9728 inst
.instruction
|= inst
.operands
[0].imm
;
9729 set_it_insn_type (NEUTRAL_IT_INSN
);
9734 do_t_branch23 (void)
9736 set_it_insn_type_last ();
9737 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9738 inst
.reloc
.pc_rel
= 1;
9740 #if defined(OBJ_COFF)
9741 /* If the destination of the branch is a defined symbol which does not have
9742 the THUMB_FUNC attribute, then we must be calling a function which has
9743 the (interfacearm) attribute. We look for the Thumb entry point to that
9744 function and change the branch to refer to that function instead. */
9745 if ( inst
.reloc
.exp
.X_op
== O_symbol
9746 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9747 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9748 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9749 inst
.reloc
.exp
.X_add_symbol
=
9750 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9757 set_it_insn_type_last ();
9758 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9759 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9760 should cause the alignment to be checked once it is known. This is
9761 because BX PC only works if the instruction is word aligned. */
9769 set_it_insn_type_last ();
9770 Rm
= inst
.operands
[0].reg
;
9771 reject_bad_reg (Rm
);
9772 inst
.instruction
|= Rm
<< 16;
9781 Rd
= inst
.operands
[0].reg
;
9782 Rm
= inst
.operands
[1].reg
;
9784 reject_bad_reg (Rd
);
9785 reject_bad_reg (Rm
);
9787 inst
.instruction
|= Rd
<< 8;
9788 inst
.instruction
|= Rm
<< 16;
9789 inst
.instruction
|= Rm
;
9795 set_it_insn_type (OUTSIDE_IT_INSN
);
9796 inst
.instruction
|= inst
.operands
[0].imm
;
9802 set_it_insn_type (OUTSIDE_IT_INSN
);
9804 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9805 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9807 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9808 inst
.instruction
= 0xf3af8000;
9809 inst
.instruction
|= imod
<< 9;
9810 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9811 if (inst
.operands
[1].present
)
9812 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9816 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9817 && (inst
.operands
[0].imm
& 4),
9818 _("selected processor does not support 'A' form "
9819 "of this instruction"));
9820 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9821 _("Thumb does not support the 2-argument "
9822 "form of this instruction"));
9823 inst
.instruction
|= inst
.operands
[0].imm
;
9827 /* THUMB CPY instruction (argument parse). */
9832 if (inst
.size_req
== 4)
9834 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9835 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9836 inst
.instruction
|= inst
.operands
[1].reg
;
9840 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9841 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9842 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9849 set_it_insn_type (OUTSIDE_IT_INSN
);
9850 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9851 inst
.instruction
|= inst
.operands
[0].reg
;
9852 inst
.reloc
.pc_rel
= 1;
9853 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9859 inst
.instruction
|= inst
.operands
[0].imm
;
9865 unsigned Rd
, Rn
, Rm
;
9867 Rd
= inst
.operands
[0].reg
;
9868 Rn
= (inst
.operands
[1].present
9869 ? inst
.operands
[1].reg
: Rd
);
9870 Rm
= inst
.operands
[2].reg
;
9872 reject_bad_reg (Rd
);
9873 reject_bad_reg (Rn
);
9874 reject_bad_reg (Rm
);
9876 inst
.instruction
|= Rd
<< 8;
9877 inst
.instruction
|= Rn
<< 16;
9878 inst
.instruction
|= Rm
;
9884 if (unified_syntax
&& inst
.size_req
== 4)
9885 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9887 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9893 unsigned int cond
= inst
.operands
[0].imm
;
9895 set_it_insn_type (IT_INSN
);
9896 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9899 /* If the condition is a negative condition, invert the mask. */
9900 if ((cond
& 0x1) == 0x0)
9902 unsigned int mask
= inst
.instruction
& 0x000f;
9904 if ((mask
& 0x7) == 0)
9905 /* no conversion needed */;
9906 else if ((mask
& 0x3) == 0)
9908 else if ((mask
& 0x1) == 0)
9913 inst
.instruction
&= 0xfff0;
9914 inst
.instruction
|= mask
;
9917 inst
.instruction
|= cond
<< 4;
9920 /* Helper function used for both push/pop and ldm/stm. */
9922 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9926 load
= (inst
.instruction
& (1 << 20)) != 0;
9928 if (mask
& (1 << 13))
9929 inst
.error
= _("SP not allowed in register list");
9931 if ((mask
& (1 << base
)) != 0
9933 inst
.error
= _("having the base register in the register list when "
9934 "using write back is UNPREDICTABLE");
9938 if (mask
& (1 << 15))
9940 if (mask
& (1 << 14))
9941 inst
.error
= _("LR and PC should not both be in register list");
9943 set_it_insn_type_last ();
9948 if (mask
& (1 << 15))
9949 inst
.error
= _("PC not allowed in register list");
9952 if ((mask
& (mask
- 1)) == 0)
9954 /* Single register transfers implemented as str/ldr. */
9957 if (inst
.instruction
& (1 << 23))
9958 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9960 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9964 if (inst
.instruction
& (1 << 23))
9965 inst
.instruction
= 0x00800000; /* ia -> [base] */
9967 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9970 inst
.instruction
|= 0xf8400000;
9972 inst
.instruction
|= 0x00100000;
9974 mask
= ffs (mask
) - 1;
9978 inst
.instruction
|= WRITE_BACK
;
9980 inst
.instruction
|= mask
;
9981 inst
.instruction
|= base
<< 16;
9987 /* This really doesn't seem worth it. */
9988 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9989 _("expression too complex"));
9990 constraint (inst
.operands
[1].writeback
,
9991 _("Thumb load/store multiple does not support {reglist}^"));
9999 /* See if we can use a 16-bit instruction. */
10000 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10001 && inst
.size_req
!= 4
10002 && !(inst
.operands
[1].imm
& ~0xff))
10004 mask
= 1 << inst
.operands
[0].reg
;
10006 if (inst
.operands
[0].reg
<= 7)
10008 if (inst
.instruction
== T_MNEM_stmia
10009 ? inst
.operands
[0].writeback
10010 : (inst
.operands
[0].writeback
10011 == !(inst
.operands
[1].imm
& mask
)))
10013 if (inst
.instruction
== T_MNEM_stmia
10014 && (inst
.operands
[1].imm
& mask
)
10015 && (inst
.operands
[1].imm
& (mask
- 1)))
10016 as_warn (_("value stored for r%d is UNKNOWN"),
10017 inst
.operands
[0].reg
);
10019 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10020 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10021 inst
.instruction
|= inst
.operands
[1].imm
;
10024 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10026 /* This means 1 register in reg list one of 3 situations:
10027 1. Instruction is stmia, but without writeback.
10028 2. lmdia without writeback, but with Rn not in
10030 3. ldmia with writeback, but with Rn in reglist.
10031 Case 3 is UNPREDICTABLE behaviour, so we handle
10032 case 1 and 2 which can be converted into a 16-bit
10033 str or ldr. The SP cases are handled below. */
10034 unsigned long opcode
;
10035 /* First, record an error for Case 3. */
10036 if (inst
.operands
[1].imm
& mask
10037 && inst
.operands
[0].writeback
)
10039 _("having the base register in the register list when "
10040 "using write back is UNPREDICTABLE");
10042 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10044 inst
.instruction
= THUMB_OP16 (opcode
);
10045 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10046 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10050 else if (inst
.operands
[0] .reg
== REG_SP
)
10052 if (inst
.operands
[0].writeback
)
10055 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10056 ? T_MNEM_push
: T_MNEM_pop
);
10057 inst
.instruction
|= inst
.operands
[1].imm
;
10060 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10063 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10064 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10065 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10073 if (inst
.instruction
< 0xffff)
10074 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10076 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10077 inst
.operands
[0].writeback
);
10082 constraint (inst
.operands
[0].reg
> 7
10083 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10084 constraint (inst
.instruction
!= T_MNEM_ldmia
10085 && inst
.instruction
!= T_MNEM_stmia
,
10086 _("Thumb-2 instruction only valid in unified syntax"));
10087 if (inst
.instruction
== T_MNEM_stmia
)
10089 if (!inst
.operands
[0].writeback
)
10090 as_warn (_("this instruction will write back the base register"));
10091 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10092 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10093 as_warn (_("value stored for r%d is UNKNOWN"),
10094 inst
.operands
[0].reg
);
10098 if (!inst
.operands
[0].writeback
10099 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10100 as_warn (_("this instruction will write back the base register"));
10101 else if (inst
.operands
[0].writeback
10102 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10103 as_warn (_("this instruction will not write back the base register"));
10106 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10107 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10108 inst
.instruction
|= inst
.operands
[1].imm
;
10115 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10116 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10117 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10118 || inst
.operands
[1].negative
,
10121 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10124 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10125 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10131 if (!inst
.operands
[1].present
)
10133 constraint (inst
.operands
[0].reg
== REG_LR
,
10134 _("r14 not allowed as first register "
10135 "when second register is omitted"));
10136 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10138 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10141 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10142 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10143 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10149 unsigned long opcode
;
10152 if (inst
.operands
[0].isreg
10153 && !inst
.operands
[0].preind
10154 && inst
.operands
[0].reg
== REG_PC
)
10155 set_it_insn_type_last ();
10157 opcode
= inst
.instruction
;
10158 if (unified_syntax
)
10160 if (!inst
.operands
[1].isreg
)
10162 if (opcode
<= 0xffff)
10163 inst
.instruction
= THUMB_OP32 (opcode
);
10164 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10167 if (inst
.operands
[1].isreg
10168 && !inst
.operands
[1].writeback
10169 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10170 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10171 && opcode
<= 0xffff
10172 && inst
.size_req
!= 4)
10174 /* Insn may have a 16-bit form. */
10175 Rn
= inst
.operands
[1].reg
;
10176 if (inst
.operands
[1].immisreg
)
10178 inst
.instruction
= THUMB_OP16 (opcode
);
10180 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10182 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10183 reject_bad_reg (inst
.operands
[1].imm
);
10185 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10186 && opcode
!= T_MNEM_ldrsb
)
10187 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10188 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10195 if (inst
.reloc
.pc_rel
)
10196 opcode
= T_MNEM_ldr_pc2
;
10198 opcode
= T_MNEM_ldr_pc
;
10202 if (opcode
== T_MNEM_ldr
)
10203 opcode
= T_MNEM_ldr_sp
;
10205 opcode
= T_MNEM_str_sp
;
10207 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10211 inst
.instruction
= inst
.operands
[0].reg
;
10212 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10214 inst
.instruction
|= THUMB_OP16 (opcode
);
10215 if (inst
.size_req
== 2)
10216 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10218 inst
.relax
= opcode
;
10222 /* Definitely a 32-bit variant. */
10224 /* Do some validations regarding addressing modes. */
10225 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10226 && opcode
!= T_MNEM_str
)
10227 reject_bad_reg (inst
.operands
[1].imm
);
10229 inst
.instruction
= THUMB_OP32 (opcode
);
10230 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10231 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10235 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10237 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10239 /* Only [Rn,Rm] is acceptable. */
10240 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10241 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10242 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10243 || inst
.operands
[1].negative
,
10244 _("Thumb does not support this addressing mode"));
10245 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10249 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10250 if (!inst
.operands
[1].isreg
)
10251 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10254 constraint (!inst
.operands
[1].preind
10255 || inst
.operands
[1].shifted
10256 || inst
.operands
[1].writeback
,
10257 _("Thumb does not support this addressing mode"));
10258 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10260 constraint (inst
.instruction
& 0x0600,
10261 _("byte or halfword not valid for base register"));
10262 constraint (inst
.operands
[1].reg
== REG_PC
10263 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10264 _("r15 based store not allowed"));
10265 constraint (inst
.operands
[1].immisreg
,
10266 _("invalid base register for register offset"));
10268 if (inst
.operands
[1].reg
== REG_PC
)
10269 inst
.instruction
= T_OPCODE_LDR_PC
;
10270 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10271 inst
.instruction
= T_OPCODE_LDR_SP
;
10273 inst
.instruction
= T_OPCODE_STR_SP
;
10275 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10276 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10280 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10281 if (!inst
.operands
[1].immisreg
)
10283 /* Immediate offset. */
10284 inst
.instruction
|= inst
.operands
[0].reg
;
10285 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10286 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10290 /* Register offset. */
10291 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10292 constraint (inst
.operands
[1].negative
,
10293 _("Thumb does not support this addressing mode"));
10296 switch (inst
.instruction
)
10298 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10299 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10300 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10301 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10302 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10303 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10304 case 0x5600 /* ldrsb */:
10305 case 0x5e00 /* ldrsh */: break;
10309 inst
.instruction
|= inst
.operands
[0].reg
;
10310 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10311 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10317 if (!inst
.operands
[1].present
)
10319 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10320 constraint (inst
.operands
[0].reg
== REG_LR
,
10321 _("r14 not allowed here"));
10323 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10324 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10325 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10332 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10338 unsigned Rd
, Rn
, Rm
, Ra
;
10340 Rd
= inst
.operands
[0].reg
;
10341 Rn
= inst
.operands
[1].reg
;
10342 Rm
= inst
.operands
[2].reg
;
10343 Ra
= inst
.operands
[3].reg
;
10345 reject_bad_reg (Rd
);
10346 reject_bad_reg (Rn
);
10347 reject_bad_reg (Rm
);
10348 reject_bad_reg (Ra
);
10350 inst
.instruction
|= Rd
<< 8;
10351 inst
.instruction
|= Rn
<< 16;
10352 inst
.instruction
|= Rm
;
10353 inst
.instruction
|= Ra
<< 12;
10359 unsigned RdLo
, RdHi
, Rn
, Rm
;
10361 RdLo
= inst
.operands
[0].reg
;
10362 RdHi
= inst
.operands
[1].reg
;
10363 Rn
= inst
.operands
[2].reg
;
10364 Rm
= inst
.operands
[3].reg
;
10366 reject_bad_reg (RdLo
);
10367 reject_bad_reg (RdHi
);
10368 reject_bad_reg (Rn
);
10369 reject_bad_reg (Rm
);
10371 inst
.instruction
|= RdLo
<< 12;
10372 inst
.instruction
|= RdHi
<< 8;
10373 inst
.instruction
|= Rn
<< 16;
10374 inst
.instruction
|= Rm
;
10378 do_t_mov_cmp (void)
10382 Rn
= inst
.operands
[0].reg
;
10383 Rm
= inst
.operands
[1].reg
;
10386 set_it_insn_type_last ();
10388 if (unified_syntax
)
10390 int r0off
= (inst
.instruction
== T_MNEM_mov
10391 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10392 unsigned long opcode
;
10393 bfd_boolean narrow
;
10394 bfd_boolean low_regs
;
10396 low_regs
= (Rn
<= 7 && Rm
<= 7);
10397 opcode
= inst
.instruction
;
10398 if (in_it_block ())
10399 narrow
= opcode
!= T_MNEM_movs
;
10401 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10402 if (inst
.size_req
== 4
10403 || inst
.operands
[1].shifted
)
10406 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10407 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10408 && !inst
.operands
[1].shifted
10412 inst
.instruction
= T2_SUBS_PC_LR
;
10416 if (opcode
== T_MNEM_cmp
)
10418 constraint (Rn
== REG_PC
, BAD_PC
);
10421 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10423 warn_deprecated_sp (Rm
);
10424 /* R15 was documented as a valid choice for Rm in ARMv6,
10425 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10426 tools reject R15, so we do too. */
10427 constraint (Rm
== REG_PC
, BAD_PC
);
10430 reject_bad_reg (Rm
);
10432 else if (opcode
== T_MNEM_mov
10433 || opcode
== T_MNEM_movs
)
10435 if (inst
.operands
[1].isreg
)
10437 if (opcode
== T_MNEM_movs
)
10439 reject_bad_reg (Rn
);
10440 reject_bad_reg (Rm
);
10444 /* This is mov.n. */
10445 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10446 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10448 as_warn (_("Use of r%u as a source register is "
10449 "deprecated when r%u is the destination "
10450 "register."), Rm
, Rn
);
10455 /* This is mov.w. */
10456 constraint (Rn
== REG_PC
, BAD_PC
);
10457 constraint (Rm
== REG_PC
, BAD_PC
);
10458 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10462 reject_bad_reg (Rn
);
10465 if (!inst
.operands
[1].isreg
)
10467 /* Immediate operand. */
10468 if (!in_it_block () && opcode
== T_MNEM_mov
)
10470 if (low_regs
&& narrow
)
10472 inst
.instruction
= THUMB_OP16 (opcode
);
10473 inst
.instruction
|= Rn
<< 8;
10474 if (inst
.size_req
== 2)
10475 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10477 inst
.relax
= opcode
;
10481 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10482 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10483 inst
.instruction
|= Rn
<< r0off
;
10484 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10487 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10488 && (inst
.instruction
== T_MNEM_mov
10489 || inst
.instruction
== T_MNEM_movs
))
10491 /* Register shifts are encoded as separate shift instructions. */
10492 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10494 if (in_it_block ())
10499 if (inst
.size_req
== 4)
10502 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10508 switch (inst
.operands
[1].shift_kind
)
10511 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10514 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10517 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10520 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10526 inst
.instruction
= opcode
;
10529 inst
.instruction
|= Rn
;
10530 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10535 inst
.instruction
|= CONDS_BIT
;
10537 inst
.instruction
|= Rn
<< 8;
10538 inst
.instruction
|= Rm
<< 16;
10539 inst
.instruction
|= inst
.operands
[1].imm
;
10544 /* Some mov with immediate shift have narrow variants.
10545 Register shifts are handled above. */
10546 if (low_regs
&& inst
.operands
[1].shifted
10547 && (inst
.instruction
== T_MNEM_mov
10548 || inst
.instruction
== T_MNEM_movs
))
10550 if (in_it_block ())
10551 narrow
= (inst
.instruction
== T_MNEM_mov
);
10553 narrow
= (inst
.instruction
== T_MNEM_movs
);
10558 switch (inst
.operands
[1].shift_kind
)
10560 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10561 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10562 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10563 default: narrow
= FALSE
; break;
10569 inst
.instruction
|= Rn
;
10570 inst
.instruction
|= Rm
<< 3;
10571 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10575 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10576 inst
.instruction
|= Rn
<< r0off
;
10577 encode_thumb32_shifted_operand (1);
10581 switch (inst
.instruction
)
10584 inst
.instruction
= T_OPCODE_MOV_HR
;
10585 inst
.instruction
|= (Rn
& 0x8) << 4;
10586 inst
.instruction
|= (Rn
& 0x7);
10587 inst
.instruction
|= Rm
<< 3;
10591 /* We know we have low registers at this point.
10592 Generate LSLS Rd, Rs, #0. */
10593 inst
.instruction
= T_OPCODE_LSL_I
;
10594 inst
.instruction
|= Rn
;
10595 inst
.instruction
|= Rm
<< 3;
10601 inst
.instruction
= T_OPCODE_CMP_LR
;
10602 inst
.instruction
|= Rn
;
10603 inst
.instruction
|= Rm
<< 3;
10607 inst
.instruction
= T_OPCODE_CMP_HR
;
10608 inst
.instruction
|= (Rn
& 0x8) << 4;
10609 inst
.instruction
|= (Rn
& 0x7);
10610 inst
.instruction
|= Rm
<< 3;
10617 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10619 /* PR 10443: Do not silently ignore shifted operands. */
10620 constraint (inst
.operands
[1].shifted
,
10621 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10623 if (inst
.operands
[1].isreg
)
10625 if (Rn
< 8 && Rm
< 8)
10627 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10628 since a MOV instruction produces unpredictable results. */
10629 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10630 inst
.instruction
= T_OPCODE_ADD_I3
;
10632 inst
.instruction
= T_OPCODE_CMP_LR
;
10634 inst
.instruction
|= Rn
;
10635 inst
.instruction
|= Rm
<< 3;
10639 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10640 inst
.instruction
= T_OPCODE_MOV_HR
;
10642 inst
.instruction
= T_OPCODE_CMP_HR
;
10648 constraint (Rn
> 7,
10649 _("only lo regs allowed with immediate"));
10650 inst
.instruction
|= Rn
<< 8;
10651 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10662 top
= (inst
.instruction
& 0x00800000) != 0;
10663 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10665 constraint (top
, _(":lower16: not allowed this instruction"));
10666 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10668 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10670 constraint (!top
, _(":upper16: not allowed this instruction"));
10671 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10674 Rd
= inst
.operands
[0].reg
;
10675 reject_bad_reg (Rd
);
10677 inst
.instruction
|= Rd
<< 8;
10678 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10680 imm
= inst
.reloc
.exp
.X_add_number
;
10681 inst
.instruction
|= (imm
& 0xf000) << 4;
10682 inst
.instruction
|= (imm
& 0x0800) << 15;
10683 inst
.instruction
|= (imm
& 0x0700) << 4;
10684 inst
.instruction
|= (imm
& 0x00ff);
10689 do_t_mvn_tst (void)
10693 Rn
= inst
.operands
[0].reg
;
10694 Rm
= inst
.operands
[1].reg
;
10696 if (inst
.instruction
== T_MNEM_cmp
10697 || inst
.instruction
== T_MNEM_cmn
)
10698 constraint (Rn
== REG_PC
, BAD_PC
);
10700 reject_bad_reg (Rn
);
10701 reject_bad_reg (Rm
);
10703 if (unified_syntax
)
10705 int r0off
= (inst
.instruction
== T_MNEM_mvn
10706 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10707 bfd_boolean narrow
;
10709 if (inst
.size_req
== 4
10710 || inst
.instruction
> 0xffff
10711 || inst
.operands
[1].shifted
10712 || Rn
> 7 || Rm
> 7)
10714 else if (inst
.instruction
== T_MNEM_cmn
)
10716 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10717 narrow
= !in_it_block ();
10719 narrow
= in_it_block ();
10721 if (!inst
.operands
[1].isreg
)
10723 /* For an immediate, we always generate a 32-bit opcode;
10724 section relaxation will shrink it later if possible. */
10725 if (inst
.instruction
< 0xffff)
10726 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10727 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10728 inst
.instruction
|= Rn
<< r0off
;
10729 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10733 /* See if we can do this with a 16-bit instruction. */
10736 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10737 inst
.instruction
|= Rn
;
10738 inst
.instruction
|= Rm
<< 3;
10742 constraint (inst
.operands
[1].shifted
10743 && inst
.operands
[1].immisreg
,
10744 _("shift must be constant"));
10745 if (inst
.instruction
< 0xffff)
10746 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10747 inst
.instruction
|= Rn
<< r0off
;
10748 encode_thumb32_shifted_operand (1);
10754 constraint (inst
.instruction
> 0xffff
10755 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10756 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10757 _("unshifted register required"));
10758 constraint (Rn
> 7 || Rm
> 7,
10761 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10762 inst
.instruction
|= Rn
;
10763 inst
.instruction
|= Rm
<< 3;
10772 if (do_vfp_nsyn_mrs () == SUCCESS
)
10775 Rd
= inst
.operands
[0].reg
;
10776 reject_bad_reg (Rd
);
10777 inst
.instruction
|= Rd
<< 8;
10779 if (inst
.operands
[1].isreg
)
10781 unsigned br
= inst
.operands
[1].reg
;
10782 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
10783 as_bad (_("bad register for mrs"));
10785 inst
.instruction
|= br
& (0xf << 16);
10786 inst
.instruction
|= (br
& 0x300) >> 4;
10787 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
10791 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10795 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10796 _("selected processor does not support "
10797 "requested special purpose register"));
10801 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10802 _("selected processor does not support "
10803 "requested special purpose register"));
10804 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10805 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10806 _("'CPSR' or 'SPSR' expected"));
10809 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10810 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10811 inst
.instruction
|= 0xf0000;
10821 if (do_vfp_nsyn_msr () == SUCCESS
)
10824 constraint (!inst
.operands
[1].isreg
,
10825 _("Thumb encoding does not support an immediate here"));
10827 if (inst
.operands
[0].isreg
)
10828 flags
= (int)(inst
.operands
[0].reg
);
10830 flags
= inst
.operands
[0].imm
;
10834 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10835 _("selected processor does not support "
10836 "requested special purpose register"));
10840 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10841 _("selected processor does not support "
10842 "requested special purpose register"));
10846 Rn
= inst
.operands
[1].reg
;
10847 reject_bad_reg (Rn
);
10849 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10850 inst
.instruction
|= (flags
& 0xf0000) >> 8;
10851 inst
.instruction
|= (flags
& 0x300) >> 4;
10852 inst
.instruction
|= (flags
& 0xff);
10853 inst
.instruction
|= Rn
<< 16;
10859 bfd_boolean narrow
;
10860 unsigned Rd
, Rn
, Rm
;
10862 if (!inst
.operands
[2].present
)
10863 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10865 Rd
= inst
.operands
[0].reg
;
10866 Rn
= inst
.operands
[1].reg
;
10867 Rm
= inst
.operands
[2].reg
;
10869 if (unified_syntax
)
10871 if (inst
.size_req
== 4
10877 else if (inst
.instruction
== T_MNEM_muls
)
10878 narrow
= !in_it_block ();
10880 narrow
= in_it_block ();
10884 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10885 constraint (Rn
> 7 || Rm
> 7,
10892 /* 16-bit MULS/Conditional MUL. */
10893 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10894 inst
.instruction
|= Rd
;
10897 inst
.instruction
|= Rm
<< 3;
10899 inst
.instruction
|= Rn
<< 3;
10901 constraint (1, _("dest must overlap one source register"));
10905 constraint (inst
.instruction
!= T_MNEM_mul
,
10906 _("Thumb-2 MUL must not set flags"));
10908 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10909 inst
.instruction
|= Rd
<< 8;
10910 inst
.instruction
|= Rn
<< 16;
10911 inst
.instruction
|= Rm
<< 0;
10913 reject_bad_reg (Rd
);
10914 reject_bad_reg (Rn
);
10915 reject_bad_reg (Rm
);
10922 unsigned RdLo
, RdHi
, Rn
, Rm
;
10924 RdLo
= inst
.operands
[0].reg
;
10925 RdHi
= inst
.operands
[1].reg
;
10926 Rn
= inst
.operands
[2].reg
;
10927 Rm
= inst
.operands
[3].reg
;
10929 reject_bad_reg (RdLo
);
10930 reject_bad_reg (RdHi
);
10931 reject_bad_reg (Rn
);
10932 reject_bad_reg (Rm
);
10934 inst
.instruction
|= RdLo
<< 12;
10935 inst
.instruction
|= RdHi
<< 8;
10936 inst
.instruction
|= Rn
<< 16;
10937 inst
.instruction
|= Rm
;
10940 as_tsktsk (_("rdhi and rdlo must be different"));
10946 set_it_insn_type (NEUTRAL_IT_INSN
);
10948 if (unified_syntax
)
10950 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10952 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10953 inst
.instruction
|= inst
.operands
[0].imm
;
10957 /* PR9722: Check for Thumb2 availability before
10958 generating a thumb2 nop instruction. */
10959 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10961 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10962 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10965 inst
.instruction
= 0x46c0;
10970 constraint (inst
.operands
[0].present
,
10971 _("Thumb does not support NOP with hints"));
10972 inst
.instruction
= 0x46c0;
10979 if (unified_syntax
)
10981 bfd_boolean narrow
;
10983 if (THUMB_SETS_FLAGS (inst
.instruction
))
10984 narrow
= !in_it_block ();
10986 narrow
= in_it_block ();
10987 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10989 if (inst
.size_req
== 4)
10994 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10995 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10996 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11000 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11001 inst
.instruction
|= inst
.operands
[0].reg
;
11002 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11007 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11009 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11011 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11012 inst
.instruction
|= inst
.operands
[0].reg
;
11013 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11022 Rd
= inst
.operands
[0].reg
;
11023 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11025 reject_bad_reg (Rd
);
11026 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11027 reject_bad_reg (Rn
);
11029 inst
.instruction
|= Rd
<< 8;
11030 inst
.instruction
|= Rn
<< 16;
11032 if (!inst
.operands
[2].isreg
)
11034 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11035 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11041 Rm
= inst
.operands
[2].reg
;
11042 reject_bad_reg (Rm
);
11044 constraint (inst
.operands
[2].shifted
11045 && inst
.operands
[2].immisreg
,
11046 _("shift must be constant"));
11047 encode_thumb32_shifted_operand (2);
11054 unsigned Rd
, Rn
, Rm
;
11056 Rd
= inst
.operands
[0].reg
;
11057 Rn
= inst
.operands
[1].reg
;
11058 Rm
= inst
.operands
[2].reg
;
11060 reject_bad_reg (Rd
);
11061 reject_bad_reg (Rn
);
11062 reject_bad_reg (Rm
);
11064 inst
.instruction
|= Rd
<< 8;
11065 inst
.instruction
|= Rn
<< 16;
11066 inst
.instruction
|= Rm
;
11067 if (inst
.operands
[3].present
)
11069 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11070 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11071 _("expression too complex"));
11072 inst
.instruction
|= (val
& 0x1c) << 10;
11073 inst
.instruction
|= (val
& 0x03) << 6;
11080 if (!inst
.operands
[3].present
)
11084 inst
.instruction
&= ~0x00000020;
11086 /* PR 10168. Swap the Rm and Rn registers. */
11087 Rtmp
= inst
.operands
[1].reg
;
11088 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11089 inst
.operands
[2].reg
= Rtmp
;
11097 if (inst
.operands
[0].immisreg
)
11098 reject_bad_reg (inst
.operands
[0].imm
);
11100 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11104 do_t_push_pop (void)
11108 constraint (inst
.operands
[0].writeback
,
11109 _("push/pop do not support {reglist}^"));
11110 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11111 _("expression too complex"));
11113 mask
= inst
.operands
[0].imm
;
11114 if ((mask
& ~0xff) == 0)
11115 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11116 else if ((inst
.instruction
== T_MNEM_push
11117 && (mask
& ~0xff) == 1 << REG_LR
)
11118 || (inst
.instruction
== T_MNEM_pop
11119 && (mask
& ~0xff) == 1 << REG_PC
))
11121 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11122 inst
.instruction
|= THUMB_PP_PC_LR
;
11123 inst
.instruction
|= mask
& 0xff;
11125 else if (unified_syntax
)
11127 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11128 encode_thumb2_ldmstm (13, mask
, TRUE
);
11132 inst
.error
= _("invalid register list to push/pop instruction");
11142 Rd
= inst
.operands
[0].reg
;
11143 Rm
= inst
.operands
[1].reg
;
11145 reject_bad_reg (Rd
);
11146 reject_bad_reg (Rm
);
11148 inst
.instruction
|= Rd
<< 8;
11149 inst
.instruction
|= Rm
<< 16;
11150 inst
.instruction
|= Rm
;
11158 Rd
= inst
.operands
[0].reg
;
11159 Rm
= inst
.operands
[1].reg
;
11161 reject_bad_reg (Rd
);
11162 reject_bad_reg (Rm
);
11164 if (Rd
<= 7 && Rm
<= 7
11165 && inst
.size_req
!= 4)
11167 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11168 inst
.instruction
|= Rd
;
11169 inst
.instruction
|= Rm
<< 3;
11171 else if (unified_syntax
)
11173 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11174 inst
.instruction
|= Rd
<< 8;
11175 inst
.instruction
|= Rm
<< 16;
11176 inst
.instruction
|= Rm
;
11179 inst
.error
= BAD_HIREG
;
11187 Rd
= inst
.operands
[0].reg
;
11188 Rm
= inst
.operands
[1].reg
;
11190 reject_bad_reg (Rd
);
11191 reject_bad_reg (Rm
);
11193 inst
.instruction
|= Rd
<< 8;
11194 inst
.instruction
|= Rm
;
11202 Rd
= inst
.operands
[0].reg
;
11203 Rs
= (inst
.operands
[1].present
11204 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11205 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11207 reject_bad_reg (Rd
);
11208 reject_bad_reg (Rs
);
11209 if (inst
.operands
[2].isreg
)
11210 reject_bad_reg (inst
.operands
[2].reg
);
11212 inst
.instruction
|= Rd
<< 8;
11213 inst
.instruction
|= Rs
<< 16;
11214 if (!inst
.operands
[2].isreg
)
11216 bfd_boolean narrow
;
11218 if ((inst
.instruction
& 0x00100000) != 0)
11219 narrow
= !in_it_block ();
11221 narrow
= in_it_block ();
11223 if (Rd
> 7 || Rs
> 7)
11226 if (inst
.size_req
== 4 || !unified_syntax
)
11229 if (inst
.reloc
.exp
.X_op
!= O_constant
11230 || inst
.reloc
.exp
.X_add_number
!= 0)
11233 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11234 relaxation, but it doesn't seem worth the hassle. */
11237 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11238 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11239 inst
.instruction
|= Rs
<< 3;
11240 inst
.instruction
|= Rd
;
11244 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11245 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11249 encode_thumb32_shifted_operand (2);
11255 set_it_insn_type (OUTSIDE_IT_INSN
);
11256 if (inst
.operands
[0].imm
)
11257 inst
.instruction
|= 0x8;
11263 if (!inst
.operands
[1].present
)
11264 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11266 if (unified_syntax
)
11268 bfd_boolean narrow
;
11271 switch (inst
.instruction
)
11274 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11276 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11278 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11280 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11284 if (THUMB_SETS_FLAGS (inst
.instruction
))
11285 narrow
= !in_it_block ();
11287 narrow
= in_it_block ();
11288 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11290 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11292 if (inst
.operands
[2].isreg
11293 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11294 || inst
.operands
[2].reg
> 7))
11296 if (inst
.size_req
== 4)
11299 reject_bad_reg (inst
.operands
[0].reg
);
11300 reject_bad_reg (inst
.operands
[1].reg
);
11304 if (inst
.operands
[2].isreg
)
11306 reject_bad_reg (inst
.operands
[2].reg
);
11307 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11308 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11309 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11310 inst
.instruction
|= inst
.operands
[2].reg
;
11314 inst
.operands
[1].shifted
= 1;
11315 inst
.operands
[1].shift_kind
= shift_kind
;
11316 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11317 ? T_MNEM_movs
: T_MNEM_mov
);
11318 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11319 encode_thumb32_shifted_operand (1);
11320 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11321 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11326 if (inst
.operands
[2].isreg
)
11328 switch (shift_kind
)
11330 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11331 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11332 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11333 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11337 inst
.instruction
|= inst
.operands
[0].reg
;
11338 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11342 switch (shift_kind
)
11344 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11345 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11346 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11349 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11350 inst
.instruction
|= inst
.operands
[0].reg
;
11351 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11357 constraint (inst
.operands
[0].reg
> 7
11358 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11359 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11361 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11363 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11364 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11365 _("source1 and dest must be same register"));
11367 switch (inst
.instruction
)
11369 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11370 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11371 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11372 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11376 inst
.instruction
|= inst
.operands
[0].reg
;
11377 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11381 switch (inst
.instruction
)
11383 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11384 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11385 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11386 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11389 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11390 inst
.instruction
|= inst
.operands
[0].reg
;
11391 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11399 unsigned Rd
, Rn
, Rm
;
11401 Rd
= inst
.operands
[0].reg
;
11402 Rn
= inst
.operands
[1].reg
;
11403 Rm
= inst
.operands
[2].reg
;
11405 reject_bad_reg (Rd
);
11406 reject_bad_reg (Rn
);
11407 reject_bad_reg (Rm
);
11409 inst
.instruction
|= Rd
<< 8;
11410 inst
.instruction
|= Rn
<< 16;
11411 inst
.instruction
|= Rm
;
11417 unsigned Rd
, Rn
, Rm
;
11419 Rd
= inst
.operands
[0].reg
;
11420 Rm
= inst
.operands
[1].reg
;
11421 Rn
= inst
.operands
[2].reg
;
11423 reject_bad_reg (Rd
);
11424 reject_bad_reg (Rn
);
11425 reject_bad_reg (Rm
);
11427 inst
.instruction
|= Rd
<< 8;
11428 inst
.instruction
|= Rn
<< 16;
11429 inst
.instruction
|= Rm
;
11435 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11436 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11437 _("SMC is not permitted on this architecture"));
11438 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11439 _("expression too complex"));
11440 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11441 inst
.instruction
|= (value
& 0xf000) >> 12;
11442 inst
.instruction
|= (value
& 0x0ff0);
11443 inst
.instruction
|= (value
& 0x000f) << 16;
11449 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11451 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11452 inst
.instruction
|= (value
& 0x0fff);
11453 inst
.instruction
|= (value
& 0xf000) << 4;
11457 do_t_ssat_usat (int bias
)
11461 Rd
= inst
.operands
[0].reg
;
11462 Rn
= inst
.operands
[2].reg
;
11464 reject_bad_reg (Rd
);
11465 reject_bad_reg (Rn
);
11467 inst
.instruction
|= Rd
<< 8;
11468 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11469 inst
.instruction
|= Rn
<< 16;
11471 if (inst
.operands
[3].present
)
11473 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11475 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11477 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11478 _("expression too complex"));
11480 if (shift_amount
!= 0)
11482 constraint (shift_amount
> 31,
11483 _("shift expression is too large"));
11485 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11486 inst
.instruction
|= 0x00200000; /* sh bit. */
11488 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11489 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11497 do_t_ssat_usat (1);
11505 Rd
= inst
.operands
[0].reg
;
11506 Rn
= inst
.operands
[2].reg
;
11508 reject_bad_reg (Rd
);
11509 reject_bad_reg (Rn
);
11511 inst
.instruction
|= Rd
<< 8;
11512 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11513 inst
.instruction
|= Rn
<< 16;
11519 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11520 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11521 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11522 || inst
.operands
[2].negative
,
11525 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11527 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11528 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11529 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11530 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11536 if (!inst
.operands
[2].present
)
11537 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11539 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11540 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11541 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11544 inst
.instruction
|= inst
.operands
[0].reg
;
11545 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11546 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11547 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11553 unsigned Rd
, Rn
, Rm
;
11555 Rd
= inst
.operands
[0].reg
;
11556 Rn
= inst
.operands
[1].reg
;
11557 Rm
= inst
.operands
[2].reg
;
11559 reject_bad_reg (Rd
);
11560 reject_bad_reg (Rn
);
11561 reject_bad_reg (Rm
);
11563 inst
.instruction
|= Rd
<< 8;
11564 inst
.instruction
|= Rn
<< 16;
11565 inst
.instruction
|= Rm
;
11566 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11574 Rd
= inst
.operands
[0].reg
;
11575 Rm
= inst
.operands
[1].reg
;
11577 reject_bad_reg (Rd
);
11578 reject_bad_reg (Rm
);
11580 if (inst
.instruction
<= 0xffff
11581 && inst
.size_req
!= 4
11582 && Rd
<= 7 && Rm
<= 7
11583 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11585 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11586 inst
.instruction
|= Rd
;
11587 inst
.instruction
|= Rm
<< 3;
11589 else if (unified_syntax
)
11591 if (inst
.instruction
<= 0xffff)
11592 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11593 inst
.instruction
|= Rd
<< 8;
11594 inst
.instruction
|= Rm
;
11595 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11599 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11600 _("Thumb encoding does not support rotation"));
11601 constraint (1, BAD_HIREG
);
11608 /* We have to do the following check manually as ARM_EXT_OS only applies
11610 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11612 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
))
11613 as_bad (_("SVC is not permitted on this architecture"));
11614 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11617 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11626 half
= (inst
.instruction
& 0x10) != 0;
11627 set_it_insn_type_last ();
11628 constraint (inst
.operands
[0].immisreg
,
11629 _("instruction requires register index"));
11631 Rn
= inst
.operands
[0].reg
;
11632 Rm
= inst
.operands
[0].imm
;
11634 constraint (Rn
== REG_SP
, BAD_SP
);
11635 reject_bad_reg (Rm
);
11637 constraint (!half
&& inst
.operands
[0].shifted
,
11638 _("instruction does not allow shifted index"));
11639 inst
.instruction
|= (Rn
<< 16) | Rm
;
11645 do_t_ssat_usat (0);
11653 Rd
= inst
.operands
[0].reg
;
11654 Rn
= inst
.operands
[2].reg
;
11656 reject_bad_reg (Rd
);
11657 reject_bad_reg (Rn
);
11659 inst
.instruction
|= Rd
<< 8;
11660 inst
.instruction
|= inst
.operands
[1].imm
;
11661 inst
.instruction
|= Rn
<< 16;
11664 /* Neon instruction encoder helpers. */
11666 /* Encodings for the different types for various Neon opcodes. */
11668 /* An "invalid" code for the following tables. */
11671 struct neon_tab_entry
11674 unsigned float_or_poly
;
11675 unsigned scalar_or_imm
;
11678 /* Map overloaded Neon opcodes to their respective encodings. */
11679 #define NEON_ENC_TAB \
11680 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11681 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11682 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11683 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11684 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11685 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11686 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11687 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11688 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11689 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11690 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11691 /* Register variants of the following two instructions are encoded as
11692 vcge / vcgt with the operands reversed. */ \
11693 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11694 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11695 X(vfma, N_INV, 0x0000c10, N_INV), \
11696 X(vfms, N_INV, 0x0200c10, N_INV), \
11697 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11698 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11699 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11700 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11701 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11702 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11703 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11704 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11705 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11706 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11707 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11708 X(vshl, 0x0000400, N_INV, 0x0800510), \
11709 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11710 X(vand, 0x0000110, N_INV, 0x0800030), \
11711 X(vbic, 0x0100110, N_INV, 0x0800030), \
11712 X(veor, 0x1000110, N_INV, N_INV), \
11713 X(vorn, 0x0300110, N_INV, 0x0800010), \
11714 X(vorr, 0x0200110, N_INV, 0x0800010), \
11715 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11716 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11717 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11718 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11719 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11720 X(vst1, 0x0000000, 0x0800000, N_INV), \
11721 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11722 X(vst2, 0x0000100, 0x0800100, N_INV), \
11723 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11724 X(vst3, 0x0000200, 0x0800200, N_INV), \
11725 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11726 X(vst4, 0x0000300, 0x0800300, N_INV), \
11727 X(vmovn, 0x1b20200, N_INV, N_INV), \
11728 X(vtrn, 0x1b20080, N_INV, N_INV), \
11729 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11730 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11731 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11732 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11733 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11734 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11735 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11736 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11737 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11738 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11739 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11743 #define X(OPC,I,F,S) N_MNEM_##OPC
11748 static const struct neon_tab_entry neon_enc_tab
[] =
11750 #define X(OPC,I,F,S) { (I), (F), (S) }
11755 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11756 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11757 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11758 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11759 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11760 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11761 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11762 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11763 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11764 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11765 #define NEON_ENC_SINGLE_(X) \
11766 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11767 #define NEON_ENC_DOUBLE_(X) \
11768 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11770 #define NEON_ENCODE(type, inst) \
11773 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11774 inst.is_neon = 1; \
11778 #define check_neon_suffixes \
11781 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11783 as_bad (_("invalid neon suffix for non neon instruction")); \
11789 /* Define shapes for instruction operands. The following mnemonic characters
11790 are used in this table:
11792 F - VFP S<n> register
11793 D - Neon D<n> register
11794 Q - Neon Q<n> register
11798 L - D<n> register list
11800 This table is used to generate various data:
11801 - enumerations of the form NS_DDR to be used as arguments to
11803 - a table classifying shapes into single, double, quad, mixed.
11804 - a table used to drive neon_select_shape. */
11806 #define NEON_SHAPE_DEF \
11807 X(3, (D, D, D), DOUBLE), \
11808 X(3, (Q, Q, Q), QUAD), \
11809 X(3, (D, D, I), DOUBLE), \
11810 X(3, (Q, Q, I), QUAD), \
11811 X(3, (D, D, S), DOUBLE), \
11812 X(3, (Q, Q, S), QUAD), \
11813 X(2, (D, D), DOUBLE), \
11814 X(2, (Q, Q), QUAD), \
11815 X(2, (D, S), DOUBLE), \
11816 X(2, (Q, S), QUAD), \
11817 X(2, (D, R), DOUBLE), \
11818 X(2, (Q, R), QUAD), \
11819 X(2, (D, I), DOUBLE), \
11820 X(2, (Q, I), QUAD), \
11821 X(3, (D, L, D), DOUBLE), \
11822 X(2, (D, Q), MIXED), \
11823 X(2, (Q, D), MIXED), \
11824 X(3, (D, Q, I), MIXED), \
11825 X(3, (Q, D, I), MIXED), \
11826 X(3, (Q, D, D), MIXED), \
11827 X(3, (D, Q, Q), MIXED), \
11828 X(3, (Q, Q, D), MIXED), \
11829 X(3, (Q, D, S), MIXED), \
11830 X(3, (D, Q, S), MIXED), \
11831 X(4, (D, D, D, I), DOUBLE), \
11832 X(4, (Q, Q, Q, I), QUAD), \
11833 X(2, (F, F), SINGLE), \
11834 X(3, (F, F, F), SINGLE), \
11835 X(2, (F, I), SINGLE), \
11836 X(2, (F, D), MIXED), \
11837 X(2, (D, F), MIXED), \
11838 X(3, (F, F, I), MIXED), \
11839 X(4, (R, R, F, F), SINGLE), \
11840 X(4, (F, F, R, R), SINGLE), \
11841 X(3, (D, R, R), DOUBLE), \
11842 X(3, (R, R, D), DOUBLE), \
11843 X(2, (S, R), SINGLE), \
11844 X(2, (R, S), SINGLE), \
11845 X(2, (F, R), SINGLE), \
11846 X(2, (R, F), SINGLE)
11848 #define S2(A,B) NS_##A##B
11849 #define S3(A,B,C) NS_##A##B##C
11850 #define S4(A,B,C,D) NS_##A##B##C##D
11852 #define X(N, L, C) S##N L
11865 enum neon_shape_class
11873 #define X(N, L, C) SC_##C
11875 static enum neon_shape_class neon_shape_class
[] =
11893 /* Register widths of above. */
11894 static unsigned neon_shape_el_size
[] =
11905 struct neon_shape_info
11908 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11911 #define S2(A,B) { SE_##A, SE_##B }
11912 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11913 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11915 #define X(N, L, C) { N, S##N L }
11917 static struct neon_shape_info neon_shape_tab
[] =
11927 /* Bit masks used in type checking given instructions.
11928 'N_EQK' means the type must be the same as (or based on in some way) the key
11929 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11930 set, various other bits can be set as well in order to modify the meaning of
11931 the type constraint. */
11933 enum neon_type_mask
11956 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11957 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11958 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11959 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11960 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11961 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11962 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11963 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11964 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11965 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11967 N_MAX_NONSPECIAL
= N_F64
11970 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11972 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11973 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11974 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11975 #define N_SUF_32 (N_SU_32 | N_F32)
11976 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11977 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11979 /* Pass this as the first type argument to neon_check_type to ignore types
11981 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11983 /* Select a "shape" for the current instruction (describing register types or
11984 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11985 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11986 function of operand parsing, so this function doesn't need to be called.
11987 Shapes should be listed in order of decreasing length. */
11989 static enum neon_shape
11990 neon_select_shape (enum neon_shape shape
, ...)
11993 enum neon_shape first_shape
= shape
;
11995 /* Fix missing optional operands. FIXME: we don't know at this point how
11996 many arguments we should have, so this makes the assumption that we have
11997 > 1. This is true of all current Neon opcodes, I think, but may not be
11998 true in the future. */
11999 if (!inst
.operands
[1].present
)
12000 inst
.operands
[1] = inst
.operands
[0];
12002 va_start (ap
, shape
);
12004 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12009 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12011 if (!inst
.operands
[j
].present
)
12017 switch (neon_shape_tab
[shape
].el
[j
])
12020 if (!(inst
.operands
[j
].isreg
12021 && inst
.operands
[j
].isvec
12022 && inst
.operands
[j
].issingle
12023 && !inst
.operands
[j
].isquad
))
12028 if (!(inst
.operands
[j
].isreg
12029 && inst
.operands
[j
].isvec
12030 && !inst
.operands
[j
].isquad
12031 && !inst
.operands
[j
].issingle
))
12036 if (!(inst
.operands
[j
].isreg
12037 && !inst
.operands
[j
].isvec
))
12042 if (!(inst
.operands
[j
].isreg
12043 && inst
.operands
[j
].isvec
12044 && inst
.operands
[j
].isquad
12045 && !inst
.operands
[j
].issingle
))
12050 if (!(!inst
.operands
[j
].isreg
12051 && !inst
.operands
[j
].isscalar
))
12056 if (!(!inst
.operands
[j
].isreg
12057 && inst
.operands
[j
].isscalar
))
12073 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12074 first_error (_("invalid instruction shape"));
12079 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12080 means the Q bit should be set). */
12083 neon_quad (enum neon_shape shape
)
12085 return neon_shape_class
[shape
] == SC_QUAD
;
12089 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12092 /* Allow modification to be made to types which are constrained to be
12093 based on the key element, based on bits set alongside N_EQK. */
12094 if ((typebits
& N_EQK
) != 0)
12096 if ((typebits
& N_HLF
) != 0)
12098 else if ((typebits
& N_DBL
) != 0)
12100 if ((typebits
& N_SGN
) != 0)
12101 *g_type
= NT_signed
;
12102 else if ((typebits
& N_UNS
) != 0)
12103 *g_type
= NT_unsigned
;
12104 else if ((typebits
& N_INT
) != 0)
12105 *g_type
= NT_integer
;
12106 else if ((typebits
& N_FLT
) != 0)
12107 *g_type
= NT_float
;
12108 else if ((typebits
& N_SIZ
) != 0)
12109 *g_type
= NT_untyped
;
12113 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12114 operand type, i.e. the single type specified in a Neon instruction when it
12115 is the only one given. */
12117 static struct neon_type_el
12118 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12120 struct neon_type_el dest
= *key
;
12122 gas_assert ((thisarg
& N_EQK
) != 0);
12124 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12129 /* Convert Neon type and size into compact bitmask representation. */
12131 static enum neon_type_mask
12132 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12139 case 8: return N_8
;
12140 case 16: return N_16
;
12141 case 32: return N_32
;
12142 case 64: return N_64
;
12150 case 8: return N_I8
;
12151 case 16: return N_I16
;
12152 case 32: return N_I32
;
12153 case 64: return N_I64
;
12161 case 16: return N_F16
;
12162 case 32: return N_F32
;
12163 case 64: return N_F64
;
12171 case 8: return N_P8
;
12172 case 16: return N_P16
;
12180 case 8: return N_S8
;
12181 case 16: return N_S16
;
12182 case 32: return N_S32
;
12183 case 64: return N_S64
;
12191 case 8: return N_U8
;
12192 case 16: return N_U16
;
12193 case 32: return N_U32
;
12194 case 64: return N_U64
;
12205 /* Convert compact Neon bitmask type representation to a type and size. Only
12206 handles the case where a single bit is set in the mask. */
12209 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12210 enum neon_type_mask mask
)
12212 if ((mask
& N_EQK
) != 0)
12215 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12217 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12219 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12221 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12226 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12228 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12229 *type
= NT_unsigned
;
12230 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12231 *type
= NT_integer
;
12232 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12233 *type
= NT_untyped
;
12234 else if ((mask
& (N_P8
| N_P16
)) != 0)
12236 else if ((mask
& (N_F32
| N_F64
)) != 0)
12244 /* Modify a bitmask of allowed types. This is only needed for type
12248 modify_types_allowed (unsigned allowed
, unsigned mods
)
12251 enum neon_el_type type
;
12257 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12259 if (el_type_of_type_chk (&type
, &size
,
12260 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12262 neon_modify_type_size (mods
, &type
, &size
);
12263 destmask
|= type_chk_of_el_type (type
, size
);
12270 /* Check type and return type classification.
12271 The manual states (paraphrase): If one datatype is given, it indicates the
12273 - the second operand, if there is one
12274 - the operand, if there is no second operand
12275 - the result, if there are no operands.
12276 This isn't quite good enough though, so we use a concept of a "key" datatype
12277 which is set on a per-instruction basis, which is the one which matters when
12278 only one data type is written.
12279 Note: this function has side-effects (e.g. filling in missing operands). All
12280 Neon instructions should call it before performing bit encoding. */
12282 static struct neon_type_el
12283 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12286 unsigned i
, pass
, key_el
= 0;
12287 unsigned types
[NEON_MAX_TYPE_ELS
];
12288 enum neon_el_type k_type
= NT_invtype
;
12289 unsigned k_size
= -1u;
12290 struct neon_type_el badtype
= {NT_invtype
, -1};
12291 unsigned key_allowed
= 0;
12293 /* Optional registers in Neon instructions are always (not) in operand 1.
12294 Fill in the missing operand here, if it was omitted. */
12295 if (els
> 1 && !inst
.operands
[1].present
)
12296 inst
.operands
[1] = inst
.operands
[0];
12298 /* Suck up all the varargs. */
12300 for (i
= 0; i
< els
; i
++)
12302 unsigned thisarg
= va_arg (ap
, unsigned);
12303 if (thisarg
== N_IGNORE_TYPE
)
12308 types
[i
] = thisarg
;
12309 if ((thisarg
& N_KEY
) != 0)
12314 if (inst
.vectype
.elems
> 0)
12315 for (i
= 0; i
< els
; i
++)
12316 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12318 first_error (_("types specified in both the mnemonic and operands"));
12322 /* Duplicate inst.vectype elements here as necessary.
12323 FIXME: No idea if this is exactly the same as the ARM assembler,
12324 particularly when an insn takes one register and one non-register
12326 if (inst
.vectype
.elems
== 1 && els
> 1)
12329 inst
.vectype
.elems
= els
;
12330 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12331 for (j
= 0; j
< els
; j
++)
12333 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12336 else if (inst
.vectype
.elems
== 0 && els
> 0)
12339 /* No types were given after the mnemonic, so look for types specified
12340 after each operand. We allow some flexibility here; as long as the
12341 "key" operand has a type, we can infer the others. */
12342 for (j
= 0; j
< els
; j
++)
12343 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12344 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12346 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12348 for (j
= 0; j
< els
; j
++)
12349 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12350 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12355 first_error (_("operand types can't be inferred"));
12359 else if (inst
.vectype
.elems
!= els
)
12361 first_error (_("type specifier has the wrong number of parts"));
12365 for (pass
= 0; pass
< 2; pass
++)
12367 for (i
= 0; i
< els
; i
++)
12369 unsigned thisarg
= types
[i
];
12370 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12371 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12372 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12373 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12375 /* Decay more-specific signed & unsigned types to sign-insensitive
12376 integer types if sign-specific variants are unavailable. */
12377 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12378 && (types_allowed
& N_SU_ALL
) == 0)
12379 g_type
= NT_integer
;
12381 /* If only untyped args are allowed, decay any more specific types to
12382 them. Some instructions only care about signs for some element
12383 sizes, so handle that properly. */
12384 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12385 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12386 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12387 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12388 g_type
= NT_untyped
;
12392 if ((thisarg
& N_KEY
) != 0)
12396 key_allowed
= thisarg
& ~N_KEY
;
12401 if ((thisarg
& N_VFP
) != 0)
12403 enum neon_shape_el regshape
;
12404 unsigned regwidth
, match
;
12406 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12409 first_error (_("invalid instruction shape"));
12412 regshape
= neon_shape_tab
[ns
].el
[i
];
12413 regwidth
= neon_shape_el_size
[regshape
];
12415 /* In VFP mode, operands must match register widths. If we
12416 have a key operand, use its width, else use the width of
12417 the current operand. */
12423 if (regwidth
!= match
)
12425 first_error (_("operand size must match register width"));
12430 if ((thisarg
& N_EQK
) == 0)
12432 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12434 if ((given_type
& types_allowed
) == 0)
12436 first_error (_("bad type in Neon instruction"));
12442 enum neon_el_type mod_k_type
= k_type
;
12443 unsigned mod_k_size
= k_size
;
12444 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12445 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12447 first_error (_("inconsistent types in Neon instruction"));
12455 return inst
.vectype
.el
[key_el
];
12458 /* Neon-style VFP instruction forwarding. */
12460 /* Thumb VFP instructions have 0xE in the condition field. */
12463 do_vfp_cond_or_thumb (void)
12468 inst
.instruction
|= 0xe0000000;
12470 inst
.instruction
|= inst
.cond
<< 28;
12473 /* Look up and encode a simple mnemonic, for use as a helper function for the
12474 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12475 etc. It is assumed that operand parsing has already been done, and that the
12476 operands are in the form expected by the given opcode (this isn't necessarily
12477 the same as the form in which they were parsed, hence some massaging must
12478 take place before this function is called).
12479 Checks current arch version against that in the looked-up opcode. */
12482 do_vfp_nsyn_opcode (const char *opname
)
12484 const struct asm_opcode
*opcode
;
12486 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12491 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12492 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12499 inst
.instruction
= opcode
->tvalue
;
12500 opcode
->tencode ();
12504 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12505 opcode
->aencode ();
12510 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12512 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12517 do_vfp_nsyn_opcode ("fadds");
12519 do_vfp_nsyn_opcode ("fsubs");
12524 do_vfp_nsyn_opcode ("faddd");
12526 do_vfp_nsyn_opcode ("fsubd");
12530 /* Check operand types to see if this is a VFP instruction, and if so call
12534 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12536 enum neon_shape rs
;
12537 struct neon_type_el et
;
12542 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12543 et
= neon_check_type (2, rs
,
12544 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12548 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12549 et
= neon_check_type (3, rs
,
12550 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12557 if (et
.type
!= NT_invtype
)
12568 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12570 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12575 do_vfp_nsyn_opcode ("fmacs");
12577 do_vfp_nsyn_opcode ("fnmacs");
12582 do_vfp_nsyn_opcode ("fmacd");
12584 do_vfp_nsyn_opcode ("fnmacd");
12589 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12591 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12596 do_vfp_nsyn_opcode ("ffmas");
12598 do_vfp_nsyn_opcode ("ffnmas");
12603 do_vfp_nsyn_opcode ("ffmad");
12605 do_vfp_nsyn_opcode ("ffnmad");
12610 do_vfp_nsyn_mul (enum neon_shape rs
)
12613 do_vfp_nsyn_opcode ("fmuls");
12615 do_vfp_nsyn_opcode ("fmuld");
12619 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12621 int is_neg
= (inst
.instruction
& 0x80) != 0;
12622 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12627 do_vfp_nsyn_opcode ("fnegs");
12629 do_vfp_nsyn_opcode ("fabss");
12634 do_vfp_nsyn_opcode ("fnegd");
12636 do_vfp_nsyn_opcode ("fabsd");
12640 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12641 insns belong to Neon, and are handled elsewhere. */
12644 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12646 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12650 do_vfp_nsyn_opcode ("fldmdbs");
12652 do_vfp_nsyn_opcode ("fldmias");
12657 do_vfp_nsyn_opcode ("fstmdbs");
12659 do_vfp_nsyn_opcode ("fstmias");
12664 do_vfp_nsyn_sqrt (void)
12666 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12667 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12670 do_vfp_nsyn_opcode ("fsqrts");
12672 do_vfp_nsyn_opcode ("fsqrtd");
12676 do_vfp_nsyn_div (void)
12678 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12679 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12680 N_F32
| N_F64
| N_KEY
| N_VFP
);
12683 do_vfp_nsyn_opcode ("fdivs");
12685 do_vfp_nsyn_opcode ("fdivd");
12689 do_vfp_nsyn_nmul (void)
12691 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12692 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12693 N_F32
| N_F64
| N_KEY
| N_VFP
);
12697 NEON_ENCODE (SINGLE
, inst
);
12698 do_vfp_sp_dyadic ();
12702 NEON_ENCODE (DOUBLE
, inst
);
12703 do_vfp_dp_rd_rn_rm ();
12705 do_vfp_cond_or_thumb ();
12709 do_vfp_nsyn_cmp (void)
12711 if (inst
.operands
[1].isreg
)
12713 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12714 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12718 NEON_ENCODE (SINGLE
, inst
);
12719 do_vfp_sp_monadic ();
12723 NEON_ENCODE (DOUBLE
, inst
);
12724 do_vfp_dp_rd_rm ();
12729 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12730 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12732 switch (inst
.instruction
& 0x0fffffff)
12735 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12738 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12746 NEON_ENCODE (SINGLE
, inst
);
12747 do_vfp_sp_compare_z ();
12751 NEON_ENCODE (DOUBLE
, inst
);
12755 do_vfp_cond_or_thumb ();
12759 nsyn_insert_sp (void)
12761 inst
.operands
[1] = inst
.operands
[0];
12762 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12763 inst
.operands
[0].reg
= REG_SP
;
12764 inst
.operands
[0].isreg
= 1;
12765 inst
.operands
[0].writeback
= 1;
12766 inst
.operands
[0].present
= 1;
12770 do_vfp_nsyn_push (void)
12773 if (inst
.operands
[1].issingle
)
12774 do_vfp_nsyn_opcode ("fstmdbs");
12776 do_vfp_nsyn_opcode ("fstmdbd");
12780 do_vfp_nsyn_pop (void)
12783 if (inst
.operands
[1].issingle
)
12784 do_vfp_nsyn_opcode ("fldmias");
12786 do_vfp_nsyn_opcode ("fldmiad");
12789 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12790 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12793 neon_dp_fixup (struct arm_it
* insn
)
12795 unsigned int i
= insn
->instruction
;
12800 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12811 insn
->instruction
= i
;
12814 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12818 neon_logbits (unsigned x
)
12820 return ffs (x
) - 4;
12823 #define LOW4(R) ((R) & 0xf)
12824 #define HI1(R) (((R) >> 4) & 1)
12826 /* Encode insns with bit pattern:
12828 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12829 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12831 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12832 different meaning for some instruction. */
12835 neon_three_same (int isquad
, int ubit
, int size
)
12837 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12838 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12839 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12840 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12841 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12842 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12843 inst
.instruction
|= (isquad
!= 0) << 6;
12844 inst
.instruction
|= (ubit
!= 0) << 24;
12846 inst
.instruction
|= neon_logbits (size
) << 20;
12848 neon_dp_fixup (&inst
);
12851 /* Encode instructions of the form:
12853 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12854 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12856 Don't write size if SIZE == -1. */
12859 neon_two_same (int qbit
, int ubit
, int size
)
12861 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12862 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12863 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12864 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12865 inst
.instruction
|= (qbit
!= 0) << 6;
12866 inst
.instruction
|= (ubit
!= 0) << 24;
12869 inst
.instruction
|= neon_logbits (size
) << 18;
12871 neon_dp_fixup (&inst
);
12874 /* Neon instruction encoders, in approximate order of appearance. */
12877 do_neon_dyadic_i_su (void)
12879 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12880 struct neon_type_el et
= neon_check_type (3, rs
,
12881 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12882 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12886 do_neon_dyadic_i64_su (void)
12888 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12889 struct neon_type_el et
= neon_check_type (3, rs
,
12890 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12891 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12895 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12898 unsigned size
= et
.size
>> 3;
12899 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12900 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12901 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12902 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12903 inst
.instruction
|= (isquad
!= 0) << 6;
12904 inst
.instruction
|= immbits
<< 16;
12905 inst
.instruction
|= (size
>> 3) << 7;
12906 inst
.instruction
|= (size
& 0x7) << 19;
12908 inst
.instruction
|= (uval
!= 0) << 24;
12910 neon_dp_fixup (&inst
);
12914 do_neon_shl_imm (void)
12916 if (!inst
.operands
[2].isreg
)
12918 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12919 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12920 NEON_ENCODE (IMMED
, inst
);
12921 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12925 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12926 struct neon_type_el et
= neon_check_type (3, rs
,
12927 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12930 /* VSHL/VQSHL 3-register variants have syntax such as:
12932 whereas other 3-register operations encoded by neon_three_same have
12935 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12937 tmp
= inst
.operands
[2].reg
;
12938 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12939 inst
.operands
[1].reg
= tmp
;
12940 NEON_ENCODE (INTEGER
, inst
);
12941 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12946 do_neon_qshl_imm (void)
12948 if (!inst
.operands
[2].isreg
)
12950 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12951 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12953 NEON_ENCODE (IMMED
, inst
);
12954 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12955 inst
.operands
[2].imm
);
12959 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12960 struct neon_type_el et
= neon_check_type (3, rs
,
12961 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12964 /* See note in do_neon_shl_imm. */
12965 tmp
= inst
.operands
[2].reg
;
12966 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12967 inst
.operands
[1].reg
= tmp
;
12968 NEON_ENCODE (INTEGER
, inst
);
12969 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12974 do_neon_rshl (void)
12976 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12977 struct neon_type_el et
= neon_check_type (3, rs
,
12978 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12981 tmp
= inst
.operands
[2].reg
;
12982 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12983 inst
.operands
[1].reg
= tmp
;
12984 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12988 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12990 /* Handle .I8 pseudo-instructions. */
12993 /* Unfortunately, this will make everything apart from zero out-of-range.
12994 FIXME is this the intended semantics? There doesn't seem much point in
12995 accepting .I8 if so. */
12996 immediate
|= immediate
<< 8;
13002 if (immediate
== (immediate
& 0x000000ff))
13004 *immbits
= immediate
;
13007 else if (immediate
== (immediate
& 0x0000ff00))
13009 *immbits
= immediate
>> 8;
13012 else if (immediate
== (immediate
& 0x00ff0000))
13014 *immbits
= immediate
>> 16;
13017 else if (immediate
== (immediate
& 0xff000000))
13019 *immbits
= immediate
>> 24;
13022 if ((immediate
& 0xffff) != (immediate
>> 16))
13023 goto bad_immediate
;
13024 immediate
&= 0xffff;
13027 if (immediate
== (immediate
& 0x000000ff))
13029 *immbits
= immediate
;
13032 else if (immediate
== (immediate
& 0x0000ff00))
13034 *immbits
= immediate
>> 8;
13039 first_error (_("immediate value out of range"));
13043 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13047 neon_bits_same_in_bytes (unsigned imm
)
13049 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13050 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13051 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13052 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13055 /* For immediate of above form, return 0bABCD. */
13058 neon_squash_bits (unsigned imm
)
13060 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13061 | ((imm
& 0x01000000) >> 21);
13064 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13067 neon_qfloat_bits (unsigned imm
)
13069 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13072 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13073 the instruction. *OP is passed as the initial value of the op field, and
13074 may be set to a different value depending on the constant (i.e.
13075 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13076 MVN). If the immediate looks like a repeated pattern then also
13077 try smaller element sizes. */
13080 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13081 unsigned *immbits
, int *op
, int size
,
13082 enum neon_el_type type
)
13084 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13086 if (type
== NT_float
&& !float_p
)
13089 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13091 if (size
!= 32 || *op
== 1)
13093 *immbits
= neon_qfloat_bits (immlo
);
13099 if (neon_bits_same_in_bytes (immhi
)
13100 && neon_bits_same_in_bytes (immlo
))
13104 *immbits
= (neon_squash_bits (immhi
) << 4)
13105 | neon_squash_bits (immlo
);
13110 if (immhi
!= immlo
)
13116 if (immlo
== (immlo
& 0x000000ff))
13121 else if (immlo
== (immlo
& 0x0000ff00))
13123 *immbits
= immlo
>> 8;
13126 else if (immlo
== (immlo
& 0x00ff0000))
13128 *immbits
= immlo
>> 16;
13131 else if (immlo
== (immlo
& 0xff000000))
13133 *immbits
= immlo
>> 24;
13136 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13138 *immbits
= (immlo
>> 8) & 0xff;
13141 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13143 *immbits
= (immlo
>> 16) & 0xff;
13147 if ((immlo
& 0xffff) != (immlo
>> 16))
13154 if (immlo
== (immlo
& 0x000000ff))
13159 else if (immlo
== (immlo
& 0x0000ff00))
13161 *immbits
= immlo
>> 8;
13165 if ((immlo
& 0xff) != (immlo
>> 8))
13170 if (immlo
== (immlo
& 0x000000ff))
13172 /* Don't allow MVN with 8-bit immediate. */
13182 /* Write immediate bits [7:0] to the following locations:
13184 |28/24|23 19|18 16|15 4|3 0|
13185 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13187 This function is used by VMOV/VMVN/VORR/VBIC. */
13190 neon_write_immbits (unsigned immbits
)
13192 inst
.instruction
|= immbits
& 0xf;
13193 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13194 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13197 /* Invert low-order SIZE bits of XHI:XLO. */
13200 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13202 unsigned immlo
= xlo
? *xlo
: 0;
13203 unsigned immhi
= xhi
? *xhi
: 0;
13208 immlo
= (~immlo
) & 0xff;
13212 immlo
= (~immlo
) & 0xffff;
13216 immhi
= (~immhi
) & 0xffffffff;
13217 /* fall through. */
13220 immlo
= (~immlo
) & 0xffffffff;
13235 do_neon_logic (void)
13237 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13239 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13240 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13241 /* U bit and size field were set as part of the bitmask. */
13242 NEON_ENCODE (INTEGER
, inst
);
13243 neon_three_same (neon_quad (rs
), 0, -1);
13247 const int three_ops_form
= (inst
.operands
[2].present
13248 && !inst
.operands
[2].isreg
);
13249 const int immoperand
= (three_ops_form
? 2 : 1);
13250 enum neon_shape rs
= (three_ops_form
13251 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13252 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13253 struct neon_type_el et
= neon_check_type (2, rs
,
13254 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13255 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13259 if (et
.type
== NT_invtype
)
13262 if (three_ops_form
)
13263 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13264 _("first and second operands shall be the same register"));
13266 NEON_ENCODE (IMMED
, inst
);
13268 immbits
= inst
.operands
[immoperand
].imm
;
13271 /* .i64 is a pseudo-op, so the immediate must be a repeating
13273 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13274 inst
.operands
[immoperand
].reg
: 0))
13276 /* Set immbits to an invalid constant. */
13277 immbits
= 0xdeadbeef;
13284 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13288 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13292 /* Pseudo-instruction for VBIC. */
13293 neon_invert_size (&immbits
, 0, et
.size
);
13294 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13298 /* Pseudo-instruction for VORR. */
13299 neon_invert_size (&immbits
, 0, et
.size
);
13300 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13310 inst
.instruction
|= neon_quad (rs
) << 6;
13311 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13312 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13313 inst
.instruction
|= cmode
<< 8;
13314 neon_write_immbits (immbits
);
13316 neon_dp_fixup (&inst
);
13321 do_neon_bitfield (void)
13323 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13324 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13325 neon_three_same (neon_quad (rs
), 0, -1);
13329 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13332 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13333 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13335 if (et
.type
== NT_float
)
13337 NEON_ENCODE (FLOAT
, inst
);
13338 neon_three_same (neon_quad (rs
), 0, -1);
13342 NEON_ENCODE (INTEGER
, inst
);
13343 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13348 do_neon_dyadic_if_su (void)
13350 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13354 do_neon_dyadic_if_su_d (void)
13356 /* This version only allow D registers, but that constraint is enforced during
13357 operand parsing so we don't need to do anything extra here. */
13358 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13362 do_neon_dyadic_if_i_d (void)
13364 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13365 affected if we specify unsigned args. */
13366 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13369 enum vfp_or_neon_is_neon_bits
13372 NEON_CHECK_ARCH
= 2
13375 /* Call this function if an instruction which may have belonged to the VFP or
13376 Neon instruction sets, but turned out to be a Neon instruction (due to the
13377 operand types involved, etc.). We have to check and/or fix-up a couple of
13380 - Make sure the user hasn't attempted to make a Neon instruction
13382 - Alter the value in the condition code field if necessary.
13383 - Make sure that the arch supports Neon instructions.
13385 Which of these operations take place depends on bits from enum
13386 vfp_or_neon_is_neon_bits.
13388 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13389 current instruction's condition is COND_ALWAYS, the condition field is
13390 changed to inst.uncond_value. This is necessary because instructions shared
13391 between VFP and Neon may be conditional for the VFP variants only, and the
13392 unconditional Neon version must have, e.g., 0xF in the condition field. */
13395 vfp_or_neon_is_neon (unsigned check
)
13397 /* Conditions are always legal in Thumb mode (IT blocks). */
13398 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13400 if (inst
.cond
!= COND_ALWAYS
)
13402 first_error (_(BAD_COND
));
13405 if (inst
.uncond_value
!= -1)
13406 inst
.instruction
|= inst
.uncond_value
<< 28;
13409 if ((check
& NEON_CHECK_ARCH
)
13410 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13412 first_error (_(BAD_FPU
));
13420 do_neon_addsub_if_i (void)
13422 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13425 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13428 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13429 affected if we specify unsigned args. */
13430 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13433 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13435 V<op> A,B (A is operand 0, B is operand 2)
13440 so handle that case specially. */
13443 neon_exchange_operands (void)
13445 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13446 if (inst
.operands
[1].present
)
13448 /* Swap operands[1] and operands[2]. */
13449 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13450 inst
.operands
[1] = inst
.operands
[2];
13451 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13455 inst
.operands
[1] = inst
.operands
[2];
13456 inst
.operands
[2] = inst
.operands
[0];
13461 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13463 if (inst
.operands
[2].isreg
)
13466 neon_exchange_operands ();
13467 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13471 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13472 struct neon_type_el et
= neon_check_type (2, rs
,
13473 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13475 NEON_ENCODE (IMMED
, inst
);
13476 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13477 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13478 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13479 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13480 inst
.instruction
|= neon_quad (rs
) << 6;
13481 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13482 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13484 neon_dp_fixup (&inst
);
13491 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13495 do_neon_cmp_inv (void)
13497 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13503 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13506 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13507 scalars, which are encoded in 5 bits, M : Rm.
13508 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13509 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13513 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13515 unsigned regno
= NEON_SCALAR_REG (scalar
);
13516 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13521 if (regno
> 7 || elno
> 3)
13523 return regno
| (elno
<< 3);
13526 if (regno
> 15 || elno
> 1)
13528 return regno
| (elno
<< 4);
13532 first_error (_("scalar out of range for multiply instruction"));
13538 /* Encode multiply / multiply-accumulate scalar instructions. */
13541 neon_mul_mac (struct neon_type_el et
, int ubit
)
13545 /* Give a more helpful error message if we have an invalid type. */
13546 if (et
.type
== NT_invtype
)
13549 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13550 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13551 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13552 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13553 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13554 inst
.instruction
|= LOW4 (scalar
);
13555 inst
.instruction
|= HI1 (scalar
) << 5;
13556 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13557 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13558 inst
.instruction
|= (ubit
!= 0) << 24;
13560 neon_dp_fixup (&inst
);
13564 do_neon_mac_maybe_scalar (void)
13566 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13569 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13572 if (inst
.operands
[2].isscalar
)
13574 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13575 struct neon_type_el et
= neon_check_type (3, rs
,
13576 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13577 NEON_ENCODE (SCALAR
, inst
);
13578 neon_mul_mac (et
, neon_quad (rs
));
13582 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13583 affected if we specify unsigned args. */
13584 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13589 do_neon_fmac (void)
13591 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13594 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13597 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13603 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13604 struct neon_type_el et
= neon_check_type (3, rs
,
13605 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13606 neon_three_same (neon_quad (rs
), 0, et
.size
);
13609 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13610 same types as the MAC equivalents. The polynomial type for this instruction
13611 is encoded the same as the integer type. */
13616 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13619 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13622 if (inst
.operands
[2].isscalar
)
13623 do_neon_mac_maybe_scalar ();
13625 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13629 do_neon_qdmulh (void)
13631 if (inst
.operands
[2].isscalar
)
13633 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13634 struct neon_type_el et
= neon_check_type (3, rs
,
13635 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13636 NEON_ENCODE (SCALAR
, inst
);
13637 neon_mul_mac (et
, neon_quad (rs
));
13641 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13642 struct neon_type_el et
= neon_check_type (3, rs
,
13643 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13644 NEON_ENCODE (INTEGER
, inst
);
13645 /* The U bit (rounding) comes from bit mask. */
13646 neon_three_same (neon_quad (rs
), 0, et
.size
);
13651 do_neon_fcmp_absolute (void)
13653 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13654 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13655 /* Size field comes from bit mask. */
13656 neon_three_same (neon_quad (rs
), 1, -1);
13660 do_neon_fcmp_absolute_inv (void)
13662 neon_exchange_operands ();
13663 do_neon_fcmp_absolute ();
13667 do_neon_step (void)
13669 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13670 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13671 neon_three_same (neon_quad (rs
), 0, -1);
13675 do_neon_abs_neg (void)
13677 enum neon_shape rs
;
13678 struct neon_type_el et
;
13680 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13683 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13686 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13687 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13689 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13690 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13691 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13692 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13693 inst
.instruction
|= neon_quad (rs
) << 6;
13694 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13695 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13697 neon_dp_fixup (&inst
);
13703 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13704 struct neon_type_el et
= neon_check_type (2, rs
,
13705 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13706 int imm
= inst
.operands
[2].imm
;
13707 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13708 _("immediate out of range for insert"));
13709 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13715 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13716 struct neon_type_el et
= neon_check_type (2, rs
,
13717 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13718 int imm
= inst
.operands
[2].imm
;
13719 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13720 _("immediate out of range for insert"));
13721 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13725 do_neon_qshlu_imm (void)
13727 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13728 struct neon_type_el et
= neon_check_type (2, rs
,
13729 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13730 int imm
= inst
.operands
[2].imm
;
13731 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13732 _("immediate out of range for shift"));
13733 /* Only encodes the 'U present' variant of the instruction.
13734 In this case, signed types have OP (bit 8) set to 0.
13735 Unsigned types have OP set to 1. */
13736 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13737 /* The rest of the bits are the same as other immediate shifts. */
13738 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13742 do_neon_qmovn (void)
13744 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13745 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13746 /* Saturating move where operands can be signed or unsigned, and the
13747 destination has the same signedness. */
13748 NEON_ENCODE (INTEGER
, inst
);
13749 if (et
.type
== NT_unsigned
)
13750 inst
.instruction
|= 0xc0;
13752 inst
.instruction
|= 0x80;
13753 neon_two_same (0, 1, et
.size
/ 2);
13757 do_neon_qmovun (void)
13759 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13760 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13761 /* Saturating move with unsigned results. Operands must be signed. */
13762 NEON_ENCODE (INTEGER
, inst
);
13763 neon_two_same (0, 1, et
.size
/ 2);
13767 do_neon_rshift_sat_narrow (void)
13769 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13770 or unsigned. If operands are unsigned, results must also be unsigned. */
13771 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13772 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13773 int imm
= inst
.operands
[2].imm
;
13774 /* This gets the bounds check, size encoding and immediate bits calculation
13778 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13779 VQMOVN.I<size> <Dd>, <Qm>. */
13782 inst
.operands
[2].present
= 0;
13783 inst
.instruction
= N_MNEM_vqmovn
;
13788 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13789 _("immediate out of range"));
13790 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13794 do_neon_rshift_sat_narrow_u (void)
13796 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13797 or unsigned. If operands are unsigned, results must also be unsigned. */
13798 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13799 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13800 int imm
= inst
.operands
[2].imm
;
13801 /* This gets the bounds check, size encoding and immediate bits calculation
13805 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13806 VQMOVUN.I<size> <Dd>, <Qm>. */
13809 inst
.operands
[2].present
= 0;
13810 inst
.instruction
= N_MNEM_vqmovun
;
13815 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13816 _("immediate out of range"));
13817 /* FIXME: The manual is kind of unclear about what value U should have in
13818 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13820 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13824 do_neon_movn (void)
13826 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13827 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13828 NEON_ENCODE (INTEGER
, inst
);
13829 neon_two_same (0, 1, et
.size
/ 2);
13833 do_neon_rshift_narrow (void)
13835 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13836 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13837 int imm
= inst
.operands
[2].imm
;
13838 /* This gets the bounds check, size encoding and immediate bits calculation
13842 /* If immediate is zero then we are a pseudo-instruction for
13843 VMOVN.I<size> <Dd>, <Qm> */
13846 inst
.operands
[2].present
= 0;
13847 inst
.instruction
= N_MNEM_vmovn
;
13852 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13853 _("immediate out of range for narrowing operation"));
13854 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13858 do_neon_shll (void)
13860 /* FIXME: Type checking when lengthening. */
13861 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13862 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13863 unsigned imm
= inst
.operands
[2].imm
;
13865 if (imm
== et
.size
)
13867 /* Maximum shift variant. */
13868 NEON_ENCODE (INTEGER
, inst
);
13869 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13870 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13871 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13872 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13873 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13875 neon_dp_fixup (&inst
);
13879 /* A more-specific type check for non-max versions. */
13880 et
= neon_check_type (2, NS_QDI
,
13881 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13882 NEON_ENCODE (IMMED
, inst
);
13883 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13887 /* Check the various types for the VCVT instruction, and return which version
13888 the current instruction is. */
13891 neon_cvt_flavour (enum neon_shape rs
)
13893 #define CVT_VAR(C,X,Y) \
13894 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13895 if (et.type != NT_invtype) \
13897 inst.error = NULL; \
13900 struct neon_type_el et
;
13901 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13902 || rs
== NS_FF
) ? N_VFP
: 0;
13903 /* The instruction versions which take an immediate take one register
13904 argument, which is extended to the width of the full register. Thus the
13905 "source" and "destination" registers must have the same width. Hack that
13906 here by making the size equal to the key (wider, in this case) operand. */
13907 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13909 CVT_VAR (0, N_S32
, N_F32
);
13910 CVT_VAR (1, N_U32
, N_F32
);
13911 CVT_VAR (2, N_F32
, N_S32
);
13912 CVT_VAR (3, N_F32
, N_U32
);
13913 /* Half-precision conversions. */
13914 CVT_VAR (4, N_F32
, N_F16
);
13915 CVT_VAR (5, N_F16
, N_F32
);
13919 /* VFP instructions. */
13920 CVT_VAR (6, N_F32
, N_F64
);
13921 CVT_VAR (7, N_F64
, N_F32
);
13922 CVT_VAR (8, N_S32
, N_F64
| key
);
13923 CVT_VAR (9, N_U32
, N_F64
| key
);
13924 CVT_VAR (10, N_F64
| key
, N_S32
);
13925 CVT_VAR (11, N_F64
| key
, N_U32
);
13926 /* VFP instructions with bitshift. */
13927 CVT_VAR (12, N_F32
| key
, N_S16
);
13928 CVT_VAR (13, N_F32
| key
, N_U16
);
13929 CVT_VAR (14, N_F64
| key
, N_S16
);
13930 CVT_VAR (15, N_F64
| key
, N_U16
);
13931 CVT_VAR (16, N_S16
, N_F32
| key
);
13932 CVT_VAR (17, N_U16
, N_F32
| key
);
13933 CVT_VAR (18, N_S16
, N_F64
| key
);
13934 CVT_VAR (19, N_U16
, N_F64
| key
);
13940 /* Neon-syntax VFP conversions. */
13943 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13945 const char *opname
= 0;
13947 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13949 /* Conversions with immediate bitshift. */
13950 const char *enc
[] =
13974 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13976 opname
= enc
[flavour
];
13977 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13978 _("operands 0 and 1 must be the same register"));
13979 inst
.operands
[1] = inst
.operands
[2];
13980 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13985 /* Conversions without bitshift. */
13986 const char *enc
[] =
14002 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14003 opname
= enc
[flavour
];
14007 do_vfp_nsyn_opcode (opname
);
14011 do_vfp_nsyn_cvtz (void)
14013 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14014 int flavour
= neon_cvt_flavour (rs
);
14015 const char *enc
[] =
14029 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14030 do_vfp_nsyn_opcode (enc
[flavour
]);
14034 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14036 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14037 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14038 int flavour
= neon_cvt_flavour (rs
);
14040 /* PR11109: Handle round-to-zero for VCVT conversions. */
14042 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14043 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14044 && (rs
== NS_FD
|| rs
== NS_FF
))
14046 do_vfp_nsyn_cvtz ();
14050 /* VFP rather than Neon conversions. */
14053 do_vfp_nsyn_cvt (rs
, flavour
);
14063 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14065 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14068 /* Fixed-point conversion with #0 immediate is encoded as an
14069 integer conversion. */
14070 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14072 immbits
= 32 - inst
.operands
[2].imm
;
14073 NEON_ENCODE (IMMED
, inst
);
14075 inst
.instruction
|= enctab
[flavour
];
14076 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14077 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14078 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14079 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14080 inst
.instruction
|= neon_quad (rs
) << 6;
14081 inst
.instruction
|= 1 << 21;
14082 inst
.instruction
|= immbits
<< 16;
14084 neon_dp_fixup (&inst
);
14092 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14094 NEON_ENCODE (INTEGER
, inst
);
14096 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14100 inst
.instruction
|= enctab
[flavour
];
14102 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14103 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14104 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14105 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14106 inst
.instruction
|= neon_quad (rs
) << 6;
14107 inst
.instruction
|= 2 << 18;
14109 neon_dp_fixup (&inst
);
14113 /* Half-precision conversions for Advanced SIMD -- neon. */
14118 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14120 as_bad (_("operand size must match register width"));
14125 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14127 as_bad (_("operand size must match register width"));
14132 inst
.instruction
= 0x3b60600;
14134 inst
.instruction
= 0x3b60700;
14136 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14137 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14138 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14139 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14140 neon_dp_fixup (&inst
);
14144 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14145 do_vfp_nsyn_cvt (rs
, flavour
);
14150 do_neon_cvtr (void)
14152 do_neon_cvt_1 (FALSE
);
14158 do_neon_cvt_1 (TRUE
);
14162 do_neon_cvtb (void)
14164 inst
.instruction
= 0xeb20a40;
14166 /* The sizes are attached to the mnemonic. */
14167 if (inst
.vectype
.el
[0].type
!= NT_invtype
14168 && inst
.vectype
.el
[0].size
== 16)
14169 inst
.instruction
|= 0x00010000;
14171 /* Programmer's syntax: the sizes are attached to the operands. */
14172 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14173 && inst
.operands
[0].vectype
.size
== 16)
14174 inst
.instruction
|= 0x00010000;
14176 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14177 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14178 do_vfp_cond_or_thumb ();
14183 do_neon_cvtt (void)
14186 inst
.instruction
|= 0x80;
14190 neon_move_immediate (void)
14192 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14193 struct neon_type_el et
= neon_check_type (2, rs
,
14194 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14195 unsigned immlo
, immhi
= 0, immbits
;
14196 int op
, cmode
, float_p
;
14198 constraint (et
.type
== NT_invtype
,
14199 _("operand size must be specified for immediate VMOV"));
14201 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14202 op
= (inst
.instruction
& (1 << 5)) != 0;
14204 immlo
= inst
.operands
[1].imm
;
14205 if (inst
.operands
[1].regisimm
)
14206 immhi
= inst
.operands
[1].reg
;
14208 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14209 _("immediate has bits set outside the operand size"));
14211 float_p
= inst
.operands
[1].immisfloat
;
14213 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14214 et
.size
, et
.type
)) == FAIL
)
14216 /* Invert relevant bits only. */
14217 neon_invert_size (&immlo
, &immhi
, et
.size
);
14218 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14219 with one or the other; those cases are caught by
14220 neon_cmode_for_move_imm. */
14222 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14223 &op
, et
.size
, et
.type
)) == FAIL
)
14225 first_error (_("immediate out of range"));
14230 inst
.instruction
&= ~(1 << 5);
14231 inst
.instruction
|= op
<< 5;
14233 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14234 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14235 inst
.instruction
|= neon_quad (rs
) << 6;
14236 inst
.instruction
|= cmode
<< 8;
14238 neon_write_immbits (immbits
);
14244 if (inst
.operands
[1].isreg
)
14246 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14248 NEON_ENCODE (INTEGER
, inst
);
14249 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14250 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14251 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14252 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14253 inst
.instruction
|= neon_quad (rs
) << 6;
14257 NEON_ENCODE (IMMED
, inst
);
14258 neon_move_immediate ();
14261 neon_dp_fixup (&inst
);
14264 /* Encode instructions of form:
14266 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14267 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14270 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14272 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14273 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14274 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14275 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14276 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14277 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14278 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14279 inst
.instruction
|= neon_logbits (size
) << 20;
14281 neon_dp_fixup (&inst
);
14285 do_neon_dyadic_long (void)
14287 /* FIXME: Type checking for lengthening op. */
14288 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14289 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14290 neon_mixed_length (et
, et
.size
);
14294 do_neon_abal (void)
14296 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14297 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14298 neon_mixed_length (et
, et
.size
);
14302 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14304 if (inst
.operands
[2].isscalar
)
14306 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14307 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14308 NEON_ENCODE (SCALAR
, inst
);
14309 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14313 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14314 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14315 NEON_ENCODE (INTEGER
, inst
);
14316 neon_mixed_length (et
, et
.size
);
14321 do_neon_mac_maybe_scalar_long (void)
14323 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14327 do_neon_dyadic_wide (void)
14329 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14330 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14331 neon_mixed_length (et
, et
.size
);
14335 do_neon_dyadic_narrow (void)
14337 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14338 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14339 /* Operand sign is unimportant, and the U bit is part of the opcode,
14340 so force the operand type to integer. */
14341 et
.type
= NT_integer
;
14342 neon_mixed_length (et
, et
.size
/ 2);
14346 do_neon_mul_sat_scalar_long (void)
14348 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14352 do_neon_vmull (void)
14354 if (inst
.operands
[2].isscalar
)
14355 do_neon_mac_maybe_scalar_long ();
14358 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14359 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14360 if (et
.type
== NT_poly
)
14361 NEON_ENCODE (POLY
, inst
);
14363 NEON_ENCODE (INTEGER
, inst
);
14364 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14365 zero. Should be OK as-is. */
14366 neon_mixed_length (et
, et
.size
);
14373 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14374 struct neon_type_el et
= neon_check_type (3, rs
,
14375 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14376 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14378 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14379 _("shift out of range"));
14380 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14381 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14382 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14383 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14384 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14385 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14386 inst
.instruction
|= neon_quad (rs
) << 6;
14387 inst
.instruction
|= imm
<< 8;
14389 neon_dp_fixup (&inst
);
14395 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14396 struct neon_type_el et
= neon_check_type (2, rs
,
14397 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14398 unsigned op
= (inst
.instruction
>> 7) & 3;
14399 /* N (width of reversed regions) is encoded as part of the bitmask. We
14400 extract it here to check the elements to be reversed are smaller.
14401 Otherwise we'd get a reserved instruction. */
14402 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14403 gas_assert (elsize
!= 0);
14404 constraint (et
.size
>= elsize
,
14405 _("elements must be smaller than reversal region"));
14406 neon_two_same (neon_quad (rs
), 1, et
.size
);
14412 if (inst
.operands
[1].isscalar
)
14414 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14415 struct neon_type_el et
= neon_check_type (2, rs
,
14416 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14417 unsigned sizebits
= et
.size
>> 3;
14418 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14419 int logsize
= neon_logbits (et
.size
);
14420 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14422 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14425 NEON_ENCODE (SCALAR
, inst
);
14426 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14427 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14428 inst
.instruction
|= LOW4 (dm
);
14429 inst
.instruction
|= HI1 (dm
) << 5;
14430 inst
.instruction
|= neon_quad (rs
) << 6;
14431 inst
.instruction
|= x
<< 17;
14432 inst
.instruction
|= sizebits
<< 16;
14434 neon_dp_fixup (&inst
);
14438 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14439 struct neon_type_el et
= neon_check_type (2, rs
,
14440 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14441 /* Duplicate ARM register to lanes of vector. */
14442 NEON_ENCODE (ARMREG
, inst
);
14445 case 8: inst
.instruction
|= 0x400000; break;
14446 case 16: inst
.instruction
|= 0x000020; break;
14447 case 32: inst
.instruction
|= 0x000000; break;
14450 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14451 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14452 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14453 inst
.instruction
|= neon_quad (rs
) << 21;
14454 /* The encoding for this instruction is identical for the ARM and Thumb
14455 variants, except for the condition field. */
14456 do_vfp_cond_or_thumb ();
14460 /* VMOV has particularly many variations. It can be one of:
14461 0. VMOV<c><q> <Qd>, <Qm>
14462 1. VMOV<c><q> <Dd>, <Dm>
14463 (Register operations, which are VORR with Rm = Rn.)
14464 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14465 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14467 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14468 (ARM register to scalar.)
14469 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14470 (Two ARM registers to vector.)
14471 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14472 (Scalar to ARM register.)
14473 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14474 (Vector to two ARM registers.)
14475 8. VMOV.F32 <Sd>, <Sm>
14476 9. VMOV.F64 <Dd>, <Dm>
14477 (VFP register moves.)
14478 10. VMOV.F32 <Sd>, #imm
14479 11. VMOV.F64 <Dd>, #imm
14480 (VFP float immediate load.)
14481 12. VMOV <Rd>, <Sm>
14482 (VFP single to ARM reg.)
14483 13. VMOV <Sd>, <Rm>
14484 (ARM reg to VFP single.)
14485 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14486 (Two ARM regs to two VFP singles.)
14487 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14488 (Two VFP singles to two ARM regs.)
14490 These cases can be disambiguated using neon_select_shape, except cases 1/9
14491 and 3/11 which depend on the operand type too.
14493 All the encoded bits are hardcoded by this function.
14495 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14496 Cases 5, 7 may be used with VFPv2 and above.
14498 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14499 can specify a type where it doesn't make sense to, and is ignored). */
14504 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14505 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14507 struct neon_type_el et
;
14508 const char *ldconst
= 0;
14512 case NS_DD
: /* case 1/9. */
14513 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14514 /* It is not an error here if no type is given. */
14516 if (et
.type
== NT_float
&& et
.size
== 64)
14518 do_vfp_nsyn_opcode ("fcpyd");
14521 /* fall through. */
14523 case NS_QQ
: /* case 0/1. */
14525 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14527 /* The architecture manual I have doesn't explicitly state which
14528 value the U bit should have for register->register moves, but
14529 the equivalent VORR instruction has U = 0, so do that. */
14530 inst
.instruction
= 0x0200110;
14531 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14532 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14533 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14534 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14535 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14536 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14537 inst
.instruction
|= neon_quad (rs
) << 6;
14539 neon_dp_fixup (&inst
);
14543 case NS_DI
: /* case 3/11. */
14544 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14546 if (et
.type
== NT_float
&& et
.size
== 64)
14548 /* case 11 (fconstd). */
14549 ldconst
= "fconstd";
14550 goto encode_fconstd
;
14552 /* fall through. */
14554 case NS_QI
: /* case 2/3. */
14555 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14557 inst
.instruction
= 0x0800010;
14558 neon_move_immediate ();
14559 neon_dp_fixup (&inst
);
14562 case NS_SR
: /* case 4. */
14564 unsigned bcdebits
= 0;
14566 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14567 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14569 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14570 logsize
= neon_logbits (et
.size
);
14572 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14574 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14575 && et
.size
!= 32, _(BAD_FPU
));
14576 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14577 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14581 case 8: bcdebits
= 0x8; break;
14582 case 16: bcdebits
= 0x1; break;
14583 case 32: bcdebits
= 0x0; break;
14587 bcdebits
|= x
<< logsize
;
14589 inst
.instruction
= 0xe000b10;
14590 do_vfp_cond_or_thumb ();
14591 inst
.instruction
|= LOW4 (dn
) << 16;
14592 inst
.instruction
|= HI1 (dn
) << 7;
14593 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14594 inst
.instruction
|= (bcdebits
& 3) << 5;
14595 inst
.instruction
|= (bcdebits
>> 2) << 21;
14599 case NS_DRR
: /* case 5 (fmdrr). */
14600 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14603 inst
.instruction
= 0xc400b10;
14604 do_vfp_cond_or_thumb ();
14605 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14606 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14607 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14608 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14611 case NS_RS
: /* case 6. */
14614 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14615 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14616 unsigned abcdebits
= 0;
14618 et
= neon_check_type (2, NS_NULL
,
14619 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14620 logsize
= neon_logbits (et
.size
);
14622 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14624 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14625 && et
.size
!= 32, _(BAD_FPU
));
14626 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14627 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14631 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14632 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14633 case 32: abcdebits
= 0x00; break;
14637 abcdebits
|= x
<< logsize
;
14638 inst
.instruction
= 0xe100b10;
14639 do_vfp_cond_or_thumb ();
14640 inst
.instruction
|= LOW4 (dn
) << 16;
14641 inst
.instruction
|= HI1 (dn
) << 7;
14642 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14643 inst
.instruction
|= (abcdebits
& 3) << 5;
14644 inst
.instruction
|= (abcdebits
>> 2) << 21;
14648 case NS_RRD
: /* case 7 (fmrrd). */
14649 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14652 inst
.instruction
= 0xc500b10;
14653 do_vfp_cond_or_thumb ();
14654 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14655 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14656 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14657 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14660 case NS_FF
: /* case 8 (fcpys). */
14661 do_vfp_nsyn_opcode ("fcpys");
14664 case NS_FI
: /* case 10 (fconsts). */
14665 ldconst
= "fconsts";
14667 if (is_quarter_float (inst
.operands
[1].imm
))
14669 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14670 do_vfp_nsyn_opcode (ldconst
);
14673 first_error (_("immediate out of range"));
14676 case NS_RF
: /* case 12 (fmrs). */
14677 do_vfp_nsyn_opcode ("fmrs");
14680 case NS_FR
: /* case 13 (fmsr). */
14681 do_vfp_nsyn_opcode ("fmsr");
14684 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14685 (one of which is a list), but we have parsed four. Do some fiddling to
14686 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14688 case NS_RRFF
: /* case 14 (fmrrs). */
14689 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14690 _("VFP registers must be adjacent"));
14691 inst
.operands
[2].imm
= 2;
14692 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14693 do_vfp_nsyn_opcode ("fmrrs");
14696 case NS_FFRR
: /* case 15 (fmsrr). */
14697 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14698 _("VFP registers must be adjacent"));
14699 inst
.operands
[1] = inst
.operands
[2];
14700 inst
.operands
[2] = inst
.operands
[3];
14701 inst
.operands
[0].imm
= 2;
14702 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14703 do_vfp_nsyn_opcode ("fmsrr");
14712 do_neon_rshift_round_imm (void)
14714 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14715 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14716 int imm
= inst
.operands
[2].imm
;
14718 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14721 inst
.operands
[2].present
= 0;
14726 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14727 _("immediate out of range for shift"));
14728 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14733 do_neon_movl (void)
14735 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14736 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14737 unsigned sizebits
= et
.size
>> 3;
14738 inst
.instruction
|= sizebits
<< 19;
14739 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14745 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14746 struct neon_type_el et
= neon_check_type (2, rs
,
14747 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14748 NEON_ENCODE (INTEGER
, inst
);
14749 neon_two_same (neon_quad (rs
), 1, et
.size
);
14753 do_neon_zip_uzp (void)
14755 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14756 struct neon_type_el et
= neon_check_type (2, rs
,
14757 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14758 if (rs
== NS_DD
&& et
.size
== 32)
14760 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14761 inst
.instruction
= N_MNEM_vtrn
;
14765 neon_two_same (neon_quad (rs
), 1, et
.size
);
14769 do_neon_sat_abs_neg (void)
14771 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14772 struct neon_type_el et
= neon_check_type (2, rs
,
14773 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14774 neon_two_same (neon_quad (rs
), 1, et
.size
);
14778 do_neon_pair_long (void)
14780 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14781 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14782 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14783 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14784 neon_two_same (neon_quad (rs
), 1, et
.size
);
14788 do_neon_recip_est (void)
14790 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14791 struct neon_type_el et
= neon_check_type (2, rs
,
14792 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14793 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14794 neon_two_same (neon_quad (rs
), 1, et
.size
);
14800 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14801 struct neon_type_el et
= neon_check_type (2, rs
,
14802 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14803 neon_two_same (neon_quad (rs
), 1, et
.size
);
14809 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14810 struct neon_type_el et
= neon_check_type (2, rs
,
14811 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14812 neon_two_same (neon_quad (rs
), 1, et
.size
);
14818 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14819 struct neon_type_el et
= neon_check_type (2, rs
,
14820 N_EQK
| N_INT
, N_8
| N_KEY
);
14821 neon_two_same (neon_quad (rs
), 1, et
.size
);
14827 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14828 neon_two_same (neon_quad (rs
), 1, -1);
14832 do_neon_tbl_tbx (void)
14834 unsigned listlenbits
;
14835 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14837 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14839 first_error (_("bad list length for table lookup"));
14843 listlenbits
= inst
.operands
[1].imm
- 1;
14844 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14845 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14846 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14847 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14848 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14849 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14850 inst
.instruction
|= listlenbits
<< 8;
14852 neon_dp_fixup (&inst
);
14856 do_neon_ldm_stm (void)
14858 /* P, U and L bits are part of bitmask. */
14859 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14860 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14862 if (inst
.operands
[1].issingle
)
14864 do_vfp_nsyn_ldm_stm (is_dbmode
);
14868 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14869 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14871 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14872 _("register list must contain at least 1 and at most 16 "
14875 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14876 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14877 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14878 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14880 inst
.instruction
|= offsetbits
;
14882 do_vfp_cond_or_thumb ();
14886 do_neon_ldr_str (void)
14888 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14890 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
14891 And is UNPREDICTABLE in thumb mode. */
14893 && inst
.operands
[1].reg
== REG_PC
14894 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
14896 if (!thumb_mode
&& warn_on_deprecated
)
14897 as_warn (_("Use of PC here is deprecated"));
14899 inst
.error
= _("Use of PC here is UNPREDICTABLE");
14902 if (inst
.operands
[0].issingle
)
14905 do_vfp_nsyn_opcode ("flds");
14907 do_vfp_nsyn_opcode ("fsts");
14912 do_vfp_nsyn_opcode ("fldd");
14914 do_vfp_nsyn_opcode ("fstd");
14918 /* "interleave" version also handles non-interleaving register VLD1/VST1
14922 do_neon_ld_st_interleave (void)
14924 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14925 N_8
| N_16
| N_32
| N_64
);
14926 unsigned alignbits
= 0;
14928 /* The bits in this table go:
14929 0: register stride of one (0) or two (1)
14930 1,2: register list length, minus one (1, 2, 3, 4).
14931 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14932 We use -1 for invalid entries. */
14933 const int typetable
[] =
14935 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14936 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14937 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14938 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14942 if (et
.type
== NT_invtype
)
14945 if (inst
.operands
[1].immisalign
)
14946 switch (inst
.operands
[1].imm
>> 8)
14948 case 64: alignbits
= 1; break;
14950 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14951 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14952 goto bad_alignment
;
14956 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14957 goto bad_alignment
;
14962 first_error (_("bad alignment"));
14966 inst
.instruction
|= alignbits
<< 4;
14967 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14969 /* Bits [4:6] of the immediate in a list specifier encode register stride
14970 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14971 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14972 up the right value for "type" in a table based on this value and the given
14973 list style, then stick it back. */
14974 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14975 | (((inst
.instruction
>> 8) & 3) << 3);
14977 typebits
= typetable
[idx
];
14979 constraint (typebits
== -1, _("bad list type for instruction"));
14981 inst
.instruction
&= ~0xf00;
14982 inst
.instruction
|= typebits
<< 8;
14985 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14986 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14987 otherwise. The variable arguments are a list of pairs of legal (size, align)
14988 values, terminated with -1. */
14991 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14994 int result
= FAIL
, thissize
, thisalign
;
14996 if (!inst
.operands
[1].immisalign
)
15002 va_start (ap
, do_align
);
15006 thissize
= va_arg (ap
, int);
15007 if (thissize
== -1)
15009 thisalign
= va_arg (ap
, int);
15011 if (size
== thissize
&& align
== thisalign
)
15014 while (result
!= SUCCESS
);
15018 if (result
== SUCCESS
)
15021 first_error (_("unsupported alignment for instruction"));
15027 do_neon_ld_st_lane (void)
15029 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15030 int align_good
, do_align
= 0;
15031 int logsize
= neon_logbits (et
.size
);
15032 int align
= inst
.operands
[1].imm
>> 8;
15033 int n
= (inst
.instruction
>> 8) & 3;
15034 int max_el
= 64 / et
.size
;
15036 if (et
.type
== NT_invtype
)
15039 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15040 _("bad list length"));
15041 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15042 _("scalar index out of range"));
15043 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15045 _("stride of 2 unavailable when element size is 8"));
15049 case 0: /* VLD1 / VST1. */
15050 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15052 if (align_good
== FAIL
)
15056 unsigned alignbits
= 0;
15059 case 16: alignbits
= 0x1; break;
15060 case 32: alignbits
= 0x3; break;
15063 inst
.instruction
|= alignbits
<< 4;
15067 case 1: /* VLD2 / VST2. */
15068 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15070 if (align_good
== FAIL
)
15073 inst
.instruction
|= 1 << 4;
15076 case 2: /* VLD3 / VST3. */
15077 constraint (inst
.operands
[1].immisalign
,
15078 _("can't use alignment with this instruction"));
15081 case 3: /* VLD4 / VST4. */
15082 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15083 16, 64, 32, 64, 32, 128, -1);
15084 if (align_good
== FAIL
)
15088 unsigned alignbits
= 0;
15091 case 8: alignbits
= 0x1; break;
15092 case 16: alignbits
= 0x1; break;
15093 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15096 inst
.instruction
|= alignbits
<< 4;
15103 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15104 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15105 inst
.instruction
|= 1 << (4 + logsize
);
15107 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15108 inst
.instruction
|= logsize
<< 10;
15111 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15114 do_neon_ld_dup (void)
15116 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15117 int align_good
, do_align
= 0;
15119 if (et
.type
== NT_invtype
)
15122 switch ((inst
.instruction
>> 8) & 3)
15124 case 0: /* VLD1. */
15125 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15126 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15127 &do_align
, 16, 16, 32, 32, -1);
15128 if (align_good
== FAIL
)
15130 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15133 case 2: inst
.instruction
|= 1 << 5; break;
15134 default: first_error (_("bad list length")); return;
15136 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15139 case 1: /* VLD2. */
15140 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15141 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15142 if (align_good
== FAIL
)
15144 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15145 _("bad list length"));
15146 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15147 inst
.instruction
|= 1 << 5;
15148 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15151 case 2: /* VLD3. */
15152 constraint (inst
.operands
[1].immisalign
,
15153 _("can't use alignment with this instruction"));
15154 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15155 _("bad list length"));
15156 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15157 inst
.instruction
|= 1 << 5;
15158 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15161 case 3: /* VLD4. */
15163 int align
= inst
.operands
[1].imm
>> 8;
15164 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15165 16, 64, 32, 64, 32, 128, -1);
15166 if (align_good
== FAIL
)
15168 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15169 _("bad list length"));
15170 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15171 inst
.instruction
|= 1 << 5;
15172 if (et
.size
== 32 && align
== 128)
15173 inst
.instruction
|= 0x3 << 6;
15175 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15182 inst
.instruction
|= do_align
<< 4;
15185 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15186 apart from bits [11:4]. */
15189 do_neon_ldx_stx (void)
15191 if (inst
.operands
[1].isreg
)
15192 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15194 switch (NEON_LANE (inst
.operands
[0].imm
))
15196 case NEON_INTERLEAVE_LANES
:
15197 NEON_ENCODE (INTERLV
, inst
);
15198 do_neon_ld_st_interleave ();
15201 case NEON_ALL_LANES
:
15202 NEON_ENCODE (DUP
, inst
);
15207 NEON_ENCODE (LANE
, inst
);
15208 do_neon_ld_st_lane ();
15211 /* L bit comes from bit mask. */
15212 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15213 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15214 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15216 if (inst
.operands
[1].postind
)
15218 int postreg
= inst
.operands
[1].imm
& 0xf;
15219 constraint (!inst
.operands
[1].immisreg
,
15220 _("post-index must be a register"));
15221 constraint (postreg
== 0xd || postreg
== 0xf,
15222 _("bad register for post-index"));
15223 inst
.instruction
|= postreg
;
15225 else if (inst
.operands
[1].writeback
)
15227 inst
.instruction
|= 0xd;
15230 inst
.instruction
|= 0xf;
15233 inst
.instruction
|= 0xf9000000;
15235 inst
.instruction
|= 0xf4000000;
15238 /* Overall per-instruction processing. */
15240 /* We need to be able to fix up arbitrary expressions in some statements.
15241 This is so that we can handle symbols that are an arbitrary distance from
15242 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15243 which returns part of an address in a form which will be valid for
15244 a data instruction. We do this by pushing the expression into a symbol
15245 in the expr_section, and creating a fix for that. */
15248 fix_new_arm (fragS
* frag
,
15263 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15264 (enum bfd_reloc_code_real
) reloc
);
15268 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15269 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15273 /* Mark whether the fix is to a THUMB instruction, or an ARM
15275 new_fix
->tc_fix_data
= thumb_mode
;
15278 /* Create a frg for an instruction requiring relaxation. */
15280 output_relax_insn (void)
15286 /* The size of the instruction is unknown, so tie the debug info to the
15287 start of the instruction. */
15288 dwarf2_emit_insn (0);
15290 switch (inst
.reloc
.exp
.X_op
)
15293 sym
= inst
.reloc
.exp
.X_add_symbol
;
15294 offset
= inst
.reloc
.exp
.X_add_number
;
15298 offset
= inst
.reloc
.exp
.X_add_number
;
15301 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15305 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15306 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15307 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15310 /* Write a 32-bit thumb instruction to buf. */
15312 put_thumb32_insn (char * buf
, unsigned long insn
)
15314 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15315 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15319 output_inst (const char * str
)
15325 as_bad ("%s -- `%s'", inst
.error
, str
);
15330 output_relax_insn ();
15333 if (inst
.size
== 0)
15336 to
= frag_more (inst
.size
);
15337 /* PR 9814: Record the thumb mode into the current frag so that we know
15338 what type of NOP padding to use, if necessary. We override any previous
15339 setting so that if the mode has changed then the NOPS that we use will
15340 match the encoding of the last instruction in the frag. */
15341 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15343 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15345 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15346 put_thumb32_insn (to
, inst
.instruction
);
15348 else if (inst
.size
> INSN_SIZE
)
15350 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15351 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15352 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15355 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15357 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15358 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15359 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15362 dwarf2_emit_insn (inst
.size
);
15366 output_it_inst (int cond
, int mask
, char * to
)
15368 unsigned long instruction
= 0xbf00;
15371 instruction
|= mask
;
15372 instruction
|= cond
<< 4;
15376 to
= frag_more (2);
15378 dwarf2_emit_insn (2);
15382 md_number_to_chars (to
, instruction
, 2);
15387 /* Tag values used in struct asm_opcode's tag field. */
15390 OT_unconditional
, /* Instruction cannot be conditionalized.
15391 The ARM condition field is still 0xE. */
15392 OT_unconditionalF
, /* Instruction cannot be conditionalized
15393 and carries 0xF in its ARM condition field. */
15394 OT_csuffix
, /* Instruction takes a conditional suffix. */
15395 OT_csuffixF
, /* Some forms of the instruction take a conditional
15396 suffix, others place 0xF where the condition field
15398 OT_cinfix3
, /* Instruction takes a conditional infix,
15399 beginning at character index 3. (In
15400 unified mode, it becomes a suffix.) */
15401 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15402 tsts, cmps, cmns, and teqs. */
15403 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15404 character index 3, even in unified mode. Used for
15405 legacy instructions where suffix and infix forms
15406 may be ambiguous. */
15407 OT_csuf_or_in3
, /* Instruction takes either a conditional
15408 suffix or an infix at character index 3. */
15409 OT_odd_infix_unc
, /* This is the unconditional variant of an
15410 instruction that takes a conditional infix
15411 at an unusual position. In unified mode,
15412 this variant will accept a suffix. */
15413 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15414 are the conditional variants of instructions that
15415 take conditional infixes in unusual positions.
15416 The infix appears at character index
15417 (tag - OT_odd_infix_0). These are not accepted
15418 in unified mode. */
15421 /* Subroutine of md_assemble, responsible for looking up the primary
15422 opcode from the mnemonic the user wrote. STR points to the
15423 beginning of the mnemonic.
15425 This is not simply a hash table lookup, because of conditional
15426 variants. Most instructions have conditional variants, which are
15427 expressed with a _conditional affix_ to the mnemonic. If we were
15428 to encode each conditional variant as a literal string in the opcode
15429 table, it would have approximately 20,000 entries.
15431 Most mnemonics take this affix as a suffix, and in unified syntax,
15432 'most' is upgraded to 'all'. However, in the divided syntax, some
15433 instructions take the affix as an infix, notably the s-variants of
15434 the arithmetic instructions. Of those instructions, all but six
15435 have the infix appear after the third character of the mnemonic.
15437 Accordingly, the algorithm for looking up primary opcodes given
15440 1. Look up the identifier in the opcode table.
15441 If we find a match, go to step U.
15443 2. Look up the last two characters of the identifier in the
15444 conditions table. If we find a match, look up the first N-2
15445 characters of the identifier in the opcode table. If we
15446 find a match, go to step CE.
15448 3. Look up the fourth and fifth characters of the identifier in
15449 the conditions table. If we find a match, extract those
15450 characters from the identifier, and look up the remaining
15451 characters in the opcode table. If we find a match, go
15456 U. Examine the tag field of the opcode structure, in case this is
15457 one of the six instructions with its conditional infix in an
15458 unusual place. If it is, the tag tells us where to find the
15459 infix; look it up in the conditions table and set inst.cond
15460 accordingly. Otherwise, this is an unconditional instruction.
15461 Again set inst.cond accordingly. Return the opcode structure.
15463 CE. Examine the tag field to make sure this is an instruction that
15464 should receive a conditional suffix. If it is not, fail.
15465 Otherwise, set inst.cond from the suffix we already looked up,
15466 and return the opcode structure.
15468 CM. Examine the tag field to make sure this is an instruction that
15469 should receive a conditional infix after the third character.
15470 If it is not, fail. Otherwise, undo the edits to the current
15471 line of input and proceed as for case CE. */
15473 static const struct asm_opcode
*
15474 opcode_lookup (char **str
)
15478 const struct asm_opcode
*opcode
;
15479 const struct asm_cond
*cond
;
15482 /* Scan up to the end of the mnemonic, which must end in white space,
15483 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15484 for (base
= end
= *str
; *end
!= '\0'; end
++)
15485 if (*end
== ' ' || *end
== '.')
15491 /* Handle a possible width suffix and/or Neon type suffix. */
15496 /* The .w and .n suffixes are only valid if the unified syntax is in
15498 if (unified_syntax
&& end
[1] == 'w')
15500 else if (unified_syntax
&& end
[1] == 'n')
15505 inst
.vectype
.elems
= 0;
15507 *str
= end
+ offset
;
15509 if (end
[offset
] == '.')
15511 /* See if we have a Neon type suffix (possible in either unified or
15512 non-unified ARM syntax mode). */
15513 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15516 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15522 /* Look for unaffixed or special-case affixed mnemonic. */
15523 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15528 if (opcode
->tag
< OT_odd_infix_0
)
15530 inst
.cond
= COND_ALWAYS
;
15534 if (warn_on_deprecated
&& unified_syntax
)
15535 as_warn (_("conditional infixes are deprecated in unified syntax"));
15536 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15537 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15540 inst
.cond
= cond
->value
;
15544 /* Cannot have a conditional suffix on a mnemonic of less than two
15546 if (end
- base
< 3)
15549 /* Look for suffixed mnemonic. */
15551 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15552 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15554 if (opcode
&& cond
)
15557 switch (opcode
->tag
)
15559 case OT_cinfix3_legacy
:
15560 /* Ignore conditional suffixes matched on infix only mnemonics. */
15564 case OT_cinfix3_deprecated
:
15565 case OT_odd_infix_unc
:
15566 if (!unified_syntax
)
15568 /* else fall through */
15572 case OT_csuf_or_in3
:
15573 inst
.cond
= cond
->value
;
15576 case OT_unconditional
:
15577 case OT_unconditionalF
:
15579 inst
.cond
= cond
->value
;
15582 /* Delayed diagnostic. */
15583 inst
.error
= BAD_COND
;
15584 inst
.cond
= COND_ALWAYS
;
15593 /* Cannot have a usual-position infix on a mnemonic of less than
15594 six characters (five would be a suffix). */
15595 if (end
- base
< 6)
15598 /* Look for infixed mnemonic in the usual position. */
15600 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15604 memcpy (save
, affix
, 2);
15605 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15606 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15608 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15609 memcpy (affix
, save
, 2);
15612 && (opcode
->tag
== OT_cinfix3
15613 || opcode
->tag
== OT_cinfix3_deprecated
15614 || opcode
->tag
== OT_csuf_or_in3
15615 || opcode
->tag
== OT_cinfix3_legacy
))
15618 if (warn_on_deprecated
&& unified_syntax
15619 && (opcode
->tag
== OT_cinfix3
15620 || opcode
->tag
== OT_cinfix3_deprecated
))
15621 as_warn (_("conditional infixes are deprecated in unified syntax"));
15623 inst
.cond
= cond
->value
;
15630 /* This function generates an initial IT instruction, leaving its block
15631 virtually open for the new instructions. Eventually,
15632 the mask will be updated by now_it_add_mask () each time
15633 a new instruction needs to be included in the IT block.
15634 Finally, the block is closed with close_automatic_it_block ().
15635 The block closure can be requested either from md_assemble (),
15636 a tencode (), or due to a label hook. */
15639 new_automatic_it_block (int cond
)
15641 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15642 now_it
.mask
= 0x18;
15644 now_it
.block_length
= 1;
15645 mapping_state (MAP_THUMB
);
15646 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15649 /* Close an automatic IT block.
15650 See comments in new_automatic_it_block (). */
15653 close_automatic_it_block (void)
15655 now_it
.mask
= 0x10;
15656 now_it
.block_length
= 0;
15659 /* Update the mask of the current automatically-generated IT
15660 instruction. See comments in new_automatic_it_block (). */
15663 now_it_add_mask (int cond
)
15665 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15666 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15667 | ((bitvalue) << (nbit)))
15668 const int resulting_bit
= (cond
& 1);
15670 now_it
.mask
&= 0xf;
15671 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15673 (5 - now_it
.block_length
));
15674 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15676 ((5 - now_it
.block_length
) - 1) );
15677 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15680 #undef SET_BIT_VALUE
15683 /* The IT blocks handling machinery is accessed through the these functions:
15684 it_fsm_pre_encode () from md_assemble ()
15685 set_it_insn_type () optional, from the tencode functions
15686 set_it_insn_type_last () ditto
15687 in_it_block () ditto
15688 it_fsm_post_encode () from md_assemble ()
15689 force_automatic_it_block_close () from label habdling functions
15692 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15693 initializing the IT insn type with a generic initial value depending
15694 on the inst.condition.
15695 2) During the tencode function, two things may happen:
15696 a) The tencode function overrides the IT insn type by
15697 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15698 b) The tencode function queries the IT block state by
15699 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15701 Both set_it_insn_type and in_it_block run the internal FSM state
15702 handling function (handle_it_state), because: a) setting the IT insn
15703 type may incur in an invalid state (exiting the function),
15704 and b) querying the state requires the FSM to be updated.
15705 Specifically we want to avoid creating an IT block for conditional
15706 branches, so it_fsm_pre_encode is actually a guess and we can't
15707 determine whether an IT block is required until the tencode () routine
15708 has decided what type of instruction this actually it.
15709 Because of this, if set_it_insn_type and in_it_block have to be used,
15710 set_it_insn_type has to be called first.
15712 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15713 determines the insn IT type depending on the inst.cond code.
15714 When a tencode () routine encodes an instruction that can be
15715 either outside an IT block, or, in the case of being inside, has to be
15716 the last one, set_it_insn_type_last () will determine the proper
15717 IT instruction type based on the inst.cond code. Otherwise,
15718 set_it_insn_type can be called for overriding that logic or
15719 for covering other cases.
15721 Calling handle_it_state () may not transition the IT block state to
15722 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15723 still queried. Instead, if the FSM determines that the state should
15724 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15725 after the tencode () function: that's what it_fsm_post_encode () does.
15727 Since in_it_block () calls the state handling function to get an
15728 updated state, an error may occur (due to invalid insns combination).
15729 In that case, inst.error is set.
15730 Therefore, inst.error has to be checked after the execution of
15731 the tencode () routine.
15733 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15734 any pending state change (if any) that didn't take place in
15735 handle_it_state () as explained above. */
15738 it_fsm_pre_encode (void)
15740 if (inst
.cond
!= COND_ALWAYS
)
15741 inst
.it_insn_type
= INSIDE_IT_INSN
;
15743 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15745 now_it
.state_handled
= 0;
15748 /* IT state FSM handling function. */
15751 handle_it_state (void)
15753 now_it
.state_handled
= 1;
15755 switch (now_it
.state
)
15757 case OUTSIDE_IT_BLOCK
:
15758 switch (inst
.it_insn_type
)
15760 case OUTSIDE_IT_INSN
:
15763 case INSIDE_IT_INSN
:
15764 case INSIDE_IT_LAST_INSN
:
15765 if (thumb_mode
== 0)
15768 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15769 as_tsktsk (_("Warning: conditional outside an IT block"\
15774 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15775 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15777 /* Automatically generate the IT instruction. */
15778 new_automatic_it_block (inst
.cond
);
15779 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15780 close_automatic_it_block ();
15784 inst
.error
= BAD_OUT_IT
;
15790 case IF_INSIDE_IT_LAST_INSN
:
15791 case NEUTRAL_IT_INSN
:
15795 now_it
.state
= MANUAL_IT_BLOCK
;
15796 now_it
.block_length
= 0;
15801 case AUTOMATIC_IT_BLOCK
:
15802 /* Three things may happen now:
15803 a) We should increment current it block size;
15804 b) We should close current it block (closing insn or 4 insns);
15805 c) We should close current it block and start a new one (due
15806 to incompatible conditions or
15807 4 insns-length block reached). */
15809 switch (inst
.it_insn_type
)
15811 case OUTSIDE_IT_INSN
:
15812 /* The closure of the block shall happen immediatelly,
15813 so any in_it_block () call reports the block as closed. */
15814 force_automatic_it_block_close ();
15817 case INSIDE_IT_INSN
:
15818 case INSIDE_IT_LAST_INSN
:
15819 case IF_INSIDE_IT_LAST_INSN
:
15820 now_it
.block_length
++;
15822 if (now_it
.block_length
> 4
15823 || !now_it_compatible (inst
.cond
))
15825 force_automatic_it_block_close ();
15826 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15827 new_automatic_it_block (inst
.cond
);
15831 now_it_add_mask (inst
.cond
);
15834 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15835 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15836 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15837 close_automatic_it_block ();
15840 case NEUTRAL_IT_INSN
:
15841 now_it
.block_length
++;
15843 if (now_it
.block_length
> 4)
15844 force_automatic_it_block_close ();
15846 now_it_add_mask (now_it
.cc
& 1);
15850 close_automatic_it_block ();
15851 now_it
.state
= MANUAL_IT_BLOCK
;
15856 case MANUAL_IT_BLOCK
:
15858 /* Check conditional suffixes. */
15859 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15862 now_it
.mask
&= 0x1f;
15863 is_last
= (now_it
.mask
== 0x10);
15865 switch (inst
.it_insn_type
)
15867 case OUTSIDE_IT_INSN
:
15868 inst
.error
= BAD_NOT_IT
;
15871 case INSIDE_IT_INSN
:
15872 if (cond
!= inst
.cond
)
15874 inst
.error
= BAD_IT_COND
;
15879 case INSIDE_IT_LAST_INSN
:
15880 case IF_INSIDE_IT_LAST_INSN
:
15881 if (cond
!= inst
.cond
)
15883 inst
.error
= BAD_IT_COND
;
15888 inst
.error
= BAD_BRANCH
;
15893 case NEUTRAL_IT_INSN
:
15894 /* The BKPT instruction is unconditional even in an IT block. */
15898 inst
.error
= BAD_IT_IT
;
15909 it_fsm_post_encode (void)
15913 if (!now_it
.state_handled
)
15914 handle_it_state ();
15916 is_last
= (now_it
.mask
== 0x10);
15919 now_it
.state
= OUTSIDE_IT_BLOCK
;
15925 force_automatic_it_block_close (void)
15927 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15929 close_automatic_it_block ();
15930 now_it
.state
= OUTSIDE_IT_BLOCK
;
15938 if (!now_it
.state_handled
)
15939 handle_it_state ();
15941 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15945 md_assemble (char *str
)
15948 const struct asm_opcode
* opcode
;
15950 /* Align the previous label if needed. */
15951 if (last_label_seen
!= NULL
)
15953 symbol_set_frag (last_label_seen
, frag_now
);
15954 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15955 S_SET_SEGMENT (last_label_seen
, now_seg
);
15958 memset (&inst
, '\0', sizeof (inst
));
15959 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15961 opcode
= opcode_lookup (&p
);
15964 /* It wasn't an instruction, but it might be a register alias of
15965 the form alias .req reg, or a Neon .dn/.qn directive. */
15966 if (! create_register_alias (str
, p
)
15967 && ! create_neon_reg_alias (str
, p
))
15968 as_bad (_("bad instruction `%s'"), str
);
15973 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15974 as_warn (_("s suffix on comparison instruction is deprecated"));
15976 /* The value which unconditional instructions should have in place of the
15977 condition field. */
15978 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15982 arm_feature_set variant
;
15984 variant
= cpu_variant
;
15985 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15986 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15987 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15988 /* Check that this instruction is supported for this CPU. */
15989 if (!opcode
->tvariant
15990 || (thumb_mode
== 1
15991 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15993 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15996 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15997 && opcode
->tencode
!= do_t_branch
)
15999 as_bad (_("Thumb does not support conditional execution"));
16003 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16005 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16006 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16007 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16009 /* Two things are addressed here.
16010 1) Implicit require narrow instructions on Thumb-1.
16011 This avoids relaxation accidentally introducing Thumb-2
16013 2) Reject wide instructions in non Thumb-2 cores. */
16014 if (inst
.size_req
== 0)
16016 else if (inst
.size_req
== 4)
16018 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16024 inst
.instruction
= opcode
->tvalue
;
16026 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16028 /* Prepare the it_insn_type for those encodings that don't set
16030 it_fsm_pre_encode ();
16032 opcode
->tencode ();
16034 it_fsm_post_encode ();
16037 if (!(inst
.error
|| inst
.relax
))
16039 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16040 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16041 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16043 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16048 /* Something has gone badly wrong if we try to relax a fixed size
16050 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16052 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16053 *opcode
->tvariant
);
16054 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16055 set those bits when Thumb-2 32-bit instructions are seen. ie.
16056 anything other than bl/blx and v6-M instructions.
16057 This is overly pessimistic for relaxable instructions. */
16058 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16060 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16061 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16062 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16065 check_neon_suffixes
;
16069 mapping_state (MAP_THUMB
);
16072 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16076 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16077 is_bx
= (opcode
->aencode
== do_bx
);
16079 /* Check that this instruction is supported for this CPU. */
16080 if (!(is_bx
&& fix_v4bx
)
16081 && !(opcode
->avariant
&&
16082 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16084 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16089 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16093 inst
.instruction
= opcode
->avalue
;
16094 if (opcode
->tag
== OT_unconditionalF
)
16095 inst
.instruction
|= 0xF << 28;
16097 inst
.instruction
|= inst
.cond
<< 28;
16098 inst
.size
= INSN_SIZE
;
16099 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16101 it_fsm_pre_encode ();
16102 opcode
->aencode ();
16103 it_fsm_post_encode ();
16105 /* Arm mode bx is marked as both v4T and v5 because it's still required
16106 on a hypothetical non-thumb v5 core. */
16108 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16110 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16111 *opcode
->avariant
);
16113 check_neon_suffixes
;
16117 mapping_state (MAP_ARM
);
16122 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16130 check_it_blocks_finished (void)
16135 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16136 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16137 == MANUAL_IT_BLOCK
)
16139 as_warn (_("section '%s' finished with an open IT block."),
16143 if (now_it
.state
== MANUAL_IT_BLOCK
)
16144 as_warn (_("file finished with an open IT block."));
16148 /* Various frobbings of labels and their addresses. */
16151 arm_start_line_hook (void)
16153 last_label_seen
= NULL
;
16157 arm_frob_label (symbolS
* sym
)
16159 last_label_seen
= sym
;
16161 ARM_SET_THUMB (sym
, thumb_mode
);
16163 #if defined OBJ_COFF || defined OBJ_ELF
16164 ARM_SET_INTERWORK (sym
, support_interwork
);
16167 force_automatic_it_block_close ();
16169 /* Note - do not allow local symbols (.Lxxx) to be labelled
16170 as Thumb functions. This is because these labels, whilst
16171 they exist inside Thumb code, are not the entry points for
16172 possible ARM->Thumb calls. Also, these labels can be used
16173 as part of a computed goto or switch statement. eg gcc
16174 can generate code that looks like this:
16176 ldr r2, [pc, .Laaa]
16186 The first instruction loads the address of the jump table.
16187 The second instruction converts a table index into a byte offset.
16188 The third instruction gets the jump address out of the table.
16189 The fourth instruction performs the jump.
16191 If the address stored at .Laaa is that of a symbol which has the
16192 Thumb_Func bit set, then the linker will arrange for this address
16193 to have the bottom bit set, which in turn would mean that the
16194 address computation performed by the third instruction would end
16195 up with the bottom bit set. Since the ARM is capable of unaligned
16196 word loads, the instruction would then load the incorrect address
16197 out of the jump table, and chaos would ensue. */
16198 if (label_is_thumb_function_name
16199 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16200 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16202 /* When the address of a Thumb function is taken the bottom
16203 bit of that address should be set. This will allow
16204 interworking between Arm and Thumb functions to work
16207 THUMB_SET_FUNC (sym
, 1);
16209 label_is_thumb_function_name
= FALSE
;
16212 dwarf2_emit_label (sym
);
16216 arm_data_in_code (void)
16218 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16220 *input_line_pointer
= '/';
16221 input_line_pointer
+= 5;
16222 *input_line_pointer
= 0;
16230 arm_canonicalize_symbol_name (char * name
)
16234 if (thumb_mode
&& (len
= strlen (name
)) > 5
16235 && streq (name
+ len
- 5, "/data"))
16236 *(name
+ len
- 5) = 0;
16241 /* Table of all register names defined by default. The user can
16242 define additional names with .req. Note that all register names
16243 should appear in both upper and lowercase variants. Some registers
16244 also have mixed-case names. */
16246 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16247 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16248 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16249 #define REGSET(p,t) \
16250 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16251 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16252 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16253 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16254 #define REGSETH(p,t) \
16255 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16256 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16257 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16258 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16259 #define REGSET2(p,t) \
16260 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16261 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16262 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16263 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16264 #define SPLRBANK(base,bank,t) \
16265 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16266 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16267 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16268 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16269 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16270 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16272 static const struct reg_entry reg_names
[] =
16274 /* ARM integer registers. */
16275 REGSET(r
, RN
), REGSET(R
, RN
),
16277 /* ATPCS synonyms. */
16278 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16279 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16280 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16282 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16283 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16284 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16286 /* Well-known aliases. */
16287 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16288 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16290 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16291 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16293 /* Coprocessor numbers. */
16294 REGSET(p
, CP
), REGSET(P
, CP
),
16296 /* Coprocessor register numbers. The "cr" variants are for backward
16298 REGSET(c
, CN
), REGSET(C
, CN
),
16299 REGSET(cr
, CN
), REGSET(CR
, CN
),
16301 /* ARM banked registers. */
16302 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16303 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16304 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16305 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16306 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16307 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16308 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16310 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16311 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16312 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16313 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16314 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16315 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16316 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16317 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16319 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16320 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16321 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16322 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16323 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16324 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16325 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16326 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16327 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16329 /* FPA registers. */
16330 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16331 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16333 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16334 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16336 /* VFP SP registers. */
16337 REGSET(s
,VFS
), REGSET(S
,VFS
),
16338 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16340 /* VFP DP Registers. */
16341 REGSET(d
,VFD
), REGSET(D
,VFD
),
16342 /* Extra Neon DP registers. */
16343 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16345 /* Neon QP registers. */
16346 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16348 /* VFP control registers. */
16349 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16350 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16351 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16352 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16353 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16354 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16356 /* Maverick DSP coprocessor registers. */
16357 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16358 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16360 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16361 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16362 REGDEF(dspsc
,0,DSPSC
),
16364 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16365 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16366 REGDEF(DSPSC
,0,DSPSC
),
16368 /* iWMMXt data registers - p0, c0-15. */
16369 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16371 /* iWMMXt control registers - p1, c0-3. */
16372 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16373 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16374 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16375 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16377 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16378 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16379 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16380 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16381 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16383 /* XScale accumulator registers. */
16384 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16390 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16391 within psr_required_here. */
16392 static const struct asm_psr psrs
[] =
16394 /* Backward compatibility notation. Note that "all" is no longer
16395 truly all possible PSR bits. */
16396 {"all", PSR_c
| PSR_f
},
16400 /* Individual flags. */
16407 /* Combinations of flags. */
16408 {"fs", PSR_f
| PSR_s
},
16409 {"fx", PSR_f
| PSR_x
},
16410 {"fc", PSR_f
| PSR_c
},
16411 {"sf", PSR_s
| PSR_f
},
16412 {"sx", PSR_s
| PSR_x
},
16413 {"sc", PSR_s
| PSR_c
},
16414 {"xf", PSR_x
| PSR_f
},
16415 {"xs", PSR_x
| PSR_s
},
16416 {"xc", PSR_x
| PSR_c
},
16417 {"cf", PSR_c
| PSR_f
},
16418 {"cs", PSR_c
| PSR_s
},
16419 {"cx", PSR_c
| PSR_x
},
16420 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16421 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16422 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16423 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16424 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16425 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16426 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16427 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16428 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16429 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16430 {"scf", PSR_s
| PSR_c
| PSR_f
},
16431 {"scx", PSR_s
| PSR_c
| PSR_x
},
16432 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16433 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16434 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16435 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16436 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16437 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16438 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16439 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16440 {"csf", PSR_c
| PSR_s
| PSR_f
},
16441 {"csx", PSR_c
| PSR_s
| PSR_x
},
16442 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16443 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16444 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16445 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16446 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16447 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16448 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16449 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16450 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16451 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16452 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16453 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16454 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16455 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16456 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16457 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16458 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16459 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16460 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16461 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16462 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16463 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16464 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16465 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16466 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16467 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16471 {"nzcvqg", PSR_s
| PSR_f
}
16474 /* Table of V7M psr names. */
16475 static const struct asm_psr v7m_psrs
[] =
16477 {"apsr", 0 }, {"APSR", 0 },
16478 {"iapsr", 1 }, {"IAPSR", 1 },
16479 {"eapsr", 2 }, {"EAPSR", 2 },
16480 {"psr", 3 }, {"PSR", 3 },
16481 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16482 {"ipsr", 5 }, {"IPSR", 5 },
16483 {"epsr", 6 }, {"EPSR", 6 },
16484 {"iepsr", 7 }, {"IEPSR", 7 },
16485 {"msp", 8 }, {"MSP", 8 },
16486 {"psp", 9 }, {"PSP", 9 },
16487 {"primask", 16}, {"PRIMASK", 16},
16488 {"basepri", 17}, {"BASEPRI", 17},
16489 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16490 {"faultmask", 19}, {"FAULTMASK", 19},
16491 {"control", 20}, {"CONTROL", 20}
16494 /* Table of all shift-in-operand names. */
16495 static const struct asm_shift_name shift_names
[] =
16497 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16498 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16499 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16500 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16501 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16502 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16505 /* Table of all explicit relocation names. */
16507 static struct reloc_entry reloc_names
[] =
16509 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16510 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16511 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16512 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16513 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16514 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16515 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16516 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16517 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16518 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16519 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16520 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16524 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16525 static const struct asm_cond conds
[] =
16529 {"cs", 0x2}, {"hs", 0x2},
16530 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16544 static struct asm_barrier_opt barrier_opt_names
[] =
16546 { "sy", 0xf }, { "SY", 0xf },
16547 { "un", 0x7 }, { "UN", 0x7 },
16548 { "st", 0xe }, { "ST", 0xe },
16549 { "unst", 0x6 }, { "UNST", 0x6 },
16550 { "ish", 0xb }, { "ISH", 0xb },
16551 { "sh", 0xb }, { "SH", 0xb },
16552 { "ishst", 0xa }, { "ISHST", 0xa },
16553 { "shst", 0xa }, { "SHST", 0xa },
16554 { "nsh", 0x7 }, { "NSH", 0x7 },
16555 { "nshst", 0x6 }, { "NSHST", 0x6 },
16556 { "osh", 0x3 }, { "OSH", 0x3 },
16557 { "oshst", 0x2 }, { "OSHST", 0x2 }
16560 /* Table of ARM-format instructions. */
16562 /* Macros for gluing together operand strings. N.B. In all cases
16563 other than OPS0, the trailing OP_stop comes from default
16564 zero-initialization of the unspecified elements of the array. */
16565 #define OPS0() { OP_stop, }
16566 #define OPS1(a) { OP_##a, }
16567 #define OPS2(a,b) { OP_##a,OP_##b, }
16568 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16569 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16570 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16571 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16573 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16574 This is useful when mixing operands for ARM and THUMB, i.e. using the
16575 MIX_ARM_THUMB_OPERANDS macro.
16576 In order to use these macros, prefix the number of operands with _
16578 #define OPS_1(a) { a, }
16579 #define OPS_2(a,b) { a,b, }
16580 #define OPS_3(a,b,c) { a,b,c, }
16581 #define OPS_4(a,b,c,d) { a,b,c,d, }
16582 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16583 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16585 /* These macros abstract out the exact format of the mnemonic table and
16586 save some repeated characters. */
16588 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16589 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16590 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16591 THUMB_VARIANT, do_##ae, do_##te }
16593 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16594 a T_MNEM_xyz enumerator. */
16595 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16596 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16597 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16598 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16600 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16601 infix after the third character. */
16602 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16603 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16604 THUMB_VARIANT, do_##ae, do_##te }
16605 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16606 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16607 THUMB_VARIANT, do_##ae, do_##te }
16608 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16609 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16610 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16611 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16612 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16613 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16614 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16615 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16617 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16618 appear in the condition table. */
16619 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16620 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16621 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16623 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16624 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16625 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16626 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16627 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16628 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16629 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16630 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16631 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16632 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16633 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16634 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16635 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16636 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16637 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16638 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16639 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16640 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16641 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16642 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16644 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16645 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16646 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16647 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16649 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16650 field is still 0xE. Many of the Thumb variants can be executed
16651 conditionally, so this is checked separately. */
16652 #define TUE(mnem, op, top, nops, ops, ae, te) \
16653 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16654 THUMB_VARIANT, do_##ae, do_##te }
16656 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16657 condition code field. */
16658 #define TUF(mnem, op, top, nops, ops, ae, te) \
16659 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16660 THUMB_VARIANT, do_##ae, do_##te }
16662 /* ARM-only variants of all the above. */
16663 #define CE(mnem, op, nops, ops, ae) \
16664 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16666 #define C3(mnem, op, nops, ops, ae) \
16667 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16669 /* Legacy mnemonics that always have conditional infix after the third
16671 #define CL(mnem, op, nops, ops, ae) \
16672 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16673 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16675 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16676 #define cCE(mnem, op, nops, ops, ae) \
16677 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16679 /* Legacy coprocessor instructions where conditional infix and conditional
16680 suffix are ambiguous. For consistency this includes all FPA instructions,
16681 not just the potentially ambiguous ones. */
16682 #define cCL(mnem, op, nops, ops, ae) \
16683 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16684 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16686 /* Coprocessor, takes either a suffix or a position-3 infix
16687 (for an FPA corner case). */
16688 #define C3E(mnem, op, nops, ops, ae) \
16689 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16690 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16692 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16693 { m1 #m2 m3, OPS##nops ops, \
16694 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16695 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16697 #define CM(m1, m2, op, nops, ops, ae) \
16698 xCM_ (m1, , m2, op, nops, ops, ae), \
16699 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16700 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16701 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16702 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16703 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16704 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16705 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16706 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16707 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16708 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16709 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16710 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16711 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16712 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16713 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16714 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16715 xCM_ (m1, le, m2, op, nops, ops, ae), \
16716 xCM_ (m1, al, m2, op, nops, ops, ae)
16718 #define UE(mnem, op, nops, ops, ae) \
16719 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16721 #define UF(mnem, op, nops, ops, ae) \
16722 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16724 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16725 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16726 use the same encoding function for each. */
16727 #define NUF(mnem, op, nops, ops, enc) \
16728 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16729 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16731 /* Neon data processing, version which indirects through neon_enc_tab for
16732 the various overloaded versions of opcodes. */
16733 #define nUF(mnem, op, nops, ops, enc) \
16734 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16735 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16737 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16739 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16740 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16741 THUMB_VARIANT, do_##enc, do_##enc }
16743 #define NCE(mnem, op, nops, ops, enc) \
16744 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16746 #define NCEF(mnem, op, nops, ops, enc) \
16747 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16749 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16750 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16751 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16752 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16754 #define nCE(mnem, op, nops, ops, enc) \
16755 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16757 #define nCEF(mnem, op, nops, ops, enc) \
16758 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16762 static const struct asm_opcode insns
[] =
16764 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16765 #define THUMB_VARIANT &arm_ext_v4t
16766 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16767 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16768 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16769 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16770 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16771 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16772 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16773 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16774 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16775 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16776 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16777 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16778 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16779 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16780 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16781 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16783 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16784 for setting PSR flag bits. They are obsolete in V6 and do not
16785 have Thumb equivalents. */
16786 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16787 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16788 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16789 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16790 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16791 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16792 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16793 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16794 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16796 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16797 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16798 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16799 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16801 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16802 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16803 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16805 OP_ADDRGLDR
),ldst
, t_ldst
),
16806 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16808 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16809 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16810 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16811 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16812 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16813 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16815 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16816 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16817 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16818 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16821 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16822 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16823 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16825 /* Thumb-compatibility pseudo ops. */
16826 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16827 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16828 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16829 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16830 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16831 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16832 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16833 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16834 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16835 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16836 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16837 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16839 /* These may simplify to neg. */
16840 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16841 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16843 #undef THUMB_VARIANT
16844 #define THUMB_VARIANT & arm_ext_v6
16846 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16848 /* V1 instructions with no Thumb analogue prior to V6T2. */
16849 #undef THUMB_VARIANT
16850 #define THUMB_VARIANT & arm_ext_v6t2
16852 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16853 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16854 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16856 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16857 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16858 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16859 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16861 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16862 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16864 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16865 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16867 /* V1 instructions with no Thumb analogue at all. */
16868 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16869 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16871 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16872 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16873 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16874 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16875 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16876 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16877 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16878 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16881 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16882 #undef THUMB_VARIANT
16883 #define THUMB_VARIANT & arm_ext_v4t
16885 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16886 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16888 #undef THUMB_VARIANT
16889 #define THUMB_VARIANT & arm_ext_v6t2
16891 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16892 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16894 /* Generic coprocessor instructions. */
16895 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16896 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16897 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16898 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16899 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16900 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16901 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16904 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16906 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16907 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16910 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16911 #undef THUMB_VARIANT
16912 #define THUMB_VARIANT & arm_ext_msr
16914 TCE("mrs", 1000000, f3e08000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16915 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16918 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16919 #undef THUMB_VARIANT
16920 #define THUMB_VARIANT & arm_ext_v6t2
16922 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16923 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16924 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16925 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16926 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16927 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16928 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16929 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16932 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16933 #undef THUMB_VARIANT
16934 #define THUMB_VARIANT & arm_ext_v4t
16936 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16937 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16938 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16939 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16940 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16941 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16944 #define ARM_VARIANT & arm_ext_v4t_5
16946 /* ARM Architecture 4T. */
16947 /* Note: bx (and blx) are required on V5, even if the processor does
16948 not support Thumb. */
16949 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16952 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16953 #undef THUMB_VARIANT
16954 #define THUMB_VARIANT & arm_ext_v5t
16956 /* Note: blx has 2 variants; the .value coded here is for
16957 BLX(2). Only this variant has conditional execution. */
16958 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16959 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16961 #undef THUMB_VARIANT
16962 #define THUMB_VARIANT & arm_ext_v6t2
16964 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16965 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16966 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16967 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16968 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16969 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16970 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16971 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16974 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16975 #undef THUMB_VARIANT
16976 #define THUMB_VARIANT &arm_ext_v5exp
16978 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16979 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16980 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16981 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16983 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16984 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16986 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16987 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16988 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16989 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16991 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16992 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16993 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16994 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16996 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16997 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16999 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17000 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17001 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17002 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17005 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17006 #undef THUMB_VARIANT
17007 #define THUMB_VARIANT &arm_ext_v6t2
17009 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17010 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17012 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17013 ADDRGLDRS
), ldrd
, t_ldstd
),
17015 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17016 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17019 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17021 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17024 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17025 #undef THUMB_VARIANT
17026 #define THUMB_VARIANT & arm_ext_v6
17028 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17029 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17030 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17031 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17032 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17033 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17034 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17035 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17036 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17037 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17039 #undef THUMB_VARIANT
17040 #define THUMB_VARIANT & arm_ext_v6t2
17042 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17043 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17045 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17046 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17048 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17049 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17051 /* ARM V6 not included in V7M. */
17052 #undef THUMB_VARIANT
17053 #define THUMB_VARIANT & arm_ext_v6_notm
17054 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17055 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17056 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17057 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17058 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17059 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17060 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17061 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17062 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17063 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17064 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17065 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17067 /* ARM V6 not included in V7M (eg. integer SIMD). */
17068 #undef THUMB_VARIANT
17069 #define THUMB_VARIANT & arm_ext_v6_dsp
17070 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17071 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17072 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17073 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17074 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17075 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17076 /* Old name for QASX. */
17077 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17078 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17079 /* Old name for QSAX. */
17080 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17081 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17082 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17083 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17084 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17085 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17086 /* Old name for SASX. */
17087 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17088 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17089 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17090 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17091 /* Old name for SHASX. */
17092 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17093 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17094 /* Old name for SHSAX. */
17095 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17096 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17097 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17098 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17099 /* Old name for SSAX. */
17100 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17101 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17102 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17103 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17104 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17105 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17106 /* Old name for UASX. */
17107 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17108 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17109 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17110 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17111 /* Old name for UHASX. */
17112 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17113 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17114 /* Old name for UHSAX. */
17115 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17116 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17117 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17118 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17119 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17120 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17121 /* Old name for UQASX. */
17122 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17123 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17124 /* Old name for UQSAX. */
17125 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17126 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17127 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17128 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17129 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17130 /* Old name for USAX. */
17131 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17132 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17133 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17134 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17135 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17136 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17137 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17138 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17139 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17140 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17141 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17142 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17143 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17144 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17145 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17146 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17147 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17148 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17149 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17150 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17151 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17152 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17153 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17154 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17155 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17156 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17157 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17158 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17159 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17160 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17161 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17162 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17163 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17164 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17167 #define ARM_VARIANT & arm_ext_v6k
17168 #undef THUMB_VARIANT
17169 #define THUMB_VARIANT & arm_ext_v6k
17171 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17172 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17173 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17174 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17176 #undef THUMB_VARIANT
17177 #define THUMB_VARIANT & arm_ext_v6_notm
17178 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17180 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17181 RRnpcb
), strexd
, t_strexd
),
17183 #undef THUMB_VARIANT
17184 #define THUMB_VARIANT & arm_ext_v6t2
17185 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17187 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17189 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17191 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17193 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17196 #define ARM_VARIANT & arm_ext_sec
17197 #undef THUMB_VARIANT
17198 #define THUMB_VARIANT & arm_ext_sec
17200 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17203 #define ARM_VARIANT & arm_ext_virt
17204 #undef THUMB_VARIANT
17205 #define THUMB_VARIANT & arm_ext_virt
17207 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17208 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17211 #define ARM_VARIANT & arm_ext_v6t2
17212 #undef THUMB_VARIANT
17213 #define THUMB_VARIANT & arm_ext_v6t2
17215 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17216 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17217 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17218 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17220 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17221 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17222 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17223 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17225 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17226 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17227 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17228 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17230 /* Thumb-only instructions. */
17232 #define ARM_VARIANT NULL
17233 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17234 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17236 /* ARM does not really have an IT instruction, so always allow it.
17237 The opcode is copied from Thumb in order to allow warnings in
17238 -mimplicit-it=[never | arm] modes. */
17240 #define ARM_VARIANT & arm_ext_v1
17242 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17243 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17244 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17245 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17246 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17247 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17248 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17249 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17250 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17251 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17252 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17253 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17254 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17255 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17256 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17257 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17258 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17259 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17261 /* Thumb2 only instructions. */
17263 #define ARM_VARIANT NULL
17265 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17266 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17267 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17268 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17269 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17270 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17272 /* Hardware division instructions. */
17274 #define ARM_VARIANT & arm_ext_adiv
17275 #undef THUMB_VARIANT
17276 #define THUMB_VARIANT & arm_ext_div
17278 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17279 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17281 /* ARM V6M/V7 instructions. */
17283 #define ARM_VARIANT & arm_ext_barrier
17284 #undef THUMB_VARIANT
17285 #define THUMB_VARIANT & arm_ext_barrier
17287 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17288 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17289 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17291 /* ARM V7 instructions. */
17293 #define ARM_VARIANT & arm_ext_v7
17294 #undef THUMB_VARIANT
17295 #define THUMB_VARIANT & arm_ext_v7
17297 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17298 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17301 #define ARM_VARIANT & arm_ext_mp
17302 #undef THUMB_VARIANT
17303 #define THUMB_VARIANT & arm_ext_mp
17305 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17308 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17310 cCE("wfs", e200110
, 1, (RR
), rd
),
17311 cCE("rfs", e300110
, 1, (RR
), rd
),
17312 cCE("wfc", e400110
, 1, (RR
), rd
),
17313 cCE("rfc", e500110
, 1, (RR
), rd
),
17315 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17316 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17317 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17318 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17320 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17321 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17322 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17323 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17325 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17326 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17327 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17328 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17329 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17330 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17331 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17332 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17333 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17334 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17335 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17336 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17338 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17339 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17340 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17341 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17342 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17343 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17344 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17345 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17346 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17347 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17348 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17349 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17351 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17352 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17353 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17354 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17355 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17356 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17357 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17358 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17359 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17360 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17361 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17362 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17364 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17365 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17366 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17367 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17368 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17369 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17370 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17371 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17372 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17373 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17374 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17375 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17377 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17378 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17379 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17380 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17381 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17382 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17383 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17384 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17385 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17386 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17387 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17388 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17390 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17391 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17392 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17393 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17394 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17395 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17396 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17397 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17398 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17399 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17400 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17401 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17403 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17404 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17405 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17406 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17407 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17408 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17409 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17410 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17411 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17412 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17413 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17414 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17416 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17417 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17418 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17419 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17420 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17421 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17422 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17423 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17424 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17425 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17426 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17427 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17429 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17430 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17431 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17432 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17433 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17434 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17435 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17436 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17437 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17438 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17439 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17440 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17442 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17443 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17444 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17445 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17446 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17447 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17448 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17449 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17450 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17451 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17452 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17453 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17455 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17456 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17457 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17458 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17459 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17460 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17461 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17462 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17463 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17464 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17465 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17466 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17468 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17469 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17470 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17471 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17472 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17473 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17474 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17475 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17476 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17477 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17478 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17479 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17481 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17482 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17483 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17484 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17485 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17486 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17487 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17488 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17489 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17490 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17491 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17492 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17494 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17495 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17496 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17497 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17498 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17499 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17500 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17501 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17502 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17503 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17504 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17505 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17507 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17508 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17509 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17510 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17511 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17512 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17513 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17514 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17515 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17516 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17517 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17518 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17520 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17521 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17522 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17523 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17524 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17525 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17526 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17527 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17528 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17529 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17530 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17531 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17533 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17534 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17535 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17536 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17537 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17538 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17539 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17540 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17541 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17542 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17543 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17544 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17546 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17547 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17548 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17549 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17550 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17551 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17552 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17553 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17554 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17555 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17556 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17557 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17559 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17560 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17561 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17562 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17563 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17564 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17565 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17566 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17567 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17568 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17569 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17570 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17572 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17573 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17574 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17575 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17576 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17577 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17578 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17579 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17580 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17581 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17582 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17583 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17585 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17586 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17587 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17588 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17589 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17590 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17591 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17592 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17593 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17594 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17595 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17596 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17598 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17599 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17600 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17601 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17602 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17603 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17604 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17605 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17606 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17607 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17608 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17609 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17611 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17612 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17613 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17614 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17615 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17616 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17617 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17618 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17619 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17620 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17621 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17622 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17624 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17625 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17626 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17627 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17628 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17629 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17630 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17631 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17632 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17633 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17634 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17635 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17637 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17638 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17639 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17640 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17641 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17642 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17643 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17644 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17645 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17646 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17647 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17648 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17650 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17651 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17652 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17653 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17654 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17655 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17656 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17657 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17658 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17659 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17660 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17661 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17663 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17664 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17665 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17666 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17667 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17668 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17669 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17670 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17671 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17672 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17673 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17674 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17676 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17677 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17678 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17679 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17680 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17681 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17682 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17683 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17684 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17685 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17686 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17687 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17689 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17690 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17691 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17692 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17693 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17694 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17695 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17696 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17697 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17698 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17699 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17700 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17702 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17703 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17704 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17705 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17707 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17708 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17709 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17710 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17711 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17712 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17713 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17714 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17715 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17716 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17717 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17718 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17720 /* The implementation of the FIX instruction is broken on some
17721 assemblers, in that it accepts a precision specifier as well as a
17722 rounding specifier, despite the fact that this is meaningless.
17723 To be more compatible, we accept it as well, though of course it
17724 does not set any bits. */
17725 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17726 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17727 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17728 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17729 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17730 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17731 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17732 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17733 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17734 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17735 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17736 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17737 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17739 /* Instructions that were new with the real FPA, call them V2. */
17741 #define ARM_VARIANT & fpu_fpa_ext_v2
17743 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17744 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17745 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17746 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17747 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17748 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17751 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17753 /* Moves and type conversions. */
17754 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17755 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17756 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17757 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17758 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17759 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17760 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17761 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17762 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17763 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17764 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17765 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17766 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17767 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17769 /* Memory operations. */
17770 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17771 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17772 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17773 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17774 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17775 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17776 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17777 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17778 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17779 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17780 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17781 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17782 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17783 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17784 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17785 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17786 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17787 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17789 /* Monadic operations. */
17790 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17791 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17792 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17794 /* Dyadic operations. */
17795 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17796 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17797 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17798 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17799 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17800 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17801 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17802 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17803 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17806 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17807 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17808 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17809 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17811 /* Double precision load/store are still present on single precision
17812 implementations. */
17813 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17814 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17815 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17816 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17817 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17818 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17819 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17820 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17821 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17822 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17825 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17827 /* Moves and type conversions. */
17828 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17829 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17830 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17831 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17832 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17833 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17834 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17835 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17836 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17837 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17838 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17839 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17840 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17842 /* Monadic operations. */
17843 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17844 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17845 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17847 /* Dyadic operations. */
17848 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17849 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17850 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17851 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17852 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17853 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17854 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17855 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17856 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17859 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17860 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17861 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17862 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17865 #define ARM_VARIANT & fpu_vfp_ext_v2
17867 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17868 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17869 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17870 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17872 /* Instructions which may belong to either the Neon or VFP instruction sets.
17873 Individual encoder functions perform additional architecture checks. */
17875 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17876 #undef THUMB_VARIANT
17877 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17879 /* These mnemonics are unique to VFP. */
17880 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17881 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17882 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17883 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17884 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17885 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17886 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17887 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17888 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17889 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17891 /* Mnemonics shared by Neon and VFP. */
17892 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17893 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17894 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17896 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17897 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17899 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17900 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17902 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17903 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17904 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17905 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17906 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17907 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17908 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17909 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17911 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17912 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17913 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17914 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17917 /* NOTE: All VMOV encoding is special-cased! */
17918 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17919 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17921 #undef THUMB_VARIANT
17922 #define THUMB_VARIANT & fpu_neon_ext_v1
17924 #define ARM_VARIANT & fpu_neon_ext_v1
17926 /* Data processing with three registers of the same length. */
17927 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17928 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17929 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17930 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17931 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17932 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17933 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17934 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17935 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17936 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17937 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17938 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17939 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17940 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17941 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17942 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17943 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17944 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17945 /* If not immediate, fall back to neon_dyadic_i64_su.
17946 shl_imm should accept I8 I16 I32 I64,
17947 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17948 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17949 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17950 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17951 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17952 /* Logic ops, types optional & ignored. */
17953 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17954 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17955 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17956 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17957 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17958 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17959 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17960 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17961 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17962 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17963 /* Bitfield ops, untyped. */
17964 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17965 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17966 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17967 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17968 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17969 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17970 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17971 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17972 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17973 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17974 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17975 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17976 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17977 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17978 back to neon_dyadic_if_su. */
17979 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17980 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17981 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17982 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17983 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17984 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17985 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17986 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17987 /* Comparison. Type I8 I16 I32 F32. */
17988 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17989 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17990 /* As above, D registers only. */
17991 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17992 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17993 /* Int and float variants, signedness unimportant. */
17994 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17995 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17996 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17997 /* Add/sub take types I8 I16 I32 I64 F32. */
17998 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17999 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18000 /* vtst takes sizes 8, 16, 32. */
18001 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18002 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18003 /* VMUL takes I8 I16 I32 F32 P8. */
18004 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18005 /* VQD{R}MULH takes S16 S32. */
18006 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18007 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18008 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18009 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18010 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18011 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18012 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18013 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18014 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18015 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18016 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18017 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18018 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18019 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18020 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18021 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18023 /* Two address, int/float. Types S8 S16 S32 F32. */
18024 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18025 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18027 /* Data processing with two registers and a shift amount. */
18028 /* Right shifts, and variants with rounding.
18029 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18030 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18031 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18032 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18033 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18034 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18035 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18036 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18037 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18038 /* Shift and insert. Sizes accepted 8 16 32 64. */
18039 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18040 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18041 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18042 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18043 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18044 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18045 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18046 /* Right shift immediate, saturating & narrowing, with rounding variants.
18047 Types accepted S16 S32 S64 U16 U32 U64. */
18048 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18049 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18050 /* As above, unsigned. Types accepted S16 S32 S64. */
18051 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18052 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18053 /* Right shift narrowing. Types accepted I16 I32 I64. */
18054 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18055 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18056 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18057 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18058 /* CVT with optional immediate for fixed-point variant. */
18059 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18061 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18062 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18064 /* Data processing, three registers of different lengths. */
18065 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18066 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18067 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18068 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18069 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18070 /* If not scalar, fall back to neon_dyadic_long.
18071 Vector types as above, scalar types S16 S32 U16 U32. */
18072 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18073 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18074 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18075 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18076 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18077 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18078 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18079 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18080 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18081 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18082 /* Saturating doubling multiplies. Types S16 S32. */
18083 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18084 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18085 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18086 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18087 S16 S32 U16 U32. */
18088 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18090 /* Extract. Size 8. */
18091 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18092 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18094 /* Two registers, miscellaneous. */
18095 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18096 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18097 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18098 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18099 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18100 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18101 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18102 /* Vector replicate. Sizes 8 16 32. */
18103 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18104 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18105 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18106 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18107 /* VMOVN. Types I16 I32 I64. */
18108 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18109 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18110 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18111 /* VQMOVUN. Types S16 S32 S64. */
18112 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18113 /* VZIP / VUZP. Sizes 8 16 32. */
18114 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18115 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18116 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18117 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18118 /* VQABS / VQNEG. Types S8 S16 S32. */
18119 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18120 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18121 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18122 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18123 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18124 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18125 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18126 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18127 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18128 /* Reciprocal estimates. Types U32 F32. */
18129 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18130 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18131 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18132 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18133 /* VCLS. Types S8 S16 S32. */
18134 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18135 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18136 /* VCLZ. Types I8 I16 I32. */
18137 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18138 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18139 /* VCNT. Size 8. */
18140 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18141 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18142 /* Two address, untyped. */
18143 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18144 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18145 /* VTRN. Sizes 8 16 32. */
18146 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18147 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18149 /* Table lookup. Size 8. */
18150 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18151 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18153 #undef THUMB_VARIANT
18154 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18156 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18158 /* Neon element/structure load/store. */
18159 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18160 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18161 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18162 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18163 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18164 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18165 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18166 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18168 #undef THUMB_VARIANT
18169 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18171 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18172 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18173 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18174 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18175 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18176 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18177 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18178 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18179 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18180 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18182 #undef THUMB_VARIANT
18183 #define THUMB_VARIANT & fpu_vfp_ext_v3
18185 #define ARM_VARIANT & fpu_vfp_ext_v3
18187 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18188 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18189 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18190 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18191 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18192 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18193 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18194 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18195 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18198 #define ARM_VARIANT &fpu_vfp_ext_fma
18199 #undef THUMB_VARIANT
18200 #define THUMB_VARIANT &fpu_vfp_ext_fma
18201 /* Mnemonics shared by Neon and VFP. These are included in the
18202 VFP FMA variant; NEON and VFP FMA always includes the NEON
18203 FMA instructions. */
18204 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18205 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18206 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18207 the v form should always be used. */
18208 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18209 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18210 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18211 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18212 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18213 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18215 #undef THUMB_VARIANT
18217 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18219 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18220 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18221 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18222 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18223 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18224 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18225 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18226 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18229 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18231 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18232 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18233 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18234 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18235 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18236 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18237 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18238 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18239 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18240 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18241 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18242 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18243 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18244 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18245 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18246 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18247 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18248 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18249 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18250 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18251 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18252 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18253 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18254 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18255 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18256 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18257 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18258 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18259 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18260 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18261 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18262 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18263 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18264 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18265 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18266 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18267 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18268 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18269 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18270 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18271 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18272 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18273 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18274 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18275 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18276 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18277 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18278 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18279 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18280 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18281 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18282 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18283 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18284 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18285 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18286 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18287 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18288 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18289 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18290 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18291 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18292 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18293 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18294 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18295 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18296 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18297 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18298 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18299 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18300 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18301 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18302 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18303 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18304 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18305 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18306 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18307 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18308 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18309 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18310 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18311 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18312 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18313 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18314 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18315 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18316 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18317 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18318 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18319 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18320 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18321 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18322 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18323 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18324 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18325 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18326 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18327 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18328 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18329 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18330 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18331 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18332 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18333 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18334 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18335 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18336 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18337 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18338 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18339 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18340 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18341 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18342 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18343 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18344 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18345 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18346 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18347 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18348 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18349 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18350 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18351 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18352 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18353 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18354 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18355 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18356 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18357 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18358 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18359 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18360 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18361 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18362 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18363 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18364 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18365 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18366 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18367 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18368 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18369 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18370 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18371 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18372 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18373 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18374 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18375 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18376 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18377 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18378 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18379 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18380 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18381 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18382 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18383 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18384 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18385 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18386 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18387 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18388 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18389 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18390 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18391 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18392 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18395 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18397 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18398 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18399 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18400 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18401 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18402 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18403 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18404 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18405 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18406 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18407 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18408 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18409 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18410 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18411 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18412 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18413 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18414 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18415 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18416 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18417 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18418 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18419 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18420 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18421 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18422 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18423 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18424 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18425 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18426 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18427 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18428 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18429 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18430 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18431 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18432 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18433 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18434 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18435 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18436 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18437 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18438 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18439 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18440 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18441 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18442 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18443 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18444 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18445 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18446 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18447 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18448 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18449 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18450 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18451 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18452 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18453 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18456 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18458 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18459 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18460 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18461 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18462 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18463 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18464 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18465 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18466 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18467 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18468 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18469 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18470 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18471 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18472 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18473 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18474 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18475 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18476 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18477 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18478 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18479 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18480 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18481 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18482 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18483 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18484 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18485 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18486 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18487 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18488 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18489 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18490 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18491 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18492 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18493 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18494 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18495 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18496 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18497 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18498 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18499 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18500 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18501 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18502 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18503 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18504 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18505 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18506 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18507 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18508 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18509 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18510 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18511 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18512 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18513 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18514 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18515 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18516 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18517 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18518 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18519 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18520 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18521 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18522 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18523 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18524 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18525 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18526 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18527 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18528 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18529 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18530 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18531 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18532 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18533 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18536 #undef THUMB_VARIANT
18563 /* MD interface: bits in the object file. */
18565 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18566 for use in the a.out file, and stores them in the array pointed to by buf.
18567 This knows about the endian-ness of the target machine and does
18568 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18569 2 (short) and 4 (long) Floating numbers are put out as a series of
18570 LITTLENUMS (shorts, here at least). */
18573 md_number_to_chars (char * buf
, valueT val
, int n
)
18575 if (target_big_endian
)
18576 number_to_chars_bigendian (buf
, val
, n
);
18578 number_to_chars_littleendian (buf
, val
, n
);
18582 md_chars_to_number (char * buf
, int n
)
18585 unsigned char * where
= (unsigned char *) buf
;
18587 if (target_big_endian
)
18592 result
|= (*where
++ & 255);
18600 result
|= (where
[n
] & 255);
18607 /* MD interface: Sections. */
18609 /* Estimate the size of a frag before relaxing. Assume everything fits in
18613 md_estimate_size_before_relax (fragS
* fragp
,
18614 segT segtype ATTRIBUTE_UNUSED
)
18620 /* Convert a machine dependent frag. */
18623 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18625 unsigned long insn
;
18626 unsigned long old_op
;
18634 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18636 old_op
= bfd_get_16(abfd
, buf
);
18637 if (fragp
->fr_symbol
)
18639 exp
.X_op
= O_symbol
;
18640 exp
.X_add_symbol
= fragp
->fr_symbol
;
18644 exp
.X_op
= O_constant
;
18646 exp
.X_add_number
= fragp
->fr_offset
;
18647 opcode
= fragp
->fr_subtype
;
18650 case T_MNEM_ldr_pc
:
18651 case T_MNEM_ldr_pc2
:
18652 case T_MNEM_ldr_sp
:
18653 case T_MNEM_str_sp
:
18660 if (fragp
->fr_var
== 4)
18662 insn
= THUMB_OP32 (opcode
);
18663 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18665 insn
|= (old_op
& 0x700) << 4;
18669 insn
|= (old_op
& 7) << 12;
18670 insn
|= (old_op
& 0x38) << 13;
18672 insn
|= 0x00000c00;
18673 put_thumb32_insn (buf
, insn
);
18674 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18678 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18680 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18683 if (fragp
->fr_var
== 4)
18685 insn
= THUMB_OP32 (opcode
);
18686 insn
|= (old_op
& 0xf0) << 4;
18687 put_thumb32_insn (buf
, insn
);
18688 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18692 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18693 exp
.X_add_number
-= 4;
18701 if (fragp
->fr_var
== 4)
18703 int r0off
= (opcode
== T_MNEM_mov
18704 || opcode
== T_MNEM_movs
) ? 0 : 8;
18705 insn
= THUMB_OP32 (opcode
);
18706 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18707 insn
|= (old_op
& 0x700) << r0off
;
18708 put_thumb32_insn (buf
, insn
);
18709 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18713 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18718 if (fragp
->fr_var
== 4)
18720 insn
= THUMB_OP32(opcode
);
18721 put_thumb32_insn (buf
, insn
);
18722 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18725 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18729 if (fragp
->fr_var
== 4)
18731 insn
= THUMB_OP32(opcode
);
18732 insn
|= (old_op
& 0xf00) << 14;
18733 put_thumb32_insn (buf
, insn
);
18734 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18737 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18740 case T_MNEM_add_sp
:
18741 case T_MNEM_add_pc
:
18742 case T_MNEM_inc_sp
:
18743 case T_MNEM_dec_sp
:
18744 if (fragp
->fr_var
== 4)
18746 /* ??? Choose between add and addw. */
18747 insn
= THUMB_OP32 (opcode
);
18748 insn
|= (old_op
& 0xf0) << 4;
18749 put_thumb32_insn (buf
, insn
);
18750 if (opcode
== T_MNEM_add_pc
)
18751 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18753 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18756 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18764 if (fragp
->fr_var
== 4)
18766 insn
= THUMB_OP32 (opcode
);
18767 insn
|= (old_op
& 0xf0) << 4;
18768 insn
|= (old_op
& 0xf) << 16;
18769 put_thumb32_insn (buf
, insn
);
18770 if (insn
& (1 << 20))
18771 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18773 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18776 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18782 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18783 (enum bfd_reloc_code_real
) reloc_type
);
18784 fixp
->fx_file
= fragp
->fr_file
;
18785 fixp
->fx_line
= fragp
->fr_line
;
18786 fragp
->fr_fix
+= fragp
->fr_var
;
18789 /* Return the size of a relaxable immediate operand instruction.
18790 SHIFT and SIZE specify the form of the allowable immediate. */
18792 relax_immediate (fragS
*fragp
, int size
, int shift
)
18798 /* ??? Should be able to do better than this. */
18799 if (fragp
->fr_symbol
)
18802 low
= (1 << shift
) - 1;
18803 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18804 offset
= fragp
->fr_offset
;
18805 /* Force misaligned offsets to 32-bit variant. */
18808 if (offset
& ~mask
)
18813 /* Get the address of a symbol during relaxation. */
18815 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18821 sym
= fragp
->fr_symbol
;
18822 sym_frag
= symbol_get_frag (sym
);
18823 know (S_GET_SEGMENT (sym
) != absolute_section
18824 || sym_frag
== &zero_address_frag
);
18825 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18827 /* If frag has yet to be reached on this pass, assume it will
18828 move by STRETCH just as we did. If this is not so, it will
18829 be because some frag between grows, and that will force
18833 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18837 /* Adjust stretch for any alignment frag. Note that if have
18838 been expanding the earlier code, the symbol may be
18839 defined in what appears to be an earlier frag. FIXME:
18840 This doesn't handle the fr_subtype field, which specifies
18841 a maximum number of bytes to skip when doing an
18843 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18845 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18848 stretch
= - ((- stretch
)
18849 & ~ ((1 << (int) f
->fr_offset
) - 1));
18851 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18863 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18866 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18871 /* Assume worst case for symbols not known to be in the same section. */
18872 if (fragp
->fr_symbol
== NULL
18873 || !S_IS_DEFINED (fragp
->fr_symbol
)
18874 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18875 || S_IS_WEAK (fragp
->fr_symbol
))
18878 val
= relaxed_symbol_addr (fragp
, stretch
);
18879 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18880 addr
= (addr
+ 4) & ~3;
18881 /* Force misaligned targets to 32-bit variant. */
18885 if (val
< 0 || val
> 1020)
18890 /* Return the size of a relaxable add/sub immediate instruction. */
18892 relax_addsub (fragS
*fragp
, asection
*sec
)
18897 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18898 op
= bfd_get_16(sec
->owner
, buf
);
18899 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18900 return relax_immediate (fragp
, 8, 0);
18902 return relax_immediate (fragp
, 3, 0);
18906 /* Return the size of a relaxable branch instruction. BITS is the
18907 size of the offset field in the narrow instruction. */
18910 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18916 /* Assume worst case for symbols not known to be in the same section. */
18917 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18918 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18919 || S_IS_WEAK (fragp
->fr_symbol
))
18923 if (S_IS_DEFINED (fragp
->fr_symbol
)
18924 && ARM_IS_FUNC (fragp
->fr_symbol
))
18928 val
= relaxed_symbol_addr (fragp
, stretch
);
18929 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18932 /* Offset is a signed value *2 */
18934 if (val
>= limit
|| val
< -limit
)
18940 /* Relax a machine dependent frag. This returns the amount by which
18941 the current size of the frag should change. */
18944 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18949 oldsize
= fragp
->fr_var
;
18950 switch (fragp
->fr_subtype
)
18952 case T_MNEM_ldr_pc2
:
18953 newsize
= relax_adr (fragp
, sec
, stretch
);
18955 case T_MNEM_ldr_pc
:
18956 case T_MNEM_ldr_sp
:
18957 case T_MNEM_str_sp
:
18958 newsize
= relax_immediate (fragp
, 8, 2);
18962 newsize
= relax_immediate (fragp
, 5, 2);
18966 newsize
= relax_immediate (fragp
, 5, 1);
18970 newsize
= relax_immediate (fragp
, 5, 0);
18973 newsize
= relax_adr (fragp
, sec
, stretch
);
18979 newsize
= relax_immediate (fragp
, 8, 0);
18982 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18985 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18987 case T_MNEM_add_sp
:
18988 case T_MNEM_add_pc
:
18989 newsize
= relax_immediate (fragp
, 8, 2);
18991 case T_MNEM_inc_sp
:
18992 case T_MNEM_dec_sp
:
18993 newsize
= relax_immediate (fragp
, 7, 2);
18999 newsize
= relax_addsub (fragp
, sec
);
19005 fragp
->fr_var
= newsize
;
19006 /* Freeze wide instructions that are at or before the same location as
19007 in the previous pass. This avoids infinite loops.
19008 Don't freeze them unconditionally because targets may be artificially
19009 misaligned by the expansion of preceding frags. */
19010 if (stretch
<= 0 && newsize
> 2)
19012 md_convert_frag (sec
->owner
, sec
, fragp
);
19016 return newsize
- oldsize
;
19019 /* Round up a section size to the appropriate boundary. */
19022 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19025 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19026 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19028 /* For a.out, force the section size to be aligned. If we don't do
19029 this, BFD will align it for us, but it will not write out the
19030 final bytes of the section. This may be a bug in BFD, but it is
19031 easier to fix it here since that is how the other a.out targets
19035 align
= bfd_get_section_alignment (stdoutput
, segment
);
19036 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19043 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19044 of an rs_align_code fragment. */
19047 arm_handle_align (fragS
* fragP
)
19049 static char const arm_noop
[2][2][4] =
19052 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19053 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19056 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19057 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19060 static char const thumb_noop
[2][2][2] =
19063 {0xc0, 0x46}, /* LE */
19064 {0x46, 0xc0}, /* BE */
19067 {0x00, 0xbf}, /* LE */
19068 {0xbf, 0x00} /* BE */
19071 static char const wide_thumb_noop
[2][4] =
19072 { /* Wide Thumb-2 */
19073 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19074 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19077 unsigned bytes
, fix
, noop_size
;
19080 const char *narrow_noop
= NULL
;
19085 if (fragP
->fr_type
!= rs_align_code
)
19088 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19089 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19092 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19093 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19095 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19097 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19099 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19101 narrow_noop
= thumb_noop
[1][target_big_endian
];
19102 noop
= wide_thumb_noop
[target_big_endian
];
19105 noop
= thumb_noop
[0][target_big_endian
];
19113 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19114 [target_big_endian
];
19121 fragP
->fr_var
= noop_size
;
19123 if (bytes
& (noop_size
- 1))
19125 fix
= bytes
& (noop_size
- 1);
19127 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19129 memset (p
, 0, fix
);
19136 if (bytes
& noop_size
)
19138 /* Insert a narrow noop. */
19139 memcpy (p
, narrow_noop
, noop_size
);
19141 bytes
-= noop_size
;
19145 /* Use wide noops for the remainder */
19149 while (bytes
>= noop_size
)
19151 memcpy (p
, noop
, noop_size
);
19153 bytes
-= noop_size
;
19157 fragP
->fr_fix
+= fix
;
19160 /* Called from md_do_align. Used to create an alignment
19161 frag in a code section. */
19164 arm_frag_align_code (int n
, int max
)
19168 /* We assume that there will never be a requirement
19169 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19170 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19175 _("alignments greater than %d bytes not supported in .text sections."),
19176 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19177 as_fatal ("%s", err_msg
);
19180 p
= frag_var (rs_align_code
,
19181 MAX_MEM_FOR_RS_ALIGN_CODE
,
19183 (relax_substateT
) max
,
19190 /* Perform target specific initialisation of a frag.
19191 Note - despite the name this initialisation is not done when the frag
19192 is created, but only when its type is assigned. A frag can be created
19193 and used a long time before its type is set, so beware of assuming that
19194 this initialisationis performed first. */
19198 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19200 /* Record whether this frag is in an ARM or a THUMB area. */
19201 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19204 #else /* OBJ_ELF is defined. */
19206 arm_init_frag (fragS
* fragP
, int max_chars
)
19208 /* If the current ARM vs THUMB mode has not already
19209 been recorded into this frag then do so now. */
19210 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19212 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19214 /* Record a mapping symbol for alignment frags. We will delete this
19215 later if the alignment ends up empty. */
19216 switch (fragP
->fr_type
)
19219 case rs_align_test
:
19221 mapping_state_2 (MAP_DATA
, max_chars
);
19223 case rs_align_code
:
19224 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19232 /* When we change sections we need to issue a new mapping symbol. */
19235 arm_elf_change_section (void)
19237 /* Link an unlinked unwind index table section to the .text section. */
19238 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19239 && elf_linked_to_section (now_seg
) == NULL
)
19240 elf_linked_to_section (now_seg
) = text_section
;
19244 arm_elf_section_type (const char * str
, size_t len
)
19246 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19247 return SHT_ARM_EXIDX
;
19252 /* Code to deal with unwinding tables. */
19254 static void add_unwind_adjustsp (offsetT
);
19256 /* Generate any deferred unwind frame offset. */
19259 flush_pending_unwind (void)
19263 offset
= unwind
.pending_offset
;
19264 unwind
.pending_offset
= 0;
19266 add_unwind_adjustsp (offset
);
19269 /* Add an opcode to this list for this function. Two-byte opcodes should
19270 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19274 add_unwind_opcode (valueT op
, int length
)
19276 /* Add any deferred stack adjustment. */
19277 if (unwind
.pending_offset
)
19278 flush_pending_unwind ();
19280 unwind
.sp_restored
= 0;
19282 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19284 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19285 if (unwind
.opcodes
)
19286 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19287 unwind
.opcode_alloc
);
19289 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19294 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19296 unwind
.opcode_count
++;
19300 /* Add unwind opcodes to adjust the stack pointer. */
19303 add_unwind_adjustsp (offsetT offset
)
19307 if (offset
> 0x200)
19309 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19314 /* Long form: 0xb2, uleb128. */
19315 /* This might not fit in a word so add the individual bytes,
19316 remembering the list is built in reverse order. */
19317 o
= (valueT
) ((offset
- 0x204) >> 2);
19319 add_unwind_opcode (0, 1);
19321 /* Calculate the uleb128 encoding of the offset. */
19325 bytes
[n
] = o
& 0x7f;
19331 /* Add the insn. */
19333 add_unwind_opcode (bytes
[n
- 1], 1);
19334 add_unwind_opcode (0xb2, 1);
19336 else if (offset
> 0x100)
19338 /* Two short opcodes. */
19339 add_unwind_opcode (0x3f, 1);
19340 op
= (offset
- 0x104) >> 2;
19341 add_unwind_opcode (op
, 1);
19343 else if (offset
> 0)
19345 /* Short opcode. */
19346 op
= (offset
- 4) >> 2;
19347 add_unwind_opcode (op
, 1);
19349 else if (offset
< 0)
19352 while (offset
> 0x100)
19354 add_unwind_opcode (0x7f, 1);
19357 op
= ((offset
- 4) >> 2) | 0x40;
19358 add_unwind_opcode (op
, 1);
19362 /* Finish the list of unwind opcodes for this function. */
19364 finish_unwind_opcodes (void)
19368 if (unwind
.fp_used
)
19370 /* Adjust sp as necessary. */
19371 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19372 flush_pending_unwind ();
19374 /* After restoring sp from the frame pointer. */
19375 op
= 0x90 | unwind
.fp_reg
;
19376 add_unwind_opcode (op
, 1);
19379 flush_pending_unwind ();
19383 /* Start an exception table entry. If idx is nonzero this is an index table
19387 start_unwind_section (const segT text_seg
, int idx
)
19389 const char * text_name
;
19390 const char * prefix
;
19391 const char * prefix_once
;
19392 const char * group_name
;
19396 size_t sec_name_len
;
19403 prefix
= ELF_STRING_ARM_unwind
;
19404 prefix_once
= ELF_STRING_ARM_unwind_once
;
19405 type
= SHT_ARM_EXIDX
;
19409 prefix
= ELF_STRING_ARM_unwind_info
;
19410 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19411 type
= SHT_PROGBITS
;
19414 text_name
= segment_name (text_seg
);
19415 if (streq (text_name
, ".text"))
19418 if (strncmp (text_name
, ".gnu.linkonce.t.",
19419 strlen (".gnu.linkonce.t.")) == 0)
19421 prefix
= prefix_once
;
19422 text_name
+= strlen (".gnu.linkonce.t.");
19425 prefix_len
= strlen (prefix
);
19426 text_len
= strlen (text_name
);
19427 sec_name_len
= prefix_len
+ text_len
;
19428 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19429 memcpy (sec_name
, prefix
, prefix_len
);
19430 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19431 sec_name
[prefix_len
+ text_len
] = '\0';
19437 /* Handle COMDAT group. */
19438 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19440 group_name
= elf_group_name (text_seg
);
19441 if (group_name
== NULL
)
19443 as_bad (_("Group section `%s' has no group signature"),
19444 segment_name (text_seg
));
19445 ignore_rest_of_line ();
19448 flags
|= SHF_GROUP
;
19452 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19454 /* Set the section link for index tables. */
19456 elf_linked_to_section (now_seg
) = text_seg
;
19460 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19461 personality routine data. Returns zero, or the index table value for
19462 and inline entry. */
19465 create_unwind_entry (int have_data
)
19470 /* The current word of data. */
19472 /* The number of bytes left in this word. */
19475 finish_unwind_opcodes ();
19477 /* Remember the current text section. */
19478 unwind
.saved_seg
= now_seg
;
19479 unwind
.saved_subseg
= now_subseg
;
19481 start_unwind_section (now_seg
, 0);
19483 if (unwind
.personality_routine
== NULL
)
19485 if (unwind
.personality_index
== -2)
19488 as_bad (_("handlerdata in cantunwind frame"));
19489 return 1; /* EXIDX_CANTUNWIND. */
19492 /* Use a default personality routine if none is specified. */
19493 if (unwind
.personality_index
== -1)
19495 if (unwind
.opcode_count
> 3)
19496 unwind
.personality_index
= 1;
19498 unwind
.personality_index
= 0;
19501 /* Space for the personality routine entry. */
19502 if (unwind
.personality_index
== 0)
19504 if (unwind
.opcode_count
> 3)
19505 as_bad (_("too many unwind opcodes for personality routine 0"));
19509 /* All the data is inline in the index table. */
19512 while (unwind
.opcode_count
> 0)
19514 unwind
.opcode_count
--;
19515 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19519 /* Pad with "finish" opcodes. */
19521 data
= (data
<< 8) | 0xb0;
19528 /* We get two opcodes "free" in the first word. */
19529 size
= unwind
.opcode_count
- 2;
19532 /* An extra byte is required for the opcode count. */
19533 size
= unwind
.opcode_count
+ 1;
19535 size
= (size
+ 3) >> 2;
19537 as_bad (_("too many unwind opcodes"));
19539 frag_align (2, 0, 0);
19540 record_alignment (now_seg
, 2);
19541 unwind
.table_entry
= expr_build_dot ();
19543 /* Allocate the table entry. */
19544 ptr
= frag_more ((size
<< 2) + 4);
19545 where
= frag_now_fix () - ((size
<< 2) + 4);
19547 switch (unwind
.personality_index
)
19550 /* ??? Should this be a PLT generating relocation? */
19551 /* Custom personality routine. */
19552 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19553 BFD_RELOC_ARM_PREL31
);
19558 /* Set the first byte to the number of additional words. */
19563 /* ABI defined personality routines. */
19565 /* Three opcodes bytes are packed into the first word. */
19572 /* The size and first two opcode bytes go in the first word. */
19573 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19578 /* Should never happen. */
19582 /* Pack the opcodes into words (MSB first), reversing the list at the same
19584 while (unwind
.opcode_count
> 0)
19588 md_number_to_chars (ptr
, data
, 4);
19593 unwind
.opcode_count
--;
19595 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19598 /* Finish off the last word. */
19601 /* Pad with "finish" opcodes. */
19603 data
= (data
<< 8) | 0xb0;
19605 md_number_to_chars (ptr
, data
, 4);
19610 /* Add an empty descriptor if there is no user-specified data. */
19611 ptr
= frag_more (4);
19612 md_number_to_chars (ptr
, 0, 4);
19619 /* Initialize the DWARF-2 unwind information for this procedure. */
19622 tc_arm_frame_initial_instructions (void)
19624 cfi_add_CFA_def_cfa (REG_SP
, 0);
19626 #endif /* OBJ_ELF */
19628 /* Convert REGNAME to a DWARF-2 register number. */
19631 tc_arm_regname_to_dw2regnum (char *regname
)
19633 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19643 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19647 exp
.X_op
= O_secrel
;
19648 exp
.X_add_symbol
= symbol
;
19649 exp
.X_add_number
= 0;
19650 emit_expr (&exp
, size
);
19654 /* MD interface: Symbol and relocation handling. */
19656 /* Return the address within the segment that a PC-relative fixup is
19657 relative to. For ARM, PC-relative fixups applied to instructions
19658 are generally relative to the location of the fixup plus 8 bytes.
19659 Thumb branches are offset by 4, and Thumb loads relative to PC
19660 require special handling. */
19663 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19665 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19667 /* If this is pc-relative and we are going to emit a relocation
19668 then we just want to put out any pipeline compensation that the linker
19669 will need. Otherwise we want to use the calculated base.
19670 For WinCE we skip the bias for externals as well, since this
19671 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19673 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19674 || (arm_force_relocation (fixP
)
19676 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19682 switch (fixP
->fx_r_type
)
19684 /* PC relative addressing on the Thumb is slightly odd as the
19685 bottom two bits of the PC are forced to zero for the
19686 calculation. This happens *after* application of the
19687 pipeline offset. However, Thumb adrl already adjusts for
19688 this, so we need not do it again. */
19689 case BFD_RELOC_ARM_THUMB_ADD
:
19692 case BFD_RELOC_ARM_THUMB_OFFSET
:
19693 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19694 case BFD_RELOC_ARM_T32_ADD_PC12
:
19695 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19696 return (base
+ 4) & ~3;
19698 /* Thumb branches are simply offset by +4. */
19699 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19700 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19701 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19702 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19703 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19706 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19708 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19709 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19710 && ARM_IS_FUNC (fixP
->fx_addsy
)
19711 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19712 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19715 /* BLX is like branches above, but forces the low two bits of PC to
19717 case BFD_RELOC_THUMB_PCREL_BLX
:
19719 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19720 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19721 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19722 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19723 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19724 return (base
+ 4) & ~3;
19726 /* ARM mode branches are offset by +8. However, the Windows CE
19727 loader expects the relocation not to take this into account. */
19728 case BFD_RELOC_ARM_PCREL_BLX
:
19730 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19731 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19732 && ARM_IS_FUNC (fixP
->fx_addsy
)
19733 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19734 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19737 case BFD_RELOC_ARM_PCREL_CALL
:
19739 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19740 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19741 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19742 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19743 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19746 case BFD_RELOC_ARM_PCREL_BRANCH
:
19747 case BFD_RELOC_ARM_PCREL_JUMP
:
19748 case BFD_RELOC_ARM_PLT32
:
19750 /* When handling fixups immediately, because we have already
19751 discovered the value of a symbol, or the address of the frag involved
19752 we must account for the offset by +8, as the OS loader will never see the reloc.
19753 see fixup_segment() in write.c
19754 The S_IS_EXTERNAL test handles the case of global symbols.
19755 Those need the calculated base, not just the pipe compensation the linker will need. */
19757 && fixP
->fx_addsy
!= NULL
19758 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19759 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19767 /* ARM mode loads relative to PC are also offset by +8. Unlike
19768 branches, the Windows CE loader *does* expect the relocation
19769 to take this into account. */
19770 case BFD_RELOC_ARM_OFFSET_IMM
:
19771 case BFD_RELOC_ARM_OFFSET_IMM8
:
19772 case BFD_RELOC_ARM_HWLITERAL
:
19773 case BFD_RELOC_ARM_LITERAL
:
19774 case BFD_RELOC_ARM_CP_OFF_IMM
:
19778 /* Other PC-relative relocations are un-offset. */
19784 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19785 Otherwise we have no need to default values of symbols. */
19788 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19791 if (name
[0] == '_' && name
[1] == 'G'
19792 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19796 if (symbol_find (name
))
19797 as_bad (_("GOT already in the symbol table"));
19799 GOT_symbol
= symbol_new (name
, undefined_section
,
19800 (valueT
) 0, & zero_address_frag
);
19810 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19811 computed as two separate immediate values, added together. We
19812 already know that this value cannot be computed by just one ARM
19815 static unsigned int
19816 validate_immediate_twopart (unsigned int val
,
19817 unsigned int * highpart
)
19822 for (i
= 0; i
< 32; i
+= 2)
19823 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19829 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19831 else if (a
& 0xff0000)
19833 if (a
& 0xff000000)
19835 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19839 gas_assert (a
& 0xff000000);
19840 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19843 return (a
& 0xff) | (i
<< 7);
19850 validate_offset_imm (unsigned int val
, int hwse
)
19852 if ((hwse
&& val
> 255) || val
> 4095)
19857 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19858 negative immediate constant by altering the instruction. A bit of
19863 by inverting the second operand, and
19866 by negating the second operand. */
19869 negate_data_op (unsigned long * instruction
,
19870 unsigned long value
)
19873 unsigned long negated
, inverted
;
19875 negated
= encode_arm_immediate (-value
);
19876 inverted
= encode_arm_immediate (~value
);
19878 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19881 /* First negates. */
19882 case OPCODE_SUB
: /* ADD <-> SUB */
19883 new_inst
= OPCODE_ADD
;
19888 new_inst
= OPCODE_SUB
;
19892 case OPCODE_CMP
: /* CMP <-> CMN */
19893 new_inst
= OPCODE_CMN
;
19898 new_inst
= OPCODE_CMP
;
19902 /* Now Inverted ops. */
19903 case OPCODE_MOV
: /* MOV <-> MVN */
19904 new_inst
= OPCODE_MVN
;
19909 new_inst
= OPCODE_MOV
;
19913 case OPCODE_AND
: /* AND <-> BIC */
19914 new_inst
= OPCODE_BIC
;
19919 new_inst
= OPCODE_AND
;
19923 case OPCODE_ADC
: /* ADC <-> SBC */
19924 new_inst
= OPCODE_SBC
;
19929 new_inst
= OPCODE_ADC
;
19933 /* We cannot do anything. */
19938 if (value
== (unsigned) FAIL
)
19941 *instruction
&= OPCODE_MASK
;
19942 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19946 /* Like negate_data_op, but for Thumb-2. */
19948 static unsigned int
19949 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19953 unsigned int negated
, inverted
;
19955 negated
= encode_thumb32_immediate (-value
);
19956 inverted
= encode_thumb32_immediate (~value
);
19958 rd
= (*instruction
>> 8) & 0xf;
19959 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19962 /* ADD <-> SUB. Includes CMP <-> CMN. */
19963 case T2_OPCODE_SUB
:
19964 new_inst
= T2_OPCODE_ADD
;
19968 case T2_OPCODE_ADD
:
19969 new_inst
= T2_OPCODE_SUB
;
19973 /* ORR <-> ORN. Includes MOV <-> MVN. */
19974 case T2_OPCODE_ORR
:
19975 new_inst
= T2_OPCODE_ORN
;
19979 case T2_OPCODE_ORN
:
19980 new_inst
= T2_OPCODE_ORR
;
19984 /* AND <-> BIC. TST has no inverted equivalent. */
19985 case T2_OPCODE_AND
:
19986 new_inst
= T2_OPCODE_BIC
;
19993 case T2_OPCODE_BIC
:
19994 new_inst
= T2_OPCODE_AND
;
19999 case T2_OPCODE_ADC
:
20000 new_inst
= T2_OPCODE_SBC
;
20004 case T2_OPCODE_SBC
:
20005 new_inst
= T2_OPCODE_ADC
;
20009 /* We cannot do anything. */
20014 if (value
== (unsigned int)FAIL
)
20017 *instruction
&= T2_OPCODE_MASK
;
20018 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20022 /* Read a 32-bit thumb instruction from buf. */
20023 static unsigned long
20024 get_thumb32_insn (char * buf
)
20026 unsigned long insn
;
20027 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20028 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20034 /* We usually want to set the low bit on the address of thumb function
20035 symbols. In particular .word foo - . should have the low bit set.
20036 Generic code tries to fold the difference of two symbols to
20037 a constant. Prevent this and force a relocation when the first symbols
20038 is a thumb function. */
20041 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20043 if (op
== O_subtract
20044 && l
->X_op
== O_symbol
20045 && r
->X_op
== O_symbol
20046 && THUMB_IS_FUNC (l
->X_add_symbol
))
20048 l
->X_op
= O_subtract
;
20049 l
->X_op_symbol
= r
->X_add_symbol
;
20050 l
->X_add_number
-= r
->X_add_number
;
20054 /* Process as normal. */
20058 /* Encode Thumb2 unconditional branches and calls. The encoding
20059 for the 2 are identical for the immediate values. */
20062 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20064 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20067 addressT S
, I1
, I2
, lo
, hi
;
20069 S
= (value
>> 24) & 0x01;
20070 I1
= (value
>> 23) & 0x01;
20071 I2
= (value
>> 22) & 0x01;
20072 hi
= (value
>> 12) & 0x3ff;
20073 lo
= (value
>> 1) & 0x7ff;
20074 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20075 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20076 newval
|= (S
<< 10) | hi
;
20077 newval2
&= ~T2I1I2MASK
;
20078 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20079 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20080 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20084 md_apply_fix (fixS
* fixP
,
20088 offsetT value
= * valP
;
20090 unsigned int newimm
;
20091 unsigned long temp
;
20093 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20095 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20097 /* Note whether this will delete the relocation. */
20099 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20102 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20103 consistency with the behaviour on 32-bit hosts. Remember value
20105 value
&= 0xffffffff;
20106 value
^= 0x80000000;
20107 value
-= 0x80000000;
20110 fixP
->fx_addnumber
= value
;
20112 /* Same treatment for fixP->fx_offset. */
20113 fixP
->fx_offset
&= 0xffffffff;
20114 fixP
->fx_offset
^= 0x80000000;
20115 fixP
->fx_offset
-= 0x80000000;
20117 switch (fixP
->fx_r_type
)
20119 case BFD_RELOC_NONE
:
20120 /* This will need to go in the object file. */
20124 case BFD_RELOC_ARM_IMMEDIATE
:
20125 /* We claim that this fixup has been processed here,
20126 even if in fact we generate an error because we do
20127 not have a reloc for it, so tc_gen_reloc will reject it. */
20130 if (fixP
->fx_addsy
)
20132 const char *msg
= 0;
20134 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20135 msg
= _("undefined symbol %s used as an immediate value");
20136 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20137 msg
= _("symbol %s is in a different section");
20138 else if (S_IS_WEAK (fixP
->fx_addsy
))
20139 msg
= _("symbol %s is weak and may be overridden later");
20143 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20144 msg
, S_GET_NAME (fixP
->fx_addsy
));
20149 newimm
= encode_arm_immediate (value
);
20150 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20152 /* If the instruction will fail, see if we can fix things up by
20153 changing the opcode. */
20154 if (newimm
== (unsigned int) FAIL
20155 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20157 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20158 _("invalid constant (%lx) after fixup"),
20159 (unsigned long) value
);
20163 newimm
|= (temp
& 0xfffff000);
20164 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20167 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20169 unsigned int highpart
= 0;
20170 unsigned int newinsn
= 0xe1a00000; /* nop. */
20172 if (fixP
->fx_addsy
)
20174 const char *msg
= 0;
20176 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20177 msg
= _("undefined symbol %s used as an immediate value");
20178 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20179 msg
= _("symbol %s is in a different section");
20180 else if (S_IS_WEAK (fixP
->fx_addsy
))
20181 msg
= _("symbol %s is weak and may be overridden later");
20185 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20186 msg
, S_GET_NAME (fixP
->fx_addsy
));
20191 newimm
= encode_arm_immediate (value
);
20192 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20194 /* If the instruction will fail, see if we can fix things up by
20195 changing the opcode. */
20196 if (newimm
== (unsigned int) FAIL
20197 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20199 /* No ? OK - try using two ADD instructions to generate
20201 newimm
= validate_immediate_twopart (value
, & highpart
);
20203 /* Yes - then make sure that the second instruction is
20205 if (newimm
!= (unsigned int) FAIL
)
20207 /* Still No ? Try using a negated value. */
20208 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20209 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20210 /* Otherwise - give up. */
20213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20214 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20219 /* Replace the first operand in the 2nd instruction (which
20220 is the PC) with the destination register. We have
20221 already added in the PC in the first instruction and we
20222 do not want to do it again. */
20223 newinsn
&= ~ 0xf0000;
20224 newinsn
|= ((newinsn
& 0x0f000) << 4);
20227 newimm
|= (temp
& 0xfffff000);
20228 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20230 highpart
|= (newinsn
& 0xfffff000);
20231 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20235 case BFD_RELOC_ARM_OFFSET_IMM
:
20236 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20239 case BFD_RELOC_ARM_LITERAL
:
20245 if (validate_offset_imm (value
, 0) == FAIL
)
20247 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20249 _("invalid literal constant: pool needs to be closer"));
20251 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20252 _("bad immediate value for offset (%ld)"),
20257 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20258 newval
&= 0xff7ff000;
20259 newval
|= value
| (sign
? INDEX_UP
: 0);
20260 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20263 case BFD_RELOC_ARM_OFFSET_IMM8
:
20264 case BFD_RELOC_ARM_HWLITERAL
:
20270 if (validate_offset_imm (value
, 1) == FAIL
)
20272 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20274 _("invalid literal constant: pool needs to be closer"));
20276 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20281 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20282 newval
&= 0xff7ff0f0;
20283 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20284 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20287 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20288 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20290 _("bad immediate value for offset (%ld)"), (long) value
);
20293 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20295 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20298 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20299 /* This is a complicated relocation used for all varieties of Thumb32
20300 load/store instruction with immediate offset:
20302 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20303 *4, optional writeback(W)
20304 (doubleword load/store)
20306 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20307 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20308 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20309 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20310 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20312 Uppercase letters indicate bits that are already encoded at
20313 this point. Lowercase letters are our problem. For the
20314 second block of instructions, the secondary opcode nybble
20315 (bits 8..11) is present, and bit 23 is zero, even if this is
20316 a PC-relative operation. */
20317 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20319 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20321 if ((newval
& 0xf0000000) == 0xe0000000)
20323 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20325 newval
|= (1 << 23);
20328 if (value
% 4 != 0)
20330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20331 _("offset not a multiple of 4"));
20337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20338 _("offset out of range"));
20343 else if ((newval
& 0x000f0000) == 0x000f0000)
20345 /* PC-relative, 12-bit offset. */
20347 newval
|= (1 << 23);
20352 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20353 _("offset out of range"));
20358 else if ((newval
& 0x00000100) == 0x00000100)
20360 /* Writeback: 8-bit, +/- offset. */
20362 newval
|= (1 << 9);
20367 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20368 _("offset out of range"));
20373 else if ((newval
& 0x00000f00) == 0x00000e00)
20375 /* T-instruction: positive 8-bit offset. */
20376 if (value
< 0 || value
> 0xff)
20378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20379 _("offset out of range"));
20387 /* Positive 12-bit or negative 8-bit offset. */
20391 newval
|= (1 << 23);
20401 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20402 _("offset out of range"));
20409 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20410 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20413 case BFD_RELOC_ARM_SHIFT_IMM
:
20414 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20415 if (((unsigned long) value
) > 32
20417 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20420 _("shift expression is too large"));
20425 /* Shifts of zero must be done as lsl. */
20427 else if (value
== 32)
20429 newval
&= 0xfffff07f;
20430 newval
|= (value
& 0x1f) << 7;
20431 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20434 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20435 case BFD_RELOC_ARM_T32_ADD_IMM
:
20436 case BFD_RELOC_ARM_T32_IMM12
:
20437 case BFD_RELOC_ARM_T32_ADD_PC12
:
20438 /* We claim that this fixup has been processed here,
20439 even if in fact we generate an error because we do
20440 not have a reloc for it, so tc_gen_reloc will reject it. */
20444 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20447 _("undefined symbol %s used as an immediate value"),
20448 S_GET_NAME (fixP
->fx_addsy
));
20452 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20454 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20457 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20458 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20460 newimm
= encode_thumb32_immediate (value
);
20461 if (newimm
== (unsigned int) FAIL
)
20462 newimm
= thumb32_negate_data_op (&newval
, value
);
20464 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20465 && newimm
== (unsigned int) FAIL
)
20467 /* Turn add/sum into addw/subw. */
20468 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20469 newval
= (newval
& 0xfeffffff) | 0x02000000;
20470 /* No flat 12-bit imm encoding for addsw/subsw. */
20471 if ((newval
& 0x00100000) == 0)
20473 /* 12 bit immediate for addw/subw. */
20477 newval
^= 0x00a00000;
20480 newimm
= (unsigned int) FAIL
;
20486 if (newimm
== (unsigned int)FAIL
)
20488 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20489 _("invalid constant (%lx) after fixup"),
20490 (unsigned long) value
);
20494 newval
|= (newimm
& 0x800) << 15;
20495 newval
|= (newimm
& 0x700) << 4;
20496 newval
|= (newimm
& 0x0ff);
20498 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20499 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20502 case BFD_RELOC_ARM_SMC
:
20503 if (((unsigned long) value
) > 0xffff)
20504 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20505 _("invalid smc expression"));
20506 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20507 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20508 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20511 case BFD_RELOC_ARM_HVC
:
20512 if (((unsigned long) value
) > 0xffff)
20513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20514 _("invalid hvc expression"));
20515 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20516 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20517 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20520 case BFD_RELOC_ARM_SWI
:
20521 if (fixP
->tc_fix_data
!= 0)
20523 if (((unsigned long) value
) > 0xff)
20524 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20525 _("invalid swi expression"));
20526 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20528 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20532 if (((unsigned long) value
) > 0x00ffffff)
20533 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20534 _("invalid swi expression"));
20535 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20537 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20541 case BFD_RELOC_ARM_MULTI
:
20542 if (((unsigned long) value
) > 0xffff)
20543 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20544 _("invalid expression in load/store multiple"));
20545 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20546 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20550 case BFD_RELOC_ARM_PCREL_CALL
:
20552 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20554 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20555 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20556 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20557 /* Flip the bl to blx. This is a simple flip
20558 bit here because we generate PCREL_CALL for
20559 unconditional bls. */
20561 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20562 newval
= newval
| 0x10000000;
20563 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20569 goto arm_branch_common
;
20571 case BFD_RELOC_ARM_PCREL_JUMP
:
20572 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20574 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20575 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20576 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20578 /* This would map to a bl<cond>, b<cond>,
20579 b<always> to a Thumb function. We
20580 need to force a relocation for this particular
20582 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20586 case BFD_RELOC_ARM_PLT32
:
20588 case BFD_RELOC_ARM_PCREL_BRANCH
:
20590 goto arm_branch_common
;
20592 case BFD_RELOC_ARM_PCREL_BLX
:
20595 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20597 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20598 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20599 && ARM_IS_FUNC (fixP
->fx_addsy
))
20601 /* Flip the blx to a bl and warn. */
20602 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20603 newval
= 0xeb000000;
20604 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20605 _("blx to '%s' an ARM ISA state function changed to bl"),
20607 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20613 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20614 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20618 /* We are going to store value (shifted right by two) in the
20619 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20620 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20621 also be be clear. */
20623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20624 _("misaligned branch destination"));
20625 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20626 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20628 _("branch out of range"));
20630 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20632 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20633 newval
|= (value
>> 2) & 0x00ffffff;
20634 /* Set the H bit on BLX instructions. */
20638 newval
|= 0x01000000;
20640 newval
&= ~0x01000000;
20642 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20646 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20647 /* CBZ can only branch forward. */
20649 /* Attempts to use CBZ to branch to the next instruction
20650 (which, strictly speaking, are prohibited) will be turned into
20653 FIXME: It may be better to remove the instruction completely and
20654 perform relaxation. */
20657 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20658 newval
= 0xbf00; /* NOP encoding T1 */
20659 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20665 _("branch out of range"));
20667 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20669 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20670 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20671 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20676 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20677 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20678 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20679 _("branch out of range"));
20681 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20683 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20684 newval
|= (value
& 0x1ff) >> 1;
20685 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20689 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20690 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20691 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20692 _("branch out of range"));
20694 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20696 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20697 newval
|= (value
& 0xfff) >> 1;
20698 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20702 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20704 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20705 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20706 && S_IS_DEFINED (fixP
->fx_addsy
)
20707 && ARM_IS_FUNC (fixP
->fx_addsy
)
20708 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20710 /* Force a relocation for a branch 20 bits wide. */
20713 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20715 _("conditional branch out of range"));
20717 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20720 addressT S
, J1
, J2
, lo
, hi
;
20722 S
= (value
& 0x00100000) >> 20;
20723 J2
= (value
& 0x00080000) >> 19;
20724 J1
= (value
& 0x00040000) >> 18;
20725 hi
= (value
& 0x0003f000) >> 12;
20726 lo
= (value
& 0x00000ffe) >> 1;
20728 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20729 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20730 newval
|= (S
<< 10) | hi
;
20731 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20732 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20733 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20737 case BFD_RELOC_THUMB_PCREL_BLX
:
20739 /* If there is a blx from a thumb state function to
20740 another thumb function flip this to a bl and warn
20744 && S_IS_DEFINED (fixP
->fx_addsy
)
20745 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20746 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20747 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20749 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20750 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20751 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20753 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20754 newval
= newval
| 0x1000;
20755 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20756 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20761 goto thumb_bl_common
;
20763 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20765 /* A bl from Thumb state ISA to an internal ARM state function
20766 is converted to a blx. */
20768 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20769 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20770 && S_IS_DEFINED (fixP
->fx_addsy
)
20771 && ARM_IS_FUNC (fixP
->fx_addsy
)
20772 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20774 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20775 newval
= newval
& ~0x1000;
20776 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20777 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20784 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20785 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20786 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20789 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20790 /* For a BLX instruction, make sure that the relocation is rounded up
20791 to a word boundary. This follows the semantics of the instruction
20792 which specifies that bit 1 of the target address will come from bit
20793 1 of the base address. */
20794 value
= (value
+ 1) & ~ 1;
20797 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20799 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20801 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20802 _("branch out of range"));
20804 else if ((value
& ~0x1ffffff)
20805 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20808 _("Thumb2 branch out of range"));
20812 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20813 encode_thumb2_b_bl_offset (buf
, value
);
20817 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20818 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20820 _("branch out of range"));
20822 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20823 encode_thumb2_b_bl_offset (buf
, value
);
20828 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20829 md_number_to_chars (buf
, value
, 1);
20833 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20834 md_number_to_chars (buf
, value
, 2);
20838 case BFD_RELOC_ARM_TLS_GD32
:
20839 case BFD_RELOC_ARM_TLS_LE32
:
20840 case BFD_RELOC_ARM_TLS_IE32
:
20841 case BFD_RELOC_ARM_TLS_LDM32
:
20842 case BFD_RELOC_ARM_TLS_LDO32
:
20843 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20846 case BFD_RELOC_ARM_GOT32
:
20847 case BFD_RELOC_ARM_GOTOFF
:
20848 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20849 md_number_to_chars (buf
, 0, 4);
20852 case BFD_RELOC_ARM_GOT_PREL
:
20853 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20854 md_number_to_chars (buf
, value
, 4);
20857 case BFD_RELOC_ARM_TARGET2
:
20858 /* TARGET2 is not partial-inplace, so we need to write the
20859 addend here for REL targets, because it won't be written out
20860 during reloc processing later. */
20861 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20862 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20866 case BFD_RELOC_RVA
:
20868 case BFD_RELOC_ARM_TARGET1
:
20869 case BFD_RELOC_ARM_ROSEGREL32
:
20870 case BFD_RELOC_ARM_SBREL32
:
20871 case BFD_RELOC_32_PCREL
:
20873 case BFD_RELOC_32_SECREL
:
20875 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20877 /* For WinCE we only do this for pcrel fixups. */
20878 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20880 md_number_to_chars (buf
, value
, 4);
20884 case BFD_RELOC_ARM_PREL31
:
20885 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20887 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20888 if ((value
^ (value
>> 1)) & 0x40000000)
20890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20891 _("rel31 relocation overflow"));
20893 newval
|= value
& 0x7fffffff;
20894 md_number_to_chars (buf
, newval
, 4);
20899 case BFD_RELOC_ARM_CP_OFF_IMM
:
20900 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20901 if (value
< -1023 || value
> 1023 || (value
& 3))
20902 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20903 _("co-processor offset out of range"));
20908 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20909 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20910 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20912 newval
= get_thumb32_insn (buf
);
20913 newval
&= 0xff7fff00;
20914 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20915 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20916 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20917 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20919 put_thumb32_insn (buf
, newval
);
20922 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20923 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20924 if (value
< -255 || value
> 255)
20925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20926 _("co-processor offset out of range"));
20928 goto cp_off_common
;
20930 case BFD_RELOC_ARM_THUMB_OFFSET
:
20931 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20932 /* Exactly what ranges, and where the offset is inserted depends
20933 on the type of instruction, we can establish this from the
20935 switch (newval
>> 12)
20937 case 4: /* PC load. */
20938 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20939 forced to zero for these loads; md_pcrel_from has already
20940 compensated for this. */
20942 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20943 _("invalid offset, target not word aligned (0x%08lX)"),
20944 (((unsigned long) fixP
->fx_frag
->fr_address
20945 + (unsigned long) fixP
->fx_where
) & ~3)
20946 + (unsigned long) value
);
20948 if (value
& ~0x3fc)
20949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20950 _("invalid offset, value too big (0x%08lX)"),
20953 newval
|= value
>> 2;
20956 case 9: /* SP load/store. */
20957 if (value
& ~0x3fc)
20958 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20959 _("invalid offset, value too big (0x%08lX)"),
20961 newval
|= value
>> 2;
20964 case 6: /* Word load/store. */
20966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20967 _("invalid offset, value too big (0x%08lX)"),
20969 newval
|= value
<< 4; /* 6 - 2. */
20972 case 7: /* Byte load/store. */
20974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20975 _("invalid offset, value too big (0x%08lX)"),
20977 newval
|= value
<< 6;
20980 case 8: /* Halfword load/store. */
20982 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20983 _("invalid offset, value too big (0x%08lX)"),
20985 newval
|= value
<< 5; /* 6 - 1. */
20989 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20990 "Unable to process relocation for thumb opcode: %lx",
20991 (unsigned long) newval
);
20994 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20997 case BFD_RELOC_ARM_THUMB_ADD
:
20998 /* This is a complicated relocation, since we use it for all of
20999 the following immediate relocations:
21003 9bit ADD/SUB SP word-aligned
21004 10bit ADD PC/SP word-aligned
21006 The type of instruction being processed is encoded in the
21013 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21015 int rd
= (newval
>> 4) & 0xf;
21016 int rs
= newval
& 0xf;
21017 int subtract
= !!(newval
& 0x8000);
21019 /* Check for HI regs, only very restricted cases allowed:
21020 Adjusting SP, and using PC or SP to get an address. */
21021 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21022 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21023 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21024 _("invalid Hi register with immediate"));
21026 /* If value is negative, choose the opposite instruction. */
21030 subtract
= !subtract
;
21032 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21033 _("immediate value out of range"));
21038 if (value
& ~0x1fc)
21039 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21040 _("invalid immediate for stack address calculation"));
21041 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21042 newval
|= value
>> 2;
21044 else if (rs
== REG_PC
|| rs
== REG_SP
)
21046 if (subtract
|| value
& ~0x3fc)
21047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21048 _("invalid immediate for address calculation (value = 0x%08lX)"),
21049 (unsigned long) value
);
21050 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21052 newval
|= value
>> 2;
21057 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21058 _("immediate value out of range"));
21059 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21060 newval
|= (rd
<< 8) | value
;
21065 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21066 _("immediate value out of range"));
21067 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21068 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21071 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21074 case BFD_RELOC_ARM_THUMB_IMM
:
21075 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21076 if (value
< 0 || value
> 255)
21077 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21078 _("invalid immediate: %ld is out of range"),
21081 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21084 case BFD_RELOC_ARM_THUMB_SHIFT
:
21085 /* 5bit shift value (0..32). LSL cannot take 32. */
21086 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21087 temp
= newval
& 0xf800;
21088 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21089 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21090 _("invalid shift value: %ld"), (long) value
);
21091 /* Shifts of zero must be encoded as LSL. */
21093 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21094 /* Shifts of 32 are encoded as zero. */
21095 else if (value
== 32)
21097 newval
|= value
<< 6;
21098 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21101 case BFD_RELOC_VTABLE_INHERIT
:
21102 case BFD_RELOC_VTABLE_ENTRY
:
21106 case BFD_RELOC_ARM_MOVW
:
21107 case BFD_RELOC_ARM_MOVT
:
21108 case BFD_RELOC_ARM_THUMB_MOVW
:
21109 case BFD_RELOC_ARM_THUMB_MOVT
:
21110 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21112 /* REL format relocations are limited to a 16-bit addend. */
21113 if (!fixP
->fx_done
)
21115 if (value
< -0x8000 || value
> 0x7fff)
21116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21117 _("offset out of range"));
21119 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21120 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21125 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21126 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21128 newval
= get_thumb32_insn (buf
);
21129 newval
&= 0xfbf08f00;
21130 newval
|= (value
& 0xf000) << 4;
21131 newval
|= (value
& 0x0800) << 15;
21132 newval
|= (value
& 0x0700) << 4;
21133 newval
|= (value
& 0x00ff);
21134 put_thumb32_insn (buf
, newval
);
21138 newval
= md_chars_to_number (buf
, 4);
21139 newval
&= 0xfff0f000;
21140 newval
|= value
& 0x0fff;
21141 newval
|= (value
& 0xf000) << 4;
21142 md_number_to_chars (buf
, newval
, 4);
21147 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21148 case BFD_RELOC_ARM_ALU_PC_G0
:
21149 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21150 case BFD_RELOC_ARM_ALU_PC_G1
:
21151 case BFD_RELOC_ARM_ALU_PC_G2
:
21152 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21153 case BFD_RELOC_ARM_ALU_SB_G0
:
21154 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21155 case BFD_RELOC_ARM_ALU_SB_G1
:
21156 case BFD_RELOC_ARM_ALU_SB_G2
:
21157 gas_assert (!fixP
->fx_done
);
21158 if (!seg
->use_rela_p
)
21161 bfd_vma encoded_addend
;
21162 bfd_vma addend_abs
= abs (value
);
21164 /* Check that the absolute value of the addend can be
21165 expressed as an 8-bit constant plus a rotation. */
21166 encoded_addend
= encode_arm_immediate (addend_abs
);
21167 if (encoded_addend
== (unsigned int) FAIL
)
21168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21169 _("the offset 0x%08lX is not representable"),
21170 (unsigned long) addend_abs
);
21172 /* Extract the instruction. */
21173 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21175 /* If the addend is positive, use an ADD instruction.
21176 Otherwise use a SUB. Take care not to destroy the S bit. */
21177 insn
&= 0xff1fffff;
21183 /* Place the encoded addend into the first 12 bits of the
21185 insn
&= 0xfffff000;
21186 insn
|= encoded_addend
;
21188 /* Update the instruction. */
21189 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21193 case BFD_RELOC_ARM_LDR_PC_G0
:
21194 case BFD_RELOC_ARM_LDR_PC_G1
:
21195 case BFD_RELOC_ARM_LDR_PC_G2
:
21196 case BFD_RELOC_ARM_LDR_SB_G0
:
21197 case BFD_RELOC_ARM_LDR_SB_G1
:
21198 case BFD_RELOC_ARM_LDR_SB_G2
:
21199 gas_assert (!fixP
->fx_done
);
21200 if (!seg
->use_rela_p
)
21203 bfd_vma addend_abs
= abs (value
);
21205 /* Check that the absolute value of the addend can be
21206 encoded in 12 bits. */
21207 if (addend_abs
>= 0x1000)
21208 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21209 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21210 (unsigned long) addend_abs
);
21212 /* Extract the instruction. */
21213 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21215 /* If the addend is negative, clear bit 23 of the instruction.
21216 Otherwise set it. */
21218 insn
&= ~(1 << 23);
21222 /* Place the absolute value of the addend into the first 12 bits
21223 of the instruction. */
21224 insn
&= 0xfffff000;
21225 insn
|= addend_abs
;
21227 /* Update the instruction. */
21228 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21232 case BFD_RELOC_ARM_LDRS_PC_G0
:
21233 case BFD_RELOC_ARM_LDRS_PC_G1
:
21234 case BFD_RELOC_ARM_LDRS_PC_G2
:
21235 case BFD_RELOC_ARM_LDRS_SB_G0
:
21236 case BFD_RELOC_ARM_LDRS_SB_G1
:
21237 case BFD_RELOC_ARM_LDRS_SB_G2
:
21238 gas_assert (!fixP
->fx_done
);
21239 if (!seg
->use_rela_p
)
21242 bfd_vma addend_abs
= abs (value
);
21244 /* Check that the absolute value of the addend can be
21245 encoded in 8 bits. */
21246 if (addend_abs
>= 0x100)
21247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21248 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21249 (unsigned long) addend_abs
);
21251 /* Extract the instruction. */
21252 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21254 /* If the addend is negative, clear bit 23 of the instruction.
21255 Otherwise set it. */
21257 insn
&= ~(1 << 23);
21261 /* Place the first four bits of the absolute value of the addend
21262 into the first 4 bits of the instruction, and the remaining
21263 four into bits 8 .. 11. */
21264 insn
&= 0xfffff0f0;
21265 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21267 /* Update the instruction. */
21268 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21272 case BFD_RELOC_ARM_LDC_PC_G0
:
21273 case BFD_RELOC_ARM_LDC_PC_G1
:
21274 case BFD_RELOC_ARM_LDC_PC_G2
:
21275 case BFD_RELOC_ARM_LDC_SB_G0
:
21276 case BFD_RELOC_ARM_LDC_SB_G1
:
21277 case BFD_RELOC_ARM_LDC_SB_G2
:
21278 gas_assert (!fixP
->fx_done
);
21279 if (!seg
->use_rela_p
)
21282 bfd_vma addend_abs
= abs (value
);
21284 /* Check that the absolute value of the addend is a multiple of
21285 four and, when divided by four, fits in 8 bits. */
21286 if (addend_abs
& 0x3)
21287 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21288 _("bad offset 0x%08lX (must be word-aligned)"),
21289 (unsigned long) addend_abs
);
21291 if ((addend_abs
>> 2) > 0xff)
21292 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21293 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21294 (unsigned long) addend_abs
);
21296 /* Extract the instruction. */
21297 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21299 /* If the addend is negative, clear bit 23 of the instruction.
21300 Otherwise set it. */
21302 insn
&= ~(1 << 23);
21306 /* Place the addend (divided by four) into the first eight
21307 bits of the instruction. */
21308 insn
&= 0xfffffff0;
21309 insn
|= addend_abs
>> 2;
21311 /* Update the instruction. */
21312 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21316 case BFD_RELOC_ARM_V4BX
:
21317 /* This will need to go in the object file. */
21321 case BFD_RELOC_UNUSED
:
21323 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21324 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21328 /* Translate internal representation of relocation info to BFD target
21332 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21335 bfd_reloc_code_real_type code
;
21337 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21339 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21340 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21341 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21343 if (fixp
->fx_pcrel
)
21345 if (section
->use_rela_p
)
21346 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21348 fixp
->fx_offset
= reloc
->address
;
21350 reloc
->addend
= fixp
->fx_offset
;
21352 switch (fixp
->fx_r_type
)
21355 if (fixp
->fx_pcrel
)
21357 code
= BFD_RELOC_8_PCREL
;
21362 if (fixp
->fx_pcrel
)
21364 code
= BFD_RELOC_16_PCREL
;
21369 if (fixp
->fx_pcrel
)
21371 code
= BFD_RELOC_32_PCREL
;
21375 case BFD_RELOC_ARM_MOVW
:
21376 if (fixp
->fx_pcrel
)
21378 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21382 case BFD_RELOC_ARM_MOVT
:
21383 if (fixp
->fx_pcrel
)
21385 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21389 case BFD_RELOC_ARM_THUMB_MOVW
:
21390 if (fixp
->fx_pcrel
)
21392 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21396 case BFD_RELOC_ARM_THUMB_MOVT
:
21397 if (fixp
->fx_pcrel
)
21399 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21403 case BFD_RELOC_NONE
:
21404 case BFD_RELOC_ARM_PCREL_BRANCH
:
21405 case BFD_RELOC_ARM_PCREL_BLX
:
21406 case BFD_RELOC_RVA
:
21407 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21408 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21409 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21410 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21411 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21412 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21413 case BFD_RELOC_VTABLE_ENTRY
:
21414 case BFD_RELOC_VTABLE_INHERIT
:
21416 case BFD_RELOC_32_SECREL
:
21418 code
= fixp
->fx_r_type
;
21421 case BFD_RELOC_THUMB_PCREL_BLX
:
21423 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21424 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21427 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21430 case BFD_RELOC_ARM_LITERAL
:
21431 case BFD_RELOC_ARM_HWLITERAL
:
21432 /* If this is called then the a literal has
21433 been referenced across a section boundary. */
21434 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21435 _("literal referenced across section boundary"));
21439 case BFD_RELOC_ARM_GOT32
:
21440 case BFD_RELOC_ARM_GOTOFF
:
21441 case BFD_RELOC_ARM_GOT_PREL
:
21442 case BFD_RELOC_ARM_PLT32
:
21443 case BFD_RELOC_ARM_TARGET1
:
21444 case BFD_RELOC_ARM_ROSEGREL32
:
21445 case BFD_RELOC_ARM_SBREL32
:
21446 case BFD_RELOC_ARM_PREL31
:
21447 case BFD_RELOC_ARM_TARGET2
:
21448 case BFD_RELOC_ARM_TLS_LE32
:
21449 case BFD_RELOC_ARM_TLS_LDO32
:
21450 case BFD_RELOC_ARM_PCREL_CALL
:
21451 case BFD_RELOC_ARM_PCREL_JUMP
:
21452 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21453 case BFD_RELOC_ARM_ALU_PC_G0
:
21454 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21455 case BFD_RELOC_ARM_ALU_PC_G1
:
21456 case BFD_RELOC_ARM_ALU_PC_G2
:
21457 case BFD_RELOC_ARM_LDR_PC_G0
:
21458 case BFD_RELOC_ARM_LDR_PC_G1
:
21459 case BFD_RELOC_ARM_LDR_PC_G2
:
21460 case BFD_RELOC_ARM_LDRS_PC_G0
:
21461 case BFD_RELOC_ARM_LDRS_PC_G1
:
21462 case BFD_RELOC_ARM_LDRS_PC_G2
:
21463 case BFD_RELOC_ARM_LDC_PC_G0
:
21464 case BFD_RELOC_ARM_LDC_PC_G1
:
21465 case BFD_RELOC_ARM_LDC_PC_G2
:
21466 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21467 case BFD_RELOC_ARM_ALU_SB_G0
:
21468 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21469 case BFD_RELOC_ARM_ALU_SB_G1
:
21470 case BFD_RELOC_ARM_ALU_SB_G2
:
21471 case BFD_RELOC_ARM_LDR_SB_G0
:
21472 case BFD_RELOC_ARM_LDR_SB_G1
:
21473 case BFD_RELOC_ARM_LDR_SB_G2
:
21474 case BFD_RELOC_ARM_LDRS_SB_G0
:
21475 case BFD_RELOC_ARM_LDRS_SB_G1
:
21476 case BFD_RELOC_ARM_LDRS_SB_G2
:
21477 case BFD_RELOC_ARM_LDC_SB_G0
:
21478 case BFD_RELOC_ARM_LDC_SB_G1
:
21479 case BFD_RELOC_ARM_LDC_SB_G2
:
21480 case BFD_RELOC_ARM_V4BX
:
21481 code
= fixp
->fx_r_type
;
21484 case BFD_RELOC_ARM_TLS_GD32
:
21485 case BFD_RELOC_ARM_TLS_IE32
:
21486 case BFD_RELOC_ARM_TLS_LDM32
:
21487 /* BFD will include the symbol's address in the addend.
21488 But we don't want that, so subtract it out again here. */
21489 if (!S_IS_COMMON (fixp
->fx_addsy
))
21490 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21491 code
= fixp
->fx_r_type
;
21495 case BFD_RELOC_ARM_IMMEDIATE
:
21496 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21497 _("internal relocation (type: IMMEDIATE) not fixed up"));
21500 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21501 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21502 _("ADRL used for a symbol not defined in the same file"));
21505 case BFD_RELOC_ARM_OFFSET_IMM
:
21506 if (section
->use_rela_p
)
21508 code
= fixp
->fx_r_type
;
21512 if (fixp
->fx_addsy
!= NULL
21513 && !S_IS_DEFINED (fixp
->fx_addsy
)
21514 && S_IS_LOCAL (fixp
->fx_addsy
))
21516 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21517 _("undefined local label `%s'"),
21518 S_GET_NAME (fixp
->fx_addsy
));
21522 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21523 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21530 switch (fixp
->fx_r_type
)
21532 case BFD_RELOC_NONE
: type
= "NONE"; break;
21533 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21534 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21535 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21536 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21537 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21538 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21539 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21540 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21541 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21542 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21543 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21544 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21545 default: type
= _("<unknown>"); break;
21547 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21548 _("cannot represent %s relocation in this object file format"),
21555 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21557 && fixp
->fx_addsy
== GOT_symbol
)
21559 code
= BFD_RELOC_ARM_GOTPC
;
21560 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21564 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21566 if (reloc
->howto
== NULL
)
21568 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21569 _("cannot represent %s relocation in this object file format"),
21570 bfd_get_reloc_code_name (code
));
21574 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21575 vtable entry to be used in the relocation's section offset. */
21576 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21577 reloc
->address
= fixp
->fx_offset
;
21582 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21585 cons_fix_new_arm (fragS
* frag
,
21590 bfd_reloc_code_real_type type
;
21594 FIXME: @@ Should look at CPU word size. */
21598 type
= BFD_RELOC_8
;
21601 type
= BFD_RELOC_16
;
21605 type
= BFD_RELOC_32
;
21608 type
= BFD_RELOC_64
;
21613 if (exp
->X_op
== O_secrel
)
21615 exp
->X_op
= O_symbol
;
21616 type
= BFD_RELOC_32_SECREL
;
21620 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21623 #if defined (OBJ_COFF)
21625 arm_validate_fix (fixS
* fixP
)
21627 /* If the destination of the branch is a defined symbol which does not have
21628 the THUMB_FUNC attribute, then we must be calling a function which has
21629 the (interfacearm) attribute. We look for the Thumb entry point to that
21630 function and change the branch to refer to that function instead. */
21631 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21632 && fixP
->fx_addsy
!= NULL
21633 && S_IS_DEFINED (fixP
->fx_addsy
)
21634 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21636 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21643 arm_force_relocation (struct fix
* fixp
)
21645 #if defined (OBJ_COFF) && defined (TE_PE)
21646 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21650 /* In case we have a call or a branch to a function in ARM ISA mode from
21651 a thumb function or vice-versa force the relocation. These relocations
21652 are cleared off for some cores that might have blx and simple transformations
21656 switch (fixp
->fx_r_type
)
21658 case BFD_RELOC_ARM_PCREL_JUMP
:
21659 case BFD_RELOC_ARM_PCREL_CALL
:
21660 case BFD_RELOC_THUMB_PCREL_BLX
:
21661 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21665 case BFD_RELOC_ARM_PCREL_BLX
:
21666 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21667 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21668 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21669 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21678 /* Resolve these relocations even if the symbol is extern or weak. */
21679 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21680 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21681 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21682 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21683 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21684 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21685 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21688 /* Always leave these relocations for the linker. */
21689 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21690 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21691 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21694 /* Always generate relocations against function symbols. */
21695 if (fixp
->fx_r_type
== BFD_RELOC_32
21697 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21700 return generic_force_reloc (fixp
);
21703 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21704 /* Relocations against function names must be left unadjusted,
21705 so that the linker can use this information to generate interworking
21706 stubs. The MIPS version of this function
21707 also prevents relocations that are mips-16 specific, but I do not
21708 know why it does this.
21711 There is one other problem that ought to be addressed here, but
21712 which currently is not: Taking the address of a label (rather
21713 than a function) and then later jumping to that address. Such
21714 addresses also ought to have their bottom bit set (assuming that
21715 they reside in Thumb code), but at the moment they will not. */
21718 arm_fix_adjustable (fixS
* fixP
)
21720 if (fixP
->fx_addsy
== NULL
)
21723 /* Preserve relocations against symbols with function type. */
21724 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21727 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21728 && fixP
->fx_subsy
== NULL
)
21731 /* We need the symbol name for the VTABLE entries. */
21732 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21733 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21736 /* Don't allow symbols to be discarded on GOT related relocs. */
21737 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21738 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21739 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21740 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21741 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21742 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21743 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21744 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21745 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21748 /* Similarly for group relocations. */
21749 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21750 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21751 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21754 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21755 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21756 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21757 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21758 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21759 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21760 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21761 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21762 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21767 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21772 elf32_arm_target_format (void)
21775 return (target_big_endian
21776 ? "elf32-bigarm-symbian"
21777 : "elf32-littlearm-symbian");
21778 #elif defined (TE_VXWORKS)
21779 return (target_big_endian
21780 ? "elf32-bigarm-vxworks"
21781 : "elf32-littlearm-vxworks");
21783 if (target_big_endian
)
21784 return "elf32-bigarm";
21786 return "elf32-littlearm";
21791 armelf_frob_symbol (symbolS
* symp
,
21794 elf_frob_symbol (symp
, puntp
);
21798 /* MD interface: Finalization. */
21803 literal_pool
* pool
;
21805 /* Ensure that all the IT blocks are properly closed. */
21806 check_it_blocks_finished ();
21808 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21810 /* Put it at the end of the relevant section. */
21811 subseg_set (pool
->section
, pool
->sub_section
);
21813 arm_elf_change_section ();
21820 /* Remove any excess mapping symbols generated for alignment frags in
21821 SEC. We may have created a mapping symbol before a zero byte
21822 alignment; remove it if there's a mapping symbol after the
21825 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21826 void *dummy ATTRIBUTE_UNUSED
)
21828 segment_info_type
*seginfo
= seg_info (sec
);
21831 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21834 for (fragp
= seginfo
->frchainP
->frch_root
;
21836 fragp
= fragp
->fr_next
)
21838 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21839 fragS
*next
= fragp
->fr_next
;
21841 /* Variable-sized frags have been converted to fixed size by
21842 this point. But if this was variable-sized to start with,
21843 there will be a fixed-size frag after it. So don't handle
21845 if (sym
== NULL
|| next
== NULL
)
21848 if (S_GET_VALUE (sym
) < next
->fr_address
)
21849 /* Not at the end of this frag. */
21851 know (S_GET_VALUE (sym
) == next
->fr_address
);
21855 if (next
->tc_frag_data
.first_map
!= NULL
)
21857 /* Next frag starts with a mapping symbol. Discard this
21859 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21863 if (next
->fr_next
== NULL
)
21865 /* This mapping symbol is at the end of the section. Discard
21867 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21868 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21872 /* As long as we have empty frags without any mapping symbols,
21874 /* If the next frag is non-empty and does not start with a
21875 mapping symbol, then this mapping symbol is required. */
21876 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21879 next
= next
->fr_next
;
21881 while (next
!= NULL
);
21886 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21890 arm_adjust_symtab (void)
21895 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21897 if (ARM_IS_THUMB (sym
))
21899 if (THUMB_IS_FUNC (sym
))
21901 /* Mark the symbol as a Thumb function. */
21902 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21903 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21904 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21906 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21907 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21909 as_bad (_("%s: unexpected function type: %d"),
21910 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21912 else switch (S_GET_STORAGE_CLASS (sym
))
21915 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21918 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21921 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21929 if (ARM_IS_INTERWORK (sym
))
21930 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21937 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21939 if (ARM_IS_THUMB (sym
))
21941 elf_symbol_type
* elf_sym
;
21943 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21944 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21946 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21947 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21949 /* If it's a .thumb_func, declare it as so,
21950 otherwise tag label as .code 16. */
21951 if (THUMB_IS_FUNC (sym
))
21952 elf_sym
->internal_elf_sym
.st_info
=
21953 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21954 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21955 elf_sym
->internal_elf_sym
.st_info
=
21956 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21961 /* Remove any overlapping mapping symbols generated by alignment frags. */
21962 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21963 /* Now do generic ELF adjustments. */
21964 elf_adjust_symtab ();
21968 /* MD interface: Initialization. */
21971 set_constant_flonums (void)
21975 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21976 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21980 /* Auto-select Thumb mode if it's the only available instruction set for the
21981 given architecture. */
21984 autoselect_thumb_from_cpu_variant (void)
21986 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21987 opcode_select (16);
21996 if ( (arm_ops_hsh
= hash_new ()) == NULL
21997 || (arm_cond_hsh
= hash_new ()) == NULL
21998 || (arm_shift_hsh
= hash_new ()) == NULL
21999 || (arm_psr_hsh
= hash_new ()) == NULL
22000 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22001 || (arm_reg_hsh
= hash_new ()) == NULL
22002 || (arm_reloc_hsh
= hash_new ()) == NULL
22003 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22004 as_fatal (_("virtual memory exhausted"));
22006 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22007 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22008 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22009 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22010 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22011 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22012 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22013 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22014 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22015 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22016 (void *) (v7m_psrs
+ i
));
22017 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22018 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22020 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22022 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22023 (void *) (barrier_opt_names
+ i
));
22025 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22026 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22029 set_constant_flonums ();
22031 /* Set the cpu variant based on the command-line options. We prefer
22032 -mcpu= over -march= if both are set (as for GCC); and we prefer
22033 -mfpu= over any other way of setting the floating point unit.
22034 Use of legacy options with new options are faulted. */
22037 if (mcpu_cpu_opt
|| march_cpu_opt
)
22038 as_bad (_("use of old and new-style options to set CPU type"));
22040 mcpu_cpu_opt
= legacy_cpu
;
22042 else if (!mcpu_cpu_opt
)
22043 mcpu_cpu_opt
= march_cpu_opt
;
22048 as_bad (_("use of old and new-style options to set FPU type"));
22050 mfpu_opt
= legacy_fpu
;
22052 else if (!mfpu_opt
)
22054 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22055 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22056 /* Some environments specify a default FPU. If they don't, infer it
22057 from the processor. */
22059 mfpu_opt
= mcpu_fpu_opt
;
22061 mfpu_opt
= march_fpu_opt
;
22063 mfpu_opt
= &fpu_default
;
22069 if (mcpu_cpu_opt
!= NULL
)
22070 mfpu_opt
= &fpu_default
;
22071 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22072 mfpu_opt
= &fpu_arch_vfp_v2
;
22074 mfpu_opt
= &fpu_arch_fpa
;
22080 mcpu_cpu_opt
= &cpu_default
;
22081 selected_cpu
= cpu_default
;
22085 selected_cpu
= *mcpu_cpu_opt
;
22087 mcpu_cpu_opt
= &arm_arch_any
;
22090 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22092 autoselect_thumb_from_cpu_variant ();
22094 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22096 #if defined OBJ_COFF || defined OBJ_ELF
22098 unsigned int flags
= 0;
22100 #if defined OBJ_ELF
22101 flags
= meabi_flags
;
22103 switch (meabi_flags
)
22105 case EF_ARM_EABI_UNKNOWN
:
22107 /* Set the flags in the private structure. */
22108 if (uses_apcs_26
) flags
|= F_APCS26
;
22109 if (support_interwork
) flags
|= F_INTERWORK
;
22110 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22111 if (pic_code
) flags
|= F_PIC
;
22112 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22113 flags
|= F_SOFT_FLOAT
;
22115 switch (mfloat_abi_opt
)
22117 case ARM_FLOAT_ABI_SOFT
:
22118 case ARM_FLOAT_ABI_SOFTFP
:
22119 flags
|= F_SOFT_FLOAT
;
22122 case ARM_FLOAT_ABI_HARD
:
22123 if (flags
& F_SOFT_FLOAT
)
22124 as_bad (_("hard-float conflicts with specified fpu"));
22128 /* Using pure-endian doubles (even if soft-float). */
22129 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22130 flags
|= F_VFP_FLOAT
;
22132 #if defined OBJ_ELF
22133 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22134 flags
|= EF_ARM_MAVERICK_FLOAT
;
22137 case EF_ARM_EABI_VER4
:
22138 case EF_ARM_EABI_VER5
:
22139 /* No additional flags to set. */
22146 bfd_set_private_flags (stdoutput
, flags
);
22148 /* We have run out flags in the COFF header to encode the
22149 status of ATPCS support, so instead we create a dummy,
22150 empty, debug section called .arm.atpcs. */
22155 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22159 bfd_set_section_flags
22160 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22161 bfd_set_section_size (stdoutput
, sec
, 0);
22162 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22168 /* Record the CPU type as well. */
22169 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22170 mach
= bfd_mach_arm_iWMMXt2
;
22171 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22172 mach
= bfd_mach_arm_iWMMXt
;
22173 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22174 mach
= bfd_mach_arm_XScale
;
22175 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22176 mach
= bfd_mach_arm_ep9312
;
22177 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22178 mach
= bfd_mach_arm_5TE
;
22179 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22181 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22182 mach
= bfd_mach_arm_5T
;
22184 mach
= bfd_mach_arm_5
;
22186 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22188 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22189 mach
= bfd_mach_arm_4T
;
22191 mach
= bfd_mach_arm_4
;
22193 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22194 mach
= bfd_mach_arm_3M
;
22195 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22196 mach
= bfd_mach_arm_3
;
22197 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22198 mach
= bfd_mach_arm_2a
;
22199 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22200 mach
= bfd_mach_arm_2
;
22202 mach
= bfd_mach_arm_unknown
;
22204 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22207 /* Command line processing. */
22210 Invocation line includes a switch not recognized by the base assembler.
22211 See if it's a processor-specific option.
22213 This routine is somewhat complicated by the need for backwards
22214 compatibility (since older releases of gcc can't be changed).
22215 The new options try to make the interface as compatible as
22218 New options (supported) are:
22220 -mcpu=<cpu name> Assemble for selected processor
22221 -march=<architecture name> Assemble for selected architecture
22222 -mfpu=<fpu architecture> Assemble for selected FPU.
22223 -EB/-mbig-endian Big-endian
22224 -EL/-mlittle-endian Little-endian
22225 -k Generate PIC code
22226 -mthumb Start in Thumb mode
22227 -mthumb-interwork Code supports ARM/Thumb interworking
22229 -m[no-]warn-deprecated Warn about deprecated features
22231 For now we will also provide support for:
22233 -mapcs-32 32-bit Program counter
22234 -mapcs-26 26-bit Program counter
22235 -macps-float Floats passed in FP registers
22236 -mapcs-reentrant Reentrant code
22238 (sometime these will probably be replaced with -mapcs=<list of options>
22239 and -matpcs=<list of options>)
22241 The remaining options are only supported for back-wards compatibility.
22242 Cpu variants, the arm part is optional:
22243 -m[arm]1 Currently not supported.
22244 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22245 -m[arm]3 Arm 3 processor
22246 -m[arm]6[xx], Arm 6 processors
22247 -m[arm]7[xx][t][[d]m] Arm 7 processors
22248 -m[arm]8[10] Arm 8 processors
22249 -m[arm]9[20][tdmi] Arm 9 processors
22250 -mstrongarm[110[0]] StrongARM processors
22251 -mxscale XScale processors
22252 -m[arm]v[2345[t[e]]] Arm architectures
22253 -mall All (except the ARM1)
22255 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22256 -mfpe-old (No float load/store multiples)
22257 -mvfpxd VFP Single precision
22259 -mno-fpu Disable all floating point instructions
22261 The following CPU names are recognized:
22262 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22263 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22264 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22265 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22266 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22267 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22268 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22272 const char * md_shortopts
= "m:k";
22274 #ifdef ARM_BI_ENDIAN
22275 #define OPTION_EB (OPTION_MD_BASE + 0)
22276 #define OPTION_EL (OPTION_MD_BASE + 1)
22278 #if TARGET_BYTES_BIG_ENDIAN
22279 #define OPTION_EB (OPTION_MD_BASE + 0)
22281 #define OPTION_EL (OPTION_MD_BASE + 1)
22284 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22286 struct option md_longopts
[] =
22289 {"EB", no_argument
, NULL
, OPTION_EB
},
22292 {"EL", no_argument
, NULL
, OPTION_EL
},
22294 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22295 {NULL
, no_argument
, NULL
, 0}
22298 size_t md_longopts_size
= sizeof (md_longopts
);
22300 struct arm_option_table
22302 char *option
; /* Option name to match. */
22303 char *help
; /* Help information. */
22304 int *var
; /* Variable to change. */
22305 int value
; /* What to change it to. */
22306 char *deprecated
; /* If non-null, print this message. */
22309 struct arm_option_table arm_opts
[] =
22311 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22312 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22313 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22314 &support_interwork
, 1, NULL
},
22315 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22316 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22317 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22319 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22320 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22321 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22322 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22325 /* These are recognized by the assembler, but have no affect on code. */
22326 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22327 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22329 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22330 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22331 &warn_on_deprecated
, 0, NULL
},
22332 {NULL
, NULL
, NULL
, 0, NULL
}
22335 struct arm_legacy_option_table
22337 char *option
; /* Option name to match. */
22338 const arm_feature_set
**var
; /* Variable to change. */
22339 const arm_feature_set value
; /* What to change it to. */
22340 char *deprecated
; /* If non-null, print this message. */
22343 const struct arm_legacy_option_table arm_legacy_opts
[] =
22345 /* DON'T add any new processors to this list -- we want the whole list
22346 to go away... Add them to the processors table instead. */
22347 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22348 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22349 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22350 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22351 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22352 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22353 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22354 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22355 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22356 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22357 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22358 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22359 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22360 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22361 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22362 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22363 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22364 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22365 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22366 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22367 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22368 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22369 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22370 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22371 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22372 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22373 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22374 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22375 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22376 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22377 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22378 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22379 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22380 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22381 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22382 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22383 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22384 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22385 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22386 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22387 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22388 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22389 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22390 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22391 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22392 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22393 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22394 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22395 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22396 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22397 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22398 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22399 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22400 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22401 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22402 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22403 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22404 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22405 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22406 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22407 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22408 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22409 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22410 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22411 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22412 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22413 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22414 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22415 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22416 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22417 N_("use -mcpu=strongarm110")},
22418 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22419 N_("use -mcpu=strongarm1100")},
22420 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22421 N_("use -mcpu=strongarm1110")},
22422 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22423 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22424 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22426 /* Architecture variants -- don't add any more to this list either. */
22427 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22428 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22429 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22430 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22431 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22432 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22433 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22434 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22435 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22436 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22437 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22438 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22439 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22440 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22441 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22442 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22443 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22444 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22446 /* Floating point variants -- don't add any more to this list either. */
22447 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22448 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22449 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22450 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22451 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22453 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22456 struct arm_cpu_option_table
22459 const arm_feature_set value
;
22460 /* For some CPUs we assume an FPU unless the user explicitly sets
22462 const arm_feature_set default_fpu
;
22463 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22465 const char *canonical_name
;
22468 /* This list should, at a minimum, contain all the cpu names
22469 recognized by GCC. */
22470 static const struct arm_cpu_option_table arm_cpus
[] =
22472 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22473 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22474 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22475 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22476 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22477 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22478 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22479 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22480 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22481 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22482 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22483 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22484 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22485 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22486 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22487 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22488 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22489 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22490 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22491 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22492 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22493 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22494 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22495 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22496 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22497 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22498 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22499 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22500 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22501 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22502 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22503 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22504 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22505 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22506 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22507 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22508 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22509 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22510 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22511 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22512 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22513 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22514 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22515 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22516 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22517 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22518 /* For V5 or later processors we default to using VFP; but the user
22519 should really set the FPU type explicitly. */
22520 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22521 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22522 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22523 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22524 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22525 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22526 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22527 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22528 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22529 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22530 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22531 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22532 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22533 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22534 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22535 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22536 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22537 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22538 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22539 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22540 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22541 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22542 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22543 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22544 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22545 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22546 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22547 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22548 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22549 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22550 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22551 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22552 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22553 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22554 FPU_NONE
, "Cortex-A5"},
22555 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22556 ARM_FEATURE (0, FPU_VFP_V3
22557 | FPU_NEON_EXT_V1
),
22559 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22560 ARM_FEATURE (0, FPU_VFP_V3
22561 | FPU_NEON_EXT_V1
),
22563 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22564 FPU_ARCH_NEON_VFP_V4
,
22566 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22567 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22569 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22570 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22571 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22572 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22573 /* ??? XSCALE is really an architecture. */
22574 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22575 /* ??? iwmmxt is not a processor. */
22576 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22577 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22578 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22580 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22581 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22584 struct arm_arch_option_table
22587 const arm_feature_set value
;
22588 const arm_feature_set default_fpu
;
22591 /* This list should, at a minimum, contain all the architecture names
22592 recognized by GCC. */
22593 static const struct arm_arch_option_table arm_archs
[] =
22595 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22596 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22597 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22598 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22599 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22600 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22601 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22602 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22603 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22604 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22605 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22606 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22607 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22608 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22609 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22610 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22611 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22612 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22613 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22614 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22615 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22616 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22617 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22618 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22619 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22620 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22621 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22622 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22623 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22624 /* The official spelling of the ARMv7 profile variants is the dashed form.
22625 Accept the non-dashed form for compatibility with old toolchains. */
22626 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22627 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22628 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22629 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22630 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22631 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22632 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22633 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22634 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22635 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22636 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22639 /* ISA extensions in the co-processor and main instruction set space. */
22640 struct arm_option_extension_value_table
22643 const arm_feature_set value
;
22644 const arm_feature_set allowed_archs
;
22647 /* The following table must be in alphabetical order with a NULL last entry.
22649 static const struct arm_option_extension_value_table arm_extensions
[] =
22651 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22652 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22653 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22654 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22655 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22656 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22657 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22658 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
22659 ARM_FEATURE (ARM_EXT_V6M
, 0)},
22660 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
22661 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
22662 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22663 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22664 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22665 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22668 /* ISA floating-point and Advanced SIMD extensions. */
22669 struct arm_option_fpu_value_table
22672 const arm_feature_set value
;
22675 /* This list should, at a minimum, contain all the fpu names
22676 recognized by GCC. */
22677 static const struct arm_option_fpu_value_table arm_fpus
[] =
22679 {"softfpa", FPU_NONE
},
22680 {"fpe", FPU_ARCH_FPE
},
22681 {"fpe2", FPU_ARCH_FPE
},
22682 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22683 {"fpa", FPU_ARCH_FPA
},
22684 {"fpa10", FPU_ARCH_FPA
},
22685 {"fpa11", FPU_ARCH_FPA
},
22686 {"arm7500fe", FPU_ARCH_FPA
},
22687 {"softvfp", FPU_ARCH_VFP
},
22688 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22689 {"vfp", FPU_ARCH_VFP_V2
},
22690 {"vfp9", FPU_ARCH_VFP_V2
},
22691 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22692 {"vfp10", FPU_ARCH_VFP_V2
},
22693 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22694 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22695 {"vfpv2", FPU_ARCH_VFP_V2
},
22696 {"vfpv3", FPU_ARCH_VFP_V3
},
22697 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22698 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22699 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22700 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22701 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22702 {"arm1020t", FPU_ARCH_VFP_V1
},
22703 {"arm1020e", FPU_ARCH_VFP_V2
},
22704 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22705 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22706 {"maverick", FPU_ARCH_MAVERICK
},
22707 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22708 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22709 {"vfpv4", FPU_ARCH_VFP_V4
},
22710 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22711 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22712 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22713 {NULL
, ARM_ARCH_NONE
}
22716 struct arm_option_value_table
22722 static const struct arm_option_value_table arm_float_abis
[] =
22724 {"hard", ARM_FLOAT_ABI_HARD
},
22725 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22726 {"soft", ARM_FLOAT_ABI_SOFT
},
22731 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22732 static const struct arm_option_value_table arm_eabis
[] =
22734 {"gnu", EF_ARM_EABI_UNKNOWN
},
22735 {"4", EF_ARM_EABI_VER4
},
22736 {"5", EF_ARM_EABI_VER5
},
22741 struct arm_long_option_table
22743 char * option
; /* Substring to match. */
22744 char * help
; /* Help information. */
22745 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22746 char * deprecated
; /* If non-null, print this message. */
22750 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22752 arm_feature_set
*ext_set
= (arm_feature_set
*)
22753 xmalloc (sizeof (arm_feature_set
));
22755 /* We insist on extensions being specified in alphabetical order, and with
22756 extensions being added before being removed. We achieve this by having
22757 the global ARM_EXTENSIONS table in alphabetical order, and using the
22758 ADDING_VALUE variable to indicate whether we are adding an extension (1)
22759 or removing it (0) and only allowing it to change in the order
22761 const struct arm_option_extension_value_table
* opt
= NULL
;
22762 int adding_value
= -1;
22764 /* Copy the feature set, so that we can modify it. */
22765 *ext_set
= **opt_p
;
22768 while (str
!= NULL
&& *str
!= 0)
22775 as_bad (_("invalid architectural extension"));
22780 ext
= strchr (str
, '+');
22783 optlen
= ext
- str
;
22785 optlen
= strlen (str
);
22788 && strncmp (str
, "no", 2) == 0)
22790 if (adding_value
!= 0)
22793 opt
= arm_extensions
;
22799 else if (optlen
> 0)
22801 if (adding_value
== -1)
22804 opt
= arm_extensions
;
22806 else if (adding_value
!= 1)
22808 as_bad (_("must specify extensions to add before specifying "
22809 "those to remove"));
22816 as_bad (_("missing architectural extension"));
22820 gas_assert (adding_value
!= -1);
22821 gas_assert (opt
!= NULL
);
22823 /* Scan over the options table trying to find an exact match. */
22824 for (; opt
->name
!= NULL
; opt
++)
22825 if (strncmp (opt
->name
, str
, optlen
) == 0
22826 && strlen (opt
->name
) == optlen
)
22828 /* Check we can apply the extension to this architecture. */
22829 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
22831 as_bad (_("extension does not apply to the base architecture"));
22835 /* Add or remove the extension. */
22837 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22839 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
22844 if (opt
->name
== NULL
)
22846 /* Did we fail to find an extension because it wasn't specified in
22847 alphabetical order, or because it does not exist? */
22849 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22850 if (strncmp (opt
->name
, str
, optlen
) == 0)
22853 if (opt
->name
== NULL
)
22854 as_bad (_("unknown architectural extension `%s'"), str
);
22856 as_bad (_("architectural extensions must be specified in "
22857 "alphabetical order"));
22863 /* We should skip the extension we've just matched the next time
22875 arm_parse_cpu (char * str
)
22877 const struct arm_cpu_option_table
* opt
;
22878 char * ext
= strchr (str
, '+');
22882 optlen
= ext
- str
;
22884 optlen
= strlen (str
);
22888 as_bad (_("missing cpu name `%s'"), str
);
22892 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22893 if (strncmp (opt
->name
, str
, optlen
) == 0)
22895 mcpu_cpu_opt
= &opt
->value
;
22896 mcpu_fpu_opt
= &opt
->default_fpu
;
22897 if (opt
->canonical_name
)
22898 strcpy (selected_cpu_name
, opt
->canonical_name
);
22903 for (i
= 0; i
< optlen
; i
++)
22904 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22905 selected_cpu_name
[i
] = 0;
22909 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22914 as_bad (_("unknown cpu `%s'"), str
);
22919 arm_parse_arch (char * str
)
22921 const struct arm_arch_option_table
*opt
;
22922 char *ext
= strchr (str
, '+');
22926 optlen
= ext
- str
;
22928 optlen
= strlen (str
);
22932 as_bad (_("missing architecture name `%s'"), str
);
22936 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22937 if (strncmp (opt
->name
, str
, optlen
) == 0)
22939 march_cpu_opt
= &opt
->value
;
22940 march_fpu_opt
= &opt
->default_fpu
;
22941 strcpy (selected_cpu_name
, opt
->name
);
22944 return arm_parse_extension (ext
, &march_cpu_opt
);
22949 as_bad (_("unknown architecture `%s'\n"), str
);
22954 arm_parse_fpu (char * str
)
22956 const struct arm_option_fpu_value_table
* opt
;
22958 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22959 if (streq (opt
->name
, str
))
22961 mfpu_opt
= &opt
->value
;
22965 as_bad (_("unknown floating point format `%s'\n"), str
);
22970 arm_parse_float_abi (char * str
)
22972 const struct arm_option_value_table
* opt
;
22974 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22975 if (streq (opt
->name
, str
))
22977 mfloat_abi_opt
= opt
->value
;
22981 as_bad (_("unknown floating point abi `%s'\n"), str
);
22987 arm_parse_eabi (char * str
)
22989 const struct arm_option_value_table
*opt
;
22991 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22992 if (streq (opt
->name
, str
))
22994 meabi_flags
= opt
->value
;
22997 as_bad (_("unknown EABI `%s'\n"), str
);
23003 arm_parse_it_mode (char * str
)
23005 bfd_boolean ret
= TRUE
;
23007 if (streq ("arm", str
))
23008 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23009 else if (streq ("thumb", str
))
23010 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23011 else if (streq ("always", str
))
23012 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23013 else if (streq ("never", str
))
23014 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23017 as_bad (_("unknown implicit IT mode `%s', should be "\
23018 "arm, thumb, always, or never."), str
);
23025 struct arm_long_option_table arm_long_opts
[] =
23027 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23028 arm_parse_cpu
, NULL
},
23029 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23030 arm_parse_arch
, NULL
},
23031 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23032 arm_parse_fpu
, NULL
},
23033 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23034 arm_parse_float_abi
, NULL
},
23036 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23037 arm_parse_eabi
, NULL
},
23039 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23040 arm_parse_it_mode
, NULL
},
23041 {NULL
, NULL
, 0, NULL
}
23045 md_parse_option (int c
, char * arg
)
23047 struct arm_option_table
*opt
;
23048 const struct arm_legacy_option_table
*fopt
;
23049 struct arm_long_option_table
*lopt
;
23055 target_big_endian
= 1;
23061 target_big_endian
= 0;
23065 case OPTION_FIX_V4BX
:
23070 /* Listing option. Just ignore these, we don't support additional
23075 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23077 if (c
== opt
->option
[0]
23078 && ((arg
== NULL
&& opt
->option
[1] == 0)
23079 || streq (arg
, opt
->option
+ 1)))
23081 /* If the option is deprecated, tell the user. */
23082 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23083 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23084 arg
? arg
: "", _(opt
->deprecated
));
23086 if (opt
->var
!= NULL
)
23087 *opt
->var
= opt
->value
;
23093 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23095 if (c
== fopt
->option
[0]
23096 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23097 || streq (arg
, fopt
->option
+ 1)))
23099 /* If the option is deprecated, tell the user. */
23100 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23101 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23102 arg
? arg
: "", _(fopt
->deprecated
));
23104 if (fopt
->var
!= NULL
)
23105 *fopt
->var
= &fopt
->value
;
23111 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23113 /* These options are expected to have an argument. */
23114 if (c
== lopt
->option
[0]
23116 && strncmp (arg
, lopt
->option
+ 1,
23117 strlen (lopt
->option
+ 1)) == 0)
23119 /* If the option is deprecated, tell the user. */
23120 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23121 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23122 _(lopt
->deprecated
));
23124 /* Call the sup-option parser. */
23125 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23136 md_show_usage (FILE * fp
)
23138 struct arm_option_table
*opt
;
23139 struct arm_long_option_table
*lopt
;
23141 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23143 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23144 if (opt
->help
!= NULL
)
23145 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23147 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23148 if (lopt
->help
!= NULL
)
23149 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23153 -EB assemble code for a big-endian cpu\n"));
23158 -EL assemble code for a little-endian cpu\n"));
23162 --fix-v4bx Allow BX in ARMv4 code\n"));
23170 arm_feature_set flags
;
23171 } cpu_arch_ver_table
;
23173 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23174 least features first. */
23175 static const cpu_arch_ver_table cpu_arch_ver
[] =
23181 {4, ARM_ARCH_V5TE
},
23182 {5, ARM_ARCH_V5TEJ
},
23186 {11, ARM_ARCH_V6M
},
23187 {12, ARM_ARCH_V6SM
},
23188 {8, ARM_ARCH_V6T2
},
23189 {10, ARM_ARCH_V7A
},
23190 {10, ARM_ARCH_V7R
},
23191 {10, ARM_ARCH_V7M
},
23195 /* Set an attribute if it has not already been set by the user. */
23197 aeabi_set_attribute_int (int tag
, int value
)
23200 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23201 || !attributes_set_explicitly
[tag
])
23202 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23206 aeabi_set_attribute_string (int tag
, const char *value
)
23209 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23210 || !attributes_set_explicitly
[tag
])
23211 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23214 /* Set the public EABI object attributes. */
23216 aeabi_set_public_attributes (void)
23220 arm_feature_set flags
;
23221 arm_feature_set tmp
;
23222 const cpu_arch_ver_table
*p
;
23224 /* Choose the architecture based on the capabilities of the requested cpu
23225 (if any) and/or the instructions actually used. */
23226 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23227 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23228 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23229 /*Allow the user to override the reported architecture. */
23232 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23233 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23236 /* We need to make sure that the attributes do not identify us as v6S-M
23237 when the only v6S-M feature in use is the Operating System Extensions. */
23238 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23239 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23240 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23244 for (p
= cpu_arch_ver
; p
->val
; p
++)
23246 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23249 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23253 /* The table lookup above finds the last architecture to contribute
23254 a new feature. Unfortunately, Tag13 is a subset of the union of
23255 v6T2 and v7-M, so it is never seen as contributing a new feature.
23256 We can not search for the last entry which is entirely used,
23257 because if no CPU is specified we build up only those flags
23258 actually used. Perhaps we should separate out the specified
23259 and implicit cases. Avoid taking this path for -march=all by
23260 checking for contradictory v7-A / v7-M features. */
23262 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23263 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23264 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23267 /* Tag_CPU_name. */
23268 if (selected_cpu_name
[0])
23272 q
= selected_cpu_name
;
23273 if (strncmp (q
, "armv", 4) == 0)
23278 for (i
= 0; q
[i
]; i
++)
23279 q
[i
] = TOUPPER (q
[i
]);
23281 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23284 /* Tag_CPU_arch. */
23285 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23287 /* Tag_CPU_arch_profile. */
23288 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23289 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23290 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23291 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23292 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23293 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23295 /* Tag_ARM_ISA_use. */
23296 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23298 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23300 /* Tag_THUMB_ISA_use. */
23301 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23303 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23304 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23306 /* Tag_VFP_arch. */
23307 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23308 aeabi_set_attribute_int (Tag_VFP_arch
,
23309 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23311 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23312 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23313 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23314 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23315 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23316 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23317 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23318 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23319 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23321 /* Tag_ABI_HardFP_use. */
23322 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23323 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23324 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23326 /* Tag_WMMX_arch. */
23327 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23328 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23329 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23330 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23332 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23333 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23334 aeabi_set_attribute_int
23335 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23338 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23339 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23340 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23343 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23344 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23345 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23346 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23348 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23350 /* Tag_MP_extension_use. */
23351 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23352 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23354 /* Tag Virtualization_use. */
23355 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23357 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23360 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23363 /* Add the default contents for the .ARM.attributes section. */
23367 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23370 aeabi_set_public_attributes ();
23372 #endif /* OBJ_ELF */
23375 /* Parse a .cpu directive. */
23378 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23380 const struct arm_cpu_option_table
*opt
;
23384 name
= input_line_pointer
;
23385 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23386 input_line_pointer
++;
23387 saved_char
= *input_line_pointer
;
23388 *input_line_pointer
= 0;
23390 /* Skip the first "all" entry. */
23391 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23392 if (streq (opt
->name
, name
))
23394 mcpu_cpu_opt
= &opt
->value
;
23395 selected_cpu
= opt
->value
;
23396 if (opt
->canonical_name
)
23397 strcpy (selected_cpu_name
, opt
->canonical_name
);
23401 for (i
= 0; opt
->name
[i
]; i
++)
23402 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23403 selected_cpu_name
[i
] = 0;
23405 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23406 *input_line_pointer
= saved_char
;
23407 demand_empty_rest_of_line ();
23410 as_bad (_("unknown cpu `%s'"), name
);
23411 *input_line_pointer
= saved_char
;
23412 ignore_rest_of_line ();
23416 /* Parse a .arch directive. */
23419 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23421 const struct arm_arch_option_table
*opt
;
23425 name
= input_line_pointer
;
23426 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23427 input_line_pointer
++;
23428 saved_char
= *input_line_pointer
;
23429 *input_line_pointer
= 0;
23431 /* Skip the first "all" entry. */
23432 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23433 if (streq (opt
->name
, name
))
23435 mcpu_cpu_opt
= &opt
->value
;
23436 selected_cpu
= opt
->value
;
23437 strcpy (selected_cpu_name
, opt
->name
);
23438 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23439 *input_line_pointer
= saved_char
;
23440 demand_empty_rest_of_line ();
23444 as_bad (_("unknown architecture `%s'\n"), name
);
23445 *input_line_pointer
= saved_char
;
23446 ignore_rest_of_line ();
23450 /* Parse a .object_arch directive. */
23453 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23455 const struct arm_arch_option_table
*opt
;
23459 name
= input_line_pointer
;
23460 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23461 input_line_pointer
++;
23462 saved_char
= *input_line_pointer
;
23463 *input_line_pointer
= 0;
23465 /* Skip the first "all" entry. */
23466 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23467 if (streq (opt
->name
, name
))
23469 object_arch
= &opt
->value
;
23470 *input_line_pointer
= saved_char
;
23471 demand_empty_rest_of_line ();
23475 as_bad (_("unknown architecture `%s'\n"), name
);
23476 *input_line_pointer
= saved_char
;
23477 ignore_rest_of_line ();
23480 /* Parse a .arch_extension directive. */
23483 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23485 const struct arm_option_extension_value_table
*opt
;
23488 int adding_value
= 1;
23490 name
= input_line_pointer
;
23491 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23492 input_line_pointer
++;
23493 saved_char
= *input_line_pointer
;
23494 *input_line_pointer
= 0;
23496 if (strlen (name
) >= 2
23497 && strncmp (name
, "no", 2) == 0)
23503 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23504 if (streq (opt
->name
, name
))
23506 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23508 as_bad (_("architectural extension `%s' is not allowed for the "
23509 "current base architecture"), name
);
23514 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23516 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23518 mcpu_cpu_opt
= &selected_cpu
;
23519 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23520 *input_line_pointer
= saved_char
;
23521 demand_empty_rest_of_line ();
23525 if (opt
->name
== NULL
)
23526 as_bad (_("unknown architecture `%s'\n"), name
);
23528 *input_line_pointer
= saved_char
;
23529 ignore_rest_of_line ();
23532 /* Parse a .fpu directive. */
23535 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23537 const struct arm_option_fpu_value_table
*opt
;
23541 name
= input_line_pointer
;
23542 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23543 input_line_pointer
++;
23544 saved_char
= *input_line_pointer
;
23545 *input_line_pointer
= 0;
23547 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23548 if (streq (opt
->name
, name
))
23550 mfpu_opt
= &opt
->value
;
23551 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23552 *input_line_pointer
= saved_char
;
23553 demand_empty_rest_of_line ();
23557 as_bad (_("unknown floating point format `%s'\n"), name
);
23558 *input_line_pointer
= saved_char
;
23559 ignore_rest_of_line ();
23562 /* Copy symbol information. */
23565 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23567 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23571 /* Given a symbolic attribute NAME, return the proper integer value.
23572 Returns -1 if the attribute is not known. */
23575 arm_convert_symbolic_attribute (const char *name
)
23577 static const struct
23582 attribute_table
[] =
23584 /* When you modify this table you should
23585 also modify the list in doc/c-arm.texi. */
23586 #define T(tag) {#tag, tag}
23587 T (Tag_CPU_raw_name
),
23590 T (Tag_CPU_arch_profile
),
23591 T (Tag_ARM_ISA_use
),
23592 T (Tag_THUMB_ISA_use
),
23596 T (Tag_Advanced_SIMD_arch
),
23597 T (Tag_PCS_config
),
23598 T (Tag_ABI_PCS_R9_use
),
23599 T (Tag_ABI_PCS_RW_data
),
23600 T (Tag_ABI_PCS_RO_data
),
23601 T (Tag_ABI_PCS_GOT_use
),
23602 T (Tag_ABI_PCS_wchar_t
),
23603 T (Tag_ABI_FP_rounding
),
23604 T (Tag_ABI_FP_denormal
),
23605 T (Tag_ABI_FP_exceptions
),
23606 T (Tag_ABI_FP_user_exceptions
),
23607 T (Tag_ABI_FP_number_model
),
23608 T (Tag_ABI_align_needed
),
23609 T (Tag_ABI_align8_needed
),
23610 T (Tag_ABI_align_preserved
),
23611 T (Tag_ABI_align8_preserved
),
23612 T (Tag_ABI_enum_size
),
23613 T (Tag_ABI_HardFP_use
),
23614 T (Tag_ABI_VFP_args
),
23615 T (Tag_ABI_WMMX_args
),
23616 T (Tag_ABI_optimization_goals
),
23617 T (Tag_ABI_FP_optimization_goals
),
23618 T (Tag_compatibility
),
23619 T (Tag_CPU_unaligned_access
),
23620 T (Tag_FP_HP_extension
),
23621 T (Tag_VFP_HP_extension
),
23622 T (Tag_ABI_FP_16bit_format
),
23623 T (Tag_MPextension_use
),
23625 T (Tag_nodefaults
),
23626 T (Tag_also_compatible_with
),
23627 T (Tag_conformance
),
23629 T (Tag_Virtualization_use
),
23630 /* We deliberately do not include Tag_MPextension_use_legacy. */
23638 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23639 if (streq (name
, attribute_table
[i
].name
))
23640 return attribute_table
[i
].tag
;
23646 /* Apply sym value for relocations only in the case that
23647 they are for local symbols and you have the respective
23648 architectural feature for blx and simple switches. */
23650 arm_apply_sym_value (struct fix
* fixP
)
23653 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23654 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23656 switch (fixP
->fx_r_type
)
23658 case BFD_RELOC_ARM_PCREL_BLX
:
23659 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23660 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23664 case BFD_RELOC_ARM_PCREL_CALL
:
23665 case BFD_RELOC_THUMB_PCREL_BLX
:
23666 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23677 #endif /* OBJ_ELF */