1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
,
205 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
206 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
207 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
208 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
209 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
210 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
211 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
212 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
213 static const arm_feature_set arm_ext_v8m_main
=
214 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
215 /* Instructions in ARMv8-M only found in M profile architectures. */
216 static const arm_feature_set arm_ext_v8m_m_only
=
217 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
218 static const arm_feature_set arm_ext_v6t2_v8m
=
219 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
220 /* Instructions shared between ARMv8-A and ARMv8-M. */
221 static const arm_feature_set arm_ext_atomics
=
222 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
223 /* DSP instructions Tag_DSP_extension refers to. */
224 static const arm_feature_set arm_ext_dsp
=
225 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
226 static const arm_feature_set arm_ext_v8_2
=
227 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
228 /* FP16 instructions. */
229 static const arm_feature_set arm_ext_fp16
=
230 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
232 static const arm_feature_set arm_arch_any
= ARM_ANY
;
233 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
234 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
235 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
236 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
238 static const arm_feature_set arm_cext_iwmmxt2
=
239 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
240 static const arm_feature_set arm_cext_iwmmxt
=
241 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
242 static const arm_feature_set arm_cext_xscale
=
243 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
244 static const arm_feature_set arm_cext_maverick
=
245 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
246 static const arm_feature_set fpu_fpa_ext_v1
=
247 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
248 static const arm_feature_set fpu_fpa_ext_v2
=
249 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
250 static const arm_feature_set fpu_vfp_ext_v1xd
=
251 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
252 static const arm_feature_set fpu_vfp_ext_v1
=
253 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
254 static const arm_feature_set fpu_vfp_ext_v2
=
255 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
256 static const arm_feature_set fpu_vfp_ext_v3xd
=
257 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
258 static const arm_feature_set fpu_vfp_ext_v3
=
259 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
260 static const arm_feature_set fpu_vfp_ext_d32
=
261 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
262 static const arm_feature_set fpu_neon_ext_v1
=
263 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
264 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
265 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
266 static const arm_feature_set fpu_vfp_fp16
=
267 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
268 static const arm_feature_set fpu_neon_ext_fma
=
269 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
270 static const arm_feature_set fpu_vfp_ext_fma
=
271 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
272 static const arm_feature_set fpu_vfp_ext_armv8
=
273 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
274 static const arm_feature_set fpu_vfp_ext_armv8xd
=
275 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
276 static const arm_feature_set fpu_neon_ext_armv8
=
277 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
278 static const arm_feature_set fpu_crypto_ext_armv8
=
279 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
280 static const arm_feature_set crc_ext_armv8
=
281 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
282 static const arm_feature_set fpu_neon_ext_v8_1
=
283 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
285 static int mfloat_abi_opt
= -1;
286 /* Record user cpu selection for object attributes. */
287 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
288 /* Must be long enough to hold any of the names in arm_cpus. */
289 static char selected_cpu_name
[20];
291 extern FLONUM_TYPE generic_floating_point_number
;
293 /* Return if no cpu was selected on command-line. */
295 no_cpu_selected (void)
297 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
302 static int meabi_flags
= EABI_DEFAULT
;
304 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
307 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
312 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
317 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
318 symbolS
* GOT_symbol
;
321 /* 0: assemble for ARM,
322 1: assemble for Thumb,
323 2: assemble for Thumb even though target CPU does not support thumb
325 static int thumb_mode
= 0;
326 /* A value distinct from the possible values for thumb_mode that we
327 can use to record whether thumb_mode has been copied into the
328 tc_frag_data field of a frag. */
329 #define MODE_RECORDED (1 << 4)
331 /* Specifies the intrinsic IT insn behavior mode. */
332 enum implicit_it_mode
334 IMPLICIT_IT_MODE_NEVER
= 0x00,
335 IMPLICIT_IT_MODE_ARM
= 0x01,
336 IMPLICIT_IT_MODE_THUMB
= 0x02,
337 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
339 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
341 /* If unified_syntax is true, we are processing the new unified
342 ARM/Thumb syntax. Important differences from the old ARM mode:
344 - Immediate operands do not require a # prefix.
345 - Conditional affixes always appear at the end of the
346 instruction. (For backward compatibility, those instructions
347 that formerly had them in the middle, continue to accept them
349 - The IT instruction may appear, and if it does is validated
350 against subsequent conditional affixes. It does not generate
353 Important differences from the old Thumb mode:
355 - Immediate operands do not require a # prefix.
356 - Most of the V6T2 instructions are only available in unified mode.
357 - The .N and .W suffixes are recognized and honored (it is an error
358 if they cannot be honored).
359 - All instructions set the flags if and only if they have an 's' affix.
360 - Conditional affixes may be used. They are validated against
361 preceding IT instructions. Unlike ARM mode, you cannot use a
362 conditional affix except in the scope of an IT instruction. */
364 static bfd_boolean unified_syntax
= FALSE
;
366 /* An immediate operand can start with #, and ld*, st*, pld operands
367 can contain [ and ]. We need to tell APP not to elide whitespace
368 before a [, which can appear as the first operand for pld.
369 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
370 const char arm_symbol_chars
[] = "#[]{}";
385 enum neon_el_type type
;
389 #define NEON_MAX_TYPE_ELS 4
393 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
397 enum it_instruction_type
402 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
403 if inside, should be the last one. */
404 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
405 i.e. BKPT and NOP. */
406 IT_INSN
/* The IT insn has been parsed. */
409 /* The maximum number of operands we need. */
410 #define ARM_IT_MAX_OPERANDS 6
415 unsigned long instruction
;
419 /* "uncond_value" is set to the value in place of the conditional field in
420 unconditional versions of the instruction, or -1 if nothing is
423 struct neon_type vectype
;
424 /* This does not indicate an actual NEON instruction, only that
425 the mnemonic accepts neon-style type suffixes. */
427 /* Set to the opcode if the instruction needs relaxation.
428 Zero if the instruction is not relaxed. */
432 bfd_reloc_code_real_type type
;
437 enum it_instruction_type it_insn_type
;
443 struct neon_type_el vectype
;
444 unsigned present
: 1; /* Operand present. */
445 unsigned isreg
: 1; /* Operand was a register. */
446 unsigned immisreg
: 1; /* .imm field is a second register. */
447 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
448 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
449 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
450 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
451 instructions. This allows us to disambiguate ARM <-> vector insns. */
452 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
453 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
454 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
455 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
456 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
457 unsigned writeback
: 1; /* Operand has trailing ! */
458 unsigned preind
: 1; /* Preindexed address. */
459 unsigned postind
: 1; /* Postindexed address. */
460 unsigned negative
: 1; /* Index register was negated. */
461 unsigned shifted
: 1; /* Shift applied to operation. */
462 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
463 } operands
[ARM_IT_MAX_OPERANDS
];
466 static struct arm_it inst
;
468 #define NUM_FLOAT_VALS 8
470 const char * fp_const
[] =
472 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
475 /* Number of littlenums required to hold an extended precision number. */
476 #define MAX_LITTLENUMS 6
478 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
488 #define CP_T_X 0x00008000
489 #define CP_T_Y 0x00400000
491 #define CONDS_BIT 0x00100000
492 #define LOAD_BIT 0x00100000
494 #define DOUBLE_LOAD_FLAG 0x00000001
498 const char * template_name
;
502 #define COND_ALWAYS 0xE
506 const char * template_name
;
510 struct asm_barrier_opt
512 const char * template_name
;
514 const arm_feature_set arch
;
517 /* The bit that distinguishes CPSR and SPSR. */
518 #define SPSR_BIT (1 << 22)
520 /* The individual PSR flag bits. */
521 #define PSR_c (1 << 16)
522 #define PSR_x (1 << 17)
523 #define PSR_s (1 << 18)
524 #define PSR_f (1 << 19)
529 bfd_reloc_code_real_type reloc
;
534 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
535 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
540 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
543 /* Bits for DEFINED field in neon_typed_alias. */
544 #define NTA_HASTYPE 1
545 #define NTA_HASINDEX 2
547 struct neon_typed_alias
549 unsigned char defined
;
551 struct neon_type_el eltype
;
554 /* ARM register categories. This includes coprocessor numbers and various
555 architecture extensions' registers. */
582 /* Structure for a hash table entry for a register.
583 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
584 information which states whether a vector type or index is specified (for a
585 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
591 unsigned char builtin
;
592 struct neon_typed_alias
* neon
;
595 /* Diagnostics used when we don't get a register of the expected type. */
596 const char * const reg_expected_msgs
[] =
598 N_("ARM register expected"),
599 N_("bad or missing co-processor number"),
600 N_("co-processor register expected"),
601 N_("FPA register expected"),
602 N_("VFP single precision register expected"),
603 N_("VFP/Neon double precision register expected"),
604 N_("Neon quad precision register expected"),
605 N_("VFP single or double precision register expected"),
606 N_("Neon double or quad precision register expected"),
607 N_("VFP single, double or Neon quad precision register expected"),
608 N_("VFP system register expected"),
609 N_("Maverick MVF register expected"),
610 N_("Maverick MVD register expected"),
611 N_("Maverick MVFX register expected"),
612 N_("Maverick MVDX register expected"),
613 N_("Maverick MVAX register expected"),
614 N_("Maverick DSPSC register expected"),
615 N_("iWMMXt data register expected"),
616 N_("iWMMXt control register expected"),
617 N_("iWMMXt scalar register expected"),
618 N_("XScale accumulator register expected"),
621 /* Some well known registers that we refer to directly elsewhere. */
627 /* ARM instructions take 4bytes in the object file, Thumb instructions
633 /* Basic string to match. */
634 const char * template_name
;
636 /* Parameters to instruction. */
637 unsigned int operands
[8];
639 /* Conditional tag - see opcode_lookup. */
640 unsigned int tag
: 4;
642 /* Basic instruction code. */
643 unsigned int avalue
: 28;
645 /* Thumb-format instruction code. */
648 /* Which architecture variant provides this instruction. */
649 const arm_feature_set
* avariant
;
650 const arm_feature_set
* tvariant
;
652 /* Function to call to encode instruction in ARM format. */
653 void (* aencode
) (void);
655 /* Function to call to encode instruction in Thumb format. */
656 void (* tencode
) (void);
659 /* Defines for various bits that we will want to toggle. */
660 #define INST_IMMEDIATE 0x02000000
661 #define OFFSET_REG 0x02000000
662 #define HWOFFSET_IMM 0x00400000
663 #define SHIFT_BY_REG 0x00000010
664 #define PRE_INDEX 0x01000000
665 #define INDEX_UP 0x00800000
666 #define WRITE_BACK 0x00200000
667 #define LDM_TYPE_2_OR_3 0x00400000
668 #define CPSI_MMOD 0x00020000
670 #define LITERAL_MASK 0xf000f000
671 #define OPCODE_MASK 0xfe1fffff
672 #define V4_STR_BIT 0x00000020
673 #define VLDR_VMOV_SAME 0x0040f000
675 #define T2_SUBS_PC_LR 0xf3de8f00
677 #define DATA_OP_SHIFT 21
679 #define T2_OPCODE_MASK 0xfe1fffff
680 #define T2_DATA_OP_SHIFT 21
682 #define A_COND_MASK 0xf0000000
683 #define A_PUSH_POP_OP_MASK 0x0fff0000
685 /* Opcodes for pushing/poping registers to/from the stack. */
686 #define A1_OPCODE_PUSH 0x092d0000
687 #define A2_OPCODE_PUSH 0x052d0004
688 #define A2_OPCODE_POP 0x049d0004
690 /* Codes to distinguish the arithmetic instructions. */
701 #define OPCODE_CMP 10
702 #define OPCODE_CMN 11
703 #define OPCODE_ORR 12
704 #define OPCODE_MOV 13
705 #define OPCODE_BIC 14
706 #define OPCODE_MVN 15
708 #define T2_OPCODE_AND 0
709 #define T2_OPCODE_BIC 1
710 #define T2_OPCODE_ORR 2
711 #define T2_OPCODE_ORN 3
712 #define T2_OPCODE_EOR 4
713 #define T2_OPCODE_ADD 8
714 #define T2_OPCODE_ADC 10
715 #define T2_OPCODE_SBC 11
716 #define T2_OPCODE_SUB 13
717 #define T2_OPCODE_RSB 14
719 #define T_OPCODE_MUL 0x4340
720 #define T_OPCODE_TST 0x4200
721 #define T_OPCODE_CMN 0x42c0
722 #define T_OPCODE_NEG 0x4240
723 #define T_OPCODE_MVN 0x43c0
725 #define T_OPCODE_ADD_R3 0x1800
726 #define T_OPCODE_SUB_R3 0x1a00
727 #define T_OPCODE_ADD_HI 0x4400
728 #define T_OPCODE_ADD_ST 0xb000
729 #define T_OPCODE_SUB_ST 0xb080
730 #define T_OPCODE_ADD_SP 0xa800
731 #define T_OPCODE_ADD_PC 0xa000
732 #define T_OPCODE_ADD_I8 0x3000
733 #define T_OPCODE_SUB_I8 0x3800
734 #define T_OPCODE_ADD_I3 0x1c00
735 #define T_OPCODE_SUB_I3 0x1e00
737 #define T_OPCODE_ASR_R 0x4100
738 #define T_OPCODE_LSL_R 0x4080
739 #define T_OPCODE_LSR_R 0x40c0
740 #define T_OPCODE_ROR_R 0x41c0
741 #define T_OPCODE_ASR_I 0x1000
742 #define T_OPCODE_LSL_I 0x0000
743 #define T_OPCODE_LSR_I 0x0800
745 #define T_OPCODE_MOV_I8 0x2000
746 #define T_OPCODE_CMP_I8 0x2800
747 #define T_OPCODE_CMP_LR 0x4280
748 #define T_OPCODE_MOV_HR 0x4600
749 #define T_OPCODE_CMP_HR 0x4500
751 #define T_OPCODE_LDR_PC 0x4800
752 #define T_OPCODE_LDR_SP 0x9800
753 #define T_OPCODE_STR_SP 0x9000
754 #define T_OPCODE_LDR_IW 0x6800
755 #define T_OPCODE_STR_IW 0x6000
756 #define T_OPCODE_LDR_IH 0x8800
757 #define T_OPCODE_STR_IH 0x8000
758 #define T_OPCODE_LDR_IB 0x7800
759 #define T_OPCODE_STR_IB 0x7000
760 #define T_OPCODE_LDR_RW 0x5800
761 #define T_OPCODE_STR_RW 0x5000
762 #define T_OPCODE_LDR_RH 0x5a00
763 #define T_OPCODE_STR_RH 0x5200
764 #define T_OPCODE_LDR_RB 0x5c00
765 #define T_OPCODE_STR_RB 0x5400
767 #define T_OPCODE_PUSH 0xb400
768 #define T_OPCODE_POP 0xbc00
770 #define T_OPCODE_BRANCH 0xe000
772 #define THUMB_SIZE 2 /* Size of thumb instruction. */
773 #define THUMB_PP_PC_LR 0x0100
774 #define THUMB_LOAD_BIT 0x0800
775 #define THUMB2_LOAD_BIT 0x00100000
777 #define BAD_ARGS _("bad arguments to instruction")
778 #define BAD_SP _("r13 not allowed here")
779 #define BAD_PC _("r15 not allowed here")
780 #define BAD_COND _("instruction cannot be conditional")
781 #define BAD_OVERLAP _("registers may not be the same")
782 #define BAD_HIREG _("lo register required")
783 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
784 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
785 #define BAD_BRANCH _("branch must be last instruction in IT block")
786 #define BAD_NOT_IT _("instruction not allowed in IT block")
787 #define BAD_FPU _("selected FPU does not support instruction")
788 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
789 #define BAD_IT_COND _("incorrect condition in IT block")
790 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
791 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
792 #define BAD_PC_ADDRESSING \
793 _("cannot use register index with PC-relative addressing")
794 #define BAD_PC_WRITEBACK \
795 _("cannot use writeback with PC-relative addressing")
796 #define BAD_RANGE _("branch out of range")
797 #define BAD_FP16 _("selected processor does not support fp16 instruction")
798 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
799 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
801 static struct hash_control
* arm_ops_hsh
;
802 static struct hash_control
* arm_cond_hsh
;
803 static struct hash_control
* arm_shift_hsh
;
804 static struct hash_control
* arm_psr_hsh
;
805 static struct hash_control
* arm_v7m_psr_hsh
;
806 static struct hash_control
* arm_reg_hsh
;
807 static struct hash_control
* arm_reloc_hsh
;
808 static struct hash_control
* arm_barrier_opt_hsh
;
810 /* Stuff needed to resolve the label ambiguity
819 symbolS
* last_label_seen
;
820 static int label_is_thumb_function_name
= FALSE
;
822 /* Literal pool structure. Held on a per-section
823 and per-sub-section basis. */
825 #define MAX_LITERAL_POOL_SIZE 1024
826 typedef struct literal_pool
828 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
829 unsigned int next_free_entry
;
835 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
837 struct literal_pool
* next
;
838 unsigned int alignment
;
841 /* Pointer to a linked list of literal pools. */
842 literal_pool
* list_of_pools
= NULL
;
844 typedef enum asmfunc_states
847 WAITING_ASMFUNC_NAME
,
851 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
854 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
856 static struct current_it now_it
;
860 now_it_compatible (int cond
)
862 return (cond
& ~1) == (now_it
.cc
& ~1);
866 conditional_insn (void)
868 return inst
.cond
!= COND_ALWAYS
;
871 static int in_it_block (void);
873 static int handle_it_state (void);
875 static void force_automatic_it_block_close (void);
877 static void it_fsm_post_encode (void);
879 #define set_it_insn_type(type) \
882 inst.it_insn_type = type; \
883 if (handle_it_state () == FAIL) \
888 #define set_it_insn_type_nonvoid(type, failret) \
891 inst.it_insn_type = type; \
892 if (handle_it_state () == FAIL) \
897 #define set_it_insn_type_last() \
900 if (inst.cond == COND_ALWAYS) \
901 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
903 set_it_insn_type (INSIDE_IT_LAST_INSN); \
909 /* This array holds the chars that always start a comment. If the
910 pre-processor is disabled, these aren't very useful. */
911 char arm_comment_chars
[] = "@";
913 /* This array holds the chars that only start a comment at the beginning of
914 a line. If the line seems to have the form '# 123 filename'
915 .line and .file directives will appear in the pre-processed output. */
916 /* Note that input_file.c hand checks for '#' at the beginning of the
917 first line of the input file. This is because the compiler outputs
918 #NO_APP at the beginning of its output. */
919 /* Also note that comments like this one will always work. */
920 const char line_comment_chars
[] = "#";
922 char arm_line_separator_chars
[] = ";";
924 /* Chars that can be used to separate mant
925 from exp in floating point numbers. */
926 const char EXP_CHARS
[] = "eE";
928 /* Chars that mean this number is a floating point constant. */
932 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
934 /* Prefix characters that indicate the start of an immediate
936 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
938 /* Separator character handling. */
940 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
943 skip_past_char (char ** str
, char c
)
945 /* PR gas/14987: Allow for whitespace before the expected character. */
946 skip_whitespace (*str
);
957 #define skip_past_comma(str) skip_past_char (str, ',')
959 /* Arithmetic expressions (possibly involving symbols). */
961 /* Return TRUE if anything in the expression is a bignum. */
964 walk_no_bignums (symbolS
* sp
)
966 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
969 if (symbol_get_value_expression (sp
)->X_add_symbol
)
971 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
972 || (symbol_get_value_expression (sp
)->X_op_symbol
973 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
979 static int in_my_get_expression
= 0;
981 /* Third argument to my_get_expression. */
982 #define GE_NO_PREFIX 0
983 #define GE_IMM_PREFIX 1
984 #define GE_OPT_PREFIX 2
985 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
986 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
987 #define GE_OPT_PREFIX_BIG 3
990 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
995 /* In unified syntax, all prefixes are optional. */
997 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1000 switch (prefix_mode
)
1002 case GE_NO_PREFIX
: break;
1004 if (!is_immediate_prefix (**str
))
1006 inst
.error
= _("immediate expression requires a # prefix");
1012 case GE_OPT_PREFIX_BIG
:
1013 if (is_immediate_prefix (**str
))
1019 memset (ep
, 0, sizeof (expressionS
));
1021 save_in
= input_line_pointer
;
1022 input_line_pointer
= *str
;
1023 in_my_get_expression
= 1;
1024 seg
= expression (ep
);
1025 in_my_get_expression
= 0;
1027 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1029 /* We found a bad or missing expression in md_operand(). */
1030 *str
= input_line_pointer
;
1031 input_line_pointer
= save_in
;
1032 if (inst
.error
== NULL
)
1033 inst
.error
= (ep
->X_op
== O_absent
1034 ? _("missing expression") :_("bad expression"));
1039 if (seg
!= absolute_section
1040 && seg
!= text_section
1041 && seg
!= data_section
1042 && seg
!= bss_section
1043 && seg
!= undefined_section
)
1045 inst
.error
= _("bad segment");
1046 *str
= input_line_pointer
;
1047 input_line_pointer
= save_in
;
1054 /* Get rid of any bignums now, so that we don't generate an error for which
1055 we can't establish a line number later on. Big numbers are never valid
1056 in instructions, which is where this routine is always called. */
1057 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1058 && (ep
->X_op
== O_big
1059 || (ep
->X_add_symbol
1060 && (walk_no_bignums (ep
->X_add_symbol
)
1062 && walk_no_bignums (ep
->X_op_symbol
))))))
1064 inst
.error
= _("invalid constant");
1065 *str
= input_line_pointer
;
1066 input_line_pointer
= save_in
;
1070 *str
= input_line_pointer
;
1071 input_line_pointer
= save_in
;
1075 /* Turn a string in input_line_pointer into a floating point constant
1076 of type TYPE, and store the appropriate bytes in *LITP. The number
1077 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1078 returned, or NULL on OK.
1080 Note that fp constants aren't represent in the normal way on the ARM.
1081 In big endian mode, things are as expected. However, in little endian
1082 mode fp constants are big-endian word-wise, and little-endian byte-wise
1083 within the words. For example, (double) 1.1 in big endian mode is
1084 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1085 the byte sequence 99 99 f1 3f 9a 99 99 99.
1087 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1090 md_atof (int type
, char * litP
, int * sizeP
)
1093 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1125 return _("Unrecognized or unsupported floating point constant");
1128 t
= atof_ieee (input_line_pointer
, type
, words
);
1130 input_line_pointer
= t
;
1131 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1133 if (target_big_endian
)
1135 for (i
= 0; i
< prec
; i
++)
1137 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1138 litP
+= sizeof (LITTLENUM_TYPE
);
1143 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1144 for (i
= prec
- 1; i
>= 0; i
--)
1146 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1147 litP
+= sizeof (LITTLENUM_TYPE
);
1150 /* For a 4 byte float the order of elements in `words' is 1 0.
1151 For an 8 byte float the order is 1 0 3 2. */
1152 for (i
= 0; i
< prec
; i
+= 2)
1154 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1155 sizeof (LITTLENUM_TYPE
));
1156 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1157 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1158 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1165 /* We handle all bad expressions here, so that we can report the faulty
1166 instruction in the error message. */
1168 md_operand (expressionS
* exp
)
1170 if (in_my_get_expression
)
1171 exp
->X_op
= O_illegal
;
1174 /* Immediate values. */
1176 /* Generic immediate-value read function for use in directives.
1177 Accepts anything that 'expression' can fold to a constant.
1178 *val receives the number. */
1181 immediate_for_directive (int *val
)
1184 exp
.X_op
= O_illegal
;
1186 if (is_immediate_prefix (*input_line_pointer
))
1188 input_line_pointer
++;
1192 if (exp
.X_op
!= O_constant
)
1194 as_bad (_("expected #constant"));
1195 ignore_rest_of_line ();
1198 *val
= exp
.X_add_number
;
1203 /* Register parsing. */
1205 /* Generic register parser. CCP points to what should be the
1206 beginning of a register name. If it is indeed a valid register
1207 name, advance CCP over it and return the reg_entry structure;
1208 otherwise return NULL. Does not issue diagnostics. */
1210 static struct reg_entry
*
1211 arm_reg_parse_multi (char **ccp
)
1215 struct reg_entry
*reg
;
1217 skip_whitespace (start
);
1219 #ifdef REGISTER_PREFIX
1220 if (*start
!= REGISTER_PREFIX
)
1224 #ifdef OPTIONAL_REGISTER_PREFIX
1225 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1230 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1235 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1237 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1247 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1248 enum arm_reg_type type
)
1250 /* Alternative syntaxes are accepted for a few register classes. */
1257 /* Generic coprocessor register names are allowed for these. */
1258 if (reg
&& reg
->type
== REG_TYPE_CN
)
1263 /* For backward compatibility, a bare number is valid here. */
1265 unsigned long processor
= strtoul (start
, ccp
, 10);
1266 if (*ccp
!= start
&& processor
<= 15)
1270 case REG_TYPE_MMXWC
:
1271 /* WC includes WCG. ??? I'm not sure this is true for all
1272 instructions that take WC registers. */
1273 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1284 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1285 return value is the register number or FAIL. */
1288 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1291 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1294 /* Do not allow a scalar (reg+index) to parse as a register. */
1295 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1298 if (reg
&& reg
->type
== type
)
1301 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1308 /* Parse a Neon type specifier. *STR should point at the leading '.'
1309 character. Does no verification at this stage that the type fits the opcode
1316 Can all be legally parsed by this function.
1318 Fills in neon_type struct pointer with parsed information, and updates STR
1319 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1320 type, FAIL if not. */
1323 parse_neon_type (struct neon_type
*type
, char **str
)
1330 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1332 enum neon_el_type thistype
= NT_untyped
;
1333 unsigned thissize
= -1u;
1340 /* Just a size without an explicit type. */
1344 switch (TOLOWER (*ptr
))
1346 case 'i': thistype
= NT_integer
; break;
1347 case 'f': thistype
= NT_float
; break;
1348 case 'p': thistype
= NT_poly
; break;
1349 case 's': thistype
= NT_signed
; break;
1350 case 'u': thistype
= NT_unsigned
; break;
1352 thistype
= NT_float
;
1357 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1363 /* .f is an abbreviation for .f32. */
1364 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1369 thissize
= strtoul (ptr
, &ptr
, 10);
1371 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1374 as_bad (_("bad size %d in type specifier"), thissize
);
1382 type
->el
[type
->elems
].type
= thistype
;
1383 type
->el
[type
->elems
].size
= thissize
;
1388 /* Empty/missing type is not a successful parse. */
1389 if (type
->elems
== 0)
1397 /* Errors may be set multiple times during parsing or bit encoding
1398 (particularly in the Neon bits), but usually the earliest error which is set
1399 will be the most meaningful. Avoid overwriting it with later (cascading)
1400 errors by calling this function. */
1403 first_error (const char *err
)
1409 /* Parse a single type, e.g. ".s32", leading period included. */
1411 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1414 struct neon_type optype
;
1418 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1420 if (optype
.elems
== 1)
1421 *vectype
= optype
.el
[0];
1424 first_error (_("only one type should be specified for operand"));
1430 first_error (_("vector type expected"));
1442 /* Special meanings for indices (which have a range of 0-7), which will fit into
1445 #define NEON_ALL_LANES 15
1446 #define NEON_INTERLEAVE_LANES 14
1448 /* Parse either a register or a scalar, with an optional type. Return the
1449 register number, and optionally fill in the actual type of the register
1450 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1451 type/index information in *TYPEINFO. */
1454 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1455 enum arm_reg_type
*rtype
,
1456 struct neon_typed_alias
*typeinfo
)
1459 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1460 struct neon_typed_alias atype
;
1461 struct neon_type_el parsetype
;
1465 atype
.eltype
.type
= NT_invtype
;
1466 atype
.eltype
.size
= -1;
1468 /* Try alternate syntax for some types of register. Note these are mutually
1469 exclusive with the Neon syntax extensions. */
1472 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1480 /* Undo polymorphism when a set of register types may be accepted. */
1481 if ((type
== REG_TYPE_NDQ
1482 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1483 || (type
== REG_TYPE_VFSD
1484 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1485 || (type
== REG_TYPE_NSDQ
1486 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1487 || reg
->type
== REG_TYPE_NQ
))
1488 || (type
== REG_TYPE_MMXWC
1489 && (reg
->type
== REG_TYPE_MMXWCG
)))
1490 type
= (enum arm_reg_type
) reg
->type
;
1492 if (type
!= reg
->type
)
1498 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1500 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1502 first_error (_("can't redefine type for operand"));
1505 atype
.defined
|= NTA_HASTYPE
;
1506 atype
.eltype
= parsetype
;
1509 if (skip_past_char (&str
, '[') == SUCCESS
)
1511 if (type
!= REG_TYPE_VFD
)
1513 first_error (_("only D registers may be indexed"));
1517 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1519 first_error (_("can't change index for operand"));
1523 atype
.defined
|= NTA_HASINDEX
;
1525 if (skip_past_char (&str
, ']') == SUCCESS
)
1526 atype
.index
= NEON_ALL_LANES
;
1531 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1533 if (exp
.X_op
!= O_constant
)
1535 first_error (_("constant expression required"));
1539 if (skip_past_char (&str
, ']') == FAIL
)
1542 atype
.index
= exp
.X_add_number
;
1557 /* Like arm_reg_parse, but allow allow the following extra features:
1558 - If RTYPE is non-zero, return the (possibly restricted) type of the
1559 register (e.g. Neon double or quad reg when either has been requested).
1560 - If this is a Neon vector type with additional type information, fill
1561 in the struct pointed to by VECTYPE (if non-NULL).
1562 This function will fault on encountering a scalar. */
1565 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1566 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1568 struct neon_typed_alias atype
;
1570 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1575 /* Do not allow regname(... to parse as a register. */
1579 /* Do not allow a scalar (reg+index) to parse as a register. */
1580 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1582 first_error (_("register operand expected, but got scalar"));
1587 *vectype
= atype
.eltype
;
1594 #define NEON_SCALAR_REG(X) ((X) >> 4)
1595 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1597 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1598 have enough information to be able to do a good job bounds-checking. So, we
1599 just do easy checks here, and do further checks later. */
1602 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1606 struct neon_typed_alias atype
;
1608 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1610 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1613 if (atype
.index
== NEON_ALL_LANES
)
1615 first_error (_("scalar must have an index"));
1618 else if (atype
.index
>= 64 / elsize
)
1620 first_error (_("scalar index out of range"));
1625 *type
= atype
.eltype
;
1629 return reg
* 16 + atype
.index
;
1632 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1635 parse_reg_list (char ** strp
)
1637 char * str
= * strp
;
1641 /* We come back here if we get ranges concatenated by '+' or '|'. */
1644 skip_whitespace (str
);
1658 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1660 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1670 first_error (_("bad range in register list"));
1674 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1676 if (range
& (1 << i
))
1678 (_("Warning: duplicated register (r%d) in register list"),
1686 if (range
& (1 << reg
))
1687 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1689 else if (reg
<= cur_reg
)
1690 as_tsktsk (_("Warning: register range not in ascending order"));
1695 while (skip_past_comma (&str
) != FAIL
1696 || (in_range
= 1, *str
++ == '-'));
1699 if (skip_past_char (&str
, '}') == FAIL
)
1701 first_error (_("missing `}'"));
1709 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1712 if (exp
.X_op
== O_constant
)
1714 if (exp
.X_add_number
1715 != (exp
.X_add_number
& 0x0000ffff))
1717 inst
.error
= _("invalid register mask");
1721 if ((range
& exp
.X_add_number
) != 0)
1723 int regno
= range
& exp
.X_add_number
;
1726 regno
= (1 << regno
) - 1;
1728 (_("Warning: duplicated register (r%d) in register list"),
1732 range
|= exp
.X_add_number
;
1736 if (inst
.reloc
.type
!= 0)
1738 inst
.error
= _("expression too complex");
1742 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1743 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1744 inst
.reloc
.pc_rel
= 0;
1748 if (*str
== '|' || *str
== '+')
1754 while (another_range
);
1760 /* Types of registers in a list. */
1769 /* Parse a VFP register list. If the string is invalid return FAIL.
1770 Otherwise return the number of registers, and set PBASE to the first
1771 register. Parses registers of type ETYPE.
1772 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1773 - Q registers can be used to specify pairs of D registers
1774 - { } can be omitted from around a singleton register list
1775 FIXME: This is not implemented, as it would require backtracking in
1778 This could be done (the meaning isn't really ambiguous), but doesn't
1779 fit in well with the current parsing framework.
1780 - 32 D registers may be used (also true for VFPv3).
1781 FIXME: Types are ignored in these register lists, which is probably a
1785 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1790 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1794 unsigned long mask
= 0;
1797 if (skip_past_char (&str
, '{') == FAIL
)
1799 inst
.error
= _("expecting {");
1806 regtype
= REG_TYPE_VFS
;
1811 regtype
= REG_TYPE_VFD
;
1814 case REGLIST_NEON_D
:
1815 regtype
= REG_TYPE_NDQ
;
1819 if (etype
!= REGLIST_VFP_S
)
1821 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1822 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1826 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1829 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1836 base_reg
= max_regs
;
1840 int setmask
= 1, addregs
= 1;
1842 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1844 if (new_base
== FAIL
)
1846 first_error (_(reg_expected_msgs
[regtype
]));
1850 if (new_base
>= max_regs
)
1852 first_error (_("register out of range in list"));
1856 /* Note: a value of 2 * n is returned for the register Q<n>. */
1857 if (regtype
== REG_TYPE_NQ
)
1863 if (new_base
< base_reg
)
1864 base_reg
= new_base
;
1866 if (mask
& (setmask
<< new_base
))
1868 first_error (_("invalid register list"));
1872 if ((mask
>> new_base
) != 0 && ! warned
)
1874 as_tsktsk (_("register list not in ascending order"));
1878 mask
|= setmask
<< new_base
;
1881 if (*str
== '-') /* We have the start of a range expression */
1887 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1890 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1894 if (high_range
>= max_regs
)
1896 first_error (_("register out of range in list"));
1900 if (regtype
== REG_TYPE_NQ
)
1901 high_range
= high_range
+ 1;
1903 if (high_range
<= new_base
)
1905 inst
.error
= _("register range not in ascending order");
1909 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1911 if (mask
& (setmask
<< new_base
))
1913 inst
.error
= _("invalid register list");
1917 mask
|= setmask
<< new_base
;
1922 while (skip_past_comma (&str
) != FAIL
);
1926 /* Sanity check -- should have raised a parse error above. */
1927 if (count
== 0 || count
> max_regs
)
1932 /* Final test -- the registers must be consecutive. */
1934 for (i
= 0; i
< count
; i
++)
1936 if ((mask
& (1u << i
)) == 0)
1938 inst
.error
= _("non-contiguous register range");
1948 /* True if two alias types are the same. */
1951 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1959 if (a
->defined
!= b
->defined
)
1962 if ((a
->defined
& NTA_HASTYPE
) != 0
1963 && (a
->eltype
.type
!= b
->eltype
.type
1964 || a
->eltype
.size
!= b
->eltype
.size
))
1967 if ((a
->defined
& NTA_HASINDEX
) != 0
1968 && (a
->index
!= b
->index
))
1974 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1975 The base register is put in *PBASE.
1976 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1978 The register stride (minus one) is put in bit 4 of the return value.
1979 Bits [6:5] encode the list length (minus one).
1980 The type of the list elements is put in *ELTYPE, if non-NULL. */
1982 #define NEON_LANE(X) ((X) & 0xf)
1983 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1984 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1987 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1988 struct neon_type_el
*eltype
)
1995 int leading_brace
= 0;
1996 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1997 const char *const incr_error
= _("register stride must be 1 or 2");
1998 const char *const type_error
= _("mismatched element/structure types in list");
1999 struct neon_typed_alias firsttype
;
2000 firsttype
.defined
= 0;
2001 firsttype
.eltype
.type
= NT_invtype
;
2002 firsttype
.eltype
.size
= -1;
2003 firsttype
.index
= -1;
2005 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2010 struct neon_typed_alias atype
;
2011 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2015 first_error (_(reg_expected_msgs
[rtype
]));
2022 if (rtype
== REG_TYPE_NQ
)
2028 else if (reg_incr
== -1)
2030 reg_incr
= getreg
- base_reg
;
2031 if (reg_incr
< 1 || reg_incr
> 2)
2033 first_error (_(incr_error
));
2037 else if (getreg
!= base_reg
+ reg_incr
* count
)
2039 first_error (_(incr_error
));
2043 if (! neon_alias_types_same (&atype
, &firsttype
))
2045 first_error (_(type_error
));
2049 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2053 struct neon_typed_alias htype
;
2054 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2056 lane
= NEON_INTERLEAVE_LANES
;
2057 else if (lane
!= NEON_INTERLEAVE_LANES
)
2059 first_error (_(type_error
));
2064 else if (reg_incr
!= 1)
2066 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2070 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2073 first_error (_(reg_expected_msgs
[rtype
]));
2076 if (! neon_alias_types_same (&htype
, &firsttype
))
2078 first_error (_(type_error
));
2081 count
+= hireg
+ dregs
- getreg
;
2085 /* If we're using Q registers, we can't use [] or [n] syntax. */
2086 if (rtype
== REG_TYPE_NQ
)
2092 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2096 else if (lane
!= atype
.index
)
2098 first_error (_(type_error
));
2102 else if (lane
== -1)
2103 lane
= NEON_INTERLEAVE_LANES
;
2104 else if (lane
!= NEON_INTERLEAVE_LANES
)
2106 first_error (_(type_error
));
2111 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2113 /* No lane set by [x]. We must be interleaving structures. */
2115 lane
= NEON_INTERLEAVE_LANES
;
2118 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2119 || (count
> 1 && reg_incr
== -1))
2121 first_error (_("error parsing element/structure list"));
2125 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2127 first_error (_("expected }"));
2135 *eltype
= firsttype
.eltype
;
2140 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2143 /* Parse an explicit relocation suffix on an expression. This is
2144 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2145 arm_reloc_hsh contains no entries, so this function can only
2146 succeed if there is no () after the word. Returns -1 on error,
2147 BFD_RELOC_UNUSED if there wasn't any suffix. */
2150 parse_reloc (char **str
)
2152 struct reloc_entry
*r
;
2156 return BFD_RELOC_UNUSED
;
2161 while (*q
&& *q
!= ')' && *q
!= ',')
2166 if ((r
= (struct reloc_entry
*)
2167 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2174 /* Directives: register aliases. */
2176 static struct reg_entry
*
2177 insert_reg_alias (char *str
, unsigned number
, int type
)
2179 struct reg_entry
*new_reg
;
2182 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2184 if (new_reg
->builtin
)
2185 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2187 /* Only warn about a redefinition if it's not defined as the
2189 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2190 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2195 name
= xstrdup (str
);
2196 new_reg
= XNEW (struct reg_entry
);
2198 new_reg
->name
= name
;
2199 new_reg
->number
= number
;
2200 new_reg
->type
= type
;
2201 new_reg
->builtin
= FALSE
;
2202 new_reg
->neon
= NULL
;
2204 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2211 insert_neon_reg_alias (char *str
, int number
, int type
,
2212 struct neon_typed_alias
*atype
)
2214 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2218 first_error (_("attempt to redefine typed alias"));
2224 reg
->neon
= XNEW (struct neon_typed_alias
);
2225 *reg
->neon
= *atype
;
2229 /* Look for the .req directive. This is of the form:
2231 new_register_name .req existing_register_name
2233 If we find one, or if it looks sufficiently like one that we want to
2234 handle any error here, return TRUE. Otherwise return FALSE. */
2237 create_register_alias (char * newname
, char *p
)
2239 struct reg_entry
*old
;
2240 char *oldname
, *nbuf
;
2243 /* The input scrubber ensures that whitespace after the mnemonic is
2244 collapsed to single spaces. */
2246 if (strncmp (oldname
, " .req ", 6) != 0)
2250 if (*oldname
== '\0')
2253 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2256 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2260 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2261 the desired alias name, and p points to its end. If not, then
2262 the desired alias name is in the global original_case_string. */
2263 #ifdef TC_CASE_SENSITIVE
2266 newname
= original_case_string
;
2267 nlen
= strlen (newname
);
2270 nbuf
= xmemdup0 (newname
, nlen
);
2272 /* Create aliases under the new name as stated; an all-lowercase
2273 version of the new name; and an all-uppercase version of the new
2275 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2277 for (p
= nbuf
; *p
; p
++)
2280 if (strncmp (nbuf
, newname
, nlen
))
2282 /* If this attempt to create an additional alias fails, do not bother
2283 trying to create the all-lower case alias. We will fail and issue
2284 a second, duplicate error message. This situation arises when the
2285 programmer does something like:
2288 The second .req creates the "Foo" alias but then fails to create
2289 the artificial FOO alias because it has already been created by the
2291 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2298 for (p
= nbuf
; *p
; p
++)
2301 if (strncmp (nbuf
, newname
, nlen
))
2302 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2309 /* Create a Neon typed/indexed register alias using directives, e.g.:
2314 These typed registers can be used instead of the types specified after the
2315 Neon mnemonic, so long as all operands given have types. Types can also be
2316 specified directly, e.g.:
2317 vadd d0.s32, d1.s32, d2.s32 */
2320 create_neon_reg_alias (char *newname
, char *p
)
2322 enum arm_reg_type basetype
;
2323 struct reg_entry
*basereg
;
2324 struct reg_entry mybasereg
;
2325 struct neon_type ntype
;
2326 struct neon_typed_alias typeinfo
;
2327 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2330 typeinfo
.defined
= 0;
2331 typeinfo
.eltype
.type
= NT_invtype
;
2332 typeinfo
.eltype
.size
= -1;
2333 typeinfo
.index
= -1;
2337 if (strncmp (p
, " .dn ", 5) == 0)
2338 basetype
= REG_TYPE_VFD
;
2339 else if (strncmp (p
, " .qn ", 5) == 0)
2340 basetype
= REG_TYPE_NQ
;
2349 basereg
= arm_reg_parse_multi (&p
);
2351 if (basereg
&& basereg
->type
!= basetype
)
2353 as_bad (_("bad type for register"));
2357 if (basereg
== NULL
)
2360 /* Try parsing as an integer. */
2361 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2362 if (exp
.X_op
!= O_constant
)
2364 as_bad (_("expression must be constant"));
2367 basereg
= &mybasereg
;
2368 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2374 typeinfo
= *basereg
->neon
;
2376 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2378 /* We got a type. */
2379 if (typeinfo
.defined
& NTA_HASTYPE
)
2381 as_bad (_("can't redefine the type of a register alias"));
2385 typeinfo
.defined
|= NTA_HASTYPE
;
2386 if (ntype
.elems
!= 1)
2388 as_bad (_("you must specify a single type only"));
2391 typeinfo
.eltype
= ntype
.el
[0];
2394 if (skip_past_char (&p
, '[') == SUCCESS
)
2397 /* We got a scalar index. */
2399 if (typeinfo
.defined
& NTA_HASINDEX
)
2401 as_bad (_("can't redefine the index of a scalar alias"));
2405 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2407 if (exp
.X_op
!= O_constant
)
2409 as_bad (_("scalar index must be constant"));
2413 typeinfo
.defined
|= NTA_HASINDEX
;
2414 typeinfo
.index
= exp
.X_add_number
;
2416 if (skip_past_char (&p
, ']') == FAIL
)
2418 as_bad (_("expecting ]"));
2423 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2424 the desired alias name, and p points to its end. If not, then
2425 the desired alias name is in the global original_case_string. */
2426 #ifdef TC_CASE_SENSITIVE
2427 namelen
= nameend
- newname
;
2429 newname
= original_case_string
;
2430 namelen
= strlen (newname
);
2433 namebuf
= xmemdup0 (newname
, namelen
);
2435 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2436 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2438 /* Insert name in all uppercase. */
2439 for (p
= namebuf
; *p
; p
++)
2442 if (strncmp (namebuf
, newname
, namelen
))
2443 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2444 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2446 /* Insert name in all lowercase. */
2447 for (p
= namebuf
; *p
; p
++)
2450 if (strncmp (namebuf
, newname
, namelen
))
2451 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2452 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2458 /* Should never be called, as .req goes between the alias and the
2459 register name, not at the beginning of the line. */
2462 s_req (int a ATTRIBUTE_UNUSED
)
2464 as_bad (_("invalid syntax for .req directive"));
2468 s_dn (int a ATTRIBUTE_UNUSED
)
2470 as_bad (_("invalid syntax for .dn directive"));
2474 s_qn (int a ATTRIBUTE_UNUSED
)
2476 as_bad (_("invalid syntax for .qn directive"));
2479 /* The .unreq directive deletes an alias which was previously defined
2480 by .req. For example:
2486 s_unreq (int a ATTRIBUTE_UNUSED
)
2491 name
= input_line_pointer
;
2493 while (*input_line_pointer
!= 0
2494 && *input_line_pointer
!= ' '
2495 && *input_line_pointer
!= '\n')
2496 ++input_line_pointer
;
2498 saved_char
= *input_line_pointer
;
2499 *input_line_pointer
= 0;
2502 as_bad (_("invalid syntax for .unreq directive"));
2505 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2509 as_bad (_("unknown register alias '%s'"), name
);
2510 else if (reg
->builtin
)
2511 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2518 hash_delete (arm_reg_hsh
, name
, FALSE
);
2519 free ((char *) reg
->name
);
2524 /* Also locate the all upper case and all lower case versions.
2525 Do not complain if we cannot find one or the other as it
2526 was probably deleted above. */
2528 nbuf
= strdup (name
);
2529 for (p
= nbuf
; *p
; p
++)
2531 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2534 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2535 free ((char *) reg
->name
);
2541 for (p
= nbuf
; *p
; p
++)
2543 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2546 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2547 free ((char *) reg
->name
);
2557 *input_line_pointer
= saved_char
;
2558 demand_empty_rest_of_line ();
2561 /* Directives: Instruction set selection. */
2564 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2565 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2566 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2567 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2569 /* Create a new mapping symbol for the transition to STATE. */
2572 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2575 const char * symname
;
2582 type
= BSF_NO_FLAGS
;
2586 type
= BSF_NO_FLAGS
;
2590 type
= BSF_NO_FLAGS
;
2596 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2597 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2602 THUMB_SET_FUNC (symbolP
, 0);
2603 ARM_SET_THUMB (symbolP
, 0);
2604 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2608 THUMB_SET_FUNC (symbolP
, 1);
2609 ARM_SET_THUMB (symbolP
, 1);
2610 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2618 /* Save the mapping symbols for future reference. Also check that
2619 we do not place two mapping symbols at the same offset within a
2620 frag. We'll handle overlap between frags in
2621 check_mapping_symbols.
2623 If .fill or other data filling directive generates zero sized data,
2624 the mapping symbol for the following code will have the same value
2625 as the one generated for the data filling directive. In this case,
2626 we replace the old symbol with the new one at the same address. */
2629 if (frag
->tc_frag_data
.first_map
!= NULL
)
2631 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2632 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2634 frag
->tc_frag_data
.first_map
= symbolP
;
2636 if (frag
->tc_frag_data
.last_map
!= NULL
)
2638 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2639 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2640 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2642 frag
->tc_frag_data
.last_map
= symbolP
;
2645 /* We must sometimes convert a region marked as code to data during
2646 code alignment, if an odd number of bytes have to be padded. The
2647 code mapping symbol is pushed to an aligned address. */
2650 insert_data_mapping_symbol (enum mstate state
,
2651 valueT value
, fragS
*frag
, offsetT bytes
)
2653 /* If there was already a mapping symbol, remove it. */
2654 if (frag
->tc_frag_data
.last_map
!= NULL
2655 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2657 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2661 know (frag
->tc_frag_data
.first_map
== symp
);
2662 frag
->tc_frag_data
.first_map
= NULL
;
2664 frag
->tc_frag_data
.last_map
= NULL
;
2665 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2668 make_mapping_symbol (MAP_DATA
, value
, frag
);
2669 make_mapping_symbol (state
, value
+ bytes
, frag
);
2672 static void mapping_state_2 (enum mstate state
, int max_chars
);
2674 /* Set the mapping state to STATE. Only call this when about to
2675 emit some STATE bytes to the file. */
2677 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2679 mapping_state (enum mstate state
)
2681 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2683 if (mapstate
== state
)
2684 /* The mapping symbol has already been emitted.
2685 There is nothing else to do. */
2688 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2690 All ARM instructions require 4-byte alignment.
2691 (Almost) all Thumb instructions require 2-byte alignment.
2693 When emitting instructions into any section, mark the section
2696 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2697 but themselves require 2-byte alignment; this applies to some
2698 PC- relative forms. However, these cases will invovle implicit
2699 literal pool generation or an explicit .align >=2, both of
2700 which will cause the section to me marked with sufficient
2701 alignment. Thus, we don't handle those cases here. */
2702 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2704 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2705 /* This case will be evaluated later. */
2708 mapping_state_2 (state
, 0);
2711 /* Same as mapping_state, but MAX_CHARS bytes have already been
2712 allocated. Put the mapping symbol that far back. */
2715 mapping_state_2 (enum mstate state
, int max_chars
)
2717 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2719 if (!SEG_NORMAL (now_seg
))
2722 if (mapstate
== state
)
2723 /* The mapping symbol has already been emitted.
2724 There is nothing else to do. */
2727 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2728 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2730 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2731 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2734 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2737 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2738 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2742 #define mapping_state(x) ((void)0)
2743 #define mapping_state_2(x, y) ((void)0)
2746 /* Find the real, Thumb encoded start of a Thumb function. */
2750 find_real_start (symbolS
* symbolP
)
2753 const char * name
= S_GET_NAME (symbolP
);
2754 symbolS
* new_target
;
2756 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2757 #define STUB_NAME ".real_start_of"
2762 /* The compiler may generate BL instructions to local labels because
2763 it needs to perform a branch to a far away location. These labels
2764 do not have a corresponding ".real_start_of" label. We check
2765 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2766 the ".real_start_of" convention for nonlocal branches. */
2767 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2770 real_start
= concat (STUB_NAME
, name
, NULL
);
2771 new_target
= symbol_find (real_start
);
2774 if (new_target
== NULL
)
2776 as_warn (_("Failed to find real start of function: %s\n"), name
);
2777 new_target
= symbolP
;
2785 opcode_select (int width
)
2792 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2793 as_bad (_("selected processor does not support THUMB opcodes"));
2796 /* No need to force the alignment, since we will have been
2797 coming from ARM mode, which is word-aligned. */
2798 record_alignment (now_seg
, 1);
2805 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2806 as_bad (_("selected processor does not support ARM opcodes"));
2811 frag_align (2, 0, 0);
2813 record_alignment (now_seg
, 1);
2818 as_bad (_("invalid instruction size selected (%d)"), width
);
2823 s_arm (int ignore ATTRIBUTE_UNUSED
)
2826 demand_empty_rest_of_line ();
2830 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2833 demand_empty_rest_of_line ();
2837 s_code (int unused ATTRIBUTE_UNUSED
)
2841 temp
= get_absolute_expression ();
2846 opcode_select (temp
);
2850 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2855 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2857 /* If we are not already in thumb mode go into it, EVEN if
2858 the target processor does not support thumb instructions.
2859 This is used by gcc/config/arm/lib1funcs.asm for example
2860 to compile interworking support functions even if the
2861 target processor should not support interworking. */
2865 record_alignment (now_seg
, 1);
2868 demand_empty_rest_of_line ();
2872 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2876 /* The following label is the name/address of the start of a Thumb function.
2877 We need to know this for the interworking support. */
2878 label_is_thumb_function_name
= TRUE
;
2881 /* Perform a .set directive, but also mark the alias as
2882 being a thumb function. */
2885 s_thumb_set (int equiv
)
2887 /* XXX the following is a duplicate of the code for s_set() in read.c
2888 We cannot just call that code as we need to get at the symbol that
2895 /* Especial apologies for the random logic:
2896 This just grew, and could be parsed much more simply!
2898 delim
= get_symbol_name (& name
);
2899 end_name
= input_line_pointer
;
2900 (void) restore_line_pointer (delim
);
2902 if (*input_line_pointer
!= ',')
2905 as_bad (_("expected comma after name \"%s\""), name
);
2907 ignore_rest_of_line ();
2911 input_line_pointer
++;
2914 if (name
[0] == '.' && name
[1] == '\0')
2916 /* XXX - this should not happen to .thumb_set. */
2920 if ((symbolP
= symbol_find (name
)) == NULL
2921 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2924 /* When doing symbol listings, play games with dummy fragments living
2925 outside the normal fragment chain to record the file and line info
2927 if (listing
& LISTING_SYMBOLS
)
2929 extern struct list_info_struct
* listing_tail
;
2930 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2932 memset (dummy_frag
, 0, sizeof (fragS
));
2933 dummy_frag
->fr_type
= rs_fill
;
2934 dummy_frag
->line
= listing_tail
;
2935 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2936 dummy_frag
->fr_symbol
= symbolP
;
2940 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2943 /* "set" symbols are local unless otherwise specified. */
2944 SF_SET_LOCAL (symbolP
);
2945 #endif /* OBJ_COFF */
2946 } /* Make a new symbol. */
2948 symbol_table_insert (symbolP
);
2953 && S_IS_DEFINED (symbolP
)
2954 && S_GET_SEGMENT (symbolP
) != reg_section
)
2955 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2957 pseudo_set (symbolP
);
2959 demand_empty_rest_of_line ();
2961 /* XXX Now we come to the Thumb specific bit of code. */
2963 THUMB_SET_FUNC (symbolP
, 1);
2964 ARM_SET_THUMB (symbolP
, 1);
2965 #if defined OBJ_ELF || defined OBJ_COFF
2966 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2970 /* Directives: Mode selection. */
2972 /* .syntax [unified|divided] - choose the new unified syntax
2973 (same for Arm and Thumb encoding, modulo slight differences in what
2974 can be represented) or the old divergent syntax for each mode. */
2976 s_syntax (int unused ATTRIBUTE_UNUSED
)
2980 delim
= get_symbol_name (& name
);
2982 if (!strcasecmp (name
, "unified"))
2983 unified_syntax
= TRUE
;
2984 else if (!strcasecmp (name
, "divided"))
2985 unified_syntax
= FALSE
;
2988 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2991 (void) restore_line_pointer (delim
);
2992 demand_empty_rest_of_line ();
2995 /* Directives: sectioning and alignment. */
2998 s_bss (int ignore ATTRIBUTE_UNUSED
)
3000 /* We don't support putting frags in the BSS segment, we fake it by
3001 marking in_bss, then looking at s_skip for clues. */
3002 subseg_set (bss_section
, 0);
3003 demand_empty_rest_of_line ();
3005 #ifdef md_elf_section_change_hook
3006 md_elf_section_change_hook ();
3011 s_even (int ignore ATTRIBUTE_UNUSED
)
3013 /* Never make frag if expect extra pass. */
3015 frag_align (1, 0, 0);
3017 record_alignment (now_seg
, 1);
3019 demand_empty_rest_of_line ();
3022 /* Directives: CodeComposer Studio. */
3024 /* .ref (for CodeComposer Studio syntax only). */
3026 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3028 if (codecomposer_syntax
)
3029 ignore_rest_of_line ();
3031 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3034 /* If name is not NULL, then it is used for marking the beginning of a
3035 function, wherease if it is NULL then it means the function end. */
3037 asmfunc_debug (const char * name
)
3039 static const char * last_name
= NULL
;
3043 gas_assert (last_name
== NULL
);
3046 if (debug_type
== DEBUG_STABS
)
3047 stabs_generate_asm_func (name
, name
);
3051 gas_assert (last_name
!= NULL
);
3053 if (debug_type
== DEBUG_STABS
)
3054 stabs_generate_asm_endfunc (last_name
, last_name
);
3061 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3063 if (codecomposer_syntax
)
3065 switch (asmfunc_state
)
3067 case OUTSIDE_ASMFUNC
:
3068 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3071 case WAITING_ASMFUNC_NAME
:
3072 as_bad (_(".asmfunc repeated."));
3075 case WAITING_ENDASMFUNC
:
3076 as_bad (_(".asmfunc without function."));
3079 demand_empty_rest_of_line ();
3082 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3086 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3088 if (codecomposer_syntax
)
3090 switch (asmfunc_state
)
3092 case OUTSIDE_ASMFUNC
:
3093 as_bad (_(".endasmfunc without a .asmfunc."));
3096 case WAITING_ASMFUNC_NAME
:
3097 as_bad (_(".endasmfunc without function."));
3100 case WAITING_ENDASMFUNC
:
3101 asmfunc_state
= OUTSIDE_ASMFUNC
;
3102 asmfunc_debug (NULL
);
3105 demand_empty_rest_of_line ();
3108 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3112 s_ccs_def (int name
)
3114 if (codecomposer_syntax
)
3117 as_bad (_(".def pseudo-op only available with -mccs flag."));
3120 /* Directives: Literal pools. */
3122 static literal_pool
*
3123 find_literal_pool (void)
3125 literal_pool
* pool
;
3127 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3129 if (pool
->section
== now_seg
3130 && pool
->sub_section
== now_subseg
)
3137 static literal_pool
*
3138 find_or_make_literal_pool (void)
3140 /* Next literal pool ID number. */
3141 static unsigned int latest_pool_num
= 1;
3142 literal_pool
* pool
;
3144 pool
= find_literal_pool ();
3148 /* Create a new pool. */
3149 pool
= XNEW (literal_pool
);
3153 pool
->next_free_entry
= 0;
3154 pool
->section
= now_seg
;
3155 pool
->sub_section
= now_subseg
;
3156 pool
->next
= list_of_pools
;
3157 pool
->symbol
= NULL
;
3158 pool
->alignment
= 2;
3160 /* Add it to the list. */
3161 list_of_pools
= pool
;
3164 /* New pools, and emptied pools, will have a NULL symbol. */
3165 if (pool
->symbol
== NULL
)
3167 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3168 (valueT
) 0, &zero_address_frag
);
3169 pool
->id
= latest_pool_num
++;
3176 /* Add the literal in the global 'inst'
3177 structure to the relevant literal pool. */
3180 add_to_lit_pool (unsigned int nbytes
)
3182 #define PADDING_SLOT 0x1
3183 #define LIT_ENTRY_SIZE_MASK 0xFF
3184 literal_pool
* pool
;
3185 unsigned int entry
, pool_size
= 0;
3186 bfd_boolean padding_slot_p
= FALSE
;
3192 imm1
= inst
.operands
[1].imm
;
3193 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3194 : inst
.reloc
.exp
.X_unsigned
? 0
3195 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3196 if (target_big_endian
)
3199 imm2
= inst
.operands
[1].imm
;
3203 pool
= find_or_make_literal_pool ();
3205 /* Check if this literal value is already in the pool. */
3206 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3210 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3211 && (inst
.reloc
.exp
.X_op
== O_constant
)
3212 && (pool
->literals
[entry
].X_add_number
3213 == inst
.reloc
.exp
.X_add_number
)
3214 && (pool
->literals
[entry
].X_md
== nbytes
)
3215 && (pool
->literals
[entry
].X_unsigned
3216 == inst
.reloc
.exp
.X_unsigned
))
3219 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3220 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3221 && (pool
->literals
[entry
].X_add_number
3222 == inst
.reloc
.exp
.X_add_number
)
3223 && (pool
->literals
[entry
].X_add_symbol
3224 == inst
.reloc
.exp
.X_add_symbol
)
3225 && (pool
->literals
[entry
].X_op_symbol
3226 == inst
.reloc
.exp
.X_op_symbol
)
3227 && (pool
->literals
[entry
].X_md
== nbytes
))
3230 else if ((nbytes
== 8)
3231 && !(pool_size
& 0x7)
3232 && ((entry
+ 1) != pool
->next_free_entry
)
3233 && (pool
->literals
[entry
].X_op
== O_constant
)
3234 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3235 && (pool
->literals
[entry
].X_unsigned
3236 == inst
.reloc
.exp
.X_unsigned
)
3237 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3238 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3239 && (pool
->literals
[entry
+ 1].X_unsigned
3240 == inst
.reloc
.exp
.X_unsigned
))
3243 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3244 if (padding_slot_p
&& (nbytes
== 4))
3250 /* Do we need to create a new entry? */
3251 if (entry
== pool
->next_free_entry
)
3253 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3255 inst
.error
= _("literal pool overflow");
3261 /* For 8-byte entries, we align to an 8-byte boundary,
3262 and split it into two 4-byte entries, because on 32-bit
3263 host, 8-byte constants are treated as big num, thus
3264 saved in "generic_bignum" which will be overwritten
3265 by later assignments.
3267 We also need to make sure there is enough space for
3270 We also check to make sure the literal operand is a
3272 if (!(inst
.reloc
.exp
.X_op
== O_constant
3273 || inst
.reloc
.exp
.X_op
== O_big
))
3275 inst
.error
= _("invalid type for literal pool");
3278 else if (pool_size
& 0x7)
3280 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3282 inst
.error
= _("literal pool overflow");
3286 pool
->literals
[entry
] = inst
.reloc
.exp
;
3287 pool
->literals
[entry
].X_op
= O_constant
;
3288 pool
->literals
[entry
].X_add_number
= 0;
3289 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3290 pool
->next_free_entry
+= 1;
3293 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3295 inst
.error
= _("literal pool overflow");
3299 pool
->literals
[entry
] = inst
.reloc
.exp
;
3300 pool
->literals
[entry
].X_op
= O_constant
;
3301 pool
->literals
[entry
].X_add_number
= imm1
;
3302 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3303 pool
->literals
[entry
++].X_md
= 4;
3304 pool
->literals
[entry
] = inst
.reloc
.exp
;
3305 pool
->literals
[entry
].X_op
= O_constant
;
3306 pool
->literals
[entry
].X_add_number
= imm2
;
3307 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3308 pool
->literals
[entry
].X_md
= 4;
3309 pool
->alignment
= 3;
3310 pool
->next_free_entry
+= 1;
3314 pool
->literals
[entry
] = inst
.reloc
.exp
;
3315 pool
->literals
[entry
].X_md
= 4;
3319 /* PR ld/12974: Record the location of the first source line to reference
3320 this entry in the literal pool. If it turns out during linking that the
3321 symbol does not exist we will be able to give an accurate line number for
3322 the (first use of the) missing reference. */
3323 if (debug_type
== DEBUG_DWARF2
)
3324 dwarf2_where (pool
->locs
+ entry
);
3326 pool
->next_free_entry
+= 1;
3328 else if (padding_slot_p
)
3330 pool
->literals
[entry
] = inst
.reloc
.exp
;
3331 pool
->literals
[entry
].X_md
= nbytes
;
3334 inst
.reloc
.exp
.X_op
= O_symbol
;
3335 inst
.reloc
.exp
.X_add_number
= pool_size
;
3336 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3342 tc_start_label_without_colon (void)
3344 bfd_boolean ret
= TRUE
;
3346 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3348 const char *label
= input_line_pointer
;
3350 while (!is_end_of_line
[(int) label
[-1]])
3355 as_bad (_("Invalid label '%s'"), label
);
3359 asmfunc_debug (label
);
3361 asmfunc_state
= WAITING_ENDASMFUNC
;
3367 /* Can't use symbol_new here, so have to create a symbol and then at
3368 a later date assign it a value. Thats what these functions do. */
3371 symbol_locate (symbolS
* symbolP
,
3372 const char * name
, /* It is copied, the caller can modify. */
3373 segT segment
, /* Segment identifier (SEG_<something>). */
3374 valueT valu
, /* Symbol value. */
3375 fragS
* frag
) /* Associated fragment. */
3378 char * preserved_copy_of_name
;
3380 name_length
= strlen (name
) + 1; /* +1 for \0. */
3381 obstack_grow (¬es
, name
, name_length
);
3382 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3384 #ifdef tc_canonicalize_symbol_name
3385 preserved_copy_of_name
=
3386 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3389 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3391 S_SET_SEGMENT (symbolP
, segment
);
3392 S_SET_VALUE (symbolP
, valu
);
3393 symbol_clear_list_pointers (symbolP
);
3395 symbol_set_frag (symbolP
, frag
);
3397 /* Link to end of symbol chain. */
3399 extern int symbol_table_frozen
;
3401 if (symbol_table_frozen
)
3405 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3407 obj_symbol_new_hook (symbolP
);
3409 #ifdef tc_symbol_new_hook
3410 tc_symbol_new_hook (symbolP
);
3414 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3415 #endif /* DEBUG_SYMS */
3419 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3422 literal_pool
* pool
;
3425 pool
= find_literal_pool ();
3427 || pool
->symbol
== NULL
3428 || pool
->next_free_entry
== 0)
3431 /* Align pool as you have word accesses.
3432 Only make a frag if we have to. */
3434 frag_align (pool
->alignment
, 0, 0);
3436 record_alignment (now_seg
, 2);
3439 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3440 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3442 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3444 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3445 (valueT
) frag_now_fix (), frag_now
);
3446 symbol_table_insert (pool
->symbol
);
3448 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3450 #if defined OBJ_COFF || defined OBJ_ELF
3451 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3454 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3457 if (debug_type
== DEBUG_DWARF2
)
3458 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3460 /* First output the expression in the instruction to the pool. */
3461 emit_expr (&(pool
->literals
[entry
]),
3462 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3465 /* Mark the pool as empty. */
3466 pool
->next_free_entry
= 0;
3467 pool
->symbol
= NULL
;
3471 /* Forward declarations for functions below, in the MD interface
3473 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3474 static valueT
create_unwind_entry (int);
3475 static void start_unwind_section (const segT
, int);
3476 static void add_unwind_opcode (valueT
, int);
3477 static void flush_pending_unwind (void);
3479 /* Directives: Data. */
3482 s_arm_elf_cons (int nbytes
)
3486 #ifdef md_flush_pending_output
3487 md_flush_pending_output ();
3490 if (is_it_end_of_statement ())
3492 demand_empty_rest_of_line ();
3496 #ifdef md_cons_align
3497 md_cons_align (nbytes
);
3500 mapping_state (MAP_DATA
);
3504 char *base
= input_line_pointer
;
3508 if (exp
.X_op
!= O_symbol
)
3509 emit_expr (&exp
, (unsigned int) nbytes
);
3512 char *before_reloc
= input_line_pointer
;
3513 reloc
= parse_reloc (&input_line_pointer
);
3516 as_bad (_("unrecognized relocation suffix"));
3517 ignore_rest_of_line ();
3520 else if (reloc
== BFD_RELOC_UNUSED
)
3521 emit_expr (&exp
, (unsigned int) nbytes
);
3524 reloc_howto_type
*howto
= (reloc_howto_type
*)
3525 bfd_reloc_type_lookup (stdoutput
,
3526 (bfd_reloc_code_real_type
) reloc
);
3527 int size
= bfd_get_reloc_size (howto
);
3529 if (reloc
== BFD_RELOC_ARM_PLT32
)
3531 as_bad (_("(plt) is only valid on branch targets"));
3532 reloc
= BFD_RELOC_UNUSED
;
3537 as_bad (_("%s relocations do not fit in %d bytes"),
3538 howto
->name
, nbytes
);
3541 /* We've parsed an expression stopping at O_symbol.
3542 But there may be more expression left now that we
3543 have parsed the relocation marker. Parse it again.
3544 XXX Surely there is a cleaner way to do this. */
3545 char *p
= input_line_pointer
;
3547 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3549 memcpy (save_buf
, base
, input_line_pointer
- base
);
3550 memmove (base
+ (input_line_pointer
- before_reloc
),
3551 base
, before_reloc
- base
);
3553 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3555 memcpy (base
, save_buf
, p
- base
);
3557 offset
= nbytes
- size
;
3558 p
= frag_more (nbytes
);
3559 memset (p
, 0, nbytes
);
3560 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3561 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3567 while (*input_line_pointer
++ == ',');
3569 /* Put terminator back into stream. */
3570 input_line_pointer
--;
3571 demand_empty_rest_of_line ();
3574 /* Emit an expression containing a 32-bit thumb instruction.
3575 Implementation based on put_thumb32_insn. */
3578 emit_thumb32_expr (expressionS
* exp
)
3580 expressionS exp_high
= *exp
;
3582 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3583 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3584 exp
->X_add_number
&= 0xffff;
3585 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3588 /* Guess the instruction size based on the opcode. */
3591 thumb_insn_size (int opcode
)
3593 if ((unsigned int) opcode
< 0xe800u
)
3595 else if ((unsigned int) opcode
>= 0xe8000000u
)
3602 emit_insn (expressionS
*exp
, int nbytes
)
3606 if (exp
->X_op
== O_constant
)
3611 size
= thumb_insn_size (exp
->X_add_number
);
3615 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3617 as_bad (_(".inst.n operand too big. "\
3618 "Use .inst.w instead"));
3623 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3624 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3626 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3628 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3629 emit_thumb32_expr (exp
);
3631 emit_expr (exp
, (unsigned int) size
);
3633 it_fsm_post_encode ();
3637 as_bad (_("cannot determine Thumb instruction size. " \
3638 "Use .inst.n/.inst.w instead"));
3641 as_bad (_("constant expression required"));
3646 /* Like s_arm_elf_cons but do not use md_cons_align and
3647 set the mapping state to MAP_ARM/MAP_THUMB. */
3650 s_arm_elf_inst (int nbytes
)
3652 if (is_it_end_of_statement ())
3654 demand_empty_rest_of_line ();
3658 /* Calling mapping_state () here will not change ARM/THUMB,
3659 but will ensure not to be in DATA state. */
3662 mapping_state (MAP_THUMB
);
3667 as_bad (_("width suffixes are invalid in ARM mode"));
3668 ignore_rest_of_line ();
3674 mapping_state (MAP_ARM
);
3683 if (! emit_insn (& exp
, nbytes
))
3685 ignore_rest_of_line ();
3689 while (*input_line_pointer
++ == ',');
3691 /* Put terminator back into stream. */
3692 input_line_pointer
--;
3693 demand_empty_rest_of_line ();
3696 /* Parse a .rel31 directive. */
3699 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3706 if (*input_line_pointer
== '1')
3707 highbit
= 0x80000000;
3708 else if (*input_line_pointer
!= '0')
3709 as_bad (_("expected 0 or 1"));
3711 input_line_pointer
++;
3712 if (*input_line_pointer
!= ',')
3713 as_bad (_("missing comma"));
3714 input_line_pointer
++;
3716 #ifdef md_flush_pending_output
3717 md_flush_pending_output ();
3720 #ifdef md_cons_align
3724 mapping_state (MAP_DATA
);
3729 md_number_to_chars (p
, highbit
, 4);
3730 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3731 BFD_RELOC_ARM_PREL31
);
3733 demand_empty_rest_of_line ();
3736 /* Directives: AEABI stack-unwind tables. */
3738 /* Parse an unwind_fnstart directive. Simply records the current location. */
3741 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3743 demand_empty_rest_of_line ();
3744 if (unwind
.proc_start
)
3746 as_bad (_("duplicate .fnstart directive"));
3750 /* Mark the start of the function. */
3751 unwind
.proc_start
= expr_build_dot ();
3753 /* Reset the rest of the unwind info. */
3754 unwind
.opcode_count
= 0;
3755 unwind
.table_entry
= NULL
;
3756 unwind
.personality_routine
= NULL
;
3757 unwind
.personality_index
= -1;
3758 unwind
.frame_size
= 0;
3759 unwind
.fp_offset
= 0;
3760 unwind
.fp_reg
= REG_SP
;
3762 unwind
.sp_restored
= 0;
3766 /* Parse a handlerdata directive. Creates the exception handling table entry
3767 for the function. */
3770 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3772 demand_empty_rest_of_line ();
3773 if (!unwind
.proc_start
)
3774 as_bad (MISSING_FNSTART
);
3776 if (unwind
.table_entry
)
3777 as_bad (_("duplicate .handlerdata directive"));
3779 create_unwind_entry (1);
3782 /* Parse an unwind_fnend directive. Generates the index table entry. */
3785 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3790 unsigned int marked_pr_dependency
;
3792 demand_empty_rest_of_line ();
3794 if (!unwind
.proc_start
)
3796 as_bad (_(".fnend directive without .fnstart"));
3800 /* Add eh table entry. */
3801 if (unwind
.table_entry
== NULL
)
3802 val
= create_unwind_entry (0);
3806 /* Add index table entry. This is two words. */
3807 start_unwind_section (unwind
.saved_seg
, 1);
3808 frag_align (2, 0, 0);
3809 record_alignment (now_seg
, 2);
3811 ptr
= frag_more (8);
3813 where
= frag_now_fix () - 8;
3815 /* Self relative offset of the function start. */
3816 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3817 BFD_RELOC_ARM_PREL31
);
3819 /* Indicate dependency on EHABI-defined personality routines to the
3820 linker, if it hasn't been done already. */
3821 marked_pr_dependency
3822 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3823 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3824 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3826 static const char *const name
[] =
3828 "__aeabi_unwind_cpp_pr0",
3829 "__aeabi_unwind_cpp_pr1",
3830 "__aeabi_unwind_cpp_pr2"
3832 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3833 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3834 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3835 |= 1 << unwind
.personality_index
;
3839 /* Inline exception table entry. */
3840 md_number_to_chars (ptr
+ 4, val
, 4);
3842 /* Self relative offset of the table entry. */
3843 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3844 BFD_RELOC_ARM_PREL31
);
3846 /* Restore the original section. */
3847 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3849 unwind
.proc_start
= NULL
;
3853 /* Parse an unwind_cantunwind directive. */
3856 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3858 demand_empty_rest_of_line ();
3859 if (!unwind
.proc_start
)
3860 as_bad (MISSING_FNSTART
);
3862 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3863 as_bad (_("personality routine specified for cantunwind frame"));
3865 unwind
.personality_index
= -2;
3869 /* Parse a personalityindex directive. */
3872 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3876 if (!unwind
.proc_start
)
3877 as_bad (MISSING_FNSTART
);
3879 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3880 as_bad (_("duplicate .personalityindex directive"));
3884 if (exp
.X_op
!= O_constant
3885 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3887 as_bad (_("bad personality routine number"));
3888 ignore_rest_of_line ();
3892 unwind
.personality_index
= exp
.X_add_number
;
3894 demand_empty_rest_of_line ();
3898 /* Parse a personality directive. */
3901 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3905 if (!unwind
.proc_start
)
3906 as_bad (MISSING_FNSTART
);
3908 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3909 as_bad (_("duplicate .personality directive"));
3911 c
= get_symbol_name (& name
);
3912 p
= input_line_pointer
;
3914 ++ input_line_pointer
;
3915 unwind
.personality_routine
= symbol_find_or_make (name
);
3917 demand_empty_rest_of_line ();
3921 /* Parse a directive saving core registers. */
3924 s_arm_unwind_save_core (void)
3930 range
= parse_reg_list (&input_line_pointer
);
3933 as_bad (_("expected register list"));
3934 ignore_rest_of_line ();
3938 demand_empty_rest_of_line ();
3940 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3941 into .unwind_save {..., sp...}. We aren't bothered about the value of
3942 ip because it is clobbered by calls. */
3943 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3944 && (range
& 0x3000) == 0x1000)
3946 unwind
.opcode_count
--;
3947 unwind
.sp_restored
= 0;
3948 range
= (range
| 0x2000) & ~0x1000;
3949 unwind
.pending_offset
= 0;
3955 /* See if we can use the short opcodes. These pop a block of up to 8
3956 registers starting with r4, plus maybe r14. */
3957 for (n
= 0; n
< 8; n
++)
3959 /* Break at the first non-saved register. */
3960 if ((range
& (1 << (n
+ 4))) == 0)
3963 /* See if there are any other bits set. */
3964 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3966 /* Use the long form. */
3967 op
= 0x8000 | ((range
>> 4) & 0xfff);
3968 add_unwind_opcode (op
, 2);
3972 /* Use the short form. */
3974 op
= 0xa8; /* Pop r14. */
3976 op
= 0xa0; /* Do not pop r14. */
3978 add_unwind_opcode (op
, 1);
3985 op
= 0xb100 | (range
& 0xf);
3986 add_unwind_opcode (op
, 2);
3989 /* Record the number of bytes pushed. */
3990 for (n
= 0; n
< 16; n
++)
3992 if (range
& (1 << n
))
3993 unwind
.frame_size
+= 4;
3998 /* Parse a directive saving FPA registers. */
4001 s_arm_unwind_save_fpa (int reg
)
4007 /* Get Number of registers to transfer. */
4008 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4011 exp
.X_op
= O_illegal
;
4013 if (exp
.X_op
!= O_constant
)
4015 as_bad (_("expected , <constant>"));
4016 ignore_rest_of_line ();
4020 num_regs
= exp
.X_add_number
;
4022 if (num_regs
< 1 || num_regs
> 4)
4024 as_bad (_("number of registers must be in the range [1:4]"));
4025 ignore_rest_of_line ();
4029 demand_empty_rest_of_line ();
4034 op
= 0xb4 | (num_regs
- 1);
4035 add_unwind_opcode (op
, 1);
4040 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4041 add_unwind_opcode (op
, 2);
4043 unwind
.frame_size
+= num_regs
* 12;
4047 /* Parse a directive saving VFP registers for ARMv6 and above. */
4050 s_arm_unwind_save_vfp_armv6 (void)
4055 int num_vfpv3_regs
= 0;
4056 int num_regs_below_16
;
4058 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4061 as_bad (_("expected register list"));
4062 ignore_rest_of_line ();
4066 demand_empty_rest_of_line ();
4068 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4069 than FSTMX/FLDMX-style ones). */
4071 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4073 num_vfpv3_regs
= count
;
4074 else if (start
+ count
> 16)
4075 num_vfpv3_regs
= start
+ count
- 16;
4077 if (num_vfpv3_regs
> 0)
4079 int start_offset
= start
> 16 ? start
- 16 : 0;
4080 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4081 add_unwind_opcode (op
, 2);
4084 /* Generate opcode for registers numbered in the range 0 .. 15. */
4085 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4086 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4087 if (num_regs_below_16
> 0)
4089 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4090 add_unwind_opcode (op
, 2);
4093 unwind
.frame_size
+= count
* 8;
4097 /* Parse a directive saving VFP registers for pre-ARMv6. */
4100 s_arm_unwind_save_vfp (void)
4106 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4109 as_bad (_("expected register list"));
4110 ignore_rest_of_line ();
4114 demand_empty_rest_of_line ();
4119 op
= 0xb8 | (count
- 1);
4120 add_unwind_opcode (op
, 1);
4125 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4126 add_unwind_opcode (op
, 2);
4128 unwind
.frame_size
+= count
* 8 + 4;
4132 /* Parse a directive saving iWMMXt data registers. */
4135 s_arm_unwind_save_mmxwr (void)
4143 if (*input_line_pointer
== '{')
4144 input_line_pointer
++;
4148 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4152 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4157 as_tsktsk (_("register list not in ascending order"));
4160 if (*input_line_pointer
== '-')
4162 input_line_pointer
++;
4163 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4166 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4169 else if (reg
>= hi_reg
)
4171 as_bad (_("bad register range"));
4174 for (; reg
< hi_reg
; reg
++)
4178 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4180 skip_past_char (&input_line_pointer
, '}');
4182 demand_empty_rest_of_line ();
4184 /* Generate any deferred opcodes because we're going to be looking at
4186 flush_pending_unwind ();
4188 for (i
= 0; i
< 16; i
++)
4190 if (mask
& (1 << i
))
4191 unwind
.frame_size
+= 8;
4194 /* Attempt to combine with a previous opcode. We do this because gcc
4195 likes to output separate unwind directives for a single block of
4197 if (unwind
.opcode_count
> 0)
4199 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4200 if ((i
& 0xf8) == 0xc0)
4203 /* Only merge if the blocks are contiguous. */
4206 if ((mask
& 0xfe00) == (1 << 9))
4208 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4209 unwind
.opcode_count
--;
4212 else if (i
== 6 && unwind
.opcode_count
>= 2)
4214 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4218 op
= 0xffff << (reg
- 1);
4220 && ((mask
& op
) == (1u << (reg
- 1))))
4222 op
= (1 << (reg
+ i
+ 1)) - 1;
4223 op
&= ~((1 << reg
) - 1);
4225 unwind
.opcode_count
-= 2;
4232 /* We want to generate opcodes in the order the registers have been
4233 saved, ie. descending order. */
4234 for (reg
= 15; reg
>= -1; reg
--)
4236 /* Save registers in blocks. */
4238 || !(mask
& (1 << reg
)))
4240 /* We found an unsaved reg. Generate opcodes to save the
4247 op
= 0xc0 | (hi_reg
- 10);
4248 add_unwind_opcode (op
, 1);
4253 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4254 add_unwind_opcode (op
, 2);
4263 ignore_rest_of_line ();
4267 s_arm_unwind_save_mmxwcg (void)
4274 if (*input_line_pointer
== '{')
4275 input_line_pointer
++;
4277 skip_whitespace (input_line_pointer
);
4281 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4285 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4291 as_tsktsk (_("register list not in ascending order"));
4294 if (*input_line_pointer
== '-')
4296 input_line_pointer
++;
4297 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4300 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4303 else if (reg
>= hi_reg
)
4305 as_bad (_("bad register range"));
4308 for (; reg
< hi_reg
; reg
++)
4312 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4314 skip_past_char (&input_line_pointer
, '}');
4316 demand_empty_rest_of_line ();
4318 /* Generate any deferred opcodes because we're going to be looking at
4320 flush_pending_unwind ();
4322 for (reg
= 0; reg
< 16; reg
++)
4324 if (mask
& (1 << reg
))
4325 unwind
.frame_size
+= 4;
4328 add_unwind_opcode (op
, 2);
4331 ignore_rest_of_line ();
4335 /* Parse an unwind_save directive.
4336 If the argument is non-zero, this is a .vsave directive. */
4339 s_arm_unwind_save (int arch_v6
)
4342 struct reg_entry
*reg
;
4343 bfd_boolean had_brace
= FALSE
;
4345 if (!unwind
.proc_start
)
4346 as_bad (MISSING_FNSTART
);
4348 /* Figure out what sort of save we have. */
4349 peek
= input_line_pointer
;
4357 reg
= arm_reg_parse_multi (&peek
);
4361 as_bad (_("register expected"));
4362 ignore_rest_of_line ();
4371 as_bad (_("FPA .unwind_save does not take a register list"));
4372 ignore_rest_of_line ();
4375 input_line_pointer
= peek
;
4376 s_arm_unwind_save_fpa (reg
->number
);
4380 s_arm_unwind_save_core ();
4385 s_arm_unwind_save_vfp_armv6 ();
4387 s_arm_unwind_save_vfp ();
4390 case REG_TYPE_MMXWR
:
4391 s_arm_unwind_save_mmxwr ();
4394 case REG_TYPE_MMXWCG
:
4395 s_arm_unwind_save_mmxwcg ();
4399 as_bad (_(".unwind_save does not support this kind of register"));
4400 ignore_rest_of_line ();
4405 /* Parse an unwind_movsp directive. */
4408 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4414 if (!unwind
.proc_start
)
4415 as_bad (MISSING_FNSTART
);
4417 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4420 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4421 ignore_rest_of_line ();
4425 /* Optional constant. */
4426 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4428 if (immediate_for_directive (&offset
) == FAIL
)
4434 demand_empty_rest_of_line ();
4436 if (reg
== REG_SP
|| reg
== REG_PC
)
4438 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4442 if (unwind
.fp_reg
!= REG_SP
)
4443 as_bad (_("unexpected .unwind_movsp directive"));
4445 /* Generate opcode to restore the value. */
4447 add_unwind_opcode (op
, 1);
4449 /* Record the information for later. */
4450 unwind
.fp_reg
= reg
;
4451 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4452 unwind
.sp_restored
= 1;
4455 /* Parse an unwind_pad directive. */
4458 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4462 if (!unwind
.proc_start
)
4463 as_bad (MISSING_FNSTART
);
4465 if (immediate_for_directive (&offset
) == FAIL
)
4470 as_bad (_("stack increment must be multiple of 4"));
4471 ignore_rest_of_line ();
4475 /* Don't generate any opcodes, just record the details for later. */
4476 unwind
.frame_size
+= offset
;
4477 unwind
.pending_offset
+= offset
;
4479 demand_empty_rest_of_line ();
4482 /* Parse an unwind_setfp directive. */
4485 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4491 if (!unwind
.proc_start
)
4492 as_bad (MISSING_FNSTART
);
4494 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4495 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4498 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4500 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4502 as_bad (_("expected <reg>, <reg>"));
4503 ignore_rest_of_line ();
4507 /* Optional constant. */
4508 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4510 if (immediate_for_directive (&offset
) == FAIL
)
4516 demand_empty_rest_of_line ();
4518 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4520 as_bad (_("register must be either sp or set by a previous"
4521 "unwind_movsp directive"));
4525 /* Don't generate any opcodes, just record the information for later. */
4526 unwind
.fp_reg
= fp_reg
;
4528 if (sp_reg
== REG_SP
)
4529 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4531 unwind
.fp_offset
-= offset
;
4534 /* Parse an unwind_raw directive. */
4537 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4540 /* This is an arbitrary limit. */
4541 unsigned char op
[16];
4544 if (!unwind
.proc_start
)
4545 as_bad (MISSING_FNSTART
);
4548 if (exp
.X_op
== O_constant
4549 && skip_past_comma (&input_line_pointer
) != FAIL
)
4551 unwind
.frame_size
+= exp
.X_add_number
;
4555 exp
.X_op
= O_illegal
;
4557 if (exp
.X_op
!= O_constant
)
4559 as_bad (_("expected <offset>, <opcode>"));
4560 ignore_rest_of_line ();
4566 /* Parse the opcode. */
4571 as_bad (_("unwind opcode too long"));
4572 ignore_rest_of_line ();
4574 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4576 as_bad (_("invalid unwind opcode"));
4577 ignore_rest_of_line ();
4580 op
[count
++] = exp
.X_add_number
;
4582 /* Parse the next byte. */
4583 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4589 /* Add the opcode bytes in reverse order. */
4591 add_unwind_opcode (op
[count
], 1);
4593 demand_empty_rest_of_line ();
4597 /* Parse a .eabi_attribute directive. */
4600 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4602 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4604 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4605 attributes_set_explicitly
[tag
] = 1;
4608 /* Emit a tls fix for the symbol. */
4611 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4615 #ifdef md_flush_pending_output
4616 md_flush_pending_output ();
4619 #ifdef md_cons_align
4623 /* Since we're just labelling the code, there's no need to define a
4626 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4627 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4628 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4629 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4631 #endif /* OBJ_ELF */
4633 static void s_arm_arch (int);
4634 static void s_arm_object_arch (int);
4635 static void s_arm_cpu (int);
4636 static void s_arm_fpu (int);
4637 static void s_arm_arch_extension (int);
4642 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4649 if (exp
.X_op
== O_symbol
)
4650 exp
.X_op
= O_secrel
;
4652 emit_expr (&exp
, 4);
4654 while (*input_line_pointer
++ == ',');
4656 input_line_pointer
--;
4657 demand_empty_rest_of_line ();
4661 /* This table describes all the machine specific pseudo-ops the assembler
4662 has to support. The fields are:
4663 pseudo-op name without dot
4664 function to call to execute this pseudo-op
4665 Integer arg to pass to the function. */
4667 const pseudo_typeS md_pseudo_table
[] =
4669 /* Never called because '.req' does not start a line. */
4670 { "req", s_req
, 0 },
4671 /* Following two are likewise never called. */
4674 { "unreq", s_unreq
, 0 },
4675 { "bss", s_bss
, 0 },
4676 { "align", s_align_ptwo
, 2 },
4677 { "arm", s_arm
, 0 },
4678 { "thumb", s_thumb
, 0 },
4679 { "code", s_code
, 0 },
4680 { "force_thumb", s_force_thumb
, 0 },
4681 { "thumb_func", s_thumb_func
, 0 },
4682 { "thumb_set", s_thumb_set
, 0 },
4683 { "even", s_even
, 0 },
4684 { "ltorg", s_ltorg
, 0 },
4685 { "pool", s_ltorg
, 0 },
4686 { "syntax", s_syntax
, 0 },
4687 { "cpu", s_arm_cpu
, 0 },
4688 { "arch", s_arm_arch
, 0 },
4689 { "object_arch", s_arm_object_arch
, 0 },
4690 { "fpu", s_arm_fpu
, 0 },
4691 { "arch_extension", s_arm_arch_extension
, 0 },
4693 { "word", s_arm_elf_cons
, 4 },
4694 { "long", s_arm_elf_cons
, 4 },
4695 { "inst.n", s_arm_elf_inst
, 2 },
4696 { "inst.w", s_arm_elf_inst
, 4 },
4697 { "inst", s_arm_elf_inst
, 0 },
4698 { "rel31", s_arm_rel31
, 0 },
4699 { "fnstart", s_arm_unwind_fnstart
, 0 },
4700 { "fnend", s_arm_unwind_fnend
, 0 },
4701 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4702 { "personality", s_arm_unwind_personality
, 0 },
4703 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4704 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4705 { "save", s_arm_unwind_save
, 0 },
4706 { "vsave", s_arm_unwind_save
, 1 },
4707 { "movsp", s_arm_unwind_movsp
, 0 },
4708 { "pad", s_arm_unwind_pad
, 0 },
4709 { "setfp", s_arm_unwind_setfp
, 0 },
4710 { "unwind_raw", s_arm_unwind_raw
, 0 },
4711 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4712 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4716 /* These are used for dwarf. */
4720 /* These are used for dwarf2. */
4721 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4722 { "loc", dwarf2_directive_loc
, 0 },
4723 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4725 { "extend", float_cons
, 'x' },
4726 { "ldouble", float_cons
, 'x' },
4727 { "packed", float_cons
, 'p' },
4729 {"secrel32", pe_directive_secrel
, 0},
4732 /* These are for compatibility with CodeComposer Studio. */
4733 {"ref", s_ccs_ref
, 0},
4734 {"def", s_ccs_def
, 0},
4735 {"asmfunc", s_ccs_asmfunc
, 0},
4736 {"endasmfunc", s_ccs_endasmfunc
, 0},
4741 /* Parser functions used exclusively in instruction operands. */
4743 /* Generic immediate-value read function for use in insn parsing.
4744 STR points to the beginning of the immediate (the leading #);
4745 VAL receives the value; if the value is outside [MIN, MAX]
4746 issue an error. PREFIX_OPT is true if the immediate prefix is
4750 parse_immediate (char **str
, int *val
, int min
, int max
,
4751 bfd_boolean prefix_opt
)
4754 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4755 if (exp
.X_op
!= O_constant
)
4757 inst
.error
= _("constant expression required");
4761 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4763 inst
.error
= _("immediate value out of range");
4767 *val
= exp
.X_add_number
;
4771 /* Less-generic immediate-value read function with the possibility of loading a
4772 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4773 instructions. Puts the result directly in inst.operands[i]. */
4776 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4777 bfd_boolean allow_symbol_p
)
4780 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4783 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4785 if (exp_p
->X_op
== O_constant
)
4787 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4788 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4789 O_constant. We have to be careful not to break compilation for
4790 32-bit X_add_number, though. */
4791 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4793 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4794 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4796 inst
.operands
[i
].regisimm
= 1;
4799 else if (exp_p
->X_op
== O_big
4800 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4802 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4804 /* Bignums have their least significant bits in
4805 generic_bignum[0]. Make sure we put 32 bits in imm and
4806 32 bits in reg, in a (hopefully) portable way. */
4807 gas_assert (parts
!= 0);
4809 /* Make sure that the number is not too big.
4810 PR 11972: Bignums can now be sign-extended to the
4811 size of a .octa so check that the out of range bits
4812 are all zero or all one. */
4813 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4815 LITTLENUM_TYPE m
= -1;
4817 if (generic_bignum
[parts
* 2] != 0
4818 && generic_bignum
[parts
* 2] != m
)
4821 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4822 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4826 inst
.operands
[i
].imm
= 0;
4827 for (j
= 0; j
< parts
; j
++, idx
++)
4828 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4829 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4830 inst
.operands
[i
].reg
= 0;
4831 for (j
= 0; j
< parts
; j
++, idx
++)
4832 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4833 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4834 inst
.operands
[i
].regisimm
= 1;
4836 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4844 /* Returns the pseudo-register number of an FPA immediate constant,
4845 or FAIL if there isn't a valid constant here. */
4848 parse_fpa_immediate (char ** str
)
4850 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4856 /* First try and match exact strings, this is to guarantee
4857 that some formats will work even for cross assembly. */
4859 for (i
= 0; fp_const
[i
]; i
++)
4861 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4865 *str
+= strlen (fp_const
[i
]);
4866 if (is_end_of_line
[(unsigned char) **str
])
4872 /* Just because we didn't get a match doesn't mean that the constant
4873 isn't valid, just that it is in a format that we don't
4874 automatically recognize. Try parsing it with the standard
4875 expression routines. */
4877 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4879 /* Look for a raw floating point number. */
4880 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4881 && is_end_of_line
[(unsigned char) *save_in
])
4883 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4885 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4887 if (words
[j
] != fp_values
[i
][j
])
4891 if (j
== MAX_LITTLENUMS
)
4899 /* Try and parse a more complex expression, this will probably fail
4900 unless the code uses a floating point prefix (eg "0f"). */
4901 save_in
= input_line_pointer
;
4902 input_line_pointer
= *str
;
4903 if (expression (&exp
) == absolute_section
4904 && exp
.X_op
== O_big
4905 && exp
.X_add_number
< 0)
4907 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4909 #define X_PRECISION 5
4910 #define E_PRECISION 15L
4911 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4913 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4915 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4917 if (words
[j
] != fp_values
[i
][j
])
4921 if (j
== MAX_LITTLENUMS
)
4923 *str
= input_line_pointer
;
4924 input_line_pointer
= save_in
;
4931 *str
= input_line_pointer
;
4932 input_line_pointer
= save_in
;
4933 inst
.error
= _("invalid FPA immediate expression");
4937 /* Returns 1 if a number has "quarter-precision" float format
4938 0baBbbbbbc defgh000 00000000 00000000. */
4941 is_quarter_float (unsigned imm
)
4943 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4944 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4948 /* Detect the presence of a floating point or integer zero constant,
4952 parse_ifimm_zero (char **in
)
4956 if (!is_immediate_prefix (**in
))
4961 /* Accept #0x0 as a synonym for #0. */
4962 if (strncmp (*in
, "0x", 2) == 0)
4965 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4970 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4971 &generic_floating_point_number
);
4974 && generic_floating_point_number
.sign
== '+'
4975 && (generic_floating_point_number
.low
4976 > generic_floating_point_number
.leader
))
4982 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4983 0baBbbbbbc defgh000 00000000 00000000.
4984 The zero and minus-zero cases need special handling, since they can't be
4985 encoded in the "quarter-precision" float format, but can nonetheless be
4986 loaded as integer constants. */
4989 parse_qfloat_immediate (char **ccp
, int *immed
)
4993 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4994 int found_fpchar
= 0;
4996 skip_past_char (&str
, '#');
4998 /* We must not accidentally parse an integer as a floating-point number. Make
4999 sure that the value we parse is not an integer by checking for special
5000 characters '.' or 'e'.
5001 FIXME: This is a horrible hack, but doing better is tricky because type
5002 information isn't in a very usable state at parse time. */
5004 skip_whitespace (fpnum
);
5006 if (strncmp (fpnum
, "0x", 2) == 0)
5010 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5011 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5021 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5023 unsigned fpword
= 0;
5026 /* Our FP word must be 32 bits (single-precision FP). */
5027 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5029 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5033 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5046 /* Shift operands. */
5049 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5052 struct asm_shift_name
5055 enum shift_kind kind
;
5058 /* Third argument to parse_shift. */
5059 enum parse_shift_mode
5061 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5062 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5063 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5064 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5065 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5068 /* Parse a <shift> specifier on an ARM data processing instruction.
5069 This has three forms:
5071 (LSL|LSR|ASL|ASR|ROR) Rs
5072 (LSL|LSR|ASL|ASR|ROR) #imm
5075 Note that ASL is assimilated to LSL in the instruction encoding, and
5076 RRX to ROR #0 (which cannot be written as such). */
5079 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5081 const struct asm_shift_name
*shift_name
;
5082 enum shift_kind shift
;
5087 for (p
= *str
; ISALPHA (*p
); p
++)
5092 inst
.error
= _("shift expression expected");
5096 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5099 if (shift_name
== NULL
)
5101 inst
.error
= _("shift expression expected");
5105 shift
= shift_name
->kind
;
5109 case NO_SHIFT_RESTRICT
:
5110 case SHIFT_IMMEDIATE
: break;
5112 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5113 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5115 inst
.error
= _("'LSL' or 'ASR' required");
5120 case SHIFT_LSL_IMMEDIATE
:
5121 if (shift
!= SHIFT_LSL
)
5123 inst
.error
= _("'LSL' required");
5128 case SHIFT_ASR_IMMEDIATE
:
5129 if (shift
!= SHIFT_ASR
)
5131 inst
.error
= _("'ASR' required");
5139 if (shift
!= SHIFT_RRX
)
5141 /* Whitespace can appear here if the next thing is a bare digit. */
5142 skip_whitespace (p
);
5144 if (mode
== NO_SHIFT_RESTRICT
5145 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5147 inst
.operands
[i
].imm
= reg
;
5148 inst
.operands
[i
].immisreg
= 1;
5150 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5153 inst
.operands
[i
].shift_kind
= shift
;
5154 inst
.operands
[i
].shifted
= 1;
5159 /* Parse a <shifter_operand> for an ARM data processing instruction:
5162 #<immediate>, <rotate>
5166 where <shift> is defined by parse_shift above, and <rotate> is a
5167 multiple of 2 between 0 and 30. Validation of immediate operands
5168 is deferred to md_apply_fix. */
5171 parse_shifter_operand (char **str
, int i
)
5176 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5178 inst
.operands
[i
].reg
= value
;
5179 inst
.operands
[i
].isreg
= 1;
5181 /* parse_shift will override this if appropriate */
5182 inst
.reloc
.exp
.X_op
= O_constant
;
5183 inst
.reloc
.exp
.X_add_number
= 0;
5185 if (skip_past_comma (str
) == FAIL
)
5188 /* Shift operation on register. */
5189 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5192 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5195 if (skip_past_comma (str
) == SUCCESS
)
5197 /* #x, y -- ie explicit rotation by Y. */
5198 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5201 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5203 inst
.error
= _("constant expression expected");
5207 value
= exp
.X_add_number
;
5208 if (value
< 0 || value
> 30 || value
% 2 != 0)
5210 inst
.error
= _("invalid rotation");
5213 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5215 inst
.error
= _("invalid constant");
5219 /* Encode as specified. */
5220 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5224 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5225 inst
.reloc
.pc_rel
= 0;
5229 /* Group relocation information. Each entry in the table contains the
5230 textual name of the relocation as may appear in assembler source
5231 and must end with a colon.
5232 Along with this textual name are the relocation codes to be used if
5233 the corresponding instruction is an ALU instruction (ADD or SUB only),
5234 an LDR, an LDRS, or an LDC. */
5236 struct group_reloc_table_entry
5247 /* Varieties of non-ALU group relocation. */
5254 static struct group_reloc_table_entry group_reloc_table
[] =
5255 { /* Program counter relative: */
5257 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5262 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5263 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5264 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5265 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5267 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5272 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5273 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5274 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5275 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5277 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5278 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5279 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5280 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5281 /* Section base relative */
5283 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5288 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5289 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5290 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5291 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5293 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5298 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5299 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5300 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5301 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5303 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5304 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5305 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5306 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5307 /* Absolute thumb alu relocations. */
5309 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5314 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5319 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5324 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5329 /* Given the address of a pointer pointing to the textual name of a group
5330 relocation as may appear in assembler source, attempt to find its details
5331 in group_reloc_table. The pointer will be updated to the character after
5332 the trailing colon. On failure, FAIL will be returned; SUCCESS
5333 otherwise. On success, *entry will be updated to point at the relevant
5334 group_reloc_table entry. */
5337 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5340 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5342 int length
= strlen (group_reloc_table
[i
].name
);
5344 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5345 && (*str
)[length
] == ':')
5347 *out
= &group_reloc_table
[i
];
5348 *str
+= (length
+ 1);
5356 /* Parse a <shifter_operand> for an ARM data processing instruction
5357 (as for parse_shifter_operand) where group relocations are allowed:
5360 #<immediate>, <rotate>
5361 #:<group_reloc>:<expression>
5365 where <group_reloc> is one of the strings defined in group_reloc_table.
5366 The hashes are optional.
5368 Everything else is as for parse_shifter_operand. */
5370 static parse_operand_result
5371 parse_shifter_operand_group_reloc (char **str
, int i
)
5373 /* Determine if we have the sequence of characters #: or just :
5374 coming next. If we do, then we check for a group relocation.
5375 If we don't, punt the whole lot to parse_shifter_operand. */
5377 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5378 || (*str
)[0] == ':')
5380 struct group_reloc_table_entry
*entry
;
5382 if ((*str
)[0] == '#')
5387 /* Try to parse a group relocation. Anything else is an error. */
5388 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5390 inst
.error
= _("unknown group relocation");
5391 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5394 /* We now have the group relocation table entry corresponding to
5395 the name in the assembler source. Next, we parse the expression. */
5396 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5397 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5399 /* Record the relocation type (always the ALU variant here). */
5400 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5401 gas_assert (inst
.reloc
.type
!= 0);
5403 return PARSE_OPERAND_SUCCESS
;
5406 return parse_shifter_operand (str
, i
) == SUCCESS
5407 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5409 /* Never reached. */
5412 /* Parse a Neon alignment expression. Information is written to
5413 inst.operands[i]. We assume the initial ':' has been skipped.
5415 align .imm = align << 8, .immisalign=1, .preind=0 */
5416 static parse_operand_result
5417 parse_neon_alignment (char **str
, int i
)
5422 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5424 if (exp
.X_op
!= O_constant
)
5426 inst
.error
= _("alignment must be constant");
5427 return PARSE_OPERAND_FAIL
;
5430 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5431 inst
.operands
[i
].immisalign
= 1;
5432 /* Alignments are not pre-indexes. */
5433 inst
.operands
[i
].preind
= 0;
5436 return PARSE_OPERAND_SUCCESS
;
5439 /* Parse all forms of an ARM address expression. Information is written
5440 to inst.operands[i] and/or inst.reloc.
5442 Preindexed addressing (.preind=1):
5444 [Rn, #offset] .reg=Rn .reloc.exp=offset
5445 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5446 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5447 .shift_kind=shift .reloc.exp=shift_imm
5449 These three may have a trailing ! which causes .writeback to be set also.
5451 Postindexed addressing (.postind=1, .writeback=1):
5453 [Rn], #offset .reg=Rn .reloc.exp=offset
5454 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5455 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5456 .shift_kind=shift .reloc.exp=shift_imm
5458 Unindexed addressing (.preind=0, .postind=0):
5460 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5464 [Rn]{!} shorthand for [Rn,#0]{!}
5465 =immediate .isreg=0 .reloc.exp=immediate
5466 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5468 It is the caller's responsibility to check for addressing modes not
5469 supported by the instruction, and to set inst.reloc.type. */
5471 static parse_operand_result
5472 parse_address_main (char **str
, int i
, int group_relocations
,
5473 group_reloc_type group_type
)
5478 if (skip_past_char (&p
, '[') == FAIL
)
5480 if (skip_past_char (&p
, '=') == FAIL
)
5482 /* Bare address - translate to PC-relative offset. */
5483 inst
.reloc
.pc_rel
= 1;
5484 inst
.operands
[i
].reg
= REG_PC
;
5485 inst
.operands
[i
].isreg
= 1;
5486 inst
.operands
[i
].preind
= 1;
5488 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5489 return PARSE_OPERAND_FAIL
;
5491 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5492 /*allow_symbol_p=*/TRUE
))
5493 return PARSE_OPERAND_FAIL
;
5496 return PARSE_OPERAND_SUCCESS
;
5499 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5500 skip_whitespace (p
);
5502 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5504 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5505 return PARSE_OPERAND_FAIL
;
5507 inst
.operands
[i
].reg
= reg
;
5508 inst
.operands
[i
].isreg
= 1;
5510 if (skip_past_comma (&p
) == SUCCESS
)
5512 inst
.operands
[i
].preind
= 1;
5515 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5517 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5519 inst
.operands
[i
].imm
= reg
;
5520 inst
.operands
[i
].immisreg
= 1;
5522 if (skip_past_comma (&p
) == SUCCESS
)
5523 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5524 return PARSE_OPERAND_FAIL
;
5526 else if (skip_past_char (&p
, ':') == SUCCESS
)
5528 /* FIXME: '@' should be used here, but it's filtered out by generic
5529 code before we get to see it here. This may be subject to
5531 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5533 if (result
!= PARSE_OPERAND_SUCCESS
)
5538 if (inst
.operands
[i
].negative
)
5540 inst
.operands
[i
].negative
= 0;
5544 if (group_relocations
5545 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5547 struct group_reloc_table_entry
*entry
;
5549 /* Skip over the #: or : sequence. */
5555 /* Try to parse a group relocation. Anything else is an
5557 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5559 inst
.error
= _("unknown group relocation");
5560 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5563 /* We now have the group relocation table entry corresponding to
5564 the name in the assembler source. Next, we parse the
5566 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5567 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5569 /* Record the relocation type. */
5573 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5577 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5581 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5588 if (inst
.reloc
.type
== 0)
5590 inst
.error
= _("this group relocation is not allowed on this instruction");
5591 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5597 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5598 return PARSE_OPERAND_FAIL
;
5599 /* If the offset is 0, find out if it's a +0 or -0. */
5600 if (inst
.reloc
.exp
.X_op
== O_constant
5601 && inst
.reloc
.exp
.X_add_number
== 0)
5603 skip_whitespace (q
);
5607 skip_whitespace (q
);
5610 inst
.operands
[i
].negative
= 1;
5615 else if (skip_past_char (&p
, ':') == SUCCESS
)
5617 /* FIXME: '@' should be used here, but it's filtered out by generic code
5618 before we get to see it here. This may be subject to change. */
5619 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5621 if (result
!= PARSE_OPERAND_SUCCESS
)
5625 if (skip_past_char (&p
, ']') == FAIL
)
5627 inst
.error
= _("']' expected");
5628 return PARSE_OPERAND_FAIL
;
5631 if (skip_past_char (&p
, '!') == SUCCESS
)
5632 inst
.operands
[i
].writeback
= 1;
5634 else if (skip_past_comma (&p
) == SUCCESS
)
5636 if (skip_past_char (&p
, '{') == SUCCESS
)
5638 /* [Rn], {expr} - unindexed, with option */
5639 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5640 0, 255, TRUE
) == FAIL
)
5641 return PARSE_OPERAND_FAIL
;
5643 if (skip_past_char (&p
, '}') == FAIL
)
5645 inst
.error
= _("'}' expected at end of 'option' field");
5646 return PARSE_OPERAND_FAIL
;
5648 if (inst
.operands
[i
].preind
)
5650 inst
.error
= _("cannot combine index with option");
5651 return PARSE_OPERAND_FAIL
;
5654 return PARSE_OPERAND_SUCCESS
;
5658 inst
.operands
[i
].postind
= 1;
5659 inst
.operands
[i
].writeback
= 1;
5661 if (inst
.operands
[i
].preind
)
5663 inst
.error
= _("cannot combine pre- and post-indexing");
5664 return PARSE_OPERAND_FAIL
;
5668 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5670 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5672 /* We might be using the immediate for alignment already. If we
5673 are, OR the register number into the low-order bits. */
5674 if (inst
.operands
[i
].immisalign
)
5675 inst
.operands
[i
].imm
|= reg
;
5677 inst
.operands
[i
].imm
= reg
;
5678 inst
.operands
[i
].immisreg
= 1;
5680 if (skip_past_comma (&p
) == SUCCESS
)
5681 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5682 return PARSE_OPERAND_FAIL
;
5687 if (inst
.operands
[i
].negative
)
5689 inst
.operands
[i
].negative
= 0;
5692 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5693 return PARSE_OPERAND_FAIL
;
5694 /* If the offset is 0, find out if it's a +0 or -0. */
5695 if (inst
.reloc
.exp
.X_op
== O_constant
5696 && inst
.reloc
.exp
.X_add_number
== 0)
5698 skip_whitespace (q
);
5702 skip_whitespace (q
);
5705 inst
.operands
[i
].negative
= 1;
5711 /* If at this point neither .preind nor .postind is set, we have a
5712 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5713 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5715 inst
.operands
[i
].preind
= 1;
5716 inst
.reloc
.exp
.X_op
= O_constant
;
5717 inst
.reloc
.exp
.X_add_number
= 0;
5720 return PARSE_OPERAND_SUCCESS
;
5724 parse_address (char **str
, int i
)
5726 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5730 static parse_operand_result
5731 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5733 return parse_address_main (str
, i
, 1, type
);
5736 /* Parse an operand for a MOVW or MOVT instruction. */
5738 parse_half (char **str
)
5743 skip_past_char (&p
, '#');
5744 if (strncasecmp (p
, ":lower16:", 9) == 0)
5745 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5746 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5747 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5749 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5752 skip_whitespace (p
);
5755 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5758 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5760 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5762 inst
.error
= _("constant expression expected");
5765 if (inst
.reloc
.exp
.X_add_number
< 0
5766 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5768 inst
.error
= _("immediate value out of range");
5776 /* Miscellaneous. */
5778 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5779 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5781 parse_psr (char **str
, bfd_boolean lhs
)
5784 unsigned long psr_field
;
5785 const struct asm_psr
*psr
;
5787 bfd_boolean is_apsr
= FALSE
;
5788 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5790 /* PR gas/12698: If the user has specified -march=all then m_profile will
5791 be TRUE, but we want to ignore it in this case as we are building for any
5792 CPU type, including non-m variants. */
5793 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5796 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5797 feature for ease of use and backwards compatibility. */
5799 if (strncasecmp (p
, "SPSR", 4) == 0)
5802 goto unsupported_psr
;
5804 psr_field
= SPSR_BIT
;
5806 else if (strncasecmp (p
, "CPSR", 4) == 0)
5809 goto unsupported_psr
;
5813 else if (strncasecmp (p
, "APSR", 4) == 0)
5815 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5816 and ARMv7-R architecture CPUs. */
5825 while (ISALNUM (*p
) || *p
== '_');
5827 if (strncasecmp (start
, "iapsr", 5) == 0
5828 || strncasecmp (start
, "eapsr", 5) == 0
5829 || strncasecmp (start
, "xpsr", 4) == 0
5830 || strncasecmp (start
, "psr", 3) == 0)
5831 p
= start
+ strcspn (start
, "rR") + 1;
5833 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5839 /* If APSR is being written, a bitfield may be specified. Note that
5840 APSR itself is handled above. */
5841 if (psr
->field
<= 3)
5843 psr_field
= psr
->field
;
5849 /* M-profile MSR instructions have the mask field set to "10", except
5850 *PSR variants which modify APSR, which may use a different mask (and
5851 have been handled already). Do that by setting the PSR_f field
5853 return psr
->field
| (lhs
? PSR_f
: 0);
5856 goto unsupported_psr
;
5862 /* A suffix follows. */
5868 while (ISALNUM (*p
) || *p
== '_');
5872 /* APSR uses a notation for bits, rather than fields. */
5873 unsigned int nzcvq_bits
= 0;
5874 unsigned int g_bit
= 0;
5877 for (bit
= start
; bit
!= p
; bit
++)
5879 switch (TOLOWER (*bit
))
5882 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5886 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5890 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5894 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5898 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5902 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5906 inst
.error
= _("unexpected bit specified after APSR");
5911 if (nzcvq_bits
== 0x1f)
5916 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5918 inst
.error
= _("selected processor does not "
5919 "support DSP extension");
5926 if ((nzcvq_bits
& 0x20) != 0
5927 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5928 || (g_bit
& 0x2) != 0)
5930 inst
.error
= _("bad bitmask specified after APSR");
5936 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5941 psr_field
|= psr
->field
;
5947 goto error
; /* Garbage after "[CS]PSR". */
5949 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5950 is deprecated, but allow it anyway. */
5954 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5957 else if (!m_profile
)
5958 /* These bits are never right for M-profile devices: don't set them
5959 (only code paths which read/write APSR reach here). */
5960 psr_field
|= (PSR_c
| PSR_f
);
5966 inst
.error
= _("selected processor does not support requested special "
5967 "purpose register");
5971 inst
.error
= _("flag for {c}psr instruction expected");
5975 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5976 value suitable for splatting into the AIF field of the instruction. */
5979 parse_cps_flags (char **str
)
5988 case '\0': case ',':
5991 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5992 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5993 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5996 inst
.error
= _("unrecognized CPS flag");
6001 if (saw_a_flag
== 0)
6003 inst
.error
= _("missing CPS flags");
6011 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6012 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6015 parse_endian_specifier (char **str
)
6020 if (strncasecmp (s
, "BE", 2))
6022 else if (strncasecmp (s
, "LE", 2))
6026 inst
.error
= _("valid endian specifiers are be or le");
6030 if (ISALNUM (s
[2]) || s
[2] == '_')
6032 inst
.error
= _("valid endian specifiers are be or le");
6037 return little_endian
;
6040 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6041 value suitable for poking into the rotate field of an sxt or sxta
6042 instruction, or FAIL on error. */
6045 parse_ror (char **str
)
6050 if (strncasecmp (s
, "ROR", 3) == 0)
6054 inst
.error
= _("missing rotation field after comma");
6058 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6063 case 0: *str
= s
; return 0x0;
6064 case 8: *str
= s
; return 0x1;
6065 case 16: *str
= s
; return 0x2;
6066 case 24: *str
= s
; return 0x3;
6069 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6074 /* Parse a conditional code (from conds[] below). The value returned is in the
6075 range 0 .. 14, or FAIL. */
6077 parse_cond (char **str
)
6080 const struct asm_cond
*c
;
6082 /* Condition codes are always 2 characters, so matching up to
6083 3 characters is sufficient. */
6088 while (ISALPHA (*q
) && n
< 3)
6090 cond
[n
] = TOLOWER (*q
);
6095 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6098 inst
.error
= _("condition required");
6106 /* Record a use of the given feature. */
6108 record_feature_use (const arm_feature_set
*feature
)
6111 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6113 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6116 /* If the given feature available in the selected CPU, mark it as used.
6117 Returns TRUE iff feature is available. */
6119 mark_feature_used (const arm_feature_set
*feature
)
6121 /* Ensure the option is valid on the current architecture. */
6122 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6125 /* Add the appropriate architecture feature for the barrier option used.
6127 record_feature_use (feature
);
6132 /* Parse an option for a barrier instruction. Returns the encoding for the
6135 parse_barrier (char **str
)
6138 const struct asm_barrier_opt
*o
;
6141 while (ISALPHA (*q
))
6144 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6149 if (!mark_feature_used (&o
->arch
))
6156 /* Parse the operands of a table branch instruction. Similar to a memory
6159 parse_tb (char **str
)
6164 if (skip_past_char (&p
, '[') == FAIL
)
6166 inst
.error
= _("'[' expected");
6170 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6172 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6175 inst
.operands
[0].reg
= reg
;
6177 if (skip_past_comma (&p
) == FAIL
)
6179 inst
.error
= _("',' expected");
6183 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6185 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6188 inst
.operands
[0].imm
= reg
;
6190 if (skip_past_comma (&p
) == SUCCESS
)
6192 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6194 if (inst
.reloc
.exp
.X_add_number
!= 1)
6196 inst
.error
= _("invalid shift");
6199 inst
.operands
[0].shifted
= 1;
6202 if (skip_past_char (&p
, ']') == FAIL
)
6204 inst
.error
= _("']' expected");
6211 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6212 information on the types the operands can take and how they are encoded.
6213 Up to four operands may be read; this function handles setting the
6214 ".present" field for each read operand itself.
6215 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6216 else returns FAIL. */
6219 parse_neon_mov (char **str
, int *which_operand
)
6221 int i
= *which_operand
, val
;
6222 enum arm_reg_type rtype
;
6224 struct neon_type_el optype
;
6226 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6228 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6229 inst
.operands
[i
].reg
= val
;
6230 inst
.operands
[i
].isscalar
= 1;
6231 inst
.operands
[i
].vectype
= optype
;
6232 inst
.operands
[i
++].present
= 1;
6234 if (skip_past_comma (&ptr
) == FAIL
)
6237 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6240 inst
.operands
[i
].reg
= val
;
6241 inst
.operands
[i
].isreg
= 1;
6242 inst
.operands
[i
].present
= 1;
6244 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6247 /* Cases 0, 1, 2, 3, 5 (D only). */
6248 if (skip_past_comma (&ptr
) == FAIL
)
6251 inst
.operands
[i
].reg
= val
;
6252 inst
.operands
[i
].isreg
= 1;
6253 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6254 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6255 inst
.operands
[i
].isvec
= 1;
6256 inst
.operands
[i
].vectype
= optype
;
6257 inst
.operands
[i
++].present
= 1;
6259 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6261 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6262 Case 13: VMOV <Sd>, <Rm> */
6263 inst
.operands
[i
].reg
= val
;
6264 inst
.operands
[i
].isreg
= 1;
6265 inst
.operands
[i
].present
= 1;
6267 if (rtype
== REG_TYPE_NQ
)
6269 first_error (_("can't use Neon quad register here"));
6272 else if (rtype
!= REG_TYPE_VFS
)
6275 if (skip_past_comma (&ptr
) == FAIL
)
6277 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6279 inst
.operands
[i
].reg
= val
;
6280 inst
.operands
[i
].isreg
= 1;
6281 inst
.operands
[i
].present
= 1;
6284 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6287 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6288 Case 1: VMOV<c><q> <Dd>, <Dm>
6289 Case 8: VMOV.F32 <Sd>, <Sm>
6290 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6292 inst
.operands
[i
].reg
= val
;
6293 inst
.operands
[i
].isreg
= 1;
6294 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6295 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6296 inst
.operands
[i
].isvec
= 1;
6297 inst
.operands
[i
].vectype
= optype
;
6298 inst
.operands
[i
].present
= 1;
6300 if (skip_past_comma (&ptr
) == SUCCESS
)
6305 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6308 inst
.operands
[i
].reg
= val
;
6309 inst
.operands
[i
].isreg
= 1;
6310 inst
.operands
[i
++].present
= 1;
6312 if (skip_past_comma (&ptr
) == FAIL
)
6315 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6318 inst
.operands
[i
].reg
= val
;
6319 inst
.operands
[i
].isreg
= 1;
6320 inst
.operands
[i
].present
= 1;
6323 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6324 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6325 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6326 Case 10: VMOV.F32 <Sd>, #<imm>
6327 Case 11: VMOV.F64 <Dd>, #<imm> */
6328 inst
.operands
[i
].immisfloat
= 1;
6329 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6331 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6332 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6336 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6340 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6343 inst
.operands
[i
].reg
= val
;
6344 inst
.operands
[i
].isreg
= 1;
6345 inst
.operands
[i
++].present
= 1;
6347 if (skip_past_comma (&ptr
) == FAIL
)
6350 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6352 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6353 inst
.operands
[i
].reg
= val
;
6354 inst
.operands
[i
].isscalar
= 1;
6355 inst
.operands
[i
].present
= 1;
6356 inst
.operands
[i
].vectype
= optype
;
6358 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6360 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6361 inst
.operands
[i
].reg
= val
;
6362 inst
.operands
[i
].isreg
= 1;
6363 inst
.operands
[i
++].present
= 1;
6365 if (skip_past_comma (&ptr
) == FAIL
)
6368 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6371 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6375 inst
.operands
[i
].reg
= val
;
6376 inst
.operands
[i
].isreg
= 1;
6377 inst
.operands
[i
].isvec
= 1;
6378 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6379 inst
.operands
[i
].vectype
= optype
;
6380 inst
.operands
[i
].present
= 1;
6382 if (rtype
== REG_TYPE_VFS
)
6386 if (skip_past_comma (&ptr
) == FAIL
)
6388 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6391 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6394 inst
.operands
[i
].reg
= val
;
6395 inst
.operands
[i
].isreg
= 1;
6396 inst
.operands
[i
].isvec
= 1;
6397 inst
.operands
[i
].issingle
= 1;
6398 inst
.operands
[i
].vectype
= optype
;
6399 inst
.operands
[i
].present
= 1;
6402 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6406 inst
.operands
[i
].reg
= val
;
6407 inst
.operands
[i
].isreg
= 1;
6408 inst
.operands
[i
].isvec
= 1;
6409 inst
.operands
[i
].issingle
= 1;
6410 inst
.operands
[i
].vectype
= optype
;
6411 inst
.operands
[i
].present
= 1;
6416 first_error (_("parse error"));
6420 /* Successfully parsed the operands. Update args. */
6426 first_error (_("expected comma"));
6430 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6434 /* Use this macro when the operand constraints are different
6435 for ARM and THUMB (e.g. ldrd). */
6436 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6437 ((arm_operand) | ((thumb_operand) << 16))
6439 /* Matcher codes for parse_operands. */
6440 enum operand_parse_code
6442 OP_stop
, /* end of line */
6444 OP_RR
, /* ARM register */
6445 OP_RRnpc
, /* ARM register, not r15 */
6446 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6447 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6448 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6449 optional trailing ! */
6450 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6451 OP_RCP
, /* Coprocessor number */
6452 OP_RCN
, /* Coprocessor register */
6453 OP_RF
, /* FPA register */
6454 OP_RVS
, /* VFP single precision register */
6455 OP_RVD
, /* VFP double precision register (0..15) */
6456 OP_RND
, /* Neon double precision register (0..31) */
6457 OP_RNQ
, /* Neon quad precision register */
6458 OP_RVSD
, /* VFP single or double precision register */
6459 OP_RNDQ
, /* Neon double or quad precision register */
6460 OP_RNSDQ
, /* Neon single, double or quad precision register */
6461 OP_RNSC
, /* Neon scalar D[X] */
6462 OP_RVC
, /* VFP control register */
6463 OP_RMF
, /* Maverick F register */
6464 OP_RMD
, /* Maverick D register */
6465 OP_RMFX
, /* Maverick FX register */
6466 OP_RMDX
, /* Maverick DX register */
6467 OP_RMAX
, /* Maverick AX register */
6468 OP_RMDS
, /* Maverick DSPSC register */
6469 OP_RIWR
, /* iWMMXt wR register */
6470 OP_RIWC
, /* iWMMXt wC register */
6471 OP_RIWG
, /* iWMMXt wCG register */
6472 OP_RXA
, /* XScale accumulator register */
6474 OP_REGLST
, /* ARM register list */
6475 OP_VRSLST
, /* VFP single-precision register list */
6476 OP_VRDLST
, /* VFP double-precision register list */
6477 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6478 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6479 OP_NSTRLST
, /* Neon element/structure list */
6481 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6482 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6483 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6484 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6485 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6486 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6487 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6488 OP_VMOV
, /* Neon VMOV operands. */
6489 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6490 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6491 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6493 OP_I0
, /* immediate zero */
6494 OP_I7
, /* immediate value 0 .. 7 */
6495 OP_I15
, /* 0 .. 15 */
6496 OP_I16
, /* 1 .. 16 */
6497 OP_I16z
, /* 0 .. 16 */
6498 OP_I31
, /* 0 .. 31 */
6499 OP_I31w
, /* 0 .. 31, optional trailing ! */
6500 OP_I32
, /* 1 .. 32 */
6501 OP_I32z
, /* 0 .. 32 */
6502 OP_I63
, /* 0 .. 63 */
6503 OP_I63s
, /* -64 .. 63 */
6504 OP_I64
, /* 1 .. 64 */
6505 OP_I64z
, /* 0 .. 64 */
6506 OP_I255
, /* 0 .. 255 */
6508 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6509 OP_I7b
, /* 0 .. 7 */
6510 OP_I15b
, /* 0 .. 15 */
6511 OP_I31b
, /* 0 .. 31 */
6513 OP_SH
, /* shifter operand */
6514 OP_SHG
, /* shifter operand with possible group relocation */
6515 OP_ADDR
, /* Memory address expression (any mode) */
6516 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6517 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6518 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6519 OP_EXP
, /* arbitrary expression */
6520 OP_EXPi
, /* same, with optional immediate prefix */
6521 OP_EXPr
, /* same, with optional relocation suffix */
6522 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6524 OP_CPSF
, /* CPS flags */
6525 OP_ENDI
, /* Endianness specifier */
6526 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6527 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6528 OP_COND
, /* conditional code */
6529 OP_TB
, /* Table branch. */
6531 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6533 OP_RRnpc_I0
, /* ARM register or literal 0 */
6534 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6535 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6536 OP_RF_IF
, /* FPA register or immediate */
6537 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6538 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6540 /* Optional operands. */
6541 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6542 OP_oI31b
, /* 0 .. 31 */
6543 OP_oI32b
, /* 1 .. 32 */
6544 OP_oI32z
, /* 0 .. 32 */
6545 OP_oIffffb
, /* 0 .. 65535 */
6546 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6548 OP_oRR
, /* ARM register */
6549 OP_oRRnpc
, /* ARM register, not the PC */
6550 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6551 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6552 OP_oRND
, /* Optional Neon double precision register */
6553 OP_oRNQ
, /* Optional Neon quad precision register */
6554 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6555 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6556 OP_oSHll
, /* LSL immediate */
6557 OP_oSHar
, /* ASR immediate */
6558 OP_oSHllar
, /* LSL or ASR immediate */
6559 OP_oROR
, /* ROR 0/8/16/24 */
6560 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6562 /* Some pre-defined mixed (ARM/THUMB) operands. */
6563 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6564 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6565 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6567 OP_FIRST_OPTIONAL
= OP_oI7b
6570 /* Generic instruction operand parser. This does no encoding and no
6571 semantic validation; it merely squirrels values away in the inst
6572 structure. Returns SUCCESS or FAIL depending on whether the
6573 specified grammar matched. */
6575 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6577 unsigned const int *upat
= pattern
;
6578 char *backtrack_pos
= 0;
6579 const char *backtrack_error
= 0;
6580 int i
, val
= 0, backtrack_index
= 0;
6581 enum arm_reg_type rtype
;
6582 parse_operand_result result
;
6583 unsigned int op_parse_code
;
6585 #define po_char_or_fail(chr) \
6588 if (skip_past_char (&str, chr) == FAIL) \
6593 #define po_reg_or_fail(regtype) \
6596 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6597 & inst.operands[i].vectype); \
6600 first_error (_(reg_expected_msgs[regtype])); \
6603 inst.operands[i].reg = val; \
6604 inst.operands[i].isreg = 1; \
6605 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6606 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6607 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6608 || rtype == REG_TYPE_VFD \
6609 || rtype == REG_TYPE_NQ); \
6613 #define po_reg_or_goto(regtype, label) \
6616 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6617 & inst.operands[i].vectype); \
6621 inst.operands[i].reg = val; \
6622 inst.operands[i].isreg = 1; \
6623 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6624 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6625 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6626 || rtype == REG_TYPE_VFD \
6627 || rtype == REG_TYPE_NQ); \
6631 #define po_imm_or_fail(min, max, popt) \
6634 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6636 inst.operands[i].imm = val; \
6640 #define po_scalar_or_goto(elsz, label) \
6643 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6646 inst.operands[i].reg = val; \
6647 inst.operands[i].isscalar = 1; \
6651 #define po_misc_or_fail(expr) \
6659 #define po_misc_or_fail_no_backtrack(expr) \
6663 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6664 backtrack_pos = 0; \
6665 if (result != PARSE_OPERAND_SUCCESS) \
6670 #define po_barrier_or_imm(str) \
6673 val = parse_barrier (&str); \
6674 if (val == FAIL && ! ISALPHA (*str)) \
6677 /* ISB can only take SY as an option. */ \
6678 || ((inst.instruction & 0xf0) == 0x60 \
6681 inst.error = _("invalid barrier type"); \
6682 backtrack_pos = 0; \
6688 skip_whitespace (str
);
6690 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6692 op_parse_code
= upat
[i
];
6693 if (op_parse_code
>= 1<<16)
6694 op_parse_code
= thumb
? (op_parse_code
>> 16)
6695 : (op_parse_code
& ((1<<16)-1));
6697 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6699 /* Remember where we are in case we need to backtrack. */
6700 gas_assert (!backtrack_pos
);
6701 backtrack_pos
= str
;
6702 backtrack_error
= inst
.error
;
6703 backtrack_index
= i
;
6706 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6707 po_char_or_fail (',');
6709 switch (op_parse_code
)
6717 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6718 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6719 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6720 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6721 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6722 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6724 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6726 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6728 /* Also accept generic coprocessor regs for unknown registers. */
6730 po_reg_or_fail (REG_TYPE_CN
);
6732 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6733 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6734 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6735 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6736 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6737 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6738 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6739 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6740 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6741 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6743 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6745 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6746 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6748 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6750 /* Neon scalar. Using an element size of 8 means that some invalid
6751 scalars are accepted here, so deal with those in later code. */
6752 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6756 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6759 po_imm_or_fail (0, 0, TRUE
);
6764 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6769 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6772 if (parse_ifimm_zero (&str
))
6773 inst
.operands
[i
].imm
= 0;
6777 = _("only floating point zero is allowed as immediate value");
6785 po_scalar_or_goto (8, try_rr
);
6788 po_reg_or_fail (REG_TYPE_RN
);
6794 po_scalar_or_goto (8, try_nsdq
);
6797 po_reg_or_fail (REG_TYPE_NSDQ
);
6803 po_scalar_or_goto (8, try_ndq
);
6806 po_reg_or_fail (REG_TYPE_NDQ
);
6812 po_scalar_or_goto (8, try_vfd
);
6815 po_reg_or_fail (REG_TYPE_VFD
);
6820 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6821 not careful then bad things might happen. */
6822 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6827 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6830 /* There's a possibility of getting a 64-bit immediate here, so
6831 we need special handling. */
6832 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6835 inst
.error
= _("immediate value is out of range");
6843 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6846 po_imm_or_fail (0, 63, TRUE
);
6851 po_char_or_fail ('[');
6852 po_reg_or_fail (REG_TYPE_RN
);
6853 po_char_or_fail (']');
6859 po_reg_or_fail (REG_TYPE_RN
);
6860 if (skip_past_char (&str
, '!') == SUCCESS
)
6861 inst
.operands
[i
].writeback
= 1;
6865 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6866 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6867 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6868 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6869 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6870 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6871 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6872 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6873 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6874 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6875 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6876 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6878 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6880 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6881 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6883 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6884 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6885 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6886 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6888 /* Immediate variants */
6890 po_char_or_fail ('{');
6891 po_imm_or_fail (0, 255, TRUE
);
6892 po_char_or_fail ('}');
6896 /* The expression parser chokes on a trailing !, so we have
6897 to find it first and zap it. */
6900 while (*s
&& *s
!= ',')
6905 inst
.operands
[i
].writeback
= 1;
6907 po_imm_or_fail (0, 31, TRUE
);
6915 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6920 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6925 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6927 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6929 val
= parse_reloc (&str
);
6932 inst
.error
= _("unrecognized relocation suffix");
6935 else if (val
!= BFD_RELOC_UNUSED
)
6937 inst
.operands
[i
].imm
= val
;
6938 inst
.operands
[i
].hasreloc
= 1;
6943 /* Operand for MOVW or MOVT. */
6945 po_misc_or_fail (parse_half (&str
));
6948 /* Register or expression. */
6949 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6950 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6952 /* Register or immediate. */
6953 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6954 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6956 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6958 if (!is_immediate_prefix (*str
))
6961 val
= parse_fpa_immediate (&str
);
6964 /* FPA immediates are encoded as registers 8-15.
6965 parse_fpa_immediate has already applied the offset. */
6966 inst
.operands
[i
].reg
= val
;
6967 inst
.operands
[i
].isreg
= 1;
6970 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6971 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6973 /* Two kinds of register. */
6976 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6978 || (rege
->type
!= REG_TYPE_MMXWR
6979 && rege
->type
!= REG_TYPE_MMXWC
6980 && rege
->type
!= REG_TYPE_MMXWCG
))
6982 inst
.error
= _("iWMMXt data or control register expected");
6985 inst
.operands
[i
].reg
= rege
->number
;
6986 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6992 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6994 || (rege
->type
!= REG_TYPE_MMXWC
6995 && rege
->type
!= REG_TYPE_MMXWCG
))
6997 inst
.error
= _("iWMMXt control register expected");
7000 inst
.operands
[i
].reg
= rege
->number
;
7001 inst
.operands
[i
].isreg
= 1;
7006 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7007 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7008 case OP_oROR
: val
= parse_ror (&str
); break;
7009 case OP_COND
: val
= parse_cond (&str
); break;
7010 case OP_oBARRIER_I15
:
7011 po_barrier_or_imm (str
); break;
7013 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7019 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7020 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7022 inst
.error
= _("Banked registers are not available with this "
7028 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7032 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7035 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7037 if (strncasecmp (str
, "APSR_", 5) == 0)
7044 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7045 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7046 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7047 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7048 default: found
= 16;
7052 inst
.operands
[i
].isvec
= 1;
7053 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7054 inst
.operands
[i
].reg
= REG_PC
;
7061 po_misc_or_fail (parse_tb (&str
));
7064 /* Register lists. */
7066 val
= parse_reg_list (&str
);
7069 inst
.operands
[i
].writeback
= 1;
7075 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7079 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7083 /* Allow Q registers too. */
7084 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7089 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7091 inst
.operands
[i
].issingle
= 1;
7096 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7101 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7102 &inst
.operands
[i
].vectype
);
7105 /* Addressing modes */
7107 po_misc_or_fail (parse_address (&str
, i
));
7111 po_misc_or_fail_no_backtrack (
7112 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7116 po_misc_or_fail_no_backtrack (
7117 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7121 po_misc_or_fail_no_backtrack (
7122 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7126 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7130 po_misc_or_fail_no_backtrack (
7131 parse_shifter_operand_group_reloc (&str
, i
));
7135 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7139 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7143 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7147 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7150 /* Various value-based sanity checks and shared operations. We
7151 do not signal immediate failures for the register constraints;
7152 this allows a syntax error to take precedence. */
7153 switch (op_parse_code
)
7161 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7162 inst
.error
= BAD_PC
;
7167 if (inst
.operands
[i
].isreg
)
7169 if (inst
.operands
[i
].reg
== REG_PC
)
7170 inst
.error
= BAD_PC
;
7171 else if (inst
.operands
[i
].reg
== REG_SP
)
7172 inst
.error
= BAD_SP
;
7177 if (inst
.operands
[i
].isreg
7178 && inst
.operands
[i
].reg
== REG_PC
7179 && (inst
.operands
[i
].writeback
|| thumb
))
7180 inst
.error
= BAD_PC
;
7189 case OP_oBARRIER_I15
:
7198 inst
.operands
[i
].imm
= val
;
7205 /* If we get here, this operand was successfully parsed. */
7206 inst
.operands
[i
].present
= 1;
7210 inst
.error
= BAD_ARGS
;
7215 /* The parse routine should already have set inst.error, but set a
7216 default here just in case. */
7218 inst
.error
= _("syntax error");
7222 /* Do not backtrack over a trailing optional argument that
7223 absorbed some text. We will only fail again, with the
7224 'garbage following instruction' error message, which is
7225 probably less helpful than the current one. */
7226 if (backtrack_index
== i
&& backtrack_pos
!= str
7227 && upat
[i
+1] == OP_stop
)
7230 inst
.error
= _("syntax error");
7234 /* Try again, skipping the optional argument at backtrack_pos. */
7235 str
= backtrack_pos
;
7236 inst
.error
= backtrack_error
;
7237 inst
.operands
[backtrack_index
].present
= 0;
7238 i
= backtrack_index
;
7242 /* Check that we have parsed all the arguments. */
7243 if (*str
!= '\0' && !inst
.error
)
7244 inst
.error
= _("garbage following instruction");
7246 return inst
.error
? FAIL
: SUCCESS
;
7249 #undef po_char_or_fail
7250 #undef po_reg_or_fail
7251 #undef po_reg_or_goto
7252 #undef po_imm_or_fail
7253 #undef po_scalar_or_fail
7254 #undef po_barrier_or_imm
7256 /* Shorthand macro for instruction encoding functions issuing errors. */
7257 #define constraint(expr, err) \
7268 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7269 instructions are unpredictable if these registers are used. This
7270 is the BadReg predicate in ARM's Thumb-2 documentation. */
7271 #define reject_bad_reg(reg) \
7273 if (reg == REG_SP || reg == REG_PC) \
7275 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7280 /* If REG is R13 (the stack pointer), warn that its use is
7282 #define warn_deprecated_sp(reg) \
7284 if (warn_on_deprecated && reg == REG_SP) \
7285 as_tsktsk (_("use of r13 is deprecated")); \
7288 /* Functions for operand encoding. ARM, then Thumb. */
7290 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7292 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7294 The only binary encoding difference is the Coprocessor number. Coprocessor
7295 9 is used for half-precision calculations or conversions. The format of the
7296 instruction is the same as the equivalent Coprocessor 10 instuction that
7297 exists for Single-Precision operation. */
7300 do_scalar_fp16_v82_encode (void)
7302 if (inst
.cond
!= COND_ALWAYS
)
7303 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7304 " the behaviour is UNPREDICTABLE"));
7305 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7308 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7309 mark_feature_used (&arm_ext_fp16
);
7312 /* If VAL can be encoded in the immediate field of an ARM instruction,
7313 return the encoded form. Otherwise, return FAIL. */
7316 encode_arm_immediate (unsigned int val
)
7323 for (i
= 2; i
< 32; i
+= 2)
7324 if ((a
= rotate_left (val
, i
)) <= 0xff)
7325 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7330 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7331 return the encoded form. Otherwise, return FAIL. */
7333 encode_thumb32_immediate (unsigned int val
)
7340 for (i
= 1; i
<= 24; i
++)
7343 if ((val
& ~(0xff << i
)) == 0)
7344 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7348 if (val
== ((a
<< 16) | a
))
7350 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7354 if (val
== ((a
<< 16) | a
))
7355 return 0x200 | (a
>> 8);
7359 /* Encode a VFP SP or DP register number into inst.instruction. */
7362 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7364 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7367 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7370 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7373 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7378 first_error (_("D register out of range for selected VFP version"));
7386 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7390 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7394 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7398 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7402 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7406 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7414 /* Encode a <shift> in an ARM-format instruction. The immediate,
7415 if any, is handled by md_apply_fix. */
7417 encode_arm_shift (int i
)
7419 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7420 inst
.instruction
|= SHIFT_ROR
<< 5;
7423 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7424 if (inst
.operands
[i
].immisreg
)
7426 inst
.instruction
|= SHIFT_BY_REG
;
7427 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7430 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7435 encode_arm_shifter_operand (int i
)
7437 if (inst
.operands
[i
].isreg
)
7439 inst
.instruction
|= inst
.operands
[i
].reg
;
7440 encode_arm_shift (i
);
7444 inst
.instruction
|= INST_IMMEDIATE
;
7445 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7446 inst
.instruction
|= inst
.operands
[i
].imm
;
7450 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7452 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7455 Generate an error if the operand is not a register. */
7456 constraint (!inst
.operands
[i
].isreg
,
7457 _("Instruction does not support =N addresses"));
7459 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7461 if (inst
.operands
[i
].preind
)
7465 inst
.error
= _("instruction does not accept preindexed addressing");
7468 inst
.instruction
|= PRE_INDEX
;
7469 if (inst
.operands
[i
].writeback
)
7470 inst
.instruction
|= WRITE_BACK
;
7473 else if (inst
.operands
[i
].postind
)
7475 gas_assert (inst
.operands
[i
].writeback
);
7477 inst
.instruction
|= WRITE_BACK
;
7479 else /* unindexed - only for coprocessor */
7481 inst
.error
= _("instruction does not accept unindexed addressing");
7485 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7486 && (((inst
.instruction
& 0x000f0000) >> 16)
7487 == ((inst
.instruction
& 0x0000f000) >> 12)))
7488 as_warn ((inst
.instruction
& LOAD_BIT
)
7489 ? _("destination register same as write-back base")
7490 : _("source register same as write-back base"));
7493 /* inst.operands[i] was set up by parse_address. Encode it into an
7494 ARM-format mode 2 load or store instruction. If is_t is true,
7495 reject forms that cannot be used with a T instruction (i.e. not
7498 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7500 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7502 encode_arm_addr_mode_common (i
, is_t
);
7504 if (inst
.operands
[i
].immisreg
)
7506 constraint ((inst
.operands
[i
].imm
== REG_PC
7507 || (is_pc
&& inst
.operands
[i
].writeback
)),
7509 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7510 inst
.instruction
|= inst
.operands
[i
].imm
;
7511 if (!inst
.operands
[i
].negative
)
7512 inst
.instruction
|= INDEX_UP
;
7513 if (inst
.operands
[i
].shifted
)
7515 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7516 inst
.instruction
|= SHIFT_ROR
<< 5;
7519 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7520 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7524 else /* immediate offset in inst.reloc */
7526 if (is_pc
&& !inst
.reloc
.pc_rel
)
7528 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7530 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7531 cannot use PC in addressing.
7532 PC cannot be used in writeback addressing, either. */
7533 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7536 /* Use of PC in str is deprecated for ARMv7. */
7537 if (warn_on_deprecated
7539 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7540 as_tsktsk (_("use of PC in this instruction is deprecated"));
7543 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7545 /* Prefer + for zero encoded value. */
7546 if (!inst
.operands
[i
].negative
)
7547 inst
.instruction
|= INDEX_UP
;
7548 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7553 /* inst.operands[i] was set up by parse_address. Encode it into an
7554 ARM-format mode 3 load or store instruction. Reject forms that
7555 cannot be used with such instructions. If is_t is true, reject
7556 forms that cannot be used with a T instruction (i.e. not
7559 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7561 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7563 inst
.error
= _("instruction does not accept scaled register index");
7567 encode_arm_addr_mode_common (i
, is_t
);
7569 if (inst
.operands
[i
].immisreg
)
7571 constraint ((inst
.operands
[i
].imm
== REG_PC
7572 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7574 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7576 inst
.instruction
|= inst
.operands
[i
].imm
;
7577 if (!inst
.operands
[i
].negative
)
7578 inst
.instruction
|= INDEX_UP
;
7580 else /* immediate offset in inst.reloc */
7582 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7583 && inst
.operands
[i
].writeback
),
7585 inst
.instruction
|= HWOFFSET_IMM
;
7586 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7588 /* Prefer + for zero encoded value. */
7589 if (!inst
.operands
[i
].negative
)
7590 inst
.instruction
|= INDEX_UP
;
7592 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7597 /* Write immediate bits [7:0] to the following locations:
7599 |28/24|23 19|18 16|15 4|3 0|
7600 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7602 This function is used by VMOV/VMVN/VORR/VBIC. */
7605 neon_write_immbits (unsigned immbits
)
7607 inst
.instruction
|= immbits
& 0xf;
7608 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7609 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7612 /* Invert low-order SIZE bits of XHI:XLO. */
7615 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7617 unsigned immlo
= xlo
? *xlo
: 0;
7618 unsigned immhi
= xhi
? *xhi
: 0;
7623 immlo
= (~immlo
) & 0xff;
7627 immlo
= (~immlo
) & 0xffff;
7631 immhi
= (~immhi
) & 0xffffffff;
7635 immlo
= (~immlo
) & 0xffffffff;
7649 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7653 neon_bits_same_in_bytes (unsigned imm
)
7655 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7656 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7657 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7658 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7661 /* For immediate of above form, return 0bABCD. */
7664 neon_squash_bits (unsigned imm
)
7666 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7667 | ((imm
& 0x01000000) >> 21);
7670 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7673 neon_qfloat_bits (unsigned imm
)
7675 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7678 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7679 the instruction. *OP is passed as the initial value of the op field, and
7680 may be set to a different value depending on the constant (i.e.
7681 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7682 MVN). If the immediate looks like a repeated pattern then also
7683 try smaller element sizes. */
7686 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7687 unsigned *immbits
, int *op
, int size
,
7688 enum neon_el_type type
)
7690 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7692 if (type
== NT_float
&& !float_p
)
7695 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7697 if (size
!= 32 || *op
== 1)
7699 *immbits
= neon_qfloat_bits (immlo
);
7705 if (neon_bits_same_in_bytes (immhi
)
7706 && neon_bits_same_in_bytes (immlo
))
7710 *immbits
= (neon_squash_bits (immhi
) << 4)
7711 | neon_squash_bits (immlo
);
7722 if (immlo
== (immlo
& 0x000000ff))
7727 else if (immlo
== (immlo
& 0x0000ff00))
7729 *immbits
= immlo
>> 8;
7732 else if (immlo
== (immlo
& 0x00ff0000))
7734 *immbits
= immlo
>> 16;
7737 else if (immlo
== (immlo
& 0xff000000))
7739 *immbits
= immlo
>> 24;
7742 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7744 *immbits
= (immlo
>> 8) & 0xff;
7747 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7749 *immbits
= (immlo
>> 16) & 0xff;
7753 if ((immlo
& 0xffff) != (immlo
>> 16))
7760 if (immlo
== (immlo
& 0x000000ff))
7765 else if (immlo
== (immlo
& 0x0000ff00))
7767 *immbits
= immlo
>> 8;
7771 if ((immlo
& 0xff) != (immlo
>> 8))
7776 if (immlo
== (immlo
& 0x000000ff))
7778 /* Don't allow MVN with 8-bit immediate. */
7788 #if defined BFD_HOST_64_BIT
7789 /* Returns TRUE if double precision value V may be cast
7790 to single precision without loss of accuracy. */
7793 is_double_a_single (bfd_int64_t v
)
7795 int exp
= (int)((v
>> 52) & 0x7FF);
7796 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7798 return (exp
== 0 || exp
== 0x7FF
7799 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7800 && (mantissa
& 0x1FFFFFFFl
) == 0;
7803 /* Returns a double precision value casted to single precision
7804 (ignoring the least significant bits in exponent and mantissa). */
7807 double_to_single (bfd_int64_t v
)
7809 int sign
= (int) ((v
>> 63) & 1l);
7810 int exp
= (int) ((v
>> 52) & 0x7FF);
7811 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7817 exp
= exp
- 1023 + 127;
7826 /* No denormalized numbers. */
7832 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7834 #endif /* BFD_HOST_64_BIT */
7843 static void do_vfp_nsyn_opcode (const char *);
7845 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7846 Determine whether it can be performed with a move instruction; if
7847 it can, convert inst.instruction to that move instruction and
7848 return TRUE; if it can't, convert inst.instruction to a literal-pool
7849 load and return FALSE. If this is not a valid thing to do in the
7850 current context, set inst.error and return TRUE.
7852 inst.operands[i] describes the destination register. */
7855 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7858 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7859 bfd_boolean arm_p
= (t
== CONST_ARM
);
7862 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7866 if ((inst
.instruction
& tbit
) == 0)
7868 inst
.error
= _("invalid pseudo operation");
7872 if (inst
.reloc
.exp
.X_op
!= O_constant
7873 && inst
.reloc
.exp
.X_op
!= O_symbol
7874 && inst
.reloc
.exp
.X_op
!= O_big
)
7876 inst
.error
= _("constant expression expected");
7880 if (inst
.reloc
.exp
.X_op
== O_constant
7881 || inst
.reloc
.exp
.X_op
== O_big
)
7883 #if defined BFD_HOST_64_BIT
7888 if (inst
.reloc
.exp
.X_op
== O_big
)
7890 LITTLENUM_TYPE w
[X_PRECISION
];
7893 if (inst
.reloc
.exp
.X_add_number
== -1)
7895 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7897 /* FIXME: Should we check words w[2..5] ? */
7902 #if defined BFD_HOST_64_BIT
7904 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7905 << LITTLENUM_NUMBER_OF_BITS
)
7906 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7907 << LITTLENUM_NUMBER_OF_BITS
)
7908 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7909 << LITTLENUM_NUMBER_OF_BITS
)
7910 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7912 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7913 | (l
[0] & LITTLENUM_MASK
);
7917 v
= inst
.reloc
.exp
.X_add_number
;
7919 if (!inst
.operands
[i
].issingle
)
7923 /* This can be encoded only for a low register. */
7924 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7926 /* This can be done with a mov(1) instruction. */
7927 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7928 inst
.instruction
|= v
;
7932 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7933 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7935 /* Check if on thumb2 it can be done with a mov.w, mvn or
7936 movw instruction. */
7937 unsigned int newimm
;
7938 bfd_boolean isNegated
;
7940 newimm
= encode_thumb32_immediate (v
);
7941 if (newimm
!= (unsigned int) FAIL
)
7945 newimm
= encode_thumb32_immediate (~v
);
7946 if (newimm
!= (unsigned int) FAIL
)
7950 /* The number can be loaded with a mov.w or mvn
7952 if (newimm
!= (unsigned int) FAIL
7953 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7955 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7956 | (inst
.operands
[i
].reg
<< 8));
7957 /* Change to MOVN. */
7958 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7959 inst
.instruction
|= (newimm
& 0x800) << 15;
7960 inst
.instruction
|= (newimm
& 0x700) << 4;
7961 inst
.instruction
|= (newimm
& 0x0ff);
7964 /* The number can be loaded with a movw instruction. */
7965 else if ((v
& ~0xFFFF) == 0
7966 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7968 int imm
= v
& 0xFFFF;
7970 inst
.instruction
= 0xf2400000; /* MOVW. */
7971 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7972 inst
.instruction
|= (imm
& 0xf000) << 4;
7973 inst
.instruction
|= (imm
& 0x0800) << 15;
7974 inst
.instruction
|= (imm
& 0x0700) << 4;
7975 inst
.instruction
|= (imm
& 0x00ff);
7982 int value
= encode_arm_immediate (v
);
7986 /* This can be done with a mov instruction. */
7987 inst
.instruction
&= LITERAL_MASK
;
7988 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7989 inst
.instruction
|= value
& 0xfff;
7993 value
= encode_arm_immediate (~ v
);
7996 /* This can be done with a mvn instruction. */
7997 inst
.instruction
&= LITERAL_MASK
;
7998 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7999 inst
.instruction
|= value
& 0xfff;
8003 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8006 unsigned immbits
= 0;
8007 unsigned immlo
= inst
.operands
[1].imm
;
8008 unsigned immhi
= inst
.operands
[1].regisimm
8009 ? inst
.operands
[1].reg
8010 : inst
.reloc
.exp
.X_unsigned
8012 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8013 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8014 &op
, 64, NT_invtype
);
8018 neon_invert_size (&immlo
, &immhi
, 64);
8020 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8021 &op
, 64, NT_invtype
);
8026 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8032 /* Fill other bits in vmov encoding for both thumb and arm. */
8034 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8036 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8037 neon_write_immbits (immbits
);
8045 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8046 if (inst
.operands
[i
].issingle
8047 && is_quarter_float (inst
.operands
[1].imm
)
8048 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8050 inst
.operands
[1].imm
=
8051 neon_qfloat_bits (v
);
8052 do_vfp_nsyn_opcode ("fconsts");
8056 /* If our host does not support a 64-bit type then we cannot perform
8057 the following optimization. This mean that there will be a
8058 discrepancy between the output produced by an assembler built for
8059 a 32-bit-only host and the output produced from a 64-bit host, but
8060 this cannot be helped. */
8061 #if defined BFD_HOST_64_BIT
8062 else if (!inst
.operands
[1].issingle
8063 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8065 if (is_double_a_single (v
)
8066 && is_quarter_float (double_to_single (v
)))
8068 inst
.operands
[1].imm
=
8069 neon_qfloat_bits (double_to_single (v
));
8070 do_vfp_nsyn_opcode ("fconstd");
8078 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8079 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8082 inst
.operands
[1].reg
= REG_PC
;
8083 inst
.operands
[1].isreg
= 1;
8084 inst
.operands
[1].preind
= 1;
8085 inst
.reloc
.pc_rel
= 1;
8086 inst
.reloc
.type
= (thumb_p
8087 ? BFD_RELOC_ARM_THUMB_OFFSET
8089 ? BFD_RELOC_ARM_HWLITERAL
8090 : BFD_RELOC_ARM_LITERAL
));
8094 /* inst.operands[i] was set up by parse_address. Encode it into an
8095 ARM-format instruction. Reject all forms which cannot be encoded
8096 into a coprocessor load/store instruction. If wb_ok is false,
8097 reject use of writeback; if unind_ok is false, reject use of
8098 unindexed addressing. If reloc_override is not 0, use it instead
8099 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8100 (in which case it is preserved). */
8103 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8105 if (!inst
.operands
[i
].isreg
)
8108 if (! inst
.operands
[0].isvec
)
8110 inst
.error
= _("invalid co-processor operand");
8113 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8117 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8119 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8121 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8123 gas_assert (!inst
.operands
[i
].writeback
);
8126 inst
.error
= _("instruction does not support unindexed addressing");
8129 inst
.instruction
|= inst
.operands
[i
].imm
;
8130 inst
.instruction
|= INDEX_UP
;
8134 if (inst
.operands
[i
].preind
)
8135 inst
.instruction
|= PRE_INDEX
;
8137 if (inst
.operands
[i
].writeback
)
8139 if (inst
.operands
[i
].reg
== REG_PC
)
8141 inst
.error
= _("pc may not be used with write-back");
8146 inst
.error
= _("instruction does not support writeback");
8149 inst
.instruction
|= WRITE_BACK
;
8153 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8154 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8155 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8156 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8159 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8161 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8164 /* Prefer + for zero encoded value. */
8165 if (!inst
.operands
[i
].negative
)
8166 inst
.instruction
|= INDEX_UP
;
8171 /* Functions for instruction encoding, sorted by sub-architecture.
8172 First some generics; their names are taken from the conventional
8173 bit positions for register arguments in ARM format instructions. */
8183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8189 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8195 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8196 inst
.instruction
|= inst
.operands
[1].reg
;
8202 inst
.instruction
|= inst
.operands
[0].reg
;
8203 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8210 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8216 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8217 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8223 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8224 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8228 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8230 if (ARM_CPU_IS_ANY (cpu_variant
))
8232 as_tsktsk ("%s", msg
);
8235 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8247 unsigned Rn
= inst
.operands
[2].reg
;
8248 /* Enforce restrictions on SWP instruction. */
8249 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8251 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8252 _("Rn must not overlap other operands"));
8254 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8256 if (!check_obsolete (&arm_ext_v8
,
8257 _("swp{b} use is obsoleted for ARMv8 and later"))
8258 && warn_on_deprecated
8259 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8260 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8264 inst
.instruction
|= inst
.operands
[1].reg
;
8265 inst
.instruction
|= Rn
<< 16;
8271 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8272 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8273 inst
.instruction
|= inst
.operands
[2].reg
;
8279 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8280 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8281 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8282 || inst
.reloc
.exp
.X_add_number
!= 0),
8284 inst
.instruction
|= inst
.operands
[0].reg
;
8285 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8286 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8292 inst
.instruction
|= inst
.operands
[0].imm
;
8298 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8299 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8302 /* ARM instructions, in alphabetical order by function name (except
8303 that wrapper functions appear immediately after the function they
8306 /* This is a pseudo-op of the form "adr rd, label" to be converted
8307 into a relative address of the form "add rd, pc, #label-.-8". */
8312 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8314 /* Frag hacking will turn this into a sub instruction if the offset turns
8315 out to be negative. */
8316 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8317 inst
.reloc
.pc_rel
= 1;
8318 inst
.reloc
.exp
.X_add_number
-= 8;
8321 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8322 into a relative address of the form:
8323 add rd, pc, #low(label-.-8)"
8324 add rd, rd, #high(label-.-8)" */
8329 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8331 /* Frag hacking will turn this into a sub instruction if the offset turns
8332 out to be negative. */
8333 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8334 inst
.reloc
.pc_rel
= 1;
8335 inst
.size
= INSN_SIZE
* 2;
8336 inst
.reloc
.exp
.X_add_number
-= 8;
8342 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8343 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8345 if (!inst
.operands
[1].present
)
8346 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8347 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8348 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8349 encode_arm_shifter_operand (2);
8355 if (inst
.operands
[0].present
)
8356 inst
.instruction
|= inst
.operands
[0].imm
;
8358 inst
.instruction
|= 0xf;
8364 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8365 constraint (msb
> 32, _("bit-field extends past end of register"));
8366 /* The instruction encoding stores the LSB and MSB,
8367 not the LSB and width. */
8368 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8369 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8370 inst
.instruction
|= (msb
- 1) << 16;
8378 /* #0 in second position is alternative syntax for bfc, which is
8379 the same instruction but with REG_PC in the Rm field. */
8380 if (!inst
.operands
[1].isreg
)
8381 inst
.operands
[1].reg
= REG_PC
;
8383 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8384 constraint (msb
> 32, _("bit-field extends past end of register"));
8385 /* The instruction encoding stores the LSB and MSB,
8386 not the LSB and width. */
8387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8388 inst
.instruction
|= inst
.operands
[1].reg
;
8389 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8390 inst
.instruction
|= (msb
- 1) << 16;
8396 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8397 _("bit-field extends past end of register"));
8398 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8399 inst
.instruction
|= inst
.operands
[1].reg
;
8400 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8401 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8404 /* ARM V5 breakpoint instruction (argument parse)
8405 BKPT <16 bit unsigned immediate>
8406 Instruction is not conditional.
8407 The bit pattern given in insns[] has the COND_ALWAYS condition,
8408 and it is an error if the caller tried to override that. */
8413 /* Top 12 of 16 bits to bits 19:8. */
8414 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8416 /* Bottom 4 of 16 bits to bits 3:0. */
8417 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8421 encode_branch (int default_reloc
)
8423 if (inst
.operands
[0].hasreloc
)
8425 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8426 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8427 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8428 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8429 ? BFD_RELOC_ARM_PLT32
8430 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8433 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8434 inst
.reloc
.pc_rel
= 1;
8441 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8442 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8445 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8452 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8454 if (inst
.cond
== COND_ALWAYS
)
8455 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8457 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8461 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8464 /* ARM V5 branch-link-exchange instruction (argument parse)
8465 BLX <target_addr> ie BLX(1)
8466 BLX{<condition>} <Rm> ie BLX(2)
8467 Unfortunately, there are two different opcodes for this mnemonic.
8468 So, the insns[].value is not used, and the code here zaps values
8469 into inst.instruction.
8470 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8475 if (inst
.operands
[0].isreg
)
8477 /* Arg is a register; the opcode provided by insns[] is correct.
8478 It is not illegal to do "blx pc", just useless. */
8479 if (inst
.operands
[0].reg
== REG_PC
)
8480 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8482 inst
.instruction
|= inst
.operands
[0].reg
;
8486 /* Arg is an address; this instruction cannot be executed
8487 conditionally, and the opcode must be adjusted.
8488 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8489 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8490 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8491 inst
.instruction
= 0xfa000000;
8492 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8499 bfd_boolean want_reloc
;
8501 if (inst
.operands
[0].reg
== REG_PC
)
8502 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8504 inst
.instruction
|= inst
.operands
[0].reg
;
8505 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8506 it is for ARMv4t or earlier. */
8507 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8508 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8512 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8517 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8521 /* ARM v5TEJ. Jump to Jazelle code. */
8526 if (inst
.operands
[0].reg
== REG_PC
)
8527 as_tsktsk (_("use of r15 in bxj is not really useful"));
8529 inst
.instruction
|= inst
.operands
[0].reg
;
8532 /* Co-processor data operation:
8533 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8534 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8538 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8539 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8540 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8541 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8542 inst
.instruction
|= inst
.operands
[4].reg
;
8543 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8549 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8550 encode_arm_shifter_operand (1);
8553 /* Transfer between coprocessor and ARM registers.
8554 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8559 No special properties. */
8561 struct deprecated_coproc_regs_s
8568 arm_feature_set deprecated
;
8569 arm_feature_set obsoleted
;
8570 const char *dep_msg
;
8571 const char *obs_msg
;
8574 #define DEPR_ACCESS_V8 \
8575 N_("This coprocessor register access is deprecated in ARMv8")
8577 /* Table of all deprecated coprocessor registers. */
8578 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8580 {15, 0, 7, 10, 5, /* CP15DMB. */
8581 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8582 DEPR_ACCESS_V8
, NULL
},
8583 {15, 0, 7, 10, 4, /* CP15DSB. */
8584 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8585 DEPR_ACCESS_V8
, NULL
},
8586 {15, 0, 7, 5, 4, /* CP15ISB. */
8587 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8588 DEPR_ACCESS_V8
, NULL
},
8589 {14, 6, 1, 0, 0, /* TEEHBR. */
8590 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8591 DEPR_ACCESS_V8
, NULL
},
8592 {14, 6, 0, 0, 0, /* TEECR. */
8593 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8594 DEPR_ACCESS_V8
, NULL
},
8597 #undef DEPR_ACCESS_V8
8599 static const size_t deprecated_coproc_reg_count
=
8600 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8608 Rd
= inst
.operands
[2].reg
;
8611 if (inst
.instruction
== 0xee000010
8612 || inst
.instruction
== 0xfe000010)
8614 reject_bad_reg (Rd
);
8617 constraint (Rd
== REG_SP
, BAD_SP
);
8622 if (inst
.instruction
== 0xe000010)
8623 constraint (Rd
== REG_PC
, BAD_PC
);
8626 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8628 const struct deprecated_coproc_regs_s
*r
=
8629 deprecated_coproc_regs
+ i
;
8631 if (inst
.operands
[0].reg
== r
->cp
8632 && inst
.operands
[1].imm
== r
->opc1
8633 && inst
.operands
[3].reg
== r
->crn
8634 && inst
.operands
[4].reg
== r
->crm
8635 && inst
.operands
[5].imm
== r
->opc2
)
8637 if (! ARM_CPU_IS_ANY (cpu_variant
)
8638 && warn_on_deprecated
8639 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8640 as_tsktsk ("%s", r
->dep_msg
);
8644 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8645 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8646 inst
.instruction
|= Rd
<< 12;
8647 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8648 inst
.instruction
|= inst
.operands
[4].reg
;
8649 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8652 /* Transfer between coprocessor register and pair of ARM registers.
8653 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8658 Two XScale instructions are special cases of these:
8660 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8661 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8663 Result unpredictable if Rd or Rn is R15. */
8670 Rd
= inst
.operands
[2].reg
;
8671 Rn
= inst
.operands
[3].reg
;
8675 reject_bad_reg (Rd
);
8676 reject_bad_reg (Rn
);
8680 constraint (Rd
== REG_PC
, BAD_PC
);
8681 constraint (Rn
== REG_PC
, BAD_PC
);
8684 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8685 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8686 inst
.instruction
|= Rd
<< 12;
8687 inst
.instruction
|= Rn
<< 16;
8688 inst
.instruction
|= inst
.operands
[4].reg
;
8694 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8695 if (inst
.operands
[1].present
)
8697 inst
.instruction
|= CPSI_MMOD
;
8698 inst
.instruction
|= inst
.operands
[1].imm
;
8705 inst
.instruction
|= inst
.operands
[0].imm
;
8711 unsigned Rd
, Rn
, Rm
;
8713 Rd
= inst
.operands
[0].reg
;
8714 Rn
= (inst
.operands
[1].present
8715 ? inst
.operands
[1].reg
: Rd
);
8716 Rm
= inst
.operands
[2].reg
;
8718 constraint ((Rd
== REG_PC
), BAD_PC
);
8719 constraint ((Rn
== REG_PC
), BAD_PC
);
8720 constraint ((Rm
== REG_PC
), BAD_PC
);
8722 inst
.instruction
|= Rd
<< 16;
8723 inst
.instruction
|= Rn
<< 0;
8724 inst
.instruction
|= Rm
<< 8;
8730 /* There is no IT instruction in ARM mode. We
8731 process it to do the validation as if in
8732 thumb mode, just in case the code gets
8733 assembled for thumb using the unified syntax. */
8738 set_it_insn_type (IT_INSN
);
8739 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8740 now_it
.cc
= inst
.operands
[0].imm
;
8744 /* If there is only one register in the register list,
8745 then return its register number. Otherwise return -1. */
8747 only_one_reg_in_list (int range
)
8749 int i
= ffs (range
) - 1;
8750 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8754 encode_ldmstm(int from_push_pop_mnem
)
8756 int base_reg
= inst
.operands
[0].reg
;
8757 int range
= inst
.operands
[1].imm
;
8760 inst
.instruction
|= base_reg
<< 16;
8761 inst
.instruction
|= range
;
8763 if (inst
.operands
[1].writeback
)
8764 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8766 if (inst
.operands
[0].writeback
)
8768 inst
.instruction
|= WRITE_BACK
;
8769 /* Check for unpredictable uses of writeback. */
8770 if (inst
.instruction
& LOAD_BIT
)
8772 /* Not allowed in LDM type 2. */
8773 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8774 && ((range
& (1 << REG_PC
)) == 0))
8775 as_warn (_("writeback of base register is UNPREDICTABLE"));
8776 /* Only allowed if base reg not in list for other types. */
8777 else if (range
& (1 << base_reg
))
8778 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8782 /* Not allowed for type 2. */
8783 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8784 as_warn (_("writeback of base register is UNPREDICTABLE"));
8785 /* Only allowed if base reg not in list, or first in list. */
8786 else if ((range
& (1 << base_reg
))
8787 && (range
& ((1 << base_reg
) - 1)))
8788 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8792 /* If PUSH/POP has only one register, then use the A2 encoding. */
8793 one_reg
= only_one_reg_in_list (range
);
8794 if (from_push_pop_mnem
&& one_reg
>= 0)
8796 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8798 inst
.instruction
&= A_COND_MASK
;
8799 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8800 inst
.instruction
|= one_reg
<< 12;
8807 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8810 /* ARMv5TE load-consecutive (argument parse)
8819 constraint (inst
.operands
[0].reg
% 2 != 0,
8820 _("first transfer register must be even"));
8821 constraint (inst
.operands
[1].present
8822 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8823 _("can only transfer two consecutive registers"));
8824 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8825 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8827 if (!inst
.operands
[1].present
)
8828 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8830 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8831 register and the first register written; we have to diagnose
8832 overlap between the base and the second register written here. */
8834 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8835 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8836 as_warn (_("base register written back, and overlaps "
8837 "second transfer register"));
8839 if (!(inst
.instruction
& V4_STR_BIT
))
8841 /* For an index-register load, the index register must not overlap the
8842 destination (even if not write-back). */
8843 if (inst
.operands
[2].immisreg
8844 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8845 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8846 as_warn (_("index register overlaps transfer register"));
8848 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8849 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8855 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8856 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8857 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8858 || inst
.operands
[1].negative
8859 /* This can arise if the programmer has written
8861 or if they have mistakenly used a register name as the last
8864 It is very difficult to distinguish between these two cases
8865 because "rX" might actually be a label. ie the register
8866 name has been occluded by a symbol of the same name. So we
8867 just generate a general 'bad addressing mode' type error
8868 message and leave it up to the programmer to discover the
8869 true cause and fix their mistake. */
8870 || (inst
.operands
[1].reg
== REG_PC
),
8873 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8874 || inst
.reloc
.exp
.X_add_number
!= 0,
8875 _("offset must be zero in ARM encoding"));
8877 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8880 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8881 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8887 constraint (inst
.operands
[0].reg
% 2 != 0,
8888 _("even register required"));
8889 constraint (inst
.operands
[1].present
8890 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8891 _("can only load two consecutive registers"));
8892 /* If op 1 were present and equal to PC, this function wouldn't
8893 have been called in the first place. */
8894 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8897 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8900 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8901 which is not a multiple of four is UNPREDICTABLE. */
8903 check_ldr_r15_aligned (void)
8905 constraint (!(inst
.operands
[1].immisreg
)
8906 && (inst
.operands
[0].reg
== REG_PC
8907 && inst
.operands
[1].reg
== REG_PC
8908 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8909 _("ldr to register 15 must be 4-byte alligned"));
8915 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8916 if (!inst
.operands
[1].isreg
)
8917 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8919 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8920 check_ldr_r15_aligned ();
8926 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8928 if (inst
.operands
[1].preind
)
8930 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8931 || inst
.reloc
.exp
.X_add_number
!= 0,
8932 _("this instruction requires a post-indexed address"));
8934 inst
.operands
[1].preind
= 0;
8935 inst
.operands
[1].postind
= 1;
8936 inst
.operands
[1].writeback
= 1;
8938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8939 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8942 /* Halfword and signed-byte load/store operations. */
8947 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8948 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8949 if (!inst
.operands
[1].isreg
)
8950 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8952 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8958 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8960 if (inst
.operands
[1].preind
)
8962 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8963 || inst
.reloc
.exp
.X_add_number
!= 0,
8964 _("this instruction requires a post-indexed address"));
8966 inst
.operands
[1].preind
= 0;
8967 inst
.operands
[1].postind
= 1;
8968 inst
.operands
[1].writeback
= 1;
8970 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8971 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8974 /* Co-processor register load/store.
8975 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8979 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8980 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8981 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8987 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8988 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8989 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8990 && !(inst
.instruction
& 0x00400000))
8991 as_tsktsk (_("Rd and Rm should be different in mla"));
8993 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8994 inst
.instruction
|= inst
.operands
[1].reg
;
8995 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8996 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9002 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9003 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9005 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9006 encode_arm_shifter_operand (1);
9009 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9016 top
= (inst
.instruction
& 0x00400000) != 0;
9017 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9018 _(":lower16: not allowed this instruction"));
9019 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9020 _(":upper16: not allowed instruction"));
9021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9022 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9024 imm
= inst
.reloc
.exp
.X_add_number
;
9025 /* The value is in two pieces: 0:11, 16:19. */
9026 inst
.instruction
|= (imm
& 0x00000fff);
9027 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9032 do_vfp_nsyn_mrs (void)
9034 if (inst
.operands
[0].isvec
)
9036 if (inst
.operands
[1].reg
!= 1)
9037 first_error (_("operand 1 must be FPSCR"));
9038 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9039 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9040 do_vfp_nsyn_opcode ("fmstat");
9042 else if (inst
.operands
[1].isvec
)
9043 do_vfp_nsyn_opcode ("fmrx");
9051 do_vfp_nsyn_msr (void)
9053 if (inst
.operands
[0].isvec
)
9054 do_vfp_nsyn_opcode ("fmxr");
9064 unsigned Rt
= inst
.operands
[0].reg
;
9066 if (thumb_mode
&& Rt
== REG_SP
)
9068 inst
.error
= BAD_SP
;
9072 /* APSR_ sets isvec. All other refs to PC are illegal. */
9073 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9075 inst
.error
= BAD_PC
;
9079 /* If we get through parsing the register name, we just insert the number
9080 generated into the instruction without further validation. */
9081 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9082 inst
.instruction
|= (Rt
<< 12);
9088 unsigned Rt
= inst
.operands
[1].reg
;
9091 reject_bad_reg (Rt
);
9092 else if (Rt
== REG_PC
)
9094 inst
.error
= BAD_PC
;
9098 /* If we get through parsing the register name, we just insert the number
9099 generated into the instruction without further validation. */
9100 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9101 inst
.instruction
|= (Rt
<< 12);
9109 if (do_vfp_nsyn_mrs () == SUCCESS
)
9112 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9113 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9115 if (inst
.operands
[1].isreg
)
9117 br
= inst
.operands
[1].reg
;
9118 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9119 as_bad (_("bad register for mrs"));
9123 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9124 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9126 _("'APSR', 'CPSR' or 'SPSR' expected"));
9127 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9130 inst
.instruction
|= br
;
9133 /* Two possible forms:
9134 "{C|S}PSR_<field>, Rm",
9135 "{C|S}PSR_f, #expression". */
9140 if (do_vfp_nsyn_msr () == SUCCESS
)
9143 inst
.instruction
|= inst
.operands
[0].imm
;
9144 if (inst
.operands
[1].isreg
)
9145 inst
.instruction
|= inst
.operands
[1].reg
;
9148 inst
.instruction
|= INST_IMMEDIATE
;
9149 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9150 inst
.reloc
.pc_rel
= 0;
9157 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9159 if (!inst
.operands
[2].present
)
9160 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9161 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9162 inst
.instruction
|= inst
.operands
[1].reg
;
9163 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9165 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9166 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9167 as_tsktsk (_("Rd and Rm should be different in mul"));
9170 /* Long Multiply Parser
9171 UMULL RdLo, RdHi, Rm, Rs
9172 SMULL RdLo, RdHi, Rm, Rs
9173 UMLAL RdLo, RdHi, Rm, Rs
9174 SMLAL RdLo, RdHi, Rm, Rs. */
9179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9181 inst
.instruction
|= inst
.operands
[2].reg
;
9182 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9184 /* rdhi and rdlo must be different. */
9185 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9186 as_tsktsk (_("rdhi and rdlo must be different"));
9188 /* rdhi, rdlo and rm must all be different before armv6. */
9189 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9190 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9191 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9192 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9198 if (inst
.operands
[0].present
9199 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9201 /* Architectural NOP hints are CPSR sets with no bits selected. */
9202 inst
.instruction
&= 0xf0000000;
9203 inst
.instruction
|= 0x0320f000;
9204 if (inst
.operands
[0].present
)
9205 inst
.instruction
|= inst
.operands
[0].imm
;
9209 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9210 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9211 Condition defaults to COND_ALWAYS.
9212 Error if Rd, Rn or Rm are R15. */
9217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9218 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9219 inst
.instruction
|= inst
.operands
[2].reg
;
9220 if (inst
.operands
[3].present
)
9221 encode_arm_shift (3);
9224 /* ARM V6 PKHTB (Argument Parse). */
9229 if (!inst
.operands
[3].present
)
9231 /* If the shift specifier is omitted, turn the instruction
9232 into pkhbt rd, rm, rn. */
9233 inst
.instruction
&= 0xfff00010;
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9235 inst
.instruction
|= inst
.operands
[1].reg
;
9236 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9240 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9241 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9242 inst
.instruction
|= inst
.operands
[2].reg
;
9243 encode_arm_shift (3);
9247 /* ARMv5TE: Preload-Cache
9248 MP Extensions: Preload for write
9252 Syntactically, like LDR with B=1, W=0, L=1. */
9257 constraint (!inst
.operands
[0].isreg
,
9258 _("'[' expected after PLD mnemonic"));
9259 constraint (inst
.operands
[0].postind
,
9260 _("post-indexed expression used in preload instruction"));
9261 constraint (inst
.operands
[0].writeback
,
9262 _("writeback used in preload instruction"));
9263 constraint (!inst
.operands
[0].preind
,
9264 _("unindexed addressing used in preload instruction"));
9265 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9268 /* ARMv7: PLI <addr_mode> */
9272 constraint (!inst
.operands
[0].isreg
,
9273 _("'[' expected after PLI mnemonic"));
9274 constraint (inst
.operands
[0].postind
,
9275 _("post-indexed expression used in preload instruction"));
9276 constraint (inst
.operands
[0].writeback
,
9277 _("writeback used in preload instruction"));
9278 constraint (!inst
.operands
[0].preind
,
9279 _("unindexed addressing used in preload instruction"));
9280 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9281 inst
.instruction
&= ~PRE_INDEX
;
9287 constraint (inst
.operands
[0].writeback
,
9288 _("push/pop do not support {reglist}^"));
9289 inst
.operands
[1] = inst
.operands
[0];
9290 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9291 inst
.operands
[0].isreg
= 1;
9292 inst
.operands
[0].writeback
= 1;
9293 inst
.operands
[0].reg
= REG_SP
;
9294 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9297 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9298 word at the specified address and the following word
9300 Unconditionally executed.
9301 Error if Rn is R15. */
9306 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9307 if (inst
.operands
[0].writeback
)
9308 inst
.instruction
|= WRITE_BACK
;
9311 /* ARM V6 ssat (argument parse). */
9316 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9317 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9318 inst
.instruction
|= inst
.operands
[2].reg
;
9320 if (inst
.operands
[3].present
)
9321 encode_arm_shift (3);
9324 /* ARM V6 usat (argument parse). */
9329 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9330 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9331 inst
.instruction
|= inst
.operands
[2].reg
;
9333 if (inst
.operands
[3].present
)
9334 encode_arm_shift (3);
9337 /* ARM V6 ssat16 (argument parse). */
9342 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9343 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9344 inst
.instruction
|= inst
.operands
[2].reg
;
9350 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9351 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9352 inst
.instruction
|= inst
.operands
[2].reg
;
9355 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9356 preserving the other bits.
9358 setend <endian_specifier>, where <endian_specifier> is either
9364 if (warn_on_deprecated
9365 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9366 as_tsktsk (_("setend use is deprecated for ARMv8"));
9368 if (inst
.operands
[0].imm
)
9369 inst
.instruction
|= 0x200;
9375 unsigned int Rm
= (inst
.operands
[1].present
9376 ? inst
.operands
[1].reg
9377 : inst
.operands
[0].reg
);
9379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9380 inst
.instruction
|= Rm
;
9381 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9383 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9384 inst
.instruction
|= SHIFT_BY_REG
;
9385 /* PR 12854: Error on extraneous shifts. */
9386 constraint (inst
.operands
[2].shifted
,
9387 _("extraneous shift as part of operand to shift insn"));
9390 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9396 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9397 inst
.reloc
.pc_rel
= 0;
9403 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9404 inst
.reloc
.pc_rel
= 0;
9410 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9411 inst
.reloc
.pc_rel
= 0;
9417 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9418 _("selected processor does not support SETPAN instruction"));
9420 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9426 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9427 _("selected processor does not support SETPAN instruction"));
9429 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9432 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9433 SMLAxy{cond} Rd,Rm,Rs,Rn
9434 SMLAWy{cond} Rd,Rm,Rs,Rn
9435 Error if any register is R15. */
9440 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9441 inst
.instruction
|= inst
.operands
[1].reg
;
9442 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9443 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9446 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9447 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9448 Error if any register is R15.
9449 Warning if Rdlo == Rdhi. */
9454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9455 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9456 inst
.instruction
|= inst
.operands
[2].reg
;
9457 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9459 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9460 as_tsktsk (_("rdhi and rdlo must be different"));
9463 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9464 SMULxy{cond} Rd,Rm,Rs
9465 Error if any register is R15. */
9470 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9471 inst
.instruction
|= inst
.operands
[1].reg
;
9472 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9475 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9476 the same for both ARM and Thumb-2. */
9483 if (inst
.operands
[0].present
)
9485 reg
= inst
.operands
[0].reg
;
9486 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9491 inst
.instruction
|= reg
<< 16;
9492 inst
.instruction
|= inst
.operands
[1].imm
;
9493 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9494 inst
.instruction
|= WRITE_BACK
;
9497 /* ARM V6 strex (argument parse). */
9502 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9503 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9504 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9505 || inst
.operands
[2].negative
9506 /* See comment in do_ldrex(). */
9507 || (inst
.operands
[2].reg
== REG_PC
),
9510 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9511 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9513 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9514 || inst
.reloc
.exp
.X_add_number
!= 0,
9515 _("offset must be zero in ARM encoding"));
9517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9518 inst
.instruction
|= inst
.operands
[1].reg
;
9519 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9520 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9526 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9527 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9528 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9529 || inst
.operands
[2].negative
,
9532 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9533 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9541 constraint (inst
.operands
[1].reg
% 2 != 0,
9542 _("even register required"));
9543 constraint (inst
.operands
[2].present
9544 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9545 _("can only store two consecutive registers"));
9546 /* If op 2 were present and equal to PC, this function wouldn't
9547 have been called in the first place. */
9548 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9550 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9551 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9552 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9555 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9556 inst
.instruction
|= inst
.operands
[1].reg
;
9557 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9564 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9565 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9573 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9574 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9579 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9580 extends it to 32-bits, and adds the result to a value in another
9581 register. You can specify a rotation by 0, 8, 16, or 24 bits
9582 before extracting the 16-bit value.
9583 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9584 Condition defaults to COND_ALWAYS.
9585 Error if any register uses R15. */
9590 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9591 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9592 inst
.instruction
|= inst
.operands
[2].reg
;
9593 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9598 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9599 Condition defaults to COND_ALWAYS.
9600 Error if any register uses R15. */
9605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9606 inst
.instruction
|= inst
.operands
[1].reg
;
9607 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9610 /* VFP instructions. In a logical order: SP variant first, monad
9611 before dyad, arithmetic then move then load/store. */
9614 do_vfp_sp_monadic (void)
9616 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9617 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9621 do_vfp_sp_dyadic (void)
9623 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9624 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9625 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9629 do_vfp_sp_compare_z (void)
9631 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9635 do_vfp_dp_sp_cvt (void)
9637 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9638 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9642 do_vfp_sp_dp_cvt (void)
9644 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9645 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9649 do_vfp_reg_from_sp (void)
9651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9652 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9656 do_vfp_reg2_from_sp2 (void)
9658 constraint (inst
.operands
[2].imm
!= 2,
9659 _("only two consecutive VFP SP registers allowed here"));
9660 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9661 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9662 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9666 do_vfp_sp_from_reg (void)
9668 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9669 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9673 do_vfp_sp2_from_reg2 (void)
9675 constraint (inst
.operands
[0].imm
!= 2,
9676 _("only two consecutive VFP SP registers allowed here"));
9677 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9678 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9679 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9683 do_vfp_sp_ldst (void)
9685 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9686 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9690 do_vfp_dp_ldst (void)
9692 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9693 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9698 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9700 if (inst
.operands
[0].writeback
)
9701 inst
.instruction
|= WRITE_BACK
;
9703 constraint (ldstm_type
!= VFP_LDSTMIA
,
9704 _("this addressing mode requires base-register writeback"));
9705 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9706 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9707 inst
.instruction
|= inst
.operands
[1].imm
;
9711 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9715 if (inst
.operands
[0].writeback
)
9716 inst
.instruction
|= WRITE_BACK
;
9718 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9719 _("this addressing mode requires base-register writeback"));
9721 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9722 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9724 count
= inst
.operands
[1].imm
<< 1;
9725 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9728 inst
.instruction
|= count
;
9732 do_vfp_sp_ldstmia (void)
9734 vfp_sp_ldstm (VFP_LDSTMIA
);
9738 do_vfp_sp_ldstmdb (void)
9740 vfp_sp_ldstm (VFP_LDSTMDB
);
9744 do_vfp_dp_ldstmia (void)
9746 vfp_dp_ldstm (VFP_LDSTMIA
);
9750 do_vfp_dp_ldstmdb (void)
9752 vfp_dp_ldstm (VFP_LDSTMDB
);
9756 do_vfp_xp_ldstmia (void)
9758 vfp_dp_ldstm (VFP_LDSTMIAX
);
9762 do_vfp_xp_ldstmdb (void)
9764 vfp_dp_ldstm (VFP_LDSTMDBX
);
9768 do_vfp_dp_rd_rm (void)
9770 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9771 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9775 do_vfp_dp_rn_rd (void)
9777 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9778 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9782 do_vfp_dp_rd_rn (void)
9784 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9785 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9789 do_vfp_dp_rd_rn_rm (void)
9791 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9792 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9793 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9799 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9803 do_vfp_dp_rm_rd_rn (void)
9805 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9806 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9807 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9810 /* VFPv3 instructions. */
9812 do_vfp_sp_const (void)
9814 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9815 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9816 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9820 do_vfp_dp_const (void)
9822 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9823 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9824 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9828 vfp_conv (int srcsize
)
9830 int immbits
= srcsize
- inst
.operands
[1].imm
;
9832 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9834 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9835 i.e. immbits must be in range 0 - 16. */
9836 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9839 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9841 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9842 i.e. immbits must be in range 0 - 31. */
9843 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9847 inst
.instruction
|= (immbits
& 1) << 5;
9848 inst
.instruction
|= (immbits
>> 1);
9852 do_vfp_sp_conv_16 (void)
9854 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9859 do_vfp_dp_conv_16 (void)
9861 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9866 do_vfp_sp_conv_32 (void)
9868 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9873 do_vfp_dp_conv_32 (void)
9875 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9879 /* FPA instructions. Also in a logical order. */
9884 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9885 inst
.instruction
|= inst
.operands
[1].reg
;
9889 do_fpa_ldmstm (void)
9891 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9892 switch (inst
.operands
[1].imm
)
9894 case 1: inst
.instruction
|= CP_T_X
; break;
9895 case 2: inst
.instruction
|= CP_T_Y
; break;
9896 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9901 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9903 /* The instruction specified "ea" or "fd", so we can only accept
9904 [Rn]{!}. The instruction does not really support stacking or
9905 unstacking, so we have to emulate these by setting appropriate
9906 bits and offsets. */
9907 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9908 || inst
.reloc
.exp
.X_add_number
!= 0,
9909 _("this instruction does not support indexing"));
9911 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9912 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9914 if (!(inst
.instruction
& INDEX_UP
))
9915 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9917 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9919 inst
.operands
[2].preind
= 0;
9920 inst
.operands
[2].postind
= 1;
9924 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9927 /* iWMMXt instructions: strictly in alphabetical order. */
9930 do_iwmmxt_tandorc (void)
9932 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9936 do_iwmmxt_textrc (void)
9938 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9939 inst
.instruction
|= inst
.operands
[1].imm
;
9943 do_iwmmxt_textrm (void)
9945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9946 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9947 inst
.instruction
|= inst
.operands
[2].imm
;
9951 do_iwmmxt_tinsr (void)
9953 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9954 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9955 inst
.instruction
|= inst
.operands
[2].imm
;
9959 do_iwmmxt_tmia (void)
9961 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9962 inst
.instruction
|= inst
.operands
[1].reg
;
9963 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9967 do_iwmmxt_waligni (void)
9969 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9970 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9971 inst
.instruction
|= inst
.operands
[2].reg
;
9972 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9976 do_iwmmxt_wmerge (void)
9978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9979 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9980 inst
.instruction
|= inst
.operands
[2].reg
;
9981 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9985 do_iwmmxt_wmov (void)
9987 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9988 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9989 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9990 inst
.instruction
|= inst
.operands
[1].reg
;
9994 do_iwmmxt_wldstbh (void)
9997 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9999 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10001 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10002 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10006 do_iwmmxt_wldstw (void)
10008 /* RIWR_RIWC clears .isreg for a control register. */
10009 if (!inst
.operands
[0].isreg
)
10011 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10012 inst
.instruction
|= 0xf0000000;
10015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10016 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10020 do_iwmmxt_wldstd (void)
10022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10023 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10024 && inst
.operands
[1].immisreg
)
10026 inst
.instruction
&= ~0x1a000ff;
10027 inst
.instruction
|= (0xfU
<< 28);
10028 if (inst
.operands
[1].preind
)
10029 inst
.instruction
|= PRE_INDEX
;
10030 if (!inst
.operands
[1].negative
)
10031 inst
.instruction
|= INDEX_UP
;
10032 if (inst
.operands
[1].writeback
)
10033 inst
.instruction
|= WRITE_BACK
;
10034 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10035 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10036 inst
.instruction
|= inst
.operands
[1].imm
;
10039 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10043 do_iwmmxt_wshufh (void)
10045 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10046 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10047 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10048 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10052 do_iwmmxt_wzero (void)
10054 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10055 inst
.instruction
|= inst
.operands
[0].reg
;
10056 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10057 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10061 do_iwmmxt_wrwrwr_or_imm5 (void)
10063 if (inst
.operands
[2].isreg
)
10066 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10067 _("immediate operand requires iWMMXt2"));
10069 if (inst
.operands
[2].imm
== 0)
10071 switch ((inst
.instruction
>> 20) & 0xf)
10077 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10078 inst
.operands
[2].imm
= 16;
10079 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10085 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10086 inst
.operands
[2].imm
= 32;
10087 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10094 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10096 wrn
= (inst
.instruction
>> 16) & 0xf;
10097 inst
.instruction
&= 0xff0fff0f;
10098 inst
.instruction
|= wrn
;
10099 /* Bail out here; the instruction is now assembled. */
10104 /* Map 32 -> 0, etc. */
10105 inst
.operands
[2].imm
&= 0x1f;
10106 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10110 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10111 operations first, then control, shift, and load/store. */
10113 /* Insns like "foo X,Y,Z". */
10116 do_mav_triple (void)
10118 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10119 inst
.instruction
|= inst
.operands
[1].reg
;
10120 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10123 /* Insns like "foo W,X,Y,Z".
10124 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10129 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10130 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10131 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10132 inst
.instruction
|= inst
.operands
[3].reg
;
10135 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10137 do_mav_dspsc (void)
10139 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10142 /* Maverick shift immediate instructions.
10143 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10144 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10147 do_mav_shift (void)
10149 int imm
= inst
.operands
[2].imm
;
10151 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10152 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10154 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10155 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10156 Bit 4 should be 0. */
10157 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10159 inst
.instruction
|= imm
;
10162 /* XScale instructions. Also sorted arithmetic before move. */
10164 /* Xscale multiply-accumulate (argument parse)
10167 MIAxycc acc0,Rm,Rs. */
10172 inst
.instruction
|= inst
.operands
[1].reg
;
10173 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10176 /* Xscale move-accumulator-register (argument parse)
10178 MARcc acc0,RdLo,RdHi. */
10183 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10184 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10187 /* Xscale move-register-accumulator (argument parse)
10189 MRAcc RdLo,RdHi,acc0. */
10194 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10195 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10196 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10199 /* Encoding functions relevant only to Thumb. */
10201 /* inst.operands[i] is a shifted-register operand; encode
10202 it into inst.instruction in the format used by Thumb32. */
10205 encode_thumb32_shifted_operand (int i
)
10207 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10208 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10210 constraint (inst
.operands
[i
].immisreg
,
10211 _("shift by register not allowed in thumb mode"));
10212 inst
.instruction
|= inst
.operands
[i
].reg
;
10213 if (shift
== SHIFT_RRX
)
10214 inst
.instruction
|= SHIFT_ROR
<< 4;
10217 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10218 _("expression too complex"));
10220 constraint (value
> 32
10221 || (value
== 32 && (shift
== SHIFT_LSL
10222 || shift
== SHIFT_ROR
)),
10223 _("shift expression is too large"));
10227 else if (value
== 32)
10230 inst
.instruction
|= shift
<< 4;
10231 inst
.instruction
|= (value
& 0x1c) << 10;
10232 inst
.instruction
|= (value
& 0x03) << 6;
10237 /* inst.operands[i] was set up by parse_address. Encode it into a
10238 Thumb32 format load or store instruction. Reject forms that cannot
10239 be used with such instructions. If is_t is true, reject forms that
10240 cannot be used with a T instruction; if is_d is true, reject forms
10241 that cannot be used with a D instruction. If it is a store insn,
10242 reject PC in Rn. */
10245 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10247 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10249 constraint (!inst
.operands
[i
].isreg
,
10250 _("Instruction does not support =N addresses"));
10252 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10253 if (inst
.operands
[i
].immisreg
)
10255 constraint (is_pc
, BAD_PC_ADDRESSING
);
10256 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10257 constraint (inst
.operands
[i
].negative
,
10258 _("Thumb does not support negative register indexing"));
10259 constraint (inst
.operands
[i
].postind
,
10260 _("Thumb does not support register post-indexing"));
10261 constraint (inst
.operands
[i
].writeback
,
10262 _("Thumb does not support register indexing with writeback"));
10263 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10264 _("Thumb supports only LSL in shifted register indexing"));
10266 inst
.instruction
|= inst
.operands
[i
].imm
;
10267 if (inst
.operands
[i
].shifted
)
10269 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10270 _("expression too complex"));
10271 constraint (inst
.reloc
.exp
.X_add_number
< 0
10272 || inst
.reloc
.exp
.X_add_number
> 3,
10273 _("shift out of range"));
10274 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10276 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10278 else if (inst
.operands
[i
].preind
)
10280 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10281 constraint (is_t
&& inst
.operands
[i
].writeback
,
10282 _("cannot use writeback with this instruction"));
10283 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10284 BAD_PC_ADDRESSING
);
10288 inst
.instruction
|= 0x01000000;
10289 if (inst
.operands
[i
].writeback
)
10290 inst
.instruction
|= 0x00200000;
10294 inst
.instruction
|= 0x00000c00;
10295 if (inst
.operands
[i
].writeback
)
10296 inst
.instruction
|= 0x00000100;
10298 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10300 else if (inst
.operands
[i
].postind
)
10302 gas_assert (inst
.operands
[i
].writeback
);
10303 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10304 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10307 inst
.instruction
|= 0x00200000;
10309 inst
.instruction
|= 0x00000900;
10310 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10312 else /* unindexed - only for coprocessor */
10313 inst
.error
= _("instruction does not accept unindexed addressing");
10316 /* Table of Thumb instructions which exist in both 16- and 32-bit
10317 encodings (the latter only in post-V6T2 cores). The index is the
10318 value used in the insns table below. When there is more than one
10319 possible 16-bit encoding for the instruction, this table always
10321 Also contains several pseudo-instructions used during relaxation. */
10322 #define T16_32_TAB \
10323 X(_adc, 4140, eb400000), \
10324 X(_adcs, 4140, eb500000), \
10325 X(_add, 1c00, eb000000), \
10326 X(_adds, 1c00, eb100000), \
10327 X(_addi, 0000, f1000000), \
10328 X(_addis, 0000, f1100000), \
10329 X(_add_pc,000f, f20f0000), \
10330 X(_add_sp,000d, f10d0000), \
10331 X(_adr, 000f, f20f0000), \
10332 X(_and, 4000, ea000000), \
10333 X(_ands, 4000, ea100000), \
10334 X(_asr, 1000, fa40f000), \
10335 X(_asrs, 1000, fa50f000), \
10336 X(_b, e000, f000b000), \
10337 X(_bcond, d000, f0008000), \
10338 X(_bic, 4380, ea200000), \
10339 X(_bics, 4380, ea300000), \
10340 X(_cmn, 42c0, eb100f00), \
10341 X(_cmp, 2800, ebb00f00), \
10342 X(_cpsie, b660, f3af8400), \
10343 X(_cpsid, b670, f3af8600), \
10344 X(_cpy, 4600, ea4f0000), \
10345 X(_dec_sp,80dd, f1ad0d00), \
10346 X(_eor, 4040, ea800000), \
10347 X(_eors, 4040, ea900000), \
10348 X(_inc_sp,00dd, f10d0d00), \
10349 X(_ldmia, c800, e8900000), \
10350 X(_ldr, 6800, f8500000), \
10351 X(_ldrb, 7800, f8100000), \
10352 X(_ldrh, 8800, f8300000), \
10353 X(_ldrsb, 5600, f9100000), \
10354 X(_ldrsh, 5e00, f9300000), \
10355 X(_ldr_pc,4800, f85f0000), \
10356 X(_ldr_pc2,4800, f85f0000), \
10357 X(_ldr_sp,9800, f85d0000), \
10358 X(_lsl, 0000, fa00f000), \
10359 X(_lsls, 0000, fa10f000), \
10360 X(_lsr, 0800, fa20f000), \
10361 X(_lsrs, 0800, fa30f000), \
10362 X(_mov, 2000, ea4f0000), \
10363 X(_movs, 2000, ea5f0000), \
10364 X(_mul, 4340, fb00f000), \
10365 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10366 X(_mvn, 43c0, ea6f0000), \
10367 X(_mvns, 43c0, ea7f0000), \
10368 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10369 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10370 X(_orr, 4300, ea400000), \
10371 X(_orrs, 4300, ea500000), \
10372 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10373 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10374 X(_rev, ba00, fa90f080), \
10375 X(_rev16, ba40, fa90f090), \
10376 X(_revsh, bac0, fa90f0b0), \
10377 X(_ror, 41c0, fa60f000), \
10378 X(_rors, 41c0, fa70f000), \
10379 X(_sbc, 4180, eb600000), \
10380 X(_sbcs, 4180, eb700000), \
10381 X(_stmia, c000, e8800000), \
10382 X(_str, 6000, f8400000), \
10383 X(_strb, 7000, f8000000), \
10384 X(_strh, 8000, f8200000), \
10385 X(_str_sp,9000, f84d0000), \
10386 X(_sub, 1e00, eba00000), \
10387 X(_subs, 1e00, ebb00000), \
10388 X(_subi, 8000, f1a00000), \
10389 X(_subis, 8000, f1b00000), \
10390 X(_sxtb, b240, fa4ff080), \
10391 X(_sxth, b200, fa0ff080), \
10392 X(_tst, 4200, ea100f00), \
10393 X(_uxtb, b2c0, fa5ff080), \
10394 X(_uxth, b280, fa1ff080), \
10395 X(_nop, bf00, f3af8000), \
10396 X(_yield, bf10, f3af8001), \
10397 X(_wfe, bf20, f3af8002), \
10398 X(_wfi, bf30, f3af8003), \
10399 X(_sev, bf40, f3af8004), \
10400 X(_sevl, bf50, f3af8005), \
10401 X(_udf, de00, f7f0a000)
10403 /* To catch errors in encoding functions, the codes are all offset by
10404 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10405 as 16-bit instructions. */
10406 #define X(a,b,c) T_MNEM##a
10407 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10410 #define X(a,b,c) 0x##b
10411 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10412 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10415 #define X(a,b,c) 0x##c
10416 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10417 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10418 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10422 /* Thumb instruction encoders, in alphabetical order. */
10424 /* ADDW or SUBW. */
10427 do_t_add_sub_w (void)
10431 Rd
= inst
.operands
[0].reg
;
10432 Rn
= inst
.operands
[1].reg
;
10434 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10435 is the SP-{plus,minus}-immediate form of the instruction. */
10437 constraint (Rd
== REG_PC
, BAD_PC
);
10439 reject_bad_reg (Rd
);
10441 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10442 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10445 /* Parse an add or subtract instruction. We get here with inst.instruction
10446 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10449 do_t_add_sub (void)
10453 Rd
= inst
.operands
[0].reg
;
10454 Rs
= (inst
.operands
[1].present
10455 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10456 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10459 set_it_insn_type_last ();
10461 if (unified_syntax
)
10464 bfd_boolean narrow
;
10467 flags
= (inst
.instruction
== T_MNEM_adds
10468 || inst
.instruction
== T_MNEM_subs
);
10470 narrow
= !in_it_block ();
10472 narrow
= in_it_block ();
10473 if (!inst
.operands
[2].isreg
)
10477 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10479 add
= (inst
.instruction
== T_MNEM_add
10480 || inst
.instruction
== T_MNEM_adds
);
10482 if (inst
.size_req
!= 4)
10484 /* Attempt to use a narrow opcode, with relaxation if
10486 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10487 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10488 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10489 opcode
= T_MNEM_add_sp
;
10490 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10491 opcode
= T_MNEM_add_pc
;
10492 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10495 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10497 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10501 inst
.instruction
= THUMB_OP16(opcode
);
10502 inst
.instruction
|= (Rd
<< 4) | Rs
;
10503 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10504 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10506 if (inst
.size_req
== 2)
10507 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10509 inst
.relax
= opcode
;
10513 constraint (inst
.size_req
== 2, BAD_HIREG
);
10515 if (inst
.size_req
== 4
10516 || (inst
.size_req
!= 2 && !opcode
))
10518 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10519 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10520 THUMB1_RELOC_ONLY
);
10523 constraint (add
, BAD_PC
);
10524 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10525 _("only SUBS PC, LR, #const allowed"));
10526 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10527 _("expression too complex"));
10528 constraint (inst
.reloc
.exp
.X_add_number
< 0
10529 || inst
.reloc
.exp
.X_add_number
> 0xff,
10530 _("immediate value out of range"));
10531 inst
.instruction
= T2_SUBS_PC_LR
10532 | inst
.reloc
.exp
.X_add_number
;
10533 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10536 else if (Rs
== REG_PC
)
10538 /* Always use addw/subw. */
10539 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10540 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10544 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10545 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10548 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10550 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10552 inst
.instruction
|= Rd
<< 8;
10553 inst
.instruction
|= Rs
<< 16;
10558 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10559 unsigned int shift
= inst
.operands
[2].shift_kind
;
10561 Rn
= inst
.operands
[2].reg
;
10562 /* See if we can do this with a 16-bit instruction. */
10563 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10565 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10570 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10571 || inst
.instruction
== T_MNEM_add
)
10573 : T_OPCODE_SUB_R3
);
10574 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10578 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10580 /* Thumb-1 cores (except v6-M) require at least one high
10581 register in a narrow non flag setting add. */
10582 if (Rd
> 7 || Rn
> 7
10583 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10584 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10591 inst
.instruction
= T_OPCODE_ADD_HI
;
10592 inst
.instruction
|= (Rd
& 8) << 4;
10593 inst
.instruction
|= (Rd
& 7);
10594 inst
.instruction
|= Rn
<< 3;
10600 constraint (Rd
== REG_PC
, BAD_PC
);
10601 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10602 constraint (Rs
== REG_PC
, BAD_PC
);
10603 reject_bad_reg (Rn
);
10605 /* If we get here, it can't be done in 16 bits. */
10606 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10607 _("shift must be constant"));
10608 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10609 inst
.instruction
|= Rd
<< 8;
10610 inst
.instruction
|= Rs
<< 16;
10611 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10612 _("shift value over 3 not allowed in thumb mode"));
10613 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10614 _("only LSL shift allowed in thumb mode"));
10615 encode_thumb32_shifted_operand (2);
10620 constraint (inst
.instruction
== T_MNEM_adds
10621 || inst
.instruction
== T_MNEM_subs
,
10624 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10626 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10627 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10630 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10631 ? 0x0000 : 0x8000);
10632 inst
.instruction
|= (Rd
<< 4) | Rs
;
10633 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10637 Rn
= inst
.operands
[2].reg
;
10638 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10640 /* We now have Rd, Rs, and Rn set to registers. */
10641 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10643 /* Can't do this for SUB. */
10644 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10645 inst
.instruction
= T_OPCODE_ADD_HI
;
10646 inst
.instruction
|= (Rd
& 8) << 4;
10647 inst
.instruction
|= (Rd
& 7);
10649 inst
.instruction
|= Rn
<< 3;
10651 inst
.instruction
|= Rs
<< 3;
10653 constraint (1, _("dest must overlap one source register"));
10657 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10658 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10659 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10669 Rd
= inst
.operands
[0].reg
;
10670 reject_bad_reg (Rd
);
10672 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10674 /* Defer to section relaxation. */
10675 inst
.relax
= inst
.instruction
;
10676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10677 inst
.instruction
|= Rd
<< 4;
10679 else if (unified_syntax
&& inst
.size_req
!= 2)
10681 /* Generate a 32-bit opcode. */
10682 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10683 inst
.instruction
|= Rd
<< 8;
10684 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10685 inst
.reloc
.pc_rel
= 1;
10689 /* Generate a 16-bit opcode. */
10690 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10691 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10692 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10693 inst
.reloc
.pc_rel
= 1;
10695 inst
.instruction
|= Rd
<< 4;
10699 /* Arithmetic instructions for which there is just one 16-bit
10700 instruction encoding, and it allows only two low registers.
10701 For maximal compatibility with ARM syntax, we allow three register
10702 operands even when Thumb-32 instructions are not available, as long
10703 as the first two are identical. For instance, both "sbc r0,r1" and
10704 "sbc r0,r0,r1" are allowed. */
10710 Rd
= inst
.operands
[0].reg
;
10711 Rs
= (inst
.operands
[1].present
10712 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10713 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10714 Rn
= inst
.operands
[2].reg
;
10716 reject_bad_reg (Rd
);
10717 reject_bad_reg (Rs
);
10718 if (inst
.operands
[2].isreg
)
10719 reject_bad_reg (Rn
);
10721 if (unified_syntax
)
10723 if (!inst
.operands
[2].isreg
)
10725 /* For an immediate, we always generate a 32-bit opcode;
10726 section relaxation will shrink it later if possible. */
10727 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10728 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10729 inst
.instruction
|= Rd
<< 8;
10730 inst
.instruction
|= Rs
<< 16;
10731 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10735 bfd_boolean narrow
;
10737 /* See if we can do this with a 16-bit instruction. */
10738 if (THUMB_SETS_FLAGS (inst
.instruction
))
10739 narrow
= !in_it_block ();
10741 narrow
= in_it_block ();
10743 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10745 if (inst
.operands
[2].shifted
)
10747 if (inst
.size_req
== 4)
10753 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10754 inst
.instruction
|= Rd
;
10755 inst
.instruction
|= Rn
<< 3;
10759 /* If we get here, it can't be done in 16 bits. */
10760 constraint (inst
.operands
[2].shifted
10761 && inst
.operands
[2].immisreg
,
10762 _("shift must be constant"));
10763 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10764 inst
.instruction
|= Rd
<< 8;
10765 inst
.instruction
|= Rs
<< 16;
10766 encode_thumb32_shifted_operand (2);
10771 /* On its face this is a lie - the instruction does set the
10772 flags. However, the only supported mnemonic in this mode
10773 says it doesn't. */
10774 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10776 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10777 _("unshifted register required"));
10778 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10779 constraint (Rd
!= Rs
,
10780 _("dest and source1 must be the same register"));
10782 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10783 inst
.instruction
|= Rd
;
10784 inst
.instruction
|= Rn
<< 3;
10788 /* Similarly, but for instructions where the arithmetic operation is
10789 commutative, so we can allow either of them to be different from
10790 the destination operand in a 16-bit instruction. For instance, all
10791 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10798 Rd
= inst
.operands
[0].reg
;
10799 Rs
= (inst
.operands
[1].present
10800 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10801 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10802 Rn
= inst
.operands
[2].reg
;
10804 reject_bad_reg (Rd
);
10805 reject_bad_reg (Rs
);
10806 if (inst
.operands
[2].isreg
)
10807 reject_bad_reg (Rn
);
10809 if (unified_syntax
)
10811 if (!inst
.operands
[2].isreg
)
10813 /* For an immediate, we always generate a 32-bit opcode;
10814 section relaxation will shrink it later if possible. */
10815 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10816 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10817 inst
.instruction
|= Rd
<< 8;
10818 inst
.instruction
|= Rs
<< 16;
10819 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10823 bfd_boolean narrow
;
10825 /* See if we can do this with a 16-bit instruction. */
10826 if (THUMB_SETS_FLAGS (inst
.instruction
))
10827 narrow
= !in_it_block ();
10829 narrow
= in_it_block ();
10831 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10833 if (inst
.operands
[2].shifted
)
10835 if (inst
.size_req
== 4)
10842 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10843 inst
.instruction
|= Rd
;
10844 inst
.instruction
|= Rn
<< 3;
10849 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10850 inst
.instruction
|= Rd
;
10851 inst
.instruction
|= Rs
<< 3;
10856 /* If we get here, it can't be done in 16 bits. */
10857 constraint (inst
.operands
[2].shifted
10858 && inst
.operands
[2].immisreg
,
10859 _("shift must be constant"));
10860 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10861 inst
.instruction
|= Rd
<< 8;
10862 inst
.instruction
|= Rs
<< 16;
10863 encode_thumb32_shifted_operand (2);
10868 /* On its face this is a lie - the instruction does set the
10869 flags. However, the only supported mnemonic in this mode
10870 says it doesn't. */
10871 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10873 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10874 _("unshifted register required"));
10875 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10877 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10878 inst
.instruction
|= Rd
;
10881 inst
.instruction
|= Rn
<< 3;
10883 inst
.instruction
|= Rs
<< 3;
10885 constraint (1, _("dest must overlap one source register"));
10893 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10894 constraint (msb
> 32, _("bit-field extends past end of register"));
10895 /* The instruction encoding stores the LSB and MSB,
10896 not the LSB and width. */
10897 Rd
= inst
.operands
[0].reg
;
10898 reject_bad_reg (Rd
);
10899 inst
.instruction
|= Rd
<< 8;
10900 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10901 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10902 inst
.instruction
|= msb
- 1;
10911 Rd
= inst
.operands
[0].reg
;
10912 reject_bad_reg (Rd
);
10914 /* #0 in second position is alternative syntax for bfc, which is
10915 the same instruction but with REG_PC in the Rm field. */
10916 if (!inst
.operands
[1].isreg
)
10920 Rn
= inst
.operands
[1].reg
;
10921 reject_bad_reg (Rn
);
10924 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10925 constraint (msb
> 32, _("bit-field extends past end of register"));
10926 /* The instruction encoding stores the LSB and MSB,
10927 not the LSB and width. */
10928 inst
.instruction
|= Rd
<< 8;
10929 inst
.instruction
|= Rn
<< 16;
10930 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10931 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10932 inst
.instruction
|= msb
- 1;
10940 Rd
= inst
.operands
[0].reg
;
10941 Rn
= inst
.operands
[1].reg
;
10943 reject_bad_reg (Rd
);
10944 reject_bad_reg (Rn
);
10946 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10947 _("bit-field extends past end of register"));
10948 inst
.instruction
|= Rd
<< 8;
10949 inst
.instruction
|= Rn
<< 16;
10950 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10951 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10952 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10955 /* ARM V5 Thumb BLX (argument parse)
10956 BLX <target_addr> which is BLX(1)
10957 BLX <Rm> which is BLX(2)
10958 Unfortunately, there are two different opcodes for this mnemonic.
10959 So, the insns[].value is not used, and the code here zaps values
10960 into inst.instruction.
10962 ??? How to take advantage of the additional two bits of displacement
10963 available in Thumb32 mode? Need new relocation? */
10968 set_it_insn_type_last ();
10970 if (inst
.operands
[0].isreg
)
10972 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10973 /* We have a register, so this is BLX(2). */
10974 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10978 /* No register. This must be BLX(1). */
10979 inst
.instruction
= 0xf000e800;
10980 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10989 bfd_reloc_code_real_type reloc
;
10992 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10994 if (in_it_block ())
10996 /* Conditional branches inside IT blocks are encoded as unconditional
10998 cond
= COND_ALWAYS
;
11003 if (cond
!= COND_ALWAYS
)
11004 opcode
= T_MNEM_bcond
;
11006 opcode
= inst
.instruction
;
11009 && (inst
.size_req
== 4
11010 || (inst
.size_req
!= 2
11011 && (inst
.operands
[0].hasreloc
11012 || inst
.reloc
.exp
.X_op
== O_constant
))))
11014 inst
.instruction
= THUMB_OP32(opcode
);
11015 if (cond
== COND_ALWAYS
)
11016 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11019 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11020 _("selected architecture does not support "
11021 "wide conditional branch instruction"));
11023 gas_assert (cond
!= 0xF);
11024 inst
.instruction
|= cond
<< 22;
11025 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11030 inst
.instruction
= THUMB_OP16(opcode
);
11031 if (cond
== COND_ALWAYS
)
11032 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11035 inst
.instruction
|= cond
<< 8;
11036 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11038 /* Allow section relaxation. */
11039 if (unified_syntax
&& inst
.size_req
!= 2)
11040 inst
.relax
= opcode
;
11042 inst
.reloc
.type
= reloc
;
11043 inst
.reloc
.pc_rel
= 1;
11046 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11047 between the two is the maximum immediate allowed - which is passed in
11050 do_t_bkpt_hlt1 (int range
)
11052 constraint (inst
.cond
!= COND_ALWAYS
,
11053 _("instruction is always unconditional"));
11054 if (inst
.operands
[0].present
)
11056 constraint (inst
.operands
[0].imm
> range
,
11057 _("immediate value out of range"));
11058 inst
.instruction
|= inst
.operands
[0].imm
;
11061 set_it_insn_type (NEUTRAL_IT_INSN
);
11067 do_t_bkpt_hlt1 (63);
11073 do_t_bkpt_hlt1 (255);
11077 do_t_branch23 (void)
11079 set_it_insn_type_last ();
11080 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11082 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11083 this file. We used to simply ignore the PLT reloc type here --
11084 the branch encoding is now needed to deal with TLSCALL relocs.
11085 So if we see a PLT reloc now, put it back to how it used to be to
11086 keep the preexisting behaviour. */
11087 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11088 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11090 #if defined(OBJ_COFF)
11091 /* If the destination of the branch is a defined symbol which does not have
11092 the THUMB_FUNC attribute, then we must be calling a function which has
11093 the (interfacearm) attribute. We look for the Thumb entry point to that
11094 function and change the branch to refer to that function instead. */
11095 if ( inst
.reloc
.exp
.X_op
== O_symbol
11096 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11097 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11098 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11099 inst
.reloc
.exp
.X_add_symbol
=
11100 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11107 set_it_insn_type_last ();
11108 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11109 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11110 should cause the alignment to be checked once it is known. This is
11111 because BX PC only works if the instruction is word aligned. */
11119 set_it_insn_type_last ();
11120 Rm
= inst
.operands
[0].reg
;
11121 reject_bad_reg (Rm
);
11122 inst
.instruction
|= Rm
<< 16;
11131 Rd
= inst
.operands
[0].reg
;
11132 Rm
= inst
.operands
[1].reg
;
11134 reject_bad_reg (Rd
);
11135 reject_bad_reg (Rm
);
11137 inst
.instruction
|= Rd
<< 8;
11138 inst
.instruction
|= Rm
<< 16;
11139 inst
.instruction
|= Rm
;
11145 set_it_insn_type (OUTSIDE_IT_INSN
);
11146 inst
.instruction
|= inst
.operands
[0].imm
;
11152 set_it_insn_type (OUTSIDE_IT_INSN
);
11154 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11155 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11157 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11158 inst
.instruction
= 0xf3af8000;
11159 inst
.instruction
|= imod
<< 9;
11160 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11161 if (inst
.operands
[1].present
)
11162 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11166 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11167 && (inst
.operands
[0].imm
& 4),
11168 _("selected processor does not support 'A' form "
11169 "of this instruction"));
11170 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11171 _("Thumb does not support the 2-argument "
11172 "form of this instruction"));
11173 inst
.instruction
|= inst
.operands
[0].imm
;
11177 /* THUMB CPY instruction (argument parse). */
11182 if (inst
.size_req
== 4)
11184 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11185 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11186 inst
.instruction
|= inst
.operands
[1].reg
;
11190 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11191 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11192 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11199 set_it_insn_type (OUTSIDE_IT_INSN
);
11200 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11201 inst
.instruction
|= inst
.operands
[0].reg
;
11202 inst
.reloc
.pc_rel
= 1;
11203 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11209 inst
.instruction
|= inst
.operands
[0].imm
;
11215 unsigned Rd
, Rn
, Rm
;
11217 Rd
= inst
.operands
[0].reg
;
11218 Rn
= (inst
.operands
[1].present
11219 ? inst
.operands
[1].reg
: Rd
);
11220 Rm
= inst
.operands
[2].reg
;
11222 reject_bad_reg (Rd
);
11223 reject_bad_reg (Rn
);
11224 reject_bad_reg (Rm
);
11226 inst
.instruction
|= Rd
<< 8;
11227 inst
.instruction
|= Rn
<< 16;
11228 inst
.instruction
|= Rm
;
11234 if (unified_syntax
&& inst
.size_req
== 4)
11235 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11237 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11243 unsigned int cond
= inst
.operands
[0].imm
;
11245 set_it_insn_type (IT_INSN
);
11246 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11248 now_it
.warn_deprecated
= FALSE
;
11250 /* If the condition is a negative condition, invert the mask. */
11251 if ((cond
& 0x1) == 0x0)
11253 unsigned int mask
= inst
.instruction
& 0x000f;
11255 if ((mask
& 0x7) == 0)
11257 /* No conversion needed. */
11258 now_it
.block_length
= 1;
11260 else if ((mask
& 0x3) == 0)
11263 now_it
.block_length
= 2;
11265 else if ((mask
& 0x1) == 0)
11268 now_it
.block_length
= 3;
11273 now_it
.block_length
= 4;
11276 inst
.instruction
&= 0xfff0;
11277 inst
.instruction
|= mask
;
11280 inst
.instruction
|= cond
<< 4;
11283 /* Helper function used for both push/pop and ldm/stm. */
11285 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11289 load
= (inst
.instruction
& (1 << 20)) != 0;
11291 if (mask
& (1 << 13))
11292 inst
.error
= _("SP not allowed in register list");
11294 if ((mask
& (1 << base
)) != 0
11296 inst
.error
= _("having the base register in the register list when "
11297 "using write back is UNPREDICTABLE");
11301 if (mask
& (1 << 15))
11303 if (mask
& (1 << 14))
11304 inst
.error
= _("LR and PC should not both be in register list");
11306 set_it_insn_type_last ();
11311 if (mask
& (1 << 15))
11312 inst
.error
= _("PC not allowed in register list");
11315 if ((mask
& (mask
- 1)) == 0)
11317 /* Single register transfers implemented as str/ldr. */
11320 if (inst
.instruction
& (1 << 23))
11321 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11323 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11327 if (inst
.instruction
& (1 << 23))
11328 inst
.instruction
= 0x00800000; /* ia -> [base] */
11330 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11333 inst
.instruction
|= 0xf8400000;
11335 inst
.instruction
|= 0x00100000;
11337 mask
= ffs (mask
) - 1;
11340 else if (writeback
)
11341 inst
.instruction
|= WRITE_BACK
;
11343 inst
.instruction
|= mask
;
11344 inst
.instruction
|= base
<< 16;
11350 /* This really doesn't seem worth it. */
11351 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11352 _("expression too complex"));
11353 constraint (inst
.operands
[1].writeback
,
11354 _("Thumb load/store multiple does not support {reglist}^"));
11356 if (unified_syntax
)
11358 bfd_boolean narrow
;
11362 /* See if we can use a 16-bit instruction. */
11363 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11364 && inst
.size_req
!= 4
11365 && !(inst
.operands
[1].imm
& ~0xff))
11367 mask
= 1 << inst
.operands
[0].reg
;
11369 if (inst
.operands
[0].reg
<= 7)
11371 if (inst
.instruction
== T_MNEM_stmia
11372 ? inst
.operands
[0].writeback
11373 : (inst
.operands
[0].writeback
11374 == !(inst
.operands
[1].imm
& mask
)))
11376 if (inst
.instruction
== T_MNEM_stmia
11377 && (inst
.operands
[1].imm
& mask
)
11378 && (inst
.operands
[1].imm
& (mask
- 1)))
11379 as_warn (_("value stored for r%d is UNKNOWN"),
11380 inst
.operands
[0].reg
);
11382 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11383 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11384 inst
.instruction
|= inst
.operands
[1].imm
;
11387 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11389 /* This means 1 register in reg list one of 3 situations:
11390 1. Instruction is stmia, but without writeback.
11391 2. lmdia without writeback, but with Rn not in
11393 3. ldmia with writeback, but with Rn in reglist.
11394 Case 3 is UNPREDICTABLE behaviour, so we handle
11395 case 1 and 2 which can be converted into a 16-bit
11396 str or ldr. The SP cases are handled below. */
11397 unsigned long opcode
;
11398 /* First, record an error for Case 3. */
11399 if (inst
.operands
[1].imm
& mask
11400 && inst
.operands
[0].writeback
)
11402 _("having the base register in the register list when "
11403 "using write back is UNPREDICTABLE");
11405 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11407 inst
.instruction
= THUMB_OP16 (opcode
);
11408 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11409 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11413 else if (inst
.operands
[0] .reg
== REG_SP
)
11415 if (inst
.operands
[0].writeback
)
11418 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11419 ? T_MNEM_push
: T_MNEM_pop
);
11420 inst
.instruction
|= inst
.operands
[1].imm
;
11423 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11426 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11427 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11428 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11436 if (inst
.instruction
< 0xffff)
11437 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11439 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11440 inst
.operands
[0].writeback
);
11445 constraint (inst
.operands
[0].reg
> 7
11446 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11447 constraint (inst
.instruction
!= T_MNEM_ldmia
11448 && inst
.instruction
!= T_MNEM_stmia
,
11449 _("Thumb-2 instruction only valid in unified syntax"));
11450 if (inst
.instruction
== T_MNEM_stmia
)
11452 if (!inst
.operands
[0].writeback
)
11453 as_warn (_("this instruction will write back the base register"));
11454 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11455 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11456 as_warn (_("value stored for r%d is UNKNOWN"),
11457 inst
.operands
[0].reg
);
11461 if (!inst
.operands
[0].writeback
11462 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11463 as_warn (_("this instruction will write back the base register"));
11464 else if (inst
.operands
[0].writeback
11465 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11466 as_warn (_("this instruction will not write back the base register"));
11469 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11470 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11471 inst
.instruction
|= inst
.operands
[1].imm
;
11478 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11479 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11480 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11481 || inst
.operands
[1].negative
,
11484 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11486 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11487 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11488 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11494 if (!inst
.operands
[1].present
)
11496 constraint (inst
.operands
[0].reg
== REG_LR
,
11497 _("r14 not allowed as first register "
11498 "when second register is omitted"));
11499 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11501 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11504 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11505 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11506 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11512 unsigned long opcode
;
11515 if (inst
.operands
[0].isreg
11516 && !inst
.operands
[0].preind
11517 && inst
.operands
[0].reg
== REG_PC
)
11518 set_it_insn_type_last ();
11520 opcode
= inst
.instruction
;
11521 if (unified_syntax
)
11523 if (!inst
.operands
[1].isreg
)
11525 if (opcode
<= 0xffff)
11526 inst
.instruction
= THUMB_OP32 (opcode
);
11527 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11530 if (inst
.operands
[1].isreg
11531 && !inst
.operands
[1].writeback
11532 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11533 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11534 && opcode
<= 0xffff
11535 && inst
.size_req
!= 4)
11537 /* Insn may have a 16-bit form. */
11538 Rn
= inst
.operands
[1].reg
;
11539 if (inst
.operands
[1].immisreg
)
11541 inst
.instruction
= THUMB_OP16 (opcode
);
11543 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11545 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11546 reject_bad_reg (inst
.operands
[1].imm
);
11548 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11549 && opcode
!= T_MNEM_ldrsb
)
11550 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11551 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11558 if (inst
.reloc
.pc_rel
)
11559 opcode
= T_MNEM_ldr_pc2
;
11561 opcode
= T_MNEM_ldr_pc
;
11565 if (opcode
== T_MNEM_ldr
)
11566 opcode
= T_MNEM_ldr_sp
;
11568 opcode
= T_MNEM_str_sp
;
11570 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11574 inst
.instruction
= inst
.operands
[0].reg
;
11575 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11577 inst
.instruction
|= THUMB_OP16 (opcode
);
11578 if (inst
.size_req
== 2)
11579 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11581 inst
.relax
= opcode
;
11585 /* Definitely a 32-bit variant. */
11587 /* Warning for Erratum 752419. */
11588 if (opcode
== T_MNEM_ldr
11589 && inst
.operands
[0].reg
== REG_SP
11590 && inst
.operands
[1].writeback
== 1
11591 && !inst
.operands
[1].immisreg
)
11593 if (no_cpu_selected ()
11594 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11595 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11596 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11597 as_warn (_("This instruction may be unpredictable "
11598 "if executed on M-profile cores "
11599 "with interrupts enabled."));
11602 /* Do some validations regarding addressing modes. */
11603 if (inst
.operands
[1].immisreg
)
11604 reject_bad_reg (inst
.operands
[1].imm
);
11606 constraint (inst
.operands
[1].writeback
== 1
11607 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11610 inst
.instruction
= THUMB_OP32 (opcode
);
11611 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11612 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11613 check_ldr_r15_aligned ();
11617 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11619 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11621 /* Only [Rn,Rm] is acceptable. */
11622 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11623 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11624 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11625 || inst
.operands
[1].negative
,
11626 _("Thumb does not support this addressing mode"));
11627 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11631 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11632 if (!inst
.operands
[1].isreg
)
11633 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11636 constraint (!inst
.operands
[1].preind
11637 || inst
.operands
[1].shifted
11638 || inst
.operands
[1].writeback
,
11639 _("Thumb does not support this addressing mode"));
11640 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11642 constraint (inst
.instruction
& 0x0600,
11643 _("byte or halfword not valid for base register"));
11644 constraint (inst
.operands
[1].reg
== REG_PC
11645 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11646 _("r15 based store not allowed"));
11647 constraint (inst
.operands
[1].immisreg
,
11648 _("invalid base register for register offset"));
11650 if (inst
.operands
[1].reg
== REG_PC
)
11651 inst
.instruction
= T_OPCODE_LDR_PC
;
11652 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11653 inst
.instruction
= T_OPCODE_LDR_SP
;
11655 inst
.instruction
= T_OPCODE_STR_SP
;
11657 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11658 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11662 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11663 if (!inst
.operands
[1].immisreg
)
11665 /* Immediate offset. */
11666 inst
.instruction
|= inst
.operands
[0].reg
;
11667 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11668 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11672 /* Register offset. */
11673 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11674 constraint (inst
.operands
[1].negative
,
11675 _("Thumb does not support this addressing mode"));
11678 switch (inst
.instruction
)
11680 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11681 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11682 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11683 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11684 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11685 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11686 case 0x5600 /* ldrsb */:
11687 case 0x5e00 /* ldrsh */: break;
11691 inst
.instruction
|= inst
.operands
[0].reg
;
11692 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11693 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11699 if (!inst
.operands
[1].present
)
11701 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11702 constraint (inst
.operands
[0].reg
== REG_LR
,
11703 _("r14 not allowed here"));
11704 constraint (inst
.operands
[0].reg
== REG_R12
,
11705 _("r12 not allowed here"));
11708 if (inst
.operands
[2].writeback
11709 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11710 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11711 as_warn (_("base register written back, and overlaps "
11712 "one of transfer registers"));
11714 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11715 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11716 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11722 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11723 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11729 unsigned Rd
, Rn
, Rm
, Ra
;
11731 Rd
= inst
.operands
[0].reg
;
11732 Rn
= inst
.operands
[1].reg
;
11733 Rm
= inst
.operands
[2].reg
;
11734 Ra
= inst
.operands
[3].reg
;
11736 reject_bad_reg (Rd
);
11737 reject_bad_reg (Rn
);
11738 reject_bad_reg (Rm
);
11739 reject_bad_reg (Ra
);
11741 inst
.instruction
|= Rd
<< 8;
11742 inst
.instruction
|= Rn
<< 16;
11743 inst
.instruction
|= Rm
;
11744 inst
.instruction
|= Ra
<< 12;
11750 unsigned RdLo
, RdHi
, Rn
, Rm
;
11752 RdLo
= inst
.operands
[0].reg
;
11753 RdHi
= inst
.operands
[1].reg
;
11754 Rn
= inst
.operands
[2].reg
;
11755 Rm
= inst
.operands
[3].reg
;
11757 reject_bad_reg (RdLo
);
11758 reject_bad_reg (RdHi
);
11759 reject_bad_reg (Rn
);
11760 reject_bad_reg (Rm
);
11762 inst
.instruction
|= RdLo
<< 12;
11763 inst
.instruction
|= RdHi
<< 8;
11764 inst
.instruction
|= Rn
<< 16;
11765 inst
.instruction
|= Rm
;
11769 do_t_mov_cmp (void)
11773 Rn
= inst
.operands
[0].reg
;
11774 Rm
= inst
.operands
[1].reg
;
11777 set_it_insn_type_last ();
11779 if (unified_syntax
)
11781 int r0off
= (inst
.instruction
== T_MNEM_mov
11782 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11783 unsigned long opcode
;
11784 bfd_boolean narrow
;
11785 bfd_boolean low_regs
;
11787 low_regs
= (Rn
<= 7 && Rm
<= 7);
11788 opcode
= inst
.instruction
;
11789 if (in_it_block ())
11790 narrow
= opcode
!= T_MNEM_movs
;
11792 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11793 if (inst
.size_req
== 4
11794 || inst
.operands
[1].shifted
)
11797 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11798 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11799 && !inst
.operands
[1].shifted
11803 inst
.instruction
= T2_SUBS_PC_LR
;
11807 if (opcode
== T_MNEM_cmp
)
11809 constraint (Rn
== REG_PC
, BAD_PC
);
11812 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11814 warn_deprecated_sp (Rm
);
11815 /* R15 was documented as a valid choice for Rm in ARMv6,
11816 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11817 tools reject R15, so we do too. */
11818 constraint (Rm
== REG_PC
, BAD_PC
);
11821 reject_bad_reg (Rm
);
11823 else if (opcode
== T_MNEM_mov
11824 || opcode
== T_MNEM_movs
)
11826 if (inst
.operands
[1].isreg
)
11828 if (opcode
== T_MNEM_movs
)
11830 reject_bad_reg (Rn
);
11831 reject_bad_reg (Rm
);
11835 /* This is mov.n. */
11836 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11837 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11839 as_tsktsk (_("Use of r%u as a source register is "
11840 "deprecated when r%u is the destination "
11841 "register."), Rm
, Rn
);
11846 /* This is mov.w. */
11847 constraint (Rn
== REG_PC
, BAD_PC
);
11848 constraint (Rm
== REG_PC
, BAD_PC
);
11849 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11853 reject_bad_reg (Rn
);
11856 if (!inst
.operands
[1].isreg
)
11858 /* Immediate operand. */
11859 if (!in_it_block () && opcode
== T_MNEM_mov
)
11861 if (low_regs
&& narrow
)
11863 inst
.instruction
= THUMB_OP16 (opcode
);
11864 inst
.instruction
|= Rn
<< 8;
11865 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11866 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11868 if (inst
.size_req
== 2)
11869 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11871 inst
.relax
= opcode
;
11876 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11877 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11878 THUMB1_RELOC_ONLY
);
11880 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11881 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11882 inst
.instruction
|= Rn
<< r0off
;
11883 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11886 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11887 && (inst
.instruction
== T_MNEM_mov
11888 || inst
.instruction
== T_MNEM_movs
))
11890 /* Register shifts are encoded as separate shift instructions. */
11891 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11893 if (in_it_block ())
11898 if (inst
.size_req
== 4)
11901 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11907 switch (inst
.operands
[1].shift_kind
)
11910 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11913 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11916 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11919 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11925 inst
.instruction
= opcode
;
11928 inst
.instruction
|= Rn
;
11929 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11934 inst
.instruction
|= CONDS_BIT
;
11936 inst
.instruction
|= Rn
<< 8;
11937 inst
.instruction
|= Rm
<< 16;
11938 inst
.instruction
|= inst
.operands
[1].imm
;
11943 /* Some mov with immediate shift have narrow variants.
11944 Register shifts are handled above. */
11945 if (low_regs
&& inst
.operands
[1].shifted
11946 && (inst
.instruction
== T_MNEM_mov
11947 || inst
.instruction
== T_MNEM_movs
))
11949 if (in_it_block ())
11950 narrow
= (inst
.instruction
== T_MNEM_mov
);
11952 narrow
= (inst
.instruction
== T_MNEM_movs
);
11957 switch (inst
.operands
[1].shift_kind
)
11959 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11960 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11961 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11962 default: narrow
= FALSE
; break;
11968 inst
.instruction
|= Rn
;
11969 inst
.instruction
|= Rm
<< 3;
11970 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11974 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11975 inst
.instruction
|= Rn
<< r0off
;
11976 encode_thumb32_shifted_operand (1);
11980 switch (inst
.instruction
)
11983 /* In v4t or v5t a move of two lowregs produces unpredictable
11984 results. Don't allow this. */
11987 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11988 "MOV Rd, Rs with two low registers is not "
11989 "permitted on this architecture");
11990 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11994 inst
.instruction
= T_OPCODE_MOV_HR
;
11995 inst
.instruction
|= (Rn
& 0x8) << 4;
11996 inst
.instruction
|= (Rn
& 0x7);
11997 inst
.instruction
|= Rm
<< 3;
12001 /* We know we have low registers at this point.
12002 Generate LSLS Rd, Rs, #0. */
12003 inst
.instruction
= T_OPCODE_LSL_I
;
12004 inst
.instruction
|= Rn
;
12005 inst
.instruction
|= Rm
<< 3;
12011 inst
.instruction
= T_OPCODE_CMP_LR
;
12012 inst
.instruction
|= Rn
;
12013 inst
.instruction
|= Rm
<< 3;
12017 inst
.instruction
= T_OPCODE_CMP_HR
;
12018 inst
.instruction
|= (Rn
& 0x8) << 4;
12019 inst
.instruction
|= (Rn
& 0x7);
12020 inst
.instruction
|= Rm
<< 3;
12027 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12029 /* PR 10443: Do not silently ignore shifted operands. */
12030 constraint (inst
.operands
[1].shifted
,
12031 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12033 if (inst
.operands
[1].isreg
)
12035 if (Rn
< 8 && Rm
< 8)
12037 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12038 since a MOV instruction produces unpredictable results. */
12039 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12040 inst
.instruction
= T_OPCODE_ADD_I3
;
12042 inst
.instruction
= T_OPCODE_CMP_LR
;
12044 inst
.instruction
|= Rn
;
12045 inst
.instruction
|= Rm
<< 3;
12049 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12050 inst
.instruction
= T_OPCODE_MOV_HR
;
12052 inst
.instruction
= T_OPCODE_CMP_HR
;
12058 constraint (Rn
> 7,
12059 _("only lo regs allowed with immediate"));
12060 inst
.instruction
|= Rn
<< 8;
12061 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12072 top
= (inst
.instruction
& 0x00800000) != 0;
12073 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12075 constraint (top
, _(":lower16: not allowed this instruction"));
12076 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12078 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12080 constraint (!top
, _(":upper16: not allowed this instruction"));
12081 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12084 Rd
= inst
.operands
[0].reg
;
12085 reject_bad_reg (Rd
);
12087 inst
.instruction
|= Rd
<< 8;
12088 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12090 imm
= inst
.reloc
.exp
.X_add_number
;
12091 inst
.instruction
|= (imm
& 0xf000) << 4;
12092 inst
.instruction
|= (imm
& 0x0800) << 15;
12093 inst
.instruction
|= (imm
& 0x0700) << 4;
12094 inst
.instruction
|= (imm
& 0x00ff);
12099 do_t_mvn_tst (void)
12103 Rn
= inst
.operands
[0].reg
;
12104 Rm
= inst
.operands
[1].reg
;
12106 if (inst
.instruction
== T_MNEM_cmp
12107 || inst
.instruction
== T_MNEM_cmn
)
12108 constraint (Rn
== REG_PC
, BAD_PC
);
12110 reject_bad_reg (Rn
);
12111 reject_bad_reg (Rm
);
12113 if (unified_syntax
)
12115 int r0off
= (inst
.instruction
== T_MNEM_mvn
12116 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12117 bfd_boolean narrow
;
12119 if (inst
.size_req
== 4
12120 || inst
.instruction
> 0xffff
12121 || inst
.operands
[1].shifted
12122 || Rn
> 7 || Rm
> 7)
12124 else if (inst
.instruction
== T_MNEM_cmn
12125 || inst
.instruction
== T_MNEM_tst
)
12127 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12128 narrow
= !in_it_block ();
12130 narrow
= in_it_block ();
12132 if (!inst
.operands
[1].isreg
)
12134 /* For an immediate, we always generate a 32-bit opcode;
12135 section relaxation will shrink it later if possible. */
12136 if (inst
.instruction
< 0xffff)
12137 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12138 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12139 inst
.instruction
|= Rn
<< r0off
;
12140 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12144 /* See if we can do this with a 16-bit instruction. */
12147 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12148 inst
.instruction
|= Rn
;
12149 inst
.instruction
|= Rm
<< 3;
12153 constraint (inst
.operands
[1].shifted
12154 && inst
.operands
[1].immisreg
,
12155 _("shift must be constant"));
12156 if (inst
.instruction
< 0xffff)
12157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12158 inst
.instruction
|= Rn
<< r0off
;
12159 encode_thumb32_shifted_operand (1);
12165 constraint (inst
.instruction
> 0xffff
12166 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12167 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12168 _("unshifted register required"));
12169 constraint (Rn
> 7 || Rm
> 7,
12172 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12173 inst
.instruction
|= Rn
;
12174 inst
.instruction
|= Rm
<< 3;
12183 if (do_vfp_nsyn_mrs () == SUCCESS
)
12186 Rd
= inst
.operands
[0].reg
;
12187 reject_bad_reg (Rd
);
12188 inst
.instruction
|= Rd
<< 8;
12190 if (inst
.operands
[1].isreg
)
12192 unsigned br
= inst
.operands
[1].reg
;
12193 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12194 as_bad (_("bad register for mrs"));
12196 inst
.instruction
|= br
& (0xf << 16);
12197 inst
.instruction
|= (br
& 0x300) >> 4;
12198 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12202 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12204 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12206 /* PR gas/12698: The constraint is only applied for m_profile.
12207 If the user has specified -march=all, we want to ignore it as
12208 we are building for any CPU type, including non-m variants. */
12209 bfd_boolean m_profile
=
12210 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12211 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12212 "not support requested special purpose register"));
12215 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12217 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12218 _("'APSR', 'CPSR' or 'SPSR' expected"));
12220 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12221 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12222 inst
.instruction
|= 0xf0000;
12232 if (do_vfp_nsyn_msr () == SUCCESS
)
12235 constraint (!inst
.operands
[1].isreg
,
12236 _("Thumb encoding does not support an immediate here"));
12238 if (inst
.operands
[0].isreg
)
12239 flags
= (int)(inst
.operands
[0].reg
);
12241 flags
= inst
.operands
[0].imm
;
12243 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12245 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12247 /* PR gas/12698: The constraint is only applied for m_profile.
12248 If the user has specified -march=all, we want to ignore it as
12249 we are building for any CPU type, including non-m variants. */
12250 bfd_boolean m_profile
=
12251 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12252 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12253 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12254 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12255 && bits
!= PSR_f
)) && m_profile
,
12256 _("selected processor does not support requested special "
12257 "purpose register"));
12260 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12261 "requested special purpose register"));
12263 Rn
= inst
.operands
[1].reg
;
12264 reject_bad_reg (Rn
);
12266 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12267 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12268 inst
.instruction
|= (flags
& 0x300) >> 4;
12269 inst
.instruction
|= (flags
& 0xff);
12270 inst
.instruction
|= Rn
<< 16;
12276 bfd_boolean narrow
;
12277 unsigned Rd
, Rn
, Rm
;
12279 if (!inst
.operands
[2].present
)
12280 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12282 Rd
= inst
.operands
[0].reg
;
12283 Rn
= inst
.operands
[1].reg
;
12284 Rm
= inst
.operands
[2].reg
;
12286 if (unified_syntax
)
12288 if (inst
.size_req
== 4
12294 else if (inst
.instruction
== T_MNEM_muls
)
12295 narrow
= !in_it_block ();
12297 narrow
= in_it_block ();
12301 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12302 constraint (Rn
> 7 || Rm
> 7,
12309 /* 16-bit MULS/Conditional MUL. */
12310 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12311 inst
.instruction
|= Rd
;
12314 inst
.instruction
|= Rm
<< 3;
12316 inst
.instruction
|= Rn
<< 3;
12318 constraint (1, _("dest must overlap one source register"));
12322 constraint (inst
.instruction
!= T_MNEM_mul
,
12323 _("Thumb-2 MUL must not set flags"));
12325 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12326 inst
.instruction
|= Rd
<< 8;
12327 inst
.instruction
|= Rn
<< 16;
12328 inst
.instruction
|= Rm
<< 0;
12330 reject_bad_reg (Rd
);
12331 reject_bad_reg (Rn
);
12332 reject_bad_reg (Rm
);
12339 unsigned RdLo
, RdHi
, Rn
, Rm
;
12341 RdLo
= inst
.operands
[0].reg
;
12342 RdHi
= inst
.operands
[1].reg
;
12343 Rn
= inst
.operands
[2].reg
;
12344 Rm
= inst
.operands
[3].reg
;
12346 reject_bad_reg (RdLo
);
12347 reject_bad_reg (RdHi
);
12348 reject_bad_reg (Rn
);
12349 reject_bad_reg (Rm
);
12351 inst
.instruction
|= RdLo
<< 12;
12352 inst
.instruction
|= RdHi
<< 8;
12353 inst
.instruction
|= Rn
<< 16;
12354 inst
.instruction
|= Rm
;
12357 as_tsktsk (_("rdhi and rdlo must be different"));
12363 set_it_insn_type (NEUTRAL_IT_INSN
);
12365 if (unified_syntax
)
12367 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12369 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12370 inst
.instruction
|= inst
.operands
[0].imm
;
12374 /* PR9722: Check for Thumb2 availability before
12375 generating a thumb2 nop instruction. */
12376 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12378 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12379 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12382 inst
.instruction
= 0x46c0;
12387 constraint (inst
.operands
[0].present
,
12388 _("Thumb does not support NOP with hints"));
12389 inst
.instruction
= 0x46c0;
12396 if (unified_syntax
)
12398 bfd_boolean narrow
;
12400 if (THUMB_SETS_FLAGS (inst
.instruction
))
12401 narrow
= !in_it_block ();
12403 narrow
= in_it_block ();
12404 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12406 if (inst
.size_req
== 4)
12411 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12412 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12413 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12417 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12418 inst
.instruction
|= inst
.operands
[0].reg
;
12419 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12424 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12426 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12428 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12429 inst
.instruction
|= inst
.operands
[0].reg
;
12430 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12439 Rd
= inst
.operands
[0].reg
;
12440 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12442 reject_bad_reg (Rd
);
12443 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12444 reject_bad_reg (Rn
);
12446 inst
.instruction
|= Rd
<< 8;
12447 inst
.instruction
|= Rn
<< 16;
12449 if (!inst
.operands
[2].isreg
)
12451 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12452 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12458 Rm
= inst
.operands
[2].reg
;
12459 reject_bad_reg (Rm
);
12461 constraint (inst
.operands
[2].shifted
12462 && inst
.operands
[2].immisreg
,
12463 _("shift must be constant"));
12464 encode_thumb32_shifted_operand (2);
12471 unsigned Rd
, Rn
, Rm
;
12473 Rd
= inst
.operands
[0].reg
;
12474 Rn
= inst
.operands
[1].reg
;
12475 Rm
= inst
.operands
[2].reg
;
12477 reject_bad_reg (Rd
);
12478 reject_bad_reg (Rn
);
12479 reject_bad_reg (Rm
);
12481 inst
.instruction
|= Rd
<< 8;
12482 inst
.instruction
|= Rn
<< 16;
12483 inst
.instruction
|= Rm
;
12484 if (inst
.operands
[3].present
)
12486 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12487 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12488 _("expression too complex"));
12489 inst
.instruction
|= (val
& 0x1c) << 10;
12490 inst
.instruction
|= (val
& 0x03) << 6;
12497 if (!inst
.operands
[3].present
)
12501 inst
.instruction
&= ~0x00000020;
12503 /* PR 10168. Swap the Rm and Rn registers. */
12504 Rtmp
= inst
.operands
[1].reg
;
12505 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12506 inst
.operands
[2].reg
= Rtmp
;
12514 if (inst
.operands
[0].immisreg
)
12515 reject_bad_reg (inst
.operands
[0].imm
);
12517 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12521 do_t_push_pop (void)
12525 constraint (inst
.operands
[0].writeback
,
12526 _("push/pop do not support {reglist}^"));
12527 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12528 _("expression too complex"));
12530 mask
= inst
.operands
[0].imm
;
12531 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12532 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12533 else if (inst
.size_req
!= 4
12534 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12535 ? REG_LR
: REG_PC
)))
12537 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12538 inst
.instruction
|= THUMB_PP_PC_LR
;
12539 inst
.instruction
|= mask
& 0xff;
12541 else if (unified_syntax
)
12543 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12544 encode_thumb2_ldmstm (13, mask
, TRUE
);
12548 inst
.error
= _("invalid register list to push/pop instruction");
12558 Rd
= inst
.operands
[0].reg
;
12559 Rm
= inst
.operands
[1].reg
;
12561 reject_bad_reg (Rd
);
12562 reject_bad_reg (Rm
);
12564 inst
.instruction
|= Rd
<< 8;
12565 inst
.instruction
|= Rm
<< 16;
12566 inst
.instruction
|= Rm
;
12574 Rd
= inst
.operands
[0].reg
;
12575 Rm
= inst
.operands
[1].reg
;
12577 reject_bad_reg (Rd
);
12578 reject_bad_reg (Rm
);
12580 if (Rd
<= 7 && Rm
<= 7
12581 && inst
.size_req
!= 4)
12583 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12584 inst
.instruction
|= Rd
;
12585 inst
.instruction
|= Rm
<< 3;
12587 else if (unified_syntax
)
12589 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12590 inst
.instruction
|= Rd
<< 8;
12591 inst
.instruction
|= Rm
<< 16;
12592 inst
.instruction
|= Rm
;
12595 inst
.error
= BAD_HIREG
;
12603 Rd
= inst
.operands
[0].reg
;
12604 Rm
= inst
.operands
[1].reg
;
12606 reject_bad_reg (Rd
);
12607 reject_bad_reg (Rm
);
12609 inst
.instruction
|= Rd
<< 8;
12610 inst
.instruction
|= Rm
;
12618 Rd
= inst
.operands
[0].reg
;
12619 Rs
= (inst
.operands
[1].present
12620 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12621 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12623 reject_bad_reg (Rd
);
12624 reject_bad_reg (Rs
);
12625 if (inst
.operands
[2].isreg
)
12626 reject_bad_reg (inst
.operands
[2].reg
);
12628 inst
.instruction
|= Rd
<< 8;
12629 inst
.instruction
|= Rs
<< 16;
12630 if (!inst
.operands
[2].isreg
)
12632 bfd_boolean narrow
;
12634 if ((inst
.instruction
& 0x00100000) != 0)
12635 narrow
= !in_it_block ();
12637 narrow
= in_it_block ();
12639 if (Rd
> 7 || Rs
> 7)
12642 if (inst
.size_req
== 4 || !unified_syntax
)
12645 if (inst
.reloc
.exp
.X_op
!= O_constant
12646 || inst
.reloc
.exp
.X_add_number
!= 0)
12649 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12650 relaxation, but it doesn't seem worth the hassle. */
12653 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12654 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12655 inst
.instruction
|= Rs
<< 3;
12656 inst
.instruction
|= Rd
;
12660 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12661 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12665 encode_thumb32_shifted_operand (2);
12671 if (warn_on_deprecated
12672 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12673 as_tsktsk (_("setend use is deprecated for ARMv8"));
12675 set_it_insn_type (OUTSIDE_IT_INSN
);
12676 if (inst
.operands
[0].imm
)
12677 inst
.instruction
|= 0x8;
12683 if (!inst
.operands
[1].present
)
12684 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12686 if (unified_syntax
)
12688 bfd_boolean narrow
;
12691 switch (inst
.instruction
)
12694 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12696 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12698 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12700 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12704 if (THUMB_SETS_FLAGS (inst
.instruction
))
12705 narrow
= !in_it_block ();
12707 narrow
= in_it_block ();
12708 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12710 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12712 if (inst
.operands
[2].isreg
12713 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12714 || inst
.operands
[2].reg
> 7))
12716 if (inst
.size_req
== 4)
12719 reject_bad_reg (inst
.operands
[0].reg
);
12720 reject_bad_reg (inst
.operands
[1].reg
);
12724 if (inst
.operands
[2].isreg
)
12726 reject_bad_reg (inst
.operands
[2].reg
);
12727 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12728 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12729 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12730 inst
.instruction
|= inst
.operands
[2].reg
;
12732 /* PR 12854: Error on extraneous shifts. */
12733 constraint (inst
.operands
[2].shifted
,
12734 _("extraneous shift as part of operand to shift insn"));
12738 inst
.operands
[1].shifted
= 1;
12739 inst
.operands
[1].shift_kind
= shift_kind
;
12740 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12741 ? T_MNEM_movs
: T_MNEM_mov
);
12742 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12743 encode_thumb32_shifted_operand (1);
12744 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12745 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12750 if (inst
.operands
[2].isreg
)
12752 switch (shift_kind
)
12754 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12755 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12756 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12757 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12761 inst
.instruction
|= inst
.operands
[0].reg
;
12762 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12764 /* PR 12854: Error on extraneous shifts. */
12765 constraint (inst
.operands
[2].shifted
,
12766 _("extraneous shift as part of operand to shift insn"));
12770 switch (shift_kind
)
12772 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12773 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12774 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12777 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12778 inst
.instruction
|= inst
.operands
[0].reg
;
12779 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12785 constraint (inst
.operands
[0].reg
> 7
12786 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12787 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12789 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12791 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12792 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12793 _("source1 and dest must be same register"));
12795 switch (inst
.instruction
)
12797 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12798 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12799 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12800 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12804 inst
.instruction
|= inst
.operands
[0].reg
;
12805 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12807 /* PR 12854: Error on extraneous shifts. */
12808 constraint (inst
.operands
[2].shifted
,
12809 _("extraneous shift as part of operand to shift insn"));
12813 switch (inst
.instruction
)
12815 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12816 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12817 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12818 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12821 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12822 inst
.instruction
|= inst
.operands
[0].reg
;
12823 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12831 unsigned Rd
, Rn
, Rm
;
12833 Rd
= inst
.operands
[0].reg
;
12834 Rn
= inst
.operands
[1].reg
;
12835 Rm
= inst
.operands
[2].reg
;
12837 reject_bad_reg (Rd
);
12838 reject_bad_reg (Rn
);
12839 reject_bad_reg (Rm
);
12841 inst
.instruction
|= Rd
<< 8;
12842 inst
.instruction
|= Rn
<< 16;
12843 inst
.instruction
|= Rm
;
12849 unsigned Rd
, Rn
, Rm
;
12851 Rd
= inst
.operands
[0].reg
;
12852 Rm
= inst
.operands
[1].reg
;
12853 Rn
= inst
.operands
[2].reg
;
12855 reject_bad_reg (Rd
);
12856 reject_bad_reg (Rn
);
12857 reject_bad_reg (Rm
);
12859 inst
.instruction
|= Rd
<< 8;
12860 inst
.instruction
|= Rn
<< 16;
12861 inst
.instruction
|= Rm
;
12867 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12868 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12869 _("SMC is not permitted on this architecture"));
12870 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12871 _("expression too complex"));
12872 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12873 inst
.instruction
|= (value
& 0xf000) >> 12;
12874 inst
.instruction
|= (value
& 0x0ff0);
12875 inst
.instruction
|= (value
& 0x000f) << 16;
12876 /* PR gas/15623: SMC instructions must be last in an IT block. */
12877 set_it_insn_type_last ();
12883 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12885 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12886 inst
.instruction
|= (value
& 0x0fff);
12887 inst
.instruction
|= (value
& 0xf000) << 4;
12891 do_t_ssat_usat (int bias
)
12895 Rd
= inst
.operands
[0].reg
;
12896 Rn
= inst
.operands
[2].reg
;
12898 reject_bad_reg (Rd
);
12899 reject_bad_reg (Rn
);
12901 inst
.instruction
|= Rd
<< 8;
12902 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12903 inst
.instruction
|= Rn
<< 16;
12905 if (inst
.operands
[3].present
)
12907 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12909 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12911 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12912 _("expression too complex"));
12914 if (shift_amount
!= 0)
12916 constraint (shift_amount
> 31,
12917 _("shift expression is too large"));
12919 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12920 inst
.instruction
|= 0x00200000; /* sh bit. */
12922 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12923 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12931 do_t_ssat_usat (1);
12939 Rd
= inst
.operands
[0].reg
;
12940 Rn
= inst
.operands
[2].reg
;
12942 reject_bad_reg (Rd
);
12943 reject_bad_reg (Rn
);
12945 inst
.instruction
|= Rd
<< 8;
12946 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12947 inst
.instruction
|= Rn
<< 16;
12953 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12954 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12955 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12956 || inst
.operands
[2].negative
,
12959 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12961 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12962 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12963 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12964 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12970 if (!inst
.operands
[2].present
)
12971 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12973 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12974 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12975 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12978 inst
.instruction
|= inst
.operands
[0].reg
;
12979 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12980 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12981 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12987 unsigned Rd
, Rn
, Rm
;
12989 Rd
= inst
.operands
[0].reg
;
12990 Rn
= inst
.operands
[1].reg
;
12991 Rm
= inst
.operands
[2].reg
;
12993 reject_bad_reg (Rd
);
12994 reject_bad_reg (Rn
);
12995 reject_bad_reg (Rm
);
12997 inst
.instruction
|= Rd
<< 8;
12998 inst
.instruction
|= Rn
<< 16;
12999 inst
.instruction
|= Rm
;
13000 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13008 Rd
= inst
.operands
[0].reg
;
13009 Rm
= inst
.operands
[1].reg
;
13011 reject_bad_reg (Rd
);
13012 reject_bad_reg (Rm
);
13014 if (inst
.instruction
<= 0xffff
13015 && inst
.size_req
!= 4
13016 && Rd
<= 7 && Rm
<= 7
13017 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13019 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13020 inst
.instruction
|= Rd
;
13021 inst
.instruction
|= Rm
<< 3;
13023 else if (unified_syntax
)
13025 if (inst
.instruction
<= 0xffff)
13026 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13027 inst
.instruction
|= Rd
<< 8;
13028 inst
.instruction
|= Rm
;
13029 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13033 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13034 _("Thumb encoding does not support rotation"));
13035 constraint (1, BAD_HIREG
);
13042 /* We have to do the following check manually as ARM_EXT_OS only applies
13044 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13046 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13047 /* This only applies to the v6m howver, not later architectures. */
13048 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13049 as_bad (_("SVC is not permitted on this architecture"));
13050 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13053 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13062 half
= (inst
.instruction
& 0x10) != 0;
13063 set_it_insn_type_last ();
13064 constraint (inst
.operands
[0].immisreg
,
13065 _("instruction requires register index"));
13067 Rn
= inst
.operands
[0].reg
;
13068 Rm
= inst
.operands
[0].imm
;
13070 constraint (Rn
== REG_SP
, BAD_SP
);
13071 reject_bad_reg (Rm
);
13073 constraint (!half
&& inst
.operands
[0].shifted
,
13074 _("instruction does not allow shifted index"));
13075 inst
.instruction
|= (Rn
<< 16) | Rm
;
13081 if (!inst
.operands
[0].present
)
13082 inst
.operands
[0].imm
= 0;
13084 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13086 constraint (inst
.size_req
== 2,
13087 _("immediate value out of range"));
13088 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13089 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13090 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13094 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13095 inst
.instruction
|= inst
.operands
[0].imm
;
13098 set_it_insn_type (NEUTRAL_IT_INSN
);
13105 do_t_ssat_usat (0);
13113 Rd
= inst
.operands
[0].reg
;
13114 Rn
= inst
.operands
[2].reg
;
13116 reject_bad_reg (Rd
);
13117 reject_bad_reg (Rn
);
13119 inst
.instruction
|= Rd
<< 8;
13120 inst
.instruction
|= inst
.operands
[1].imm
;
13121 inst
.instruction
|= Rn
<< 16;
13124 /* Neon instruction encoder helpers. */
13126 /* Encodings for the different types for various Neon opcodes. */
13128 /* An "invalid" code for the following tables. */
13131 struct neon_tab_entry
13134 unsigned float_or_poly
;
13135 unsigned scalar_or_imm
;
13138 /* Map overloaded Neon opcodes to their respective encodings. */
13139 #define NEON_ENC_TAB \
13140 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13141 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13142 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13143 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13144 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13145 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13146 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13147 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13148 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13149 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13150 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13151 /* Register variants of the following two instructions are encoded as
13152 vcge / vcgt with the operands reversed. */ \
13153 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13154 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13155 X(vfma, N_INV, 0x0000c10, N_INV), \
13156 X(vfms, N_INV, 0x0200c10, N_INV), \
13157 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13158 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13159 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13160 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13161 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13162 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13163 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13164 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13165 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13166 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13167 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13168 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13169 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13170 X(vshl, 0x0000400, N_INV, 0x0800510), \
13171 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13172 X(vand, 0x0000110, N_INV, 0x0800030), \
13173 X(vbic, 0x0100110, N_INV, 0x0800030), \
13174 X(veor, 0x1000110, N_INV, N_INV), \
13175 X(vorn, 0x0300110, N_INV, 0x0800010), \
13176 X(vorr, 0x0200110, N_INV, 0x0800010), \
13177 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13178 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13179 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13180 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13181 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13182 X(vst1, 0x0000000, 0x0800000, N_INV), \
13183 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13184 X(vst2, 0x0000100, 0x0800100, N_INV), \
13185 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13186 X(vst3, 0x0000200, 0x0800200, N_INV), \
13187 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13188 X(vst4, 0x0000300, 0x0800300, N_INV), \
13189 X(vmovn, 0x1b20200, N_INV, N_INV), \
13190 X(vtrn, 0x1b20080, N_INV, N_INV), \
13191 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13192 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13193 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13194 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13195 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13196 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13197 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13198 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13199 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13200 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13201 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13202 X(vseleq, 0xe000a00, N_INV, N_INV), \
13203 X(vselvs, 0xe100a00, N_INV, N_INV), \
13204 X(vselge, 0xe200a00, N_INV, N_INV), \
13205 X(vselgt, 0xe300a00, N_INV, N_INV), \
13206 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13207 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13208 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13209 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13210 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13211 X(aes, 0x3b00300, N_INV, N_INV), \
13212 X(sha3op, 0x2000c00, N_INV, N_INV), \
13213 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13214 X(sha2op, 0x3ba0380, N_INV, N_INV)
13218 #define X(OPC,I,F,S) N_MNEM_##OPC
13223 static const struct neon_tab_entry neon_enc_tab
[] =
13225 #define X(OPC,I,F,S) { (I), (F), (S) }
13230 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13231 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13232 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13233 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13234 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13235 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13236 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13237 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13238 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13239 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13240 #define NEON_ENC_SINGLE_(X) \
13241 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13242 #define NEON_ENC_DOUBLE_(X) \
13243 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13244 #define NEON_ENC_FPV8_(X) \
13245 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13247 #define NEON_ENCODE(type, inst) \
13250 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13251 inst.is_neon = 1; \
13255 #define check_neon_suffixes \
13258 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13260 as_bad (_("invalid neon suffix for non neon instruction")); \
13266 /* Define shapes for instruction operands. The following mnemonic characters
13267 are used in this table:
13269 F - VFP S<n> register
13270 D - Neon D<n> register
13271 Q - Neon Q<n> register
13275 L - D<n> register list
13277 This table is used to generate various data:
13278 - enumerations of the form NS_DDR to be used as arguments to
13280 - a table classifying shapes into single, double, quad, mixed.
13281 - a table used to drive neon_select_shape. */
13283 #define NEON_SHAPE_DEF \
13284 X(3, (D, D, D), DOUBLE), \
13285 X(3, (Q, Q, Q), QUAD), \
13286 X(3, (D, D, I), DOUBLE), \
13287 X(3, (Q, Q, I), QUAD), \
13288 X(3, (D, D, S), DOUBLE), \
13289 X(3, (Q, Q, S), QUAD), \
13290 X(2, (D, D), DOUBLE), \
13291 X(2, (Q, Q), QUAD), \
13292 X(2, (D, S), DOUBLE), \
13293 X(2, (Q, S), QUAD), \
13294 X(2, (D, R), DOUBLE), \
13295 X(2, (Q, R), QUAD), \
13296 X(2, (D, I), DOUBLE), \
13297 X(2, (Q, I), QUAD), \
13298 X(3, (D, L, D), DOUBLE), \
13299 X(2, (D, Q), MIXED), \
13300 X(2, (Q, D), MIXED), \
13301 X(3, (D, Q, I), MIXED), \
13302 X(3, (Q, D, I), MIXED), \
13303 X(3, (Q, D, D), MIXED), \
13304 X(3, (D, Q, Q), MIXED), \
13305 X(3, (Q, Q, D), MIXED), \
13306 X(3, (Q, D, S), MIXED), \
13307 X(3, (D, Q, S), MIXED), \
13308 X(4, (D, D, D, I), DOUBLE), \
13309 X(4, (Q, Q, Q, I), QUAD), \
13310 X(2, (F, F), SINGLE), \
13311 X(3, (F, F, F), SINGLE), \
13312 X(2, (F, I), SINGLE), \
13313 X(2, (F, D), MIXED), \
13314 X(2, (D, F), MIXED), \
13315 X(3, (F, F, I), MIXED), \
13316 X(4, (R, R, F, F), SINGLE), \
13317 X(4, (F, F, R, R), SINGLE), \
13318 X(3, (D, R, R), DOUBLE), \
13319 X(3, (R, R, D), DOUBLE), \
13320 X(2, (S, R), SINGLE), \
13321 X(2, (R, S), SINGLE), \
13322 X(2, (F, R), SINGLE), \
13323 X(2, (R, F), SINGLE), \
13324 /* Half float shape supported so far. */\
13325 X (2, (H, D), MIXED), \
13326 X (2, (D, H), MIXED), \
13327 X (2, (H, F), MIXED), \
13328 X (2, (F, H), MIXED), \
13329 X (2, (H, H), HALF), \
13330 X (2, (H, R), HALF), \
13331 X (2, (R, H), HALF), \
13332 X (2, (H, I), HALF), \
13333 X (3, (H, H, H), HALF), \
13334 X (3, (H, F, I), MIXED), \
13335 X (3, (F, H, I), MIXED)
13337 #define S2(A,B) NS_##A##B
13338 #define S3(A,B,C) NS_##A##B##C
13339 #define S4(A,B,C,D) NS_##A##B##C##D
13341 #define X(N, L, C) S##N L
13354 enum neon_shape_class
13363 #define X(N, L, C) SC_##C
13365 static enum neon_shape_class neon_shape_class
[] =
13384 /* Register widths of above. */
13385 static unsigned neon_shape_el_size
[] =
13397 struct neon_shape_info
13400 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13403 #define S2(A,B) { SE_##A, SE_##B }
13404 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13405 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13407 #define X(N, L, C) { N, S##N L }
13409 static struct neon_shape_info neon_shape_tab
[] =
13419 /* Bit masks used in type checking given instructions.
13420 'N_EQK' means the type must be the same as (or based on in some way) the key
13421 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13422 set, various other bits can be set as well in order to modify the meaning of
13423 the type constraint. */
13425 enum neon_type_mask
13449 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13450 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13451 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13452 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13453 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13454 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13455 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13456 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13457 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13458 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13459 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13461 N_MAX_NONSPECIAL
= N_P64
13464 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13466 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13467 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13468 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13469 #define N_S_32 (N_S8 | N_S16 | N_S32)
13470 #define N_F_16_32 (N_F16 | N_F32)
13471 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13472 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13473 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13474 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13476 /* Pass this as the first type argument to neon_check_type to ignore types
13478 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13480 /* Select a "shape" for the current instruction (describing register types or
13481 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13482 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13483 function of operand parsing, so this function doesn't need to be called.
13484 Shapes should be listed in order of decreasing length. */
13486 static enum neon_shape
13487 neon_select_shape (enum neon_shape shape
, ...)
13490 enum neon_shape first_shape
= shape
;
13492 /* Fix missing optional operands. FIXME: we don't know at this point how
13493 many arguments we should have, so this makes the assumption that we have
13494 > 1. This is true of all current Neon opcodes, I think, but may not be
13495 true in the future. */
13496 if (!inst
.operands
[1].present
)
13497 inst
.operands
[1] = inst
.operands
[0];
13499 va_start (ap
, shape
);
13501 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13506 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13508 if (!inst
.operands
[j
].present
)
13514 switch (neon_shape_tab
[shape
].el
[j
])
13516 /* If a .f16, .16, .u16, .s16 type specifier is given over
13517 a VFP single precision register operand, it's essentially
13518 means only half of the register is used.
13520 If the type specifier is given after the mnemonics, the
13521 information is stored in inst.vectype. If the type specifier
13522 is given after register operand, the information is stored
13523 in inst.operands[].vectype.
13525 When there is only one type specifier, and all the register
13526 operands are the same type of hardware register, the type
13527 specifier applies to all register operands.
13529 If no type specifier is given, the shape is inferred from
13530 operand information.
13533 vadd.f16 s0, s1, s2: NS_HHH
13534 vabs.f16 s0, s1: NS_HH
13535 vmov.f16 s0, r1: NS_HR
13536 vmov.f16 r0, s1: NS_RH
13537 vcvt.f16 r0, s1: NS_RH
13538 vcvt.f16.s32 s2, s2, #29: NS_HFI
13539 vcvt.f16.s32 s2, s2: NS_HF
13542 if (!(inst
.operands
[j
].isreg
13543 && inst
.operands
[j
].isvec
13544 && inst
.operands
[j
].issingle
13545 && !inst
.operands
[j
].isquad
13546 && ((inst
.vectype
.elems
== 1
13547 && inst
.vectype
.el
[0].size
== 16)
13548 || (inst
.vectype
.elems
> 1
13549 && inst
.vectype
.el
[j
].size
== 16)
13550 || (inst
.vectype
.elems
== 0
13551 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13552 && inst
.operands
[j
].vectype
.size
== 16))))
13557 if (!(inst
.operands
[j
].isreg
13558 && inst
.operands
[j
].isvec
13559 && inst
.operands
[j
].issingle
13560 && !inst
.operands
[j
].isquad
13561 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13562 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13563 || (inst
.vectype
.elems
== 0
13564 && (inst
.operands
[j
].vectype
.size
== 32
13565 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13570 if (!(inst
.operands
[j
].isreg
13571 && inst
.operands
[j
].isvec
13572 && !inst
.operands
[j
].isquad
13573 && !inst
.operands
[j
].issingle
))
13578 if (!(inst
.operands
[j
].isreg
13579 && !inst
.operands
[j
].isvec
))
13584 if (!(inst
.operands
[j
].isreg
13585 && inst
.operands
[j
].isvec
13586 && inst
.operands
[j
].isquad
13587 && !inst
.operands
[j
].issingle
))
13592 if (!(!inst
.operands
[j
].isreg
13593 && !inst
.operands
[j
].isscalar
))
13598 if (!(!inst
.operands
[j
].isreg
13599 && inst
.operands
[j
].isscalar
))
13609 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13610 /* We've matched all the entries in the shape table, and we don't
13611 have any left over operands which have not been matched. */
13617 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13618 first_error (_("invalid instruction shape"));
13623 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13624 means the Q bit should be set). */
13627 neon_quad (enum neon_shape shape
)
13629 return neon_shape_class
[shape
] == SC_QUAD
;
13633 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13636 /* Allow modification to be made to types which are constrained to be
13637 based on the key element, based on bits set alongside N_EQK. */
13638 if ((typebits
& N_EQK
) != 0)
13640 if ((typebits
& N_HLF
) != 0)
13642 else if ((typebits
& N_DBL
) != 0)
13644 if ((typebits
& N_SGN
) != 0)
13645 *g_type
= NT_signed
;
13646 else if ((typebits
& N_UNS
) != 0)
13647 *g_type
= NT_unsigned
;
13648 else if ((typebits
& N_INT
) != 0)
13649 *g_type
= NT_integer
;
13650 else if ((typebits
& N_FLT
) != 0)
13651 *g_type
= NT_float
;
13652 else if ((typebits
& N_SIZ
) != 0)
13653 *g_type
= NT_untyped
;
13657 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13658 operand type, i.e. the single type specified in a Neon instruction when it
13659 is the only one given. */
13661 static struct neon_type_el
13662 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13664 struct neon_type_el dest
= *key
;
13666 gas_assert ((thisarg
& N_EQK
) != 0);
13668 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13673 /* Convert Neon type and size into compact bitmask representation. */
13675 static enum neon_type_mask
13676 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13683 case 8: return N_8
;
13684 case 16: return N_16
;
13685 case 32: return N_32
;
13686 case 64: return N_64
;
13694 case 8: return N_I8
;
13695 case 16: return N_I16
;
13696 case 32: return N_I32
;
13697 case 64: return N_I64
;
13705 case 16: return N_F16
;
13706 case 32: return N_F32
;
13707 case 64: return N_F64
;
13715 case 8: return N_P8
;
13716 case 16: return N_P16
;
13717 case 64: return N_P64
;
13725 case 8: return N_S8
;
13726 case 16: return N_S16
;
13727 case 32: return N_S32
;
13728 case 64: return N_S64
;
13736 case 8: return N_U8
;
13737 case 16: return N_U16
;
13738 case 32: return N_U32
;
13739 case 64: return N_U64
;
13750 /* Convert compact Neon bitmask type representation to a type and size. Only
13751 handles the case where a single bit is set in the mask. */
13754 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13755 enum neon_type_mask mask
)
13757 if ((mask
& N_EQK
) != 0)
13760 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13762 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13764 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13766 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13771 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13773 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13774 *type
= NT_unsigned
;
13775 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13776 *type
= NT_integer
;
13777 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13778 *type
= NT_untyped
;
13779 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13781 else if ((mask
& (N_F_ALL
)) != 0)
13789 /* Modify a bitmask of allowed types. This is only needed for type
13793 modify_types_allowed (unsigned allowed
, unsigned mods
)
13796 enum neon_el_type type
;
13802 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13804 if (el_type_of_type_chk (&type
, &size
,
13805 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13807 neon_modify_type_size (mods
, &type
, &size
);
13808 destmask
|= type_chk_of_el_type (type
, size
);
13815 /* Check type and return type classification.
13816 The manual states (paraphrase): If one datatype is given, it indicates the
13818 - the second operand, if there is one
13819 - the operand, if there is no second operand
13820 - the result, if there are no operands.
13821 This isn't quite good enough though, so we use a concept of a "key" datatype
13822 which is set on a per-instruction basis, which is the one which matters when
13823 only one data type is written.
13824 Note: this function has side-effects (e.g. filling in missing operands). All
13825 Neon instructions should call it before performing bit encoding. */
13827 static struct neon_type_el
13828 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13831 unsigned i
, pass
, key_el
= 0;
13832 unsigned types
[NEON_MAX_TYPE_ELS
];
13833 enum neon_el_type k_type
= NT_invtype
;
13834 unsigned k_size
= -1u;
13835 struct neon_type_el badtype
= {NT_invtype
, -1};
13836 unsigned key_allowed
= 0;
13838 /* Optional registers in Neon instructions are always (not) in operand 1.
13839 Fill in the missing operand here, if it was omitted. */
13840 if (els
> 1 && !inst
.operands
[1].present
)
13841 inst
.operands
[1] = inst
.operands
[0];
13843 /* Suck up all the varargs. */
13845 for (i
= 0; i
< els
; i
++)
13847 unsigned thisarg
= va_arg (ap
, unsigned);
13848 if (thisarg
== N_IGNORE_TYPE
)
13853 types
[i
] = thisarg
;
13854 if ((thisarg
& N_KEY
) != 0)
13859 if (inst
.vectype
.elems
> 0)
13860 for (i
= 0; i
< els
; i
++)
13861 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13863 first_error (_("types specified in both the mnemonic and operands"));
13867 /* Duplicate inst.vectype elements here as necessary.
13868 FIXME: No idea if this is exactly the same as the ARM assembler,
13869 particularly when an insn takes one register and one non-register
13871 if (inst
.vectype
.elems
== 1 && els
> 1)
13874 inst
.vectype
.elems
= els
;
13875 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13876 for (j
= 0; j
< els
; j
++)
13878 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13881 else if (inst
.vectype
.elems
== 0 && els
> 0)
13884 /* No types were given after the mnemonic, so look for types specified
13885 after each operand. We allow some flexibility here; as long as the
13886 "key" operand has a type, we can infer the others. */
13887 for (j
= 0; j
< els
; j
++)
13888 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13889 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13891 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13893 for (j
= 0; j
< els
; j
++)
13894 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13895 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13900 first_error (_("operand types can't be inferred"));
13904 else if (inst
.vectype
.elems
!= els
)
13906 first_error (_("type specifier has the wrong number of parts"));
13910 for (pass
= 0; pass
< 2; pass
++)
13912 for (i
= 0; i
< els
; i
++)
13914 unsigned thisarg
= types
[i
];
13915 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13916 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13917 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13918 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13920 /* Decay more-specific signed & unsigned types to sign-insensitive
13921 integer types if sign-specific variants are unavailable. */
13922 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13923 && (types_allowed
& N_SU_ALL
) == 0)
13924 g_type
= NT_integer
;
13926 /* If only untyped args are allowed, decay any more specific types to
13927 them. Some instructions only care about signs for some element
13928 sizes, so handle that properly. */
13929 if (((types_allowed
& N_UNT
) == 0)
13930 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13931 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13932 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13933 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13934 g_type
= NT_untyped
;
13938 if ((thisarg
& N_KEY
) != 0)
13942 key_allowed
= thisarg
& ~N_KEY
;
13944 /* Check architecture constraint on FP16 extension. */
13946 && k_type
== NT_float
13947 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13949 inst
.error
= _(BAD_FP16
);
13956 if ((thisarg
& N_VFP
) != 0)
13958 enum neon_shape_el regshape
;
13959 unsigned regwidth
, match
;
13961 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13964 first_error (_("invalid instruction shape"));
13967 regshape
= neon_shape_tab
[ns
].el
[i
];
13968 regwidth
= neon_shape_el_size
[regshape
];
13970 /* In VFP mode, operands must match register widths. If we
13971 have a key operand, use its width, else use the width of
13972 the current operand. */
13978 /* FP16 will use a single precision register. */
13979 if (regwidth
== 32 && match
== 16)
13981 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13985 inst
.error
= _(BAD_FP16
);
13990 if (regwidth
!= match
)
13992 first_error (_("operand size must match register width"));
13997 if ((thisarg
& N_EQK
) == 0)
13999 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14001 if ((given_type
& types_allowed
) == 0)
14003 first_error (_("bad type in Neon instruction"));
14009 enum neon_el_type mod_k_type
= k_type
;
14010 unsigned mod_k_size
= k_size
;
14011 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14012 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14014 first_error (_("inconsistent types in Neon instruction"));
14022 return inst
.vectype
.el
[key_el
];
14025 /* Neon-style VFP instruction forwarding. */
14027 /* Thumb VFP instructions have 0xE in the condition field. */
14030 do_vfp_cond_or_thumb (void)
14035 inst
.instruction
|= 0xe0000000;
14037 inst
.instruction
|= inst
.cond
<< 28;
14040 /* Look up and encode a simple mnemonic, for use as a helper function for the
14041 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14042 etc. It is assumed that operand parsing has already been done, and that the
14043 operands are in the form expected by the given opcode (this isn't necessarily
14044 the same as the form in which they were parsed, hence some massaging must
14045 take place before this function is called).
14046 Checks current arch version against that in the looked-up opcode. */
14049 do_vfp_nsyn_opcode (const char *opname
)
14051 const struct asm_opcode
*opcode
;
14053 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14058 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14059 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14066 inst
.instruction
= opcode
->tvalue
;
14067 opcode
->tencode ();
14071 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14072 opcode
->aencode ();
14077 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14079 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14081 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14084 do_vfp_nsyn_opcode ("fadds");
14086 do_vfp_nsyn_opcode ("fsubs");
14088 /* ARMv8.2 fp16 instruction. */
14090 do_scalar_fp16_v82_encode ();
14095 do_vfp_nsyn_opcode ("faddd");
14097 do_vfp_nsyn_opcode ("fsubd");
14101 /* Check operand types to see if this is a VFP instruction, and if so call
14105 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14107 enum neon_shape rs
;
14108 struct neon_type_el et
;
14113 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14114 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14118 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14119 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14120 N_F_ALL
| N_KEY
| N_VFP
);
14127 if (et
.type
!= NT_invtype
)
14138 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14140 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14142 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14145 do_vfp_nsyn_opcode ("fmacs");
14147 do_vfp_nsyn_opcode ("fnmacs");
14149 /* ARMv8.2 fp16 instruction. */
14151 do_scalar_fp16_v82_encode ();
14156 do_vfp_nsyn_opcode ("fmacd");
14158 do_vfp_nsyn_opcode ("fnmacd");
14163 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14165 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14167 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14170 do_vfp_nsyn_opcode ("ffmas");
14172 do_vfp_nsyn_opcode ("ffnmas");
14174 /* ARMv8.2 fp16 instruction. */
14176 do_scalar_fp16_v82_encode ();
14181 do_vfp_nsyn_opcode ("ffmad");
14183 do_vfp_nsyn_opcode ("ffnmad");
14188 do_vfp_nsyn_mul (enum neon_shape rs
)
14190 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14192 do_vfp_nsyn_opcode ("fmuls");
14194 /* ARMv8.2 fp16 instruction. */
14196 do_scalar_fp16_v82_encode ();
14199 do_vfp_nsyn_opcode ("fmuld");
14203 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14205 int is_neg
= (inst
.instruction
& 0x80) != 0;
14206 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14208 if (rs
== NS_FF
|| rs
== NS_HH
)
14211 do_vfp_nsyn_opcode ("fnegs");
14213 do_vfp_nsyn_opcode ("fabss");
14215 /* ARMv8.2 fp16 instruction. */
14217 do_scalar_fp16_v82_encode ();
14222 do_vfp_nsyn_opcode ("fnegd");
14224 do_vfp_nsyn_opcode ("fabsd");
14228 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14229 insns belong to Neon, and are handled elsewhere. */
14232 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14234 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14238 do_vfp_nsyn_opcode ("fldmdbs");
14240 do_vfp_nsyn_opcode ("fldmias");
14245 do_vfp_nsyn_opcode ("fstmdbs");
14247 do_vfp_nsyn_opcode ("fstmias");
14252 do_vfp_nsyn_sqrt (void)
14254 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14255 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14257 if (rs
== NS_FF
|| rs
== NS_HH
)
14259 do_vfp_nsyn_opcode ("fsqrts");
14261 /* ARMv8.2 fp16 instruction. */
14263 do_scalar_fp16_v82_encode ();
14266 do_vfp_nsyn_opcode ("fsqrtd");
14270 do_vfp_nsyn_div (void)
14272 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14273 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14274 N_F_ALL
| N_KEY
| N_VFP
);
14276 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14278 do_vfp_nsyn_opcode ("fdivs");
14280 /* ARMv8.2 fp16 instruction. */
14282 do_scalar_fp16_v82_encode ();
14285 do_vfp_nsyn_opcode ("fdivd");
14289 do_vfp_nsyn_nmul (void)
14291 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14292 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14293 N_F_ALL
| N_KEY
| N_VFP
);
14295 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14297 NEON_ENCODE (SINGLE
, inst
);
14298 do_vfp_sp_dyadic ();
14300 /* ARMv8.2 fp16 instruction. */
14302 do_scalar_fp16_v82_encode ();
14306 NEON_ENCODE (DOUBLE
, inst
);
14307 do_vfp_dp_rd_rn_rm ();
14309 do_vfp_cond_or_thumb ();
14314 do_vfp_nsyn_cmp (void)
14316 enum neon_shape rs
;
14317 if (inst
.operands
[1].isreg
)
14319 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14320 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14322 if (rs
== NS_FF
|| rs
== NS_HH
)
14324 NEON_ENCODE (SINGLE
, inst
);
14325 do_vfp_sp_monadic ();
14329 NEON_ENCODE (DOUBLE
, inst
);
14330 do_vfp_dp_rd_rm ();
14335 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14336 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14338 switch (inst
.instruction
& 0x0fffffff)
14341 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14344 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14350 if (rs
== NS_FI
|| rs
== NS_HI
)
14352 NEON_ENCODE (SINGLE
, inst
);
14353 do_vfp_sp_compare_z ();
14357 NEON_ENCODE (DOUBLE
, inst
);
14361 do_vfp_cond_or_thumb ();
14363 /* ARMv8.2 fp16 instruction. */
14364 if (rs
== NS_HI
|| rs
== NS_HH
)
14365 do_scalar_fp16_v82_encode ();
14369 nsyn_insert_sp (void)
14371 inst
.operands
[1] = inst
.operands
[0];
14372 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14373 inst
.operands
[0].reg
= REG_SP
;
14374 inst
.operands
[0].isreg
= 1;
14375 inst
.operands
[0].writeback
= 1;
14376 inst
.operands
[0].present
= 1;
14380 do_vfp_nsyn_push (void)
14383 if (inst
.operands
[1].issingle
)
14384 do_vfp_nsyn_opcode ("fstmdbs");
14386 do_vfp_nsyn_opcode ("fstmdbd");
14390 do_vfp_nsyn_pop (void)
14393 if (inst
.operands
[1].issingle
)
14394 do_vfp_nsyn_opcode ("fldmias");
14396 do_vfp_nsyn_opcode ("fldmiad");
14399 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14400 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14403 neon_dp_fixup (struct arm_it
* insn
)
14405 unsigned int i
= insn
->instruction
;
14410 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14421 insn
->instruction
= i
;
14424 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14428 neon_logbits (unsigned x
)
14430 return ffs (x
) - 4;
14433 #define LOW4(R) ((R) & 0xf)
14434 #define HI1(R) (((R) >> 4) & 1)
14436 /* Encode insns with bit pattern:
14438 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14439 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14441 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14442 different meaning for some instruction. */
14445 neon_three_same (int isquad
, int ubit
, int size
)
14447 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14448 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14449 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14450 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14451 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14452 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14453 inst
.instruction
|= (isquad
!= 0) << 6;
14454 inst
.instruction
|= (ubit
!= 0) << 24;
14456 inst
.instruction
|= neon_logbits (size
) << 20;
14458 neon_dp_fixup (&inst
);
14461 /* Encode instructions of the form:
14463 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14464 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14466 Don't write size if SIZE == -1. */
14469 neon_two_same (int qbit
, int ubit
, int size
)
14471 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14472 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14473 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14474 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14475 inst
.instruction
|= (qbit
!= 0) << 6;
14476 inst
.instruction
|= (ubit
!= 0) << 24;
14479 inst
.instruction
|= neon_logbits (size
) << 18;
14481 neon_dp_fixup (&inst
);
14484 /* Neon instruction encoders, in approximate order of appearance. */
14487 do_neon_dyadic_i_su (void)
14489 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14490 struct neon_type_el et
= neon_check_type (3, rs
,
14491 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14492 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14496 do_neon_dyadic_i64_su (void)
14498 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14499 struct neon_type_el et
= neon_check_type (3, rs
,
14500 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14501 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14505 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14508 unsigned size
= et
.size
>> 3;
14509 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14510 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14511 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14512 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14513 inst
.instruction
|= (isquad
!= 0) << 6;
14514 inst
.instruction
|= immbits
<< 16;
14515 inst
.instruction
|= (size
>> 3) << 7;
14516 inst
.instruction
|= (size
& 0x7) << 19;
14518 inst
.instruction
|= (uval
!= 0) << 24;
14520 neon_dp_fixup (&inst
);
14524 do_neon_shl_imm (void)
14526 if (!inst
.operands
[2].isreg
)
14528 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14529 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14530 int imm
= inst
.operands
[2].imm
;
14532 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14533 _("immediate out of range for shift"));
14534 NEON_ENCODE (IMMED
, inst
);
14535 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14539 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14540 struct neon_type_el et
= neon_check_type (3, rs
,
14541 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14544 /* VSHL/VQSHL 3-register variants have syntax such as:
14546 whereas other 3-register operations encoded by neon_three_same have
14549 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14551 tmp
= inst
.operands
[2].reg
;
14552 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14553 inst
.operands
[1].reg
= tmp
;
14554 NEON_ENCODE (INTEGER
, inst
);
14555 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14560 do_neon_qshl_imm (void)
14562 if (!inst
.operands
[2].isreg
)
14564 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14565 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14566 int imm
= inst
.operands
[2].imm
;
14568 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14569 _("immediate out of range for shift"));
14570 NEON_ENCODE (IMMED
, inst
);
14571 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14575 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14576 struct neon_type_el et
= neon_check_type (3, rs
,
14577 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14580 /* See note in do_neon_shl_imm. */
14581 tmp
= inst
.operands
[2].reg
;
14582 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14583 inst
.operands
[1].reg
= tmp
;
14584 NEON_ENCODE (INTEGER
, inst
);
14585 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14590 do_neon_rshl (void)
14592 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14593 struct neon_type_el et
= neon_check_type (3, rs
,
14594 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14597 tmp
= inst
.operands
[2].reg
;
14598 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14599 inst
.operands
[1].reg
= tmp
;
14600 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14604 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14606 /* Handle .I8 pseudo-instructions. */
14609 /* Unfortunately, this will make everything apart from zero out-of-range.
14610 FIXME is this the intended semantics? There doesn't seem much point in
14611 accepting .I8 if so. */
14612 immediate
|= immediate
<< 8;
14618 if (immediate
== (immediate
& 0x000000ff))
14620 *immbits
= immediate
;
14623 else if (immediate
== (immediate
& 0x0000ff00))
14625 *immbits
= immediate
>> 8;
14628 else if (immediate
== (immediate
& 0x00ff0000))
14630 *immbits
= immediate
>> 16;
14633 else if (immediate
== (immediate
& 0xff000000))
14635 *immbits
= immediate
>> 24;
14638 if ((immediate
& 0xffff) != (immediate
>> 16))
14639 goto bad_immediate
;
14640 immediate
&= 0xffff;
14643 if (immediate
== (immediate
& 0x000000ff))
14645 *immbits
= immediate
;
14648 else if (immediate
== (immediate
& 0x0000ff00))
14650 *immbits
= immediate
>> 8;
14655 first_error (_("immediate value out of range"));
14660 do_neon_logic (void)
14662 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14664 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14665 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14666 /* U bit and size field were set as part of the bitmask. */
14667 NEON_ENCODE (INTEGER
, inst
);
14668 neon_three_same (neon_quad (rs
), 0, -1);
14672 const int three_ops_form
= (inst
.operands
[2].present
14673 && !inst
.operands
[2].isreg
);
14674 const int immoperand
= (three_ops_form
? 2 : 1);
14675 enum neon_shape rs
= (three_ops_form
14676 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14677 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14678 struct neon_type_el et
= neon_check_type (2, rs
,
14679 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14680 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14684 if (et
.type
== NT_invtype
)
14687 if (three_ops_form
)
14688 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14689 _("first and second operands shall be the same register"));
14691 NEON_ENCODE (IMMED
, inst
);
14693 immbits
= inst
.operands
[immoperand
].imm
;
14696 /* .i64 is a pseudo-op, so the immediate must be a repeating
14698 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14699 inst
.operands
[immoperand
].reg
: 0))
14701 /* Set immbits to an invalid constant. */
14702 immbits
= 0xdeadbeef;
14709 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14713 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14717 /* Pseudo-instruction for VBIC. */
14718 neon_invert_size (&immbits
, 0, et
.size
);
14719 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14723 /* Pseudo-instruction for VORR. */
14724 neon_invert_size (&immbits
, 0, et
.size
);
14725 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14735 inst
.instruction
|= neon_quad (rs
) << 6;
14736 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14737 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14738 inst
.instruction
|= cmode
<< 8;
14739 neon_write_immbits (immbits
);
14741 neon_dp_fixup (&inst
);
14746 do_neon_bitfield (void)
14748 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14749 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14750 neon_three_same (neon_quad (rs
), 0, -1);
14754 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14757 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14758 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14760 if (et
.type
== NT_float
)
14762 NEON_ENCODE (FLOAT
, inst
);
14763 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14767 NEON_ENCODE (INTEGER
, inst
);
14768 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14773 do_neon_dyadic_if_su (void)
14775 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14779 do_neon_dyadic_if_su_d (void)
14781 /* This version only allow D registers, but that constraint is enforced during
14782 operand parsing so we don't need to do anything extra here. */
14783 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14787 do_neon_dyadic_if_i_d (void)
14789 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14790 affected if we specify unsigned args. */
14791 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14794 enum vfp_or_neon_is_neon_bits
14797 NEON_CHECK_ARCH
= 2,
14798 NEON_CHECK_ARCH8
= 4
14801 /* Call this function if an instruction which may have belonged to the VFP or
14802 Neon instruction sets, but turned out to be a Neon instruction (due to the
14803 operand types involved, etc.). We have to check and/or fix-up a couple of
14806 - Make sure the user hasn't attempted to make a Neon instruction
14808 - Alter the value in the condition code field if necessary.
14809 - Make sure that the arch supports Neon instructions.
14811 Which of these operations take place depends on bits from enum
14812 vfp_or_neon_is_neon_bits.
14814 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14815 current instruction's condition is COND_ALWAYS, the condition field is
14816 changed to inst.uncond_value. This is necessary because instructions shared
14817 between VFP and Neon may be conditional for the VFP variants only, and the
14818 unconditional Neon version must have, e.g., 0xF in the condition field. */
14821 vfp_or_neon_is_neon (unsigned check
)
14823 /* Conditions are always legal in Thumb mode (IT blocks). */
14824 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14826 if (inst
.cond
!= COND_ALWAYS
)
14828 first_error (_(BAD_COND
));
14831 if (inst
.uncond_value
!= -1)
14832 inst
.instruction
|= inst
.uncond_value
<< 28;
14835 if ((check
& NEON_CHECK_ARCH
)
14836 && !mark_feature_used (&fpu_neon_ext_v1
))
14838 first_error (_(BAD_FPU
));
14842 if ((check
& NEON_CHECK_ARCH8
)
14843 && !mark_feature_used (&fpu_neon_ext_armv8
))
14845 first_error (_(BAD_FPU
));
14853 do_neon_addsub_if_i (void)
14855 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14858 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14861 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14862 affected if we specify unsigned args. */
14863 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14866 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14868 V<op> A,B (A is operand 0, B is operand 2)
14873 so handle that case specially. */
14876 neon_exchange_operands (void)
14878 if (inst
.operands
[1].present
)
14880 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14882 /* Swap operands[1] and operands[2]. */
14883 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14884 inst
.operands
[1] = inst
.operands
[2];
14885 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14890 inst
.operands
[1] = inst
.operands
[2];
14891 inst
.operands
[2] = inst
.operands
[0];
14896 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14898 if (inst
.operands
[2].isreg
)
14901 neon_exchange_operands ();
14902 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14906 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14907 struct neon_type_el et
= neon_check_type (2, rs
,
14908 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14910 NEON_ENCODE (IMMED
, inst
);
14911 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14912 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14913 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14914 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14915 inst
.instruction
|= neon_quad (rs
) << 6;
14916 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14917 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14919 neon_dp_fixup (&inst
);
14926 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14930 do_neon_cmp_inv (void)
14932 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14938 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14941 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14942 scalars, which are encoded in 5 bits, M : Rm.
14943 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14944 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14948 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14950 unsigned regno
= NEON_SCALAR_REG (scalar
);
14951 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14956 if (regno
> 7 || elno
> 3)
14958 return regno
| (elno
<< 3);
14961 if (regno
> 15 || elno
> 1)
14963 return regno
| (elno
<< 4);
14967 first_error (_("scalar out of range for multiply instruction"));
14973 /* Encode multiply / multiply-accumulate scalar instructions. */
14976 neon_mul_mac (struct neon_type_el et
, int ubit
)
14980 /* Give a more helpful error message if we have an invalid type. */
14981 if (et
.type
== NT_invtype
)
14984 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14985 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14986 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14987 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14988 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14989 inst
.instruction
|= LOW4 (scalar
);
14990 inst
.instruction
|= HI1 (scalar
) << 5;
14991 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14992 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14993 inst
.instruction
|= (ubit
!= 0) << 24;
14995 neon_dp_fixup (&inst
);
14999 do_neon_mac_maybe_scalar (void)
15001 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15004 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15007 if (inst
.operands
[2].isscalar
)
15009 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15010 struct neon_type_el et
= neon_check_type (3, rs
,
15011 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15012 NEON_ENCODE (SCALAR
, inst
);
15013 neon_mul_mac (et
, neon_quad (rs
));
15017 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15018 affected if we specify unsigned args. */
15019 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15024 do_neon_fmac (void)
15026 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15029 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15032 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15038 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15039 struct neon_type_el et
= neon_check_type (3, rs
,
15040 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15041 neon_three_same (neon_quad (rs
), 0, et
.size
);
15044 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15045 same types as the MAC equivalents. The polynomial type for this instruction
15046 is encoded the same as the integer type. */
15051 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15054 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15057 if (inst
.operands
[2].isscalar
)
15058 do_neon_mac_maybe_scalar ();
15060 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15064 do_neon_qdmulh (void)
15066 if (inst
.operands
[2].isscalar
)
15068 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15069 struct neon_type_el et
= neon_check_type (3, rs
,
15070 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15071 NEON_ENCODE (SCALAR
, inst
);
15072 neon_mul_mac (et
, neon_quad (rs
));
15076 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15077 struct neon_type_el et
= neon_check_type (3, rs
,
15078 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15079 NEON_ENCODE (INTEGER
, inst
);
15080 /* The U bit (rounding) comes from bit mask. */
15081 neon_three_same (neon_quad (rs
), 0, et
.size
);
15086 do_neon_qrdmlah (void)
15088 /* Check we're on the correct architecture. */
15089 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15091 _("instruction form not available on this architecture.");
15092 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15094 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15095 record_feature_use (&fpu_neon_ext_v8_1
);
15098 if (inst
.operands
[2].isscalar
)
15100 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15101 struct neon_type_el et
= neon_check_type (3, rs
,
15102 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15103 NEON_ENCODE (SCALAR
, inst
);
15104 neon_mul_mac (et
, neon_quad (rs
));
15108 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15109 struct neon_type_el et
= neon_check_type (3, rs
,
15110 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15111 NEON_ENCODE (INTEGER
, inst
);
15112 /* The U bit (rounding) comes from bit mask. */
15113 neon_three_same (neon_quad (rs
), 0, et
.size
);
15118 do_neon_fcmp_absolute (void)
15120 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15121 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15122 N_F_16_32
| N_KEY
);
15123 /* Size field comes from bit mask. */
15124 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15128 do_neon_fcmp_absolute_inv (void)
15130 neon_exchange_operands ();
15131 do_neon_fcmp_absolute ();
15135 do_neon_step (void)
15137 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15138 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15139 N_F_16_32
| N_KEY
);
15140 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15144 do_neon_abs_neg (void)
15146 enum neon_shape rs
;
15147 struct neon_type_el et
;
15149 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15152 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15155 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15156 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15158 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15159 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15160 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15161 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15162 inst
.instruction
|= neon_quad (rs
) << 6;
15163 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15164 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15166 neon_dp_fixup (&inst
);
15172 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15173 struct neon_type_el et
= neon_check_type (2, rs
,
15174 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15175 int imm
= inst
.operands
[2].imm
;
15176 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15177 _("immediate out of range for insert"));
15178 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15184 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15185 struct neon_type_el et
= neon_check_type (2, rs
,
15186 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15187 int imm
= inst
.operands
[2].imm
;
15188 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15189 _("immediate out of range for insert"));
15190 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15194 do_neon_qshlu_imm (void)
15196 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15197 struct neon_type_el et
= neon_check_type (2, rs
,
15198 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15199 int imm
= inst
.operands
[2].imm
;
15200 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15201 _("immediate out of range for shift"));
15202 /* Only encodes the 'U present' variant of the instruction.
15203 In this case, signed types have OP (bit 8) set to 0.
15204 Unsigned types have OP set to 1. */
15205 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15206 /* The rest of the bits are the same as other immediate shifts. */
15207 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15211 do_neon_qmovn (void)
15213 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15214 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15215 /* Saturating move where operands can be signed or unsigned, and the
15216 destination has the same signedness. */
15217 NEON_ENCODE (INTEGER
, inst
);
15218 if (et
.type
== NT_unsigned
)
15219 inst
.instruction
|= 0xc0;
15221 inst
.instruction
|= 0x80;
15222 neon_two_same (0, 1, et
.size
/ 2);
15226 do_neon_qmovun (void)
15228 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15229 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15230 /* Saturating move with unsigned results. Operands must be signed. */
15231 NEON_ENCODE (INTEGER
, inst
);
15232 neon_two_same (0, 1, et
.size
/ 2);
15236 do_neon_rshift_sat_narrow (void)
15238 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15239 or unsigned. If operands are unsigned, results must also be unsigned. */
15240 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15241 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15242 int imm
= inst
.operands
[2].imm
;
15243 /* This gets the bounds check, size encoding and immediate bits calculation
15247 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15248 VQMOVN.I<size> <Dd>, <Qm>. */
15251 inst
.operands
[2].present
= 0;
15252 inst
.instruction
= N_MNEM_vqmovn
;
15257 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15258 _("immediate out of range"));
15259 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15263 do_neon_rshift_sat_narrow_u (void)
15265 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15266 or unsigned. If operands are unsigned, results must also be unsigned. */
15267 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15268 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15269 int imm
= inst
.operands
[2].imm
;
15270 /* This gets the bounds check, size encoding and immediate bits calculation
15274 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15275 VQMOVUN.I<size> <Dd>, <Qm>. */
15278 inst
.operands
[2].present
= 0;
15279 inst
.instruction
= N_MNEM_vqmovun
;
15284 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15285 _("immediate out of range"));
15286 /* FIXME: The manual is kind of unclear about what value U should have in
15287 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15289 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15293 do_neon_movn (void)
15295 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15296 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15297 NEON_ENCODE (INTEGER
, inst
);
15298 neon_two_same (0, 1, et
.size
/ 2);
15302 do_neon_rshift_narrow (void)
15304 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15305 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15306 int imm
= inst
.operands
[2].imm
;
15307 /* This gets the bounds check, size encoding and immediate bits calculation
15311 /* If immediate is zero then we are a pseudo-instruction for
15312 VMOVN.I<size> <Dd>, <Qm> */
15315 inst
.operands
[2].present
= 0;
15316 inst
.instruction
= N_MNEM_vmovn
;
15321 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15322 _("immediate out of range for narrowing operation"));
15323 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15327 do_neon_shll (void)
15329 /* FIXME: Type checking when lengthening. */
15330 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15331 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15332 unsigned imm
= inst
.operands
[2].imm
;
15334 if (imm
== et
.size
)
15336 /* Maximum shift variant. */
15337 NEON_ENCODE (INTEGER
, inst
);
15338 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15339 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15340 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15341 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15342 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15344 neon_dp_fixup (&inst
);
15348 /* A more-specific type check for non-max versions. */
15349 et
= neon_check_type (2, NS_QDI
,
15350 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15351 NEON_ENCODE (IMMED
, inst
);
15352 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15356 /* Check the various types for the VCVT instruction, and return which version
15357 the current instruction is. */
15359 #define CVT_FLAVOUR_VAR \
15360 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15361 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15362 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15363 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15364 /* Half-precision conversions. */ \
15365 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15366 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15367 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15368 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15369 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15370 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15371 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15372 Compared with single/double precision variants, only the co-processor \
15373 field is different, so the encoding flow is reused here. */ \
15374 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15375 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15376 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15377 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15378 /* VFP instructions. */ \
15379 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15380 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15381 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15382 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15383 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15384 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15385 /* VFP instructions with bitshift. */ \
15386 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15387 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15388 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15389 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15390 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15391 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15392 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15393 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15395 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15396 neon_cvt_flavour_##C,
15398 /* The different types of conversions we can do. */
15399 enum neon_cvt_flavour
15402 neon_cvt_flavour_invalid
,
15403 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15408 static enum neon_cvt_flavour
15409 get_neon_cvt_flavour (enum neon_shape rs
)
15411 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15412 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15413 if (et.type != NT_invtype) \
15415 inst.error = NULL; \
15416 return (neon_cvt_flavour_##C); \
15419 struct neon_type_el et
;
15420 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15421 || rs
== NS_FF
) ? N_VFP
: 0;
15422 /* The instruction versions which take an immediate take one register
15423 argument, which is extended to the width of the full register. Thus the
15424 "source" and "destination" registers must have the same width. Hack that
15425 here by making the size equal to the key (wider, in this case) operand. */
15426 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15430 return neon_cvt_flavour_invalid
;
15445 /* Neon-syntax VFP conversions. */
15448 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15450 const char *opname
= 0;
15452 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15453 || rs
== NS_FHI
|| rs
== NS_HFI
)
15455 /* Conversions with immediate bitshift. */
15456 const char *enc
[] =
15458 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15464 if (flavour
< (int) ARRAY_SIZE (enc
))
15466 opname
= enc
[flavour
];
15467 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15468 _("operands 0 and 1 must be the same register"));
15469 inst
.operands
[1] = inst
.operands
[2];
15470 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15475 /* Conversions without bitshift. */
15476 const char *enc
[] =
15478 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15484 if (flavour
< (int) ARRAY_SIZE (enc
))
15485 opname
= enc
[flavour
];
15489 do_vfp_nsyn_opcode (opname
);
15491 /* ARMv8.2 fp16 VCVT instruction. */
15492 if (flavour
== neon_cvt_flavour_s32_f16
15493 || flavour
== neon_cvt_flavour_u32_f16
15494 || flavour
== neon_cvt_flavour_f16_u32
15495 || flavour
== neon_cvt_flavour_f16_s32
)
15496 do_scalar_fp16_v82_encode ();
15500 do_vfp_nsyn_cvtz (void)
15502 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15503 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15504 const char *enc
[] =
15506 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15512 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15513 do_vfp_nsyn_opcode (enc
[flavour
]);
15517 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15518 enum neon_cvt_mode mode
)
15523 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15524 D register operands. */
15525 if (flavour
== neon_cvt_flavour_s32_f64
15526 || flavour
== neon_cvt_flavour_u32_f64
)
15527 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15530 if (flavour
== neon_cvt_flavour_s32_f16
15531 || flavour
== neon_cvt_flavour_u32_f16
)
15532 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15535 set_it_insn_type (OUTSIDE_IT_INSN
);
15539 case neon_cvt_flavour_s32_f64
:
15543 case neon_cvt_flavour_s32_f32
:
15547 case neon_cvt_flavour_s32_f16
:
15551 case neon_cvt_flavour_u32_f64
:
15555 case neon_cvt_flavour_u32_f32
:
15559 case neon_cvt_flavour_u32_f16
:
15564 first_error (_("invalid instruction shape"));
15570 case neon_cvt_mode_a
: rm
= 0; break;
15571 case neon_cvt_mode_n
: rm
= 1; break;
15572 case neon_cvt_mode_p
: rm
= 2; break;
15573 case neon_cvt_mode_m
: rm
= 3; break;
15574 default: first_error (_("invalid rounding mode")); return;
15577 NEON_ENCODE (FPV8
, inst
);
15578 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15579 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15580 inst
.instruction
|= sz
<< 8;
15582 /* ARMv8.2 fp16 VCVT instruction. */
15583 if (flavour
== neon_cvt_flavour_s32_f16
15584 ||flavour
== neon_cvt_flavour_u32_f16
)
15585 do_scalar_fp16_v82_encode ();
15586 inst
.instruction
|= op
<< 7;
15587 inst
.instruction
|= rm
<< 16;
15588 inst
.instruction
|= 0xf0000000;
15589 inst
.is_neon
= TRUE
;
15593 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15595 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15596 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15597 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15599 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15601 if (flavour
== neon_cvt_flavour_invalid
)
15604 /* PR11109: Handle round-to-zero for VCVT conversions. */
15605 if (mode
== neon_cvt_mode_z
15606 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15607 && (flavour
== neon_cvt_flavour_s16_f16
15608 || flavour
== neon_cvt_flavour_u16_f16
15609 || flavour
== neon_cvt_flavour_s32_f32
15610 || flavour
== neon_cvt_flavour_u32_f32
15611 || flavour
== neon_cvt_flavour_s32_f64
15612 || flavour
== neon_cvt_flavour_u32_f64
)
15613 && (rs
== NS_FD
|| rs
== NS_FF
))
15615 do_vfp_nsyn_cvtz ();
15619 /* ARMv8.2 fp16 VCVT conversions. */
15620 if (mode
== neon_cvt_mode_z
15621 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15622 && (flavour
== neon_cvt_flavour_s32_f16
15623 || flavour
== neon_cvt_flavour_u32_f16
)
15626 do_vfp_nsyn_cvtz ();
15627 do_scalar_fp16_v82_encode ();
15631 /* VFP rather than Neon conversions. */
15632 if (flavour
>= neon_cvt_flavour_first_fp
)
15634 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15635 do_vfp_nsyn_cvt (rs
, flavour
);
15637 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15648 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15649 0x0000100, 0x1000100, 0x0, 0x1000000};
15651 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15654 /* Fixed-point conversion with #0 immediate is encoded as an
15655 integer conversion. */
15656 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15658 NEON_ENCODE (IMMED
, inst
);
15659 if (flavour
!= neon_cvt_flavour_invalid
)
15660 inst
.instruction
|= enctab
[flavour
];
15661 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15662 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15663 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15664 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15665 inst
.instruction
|= neon_quad (rs
) << 6;
15666 inst
.instruction
|= 1 << 21;
15667 if (flavour
< neon_cvt_flavour_s16_f16
)
15669 inst
.instruction
|= 1 << 21;
15670 immbits
= 32 - inst
.operands
[2].imm
;
15671 inst
.instruction
|= immbits
<< 16;
15675 inst
.instruction
|= 3 << 20;
15676 immbits
= 16 - inst
.operands
[2].imm
;
15677 inst
.instruction
|= immbits
<< 16;
15678 inst
.instruction
&= ~(1 << 9);
15681 neon_dp_fixup (&inst
);
15687 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15689 NEON_ENCODE (FLOAT
, inst
);
15690 set_it_insn_type (OUTSIDE_IT_INSN
);
15692 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15695 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15696 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15697 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15698 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15699 inst
.instruction
|= neon_quad (rs
) << 6;
15700 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15701 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15702 inst
.instruction
|= mode
<< 8;
15703 if (flavour
== neon_cvt_flavour_u16_f16
15704 || flavour
== neon_cvt_flavour_s16_f16
)
15705 /* Mask off the original size bits and reencode them. */
15706 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15709 inst
.instruction
|= 0xfc000000;
15711 inst
.instruction
|= 0xf0000000;
15717 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15718 0x100, 0x180, 0x0, 0x080};
15720 NEON_ENCODE (INTEGER
, inst
);
15722 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15725 if (flavour
!= neon_cvt_flavour_invalid
)
15726 inst
.instruction
|= enctab
[flavour
];
15728 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15729 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15730 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15731 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15732 inst
.instruction
|= neon_quad (rs
) << 6;
15733 if (flavour
>= neon_cvt_flavour_s16_f16
15734 && flavour
<= neon_cvt_flavour_f16_u16
)
15735 /* Half precision. */
15736 inst
.instruction
|= 1 << 18;
15738 inst
.instruction
|= 2 << 18;
15740 neon_dp_fixup (&inst
);
15745 /* Half-precision conversions for Advanced SIMD -- neon. */
15750 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15752 as_bad (_("operand size must match register width"));
15757 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15759 as_bad (_("operand size must match register width"));
15764 inst
.instruction
= 0x3b60600;
15766 inst
.instruction
= 0x3b60700;
15768 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15769 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15770 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15771 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15772 neon_dp_fixup (&inst
);
15776 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15777 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15778 do_vfp_nsyn_cvt (rs
, flavour
);
15780 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15785 do_neon_cvtr (void)
15787 do_neon_cvt_1 (neon_cvt_mode_x
);
15793 do_neon_cvt_1 (neon_cvt_mode_z
);
15797 do_neon_cvta (void)
15799 do_neon_cvt_1 (neon_cvt_mode_a
);
15803 do_neon_cvtn (void)
15805 do_neon_cvt_1 (neon_cvt_mode_n
);
15809 do_neon_cvtp (void)
15811 do_neon_cvt_1 (neon_cvt_mode_p
);
15815 do_neon_cvtm (void)
15817 do_neon_cvt_1 (neon_cvt_mode_m
);
15821 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15824 mark_feature_used (&fpu_vfp_ext_armv8
);
15826 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15827 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15828 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15829 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15830 inst
.instruction
|= to
? 0x10000 : 0;
15831 inst
.instruction
|= t
? 0x80 : 0;
15832 inst
.instruction
|= is_double
? 0x100 : 0;
15833 do_vfp_cond_or_thumb ();
15837 do_neon_cvttb_1 (bfd_boolean t
)
15839 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15840 NS_DF
, NS_DH
, NS_NULL
);
15844 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15847 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15849 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15852 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15854 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15856 /* The VCVTB and VCVTT instructions with D-register operands
15857 don't work for SP only targets. */
15858 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15862 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15864 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15866 /* The VCVTB and VCVTT instructions with D-register operands
15867 don't work for SP only targets. */
15868 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15872 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15879 do_neon_cvtb (void)
15881 do_neon_cvttb_1 (FALSE
);
15886 do_neon_cvtt (void)
15888 do_neon_cvttb_1 (TRUE
);
15892 neon_move_immediate (void)
15894 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15895 struct neon_type_el et
= neon_check_type (2, rs
,
15896 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15897 unsigned immlo
, immhi
= 0, immbits
;
15898 int op
, cmode
, float_p
;
15900 constraint (et
.type
== NT_invtype
,
15901 _("operand size must be specified for immediate VMOV"));
15903 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15904 op
= (inst
.instruction
& (1 << 5)) != 0;
15906 immlo
= inst
.operands
[1].imm
;
15907 if (inst
.operands
[1].regisimm
)
15908 immhi
= inst
.operands
[1].reg
;
15910 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15911 _("immediate has bits set outside the operand size"));
15913 float_p
= inst
.operands
[1].immisfloat
;
15915 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15916 et
.size
, et
.type
)) == FAIL
)
15918 /* Invert relevant bits only. */
15919 neon_invert_size (&immlo
, &immhi
, et
.size
);
15920 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15921 with one or the other; those cases are caught by
15922 neon_cmode_for_move_imm. */
15924 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15925 &op
, et
.size
, et
.type
)) == FAIL
)
15927 first_error (_("immediate out of range"));
15932 inst
.instruction
&= ~(1 << 5);
15933 inst
.instruction
|= op
<< 5;
15935 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15936 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15937 inst
.instruction
|= neon_quad (rs
) << 6;
15938 inst
.instruction
|= cmode
<< 8;
15940 neon_write_immbits (immbits
);
15946 if (inst
.operands
[1].isreg
)
15948 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15950 NEON_ENCODE (INTEGER
, inst
);
15951 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15952 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15953 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15954 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15955 inst
.instruction
|= neon_quad (rs
) << 6;
15959 NEON_ENCODE (IMMED
, inst
);
15960 neon_move_immediate ();
15963 neon_dp_fixup (&inst
);
15966 /* Encode instructions of form:
15968 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15969 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15972 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15974 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15975 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15976 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15977 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15978 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15979 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15980 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15981 inst
.instruction
|= neon_logbits (size
) << 20;
15983 neon_dp_fixup (&inst
);
15987 do_neon_dyadic_long (void)
15989 /* FIXME: Type checking for lengthening op. */
15990 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15991 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15992 neon_mixed_length (et
, et
.size
);
15996 do_neon_abal (void)
15998 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15999 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16000 neon_mixed_length (et
, et
.size
);
16004 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16006 if (inst
.operands
[2].isscalar
)
16008 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16009 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16010 NEON_ENCODE (SCALAR
, inst
);
16011 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16015 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16016 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16017 NEON_ENCODE (INTEGER
, inst
);
16018 neon_mixed_length (et
, et
.size
);
16023 do_neon_mac_maybe_scalar_long (void)
16025 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16029 do_neon_dyadic_wide (void)
16031 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16032 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16033 neon_mixed_length (et
, et
.size
);
16037 do_neon_dyadic_narrow (void)
16039 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16040 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16041 /* Operand sign is unimportant, and the U bit is part of the opcode,
16042 so force the operand type to integer. */
16043 et
.type
= NT_integer
;
16044 neon_mixed_length (et
, et
.size
/ 2);
16048 do_neon_mul_sat_scalar_long (void)
16050 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16054 do_neon_vmull (void)
16056 if (inst
.operands
[2].isscalar
)
16057 do_neon_mac_maybe_scalar_long ();
16060 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16061 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16063 if (et
.type
== NT_poly
)
16064 NEON_ENCODE (POLY
, inst
);
16066 NEON_ENCODE (INTEGER
, inst
);
16068 /* For polynomial encoding the U bit must be zero, and the size must
16069 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16070 obviously, as 0b10). */
16073 /* Check we're on the correct architecture. */
16074 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16076 _("Instruction form not available on this architecture.");
16081 neon_mixed_length (et
, et
.size
);
16088 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16089 struct neon_type_el et
= neon_check_type (3, rs
,
16090 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16091 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16093 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16094 _("shift out of range"));
16095 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16096 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16097 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16098 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16099 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16100 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16101 inst
.instruction
|= neon_quad (rs
) << 6;
16102 inst
.instruction
|= imm
<< 8;
16104 neon_dp_fixup (&inst
);
16110 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16111 struct neon_type_el et
= neon_check_type (2, rs
,
16112 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16113 unsigned op
= (inst
.instruction
>> 7) & 3;
16114 /* N (width of reversed regions) is encoded as part of the bitmask. We
16115 extract it here to check the elements to be reversed are smaller.
16116 Otherwise we'd get a reserved instruction. */
16117 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16118 gas_assert (elsize
!= 0);
16119 constraint (et
.size
>= elsize
,
16120 _("elements must be smaller than reversal region"));
16121 neon_two_same (neon_quad (rs
), 1, et
.size
);
16127 if (inst
.operands
[1].isscalar
)
16129 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16130 struct neon_type_el et
= neon_check_type (2, rs
,
16131 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16132 unsigned sizebits
= et
.size
>> 3;
16133 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16134 int logsize
= neon_logbits (et
.size
);
16135 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16137 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16140 NEON_ENCODE (SCALAR
, inst
);
16141 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16142 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16143 inst
.instruction
|= LOW4 (dm
);
16144 inst
.instruction
|= HI1 (dm
) << 5;
16145 inst
.instruction
|= neon_quad (rs
) << 6;
16146 inst
.instruction
|= x
<< 17;
16147 inst
.instruction
|= sizebits
<< 16;
16149 neon_dp_fixup (&inst
);
16153 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16154 struct neon_type_el et
= neon_check_type (2, rs
,
16155 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16156 /* Duplicate ARM register to lanes of vector. */
16157 NEON_ENCODE (ARMREG
, inst
);
16160 case 8: inst
.instruction
|= 0x400000; break;
16161 case 16: inst
.instruction
|= 0x000020; break;
16162 case 32: inst
.instruction
|= 0x000000; break;
16165 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16166 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16167 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16168 inst
.instruction
|= neon_quad (rs
) << 21;
16169 /* The encoding for this instruction is identical for the ARM and Thumb
16170 variants, except for the condition field. */
16171 do_vfp_cond_or_thumb ();
16175 /* VMOV has particularly many variations. It can be one of:
16176 0. VMOV<c><q> <Qd>, <Qm>
16177 1. VMOV<c><q> <Dd>, <Dm>
16178 (Register operations, which are VORR with Rm = Rn.)
16179 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16180 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16182 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16183 (ARM register to scalar.)
16184 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16185 (Two ARM registers to vector.)
16186 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16187 (Scalar to ARM register.)
16188 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16189 (Vector to two ARM registers.)
16190 8. VMOV.F32 <Sd>, <Sm>
16191 9. VMOV.F64 <Dd>, <Dm>
16192 (VFP register moves.)
16193 10. VMOV.F32 <Sd>, #imm
16194 11. VMOV.F64 <Dd>, #imm
16195 (VFP float immediate load.)
16196 12. VMOV <Rd>, <Sm>
16197 (VFP single to ARM reg.)
16198 13. VMOV <Sd>, <Rm>
16199 (ARM reg to VFP single.)
16200 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16201 (Two ARM regs to two VFP singles.)
16202 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16203 (Two VFP singles to two ARM regs.)
16205 These cases can be disambiguated using neon_select_shape, except cases 1/9
16206 and 3/11 which depend on the operand type too.
16208 All the encoded bits are hardcoded by this function.
16210 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16211 Cases 5, 7 may be used with VFPv2 and above.
16213 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16214 can specify a type where it doesn't make sense to, and is ignored). */
16219 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16220 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16221 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16222 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16223 struct neon_type_el et
;
16224 const char *ldconst
= 0;
16228 case NS_DD
: /* case 1/9. */
16229 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16230 /* It is not an error here if no type is given. */
16232 if (et
.type
== NT_float
&& et
.size
== 64)
16234 do_vfp_nsyn_opcode ("fcpyd");
16237 /* fall through. */
16239 case NS_QQ
: /* case 0/1. */
16241 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16243 /* The architecture manual I have doesn't explicitly state which
16244 value the U bit should have for register->register moves, but
16245 the equivalent VORR instruction has U = 0, so do that. */
16246 inst
.instruction
= 0x0200110;
16247 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16248 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16249 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16250 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16251 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16252 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16253 inst
.instruction
|= neon_quad (rs
) << 6;
16255 neon_dp_fixup (&inst
);
16259 case NS_DI
: /* case 3/11. */
16260 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16262 if (et
.type
== NT_float
&& et
.size
== 64)
16264 /* case 11 (fconstd). */
16265 ldconst
= "fconstd";
16266 goto encode_fconstd
;
16268 /* fall through. */
16270 case NS_QI
: /* case 2/3. */
16271 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16273 inst
.instruction
= 0x0800010;
16274 neon_move_immediate ();
16275 neon_dp_fixup (&inst
);
16278 case NS_SR
: /* case 4. */
16280 unsigned bcdebits
= 0;
16282 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16283 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16285 /* .<size> is optional here, defaulting to .32. */
16286 if (inst
.vectype
.elems
== 0
16287 && inst
.operands
[0].vectype
.type
== NT_invtype
16288 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16290 inst
.vectype
.el
[0].type
= NT_untyped
;
16291 inst
.vectype
.el
[0].size
= 32;
16292 inst
.vectype
.elems
= 1;
16295 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16296 logsize
= neon_logbits (et
.size
);
16298 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16300 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16301 && et
.size
!= 32, _(BAD_FPU
));
16302 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16303 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16307 case 8: bcdebits
= 0x8; break;
16308 case 16: bcdebits
= 0x1; break;
16309 case 32: bcdebits
= 0x0; break;
16313 bcdebits
|= x
<< logsize
;
16315 inst
.instruction
= 0xe000b10;
16316 do_vfp_cond_or_thumb ();
16317 inst
.instruction
|= LOW4 (dn
) << 16;
16318 inst
.instruction
|= HI1 (dn
) << 7;
16319 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16320 inst
.instruction
|= (bcdebits
& 3) << 5;
16321 inst
.instruction
|= (bcdebits
>> 2) << 21;
16325 case NS_DRR
: /* case 5 (fmdrr). */
16326 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16329 inst
.instruction
= 0xc400b10;
16330 do_vfp_cond_or_thumb ();
16331 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16332 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16333 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16334 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16337 case NS_RS
: /* case 6. */
16340 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16341 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16342 unsigned abcdebits
= 0;
16344 /* .<dt> is optional here, defaulting to .32. */
16345 if (inst
.vectype
.elems
== 0
16346 && inst
.operands
[0].vectype
.type
== NT_invtype
16347 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16349 inst
.vectype
.el
[0].type
= NT_untyped
;
16350 inst
.vectype
.el
[0].size
= 32;
16351 inst
.vectype
.elems
= 1;
16354 et
= neon_check_type (2, NS_NULL
,
16355 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16356 logsize
= neon_logbits (et
.size
);
16358 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16360 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16361 && et
.size
!= 32, _(BAD_FPU
));
16362 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16363 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16367 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16368 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16369 case 32: abcdebits
= 0x00; break;
16373 abcdebits
|= x
<< logsize
;
16374 inst
.instruction
= 0xe100b10;
16375 do_vfp_cond_or_thumb ();
16376 inst
.instruction
|= LOW4 (dn
) << 16;
16377 inst
.instruction
|= HI1 (dn
) << 7;
16378 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16379 inst
.instruction
|= (abcdebits
& 3) << 5;
16380 inst
.instruction
|= (abcdebits
>> 2) << 21;
16384 case NS_RRD
: /* case 7 (fmrrd). */
16385 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16388 inst
.instruction
= 0xc500b10;
16389 do_vfp_cond_or_thumb ();
16390 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16391 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16392 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16393 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16396 case NS_FF
: /* case 8 (fcpys). */
16397 do_vfp_nsyn_opcode ("fcpys");
16401 case NS_FI
: /* case 10 (fconsts). */
16402 ldconst
= "fconsts";
16404 if (is_quarter_float (inst
.operands
[1].imm
))
16406 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16407 do_vfp_nsyn_opcode (ldconst
);
16409 /* ARMv8.2 fp16 vmov.f16 instruction. */
16411 do_scalar_fp16_v82_encode ();
16414 first_error (_("immediate out of range"));
16418 case NS_RF
: /* case 12 (fmrs). */
16419 do_vfp_nsyn_opcode ("fmrs");
16420 /* ARMv8.2 fp16 vmov.f16 instruction. */
16422 do_scalar_fp16_v82_encode ();
16426 case NS_FR
: /* case 13 (fmsr). */
16427 do_vfp_nsyn_opcode ("fmsr");
16428 /* ARMv8.2 fp16 vmov.f16 instruction. */
16430 do_scalar_fp16_v82_encode ();
16433 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16434 (one of which is a list), but we have parsed four. Do some fiddling to
16435 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16437 case NS_RRFF
: /* case 14 (fmrrs). */
16438 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16439 _("VFP registers must be adjacent"));
16440 inst
.operands
[2].imm
= 2;
16441 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16442 do_vfp_nsyn_opcode ("fmrrs");
16445 case NS_FFRR
: /* case 15 (fmsrr). */
16446 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16447 _("VFP registers must be adjacent"));
16448 inst
.operands
[1] = inst
.operands
[2];
16449 inst
.operands
[2] = inst
.operands
[3];
16450 inst
.operands
[0].imm
= 2;
16451 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16452 do_vfp_nsyn_opcode ("fmsrr");
16456 /* neon_select_shape has determined that the instruction
16457 shape is wrong and has already set the error message. */
16466 do_neon_rshift_round_imm (void)
16468 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16469 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16470 int imm
= inst
.operands
[2].imm
;
16472 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16475 inst
.operands
[2].present
= 0;
16480 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16481 _("immediate out of range for shift"));
16482 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16487 do_neon_movhf (void)
16489 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16490 constraint (rs
!= NS_HH
, _("invalid suffix"));
16492 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16495 do_vfp_sp_monadic ();
16498 inst
.instruction
|= 0xf0000000;
16502 do_neon_movl (void)
16504 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16505 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16506 unsigned sizebits
= et
.size
>> 3;
16507 inst
.instruction
|= sizebits
<< 19;
16508 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16514 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16515 struct neon_type_el et
= neon_check_type (2, rs
,
16516 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16517 NEON_ENCODE (INTEGER
, inst
);
16518 neon_two_same (neon_quad (rs
), 1, et
.size
);
16522 do_neon_zip_uzp (void)
16524 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16525 struct neon_type_el et
= neon_check_type (2, rs
,
16526 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16527 if (rs
== NS_DD
&& et
.size
== 32)
16529 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16530 inst
.instruction
= N_MNEM_vtrn
;
16534 neon_two_same (neon_quad (rs
), 1, et
.size
);
16538 do_neon_sat_abs_neg (void)
16540 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16541 struct neon_type_el et
= neon_check_type (2, rs
,
16542 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16543 neon_two_same (neon_quad (rs
), 1, et
.size
);
16547 do_neon_pair_long (void)
16549 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16550 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16551 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16552 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16553 neon_two_same (neon_quad (rs
), 1, et
.size
);
16557 do_neon_recip_est (void)
16559 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16560 struct neon_type_el et
= neon_check_type (2, rs
,
16561 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16562 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16563 neon_two_same (neon_quad (rs
), 1, et
.size
);
16569 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16570 struct neon_type_el et
= neon_check_type (2, rs
,
16571 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16572 neon_two_same (neon_quad (rs
), 1, et
.size
);
16578 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16579 struct neon_type_el et
= neon_check_type (2, rs
,
16580 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16581 neon_two_same (neon_quad (rs
), 1, et
.size
);
16587 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16588 struct neon_type_el et
= neon_check_type (2, rs
,
16589 N_EQK
| N_INT
, N_8
| N_KEY
);
16590 neon_two_same (neon_quad (rs
), 1, et
.size
);
16596 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16597 neon_two_same (neon_quad (rs
), 1, -1);
16601 do_neon_tbl_tbx (void)
16603 unsigned listlenbits
;
16604 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16606 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16608 first_error (_("bad list length for table lookup"));
16612 listlenbits
= inst
.operands
[1].imm
- 1;
16613 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16614 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16615 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16616 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16617 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16618 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16619 inst
.instruction
|= listlenbits
<< 8;
16621 neon_dp_fixup (&inst
);
16625 do_neon_ldm_stm (void)
16627 /* P, U and L bits are part of bitmask. */
16628 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16629 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16631 if (inst
.operands
[1].issingle
)
16633 do_vfp_nsyn_ldm_stm (is_dbmode
);
16637 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16638 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16640 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16641 _("register list must contain at least 1 and at most 16 "
16644 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16645 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16646 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16647 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16649 inst
.instruction
|= offsetbits
;
16651 do_vfp_cond_or_thumb ();
16655 do_neon_ldr_str (void)
16657 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16659 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16660 And is UNPREDICTABLE in thumb mode. */
16662 && inst
.operands
[1].reg
== REG_PC
16663 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16666 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16667 else if (warn_on_deprecated
)
16668 as_tsktsk (_("Use of PC here is deprecated"));
16671 if (inst
.operands
[0].issingle
)
16674 do_vfp_nsyn_opcode ("flds");
16676 do_vfp_nsyn_opcode ("fsts");
16678 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16679 if (inst
.vectype
.el
[0].size
== 16)
16680 do_scalar_fp16_v82_encode ();
16685 do_vfp_nsyn_opcode ("fldd");
16687 do_vfp_nsyn_opcode ("fstd");
16691 /* "interleave" version also handles non-interleaving register VLD1/VST1
16695 do_neon_ld_st_interleave (void)
16697 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16698 N_8
| N_16
| N_32
| N_64
);
16699 unsigned alignbits
= 0;
16701 /* The bits in this table go:
16702 0: register stride of one (0) or two (1)
16703 1,2: register list length, minus one (1, 2, 3, 4).
16704 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16705 We use -1 for invalid entries. */
16706 const int typetable
[] =
16708 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16709 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16710 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16711 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16715 if (et
.type
== NT_invtype
)
16718 if (inst
.operands
[1].immisalign
)
16719 switch (inst
.operands
[1].imm
>> 8)
16721 case 64: alignbits
= 1; break;
16723 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16724 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16725 goto bad_alignment
;
16729 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16730 goto bad_alignment
;
16735 first_error (_("bad alignment"));
16739 inst
.instruction
|= alignbits
<< 4;
16740 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16742 /* Bits [4:6] of the immediate in a list specifier encode register stride
16743 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16744 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16745 up the right value for "type" in a table based on this value and the given
16746 list style, then stick it back. */
16747 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16748 | (((inst
.instruction
>> 8) & 3) << 3);
16750 typebits
= typetable
[idx
];
16752 constraint (typebits
== -1, _("bad list type for instruction"));
16753 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16754 _("bad element type for instruction"));
16756 inst
.instruction
&= ~0xf00;
16757 inst
.instruction
|= typebits
<< 8;
16760 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16761 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16762 otherwise. The variable arguments are a list of pairs of legal (size, align)
16763 values, terminated with -1. */
16766 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16769 int result
= FAIL
, thissize
, thisalign
;
16771 if (!inst
.operands
[1].immisalign
)
16777 va_start (ap
, do_alignment
);
16781 thissize
= va_arg (ap
, int);
16782 if (thissize
== -1)
16784 thisalign
= va_arg (ap
, int);
16786 if (size
== thissize
&& align
== thisalign
)
16789 while (result
!= SUCCESS
);
16793 if (result
== SUCCESS
)
16796 first_error (_("unsupported alignment for instruction"));
16802 do_neon_ld_st_lane (void)
16804 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16805 int align_good
, do_alignment
= 0;
16806 int logsize
= neon_logbits (et
.size
);
16807 int align
= inst
.operands
[1].imm
>> 8;
16808 int n
= (inst
.instruction
>> 8) & 3;
16809 int max_el
= 64 / et
.size
;
16811 if (et
.type
== NT_invtype
)
16814 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16815 _("bad list length"));
16816 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16817 _("scalar index out of range"));
16818 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16820 _("stride of 2 unavailable when element size is 8"));
16824 case 0: /* VLD1 / VST1. */
16825 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16827 if (align_good
== FAIL
)
16831 unsigned alignbits
= 0;
16834 case 16: alignbits
= 0x1; break;
16835 case 32: alignbits
= 0x3; break;
16838 inst
.instruction
|= alignbits
<< 4;
16842 case 1: /* VLD2 / VST2. */
16843 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16844 16, 32, 32, 64, -1);
16845 if (align_good
== FAIL
)
16848 inst
.instruction
|= 1 << 4;
16851 case 2: /* VLD3 / VST3. */
16852 constraint (inst
.operands
[1].immisalign
,
16853 _("can't use alignment with this instruction"));
16856 case 3: /* VLD4 / VST4. */
16857 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16858 16, 64, 32, 64, 32, 128, -1);
16859 if (align_good
== FAIL
)
16863 unsigned alignbits
= 0;
16866 case 8: alignbits
= 0x1; break;
16867 case 16: alignbits
= 0x1; break;
16868 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16871 inst
.instruction
|= alignbits
<< 4;
16878 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16879 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16880 inst
.instruction
|= 1 << (4 + logsize
);
16882 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16883 inst
.instruction
|= logsize
<< 10;
16886 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16889 do_neon_ld_dup (void)
16891 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16892 int align_good
, do_alignment
= 0;
16894 if (et
.type
== NT_invtype
)
16897 switch ((inst
.instruction
>> 8) & 3)
16899 case 0: /* VLD1. */
16900 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16901 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16902 &do_alignment
, 16, 16, 32, 32, -1);
16903 if (align_good
== FAIL
)
16905 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16908 case 2: inst
.instruction
|= 1 << 5; break;
16909 default: first_error (_("bad list length")); return;
16911 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16914 case 1: /* VLD2. */
16915 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16916 &do_alignment
, 8, 16, 16, 32, 32, 64,
16918 if (align_good
== FAIL
)
16920 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16921 _("bad list length"));
16922 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16923 inst
.instruction
|= 1 << 5;
16924 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16927 case 2: /* VLD3. */
16928 constraint (inst
.operands
[1].immisalign
,
16929 _("can't use alignment with this instruction"));
16930 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16931 _("bad list length"));
16932 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16933 inst
.instruction
|= 1 << 5;
16934 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16937 case 3: /* VLD4. */
16939 int align
= inst
.operands
[1].imm
>> 8;
16940 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16941 16, 64, 32, 64, 32, 128, -1);
16942 if (align_good
== FAIL
)
16944 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16945 _("bad list length"));
16946 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16947 inst
.instruction
|= 1 << 5;
16948 if (et
.size
== 32 && align
== 128)
16949 inst
.instruction
|= 0x3 << 6;
16951 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16958 inst
.instruction
|= do_alignment
<< 4;
16961 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16962 apart from bits [11:4]. */
16965 do_neon_ldx_stx (void)
16967 if (inst
.operands
[1].isreg
)
16968 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16970 switch (NEON_LANE (inst
.operands
[0].imm
))
16972 case NEON_INTERLEAVE_LANES
:
16973 NEON_ENCODE (INTERLV
, inst
);
16974 do_neon_ld_st_interleave ();
16977 case NEON_ALL_LANES
:
16978 NEON_ENCODE (DUP
, inst
);
16979 if (inst
.instruction
== N_INV
)
16981 first_error ("only loads support such operands");
16988 NEON_ENCODE (LANE
, inst
);
16989 do_neon_ld_st_lane ();
16992 /* L bit comes from bit mask. */
16993 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16994 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16995 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16997 if (inst
.operands
[1].postind
)
16999 int postreg
= inst
.operands
[1].imm
& 0xf;
17000 constraint (!inst
.operands
[1].immisreg
,
17001 _("post-index must be a register"));
17002 constraint (postreg
== 0xd || postreg
== 0xf,
17003 _("bad register for post-index"));
17004 inst
.instruction
|= postreg
;
17008 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17009 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17010 || inst
.reloc
.exp
.X_add_number
!= 0,
17013 if (inst
.operands
[1].writeback
)
17015 inst
.instruction
|= 0xd;
17018 inst
.instruction
|= 0xf;
17022 inst
.instruction
|= 0xf9000000;
17024 inst
.instruction
|= 0xf4000000;
17029 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17031 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17032 D register operands. */
17033 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17037 NEON_ENCODE (FPV8
, inst
);
17039 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17041 do_vfp_sp_dyadic ();
17043 /* ARMv8.2 fp16 instruction. */
17045 do_scalar_fp16_v82_encode ();
17048 do_vfp_dp_rd_rn_rm ();
17051 inst
.instruction
|= 0x100;
17053 inst
.instruction
|= 0xf0000000;
17059 set_it_insn_type (OUTSIDE_IT_INSN
);
17061 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17062 first_error (_("invalid instruction shape"));
17068 set_it_insn_type (OUTSIDE_IT_INSN
);
17070 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17073 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17076 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17080 do_vrint_1 (enum neon_cvt_mode mode
)
17082 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17083 struct neon_type_el et
;
17088 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17089 D register operands. */
17090 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17091 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17094 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17096 if (et
.type
!= NT_invtype
)
17098 /* VFP encodings. */
17099 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17100 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17101 set_it_insn_type (OUTSIDE_IT_INSN
);
17103 NEON_ENCODE (FPV8
, inst
);
17104 if (rs
== NS_FF
|| rs
== NS_HH
)
17105 do_vfp_sp_monadic ();
17107 do_vfp_dp_rd_rm ();
17111 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17112 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17113 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17114 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17115 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17116 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17117 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17121 inst
.instruction
|= (rs
== NS_DD
) << 8;
17122 do_vfp_cond_or_thumb ();
17124 /* ARMv8.2 fp16 vrint instruction. */
17126 do_scalar_fp16_v82_encode ();
17130 /* Neon encodings (or something broken...). */
17132 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17134 if (et
.type
== NT_invtype
)
17137 set_it_insn_type (OUTSIDE_IT_INSN
);
17138 NEON_ENCODE (FLOAT
, inst
);
17140 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17143 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17144 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17145 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17146 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17147 inst
.instruction
|= neon_quad (rs
) << 6;
17148 /* Mask off the original size bits and reencode them. */
17149 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17150 | neon_logbits (et
.size
) << 18);
17154 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17155 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17156 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17157 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17158 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17159 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17160 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17165 inst
.instruction
|= 0xfc000000;
17167 inst
.instruction
|= 0xf0000000;
17174 do_vrint_1 (neon_cvt_mode_x
);
17180 do_vrint_1 (neon_cvt_mode_z
);
17186 do_vrint_1 (neon_cvt_mode_r
);
17192 do_vrint_1 (neon_cvt_mode_a
);
17198 do_vrint_1 (neon_cvt_mode_n
);
17204 do_vrint_1 (neon_cvt_mode_p
);
17210 do_vrint_1 (neon_cvt_mode_m
);
17213 /* Crypto v1 instructions. */
17215 do_crypto_2op_1 (unsigned elttype
, int op
)
17217 set_it_insn_type (OUTSIDE_IT_INSN
);
17219 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17225 NEON_ENCODE (INTEGER
, inst
);
17226 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17227 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17228 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17229 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17231 inst
.instruction
|= op
<< 6;
17234 inst
.instruction
|= 0xfc000000;
17236 inst
.instruction
|= 0xf0000000;
17240 do_crypto_3op_1 (int u
, int op
)
17242 set_it_insn_type (OUTSIDE_IT_INSN
);
17244 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17245 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17250 NEON_ENCODE (INTEGER
, inst
);
17251 neon_three_same (1, u
, 8 << op
);
17257 do_crypto_2op_1 (N_8
, 0);
17263 do_crypto_2op_1 (N_8
, 1);
17269 do_crypto_2op_1 (N_8
, 2);
17275 do_crypto_2op_1 (N_8
, 3);
17281 do_crypto_3op_1 (0, 0);
17287 do_crypto_3op_1 (0, 1);
17293 do_crypto_3op_1 (0, 2);
17299 do_crypto_3op_1 (0, 3);
17305 do_crypto_3op_1 (1, 0);
17311 do_crypto_3op_1 (1, 1);
17315 do_sha256su1 (void)
17317 do_crypto_3op_1 (1, 2);
17323 do_crypto_2op_1 (N_32
, -1);
17329 do_crypto_2op_1 (N_32
, 0);
17333 do_sha256su0 (void)
17335 do_crypto_2op_1 (N_32
, 1);
17339 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17341 unsigned int Rd
= inst
.operands
[0].reg
;
17342 unsigned int Rn
= inst
.operands
[1].reg
;
17343 unsigned int Rm
= inst
.operands
[2].reg
;
17345 set_it_insn_type (OUTSIDE_IT_INSN
);
17346 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17347 inst
.instruction
|= LOW4 (Rn
) << 16;
17348 inst
.instruction
|= LOW4 (Rm
);
17349 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17350 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17352 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17353 as_warn (UNPRED_REG ("r15"));
17354 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17355 as_warn (UNPRED_REG ("r13"));
17395 /* Overall per-instruction processing. */
17397 /* We need to be able to fix up arbitrary expressions in some statements.
17398 This is so that we can handle symbols that are an arbitrary distance from
17399 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17400 which returns part of an address in a form which will be valid for
17401 a data instruction. We do this by pushing the expression into a symbol
17402 in the expr_section, and creating a fix for that. */
17405 fix_new_arm (fragS
* frag
,
17419 /* Create an absolute valued symbol, so we have something to
17420 refer to in the object file. Unfortunately for us, gas's
17421 generic expression parsing will already have folded out
17422 any use of .set foo/.type foo %function that may have
17423 been used to set type information of the target location,
17424 that's being specified symbolically. We have to presume
17425 the user knows what they are doing. */
17429 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17431 symbol
= symbol_find_or_make (name
);
17432 S_SET_SEGMENT (symbol
, absolute_section
);
17433 symbol_set_frag (symbol
, &zero_address_frag
);
17434 S_SET_VALUE (symbol
, exp
->X_add_number
);
17435 exp
->X_op
= O_symbol
;
17436 exp
->X_add_symbol
= symbol
;
17437 exp
->X_add_number
= 0;
17443 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17444 (enum bfd_reloc_code_real
) reloc
);
17448 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17449 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17453 /* Mark whether the fix is to a THUMB instruction, or an ARM
17455 new_fix
->tc_fix_data
= thumb_mode
;
17458 /* Create a frg for an instruction requiring relaxation. */
17460 output_relax_insn (void)
17466 /* The size of the instruction is unknown, so tie the debug info to the
17467 start of the instruction. */
17468 dwarf2_emit_insn (0);
17470 switch (inst
.reloc
.exp
.X_op
)
17473 sym
= inst
.reloc
.exp
.X_add_symbol
;
17474 offset
= inst
.reloc
.exp
.X_add_number
;
17478 offset
= inst
.reloc
.exp
.X_add_number
;
17481 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17485 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17486 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17487 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17490 /* Write a 32-bit thumb instruction to buf. */
17492 put_thumb32_insn (char * buf
, unsigned long insn
)
17494 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17495 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17499 output_inst (const char * str
)
17505 as_bad ("%s -- `%s'", inst
.error
, str
);
17510 output_relax_insn ();
17513 if (inst
.size
== 0)
17516 to
= frag_more (inst
.size
);
17517 /* PR 9814: Record the thumb mode into the current frag so that we know
17518 what type of NOP padding to use, if necessary. We override any previous
17519 setting so that if the mode has changed then the NOPS that we use will
17520 match the encoding of the last instruction in the frag. */
17521 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17523 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17525 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17526 put_thumb32_insn (to
, inst
.instruction
);
17528 else if (inst
.size
> INSN_SIZE
)
17530 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17531 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17532 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17535 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17537 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17538 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17539 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17542 dwarf2_emit_insn (inst
.size
);
17546 output_it_inst (int cond
, int mask
, char * to
)
17548 unsigned long instruction
= 0xbf00;
17551 instruction
|= mask
;
17552 instruction
|= cond
<< 4;
17556 to
= frag_more (2);
17558 dwarf2_emit_insn (2);
17562 md_number_to_chars (to
, instruction
, 2);
17567 /* Tag values used in struct asm_opcode's tag field. */
17570 OT_unconditional
, /* Instruction cannot be conditionalized.
17571 The ARM condition field is still 0xE. */
17572 OT_unconditionalF
, /* Instruction cannot be conditionalized
17573 and carries 0xF in its ARM condition field. */
17574 OT_csuffix
, /* Instruction takes a conditional suffix. */
17575 OT_csuffixF
, /* Some forms of the instruction take a conditional
17576 suffix, others place 0xF where the condition field
17578 OT_cinfix3
, /* Instruction takes a conditional infix,
17579 beginning at character index 3. (In
17580 unified mode, it becomes a suffix.) */
17581 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17582 tsts, cmps, cmns, and teqs. */
17583 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17584 character index 3, even in unified mode. Used for
17585 legacy instructions where suffix and infix forms
17586 may be ambiguous. */
17587 OT_csuf_or_in3
, /* Instruction takes either a conditional
17588 suffix or an infix at character index 3. */
17589 OT_odd_infix_unc
, /* This is the unconditional variant of an
17590 instruction that takes a conditional infix
17591 at an unusual position. In unified mode,
17592 this variant will accept a suffix. */
17593 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17594 are the conditional variants of instructions that
17595 take conditional infixes in unusual positions.
17596 The infix appears at character index
17597 (tag - OT_odd_infix_0). These are not accepted
17598 in unified mode. */
17601 /* Subroutine of md_assemble, responsible for looking up the primary
17602 opcode from the mnemonic the user wrote. STR points to the
17603 beginning of the mnemonic.
17605 This is not simply a hash table lookup, because of conditional
17606 variants. Most instructions have conditional variants, which are
17607 expressed with a _conditional affix_ to the mnemonic. If we were
17608 to encode each conditional variant as a literal string in the opcode
17609 table, it would have approximately 20,000 entries.
17611 Most mnemonics take this affix as a suffix, and in unified syntax,
17612 'most' is upgraded to 'all'. However, in the divided syntax, some
17613 instructions take the affix as an infix, notably the s-variants of
17614 the arithmetic instructions. Of those instructions, all but six
17615 have the infix appear after the third character of the mnemonic.
17617 Accordingly, the algorithm for looking up primary opcodes given
17620 1. Look up the identifier in the opcode table.
17621 If we find a match, go to step U.
17623 2. Look up the last two characters of the identifier in the
17624 conditions table. If we find a match, look up the first N-2
17625 characters of the identifier in the opcode table. If we
17626 find a match, go to step CE.
17628 3. Look up the fourth and fifth characters of the identifier in
17629 the conditions table. If we find a match, extract those
17630 characters from the identifier, and look up the remaining
17631 characters in the opcode table. If we find a match, go
17636 U. Examine the tag field of the opcode structure, in case this is
17637 one of the six instructions with its conditional infix in an
17638 unusual place. If it is, the tag tells us where to find the
17639 infix; look it up in the conditions table and set inst.cond
17640 accordingly. Otherwise, this is an unconditional instruction.
17641 Again set inst.cond accordingly. Return the opcode structure.
17643 CE. Examine the tag field to make sure this is an instruction that
17644 should receive a conditional suffix. If it is not, fail.
17645 Otherwise, set inst.cond from the suffix we already looked up,
17646 and return the opcode structure.
17648 CM. Examine the tag field to make sure this is an instruction that
17649 should receive a conditional infix after the third character.
17650 If it is not, fail. Otherwise, undo the edits to the current
17651 line of input and proceed as for case CE. */
17653 static const struct asm_opcode
*
17654 opcode_lookup (char **str
)
17658 const struct asm_opcode
*opcode
;
17659 const struct asm_cond
*cond
;
17662 /* Scan up to the end of the mnemonic, which must end in white space,
17663 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17664 for (base
= end
= *str
; *end
!= '\0'; end
++)
17665 if (*end
== ' ' || *end
== '.')
17671 /* Handle a possible width suffix and/or Neon type suffix. */
17676 /* The .w and .n suffixes are only valid if the unified syntax is in
17678 if (unified_syntax
&& end
[1] == 'w')
17680 else if (unified_syntax
&& end
[1] == 'n')
17685 inst
.vectype
.elems
= 0;
17687 *str
= end
+ offset
;
17689 if (end
[offset
] == '.')
17691 /* See if we have a Neon type suffix (possible in either unified or
17692 non-unified ARM syntax mode). */
17693 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17696 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17702 /* Look for unaffixed or special-case affixed mnemonic. */
17703 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17708 if (opcode
->tag
< OT_odd_infix_0
)
17710 inst
.cond
= COND_ALWAYS
;
17714 if (warn_on_deprecated
&& unified_syntax
)
17715 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17716 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17717 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17720 inst
.cond
= cond
->value
;
17724 /* Cannot have a conditional suffix on a mnemonic of less than two
17726 if (end
- base
< 3)
17729 /* Look for suffixed mnemonic. */
17731 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17732 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17734 if (opcode
&& cond
)
17737 switch (opcode
->tag
)
17739 case OT_cinfix3_legacy
:
17740 /* Ignore conditional suffixes matched on infix only mnemonics. */
17744 case OT_cinfix3_deprecated
:
17745 case OT_odd_infix_unc
:
17746 if (!unified_syntax
)
17748 /* else fall through */
17752 case OT_csuf_or_in3
:
17753 inst
.cond
= cond
->value
;
17756 case OT_unconditional
:
17757 case OT_unconditionalF
:
17759 inst
.cond
= cond
->value
;
17762 /* Delayed diagnostic. */
17763 inst
.error
= BAD_COND
;
17764 inst
.cond
= COND_ALWAYS
;
17773 /* Cannot have a usual-position infix on a mnemonic of less than
17774 six characters (five would be a suffix). */
17775 if (end
- base
< 6)
17778 /* Look for infixed mnemonic in the usual position. */
17780 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17784 memcpy (save
, affix
, 2);
17785 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17786 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17788 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17789 memcpy (affix
, save
, 2);
17792 && (opcode
->tag
== OT_cinfix3
17793 || opcode
->tag
== OT_cinfix3_deprecated
17794 || opcode
->tag
== OT_csuf_or_in3
17795 || opcode
->tag
== OT_cinfix3_legacy
))
17798 if (warn_on_deprecated
&& unified_syntax
17799 && (opcode
->tag
== OT_cinfix3
17800 || opcode
->tag
== OT_cinfix3_deprecated
))
17801 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17803 inst
.cond
= cond
->value
;
17810 /* This function generates an initial IT instruction, leaving its block
17811 virtually open for the new instructions. Eventually,
17812 the mask will be updated by now_it_add_mask () each time
17813 a new instruction needs to be included in the IT block.
17814 Finally, the block is closed with close_automatic_it_block ().
17815 The block closure can be requested either from md_assemble (),
17816 a tencode (), or due to a label hook. */
17819 new_automatic_it_block (int cond
)
17821 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17822 now_it
.mask
= 0x18;
17824 now_it
.block_length
= 1;
17825 mapping_state (MAP_THUMB
);
17826 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17827 now_it
.warn_deprecated
= FALSE
;
17828 now_it
.insn_cond
= TRUE
;
17831 /* Close an automatic IT block.
17832 See comments in new_automatic_it_block (). */
17835 close_automatic_it_block (void)
17837 now_it
.mask
= 0x10;
17838 now_it
.block_length
= 0;
17841 /* Update the mask of the current automatically-generated IT
17842 instruction. See comments in new_automatic_it_block (). */
17845 now_it_add_mask (int cond
)
17847 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17848 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17849 | ((bitvalue) << (nbit)))
17850 const int resulting_bit
= (cond
& 1);
17852 now_it
.mask
&= 0xf;
17853 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17855 (5 - now_it
.block_length
));
17856 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17858 ((5 - now_it
.block_length
) - 1) );
17859 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17862 #undef SET_BIT_VALUE
17865 /* The IT blocks handling machinery is accessed through the these functions:
17866 it_fsm_pre_encode () from md_assemble ()
17867 set_it_insn_type () optional, from the tencode functions
17868 set_it_insn_type_last () ditto
17869 in_it_block () ditto
17870 it_fsm_post_encode () from md_assemble ()
17871 force_automatic_it_block_close () from label habdling functions
17874 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17875 initializing the IT insn type with a generic initial value depending
17876 on the inst.condition.
17877 2) During the tencode function, two things may happen:
17878 a) The tencode function overrides the IT insn type by
17879 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17880 b) The tencode function queries the IT block state by
17881 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17883 Both set_it_insn_type and in_it_block run the internal FSM state
17884 handling function (handle_it_state), because: a) setting the IT insn
17885 type may incur in an invalid state (exiting the function),
17886 and b) querying the state requires the FSM to be updated.
17887 Specifically we want to avoid creating an IT block for conditional
17888 branches, so it_fsm_pre_encode is actually a guess and we can't
17889 determine whether an IT block is required until the tencode () routine
17890 has decided what type of instruction this actually it.
17891 Because of this, if set_it_insn_type and in_it_block have to be used,
17892 set_it_insn_type has to be called first.
17894 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17895 determines the insn IT type depending on the inst.cond code.
17896 When a tencode () routine encodes an instruction that can be
17897 either outside an IT block, or, in the case of being inside, has to be
17898 the last one, set_it_insn_type_last () will determine the proper
17899 IT instruction type based on the inst.cond code. Otherwise,
17900 set_it_insn_type can be called for overriding that logic or
17901 for covering other cases.
17903 Calling handle_it_state () may not transition the IT block state to
17904 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17905 still queried. Instead, if the FSM determines that the state should
17906 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17907 after the tencode () function: that's what it_fsm_post_encode () does.
17909 Since in_it_block () calls the state handling function to get an
17910 updated state, an error may occur (due to invalid insns combination).
17911 In that case, inst.error is set.
17912 Therefore, inst.error has to be checked after the execution of
17913 the tencode () routine.
17915 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17916 any pending state change (if any) that didn't take place in
17917 handle_it_state () as explained above. */
17920 it_fsm_pre_encode (void)
17922 if (inst
.cond
!= COND_ALWAYS
)
17923 inst
.it_insn_type
= INSIDE_IT_INSN
;
17925 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17927 now_it
.state_handled
= 0;
17930 /* IT state FSM handling function. */
17933 handle_it_state (void)
17935 now_it
.state_handled
= 1;
17936 now_it
.insn_cond
= FALSE
;
17938 switch (now_it
.state
)
17940 case OUTSIDE_IT_BLOCK
:
17941 switch (inst
.it_insn_type
)
17943 case OUTSIDE_IT_INSN
:
17946 case INSIDE_IT_INSN
:
17947 case INSIDE_IT_LAST_INSN
:
17948 if (thumb_mode
== 0)
17951 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17952 as_tsktsk (_("Warning: conditional outside an IT block"\
17957 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17958 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17960 /* Automatically generate the IT instruction. */
17961 new_automatic_it_block (inst
.cond
);
17962 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17963 close_automatic_it_block ();
17967 inst
.error
= BAD_OUT_IT
;
17973 case IF_INSIDE_IT_LAST_INSN
:
17974 case NEUTRAL_IT_INSN
:
17978 now_it
.state
= MANUAL_IT_BLOCK
;
17979 now_it
.block_length
= 0;
17984 case AUTOMATIC_IT_BLOCK
:
17985 /* Three things may happen now:
17986 a) We should increment current it block size;
17987 b) We should close current it block (closing insn or 4 insns);
17988 c) We should close current it block and start a new one (due
17989 to incompatible conditions or
17990 4 insns-length block reached). */
17992 switch (inst
.it_insn_type
)
17994 case OUTSIDE_IT_INSN
:
17995 /* The closure of the block shall happen immediatelly,
17996 so any in_it_block () call reports the block as closed. */
17997 force_automatic_it_block_close ();
18000 case INSIDE_IT_INSN
:
18001 case INSIDE_IT_LAST_INSN
:
18002 case IF_INSIDE_IT_LAST_INSN
:
18003 now_it
.block_length
++;
18005 if (now_it
.block_length
> 4
18006 || !now_it_compatible (inst
.cond
))
18008 force_automatic_it_block_close ();
18009 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18010 new_automatic_it_block (inst
.cond
);
18014 now_it
.insn_cond
= TRUE
;
18015 now_it_add_mask (inst
.cond
);
18018 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18019 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18020 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18021 close_automatic_it_block ();
18024 case NEUTRAL_IT_INSN
:
18025 now_it
.block_length
++;
18026 now_it
.insn_cond
= TRUE
;
18028 if (now_it
.block_length
> 4)
18029 force_automatic_it_block_close ();
18031 now_it_add_mask (now_it
.cc
& 1);
18035 close_automatic_it_block ();
18036 now_it
.state
= MANUAL_IT_BLOCK
;
18041 case MANUAL_IT_BLOCK
:
18043 /* Check conditional suffixes. */
18044 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18047 now_it
.mask
&= 0x1f;
18048 is_last
= (now_it
.mask
== 0x10);
18049 now_it
.insn_cond
= TRUE
;
18051 switch (inst
.it_insn_type
)
18053 case OUTSIDE_IT_INSN
:
18054 inst
.error
= BAD_NOT_IT
;
18057 case INSIDE_IT_INSN
:
18058 if (cond
!= inst
.cond
)
18060 inst
.error
= BAD_IT_COND
;
18065 case INSIDE_IT_LAST_INSN
:
18066 case IF_INSIDE_IT_LAST_INSN
:
18067 if (cond
!= inst
.cond
)
18069 inst
.error
= BAD_IT_COND
;
18074 inst
.error
= BAD_BRANCH
;
18079 case NEUTRAL_IT_INSN
:
18080 /* The BKPT instruction is unconditional even in an IT block. */
18084 inst
.error
= BAD_IT_IT
;
18094 struct depr_insn_mask
18096 unsigned long pattern
;
18097 unsigned long mask
;
18098 const char* description
;
18101 /* List of 16-bit instruction patterns deprecated in an IT block in
18103 static const struct depr_insn_mask depr_it_insns
[] = {
18104 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18105 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18106 { 0xa000, 0xb800, N_("ADR") },
18107 { 0x4800, 0xf800, N_("Literal loads") },
18108 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18109 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18110 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18111 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18112 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18117 it_fsm_post_encode (void)
18121 if (!now_it
.state_handled
)
18122 handle_it_state ();
18124 if (now_it
.insn_cond
18125 && !now_it
.warn_deprecated
18126 && warn_on_deprecated
18127 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18129 if (inst
.instruction
>= 0x10000)
18131 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18132 "deprecated in ARMv8"));
18133 now_it
.warn_deprecated
= TRUE
;
18137 const struct depr_insn_mask
*p
= depr_it_insns
;
18139 while (p
->mask
!= 0)
18141 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18143 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18144 "of the following class are deprecated in ARMv8: "
18145 "%s"), p
->description
);
18146 now_it
.warn_deprecated
= TRUE
;
18154 if (now_it
.block_length
> 1)
18156 as_tsktsk (_("IT blocks containing more than one conditional "
18157 "instruction are deprecated in ARMv8"));
18158 now_it
.warn_deprecated
= TRUE
;
18162 is_last
= (now_it
.mask
== 0x10);
18165 now_it
.state
= OUTSIDE_IT_BLOCK
;
18171 force_automatic_it_block_close (void)
18173 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18175 close_automatic_it_block ();
18176 now_it
.state
= OUTSIDE_IT_BLOCK
;
18184 if (!now_it
.state_handled
)
18185 handle_it_state ();
18187 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18190 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18191 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18192 here, hence the "known" in the function name. */
18195 known_t32_only_insn (const struct asm_opcode
*opcode
)
18197 /* Original Thumb-1 wide instruction. */
18198 if (opcode
->tencode
== do_t_blx
18199 || opcode
->tencode
== do_t_branch23
18200 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18201 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18204 /* Wide-only instruction added to ARMv8-M Baseline. */
18205 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18206 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18207 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18208 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18214 /* Whether wide instruction variant can be used if available for a valid OPCODE
18218 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18220 if (known_t32_only_insn (opcode
))
18223 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18224 of variant T3 of B.W is checked in do_t_branch. */
18225 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18226 && opcode
->tencode
== do_t_branch
)
18229 /* Wide instruction variants of all instructions with narrow *and* wide
18230 variants become available with ARMv6t2. Other opcodes are either
18231 narrow-only or wide-only and are thus available if OPCODE is valid. */
18232 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18235 /* OPCODE with narrow only instruction variant or wide variant not
18241 md_assemble (char *str
)
18244 const struct asm_opcode
* opcode
;
18246 /* Align the previous label if needed. */
18247 if (last_label_seen
!= NULL
)
18249 symbol_set_frag (last_label_seen
, frag_now
);
18250 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18251 S_SET_SEGMENT (last_label_seen
, now_seg
);
18254 memset (&inst
, '\0', sizeof (inst
));
18255 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18257 opcode
= opcode_lookup (&p
);
18260 /* It wasn't an instruction, but it might be a register alias of
18261 the form alias .req reg, or a Neon .dn/.qn directive. */
18262 if (! create_register_alias (str
, p
)
18263 && ! create_neon_reg_alias (str
, p
))
18264 as_bad (_("bad instruction `%s'"), str
);
18269 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18270 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18272 /* The value which unconditional instructions should have in place of the
18273 condition field. */
18274 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18278 arm_feature_set variant
;
18280 variant
= cpu_variant
;
18281 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18282 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18283 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18284 /* Check that this instruction is supported for this CPU. */
18285 if (!opcode
->tvariant
18286 || (thumb_mode
== 1
18287 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18289 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18292 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18293 && opcode
->tencode
!= do_t_branch
)
18295 as_bad (_("Thumb does not support conditional execution"));
18299 /* Two things are addressed here:
18300 1) Implicit require narrow instructions on Thumb-1.
18301 This avoids relaxation accidentally introducing Thumb-2
18303 2) Reject wide instructions in non Thumb-2 cores.
18305 Only instructions with narrow and wide variants need to be handled
18306 but selecting all non wide-only instructions is easier. */
18307 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18308 && !t32_insn_ok (variant
, opcode
))
18310 if (inst
.size_req
== 0)
18312 else if (inst
.size_req
== 4)
18314 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18315 as_bad (_("selected processor does not support 32bit wide "
18316 "variant of instruction `%s'"), str
);
18318 as_bad (_("selected processor does not support `%s' in "
18319 "Thumb-2 mode"), str
);
18324 inst
.instruction
= opcode
->tvalue
;
18326 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18328 /* Prepare the it_insn_type for those encodings that don't set
18330 it_fsm_pre_encode ();
18332 opcode
->tencode ();
18334 it_fsm_post_encode ();
18337 if (!(inst
.error
|| inst
.relax
))
18339 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18340 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18341 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18343 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18348 /* Something has gone badly wrong if we try to relax a fixed size
18350 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18352 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18353 *opcode
->tvariant
);
18354 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18355 set those bits when Thumb-2 32-bit instructions are seen. The impact
18356 of relaxable instructions will be considered later after we finish all
18358 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18359 variant
= arm_arch_none
;
18361 variant
= cpu_variant
;
18362 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18363 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18366 check_neon_suffixes
;
18370 mapping_state (MAP_THUMB
);
18373 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18377 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18378 is_bx
= (opcode
->aencode
== do_bx
);
18380 /* Check that this instruction is supported for this CPU. */
18381 if (!(is_bx
&& fix_v4bx
)
18382 && !(opcode
->avariant
&&
18383 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18385 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18390 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18394 inst
.instruction
= opcode
->avalue
;
18395 if (opcode
->tag
== OT_unconditionalF
)
18396 inst
.instruction
|= 0xFU
<< 28;
18398 inst
.instruction
|= inst
.cond
<< 28;
18399 inst
.size
= INSN_SIZE
;
18400 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18402 it_fsm_pre_encode ();
18403 opcode
->aencode ();
18404 it_fsm_post_encode ();
18406 /* Arm mode bx is marked as both v4T and v5 because it's still required
18407 on a hypothetical non-thumb v5 core. */
18409 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18411 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18412 *opcode
->avariant
);
18414 check_neon_suffixes
;
18418 mapping_state (MAP_ARM
);
18423 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18431 check_it_blocks_finished (void)
18436 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18437 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18438 == MANUAL_IT_BLOCK
)
18440 as_warn (_("section '%s' finished with an open IT block."),
18444 if (now_it
.state
== MANUAL_IT_BLOCK
)
18445 as_warn (_("file finished with an open IT block."));
18449 /* Various frobbings of labels and their addresses. */
18452 arm_start_line_hook (void)
18454 last_label_seen
= NULL
;
18458 arm_frob_label (symbolS
* sym
)
18460 last_label_seen
= sym
;
18462 ARM_SET_THUMB (sym
, thumb_mode
);
18464 #if defined OBJ_COFF || defined OBJ_ELF
18465 ARM_SET_INTERWORK (sym
, support_interwork
);
18468 force_automatic_it_block_close ();
18470 /* Note - do not allow local symbols (.Lxxx) to be labelled
18471 as Thumb functions. This is because these labels, whilst
18472 they exist inside Thumb code, are not the entry points for
18473 possible ARM->Thumb calls. Also, these labels can be used
18474 as part of a computed goto or switch statement. eg gcc
18475 can generate code that looks like this:
18477 ldr r2, [pc, .Laaa]
18487 The first instruction loads the address of the jump table.
18488 The second instruction converts a table index into a byte offset.
18489 The third instruction gets the jump address out of the table.
18490 The fourth instruction performs the jump.
18492 If the address stored at .Laaa is that of a symbol which has the
18493 Thumb_Func bit set, then the linker will arrange for this address
18494 to have the bottom bit set, which in turn would mean that the
18495 address computation performed by the third instruction would end
18496 up with the bottom bit set. Since the ARM is capable of unaligned
18497 word loads, the instruction would then load the incorrect address
18498 out of the jump table, and chaos would ensue. */
18499 if (label_is_thumb_function_name
18500 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18501 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18503 /* When the address of a Thumb function is taken the bottom
18504 bit of that address should be set. This will allow
18505 interworking between Arm and Thumb functions to work
18508 THUMB_SET_FUNC (sym
, 1);
18510 label_is_thumb_function_name
= FALSE
;
18513 dwarf2_emit_label (sym
);
18517 arm_data_in_code (void)
18519 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18521 *input_line_pointer
= '/';
18522 input_line_pointer
+= 5;
18523 *input_line_pointer
= 0;
18531 arm_canonicalize_symbol_name (char * name
)
18535 if (thumb_mode
&& (len
= strlen (name
)) > 5
18536 && streq (name
+ len
- 5, "/data"))
18537 *(name
+ len
- 5) = 0;
18542 /* Table of all register names defined by default. The user can
18543 define additional names with .req. Note that all register names
18544 should appear in both upper and lowercase variants. Some registers
18545 also have mixed-case names. */
18547 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18548 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18549 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18550 #define REGSET(p,t) \
18551 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18552 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18553 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18554 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18555 #define REGSETH(p,t) \
18556 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18557 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18558 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18559 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18560 #define REGSET2(p,t) \
18561 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18562 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18563 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18564 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18565 #define SPLRBANK(base,bank,t) \
18566 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18567 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18568 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18569 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18570 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18571 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18573 static const struct reg_entry reg_names
[] =
18575 /* ARM integer registers. */
18576 REGSET(r
, RN
), REGSET(R
, RN
),
18578 /* ATPCS synonyms. */
18579 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18580 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18581 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18583 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18584 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18585 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18587 /* Well-known aliases. */
18588 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18589 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18591 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18592 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18594 /* Coprocessor numbers. */
18595 REGSET(p
, CP
), REGSET(P
, CP
),
18597 /* Coprocessor register numbers. The "cr" variants are for backward
18599 REGSET(c
, CN
), REGSET(C
, CN
),
18600 REGSET(cr
, CN
), REGSET(CR
, CN
),
18602 /* ARM banked registers. */
18603 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18604 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18605 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18606 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18607 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18608 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18609 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18611 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18612 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18613 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18614 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18615 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18616 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18617 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18618 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18620 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18621 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18622 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18623 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18624 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18625 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18626 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18627 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18628 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18630 /* FPA registers. */
18631 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18632 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18634 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18635 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18637 /* VFP SP registers. */
18638 REGSET(s
,VFS
), REGSET(S
,VFS
),
18639 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18641 /* VFP DP Registers. */
18642 REGSET(d
,VFD
), REGSET(D
,VFD
),
18643 /* Extra Neon DP registers. */
18644 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18646 /* Neon QP registers. */
18647 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18649 /* VFP control registers. */
18650 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18651 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18652 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18653 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18654 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18655 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18657 /* Maverick DSP coprocessor registers. */
18658 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18659 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18661 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18662 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18663 REGDEF(dspsc
,0,DSPSC
),
18665 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18666 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18667 REGDEF(DSPSC
,0,DSPSC
),
18669 /* iWMMXt data registers - p0, c0-15. */
18670 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18672 /* iWMMXt control registers - p1, c0-3. */
18673 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18674 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18675 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18676 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18678 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18679 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18680 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18681 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18682 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18684 /* XScale accumulator registers. */
18685 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18691 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18692 within psr_required_here. */
18693 static const struct asm_psr psrs
[] =
18695 /* Backward compatibility notation. Note that "all" is no longer
18696 truly all possible PSR bits. */
18697 {"all", PSR_c
| PSR_f
},
18701 /* Individual flags. */
18707 /* Combinations of flags. */
18708 {"fs", PSR_f
| PSR_s
},
18709 {"fx", PSR_f
| PSR_x
},
18710 {"fc", PSR_f
| PSR_c
},
18711 {"sf", PSR_s
| PSR_f
},
18712 {"sx", PSR_s
| PSR_x
},
18713 {"sc", PSR_s
| PSR_c
},
18714 {"xf", PSR_x
| PSR_f
},
18715 {"xs", PSR_x
| PSR_s
},
18716 {"xc", PSR_x
| PSR_c
},
18717 {"cf", PSR_c
| PSR_f
},
18718 {"cs", PSR_c
| PSR_s
},
18719 {"cx", PSR_c
| PSR_x
},
18720 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18721 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18722 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18723 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18724 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18725 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18726 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18727 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18728 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18729 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18730 {"scf", PSR_s
| PSR_c
| PSR_f
},
18731 {"scx", PSR_s
| PSR_c
| PSR_x
},
18732 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18733 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18734 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18735 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18736 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18737 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18738 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18739 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18740 {"csf", PSR_c
| PSR_s
| PSR_f
},
18741 {"csx", PSR_c
| PSR_s
| PSR_x
},
18742 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18743 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18744 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18745 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18746 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18747 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18748 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18749 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18750 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18751 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18752 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18753 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18754 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18755 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18756 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18757 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18758 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18759 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18760 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18761 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18762 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18763 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18764 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18765 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18766 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18767 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18770 /* Table of V7M psr names. */
18771 static const struct asm_psr v7m_psrs
[] =
18773 {"apsr", 0 }, {"APSR", 0 },
18774 {"iapsr", 1 }, {"IAPSR", 1 },
18775 {"eapsr", 2 }, {"EAPSR", 2 },
18776 {"psr", 3 }, {"PSR", 3 },
18777 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18778 {"ipsr", 5 }, {"IPSR", 5 },
18779 {"epsr", 6 }, {"EPSR", 6 },
18780 {"iepsr", 7 }, {"IEPSR", 7 },
18781 {"msp", 8 }, {"MSP", 8 }, {"msp_s", 8 }, {"MSP_S", 8 },
18782 {"psp", 9 }, {"PSP", 9 }, {"psp_s", 9 }, {"PSP_S", 9 },
18783 {"primask", 16}, {"PRIMASK", 16},
18784 {"basepri", 17}, {"BASEPRI", 17},
18785 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18786 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18787 {"faultmask", 19}, {"FAULTMASK", 19},
18788 {"control", 20}, {"CONTROL", 20},
18789 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
18790 {"psp_ns", 0x89}, {"PSP_NS", 0x89}
18793 /* Table of all shift-in-operand names. */
18794 static const struct asm_shift_name shift_names
[] =
18796 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18797 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18798 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18799 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18800 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18801 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18804 /* Table of all explicit relocation names. */
18806 static struct reloc_entry reloc_names
[] =
18808 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18809 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18810 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18811 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18812 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18813 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18814 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18815 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18816 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18817 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18818 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18819 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18820 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18821 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18822 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18823 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18824 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18825 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18829 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18830 static const struct asm_cond conds
[] =
18834 {"cs", 0x2}, {"hs", 0x2},
18835 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18849 #define UL_BARRIER(L,U,CODE,FEAT) \
18850 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18851 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18853 static struct asm_barrier_opt barrier_opt_names
[] =
18855 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18856 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18857 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18858 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18859 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18860 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18861 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18862 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18863 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18864 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18865 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18866 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18867 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18868 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18869 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18870 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18875 /* Table of ARM-format instructions. */
18877 /* Macros for gluing together operand strings. N.B. In all cases
18878 other than OPS0, the trailing OP_stop comes from default
18879 zero-initialization of the unspecified elements of the array. */
18880 #define OPS0() { OP_stop, }
18881 #define OPS1(a) { OP_##a, }
18882 #define OPS2(a,b) { OP_##a,OP_##b, }
18883 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18884 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18885 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18886 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18888 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18889 This is useful when mixing operands for ARM and THUMB, i.e. using the
18890 MIX_ARM_THUMB_OPERANDS macro.
18891 In order to use these macros, prefix the number of operands with _
18893 #define OPS_1(a) { a, }
18894 #define OPS_2(a,b) { a,b, }
18895 #define OPS_3(a,b,c) { a,b,c, }
18896 #define OPS_4(a,b,c,d) { a,b,c,d, }
18897 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18898 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18900 /* These macros abstract out the exact format of the mnemonic table and
18901 save some repeated characters. */
18903 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18904 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18905 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18906 THUMB_VARIANT, do_##ae, do_##te }
18908 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18909 a T_MNEM_xyz enumerator. */
18910 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18911 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18912 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18913 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18915 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18916 infix after the third character. */
18917 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18918 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18919 THUMB_VARIANT, do_##ae, do_##te }
18920 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18921 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18922 THUMB_VARIANT, do_##ae, do_##te }
18923 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18924 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18925 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18926 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18927 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18928 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18929 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18930 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18932 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18933 field is still 0xE. Many of the Thumb variants can be executed
18934 conditionally, so this is checked separately. */
18935 #define TUE(mnem, op, top, nops, ops, ae, te) \
18936 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18937 THUMB_VARIANT, do_##ae, do_##te }
18939 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18940 Used by mnemonics that have very minimal differences in the encoding for
18941 ARM and Thumb variants and can be handled in a common function. */
18942 #define TUEc(mnem, op, top, nops, ops, en) \
18943 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18944 THUMB_VARIANT, do_##en, do_##en }
18946 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18947 condition code field. */
18948 #define TUF(mnem, op, top, nops, ops, ae, te) \
18949 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18950 THUMB_VARIANT, do_##ae, do_##te }
18952 /* ARM-only variants of all the above. */
18953 #define CE(mnem, op, nops, ops, ae) \
18954 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18956 #define C3(mnem, op, nops, ops, ae) \
18957 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18959 /* Legacy mnemonics that always have conditional infix after the third
18961 #define CL(mnem, op, nops, ops, ae) \
18962 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18963 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18965 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18966 #define cCE(mnem, op, nops, ops, ae) \
18967 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18969 /* Legacy coprocessor instructions where conditional infix and conditional
18970 suffix are ambiguous. For consistency this includes all FPA instructions,
18971 not just the potentially ambiguous ones. */
18972 #define cCL(mnem, op, nops, ops, ae) \
18973 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18974 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18976 /* Coprocessor, takes either a suffix or a position-3 infix
18977 (for an FPA corner case). */
18978 #define C3E(mnem, op, nops, ops, ae) \
18979 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18980 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18982 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18983 { m1 #m2 m3, OPS##nops ops, \
18984 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18985 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18987 #define CM(m1, m2, op, nops, ops, ae) \
18988 xCM_ (m1, , m2, op, nops, ops, ae), \
18989 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18990 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18991 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18992 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18993 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18994 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18995 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18996 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18997 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18998 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18999 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19000 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19001 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19002 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19003 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19004 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19005 xCM_ (m1, le, m2, op, nops, ops, ae), \
19006 xCM_ (m1, al, m2, op, nops, ops, ae)
19008 #define UE(mnem, op, nops, ops, ae) \
19009 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19011 #define UF(mnem, op, nops, ops, ae) \
19012 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19014 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19015 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19016 use the same encoding function for each. */
19017 #define NUF(mnem, op, nops, ops, enc) \
19018 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19019 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19021 /* Neon data processing, version which indirects through neon_enc_tab for
19022 the various overloaded versions of opcodes. */
19023 #define nUF(mnem, op, nops, ops, enc) \
19024 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19025 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19027 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19029 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19030 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19031 THUMB_VARIANT, do_##enc, do_##enc }
19033 #define NCE(mnem, op, nops, ops, enc) \
19034 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19036 #define NCEF(mnem, op, nops, ops, enc) \
19037 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19039 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19040 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19041 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19042 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19044 #define nCE(mnem, op, nops, ops, enc) \
19045 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19047 #define nCEF(mnem, op, nops, ops, enc) \
19048 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19052 static const struct asm_opcode insns
[] =
19054 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19055 #define THUMB_VARIANT & arm_ext_v4t
19056 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19057 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19058 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19059 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19060 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19061 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19062 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19063 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19064 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19065 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19066 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19067 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19068 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19069 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19070 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19071 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19073 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19074 for setting PSR flag bits. They are obsolete in V6 and do not
19075 have Thumb equivalents. */
19076 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19077 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19078 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19079 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19080 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19081 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19082 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19083 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19084 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19086 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19087 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19088 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19089 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19091 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19092 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19093 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19095 OP_ADDRGLDR
),ldst
, t_ldst
),
19096 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19098 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19099 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19100 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19101 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19102 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19103 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19105 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19106 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19107 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19108 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19111 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19112 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19113 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19114 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19116 /* Thumb-compatibility pseudo ops. */
19117 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19118 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19119 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19120 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19121 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19122 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19123 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19124 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19125 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19126 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19127 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19128 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19130 /* These may simplify to neg. */
19131 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19132 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19134 #undef THUMB_VARIANT
19135 #define THUMB_VARIANT & arm_ext_v6
19137 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19139 /* V1 instructions with no Thumb analogue prior to V6T2. */
19140 #undef THUMB_VARIANT
19141 #define THUMB_VARIANT & arm_ext_v6t2
19143 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19144 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19145 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19147 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19148 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19149 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19150 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19152 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19153 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19155 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19156 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19158 /* V1 instructions with no Thumb analogue at all. */
19159 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19160 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19162 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19163 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19164 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19165 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19166 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19167 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19168 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19169 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19172 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19173 #undef THUMB_VARIANT
19174 #define THUMB_VARIANT & arm_ext_v4t
19176 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19177 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19179 #undef THUMB_VARIANT
19180 #define THUMB_VARIANT & arm_ext_v6t2
19182 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19183 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19185 /* Generic coprocessor instructions. */
19186 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19187 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19188 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19189 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19190 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19191 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19192 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19195 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19197 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19198 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19201 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19202 #undef THUMB_VARIANT
19203 #define THUMB_VARIANT & arm_ext_msr
19205 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19206 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19209 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19210 #undef THUMB_VARIANT
19211 #define THUMB_VARIANT & arm_ext_v6t2
19213 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19214 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19215 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19216 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19217 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19218 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19219 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19220 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19223 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19224 #undef THUMB_VARIANT
19225 #define THUMB_VARIANT & arm_ext_v4t
19227 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19228 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19229 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19230 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19231 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19232 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19235 #define ARM_VARIANT & arm_ext_v4t_5
19237 /* ARM Architecture 4T. */
19238 /* Note: bx (and blx) are required on V5, even if the processor does
19239 not support Thumb. */
19240 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19243 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19244 #undef THUMB_VARIANT
19245 #define THUMB_VARIANT & arm_ext_v5t
19247 /* Note: blx has 2 variants; the .value coded here is for
19248 BLX(2). Only this variant has conditional execution. */
19249 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19250 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19252 #undef THUMB_VARIANT
19253 #define THUMB_VARIANT & arm_ext_v6t2
19255 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19256 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19257 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19258 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19259 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19260 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19261 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19262 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19265 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19266 #undef THUMB_VARIANT
19267 #define THUMB_VARIANT & arm_ext_v5exp
19269 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19270 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19271 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19272 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19274 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19275 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19277 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19278 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19279 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19280 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19282 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19283 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19284 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19285 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19287 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19288 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19290 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19291 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19292 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19293 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19296 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19297 #undef THUMB_VARIANT
19298 #define THUMB_VARIANT & arm_ext_v6t2
19300 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19301 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19303 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19304 ADDRGLDRS
), ldrd
, t_ldstd
),
19306 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19307 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19310 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19312 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19315 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19316 #undef THUMB_VARIANT
19317 #define THUMB_VARIANT & arm_ext_v6
19319 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19320 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19321 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19322 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19323 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19324 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19325 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19326 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19327 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19328 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19330 #undef THUMB_VARIANT
19331 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19333 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19334 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19336 #undef THUMB_VARIANT
19337 #define THUMB_VARIANT & arm_ext_v6t2
19339 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19340 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19342 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19343 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19345 /* ARM V6 not included in V7M. */
19346 #undef THUMB_VARIANT
19347 #define THUMB_VARIANT & arm_ext_v6_notm
19348 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19349 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19350 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19351 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19352 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19353 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19354 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19355 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19356 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19357 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19358 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19359 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19360 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19361 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19362 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19363 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19364 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19365 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19366 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19368 /* ARM V6 not included in V7M (eg. integer SIMD). */
19369 #undef THUMB_VARIANT
19370 #define THUMB_VARIANT & arm_ext_v6_dsp
19371 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19372 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19373 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19374 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19375 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19376 /* Old name for QASX. */
19377 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19378 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19379 /* Old name for QSAX. */
19380 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19381 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19382 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19383 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19384 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19385 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19386 /* Old name for SASX. */
19387 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19388 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19389 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19390 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19391 /* Old name for SHASX. */
19392 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19393 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19394 /* Old name for SHSAX. */
19395 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19396 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19397 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19398 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19399 /* Old name for SSAX. */
19400 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19401 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19402 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19403 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19404 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19405 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19406 /* Old name for UASX. */
19407 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19408 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19409 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19410 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19411 /* Old name for UHASX. */
19412 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19413 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19414 /* Old name for UHSAX. */
19415 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19416 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19417 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19418 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19419 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19420 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19421 /* Old name for UQASX. */
19422 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19423 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19424 /* Old name for UQSAX. */
19425 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19426 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19427 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19428 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19429 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19430 /* Old name for USAX. */
19431 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19432 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19433 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19434 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19435 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19436 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19437 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19438 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19439 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19440 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19441 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19442 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19443 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19444 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19445 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19446 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19447 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19448 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19449 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19450 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19451 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19452 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19453 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19454 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19455 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19456 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19457 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19458 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19459 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19460 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19461 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19462 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19463 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19464 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19467 #define ARM_VARIANT & arm_ext_v6k
19468 #undef THUMB_VARIANT
19469 #define THUMB_VARIANT & arm_ext_v6k
19471 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19472 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19473 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19474 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19476 #undef THUMB_VARIANT
19477 #define THUMB_VARIANT & arm_ext_v6_notm
19478 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19480 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19481 RRnpcb
), strexd
, t_strexd
),
19483 #undef THUMB_VARIANT
19484 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19485 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19487 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19489 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19491 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19493 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19496 #define ARM_VARIANT & arm_ext_sec
19497 #undef THUMB_VARIANT
19498 #define THUMB_VARIANT & arm_ext_sec
19500 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19503 #define ARM_VARIANT & arm_ext_virt
19504 #undef THUMB_VARIANT
19505 #define THUMB_VARIANT & arm_ext_virt
19507 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19508 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19511 #define ARM_VARIANT & arm_ext_pan
19512 #undef THUMB_VARIANT
19513 #define THUMB_VARIANT & arm_ext_pan
19515 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19518 #define ARM_VARIANT & arm_ext_v6t2
19519 #undef THUMB_VARIANT
19520 #define THUMB_VARIANT & arm_ext_v6t2
19522 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19523 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19524 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19525 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19527 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19528 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19530 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19531 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19532 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19533 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19535 #undef THUMB_VARIANT
19536 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19537 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19538 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19540 /* Thumb-only instructions. */
19542 #define ARM_VARIANT NULL
19543 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19544 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19546 /* ARM does not really have an IT instruction, so always allow it.
19547 The opcode is copied from Thumb in order to allow warnings in
19548 -mimplicit-it=[never | arm] modes. */
19550 #define ARM_VARIANT & arm_ext_v1
19551 #undef THUMB_VARIANT
19552 #define THUMB_VARIANT & arm_ext_v6t2
19554 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19555 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19556 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19557 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19558 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19559 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19560 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19561 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19562 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19563 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19564 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19565 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19566 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19567 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19568 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19569 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19570 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19571 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19573 /* Thumb2 only instructions. */
19575 #define ARM_VARIANT NULL
19577 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19578 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19579 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19580 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19581 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19582 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19584 /* Hardware division instructions. */
19586 #define ARM_VARIANT & arm_ext_adiv
19587 #undef THUMB_VARIANT
19588 #define THUMB_VARIANT & arm_ext_div
19590 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19591 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19593 /* ARM V6M/V7 instructions. */
19595 #define ARM_VARIANT & arm_ext_barrier
19596 #undef THUMB_VARIANT
19597 #define THUMB_VARIANT & arm_ext_barrier
19599 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19600 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19601 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19603 /* ARM V7 instructions. */
19605 #define ARM_VARIANT & arm_ext_v7
19606 #undef THUMB_VARIANT
19607 #define THUMB_VARIANT & arm_ext_v7
19609 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19610 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19613 #define ARM_VARIANT & arm_ext_mp
19614 #undef THUMB_VARIANT
19615 #define THUMB_VARIANT & arm_ext_mp
19617 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19619 /* AArchv8 instructions. */
19621 #define ARM_VARIANT & arm_ext_v8
19623 /* Instructions shared between armv8-a and armv8-m. */
19624 #undef THUMB_VARIANT
19625 #define THUMB_VARIANT & arm_ext_atomics
19627 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19628 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19629 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19630 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19631 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19632 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19633 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19634 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19635 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19636 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19638 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19640 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19642 #undef THUMB_VARIANT
19643 #define THUMB_VARIANT & arm_ext_v8
19645 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19646 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19647 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19649 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19651 /* ARMv8 T32 only. */
19653 #define ARM_VARIANT NULL
19654 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19655 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19656 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19658 /* FP for ARMv8. */
19660 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19661 #undef THUMB_VARIANT
19662 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19664 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19665 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19666 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19667 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19668 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19669 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19670 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19671 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19672 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19673 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19674 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19675 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19676 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19677 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19678 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19679 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19680 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19682 /* Crypto v1 extensions. */
19684 #define ARM_VARIANT & fpu_crypto_ext_armv8
19685 #undef THUMB_VARIANT
19686 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19688 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19689 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19690 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19691 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19692 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19693 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19694 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19695 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19696 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19697 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19698 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19699 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19700 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19701 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19704 #define ARM_VARIANT & crc_ext_armv8
19705 #undef THUMB_VARIANT
19706 #define THUMB_VARIANT & crc_ext_armv8
19707 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19708 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19709 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19710 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19711 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19712 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19714 /* ARMv8.2 RAS extension. */
19716 #define ARM_VARIANT & arm_ext_v8_2
19717 #undef THUMB_VARIANT
19718 #define THUMB_VARIANT & arm_ext_v8_2
19719 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19722 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19723 #undef THUMB_VARIANT
19724 #define THUMB_VARIANT NULL
19726 cCE("wfs", e200110
, 1, (RR
), rd
),
19727 cCE("rfs", e300110
, 1, (RR
), rd
),
19728 cCE("wfc", e400110
, 1, (RR
), rd
),
19729 cCE("rfc", e500110
, 1, (RR
), rd
),
19731 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19732 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19733 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19734 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19736 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19737 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19738 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19739 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19741 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19742 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19743 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19744 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19745 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19746 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19747 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19748 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19749 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19750 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19751 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19752 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19754 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19755 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19756 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19757 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19758 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19759 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19760 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19761 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19762 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19763 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19764 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19765 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19767 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19768 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19769 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19770 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19771 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19772 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19773 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19774 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19775 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19776 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19777 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19778 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19780 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19783 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19787 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19788 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19789 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19790 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19791 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19793 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19800 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19804 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19813 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19817 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19826 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19839 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19852 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19856 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19861 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19865 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19869 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19874 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19878 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19880 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19881 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19882 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19887 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19891 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19893 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19894 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19895 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19900 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19904 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19917 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19930 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19932 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19933 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19934 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19936 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19937 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19938 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19939 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19940 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19941 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19942 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19943 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19944 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19945 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19946 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19947 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19949 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19950 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19951 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19952 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19953 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19954 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19955 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19956 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19957 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19958 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19959 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19960 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19962 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19963 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19964 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19965 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19966 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19967 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19968 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19969 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19970 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19971 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19972 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19973 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19975 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19976 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19977 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19978 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19979 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19980 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19981 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19982 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19983 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19984 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19985 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19986 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19988 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19991 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19995 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19996 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19997 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19998 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19999 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20001 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20008 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20012 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20021 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20024 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20025 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20027 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20030 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20034 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20038 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20043 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20047 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20049 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20050 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20051 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20056 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20060 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20062 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20063 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20064 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20069 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20073 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20075 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20076 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20077 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20082 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20086 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20088 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20089 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20090 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20092 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20093 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20094 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20095 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20096 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20097 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20098 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20099 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20100 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20101 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20102 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20103 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20105 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20106 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20107 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20108 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20109 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20110 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20111 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20112 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20113 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20114 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20115 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20116 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20118 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20119 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20120 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20121 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20123 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20124 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20125 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20126 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20127 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20128 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20129 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20130 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20131 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20132 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20133 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20134 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20136 /* The implementation of the FIX instruction is broken on some
20137 assemblers, in that it accepts a precision specifier as well as a
20138 rounding specifier, despite the fact that this is meaningless.
20139 To be more compatible, we accept it as well, though of course it
20140 does not set any bits. */
20141 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20142 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20143 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20144 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20145 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20146 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20147 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20148 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20149 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20150 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20151 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20152 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20153 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20155 /* Instructions that were new with the real FPA, call them V2. */
20157 #define ARM_VARIANT & fpu_fpa_ext_v2
20159 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20160 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20161 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20162 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20163 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20164 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20167 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20169 /* Moves and type conversions. */
20170 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20171 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20172 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20173 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20174 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20175 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20176 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20177 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20178 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20179 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20180 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20181 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20182 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20183 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20185 /* Memory operations. */
20186 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20187 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20188 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20189 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20190 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20191 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20192 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20193 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20194 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20195 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20196 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20197 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20198 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20199 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20200 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20201 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20202 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20203 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20205 /* Monadic operations. */
20206 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20207 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20208 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20210 /* Dyadic operations. */
20211 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20212 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20213 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20214 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20215 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20216 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20217 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20218 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20219 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20222 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20223 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20224 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20225 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20227 /* Double precision load/store are still present on single precision
20228 implementations. */
20229 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20230 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20231 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20232 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20233 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20234 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20235 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20236 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20237 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20238 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20241 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20243 /* Moves and type conversions. */
20244 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20245 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20246 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20247 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20248 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20249 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20250 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20251 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20252 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20253 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20254 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20255 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20256 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20258 /* Monadic operations. */
20259 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20260 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20261 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20263 /* Dyadic operations. */
20264 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20265 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20266 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20267 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20268 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20269 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20270 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20271 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20272 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20275 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20276 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20277 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20278 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20281 #define ARM_VARIANT & fpu_vfp_ext_v2
20283 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20284 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20285 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20286 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20288 /* Instructions which may belong to either the Neon or VFP instruction sets.
20289 Individual encoder functions perform additional architecture checks. */
20291 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20292 #undef THUMB_VARIANT
20293 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20295 /* These mnemonics are unique to VFP. */
20296 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20297 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20298 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20299 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20300 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20301 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20302 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20303 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20304 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20305 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20307 /* Mnemonics shared by Neon and VFP. */
20308 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20309 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20310 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20312 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20313 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20315 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20316 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20318 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20319 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20320 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20321 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20322 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20323 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20324 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20325 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20327 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20328 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20329 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20330 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20333 /* NOTE: All VMOV encoding is special-cased! */
20334 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20335 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20338 #define ARM_VARIANT & arm_ext_fp16
20339 #undef THUMB_VARIANT
20340 #define THUMB_VARIANT & arm_ext_fp16
20341 /* New instructions added from v8.2, allowing the extraction and insertion of
20342 the upper 16 bits of a 32-bit vector register. */
20343 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20344 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20346 #undef THUMB_VARIANT
20347 #define THUMB_VARIANT & fpu_neon_ext_v1
20349 #define ARM_VARIANT & fpu_neon_ext_v1
20351 /* Data processing with three registers of the same length. */
20352 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20353 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20354 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20355 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20356 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20357 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20358 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20359 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20360 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20361 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20362 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20363 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20364 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20365 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20366 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20367 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20368 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20369 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20370 /* If not immediate, fall back to neon_dyadic_i64_su.
20371 shl_imm should accept I8 I16 I32 I64,
20372 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20373 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20374 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20375 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20376 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20377 /* Logic ops, types optional & ignored. */
20378 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20379 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20380 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20381 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20382 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20383 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20384 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20385 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20386 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20387 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20388 /* Bitfield ops, untyped. */
20389 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20390 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20391 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20392 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20393 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20394 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20395 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20396 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20397 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20398 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20399 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20400 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20401 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20402 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20403 back to neon_dyadic_if_su. */
20404 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20405 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20406 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20407 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20408 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20409 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20410 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20411 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20412 /* Comparison. Type I8 I16 I32 F32. */
20413 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20414 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20415 /* As above, D registers only. */
20416 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20417 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20418 /* Int and float variants, signedness unimportant. */
20419 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20420 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20421 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20422 /* Add/sub take types I8 I16 I32 I64 F32. */
20423 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20424 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20425 /* vtst takes sizes 8, 16, 32. */
20426 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20427 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20428 /* VMUL takes I8 I16 I32 F32 P8. */
20429 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20430 /* VQD{R}MULH takes S16 S32. */
20431 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20432 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20433 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20434 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20435 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20436 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20437 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20438 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20439 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20440 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20441 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20442 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20443 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20444 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20445 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20446 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20447 /* ARM v8.1 extension. */
20448 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20449 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20450 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20451 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20453 /* Two address, int/float. Types S8 S16 S32 F32. */
20454 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20455 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20457 /* Data processing with two registers and a shift amount. */
20458 /* Right shifts, and variants with rounding.
20459 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20460 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20461 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20462 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20463 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20464 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20465 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20466 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20467 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20468 /* Shift and insert. Sizes accepted 8 16 32 64. */
20469 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20470 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20471 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20472 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20473 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20474 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20475 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20476 /* Right shift immediate, saturating & narrowing, with rounding variants.
20477 Types accepted S16 S32 S64 U16 U32 U64. */
20478 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20479 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20480 /* As above, unsigned. Types accepted S16 S32 S64. */
20481 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20482 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20483 /* Right shift narrowing. Types accepted I16 I32 I64. */
20484 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20485 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20486 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20487 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20488 /* CVT with optional immediate for fixed-point variant. */
20489 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20491 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20492 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20494 /* Data processing, three registers of different lengths. */
20495 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20496 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20497 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20498 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20499 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20500 /* If not scalar, fall back to neon_dyadic_long.
20501 Vector types as above, scalar types S16 S32 U16 U32. */
20502 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20503 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20504 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20505 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20506 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20507 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20508 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20509 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20510 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20511 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20512 /* Saturating doubling multiplies. Types S16 S32. */
20513 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20514 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20515 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20516 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20517 S16 S32 U16 U32. */
20518 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20520 /* Extract. Size 8. */
20521 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20522 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20524 /* Two registers, miscellaneous. */
20525 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20526 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20527 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20528 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20529 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20530 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20531 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20532 /* Vector replicate. Sizes 8 16 32. */
20533 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20534 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20535 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20536 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20537 /* VMOVN. Types I16 I32 I64. */
20538 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20539 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20540 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20541 /* VQMOVUN. Types S16 S32 S64. */
20542 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20543 /* VZIP / VUZP. Sizes 8 16 32. */
20544 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20545 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20546 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20547 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20548 /* VQABS / VQNEG. Types S8 S16 S32. */
20549 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20550 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20551 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20552 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20553 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20554 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20555 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20556 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20557 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20558 /* Reciprocal estimates. Types U32 F16 F32. */
20559 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20560 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20561 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20562 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20563 /* VCLS. Types S8 S16 S32. */
20564 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20565 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20566 /* VCLZ. Types I8 I16 I32. */
20567 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20568 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20569 /* VCNT. Size 8. */
20570 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20571 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20572 /* Two address, untyped. */
20573 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20574 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20575 /* VTRN. Sizes 8 16 32. */
20576 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20577 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20579 /* Table lookup. Size 8. */
20580 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20581 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20583 #undef THUMB_VARIANT
20584 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20586 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20588 /* Neon element/structure load/store. */
20589 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20590 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20591 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20592 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20593 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20594 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20595 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20596 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20598 #undef THUMB_VARIANT
20599 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20601 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20602 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20603 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20604 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20605 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20606 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20607 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20608 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20609 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20610 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20612 #undef THUMB_VARIANT
20613 #define THUMB_VARIANT & fpu_vfp_ext_v3
20615 #define ARM_VARIANT & fpu_vfp_ext_v3
20617 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20618 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20619 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20620 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20621 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20622 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20623 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20624 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20625 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20628 #define ARM_VARIANT & fpu_vfp_ext_fma
20629 #undef THUMB_VARIANT
20630 #define THUMB_VARIANT & fpu_vfp_ext_fma
20631 /* Mnemonics shared by Neon and VFP. These are included in the
20632 VFP FMA variant; NEON and VFP FMA always includes the NEON
20633 FMA instructions. */
20634 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20635 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20636 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20637 the v form should always be used. */
20638 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20639 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20640 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20641 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20642 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20643 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20645 #undef THUMB_VARIANT
20647 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20649 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20650 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20651 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20652 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20653 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20654 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20655 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20656 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20659 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20661 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20662 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20663 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20664 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20665 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20666 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20667 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20668 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20669 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20670 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20671 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20672 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20673 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20674 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20675 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20676 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20677 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20678 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20679 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20680 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20681 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20682 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20683 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20684 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20685 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20686 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20687 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20688 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20689 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20690 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20691 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20692 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20693 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20694 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20695 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20696 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20697 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20698 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20699 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20700 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20701 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20702 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20703 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20704 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20705 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20706 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20707 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20708 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20709 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20710 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20711 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20712 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20713 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20714 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20715 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20716 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20717 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20718 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20719 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20720 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20721 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20722 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20723 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20724 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20725 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20726 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20727 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20728 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20729 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20730 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20731 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20732 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20733 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20734 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20735 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20736 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20737 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20738 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20739 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20740 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20741 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20744 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20745 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20746 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20747 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20748 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20749 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20750 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20751 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20752 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20753 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20754 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20755 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20756 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20757 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20758 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20759 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20760 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20761 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20762 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20763 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20764 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20765 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20766 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20767 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20768 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20769 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20770 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20771 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20772 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20773 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20774 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20775 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20776 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20777 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20778 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20779 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20780 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20781 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20782 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20783 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20784 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20785 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20786 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20787 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20788 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20789 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20790 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20791 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20792 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20793 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20794 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20795 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20796 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20797 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20798 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20799 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20800 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20801 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20802 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20803 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20804 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20805 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20806 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20807 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20808 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20809 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20810 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20811 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20812 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20813 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20814 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20815 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20816 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20817 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20818 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20819 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20820 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20821 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20822 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20825 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20827 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20828 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20829 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20830 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20831 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20832 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20833 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20834 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20835 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20836 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20837 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20838 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20839 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20840 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20841 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20842 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20843 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20844 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20845 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20846 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20847 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20848 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20849 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20850 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20851 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20852 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20853 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20854 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20855 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20856 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20857 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20858 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20859 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20860 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20861 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20862 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20863 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20864 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20865 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20866 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20867 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20868 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20869 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20870 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20871 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20872 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20873 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20874 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20875 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20876 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20877 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20878 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20879 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20880 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20881 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20882 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20883 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20886 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20888 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20889 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20890 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20891 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20892 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20893 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20894 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20895 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20896 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20897 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20898 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20899 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20900 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20901 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20902 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20903 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20904 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20905 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20906 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20907 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20908 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20909 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20910 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20911 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20912 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20913 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20914 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20915 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20916 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20917 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20918 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20919 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20920 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20921 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20922 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20923 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20924 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20925 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20926 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20927 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20928 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20929 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20930 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20931 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20932 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20933 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20934 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20935 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20936 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20937 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20938 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20939 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20940 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20941 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20942 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20943 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20944 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20945 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20946 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20947 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20948 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20949 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20950 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20951 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20952 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20953 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20954 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20955 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20956 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20957 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20958 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20959 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20960 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20961 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20962 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20963 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20965 /* ARMv8-M instructions. */
20967 #define ARM_VARIANT NULL
20968 #undef THUMB_VARIANT
20969 #define THUMB_VARIANT & arm_ext_v8m
20970 TUE("sg", 0, e97fe97f
, 0, (), 0, noargs
),
20971 TUE("blxns", 0, 4784, 1, (RRnpc
), 0, t_blx
),
20972 TUE("bxns", 0, 4704, 1, (RRnpc
), 0, t_bx
),
20973 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
20974 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
20975 TUE("tta", 0, e840f080
, 2, (RRnpc
, RRnpc
), 0, tt
),
20976 TUE("ttat", 0, e840f0c0
, 2, (RRnpc
, RRnpc
), 0, tt
),
20978 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
20979 instructions behave as nop if no VFP is present. */
20980 #undef THUMB_VARIANT
20981 #define THUMB_VARIANT & arm_ext_v8m_main
20982 TUEc("vlldm", 0, ec300a00
, 1, (RRnpc
), rn
),
20983 TUEc("vlstm", 0, ec200a00
, 1, (RRnpc
), rn
),
20986 #undef THUMB_VARIANT
21012 /* MD interface: bits in the object file. */
21014 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21015 for use in the a.out file, and stores them in the array pointed to by buf.
21016 This knows about the endian-ness of the target machine and does
21017 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21018 2 (short) and 4 (long) Floating numbers are put out as a series of
21019 LITTLENUMS (shorts, here at least). */
21022 md_number_to_chars (char * buf
, valueT val
, int n
)
21024 if (target_big_endian
)
21025 number_to_chars_bigendian (buf
, val
, n
);
21027 number_to_chars_littleendian (buf
, val
, n
);
21031 md_chars_to_number (char * buf
, int n
)
21034 unsigned char * where
= (unsigned char *) buf
;
21036 if (target_big_endian
)
21041 result
|= (*where
++ & 255);
21049 result
|= (where
[n
] & 255);
21056 /* MD interface: Sections. */
21058 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21059 that an rs_machine_dependent frag may reach. */
21062 arm_frag_max_var (fragS
*fragp
)
21064 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21065 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21067 Note that we generate relaxable instructions even for cases that don't
21068 really need it, like an immediate that's a trivial constant. So we're
21069 overestimating the instruction size for some of those cases. Rather
21070 than putting more intelligence here, it would probably be better to
21071 avoid generating a relaxation frag in the first place when it can be
21072 determined up front that a short instruction will suffice. */
21074 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21078 /* Estimate the size of a frag before relaxing. Assume everything fits in
21082 md_estimate_size_before_relax (fragS
* fragp
,
21083 segT segtype ATTRIBUTE_UNUSED
)
21089 /* Convert a machine dependent frag. */
21092 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21094 unsigned long insn
;
21095 unsigned long old_op
;
21103 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21105 old_op
= bfd_get_16(abfd
, buf
);
21106 if (fragp
->fr_symbol
)
21108 exp
.X_op
= O_symbol
;
21109 exp
.X_add_symbol
= fragp
->fr_symbol
;
21113 exp
.X_op
= O_constant
;
21115 exp
.X_add_number
= fragp
->fr_offset
;
21116 opcode
= fragp
->fr_subtype
;
21119 case T_MNEM_ldr_pc
:
21120 case T_MNEM_ldr_pc2
:
21121 case T_MNEM_ldr_sp
:
21122 case T_MNEM_str_sp
:
21129 if (fragp
->fr_var
== 4)
21131 insn
= THUMB_OP32 (opcode
);
21132 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21134 insn
|= (old_op
& 0x700) << 4;
21138 insn
|= (old_op
& 7) << 12;
21139 insn
|= (old_op
& 0x38) << 13;
21141 insn
|= 0x00000c00;
21142 put_thumb32_insn (buf
, insn
);
21143 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21147 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21149 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21152 if (fragp
->fr_var
== 4)
21154 insn
= THUMB_OP32 (opcode
);
21155 insn
|= (old_op
& 0xf0) << 4;
21156 put_thumb32_insn (buf
, insn
);
21157 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21161 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21162 exp
.X_add_number
-= 4;
21170 if (fragp
->fr_var
== 4)
21172 int r0off
= (opcode
== T_MNEM_mov
21173 || opcode
== T_MNEM_movs
) ? 0 : 8;
21174 insn
= THUMB_OP32 (opcode
);
21175 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21176 insn
|= (old_op
& 0x700) << r0off
;
21177 put_thumb32_insn (buf
, insn
);
21178 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21182 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21187 if (fragp
->fr_var
== 4)
21189 insn
= THUMB_OP32(opcode
);
21190 put_thumb32_insn (buf
, insn
);
21191 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21194 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21198 if (fragp
->fr_var
== 4)
21200 insn
= THUMB_OP32(opcode
);
21201 insn
|= (old_op
& 0xf00) << 14;
21202 put_thumb32_insn (buf
, insn
);
21203 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21206 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21209 case T_MNEM_add_sp
:
21210 case T_MNEM_add_pc
:
21211 case T_MNEM_inc_sp
:
21212 case T_MNEM_dec_sp
:
21213 if (fragp
->fr_var
== 4)
21215 /* ??? Choose between add and addw. */
21216 insn
= THUMB_OP32 (opcode
);
21217 insn
|= (old_op
& 0xf0) << 4;
21218 put_thumb32_insn (buf
, insn
);
21219 if (opcode
== T_MNEM_add_pc
)
21220 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21222 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21225 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21233 if (fragp
->fr_var
== 4)
21235 insn
= THUMB_OP32 (opcode
);
21236 insn
|= (old_op
& 0xf0) << 4;
21237 insn
|= (old_op
& 0xf) << 16;
21238 put_thumb32_insn (buf
, insn
);
21239 if (insn
& (1 << 20))
21240 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21242 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21245 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21251 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21252 (enum bfd_reloc_code_real
) reloc_type
);
21253 fixp
->fx_file
= fragp
->fr_file
;
21254 fixp
->fx_line
= fragp
->fr_line
;
21255 fragp
->fr_fix
+= fragp
->fr_var
;
21257 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21258 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21259 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21260 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21263 /* Return the size of a relaxable immediate operand instruction.
21264 SHIFT and SIZE specify the form of the allowable immediate. */
21266 relax_immediate (fragS
*fragp
, int size
, int shift
)
21272 /* ??? Should be able to do better than this. */
21273 if (fragp
->fr_symbol
)
21276 low
= (1 << shift
) - 1;
21277 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21278 offset
= fragp
->fr_offset
;
21279 /* Force misaligned offsets to 32-bit variant. */
21282 if (offset
& ~mask
)
21287 /* Get the address of a symbol during relaxation. */
21289 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21295 sym
= fragp
->fr_symbol
;
21296 sym_frag
= symbol_get_frag (sym
);
21297 know (S_GET_SEGMENT (sym
) != absolute_section
21298 || sym_frag
== &zero_address_frag
);
21299 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21301 /* If frag has yet to be reached on this pass, assume it will
21302 move by STRETCH just as we did. If this is not so, it will
21303 be because some frag between grows, and that will force
21307 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21311 /* Adjust stretch for any alignment frag. Note that if have
21312 been expanding the earlier code, the symbol may be
21313 defined in what appears to be an earlier frag. FIXME:
21314 This doesn't handle the fr_subtype field, which specifies
21315 a maximum number of bytes to skip when doing an
21317 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21319 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21322 stretch
= - ((- stretch
)
21323 & ~ ((1 << (int) f
->fr_offset
) - 1));
21325 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21337 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21340 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21345 /* Assume worst case for symbols not known to be in the same section. */
21346 if (fragp
->fr_symbol
== NULL
21347 || !S_IS_DEFINED (fragp
->fr_symbol
)
21348 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21349 || S_IS_WEAK (fragp
->fr_symbol
))
21352 val
= relaxed_symbol_addr (fragp
, stretch
);
21353 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21354 addr
= (addr
+ 4) & ~3;
21355 /* Force misaligned targets to 32-bit variant. */
21359 if (val
< 0 || val
> 1020)
21364 /* Return the size of a relaxable add/sub immediate instruction. */
21366 relax_addsub (fragS
*fragp
, asection
*sec
)
21371 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21372 op
= bfd_get_16(sec
->owner
, buf
);
21373 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21374 return relax_immediate (fragp
, 8, 0);
21376 return relax_immediate (fragp
, 3, 0);
21379 /* Return TRUE iff the definition of symbol S could be pre-empted
21380 (overridden) at link or load time. */
21382 symbol_preemptible (symbolS
*s
)
21384 /* Weak symbols can always be pre-empted. */
21388 /* Non-global symbols cannot be pre-empted. */
21389 if (! S_IS_EXTERNAL (s
))
21393 /* In ELF, a global symbol can be marked protected, or private. In that
21394 case it can't be pre-empted (other definitions in the same link unit
21395 would violate the ODR). */
21396 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21400 /* Other global symbols might be pre-empted. */
21404 /* Return the size of a relaxable branch instruction. BITS is the
21405 size of the offset field in the narrow instruction. */
21408 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21414 /* Assume worst case for symbols not known to be in the same section. */
21415 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21416 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21417 || S_IS_WEAK (fragp
->fr_symbol
))
21421 /* A branch to a function in ARM state will require interworking. */
21422 if (S_IS_DEFINED (fragp
->fr_symbol
)
21423 && ARM_IS_FUNC (fragp
->fr_symbol
))
21427 if (symbol_preemptible (fragp
->fr_symbol
))
21430 val
= relaxed_symbol_addr (fragp
, stretch
);
21431 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21434 /* Offset is a signed value *2 */
21436 if (val
>= limit
|| val
< -limit
)
21442 /* Relax a machine dependent frag. This returns the amount by which
21443 the current size of the frag should change. */
21446 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21451 oldsize
= fragp
->fr_var
;
21452 switch (fragp
->fr_subtype
)
21454 case T_MNEM_ldr_pc2
:
21455 newsize
= relax_adr (fragp
, sec
, stretch
);
21457 case T_MNEM_ldr_pc
:
21458 case T_MNEM_ldr_sp
:
21459 case T_MNEM_str_sp
:
21460 newsize
= relax_immediate (fragp
, 8, 2);
21464 newsize
= relax_immediate (fragp
, 5, 2);
21468 newsize
= relax_immediate (fragp
, 5, 1);
21472 newsize
= relax_immediate (fragp
, 5, 0);
21475 newsize
= relax_adr (fragp
, sec
, stretch
);
21481 newsize
= relax_immediate (fragp
, 8, 0);
21484 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21487 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21489 case T_MNEM_add_sp
:
21490 case T_MNEM_add_pc
:
21491 newsize
= relax_immediate (fragp
, 8, 2);
21493 case T_MNEM_inc_sp
:
21494 case T_MNEM_dec_sp
:
21495 newsize
= relax_immediate (fragp
, 7, 2);
21501 newsize
= relax_addsub (fragp
, sec
);
21507 fragp
->fr_var
= newsize
;
21508 /* Freeze wide instructions that are at or before the same location as
21509 in the previous pass. This avoids infinite loops.
21510 Don't freeze them unconditionally because targets may be artificially
21511 misaligned by the expansion of preceding frags. */
21512 if (stretch
<= 0 && newsize
> 2)
21514 md_convert_frag (sec
->owner
, sec
, fragp
);
21518 return newsize
- oldsize
;
21521 /* Round up a section size to the appropriate boundary. */
21524 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21527 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21528 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21530 /* For a.out, force the section size to be aligned. If we don't do
21531 this, BFD will align it for us, but it will not write out the
21532 final bytes of the section. This may be a bug in BFD, but it is
21533 easier to fix it here since that is how the other a.out targets
21537 align
= bfd_get_section_alignment (stdoutput
, segment
);
21538 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21545 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21546 of an rs_align_code fragment. */
21549 arm_handle_align (fragS
* fragP
)
21551 static unsigned char const arm_noop
[2][2][4] =
21554 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21555 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21558 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21559 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21562 static unsigned char const thumb_noop
[2][2][2] =
21565 {0xc0, 0x46}, /* LE */
21566 {0x46, 0xc0}, /* BE */
21569 {0x00, 0xbf}, /* LE */
21570 {0xbf, 0x00} /* BE */
21573 static unsigned char const wide_thumb_noop
[2][4] =
21574 { /* Wide Thumb-2 */
21575 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21576 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21579 unsigned bytes
, fix
, noop_size
;
21581 const unsigned char * noop
;
21582 const unsigned char *narrow_noop
= NULL
;
21587 if (fragP
->fr_type
!= rs_align_code
)
21590 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21591 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21594 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21595 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21597 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21599 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21601 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21602 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21604 narrow_noop
= thumb_noop
[1][target_big_endian
];
21605 noop
= wide_thumb_noop
[target_big_endian
];
21608 noop
= thumb_noop
[0][target_big_endian
];
21616 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21617 ? selected_cpu
: arm_arch_none
,
21619 [target_big_endian
];
21626 fragP
->fr_var
= noop_size
;
21628 if (bytes
& (noop_size
- 1))
21630 fix
= bytes
& (noop_size
- 1);
21632 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21634 memset (p
, 0, fix
);
21641 if (bytes
& noop_size
)
21643 /* Insert a narrow noop. */
21644 memcpy (p
, narrow_noop
, noop_size
);
21646 bytes
-= noop_size
;
21650 /* Use wide noops for the remainder */
21654 while (bytes
>= noop_size
)
21656 memcpy (p
, noop
, noop_size
);
21658 bytes
-= noop_size
;
21662 fragP
->fr_fix
+= fix
;
21665 /* Called from md_do_align. Used to create an alignment
21666 frag in a code section. */
21669 arm_frag_align_code (int n
, int max
)
21673 /* We assume that there will never be a requirement
21674 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21675 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21680 _("alignments greater than %d bytes not supported in .text sections."),
21681 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21682 as_fatal ("%s", err_msg
);
21685 p
= frag_var (rs_align_code
,
21686 MAX_MEM_FOR_RS_ALIGN_CODE
,
21688 (relax_substateT
) max
,
21695 /* Perform target specific initialisation of a frag.
21696 Note - despite the name this initialisation is not done when the frag
21697 is created, but only when its type is assigned. A frag can be created
21698 and used a long time before its type is set, so beware of assuming that
21699 this initialisationis performed first. */
21703 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21705 /* Record whether this frag is in an ARM or a THUMB area. */
21706 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21709 #else /* OBJ_ELF is defined. */
21711 arm_init_frag (fragS
* fragP
, int max_chars
)
21713 int frag_thumb_mode
;
21715 /* If the current ARM vs THUMB mode has not already
21716 been recorded into this frag then do so now. */
21717 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21718 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21720 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21722 /* Record a mapping symbol for alignment frags. We will delete this
21723 later if the alignment ends up empty. */
21724 switch (fragP
->fr_type
)
21727 case rs_align_test
:
21729 mapping_state_2 (MAP_DATA
, max_chars
);
21731 case rs_align_code
:
21732 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21739 /* When we change sections we need to issue a new mapping symbol. */
21742 arm_elf_change_section (void)
21744 /* Link an unlinked unwind index table section to the .text section. */
21745 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21746 && elf_linked_to_section (now_seg
) == NULL
)
21747 elf_linked_to_section (now_seg
) = text_section
;
21751 arm_elf_section_type (const char * str
, size_t len
)
21753 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21754 return SHT_ARM_EXIDX
;
21759 /* Code to deal with unwinding tables. */
21761 static void add_unwind_adjustsp (offsetT
);
21763 /* Generate any deferred unwind frame offset. */
21766 flush_pending_unwind (void)
21770 offset
= unwind
.pending_offset
;
21771 unwind
.pending_offset
= 0;
21773 add_unwind_adjustsp (offset
);
21776 /* Add an opcode to this list for this function. Two-byte opcodes should
21777 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21781 add_unwind_opcode (valueT op
, int length
)
21783 /* Add any deferred stack adjustment. */
21784 if (unwind
.pending_offset
)
21785 flush_pending_unwind ();
21787 unwind
.sp_restored
= 0;
21789 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21791 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21792 if (unwind
.opcodes
)
21793 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21794 unwind
.opcode_alloc
);
21796 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21801 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21803 unwind
.opcode_count
++;
21807 /* Add unwind opcodes to adjust the stack pointer. */
21810 add_unwind_adjustsp (offsetT offset
)
21814 if (offset
> 0x200)
21816 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21821 /* Long form: 0xb2, uleb128. */
21822 /* This might not fit in a word so add the individual bytes,
21823 remembering the list is built in reverse order. */
21824 o
= (valueT
) ((offset
- 0x204) >> 2);
21826 add_unwind_opcode (0, 1);
21828 /* Calculate the uleb128 encoding of the offset. */
21832 bytes
[n
] = o
& 0x7f;
21838 /* Add the insn. */
21840 add_unwind_opcode (bytes
[n
- 1], 1);
21841 add_unwind_opcode (0xb2, 1);
21843 else if (offset
> 0x100)
21845 /* Two short opcodes. */
21846 add_unwind_opcode (0x3f, 1);
21847 op
= (offset
- 0x104) >> 2;
21848 add_unwind_opcode (op
, 1);
21850 else if (offset
> 0)
21852 /* Short opcode. */
21853 op
= (offset
- 4) >> 2;
21854 add_unwind_opcode (op
, 1);
21856 else if (offset
< 0)
21859 while (offset
> 0x100)
21861 add_unwind_opcode (0x7f, 1);
21864 op
= ((offset
- 4) >> 2) | 0x40;
21865 add_unwind_opcode (op
, 1);
21869 /* Finish the list of unwind opcodes for this function. */
21871 finish_unwind_opcodes (void)
21875 if (unwind
.fp_used
)
21877 /* Adjust sp as necessary. */
21878 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21879 flush_pending_unwind ();
21881 /* After restoring sp from the frame pointer. */
21882 op
= 0x90 | unwind
.fp_reg
;
21883 add_unwind_opcode (op
, 1);
21886 flush_pending_unwind ();
21890 /* Start an exception table entry. If idx is nonzero this is an index table
21894 start_unwind_section (const segT text_seg
, int idx
)
21896 const char * text_name
;
21897 const char * prefix
;
21898 const char * prefix_once
;
21899 const char * group_name
;
21907 prefix
= ELF_STRING_ARM_unwind
;
21908 prefix_once
= ELF_STRING_ARM_unwind_once
;
21909 type
= SHT_ARM_EXIDX
;
21913 prefix
= ELF_STRING_ARM_unwind_info
;
21914 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21915 type
= SHT_PROGBITS
;
21918 text_name
= segment_name (text_seg
);
21919 if (streq (text_name
, ".text"))
21922 if (strncmp (text_name
, ".gnu.linkonce.t.",
21923 strlen (".gnu.linkonce.t.")) == 0)
21925 prefix
= prefix_once
;
21926 text_name
+= strlen (".gnu.linkonce.t.");
21929 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
21935 /* Handle COMDAT group. */
21936 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21938 group_name
= elf_group_name (text_seg
);
21939 if (group_name
== NULL
)
21941 as_bad (_("Group section `%s' has no group signature"),
21942 segment_name (text_seg
));
21943 ignore_rest_of_line ();
21946 flags
|= SHF_GROUP
;
21950 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21952 /* Set the section link for index tables. */
21954 elf_linked_to_section (now_seg
) = text_seg
;
21958 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21959 personality routine data. Returns zero, or the index table value for
21960 an inline entry. */
21963 create_unwind_entry (int have_data
)
21968 /* The current word of data. */
21970 /* The number of bytes left in this word. */
21973 finish_unwind_opcodes ();
21975 /* Remember the current text section. */
21976 unwind
.saved_seg
= now_seg
;
21977 unwind
.saved_subseg
= now_subseg
;
21979 start_unwind_section (now_seg
, 0);
21981 if (unwind
.personality_routine
== NULL
)
21983 if (unwind
.personality_index
== -2)
21986 as_bad (_("handlerdata in cantunwind frame"));
21987 return 1; /* EXIDX_CANTUNWIND. */
21990 /* Use a default personality routine if none is specified. */
21991 if (unwind
.personality_index
== -1)
21993 if (unwind
.opcode_count
> 3)
21994 unwind
.personality_index
= 1;
21996 unwind
.personality_index
= 0;
21999 /* Space for the personality routine entry. */
22000 if (unwind
.personality_index
== 0)
22002 if (unwind
.opcode_count
> 3)
22003 as_bad (_("too many unwind opcodes for personality routine 0"));
22007 /* All the data is inline in the index table. */
22010 while (unwind
.opcode_count
> 0)
22012 unwind
.opcode_count
--;
22013 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22017 /* Pad with "finish" opcodes. */
22019 data
= (data
<< 8) | 0xb0;
22026 /* We get two opcodes "free" in the first word. */
22027 size
= unwind
.opcode_count
- 2;
22031 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22032 if (unwind
.personality_index
!= -1)
22034 as_bad (_("attempt to recreate an unwind entry"));
22038 /* An extra byte is required for the opcode count. */
22039 size
= unwind
.opcode_count
+ 1;
22042 size
= (size
+ 3) >> 2;
22044 as_bad (_("too many unwind opcodes"));
22046 frag_align (2, 0, 0);
22047 record_alignment (now_seg
, 2);
22048 unwind
.table_entry
= expr_build_dot ();
22050 /* Allocate the table entry. */
22051 ptr
= frag_more ((size
<< 2) + 4);
22052 /* PR 13449: Zero the table entries in case some of them are not used. */
22053 memset (ptr
, 0, (size
<< 2) + 4);
22054 where
= frag_now_fix () - ((size
<< 2) + 4);
22056 switch (unwind
.personality_index
)
22059 /* ??? Should this be a PLT generating relocation? */
22060 /* Custom personality routine. */
22061 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22062 BFD_RELOC_ARM_PREL31
);
22067 /* Set the first byte to the number of additional words. */
22068 data
= size
> 0 ? size
- 1 : 0;
22072 /* ABI defined personality routines. */
22074 /* Three opcodes bytes are packed into the first word. */
22081 /* The size and first two opcode bytes go in the first word. */
22082 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22087 /* Should never happen. */
22091 /* Pack the opcodes into words (MSB first), reversing the list at the same
22093 while (unwind
.opcode_count
> 0)
22097 md_number_to_chars (ptr
, data
, 4);
22102 unwind
.opcode_count
--;
22104 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22107 /* Finish off the last word. */
22110 /* Pad with "finish" opcodes. */
22112 data
= (data
<< 8) | 0xb0;
22114 md_number_to_chars (ptr
, data
, 4);
22119 /* Add an empty descriptor if there is no user-specified data. */
22120 ptr
= frag_more (4);
22121 md_number_to_chars (ptr
, 0, 4);
22128 /* Initialize the DWARF-2 unwind information for this procedure. */
22131 tc_arm_frame_initial_instructions (void)
22133 cfi_add_CFA_def_cfa (REG_SP
, 0);
22135 #endif /* OBJ_ELF */
22137 /* Convert REGNAME to a DWARF-2 register number. */
22140 tc_arm_regname_to_dw2regnum (char *regname
)
22142 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22146 /* PR 16694: Allow VFP registers as well. */
22147 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22151 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22160 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22164 exp
.X_op
= O_secrel
;
22165 exp
.X_add_symbol
= symbol
;
22166 exp
.X_add_number
= 0;
22167 emit_expr (&exp
, size
);
22171 /* MD interface: Symbol and relocation handling. */
22173 /* Return the address within the segment that a PC-relative fixup is
22174 relative to. For ARM, PC-relative fixups applied to instructions
22175 are generally relative to the location of the fixup plus 8 bytes.
22176 Thumb branches are offset by 4, and Thumb loads relative to PC
22177 require special handling. */
22180 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22182 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22184 /* If this is pc-relative and we are going to emit a relocation
22185 then we just want to put out any pipeline compensation that the linker
22186 will need. Otherwise we want to use the calculated base.
22187 For WinCE we skip the bias for externals as well, since this
22188 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22190 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22191 || (arm_force_relocation (fixP
)
22193 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22199 switch (fixP
->fx_r_type
)
22201 /* PC relative addressing on the Thumb is slightly odd as the
22202 bottom two bits of the PC are forced to zero for the
22203 calculation. This happens *after* application of the
22204 pipeline offset. However, Thumb adrl already adjusts for
22205 this, so we need not do it again. */
22206 case BFD_RELOC_ARM_THUMB_ADD
:
22209 case BFD_RELOC_ARM_THUMB_OFFSET
:
22210 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22211 case BFD_RELOC_ARM_T32_ADD_PC12
:
22212 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22213 return (base
+ 4) & ~3;
22215 /* Thumb branches are simply offset by +4. */
22216 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22217 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22218 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22219 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22220 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22223 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22225 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22226 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22227 && ARM_IS_FUNC (fixP
->fx_addsy
)
22228 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22229 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22232 /* BLX is like branches above, but forces the low two bits of PC to
22234 case BFD_RELOC_THUMB_PCREL_BLX
:
22236 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22237 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22238 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22239 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22240 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22241 return (base
+ 4) & ~3;
22243 /* ARM mode branches are offset by +8. However, the Windows CE
22244 loader expects the relocation not to take this into account. */
22245 case BFD_RELOC_ARM_PCREL_BLX
:
22247 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22248 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22249 && ARM_IS_FUNC (fixP
->fx_addsy
)
22250 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22251 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22254 case BFD_RELOC_ARM_PCREL_CALL
:
22256 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22257 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22258 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22259 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22260 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22263 case BFD_RELOC_ARM_PCREL_BRANCH
:
22264 case BFD_RELOC_ARM_PCREL_JUMP
:
22265 case BFD_RELOC_ARM_PLT32
:
22267 /* When handling fixups immediately, because we have already
22268 discovered the value of a symbol, or the address of the frag involved
22269 we must account for the offset by +8, as the OS loader will never see the reloc.
22270 see fixup_segment() in write.c
22271 The S_IS_EXTERNAL test handles the case of global symbols.
22272 Those need the calculated base, not just the pipe compensation the linker will need. */
22274 && fixP
->fx_addsy
!= NULL
22275 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22276 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22284 /* ARM mode loads relative to PC are also offset by +8. Unlike
22285 branches, the Windows CE loader *does* expect the relocation
22286 to take this into account. */
22287 case BFD_RELOC_ARM_OFFSET_IMM
:
22288 case BFD_RELOC_ARM_OFFSET_IMM8
:
22289 case BFD_RELOC_ARM_HWLITERAL
:
22290 case BFD_RELOC_ARM_LITERAL
:
22291 case BFD_RELOC_ARM_CP_OFF_IMM
:
22295 /* Other PC-relative relocations are un-offset. */
22301 static bfd_boolean flag_warn_syms
= TRUE
;
22304 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22306 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22307 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22308 does mean that the resulting code might be very confusing to the reader.
22309 Also this warning can be triggered if the user omits an operand before
22310 an immediate address, eg:
22314 GAS treats this as an assignment of the value of the symbol foo to a
22315 symbol LDR, and so (without this code) it will not issue any kind of
22316 warning or error message.
22318 Note - ARM instructions are case-insensitive but the strings in the hash
22319 table are all stored in lower case, so we must first ensure that name is
22321 if (flag_warn_syms
&& arm_ops_hsh
)
22323 char * nbuf
= strdup (name
);
22326 for (p
= nbuf
; *p
; p
++)
22328 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22330 static struct hash_control
* already_warned
= NULL
;
22332 if (already_warned
== NULL
)
22333 already_warned
= hash_new ();
22334 /* Only warn about the symbol once. To keep the code
22335 simple we let hash_insert do the lookup for us. */
22336 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22337 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22346 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22347 Otherwise we have no need to default values of symbols. */
22350 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22353 if (name
[0] == '_' && name
[1] == 'G'
22354 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22358 if (symbol_find (name
))
22359 as_bad (_("GOT already in the symbol table"));
22361 GOT_symbol
= symbol_new (name
, undefined_section
,
22362 (valueT
) 0, & zero_address_frag
);
22372 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22373 computed as two separate immediate values, added together. We
22374 already know that this value cannot be computed by just one ARM
22377 static unsigned int
22378 validate_immediate_twopart (unsigned int val
,
22379 unsigned int * highpart
)
22384 for (i
= 0; i
< 32; i
+= 2)
22385 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22391 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22393 else if (a
& 0xff0000)
22395 if (a
& 0xff000000)
22397 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22401 gas_assert (a
& 0xff000000);
22402 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22405 return (a
& 0xff) | (i
<< 7);
22412 validate_offset_imm (unsigned int val
, int hwse
)
22414 if ((hwse
&& val
> 255) || val
> 4095)
22419 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22420 negative immediate constant by altering the instruction. A bit of
22425 by inverting the second operand, and
22428 by negating the second operand. */
22431 negate_data_op (unsigned long * instruction
,
22432 unsigned long value
)
22435 unsigned long negated
, inverted
;
22437 negated
= encode_arm_immediate (-value
);
22438 inverted
= encode_arm_immediate (~value
);
22440 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22443 /* First negates. */
22444 case OPCODE_SUB
: /* ADD <-> SUB */
22445 new_inst
= OPCODE_ADD
;
22450 new_inst
= OPCODE_SUB
;
22454 case OPCODE_CMP
: /* CMP <-> CMN */
22455 new_inst
= OPCODE_CMN
;
22460 new_inst
= OPCODE_CMP
;
22464 /* Now Inverted ops. */
22465 case OPCODE_MOV
: /* MOV <-> MVN */
22466 new_inst
= OPCODE_MVN
;
22471 new_inst
= OPCODE_MOV
;
22475 case OPCODE_AND
: /* AND <-> BIC */
22476 new_inst
= OPCODE_BIC
;
22481 new_inst
= OPCODE_AND
;
22485 case OPCODE_ADC
: /* ADC <-> SBC */
22486 new_inst
= OPCODE_SBC
;
22491 new_inst
= OPCODE_ADC
;
22495 /* We cannot do anything. */
22500 if (value
== (unsigned) FAIL
)
22503 *instruction
&= OPCODE_MASK
;
22504 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22508 /* Like negate_data_op, but for Thumb-2. */
22510 static unsigned int
22511 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22515 unsigned int negated
, inverted
;
22517 negated
= encode_thumb32_immediate (-value
);
22518 inverted
= encode_thumb32_immediate (~value
);
22520 rd
= (*instruction
>> 8) & 0xf;
22521 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22524 /* ADD <-> SUB. Includes CMP <-> CMN. */
22525 case T2_OPCODE_SUB
:
22526 new_inst
= T2_OPCODE_ADD
;
22530 case T2_OPCODE_ADD
:
22531 new_inst
= T2_OPCODE_SUB
;
22535 /* ORR <-> ORN. Includes MOV <-> MVN. */
22536 case T2_OPCODE_ORR
:
22537 new_inst
= T2_OPCODE_ORN
;
22541 case T2_OPCODE_ORN
:
22542 new_inst
= T2_OPCODE_ORR
;
22546 /* AND <-> BIC. TST has no inverted equivalent. */
22547 case T2_OPCODE_AND
:
22548 new_inst
= T2_OPCODE_BIC
;
22555 case T2_OPCODE_BIC
:
22556 new_inst
= T2_OPCODE_AND
;
22561 case T2_OPCODE_ADC
:
22562 new_inst
= T2_OPCODE_SBC
;
22566 case T2_OPCODE_SBC
:
22567 new_inst
= T2_OPCODE_ADC
;
22571 /* We cannot do anything. */
22576 if (value
== (unsigned int)FAIL
)
22579 *instruction
&= T2_OPCODE_MASK
;
22580 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22584 /* Read a 32-bit thumb instruction from buf. */
22585 static unsigned long
22586 get_thumb32_insn (char * buf
)
22588 unsigned long insn
;
22589 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22590 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22596 /* We usually want to set the low bit on the address of thumb function
22597 symbols. In particular .word foo - . should have the low bit set.
22598 Generic code tries to fold the difference of two symbols to
22599 a constant. Prevent this and force a relocation when the first symbols
22600 is a thumb function. */
22603 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22605 if (op
== O_subtract
22606 && l
->X_op
== O_symbol
22607 && r
->X_op
== O_symbol
22608 && THUMB_IS_FUNC (l
->X_add_symbol
))
22610 l
->X_op
= O_subtract
;
22611 l
->X_op_symbol
= r
->X_add_symbol
;
22612 l
->X_add_number
-= r
->X_add_number
;
22616 /* Process as normal. */
22620 /* Encode Thumb2 unconditional branches and calls. The encoding
22621 for the 2 are identical for the immediate values. */
22624 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22626 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22629 addressT S
, I1
, I2
, lo
, hi
;
22631 S
= (value
>> 24) & 0x01;
22632 I1
= (value
>> 23) & 0x01;
22633 I2
= (value
>> 22) & 0x01;
22634 hi
= (value
>> 12) & 0x3ff;
22635 lo
= (value
>> 1) & 0x7ff;
22636 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22637 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22638 newval
|= (S
<< 10) | hi
;
22639 newval2
&= ~T2I1I2MASK
;
22640 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22641 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22642 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22646 md_apply_fix (fixS
* fixP
,
22650 offsetT value
= * valP
;
22652 unsigned int newimm
;
22653 unsigned long temp
;
22655 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22657 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22659 /* Note whether this will delete the relocation. */
22661 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22664 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22665 consistency with the behaviour on 32-bit hosts. Remember value
22667 value
&= 0xffffffff;
22668 value
^= 0x80000000;
22669 value
-= 0x80000000;
22672 fixP
->fx_addnumber
= value
;
22674 /* Same treatment for fixP->fx_offset. */
22675 fixP
->fx_offset
&= 0xffffffff;
22676 fixP
->fx_offset
^= 0x80000000;
22677 fixP
->fx_offset
-= 0x80000000;
22679 switch (fixP
->fx_r_type
)
22681 case BFD_RELOC_NONE
:
22682 /* This will need to go in the object file. */
22686 case BFD_RELOC_ARM_IMMEDIATE
:
22687 /* We claim that this fixup has been processed here,
22688 even if in fact we generate an error because we do
22689 not have a reloc for it, so tc_gen_reloc will reject it. */
22692 if (fixP
->fx_addsy
)
22694 const char *msg
= 0;
22696 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22697 msg
= _("undefined symbol %s used as an immediate value");
22698 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22699 msg
= _("symbol %s is in a different section");
22700 else if (S_IS_WEAK (fixP
->fx_addsy
))
22701 msg
= _("symbol %s is weak and may be overridden later");
22705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22706 msg
, S_GET_NAME (fixP
->fx_addsy
));
22711 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22713 /* If the offset is negative, we should use encoding A2 for ADR. */
22714 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22715 newimm
= negate_data_op (&temp
, value
);
22718 newimm
= encode_arm_immediate (value
);
22720 /* If the instruction will fail, see if we can fix things up by
22721 changing the opcode. */
22722 if (newimm
== (unsigned int) FAIL
)
22723 newimm
= negate_data_op (&temp
, value
);
22726 if (newimm
== (unsigned int) FAIL
)
22728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22729 _("invalid constant (%lx) after fixup"),
22730 (unsigned long) value
);
22734 newimm
|= (temp
& 0xfffff000);
22735 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22738 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22740 unsigned int highpart
= 0;
22741 unsigned int newinsn
= 0xe1a00000; /* nop. */
22743 if (fixP
->fx_addsy
)
22745 const char *msg
= 0;
22747 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22748 msg
= _("undefined symbol %s used as an immediate value");
22749 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22750 msg
= _("symbol %s is in a different section");
22751 else if (S_IS_WEAK (fixP
->fx_addsy
))
22752 msg
= _("symbol %s is weak and may be overridden later");
22756 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22757 msg
, S_GET_NAME (fixP
->fx_addsy
));
22762 newimm
= encode_arm_immediate (value
);
22763 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22765 /* If the instruction will fail, see if we can fix things up by
22766 changing the opcode. */
22767 if (newimm
== (unsigned int) FAIL
22768 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22770 /* No ? OK - try using two ADD instructions to generate
22772 newimm
= validate_immediate_twopart (value
, & highpart
);
22774 /* Yes - then make sure that the second instruction is
22776 if (newimm
!= (unsigned int) FAIL
)
22778 /* Still No ? Try using a negated value. */
22779 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22780 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22781 /* Otherwise - give up. */
22784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22785 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22790 /* Replace the first operand in the 2nd instruction (which
22791 is the PC) with the destination register. We have
22792 already added in the PC in the first instruction and we
22793 do not want to do it again. */
22794 newinsn
&= ~ 0xf0000;
22795 newinsn
|= ((newinsn
& 0x0f000) << 4);
22798 newimm
|= (temp
& 0xfffff000);
22799 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22801 highpart
|= (newinsn
& 0xfffff000);
22802 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22806 case BFD_RELOC_ARM_OFFSET_IMM
:
22807 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22810 case BFD_RELOC_ARM_LITERAL
:
22816 if (validate_offset_imm (value
, 0) == FAIL
)
22818 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22820 _("invalid literal constant: pool needs to be closer"));
22822 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22823 _("bad immediate value for offset (%ld)"),
22828 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22830 newval
&= 0xfffff000;
22833 newval
&= 0xff7ff000;
22834 newval
|= value
| (sign
? INDEX_UP
: 0);
22836 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22839 case BFD_RELOC_ARM_OFFSET_IMM8
:
22840 case BFD_RELOC_ARM_HWLITERAL
:
22846 if (validate_offset_imm (value
, 1) == FAIL
)
22848 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22850 _("invalid literal constant: pool needs to be closer"));
22852 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22853 _("bad immediate value for 8-bit offset (%ld)"),
22858 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22860 newval
&= 0xfffff0f0;
22863 newval
&= 0xff7ff0f0;
22864 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22866 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22869 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22870 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22872 _("bad immediate value for offset (%ld)"), (long) value
);
22875 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22877 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22880 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22881 /* This is a complicated relocation used for all varieties of Thumb32
22882 load/store instruction with immediate offset:
22884 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22885 *4, optional writeback(W)
22886 (doubleword load/store)
22888 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22889 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22890 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22891 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22892 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22894 Uppercase letters indicate bits that are already encoded at
22895 this point. Lowercase letters are our problem. For the
22896 second block of instructions, the secondary opcode nybble
22897 (bits 8..11) is present, and bit 23 is zero, even if this is
22898 a PC-relative operation. */
22899 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22901 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22903 if ((newval
& 0xf0000000) == 0xe0000000)
22905 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22907 newval
|= (1 << 23);
22910 if (value
% 4 != 0)
22912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22913 _("offset not a multiple of 4"));
22919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22920 _("offset out of range"));
22925 else if ((newval
& 0x000f0000) == 0x000f0000)
22927 /* PC-relative, 12-bit offset. */
22929 newval
|= (1 << 23);
22934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22935 _("offset out of range"));
22940 else if ((newval
& 0x00000100) == 0x00000100)
22942 /* Writeback: 8-bit, +/- offset. */
22944 newval
|= (1 << 9);
22949 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22950 _("offset out of range"));
22955 else if ((newval
& 0x00000f00) == 0x00000e00)
22957 /* T-instruction: positive 8-bit offset. */
22958 if (value
< 0 || value
> 0xff)
22960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22961 _("offset out of range"));
22969 /* Positive 12-bit or negative 8-bit offset. */
22973 newval
|= (1 << 23);
22983 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22984 _("offset out of range"));
22991 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22992 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22995 case BFD_RELOC_ARM_SHIFT_IMM
:
22996 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22997 if (((unsigned long) value
) > 32
22999 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23002 _("shift expression is too large"));
23007 /* Shifts of zero must be done as lsl. */
23009 else if (value
== 32)
23011 newval
&= 0xfffff07f;
23012 newval
|= (value
& 0x1f) << 7;
23013 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23016 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23017 case BFD_RELOC_ARM_T32_ADD_IMM
:
23018 case BFD_RELOC_ARM_T32_IMM12
:
23019 case BFD_RELOC_ARM_T32_ADD_PC12
:
23020 /* We claim that this fixup has been processed here,
23021 even if in fact we generate an error because we do
23022 not have a reloc for it, so tc_gen_reloc will reject it. */
23026 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23028 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23029 _("undefined symbol %s used as an immediate value"),
23030 S_GET_NAME (fixP
->fx_addsy
));
23034 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23036 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23039 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23040 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23042 newimm
= encode_thumb32_immediate (value
);
23043 if (newimm
== (unsigned int) FAIL
)
23044 newimm
= thumb32_negate_data_op (&newval
, value
);
23046 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
23047 && newimm
== (unsigned int) FAIL
)
23049 /* Turn add/sum into addw/subw. */
23050 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23051 newval
= (newval
& 0xfeffffff) | 0x02000000;
23052 /* No flat 12-bit imm encoding for addsw/subsw. */
23053 if ((newval
& 0x00100000) == 0)
23055 /* 12 bit immediate for addw/subw. */
23059 newval
^= 0x00a00000;
23062 newimm
= (unsigned int) FAIL
;
23068 if (newimm
== (unsigned int)FAIL
)
23070 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23071 _("invalid constant (%lx) after fixup"),
23072 (unsigned long) value
);
23076 newval
|= (newimm
& 0x800) << 15;
23077 newval
|= (newimm
& 0x700) << 4;
23078 newval
|= (newimm
& 0x0ff);
23080 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23081 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23084 case BFD_RELOC_ARM_SMC
:
23085 if (((unsigned long) value
) > 0xffff)
23086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23087 _("invalid smc expression"));
23088 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23089 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23090 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23093 case BFD_RELOC_ARM_HVC
:
23094 if (((unsigned long) value
) > 0xffff)
23095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23096 _("invalid hvc expression"));
23097 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23098 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23099 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23102 case BFD_RELOC_ARM_SWI
:
23103 if (fixP
->tc_fix_data
!= 0)
23105 if (((unsigned long) value
) > 0xff)
23106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23107 _("invalid swi expression"));
23108 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23110 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23114 if (((unsigned long) value
) > 0x00ffffff)
23115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23116 _("invalid swi expression"));
23117 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23119 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23123 case BFD_RELOC_ARM_MULTI
:
23124 if (((unsigned long) value
) > 0xffff)
23125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23126 _("invalid expression in load/store multiple"));
23127 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23128 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23132 case BFD_RELOC_ARM_PCREL_CALL
:
23134 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23136 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23137 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23138 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23139 /* Flip the bl to blx. This is a simple flip
23140 bit here because we generate PCREL_CALL for
23141 unconditional bls. */
23143 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23144 newval
= newval
| 0x10000000;
23145 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23151 goto arm_branch_common
;
23153 case BFD_RELOC_ARM_PCREL_JUMP
:
23154 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23156 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23157 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23158 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23160 /* This would map to a bl<cond>, b<cond>,
23161 b<always> to a Thumb function. We
23162 need to force a relocation for this particular
23164 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23168 case BFD_RELOC_ARM_PLT32
:
23170 case BFD_RELOC_ARM_PCREL_BRANCH
:
23172 goto arm_branch_common
;
23174 case BFD_RELOC_ARM_PCREL_BLX
:
23177 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23179 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23180 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23181 && ARM_IS_FUNC (fixP
->fx_addsy
))
23183 /* Flip the blx to a bl and warn. */
23184 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23185 newval
= 0xeb000000;
23186 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23187 _("blx to '%s' an ARM ISA state function changed to bl"),
23189 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23195 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23196 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23200 /* We are going to store value (shifted right by two) in the
23201 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23202 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23203 also be be clear. */
23205 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23206 _("misaligned branch destination"));
23207 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23208 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23211 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23213 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23214 newval
|= (value
>> 2) & 0x00ffffff;
23215 /* Set the H bit on BLX instructions. */
23219 newval
|= 0x01000000;
23221 newval
&= ~0x01000000;
23223 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23227 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23228 /* CBZ can only branch forward. */
23230 /* Attempts to use CBZ to branch to the next instruction
23231 (which, strictly speaking, are prohibited) will be turned into
23234 FIXME: It may be better to remove the instruction completely and
23235 perform relaxation. */
23238 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23239 newval
= 0xbf00; /* NOP encoding T1 */
23240 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23247 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23249 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23250 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23251 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23256 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23257 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23258 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23260 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23262 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23263 newval
|= (value
& 0x1ff) >> 1;
23264 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23268 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23269 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23270 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23272 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23274 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23275 newval
|= (value
& 0xfff) >> 1;
23276 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23280 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23282 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23283 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23284 && ARM_IS_FUNC (fixP
->fx_addsy
)
23285 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23287 /* Force a relocation for a branch 20 bits wide. */
23290 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23292 _("conditional branch out of range"));
23294 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23297 addressT S
, J1
, J2
, lo
, hi
;
23299 S
= (value
& 0x00100000) >> 20;
23300 J2
= (value
& 0x00080000) >> 19;
23301 J1
= (value
& 0x00040000) >> 18;
23302 hi
= (value
& 0x0003f000) >> 12;
23303 lo
= (value
& 0x00000ffe) >> 1;
23305 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23306 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23307 newval
|= (S
<< 10) | hi
;
23308 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23309 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23310 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23314 case BFD_RELOC_THUMB_PCREL_BLX
:
23315 /* If there is a blx from a thumb state function to
23316 another thumb function flip this to a bl and warn
23320 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23321 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23322 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23324 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23325 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23326 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23328 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23329 newval
= newval
| 0x1000;
23330 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23331 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23336 goto thumb_bl_common
;
23338 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23339 /* A bl from Thumb state ISA to an internal ARM state function
23340 is converted to a blx. */
23342 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23343 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23344 && ARM_IS_FUNC (fixP
->fx_addsy
)
23345 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23347 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23348 newval
= newval
& ~0x1000;
23349 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23350 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23356 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23357 /* For a BLX instruction, make sure that the relocation is rounded up
23358 to a word boundary. This follows the semantics of the instruction
23359 which specifies that bit 1 of the target address will come from bit
23360 1 of the base address. */
23361 value
= (value
+ 3) & ~ 3;
23364 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23365 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23366 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23369 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23371 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23372 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23373 else if ((value
& ~0x1ffffff)
23374 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23375 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23376 _("Thumb2 branch out of range"));
23379 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23380 encode_thumb2_b_bl_offset (buf
, value
);
23384 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23385 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23386 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23388 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23389 encode_thumb2_b_bl_offset (buf
, value
);
23394 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23399 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23400 md_number_to_chars (buf
, value
, 2);
23404 case BFD_RELOC_ARM_TLS_CALL
:
23405 case BFD_RELOC_ARM_THM_TLS_CALL
:
23406 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23407 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23408 case BFD_RELOC_ARM_TLS_GOTDESC
:
23409 case BFD_RELOC_ARM_TLS_GD32
:
23410 case BFD_RELOC_ARM_TLS_LE32
:
23411 case BFD_RELOC_ARM_TLS_IE32
:
23412 case BFD_RELOC_ARM_TLS_LDM32
:
23413 case BFD_RELOC_ARM_TLS_LDO32
:
23414 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23417 case BFD_RELOC_ARM_GOT32
:
23418 case BFD_RELOC_ARM_GOTOFF
:
23421 case BFD_RELOC_ARM_GOT_PREL
:
23422 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23423 md_number_to_chars (buf
, value
, 4);
23426 case BFD_RELOC_ARM_TARGET2
:
23427 /* TARGET2 is not partial-inplace, so we need to write the
23428 addend here for REL targets, because it won't be written out
23429 during reloc processing later. */
23430 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23431 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23435 case BFD_RELOC_RVA
:
23437 case BFD_RELOC_ARM_TARGET1
:
23438 case BFD_RELOC_ARM_ROSEGREL32
:
23439 case BFD_RELOC_ARM_SBREL32
:
23440 case BFD_RELOC_32_PCREL
:
23442 case BFD_RELOC_32_SECREL
:
23444 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23446 /* For WinCE we only do this for pcrel fixups. */
23447 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23449 md_number_to_chars (buf
, value
, 4);
23453 case BFD_RELOC_ARM_PREL31
:
23454 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23456 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23457 if ((value
^ (value
>> 1)) & 0x40000000)
23459 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23460 _("rel31 relocation overflow"));
23462 newval
|= value
& 0x7fffffff;
23463 md_number_to_chars (buf
, newval
, 4);
23468 case BFD_RELOC_ARM_CP_OFF_IMM
:
23469 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23470 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23471 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23473 newval
= get_thumb32_insn (buf
);
23474 if ((newval
& 0x0f200f00) == 0x0d000900)
23476 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23477 has permitted values that are multiples of 2, in the range 0
23479 if (value
< -510 || value
> 510 || (value
& 1))
23480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23481 _("co-processor offset out of range"));
23483 else if (value
< -1023 || value
> 1023 || (value
& 3))
23484 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23485 _("co-processor offset out of range"));
23490 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23491 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23492 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23494 newval
= get_thumb32_insn (buf
);
23496 newval
&= 0xffffff00;
23499 newval
&= 0xff7fff00;
23500 if ((newval
& 0x0f200f00) == 0x0d000900)
23502 /* This is a fp16 vstr/vldr.
23504 It requires the immediate offset in the instruction is shifted
23505 left by 1 to be a half-word offset.
23507 Here, left shift by 1 first, and later right shift by 2
23508 should get the right offset. */
23511 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23513 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23514 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23515 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23517 put_thumb32_insn (buf
, newval
);
23520 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23521 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23522 if (value
< -255 || value
> 255)
23523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23524 _("co-processor offset out of range"));
23526 goto cp_off_common
;
23528 case BFD_RELOC_ARM_THUMB_OFFSET
:
23529 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23530 /* Exactly what ranges, and where the offset is inserted depends
23531 on the type of instruction, we can establish this from the
23533 switch (newval
>> 12)
23535 case 4: /* PC load. */
23536 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23537 forced to zero for these loads; md_pcrel_from has already
23538 compensated for this. */
23540 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23541 _("invalid offset, target not word aligned (0x%08lX)"),
23542 (((unsigned long) fixP
->fx_frag
->fr_address
23543 + (unsigned long) fixP
->fx_where
) & ~3)
23544 + (unsigned long) value
);
23546 if (value
& ~0x3fc)
23547 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23548 _("invalid offset, value too big (0x%08lX)"),
23551 newval
|= value
>> 2;
23554 case 9: /* SP load/store. */
23555 if (value
& ~0x3fc)
23556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23557 _("invalid offset, value too big (0x%08lX)"),
23559 newval
|= value
>> 2;
23562 case 6: /* Word load/store. */
23564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23565 _("invalid offset, value too big (0x%08lX)"),
23567 newval
|= value
<< 4; /* 6 - 2. */
23570 case 7: /* Byte load/store. */
23572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23573 _("invalid offset, value too big (0x%08lX)"),
23575 newval
|= value
<< 6;
23578 case 8: /* Halfword load/store. */
23580 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23581 _("invalid offset, value too big (0x%08lX)"),
23583 newval
|= value
<< 5; /* 6 - 1. */
23587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23588 "Unable to process relocation for thumb opcode: %lx",
23589 (unsigned long) newval
);
23592 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23595 case BFD_RELOC_ARM_THUMB_ADD
:
23596 /* This is a complicated relocation, since we use it for all of
23597 the following immediate relocations:
23601 9bit ADD/SUB SP word-aligned
23602 10bit ADD PC/SP word-aligned
23604 The type of instruction being processed is encoded in the
23611 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23613 int rd
= (newval
>> 4) & 0xf;
23614 int rs
= newval
& 0xf;
23615 int subtract
= !!(newval
& 0x8000);
23617 /* Check for HI regs, only very restricted cases allowed:
23618 Adjusting SP, and using PC or SP to get an address. */
23619 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23620 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23622 _("invalid Hi register with immediate"));
23624 /* If value is negative, choose the opposite instruction. */
23628 subtract
= !subtract
;
23630 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23631 _("immediate value out of range"));
23636 if (value
& ~0x1fc)
23637 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23638 _("invalid immediate for stack address calculation"));
23639 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23640 newval
|= value
>> 2;
23642 else if (rs
== REG_PC
|| rs
== REG_SP
)
23644 /* PR gas/18541. If the addition is for a defined symbol
23645 within range of an ADR instruction then accept it. */
23648 && fixP
->fx_addsy
!= NULL
)
23652 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23653 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23654 || S_IS_WEAK (fixP
->fx_addsy
))
23656 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23657 _("address calculation needs a strongly defined nearby symbol"));
23661 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23663 /* Round up to the next 4-byte boundary. */
23668 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23673 _("symbol too far away"));
23683 if (subtract
|| value
& ~0x3fc)
23684 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23685 _("invalid immediate for address calculation (value = 0x%08lX)"),
23686 (unsigned long) (subtract
? - value
: value
));
23687 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23689 newval
|= value
>> 2;
23694 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23695 _("immediate value out of range"));
23696 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23697 newval
|= (rd
<< 8) | value
;
23702 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23703 _("immediate value out of range"));
23704 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23705 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23708 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23711 case BFD_RELOC_ARM_THUMB_IMM
:
23712 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23713 if (value
< 0 || value
> 255)
23714 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23715 _("invalid immediate: %ld is out of range"),
23718 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23721 case BFD_RELOC_ARM_THUMB_SHIFT
:
23722 /* 5bit shift value (0..32). LSL cannot take 32. */
23723 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23724 temp
= newval
& 0xf800;
23725 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23726 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23727 _("invalid shift value: %ld"), (long) value
);
23728 /* Shifts of zero must be encoded as LSL. */
23730 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23731 /* Shifts of 32 are encoded as zero. */
23732 else if (value
== 32)
23734 newval
|= value
<< 6;
23735 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23738 case BFD_RELOC_VTABLE_INHERIT
:
23739 case BFD_RELOC_VTABLE_ENTRY
:
23743 case BFD_RELOC_ARM_MOVW
:
23744 case BFD_RELOC_ARM_MOVT
:
23745 case BFD_RELOC_ARM_THUMB_MOVW
:
23746 case BFD_RELOC_ARM_THUMB_MOVT
:
23747 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23749 /* REL format relocations are limited to a 16-bit addend. */
23750 if (!fixP
->fx_done
)
23752 if (value
< -0x8000 || value
> 0x7fff)
23753 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23754 _("offset out of range"));
23756 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23757 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23762 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23763 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23765 newval
= get_thumb32_insn (buf
);
23766 newval
&= 0xfbf08f00;
23767 newval
|= (value
& 0xf000) << 4;
23768 newval
|= (value
& 0x0800) << 15;
23769 newval
|= (value
& 0x0700) << 4;
23770 newval
|= (value
& 0x00ff);
23771 put_thumb32_insn (buf
, newval
);
23775 newval
= md_chars_to_number (buf
, 4);
23776 newval
&= 0xfff0f000;
23777 newval
|= value
& 0x0fff;
23778 newval
|= (value
& 0xf000) << 4;
23779 md_number_to_chars (buf
, newval
, 4);
23784 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23785 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23786 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23787 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23788 gas_assert (!fixP
->fx_done
);
23791 bfd_boolean is_mov
;
23792 bfd_vma encoded_addend
= value
;
23794 /* Check that addend can be encoded in instruction. */
23795 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23797 _("the offset 0x%08lX is not representable"),
23798 (unsigned long) encoded_addend
);
23800 /* Extract the instruction. */
23801 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23802 is_mov
= (insn
& 0xf800) == 0x2000;
23807 if (!seg
->use_rela_p
)
23808 insn
|= encoded_addend
;
23814 /* Extract the instruction. */
23815 /* Encoding is the following
23820 /* The following conditions must be true :
23825 rd
= (insn
>> 4) & 0xf;
23827 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23828 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23829 _("Unable to process relocation for thumb opcode: %lx"),
23830 (unsigned long) insn
);
23832 /* Encode as ADD immediate8 thumb 1 code. */
23833 insn
= 0x3000 | (rd
<< 8);
23835 /* Place the encoded addend into the first 8 bits of the
23837 if (!seg
->use_rela_p
)
23838 insn
|= encoded_addend
;
23841 /* Update the instruction. */
23842 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23846 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23847 case BFD_RELOC_ARM_ALU_PC_G0
:
23848 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23849 case BFD_RELOC_ARM_ALU_PC_G1
:
23850 case BFD_RELOC_ARM_ALU_PC_G2
:
23851 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23852 case BFD_RELOC_ARM_ALU_SB_G0
:
23853 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23854 case BFD_RELOC_ARM_ALU_SB_G1
:
23855 case BFD_RELOC_ARM_ALU_SB_G2
:
23856 gas_assert (!fixP
->fx_done
);
23857 if (!seg
->use_rela_p
)
23860 bfd_vma encoded_addend
;
23861 bfd_vma addend_abs
= abs (value
);
23863 /* Check that the absolute value of the addend can be
23864 expressed as an 8-bit constant plus a rotation. */
23865 encoded_addend
= encode_arm_immediate (addend_abs
);
23866 if (encoded_addend
== (unsigned int) FAIL
)
23867 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23868 _("the offset 0x%08lX is not representable"),
23869 (unsigned long) addend_abs
);
23871 /* Extract the instruction. */
23872 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23874 /* If the addend is positive, use an ADD instruction.
23875 Otherwise use a SUB. Take care not to destroy the S bit. */
23876 insn
&= 0xff1fffff;
23882 /* Place the encoded addend into the first 12 bits of the
23884 insn
&= 0xfffff000;
23885 insn
|= encoded_addend
;
23887 /* Update the instruction. */
23888 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23892 case BFD_RELOC_ARM_LDR_PC_G0
:
23893 case BFD_RELOC_ARM_LDR_PC_G1
:
23894 case BFD_RELOC_ARM_LDR_PC_G2
:
23895 case BFD_RELOC_ARM_LDR_SB_G0
:
23896 case BFD_RELOC_ARM_LDR_SB_G1
:
23897 case BFD_RELOC_ARM_LDR_SB_G2
:
23898 gas_assert (!fixP
->fx_done
);
23899 if (!seg
->use_rela_p
)
23902 bfd_vma addend_abs
= abs (value
);
23904 /* Check that the absolute value of the addend can be
23905 encoded in 12 bits. */
23906 if (addend_abs
>= 0x1000)
23907 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23908 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23909 (unsigned long) addend_abs
);
23911 /* Extract the instruction. */
23912 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23914 /* If the addend is negative, clear bit 23 of the instruction.
23915 Otherwise set it. */
23917 insn
&= ~(1 << 23);
23921 /* Place the absolute value of the addend into the first 12 bits
23922 of the instruction. */
23923 insn
&= 0xfffff000;
23924 insn
|= addend_abs
;
23926 /* Update the instruction. */
23927 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23931 case BFD_RELOC_ARM_LDRS_PC_G0
:
23932 case BFD_RELOC_ARM_LDRS_PC_G1
:
23933 case BFD_RELOC_ARM_LDRS_PC_G2
:
23934 case BFD_RELOC_ARM_LDRS_SB_G0
:
23935 case BFD_RELOC_ARM_LDRS_SB_G1
:
23936 case BFD_RELOC_ARM_LDRS_SB_G2
:
23937 gas_assert (!fixP
->fx_done
);
23938 if (!seg
->use_rela_p
)
23941 bfd_vma addend_abs
= abs (value
);
23943 /* Check that the absolute value of the addend can be
23944 encoded in 8 bits. */
23945 if (addend_abs
>= 0x100)
23946 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23947 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23948 (unsigned long) addend_abs
);
23950 /* Extract the instruction. */
23951 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23953 /* If the addend is negative, clear bit 23 of the instruction.
23954 Otherwise set it. */
23956 insn
&= ~(1 << 23);
23960 /* Place the first four bits of the absolute value of the addend
23961 into the first 4 bits of the instruction, and the remaining
23962 four into bits 8 .. 11. */
23963 insn
&= 0xfffff0f0;
23964 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23966 /* Update the instruction. */
23967 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23971 case BFD_RELOC_ARM_LDC_PC_G0
:
23972 case BFD_RELOC_ARM_LDC_PC_G1
:
23973 case BFD_RELOC_ARM_LDC_PC_G2
:
23974 case BFD_RELOC_ARM_LDC_SB_G0
:
23975 case BFD_RELOC_ARM_LDC_SB_G1
:
23976 case BFD_RELOC_ARM_LDC_SB_G2
:
23977 gas_assert (!fixP
->fx_done
);
23978 if (!seg
->use_rela_p
)
23981 bfd_vma addend_abs
= abs (value
);
23983 /* Check that the absolute value of the addend is a multiple of
23984 four and, when divided by four, fits in 8 bits. */
23985 if (addend_abs
& 0x3)
23986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23987 _("bad offset 0x%08lX (must be word-aligned)"),
23988 (unsigned long) addend_abs
);
23990 if ((addend_abs
>> 2) > 0xff)
23991 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23992 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23993 (unsigned long) addend_abs
);
23995 /* Extract the instruction. */
23996 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23998 /* If the addend is negative, clear bit 23 of the instruction.
23999 Otherwise set it. */
24001 insn
&= ~(1 << 23);
24005 /* Place the addend (divided by four) into the first eight
24006 bits of the instruction. */
24007 insn
&= 0xfffffff0;
24008 insn
|= addend_abs
>> 2;
24010 /* Update the instruction. */
24011 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24015 case BFD_RELOC_ARM_V4BX
:
24016 /* This will need to go in the object file. */
24020 case BFD_RELOC_UNUSED
:
24022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24023 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24027 /* Translate internal representation of relocation info to BFD target
24031 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24034 bfd_reloc_code_real_type code
;
24036 reloc
= XNEW (arelent
);
24038 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24039 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24040 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24042 if (fixp
->fx_pcrel
)
24044 if (section
->use_rela_p
)
24045 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24047 fixp
->fx_offset
= reloc
->address
;
24049 reloc
->addend
= fixp
->fx_offset
;
24051 switch (fixp
->fx_r_type
)
24054 if (fixp
->fx_pcrel
)
24056 code
= BFD_RELOC_8_PCREL
;
24061 if (fixp
->fx_pcrel
)
24063 code
= BFD_RELOC_16_PCREL
;
24068 if (fixp
->fx_pcrel
)
24070 code
= BFD_RELOC_32_PCREL
;
24074 case BFD_RELOC_ARM_MOVW
:
24075 if (fixp
->fx_pcrel
)
24077 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24081 case BFD_RELOC_ARM_MOVT
:
24082 if (fixp
->fx_pcrel
)
24084 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24088 case BFD_RELOC_ARM_THUMB_MOVW
:
24089 if (fixp
->fx_pcrel
)
24091 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24095 case BFD_RELOC_ARM_THUMB_MOVT
:
24096 if (fixp
->fx_pcrel
)
24098 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24102 case BFD_RELOC_NONE
:
24103 case BFD_RELOC_ARM_PCREL_BRANCH
:
24104 case BFD_RELOC_ARM_PCREL_BLX
:
24105 case BFD_RELOC_RVA
:
24106 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24107 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24108 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24109 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24110 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24111 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24112 case BFD_RELOC_VTABLE_ENTRY
:
24113 case BFD_RELOC_VTABLE_INHERIT
:
24115 case BFD_RELOC_32_SECREL
:
24117 code
= fixp
->fx_r_type
;
24120 case BFD_RELOC_THUMB_PCREL_BLX
:
24122 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24123 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24126 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24129 case BFD_RELOC_ARM_LITERAL
:
24130 case BFD_RELOC_ARM_HWLITERAL
:
24131 /* If this is called then the a literal has
24132 been referenced across a section boundary. */
24133 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24134 _("literal referenced across section boundary"));
24138 case BFD_RELOC_ARM_TLS_CALL
:
24139 case BFD_RELOC_ARM_THM_TLS_CALL
:
24140 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24141 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24142 case BFD_RELOC_ARM_GOT32
:
24143 case BFD_RELOC_ARM_GOTOFF
:
24144 case BFD_RELOC_ARM_GOT_PREL
:
24145 case BFD_RELOC_ARM_PLT32
:
24146 case BFD_RELOC_ARM_TARGET1
:
24147 case BFD_RELOC_ARM_ROSEGREL32
:
24148 case BFD_RELOC_ARM_SBREL32
:
24149 case BFD_RELOC_ARM_PREL31
:
24150 case BFD_RELOC_ARM_TARGET2
:
24151 case BFD_RELOC_ARM_TLS_LDO32
:
24152 case BFD_RELOC_ARM_PCREL_CALL
:
24153 case BFD_RELOC_ARM_PCREL_JUMP
:
24154 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24155 case BFD_RELOC_ARM_ALU_PC_G0
:
24156 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24157 case BFD_RELOC_ARM_ALU_PC_G1
:
24158 case BFD_RELOC_ARM_ALU_PC_G2
:
24159 case BFD_RELOC_ARM_LDR_PC_G0
:
24160 case BFD_RELOC_ARM_LDR_PC_G1
:
24161 case BFD_RELOC_ARM_LDR_PC_G2
:
24162 case BFD_RELOC_ARM_LDRS_PC_G0
:
24163 case BFD_RELOC_ARM_LDRS_PC_G1
:
24164 case BFD_RELOC_ARM_LDRS_PC_G2
:
24165 case BFD_RELOC_ARM_LDC_PC_G0
:
24166 case BFD_RELOC_ARM_LDC_PC_G1
:
24167 case BFD_RELOC_ARM_LDC_PC_G2
:
24168 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24169 case BFD_RELOC_ARM_ALU_SB_G0
:
24170 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24171 case BFD_RELOC_ARM_ALU_SB_G1
:
24172 case BFD_RELOC_ARM_ALU_SB_G2
:
24173 case BFD_RELOC_ARM_LDR_SB_G0
:
24174 case BFD_RELOC_ARM_LDR_SB_G1
:
24175 case BFD_RELOC_ARM_LDR_SB_G2
:
24176 case BFD_RELOC_ARM_LDRS_SB_G0
:
24177 case BFD_RELOC_ARM_LDRS_SB_G1
:
24178 case BFD_RELOC_ARM_LDRS_SB_G2
:
24179 case BFD_RELOC_ARM_LDC_SB_G0
:
24180 case BFD_RELOC_ARM_LDC_SB_G1
:
24181 case BFD_RELOC_ARM_LDC_SB_G2
:
24182 case BFD_RELOC_ARM_V4BX
:
24183 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24184 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24185 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24186 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24187 code
= fixp
->fx_r_type
;
24190 case BFD_RELOC_ARM_TLS_GOTDESC
:
24191 case BFD_RELOC_ARM_TLS_GD32
:
24192 case BFD_RELOC_ARM_TLS_LE32
:
24193 case BFD_RELOC_ARM_TLS_IE32
:
24194 case BFD_RELOC_ARM_TLS_LDM32
:
24195 /* BFD will include the symbol's address in the addend.
24196 But we don't want that, so subtract it out again here. */
24197 if (!S_IS_COMMON (fixp
->fx_addsy
))
24198 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24199 code
= fixp
->fx_r_type
;
24203 case BFD_RELOC_ARM_IMMEDIATE
:
24204 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24205 _("internal relocation (type: IMMEDIATE) not fixed up"));
24208 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24209 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24210 _("ADRL used for a symbol not defined in the same file"));
24213 case BFD_RELOC_ARM_OFFSET_IMM
:
24214 if (section
->use_rela_p
)
24216 code
= fixp
->fx_r_type
;
24220 if (fixp
->fx_addsy
!= NULL
24221 && !S_IS_DEFINED (fixp
->fx_addsy
)
24222 && S_IS_LOCAL (fixp
->fx_addsy
))
24224 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24225 _("undefined local label `%s'"),
24226 S_GET_NAME (fixp
->fx_addsy
));
24230 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24231 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24238 switch (fixp
->fx_r_type
)
24240 case BFD_RELOC_NONE
: type
= "NONE"; break;
24241 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24242 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24243 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24244 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24245 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24246 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24247 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24248 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24249 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24250 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24251 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24252 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24253 default: type
= _("<unknown>"); break;
24255 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24256 _("cannot represent %s relocation in this object file format"),
24263 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24265 && fixp
->fx_addsy
== GOT_symbol
)
24267 code
= BFD_RELOC_ARM_GOTPC
;
24268 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24272 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24274 if (reloc
->howto
== NULL
)
24276 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24277 _("cannot represent %s relocation in this object file format"),
24278 bfd_get_reloc_code_name (code
));
24282 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24283 vtable entry to be used in the relocation's section offset. */
24284 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24285 reloc
->address
= fixp
->fx_offset
;
24290 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24293 cons_fix_new_arm (fragS
* frag
,
24297 bfd_reloc_code_real_type reloc
)
24302 FIXME: @@ Should look at CPU word size. */
24306 reloc
= BFD_RELOC_8
;
24309 reloc
= BFD_RELOC_16
;
24313 reloc
= BFD_RELOC_32
;
24316 reloc
= BFD_RELOC_64
;
24321 if (exp
->X_op
== O_secrel
)
24323 exp
->X_op
= O_symbol
;
24324 reloc
= BFD_RELOC_32_SECREL
;
24328 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24331 #if defined (OBJ_COFF)
24333 arm_validate_fix (fixS
* fixP
)
24335 /* If the destination of the branch is a defined symbol which does not have
24336 the THUMB_FUNC attribute, then we must be calling a function which has
24337 the (interfacearm) attribute. We look for the Thumb entry point to that
24338 function and change the branch to refer to that function instead. */
24339 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24340 && fixP
->fx_addsy
!= NULL
24341 && S_IS_DEFINED (fixP
->fx_addsy
)
24342 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24344 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24351 arm_force_relocation (struct fix
* fixp
)
24353 #if defined (OBJ_COFF) && defined (TE_PE)
24354 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24358 /* In case we have a call or a branch to a function in ARM ISA mode from
24359 a thumb function or vice-versa force the relocation. These relocations
24360 are cleared off for some cores that might have blx and simple transformations
24364 switch (fixp
->fx_r_type
)
24366 case BFD_RELOC_ARM_PCREL_JUMP
:
24367 case BFD_RELOC_ARM_PCREL_CALL
:
24368 case BFD_RELOC_THUMB_PCREL_BLX
:
24369 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24373 case BFD_RELOC_ARM_PCREL_BLX
:
24374 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24375 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24376 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24377 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24386 /* Resolve these relocations even if the symbol is extern or weak.
24387 Technically this is probably wrong due to symbol preemption.
24388 In practice these relocations do not have enough range to be useful
24389 at dynamic link time, and some code (e.g. in the Linux kernel)
24390 expects these references to be resolved. */
24391 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24392 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24393 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24394 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24395 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24396 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24397 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24398 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24399 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24400 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24401 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24402 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24403 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24404 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24407 /* Always leave these relocations for the linker. */
24408 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24409 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24410 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24413 /* Always generate relocations against function symbols. */
24414 if (fixp
->fx_r_type
== BFD_RELOC_32
24416 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24419 return generic_force_reloc (fixp
);
24422 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24423 /* Relocations against function names must be left unadjusted,
24424 so that the linker can use this information to generate interworking
24425 stubs. The MIPS version of this function
24426 also prevents relocations that are mips-16 specific, but I do not
24427 know why it does this.
24430 There is one other problem that ought to be addressed here, but
24431 which currently is not: Taking the address of a label (rather
24432 than a function) and then later jumping to that address. Such
24433 addresses also ought to have their bottom bit set (assuming that
24434 they reside in Thumb code), but at the moment they will not. */
24437 arm_fix_adjustable (fixS
* fixP
)
24439 if (fixP
->fx_addsy
== NULL
)
24442 /* Preserve relocations against symbols with function type. */
24443 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24446 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24447 && fixP
->fx_subsy
== NULL
)
24450 /* We need the symbol name for the VTABLE entries. */
24451 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24452 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24455 /* Don't allow symbols to be discarded on GOT related relocs. */
24456 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24457 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24458 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24459 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24460 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24461 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24462 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24463 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24464 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24465 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24466 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24467 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24468 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24469 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24472 /* Similarly for group relocations. */
24473 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24474 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24475 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24478 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24479 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24480 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24481 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24482 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24483 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24484 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24485 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24486 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24489 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24490 offsets, so keep these symbols. */
24491 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24492 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24497 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24501 elf32_arm_target_format (void)
24504 return (target_big_endian
24505 ? "elf32-bigarm-symbian"
24506 : "elf32-littlearm-symbian");
24507 #elif defined (TE_VXWORKS)
24508 return (target_big_endian
24509 ? "elf32-bigarm-vxworks"
24510 : "elf32-littlearm-vxworks");
24511 #elif defined (TE_NACL)
24512 return (target_big_endian
24513 ? "elf32-bigarm-nacl"
24514 : "elf32-littlearm-nacl");
24516 if (target_big_endian
)
24517 return "elf32-bigarm";
24519 return "elf32-littlearm";
24524 armelf_frob_symbol (symbolS
* symp
,
24527 elf_frob_symbol (symp
, puntp
);
24531 /* MD interface: Finalization. */
24536 literal_pool
* pool
;
24538 /* Ensure that all the IT blocks are properly closed. */
24539 check_it_blocks_finished ();
24541 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24543 /* Put it at the end of the relevant section. */
24544 subseg_set (pool
->section
, pool
->sub_section
);
24546 arm_elf_change_section ();
24553 /* Remove any excess mapping symbols generated for alignment frags in
24554 SEC. We may have created a mapping symbol before a zero byte
24555 alignment; remove it if there's a mapping symbol after the
24558 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24559 void *dummy ATTRIBUTE_UNUSED
)
24561 segment_info_type
*seginfo
= seg_info (sec
);
24564 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24567 for (fragp
= seginfo
->frchainP
->frch_root
;
24569 fragp
= fragp
->fr_next
)
24571 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24572 fragS
*next
= fragp
->fr_next
;
24574 /* Variable-sized frags have been converted to fixed size by
24575 this point. But if this was variable-sized to start with,
24576 there will be a fixed-size frag after it. So don't handle
24578 if (sym
== NULL
|| next
== NULL
)
24581 if (S_GET_VALUE (sym
) < next
->fr_address
)
24582 /* Not at the end of this frag. */
24584 know (S_GET_VALUE (sym
) == next
->fr_address
);
24588 if (next
->tc_frag_data
.first_map
!= NULL
)
24590 /* Next frag starts with a mapping symbol. Discard this
24592 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24596 if (next
->fr_next
== NULL
)
24598 /* This mapping symbol is at the end of the section. Discard
24600 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24601 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24605 /* As long as we have empty frags without any mapping symbols,
24607 /* If the next frag is non-empty and does not start with a
24608 mapping symbol, then this mapping symbol is required. */
24609 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24612 next
= next
->fr_next
;
24614 while (next
!= NULL
);
24619 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24623 arm_adjust_symtab (void)
24628 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24630 if (ARM_IS_THUMB (sym
))
24632 if (THUMB_IS_FUNC (sym
))
24634 /* Mark the symbol as a Thumb function. */
24635 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24636 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24637 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24639 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24640 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24642 as_bad (_("%s: unexpected function type: %d"),
24643 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24645 else switch (S_GET_STORAGE_CLASS (sym
))
24648 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24651 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24654 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24662 if (ARM_IS_INTERWORK (sym
))
24663 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24670 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24672 if (ARM_IS_THUMB (sym
))
24674 elf_symbol_type
* elf_sym
;
24676 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24677 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24679 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24680 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24682 /* If it's a .thumb_func, declare it as so,
24683 otherwise tag label as .code 16. */
24684 if (THUMB_IS_FUNC (sym
))
24685 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
24686 ST_BRANCH_TO_THUMB
);
24687 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24688 elf_sym
->internal_elf_sym
.st_info
=
24689 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24694 /* Remove any overlapping mapping symbols generated by alignment frags. */
24695 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24696 /* Now do generic ELF adjustments. */
24697 elf_adjust_symtab ();
24701 /* MD interface: Initialization. */
24704 set_constant_flonums (void)
24708 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24709 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24713 /* Auto-select Thumb mode if it's the only available instruction set for the
24714 given architecture. */
24717 autoselect_thumb_from_cpu_variant (void)
24719 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24720 opcode_select (16);
24729 if ( (arm_ops_hsh
= hash_new ()) == NULL
24730 || (arm_cond_hsh
= hash_new ()) == NULL
24731 || (arm_shift_hsh
= hash_new ()) == NULL
24732 || (arm_psr_hsh
= hash_new ()) == NULL
24733 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24734 || (arm_reg_hsh
= hash_new ()) == NULL
24735 || (arm_reloc_hsh
= hash_new ()) == NULL
24736 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24737 as_fatal (_("virtual memory exhausted"));
24739 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24740 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24741 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24742 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24743 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24744 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24745 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24746 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24747 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24748 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24749 (void *) (v7m_psrs
+ i
));
24750 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24751 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24753 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24755 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24756 (void *) (barrier_opt_names
+ i
));
24758 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24760 struct reloc_entry
* entry
= reloc_names
+ i
;
24762 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24763 /* This makes encode_branch() use the EABI versions of this relocation. */
24764 entry
->reloc
= BFD_RELOC_UNUSED
;
24766 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24770 set_constant_flonums ();
24772 /* Set the cpu variant based on the command-line options. We prefer
24773 -mcpu= over -march= if both are set (as for GCC); and we prefer
24774 -mfpu= over any other way of setting the floating point unit.
24775 Use of legacy options with new options are faulted. */
24778 if (mcpu_cpu_opt
|| march_cpu_opt
)
24779 as_bad (_("use of old and new-style options to set CPU type"));
24781 mcpu_cpu_opt
= legacy_cpu
;
24783 else if (!mcpu_cpu_opt
)
24784 mcpu_cpu_opt
= march_cpu_opt
;
24789 as_bad (_("use of old and new-style options to set FPU type"));
24791 mfpu_opt
= legacy_fpu
;
24793 else if (!mfpu_opt
)
24795 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24796 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24797 /* Some environments specify a default FPU. If they don't, infer it
24798 from the processor. */
24800 mfpu_opt
= mcpu_fpu_opt
;
24802 mfpu_opt
= march_fpu_opt
;
24804 mfpu_opt
= &fpu_default
;
24810 if (mcpu_cpu_opt
!= NULL
)
24811 mfpu_opt
= &fpu_default
;
24812 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24813 mfpu_opt
= &fpu_arch_vfp_v2
;
24815 mfpu_opt
= &fpu_arch_fpa
;
24821 mcpu_cpu_opt
= &cpu_default
;
24822 selected_cpu
= cpu_default
;
24824 else if (no_cpu_selected ())
24825 selected_cpu
= cpu_default
;
24828 selected_cpu
= *mcpu_cpu_opt
;
24830 mcpu_cpu_opt
= &arm_arch_any
;
24833 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24835 autoselect_thumb_from_cpu_variant ();
24837 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24839 #if defined OBJ_COFF || defined OBJ_ELF
24841 unsigned int flags
= 0;
24843 #if defined OBJ_ELF
24844 flags
= meabi_flags
;
24846 switch (meabi_flags
)
24848 case EF_ARM_EABI_UNKNOWN
:
24850 /* Set the flags in the private structure. */
24851 if (uses_apcs_26
) flags
|= F_APCS26
;
24852 if (support_interwork
) flags
|= F_INTERWORK
;
24853 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24854 if (pic_code
) flags
|= F_PIC
;
24855 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24856 flags
|= F_SOFT_FLOAT
;
24858 switch (mfloat_abi_opt
)
24860 case ARM_FLOAT_ABI_SOFT
:
24861 case ARM_FLOAT_ABI_SOFTFP
:
24862 flags
|= F_SOFT_FLOAT
;
24865 case ARM_FLOAT_ABI_HARD
:
24866 if (flags
& F_SOFT_FLOAT
)
24867 as_bad (_("hard-float conflicts with specified fpu"));
24871 /* Using pure-endian doubles (even if soft-float). */
24872 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24873 flags
|= F_VFP_FLOAT
;
24875 #if defined OBJ_ELF
24876 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24877 flags
|= EF_ARM_MAVERICK_FLOAT
;
24880 case EF_ARM_EABI_VER4
:
24881 case EF_ARM_EABI_VER5
:
24882 /* No additional flags to set. */
24889 bfd_set_private_flags (stdoutput
, flags
);
24891 /* We have run out flags in the COFF header to encode the
24892 status of ATPCS support, so instead we create a dummy,
24893 empty, debug section called .arm.atpcs. */
24898 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24902 bfd_set_section_flags
24903 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24904 bfd_set_section_size (stdoutput
, sec
, 0);
24905 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24911 /* Record the CPU type as well. */
24912 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24913 mach
= bfd_mach_arm_iWMMXt2
;
24914 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24915 mach
= bfd_mach_arm_iWMMXt
;
24916 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24917 mach
= bfd_mach_arm_XScale
;
24918 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24919 mach
= bfd_mach_arm_ep9312
;
24920 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24921 mach
= bfd_mach_arm_5TE
;
24922 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24925 mach
= bfd_mach_arm_5T
;
24927 mach
= bfd_mach_arm_5
;
24929 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24931 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24932 mach
= bfd_mach_arm_4T
;
24934 mach
= bfd_mach_arm_4
;
24936 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24937 mach
= bfd_mach_arm_3M
;
24938 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24939 mach
= bfd_mach_arm_3
;
24940 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24941 mach
= bfd_mach_arm_2a
;
24942 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24943 mach
= bfd_mach_arm_2
;
24945 mach
= bfd_mach_arm_unknown
;
24947 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24950 /* Command line processing. */
24953 Invocation line includes a switch not recognized by the base assembler.
24954 See if it's a processor-specific option.
24956 This routine is somewhat complicated by the need for backwards
24957 compatibility (since older releases of gcc can't be changed).
24958 The new options try to make the interface as compatible as
24961 New options (supported) are:
24963 -mcpu=<cpu name> Assemble for selected processor
24964 -march=<architecture name> Assemble for selected architecture
24965 -mfpu=<fpu architecture> Assemble for selected FPU.
24966 -EB/-mbig-endian Big-endian
24967 -EL/-mlittle-endian Little-endian
24968 -k Generate PIC code
24969 -mthumb Start in Thumb mode
24970 -mthumb-interwork Code supports ARM/Thumb interworking
24972 -m[no-]warn-deprecated Warn about deprecated features
24973 -m[no-]warn-syms Warn when symbols match instructions
24975 For now we will also provide support for:
24977 -mapcs-32 32-bit Program counter
24978 -mapcs-26 26-bit Program counter
24979 -macps-float Floats passed in FP registers
24980 -mapcs-reentrant Reentrant code
24982 (sometime these will probably be replaced with -mapcs=<list of options>
24983 and -matpcs=<list of options>)
24985 The remaining options are only supported for back-wards compatibility.
24986 Cpu variants, the arm part is optional:
24987 -m[arm]1 Currently not supported.
24988 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24989 -m[arm]3 Arm 3 processor
24990 -m[arm]6[xx], Arm 6 processors
24991 -m[arm]7[xx][t][[d]m] Arm 7 processors
24992 -m[arm]8[10] Arm 8 processors
24993 -m[arm]9[20][tdmi] Arm 9 processors
24994 -mstrongarm[110[0]] StrongARM processors
24995 -mxscale XScale processors
24996 -m[arm]v[2345[t[e]]] Arm architectures
24997 -mall All (except the ARM1)
24999 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25000 -mfpe-old (No float load/store multiples)
25001 -mvfpxd VFP Single precision
25003 -mno-fpu Disable all floating point instructions
25005 The following CPU names are recognized:
25006 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25007 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25008 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25009 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25010 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25011 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25012 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25016 const char * md_shortopts
= "m:k";
25018 #ifdef ARM_BI_ENDIAN
25019 #define OPTION_EB (OPTION_MD_BASE + 0)
25020 #define OPTION_EL (OPTION_MD_BASE + 1)
25022 #if TARGET_BYTES_BIG_ENDIAN
25023 #define OPTION_EB (OPTION_MD_BASE + 0)
25025 #define OPTION_EL (OPTION_MD_BASE + 1)
25028 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25030 struct option md_longopts
[] =
25033 {"EB", no_argument
, NULL
, OPTION_EB
},
25036 {"EL", no_argument
, NULL
, OPTION_EL
},
25038 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25039 {NULL
, no_argument
, NULL
, 0}
25043 size_t md_longopts_size
= sizeof (md_longopts
);
25045 struct arm_option_table
25047 const char *option
; /* Option name to match. */
25048 const char *help
; /* Help information. */
25049 int *var
; /* Variable to change. */
25050 int value
; /* What to change it to. */
25051 const char *deprecated
; /* If non-null, print this message. */
25054 struct arm_option_table arm_opts
[] =
25056 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25057 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25058 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25059 &support_interwork
, 1, NULL
},
25060 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25061 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25062 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25064 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25065 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25066 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25067 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25070 /* These are recognized by the assembler, but have no affect on code. */
25071 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25072 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25074 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25075 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25076 &warn_on_deprecated
, 0, NULL
},
25077 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25078 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25079 {NULL
, NULL
, NULL
, 0, NULL
}
25082 struct arm_legacy_option_table
25084 const char *option
; /* Option name to match. */
25085 const arm_feature_set
**var
; /* Variable to change. */
25086 const arm_feature_set value
; /* What to change it to. */
25087 const char *deprecated
; /* If non-null, print this message. */
25090 const struct arm_legacy_option_table arm_legacy_opts
[] =
25092 /* DON'T add any new processors to this list -- we want the whole list
25093 to go away... Add them to the processors table instead. */
25094 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25095 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25096 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25097 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25098 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25099 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25100 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25101 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25102 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25103 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25104 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25105 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25106 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25107 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25108 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25109 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25110 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25111 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25112 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25113 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25114 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25115 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25116 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25117 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25118 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25119 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25120 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25121 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25122 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25123 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25124 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25125 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25126 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25127 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25128 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25129 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25130 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25131 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25132 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25133 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25134 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25135 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25136 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25137 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25138 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25139 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25140 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25141 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25142 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25143 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25144 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25145 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25146 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25147 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25148 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25149 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25150 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25151 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25152 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25153 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25154 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25155 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25156 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25157 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25158 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25159 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25160 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25161 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25162 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25163 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25164 N_("use -mcpu=strongarm110")},
25165 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25166 N_("use -mcpu=strongarm1100")},
25167 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25168 N_("use -mcpu=strongarm1110")},
25169 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25170 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25171 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25173 /* Architecture variants -- don't add any more to this list either. */
25174 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25175 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25176 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25177 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25178 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25179 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25180 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25181 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25182 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25183 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25184 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25185 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25186 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25187 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25188 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25189 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25190 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25191 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25193 /* Floating point variants -- don't add any more to this list either. */
25194 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25195 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25196 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25197 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25198 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25200 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25203 struct arm_cpu_option_table
25207 const arm_feature_set value
;
25208 /* For some CPUs we assume an FPU unless the user explicitly sets
25210 const arm_feature_set default_fpu
;
25211 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25213 const char *canonical_name
;
25216 /* This list should, at a minimum, contain all the cpu names
25217 recognized by GCC. */
25218 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25219 static const struct arm_cpu_option_table arm_cpus
[] =
25221 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25222 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25223 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25224 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25225 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25226 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25227 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25228 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25229 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25230 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25231 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25232 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25233 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25234 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25235 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25236 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25237 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25238 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25239 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25240 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25241 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25242 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25243 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25244 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25245 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25246 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25247 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25248 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25249 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25250 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25251 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25252 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25253 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25254 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25255 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25256 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25257 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25258 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25259 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25260 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25261 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25262 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25263 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25264 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25265 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25266 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25267 /* For V5 or later processors we default to using VFP; but the user
25268 should really set the FPU type explicitly. */
25269 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25270 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25271 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25272 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25273 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25274 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25275 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25276 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25277 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25278 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25279 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25280 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25281 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25282 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25283 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25284 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25285 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25286 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25287 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25288 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25290 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25291 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25292 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25293 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25294 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25295 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25296 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25297 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25298 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25300 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25301 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25302 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25303 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25304 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25305 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25306 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25307 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25308 FPU_NONE
, "Cortex-A5"),
25309 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25311 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25312 ARM_FEATURE_COPROC (FPU_VFP_V3
25313 | FPU_NEON_EXT_V1
),
25315 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25316 ARM_FEATURE_COPROC (FPU_VFP_V3
25317 | FPU_NEON_EXT_V1
),
25319 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25321 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25323 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25325 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25327 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25329 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25331 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25333 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25335 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25336 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25338 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25339 FPU_NONE
, "Cortex-R5"),
25340 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25341 FPU_ARCH_VFP_V3D16
,
25343 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25344 FPU_ARCH_VFP_V3D16
,
25346 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25347 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25348 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25349 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25350 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25351 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25352 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25355 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25359 /* ??? XSCALE is really an architecture. */
25360 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25361 /* ??? iwmmxt is not a processor. */
25362 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25363 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25364 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25366 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25367 FPU_ARCH_MAVERICK
, "ARM920T"),
25368 /* Marvell processors. */
25369 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25371 ARM_EXT2_V6T2_V8M
),
25372 FPU_ARCH_VFP_V3D16
, NULL
),
25373 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25375 ARM_EXT2_V6T2_V8M
),
25376 FPU_ARCH_NEON_VFP_V4
, NULL
),
25377 /* APM X-Gene family. */
25378 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25380 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25383 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25387 struct arm_arch_option_table
25391 const arm_feature_set value
;
25392 const arm_feature_set default_fpu
;
25395 /* This list should, at a minimum, contain all the architecture names
25396 recognized by GCC. */
25397 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25398 static const struct arm_arch_option_table arm_archs
[] =
25400 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25401 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25402 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25403 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25404 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25405 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25406 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25407 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25408 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25409 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25410 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25411 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25412 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25413 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25414 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25415 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25416 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25417 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25418 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25419 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25420 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25421 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25422 kept to preserve existing behaviour. */
25423 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25424 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25425 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25426 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25427 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25428 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25429 kept to preserve existing behaviour. */
25430 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25431 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25432 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25433 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25434 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25435 /* The official spelling of the ARMv7 profile variants is the dashed form.
25436 Accept the non-dashed form for compatibility with old toolchains. */
25437 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25438 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25439 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25440 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25441 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25442 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25443 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25444 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25445 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25446 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25447 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25448 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25449 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25450 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25451 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25452 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25453 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25455 #undef ARM_ARCH_OPT
25457 /* ISA extensions in the co-processor and main instruction set space. */
25458 struct arm_option_extension_value_table
25462 const arm_feature_set merge_value
;
25463 const arm_feature_set clear_value
;
25464 /* List of architectures for which an extension is available. ARM_ARCH_NONE
25465 indicates that an extension is available for all architectures while
25466 ARM_ANY marks an empty entry. */
25467 const arm_feature_set allowed_archs
[2];
25470 /* The following table must be in alphabetical order with a NULL last entry.
25472 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
25473 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
25474 static const struct arm_option_extension_value_table arm_extensions
[] =
25476 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25477 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25478 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25479 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25480 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25481 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25482 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
25483 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
25484 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25485 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25486 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25487 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25489 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25490 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25491 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25492 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25493 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25494 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
25495 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25496 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
25497 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25498 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
25499 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25500 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25501 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
25502 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
25503 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25504 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25505 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25506 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25507 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25508 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25509 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25510 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25511 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25512 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25513 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25514 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
25515 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25516 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25517 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25518 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25519 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25521 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25522 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25523 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25524 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
25525 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
25529 /* ISA floating-point and Advanced SIMD extensions. */
25530 struct arm_option_fpu_value_table
25533 const arm_feature_set value
;
25536 /* This list should, at a minimum, contain all the fpu names
25537 recognized by GCC. */
25538 static const struct arm_option_fpu_value_table arm_fpus
[] =
25540 {"softfpa", FPU_NONE
},
25541 {"fpe", FPU_ARCH_FPE
},
25542 {"fpe2", FPU_ARCH_FPE
},
25543 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25544 {"fpa", FPU_ARCH_FPA
},
25545 {"fpa10", FPU_ARCH_FPA
},
25546 {"fpa11", FPU_ARCH_FPA
},
25547 {"arm7500fe", FPU_ARCH_FPA
},
25548 {"softvfp", FPU_ARCH_VFP
},
25549 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25550 {"vfp", FPU_ARCH_VFP_V2
},
25551 {"vfp9", FPU_ARCH_VFP_V2
},
25552 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25553 {"vfp10", FPU_ARCH_VFP_V2
},
25554 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25555 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25556 {"vfpv2", FPU_ARCH_VFP_V2
},
25557 {"vfpv3", FPU_ARCH_VFP_V3
},
25558 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25559 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25560 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25561 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25562 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25563 {"arm1020t", FPU_ARCH_VFP_V1
},
25564 {"arm1020e", FPU_ARCH_VFP_V2
},
25565 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25566 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25567 {"maverick", FPU_ARCH_MAVERICK
},
25568 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25569 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25570 {"vfpv4", FPU_ARCH_VFP_V4
},
25571 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25572 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25573 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25574 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25575 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25576 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25577 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25578 {"crypto-neon-fp-armv8",
25579 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25580 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25581 {"crypto-neon-fp-armv8.1",
25582 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25583 {NULL
, ARM_ARCH_NONE
}
25586 struct arm_option_value_table
25592 static const struct arm_option_value_table arm_float_abis
[] =
25594 {"hard", ARM_FLOAT_ABI_HARD
},
25595 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25596 {"soft", ARM_FLOAT_ABI_SOFT
},
25601 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25602 static const struct arm_option_value_table arm_eabis
[] =
25604 {"gnu", EF_ARM_EABI_UNKNOWN
},
25605 {"4", EF_ARM_EABI_VER4
},
25606 {"5", EF_ARM_EABI_VER5
},
25611 struct arm_long_option_table
25613 const char * option
; /* Substring to match. */
25614 const char * help
; /* Help information. */
25615 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25616 const char * deprecated
; /* If non-null, print this message. */
25620 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25622 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25624 /* We insist on extensions being specified in alphabetical order, and with
25625 extensions being added before being removed. We achieve this by having
25626 the global ARM_EXTENSIONS table in alphabetical order, and using the
25627 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25628 or removing it (0) and only allowing it to change in the order
25630 const struct arm_option_extension_value_table
* opt
= NULL
;
25631 const arm_feature_set arm_any
= ARM_ANY
;
25632 int adding_value
= -1;
25634 /* Copy the feature set, so that we can modify it. */
25635 *ext_set
= **opt_p
;
25638 while (str
!= NULL
&& *str
!= 0)
25645 as_bad (_("invalid architectural extension"));
25650 ext
= strchr (str
, '+');
25655 len
= strlen (str
);
25657 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25659 if (adding_value
!= 0)
25662 opt
= arm_extensions
;
25670 if (adding_value
== -1)
25673 opt
= arm_extensions
;
25675 else if (adding_value
!= 1)
25677 as_bad (_("must specify extensions to add before specifying "
25678 "those to remove"));
25685 as_bad (_("missing architectural extension"));
25689 gas_assert (adding_value
!= -1);
25690 gas_assert (opt
!= NULL
);
25692 /* Scan over the options table trying to find an exact match. */
25693 for (; opt
->name
!= NULL
; opt
++)
25694 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25696 int i
, nb_allowed_archs
=
25697 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
25698 /* Check we can apply the extension to this architecture. */
25699 for (i
= 0; i
< nb_allowed_archs
; i
++)
25702 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
25704 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *ext_set
))
25707 if (i
== nb_allowed_archs
)
25709 as_bad (_("extension does not apply to the base architecture"));
25713 /* Add or remove the extension. */
25715 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25717 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25722 if (opt
->name
== NULL
)
25724 /* Did we fail to find an extension because it wasn't specified in
25725 alphabetical order, or because it does not exist? */
25727 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25728 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25731 if (opt
->name
== NULL
)
25732 as_bad (_("unknown architectural extension `%s'"), str
);
25734 as_bad (_("architectural extensions must be specified in "
25735 "alphabetical order"));
25741 /* We should skip the extension we've just matched the next time
25753 arm_parse_cpu (const char *str
)
25755 const struct arm_cpu_option_table
*opt
;
25756 const char *ext
= strchr (str
, '+');
25762 len
= strlen (str
);
25766 as_bad (_("missing cpu name `%s'"), str
);
25770 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25771 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25773 mcpu_cpu_opt
= &opt
->value
;
25774 mcpu_fpu_opt
= &opt
->default_fpu
;
25775 if (opt
->canonical_name
)
25777 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25778 strcpy (selected_cpu_name
, opt
->canonical_name
);
25784 if (len
>= sizeof selected_cpu_name
)
25785 len
= (sizeof selected_cpu_name
) - 1;
25787 for (i
= 0; i
< len
; i
++)
25788 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25789 selected_cpu_name
[i
] = 0;
25793 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25798 as_bad (_("unknown cpu `%s'"), str
);
25803 arm_parse_arch (const char *str
)
25805 const struct arm_arch_option_table
*opt
;
25806 const char *ext
= strchr (str
, '+');
25812 len
= strlen (str
);
25816 as_bad (_("missing architecture name `%s'"), str
);
25820 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25821 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25823 march_cpu_opt
= &opt
->value
;
25824 march_fpu_opt
= &opt
->default_fpu
;
25825 strcpy (selected_cpu_name
, opt
->name
);
25828 return arm_parse_extension (ext
, &march_cpu_opt
);
25833 as_bad (_("unknown architecture `%s'\n"), str
);
25838 arm_parse_fpu (const char * str
)
25840 const struct arm_option_fpu_value_table
* opt
;
25842 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25843 if (streq (opt
->name
, str
))
25845 mfpu_opt
= &opt
->value
;
25849 as_bad (_("unknown floating point format `%s'\n"), str
);
25854 arm_parse_float_abi (const char * str
)
25856 const struct arm_option_value_table
* opt
;
25858 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25859 if (streq (opt
->name
, str
))
25861 mfloat_abi_opt
= opt
->value
;
25865 as_bad (_("unknown floating point abi `%s'\n"), str
);
25871 arm_parse_eabi (const char * str
)
25873 const struct arm_option_value_table
*opt
;
25875 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25876 if (streq (opt
->name
, str
))
25878 meabi_flags
= opt
->value
;
25881 as_bad (_("unknown EABI `%s'\n"), str
);
25887 arm_parse_it_mode (const char * str
)
25889 bfd_boolean ret
= TRUE
;
25891 if (streq ("arm", str
))
25892 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25893 else if (streq ("thumb", str
))
25894 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25895 else if (streq ("always", str
))
25896 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25897 else if (streq ("never", str
))
25898 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25901 as_bad (_("unknown implicit IT mode `%s', should be "\
25902 "arm, thumb, always, or never."), str
);
25910 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
25912 codecomposer_syntax
= TRUE
;
25913 arm_comment_chars
[0] = ';';
25914 arm_line_separator_chars
[0] = 0;
25918 struct arm_long_option_table arm_long_opts
[] =
25920 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25921 arm_parse_cpu
, NULL
},
25922 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25923 arm_parse_arch
, NULL
},
25924 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25925 arm_parse_fpu
, NULL
},
25926 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25927 arm_parse_float_abi
, NULL
},
25929 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25930 arm_parse_eabi
, NULL
},
25932 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25933 arm_parse_it_mode
, NULL
},
25934 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25935 arm_ccs_mode
, NULL
},
25936 {NULL
, NULL
, 0, NULL
}
25940 md_parse_option (int c
, const char * arg
)
25942 struct arm_option_table
*opt
;
25943 const struct arm_legacy_option_table
*fopt
;
25944 struct arm_long_option_table
*lopt
;
25950 target_big_endian
= 1;
25956 target_big_endian
= 0;
25960 case OPTION_FIX_V4BX
:
25965 /* Listing option. Just ignore these, we don't support additional
25970 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25972 if (c
== opt
->option
[0]
25973 && ((arg
== NULL
&& opt
->option
[1] == 0)
25974 || streq (arg
, opt
->option
+ 1)))
25976 /* If the option is deprecated, tell the user. */
25977 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25978 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25979 arg
? arg
: "", _(opt
->deprecated
));
25981 if (opt
->var
!= NULL
)
25982 *opt
->var
= opt
->value
;
25988 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25990 if (c
== fopt
->option
[0]
25991 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25992 || streq (arg
, fopt
->option
+ 1)))
25994 /* If the option is deprecated, tell the user. */
25995 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25996 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25997 arg
? arg
: "", _(fopt
->deprecated
));
25999 if (fopt
->var
!= NULL
)
26000 *fopt
->var
= &fopt
->value
;
26006 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26008 /* These options are expected to have an argument. */
26009 if (c
== lopt
->option
[0]
26011 && strncmp (arg
, lopt
->option
+ 1,
26012 strlen (lopt
->option
+ 1)) == 0)
26014 /* If the option is deprecated, tell the user. */
26015 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26016 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26017 _(lopt
->deprecated
));
26019 /* Call the sup-option parser. */
26020 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26031 md_show_usage (FILE * fp
)
26033 struct arm_option_table
*opt
;
26034 struct arm_long_option_table
*lopt
;
26036 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26038 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26039 if (opt
->help
!= NULL
)
26040 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26042 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26043 if (lopt
->help
!= NULL
)
26044 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26048 -EB assemble code for a big-endian cpu\n"));
26053 -EL assemble code for a little-endian cpu\n"));
26057 --fix-v4bx Allow BX in ARMv4 code\n"));
26065 arm_feature_set flags
;
26066 } cpu_arch_ver_table
;
26068 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26069 must be sorted least features first but some reordering is needed, eg. for
26070 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26071 static const cpu_arch_ver_table cpu_arch_ver
[] =
26077 {4, ARM_ARCH_V5TE
},
26078 {5, ARM_ARCH_V5TEJ
},
26082 {11, ARM_ARCH_V6M
},
26083 {12, ARM_ARCH_V6SM
},
26084 {8, ARM_ARCH_V6T2
},
26085 {10, ARM_ARCH_V7VE
},
26086 {10, ARM_ARCH_V7R
},
26087 {10, ARM_ARCH_V7M
},
26088 {14, ARM_ARCH_V8A
},
26089 {16, ARM_ARCH_V8M_BASE
},
26090 {17, ARM_ARCH_V8M_MAIN
},
26094 /* Set an attribute if it has not already been set by the user. */
26096 aeabi_set_attribute_int (int tag
, int value
)
26099 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26100 || !attributes_set_explicitly
[tag
])
26101 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26105 aeabi_set_attribute_string (int tag
, const char *value
)
26108 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26109 || !attributes_set_explicitly
[tag
])
26110 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26113 /* Set the public EABI object attributes. */
26115 aeabi_set_public_attributes (void)
26120 int fp16_optional
= 0;
26121 arm_feature_set arm_arch
= ARM_ARCH_NONE
;
26122 arm_feature_set flags
;
26123 arm_feature_set tmp
;
26124 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26125 const cpu_arch_ver_table
*p
;
26127 /* Choose the architecture based on the capabilities of the requested cpu
26128 (if any) and/or the instructions actually used. */
26129 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26130 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26131 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26133 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26134 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26136 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26137 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26139 selected_cpu
= flags
;
26141 /* Allow the user to override the reported architecture. */
26144 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26145 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26148 /* We need to make sure that the attributes do not identify us as v6S-M
26149 when the only v6S-M feature in use is the Operating System Extensions. */
26150 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26151 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26152 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26156 for (p
= cpu_arch_ver
; p
->val
; p
++)
26158 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26161 arm_arch
= p
->flags
;
26162 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26166 /* The table lookup above finds the last architecture to contribute
26167 a new feature. Unfortunately, Tag13 is a subset of the union of
26168 v6T2 and v7-M, so it is never seen as contributing a new feature.
26169 We can not search for the last entry which is entirely used,
26170 because if no CPU is specified we build up only those flags
26171 actually used. Perhaps we should separate out the specified
26172 and implicit cases. Avoid taking this path for -march=all by
26173 checking for contradictory v7-A / v7-M features. */
26174 if (arch
== TAG_CPU_ARCH_V7
26175 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26176 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26177 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26179 arch
= TAG_CPU_ARCH_V7E_M
;
26180 arm_arch
= (arm_feature_set
) ARM_ARCH_V7EM
;
26183 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26184 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26186 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26187 arm_arch
= (arm_feature_set
) ARM_ARCH_V8M_MAIN
;
26190 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26191 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26192 ARMv8-M, -march=all must be detected as ARMv8-A. */
26193 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26194 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26196 arch
= TAG_CPU_ARCH_V8
;
26197 arm_arch
= (arm_feature_set
) ARM_ARCH_V8A
;
26200 /* Tag_CPU_name. */
26201 if (selected_cpu_name
[0])
26205 q
= selected_cpu_name
;
26206 if (strncmp (q
, "armv", 4) == 0)
26211 for (i
= 0; q
[i
]; i
++)
26212 q
[i
] = TOUPPER (q
[i
]);
26214 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26217 /* Tag_CPU_arch. */
26218 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26220 /* Tag_CPU_arch_profile. */
26221 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26222 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26223 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26224 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
)))
26226 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26228 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26233 if (profile
!= '\0')
26234 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26236 /* Tag_DSP_extension. */
26237 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_dsp
))
26239 arm_feature_set ext
;
26241 /* DSP instructions not in architecture. */
26242 ARM_CLEAR_FEATURE (ext
, flags
, arm_arch
);
26243 if (ARM_CPU_HAS_FEATURE (ext
, arm_ext_dsp
))
26244 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
26247 /* Tag_ARM_ISA_use. */
26248 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26250 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26252 /* Tag_THUMB_ISA_use. */
26253 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26258 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26259 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
26261 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26265 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26268 /* Tag_VFP_arch. */
26269 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26270 aeabi_set_attribute_int (Tag_VFP_arch
,
26271 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26273 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26274 aeabi_set_attribute_int (Tag_VFP_arch
,
26275 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26277 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26280 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26282 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26284 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26287 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26288 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26289 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26290 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26291 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26293 /* Tag_ABI_HardFP_use. */
26294 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26295 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26296 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26298 /* Tag_WMMX_arch. */
26299 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26300 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26301 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26302 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26304 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26305 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26306 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26307 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26308 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26309 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26311 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26313 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26317 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26322 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26323 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26324 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26328 We set Tag_DIV_use to two when integer divide instructions have been used
26329 in ARM state, or when Thumb integer divide instructions have been used,
26330 but we have no architecture profile set, nor have we any ARM instructions.
26332 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26333 by the base architecture.
26335 For new architectures we will have to check these tests. */
26336 gas_assert (arch
<= TAG_CPU_ARCH_V8
26337 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26338 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26339 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26340 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26341 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26342 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26343 || (profile
== '\0'
26344 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26345 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26346 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26348 /* Tag_MP_extension_use. */
26349 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26350 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26352 /* Tag Virtualization_use. */
26353 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26355 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26358 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26361 /* Add the default contents for the .ARM.attributes section. */
26365 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26368 aeabi_set_public_attributes ();
26370 #endif /* OBJ_ELF */
26373 /* Parse a .cpu directive. */
26376 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26378 const struct arm_cpu_option_table
*opt
;
26382 name
= input_line_pointer
;
26383 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26384 input_line_pointer
++;
26385 saved_char
= *input_line_pointer
;
26386 *input_line_pointer
= 0;
26388 /* Skip the first "all" entry. */
26389 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26390 if (streq (opt
->name
, name
))
26392 mcpu_cpu_opt
= &opt
->value
;
26393 selected_cpu
= opt
->value
;
26394 if (opt
->canonical_name
)
26395 strcpy (selected_cpu_name
, opt
->canonical_name
);
26399 for (i
= 0; opt
->name
[i
]; i
++)
26400 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26402 selected_cpu_name
[i
] = 0;
26404 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26405 *input_line_pointer
= saved_char
;
26406 demand_empty_rest_of_line ();
26409 as_bad (_("unknown cpu `%s'"), name
);
26410 *input_line_pointer
= saved_char
;
26411 ignore_rest_of_line ();
26415 /* Parse a .arch directive. */
26418 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26420 const struct arm_arch_option_table
*opt
;
26424 name
= input_line_pointer
;
26425 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26426 input_line_pointer
++;
26427 saved_char
= *input_line_pointer
;
26428 *input_line_pointer
= 0;
26430 /* Skip the first "all" entry. */
26431 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26432 if (streq (opt
->name
, name
))
26434 mcpu_cpu_opt
= &opt
->value
;
26435 selected_cpu
= opt
->value
;
26436 strcpy (selected_cpu_name
, opt
->name
);
26437 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26438 *input_line_pointer
= saved_char
;
26439 demand_empty_rest_of_line ();
26443 as_bad (_("unknown architecture `%s'\n"), name
);
26444 *input_line_pointer
= saved_char
;
26445 ignore_rest_of_line ();
26449 /* Parse a .object_arch directive. */
26452 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26454 const struct arm_arch_option_table
*opt
;
26458 name
= input_line_pointer
;
26459 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26460 input_line_pointer
++;
26461 saved_char
= *input_line_pointer
;
26462 *input_line_pointer
= 0;
26464 /* Skip the first "all" entry. */
26465 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26466 if (streq (opt
->name
, name
))
26468 object_arch
= &opt
->value
;
26469 *input_line_pointer
= saved_char
;
26470 demand_empty_rest_of_line ();
26474 as_bad (_("unknown architecture `%s'\n"), name
);
26475 *input_line_pointer
= saved_char
;
26476 ignore_rest_of_line ();
26479 /* Parse a .arch_extension directive. */
26482 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26484 const struct arm_option_extension_value_table
*opt
;
26485 const arm_feature_set arm_any
= ARM_ANY
;
26488 int adding_value
= 1;
26490 name
= input_line_pointer
;
26491 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26492 input_line_pointer
++;
26493 saved_char
= *input_line_pointer
;
26494 *input_line_pointer
= 0;
26496 if (strlen (name
) >= 2
26497 && strncmp (name
, "no", 2) == 0)
26503 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26504 if (streq (opt
->name
, name
))
26506 int i
, nb_allowed_archs
=
26507 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
26508 for (i
= 0; i
< nb_allowed_archs
; i
++)
26511 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26513 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *mcpu_cpu_opt
))
26517 if (i
== nb_allowed_archs
)
26519 as_bad (_("architectural extension `%s' is not allowed for the "
26520 "current base architecture"), name
);
26525 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26528 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26530 mcpu_cpu_opt
= &selected_cpu
;
26531 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26532 *input_line_pointer
= saved_char
;
26533 demand_empty_rest_of_line ();
26537 if (opt
->name
== NULL
)
26538 as_bad (_("unknown architecture extension `%s'\n"), name
);
26540 *input_line_pointer
= saved_char
;
26541 ignore_rest_of_line ();
26544 /* Parse a .fpu directive. */
26547 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26549 const struct arm_option_fpu_value_table
*opt
;
26553 name
= input_line_pointer
;
26554 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26555 input_line_pointer
++;
26556 saved_char
= *input_line_pointer
;
26557 *input_line_pointer
= 0;
26559 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26560 if (streq (opt
->name
, name
))
26562 mfpu_opt
= &opt
->value
;
26563 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26564 *input_line_pointer
= saved_char
;
26565 demand_empty_rest_of_line ();
26569 as_bad (_("unknown floating point format `%s'\n"), name
);
26570 *input_line_pointer
= saved_char
;
26571 ignore_rest_of_line ();
26574 /* Copy symbol information. */
26577 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26579 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26583 /* Given a symbolic attribute NAME, return the proper integer value.
26584 Returns -1 if the attribute is not known. */
26587 arm_convert_symbolic_attribute (const char *name
)
26589 static const struct
26594 attribute_table
[] =
26596 /* When you modify this table you should
26597 also modify the list in doc/c-arm.texi. */
26598 #define T(tag) {#tag, tag}
26599 T (Tag_CPU_raw_name
),
26602 T (Tag_CPU_arch_profile
),
26603 T (Tag_ARM_ISA_use
),
26604 T (Tag_THUMB_ISA_use
),
26608 T (Tag_Advanced_SIMD_arch
),
26609 T (Tag_PCS_config
),
26610 T (Tag_ABI_PCS_R9_use
),
26611 T (Tag_ABI_PCS_RW_data
),
26612 T (Tag_ABI_PCS_RO_data
),
26613 T (Tag_ABI_PCS_GOT_use
),
26614 T (Tag_ABI_PCS_wchar_t
),
26615 T (Tag_ABI_FP_rounding
),
26616 T (Tag_ABI_FP_denormal
),
26617 T (Tag_ABI_FP_exceptions
),
26618 T (Tag_ABI_FP_user_exceptions
),
26619 T (Tag_ABI_FP_number_model
),
26620 T (Tag_ABI_align_needed
),
26621 T (Tag_ABI_align8_needed
),
26622 T (Tag_ABI_align_preserved
),
26623 T (Tag_ABI_align8_preserved
),
26624 T (Tag_ABI_enum_size
),
26625 T (Tag_ABI_HardFP_use
),
26626 T (Tag_ABI_VFP_args
),
26627 T (Tag_ABI_WMMX_args
),
26628 T (Tag_ABI_optimization_goals
),
26629 T (Tag_ABI_FP_optimization_goals
),
26630 T (Tag_compatibility
),
26631 T (Tag_CPU_unaligned_access
),
26632 T (Tag_FP_HP_extension
),
26633 T (Tag_VFP_HP_extension
),
26634 T (Tag_ABI_FP_16bit_format
),
26635 T (Tag_MPextension_use
),
26637 T (Tag_nodefaults
),
26638 T (Tag_also_compatible_with
),
26639 T (Tag_conformance
),
26641 T (Tag_Virtualization_use
),
26642 T (Tag_DSP_extension
),
26643 /* We deliberately do not include Tag_MPextension_use_legacy. */
26651 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26652 if (streq (name
, attribute_table
[i
].name
))
26653 return attribute_table
[i
].tag
;
26659 /* Apply sym value for relocations only in the case that they are for
26660 local symbols in the same segment as the fixup and you have the
26661 respective architectural feature for blx and simple switches. */
26663 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26666 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26667 /* PR 17444: If the local symbol is in a different section then a reloc
26668 will always be generated for it, so applying the symbol value now
26669 will result in a double offset being stored in the relocation. */
26670 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26671 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26673 switch (fixP
->fx_r_type
)
26675 case BFD_RELOC_ARM_PCREL_BLX
:
26676 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26677 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26681 case BFD_RELOC_ARM_PCREL_CALL
:
26682 case BFD_RELOC_THUMB_PCREL_BLX
:
26683 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26694 #endif /* OBJ_ELF */