1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
211 static const arm_feature_set arm_cext_iwmmxt2
=
212 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
213 static const arm_feature_set arm_cext_iwmmxt
=
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
215 static const arm_feature_set arm_cext_xscale
=
216 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
217 static const arm_feature_set arm_cext_maverick
=
218 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
219 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
220 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
221 static const arm_feature_set fpu_vfp_ext_v1xd
=
222 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
223 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
224 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
225 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
226 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_ext_d32
=
228 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
229 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
230 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
231 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
232 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
233 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
234 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
236 static int mfloat_abi_opt
= -1;
237 /* Record user cpu selection for object attributes. */
238 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
239 /* Must be long enough to hold any of the names in arm_cpus. */
240 static char selected_cpu_name
[16];
243 static int meabi_flags
= EABI_DEFAULT
;
245 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
248 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
253 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
258 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
259 symbolS
* GOT_symbol
;
262 /* 0: assemble for ARM,
263 1: assemble for Thumb,
264 2: assemble for Thumb even though target CPU does not support thumb
266 static int thumb_mode
= 0;
267 /* A value distinct from the possible values for thumb_mode that we
268 can use to record whether thumb_mode has been copied into the
269 tc_frag_data field of a frag. */
270 #define MODE_RECORDED (1 << 4)
272 /* Specifies the intrinsic IT insn behavior mode. */
273 enum implicit_it_mode
275 IMPLICIT_IT_MODE_NEVER
= 0x00,
276 IMPLICIT_IT_MODE_ARM
= 0x01,
277 IMPLICIT_IT_MODE_THUMB
= 0x02,
278 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
280 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
282 /* If unified_syntax is true, we are processing the new unified
283 ARM/Thumb syntax. Important differences from the old ARM mode:
285 - Immediate operands do not require a # prefix.
286 - Conditional affixes always appear at the end of the
287 instruction. (For backward compatibility, those instructions
288 that formerly had them in the middle, continue to accept them
290 - The IT instruction may appear, and if it does is validated
291 against subsequent conditional affixes. It does not generate
294 Important differences from the old Thumb mode:
296 - Immediate operands do not require a # prefix.
297 - Most of the V6T2 instructions are only available in unified mode.
298 - The .N and .W suffixes are recognized and honored (it is an error
299 if they cannot be honored).
300 - All instructions set the flags if and only if they have an 's' affix.
301 - Conditional affixes may be used. They are validated against
302 preceding IT instructions. Unlike ARM mode, you cannot use a
303 conditional affix except in the scope of an IT instruction. */
305 static bfd_boolean unified_syntax
= FALSE
;
320 enum neon_el_type type
;
324 #define NEON_MAX_TYPE_ELS 4
328 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
332 enum it_instruction_type
337 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
338 if inside, should be the last one. */
339 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
340 i.e. BKPT and NOP. */
341 IT_INSN
/* The IT insn has been parsed. */
347 unsigned long instruction
;
351 /* "uncond_value" is set to the value in place of the conditional field in
352 unconditional versions of the instruction, or -1 if nothing is
355 struct neon_type vectype
;
356 /* This does not indicate an actual NEON instruction, only that
357 the mnemonic accepts neon-style type suffixes. */
359 /* Set to the opcode if the instruction needs relaxation.
360 Zero if the instruction is not relaxed. */
364 bfd_reloc_code_real_type type
;
369 enum it_instruction_type it_insn_type
;
375 struct neon_type_el vectype
;
376 unsigned present
: 1; /* Operand present. */
377 unsigned isreg
: 1; /* Operand was a register. */
378 unsigned immisreg
: 1; /* .imm field is a second register. */
379 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
380 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
381 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
382 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
383 instructions. This allows us to disambiguate ARM <-> vector insns. */
384 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
385 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
386 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
387 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
388 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
389 unsigned writeback
: 1; /* Operand has trailing ! */
390 unsigned preind
: 1; /* Preindexed address. */
391 unsigned postind
: 1; /* Postindexed address. */
392 unsigned negative
: 1; /* Index register was negated. */
393 unsigned shifted
: 1; /* Shift applied to operation. */
394 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
398 static struct arm_it inst
;
400 #define NUM_FLOAT_VALS 8
402 const char * fp_const
[] =
404 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
407 /* Number of littlenums required to hold an extended precision number. */
408 #define MAX_LITTLENUMS 6
410 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
420 #define CP_T_X 0x00008000
421 #define CP_T_Y 0x00400000
423 #define CONDS_BIT 0x00100000
424 #define LOAD_BIT 0x00100000
426 #define DOUBLE_LOAD_FLAG 0x00000001
430 const char * template_name
;
434 #define COND_ALWAYS 0xE
438 const char * template_name
;
442 struct asm_barrier_opt
444 const char * template_name
;
448 /* The bit that distinguishes CPSR and SPSR. */
449 #define SPSR_BIT (1 << 22)
451 /* The individual PSR flag bits. */
452 #define PSR_c (1 << 16)
453 #define PSR_x (1 << 17)
454 #define PSR_s (1 << 18)
455 #define PSR_f (1 << 19)
460 bfd_reloc_code_real_type reloc
;
465 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
466 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
471 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
474 /* Bits for DEFINED field in neon_typed_alias. */
475 #define NTA_HASTYPE 1
476 #define NTA_HASINDEX 2
478 struct neon_typed_alias
480 unsigned char defined
;
482 struct neon_type_el eltype
;
485 /* ARM register categories. This includes coprocessor numbers and various
486 architecture extensions' registers. */
513 /* Structure for a hash table entry for a register.
514 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
515 information which states whether a vector type or index is specified (for a
516 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
522 unsigned char builtin
;
523 struct neon_typed_alias
* neon
;
526 /* Diagnostics used when we don't get a register of the expected type. */
527 const char * const reg_expected_msgs
[] =
529 N_("ARM register expected"),
530 N_("bad or missing co-processor number"),
531 N_("co-processor register expected"),
532 N_("FPA register expected"),
533 N_("VFP single precision register expected"),
534 N_("VFP/Neon double precision register expected"),
535 N_("Neon quad precision register expected"),
536 N_("VFP single or double precision register expected"),
537 N_("Neon double or quad precision register expected"),
538 N_("VFP single, double or Neon quad precision register expected"),
539 N_("VFP system register expected"),
540 N_("Maverick MVF register expected"),
541 N_("Maverick MVD register expected"),
542 N_("Maverick MVFX register expected"),
543 N_("Maverick MVDX register expected"),
544 N_("Maverick MVAX register expected"),
545 N_("Maverick DSPSC register expected"),
546 N_("iWMMXt data register expected"),
547 N_("iWMMXt control register expected"),
548 N_("iWMMXt scalar register expected"),
549 N_("XScale accumulator register expected"),
552 /* Some well known registers that we refer to directly elsewhere. */
557 /* ARM instructions take 4bytes in the object file, Thumb instructions
563 /* Basic string to match. */
564 const char * template_name
;
566 /* Parameters to instruction. */
567 unsigned int operands
[8];
569 /* Conditional tag - see opcode_lookup. */
570 unsigned int tag
: 4;
572 /* Basic instruction code. */
573 unsigned int avalue
: 28;
575 /* Thumb-format instruction code. */
578 /* Which architecture variant provides this instruction. */
579 const arm_feature_set
* avariant
;
580 const arm_feature_set
* tvariant
;
582 /* Function to call to encode instruction in ARM format. */
583 void (* aencode
) (void);
585 /* Function to call to encode instruction in Thumb format. */
586 void (* tencode
) (void);
589 /* Defines for various bits that we will want to toggle. */
590 #define INST_IMMEDIATE 0x02000000
591 #define OFFSET_REG 0x02000000
592 #define HWOFFSET_IMM 0x00400000
593 #define SHIFT_BY_REG 0x00000010
594 #define PRE_INDEX 0x01000000
595 #define INDEX_UP 0x00800000
596 #define WRITE_BACK 0x00200000
597 #define LDM_TYPE_2_OR_3 0x00400000
598 #define CPSI_MMOD 0x00020000
600 #define LITERAL_MASK 0xf000f000
601 #define OPCODE_MASK 0xfe1fffff
602 #define V4_STR_BIT 0x00000020
604 #define T2_SUBS_PC_LR 0xf3de8f00
606 #define DATA_OP_SHIFT 21
608 #define T2_OPCODE_MASK 0xfe1fffff
609 #define T2_DATA_OP_SHIFT 21
611 /* Codes to distinguish the arithmetic instructions. */
622 #define OPCODE_CMP 10
623 #define OPCODE_CMN 11
624 #define OPCODE_ORR 12
625 #define OPCODE_MOV 13
626 #define OPCODE_BIC 14
627 #define OPCODE_MVN 15
629 #define T2_OPCODE_AND 0
630 #define T2_OPCODE_BIC 1
631 #define T2_OPCODE_ORR 2
632 #define T2_OPCODE_ORN 3
633 #define T2_OPCODE_EOR 4
634 #define T2_OPCODE_ADD 8
635 #define T2_OPCODE_ADC 10
636 #define T2_OPCODE_SBC 11
637 #define T2_OPCODE_SUB 13
638 #define T2_OPCODE_RSB 14
640 #define T_OPCODE_MUL 0x4340
641 #define T_OPCODE_TST 0x4200
642 #define T_OPCODE_CMN 0x42c0
643 #define T_OPCODE_NEG 0x4240
644 #define T_OPCODE_MVN 0x43c0
646 #define T_OPCODE_ADD_R3 0x1800
647 #define T_OPCODE_SUB_R3 0x1a00
648 #define T_OPCODE_ADD_HI 0x4400
649 #define T_OPCODE_ADD_ST 0xb000
650 #define T_OPCODE_SUB_ST 0xb080
651 #define T_OPCODE_ADD_SP 0xa800
652 #define T_OPCODE_ADD_PC 0xa000
653 #define T_OPCODE_ADD_I8 0x3000
654 #define T_OPCODE_SUB_I8 0x3800
655 #define T_OPCODE_ADD_I3 0x1c00
656 #define T_OPCODE_SUB_I3 0x1e00
658 #define T_OPCODE_ASR_R 0x4100
659 #define T_OPCODE_LSL_R 0x4080
660 #define T_OPCODE_LSR_R 0x40c0
661 #define T_OPCODE_ROR_R 0x41c0
662 #define T_OPCODE_ASR_I 0x1000
663 #define T_OPCODE_LSL_I 0x0000
664 #define T_OPCODE_LSR_I 0x0800
666 #define T_OPCODE_MOV_I8 0x2000
667 #define T_OPCODE_CMP_I8 0x2800
668 #define T_OPCODE_CMP_LR 0x4280
669 #define T_OPCODE_MOV_HR 0x4600
670 #define T_OPCODE_CMP_HR 0x4500
672 #define T_OPCODE_LDR_PC 0x4800
673 #define T_OPCODE_LDR_SP 0x9800
674 #define T_OPCODE_STR_SP 0x9000
675 #define T_OPCODE_LDR_IW 0x6800
676 #define T_OPCODE_STR_IW 0x6000
677 #define T_OPCODE_LDR_IH 0x8800
678 #define T_OPCODE_STR_IH 0x8000
679 #define T_OPCODE_LDR_IB 0x7800
680 #define T_OPCODE_STR_IB 0x7000
681 #define T_OPCODE_LDR_RW 0x5800
682 #define T_OPCODE_STR_RW 0x5000
683 #define T_OPCODE_LDR_RH 0x5a00
684 #define T_OPCODE_STR_RH 0x5200
685 #define T_OPCODE_LDR_RB 0x5c00
686 #define T_OPCODE_STR_RB 0x5400
688 #define T_OPCODE_PUSH 0xb400
689 #define T_OPCODE_POP 0xbc00
691 #define T_OPCODE_BRANCH 0xe000
693 #define THUMB_SIZE 2 /* Size of thumb instruction. */
694 #define THUMB_PP_PC_LR 0x0100
695 #define THUMB_LOAD_BIT 0x0800
696 #define THUMB2_LOAD_BIT 0x00100000
698 #define BAD_ARGS _("bad arguments to instruction")
699 #define BAD_SP _("r13 not allowed here")
700 #define BAD_PC _("r15 not allowed here")
701 #define BAD_COND _("instruction cannot be conditional")
702 #define BAD_OVERLAP _("registers may not be the same")
703 #define BAD_HIREG _("lo register required")
704 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
705 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
706 #define BAD_BRANCH _("branch must be last instruction in IT block")
707 #define BAD_NOT_IT _("instruction not allowed in IT block")
708 #define BAD_FPU _("selected FPU does not support instruction")
709 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
710 #define BAD_IT_COND _("incorrect condition in IT block")
711 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
712 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
713 #define BAD_PC_ADDRESSING \
714 _("cannot use register index with PC-relative addressing")
715 #define BAD_PC_WRITEBACK \
716 _("cannot use writeback with PC-relative addressing")
718 static struct hash_control
* arm_ops_hsh
;
719 static struct hash_control
* arm_cond_hsh
;
720 static struct hash_control
* arm_shift_hsh
;
721 static struct hash_control
* arm_psr_hsh
;
722 static struct hash_control
* arm_v7m_psr_hsh
;
723 static struct hash_control
* arm_reg_hsh
;
724 static struct hash_control
* arm_reloc_hsh
;
725 static struct hash_control
* arm_barrier_opt_hsh
;
727 /* Stuff needed to resolve the label ambiguity
736 symbolS
* last_label_seen
;
737 static int label_is_thumb_function_name
= FALSE
;
739 /* Literal pool structure. Held on a per-section
740 and per-sub-section basis. */
742 #define MAX_LITERAL_POOL_SIZE 1024
743 typedef struct literal_pool
745 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
746 unsigned int next_free_entry
;
751 struct literal_pool
* next
;
754 /* Pointer to a linked list of literal pools. */
755 literal_pool
* list_of_pools
= NULL
;
758 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
760 static struct current_it now_it
;
764 now_it_compatible (int cond
)
766 return (cond
& ~1) == (now_it
.cc
& ~1);
770 conditional_insn (void)
772 return inst
.cond
!= COND_ALWAYS
;
775 static int in_it_block (void);
777 static int handle_it_state (void);
779 static void force_automatic_it_block_close (void);
781 static void it_fsm_post_encode (void);
783 #define set_it_insn_type(type) \
786 inst.it_insn_type = type; \
787 if (handle_it_state () == FAIL) \
792 #define set_it_insn_type_nonvoid(type, failret) \
795 inst.it_insn_type = type; \
796 if (handle_it_state () == FAIL) \
801 #define set_it_insn_type_last() \
804 if (inst.cond == COND_ALWAYS) \
805 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
807 set_it_insn_type (INSIDE_IT_LAST_INSN); \
813 /* This array holds the chars that always start a comment. If the
814 pre-processor is disabled, these aren't very useful. */
815 const char comment_chars
[] = "@";
817 /* This array holds the chars that only start a comment at the beginning of
818 a line. If the line seems to have the form '# 123 filename'
819 .line and .file directives will appear in the pre-processed output. */
820 /* Note that input_file.c hand checks for '#' at the beginning of the
821 first line of the input file. This is because the compiler outputs
822 #NO_APP at the beginning of its output. */
823 /* Also note that comments like this one will always work. */
824 const char line_comment_chars
[] = "#";
826 const char line_separator_chars
[] = ";";
828 /* Chars that can be used to separate mant
829 from exp in floating point numbers. */
830 const char EXP_CHARS
[] = "eE";
832 /* Chars that mean this number is a floating point constant. */
836 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
838 /* Prefix characters that indicate the start of an immediate
840 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
842 /* Separator character handling. */
844 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
847 skip_past_char (char ** str
, char c
)
858 #define skip_past_comma(str) skip_past_char (str, ',')
860 /* Arithmetic expressions (possibly involving symbols). */
862 /* Return TRUE if anything in the expression is a bignum. */
865 walk_no_bignums (symbolS
* sp
)
867 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
870 if (symbol_get_value_expression (sp
)->X_add_symbol
)
872 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
873 || (symbol_get_value_expression (sp
)->X_op_symbol
874 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
880 static int in_my_get_expression
= 0;
882 /* Third argument to my_get_expression. */
883 #define GE_NO_PREFIX 0
884 #define GE_IMM_PREFIX 1
885 #define GE_OPT_PREFIX 2
886 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
887 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
888 #define GE_OPT_PREFIX_BIG 3
891 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
896 /* In unified syntax, all prefixes are optional. */
898 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
903 case GE_NO_PREFIX
: break;
905 if (!is_immediate_prefix (**str
))
907 inst
.error
= _("immediate expression requires a # prefix");
913 case GE_OPT_PREFIX_BIG
:
914 if (is_immediate_prefix (**str
))
920 memset (ep
, 0, sizeof (expressionS
));
922 save_in
= input_line_pointer
;
923 input_line_pointer
= *str
;
924 in_my_get_expression
= 1;
925 seg
= expression (ep
);
926 in_my_get_expression
= 0;
928 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
930 /* We found a bad or missing expression in md_operand(). */
931 *str
= input_line_pointer
;
932 input_line_pointer
= save_in
;
933 if (inst
.error
== NULL
)
934 inst
.error
= (ep
->X_op
== O_absent
935 ? _("missing expression") :_("bad expression"));
940 if (seg
!= absolute_section
941 && seg
!= text_section
942 && seg
!= data_section
943 && seg
!= bss_section
944 && seg
!= undefined_section
)
946 inst
.error
= _("bad segment");
947 *str
= input_line_pointer
;
948 input_line_pointer
= save_in
;
955 /* Get rid of any bignums now, so that we don't generate an error for which
956 we can't establish a line number later on. Big numbers are never valid
957 in instructions, which is where this routine is always called. */
958 if (prefix_mode
!= GE_OPT_PREFIX_BIG
959 && (ep
->X_op
== O_big
961 && (walk_no_bignums (ep
->X_add_symbol
)
963 && walk_no_bignums (ep
->X_op_symbol
))))))
965 inst
.error
= _("invalid constant");
966 *str
= input_line_pointer
;
967 input_line_pointer
= save_in
;
971 *str
= input_line_pointer
;
972 input_line_pointer
= save_in
;
976 /* Turn a string in input_line_pointer into a floating point constant
977 of type TYPE, and store the appropriate bytes in *LITP. The number
978 of LITTLENUMS emitted is stored in *SIZEP. An error message is
979 returned, or NULL on OK.
981 Note that fp constants aren't represent in the normal way on the ARM.
982 In big endian mode, things are as expected. However, in little endian
983 mode fp constants are big-endian word-wise, and little-endian byte-wise
984 within the words. For example, (double) 1.1 in big endian mode is
985 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
986 the byte sequence 99 99 f1 3f 9a 99 99 99.
988 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
991 md_atof (int type
, char * litP
, int * sizeP
)
994 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1026 return _("Unrecognized or unsupported floating point constant");
1029 t
= atof_ieee (input_line_pointer
, type
, words
);
1031 input_line_pointer
= t
;
1032 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1034 if (target_big_endian
)
1036 for (i
= 0; i
< prec
; i
++)
1038 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1039 litP
+= sizeof (LITTLENUM_TYPE
);
1044 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1045 for (i
= prec
- 1; i
>= 0; i
--)
1047 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1048 litP
+= sizeof (LITTLENUM_TYPE
);
1051 /* For a 4 byte float the order of elements in `words' is 1 0.
1052 For an 8 byte float the order is 1 0 3 2. */
1053 for (i
= 0; i
< prec
; i
+= 2)
1055 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1056 sizeof (LITTLENUM_TYPE
));
1057 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1058 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1059 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1066 /* We handle all bad expressions here, so that we can report the faulty
1067 instruction in the error message. */
1069 md_operand (expressionS
* exp
)
1071 if (in_my_get_expression
)
1072 exp
->X_op
= O_illegal
;
1075 /* Immediate values. */
1077 /* Generic immediate-value read function for use in directives.
1078 Accepts anything that 'expression' can fold to a constant.
1079 *val receives the number. */
1082 immediate_for_directive (int *val
)
1085 exp
.X_op
= O_illegal
;
1087 if (is_immediate_prefix (*input_line_pointer
))
1089 input_line_pointer
++;
1093 if (exp
.X_op
!= O_constant
)
1095 as_bad (_("expected #constant"));
1096 ignore_rest_of_line ();
1099 *val
= exp
.X_add_number
;
1104 /* Register parsing. */
1106 /* Generic register parser. CCP points to what should be the
1107 beginning of a register name. If it is indeed a valid register
1108 name, advance CCP over it and return the reg_entry structure;
1109 otherwise return NULL. Does not issue diagnostics. */
1111 static struct reg_entry
*
1112 arm_reg_parse_multi (char **ccp
)
1116 struct reg_entry
*reg
;
1118 #ifdef REGISTER_PREFIX
1119 if (*start
!= REGISTER_PREFIX
)
1123 #ifdef OPTIONAL_REGISTER_PREFIX
1124 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1129 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1134 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1136 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1146 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1147 enum arm_reg_type type
)
1149 /* Alternative syntaxes are accepted for a few register classes. */
1156 /* Generic coprocessor register names are allowed for these. */
1157 if (reg
&& reg
->type
== REG_TYPE_CN
)
1162 /* For backward compatibility, a bare number is valid here. */
1164 unsigned long processor
= strtoul (start
, ccp
, 10);
1165 if (*ccp
!= start
&& processor
<= 15)
1169 case REG_TYPE_MMXWC
:
1170 /* WC includes WCG. ??? I'm not sure this is true for all
1171 instructions that take WC registers. */
1172 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1183 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1184 return value is the register number or FAIL. */
1187 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1190 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1193 /* Do not allow a scalar (reg+index) to parse as a register. */
1194 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1197 if (reg
&& reg
->type
== type
)
1200 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1207 /* Parse a Neon type specifier. *STR should point at the leading '.'
1208 character. Does no verification at this stage that the type fits the opcode
1215 Can all be legally parsed by this function.
1217 Fills in neon_type struct pointer with parsed information, and updates STR
1218 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1219 type, FAIL if not. */
1222 parse_neon_type (struct neon_type
*type
, char **str
)
1229 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1231 enum neon_el_type thistype
= NT_untyped
;
1232 unsigned thissize
= -1u;
1239 /* Just a size without an explicit type. */
1243 switch (TOLOWER (*ptr
))
1245 case 'i': thistype
= NT_integer
; break;
1246 case 'f': thistype
= NT_float
; break;
1247 case 'p': thistype
= NT_poly
; break;
1248 case 's': thistype
= NT_signed
; break;
1249 case 'u': thistype
= NT_unsigned
; break;
1251 thistype
= NT_float
;
1256 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1262 /* .f is an abbreviation for .f32. */
1263 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1268 thissize
= strtoul (ptr
, &ptr
, 10);
1270 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1273 as_bad (_("bad size %d in type specifier"), thissize
);
1281 type
->el
[type
->elems
].type
= thistype
;
1282 type
->el
[type
->elems
].size
= thissize
;
1287 /* Empty/missing type is not a successful parse. */
1288 if (type
->elems
== 0)
1296 /* Errors may be set multiple times during parsing or bit encoding
1297 (particularly in the Neon bits), but usually the earliest error which is set
1298 will be the most meaningful. Avoid overwriting it with later (cascading)
1299 errors by calling this function. */
1302 first_error (const char *err
)
1308 /* Parse a single type, e.g. ".s32", leading period included. */
1310 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1313 struct neon_type optype
;
1317 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1319 if (optype
.elems
== 1)
1320 *vectype
= optype
.el
[0];
1323 first_error (_("only one type should be specified for operand"));
1329 first_error (_("vector type expected"));
1341 /* Special meanings for indices (which have a range of 0-7), which will fit into
1344 #define NEON_ALL_LANES 15
1345 #define NEON_INTERLEAVE_LANES 14
1347 /* Parse either a register or a scalar, with an optional type. Return the
1348 register number, and optionally fill in the actual type of the register
1349 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1350 type/index information in *TYPEINFO. */
1353 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1354 enum arm_reg_type
*rtype
,
1355 struct neon_typed_alias
*typeinfo
)
1358 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1359 struct neon_typed_alias atype
;
1360 struct neon_type_el parsetype
;
1364 atype
.eltype
.type
= NT_invtype
;
1365 atype
.eltype
.size
= -1;
1367 /* Try alternate syntax for some types of register. Note these are mutually
1368 exclusive with the Neon syntax extensions. */
1371 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1379 /* Undo polymorphism when a set of register types may be accepted. */
1380 if ((type
== REG_TYPE_NDQ
1381 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1382 || (type
== REG_TYPE_VFSD
1383 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1384 || (type
== REG_TYPE_NSDQ
1385 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1386 || reg
->type
== REG_TYPE_NQ
))
1387 || (type
== REG_TYPE_MMXWC
1388 && (reg
->type
== REG_TYPE_MMXWCG
)))
1389 type
= (enum arm_reg_type
) reg
->type
;
1391 if (type
!= reg
->type
)
1397 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1399 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1401 first_error (_("can't redefine type for operand"));
1404 atype
.defined
|= NTA_HASTYPE
;
1405 atype
.eltype
= parsetype
;
1408 if (skip_past_char (&str
, '[') == SUCCESS
)
1410 if (type
!= REG_TYPE_VFD
)
1412 first_error (_("only D registers may be indexed"));
1416 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1418 first_error (_("can't change index for operand"));
1422 atype
.defined
|= NTA_HASINDEX
;
1424 if (skip_past_char (&str
, ']') == SUCCESS
)
1425 atype
.index
= NEON_ALL_LANES
;
1430 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1432 if (exp
.X_op
!= O_constant
)
1434 first_error (_("constant expression required"));
1438 if (skip_past_char (&str
, ']') == FAIL
)
1441 atype
.index
= exp
.X_add_number
;
1456 /* Like arm_reg_parse, but allow allow the following extra features:
1457 - If RTYPE is non-zero, return the (possibly restricted) type of the
1458 register (e.g. Neon double or quad reg when either has been requested).
1459 - If this is a Neon vector type with additional type information, fill
1460 in the struct pointed to by VECTYPE (if non-NULL).
1461 This function will fault on encountering a scalar. */
1464 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1465 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1467 struct neon_typed_alias atype
;
1469 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1474 /* Do not allow a scalar (reg+index) to parse as a register. */
1475 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1477 first_error (_("register operand expected, but got scalar"));
1482 *vectype
= atype
.eltype
;
1489 #define NEON_SCALAR_REG(X) ((X) >> 4)
1490 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1492 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1493 have enough information to be able to do a good job bounds-checking. So, we
1494 just do easy checks here, and do further checks later. */
1497 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1501 struct neon_typed_alias atype
;
1503 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1505 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1508 if (atype
.index
== NEON_ALL_LANES
)
1510 first_error (_("scalar must have an index"));
1513 else if (atype
.index
>= 64 / elsize
)
1515 first_error (_("scalar index out of range"));
1520 *type
= atype
.eltype
;
1524 return reg
* 16 + atype
.index
;
1527 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1530 parse_reg_list (char ** strp
)
1532 char * str
= * strp
;
1536 /* We come back here if we get ranges concatenated by '+' or '|'. */
1551 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1553 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1563 first_error (_("bad range in register list"));
1567 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1569 if (range
& (1 << i
))
1571 (_("Warning: duplicated register (r%d) in register list"),
1579 if (range
& (1 << reg
))
1580 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1582 else if (reg
<= cur_reg
)
1583 as_tsktsk (_("Warning: register range not in ascending order"));
1588 while (skip_past_comma (&str
) != FAIL
1589 || (in_range
= 1, *str
++ == '-'));
1594 first_error (_("missing `}'"));
1602 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1605 if (exp
.X_op
== O_constant
)
1607 if (exp
.X_add_number
1608 != (exp
.X_add_number
& 0x0000ffff))
1610 inst
.error
= _("invalid register mask");
1614 if ((range
& exp
.X_add_number
) != 0)
1616 int regno
= range
& exp
.X_add_number
;
1619 regno
= (1 << regno
) - 1;
1621 (_("Warning: duplicated register (r%d) in register list"),
1625 range
|= exp
.X_add_number
;
1629 if (inst
.reloc
.type
!= 0)
1631 inst
.error
= _("expression too complex");
1635 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1636 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1637 inst
.reloc
.pc_rel
= 0;
1641 if (*str
== '|' || *str
== '+')
1647 while (another_range
);
1653 /* Types of registers in a list. */
1662 /* Parse a VFP register list. If the string is invalid return FAIL.
1663 Otherwise return the number of registers, and set PBASE to the first
1664 register. Parses registers of type ETYPE.
1665 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1666 - Q registers can be used to specify pairs of D registers
1667 - { } can be omitted from around a singleton register list
1668 FIXME: This is not implemented, as it would require backtracking in
1671 This could be done (the meaning isn't really ambiguous), but doesn't
1672 fit in well with the current parsing framework.
1673 - 32 D registers may be used (also true for VFPv3).
1674 FIXME: Types are ignored in these register lists, which is probably a
1678 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1683 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1687 unsigned long mask
= 0;
1692 inst
.error
= _("expecting {");
1701 regtype
= REG_TYPE_VFS
;
1706 regtype
= REG_TYPE_VFD
;
1709 case REGLIST_NEON_D
:
1710 regtype
= REG_TYPE_NDQ
;
1714 if (etype
!= REGLIST_VFP_S
)
1716 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1717 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1721 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1724 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1731 base_reg
= max_regs
;
1735 int setmask
= 1, addregs
= 1;
1737 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1739 if (new_base
== FAIL
)
1741 first_error (_(reg_expected_msgs
[regtype
]));
1745 if (new_base
>= max_regs
)
1747 first_error (_("register out of range in list"));
1751 /* Note: a value of 2 * n is returned for the register Q<n>. */
1752 if (regtype
== REG_TYPE_NQ
)
1758 if (new_base
< base_reg
)
1759 base_reg
= new_base
;
1761 if (mask
& (setmask
<< new_base
))
1763 first_error (_("invalid register list"));
1767 if ((mask
>> new_base
) != 0 && ! warned
)
1769 as_tsktsk (_("register list not in ascending order"));
1773 mask
|= setmask
<< new_base
;
1776 if (*str
== '-') /* We have the start of a range expression */
1782 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1785 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1789 if (high_range
>= max_regs
)
1791 first_error (_("register out of range in list"));
1795 if (regtype
== REG_TYPE_NQ
)
1796 high_range
= high_range
+ 1;
1798 if (high_range
<= new_base
)
1800 inst
.error
= _("register range not in ascending order");
1804 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1806 if (mask
& (setmask
<< new_base
))
1808 inst
.error
= _("invalid register list");
1812 mask
|= setmask
<< new_base
;
1817 while (skip_past_comma (&str
) != FAIL
);
1821 /* Sanity check -- should have raised a parse error above. */
1822 if (count
== 0 || count
> max_regs
)
1827 /* Final test -- the registers must be consecutive. */
1829 for (i
= 0; i
< count
; i
++)
1831 if ((mask
& (1u << i
)) == 0)
1833 inst
.error
= _("non-contiguous register range");
1843 /* True if two alias types are the same. */
1846 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1854 if (a
->defined
!= b
->defined
)
1857 if ((a
->defined
& NTA_HASTYPE
) != 0
1858 && (a
->eltype
.type
!= b
->eltype
.type
1859 || a
->eltype
.size
!= b
->eltype
.size
))
1862 if ((a
->defined
& NTA_HASINDEX
) != 0
1863 && (a
->index
!= b
->index
))
1869 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1870 The base register is put in *PBASE.
1871 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1873 The register stride (minus one) is put in bit 4 of the return value.
1874 Bits [6:5] encode the list length (minus one).
1875 The type of the list elements is put in *ELTYPE, if non-NULL. */
1877 #define NEON_LANE(X) ((X) & 0xf)
1878 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1879 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1882 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1883 struct neon_type_el
*eltype
)
1890 int leading_brace
= 0;
1891 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1892 const char *const incr_error
= _("register stride must be 1 or 2");
1893 const char *const type_error
= _("mismatched element/structure types in list");
1894 struct neon_typed_alias firsttype
;
1896 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1901 struct neon_typed_alias atype
;
1902 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1906 first_error (_(reg_expected_msgs
[rtype
]));
1913 if (rtype
== REG_TYPE_NQ
)
1919 else if (reg_incr
== -1)
1921 reg_incr
= getreg
- base_reg
;
1922 if (reg_incr
< 1 || reg_incr
> 2)
1924 first_error (_(incr_error
));
1928 else if (getreg
!= base_reg
+ reg_incr
* count
)
1930 first_error (_(incr_error
));
1934 if (! neon_alias_types_same (&atype
, &firsttype
))
1936 first_error (_(type_error
));
1940 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1944 struct neon_typed_alias htype
;
1945 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1947 lane
= NEON_INTERLEAVE_LANES
;
1948 else if (lane
!= NEON_INTERLEAVE_LANES
)
1950 first_error (_(type_error
));
1955 else if (reg_incr
!= 1)
1957 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1961 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1964 first_error (_(reg_expected_msgs
[rtype
]));
1967 if (! neon_alias_types_same (&htype
, &firsttype
))
1969 first_error (_(type_error
));
1972 count
+= hireg
+ dregs
- getreg
;
1976 /* If we're using Q registers, we can't use [] or [n] syntax. */
1977 if (rtype
== REG_TYPE_NQ
)
1983 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1987 else if (lane
!= atype
.index
)
1989 first_error (_(type_error
));
1993 else if (lane
== -1)
1994 lane
= NEON_INTERLEAVE_LANES
;
1995 else if (lane
!= NEON_INTERLEAVE_LANES
)
1997 first_error (_(type_error
));
2002 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2004 /* No lane set by [x]. We must be interleaving structures. */
2006 lane
= NEON_INTERLEAVE_LANES
;
2009 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2010 || (count
> 1 && reg_incr
== -1))
2012 first_error (_("error parsing element/structure list"));
2016 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2018 first_error (_("expected }"));
2026 *eltype
= firsttype
.eltype
;
2031 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2034 /* Parse an explicit relocation suffix on an expression. This is
2035 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2036 arm_reloc_hsh contains no entries, so this function can only
2037 succeed if there is no () after the word. Returns -1 on error,
2038 BFD_RELOC_UNUSED if there wasn't any suffix. */
2040 parse_reloc (char **str
)
2042 struct reloc_entry
*r
;
2046 return BFD_RELOC_UNUSED
;
2051 while (*q
&& *q
!= ')' && *q
!= ',')
2056 if ((r
= (struct reloc_entry
*)
2057 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2064 /* Directives: register aliases. */
2066 static struct reg_entry
*
2067 insert_reg_alias (char *str
, unsigned number
, int type
)
2069 struct reg_entry
*new_reg
;
2072 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2074 if (new_reg
->builtin
)
2075 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2077 /* Only warn about a redefinition if it's not defined as the
2079 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2080 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2085 name
= xstrdup (str
);
2086 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2088 new_reg
->name
= name
;
2089 new_reg
->number
= number
;
2090 new_reg
->type
= type
;
2091 new_reg
->builtin
= FALSE
;
2092 new_reg
->neon
= NULL
;
2094 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2101 insert_neon_reg_alias (char *str
, int number
, int type
,
2102 struct neon_typed_alias
*atype
)
2104 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2108 first_error (_("attempt to redefine typed alias"));
2114 reg
->neon
= (struct neon_typed_alias
*)
2115 xmalloc (sizeof (struct neon_typed_alias
));
2116 *reg
->neon
= *atype
;
2120 /* Look for the .req directive. This is of the form:
2122 new_register_name .req existing_register_name
2124 If we find one, or if it looks sufficiently like one that we want to
2125 handle any error here, return TRUE. Otherwise return FALSE. */
2128 create_register_alias (char * newname
, char *p
)
2130 struct reg_entry
*old
;
2131 char *oldname
, *nbuf
;
2134 /* The input scrubber ensures that whitespace after the mnemonic is
2135 collapsed to single spaces. */
2137 if (strncmp (oldname
, " .req ", 6) != 0)
2141 if (*oldname
== '\0')
2144 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2147 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2151 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2152 the desired alias name, and p points to its end. If not, then
2153 the desired alias name is in the global original_case_string. */
2154 #ifdef TC_CASE_SENSITIVE
2157 newname
= original_case_string
;
2158 nlen
= strlen (newname
);
2161 nbuf
= (char *) alloca (nlen
+ 1);
2162 memcpy (nbuf
, newname
, nlen
);
2165 /* Create aliases under the new name as stated; an all-lowercase
2166 version of the new name; and an all-uppercase version of the new
2168 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2170 for (p
= nbuf
; *p
; p
++)
2173 if (strncmp (nbuf
, newname
, nlen
))
2175 /* If this attempt to create an additional alias fails, do not bother
2176 trying to create the all-lower case alias. We will fail and issue
2177 a second, duplicate error message. This situation arises when the
2178 programmer does something like:
2181 The second .req creates the "Foo" alias but then fails to create
2182 the artificial FOO alias because it has already been created by the
2184 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2188 for (p
= nbuf
; *p
; p
++)
2191 if (strncmp (nbuf
, newname
, nlen
))
2192 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2198 /* Create a Neon typed/indexed register alias using directives, e.g.:
2203 These typed registers can be used instead of the types specified after the
2204 Neon mnemonic, so long as all operands given have types. Types can also be
2205 specified directly, e.g.:
2206 vadd d0.s32, d1.s32, d2.s32 */
2209 create_neon_reg_alias (char *newname
, char *p
)
2211 enum arm_reg_type basetype
;
2212 struct reg_entry
*basereg
;
2213 struct reg_entry mybasereg
;
2214 struct neon_type ntype
;
2215 struct neon_typed_alias typeinfo
;
2216 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2219 typeinfo
.defined
= 0;
2220 typeinfo
.eltype
.type
= NT_invtype
;
2221 typeinfo
.eltype
.size
= -1;
2222 typeinfo
.index
= -1;
2226 if (strncmp (p
, " .dn ", 5) == 0)
2227 basetype
= REG_TYPE_VFD
;
2228 else if (strncmp (p
, " .qn ", 5) == 0)
2229 basetype
= REG_TYPE_NQ
;
2238 basereg
= arm_reg_parse_multi (&p
);
2240 if (basereg
&& basereg
->type
!= basetype
)
2242 as_bad (_("bad type for register"));
2246 if (basereg
== NULL
)
2249 /* Try parsing as an integer. */
2250 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2251 if (exp
.X_op
!= O_constant
)
2253 as_bad (_("expression must be constant"));
2256 basereg
= &mybasereg
;
2257 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2263 typeinfo
= *basereg
->neon
;
2265 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2267 /* We got a type. */
2268 if (typeinfo
.defined
& NTA_HASTYPE
)
2270 as_bad (_("can't redefine the type of a register alias"));
2274 typeinfo
.defined
|= NTA_HASTYPE
;
2275 if (ntype
.elems
!= 1)
2277 as_bad (_("you must specify a single type only"));
2280 typeinfo
.eltype
= ntype
.el
[0];
2283 if (skip_past_char (&p
, '[') == SUCCESS
)
2286 /* We got a scalar index. */
2288 if (typeinfo
.defined
& NTA_HASINDEX
)
2290 as_bad (_("can't redefine the index of a scalar alias"));
2294 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2296 if (exp
.X_op
!= O_constant
)
2298 as_bad (_("scalar index must be constant"));
2302 typeinfo
.defined
|= NTA_HASINDEX
;
2303 typeinfo
.index
= exp
.X_add_number
;
2305 if (skip_past_char (&p
, ']') == FAIL
)
2307 as_bad (_("expecting ]"));
2312 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2313 the desired alias name, and p points to its end. If not, then
2314 the desired alias name is in the global original_case_string. */
2315 #ifdef TC_CASE_SENSITIVE
2316 namelen
= nameend
- newname
;
2318 newname
= original_case_string
;
2319 namelen
= strlen (newname
);
2322 namebuf
= (char *) alloca (namelen
+ 1);
2323 strncpy (namebuf
, newname
, namelen
);
2324 namebuf
[namelen
] = '\0';
2326 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2327 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2329 /* Insert name in all uppercase. */
2330 for (p
= namebuf
; *p
; p
++)
2333 if (strncmp (namebuf
, newname
, namelen
))
2334 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2335 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2337 /* Insert name in all lowercase. */
2338 for (p
= namebuf
; *p
; p
++)
2341 if (strncmp (namebuf
, newname
, namelen
))
2342 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2343 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2348 /* Should never be called, as .req goes between the alias and the
2349 register name, not at the beginning of the line. */
2352 s_req (int a ATTRIBUTE_UNUSED
)
2354 as_bad (_("invalid syntax for .req directive"));
2358 s_dn (int a ATTRIBUTE_UNUSED
)
2360 as_bad (_("invalid syntax for .dn directive"));
2364 s_qn (int a ATTRIBUTE_UNUSED
)
2366 as_bad (_("invalid syntax for .qn directive"));
2369 /* The .unreq directive deletes an alias which was previously defined
2370 by .req. For example:
2376 s_unreq (int a ATTRIBUTE_UNUSED
)
2381 name
= input_line_pointer
;
2383 while (*input_line_pointer
!= 0
2384 && *input_line_pointer
!= ' '
2385 && *input_line_pointer
!= '\n')
2386 ++input_line_pointer
;
2388 saved_char
= *input_line_pointer
;
2389 *input_line_pointer
= 0;
2392 as_bad (_("invalid syntax for .unreq directive"));
2395 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2399 as_bad (_("unknown register alias '%s'"), name
);
2400 else if (reg
->builtin
)
2401 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2408 hash_delete (arm_reg_hsh
, name
, FALSE
);
2409 free ((char *) reg
->name
);
2414 /* Also locate the all upper case and all lower case versions.
2415 Do not complain if we cannot find one or the other as it
2416 was probably deleted above. */
2418 nbuf
= strdup (name
);
2419 for (p
= nbuf
; *p
; p
++)
2421 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2424 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2425 free ((char *) reg
->name
);
2431 for (p
= nbuf
; *p
; p
++)
2433 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2436 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2437 free ((char *) reg
->name
);
2447 *input_line_pointer
= saved_char
;
2448 demand_empty_rest_of_line ();
2451 /* Directives: Instruction set selection. */
2454 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2455 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2456 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2457 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2459 /* Create a new mapping symbol for the transition to STATE. */
2462 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2465 const char * symname
;
2472 type
= BSF_NO_FLAGS
;
2476 type
= BSF_NO_FLAGS
;
2480 type
= BSF_NO_FLAGS
;
2486 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2487 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2492 THUMB_SET_FUNC (symbolP
, 0);
2493 ARM_SET_THUMB (symbolP
, 0);
2494 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2498 THUMB_SET_FUNC (symbolP
, 1);
2499 ARM_SET_THUMB (symbolP
, 1);
2500 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2508 /* Save the mapping symbols for future reference. Also check that
2509 we do not place two mapping symbols at the same offset within a
2510 frag. We'll handle overlap between frags in
2511 check_mapping_symbols.
2513 If .fill or other data filling directive generates zero sized data,
2514 the mapping symbol for the following code will have the same value
2515 as the one generated for the data filling directive. In this case,
2516 we replace the old symbol with the new one at the same address. */
2519 if (frag
->tc_frag_data
.first_map
!= NULL
)
2521 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2522 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2524 frag
->tc_frag_data
.first_map
= symbolP
;
2526 if (frag
->tc_frag_data
.last_map
!= NULL
)
2528 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2529 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2530 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2532 frag
->tc_frag_data
.last_map
= symbolP
;
2535 /* We must sometimes convert a region marked as code to data during
2536 code alignment, if an odd number of bytes have to be padded. The
2537 code mapping symbol is pushed to an aligned address. */
2540 insert_data_mapping_symbol (enum mstate state
,
2541 valueT value
, fragS
*frag
, offsetT bytes
)
2543 /* If there was already a mapping symbol, remove it. */
2544 if (frag
->tc_frag_data
.last_map
!= NULL
2545 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2547 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2551 know (frag
->tc_frag_data
.first_map
== symp
);
2552 frag
->tc_frag_data
.first_map
= NULL
;
2554 frag
->tc_frag_data
.last_map
= NULL
;
2555 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2558 make_mapping_symbol (MAP_DATA
, value
, frag
);
2559 make_mapping_symbol (state
, value
+ bytes
, frag
);
2562 static void mapping_state_2 (enum mstate state
, int max_chars
);
2564 /* Set the mapping state to STATE. Only call this when about to
2565 emit some STATE bytes to the file. */
2568 mapping_state (enum mstate state
)
2570 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2572 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2574 if (mapstate
== state
)
2575 /* The mapping symbol has already been emitted.
2576 There is nothing else to do. */
2578 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2579 /* This case will be evaluated later in the next else. */
2581 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2582 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2584 /* Only add the symbol if the offset is > 0:
2585 if we're at the first frag, check it's size > 0;
2586 if we're not at the first frag, then for sure
2587 the offset is > 0. */
2588 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2589 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2592 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2595 mapping_state_2 (state
, 0);
2599 /* Same as mapping_state, but MAX_CHARS bytes have already been
2600 allocated. Put the mapping symbol that far back. */
2603 mapping_state_2 (enum mstate state
, int max_chars
)
2605 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2607 if (!SEG_NORMAL (now_seg
))
2610 if (mapstate
== state
)
2611 /* The mapping symbol has already been emitted.
2612 There is nothing else to do. */
2615 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2616 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2619 #define mapping_state(x) ((void)0)
2620 #define mapping_state_2(x, y) ((void)0)
2623 /* Find the real, Thumb encoded start of a Thumb function. */
2627 find_real_start (symbolS
* symbolP
)
2630 const char * name
= S_GET_NAME (symbolP
);
2631 symbolS
* new_target
;
2633 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2634 #define STUB_NAME ".real_start_of"
2639 /* The compiler may generate BL instructions to local labels because
2640 it needs to perform a branch to a far away location. These labels
2641 do not have a corresponding ".real_start_of" label. We check
2642 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2643 the ".real_start_of" convention for nonlocal branches. */
2644 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2647 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2648 new_target
= symbol_find (real_start
);
2650 if (new_target
== NULL
)
2652 as_warn (_("Failed to find real start of function: %s\n"), name
);
2653 new_target
= symbolP
;
2661 opcode_select (int width
)
2668 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2669 as_bad (_("selected processor does not support THUMB opcodes"));
2672 /* No need to force the alignment, since we will have been
2673 coming from ARM mode, which is word-aligned. */
2674 record_alignment (now_seg
, 1);
2681 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2682 as_bad (_("selected processor does not support ARM opcodes"));
2687 frag_align (2, 0, 0);
2689 record_alignment (now_seg
, 1);
2694 as_bad (_("invalid instruction size selected (%d)"), width
);
2699 s_arm (int ignore ATTRIBUTE_UNUSED
)
2702 demand_empty_rest_of_line ();
2706 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2709 demand_empty_rest_of_line ();
2713 s_code (int unused ATTRIBUTE_UNUSED
)
2717 temp
= get_absolute_expression ();
2722 opcode_select (temp
);
2726 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2731 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2733 /* If we are not already in thumb mode go into it, EVEN if
2734 the target processor does not support thumb instructions.
2735 This is used by gcc/config/arm/lib1funcs.asm for example
2736 to compile interworking support functions even if the
2737 target processor should not support interworking. */
2741 record_alignment (now_seg
, 1);
2744 demand_empty_rest_of_line ();
2748 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2752 /* The following label is the name/address of the start of a Thumb function.
2753 We need to know this for the interworking support. */
2754 label_is_thumb_function_name
= TRUE
;
2757 /* Perform a .set directive, but also mark the alias as
2758 being a thumb function. */
2761 s_thumb_set (int equiv
)
2763 /* XXX the following is a duplicate of the code for s_set() in read.c
2764 We cannot just call that code as we need to get at the symbol that
2771 /* Especial apologies for the random logic:
2772 This just grew, and could be parsed much more simply!
2774 name
= input_line_pointer
;
2775 delim
= get_symbol_end ();
2776 end_name
= input_line_pointer
;
2779 if (*input_line_pointer
!= ',')
2782 as_bad (_("expected comma after name \"%s\""), name
);
2784 ignore_rest_of_line ();
2788 input_line_pointer
++;
2791 if (name
[0] == '.' && name
[1] == '\0')
2793 /* XXX - this should not happen to .thumb_set. */
2797 if ((symbolP
= symbol_find (name
)) == NULL
2798 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2801 /* When doing symbol listings, play games with dummy fragments living
2802 outside the normal fragment chain to record the file and line info
2804 if (listing
& LISTING_SYMBOLS
)
2806 extern struct list_info_struct
* listing_tail
;
2807 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2809 memset (dummy_frag
, 0, sizeof (fragS
));
2810 dummy_frag
->fr_type
= rs_fill
;
2811 dummy_frag
->line
= listing_tail
;
2812 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2813 dummy_frag
->fr_symbol
= symbolP
;
2817 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2820 /* "set" symbols are local unless otherwise specified. */
2821 SF_SET_LOCAL (symbolP
);
2822 #endif /* OBJ_COFF */
2823 } /* Make a new symbol. */
2825 symbol_table_insert (symbolP
);
2830 && S_IS_DEFINED (symbolP
)
2831 && S_GET_SEGMENT (symbolP
) != reg_section
)
2832 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2834 pseudo_set (symbolP
);
2836 demand_empty_rest_of_line ();
2838 /* XXX Now we come to the Thumb specific bit of code. */
2840 THUMB_SET_FUNC (symbolP
, 1);
2841 ARM_SET_THUMB (symbolP
, 1);
2842 #if defined OBJ_ELF || defined OBJ_COFF
2843 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2847 /* Directives: Mode selection. */
2849 /* .syntax [unified|divided] - choose the new unified syntax
2850 (same for Arm and Thumb encoding, modulo slight differences in what
2851 can be represented) or the old divergent syntax for each mode. */
2853 s_syntax (int unused ATTRIBUTE_UNUSED
)
2857 name
= input_line_pointer
;
2858 delim
= get_symbol_end ();
2860 if (!strcasecmp (name
, "unified"))
2861 unified_syntax
= TRUE
;
2862 else if (!strcasecmp (name
, "divided"))
2863 unified_syntax
= FALSE
;
2866 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2869 *input_line_pointer
= delim
;
2870 demand_empty_rest_of_line ();
2873 /* Directives: sectioning and alignment. */
2875 /* Same as s_align_ptwo but align 0 => align 2. */
2878 s_align (int unused ATTRIBUTE_UNUSED
)
2883 long max_alignment
= 15;
2885 temp
= get_absolute_expression ();
2886 if (temp
> max_alignment
)
2887 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2890 as_bad (_("alignment negative. 0 assumed."));
2894 if (*input_line_pointer
== ',')
2896 input_line_pointer
++;
2897 temp_fill
= get_absolute_expression ();
2909 /* Only make a frag if we HAVE to. */
2910 if (temp
&& !need_pass_2
)
2912 if (!fill_p
&& subseg_text_p (now_seg
))
2913 frag_align_code (temp
, 0);
2915 frag_align (temp
, (int) temp_fill
, 0);
2917 demand_empty_rest_of_line ();
2919 record_alignment (now_seg
, temp
);
2923 s_bss (int ignore ATTRIBUTE_UNUSED
)
2925 /* We don't support putting frags in the BSS segment, we fake it by
2926 marking in_bss, then looking at s_skip for clues. */
2927 subseg_set (bss_section
, 0);
2928 demand_empty_rest_of_line ();
2930 #ifdef md_elf_section_change_hook
2931 md_elf_section_change_hook ();
2936 s_even (int ignore ATTRIBUTE_UNUSED
)
2938 /* Never make frag if expect extra pass. */
2940 frag_align (1, 0, 0);
2942 record_alignment (now_seg
, 1);
2944 demand_empty_rest_of_line ();
2947 /* Directives: Literal pools. */
2949 static literal_pool
*
2950 find_literal_pool (void)
2952 literal_pool
* pool
;
2954 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2956 if (pool
->section
== now_seg
2957 && pool
->sub_section
== now_subseg
)
2964 static literal_pool
*
2965 find_or_make_literal_pool (void)
2967 /* Next literal pool ID number. */
2968 static unsigned int latest_pool_num
= 1;
2969 literal_pool
* pool
;
2971 pool
= find_literal_pool ();
2975 /* Create a new pool. */
2976 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2980 pool
->next_free_entry
= 0;
2981 pool
->section
= now_seg
;
2982 pool
->sub_section
= now_subseg
;
2983 pool
->next
= list_of_pools
;
2984 pool
->symbol
= NULL
;
2986 /* Add it to the list. */
2987 list_of_pools
= pool
;
2990 /* New pools, and emptied pools, will have a NULL symbol. */
2991 if (pool
->symbol
== NULL
)
2993 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2994 (valueT
) 0, &zero_address_frag
);
2995 pool
->id
= latest_pool_num
++;
3002 /* Add the literal in the global 'inst'
3003 structure to the relevant literal pool. */
3006 add_to_lit_pool (void)
3008 literal_pool
* pool
;
3011 pool
= find_or_make_literal_pool ();
3013 /* Check if this literal value is already in the pool. */
3014 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3016 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3017 && (inst
.reloc
.exp
.X_op
== O_constant
)
3018 && (pool
->literals
[entry
].X_add_number
3019 == inst
.reloc
.exp
.X_add_number
)
3020 && (pool
->literals
[entry
].X_unsigned
3021 == inst
.reloc
.exp
.X_unsigned
))
3024 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3025 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3026 && (pool
->literals
[entry
].X_add_number
3027 == inst
.reloc
.exp
.X_add_number
)
3028 && (pool
->literals
[entry
].X_add_symbol
3029 == inst
.reloc
.exp
.X_add_symbol
)
3030 && (pool
->literals
[entry
].X_op_symbol
3031 == inst
.reloc
.exp
.X_op_symbol
))
3035 /* Do we need to create a new entry? */
3036 if (entry
== pool
->next_free_entry
)
3038 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3040 inst
.error
= _("literal pool overflow");
3044 pool
->literals
[entry
] = inst
.reloc
.exp
;
3045 pool
->next_free_entry
+= 1;
3048 inst
.reloc
.exp
.X_op
= O_symbol
;
3049 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3050 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3055 /* Can't use symbol_new here, so have to create a symbol and then at
3056 a later date assign it a value. Thats what these functions do. */
3059 symbol_locate (symbolS
* symbolP
,
3060 const char * name
, /* It is copied, the caller can modify. */
3061 segT segment
, /* Segment identifier (SEG_<something>). */
3062 valueT valu
, /* Symbol value. */
3063 fragS
* frag
) /* Associated fragment. */
3065 unsigned int name_length
;
3066 char * preserved_copy_of_name
;
3068 name_length
= strlen (name
) + 1; /* +1 for \0. */
3069 obstack_grow (¬es
, name
, name_length
);
3070 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3072 #ifdef tc_canonicalize_symbol_name
3073 preserved_copy_of_name
=
3074 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3077 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3079 S_SET_SEGMENT (symbolP
, segment
);
3080 S_SET_VALUE (symbolP
, valu
);
3081 symbol_clear_list_pointers (symbolP
);
3083 symbol_set_frag (symbolP
, frag
);
3085 /* Link to end of symbol chain. */
3087 extern int symbol_table_frozen
;
3089 if (symbol_table_frozen
)
3093 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3095 obj_symbol_new_hook (symbolP
);
3097 #ifdef tc_symbol_new_hook
3098 tc_symbol_new_hook (symbolP
);
3102 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3103 #endif /* DEBUG_SYMS */
3108 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3111 literal_pool
* pool
;
3114 pool
= find_literal_pool ();
3116 || pool
->symbol
== NULL
3117 || pool
->next_free_entry
== 0)
3120 mapping_state (MAP_DATA
);
3122 /* Align pool as you have word accesses.
3123 Only make a frag if we have to. */
3125 frag_align (2, 0, 0);
3127 record_alignment (now_seg
, 2);
3129 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3131 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3132 (valueT
) frag_now_fix (), frag_now
);
3133 symbol_table_insert (pool
->symbol
);
3135 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3137 #if defined OBJ_COFF || defined OBJ_ELF
3138 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3141 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3142 /* First output the expression in the instruction to the pool. */
3143 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3145 /* Mark the pool as empty. */
3146 pool
->next_free_entry
= 0;
3147 pool
->symbol
= NULL
;
3151 /* Forward declarations for functions below, in the MD interface
3153 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3154 static valueT
create_unwind_entry (int);
3155 static void start_unwind_section (const segT
, int);
3156 static void add_unwind_opcode (valueT
, int);
3157 static void flush_pending_unwind (void);
3159 /* Directives: Data. */
3162 s_arm_elf_cons (int nbytes
)
3166 #ifdef md_flush_pending_output
3167 md_flush_pending_output ();
3170 if (is_it_end_of_statement ())
3172 demand_empty_rest_of_line ();
3176 #ifdef md_cons_align
3177 md_cons_align (nbytes
);
3180 mapping_state (MAP_DATA
);
3184 char *base
= input_line_pointer
;
3188 if (exp
.X_op
!= O_symbol
)
3189 emit_expr (&exp
, (unsigned int) nbytes
);
3192 char *before_reloc
= input_line_pointer
;
3193 reloc
= parse_reloc (&input_line_pointer
);
3196 as_bad (_("unrecognized relocation suffix"));
3197 ignore_rest_of_line ();
3200 else if (reloc
== BFD_RELOC_UNUSED
)
3201 emit_expr (&exp
, (unsigned int) nbytes
);
3204 reloc_howto_type
*howto
= (reloc_howto_type
*)
3205 bfd_reloc_type_lookup (stdoutput
,
3206 (bfd_reloc_code_real_type
) reloc
);
3207 int size
= bfd_get_reloc_size (howto
);
3209 if (reloc
== BFD_RELOC_ARM_PLT32
)
3211 as_bad (_("(plt) is only valid on branch targets"));
3212 reloc
= BFD_RELOC_UNUSED
;
3217 as_bad (_("%s relocations do not fit in %d bytes"),
3218 howto
->name
, nbytes
);
3221 /* We've parsed an expression stopping at O_symbol.
3222 But there may be more expression left now that we
3223 have parsed the relocation marker. Parse it again.
3224 XXX Surely there is a cleaner way to do this. */
3225 char *p
= input_line_pointer
;
3227 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3228 memcpy (save_buf
, base
, input_line_pointer
- base
);
3229 memmove (base
+ (input_line_pointer
- before_reloc
),
3230 base
, before_reloc
- base
);
3232 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3234 memcpy (base
, save_buf
, p
- base
);
3236 offset
= nbytes
- size
;
3237 p
= frag_more ((int) nbytes
);
3238 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3239 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3244 while (*input_line_pointer
++ == ',');
3246 /* Put terminator back into stream. */
3247 input_line_pointer
--;
3248 demand_empty_rest_of_line ();
3251 /* Emit an expression containing a 32-bit thumb instruction.
3252 Implementation based on put_thumb32_insn. */
3255 emit_thumb32_expr (expressionS
* exp
)
3257 expressionS exp_high
= *exp
;
3259 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3260 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3261 exp
->X_add_number
&= 0xffff;
3262 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3265 /* Guess the instruction size based on the opcode. */
3268 thumb_insn_size (int opcode
)
3270 if ((unsigned int) opcode
< 0xe800u
)
3272 else if ((unsigned int) opcode
>= 0xe8000000u
)
3279 emit_insn (expressionS
*exp
, int nbytes
)
3283 if (exp
->X_op
== O_constant
)
3288 size
= thumb_insn_size (exp
->X_add_number
);
3292 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3294 as_bad (_(".inst.n operand too big. "\
3295 "Use .inst.w instead"));
3300 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3301 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3303 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3305 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3306 emit_thumb32_expr (exp
);
3308 emit_expr (exp
, (unsigned int) size
);
3310 it_fsm_post_encode ();
3314 as_bad (_("cannot determine Thumb instruction size. " \
3315 "Use .inst.n/.inst.w instead"));
3318 as_bad (_("constant expression required"));
3323 /* Like s_arm_elf_cons but do not use md_cons_align and
3324 set the mapping state to MAP_ARM/MAP_THUMB. */
3327 s_arm_elf_inst (int nbytes
)
3329 if (is_it_end_of_statement ())
3331 demand_empty_rest_of_line ();
3335 /* Calling mapping_state () here will not change ARM/THUMB,
3336 but will ensure not to be in DATA state. */
3339 mapping_state (MAP_THUMB
);
3344 as_bad (_("width suffixes are invalid in ARM mode"));
3345 ignore_rest_of_line ();
3351 mapping_state (MAP_ARM
);
3360 if (! emit_insn (& exp
, nbytes
))
3362 ignore_rest_of_line ();
3366 while (*input_line_pointer
++ == ',');
3368 /* Put terminator back into stream. */
3369 input_line_pointer
--;
3370 demand_empty_rest_of_line ();
3373 /* Parse a .rel31 directive. */
3376 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3383 if (*input_line_pointer
== '1')
3384 highbit
= 0x80000000;
3385 else if (*input_line_pointer
!= '0')
3386 as_bad (_("expected 0 or 1"));
3388 input_line_pointer
++;
3389 if (*input_line_pointer
!= ',')
3390 as_bad (_("missing comma"));
3391 input_line_pointer
++;
3393 #ifdef md_flush_pending_output
3394 md_flush_pending_output ();
3397 #ifdef md_cons_align
3401 mapping_state (MAP_DATA
);
3406 md_number_to_chars (p
, highbit
, 4);
3407 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3408 BFD_RELOC_ARM_PREL31
);
3410 demand_empty_rest_of_line ();
3413 /* Directives: AEABI stack-unwind tables. */
3415 /* Parse an unwind_fnstart directive. Simply records the current location. */
3418 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3420 demand_empty_rest_of_line ();
3421 if (unwind
.proc_start
)
3423 as_bad (_("duplicate .fnstart directive"));
3427 /* Mark the start of the function. */
3428 unwind
.proc_start
= expr_build_dot ();
3430 /* Reset the rest of the unwind info. */
3431 unwind
.opcode_count
= 0;
3432 unwind
.table_entry
= NULL
;
3433 unwind
.personality_routine
= NULL
;
3434 unwind
.personality_index
= -1;
3435 unwind
.frame_size
= 0;
3436 unwind
.fp_offset
= 0;
3437 unwind
.fp_reg
= REG_SP
;
3439 unwind
.sp_restored
= 0;
3443 /* Parse a handlerdata directive. Creates the exception handling table entry
3444 for the function. */
3447 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3449 demand_empty_rest_of_line ();
3450 if (!unwind
.proc_start
)
3451 as_bad (MISSING_FNSTART
);
3453 if (unwind
.table_entry
)
3454 as_bad (_("duplicate .handlerdata directive"));
3456 create_unwind_entry (1);
3459 /* Parse an unwind_fnend directive. Generates the index table entry. */
3462 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3467 unsigned int marked_pr_dependency
;
3469 demand_empty_rest_of_line ();
3471 if (!unwind
.proc_start
)
3473 as_bad (_(".fnend directive without .fnstart"));
3477 /* Add eh table entry. */
3478 if (unwind
.table_entry
== NULL
)
3479 val
= create_unwind_entry (0);
3483 /* Add index table entry. This is two words. */
3484 start_unwind_section (unwind
.saved_seg
, 1);
3485 frag_align (2, 0, 0);
3486 record_alignment (now_seg
, 2);
3488 ptr
= frag_more (8);
3489 where
= frag_now_fix () - 8;
3491 /* Self relative offset of the function start. */
3492 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3493 BFD_RELOC_ARM_PREL31
);
3495 /* Indicate dependency on EHABI-defined personality routines to the
3496 linker, if it hasn't been done already. */
3497 marked_pr_dependency
3498 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3499 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3500 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3502 static const char *const name
[] =
3504 "__aeabi_unwind_cpp_pr0",
3505 "__aeabi_unwind_cpp_pr1",
3506 "__aeabi_unwind_cpp_pr2"
3508 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3509 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3510 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3511 |= 1 << unwind
.personality_index
;
3515 /* Inline exception table entry. */
3516 md_number_to_chars (ptr
+ 4, val
, 4);
3518 /* Self relative offset of the table entry. */
3519 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3520 BFD_RELOC_ARM_PREL31
);
3522 /* Restore the original section. */
3523 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3525 unwind
.proc_start
= NULL
;
3529 /* Parse an unwind_cantunwind directive. */
3532 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3534 demand_empty_rest_of_line ();
3535 if (!unwind
.proc_start
)
3536 as_bad (MISSING_FNSTART
);
3538 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3539 as_bad (_("personality routine specified for cantunwind frame"));
3541 unwind
.personality_index
= -2;
3545 /* Parse a personalityindex directive. */
3548 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3552 if (!unwind
.proc_start
)
3553 as_bad (MISSING_FNSTART
);
3555 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3556 as_bad (_("duplicate .personalityindex directive"));
3560 if (exp
.X_op
!= O_constant
3561 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3563 as_bad (_("bad personality routine number"));
3564 ignore_rest_of_line ();
3568 unwind
.personality_index
= exp
.X_add_number
;
3570 demand_empty_rest_of_line ();
3574 /* Parse a personality directive. */
3577 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3581 if (!unwind
.proc_start
)
3582 as_bad (MISSING_FNSTART
);
3584 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3585 as_bad (_("duplicate .personality directive"));
3587 name
= input_line_pointer
;
3588 c
= get_symbol_end ();
3589 p
= input_line_pointer
;
3590 unwind
.personality_routine
= symbol_find_or_make (name
);
3592 demand_empty_rest_of_line ();
3596 /* Parse a directive saving core registers. */
3599 s_arm_unwind_save_core (void)
3605 range
= parse_reg_list (&input_line_pointer
);
3608 as_bad (_("expected register list"));
3609 ignore_rest_of_line ();
3613 demand_empty_rest_of_line ();
3615 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3616 into .unwind_save {..., sp...}. We aren't bothered about the value of
3617 ip because it is clobbered by calls. */
3618 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3619 && (range
& 0x3000) == 0x1000)
3621 unwind
.opcode_count
--;
3622 unwind
.sp_restored
= 0;
3623 range
= (range
| 0x2000) & ~0x1000;
3624 unwind
.pending_offset
= 0;
3630 /* See if we can use the short opcodes. These pop a block of up to 8
3631 registers starting with r4, plus maybe r14. */
3632 for (n
= 0; n
< 8; n
++)
3634 /* Break at the first non-saved register. */
3635 if ((range
& (1 << (n
+ 4))) == 0)
3638 /* See if there are any other bits set. */
3639 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3641 /* Use the long form. */
3642 op
= 0x8000 | ((range
>> 4) & 0xfff);
3643 add_unwind_opcode (op
, 2);
3647 /* Use the short form. */
3649 op
= 0xa8; /* Pop r14. */
3651 op
= 0xa0; /* Do not pop r14. */
3653 add_unwind_opcode (op
, 1);
3660 op
= 0xb100 | (range
& 0xf);
3661 add_unwind_opcode (op
, 2);
3664 /* Record the number of bytes pushed. */
3665 for (n
= 0; n
< 16; n
++)
3667 if (range
& (1 << n
))
3668 unwind
.frame_size
+= 4;
3673 /* Parse a directive saving FPA registers. */
3676 s_arm_unwind_save_fpa (int reg
)
3682 /* Get Number of registers to transfer. */
3683 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3686 exp
.X_op
= O_illegal
;
3688 if (exp
.X_op
!= O_constant
)
3690 as_bad (_("expected , <constant>"));
3691 ignore_rest_of_line ();
3695 num_regs
= exp
.X_add_number
;
3697 if (num_regs
< 1 || num_regs
> 4)
3699 as_bad (_("number of registers must be in the range [1:4]"));
3700 ignore_rest_of_line ();
3704 demand_empty_rest_of_line ();
3709 op
= 0xb4 | (num_regs
- 1);
3710 add_unwind_opcode (op
, 1);
3715 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3716 add_unwind_opcode (op
, 2);
3718 unwind
.frame_size
+= num_regs
* 12;
3722 /* Parse a directive saving VFP registers for ARMv6 and above. */
3725 s_arm_unwind_save_vfp_armv6 (void)
3730 int num_vfpv3_regs
= 0;
3731 int num_regs_below_16
;
3733 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3736 as_bad (_("expected register list"));
3737 ignore_rest_of_line ();
3741 demand_empty_rest_of_line ();
3743 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3744 than FSTMX/FLDMX-style ones). */
3746 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3748 num_vfpv3_regs
= count
;
3749 else if (start
+ count
> 16)
3750 num_vfpv3_regs
= start
+ count
- 16;
3752 if (num_vfpv3_regs
> 0)
3754 int start_offset
= start
> 16 ? start
- 16 : 0;
3755 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3756 add_unwind_opcode (op
, 2);
3759 /* Generate opcode for registers numbered in the range 0 .. 15. */
3760 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3761 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3762 if (num_regs_below_16
> 0)
3764 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3765 add_unwind_opcode (op
, 2);
3768 unwind
.frame_size
+= count
* 8;
3772 /* Parse a directive saving VFP registers for pre-ARMv6. */
3775 s_arm_unwind_save_vfp (void)
3781 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3784 as_bad (_("expected register list"));
3785 ignore_rest_of_line ();
3789 demand_empty_rest_of_line ();
3794 op
= 0xb8 | (count
- 1);
3795 add_unwind_opcode (op
, 1);
3800 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3801 add_unwind_opcode (op
, 2);
3803 unwind
.frame_size
+= count
* 8 + 4;
3807 /* Parse a directive saving iWMMXt data registers. */
3810 s_arm_unwind_save_mmxwr (void)
3818 if (*input_line_pointer
== '{')
3819 input_line_pointer
++;
3823 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3827 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3832 as_tsktsk (_("register list not in ascending order"));
3835 if (*input_line_pointer
== '-')
3837 input_line_pointer
++;
3838 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3841 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3844 else if (reg
>= hi_reg
)
3846 as_bad (_("bad register range"));
3849 for (; reg
< hi_reg
; reg
++)
3853 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3855 if (*input_line_pointer
== '}')
3856 input_line_pointer
++;
3858 demand_empty_rest_of_line ();
3860 /* Generate any deferred opcodes because we're going to be looking at
3862 flush_pending_unwind ();
3864 for (i
= 0; i
< 16; i
++)
3866 if (mask
& (1 << i
))
3867 unwind
.frame_size
+= 8;
3870 /* Attempt to combine with a previous opcode. We do this because gcc
3871 likes to output separate unwind directives for a single block of
3873 if (unwind
.opcode_count
> 0)
3875 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3876 if ((i
& 0xf8) == 0xc0)
3879 /* Only merge if the blocks are contiguous. */
3882 if ((mask
& 0xfe00) == (1 << 9))
3884 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3885 unwind
.opcode_count
--;
3888 else if (i
== 6 && unwind
.opcode_count
>= 2)
3890 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3894 op
= 0xffff << (reg
- 1);
3896 && ((mask
& op
) == (1u << (reg
- 1))))
3898 op
= (1 << (reg
+ i
+ 1)) - 1;
3899 op
&= ~((1 << reg
) - 1);
3901 unwind
.opcode_count
-= 2;
3908 /* We want to generate opcodes in the order the registers have been
3909 saved, ie. descending order. */
3910 for (reg
= 15; reg
>= -1; reg
--)
3912 /* Save registers in blocks. */
3914 || !(mask
& (1 << reg
)))
3916 /* We found an unsaved reg. Generate opcodes to save the
3923 op
= 0xc0 | (hi_reg
- 10);
3924 add_unwind_opcode (op
, 1);
3929 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3930 add_unwind_opcode (op
, 2);
3939 ignore_rest_of_line ();
3943 s_arm_unwind_save_mmxwcg (void)
3950 if (*input_line_pointer
== '{')
3951 input_line_pointer
++;
3955 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3959 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3965 as_tsktsk (_("register list not in ascending order"));
3968 if (*input_line_pointer
== '-')
3970 input_line_pointer
++;
3971 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3974 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3977 else if (reg
>= hi_reg
)
3979 as_bad (_("bad register range"));
3982 for (; reg
< hi_reg
; reg
++)
3986 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3988 if (*input_line_pointer
== '}')
3989 input_line_pointer
++;
3991 demand_empty_rest_of_line ();
3993 /* Generate any deferred opcodes because we're going to be looking at
3995 flush_pending_unwind ();
3997 for (reg
= 0; reg
< 16; reg
++)
3999 if (mask
& (1 << reg
))
4000 unwind
.frame_size
+= 4;
4003 add_unwind_opcode (op
, 2);
4006 ignore_rest_of_line ();
4010 /* Parse an unwind_save directive.
4011 If the argument is non-zero, this is a .vsave directive. */
4014 s_arm_unwind_save (int arch_v6
)
4017 struct reg_entry
*reg
;
4018 bfd_boolean had_brace
= FALSE
;
4020 if (!unwind
.proc_start
)
4021 as_bad (MISSING_FNSTART
);
4023 /* Figure out what sort of save we have. */
4024 peek
= input_line_pointer
;
4032 reg
= arm_reg_parse_multi (&peek
);
4036 as_bad (_("register expected"));
4037 ignore_rest_of_line ();
4046 as_bad (_("FPA .unwind_save does not take a register list"));
4047 ignore_rest_of_line ();
4050 input_line_pointer
= peek
;
4051 s_arm_unwind_save_fpa (reg
->number
);
4054 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4057 s_arm_unwind_save_vfp_armv6 ();
4059 s_arm_unwind_save_vfp ();
4061 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4062 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4065 as_bad (_(".unwind_save does not support this kind of register"));
4066 ignore_rest_of_line ();
4071 /* Parse an unwind_movsp directive. */
4074 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4080 if (!unwind
.proc_start
)
4081 as_bad (MISSING_FNSTART
);
4083 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4086 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4087 ignore_rest_of_line ();
4091 /* Optional constant. */
4092 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4094 if (immediate_for_directive (&offset
) == FAIL
)
4100 demand_empty_rest_of_line ();
4102 if (reg
== REG_SP
|| reg
== REG_PC
)
4104 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4108 if (unwind
.fp_reg
!= REG_SP
)
4109 as_bad (_("unexpected .unwind_movsp directive"));
4111 /* Generate opcode to restore the value. */
4113 add_unwind_opcode (op
, 1);
4115 /* Record the information for later. */
4116 unwind
.fp_reg
= reg
;
4117 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4118 unwind
.sp_restored
= 1;
4121 /* Parse an unwind_pad directive. */
4124 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4128 if (!unwind
.proc_start
)
4129 as_bad (MISSING_FNSTART
);
4131 if (immediate_for_directive (&offset
) == FAIL
)
4136 as_bad (_("stack increment must be multiple of 4"));
4137 ignore_rest_of_line ();
4141 /* Don't generate any opcodes, just record the details for later. */
4142 unwind
.frame_size
+= offset
;
4143 unwind
.pending_offset
+= offset
;
4145 demand_empty_rest_of_line ();
4148 /* Parse an unwind_setfp directive. */
4151 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4157 if (!unwind
.proc_start
)
4158 as_bad (MISSING_FNSTART
);
4160 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4161 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4164 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4166 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4168 as_bad (_("expected <reg>, <reg>"));
4169 ignore_rest_of_line ();
4173 /* Optional constant. */
4174 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4176 if (immediate_for_directive (&offset
) == FAIL
)
4182 demand_empty_rest_of_line ();
4184 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4186 as_bad (_("register must be either sp or set by a previous"
4187 "unwind_movsp directive"));
4191 /* Don't generate any opcodes, just record the information for later. */
4192 unwind
.fp_reg
= fp_reg
;
4194 if (sp_reg
== REG_SP
)
4195 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4197 unwind
.fp_offset
-= offset
;
4200 /* Parse an unwind_raw directive. */
4203 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4206 /* This is an arbitrary limit. */
4207 unsigned char op
[16];
4210 if (!unwind
.proc_start
)
4211 as_bad (MISSING_FNSTART
);
4214 if (exp
.X_op
== O_constant
4215 && skip_past_comma (&input_line_pointer
) != FAIL
)
4217 unwind
.frame_size
+= exp
.X_add_number
;
4221 exp
.X_op
= O_illegal
;
4223 if (exp
.X_op
!= O_constant
)
4225 as_bad (_("expected <offset>, <opcode>"));
4226 ignore_rest_of_line ();
4232 /* Parse the opcode. */
4237 as_bad (_("unwind opcode too long"));
4238 ignore_rest_of_line ();
4240 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4242 as_bad (_("invalid unwind opcode"));
4243 ignore_rest_of_line ();
4246 op
[count
++] = exp
.X_add_number
;
4248 /* Parse the next byte. */
4249 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4255 /* Add the opcode bytes in reverse order. */
4257 add_unwind_opcode (op
[count
], 1);
4259 demand_empty_rest_of_line ();
4263 /* Parse a .eabi_attribute directive. */
4266 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4268 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4270 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4271 attributes_set_explicitly
[tag
] = 1;
4273 #endif /* OBJ_ELF */
4275 static void s_arm_arch (int);
4276 static void s_arm_object_arch (int);
4277 static void s_arm_cpu (int);
4278 static void s_arm_fpu (int);
4279 static void s_arm_arch_extension (int);
4284 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4291 if (exp
.X_op
== O_symbol
)
4292 exp
.X_op
= O_secrel
;
4294 emit_expr (&exp
, 4);
4296 while (*input_line_pointer
++ == ',');
4298 input_line_pointer
--;
4299 demand_empty_rest_of_line ();
4303 /* This table describes all the machine specific pseudo-ops the assembler
4304 has to support. The fields are:
4305 pseudo-op name without dot
4306 function to call to execute this pseudo-op
4307 Integer arg to pass to the function. */
4309 const pseudo_typeS md_pseudo_table
[] =
4311 /* Never called because '.req' does not start a line. */
4312 { "req", s_req
, 0 },
4313 /* Following two are likewise never called. */
4316 { "unreq", s_unreq
, 0 },
4317 { "bss", s_bss
, 0 },
4318 { "align", s_align
, 0 },
4319 { "arm", s_arm
, 0 },
4320 { "thumb", s_thumb
, 0 },
4321 { "code", s_code
, 0 },
4322 { "force_thumb", s_force_thumb
, 0 },
4323 { "thumb_func", s_thumb_func
, 0 },
4324 { "thumb_set", s_thumb_set
, 0 },
4325 { "even", s_even
, 0 },
4326 { "ltorg", s_ltorg
, 0 },
4327 { "pool", s_ltorg
, 0 },
4328 { "syntax", s_syntax
, 0 },
4329 { "cpu", s_arm_cpu
, 0 },
4330 { "arch", s_arm_arch
, 0 },
4331 { "object_arch", s_arm_object_arch
, 0 },
4332 { "fpu", s_arm_fpu
, 0 },
4333 { "arch_extension", s_arm_arch_extension
, 0 },
4335 { "word", s_arm_elf_cons
, 4 },
4336 { "long", s_arm_elf_cons
, 4 },
4337 { "inst.n", s_arm_elf_inst
, 2 },
4338 { "inst.w", s_arm_elf_inst
, 4 },
4339 { "inst", s_arm_elf_inst
, 0 },
4340 { "rel31", s_arm_rel31
, 0 },
4341 { "fnstart", s_arm_unwind_fnstart
, 0 },
4342 { "fnend", s_arm_unwind_fnend
, 0 },
4343 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4344 { "personality", s_arm_unwind_personality
, 0 },
4345 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4346 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4347 { "save", s_arm_unwind_save
, 0 },
4348 { "vsave", s_arm_unwind_save
, 1 },
4349 { "movsp", s_arm_unwind_movsp
, 0 },
4350 { "pad", s_arm_unwind_pad
, 0 },
4351 { "setfp", s_arm_unwind_setfp
, 0 },
4352 { "unwind_raw", s_arm_unwind_raw
, 0 },
4353 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4357 /* These are used for dwarf. */
4361 /* These are used for dwarf2. */
4362 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4363 { "loc", dwarf2_directive_loc
, 0 },
4364 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4366 { "extend", float_cons
, 'x' },
4367 { "ldouble", float_cons
, 'x' },
4368 { "packed", float_cons
, 'p' },
4370 {"secrel32", pe_directive_secrel
, 0},
4375 /* Parser functions used exclusively in instruction operands. */
4377 /* Generic immediate-value read function for use in insn parsing.
4378 STR points to the beginning of the immediate (the leading #);
4379 VAL receives the value; if the value is outside [MIN, MAX]
4380 issue an error. PREFIX_OPT is true if the immediate prefix is
4384 parse_immediate (char **str
, int *val
, int min
, int max
,
4385 bfd_boolean prefix_opt
)
4388 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4389 if (exp
.X_op
!= O_constant
)
4391 inst
.error
= _("constant expression required");
4395 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4397 inst
.error
= _("immediate value out of range");
4401 *val
= exp
.X_add_number
;
4405 /* Less-generic immediate-value read function with the possibility of loading a
4406 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4407 instructions. Puts the result directly in inst.operands[i]. */
4410 parse_big_immediate (char **str
, int i
)
4415 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4417 if (exp
.X_op
== O_constant
)
4419 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4420 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4421 O_constant. We have to be careful not to break compilation for
4422 32-bit X_add_number, though. */
4423 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4425 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4426 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4427 inst
.operands
[i
].regisimm
= 1;
4430 else if (exp
.X_op
== O_big
4431 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4433 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4435 /* Bignums have their least significant bits in
4436 generic_bignum[0]. Make sure we put 32 bits in imm and
4437 32 bits in reg, in a (hopefully) portable way. */
4438 gas_assert (parts
!= 0);
4440 /* Make sure that the number is not too big.
4441 PR 11972: Bignums can now be sign-extended to the
4442 size of a .octa so check that the out of range bits
4443 are all zero or all one. */
4444 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4446 LITTLENUM_TYPE m
= -1;
4448 if (generic_bignum
[parts
* 2] != 0
4449 && generic_bignum
[parts
* 2] != m
)
4452 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4453 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4457 inst
.operands
[i
].imm
= 0;
4458 for (j
= 0; j
< parts
; j
++, idx
++)
4459 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4460 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4461 inst
.operands
[i
].reg
= 0;
4462 for (j
= 0; j
< parts
; j
++, idx
++)
4463 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4464 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4465 inst
.operands
[i
].regisimm
= 1;
4475 /* Returns the pseudo-register number of an FPA immediate constant,
4476 or FAIL if there isn't a valid constant here. */
4479 parse_fpa_immediate (char ** str
)
4481 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4487 /* First try and match exact strings, this is to guarantee
4488 that some formats will work even for cross assembly. */
4490 for (i
= 0; fp_const
[i
]; i
++)
4492 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4496 *str
+= strlen (fp_const
[i
]);
4497 if (is_end_of_line
[(unsigned char) **str
])
4503 /* Just because we didn't get a match doesn't mean that the constant
4504 isn't valid, just that it is in a format that we don't
4505 automatically recognize. Try parsing it with the standard
4506 expression routines. */
4508 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4510 /* Look for a raw floating point number. */
4511 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4512 && is_end_of_line
[(unsigned char) *save_in
])
4514 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4516 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4518 if (words
[j
] != fp_values
[i
][j
])
4522 if (j
== MAX_LITTLENUMS
)
4530 /* Try and parse a more complex expression, this will probably fail
4531 unless the code uses a floating point prefix (eg "0f"). */
4532 save_in
= input_line_pointer
;
4533 input_line_pointer
= *str
;
4534 if (expression (&exp
) == absolute_section
4535 && exp
.X_op
== O_big
4536 && exp
.X_add_number
< 0)
4538 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4540 if (gen_to_words (words
, 5, (long) 15) == 0)
4542 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4544 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4546 if (words
[j
] != fp_values
[i
][j
])
4550 if (j
== MAX_LITTLENUMS
)
4552 *str
= input_line_pointer
;
4553 input_line_pointer
= save_in
;
4560 *str
= input_line_pointer
;
4561 input_line_pointer
= save_in
;
4562 inst
.error
= _("invalid FPA immediate expression");
4566 /* Returns 1 if a number has "quarter-precision" float format
4567 0baBbbbbbc defgh000 00000000 00000000. */
4570 is_quarter_float (unsigned imm
)
4572 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4573 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4576 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4577 0baBbbbbbc defgh000 00000000 00000000.
4578 The zero and minus-zero cases need special handling, since they can't be
4579 encoded in the "quarter-precision" float format, but can nonetheless be
4580 loaded as integer constants. */
4583 parse_qfloat_immediate (char **ccp
, int *immed
)
4587 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4588 int found_fpchar
= 0;
4590 skip_past_char (&str
, '#');
4592 /* We must not accidentally parse an integer as a floating-point number. Make
4593 sure that the value we parse is not an integer by checking for special
4594 characters '.' or 'e'.
4595 FIXME: This is a horrible hack, but doing better is tricky because type
4596 information isn't in a very usable state at parse time. */
4598 skip_whitespace (fpnum
);
4600 if (strncmp (fpnum
, "0x", 2) == 0)
4604 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4605 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4615 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4617 unsigned fpword
= 0;
4620 /* Our FP word must be 32 bits (single-precision FP). */
4621 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4623 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4627 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4640 /* Shift operands. */
4643 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4646 struct asm_shift_name
4649 enum shift_kind kind
;
4652 /* Third argument to parse_shift. */
4653 enum parse_shift_mode
4655 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4656 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4657 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4658 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4659 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4662 /* Parse a <shift> specifier on an ARM data processing instruction.
4663 This has three forms:
4665 (LSL|LSR|ASL|ASR|ROR) Rs
4666 (LSL|LSR|ASL|ASR|ROR) #imm
4669 Note that ASL is assimilated to LSL in the instruction encoding, and
4670 RRX to ROR #0 (which cannot be written as such). */
4673 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4675 const struct asm_shift_name
*shift_name
;
4676 enum shift_kind shift
;
4681 for (p
= *str
; ISALPHA (*p
); p
++)
4686 inst
.error
= _("shift expression expected");
4690 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4693 if (shift_name
== NULL
)
4695 inst
.error
= _("shift expression expected");
4699 shift
= shift_name
->kind
;
4703 case NO_SHIFT_RESTRICT
:
4704 case SHIFT_IMMEDIATE
: break;
4706 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4707 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4709 inst
.error
= _("'LSL' or 'ASR' required");
4714 case SHIFT_LSL_IMMEDIATE
:
4715 if (shift
!= SHIFT_LSL
)
4717 inst
.error
= _("'LSL' required");
4722 case SHIFT_ASR_IMMEDIATE
:
4723 if (shift
!= SHIFT_ASR
)
4725 inst
.error
= _("'ASR' required");
4733 if (shift
!= SHIFT_RRX
)
4735 /* Whitespace can appear here if the next thing is a bare digit. */
4736 skip_whitespace (p
);
4738 if (mode
== NO_SHIFT_RESTRICT
4739 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4741 inst
.operands
[i
].imm
= reg
;
4742 inst
.operands
[i
].immisreg
= 1;
4744 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4747 inst
.operands
[i
].shift_kind
= shift
;
4748 inst
.operands
[i
].shifted
= 1;
4753 /* Parse a <shifter_operand> for an ARM data processing instruction:
4756 #<immediate>, <rotate>
4760 where <shift> is defined by parse_shift above, and <rotate> is a
4761 multiple of 2 between 0 and 30. Validation of immediate operands
4762 is deferred to md_apply_fix. */
4765 parse_shifter_operand (char **str
, int i
)
4770 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4772 inst
.operands
[i
].reg
= value
;
4773 inst
.operands
[i
].isreg
= 1;
4775 /* parse_shift will override this if appropriate */
4776 inst
.reloc
.exp
.X_op
= O_constant
;
4777 inst
.reloc
.exp
.X_add_number
= 0;
4779 if (skip_past_comma (str
) == FAIL
)
4782 /* Shift operation on register. */
4783 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4786 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4789 if (skip_past_comma (str
) == SUCCESS
)
4791 /* #x, y -- ie explicit rotation by Y. */
4792 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4795 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4797 inst
.error
= _("constant expression expected");
4801 value
= exp
.X_add_number
;
4802 if (value
< 0 || value
> 30 || value
% 2 != 0)
4804 inst
.error
= _("invalid rotation");
4807 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4809 inst
.error
= _("invalid constant");
4813 /* Convert to decoded value. md_apply_fix will put it back. */
4814 inst
.reloc
.exp
.X_add_number
4815 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4816 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4819 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4820 inst
.reloc
.pc_rel
= 0;
4824 /* Group relocation information. Each entry in the table contains the
4825 textual name of the relocation as may appear in assembler source
4826 and must end with a colon.
4827 Along with this textual name are the relocation codes to be used if
4828 the corresponding instruction is an ALU instruction (ADD or SUB only),
4829 an LDR, an LDRS, or an LDC. */
4831 struct group_reloc_table_entry
4842 /* Varieties of non-ALU group relocation. */
4849 static struct group_reloc_table_entry group_reloc_table
[] =
4850 { /* Program counter relative: */
4852 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4857 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4858 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4859 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4860 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4862 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4867 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4868 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4869 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4870 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4872 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4873 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4874 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4875 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4876 /* Section base relative */
4878 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4883 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4884 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4885 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4886 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4888 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4893 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4894 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4895 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4896 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4898 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4899 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4900 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4901 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4903 /* Given the address of a pointer pointing to the textual name of a group
4904 relocation as may appear in assembler source, attempt to find its details
4905 in group_reloc_table. The pointer will be updated to the character after
4906 the trailing colon. On failure, FAIL will be returned; SUCCESS
4907 otherwise. On success, *entry will be updated to point at the relevant
4908 group_reloc_table entry. */
4911 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4914 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4916 int length
= strlen (group_reloc_table
[i
].name
);
4918 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4919 && (*str
)[length
] == ':')
4921 *out
= &group_reloc_table
[i
];
4922 *str
+= (length
+ 1);
4930 /* Parse a <shifter_operand> for an ARM data processing instruction
4931 (as for parse_shifter_operand) where group relocations are allowed:
4934 #<immediate>, <rotate>
4935 #:<group_reloc>:<expression>
4939 where <group_reloc> is one of the strings defined in group_reloc_table.
4940 The hashes are optional.
4942 Everything else is as for parse_shifter_operand. */
4944 static parse_operand_result
4945 parse_shifter_operand_group_reloc (char **str
, int i
)
4947 /* Determine if we have the sequence of characters #: or just :
4948 coming next. If we do, then we check for a group relocation.
4949 If we don't, punt the whole lot to parse_shifter_operand. */
4951 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4952 || (*str
)[0] == ':')
4954 struct group_reloc_table_entry
*entry
;
4956 if ((*str
)[0] == '#')
4961 /* Try to parse a group relocation. Anything else is an error. */
4962 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4964 inst
.error
= _("unknown group relocation");
4965 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4968 /* We now have the group relocation table entry corresponding to
4969 the name in the assembler source. Next, we parse the expression. */
4970 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4971 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4973 /* Record the relocation type (always the ALU variant here). */
4974 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4975 gas_assert (inst
.reloc
.type
!= 0);
4977 return PARSE_OPERAND_SUCCESS
;
4980 return parse_shifter_operand (str
, i
) == SUCCESS
4981 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4983 /* Never reached. */
4986 /* Parse a Neon alignment expression. Information is written to
4987 inst.operands[i]. We assume the initial ':' has been skipped.
4989 align .imm = align << 8, .immisalign=1, .preind=0 */
4990 static parse_operand_result
4991 parse_neon_alignment (char **str
, int i
)
4996 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4998 if (exp
.X_op
!= O_constant
)
5000 inst
.error
= _("alignment must be constant");
5001 return PARSE_OPERAND_FAIL
;
5004 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5005 inst
.operands
[i
].immisalign
= 1;
5006 /* Alignments are not pre-indexes. */
5007 inst
.operands
[i
].preind
= 0;
5010 return PARSE_OPERAND_SUCCESS
;
5013 /* Parse all forms of an ARM address expression. Information is written
5014 to inst.operands[i] and/or inst.reloc.
5016 Preindexed addressing (.preind=1):
5018 [Rn, #offset] .reg=Rn .reloc.exp=offset
5019 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5020 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5021 .shift_kind=shift .reloc.exp=shift_imm
5023 These three may have a trailing ! which causes .writeback to be set also.
5025 Postindexed addressing (.postind=1, .writeback=1):
5027 [Rn], #offset .reg=Rn .reloc.exp=offset
5028 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5029 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5030 .shift_kind=shift .reloc.exp=shift_imm
5032 Unindexed addressing (.preind=0, .postind=0):
5034 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5038 [Rn]{!} shorthand for [Rn,#0]{!}
5039 =immediate .isreg=0 .reloc.exp=immediate
5040 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5042 It is the caller's responsibility to check for addressing modes not
5043 supported by the instruction, and to set inst.reloc.type. */
5045 static parse_operand_result
5046 parse_address_main (char **str
, int i
, int group_relocations
,
5047 group_reloc_type group_type
)
5052 if (skip_past_char (&p
, '[') == FAIL
)
5054 if (skip_past_char (&p
, '=') == FAIL
)
5056 /* Bare address - translate to PC-relative offset. */
5057 inst
.reloc
.pc_rel
= 1;
5058 inst
.operands
[i
].reg
= REG_PC
;
5059 inst
.operands
[i
].isreg
= 1;
5060 inst
.operands
[i
].preind
= 1;
5062 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5064 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5065 return PARSE_OPERAND_FAIL
;
5068 return PARSE_OPERAND_SUCCESS
;
5071 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5073 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5074 return PARSE_OPERAND_FAIL
;
5076 inst
.operands
[i
].reg
= reg
;
5077 inst
.operands
[i
].isreg
= 1;
5079 if (skip_past_comma (&p
) == SUCCESS
)
5081 inst
.operands
[i
].preind
= 1;
5084 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5086 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5088 inst
.operands
[i
].imm
= reg
;
5089 inst
.operands
[i
].immisreg
= 1;
5091 if (skip_past_comma (&p
) == SUCCESS
)
5092 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5093 return PARSE_OPERAND_FAIL
;
5095 else if (skip_past_char (&p
, ':') == SUCCESS
)
5097 /* FIXME: '@' should be used here, but it's filtered out by generic
5098 code before we get to see it here. This may be subject to
5100 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5102 if (result
!= PARSE_OPERAND_SUCCESS
)
5107 if (inst
.operands
[i
].negative
)
5109 inst
.operands
[i
].negative
= 0;
5113 if (group_relocations
5114 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5116 struct group_reloc_table_entry
*entry
;
5118 /* Skip over the #: or : sequence. */
5124 /* Try to parse a group relocation. Anything else is an
5126 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5128 inst
.error
= _("unknown group relocation");
5129 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5132 /* We now have the group relocation table entry corresponding to
5133 the name in the assembler source. Next, we parse the
5135 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5136 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5138 /* Record the relocation type. */
5142 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5146 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5150 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5157 if (inst
.reloc
.type
== 0)
5159 inst
.error
= _("this group relocation is not allowed on this instruction");
5160 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5164 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5165 return PARSE_OPERAND_FAIL
;
5168 else if (skip_past_char (&p
, ':') == SUCCESS
)
5170 /* FIXME: '@' should be used here, but it's filtered out by generic code
5171 before we get to see it here. This may be subject to change. */
5172 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5174 if (result
!= PARSE_OPERAND_SUCCESS
)
5178 if (skip_past_char (&p
, ']') == FAIL
)
5180 inst
.error
= _("']' expected");
5181 return PARSE_OPERAND_FAIL
;
5184 if (skip_past_char (&p
, '!') == SUCCESS
)
5185 inst
.operands
[i
].writeback
= 1;
5187 else if (skip_past_comma (&p
) == SUCCESS
)
5189 if (skip_past_char (&p
, '{') == SUCCESS
)
5191 /* [Rn], {expr} - unindexed, with option */
5192 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5193 0, 255, TRUE
) == FAIL
)
5194 return PARSE_OPERAND_FAIL
;
5196 if (skip_past_char (&p
, '}') == FAIL
)
5198 inst
.error
= _("'}' expected at end of 'option' field");
5199 return PARSE_OPERAND_FAIL
;
5201 if (inst
.operands
[i
].preind
)
5203 inst
.error
= _("cannot combine index with option");
5204 return PARSE_OPERAND_FAIL
;
5207 return PARSE_OPERAND_SUCCESS
;
5211 inst
.operands
[i
].postind
= 1;
5212 inst
.operands
[i
].writeback
= 1;
5214 if (inst
.operands
[i
].preind
)
5216 inst
.error
= _("cannot combine pre- and post-indexing");
5217 return PARSE_OPERAND_FAIL
;
5221 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5223 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5225 /* We might be using the immediate for alignment already. If we
5226 are, OR the register number into the low-order bits. */
5227 if (inst
.operands
[i
].immisalign
)
5228 inst
.operands
[i
].imm
|= reg
;
5230 inst
.operands
[i
].imm
= reg
;
5231 inst
.operands
[i
].immisreg
= 1;
5233 if (skip_past_comma (&p
) == SUCCESS
)
5234 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5235 return PARSE_OPERAND_FAIL
;
5239 if (inst
.operands
[i
].negative
)
5241 inst
.operands
[i
].negative
= 0;
5244 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5245 return PARSE_OPERAND_FAIL
;
5250 /* If at this point neither .preind nor .postind is set, we have a
5251 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5252 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5254 inst
.operands
[i
].preind
= 1;
5255 inst
.reloc
.exp
.X_op
= O_constant
;
5256 inst
.reloc
.exp
.X_add_number
= 0;
5259 return PARSE_OPERAND_SUCCESS
;
5263 parse_address (char **str
, int i
)
5265 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5269 static parse_operand_result
5270 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5272 return parse_address_main (str
, i
, 1, type
);
5275 /* Parse an operand for a MOVW or MOVT instruction. */
5277 parse_half (char **str
)
5282 skip_past_char (&p
, '#');
5283 if (strncasecmp (p
, ":lower16:", 9) == 0)
5284 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5285 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5286 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5288 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5291 skip_whitespace (p
);
5294 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5297 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5299 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5301 inst
.error
= _("constant expression expected");
5304 if (inst
.reloc
.exp
.X_add_number
< 0
5305 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5307 inst
.error
= _("immediate value out of range");
5315 /* Miscellaneous. */
5317 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5318 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5320 parse_psr (char **str
)
5323 unsigned long psr_field
;
5324 const struct asm_psr
*psr
;
5327 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5328 feature for ease of use and backwards compatibility. */
5330 if (strncasecmp (p
, "SPSR", 4) == 0)
5331 psr_field
= SPSR_BIT
;
5332 else if (strncasecmp (p
, "CPSR", 4) == 0
5333 || (strncasecmp (p
, "APSR", 4) == 0
5334 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
)))
5341 while (ISALNUM (*p
) || *p
== '_');
5343 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5355 /* A suffix follows. */
5361 while (ISALNUM (*p
) || *p
== '_');
5363 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5368 psr_field
|= psr
->field
;
5373 goto error
; /* Garbage after "[CS]PSR". */
5375 psr_field
|= (PSR_c
| PSR_f
);
5381 inst
.error
= _("flag for {c}psr instruction expected");
5385 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5386 value suitable for splatting into the AIF field of the instruction. */
5389 parse_cps_flags (char **str
)
5398 case '\0': case ',':
5401 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5402 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5403 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5406 inst
.error
= _("unrecognized CPS flag");
5411 if (saw_a_flag
== 0)
5413 inst
.error
= _("missing CPS flags");
5421 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5422 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5425 parse_endian_specifier (char **str
)
5430 if (strncasecmp (s
, "BE", 2))
5432 else if (strncasecmp (s
, "LE", 2))
5436 inst
.error
= _("valid endian specifiers are be or le");
5440 if (ISALNUM (s
[2]) || s
[2] == '_')
5442 inst
.error
= _("valid endian specifiers are be or le");
5447 return little_endian
;
5450 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5451 value suitable for poking into the rotate field of an sxt or sxta
5452 instruction, or FAIL on error. */
5455 parse_ror (char **str
)
5460 if (strncasecmp (s
, "ROR", 3) == 0)
5464 inst
.error
= _("missing rotation field after comma");
5468 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5473 case 0: *str
= s
; return 0x0;
5474 case 8: *str
= s
; return 0x1;
5475 case 16: *str
= s
; return 0x2;
5476 case 24: *str
= s
; return 0x3;
5479 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5484 /* Parse a conditional code (from conds[] below). The value returned is in the
5485 range 0 .. 14, or FAIL. */
5487 parse_cond (char **str
)
5490 const struct asm_cond
*c
;
5492 /* Condition codes are always 2 characters, so matching up to
5493 3 characters is sufficient. */
5498 while (ISALPHA (*q
) && n
< 3)
5500 cond
[n
] = TOLOWER (*q
);
5505 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5508 inst
.error
= _("condition required");
5516 /* Parse an option for a barrier instruction. Returns the encoding for the
5519 parse_barrier (char **str
)
5522 const struct asm_barrier_opt
*o
;
5525 while (ISALPHA (*q
))
5528 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5537 /* Parse the operands of a table branch instruction. Similar to a memory
5540 parse_tb (char **str
)
5545 if (skip_past_char (&p
, '[') == FAIL
)
5547 inst
.error
= _("'[' expected");
5551 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5553 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5556 inst
.operands
[0].reg
= reg
;
5558 if (skip_past_comma (&p
) == FAIL
)
5560 inst
.error
= _("',' expected");
5564 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5566 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5569 inst
.operands
[0].imm
= reg
;
5571 if (skip_past_comma (&p
) == SUCCESS
)
5573 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5575 if (inst
.reloc
.exp
.X_add_number
!= 1)
5577 inst
.error
= _("invalid shift");
5580 inst
.operands
[0].shifted
= 1;
5583 if (skip_past_char (&p
, ']') == FAIL
)
5585 inst
.error
= _("']' expected");
5592 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5593 information on the types the operands can take and how they are encoded.
5594 Up to four operands may be read; this function handles setting the
5595 ".present" field for each read operand itself.
5596 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5597 else returns FAIL. */
5600 parse_neon_mov (char **str
, int *which_operand
)
5602 int i
= *which_operand
, val
;
5603 enum arm_reg_type rtype
;
5605 struct neon_type_el optype
;
5607 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5609 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5610 inst
.operands
[i
].reg
= val
;
5611 inst
.operands
[i
].isscalar
= 1;
5612 inst
.operands
[i
].vectype
= optype
;
5613 inst
.operands
[i
++].present
= 1;
5615 if (skip_past_comma (&ptr
) == FAIL
)
5618 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5621 inst
.operands
[i
].reg
= val
;
5622 inst
.operands
[i
].isreg
= 1;
5623 inst
.operands
[i
].present
= 1;
5625 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5628 /* Cases 0, 1, 2, 3, 5 (D only). */
5629 if (skip_past_comma (&ptr
) == FAIL
)
5632 inst
.operands
[i
].reg
= val
;
5633 inst
.operands
[i
].isreg
= 1;
5634 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5635 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5636 inst
.operands
[i
].isvec
= 1;
5637 inst
.operands
[i
].vectype
= optype
;
5638 inst
.operands
[i
++].present
= 1;
5640 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5642 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5643 Case 13: VMOV <Sd>, <Rm> */
5644 inst
.operands
[i
].reg
= val
;
5645 inst
.operands
[i
].isreg
= 1;
5646 inst
.operands
[i
].present
= 1;
5648 if (rtype
== REG_TYPE_NQ
)
5650 first_error (_("can't use Neon quad register here"));
5653 else if (rtype
!= REG_TYPE_VFS
)
5656 if (skip_past_comma (&ptr
) == FAIL
)
5658 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5660 inst
.operands
[i
].reg
= val
;
5661 inst
.operands
[i
].isreg
= 1;
5662 inst
.operands
[i
].present
= 1;
5665 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5668 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5669 Case 1: VMOV<c><q> <Dd>, <Dm>
5670 Case 8: VMOV.F32 <Sd>, <Sm>
5671 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5673 inst
.operands
[i
].reg
= val
;
5674 inst
.operands
[i
].isreg
= 1;
5675 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5676 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5677 inst
.operands
[i
].isvec
= 1;
5678 inst
.operands
[i
].vectype
= optype
;
5679 inst
.operands
[i
].present
= 1;
5681 if (skip_past_comma (&ptr
) == SUCCESS
)
5686 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5689 inst
.operands
[i
].reg
= val
;
5690 inst
.operands
[i
].isreg
= 1;
5691 inst
.operands
[i
++].present
= 1;
5693 if (skip_past_comma (&ptr
) == FAIL
)
5696 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5699 inst
.operands
[i
].reg
= val
;
5700 inst
.operands
[i
].isreg
= 1;
5701 inst
.operands
[i
++].present
= 1;
5704 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5705 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5706 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5707 Case 10: VMOV.F32 <Sd>, #<imm>
5708 Case 11: VMOV.F64 <Dd>, #<imm> */
5709 inst
.operands
[i
].immisfloat
= 1;
5710 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5711 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5712 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5716 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5720 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5723 inst
.operands
[i
].reg
= val
;
5724 inst
.operands
[i
].isreg
= 1;
5725 inst
.operands
[i
++].present
= 1;
5727 if (skip_past_comma (&ptr
) == FAIL
)
5730 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5732 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5733 inst
.operands
[i
].reg
= val
;
5734 inst
.operands
[i
].isscalar
= 1;
5735 inst
.operands
[i
].present
= 1;
5736 inst
.operands
[i
].vectype
= optype
;
5738 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5740 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5741 inst
.operands
[i
].reg
= val
;
5742 inst
.operands
[i
].isreg
= 1;
5743 inst
.operands
[i
++].present
= 1;
5745 if (skip_past_comma (&ptr
) == FAIL
)
5748 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5751 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5755 inst
.operands
[i
].reg
= val
;
5756 inst
.operands
[i
].isreg
= 1;
5757 inst
.operands
[i
].isvec
= 1;
5758 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5759 inst
.operands
[i
].vectype
= optype
;
5760 inst
.operands
[i
].present
= 1;
5762 if (rtype
== REG_TYPE_VFS
)
5766 if (skip_past_comma (&ptr
) == FAIL
)
5768 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5771 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5774 inst
.operands
[i
].reg
= val
;
5775 inst
.operands
[i
].isreg
= 1;
5776 inst
.operands
[i
].isvec
= 1;
5777 inst
.operands
[i
].issingle
= 1;
5778 inst
.operands
[i
].vectype
= optype
;
5779 inst
.operands
[i
].present
= 1;
5782 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5786 inst
.operands
[i
].reg
= val
;
5787 inst
.operands
[i
].isreg
= 1;
5788 inst
.operands
[i
].isvec
= 1;
5789 inst
.operands
[i
].issingle
= 1;
5790 inst
.operands
[i
].vectype
= optype
;
5791 inst
.operands
[i
++].present
= 1;
5796 first_error (_("parse error"));
5800 /* Successfully parsed the operands. Update args. */
5806 first_error (_("expected comma"));
5810 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5814 /* Use this macro when the operand constraints are different
5815 for ARM and THUMB (e.g. ldrd). */
5816 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5817 ((arm_operand) | ((thumb_operand) << 16))
5819 /* Matcher codes for parse_operands. */
5820 enum operand_parse_code
5822 OP_stop
, /* end of line */
5824 OP_RR
, /* ARM register */
5825 OP_RRnpc
, /* ARM register, not r15 */
5826 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5827 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5828 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5829 optional trailing ! */
5830 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5831 OP_RCP
, /* Coprocessor number */
5832 OP_RCN
, /* Coprocessor register */
5833 OP_RF
, /* FPA register */
5834 OP_RVS
, /* VFP single precision register */
5835 OP_RVD
, /* VFP double precision register (0..15) */
5836 OP_RND
, /* Neon double precision register (0..31) */
5837 OP_RNQ
, /* Neon quad precision register */
5838 OP_RVSD
, /* VFP single or double precision register */
5839 OP_RNDQ
, /* Neon double or quad precision register */
5840 OP_RNSDQ
, /* Neon single, double or quad precision register */
5841 OP_RNSC
, /* Neon scalar D[X] */
5842 OP_RVC
, /* VFP control register */
5843 OP_RMF
, /* Maverick F register */
5844 OP_RMD
, /* Maverick D register */
5845 OP_RMFX
, /* Maverick FX register */
5846 OP_RMDX
, /* Maverick DX register */
5847 OP_RMAX
, /* Maverick AX register */
5848 OP_RMDS
, /* Maverick DSPSC register */
5849 OP_RIWR
, /* iWMMXt wR register */
5850 OP_RIWC
, /* iWMMXt wC register */
5851 OP_RIWG
, /* iWMMXt wCG register */
5852 OP_RXA
, /* XScale accumulator register */
5854 OP_REGLST
, /* ARM register list */
5855 OP_VRSLST
, /* VFP single-precision register list */
5856 OP_VRDLST
, /* VFP double-precision register list */
5857 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5858 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5859 OP_NSTRLST
, /* Neon element/structure list */
5861 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5862 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5863 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5864 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5865 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5866 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5867 OP_VMOV
, /* Neon VMOV operands. */
5868 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5869 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5870 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5872 OP_I0
, /* immediate zero */
5873 OP_I7
, /* immediate value 0 .. 7 */
5874 OP_I15
, /* 0 .. 15 */
5875 OP_I16
, /* 1 .. 16 */
5876 OP_I16z
, /* 0 .. 16 */
5877 OP_I31
, /* 0 .. 31 */
5878 OP_I31w
, /* 0 .. 31, optional trailing ! */
5879 OP_I32
, /* 1 .. 32 */
5880 OP_I32z
, /* 0 .. 32 */
5881 OP_I63
, /* 0 .. 63 */
5882 OP_I63s
, /* -64 .. 63 */
5883 OP_I64
, /* 1 .. 64 */
5884 OP_I64z
, /* 0 .. 64 */
5885 OP_I255
, /* 0 .. 255 */
5887 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5888 OP_I7b
, /* 0 .. 7 */
5889 OP_I15b
, /* 0 .. 15 */
5890 OP_I31b
, /* 0 .. 31 */
5892 OP_SH
, /* shifter operand */
5893 OP_SHG
, /* shifter operand with possible group relocation */
5894 OP_ADDR
, /* Memory address expression (any mode) */
5895 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5896 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5897 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5898 OP_EXP
, /* arbitrary expression */
5899 OP_EXPi
, /* same, with optional immediate prefix */
5900 OP_EXPr
, /* same, with optional relocation suffix */
5901 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5903 OP_CPSF
, /* CPS flags */
5904 OP_ENDI
, /* Endianness specifier */
5905 OP_PSR
, /* CPSR/SPSR mask for msr */
5906 OP_COND
, /* conditional code */
5907 OP_TB
, /* Table branch. */
5909 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5910 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5912 OP_RRnpc_I0
, /* ARM register or literal 0 */
5913 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5914 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5915 OP_RF_IF
, /* FPA register or immediate */
5916 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5917 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5919 /* Optional operands. */
5920 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5921 OP_oI31b
, /* 0 .. 31 */
5922 OP_oI32b
, /* 1 .. 32 */
5923 OP_oIffffb
, /* 0 .. 65535 */
5924 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5926 OP_oRR
, /* ARM register */
5927 OP_oRRnpc
, /* ARM register, not the PC */
5928 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5929 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5930 OP_oRND
, /* Optional Neon double precision register */
5931 OP_oRNQ
, /* Optional Neon quad precision register */
5932 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5933 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5934 OP_oSHll
, /* LSL immediate */
5935 OP_oSHar
, /* ASR immediate */
5936 OP_oSHllar
, /* LSL or ASR immediate */
5937 OP_oROR
, /* ROR 0/8/16/24 */
5938 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5940 /* Some pre-defined mixed (ARM/THUMB) operands. */
5941 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5942 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5943 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5945 OP_FIRST_OPTIONAL
= OP_oI7b
5948 /* Generic instruction operand parser. This does no encoding and no
5949 semantic validation; it merely squirrels values away in the inst
5950 structure. Returns SUCCESS or FAIL depending on whether the
5951 specified grammar matched. */
5953 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5955 unsigned const int *upat
= pattern
;
5956 char *backtrack_pos
= 0;
5957 const char *backtrack_error
= 0;
5958 int i
, val
, backtrack_index
= 0;
5959 enum arm_reg_type rtype
;
5960 parse_operand_result result
;
5961 unsigned int op_parse_code
;
5963 #define po_char_or_fail(chr) \
5966 if (skip_past_char (&str, chr) == FAIL) \
5971 #define po_reg_or_fail(regtype) \
5974 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5975 & inst.operands[i].vectype); \
5978 first_error (_(reg_expected_msgs[regtype])); \
5981 inst.operands[i].reg = val; \
5982 inst.operands[i].isreg = 1; \
5983 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5984 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5985 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5986 || rtype == REG_TYPE_VFD \
5987 || rtype == REG_TYPE_NQ); \
5991 #define po_reg_or_goto(regtype, label) \
5994 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5995 & inst.operands[i].vectype); \
5999 inst.operands[i].reg = val; \
6000 inst.operands[i].isreg = 1; \
6001 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6002 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6003 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6004 || rtype == REG_TYPE_VFD \
6005 || rtype == REG_TYPE_NQ); \
6009 #define po_imm_or_fail(min, max, popt) \
6012 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6014 inst.operands[i].imm = val; \
6018 #define po_scalar_or_goto(elsz, label) \
6021 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6024 inst.operands[i].reg = val; \
6025 inst.operands[i].isscalar = 1; \
6029 #define po_misc_or_fail(expr) \
6037 #define po_misc_or_fail_no_backtrack(expr) \
6041 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6042 backtrack_pos = 0; \
6043 if (result != PARSE_OPERAND_SUCCESS) \
6048 #define po_barrier_or_imm(str) \
6051 val = parse_barrier (&str); \
6054 if (ISALPHA (*str)) \
6061 if ((inst.instruction & 0xf0) == 0x60 \
6064 /* ISB can only take SY as an option. */ \
6065 inst.error = _("invalid barrier type"); \
6072 skip_whitespace (str
);
6074 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6076 op_parse_code
= upat
[i
];
6077 if (op_parse_code
>= 1<<16)
6078 op_parse_code
= thumb
? (op_parse_code
>> 16)
6079 : (op_parse_code
& ((1<<16)-1));
6081 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6083 /* Remember where we are in case we need to backtrack. */
6084 gas_assert (!backtrack_pos
);
6085 backtrack_pos
= str
;
6086 backtrack_error
= inst
.error
;
6087 backtrack_index
= i
;
6090 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6091 po_char_or_fail (',');
6093 switch (op_parse_code
)
6101 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6102 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6103 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6104 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6105 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6106 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6108 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6110 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6112 /* Also accept generic coprocessor regs for unknown registers. */
6114 po_reg_or_fail (REG_TYPE_CN
);
6116 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6117 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6118 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6119 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6120 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6121 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6122 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6123 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6124 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6125 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6127 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6129 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6130 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6132 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6134 /* Neon scalar. Using an element size of 8 means that some invalid
6135 scalars are accepted here, so deal with those in later code. */
6136 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6140 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6143 po_imm_or_fail (0, 0, TRUE
);
6148 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6153 po_scalar_or_goto (8, try_rr
);
6156 po_reg_or_fail (REG_TYPE_RN
);
6162 po_scalar_or_goto (8, try_nsdq
);
6165 po_reg_or_fail (REG_TYPE_NSDQ
);
6171 po_scalar_or_goto (8, try_ndq
);
6174 po_reg_or_fail (REG_TYPE_NDQ
);
6180 po_scalar_or_goto (8, try_vfd
);
6183 po_reg_or_fail (REG_TYPE_VFD
);
6188 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6189 not careful then bad things might happen. */
6190 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6195 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6198 /* There's a possibility of getting a 64-bit immediate here, so
6199 we need special handling. */
6200 if (parse_big_immediate (&str
, i
) == FAIL
)
6202 inst
.error
= _("immediate value is out of range");
6210 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6213 po_imm_or_fail (0, 63, TRUE
);
6218 po_char_or_fail ('[');
6219 po_reg_or_fail (REG_TYPE_RN
);
6220 po_char_or_fail (']');
6226 po_reg_or_fail (REG_TYPE_RN
);
6227 if (skip_past_char (&str
, '!') == SUCCESS
)
6228 inst
.operands
[i
].writeback
= 1;
6232 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6233 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6234 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6235 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6236 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6237 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6238 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6239 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6240 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6241 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6242 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6243 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6245 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6247 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6248 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6250 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6251 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6252 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6254 /* Immediate variants */
6256 po_char_or_fail ('{');
6257 po_imm_or_fail (0, 255, TRUE
);
6258 po_char_or_fail ('}');
6262 /* The expression parser chokes on a trailing !, so we have
6263 to find it first and zap it. */
6266 while (*s
&& *s
!= ',')
6271 inst
.operands
[i
].writeback
= 1;
6273 po_imm_or_fail (0, 31, TRUE
);
6281 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6286 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6291 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6293 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6295 val
= parse_reloc (&str
);
6298 inst
.error
= _("unrecognized relocation suffix");
6301 else if (val
!= BFD_RELOC_UNUSED
)
6303 inst
.operands
[i
].imm
= val
;
6304 inst
.operands
[i
].hasreloc
= 1;
6309 /* Operand for MOVW or MOVT. */
6311 po_misc_or_fail (parse_half (&str
));
6314 /* Register or expression. */
6315 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6316 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6318 /* Register or immediate. */
6319 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6320 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6322 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6324 if (!is_immediate_prefix (*str
))
6327 val
= parse_fpa_immediate (&str
);
6330 /* FPA immediates are encoded as registers 8-15.
6331 parse_fpa_immediate has already applied the offset. */
6332 inst
.operands
[i
].reg
= val
;
6333 inst
.operands
[i
].isreg
= 1;
6336 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6337 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6339 /* Two kinds of register. */
6342 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6344 || (rege
->type
!= REG_TYPE_MMXWR
6345 && rege
->type
!= REG_TYPE_MMXWC
6346 && rege
->type
!= REG_TYPE_MMXWCG
))
6348 inst
.error
= _("iWMMXt data or control register expected");
6351 inst
.operands
[i
].reg
= rege
->number
;
6352 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6358 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6360 || (rege
->type
!= REG_TYPE_MMXWC
6361 && rege
->type
!= REG_TYPE_MMXWCG
))
6363 inst
.error
= _("iWMMXt control register expected");
6366 inst
.operands
[i
].reg
= rege
->number
;
6367 inst
.operands
[i
].isreg
= 1;
6372 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6373 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6374 case OP_oROR
: val
= parse_ror (&str
); break;
6375 case OP_PSR
: val
= parse_psr (&str
); break;
6376 case OP_COND
: val
= parse_cond (&str
); break;
6377 case OP_oBARRIER_I15
:
6378 po_barrier_or_imm (str
); break;
6380 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6385 po_reg_or_goto (REG_TYPE_VFC
, try_banked_reg
);
6386 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6389 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6390 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6392 inst
.error
= _("Banked registers are not available with this "
6398 val
= parse_psr (&str
);
6402 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6405 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6407 if (strncasecmp (str
, "APSR_", 5) == 0)
6414 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6415 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6416 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6417 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6418 default: found
= 16;
6422 inst
.operands
[i
].isvec
= 1;
6423 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6424 inst
.operands
[i
].reg
= REG_PC
;
6431 po_misc_or_fail (parse_tb (&str
));
6434 /* Register lists. */
6436 val
= parse_reg_list (&str
);
6439 inst
.operands
[1].writeback
= 1;
6445 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6449 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6453 /* Allow Q registers too. */
6454 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6459 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6461 inst
.operands
[i
].issingle
= 1;
6466 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6471 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6472 &inst
.operands
[i
].vectype
);
6475 /* Addressing modes */
6477 po_misc_or_fail (parse_address (&str
, i
));
6481 po_misc_or_fail_no_backtrack (
6482 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6486 po_misc_or_fail_no_backtrack (
6487 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6491 po_misc_or_fail_no_backtrack (
6492 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6496 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6500 po_misc_or_fail_no_backtrack (
6501 parse_shifter_operand_group_reloc (&str
, i
));
6505 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6509 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6513 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6517 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6520 /* Various value-based sanity checks and shared operations. We
6521 do not signal immediate failures for the register constraints;
6522 this allows a syntax error to take precedence. */
6523 switch (op_parse_code
)
6531 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6532 inst
.error
= BAD_PC
;
6537 if (inst
.operands
[i
].isreg
)
6539 if (inst
.operands
[i
].reg
== REG_PC
)
6540 inst
.error
= BAD_PC
;
6541 else if (inst
.operands
[i
].reg
== REG_SP
)
6542 inst
.error
= BAD_SP
;
6547 if (inst
.operands
[i
].isreg
6548 && inst
.operands
[i
].reg
== REG_PC
6549 && (inst
.operands
[i
].writeback
|| thumb
))
6550 inst
.error
= BAD_PC
;
6559 case OP_oBARRIER_I15
:
6568 inst
.operands
[i
].imm
= val
;
6575 /* If we get here, this operand was successfully parsed. */
6576 inst
.operands
[i
].present
= 1;
6580 inst
.error
= BAD_ARGS
;
6585 /* The parse routine should already have set inst.error, but set a
6586 default here just in case. */
6588 inst
.error
= _("syntax error");
6592 /* Do not backtrack over a trailing optional argument that
6593 absorbed some text. We will only fail again, with the
6594 'garbage following instruction' error message, which is
6595 probably less helpful than the current one. */
6596 if (backtrack_index
== i
&& backtrack_pos
!= str
6597 && upat
[i
+1] == OP_stop
)
6600 inst
.error
= _("syntax error");
6604 /* Try again, skipping the optional argument at backtrack_pos. */
6605 str
= backtrack_pos
;
6606 inst
.error
= backtrack_error
;
6607 inst
.operands
[backtrack_index
].present
= 0;
6608 i
= backtrack_index
;
6612 /* Check that we have parsed all the arguments. */
6613 if (*str
!= '\0' && !inst
.error
)
6614 inst
.error
= _("garbage following instruction");
6616 return inst
.error
? FAIL
: SUCCESS
;
6619 #undef po_char_or_fail
6620 #undef po_reg_or_fail
6621 #undef po_reg_or_goto
6622 #undef po_imm_or_fail
6623 #undef po_scalar_or_fail
6624 #undef po_barrier_or_imm
6626 /* Shorthand macro for instruction encoding functions issuing errors. */
6627 #define constraint(expr, err) \
6638 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6639 instructions are unpredictable if these registers are used. This
6640 is the BadReg predicate in ARM's Thumb-2 documentation. */
6641 #define reject_bad_reg(reg) \
6643 if (reg == REG_SP || reg == REG_PC) \
6645 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6650 /* If REG is R13 (the stack pointer), warn that its use is
6652 #define warn_deprecated_sp(reg) \
6654 if (warn_on_deprecated && reg == REG_SP) \
6655 as_warn (_("use of r13 is deprecated")); \
6658 /* Functions for operand encoding. ARM, then Thumb. */
6660 #define rotate_left(v, n) (v << n | v >> (32 - n))
6662 /* If VAL can be encoded in the immediate field of an ARM instruction,
6663 return the encoded form. Otherwise, return FAIL. */
6666 encode_arm_immediate (unsigned int val
)
6670 for (i
= 0; i
< 32; i
+= 2)
6671 if ((a
= rotate_left (val
, i
)) <= 0xff)
6672 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6677 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6678 return the encoded form. Otherwise, return FAIL. */
6680 encode_thumb32_immediate (unsigned int val
)
6687 for (i
= 1; i
<= 24; i
++)
6690 if ((val
& ~(0xff << i
)) == 0)
6691 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6695 if (val
== ((a
<< 16) | a
))
6697 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6701 if (val
== ((a
<< 16) | a
))
6702 return 0x200 | (a
>> 8);
6706 /* Encode a VFP SP or DP register number into inst.instruction. */
6709 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6711 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6714 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6717 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6720 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6725 first_error (_("D register out of range for selected VFP version"));
6733 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6737 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6741 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6745 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6749 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6753 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6761 /* Encode a <shift> in an ARM-format instruction. The immediate,
6762 if any, is handled by md_apply_fix. */
6764 encode_arm_shift (int i
)
6766 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6767 inst
.instruction
|= SHIFT_ROR
<< 5;
6770 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6771 if (inst
.operands
[i
].immisreg
)
6773 inst
.instruction
|= SHIFT_BY_REG
;
6774 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6777 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6782 encode_arm_shifter_operand (int i
)
6784 if (inst
.operands
[i
].isreg
)
6786 inst
.instruction
|= inst
.operands
[i
].reg
;
6787 encode_arm_shift (i
);
6790 inst
.instruction
|= INST_IMMEDIATE
;
6793 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6795 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6797 gas_assert (inst
.operands
[i
].isreg
);
6798 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6800 if (inst
.operands
[i
].preind
)
6804 inst
.error
= _("instruction does not accept preindexed addressing");
6807 inst
.instruction
|= PRE_INDEX
;
6808 if (inst
.operands
[i
].writeback
)
6809 inst
.instruction
|= WRITE_BACK
;
6812 else if (inst
.operands
[i
].postind
)
6814 gas_assert (inst
.operands
[i
].writeback
);
6816 inst
.instruction
|= WRITE_BACK
;
6818 else /* unindexed - only for coprocessor */
6820 inst
.error
= _("instruction does not accept unindexed addressing");
6824 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6825 && (((inst
.instruction
& 0x000f0000) >> 16)
6826 == ((inst
.instruction
& 0x0000f000) >> 12)))
6827 as_warn ((inst
.instruction
& LOAD_BIT
)
6828 ? _("destination register same as write-back base")
6829 : _("source register same as write-back base"));
6832 /* inst.operands[i] was set up by parse_address. Encode it into an
6833 ARM-format mode 2 load or store instruction. If is_t is true,
6834 reject forms that cannot be used with a T instruction (i.e. not
6837 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6839 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6841 encode_arm_addr_mode_common (i
, is_t
);
6843 if (inst
.operands
[i
].immisreg
)
6845 constraint ((inst
.operands
[i
].imm
== REG_PC
6846 || (is_pc
&& inst
.operands
[i
].writeback
)),
6848 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6849 inst
.instruction
|= inst
.operands
[i
].imm
;
6850 if (!inst
.operands
[i
].negative
)
6851 inst
.instruction
|= INDEX_UP
;
6852 if (inst
.operands
[i
].shifted
)
6854 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6855 inst
.instruction
|= SHIFT_ROR
<< 5;
6858 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6859 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6863 else /* immediate offset in inst.reloc */
6865 if (is_pc
&& !inst
.reloc
.pc_rel
)
6867 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6869 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6870 cannot use PC in addressing.
6871 PC cannot be used in writeback addressing, either. */
6872 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6875 /* Use of PC in str is deprecated for ARMv7. */
6876 if (warn_on_deprecated
6878 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6879 as_warn (_("use of PC in this instruction is deprecated"));
6882 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6883 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6887 /* inst.operands[i] was set up by parse_address. Encode it into an
6888 ARM-format mode 3 load or store instruction. Reject forms that
6889 cannot be used with such instructions. If is_t is true, reject
6890 forms that cannot be used with a T instruction (i.e. not
6893 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6895 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6897 inst
.error
= _("instruction does not accept scaled register index");
6901 encode_arm_addr_mode_common (i
, is_t
);
6903 if (inst
.operands
[i
].immisreg
)
6905 constraint ((inst
.operands
[i
].imm
== REG_PC
6906 || inst
.operands
[i
].reg
== REG_PC
),
6908 inst
.instruction
|= inst
.operands
[i
].imm
;
6909 if (!inst
.operands
[i
].negative
)
6910 inst
.instruction
|= INDEX_UP
;
6912 else /* immediate offset in inst.reloc */
6914 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6915 && inst
.operands
[i
].writeback
),
6917 inst
.instruction
|= HWOFFSET_IMM
;
6918 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6919 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6923 /* inst.operands[i] was set up by parse_address. Encode it into an
6924 ARM-format instruction. Reject all forms which cannot be encoded
6925 into a coprocessor load/store instruction. If wb_ok is false,
6926 reject use of writeback; if unind_ok is false, reject use of
6927 unindexed addressing. If reloc_override is not 0, use it instead
6928 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6929 (in which case it is preserved). */
6932 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6934 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6936 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6938 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6940 gas_assert (!inst
.operands
[i
].writeback
);
6943 inst
.error
= _("instruction does not support unindexed addressing");
6946 inst
.instruction
|= inst
.operands
[i
].imm
;
6947 inst
.instruction
|= INDEX_UP
;
6951 if (inst
.operands
[i
].preind
)
6952 inst
.instruction
|= PRE_INDEX
;
6954 if (inst
.operands
[i
].writeback
)
6956 if (inst
.operands
[i
].reg
== REG_PC
)
6958 inst
.error
= _("pc may not be used with write-back");
6963 inst
.error
= _("instruction does not support writeback");
6966 inst
.instruction
|= WRITE_BACK
;
6970 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6971 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6972 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6973 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6976 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6978 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6984 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6985 Determine whether it can be performed with a move instruction; if
6986 it can, convert inst.instruction to that move instruction and
6987 return TRUE; if it can't, convert inst.instruction to a literal-pool
6988 load and return FALSE. If this is not a valid thing to do in the
6989 current context, set inst.error and return TRUE.
6991 inst.operands[i] describes the destination register. */
6994 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6999 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7003 if ((inst
.instruction
& tbit
) == 0)
7005 inst
.error
= _("invalid pseudo operation");
7008 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7010 inst
.error
= _("constant expression expected");
7013 if (inst
.reloc
.exp
.X_op
== O_constant
)
7017 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7019 /* This can be done with a mov(1) instruction. */
7020 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7021 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7027 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7030 /* This can be done with a mov instruction. */
7031 inst
.instruction
&= LITERAL_MASK
;
7032 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7033 inst
.instruction
|= value
& 0xfff;
7037 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7040 /* This can be done with a mvn instruction. */
7041 inst
.instruction
&= LITERAL_MASK
;
7042 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7043 inst
.instruction
|= value
& 0xfff;
7049 if (add_to_lit_pool () == FAIL
)
7051 inst
.error
= _("literal pool insertion failed");
7054 inst
.operands
[1].reg
= REG_PC
;
7055 inst
.operands
[1].isreg
= 1;
7056 inst
.operands
[1].preind
= 1;
7057 inst
.reloc
.pc_rel
= 1;
7058 inst
.reloc
.type
= (thumb_p
7059 ? BFD_RELOC_ARM_THUMB_OFFSET
7061 ? BFD_RELOC_ARM_HWLITERAL
7062 : BFD_RELOC_ARM_LITERAL
));
7066 /* Functions for instruction encoding, sorted by sub-architecture.
7067 First some generics; their names are taken from the conventional
7068 bit positions for register arguments in ARM format instructions. */
7078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7084 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7085 inst
.instruction
|= inst
.operands
[1].reg
;
7091 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7092 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7098 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7099 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7105 unsigned Rn
= inst
.operands
[2].reg
;
7106 /* Enforce restrictions on SWP instruction. */
7107 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7109 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7110 _("Rn must not overlap other operands"));
7112 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7113 if (warn_on_deprecated
7114 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7115 as_warn (_("swp{b} use is deprecated for this architecture"));
7118 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7119 inst
.instruction
|= inst
.operands
[1].reg
;
7120 inst
.instruction
|= Rn
<< 16;
7126 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7127 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7128 inst
.instruction
|= inst
.operands
[2].reg
;
7134 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7135 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7136 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7137 || inst
.reloc
.exp
.X_add_number
!= 0),
7139 inst
.instruction
|= inst
.operands
[0].reg
;
7140 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7141 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7147 inst
.instruction
|= inst
.operands
[0].imm
;
7153 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7154 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7157 /* ARM instructions, in alphabetical order by function name (except
7158 that wrapper functions appear immediately after the function they
7161 /* This is a pseudo-op of the form "adr rd, label" to be converted
7162 into a relative address of the form "add rd, pc, #label-.-8". */
7167 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7169 /* Frag hacking will turn this into a sub instruction if the offset turns
7170 out to be negative. */
7171 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7172 inst
.reloc
.pc_rel
= 1;
7173 inst
.reloc
.exp
.X_add_number
-= 8;
7176 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7177 into a relative address of the form:
7178 add rd, pc, #low(label-.-8)"
7179 add rd, rd, #high(label-.-8)" */
7184 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7186 /* Frag hacking will turn this into a sub instruction if the offset turns
7187 out to be negative. */
7188 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7189 inst
.reloc
.pc_rel
= 1;
7190 inst
.size
= INSN_SIZE
* 2;
7191 inst
.reloc
.exp
.X_add_number
-= 8;
7197 if (!inst
.operands
[1].present
)
7198 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7199 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7200 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7201 encode_arm_shifter_operand (2);
7207 if (inst
.operands
[0].present
)
7209 constraint ((inst
.instruction
& 0xf0) != 0x40
7210 && inst
.operands
[0].imm
> 0xf
7211 && inst
.operands
[0].imm
< 0x0,
7212 _("bad barrier type"));
7213 inst
.instruction
|= inst
.operands
[0].imm
;
7216 inst
.instruction
|= 0xf;
7222 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7223 constraint (msb
> 32, _("bit-field extends past end of register"));
7224 /* The instruction encoding stores the LSB and MSB,
7225 not the LSB and width. */
7226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7227 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7228 inst
.instruction
|= (msb
- 1) << 16;
7236 /* #0 in second position is alternative syntax for bfc, which is
7237 the same instruction but with REG_PC in the Rm field. */
7238 if (!inst
.operands
[1].isreg
)
7239 inst
.operands
[1].reg
= REG_PC
;
7241 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7242 constraint (msb
> 32, _("bit-field extends past end of register"));
7243 /* The instruction encoding stores the LSB and MSB,
7244 not the LSB and width. */
7245 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7246 inst
.instruction
|= inst
.operands
[1].reg
;
7247 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7248 inst
.instruction
|= (msb
- 1) << 16;
7254 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7255 _("bit-field extends past end of register"));
7256 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7257 inst
.instruction
|= inst
.operands
[1].reg
;
7258 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7259 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7262 /* ARM V5 breakpoint instruction (argument parse)
7263 BKPT <16 bit unsigned immediate>
7264 Instruction is not conditional.
7265 The bit pattern given in insns[] has the COND_ALWAYS condition,
7266 and it is an error if the caller tried to override that. */
7271 /* Top 12 of 16 bits to bits 19:8. */
7272 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7274 /* Bottom 4 of 16 bits to bits 3:0. */
7275 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7279 encode_branch (int default_reloc
)
7281 if (inst
.operands
[0].hasreloc
)
7283 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7284 _("the only suffix valid here is '(plt)'"));
7285 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7288 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7289 inst
.reloc
.pc_rel
= 1;
7296 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7297 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7300 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7307 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7309 if (inst
.cond
== COND_ALWAYS
)
7310 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7312 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7316 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7319 /* ARM V5 branch-link-exchange instruction (argument parse)
7320 BLX <target_addr> ie BLX(1)
7321 BLX{<condition>} <Rm> ie BLX(2)
7322 Unfortunately, there are two different opcodes for this mnemonic.
7323 So, the insns[].value is not used, and the code here zaps values
7324 into inst.instruction.
7325 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7330 if (inst
.operands
[0].isreg
)
7332 /* Arg is a register; the opcode provided by insns[] is correct.
7333 It is not illegal to do "blx pc", just useless. */
7334 if (inst
.operands
[0].reg
== REG_PC
)
7335 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7337 inst
.instruction
|= inst
.operands
[0].reg
;
7341 /* Arg is an address; this instruction cannot be executed
7342 conditionally, and the opcode must be adjusted.
7343 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7344 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7345 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7346 inst
.instruction
= 0xfa000000;
7347 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7354 bfd_boolean want_reloc
;
7356 if (inst
.operands
[0].reg
== REG_PC
)
7357 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7359 inst
.instruction
|= inst
.operands
[0].reg
;
7360 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7361 it is for ARMv4t or earlier. */
7362 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7363 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7367 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7372 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7376 /* ARM v5TEJ. Jump to Jazelle code. */
7381 if (inst
.operands
[0].reg
== REG_PC
)
7382 as_tsktsk (_("use of r15 in bxj is not really useful"));
7384 inst
.instruction
|= inst
.operands
[0].reg
;
7387 /* Co-processor data operation:
7388 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7389 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7393 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7394 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7395 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7396 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7397 inst
.instruction
|= inst
.operands
[4].reg
;
7398 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7404 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7405 encode_arm_shifter_operand (1);
7408 /* Transfer between coprocessor and ARM registers.
7409 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7414 No special properties. */
7421 Rd
= inst
.operands
[2].reg
;
7424 if (inst
.instruction
== 0xee000010
7425 || inst
.instruction
== 0xfe000010)
7427 reject_bad_reg (Rd
);
7430 constraint (Rd
== REG_SP
, BAD_SP
);
7435 if (inst
.instruction
== 0xe000010)
7436 constraint (Rd
== REG_PC
, BAD_PC
);
7440 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7441 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7442 inst
.instruction
|= Rd
<< 12;
7443 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7444 inst
.instruction
|= inst
.operands
[4].reg
;
7445 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7448 /* Transfer between coprocessor register and pair of ARM registers.
7449 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7454 Two XScale instructions are special cases of these:
7456 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7457 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7459 Result unpredictable if Rd or Rn is R15. */
7466 Rd
= inst
.operands
[2].reg
;
7467 Rn
= inst
.operands
[3].reg
;
7471 reject_bad_reg (Rd
);
7472 reject_bad_reg (Rn
);
7476 constraint (Rd
== REG_PC
, BAD_PC
);
7477 constraint (Rn
== REG_PC
, BAD_PC
);
7480 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7481 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7482 inst
.instruction
|= Rd
<< 12;
7483 inst
.instruction
|= Rn
<< 16;
7484 inst
.instruction
|= inst
.operands
[4].reg
;
7490 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7491 if (inst
.operands
[1].present
)
7493 inst
.instruction
|= CPSI_MMOD
;
7494 inst
.instruction
|= inst
.operands
[1].imm
;
7501 inst
.instruction
|= inst
.operands
[0].imm
;
7507 unsigned Rd
, Rn
, Rm
;
7509 Rd
= inst
.operands
[0].reg
;
7510 Rn
= (inst
.operands
[1].present
7511 ? inst
.operands
[1].reg
: Rd
);
7512 Rm
= inst
.operands
[2].reg
;
7514 constraint ((Rd
== REG_PC
), BAD_PC
);
7515 constraint ((Rn
== REG_PC
), BAD_PC
);
7516 constraint ((Rm
== REG_PC
), BAD_PC
);
7518 inst
.instruction
|= Rd
<< 16;
7519 inst
.instruction
|= Rn
<< 0;
7520 inst
.instruction
|= Rm
<< 8;
7526 /* There is no IT instruction in ARM mode. We
7527 process it to do the validation as if in
7528 thumb mode, just in case the code gets
7529 assembled for thumb using the unified syntax. */
7534 set_it_insn_type (IT_INSN
);
7535 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7536 now_it
.cc
= inst
.operands
[0].imm
;
7543 int base_reg
= inst
.operands
[0].reg
;
7544 int range
= inst
.operands
[1].imm
;
7546 inst
.instruction
|= base_reg
<< 16;
7547 inst
.instruction
|= range
;
7549 if (inst
.operands
[1].writeback
)
7550 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7552 if (inst
.operands
[0].writeback
)
7554 inst
.instruction
|= WRITE_BACK
;
7555 /* Check for unpredictable uses of writeback. */
7556 if (inst
.instruction
& LOAD_BIT
)
7558 /* Not allowed in LDM type 2. */
7559 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7560 && ((range
& (1 << REG_PC
)) == 0))
7561 as_warn (_("writeback of base register is UNPREDICTABLE"));
7562 /* Only allowed if base reg not in list for other types. */
7563 else if (range
& (1 << base_reg
))
7564 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7568 /* Not allowed for type 2. */
7569 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7570 as_warn (_("writeback of base register is UNPREDICTABLE"));
7571 /* Only allowed if base reg not in list, or first in list. */
7572 else if ((range
& (1 << base_reg
))
7573 && (range
& ((1 << base_reg
) - 1)))
7574 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7579 /* ARMv5TE load-consecutive (argument parse)
7588 constraint (inst
.operands
[0].reg
% 2 != 0,
7589 _("first destination register must be even"));
7590 constraint (inst
.operands
[1].present
7591 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7592 _("can only load two consecutive registers"));
7593 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7594 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7596 if (!inst
.operands
[1].present
)
7597 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7599 if (inst
.instruction
& LOAD_BIT
)
7601 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7602 register and the first register written; we have to diagnose
7603 overlap between the base and the second register written here. */
7605 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7606 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7607 as_warn (_("base register written back, and overlaps "
7608 "second destination register"));
7610 /* For an index-register load, the index register must not overlap the
7611 destination (even if not write-back). */
7612 else if (inst
.operands
[2].immisreg
7613 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7614 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7615 as_warn (_("index register overlaps destination register"));
7618 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7619 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7625 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7626 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7627 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7628 || inst
.operands
[1].negative
7629 /* This can arise if the programmer has written
7631 or if they have mistakenly used a register name as the last
7634 It is very difficult to distinguish between these two cases
7635 because "rX" might actually be a label. ie the register
7636 name has been occluded by a symbol of the same name. So we
7637 just generate a general 'bad addressing mode' type error
7638 message and leave it up to the programmer to discover the
7639 true cause and fix their mistake. */
7640 || (inst
.operands
[1].reg
== REG_PC
),
7643 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7644 || inst
.reloc
.exp
.X_add_number
!= 0,
7645 _("offset must be zero in ARM encoding"));
7647 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7649 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7650 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7651 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7657 constraint (inst
.operands
[0].reg
% 2 != 0,
7658 _("even register required"));
7659 constraint (inst
.operands
[1].present
7660 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7661 _("can only load two consecutive registers"));
7662 /* If op 1 were present and equal to PC, this function wouldn't
7663 have been called in the first place. */
7664 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7666 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7667 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7673 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7674 if (!inst
.operands
[1].isreg
)
7675 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7677 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7683 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7685 if (inst
.operands
[1].preind
)
7687 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7688 || inst
.reloc
.exp
.X_add_number
!= 0,
7689 _("this instruction requires a post-indexed address"));
7691 inst
.operands
[1].preind
= 0;
7692 inst
.operands
[1].postind
= 1;
7693 inst
.operands
[1].writeback
= 1;
7695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7696 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7699 /* Halfword and signed-byte load/store operations. */
7704 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7705 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7706 if (!inst
.operands
[1].isreg
)
7707 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7709 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7715 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7717 if (inst
.operands
[1].preind
)
7719 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7720 || inst
.reloc
.exp
.X_add_number
!= 0,
7721 _("this instruction requires a post-indexed address"));
7723 inst
.operands
[1].preind
= 0;
7724 inst
.operands
[1].postind
= 1;
7725 inst
.operands
[1].writeback
= 1;
7727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7728 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7731 /* Co-processor register load/store.
7732 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7736 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7737 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7738 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7744 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7745 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7746 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7747 && !(inst
.instruction
& 0x00400000))
7748 as_tsktsk (_("Rd and Rm should be different in mla"));
7750 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7751 inst
.instruction
|= inst
.operands
[1].reg
;
7752 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7753 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7759 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7760 encode_arm_shifter_operand (1);
7763 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7770 top
= (inst
.instruction
& 0x00400000) != 0;
7771 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7772 _(":lower16: not allowed this instruction"));
7773 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7774 _(":upper16: not allowed instruction"));
7775 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7776 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7778 imm
= inst
.reloc
.exp
.X_add_number
;
7779 /* The value is in two pieces: 0:11, 16:19. */
7780 inst
.instruction
|= (imm
& 0x00000fff);
7781 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7785 static void do_vfp_nsyn_opcode (const char *);
7788 do_vfp_nsyn_mrs (void)
7790 if (inst
.operands
[0].isvec
)
7792 if (inst
.operands
[1].reg
!= 1)
7793 first_error (_("operand 1 must be FPSCR"));
7794 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7795 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7796 do_vfp_nsyn_opcode ("fmstat");
7798 else if (inst
.operands
[1].isvec
)
7799 do_vfp_nsyn_opcode ("fmrx");
7807 do_vfp_nsyn_msr (void)
7809 if (inst
.operands
[0].isvec
)
7810 do_vfp_nsyn_opcode ("fmxr");
7820 unsigned Rt
= inst
.operands
[0].reg
;
7822 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7824 inst
.error
= BAD_SP
;
7828 /* APSR_ sets isvec. All other refs to PC are illegal. */
7829 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7831 inst
.error
= BAD_PC
;
7835 if (inst
.operands
[1].reg
!= 1)
7836 first_error (_("operand 1 must be FPSCR"));
7838 inst
.instruction
|= (Rt
<< 12);
7844 unsigned Rt
= inst
.operands
[1].reg
;
7847 reject_bad_reg (Rt
);
7848 else if (Rt
== REG_PC
)
7850 inst
.error
= BAD_PC
;
7854 if (inst
.operands
[0].reg
!= 1)
7855 first_error (_("operand 0 must be FPSCR"));
7857 inst
.instruction
|= (Rt
<< 12);
7865 if (do_vfp_nsyn_mrs () == SUCCESS
)
7868 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7869 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7871 if (inst
.operands
[1].isreg
)
7873 br
= inst
.operands
[1].reg
;
7874 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
7875 as_bad (_("bad register for mrs"));
7879 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7880 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7882 _("'CPSR' or 'SPSR' expected"));
7883 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
7886 inst
.instruction
|= br
;
7889 /* Two possible forms:
7890 "{C|S}PSR_<field>, Rm",
7891 "{C|S}PSR_f, #expression". */
7896 if (do_vfp_nsyn_msr () == SUCCESS
)
7899 inst
.instruction
|= inst
.operands
[0].imm
;
7900 if (inst
.operands
[1].isreg
)
7901 inst
.instruction
|= inst
.operands
[1].reg
;
7904 inst
.instruction
|= INST_IMMEDIATE
;
7905 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7906 inst
.reloc
.pc_rel
= 0;
7913 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7915 if (!inst
.operands
[2].present
)
7916 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7917 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7918 inst
.instruction
|= inst
.operands
[1].reg
;
7919 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7921 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7922 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7923 as_tsktsk (_("Rd and Rm should be different in mul"));
7926 /* Long Multiply Parser
7927 UMULL RdLo, RdHi, Rm, Rs
7928 SMULL RdLo, RdHi, Rm, Rs
7929 UMLAL RdLo, RdHi, Rm, Rs
7930 SMLAL RdLo, RdHi, Rm, Rs. */
7935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7936 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7937 inst
.instruction
|= inst
.operands
[2].reg
;
7938 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7940 /* rdhi and rdlo must be different. */
7941 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7942 as_tsktsk (_("rdhi and rdlo must be different"));
7944 /* rdhi, rdlo and rm must all be different before armv6. */
7945 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7946 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7947 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7948 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7954 if (inst
.operands
[0].present
7955 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7957 /* Architectural NOP hints are CPSR sets with no bits selected. */
7958 inst
.instruction
&= 0xf0000000;
7959 inst
.instruction
|= 0x0320f000;
7960 if (inst
.operands
[0].present
)
7961 inst
.instruction
|= inst
.operands
[0].imm
;
7965 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7966 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7967 Condition defaults to COND_ALWAYS.
7968 Error if Rd, Rn or Rm are R15. */
7973 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7974 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7975 inst
.instruction
|= inst
.operands
[2].reg
;
7976 if (inst
.operands
[3].present
)
7977 encode_arm_shift (3);
7980 /* ARM V6 PKHTB (Argument Parse). */
7985 if (!inst
.operands
[3].present
)
7987 /* If the shift specifier is omitted, turn the instruction
7988 into pkhbt rd, rm, rn. */
7989 inst
.instruction
&= 0xfff00010;
7990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7991 inst
.instruction
|= inst
.operands
[1].reg
;
7992 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7996 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7997 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7998 inst
.instruction
|= inst
.operands
[2].reg
;
7999 encode_arm_shift (3);
8003 /* ARMv5TE: Preload-Cache
8004 MP Extensions: Preload for write
8008 Syntactically, like LDR with B=1, W=0, L=1. */
8013 constraint (!inst
.operands
[0].isreg
,
8014 _("'[' expected after PLD mnemonic"));
8015 constraint (inst
.operands
[0].postind
,
8016 _("post-indexed expression used in preload instruction"));
8017 constraint (inst
.operands
[0].writeback
,
8018 _("writeback used in preload instruction"));
8019 constraint (!inst
.operands
[0].preind
,
8020 _("unindexed addressing used in preload instruction"));
8021 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8024 /* ARMv7: PLI <addr_mode> */
8028 constraint (!inst
.operands
[0].isreg
,
8029 _("'[' expected after PLI mnemonic"));
8030 constraint (inst
.operands
[0].postind
,
8031 _("post-indexed expression used in preload instruction"));
8032 constraint (inst
.operands
[0].writeback
,
8033 _("writeback used in preload instruction"));
8034 constraint (!inst
.operands
[0].preind
,
8035 _("unindexed addressing used in preload instruction"));
8036 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8037 inst
.instruction
&= ~PRE_INDEX
;
8043 inst
.operands
[1] = inst
.operands
[0];
8044 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8045 inst
.operands
[0].isreg
= 1;
8046 inst
.operands
[0].writeback
= 1;
8047 inst
.operands
[0].reg
= REG_SP
;
8051 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8052 word at the specified address and the following word
8054 Unconditionally executed.
8055 Error if Rn is R15. */
8060 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8061 if (inst
.operands
[0].writeback
)
8062 inst
.instruction
|= WRITE_BACK
;
8065 /* ARM V6 ssat (argument parse). */
8070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8071 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8072 inst
.instruction
|= inst
.operands
[2].reg
;
8074 if (inst
.operands
[3].present
)
8075 encode_arm_shift (3);
8078 /* ARM V6 usat (argument parse). */
8083 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8084 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8085 inst
.instruction
|= inst
.operands
[2].reg
;
8087 if (inst
.operands
[3].present
)
8088 encode_arm_shift (3);
8091 /* ARM V6 ssat16 (argument parse). */
8096 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8097 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8098 inst
.instruction
|= inst
.operands
[2].reg
;
8104 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8105 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8106 inst
.instruction
|= inst
.operands
[2].reg
;
8109 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8110 preserving the other bits.
8112 setend <endian_specifier>, where <endian_specifier> is either
8118 if (inst
.operands
[0].imm
)
8119 inst
.instruction
|= 0x200;
8125 unsigned int Rm
= (inst
.operands
[1].present
8126 ? inst
.operands
[1].reg
8127 : inst
.operands
[0].reg
);
8129 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8130 inst
.instruction
|= Rm
;
8131 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8133 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8134 inst
.instruction
|= SHIFT_BY_REG
;
8137 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8143 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8144 inst
.reloc
.pc_rel
= 0;
8150 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8151 inst
.reloc
.pc_rel
= 0;
8157 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8158 inst
.reloc
.pc_rel
= 0;
8161 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8162 SMLAxy{cond} Rd,Rm,Rs,Rn
8163 SMLAWy{cond} Rd,Rm,Rs,Rn
8164 Error if any register is R15. */
8169 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8170 inst
.instruction
|= inst
.operands
[1].reg
;
8171 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8172 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8175 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8176 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8177 Error if any register is R15.
8178 Warning if Rdlo == Rdhi. */
8183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8184 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8185 inst
.instruction
|= inst
.operands
[2].reg
;
8186 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8188 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8189 as_tsktsk (_("rdhi and rdlo must be different"));
8192 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8193 SMULxy{cond} Rd,Rm,Rs
8194 Error if any register is R15. */
8199 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8200 inst
.instruction
|= inst
.operands
[1].reg
;
8201 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8204 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8205 the same for both ARM and Thumb-2. */
8212 if (inst
.operands
[0].present
)
8214 reg
= inst
.operands
[0].reg
;
8215 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8220 inst
.instruction
|= reg
<< 16;
8221 inst
.instruction
|= inst
.operands
[1].imm
;
8222 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8223 inst
.instruction
|= WRITE_BACK
;
8226 /* ARM V6 strex (argument parse). */
8231 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8232 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8233 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8234 || inst
.operands
[2].negative
8235 /* See comment in do_ldrex(). */
8236 || (inst
.operands
[2].reg
== REG_PC
),
8239 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8240 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8242 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8243 || inst
.reloc
.exp
.X_add_number
!= 0,
8244 _("offset must be zero in ARM encoding"));
8246 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8247 inst
.instruction
|= inst
.operands
[1].reg
;
8248 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8249 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8255 constraint (inst
.operands
[1].reg
% 2 != 0,
8256 _("even register required"));
8257 constraint (inst
.operands
[2].present
8258 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8259 _("can only store two consecutive registers"));
8260 /* If op 2 were present and equal to PC, this function wouldn't
8261 have been called in the first place. */
8262 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8264 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8265 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8266 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8269 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8270 inst
.instruction
|= inst
.operands
[1].reg
;
8271 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8274 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8275 extends it to 32-bits, and adds the result to a value in another
8276 register. You can specify a rotation by 0, 8, 16, or 24 bits
8277 before extracting the 16-bit value.
8278 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8279 Condition defaults to COND_ALWAYS.
8280 Error if any register uses R15. */
8285 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8286 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8287 inst
.instruction
|= inst
.operands
[2].reg
;
8288 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8293 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8294 Condition defaults to COND_ALWAYS.
8295 Error if any register uses R15. */
8300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8301 inst
.instruction
|= inst
.operands
[1].reg
;
8302 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8305 /* VFP instructions. In a logical order: SP variant first, monad
8306 before dyad, arithmetic then move then load/store. */
8309 do_vfp_sp_monadic (void)
8311 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8312 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8316 do_vfp_sp_dyadic (void)
8318 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8319 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8320 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8324 do_vfp_sp_compare_z (void)
8326 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8330 do_vfp_dp_sp_cvt (void)
8332 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8333 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8337 do_vfp_sp_dp_cvt (void)
8339 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8340 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8344 do_vfp_reg_from_sp (void)
8346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8347 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8351 do_vfp_reg2_from_sp2 (void)
8353 constraint (inst
.operands
[2].imm
!= 2,
8354 _("only two consecutive VFP SP registers allowed here"));
8355 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8356 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8357 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8361 do_vfp_sp_from_reg (void)
8363 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8364 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8368 do_vfp_sp2_from_reg2 (void)
8370 constraint (inst
.operands
[0].imm
!= 2,
8371 _("only two consecutive VFP SP registers allowed here"));
8372 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8373 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8374 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8378 do_vfp_sp_ldst (void)
8380 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8381 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8385 do_vfp_dp_ldst (void)
8387 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8388 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8393 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8395 if (inst
.operands
[0].writeback
)
8396 inst
.instruction
|= WRITE_BACK
;
8398 constraint (ldstm_type
!= VFP_LDSTMIA
,
8399 _("this addressing mode requires base-register writeback"));
8400 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8401 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8402 inst
.instruction
|= inst
.operands
[1].imm
;
8406 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8410 if (inst
.operands
[0].writeback
)
8411 inst
.instruction
|= WRITE_BACK
;
8413 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8414 _("this addressing mode requires base-register writeback"));
8416 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8417 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8419 count
= inst
.operands
[1].imm
<< 1;
8420 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8423 inst
.instruction
|= count
;
8427 do_vfp_sp_ldstmia (void)
8429 vfp_sp_ldstm (VFP_LDSTMIA
);
8433 do_vfp_sp_ldstmdb (void)
8435 vfp_sp_ldstm (VFP_LDSTMDB
);
8439 do_vfp_dp_ldstmia (void)
8441 vfp_dp_ldstm (VFP_LDSTMIA
);
8445 do_vfp_dp_ldstmdb (void)
8447 vfp_dp_ldstm (VFP_LDSTMDB
);
8451 do_vfp_xp_ldstmia (void)
8453 vfp_dp_ldstm (VFP_LDSTMIAX
);
8457 do_vfp_xp_ldstmdb (void)
8459 vfp_dp_ldstm (VFP_LDSTMDBX
);
8463 do_vfp_dp_rd_rm (void)
8465 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8466 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8470 do_vfp_dp_rn_rd (void)
8472 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8473 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8477 do_vfp_dp_rd_rn (void)
8479 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8480 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8484 do_vfp_dp_rd_rn_rm (void)
8486 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8487 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8488 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8494 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8498 do_vfp_dp_rm_rd_rn (void)
8500 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8501 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8502 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8505 /* VFPv3 instructions. */
8507 do_vfp_sp_const (void)
8509 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8510 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8511 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8515 do_vfp_dp_const (void)
8517 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8518 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8519 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8523 vfp_conv (int srcsize
)
8525 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8526 inst
.instruction
|= (immbits
& 1) << 5;
8527 inst
.instruction
|= (immbits
>> 1);
8531 do_vfp_sp_conv_16 (void)
8533 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8538 do_vfp_dp_conv_16 (void)
8540 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8545 do_vfp_sp_conv_32 (void)
8547 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8552 do_vfp_dp_conv_32 (void)
8554 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8558 /* FPA instructions. Also in a logical order. */
8563 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8564 inst
.instruction
|= inst
.operands
[1].reg
;
8568 do_fpa_ldmstm (void)
8570 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8571 switch (inst
.operands
[1].imm
)
8573 case 1: inst
.instruction
|= CP_T_X
; break;
8574 case 2: inst
.instruction
|= CP_T_Y
; break;
8575 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8580 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8582 /* The instruction specified "ea" or "fd", so we can only accept
8583 [Rn]{!}. The instruction does not really support stacking or
8584 unstacking, so we have to emulate these by setting appropriate
8585 bits and offsets. */
8586 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8587 || inst
.reloc
.exp
.X_add_number
!= 0,
8588 _("this instruction does not support indexing"));
8590 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8591 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8593 if (!(inst
.instruction
& INDEX_UP
))
8594 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8596 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8598 inst
.operands
[2].preind
= 0;
8599 inst
.operands
[2].postind
= 1;
8603 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8606 /* iWMMXt instructions: strictly in alphabetical order. */
8609 do_iwmmxt_tandorc (void)
8611 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8615 do_iwmmxt_textrc (void)
8617 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8618 inst
.instruction
|= inst
.operands
[1].imm
;
8622 do_iwmmxt_textrm (void)
8624 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8625 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8626 inst
.instruction
|= inst
.operands
[2].imm
;
8630 do_iwmmxt_tinsr (void)
8632 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8633 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8634 inst
.instruction
|= inst
.operands
[2].imm
;
8638 do_iwmmxt_tmia (void)
8640 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8641 inst
.instruction
|= inst
.operands
[1].reg
;
8642 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8646 do_iwmmxt_waligni (void)
8648 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8649 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8650 inst
.instruction
|= inst
.operands
[2].reg
;
8651 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8655 do_iwmmxt_wmerge (void)
8657 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8658 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8659 inst
.instruction
|= inst
.operands
[2].reg
;
8660 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8664 do_iwmmxt_wmov (void)
8666 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8667 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8668 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8669 inst
.instruction
|= inst
.operands
[1].reg
;
8673 do_iwmmxt_wldstbh (void)
8676 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8678 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8680 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8681 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8685 do_iwmmxt_wldstw (void)
8687 /* RIWR_RIWC clears .isreg for a control register. */
8688 if (!inst
.operands
[0].isreg
)
8690 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8691 inst
.instruction
|= 0xf0000000;
8694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8695 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8699 do_iwmmxt_wldstd (void)
8701 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8702 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8703 && inst
.operands
[1].immisreg
)
8705 inst
.instruction
&= ~0x1a000ff;
8706 inst
.instruction
|= (0xf << 28);
8707 if (inst
.operands
[1].preind
)
8708 inst
.instruction
|= PRE_INDEX
;
8709 if (!inst
.operands
[1].negative
)
8710 inst
.instruction
|= INDEX_UP
;
8711 if (inst
.operands
[1].writeback
)
8712 inst
.instruction
|= WRITE_BACK
;
8713 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8714 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8715 inst
.instruction
|= inst
.operands
[1].imm
;
8718 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8722 do_iwmmxt_wshufh (void)
8724 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8725 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8726 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8727 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8731 do_iwmmxt_wzero (void)
8733 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8734 inst
.instruction
|= inst
.operands
[0].reg
;
8735 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8736 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8740 do_iwmmxt_wrwrwr_or_imm5 (void)
8742 if (inst
.operands
[2].isreg
)
8745 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8746 _("immediate operand requires iWMMXt2"));
8748 if (inst
.operands
[2].imm
== 0)
8750 switch ((inst
.instruction
>> 20) & 0xf)
8756 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8757 inst
.operands
[2].imm
= 16;
8758 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8764 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8765 inst
.operands
[2].imm
= 32;
8766 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8773 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8775 wrn
= (inst
.instruction
>> 16) & 0xf;
8776 inst
.instruction
&= 0xff0fff0f;
8777 inst
.instruction
|= wrn
;
8778 /* Bail out here; the instruction is now assembled. */
8783 /* Map 32 -> 0, etc. */
8784 inst
.operands
[2].imm
&= 0x1f;
8785 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8789 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8790 operations first, then control, shift, and load/store. */
8792 /* Insns like "foo X,Y,Z". */
8795 do_mav_triple (void)
8797 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8798 inst
.instruction
|= inst
.operands
[1].reg
;
8799 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8802 /* Insns like "foo W,X,Y,Z".
8803 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8808 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8809 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8810 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8811 inst
.instruction
|= inst
.operands
[3].reg
;
8814 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8818 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8821 /* Maverick shift immediate instructions.
8822 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8823 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8828 int imm
= inst
.operands
[2].imm
;
8830 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8831 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8833 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8834 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8835 Bit 4 should be 0. */
8836 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8838 inst
.instruction
|= imm
;
8841 /* XScale instructions. Also sorted arithmetic before move. */
8843 /* Xscale multiply-accumulate (argument parse)
8846 MIAxycc acc0,Rm,Rs. */
8851 inst
.instruction
|= inst
.operands
[1].reg
;
8852 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8855 /* Xscale move-accumulator-register (argument parse)
8857 MARcc acc0,RdLo,RdHi. */
8862 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8863 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8866 /* Xscale move-register-accumulator (argument parse)
8868 MRAcc RdLo,RdHi,acc0. */
8873 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8875 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8878 /* Encoding functions relevant only to Thumb. */
8880 /* inst.operands[i] is a shifted-register operand; encode
8881 it into inst.instruction in the format used by Thumb32. */
8884 encode_thumb32_shifted_operand (int i
)
8886 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8887 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8889 constraint (inst
.operands
[i
].immisreg
,
8890 _("shift by register not allowed in thumb mode"));
8891 inst
.instruction
|= inst
.operands
[i
].reg
;
8892 if (shift
== SHIFT_RRX
)
8893 inst
.instruction
|= SHIFT_ROR
<< 4;
8896 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8897 _("expression too complex"));
8899 constraint (value
> 32
8900 || (value
== 32 && (shift
== SHIFT_LSL
8901 || shift
== SHIFT_ROR
)),
8902 _("shift expression is too large"));
8906 else if (value
== 32)
8909 inst
.instruction
|= shift
<< 4;
8910 inst
.instruction
|= (value
& 0x1c) << 10;
8911 inst
.instruction
|= (value
& 0x03) << 6;
8916 /* inst.operands[i] was set up by parse_address. Encode it into a
8917 Thumb32 format load or store instruction. Reject forms that cannot
8918 be used with such instructions. If is_t is true, reject forms that
8919 cannot be used with a T instruction; if is_d is true, reject forms
8920 that cannot be used with a D instruction. If it is a store insn,
8924 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8926 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8928 constraint (!inst
.operands
[i
].isreg
,
8929 _("Instruction does not support =N addresses"));
8931 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8932 if (inst
.operands
[i
].immisreg
)
8934 constraint (is_pc
, BAD_PC_ADDRESSING
);
8935 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8936 constraint (inst
.operands
[i
].negative
,
8937 _("Thumb does not support negative register indexing"));
8938 constraint (inst
.operands
[i
].postind
,
8939 _("Thumb does not support register post-indexing"));
8940 constraint (inst
.operands
[i
].writeback
,
8941 _("Thumb does not support register indexing with writeback"));
8942 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8943 _("Thumb supports only LSL in shifted register indexing"));
8945 inst
.instruction
|= inst
.operands
[i
].imm
;
8946 if (inst
.operands
[i
].shifted
)
8948 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8949 _("expression too complex"));
8950 constraint (inst
.reloc
.exp
.X_add_number
< 0
8951 || inst
.reloc
.exp
.X_add_number
> 3,
8952 _("shift out of range"));
8953 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8955 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8957 else if (inst
.operands
[i
].preind
)
8959 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8960 constraint (is_t
&& inst
.operands
[i
].writeback
,
8961 _("cannot use writeback with this instruction"));
8962 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8963 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8967 inst
.instruction
|= 0x01000000;
8968 if (inst
.operands
[i
].writeback
)
8969 inst
.instruction
|= 0x00200000;
8973 inst
.instruction
|= 0x00000c00;
8974 if (inst
.operands
[i
].writeback
)
8975 inst
.instruction
|= 0x00000100;
8977 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8979 else if (inst
.operands
[i
].postind
)
8981 gas_assert (inst
.operands
[i
].writeback
);
8982 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8983 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8986 inst
.instruction
|= 0x00200000;
8988 inst
.instruction
|= 0x00000900;
8989 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8991 else /* unindexed - only for coprocessor */
8992 inst
.error
= _("instruction does not accept unindexed addressing");
8995 /* Table of Thumb instructions which exist in both 16- and 32-bit
8996 encodings (the latter only in post-V6T2 cores). The index is the
8997 value used in the insns table below. When there is more than one
8998 possible 16-bit encoding for the instruction, this table always
9000 Also contains several pseudo-instructions used during relaxation. */
9001 #define T16_32_TAB \
9002 X(_adc, 4140, eb400000), \
9003 X(_adcs, 4140, eb500000), \
9004 X(_add, 1c00, eb000000), \
9005 X(_adds, 1c00, eb100000), \
9006 X(_addi, 0000, f1000000), \
9007 X(_addis, 0000, f1100000), \
9008 X(_add_pc,000f, f20f0000), \
9009 X(_add_sp,000d, f10d0000), \
9010 X(_adr, 000f, f20f0000), \
9011 X(_and, 4000, ea000000), \
9012 X(_ands, 4000, ea100000), \
9013 X(_asr, 1000, fa40f000), \
9014 X(_asrs, 1000, fa50f000), \
9015 X(_b, e000, f000b000), \
9016 X(_bcond, d000, f0008000), \
9017 X(_bic, 4380, ea200000), \
9018 X(_bics, 4380, ea300000), \
9019 X(_cmn, 42c0, eb100f00), \
9020 X(_cmp, 2800, ebb00f00), \
9021 X(_cpsie, b660, f3af8400), \
9022 X(_cpsid, b670, f3af8600), \
9023 X(_cpy, 4600, ea4f0000), \
9024 X(_dec_sp,80dd, f1ad0d00), \
9025 X(_eor, 4040, ea800000), \
9026 X(_eors, 4040, ea900000), \
9027 X(_inc_sp,00dd, f10d0d00), \
9028 X(_ldmia, c800, e8900000), \
9029 X(_ldr, 6800, f8500000), \
9030 X(_ldrb, 7800, f8100000), \
9031 X(_ldrh, 8800, f8300000), \
9032 X(_ldrsb, 5600, f9100000), \
9033 X(_ldrsh, 5e00, f9300000), \
9034 X(_ldr_pc,4800, f85f0000), \
9035 X(_ldr_pc2,4800, f85f0000), \
9036 X(_ldr_sp,9800, f85d0000), \
9037 X(_lsl, 0000, fa00f000), \
9038 X(_lsls, 0000, fa10f000), \
9039 X(_lsr, 0800, fa20f000), \
9040 X(_lsrs, 0800, fa30f000), \
9041 X(_mov, 2000, ea4f0000), \
9042 X(_movs, 2000, ea5f0000), \
9043 X(_mul, 4340, fb00f000), \
9044 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9045 X(_mvn, 43c0, ea6f0000), \
9046 X(_mvns, 43c0, ea7f0000), \
9047 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9048 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9049 X(_orr, 4300, ea400000), \
9050 X(_orrs, 4300, ea500000), \
9051 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9052 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9053 X(_rev, ba00, fa90f080), \
9054 X(_rev16, ba40, fa90f090), \
9055 X(_revsh, bac0, fa90f0b0), \
9056 X(_ror, 41c0, fa60f000), \
9057 X(_rors, 41c0, fa70f000), \
9058 X(_sbc, 4180, eb600000), \
9059 X(_sbcs, 4180, eb700000), \
9060 X(_stmia, c000, e8800000), \
9061 X(_str, 6000, f8400000), \
9062 X(_strb, 7000, f8000000), \
9063 X(_strh, 8000, f8200000), \
9064 X(_str_sp,9000, f84d0000), \
9065 X(_sub, 1e00, eba00000), \
9066 X(_subs, 1e00, ebb00000), \
9067 X(_subi, 8000, f1a00000), \
9068 X(_subis, 8000, f1b00000), \
9069 X(_sxtb, b240, fa4ff080), \
9070 X(_sxth, b200, fa0ff080), \
9071 X(_tst, 4200, ea100f00), \
9072 X(_uxtb, b2c0, fa5ff080), \
9073 X(_uxth, b280, fa1ff080), \
9074 X(_nop, bf00, f3af8000), \
9075 X(_yield, bf10, f3af8001), \
9076 X(_wfe, bf20, f3af8002), \
9077 X(_wfi, bf30, f3af8003), \
9078 X(_sev, bf40, f3af8004),
9080 /* To catch errors in encoding functions, the codes are all offset by
9081 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9082 as 16-bit instructions. */
9083 #define X(a,b,c) T_MNEM##a
9084 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9087 #define X(a,b,c) 0x##b
9088 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9089 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9092 #define X(a,b,c) 0x##c
9093 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9094 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9095 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9099 /* Thumb instruction encoders, in alphabetical order. */
9104 do_t_add_sub_w (void)
9108 Rd
= inst
.operands
[0].reg
;
9109 Rn
= inst
.operands
[1].reg
;
9111 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9112 is the SP-{plus,minus}-immediate form of the instruction. */
9114 constraint (Rd
== REG_PC
, BAD_PC
);
9116 reject_bad_reg (Rd
);
9118 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9119 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9122 /* Parse an add or subtract instruction. We get here with inst.instruction
9123 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9130 Rd
= inst
.operands
[0].reg
;
9131 Rs
= (inst
.operands
[1].present
9132 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9133 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9136 set_it_insn_type_last ();
9144 flags
= (inst
.instruction
== T_MNEM_adds
9145 || inst
.instruction
== T_MNEM_subs
);
9147 narrow
= !in_it_block ();
9149 narrow
= in_it_block ();
9150 if (!inst
.operands
[2].isreg
)
9154 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9156 add
= (inst
.instruction
== T_MNEM_add
9157 || inst
.instruction
== T_MNEM_adds
);
9159 if (inst
.size_req
!= 4)
9161 /* Attempt to use a narrow opcode, with relaxation if
9163 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9164 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9165 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9166 opcode
= T_MNEM_add_sp
;
9167 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9168 opcode
= T_MNEM_add_pc
;
9169 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9172 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9174 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9178 inst
.instruction
= THUMB_OP16(opcode
);
9179 inst
.instruction
|= (Rd
<< 4) | Rs
;
9180 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9181 if (inst
.size_req
!= 2)
9182 inst
.relax
= opcode
;
9185 constraint (inst
.size_req
== 2, BAD_HIREG
);
9187 if (inst
.size_req
== 4
9188 || (inst
.size_req
!= 2 && !opcode
))
9192 constraint (add
, BAD_PC
);
9193 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9194 _("only SUBS PC, LR, #const allowed"));
9195 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9196 _("expression too complex"));
9197 constraint (inst
.reloc
.exp
.X_add_number
< 0
9198 || inst
.reloc
.exp
.X_add_number
> 0xff,
9199 _("immediate value out of range"));
9200 inst
.instruction
= T2_SUBS_PC_LR
9201 | inst
.reloc
.exp
.X_add_number
;
9202 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9205 else if (Rs
== REG_PC
)
9207 /* Always use addw/subw. */
9208 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9209 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9213 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9214 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9217 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9219 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9221 inst
.instruction
|= Rd
<< 8;
9222 inst
.instruction
|= Rs
<< 16;
9227 Rn
= inst
.operands
[2].reg
;
9228 /* See if we can do this with a 16-bit instruction. */
9229 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9231 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9236 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9237 || inst
.instruction
== T_MNEM_add
)
9240 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9244 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9246 /* Thumb-1 cores (except v6-M) require at least one high
9247 register in a narrow non flag setting add. */
9248 if (Rd
> 7 || Rn
> 7
9249 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9250 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9257 inst
.instruction
= T_OPCODE_ADD_HI
;
9258 inst
.instruction
|= (Rd
& 8) << 4;
9259 inst
.instruction
|= (Rd
& 7);
9260 inst
.instruction
|= Rn
<< 3;
9266 constraint (Rd
== REG_PC
, BAD_PC
);
9267 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9268 constraint (Rs
== REG_PC
, BAD_PC
);
9269 reject_bad_reg (Rn
);
9271 /* If we get here, it can't be done in 16 bits. */
9272 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9273 _("shift must be constant"));
9274 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9275 inst
.instruction
|= Rd
<< 8;
9276 inst
.instruction
|= Rs
<< 16;
9277 encode_thumb32_shifted_operand (2);
9282 constraint (inst
.instruction
== T_MNEM_adds
9283 || inst
.instruction
== T_MNEM_subs
,
9286 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9288 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9289 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9292 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9294 inst
.instruction
|= (Rd
<< 4) | Rs
;
9295 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9299 Rn
= inst
.operands
[2].reg
;
9300 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9302 /* We now have Rd, Rs, and Rn set to registers. */
9303 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9305 /* Can't do this for SUB. */
9306 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9307 inst
.instruction
= T_OPCODE_ADD_HI
;
9308 inst
.instruction
|= (Rd
& 8) << 4;
9309 inst
.instruction
|= (Rd
& 7);
9311 inst
.instruction
|= Rn
<< 3;
9313 inst
.instruction
|= Rs
<< 3;
9315 constraint (1, _("dest must overlap one source register"));
9319 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9320 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9321 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9331 Rd
= inst
.operands
[0].reg
;
9332 reject_bad_reg (Rd
);
9334 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9336 /* Defer to section relaxation. */
9337 inst
.relax
= inst
.instruction
;
9338 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9339 inst
.instruction
|= Rd
<< 4;
9341 else if (unified_syntax
&& inst
.size_req
!= 2)
9343 /* Generate a 32-bit opcode. */
9344 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9345 inst
.instruction
|= Rd
<< 8;
9346 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9347 inst
.reloc
.pc_rel
= 1;
9351 /* Generate a 16-bit opcode. */
9352 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9353 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9354 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9355 inst
.reloc
.pc_rel
= 1;
9357 inst
.instruction
|= Rd
<< 4;
9361 /* Arithmetic instructions for which there is just one 16-bit
9362 instruction encoding, and it allows only two low registers.
9363 For maximal compatibility with ARM syntax, we allow three register
9364 operands even when Thumb-32 instructions are not available, as long
9365 as the first two are identical. For instance, both "sbc r0,r1" and
9366 "sbc r0,r0,r1" are allowed. */
9372 Rd
= inst
.operands
[0].reg
;
9373 Rs
= (inst
.operands
[1].present
9374 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9375 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9376 Rn
= inst
.operands
[2].reg
;
9378 reject_bad_reg (Rd
);
9379 reject_bad_reg (Rs
);
9380 if (inst
.operands
[2].isreg
)
9381 reject_bad_reg (Rn
);
9385 if (!inst
.operands
[2].isreg
)
9387 /* For an immediate, we always generate a 32-bit opcode;
9388 section relaxation will shrink it later if possible. */
9389 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9390 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9391 inst
.instruction
|= Rd
<< 8;
9392 inst
.instruction
|= Rs
<< 16;
9393 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9399 /* See if we can do this with a 16-bit instruction. */
9400 if (THUMB_SETS_FLAGS (inst
.instruction
))
9401 narrow
= !in_it_block ();
9403 narrow
= in_it_block ();
9405 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9407 if (inst
.operands
[2].shifted
)
9409 if (inst
.size_req
== 4)
9415 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9416 inst
.instruction
|= Rd
;
9417 inst
.instruction
|= Rn
<< 3;
9421 /* If we get here, it can't be done in 16 bits. */
9422 constraint (inst
.operands
[2].shifted
9423 && inst
.operands
[2].immisreg
,
9424 _("shift must be constant"));
9425 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9426 inst
.instruction
|= Rd
<< 8;
9427 inst
.instruction
|= Rs
<< 16;
9428 encode_thumb32_shifted_operand (2);
9433 /* On its face this is a lie - the instruction does set the
9434 flags. However, the only supported mnemonic in this mode
9436 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9438 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9439 _("unshifted register required"));
9440 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9441 constraint (Rd
!= Rs
,
9442 _("dest and source1 must be the same register"));
9444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9445 inst
.instruction
|= Rd
;
9446 inst
.instruction
|= Rn
<< 3;
9450 /* Similarly, but for instructions where the arithmetic operation is
9451 commutative, so we can allow either of them to be different from
9452 the destination operand in a 16-bit instruction. For instance, all
9453 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9460 Rd
= inst
.operands
[0].reg
;
9461 Rs
= (inst
.operands
[1].present
9462 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9463 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9464 Rn
= inst
.operands
[2].reg
;
9466 reject_bad_reg (Rd
);
9467 reject_bad_reg (Rs
);
9468 if (inst
.operands
[2].isreg
)
9469 reject_bad_reg (Rn
);
9473 if (!inst
.operands
[2].isreg
)
9475 /* For an immediate, we always generate a 32-bit opcode;
9476 section relaxation will shrink it later if possible. */
9477 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9478 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9479 inst
.instruction
|= Rd
<< 8;
9480 inst
.instruction
|= Rs
<< 16;
9481 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9487 /* See if we can do this with a 16-bit instruction. */
9488 if (THUMB_SETS_FLAGS (inst
.instruction
))
9489 narrow
= !in_it_block ();
9491 narrow
= in_it_block ();
9493 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9495 if (inst
.operands
[2].shifted
)
9497 if (inst
.size_req
== 4)
9504 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9505 inst
.instruction
|= Rd
;
9506 inst
.instruction
|= Rn
<< 3;
9511 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9512 inst
.instruction
|= Rd
;
9513 inst
.instruction
|= Rs
<< 3;
9518 /* If we get here, it can't be done in 16 bits. */
9519 constraint (inst
.operands
[2].shifted
9520 && inst
.operands
[2].immisreg
,
9521 _("shift must be constant"));
9522 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9523 inst
.instruction
|= Rd
<< 8;
9524 inst
.instruction
|= Rs
<< 16;
9525 encode_thumb32_shifted_operand (2);
9530 /* On its face this is a lie - the instruction does set the
9531 flags. However, the only supported mnemonic in this mode
9533 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9535 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9536 _("unshifted register required"));
9537 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9539 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9540 inst
.instruction
|= Rd
;
9543 inst
.instruction
|= Rn
<< 3;
9545 inst
.instruction
|= Rs
<< 3;
9547 constraint (1, _("dest must overlap one source register"));
9554 if (inst
.operands
[0].present
)
9556 constraint ((inst
.instruction
& 0xf0) != 0x40
9557 && inst
.operands
[0].imm
> 0xf
9558 && inst
.operands
[0].imm
< 0x0,
9559 _("bad barrier type"));
9560 inst
.instruction
|= inst
.operands
[0].imm
;
9563 inst
.instruction
|= 0xf;
9570 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9571 constraint (msb
> 32, _("bit-field extends past end of register"));
9572 /* The instruction encoding stores the LSB and MSB,
9573 not the LSB and width. */
9574 Rd
= inst
.operands
[0].reg
;
9575 reject_bad_reg (Rd
);
9576 inst
.instruction
|= Rd
<< 8;
9577 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9578 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9579 inst
.instruction
|= msb
- 1;
9588 Rd
= inst
.operands
[0].reg
;
9589 reject_bad_reg (Rd
);
9591 /* #0 in second position is alternative syntax for bfc, which is
9592 the same instruction but with REG_PC in the Rm field. */
9593 if (!inst
.operands
[1].isreg
)
9597 Rn
= inst
.operands
[1].reg
;
9598 reject_bad_reg (Rn
);
9601 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9602 constraint (msb
> 32, _("bit-field extends past end of register"));
9603 /* The instruction encoding stores the LSB and MSB,
9604 not the LSB and width. */
9605 inst
.instruction
|= Rd
<< 8;
9606 inst
.instruction
|= Rn
<< 16;
9607 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9608 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9609 inst
.instruction
|= msb
- 1;
9617 Rd
= inst
.operands
[0].reg
;
9618 Rn
= inst
.operands
[1].reg
;
9620 reject_bad_reg (Rd
);
9621 reject_bad_reg (Rn
);
9623 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9624 _("bit-field extends past end of register"));
9625 inst
.instruction
|= Rd
<< 8;
9626 inst
.instruction
|= Rn
<< 16;
9627 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9628 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9629 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9632 /* ARM V5 Thumb BLX (argument parse)
9633 BLX <target_addr> which is BLX(1)
9634 BLX <Rm> which is BLX(2)
9635 Unfortunately, there are two different opcodes for this mnemonic.
9636 So, the insns[].value is not used, and the code here zaps values
9637 into inst.instruction.
9639 ??? How to take advantage of the additional two bits of displacement
9640 available in Thumb32 mode? Need new relocation? */
9645 set_it_insn_type_last ();
9647 if (inst
.operands
[0].isreg
)
9649 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9650 /* We have a register, so this is BLX(2). */
9651 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9655 /* No register. This must be BLX(1). */
9656 inst
.instruction
= 0xf000e800;
9657 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9658 inst
.reloc
.pc_rel
= 1;
9670 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9674 /* Conditional branches inside IT blocks are encoded as unconditional
9681 if (cond
!= COND_ALWAYS
)
9682 opcode
= T_MNEM_bcond
;
9684 opcode
= inst
.instruction
;
9687 && (inst
.size_req
== 4
9688 || (inst
.size_req
!= 2 && inst
.operands
[0].hasreloc
)))
9690 inst
.instruction
= THUMB_OP32(opcode
);
9691 if (cond
== COND_ALWAYS
)
9692 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9695 gas_assert (cond
!= 0xF);
9696 inst
.instruction
|= cond
<< 22;
9697 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9702 inst
.instruction
= THUMB_OP16(opcode
);
9703 if (cond
== COND_ALWAYS
)
9704 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9707 inst
.instruction
|= cond
<< 8;
9708 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9710 /* Allow section relaxation. */
9711 if (unified_syntax
&& inst
.size_req
!= 2)
9712 inst
.relax
= opcode
;
9714 inst
.reloc
.type
= reloc
;
9715 inst
.reloc
.pc_rel
= 1;
9721 constraint (inst
.cond
!= COND_ALWAYS
,
9722 _("instruction is always unconditional"));
9723 if (inst
.operands
[0].present
)
9725 constraint (inst
.operands
[0].imm
> 255,
9726 _("immediate value out of range"));
9727 inst
.instruction
|= inst
.operands
[0].imm
;
9728 set_it_insn_type (NEUTRAL_IT_INSN
);
9733 do_t_branch23 (void)
9735 set_it_insn_type_last ();
9736 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9737 inst
.reloc
.pc_rel
= 1;
9739 #if defined(OBJ_COFF)
9740 /* If the destination of the branch is a defined symbol which does not have
9741 the THUMB_FUNC attribute, then we must be calling a function which has
9742 the (interfacearm) attribute. We look for the Thumb entry point to that
9743 function and change the branch to refer to that function instead. */
9744 if ( inst
.reloc
.exp
.X_op
== O_symbol
9745 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9746 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9747 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9748 inst
.reloc
.exp
.X_add_symbol
=
9749 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9756 set_it_insn_type_last ();
9757 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9758 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9759 should cause the alignment to be checked once it is known. This is
9760 because BX PC only works if the instruction is word aligned. */
9768 set_it_insn_type_last ();
9769 Rm
= inst
.operands
[0].reg
;
9770 reject_bad_reg (Rm
);
9771 inst
.instruction
|= Rm
<< 16;
9780 Rd
= inst
.operands
[0].reg
;
9781 Rm
= inst
.operands
[1].reg
;
9783 reject_bad_reg (Rd
);
9784 reject_bad_reg (Rm
);
9786 inst
.instruction
|= Rd
<< 8;
9787 inst
.instruction
|= Rm
<< 16;
9788 inst
.instruction
|= Rm
;
9794 set_it_insn_type (OUTSIDE_IT_INSN
);
9795 inst
.instruction
|= inst
.operands
[0].imm
;
9801 set_it_insn_type (OUTSIDE_IT_INSN
);
9803 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9804 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9806 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9807 inst
.instruction
= 0xf3af8000;
9808 inst
.instruction
|= imod
<< 9;
9809 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9810 if (inst
.operands
[1].present
)
9811 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9815 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9816 && (inst
.operands
[0].imm
& 4),
9817 _("selected processor does not support 'A' form "
9818 "of this instruction"));
9819 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9820 _("Thumb does not support the 2-argument "
9821 "form of this instruction"));
9822 inst
.instruction
|= inst
.operands
[0].imm
;
9826 /* THUMB CPY instruction (argument parse). */
9831 if (inst
.size_req
== 4)
9833 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9834 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9835 inst
.instruction
|= inst
.operands
[1].reg
;
9839 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9840 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9841 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9848 set_it_insn_type (OUTSIDE_IT_INSN
);
9849 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9850 inst
.instruction
|= inst
.operands
[0].reg
;
9851 inst
.reloc
.pc_rel
= 1;
9852 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9858 inst
.instruction
|= inst
.operands
[0].imm
;
9864 unsigned Rd
, Rn
, Rm
;
9866 Rd
= inst
.operands
[0].reg
;
9867 Rn
= (inst
.operands
[1].present
9868 ? inst
.operands
[1].reg
: Rd
);
9869 Rm
= inst
.operands
[2].reg
;
9871 reject_bad_reg (Rd
);
9872 reject_bad_reg (Rn
);
9873 reject_bad_reg (Rm
);
9875 inst
.instruction
|= Rd
<< 8;
9876 inst
.instruction
|= Rn
<< 16;
9877 inst
.instruction
|= Rm
;
9883 if (unified_syntax
&& inst
.size_req
== 4)
9884 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9886 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9892 unsigned int cond
= inst
.operands
[0].imm
;
9894 set_it_insn_type (IT_INSN
);
9895 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9898 /* If the condition is a negative condition, invert the mask. */
9899 if ((cond
& 0x1) == 0x0)
9901 unsigned int mask
= inst
.instruction
& 0x000f;
9903 if ((mask
& 0x7) == 0)
9904 /* no conversion needed */;
9905 else if ((mask
& 0x3) == 0)
9907 else if ((mask
& 0x1) == 0)
9912 inst
.instruction
&= 0xfff0;
9913 inst
.instruction
|= mask
;
9916 inst
.instruction
|= cond
<< 4;
9919 /* Helper function used for both push/pop and ldm/stm. */
9921 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9925 load
= (inst
.instruction
& (1 << 20)) != 0;
9927 if (mask
& (1 << 13))
9928 inst
.error
= _("SP not allowed in register list");
9930 if ((mask
& (1 << base
)) != 0
9932 inst
.error
= _("having the base register in the register list when "
9933 "using write back is UNPREDICTABLE");
9937 if (mask
& (1 << 15))
9939 if (mask
& (1 << 14))
9940 inst
.error
= _("LR and PC should not both be in register list");
9942 set_it_insn_type_last ();
9947 if (mask
& (1 << 15))
9948 inst
.error
= _("PC not allowed in register list");
9951 if ((mask
& (mask
- 1)) == 0)
9953 /* Single register transfers implemented as str/ldr. */
9956 if (inst
.instruction
& (1 << 23))
9957 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9959 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9963 if (inst
.instruction
& (1 << 23))
9964 inst
.instruction
= 0x00800000; /* ia -> [base] */
9966 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9969 inst
.instruction
|= 0xf8400000;
9971 inst
.instruction
|= 0x00100000;
9973 mask
= ffs (mask
) - 1;
9977 inst
.instruction
|= WRITE_BACK
;
9979 inst
.instruction
|= mask
;
9980 inst
.instruction
|= base
<< 16;
9986 /* This really doesn't seem worth it. */
9987 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9988 _("expression too complex"));
9989 constraint (inst
.operands
[1].writeback
,
9990 _("Thumb load/store multiple does not support {reglist}^"));
9998 /* See if we can use a 16-bit instruction. */
9999 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10000 && inst
.size_req
!= 4
10001 && !(inst
.operands
[1].imm
& ~0xff))
10003 mask
= 1 << inst
.operands
[0].reg
;
10005 if (inst
.operands
[0].reg
<= 7)
10007 if (inst
.instruction
== T_MNEM_stmia
10008 ? inst
.operands
[0].writeback
10009 : (inst
.operands
[0].writeback
10010 == !(inst
.operands
[1].imm
& mask
)))
10012 if (inst
.instruction
== T_MNEM_stmia
10013 && (inst
.operands
[1].imm
& mask
)
10014 && (inst
.operands
[1].imm
& (mask
- 1)))
10015 as_warn (_("value stored for r%d is UNKNOWN"),
10016 inst
.operands
[0].reg
);
10018 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10019 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10020 inst
.instruction
|= inst
.operands
[1].imm
;
10023 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10025 /* This means 1 register in reg list one of 3 situations:
10026 1. Instruction is stmia, but without writeback.
10027 2. lmdia without writeback, but with Rn not in
10029 3. ldmia with writeback, but with Rn in reglist.
10030 Case 3 is UNPREDICTABLE behaviour, so we handle
10031 case 1 and 2 which can be converted into a 16-bit
10032 str or ldr. The SP cases are handled below. */
10033 unsigned long opcode
;
10034 /* First, record an error for Case 3. */
10035 if (inst
.operands
[1].imm
& mask
10036 && inst
.operands
[0].writeback
)
10038 _("having the base register in the register list when "
10039 "using write back is UNPREDICTABLE");
10041 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10043 inst
.instruction
= THUMB_OP16 (opcode
);
10044 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10045 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10049 else if (inst
.operands
[0] .reg
== REG_SP
)
10051 if (inst
.operands
[0].writeback
)
10054 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10055 ? T_MNEM_push
: T_MNEM_pop
);
10056 inst
.instruction
|= inst
.operands
[1].imm
;
10059 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10062 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10063 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10064 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10072 if (inst
.instruction
< 0xffff)
10073 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10075 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10076 inst
.operands
[0].writeback
);
10081 constraint (inst
.operands
[0].reg
> 7
10082 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10083 constraint (inst
.instruction
!= T_MNEM_ldmia
10084 && inst
.instruction
!= T_MNEM_stmia
,
10085 _("Thumb-2 instruction only valid in unified syntax"));
10086 if (inst
.instruction
== T_MNEM_stmia
)
10088 if (!inst
.operands
[0].writeback
)
10089 as_warn (_("this instruction will write back the base register"));
10090 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10091 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10092 as_warn (_("value stored for r%d is UNKNOWN"),
10093 inst
.operands
[0].reg
);
10097 if (!inst
.operands
[0].writeback
10098 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10099 as_warn (_("this instruction will write back the base register"));
10100 else if (inst
.operands
[0].writeback
10101 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10102 as_warn (_("this instruction will not write back the base register"));
10105 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10106 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10107 inst
.instruction
|= inst
.operands
[1].imm
;
10114 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10115 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10116 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10117 || inst
.operands
[1].negative
,
10120 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10122 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10123 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10124 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10130 if (!inst
.operands
[1].present
)
10132 constraint (inst
.operands
[0].reg
== REG_LR
,
10133 _("r14 not allowed as first register "
10134 "when second register is omitted"));
10135 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10137 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10141 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10142 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10148 unsigned long opcode
;
10151 if (inst
.operands
[0].isreg
10152 && !inst
.operands
[0].preind
10153 && inst
.operands
[0].reg
== REG_PC
)
10154 set_it_insn_type_last ();
10156 opcode
= inst
.instruction
;
10157 if (unified_syntax
)
10159 if (!inst
.operands
[1].isreg
)
10161 if (opcode
<= 0xffff)
10162 inst
.instruction
= THUMB_OP32 (opcode
);
10163 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10166 if (inst
.operands
[1].isreg
10167 && !inst
.operands
[1].writeback
10168 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10169 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10170 && opcode
<= 0xffff
10171 && inst
.size_req
!= 4)
10173 /* Insn may have a 16-bit form. */
10174 Rn
= inst
.operands
[1].reg
;
10175 if (inst
.operands
[1].immisreg
)
10177 inst
.instruction
= THUMB_OP16 (opcode
);
10179 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10181 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10182 reject_bad_reg (inst
.operands
[1].imm
);
10184 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10185 && opcode
!= T_MNEM_ldrsb
)
10186 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10187 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10194 if (inst
.reloc
.pc_rel
)
10195 opcode
= T_MNEM_ldr_pc2
;
10197 opcode
= T_MNEM_ldr_pc
;
10201 if (opcode
== T_MNEM_ldr
)
10202 opcode
= T_MNEM_ldr_sp
;
10204 opcode
= T_MNEM_str_sp
;
10206 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10210 inst
.instruction
= inst
.operands
[0].reg
;
10211 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10213 inst
.instruction
|= THUMB_OP16 (opcode
);
10214 if (inst
.size_req
== 2)
10215 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10217 inst
.relax
= opcode
;
10221 /* Definitely a 32-bit variant. */
10223 /* Do some validations regarding addressing modes. */
10224 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10225 && opcode
!= T_MNEM_str
)
10226 reject_bad_reg (inst
.operands
[1].imm
);
10228 inst
.instruction
= THUMB_OP32 (opcode
);
10229 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10230 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10234 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10236 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10238 /* Only [Rn,Rm] is acceptable. */
10239 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10240 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10241 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10242 || inst
.operands
[1].negative
,
10243 _("Thumb does not support this addressing mode"));
10244 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10248 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10249 if (!inst
.operands
[1].isreg
)
10250 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10253 constraint (!inst
.operands
[1].preind
10254 || inst
.operands
[1].shifted
10255 || inst
.operands
[1].writeback
,
10256 _("Thumb does not support this addressing mode"));
10257 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10259 constraint (inst
.instruction
& 0x0600,
10260 _("byte or halfword not valid for base register"));
10261 constraint (inst
.operands
[1].reg
== REG_PC
10262 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10263 _("r15 based store not allowed"));
10264 constraint (inst
.operands
[1].immisreg
,
10265 _("invalid base register for register offset"));
10267 if (inst
.operands
[1].reg
== REG_PC
)
10268 inst
.instruction
= T_OPCODE_LDR_PC
;
10269 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10270 inst
.instruction
= T_OPCODE_LDR_SP
;
10272 inst
.instruction
= T_OPCODE_STR_SP
;
10274 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10275 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10279 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10280 if (!inst
.operands
[1].immisreg
)
10282 /* Immediate offset. */
10283 inst
.instruction
|= inst
.operands
[0].reg
;
10284 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10285 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10289 /* Register offset. */
10290 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10291 constraint (inst
.operands
[1].negative
,
10292 _("Thumb does not support this addressing mode"));
10295 switch (inst
.instruction
)
10297 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10298 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10299 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10300 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10301 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10302 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10303 case 0x5600 /* ldrsb */:
10304 case 0x5e00 /* ldrsh */: break;
10308 inst
.instruction
|= inst
.operands
[0].reg
;
10309 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10310 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10316 if (!inst
.operands
[1].present
)
10318 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10319 constraint (inst
.operands
[0].reg
== REG_LR
,
10320 _("r14 not allowed here"));
10322 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10323 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10324 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10330 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10331 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10337 unsigned Rd
, Rn
, Rm
, Ra
;
10339 Rd
= inst
.operands
[0].reg
;
10340 Rn
= inst
.operands
[1].reg
;
10341 Rm
= inst
.operands
[2].reg
;
10342 Ra
= inst
.operands
[3].reg
;
10344 reject_bad_reg (Rd
);
10345 reject_bad_reg (Rn
);
10346 reject_bad_reg (Rm
);
10347 reject_bad_reg (Ra
);
10349 inst
.instruction
|= Rd
<< 8;
10350 inst
.instruction
|= Rn
<< 16;
10351 inst
.instruction
|= Rm
;
10352 inst
.instruction
|= Ra
<< 12;
10358 unsigned RdLo
, RdHi
, Rn
, Rm
;
10360 RdLo
= inst
.operands
[0].reg
;
10361 RdHi
= inst
.operands
[1].reg
;
10362 Rn
= inst
.operands
[2].reg
;
10363 Rm
= inst
.operands
[3].reg
;
10365 reject_bad_reg (RdLo
);
10366 reject_bad_reg (RdHi
);
10367 reject_bad_reg (Rn
);
10368 reject_bad_reg (Rm
);
10370 inst
.instruction
|= RdLo
<< 12;
10371 inst
.instruction
|= RdHi
<< 8;
10372 inst
.instruction
|= Rn
<< 16;
10373 inst
.instruction
|= Rm
;
10377 do_t_mov_cmp (void)
10381 Rn
= inst
.operands
[0].reg
;
10382 Rm
= inst
.operands
[1].reg
;
10385 set_it_insn_type_last ();
10387 if (unified_syntax
)
10389 int r0off
= (inst
.instruction
== T_MNEM_mov
10390 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10391 unsigned long opcode
;
10392 bfd_boolean narrow
;
10393 bfd_boolean low_regs
;
10395 low_regs
= (Rn
<= 7 && Rm
<= 7);
10396 opcode
= inst
.instruction
;
10397 if (in_it_block ())
10398 narrow
= opcode
!= T_MNEM_movs
;
10400 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10401 if (inst
.size_req
== 4
10402 || inst
.operands
[1].shifted
)
10405 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10406 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10407 && !inst
.operands
[1].shifted
10411 inst
.instruction
= T2_SUBS_PC_LR
;
10415 if (opcode
== T_MNEM_cmp
)
10417 constraint (Rn
== REG_PC
, BAD_PC
);
10420 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10422 warn_deprecated_sp (Rm
);
10423 /* R15 was documented as a valid choice for Rm in ARMv6,
10424 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10425 tools reject R15, so we do too. */
10426 constraint (Rm
== REG_PC
, BAD_PC
);
10429 reject_bad_reg (Rm
);
10431 else if (opcode
== T_MNEM_mov
10432 || opcode
== T_MNEM_movs
)
10434 if (inst
.operands
[1].isreg
)
10436 if (opcode
== T_MNEM_movs
)
10438 reject_bad_reg (Rn
);
10439 reject_bad_reg (Rm
);
10443 /* This is mov.n. */
10444 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10445 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10447 as_warn (_("Use of r%u as a source register is "
10448 "deprecated when r%u is the destination "
10449 "register."), Rm
, Rn
);
10454 /* This is mov.w. */
10455 constraint (Rn
== REG_PC
, BAD_PC
);
10456 constraint (Rm
== REG_PC
, BAD_PC
);
10457 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10461 reject_bad_reg (Rn
);
10464 if (!inst
.operands
[1].isreg
)
10466 /* Immediate operand. */
10467 if (!in_it_block () && opcode
== T_MNEM_mov
)
10469 if (low_regs
&& narrow
)
10471 inst
.instruction
= THUMB_OP16 (opcode
);
10472 inst
.instruction
|= Rn
<< 8;
10473 if (inst
.size_req
== 2)
10474 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10476 inst
.relax
= opcode
;
10480 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10481 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10482 inst
.instruction
|= Rn
<< r0off
;
10483 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10486 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10487 && (inst
.instruction
== T_MNEM_mov
10488 || inst
.instruction
== T_MNEM_movs
))
10490 /* Register shifts are encoded as separate shift instructions. */
10491 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10493 if (in_it_block ())
10498 if (inst
.size_req
== 4)
10501 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10507 switch (inst
.operands
[1].shift_kind
)
10510 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10513 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10516 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10519 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10525 inst
.instruction
= opcode
;
10528 inst
.instruction
|= Rn
;
10529 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10534 inst
.instruction
|= CONDS_BIT
;
10536 inst
.instruction
|= Rn
<< 8;
10537 inst
.instruction
|= Rm
<< 16;
10538 inst
.instruction
|= inst
.operands
[1].imm
;
10543 /* Some mov with immediate shift have narrow variants.
10544 Register shifts are handled above. */
10545 if (low_regs
&& inst
.operands
[1].shifted
10546 && (inst
.instruction
== T_MNEM_mov
10547 || inst
.instruction
== T_MNEM_movs
))
10549 if (in_it_block ())
10550 narrow
= (inst
.instruction
== T_MNEM_mov
);
10552 narrow
= (inst
.instruction
== T_MNEM_movs
);
10557 switch (inst
.operands
[1].shift_kind
)
10559 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10560 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10561 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10562 default: narrow
= FALSE
; break;
10568 inst
.instruction
|= Rn
;
10569 inst
.instruction
|= Rm
<< 3;
10570 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10574 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10575 inst
.instruction
|= Rn
<< r0off
;
10576 encode_thumb32_shifted_operand (1);
10580 switch (inst
.instruction
)
10583 inst
.instruction
= T_OPCODE_MOV_HR
;
10584 inst
.instruction
|= (Rn
& 0x8) << 4;
10585 inst
.instruction
|= (Rn
& 0x7);
10586 inst
.instruction
|= Rm
<< 3;
10590 /* We know we have low registers at this point.
10591 Generate LSLS Rd, Rs, #0. */
10592 inst
.instruction
= T_OPCODE_LSL_I
;
10593 inst
.instruction
|= Rn
;
10594 inst
.instruction
|= Rm
<< 3;
10600 inst
.instruction
= T_OPCODE_CMP_LR
;
10601 inst
.instruction
|= Rn
;
10602 inst
.instruction
|= Rm
<< 3;
10606 inst
.instruction
= T_OPCODE_CMP_HR
;
10607 inst
.instruction
|= (Rn
& 0x8) << 4;
10608 inst
.instruction
|= (Rn
& 0x7);
10609 inst
.instruction
|= Rm
<< 3;
10616 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10618 /* PR 10443: Do not silently ignore shifted operands. */
10619 constraint (inst
.operands
[1].shifted
,
10620 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10622 if (inst
.operands
[1].isreg
)
10624 if (Rn
< 8 && Rm
< 8)
10626 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10627 since a MOV instruction produces unpredictable results. */
10628 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10629 inst
.instruction
= T_OPCODE_ADD_I3
;
10631 inst
.instruction
= T_OPCODE_CMP_LR
;
10633 inst
.instruction
|= Rn
;
10634 inst
.instruction
|= Rm
<< 3;
10638 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10639 inst
.instruction
= T_OPCODE_MOV_HR
;
10641 inst
.instruction
= T_OPCODE_CMP_HR
;
10647 constraint (Rn
> 7,
10648 _("only lo regs allowed with immediate"));
10649 inst
.instruction
|= Rn
<< 8;
10650 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10661 top
= (inst
.instruction
& 0x00800000) != 0;
10662 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10664 constraint (top
, _(":lower16: not allowed this instruction"));
10665 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10667 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10669 constraint (!top
, _(":upper16: not allowed this instruction"));
10670 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10673 Rd
= inst
.operands
[0].reg
;
10674 reject_bad_reg (Rd
);
10676 inst
.instruction
|= Rd
<< 8;
10677 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10679 imm
= inst
.reloc
.exp
.X_add_number
;
10680 inst
.instruction
|= (imm
& 0xf000) << 4;
10681 inst
.instruction
|= (imm
& 0x0800) << 15;
10682 inst
.instruction
|= (imm
& 0x0700) << 4;
10683 inst
.instruction
|= (imm
& 0x00ff);
10688 do_t_mvn_tst (void)
10692 Rn
= inst
.operands
[0].reg
;
10693 Rm
= inst
.operands
[1].reg
;
10695 if (inst
.instruction
== T_MNEM_cmp
10696 || inst
.instruction
== T_MNEM_cmn
)
10697 constraint (Rn
== REG_PC
, BAD_PC
);
10699 reject_bad_reg (Rn
);
10700 reject_bad_reg (Rm
);
10702 if (unified_syntax
)
10704 int r0off
= (inst
.instruction
== T_MNEM_mvn
10705 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10706 bfd_boolean narrow
;
10708 if (inst
.size_req
== 4
10709 || inst
.instruction
> 0xffff
10710 || inst
.operands
[1].shifted
10711 || Rn
> 7 || Rm
> 7)
10713 else if (inst
.instruction
== T_MNEM_cmn
)
10715 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10716 narrow
= !in_it_block ();
10718 narrow
= in_it_block ();
10720 if (!inst
.operands
[1].isreg
)
10722 /* For an immediate, we always generate a 32-bit opcode;
10723 section relaxation will shrink it later if possible. */
10724 if (inst
.instruction
< 0xffff)
10725 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10726 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10727 inst
.instruction
|= Rn
<< r0off
;
10728 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10732 /* See if we can do this with a 16-bit instruction. */
10735 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10736 inst
.instruction
|= Rn
;
10737 inst
.instruction
|= Rm
<< 3;
10741 constraint (inst
.operands
[1].shifted
10742 && inst
.operands
[1].immisreg
,
10743 _("shift must be constant"));
10744 if (inst
.instruction
< 0xffff)
10745 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10746 inst
.instruction
|= Rn
<< r0off
;
10747 encode_thumb32_shifted_operand (1);
10753 constraint (inst
.instruction
> 0xffff
10754 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10755 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10756 _("unshifted register required"));
10757 constraint (Rn
> 7 || Rm
> 7,
10760 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10761 inst
.instruction
|= Rn
;
10762 inst
.instruction
|= Rm
<< 3;
10771 if (do_vfp_nsyn_mrs () == SUCCESS
)
10774 Rd
= inst
.operands
[0].reg
;
10775 reject_bad_reg (Rd
);
10776 inst
.instruction
|= Rd
<< 8;
10778 if (inst
.operands
[1].isreg
)
10780 unsigned br
= inst
.operands
[1].reg
;
10781 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
10782 as_bad (_("bad register for mrs"));
10784 inst
.instruction
|= br
& (0xf << 16);
10785 inst
.instruction
|= (br
& 0x300) >> 4;
10786 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
10790 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10794 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10795 _("selected processor does not support "
10796 "requested special purpose register"));
10800 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10801 _("selected processor does not support "
10802 "requested special purpose register"));
10803 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10804 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10805 _("'CPSR' or 'SPSR' expected"));
10808 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10809 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10810 inst
.instruction
|= 0xf0000;
10820 if (do_vfp_nsyn_msr () == SUCCESS
)
10823 constraint (!inst
.operands
[1].isreg
,
10824 _("Thumb encoding does not support an immediate here"));
10826 if (inst
.operands
[0].isreg
)
10827 flags
= (int)(inst
.operands
[0].reg
);
10829 flags
= inst
.operands
[0].imm
;
10833 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10834 _("selected processor does not support "
10835 "requested special purpose register"));
10839 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10840 _("selected processor does not support "
10841 "requested special purpose register"));
10845 Rn
= inst
.operands
[1].reg
;
10846 reject_bad_reg (Rn
);
10848 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10849 inst
.instruction
|= (flags
& 0xf0000) >> 8;
10850 inst
.instruction
|= (flags
& 0x300) >> 4;
10851 inst
.instruction
|= (flags
& 0xff);
10852 inst
.instruction
|= Rn
<< 16;
10858 bfd_boolean narrow
;
10859 unsigned Rd
, Rn
, Rm
;
10861 if (!inst
.operands
[2].present
)
10862 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10864 Rd
= inst
.operands
[0].reg
;
10865 Rn
= inst
.operands
[1].reg
;
10866 Rm
= inst
.operands
[2].reg
;
10868 if (unified_syntax
)
10870 if (inst
.size_req
== 4
10876 else if (inst
.instruction
== T_MNEM_muls
)
10877 narrow
= !in_it_block ();
10879 narrow
= in_it_block ();
10883 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10884 constraint (Rn
> 7 || Rm
> 7,
10891 /* 16-bit MULS/Conditional MUL. */
10892 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10893 inst
.instruction
|= Rd
;
10896 inst
.instruction
|= Rm
<< 3;
10898 inst
.instruction
|= Rn
<< 3;
10900 constraint (1, _("dest must overlap one source register"));
10904 constraint (inst
.instruction
!= T_MNEM_mul
,
10905 _("Thumb-2 MUL must not set flags"));
10907 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10908 inst
.instruction
|= Rd
<< 8;
10909 inst
.instruction
|= Rn
<< 16;
10910 inst
.instruction
|= Rm
<< 0;
10912 reject_bad_reg (Rd
);
10913 reject_bad_reg (Rn
);
10914 reject_bad_reg (Rm
);
10921 unsigned RdLo
, RdHi
, Rn
, Rm
;
10923 RdLo
= inst
.operands
[0].reg
;
10924 RdHi
= inst
.operands
[1].reg
;
10925 Rn
= inst
.operands
[2].reg
;
10926 Rm
= inst
.operands
[3].reg
;
10928 reject_bad_reg (RdLo
);
10929 reject_bad_reg (RdHi
);
10930 reject_bad_reg (Rn
);
10931 reject_bad_reg (Rm
);
10933 inst
.instruction
|= RdLo
<< 12;
10934 inst
.instruction
|= RdHi
<< 8;
10935 inst
.instruction
|= Rn
<< 16;
10936 inst
.instruction
|= Rm
;
10939 as_tsktsk (_("rdhi and rdlo must be different"));
10945 set_it_insn_type (NEUTRAL_IT_INSN
);
10947 if (unified_syntax
)
10949 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10951 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10952 inst
.instruction
|= inst
.operands
[0].imm
;
10956 /* PR9722: Check for Thumb2 availability before
10957 generating a thumb2 nop instruction. */
10958 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10960 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10961 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10964 inst
.instruction
= 0x46c0;
10969 constraint (inst
.operands
[0].present
,
10970 _("Thumb does not support NOP with hints"));
10971 inst
.instruction
= 0x46c0;
10978 if (unified_syntax
)
10980 bfd_boolean narrow
;
10982 if (THUMB_SETS_FLAGS (inst
.instruction
))
10983 narrow
= !in_it_block ();
10985 narrow
= in_it_block ();
10986 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10988 if (inst
.size_req
== 4)
10993 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10994 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10995 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10999 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11000 inst
.instruction
|= inst
.operands
[0].reg
;
11001 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11006 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11008 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11010 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11011 inst
.instruction
|= inst
.operands
[0].reg
;
11012 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11021 Rd
= inst
.operands
[0].reg
;
11022 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11024 reject_bad_reg (Rd
);
11025 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11026 reject_bad_reg (Rn
);
11028 inst
.instruction
|= Rd
<< 8;
11029 inst
.instruction
|= Rn
<< 16;
11031 if (!inst
.operands
[2].isreg
)
11033 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11034 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11040 Rm
= inst
.operands
[2].reg
;
11041 reject_bad_reg (Rm
);
11043 constraint (inst
.operands
[2].shifted
11044 && inst
.operands
[2].immisreg
,
11045 _("shift must be constant"));
11046 encode_thumb32_shifted_operand (2);
11053 unsigned Rd
, Rn
, Rm
;
11055 Rd
= inst
.operands
[0].reg
;
11056 Rn
= inst
.operands
[1].reg
;
11057 Rm
= inst
.operands
[2].reg
;
11059 reject_bad_reg (Rd
);
11060 reject_bad_reg (Rn
);
11061 reject_bad_reg (Rm
);
11063 inst
.instruction
|= Rd
<< 8;
11064 inst
.instruction
|= Rn
<< 16;
11065 inst
.instruction
|= Rm
;
11066 if (inst
.operands
[3].present
)
11068 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11069 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11070 _("expression too complex"));
11071 inst
.instruction
|= (val
& 0x1c) << 10;
11072 inst
.instruction
|= (val
& 0x03) << 6;
11079 if (!inst
.operands
[3].present
)
11083 inst
.instruction
&= ~0x00000020;
11085 /* PR 10168. Swap the Rm and Rn registers. */
11086 Rtmp
= inst
.operands
[1].reg
;
11087 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11088 inst
.operands
[2].reg
= Rtmp
;
11096 if (inst
.operands
[0].immisreg
)
11097 reject_bad_reg (inst
.operands
[0].imm
);
11099 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11103 do_t_push_pop (void)
11107 constraint (inst
.operands
[0].writeback
,
11108 _("push/pop do not support {reglist}^"));
11109 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11110 _("expression too complex"));
11112 mask
= inst
.operands
[0].imm
;
11113 if ((mask
& ~0xff) == 0)
11114 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11115 else if ((inst
.instruction
== T_MNEM_push
11116 && (mask
& ~0xff) == 1 << REG_LR
)
11117 || (inst
.instruction
== T_MNEM_pop
11118 && (mask
& ~0xff) == 1 << REG_PC
))
11120 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11121 inst
.instruction
|= THUMB_PP_PC_LR
;
11122 inst
.instruction
|= mask
& 0xff;
11124 else if (unified_syntax
)
11126 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11127 encode_thumb2_ldmstm (13, mask
, TRUE
);
11131 inst
.error
= _("invalid register list to push/pop instruction");
11141 Rd
= inst
.operands
[0].reg
;
11142 Rm
= inst
.operands
[1].reg
;
11144 reject_bad_reg (Rd
);
11145 reject_bad_reg (Rm
);
11147 inst
.instruction
|= Rd
<< 8;
11148 inst
.instruction
|= Rm
<< 16;
11149 inst
.instruction
|= Rm
;
11157 Rd
= inst
.operands
[0].reg
;
11158 Rm
= inst
.operands
[1].reg
;
11160 reject_bad_reg (Rd
);
11161 reject_bad_reg (Rm
);
11163 if (Rd
<= 7 && Rm
<= 7
11164 && inst
.size_req
!= 4)
11166 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11167 inst
.instruction
|= Rd
;
11168 inst
.instruction
|= Rm
<< 3;
11170 else if (unified_syntax
)
11172 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11173 inst
.instruction
|= Rd
<< 8;
11174 inst
.instruction
|= Rm
<< 16;
11175 inst
.instruction
|= Rm
;
11178 inst
.error
= BAD_HIREG
;
11186 Rd
= inst
.operands
[0].reg
;
11187 Rm
= inst
.operands
[1].reg
;
11189 reject_bad_reg (Rd
);
11190 reject_bad_reg (Rm
);
11192 inst
.instruction
|= Rd
<< 8;
11193 inst
.instruction
|= Rm
;
11201 Rd
= inst
.operands
[0].reg
;
11202 Rs
= (inst
.operands
[1].present
11203 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11204 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11206 reject_bad_reg (Rd
);
11207 reject_bad_reg (Rs
);
11208 if (inst
.operands
[2].isreg
)
11209 reject_bad_reg (inst
.operands
[2].reg
);
11211 inst
.instruction
|= Rd
<< 8;
11212 inst
.instruction
|= Rs
<< 16;
11213 if (!inst
.operands
[2].isreg
)
11215 bfd_boolean narrow
;
11217 if ((inst
.instruction
& 0x00100000) != 0)
11218 narrow
= !in_it_block ();
11220 narrow
= in_it_block ();
11222 if (Rd
> 7 || Rs
> 7)
11225 if (inst
.size_req
== 4 || !unified_syntax
)
11228 if (inst
.reloc
.exp
.X_op
!= O_constant
11229 || inst
.reloc
.exp
.X_add_number
!= 0)
11232 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11233 relaxation, but it doesn't seem worth the hassle. */
11236 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11237 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11238 inst
.instruction
|= Rs
<< 3;
11239 inst
.instruction
|= Rd
;
11243 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11244 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11248 encode_thumb32_shifted_operand (2);
11254 set_it_insn_type (OUTSIDE_IT_INSN
);
11255 if (inst
.operands
[0].imm
)
11256 inst
.instruction
|= 0x8;
11262 if (!inst
.operands
[1].present
)
11263 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11265 if (unified_syntax
)
11267 bfd_boolean narrow
;
11270 switch (inst
.instruction
)
11273 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11275 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11277 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11279 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11283 if (THUMB_SETS_FLAGS (inst
.instruction
))
11284 narrow
= !in_it_block ();
11286 narrow
= in_it_block ();
11287 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11289 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11291 if (inst
.operands
[2].isreg
11292 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11293 || inst
.operands
[2].reg
> 7))
11295 if (inst
.size_req
== 4)
11298 reject_bad_reg (inst
.operands
[0].reg
);
11299 reject_bad_reg (inst
.operands
[1].reg
);
11303 if (inst
.operands
[2].isreg
)
11305 reject_bad_reg (inst
.operands
[2].reg
);
11306 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11307 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11308 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11309 inst
.instruction
|= inst
.operands
[2].reg
;
11313 inst
.operands
[1].shifted
= 1;
11314 inst
.operands
[1].shift_kind
= shift_kind
;
11315 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11316 ? T_MNEM_movs
: T_MNEM_mov
);
11317 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11318 encode_thumb32_shifted_operand (1);
11319 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11320 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11325 if (inst
.operands
[2].isreg
)
11327 switch (shift_kind
)
11329 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11330 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11331 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11332 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11336 inst
.instruction
|= inst
.operands
[0].reg
;
11337 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11341 switch (shift_kind
)
11343 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11344 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11345 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11348 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11349 inst
.instruction
|= inst
.operands
[0].reg
;
11350 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11356 constraint (inst
.operands
[0].reg
> 7
11357 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11358 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11360 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11362 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11363 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11364 _("source1 and dest must be same register"));
11366 switch (inst
.instruction
)
11368 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11369 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11370 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11371 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11375 inst
.instruction
|= inst
.operands
[0].reg
;
11376 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11380 switch (inst
.instruction
)
11382 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11383 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11384 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11385 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11388 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11389 inst
.instruction
|= inst
.operands
[0].reg
;
11390 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11398 unsigned Rd
, Rn
, Rm
;
11400 Rd
= inst
.operands
[0].reg
;
11401 Rn
= inst
.operands
[1].reg
;
11402 Rm
= inst
.operands
[2].reg
;
11404 reject_bad_reg (Rd
);
11405 reject_bad_reg (Rn
);
11406 reject_bad_reg (Rm
);
11408 inst
.instruction
|= Rd
<< 8;
11409 inst
.instruction
|= Rn
<< 16;
11410 inst
.instruction
|= Rm
;
11416 unsigned Rd
, Rn
, Rm
;
11418 Rd
= inst
.operands
[0].reg
;
11419 Rm
= inst
.operands
[1].reg
;
11420 Rn
= inst
.operands
[2].reg
;
11422 reject_bad_reg (Rd
);
11423 reject_bad_reg (Rn
);
11424 reject_bad_reg (Rm
);
11426 inst
.instruction
|= Rd
<< 8;
11427 inst
.instruction
|= Rn
<< 16;
11428 inst
.instruction
|= Rm
;
11434 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11435 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11436 _("SMC is not permitted on this architecture"));
11437 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11438 _("expression too complex"));
11439 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11440 inst
.instruction
|= (value
& 0xf000) >> 12;
11441 inst
.instruction
|= (value
& 0x0ff0);
11442 inst
.instruction
|= (value
& 0x000f) << 16;
11448 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11450 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11451 inst
.instruction
|= (value
& 0x0fff);
11452 inst
.instruction
|= (value
& 0xf000) << 4;
11456 do_t_ssat_usat (int bias
)
11460 Rd
= inst
.operands
[0].reg
;
11461 Rn
= inst
.operands
[2].reg
;
11463 reject_bad_reg (Rd
);
11464 reject_bad_reg (Rn
);
11466 inst
.instruction
|= Rd
<< 8;
11467 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11468 inst
.instruction
|= Rn
<< 16;
11470 if (inst
.operands
[3].present
)
11472 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11474 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11476 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11477 _("expression too complex"));
11479 if (shift_amount
!= 0)
11481 constraint (shift_amount
> 31,
11482 _("shift expression is too large"));
11484 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11485 inst
.instruction
|= 0x00200000; /* sh bit. */
11487 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11488 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11496 do_t_ssat_usat (1);
11504 Rd
= inst
.operands
[0].reg
;
11505 Rn
= inst
.operands
[2].reg
;
11507 reject_bad_reg (Rd
);
11508 reject_bad_reg (Rn
);
11510 inst
.instruction
|= Rd
<< 8;
11511 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11512 inst
.instruction
|= Rn
<< 16;
11518 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11519 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11520 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11521 || inst
.operands
[2].negative
,
11524 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11526 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11527 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11528 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11529 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11535 if (!inst
.operands
[2].present
)
11536 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11538 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11539 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11540 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11543 inst
.instruction
|= inst
.operands
[0].reg
;
11544 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11545 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11546 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11552 unsigned Rd
, Rn
, Rm
;
11554 Rd
= inst
.operands
[0].reg
;
11555 Rn
= inst
.operands
[1].reg
;
11556 Rm
= inst
.operands
[2].reg
;
11558 reject_bad_reg (Rd
);
11559 reject_bad_reg (Rn
);
11560 reject_bad_reg (Rm
);
11562 inst
.instruction
|= Rd
<< 8;
11563 inst
.instruction
|= Rn
<< 16;
11564 inst
.instruction
|= Rm
;
11565 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11573 Rd
= inst
.operands
[0].reg
;
11574 Rm
= inst
.operands
[1].reg
;
11576 reject_bad_reg (Rd
);
11577 reject_bad_reg (Rm
);
11579 if (inst
.instruction
<= 0xffff
11580 && inst
.size_req
!= 4
11581 && Rd
<= 7 && Rm
<= 7
11582 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11584 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11585 inst
.instruction
|= Rd
;
11586 inst
.instruction
|= Rm
<< 3;
11588 else if (unified_syntax
)
11590 if (inst
.instruction
<= 0xffff)
11591 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11592 inst
.instruction
|= Rd
<< 8;
11593 inst
.instruction
|= Rm
;
11594 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11598 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11599 _("Thumb encoding does not support rotation"));
11600 constraint (1, BAD_HIREG
);
11607 /* We have to do the following check manually as ARM_EXT_OS only applies
11609 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11611 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
))
11612 as_bad (_("SVC is not permitted on this architecture"));
11613 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11616 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11625 half
= (inst
.instruction
& 0x10) != 0;
11626 set_it_insn_type_last ();
11627 constraint (inst
.operands
[0].immisreg
,
11628 _("instruction requires register index"));
11630 Rn
= inst
.operands
[0].reg
;
11631 Rm
= inst
.operands
[0].imm
;
11633 constraint (Rn
== REG_SP
, BAD_SP
);
11634 reject_bad_reg (Rm
);
11636 constraint (!half
&& inst
.operands
[0].shifted
,
11637 _("instruction does not allow shifted index"));
11638 inst
.instruction
|= (Rn
<< 16) | Rm
;
11644 do_t_ssat_usat (0);
11652 Rd
= inst
.operands
[0].reg
;
11653 Rn
= inst
.operands
[2].reg
;
11655 reject_bad_reg (Rd
);
11656 reject_bad_reg (Rn
);
11658 inst
.instruction
|= Rd
<< 8;
11659 inst
.instruction
|= inst
.operands
[1].imm
;
11660 inst
.instruction
|= Rn
<< 16;
11663 /* Neon instruction encoder helpers. */
11665 /* Encodings for the different types for various Neon opcodes. */
11667 /* An "invalid" code for the following tables. */
11670 struct neon_tab_entry
11673 unsigned float_or_poly
;
11674 unsigned scalar_or_imm
;
11677 /* Map overloaded Neon opcodes to their respective encodings. */
11678 #define NEON_ENC_TAB \
11679 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11680 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11681 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11682 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11683 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11684 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11685 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11686 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11687 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11688 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11689 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11690 /* Register variants of the following two instructions are encoded as
11691 vcge / vcgt with the operands reversed. */ \
11692 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11693 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11694 X(vfma, N_INV, 0x0000c10, N_INV), \
11695 X(vfms, N_INV, 0x0200c10, N_INV), \
11696 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11697 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11698 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11699 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11700 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11701 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11702 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11703 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11704 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11705 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11706 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11707 X(vshl, 0x0000400, N_INV, 0x0800510), \
11708 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11709 X(vand, 0x0000110, N_INV, 0x0800030), \
11710 X(vbic, 0x0100110, N_INV, 0x0800030), \
11711 X(veor, 0x1000110, N_INV, N_INV), \
11712 X(vorn, 0x0300110, N_INV, 0x0800010), \
11713 X(vorr, 0x0200110, N_INV, 0x0800010), \
11714 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11715 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11716 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11717 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11718 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11719 X(vst1, 0x0000000, 0x0800000, N_INV), \
11720 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11721 X(vst2, 0x0000100, 0x0800100, N_INV), \
11722 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11723 X(vst3, 0x0000200, 0x0800200, N_INV), \
11724 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11725 X(vst4, 0x0000300, 0x0800300, N_INV), \
11726 X(vmovn, 0x1b20200, N_INV, N_INV), \
11727 X(vtrn, 0x1b20080, N_INV, N_INV), \
11728 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11729 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11730 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11731 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11732 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11733 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11734 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11735 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11736 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11737 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11738 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11742 #define X(OPC,I,F,S) N_MNEM_##OPC
11747 static const struct neon_tab_entry neon_enc_tab
[] =
11749 #define X(OPC,I,F,S) { (I), (F), (S) }
11754 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11755 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11756 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11757 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11758 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11759 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11760 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11761 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11762 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11763 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11764 #define NEON_ENC_SINGLE_(X) \
11765 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11766 #define NEON_ENC_DOUBLE_(X) \
11767 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11769 #define NEON_ENCODE(type, inst) \
11772 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11773 inst.is_neon = 1; \
11777 #define check_neon_suffixes \
11780 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11782 as_bad (_("invalid neon suffix for non neon instruction")); \
11788 /* Define shapes for instruction operands. The following mnemonic characters
11789 are used in this table:
11791 F - VFP S<n> register
11792 D - Neon D<n> register
11793 Q - Neon Q<n> register
11797 L - D<n> register list
11799 This table is used to generate various data:
11800 - enumerations of the form NS_DDR to be used as arguments to
11802 - a table classifying shapes into single, double, quad, mixed.
11803 - a table used to drive neon_select_shape. */
11805 #define NEON_SHAPE_DEF \
11806 X(3, (D, D, D), DOUBLE), \
11807 X(3, (Q, Q, Q), QUAD), \
11808 X(3, (D, D, I), DOUBLE), \
11809 X(3, (Q, Q, I), QUAD), \
11810 X(3, (D, D, S), DOUBLE), \
11811 X(3, (Q, Q, S), QUAD), \
11812 X(2, (D, D), DOUBLE), \
11813 X(2, (Q, Q), QUAD), \
11814 X(2, (D, S), DOUBLE), \
11815 X(2, (Q, S), QUAD), \
11816 X(2, (D, R), DOUBLE), \
11817 X(2, (Q, R), QUAD), \
11818 X(2, (D, I), DOUBLE), \
11819 X(2, (Q, I), QUAD), \
11820 X(3, (D, L, D), DOUBLE), \
11821 X(2, (D, Q), MIXED), \
11822 X(2, (Q, D), MIXED), \
11823 X(3, (D, Q, I), MIXED), \
11824 X(3, (Q, D, I), MIXED), \
11825 X(3, (Q, D, D), MIXED), \
11826 X(3, (D, Q, Q), MIXED), \
11827 X(3, (Q, Q, D), MIXED), \
11828 X(3, (Q, D, S), MIXED), \
11829 X(3, (D, Q, S), MIXED), \
11830 X(4, (D, D, D, I), DOUBLE), \
11831 X(4, (Q, Q, Q, I), QUAD), \
11832 X(2, (F, F), SINGLE), \
11833 X(3, (F, F, F), SINGLE), \
11834 X(2, (F, I), SINGLE), \
11835 X(2, (F, D), MIXED), \
11836 X(2, (D, F), MIXED), \
11837 X(3, (F, F, I), MIXED), \
11838 X(4, (R, R, F, F), SINGLE), \
11839 X(4, (F, F, R, R), SINGLE), \
11840 X(3, (D, R, R), DOUBLE), \
11841 X(3, (R, R, D), DOUBLE), \
11842 X(2, (S, R), SINGLE), \
11843 X(2, (R, S), SINGLE), \
11844 X(2, (F, R), SINGLE), \
11845 X(2, (R, F), SINGLE)
11847 #define S2(A,B) NS_##A##B
11848 #define S3(A,B,C) NS_##A##B##C
11849 #define S4(A,B,C,D) NS_##A##B##C##D
11851 #define X(N, L, C) S##N L
11864 enum neon_shape_class
11872 #define X(N, L, C) SC_##C
11874 static enum neon_shape_class neon_shape_class
[] =
11892 /* Register widths of above. */
11893 static unsigned neon_shape_el_size
[] =
11904 struct neon_shape_info
11907 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11910 #define S2(A,B) { SE_##A, SE_##B }
11911 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11912 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11914 #define X(N, L, C) { N, S##N L }
11916 static struct neon_shape_info neon_shape_tab
[] =
11926 /* Bit masks used in type checking given instructions.
11927 'N_EQK' means the type must be the same as (or based on in some way) the key
11928 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11929 set, various other bits can be set as well in order to modify the meaning of
11930 the type constraint. */
11932 enum neon_type_mask
11955 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11956 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11957 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11958 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11959 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11960 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11961 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11962 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11963 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11964 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11966 N_MAX_NONSPECIAL
= N_F64
11969 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11971 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11972 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11973 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11974 #define N_SUF_32 (N_SU_32 | N_F32)
11975 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11976 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11978 /* Pass this as the first type argument to neon_check_type to ignore types
11980 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11982 /* Select a "shape" for the current instruction (describing register types or
11983 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11984 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11985 function of operand parsing, so this function doesn't need to be called.
11986 Shapes should be listed in order of decreasing length. */
11988 static enum neon_shape
11989 neon_select_shape (enum neon_shape shape
, ...)
11992 enum neon_shape first_shape
= shape
;
11994 /* Fix missing optional operands. FIXME: we don't know at this point how
11995 many arguments we should have, so this makes the assumption that we have
11996 > 1. This is true of all current Neon opcodes, I think, but may not be
11997 true in the future. */
11998 if (!inst
.operands
[1].present
)
11999 inst
.operands
[1] = inst
.operands
[0];
12001 va_start (ap
, shape
);
12003 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12008 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12010 if (!inst
.operands
[j
].present
)
12016 switch (neon_shape_tab
[shape
].el
[j
])
12019 if (!(inst
.operands
[j
].isreg
12020 && inst
.operands
[j
].isvec
12021 && inst
.operands
[j
].issingle
12022 && !inst
.operands
[j
].isquad
))
12027 if (!(inst
.operands
[j
].isreg
12028 && inst
.operands
[j
].isvec
12029 && !inst
.operands
[j
].isquad
12030 && !inst
.operands
[j
].issingle
))
12035 if (!(inst
.operands
[j
].isreg
12036 && !inst
.operands
[j
].isvec
))
12041 if (!(inst
.operands
[j
].isreg
12042 && inst
.operands
[j
].isvec
12043 && inst
.operands
[j
].isquad
12044 && !inst
.operands
[j
].issingle
))
12049 if (!(!inst
.operands
[j
].isreg
12050 && !inst
.operands
[j
].isscalar
))
12055 if (!(!inst
.operands
[j
].isreg
12056 && inst
.operands
[j
].isscalar
))
12072 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12073 first_error (_("invalid instruction shape"));
12078 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12079 means the Q bit should be set). */
12082 neon_quad (enum neon_shape shape
)
12084 return neon_shape_class
[shape
] == SC_QUAD
;
12088 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12091 /* Allow modification to be made to types which are constrained to be
12092 based on the key element, based on bits set alongside N_EQK. */
12093 if ((typebits
& N_EQK
) != 0)
12095 if ((typebits
& N_HLF
) != 0)
12097 else if ((typebits
& N_DBL
) != 0)
12099 if ((typebits
& N_SGN
) != 0)
12100 *g_type
= NT_signed
;
12101 else if ((typebits
& N_UNS
) != 0)
12102 *g_type
= NT_unsigned
;
12103 else if ((typebits
& N_INT
) != 0)
12104 *g_type
= NT_integer
;
12105 else if ((typebits
& N_FLT
) != 0)
12106 *g_type
= NT_float
;
12107 else if ((typebits
& N_SIZ
) != 0)
12108 *g_type
= NT_untyped
;
12112 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12113 operand type, i.e. the single type specified in a Neon instruction when it
12114 is the only one given. */
12116 static struct neon_type_el
12117 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12119 struct neon_type_el dest
= *key
;
12121 gas_assert ((thisarg
& N_EQK
) != 0);
12123 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12128 /* Convert Neon type and size into compact bitmask representation. */
12130 static enum neon_type_mask
12131 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12138 case 8: return N_8
;
12139 case 16: return N_16
;
12140 case 32: return N_32
;
12141 case 64: return N_64
;
12149 case 8: return N_I8
;
12150 case 16: return N_I16
;
12151 case 32: return N_I32
;
12152 case 64: return N_I64
;
12160 case 16: return N_F16
;
12161 case 32: return N_F32
;
12162 case 64: return N_F64
;
12170 case 8: return N_P8
;
12171 case 16: return N_P16
;
12179 case 8: return N_S8
;
12180 case 16: return N_S16
;
12181 case 32: return N_S32
;
12182 case 64: return N_S64
;
12190 case 8: return N_U8
;
12191 case 16: return N_U16
;
12192 case 32: return N_U32
;
12193 case 64: return N_U64
;
12204 /* Convert compact Neon bitmask type representation to a type and size. Only
12205 handles the case where a single bit is set in the mask. */
12208 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12209 enum neon_type_mask mask
)
12211 if ((mask
& N_EQK
) != 0)
12214 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12216 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12218 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12220 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12225 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12227 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12228 *type
= NT_unsigned
;
12229 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12230 *type
= NT_integer
;
12231 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12232 *type
= NT_untyped
;
12233 else if ((mask
& (N_P8
| N_P16
)) != 0)
12235 else if ((mask
& (N_F32
| N_F64
)) != 0)
12243 /* Modify a bitmask of allowed types. This is only needed for type
12247 modify_types_allowed (unsigned allowed
, unsigned mods
)
12250 enum neon_el_type type
;
12256 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12258 if (el_type_of_type_chk (&type
, &size
,
12259 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12261 neon_modify_type_size (mods
, &type
, &size
);
12262 destmask
|= type_chk_of_el_type (type
, size
);
12269 /* Check type and return type classification.
12270 The manual states (paraphrase): If one datatype is given, it indicates the
12272 - the second operand, if there is one
12273 - the operand, if there is no second operand
12274 - the result, if there are no operands.
12275 This isn't quite good enough though, so we use a concept of a "key" datatype
12276 which is set on a per-instruction basis, which is the one which matters when
12277 only one data type is written.
12278 Note: this function has side-effects (e.g. filling in missing operands). All
12279 Neon instructions should call it before performing bit encoding. */
12281 static struct neon_type_el
12282 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12285 unsigned i
, pass
, key_el
= 0;
12286 unsigned types
[NEON_MAX_TYPE_ELS
];
12287 enum neon_el_type k_type
= NT_invtype
;
12288 unsigned k_size
= -1u;
12289 struct neon_type_el badtype
= {NT_invtype
, -1};
12290 unsigned key_allowed
= 0;
12292 /* Optional registers in Neon instructions are always (not) in operand 1.
12293 Fill in the missing operand here, if it was omitted. */
12294 if (els
> 1 && !inst
.operands
[1].present
)
12295 inst
.operands
[1] = inst
.operands
[0];
12297 /* Suck up all the varargs. */
12299 for (i
= 0; i
< els
; i
++)
12301 unsigned thisarg
= va_arg (ap
, unsigned);
12302 if (thisarg
== N_IGNORE_TYPE
)
12307 types
[i
] = thisarg
;
12308 if ((thisarg
& N_KEY
) != 0)
12313 if (inst
.vectype
.elems
> 0)
12314 for (i
= 0; i
< els
; i
++)
12315 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12317 first_error (_("types specified in both the mnemonic and operands"));
12321 /* Duplicate inst.vectype elements here as necessary.
12322 FIXME: No idea if this is exactly the same as the ARM assembler,
12323 particularly when an insn takes one register and one non-register
12325 if (inst
.vectype
.elems
== 1 && els
> 1)
12328 inst
.vectype
.elems
= els
;
12329 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12330 for (j
= 0; j
< els
; j
++)
12332 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12335 else if (inst
.vectype
.elems
== 0 && els
> 0)
12338 /* No types were given after the mnemonic, so look for types specified
12339 after each operand. We allow some flexibility here; as long as the
12340 "key" operand has a type, we can infer the others. */
12341 for (j
= 0; j
< els
; j
++)
12342 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12343 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12345 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12347 for (j
= 0; j
< els
; j
++)
12348 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12349 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12354 first_error (_("operand types can't be inferred"));
12358 else if (inst
.vectype
.elems
!= els
)
12360 first_error (_("type specifier has the wrong number of parts"));
12364 for (pass
= 0; pass
< 2; pass
++)
12366 for (i
= 0; i
< els
; i
++)
12368 unsigned thisarg
= types
[i
];
12369 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12370 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12371 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12372 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12374 /* Decay more-specific signed & unsigned types to sign-insensitive
12375 integer types if sign-specific variants are unavailable. */
12376 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12377 && (types_allowed
& N_SU_ALL
) == 0)
12378 g_type
= NT_integer
;
12380 /* If only untyped args are allowed, decay any more specific types to
12381 them. Some instructions only care about signs for some element
12382 sizes, so handle that properly. */
12383 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12384 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12385 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12386 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12387 g_type
= NT_untyped
;
12391 if ((thisarg
& N_KEY
) != 0)
12395 key_allowed
= thisarg
& ~N_KEY
;
12400 if ((thisarg
& N_VFP
) != 0)
12402 enum neon_shape_el regshape
;
12403 unsigned regwidth
, match
;
12405 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12408 first_error (_("invalid instruction shape"));
12411 regshape
= neon_shape_tab
[ns
].el
[i
];
12412 regwidth
= neon_shape_el_size
[regshape
];
12414 /* In VFP mode, operands must match register widths. If we
12415 have a key operand, use its width, else use the width of
12416 the current operand. */
12422 if (regwidth
!= match
)
12424 first_error (_("operand size must match register width"));
12429 if ((thisarg
& N_EQK
) == 0)
12431 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12433 if ((given_type
& types_allowed
) == 0)
12435 first_error (_("bad type in Neon instruction"));
12441 enum neon_el_type mod_k_type
= k_type
;
12442 unsigned mod_k_size
= k_size
;
12443 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12444 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12446 first_error (_("inconsistent types in Neon instruction"));
12454 return inst
.vectype
.el
[key_el
];
12457 /* Neon-style VFP instruction forwarding. */
12459 /* Thumb VFP instructions have 0xE in the condition field. */
12462 do_vfp_cond_or_thumb (void)
12467 inst
.instruction
|= 0xe0000000;
12469 inst
.instruction
|= inst
.cond
<< 28;
12472 /* Look up and encode a simple mnemonic, for use as a helper function for the
12473 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12474 etc. It is assumed that operand parsing has already been done, and that the
12475 operands are in the form expected by the given opcode (this isn't necessarily
12476 the same as the form in which they were parsed, hence some massaging must
12477 take place before this function is called).
12478 Checks current arch version against that in the looked-up opcode. */
12481 do_vfp_nsyn_opcode (const char *opname
)
12483 const struct asm_opcode
*opcode
;
12485 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12491 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12498 inst
.instruction
= opcode
->tvalue
;
12499 opcode
->tencode ();
12503 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12504 opcode
->aencode ();
12509 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12511 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12516 do_vfp_nsyn_opcode ("fadds");
12518 do_vfp_nsyn_opcode ("fsubs");
12523 do_vfp_nsyn_opcode ("faddd");
12525 do_vfp_nsyn_opcode ("fsubd");
12529 /* Check operand types to see if this is a VFP instruction, and if so call
12533 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12535 enum neon_shape rs
;
12536 struct neon_type_el et
;
12541 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12542 et
= neon_check_type (2, rs
,
12543 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12547 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12548 et
= neon_check_type (3, rs
,
12549 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12556 if (et
.type
!= NT_invtype
)
12567 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12569 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12574 do_vfp_nsyn_opcode ("fmacs");
12576 do_vfp_nsyn_opcode ("fnmacs");
12581 do_vfp_nsyn_opcode ("fmacd");
12583 do_vfp_nsyn_opcode ("fnmacd");
12588 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12590 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12595 do_vfp_nsyn_opcode ("ffmas");
12597 do_vfp_nsyn_opcode ("ffnmas");
12602 do_vfp_nsyn_opcode ("ffmad");
12604 do_vfp_nsyn_opcode ("ffnmad");
12609 do_vfp_nsyn_mul (enum neon_shape rs
)
12612 do_vfp_nsyn_opcode ("fmuls");
12614 do_vfp_nsyn_opcode ("fmuld");
12618 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12620 int is_neg
= (inst
.instruction
& 0x80) != 0;
12621 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12626 do_vfp_nsyn_opcode ("fnegs");
12628 do_vfp_nsyn_opcode ("fabss");
12633 do_vfp_nsyn_opcode ("fnegd");
12635 do_vfp_nsyn_opcode ("fabsd");
12639 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12640 insns belong to Neon, and are handled elsewhere. */
12643 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12645 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12649 do_vfp_nsyn_opcode ("fldmdbs");
12651 do_vfp_nsyn_opcode ("fldmias");
12656 do_vfp_nsyn_opcode ("fstmdbs");
12658 do_vfp_nsyn_opcode ("fstmias");
12663 do_vfp_nsyn_sqrt (void)
12665 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12666 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12669 do_vfp_nsyn_opcode ("fsqrts");
12671 do_vfp_nsyn_opcode ("fsqrtd");
12675 do_vfp_nsyn_div (void)
12677 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12678 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12679 N_F32
| N_F64
| N_KEY
| N_VFP
);
12682 do_vfp_nsyn_opcode ("fdivs");
12684 do_vfp_nsyn_opcode ("fdivd");
12688 do_vfp_nsyn_nmul (void)
12690 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12691 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12692 N_F32
| N_F64
| N_KEY
| N_VFP
);
12696 NEON_ENCODE (SINGLE
, inst
);
12697 do_vfp_sp_dyadic ();
12701 NEON_ENCODE (DOUBLE
, inst
);
12702 do_vfp_dp_rd_rn_rm ();
12704 do_vfp_cond_or_thumb ();
12708 do_vfp_nsyn_cmp (void)
12710 if (inst
.operands
[1].isreg
)
12712 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12713 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12717 NEON_ENCODE (SINGLE
, inst
);
12718 do_vfp_sp_monadic ();
12722 NEON_ENCODE (DOUBLE
, inst
);
12723 do_vfp_dp_rd_rm ();
12728 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12729 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12731 switch (inst
.instruction
& 0x0fffffff)
12734 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12737 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12745 NEON_ENCODE (SINGLE
, inst
);
12746 do_vfp_sp_compare_z ();
12750 NEON_ENCODE (DOUBLE
, inst
);
12754 do_vfp_cond_or_thumb ();
12758 nsyn_insert_sp (void)
12760 inst
.operands
[1] = inst
.operands
[0];
12761 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12762 inst
.operands
[0].reg
= REG_SP
;
12763 inst
.operands
[0].isreg
= 1;
12764 inst
.operands
[0].writeback
= 1;
12765 inst
.operands
[0].present
= 1;
12769 do_vfp_nsyn_push (void)
12772 if (inst
.operands
[1].issingle
)
12773 do_vfp_nsyn_opcode ("fstmdbs");
12775 do_vfp_nsyn_opcode ("fstmdbd");
12779 do_vfp_nsyn_pop (void)
12782 if (inst
.operands
[1].issingle
)
12783 do_vfp_nsyn_opcode ("fldmias");
12785 do_vfp_nsyn_opcode ("fldmiad");
12788 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12789 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12792 neon_dp_fixup (struct arm_it
* insn
)
12794 unsigned int i
= insn
->instruction
;
12799 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12810 insn
->instruction
= i
;
12813 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12817 neon_logbits (unsigned x
)
12819 return ffs (x
) - 4;
12822 #define LOW4(R) ((R) & 0xf)
12823 #define HI1(R) (((R) >> 4) & 1)
12825 /* Encode insns with bit pattern:
12827 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12828 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12830 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12831 different meaning for some instruction. */
12834 neon_three_same (int isquad
, int ubit
, int size
)
12836 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12837 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12838 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12839 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12840 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12841 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12842 inst
.instruction
|= (isquad
!= 0) << 6;
12843 inst
.instruction
|= (ubit
!= 0) << 24;
12845 inst
.instruction
|= neon_logbits (size
) << 20;
12847 neon_dp_fixup (&inst
);
12850 /* Encode instructions of the form:
12852 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12853 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12855 Don't write size if SIZE == -1. */
12858 neon_two_same (int qbit
, int ubit
, int size
)
12860 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12861 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12862 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12863 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12864 inst
.instruction
|= (qbit
!= 0) << 6;
12865 inst
.instruction
|= (ubit
!= 0) << 24;
12868 inst
.instruction
|= neon_logbits (size
) << 18;
12870 neon_dp_fixup (&inst
);
12873 /* Neon instruction encoders, in approximate order of appearance. */
12876 do_neon_dyadic_i_su (void)
12878 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12879 struct neon_type_el et
= neon_check_type (3, rs
,
12880 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12881 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12885 do_neon_dyadic_i64_su (void)
12887 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12888 struct neon_type_el et
= neon_check_type (3, rs
,
12889 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12890 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12894 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12897 unsigned size
= et
.size
>> 3;
12898 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12899 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12900 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12901 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12902 inst
.instruction
|= (isquad
!= 0) << 6;
12903 inst
.instruction
|= immbits
<< 16;
12904 inst
.instruction
|= (size
>> 3) << 7;
12905 inst
.instruction
|= (size
& 0x7) << 19;
12907 inst
.instruction
|= (uval
!= 0) << 24;
12909 neon_dp_fixup (&inst
);
12913 do_neon_shl_imm (void)
12915 if (!inst
.operands
[2].isreg
)
12917 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12918 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12919 NEON_ENCODE (IMMED
, inst
);
12920 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12924 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12925 struct neon_type_el et
= neon_check_type (3, rs
,
12926 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12929 /* VSHL/VQSHL 3-register variants have syntax such as:
12931 whereas other 3-register operations encoded by neon_three_same have
12934 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12936 tmp
= inst
.operands
[2].reg
;
12937 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12938 inst
.operands
[1].reg
= tmp
;
12939 NEON_ENCODE (INTEGER
, inst
);
12940 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12945 do_neon_qshl_imm (void)
12947 if (!inst
.operands
[2].isreg
)
12949 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12950 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12952 NEON_ENCODE (IMMED
, inst
);
12953 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12954 inst
.operands
[2].imm
);
12958 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12959 struct neon_type_el et
= neon_check_type (3, rs
,
12960 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12963 /* See note in do_neon_shl_imm. */
12964 tmp
= inst
.operands
[2].reg
;
12965 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12966 inst
.operands
[1].reg
= tmp
;
12967 NEON_ENCODE (INTEGER
, inst
);
12968 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12973 do_neon_rshl (void)
12975 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12976 struct neon_type_el et
= neon_check_type (3, rs
,
12977 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12980 tmp
= inst
.operands
[2].reg
;
12981 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12982 inst
.operands
[1].reg
= tmp
;
12983 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12987 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12989 /* Handle .I8 pseudo-instructions. */
12992 /* Unfortunately, this will make everything apart from zero out-of-range.
12993 FIXME is this the intended semantics? There doesn't seem much point in
12994 accepting .I8 if so. */
12995 immediate
|= immediate
<< 8;
13001 if (immediate
== (immediate
& 0x000000ff))
13003 *immbits
= immediate
;
13006 else if (immediate
== (immediate
& 0x0000ff00))
13008 *immbits
= immediate
>> 8;
13011 else if (immediate
== (immediate
& 0x00ff0000))
13013 *immbits
= immediate
>> 16;
13016 else if (immediate
== (immediate
& 0xff000000))
13018 *immbits
= immediate
>> 24;
13021 if ((immediate
& 0xffff) != (immediate
>> 16))
13022 goto bad_immediate
;
13023 immediate
&= 0xffff;
13026 if (immediate
== (immediate
& 0x000000ff))
13028 *immbits
= immediate
;
13031 else if (immediate
== (immediate
& 0x0000ff00))
13033 *immbits
= immediate
>> 8;
13038 first_error (_("immediate value out of range"));
13042 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13046 neon_bits_same_in_bytes (unsigned imm
)
13048 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13049 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13050 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13051 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13054 /* For immediate of above form, return 0bABCD. */
13057 neon_squash_bits (unsigned imm
)
13059 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13060 | ((imm
& 0x01000000) >> 21);
13063 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13066 neon_qfloat_bits (unsigned imm
)
13068 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13071 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13072 the instruction. *OP is passed as the initial value of the op field, and
13073 may be set to a different value depending on the constant (i.e.
13074 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13075 MVN). If the immediate looks like a repeated pattern then also
13076 try smaller element sizes. */
13079 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13080 unsigned *immbits
, int *op
, int size
,
13081 enum neon_el_type type
)
13083 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13085 if (type
== NT_float
&& !float_p
)
13088 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13090 if (size
!= 32 || *op
== 1)
13092 *immbits
= neon_qfloat_bits (immlo
);
13098 if (neon_bits_same_in_bytes (immhi
)
13099 && neon_bits_same_in_bytes (immlo
))
13103 *immbits
= (neon_squash_bits (immhi
) << 4)
13104 | neon_squash_bits (immlo
);
13109 if (immhi
!= immlo
)
13115 if (immlo
== (immlo
& 0x000000ff))
13120 else if (immlo
== (immlo
& 0x0000ff00))
13122 *immbits
= immlo
>> 8;
13125 else if (immlo
== (immlo
& 0x00ff0000))
13127 *immbits
= immlo
>> 16;
13130 else if (immlo
== (immlo
& 0xff000000))
13132 *immbits
= immlo
>> 24;
13135 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13137 *immbits
= (immlo
>> 8) & 0xff;
13140 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13142 *immbits
= (immlo
>> 16) & 0xff;
13146 if ((immlo
& 0xffff) != (immlo
>> 16))
13153 if (immlo
== (immlo
& 0x000000ff))
13158 else if (immlo
== (immlo
& 0x0000ff00))
13160 *immbits
= immlo
>> 8;
13164 if ((immlo
& 0xff) != (immlo
>> 8))
13169 if (immlo
== (immlo
& 0x000000ff))
13171 /* Don't allow MVN with 8-bit immediate. */
13181 /* Write immediate bits [7:0] to the following locations:
13183 |28/24|23 19|18 16|15 4|3 0|
13184 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13186 This function is used by VMOV/VMVN/VORR/VBIC. */
13189 neon_write_immbits (unsigned immbits
)
13191 inst
.instruction
|= immbits
& 0xf;
13192 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13193 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13196 /* Invert low-order SIZE bits of XHI:XLO. */
13199 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13201 unsigned immlo
= xlo
? *xlo
: 0;
13202 unsigned immhi
= xhi
? *xhi
: 0;
13207 immlo
= (~immlo
) & 0xff;
13211 immlo
= (~immlo
) & 0xffff;
13215 immhi
= (~immhi
) & 0xffffffff;
13216 /* fall through. */
13219 immlo
= (~immlo
) & 0xffffffff;
13234 do_neon_logic (void)
13236 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13238 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13239 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13240 /* U bit and size field were set as part of the bitmask. */
13241 NEON_ENCODE (INTEGER
, inst
);
13242 neon_three_same (neon_quad (rs
), 0, -1);
13246 const int three_ops_form
= (inst
.operands
[2].present
13247 && !inst
.operands
[2].isreg
);
13248 const int immoperand
= (three_ops_form
? 2 : 1);
13249 enum neon_shape rs
= (three_ops_form
13250 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13251 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13252 struct neon_type_el et
= neon_check_type (2, rs
,
13253 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13254 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13258 if (et
.type
== NT_invtype
)
13261 if (three_ops_form
)
13262 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13263 _("first and second operands shall be the same register"));
13265 NEON_ENCODE (IMMED
, inst
);
13267 immbits
= inst
.operands
[immoperand
].imm
;
13270 /* .i64 is a pseudo-op, so the immediate must be a repeating
13272 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13273 inst
.operands
[immoperand
].reg
: 0))
13275 /* Set immbits to an invalid constant. */
13276 immbits
= 0xdeadbeef;
13283 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13287 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13291 /* Pseudo-instruction for VBIC. */
13292 neon_invert_size (&immbits
, 0, et
.size
);
13293 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13297 /* Pseudo-instruction for VORR. */
13298 neon_invert_size (&immbits
, 0, et
.size
);
13299 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13309 inst
.instruction
|= neon_quad (rs
) << 6;
13310 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13311 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13312 inst
.instruction
|= cmode
<< 8;
13313 neon_write_immbits (immbits
);
13315 neon_dp_fixup (&inst
);
13320 do_neon_bitfield (void)
13322 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13323 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13324 neon_three_same (neon_quad (rs
), 0, -1);
13328 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13331 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13332 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13334 if (et
.type
== NT_float
)
13336 NEON_ENCODE (FLOAT
, inst
);
13337 neon_three_same (neon_quad (rs
), 0, -1);
13341 NEON_ENCODE (INTEGER
, inst
);
13342 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13347 do_neon_dyadic_if_su (void)
13349 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13353 do_neon_dyadic_if_su_d (void)
13355 /* This version only allow D registers, but that constraint is enforced during
13356 operand parsing so we don't need to do anything extra here. */
13357 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13361 do_neon_dyadic_if_i_d (void)
13363 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13364 affected if we specify unsigned args. */
13365 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13368 enum vfp_or_neon_is_neon_bits
13371 NEON_CHECK_ARCH
= 2
13374 /* Call this function if an instruction which may have belonged to the VFP or
13375 Neon instruction sets, but turned out to be a Neon instruction (due to the
13376 operand types involved, etc.). We have to check and/or fix-up a couple of
13379 - Make sure the user hasn't attempted to make a Neon instruction
13381 - Alter the value in the condition code field if necessary.
13382 - Make sure that the arch supports Neon instructions.
13384 Which of these operations take place depends on bits from enum
13385 vfp_or_neon_is_neon_bits.
13387 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13388 current instruction's condition is COND_ALWAYS, the condition field is
13389 changed to inst.uncond_value. This is necessary because instructions shared
13390 between VFP and Neon may be conditional for the VFP variants only, and the
13391 unconditional Neon version must have, e.g., 0xF in the condition field. */
13394 vfp_or_neon_is_neon (unsigned check
)
13396 /* Conditions are always legal in Thumb mode (IT blocks). */
13397 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13399 if (inst
.cond
!= COND_ALWAYS
)
13401 first_error (_(BAD_COND
));
13404 if (inst
.uncond_value
!= -1)
13405 inst
.instruction
|= inst
.uncond_value
<< 28;
13408 if ((check
& NEON_CHECK_ARCH
)
13409 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13411 first_error (_(BAD_FPU
));
13419 do_neon_addsub_if_i (void)
13421 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13424 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13427 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13428 affected if we specify unsigned args. */
13429 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13432 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13434 V<op> A,B (A is operand 0, B is operand 2)
13439 so handle that case specially. */
13442 neon_exchange_operands (void)
13444 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13445 if (inst
.operands
[1].present
)
13447 /* Swap operands[1] and operands[2]. */
13448 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13449 inst
.operands
[1] = inst
.operands
[2];
13450 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13454 inst
.operands
[1] = inst
.operands
[2];
13455 inst
.operands
[2] = inst
.operands
[0];
13460 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13462 if (inst
.operands
[2].isreg
)
13465 neon_exchange_operands ();
13466 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13470 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13471 struct neon_type_el et
= neon_check_type (2, rs
,
13472 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13474 NEON_ENCODE (IMMED
, inst
);
13475 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13476 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13477 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13478 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13479 inst
.instruction
|= neon_quad (rs
) << 6;
13480 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13481 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13483 neon_dp_fixup (&inst
);
13490 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13494 do_neon_cmp_inv (void)
13496 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13502 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13505 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13506 scalars, which are encoded in 5 bits, M : Rm.
13507 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13508 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13512 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13514 unsigned regno
= NEON_SCALAR_REG (scalar
);
13515 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13520 if (regno
> 7 || elno
> 3)
13522 return regno
| (elno
<< 3);
13525 if (regno
> 15 || elno
> 1)
13527 return regno
| (elno
<< 4);
13531 first_error (_("scalar out of range for multiply instruction"));
13537 /* Encode multiply / multiply-accumulate scalar instructions. */
13540 neon_mul_mac (struct neon_type_el et
, int ubit
)
13544 /* Give a more helpful error message if we have an invalid type. */
13545 if (et
.type
== NT_invtype
)
13548 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13549 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13550 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13551 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13552 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13553 inst
.instruction
|= LOW4 (scalar
);
13554 inst
.instruction
|= HI1 (scalar
) << 5;
13555 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13556 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13557 inst
.instruction
|= (ubit
!= 0) << 24;
13559 neon_dp_fixup (&inst
);
13563 do_neon_mac_maybe_scalar (void)
13565 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13568 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13571 if (inst
.operands
[2].isscalar
)
13573 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13574 struct neon_type_el et
= neon_check_type (3, rs
,
13575 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13576 NEON_ENCODE (SCALAR
, inst
);
13577 neon_mul_mac (et
, neon_quad (rs
));
13581 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13582 affected if we specify unsigned args. */
13583 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13588 do_neon_fmac (void)
13590 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13593 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13596 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13602 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13603 struct neon_type_el et
= neon_check_type (3, rs
,
13604 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13605 neon_three_same (neon_quad (rs
), 0, et
.size
);
13608 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13609 same types as the MAC equivalents. The polynomial type for this instruction
13610 is encoded the same as the integer type. */
13615 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13618 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13621 if (inst
.operands
[2].isscalar
)
13622 do_neon_mac_maybe_scalar ();
13624 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13628 do_neon_qdmulh (void)
13630 if (inst
.operands
[2].isscalar
)
13632 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13633 struct neon_type_el et
= neon_check_type (3, rs
,
13634 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13635 NEON_ENCODE (SCALAR
, inst
);
13636 neon_mul_mac (et
, neon_quad (rs
));
13640 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13641 struct neon_type_el et
= neon_check_type (3, rs
,
13642 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13643 NEON_ENCODE (INTEGER
, inst
);
13644 /* The U bit (rounding) comes from bit mask. */
13645 neon_three_same (neon_quad (rs
), 0, et
.size
);
13650 do_neon_fcmp_absolute (void)
13652 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13653 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13654 /* Size field comes from bit mask. */
13655 neon_three_same (neon_quad (rs
), 1, -1);
13659 do_neon_fcmp_absolute_inv (void)
13661 neon_exchange_operands ();
13662 do_neon_fcmp_absolute ();
13666 do_neon_step (void)
13668 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13669 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13670 neon_three_same (neon_quad (rs
), 0, -1);
13674 do_neon_abs_neg (void)
13676 enum neon_shape rs
;
13677 struct neon_type_el et
;
13679 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13682 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13685 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13686 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13688 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13689 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13690 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13691 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13692 inst
.instruction
|= neon_quad (rs
) << 6;
13693 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13694 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13696 neon_dp_fixup (&inst
);
13702 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13703 struct neon_type_el et
= neon_check_type (2, rs
,
13704 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13705 int imm
= inst
.operands
[2].imm
;
13706 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13707 _("immediate out of range for insert"));
13708 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13714 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13715 struct neon_type_el et
= neon_check_type (2, rs
,
13716 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13717 int imm
= inst
.operands
[2].imm
;
13718 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13719 _("immediate out of range for insert"));
13720 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13724 do_neon_qshlu_imm (void)
13726 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13727 struct neon_type_el et
= neon_check_type (2, rs
,
13728 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13729 int imm
= inst
.operands
[2].imm
;
13730 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13731 _("immediate out of range for shift"));
13732 /* Only encodes the 'U present' variant of the instruction.
13733 In this case, signed types have OP (bit 8) set to 0.
13734 Unsigned types have OP set to 1. */
13735 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13736 /* The rest of the bits are the same as other immediate shifts. */
13737 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13741 do_neon_qmovn (void)
13743 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13744 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13745 /* Saturating move where operands can be signed or unsigned, and the
13746 destination has the same signedness. */
13747 NEON_ENCODE (INTEGER
, inst
);
13748 if (et
.type
== NT_unsigned
)
13749 inst
.instruction
|= 0xc0;
13751 inst
.instruction
|= 0x80;
13752 neon_two_same (0, 1, et
.size
/ 2);
13756 do_neon_qmovun (void)
13758 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13759 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13760 /* Saturating move with unsigned results. Operands must be signed. */
13761 NEON_ENCODE (INTEGER
, inst
);
13762 neon_two_same (0, 1, et
.size
/ 2);
13766 do_neon_rshift_sat_narrow (void)
13768 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13769 or unsigned. If operands are unsigned, results must also be unsigned. */
13770 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13771 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13772 int imm
= inst
.operands
[2].imm
;
13773 /* This gets the bounds check, size encoding and immediate bits calculation
13777 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13778 VQMOVN.I<size> <Dd>, <Qm>. */
13781 inst
.operands
[2].present
= 0;
13782 inst
.instruction
= N_MNEM_vqmovn
;
13787 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13788 _("immediate out of range"));
13789 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13793 do_neon_rshift_sat_narrow_u (void)
13795 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13796 or unsigned. If operands are unsigned, results must also be unsigned. */
13797 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13798 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13799 int imm
= inst
.operands
[2].imm
;
13800 /* This gets the bounds check, size encoding and immediate bits calculation
13804 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13805 VQMOVUN.I<size> <Dd>, <Qm>. */
13808 inst
.operands
[2].present
= 0;
13809 inst
.instruction
= N_MNEM_vqmovun
;
13814 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13815 _("immediate out of range"));
13816 /* FIXME: The manual is kind of unclear about what value U should have in
13817 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13819 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13823 do_neon_movn (void)
13825 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13826 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13827 NEON_ENCODE (INTEGER
, inst
);
13828 neon_two_same (0, 1, et
.size
/ 2);
13832 do_neon_rshift_narrow (void)
13834 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13835 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13836 int imm
= inst
.operands
[2].imm
;
13837 /* This gets the bounds check, size encoding and immediate bits calculation
13841 /* If immediate is zero then we are a pseudo-instruction for
13842 VMOVN.I<size> <Dd>, <Qm> */
13845 inst
.operands
[2].present
= 0;
13846 inst
.instruction
= N_MNEM_vmovn
;
13851 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13852 _("immediate out of range for narrowing operation"));
13853 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13857 do_neon_shll (void)
13859 /* FIXME: Type checking when lengthening. */
13860 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13861 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13862 unsigned imm
= inst
.operands
[2].imm
;
13864 if (imm
== et
.size
)
13866 /* Maximum shift variant. */
13867 NEON_ENCODE (INTEGER
, inst
);
13868 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13869 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13870 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13871 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13872 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13874 neon_dp_fixup (&inst
);
13878 /* A more-specific type check for non-max versions. */
13879 et
= neon_check_type (2, NS_QDI
,
13880 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13881 NEON_ENCODE (IMMED
, inst
);
13882 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13886 /* Check the various types for the VCVT instruction, and return which version
13887 the current instruction is. */
13890 neon_cvt_flavour (enum neon_shape rs
)
13892 #define CVT_VAR(C,X,Y) \
13893 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13894 if (et.type != NT_invtype) \
13896 inst.error = NULL; \
13899 struct neon_type_el et
;
13900 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13901 || rs
== NS_FF
) ? N_VFP
: 0;
13902 /* The instruction versions which take an immediate take one register
13903 argument, which is extended to the width of the full register. Thus the
13904 "source" and "destination" registers must have the same width. Hack that
13905 here by making the size equal to the key (wider, in this case) operand. */
13906 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13908 CVT_VAR (0, N_S32
, N_F32
);
13909 CVT_VAR (1, N_U32
, N_F32
);
13910 CVT_VAR (2, N_F32
, N_S32
);
13911 CVT_VAR (3, N_F32
, N_U32
);
13912 /* Half-precision conversions. */
13913 CVT_VAR (4, N_F32
, N_F16
);
13914 CVT_VAR (5, N_F16
, N_F32
);
13918 /* VFP instructions. */
13919 CVT_VAR (6, N_F32
, N_F64
);
13920 CVT_VAR (7, N_F64
, N_F32
);
13921 CVT_VAR (8, N_S32
, N_F64
| key
);
13922 CVT_VAR (9, N_U32
, N_F64
| key
);
13923 CVT_VAR (10, N_F64
| key
, N_S32
);
13924 CVT_VAR (11, N_F64
| key
, N_U32
);
13925 /* VFP instructions with bitshift. */
13926 CVT_VAR (12, N_F32
| key
, N_S16
);
13927 CVT_VAR (13, N_F32
| key
, N_U16
);
13928 CVT_VAR (14, N_F64
| key
, N_S16
);
13929 CVT_VAR (15, N_F64
| key
, N_U16
);
13930 CVT_VAR (16, N_S16
, N_F32
| key
);
13931 CVT_VAR (17, N_U16
, N_F32
| key
);
13932 CVT_VAR (18, N_S16
, N_F64
| key
);
13933 CVT_VAR (19, N_U16
, N_F64
| key
);
13939 /* Neon-syntax VFP conversions. */
13942 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13944 const char *opname
= 0;
13946 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13948 /* Conversions with immediate bitshift. */
13949 const char *enc
[] =
13973 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13975 opname
= enc
[flavour
];
13976 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13977 _("operands 0 and 1 must be the same register"));
13978 inst
.operands
[1] = inst
.operands
[2];
13979 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13984 /* Conversions without bitshift. */
13985 const char *enc
[] =
14001 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14002 opname
= enc
[flavour
];
14006 do_vfp_nsyn_opcode (opname
);
14010 do_vfp_nsyn_cvtz (void)
14012 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14013 int flavour
= neon_cvt_flavour (rs
);
14014 const char *enc
[] =
14028 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14029 do_vfp_nsyn_opcode (enc
[flavour
]);
14033 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14035 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14036 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14037 int flavour
= neon_cvt_flavour (rs
);
14039 /* PR11109: Handle round-to-zero for VCVT conversions. */
14041 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14042 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14043 && (rs
== NS_FD
|| rs
== NS_FF
))
14045 do_vfp_nsyn_cvtz ();
14049 /* VFP rather than Neon conversions. */
14052 do_vfp_nsyn_cvt (rs
, flavour
);
14062 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14064 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14067 /* Fixed-point conversion with #0 immediate is encoded as an
14068 integer conversion. */
14069 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14071 immbits
= 32 - inst
.operands
[2].imm
;
14072 NEON_ENCODE (IMMED
, inst
);
14074 inst
.instruction
|= enctab
[flavour
];
14075 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14076 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14077 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14078 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14079 inst
.instruction
|= neon_quad (rs
) << 6;
14080 inst
.instruction
|= 1 << 21;
14081 inst
.instruction
|= immbits
<< 16;
14083 neon_dp_fixup (&inst
);
14091 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14093 NEON_ENCODE (INTEGER
, inst
);
14095 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14099 inst
.instruction
|= enctab
[flavour
];
14101 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14102 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14103 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14104 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14105 inst
.instruction
|= neon_quad (rs
) << 6;
14106 inst
.instruction
|= 2 << 18;
14108 neon_dp_fixup (&inst
);
14112 /* Half-precision conversions for Advanced SIMD -- neon. */
14117 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14119 as_bad (_("operand size must match register width"));
14124 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14126 as_bad (_("operand size must match register width"));
14131 inst
.instruction
= 0x3b60600;
14133 inst
.instruction
= 0x3b60700;
14135 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14136 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14137 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14138 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14139 neon_dp_fixup (&inst
);
14143 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14144 do_vfp_nsyn_cvt (rs
, flavour
);
14149 do_neon_cvtr (void)
14151 do_neon_cvt_1 (FALSE
);
14157 do_neon_cvt_1 (TRUE
);
14161 do_neon_cvtb (void)
14163 inst
.instruction
= 0xeb20a40;
14165 /* The sizes are attached to the mnemonic. */
14166 if (inst
.vectype
.el
[0].type
!= NT_invtype
14167 && inst
.vectype
.el
[0].size
== 16)
14168 inst
.instruction
|= 0x00010000;
14170 /* Programmer's syntax: the sizes are attached to the operands. */
14171 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14172 && inst
.operands
[0].vectype
.size
== 16)
14173 inst
.instruction
|= 0x00010000;
14175 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14176 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14177 do_vfp_cond_or_thumb ();
14182 do_neon_cvtt (void)
14185 inst
.instruction
|= 0x80;
14189 neon_move_immediate (void)
14191 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14192 struct neon_type_el et
= neon_check_type (2, rs
,
14193 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14194 unsigned immlo
, immhi
= 0, immbits
;
14195 int op
, cmode
, float_p
;
14197 constraint (et
.type
== NT_invtype
,
14198 _("operand size must be specified for immediate VMOV"));
14200 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14201 op
= (inst
.instruction
& (1 << 5)) != 0;
14203 immlo
= inst
.operands
[1].imm
;
14204 if (inst
.operands
[1].regisimm
)
14205 immhi
= inst
.operands
[1].reg
;
14207 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14208 _("immediate has bits set outside the operand size"));
14210 float_p
= inst
.operands
[1].immisfloat
;
14212 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14213 et
.size
, et
.type
)) == FAIL
)
14215 /* Invert relevant bits only. */
14216 neon_invert_size (&immlo
, &immhi
, et
.size
);
14217 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14218 with one or the other; those cases are caught by
14219 neon_cmode_for_move_imm. */
14221 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14222 &op
, et
.size
, et
.type
)) == FAIL
)
14224 first_error (_("immediate out of range"));
14229 inst
.instruction
&= ~(1 << 5);
14230 inst
.instruction
|= op
<< 5;
14232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14233 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14234 inst
.instruction
|= neon_quad (rs
) << 6;
14235 inst
.instruction
|= cmode
<< 8;
14237 neon_write_immbits (immbits
);
14243 if (inst
.operands
[1].isreg
)
14245 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14247 NEON_ENCODE (INTEGER
, inst
);
14248 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14249 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14250 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14251 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14252 inst
.instruction
|= neon_quad (rs
) << 6;
14256 NEON_ENCODE (IMMED
, inst
);
14257 neon_move_immediate ();
14260 neon_dp_fixup (&inst
);
14263 /* Encode instructions of form:
14265 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14266 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14269 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14271 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14272 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14273 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14274 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14275 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14276 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14277 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14278 inst
.instruction
|= neon_logbits (size
) << 20;
14280 neon_dp_fixup (&inst
);
14284 do_neon_dyadic_long (void)
14286 /* FIXME: Type checking for lengthening op. */
14287 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14288 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14289 neon_mixed_length (et
, et
.size
);
14293 do_neon_abal (void)
14295 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14296 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14297 neon_mixed_length (et
, et
.size
);
14301 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14303 if (inst
.operands
[2].isscalar
)
14305 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14306 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14307 NEON_ENCODE (SCALAR
, inst
);
14308 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14312 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14313 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14314 NEON_ENCODE (INTEGER
, inst
);
14315 neon_mixed_length (et
, et
.size
);
14320 do_neon_mac_maybe_scalar_long (void)
14322 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14326 do_neon_dyadic_wide (void)
14328 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14329 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14330 neon_mixed_length (et
, et
.size
);
14334 do_neon_dyadic_narrow (void)
14336 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14337 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14338 /* Operand sign is unimportant, and the U bit is part of the opcode,
14339 so force the operand type to integer. */
14340 et
.type
= NT_integer
;
14341 neon_mixed_length (et
, et
.size
/ 2);
14345 do_neon_mul_sat_scalar_long (void)
14347 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14351 do_neon_vmull (void)
14353 if (inst
.operands
[2].isscalar
)
14354 do_neon_mac_maybe_scalar_long ();
14357 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14358 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14359 if (et
.type
== NT_poly
)
14360 NEON_ENCODE (POLY
, inst
);
14362 NEON_ENCODE (INTEGER
, inst
);
14363 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14364 zero. Should be OK as-is. */
14365 neon_mixed_length (et
, et
.size
);
14372 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14373 struct neon_type_el et
= neon_check_type (3, rs
,
14374 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14375 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14377 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14378 _("shift out of range"));
14379 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14380 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14381 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14382 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14383 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14384 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14385 inst
.instruction
|= neon_quad (rs
) << 6;
14386 inst
.instruction
|= imm
<< 8;
14388 neon_dp_fixup (&inst
);
14394 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14395 struct neon_type_el et
= neon_check_type (2, rs
,
14396 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14397 unsigned op
= (inst
.instruction
>> 7) & 3;
14398 /* N (width of reversed regions) is encoded as part of the bitmask. We
14399 extract it here to check the elements to be reversed are smaller.
14400 Otherwise we'd get a reserved instruction. */
14401 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14402 gas_assert (elsize
!= 0);
14403 constraint (et
.size
>= elsize
,
14404 _("elements must be smaller than reversal region"));
14405 neon_two_same (neon_quad (rs
), 1, et
.size
);
14411 if (inst
.operands
[1].isscalar
)
14413 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14414 struct neon_type_el et
= neon_check_type (2, rs
,
14415 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14416 unsigned sizebits
= et
.size
>> 3;
14417 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14418 int logsize
= neon_logbits (et
.size
);
14419 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14421 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14424 NEON_ENCODE (SCALAR
, inst
);
14425 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14426 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14427 inst
.instruction
|= LOW4 (dm
);
14428 inst
.instruction
|= HI1 (dm
) << 5;
14429 inst
.instruction
|= neon_quad (rs
) << 6;
14430 inst
.instruction
|= x
<< 17;
14431 inst
.instruction
|= sizebits
<< 16;
14433 neon_dp_fixup (&inst
);
14437 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14438 struct neon_type_el et
= neon_check_type (2, rs
,
14439 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14440 /* Duplicate ARM register to lanes of vector. */
14441 NEON_ENCODE (ARMREG
, inst
);
14444 case 8: inst
.instruction
|= 0x400000; break;
14445 case 16: inst
.instruction
|= 0x000020; break;
14446 case 32: inst
.instruction
|= 0x000000; break;
14449 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14450 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14451 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14452 inst
.instruction
|= neon_quad (rs
) << 21;
14453 /* The encoding for this instruction is identical for the ARM and Thumb
14454 variants, except for the condition field. */
14455 do_vfp_cond_or_thumb ();
14459 /* VMOV has particularly many variations. It can be one of:
14460 0. VMOV<c><q> <Qd>, <Qm>
14461 1. VMOV<c><q> <Dd>, <Dm>
14462 (Register operations, which are VORR with Rm = Rn.)
14463 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14464 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14466 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14467 (ARM register to scalar.)
14468 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14469 (Two ARM registers to vector.)
14470 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14471 (Scalar to ARM register.)
14472 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14473 (Vector to two ARM registers.)
14474 8. VMOV.F32 <Sd>, <Sm>
14475 9. VMOV.F64 <Dd>, <Dm>
14476 (VFP register moves.)
14477 10. VMOV.F32 <Sd>, #imm
14478 11. VMOV.F64 <Dd>, #imm
14479 (VFP float immediate load.)
14480 12. VMOV <Rd>, <Sm>
14481 (VFP single to ARM reg.)
14482 13. VMOV <Sd>, <Rm>
14483 (ARM reg to VFP single.)
14484 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14485 (Two ARM regs to two VFP singles.)
14486 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14487 (Two VFP singles to two ARM regs.)
14489 These cases can be disambiguated using neon_select_shape, except cases 1/9
14490 and 3/11 which depend on the operand type too.
14492 All the encoded bits are hardcoded by this function.
14494 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14495 Cases 5, 7 may be used with VFPv2 and above.
14497 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14498 can specify a type where it doesn't make sense to, and is ignored). */
14503 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14504 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14506 struct neon_type_el et
;
14507 const char *ldconst
= 0;
14511 case NS_DD
: /* case 1/9. */
14512 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14513 /* It is not an error here if no type is given. */
14515 if (et
.type
== NT_float
&& et
.size
== 64)
14517 do_vfp_nsyn_opcode ("fcpyd");
14520 /* fall through. */
14522 case NS_QQ
: /* case 0/1. */
14524 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14526 /* The architecture manual I have doesn't explicitly state which
14527 value the U bit should have for register->register moves, but
14528 the equivalent VORR instruction has U = 0, so do that. */
14529 inst
.instruction
= 0x0200110;
14530 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14531 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14532 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14533 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14534 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14535 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14536 inst
.instruction
|= neon_quad (rs
) << 6;
14538 neon_dp_fixup (&inst
);
14542 case NS_DI
: /* case 3/11. */
14543 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14545 if (et
.type
== NT_float
&& et
.size
== 64)
14547 /* case 11 (fconstd). */
14548 ldconst
= "fconstd";
14549 goto encode_fconstd
;
14551 /* fall through. */
14553 case NS_QI
: /* case 2/3. */
14554 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14556 inst
.instruction
= 0x0800010;
14557 neon_move_immediate ();
14558 neon_dp_fixup (&inst
);
14561 case NS_SR
: /* case 4. */
14563 unsigned bcdebits
= 0;
14565 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14566 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14568 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14569 logsize
= neon_logbits (et
.size
);
14571 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14573 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14574 && et
.size
!= 32, _(BAD_FPU
));
14575 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14576 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14580 case 8: bcdebits
= 0x8; break;
14581 case 16: bcdebits
= 0x1; break;
14582 case 32: bcdebits
= 0x0; break;
14586 bcdebits
|= x
<< logsize
;
14588 inst
.instruction
= 0xe000b10;
14589 do_vfp_cond_or_thumb ();
14590 inst
.instruction
|= LOW4 (dn
) << 16;
14591 inst
.instruction
|= HI1 (dn
) << 7;
14592 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14593 inst
.instruction
|= (bcdebits
& 3) << 5;
14594 inst
.instruction
|= (bcdebits
>> 2) << 21;
14598 case NS_DRR
: /* case 5 (fmdrr). */
14599 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14602 inst
.instruction
= 0xc400b10;
14603 do_vfp_cond_or_thumb ();
14604 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14605 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14606 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14607 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14610 case NS_RS
: /* case 6. */
14613 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14614 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14615 unsigned abcdebits
= 0;
14617 et
= neon_check_type (2, NS_NULL
,
14618 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14619 logsize
= neon_logbits (et
.size
);
14621 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14623 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14624 && et
.size
!= 32, _(BAD_FPU
));
14625 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14626 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14630 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14631 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14632 case 32: abcdebits
= 0x00; break;
14636 abcdebits
|= x
<< logsize
;
14637 inst
.instruction
= 0xe100b10;
14638 do_vfp_cond_or_thumb ();
14639 inst
.instruction
|= LOW4 (dn
) << 16;
14640 inst
.instruction
|= HI1 (dn
) << 7;
14641 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14642 inst
.instruction
|= (abcdebits
& 3) << 5;
14643 inst
.instruction
|= (abcdebits
>> 2) << 21;
14647 case NS_RRD
: /* case 7 (fmrrd). */
14648 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14651 inst
.instruction
= 0xc500b10;
14652 do_vfp_cond_or_thumb ();
14653 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14654 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14655 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14656 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14659 case NS_FF
: /* case 8 (fcpys). */
14660 do_vfp_nsyn_opcode ("fcpys");
14663 case NS_FI
: /* case 10 (fconsts). */
14664 ldconst
= "fconsts";
14666 if (is_quarter_float (inst
.operands
[1].imm
))
14668 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14669 do_vfp_nsyn_opcode (ldconst
);
14672 first_error (_("immediate out of range"));
14675 case NS_RF
: /* case 12 (fmrs). */
14676 do_vfp_nsyn_opcode ("fmrs");
14679 case NS_FR
: /* case 13 (fmsr). */
14680 do_vfp_nsyn_opcode ("fmsr");
14683 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14684 (one of which is a list), but we have parsed four. Do some fiddling to
14685 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14687 case NS_RRFF
: /* case 14 (fmrrs). */
14688 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14689 _("VFP registers must be adjacent"));
14690 inst
.operands
[2].imm
= 2;
14691 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14692 do_vfp_nsyn_opcode ("fmrrs");
14695 case NS_FFRR
: /* case 15 (fmsrr). */
14696 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14697 _("VFP registers must be adjacent"));
14698 inst
.operands
[1] = inst
.operands
[2];
14699 inst
.operands
[2] = inst
.operands
[3];
14700 inst
.operands
[0].imm
= 2;
14701 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14702 do_vfp_nsyn_opcode ("fmsrr");
14711 do_neon_rshift_round_imm (void)
14713 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14714 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14715 int imm
= inst
.operands
[2].imm
;
14717 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14720 inst
.operands
[2].present
= 0;
14725 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14726 _("immediate out of range for shift"));
14727 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14732 do_neon_movl (void)
14734 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14735 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14736 unsigned sizebits
= et
.size
>> 3;
14737 inst
.instruction
|= sizebits
<< 19;
14738 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14744 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14745 struct neon_type_el et
= neon_check_type (2, rs
,
14746 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14747 NEON_ENCODE (INTEGER
, inst
);
14748 neon_two_same (neon_quad (rs
), 1, et
.size
);
14752 do_neon_zip_uzp (void)
14754 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14755 struct neon_type_el et
= neon_check_type (2, rs
,
14756 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14757 if (rs
== NS_DD
&& et
.size
== 32)
14759 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14760 inst
.instruction
= N_MNEM_vtrn
;
14764 neon_two_same (neon_quad (rs
), 1, et
.size
);
14768 do_neon_sat_abs_neg (void)
14770 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14771 struct neon_type_el et
= neon_check_type (2, rs
,
14772 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14773 neon_two_same (neon_quad (rs
), 1, et
.size
);
14777 do_neon_pair_long (void)
14779 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14780 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14781 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14782 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14783 neon_two_same (neon_quad (rs
), 1, et
.size
);
14787 do_neon_recip_est (void)
14789 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14790 struct neon_type_el et
= neon_check_type (2, rs
,
14791 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14792 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14793 neon_two_same (neon_quad (rs
), 1, et
.size
);
14799 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14800 struct neon_type_el et
= neon_check_type (2, rs
,
14801 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14802 neon_two_same (neon_quad (rs
), 1, et
.size
);
14808 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14809 struct neon_type_el et
= neon_check_type (2, rs
,
14810 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14811 neon_two_same (neon_quad (rs
), 1, et
.size
);
14817 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14818 struct neon_type_el et
= neon_check_type (2, rs
,
14819 N_EQK
| N_INT
, N_8
| N_KEY
);
14820 neon_two_same (neon_quad (rs
), 1, et
.size
);
14826 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14827 neon_two_same (neon_quad (rs
), 1, -1);
14831 do_neon_tbl_tbx (void)
14833 unsigned listlenbits
;
14834 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14836 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14838 first_error (_("bad list length for table lookup"));
14842 listlenbits
= inst
.operands
[1].imm
- 1;
14843 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14844 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14845 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14846 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14847 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14848 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14849 inst
.instruction
|= listlenbits
<< 8;
14851 neon_dp_fixup (&inst
);
14855 do_neon_ldm_stm (void)
14857 /* P, U and L bits are part of bitmask. */
14858 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14859 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14861 if (inst
.operands
[1].issingle
)
14863 do_vfp_nsyn_ldm_stm (is_dbmode
);
14867 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14868 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14870 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14871 _("register list must contain at least 1 and at most 16 "
14874 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14875 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14876 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14877 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14879 inst
.instruction
|= offsetbits
;
14881 do_vfp_cond_or_thumb ();
14885 do_neon_ldr_str (void)
14887 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14889 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
14890 And is UNPREDICTABLE in thumb mode. */
14892 && inst
.operands
[1].reg
== REG_PC
14893 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
14895 if (!thumb_mode
&& warn_on_deprecated
)
14896 as_warn (_("Use of PC here is deprecated"));
14898 inst
.error
= _("Use of PC here is UNPREDICTABLE");
14901 if (inst
.operands
[0].issingle
)
14904 do_vfp_nsyn_opcode ("flds");
14906 do_vfp_nsyn_opcode ("fsts");
14911 do_vfp_nsyn_opcode ("fldd");
14913 do_vfp_nsyn_opcode ("fstd");
14917 /* "interleave" version also handles non-interleaving register VLD1/VST1
14921 do_neon_ld_st_interleave (void)
14923 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14924 N_8
| N_16
| N_32
| N_64
);
14925 unsigned alignbits
= 0;
14927 /* The bits in this table go:
14928 0: register stride of one (0) or two (1)
14929 1,2: register list length, minus one (1, 2, 3, 4).
14930 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14931 We use -1 for invalid entries. */
14932 const int typetable
[] =
14934 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14935 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14936 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14937 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14941 if (et
.type
== NT_invtype
)
14944 if (inst
.operands
[1].immisalign
)
14945 switch (inst
.operands
[1].imm
>> 8)
14947 case 64: alignbits
= 1; break;
14949 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14950 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14951 goto bad_alignment
;
14955 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14956 goto bad_alignment
;
14961 first_error (_("bad alignment"));
14965 inst
.instruction
|= alignbits
<< 4;
14966 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14968 /* Bits [4:6] of the immediate in a list specifier encode register stride
14969 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14970 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14971 up the right value for "type" in a table based on this value and the given
14972 list style, then stick it back. */
14973 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14974 | (((inst
.instruction
>> 8) & 3) << 3);
14976 typebits
= typetable
[idx
];
14978 constraint (typebits
== -1, _("bad list type for instruction"));
14980 inst
.instruction
&= ~0xf00;
14981 inst
.instruction
|= typebits
<< 8;
14984 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14985 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14986 otherwise. The variable arguments are a list of pairs of legal (size, align)
14987 values, terminated with -1. */
14990 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14993 int result
= FAIL
, thissize
, thisalign
;
14995 if (!inst
.operands
[1].immisalign
)
15001 va_start (ap
, do_align
);
15005 thissize
= va_arg (ap
, int);
15006 if (thissize
== -1)
15008 thisalign
= va_arg (ap
, int);
15010 if (size
== thissize
&& align
== thisalign
)
15013 while (result
!= SUCCESS
);
15017 if (result
== SUCCESS
)
15020 first_error (_("unsupported alignment for instruction"));
15026 do_neon_ld_st_lane (void)
15028 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15029 int align_good
, do_align
= 0;
15030 int logsize
= neon_logbits (et
.size
);
15031 int align
= inst
.operands
[1].imm
>> 8;
15032 int n
= (inst
.instruction
>> 8) & 3;
15033 int max_el
= 64 / et
.size
;
15035 if (et
.type
== NT_invtype
)
15038 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15039 _("bad list length"));
15040 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15041 _("scalar index out of range"));
15042 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15044 _("stride of 2 unavailable when element size is 8"));
15048 case 0: /* VLD1 / VST1. */
15049 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15051 if (align_good
== FAIL
)
15055 unsigned alignbits
= 0;
15058 case 16: alignbits
= 0x1; break;
15059 case 32: alignbits
= 0x3; break;
15062 inst
.instruction
|= alignbits
<< 4;
15066 case 1: /* VLD2 / VST2. */
15067 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15069 if (align_good
== FAIL
)
15072 inst
.instruction
|= 1 << 4;
15075 case 2: /* VLD3 / VST3. */
15076 constraint (inst
.operands
[1].immisalign
,
15077 _("can't use alignment with this instruction"));
15080 case 3: /* VLD4 / VST4. */
15081 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15082 16, 64, 32, 64, 32, 128, -1);
15083 if (align_good
== FAIL
)
15087 unsigned alignbits
= 0;
15090 case 8: alignbits
= 0x1; break;
15091 case 16: alignbits
= 0x1; break;
15092 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15095 inst
.instruction
|= alignbits
<< 4;
15102 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15103 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15104 inst
.instruction
|= 1 << (4 + logsize
);
15106 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15107 inst
.instruction
|= logsize
<< 10;
15110 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15113 do_neon_ld_dup (void)
15115 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15116 int align_good
, do_align
= 0;
15118 if (et
.type
== NT_invtype
)
15121 switch ((inst
.instruction
>> 8) & 3)
15123 case 0: /* VLD1. */
15124 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15125 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15126 &do_align
, 16, 16, 32, 32, -1);
15127 if (align_good
== FAIL
)
15129 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15132 case 2: inst
.instruction
|= 1 << 5; break;
15133 default: first_error (_("bad list length")); return;
15135 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15138 case 1: /* VLD2. */
15139 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15140 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15141 if (align_good
== FAIL
)
15143 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15144 _("bad list length"));
15145 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15146 inst
.instruction
|= 1 << 5;
15147 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15150 case 2: /* VLD3. */
15151 constraint (inst
.operands
[1].immisalign
,
15152 _("can't use alignment with this instruction"));
15153 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15154 _("bad list length"));
15155 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15156 inst
.instruction
|= 1 << 5;
15157 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15160 case 3: /* VLD4. */
15162 int align
= inst
.operands
[1].imm
>> 8;
15163 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15164 16, 64, 32, 64, 32, 128, -1);
15165 if (align_good
== FAIL
)
15167 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15168 _("bad list length"));
15169 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15170 inst
.instruction
|= 1 << 5;
15171 if (et
.size
== 32 && align
== 128)
15172 inst
.instruction
|= 0x3 << 6;
15174 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15181 inst
.instruction
|= do_align
<< 4;
15184 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15185 apart from bits [11:4]. */
15188 do_neon_ldx_stx (void)
15190 if (inst
.operands
[1].isreg
)
15191 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15193 switch (NEON_LANE (inst
.operands
[0].imm
))
15195 case NEON_INTERLEAVE_LANES
:
15196 NEON_ENCODE (INTERLV
, inst
);
15197 do_neon_ld_st_interleave ();
15200 case NEON_ALL_LANES
:
15201 NEON_ENCODE (DUP
, inst
);
15206 NEON_ENCODE (LANE
, inst
);
15207 do_neon_ld_st_lane ();
15210 /* L bit comes from bit mask. */
15211 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15212 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15213 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15215 if (inst
.operands
[1].postind
)
15217 int postreg
= inst
.operands
[1].imm
& 0xf;
15218 constraint (!inst
.operands
[1].immisreg
,
15219 _("post-index must be a register"));
15220 constraint (postreg
== 0xd || postreg
== 0xf,
15221 _("bad register for post-index"));
15222 inst
.instruction
|= postreg
;
15224 else if (inst
.operands
[1].writeback
)
15226 inst
.instruction
|= 0xd;
15229 inst
.instruction
|= 0xf;
15232 inst
.instruction
|= 0xf9000000;
15234 inst
.instruction
|= 0xf4000000;
15237 /* Overall per-instruction processing. */
15239 /* We need to be able to fix up arbitrary expressions in some statements.
15240 This is so that we can handle symbols that are an arbitrary distance from
15241 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15242 which returns part of an address in a form which will be valid for
15243 a data instruction. We do this by pushing the expression into a symbol
15244 in the expr_section, and creating a fix for that. */
15247 fix_new_arm (fragS
* frag
,
15262 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15263 (enum bfd_reloc_code_real
) reloc
);
15267 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15268 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15272 /* Mark whether the fix is to a THUMB instruction, or an ARM
15274 new_fix
->tc_fix_data
= thumb_mode
;
15277 /* Create a frg for an instruction requiring relaxation. */
15279 output_relax_insn (void)
15285 /* The size of the instruction is unknown, so tie the debug info to the
15286 start of the instruction. */
15287 dwarf2_emit_insn (0);
15289 switch (inst
.reloc
.exp
.X_op
)
15292 sym
= inst
.reloc
.exp
.X_add_symbol
;
15293 offset
= inst
.reloc
.exp
.X_add_number
;
15297 offset
= inst
.reloc
.exp
.X_add_number
;
15300 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15304 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15305 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15306 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15309 /* Write a 32-bit thumb instruction to buf. */
15311 put_thumb32_insn (char * buf
, unsigned long insn
)
15313 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15314 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15318 output_inst (const char * str
)
15324 as_bad ("%s -- `%s'", inst
.error
, str
);
15329 output_relax_insn ();
15332 if (inst
.size
== 0)
15335 to
= frag_more (inst
.size
);
15336 /* PR 9814: Record the thumb mode into the current frag so that we know
15337 what type of NOP padding to use, if necessary. We override any previous
15338 setting so that if the mode has changed then the NOPS that we use will
15339 match the encoding of the last instruction in the frag. */
15340 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15342 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15344 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15345 put_thumb32_insn (to
, inst
.instruction
);
15347 else if (inst
.size
> INSN_SIZE
)
15349 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15350 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15351 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15354 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15356 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15357 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15358 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15361 dwarf2_emit_insn (inst
.size
);
15365 output_it_inst (int cond
, int mask
, char * to
)
15367 unsigned long instruction
= 0xbf00;
15370 instruction
|= mask
;
15371 instruction
|= cond
<< 4;
15375 to
= frag_more (2);
15377 dwarf2_emit_insn (2);
15381 md_number_to_chars (to
, instruction
, 2);
15386 /* Tag values used in struct asm_opcode's tag field. */
15389 OT_unconditional
, /* Instruction cannot be conditionalized.
15390 The ARM condition field is still 0xE. */
15391 OT_unconditionalF
, /* Instruction cannot be conditionalized
15392 and carries 0xF in its ARM condition field. */
15393 OT_csuffix
, /* Instruction takes a conditional suffix. */
15394 OT_csuffixF
, /* Some forms of the instruction take a conditional
15395 suffix, others place 0xF where the condition field
15397 OT_cinfix3
, /* Instruction takes a conditional infix,
15398 beginning at character index 3. (In
15399 unified mode, it becomes a suffix.) */
15400 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15401 tsts, cmps, cmns, and teqs. */
15402 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15403 character index 3, even in unified mode. Used for
15404 legacy instructions where suffix and infix forms
15405 may be ambiguous. */
15406 OT_csuf_or_in3
, /* Instruction takes either a conditional
15407 suffix or an infix at character index 3. */
15408 OT_odd_infix_unc
, /* This is the unconditional variant of an
15409 instruction that takes a conditional infix
15410 at an unusual position. In unified mode,
15411 this variant will accept a suffix. */
15412 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15413 are the conditional variants of instructions that
15414 take conditional infixes in unusual positions.
15415 The infix appears at character index
15416 (tag - OT_odd_infix_0). These are not accepted
15417 in unified mode. */
15420 /* Subroutine of md_assemble, responsible for looking up the primary
15421 opcode from the mnemonic the user wrote. STR points to the
15422 beginning of the mnemonic.
15424 This is not simply a hash table lookup, because of conditional
15425 variants. Most instructions have conditional variants, which are
15426 expressed with a _conditional affix_ to the mnemonic. If we were
15427 to encode each conditional variant as a literal string in the opcode
15428 table, it would have approximately 20,000 entries.
15430 Most mnemonics take this affix as a suffix, and in unified syntax,
15431 'most' is upgraded to 'all'. However, in the divided syntax, some
15432 instructions take the affix as an infix, notably the s-variants of
15433 the arithmetic instructions. Of those instructions, all but six
15434 have the infix appear after the third character of the mnemonic.
15436 Accordingly, the algorithm for looking up primary opcodes given
15439 1. Look up the identifier in the opcode table.
15440 If we find a match, go to step U.
15442 2. Look up the last two characters of the identifier in the
15443 conditions table. If we find a match, look up the first N-2
15444 characters of the identifier in the opcode table. If we
15445 find a match, go to step CE.
15447 3. Look up the fourth and fifth characters of the identifier in
15448 the conditions table. If we find a match, extract those
15449 characters from the identifier, and look up the remaining
15450 characters in the opcode table. If we find a match, go
15455 U. Examine the tag field of the opcode structure, in case this is
15456 one of the six instructions with its conditional infix in an
15457 unusual place. If it is, the tag tells us where to find the
15458 infix; look it up in the conditions table and set inst.cond
15459 accordingly. Otherwise, this is an unconditional instruction.
15460 Again set inst.cond accordingly. Return the opcode structure.
15462 CE. Examine the tag field to make sure this is an instruction that
15463 should receive a conditional suffix. If it is not, fail.
15464 Otherwise, set inst.cond from the suffix we already looked up,
15465 and return the opcode structure.
15467 CM. Examine the tag field to make sure this is an instruction that
15468 should receive a conditional infix after the third character.
15469 If it is not, fail. Otherwise, undo the edits to the current
15470 line of input and proceed as for case CE. */
15472 static const struct asm_opcode
*
15473 opcode_lookup (char **str
)
15477 const struct asm_opcode
*opcode
;
15478 const struct asm_cond
*cond
;
15481 /* Scan up to the end of the mnemonic, which must end in white space,
15482 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15483 for (base
= end
= *str
; *end
!= '\0'; end
++)
15484 if (*end
== ' ' || *end
== '.')
15490 /* Handle a possible width suffix and/or Neon type suffix. */
15495 /* The .w and .n suffixes are only valid if the unified syntax is in
15497 if (unified_syntax
&& end
[1] == 'w')
15499 else if (unified_syntax
&& end
[1] == 'n')
15504 inst
.vectype
.elems
= 0;
15506 *str
= end
+ offset
;
15508 if (end
[offset
] == '.')
15510 /* See if we have a Neon type suffix (possible in either unified or
15511 non-unified ARM syntax mode). */
15512 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15515 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15521 /* Look for unaffixed or special-case affixed mnemonic. */
15522 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15527 if (opcode
->tag
< OT_odd_infix_0
)
15529 inst
.cond
= COND_ALWAYS
;
15533 if (warn_on_deprecated
&& unified_syntax
)
15534 as_warn (_("conditional infixes are deprecated in unified syntax"));
15535 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15536 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15539 inst
.cond
= cond
->value
;
15543 /* Cannot have a conditional suffix on a mnemonic of less than two
15545 if (end
- base
< 3)
15548 /* Look for suffixed mnemonic. */
15550 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15551 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15553 if (opcode
&& cond
)
15556 switch (opcode
->tag
)
15558 case OT_cinfix3_legacy
:
15559 /* Ignore conditional suffixes matched on infix only mnemonics. */
15563 case OT_cinfix3_deprecated
:
15564 case OT_odd_infix_unc
:
15565 if (!unified_syntax
)
15567 /* else fall through */
15571 case OT_csuf_or_in3
:
15572 inst
.cond
= cond
->value
;
15575 case OT_unconditional
:
15576 case OT_unconditionalF
:
15578 inst
.cond
= cond
->value
;
15581 /* Delayed diagnostic. */
15582 inst
.error
= BAD_COND
;
15583 inst
.cond
= COND_ALWAYS
;
15592 /* Cannot have a usual-position infix on a mnemonic of less than
15593 six characters (five would be a suffix). */
15594 if (end
- base
< 6)
15597 /* Look for infixed mnemonic in the usual position. */
15599 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15603 memcpy (save
, affix
, 2);
15604 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15605 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15607 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15608 memcpy (affix
, save
, 2);
15611 && (opcode
->tag
== OT_cinfix3
15612 || opcode
->tag
== OT_cinfix3_deprecated
15613 || opcode
->tag
== OT_csuf_or_in3
15614 || opcode
->tag
== OT_cinfix3_legacy
))
15617 if (warn_on_deprecated
&& unified_syntax
15618 && (opcode
->tag
== OT_cinfix3
15619 || opcode
->tag
== OT_cinfix3_deprecated
))
15620 as_warn (_("conditional infixes are deprecated in unified syntax"));
15622 inst
.cond
= cond
->value
;
15629 /* This function generates an initial IT instruction, leaving its block
15630 virtually open for the new instructions. Eventually,
15631 the mask will be updated by now_it_add_mask () each time
15632 a new instruction needs to be included in the IT block.
15633 Finally, the block is closed with close_automatic_it_block ().
15634 The block closure can be requested either from md_assemble (),
15635 a tencode (), or due to a label hook. */
15638 new_automatic_it_block (int cond
)
15640 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15641 now_it
.mask
= 0x18;
15643 now_it
.block_length
= 1;
15644 mapping_state (MAP_THUMB
);
15645 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15648 /* Close an automatic IT block.
15649 See comments in new_automatic_it_block (). */
15652 close_automatic_it_block (void)
15654 now_it
.mask
= 0x10;
15655 now_it
.block_length
= 0;
15658 /* Update the mask of the current automatically-generated IT
15659 instruction. See comments in new_automatic_it_block (). */
15662 now_it_add_mask (int cond
)
15664 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15665 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15666 | ((bitvalue) << (nbit)))
15667 const int resulting_bit
= (cond
& 1);
15669 now_it
.mask
&= 0xf;
15670 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15672 (5 - now_it
.block_length
));
15673 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15675 ((5 - now_it
.block_length
) - 1) );
15676 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15679 #undef SET_BIT_VALUE
15682 /* The IT blocks handling machinery is accessed through the these functions:
15683 it_fsm_pre_encode () from md_assemble ()
15684 set_it_insn_type () optional, from the tencode functions
15685 set_it_insn_type_last () ditto
15686 in_it_block () ditto
15687 it_fsm_post_encode () from md_assemble ()
15688 force_automatic_it_block_close () from label habdling functions
15691 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15692 initializing the IT insn type with a generic initial value depending
15693 on the inst.condition.
15694 2) During the tencode function, two things may happen:
15695 a) The tencode function overrides the IT insn type by
15696 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15697 b) The tencode function queries the IT block state by
15698 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15700 Both set_it_insn_type and in_it_block run the internal FSM state
15701 handling function (handle_it_state), because: a) setting the IT insn
15702 type may incur in an invalid state (exiting the function),
15703 and b) querying the state requires the FSM to be updated.
15704 Specifically we want to avoid creating an IT block for conditional
15705 branches, so it_fsm_pre_encode is actually a guess and we can't
15706 determine whether an IT block is required until the tencode () routine
15707 has decided what type of instruction this actually it.
15708 Because of this, if set_it_insn_type and in_it_block have to be used,
15709 set_it_insn_type has to be called first.
15711 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15712 determines the insn IT type depending on the inst.cond code.
15713 When a tencode () routine encodes an instruction that can be
15714 either outside an IT block, or, in the case of being inside, has to be
15715 the last one, set_it_insn_type_last () will determine the proper
15716 IT instruction type based on the inst.cond code. Otherwise,
15717 set_it_insn_type can be called for overriding that logic or
15718 for covering other cases.
15720 Calling handle_it_state () may not transition the IT block state to
15721 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15722 still queried. Instead, if the FSM determines that the state should
15723 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15724 after the tencode () function: that's what it_fsm_post_encode () does.
15726 Since in_it_block () calls the state handling function to get an
15727 updated state, an error may occur (due to invalid insns combination).
15728 In that case, inst.error is set.
15729 Therefore, inst.error has to be checked after the execution of
15730 the tencode () routine.
15732 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15733 any pending state change (if any) that didn't take place in
15734 handle_it_state () as explained above. */
15737 it_fsm_pre_encode (void)
15739 if (inst
.cond
!= COND_ALWAYS
)
15740 inst
.it_insn_type
= INSIDE_IT_INSN
;
15742 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15744 now_it
.state_handled
= 0;
15747 /* IT state FSM handling function. */
15750 handle_it_state (void)
15752 now_it
.state_handled
= 1;
15754 switch (now_it
.state
)
15756 case OUTSIDE_IT_BLOCK
:
15757 switch (inst
.it_insn_type
)
15759 case OUTSIDE_IT_INSN
:
15762 case INSIDE_IT_INSN
:
15763 case INSIDE_IT_LAST_INSN
:
15764 if (thumb_mode
== 0)
15767 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15768 as_tsktsk (_("Warning: conditional outside an IT block"\
15773 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15774 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15776 /* Automatically generate the IT instruction. */
15777 new_automatic_it_block (inst
.cond
);
15778 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15779 close_automatic_it_block ();
15783 inst
.error
= BAD_OUT_IT
;
15789 case IF_INSIDE_IT_LAST_INSN
:
15790 case NEUTRAL_IT_INSN
:
15794 now_it
.state
= MANUAL_IT_BLOCK
;
15795 now_it
.block_length
= 0;
15800 case AUTOMATIC_IT_BLOCK
:
15801 /* Three things may happen now:
15802 a) We should increment current it block size;
15803 b) We should close current it block (closing insn or 4 insns);
15804 c) We should close current it block and start a new one (due
15805 to incompatible conditions or
15806 4 insns-length block reached). */
15808 switch (inst
.it_insn_type
)
15810 case OUTSIDE_IT_INSN
:
15811 /* The closure of the block shall happen immediatelly,
15812 so any in_it_block () call reports the block as closed. */
15813 force_automatic_it_block_close ();
15816 case INSIDE_IT_INSN
:
15817 case INSIDE_IT_LAST_INSN
:
15818 case IF_INSIDE_IT_LAST_INSN
:
15819 now_it
.block_length
++;
15821 if (now_it
.block_length
> 4
15822 || !now_it_compatible (inst
.cond
))
15824 force_automatic_it_block_close ();
15825 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15826 new_automatic_it_block (inst
.cond
);
15830 now_it_add_mask (inst
.cond
);
15833 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15834 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15835 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15836 close_automatic_it_block ();
15839 case NEUTRAL_IT_INSN
:
15840 now_it
.block_length
++;
15842 if (now_it
.block_length
> 4)
15843 force_automatic_it_block_close ();
15845 now_it_add_mask (now_it
.cc
& 1);
15849 close_automatic_it_block ();
15850 now_it
.state
= MANUAL_IT_BLOCK
;
15855 case MANUAL_IT_BLOCK
:
15857 /* Check conditional suffixes. */
15858 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15861 now_it
.mask
&= 0x1f;
15862 is_last
= (now_it
.mask
== 0x10);
15864 switch (inst
.it_insn_type
)
15866 case OUTSIDE_IT_INSN
:
15867 inst
.error
= BAD_NOT_IT
;
15870 case INSIDE_IT_INSN
:
15871 if (cond
!= inst
.cond
)
15873 inst
.error
= BAD_IT_COND
;
15878 case INSIDE_IT_LAST_INSN
:
15879 case IF_INSIDE_IT_LAST_INSN
:
15880 if (cond
!= inst
.cond
)
15882 inst
.error
= BAD_IT_COND
;
15887 inst
.error
= BAD_BRANCH
;
15892 case NEUTRAL_IT_INSN
:
15893 /* The BKPT instruction is unconditional even in an IT block. */
15897 inst
.error
= BAD_IT_IT
;
15908 it_fsm_post_encode (void)
15912 if (!now_it
.state_handled
)
15913 handle_it_state ();
15915 is_last
= (now_it
.mask
== 0x10);
15918 now_it
.state
= OUTSIDE_IT_BLOCK
;
15924 force_automatic_it_block_close (void)
15926 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15928 close_automatic_it_block ();
15929 now_it
.state
= OUTSIDE_IT_BLOCK
;
15937 if (!now_it
.state_handled
)
15938 handle_it_state ();
15940 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15944 md_assemble (char *str
)
15947 const struct asm_opcode
* opcode
;
15949 /* Align the previous label if needed. */
15950 if (last_label_seen
!= NULL
)
15952 symbol_set_frag (last_label_seen
, frag_now
);
15953 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15954 S_SET_SEGMENT (last_label_seen
, now_seg
);
15957 memset (&inst
, '\0', sizeof (inst
));
15958 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15960 opcode
= opcode_lookup (&p
);
15963 /* It wasn't an instruction, but it might be a register alias of
15964 the form alias .req reg, or a Neon .dn/.qn directive. */
15965 if (! create_register_alias (str
, p
)
15966 && ! create_neon_reg_alias (str
, p
))
15967 as_bad (_("bad instruction `%s'"), str
);
15972 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15973 as_warn (_("s suffix on comparison instruction is deprecated"));
15975 /* The value which unconditional instructions should have in place of the
15976 condition field. */
15977 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15981 arm_feature_set variant
;
15983 variant
= cpu_variant
;
15984 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15985 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15986 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15987 /* Check that this instruction is supported for this CPU. */
15988 if (!opcode
->tvariant
15989 || (thumb_mode
== 1
15990 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15992 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15995 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15996 && opcode
->tencode
!= do_t_branch
)
15998 as_bad (_("Thumb does not support conditional execution"));
16002 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16004 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16005 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16006 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16008 /* Two things are addressed here.
16009 1) Implicit require narrow instructions on Thumb-1.
16010 This avoids relaxation accidentally introducing Thumb-2
16012 2) Reject wide instructions in non Thumb-2 cores. */
16013 if (inst
.size_req
== 0)
16015 else if (inst
.size_req
== 4)
16017 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16023 inst
.instruction
= opcode
->tvalue
;
16025 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16027 /* Prepare the it_insn_type for those encodings that don't set
16029 it_fsm_pre_encode ();
16031 opcode
->tencode ();
16033 it_fsm_post_encode ();
16036 if (!(inst
.error
|| inst
.relax
))
16038 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16039 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16040 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16042 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16047 /* Something has gone badly wrong if we try to relax a fixed size
16049 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16051 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16052 *opcode
->tvariant
);
16053 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16054 set those bits when Thumb-2 32-bit instructions are seen. ie.
16055 anything other than bl/blx and v6-M instructions.
16056 This is overly pessimistic for relaxable instructions. */
16057 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16059 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16060 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16061 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16064 check_neon_suffixes
;
16068 mapping_state (MAP_THUMB
);
16071 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16075 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16076 is_bx
= (opcode
->aencode
== do_bx
);
16078 /* Check that this instruction is supported for this CPU. */
16079 if (!(is_bx
&& fix_v4bx
)
16080 && !(opcode
->avariant
&&
16081 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16083 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16088 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16092 inst
.instruction
= opcode
->avalue
;
16093 if (opcode
->tag
== OT_unconditionalF
)
16094 inst
.instruction
|= 0xF << 28;
16096 inst
.instruction
|= inst
.cond
<< 28;
16097 inst
.size
= INSN_SIZE
;
16098 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16100 it_fsm_pre_encode ();
16101 opcode
->aencode ();
16102 it_fsm_post_encode ();
16104 /* Arm mode bx is marked as both v4T and v5 because it's still required
16105 on a hypothetical non-thumb v5 core. */
16107 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16109 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16110 *opcode
->avariant
);
16112 check_neon_suffixes
;
16116 mapping_state (MAP_ARM
);
16121 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16129 check_it_blocks_finished (void)
16134 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16135 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16136 == MANUAL_IT_BLOCK
)
16138 as_warn (_("section '%s' finished with an open IT block."),
16142 if (now_it
.state
== MANUAL_IT_BLOCK
)
16143 as_warn (_("file finished with an open IT block."));
16147 /* Various frobbings of labels and their addresses. */
16150 arm_start_line_hook (void)
16152 last_label_seen
= NULL
;
16156 arm_frob_label (symbolS
* sym
)
16158 last_label_seen
= sym
;
16160 ARM_SET_THUMB (sym
, thumb_mode
);
16162 #if defined OBJ_COFF || defined OBJ_ELF
16163 ARM_SET_INTERWORK (sym
, support_interwork
);
16166 force_automatic_it_block_close ();
16168 /* Note - do not allow local symbols (.Lxxx) to be labelled
16169 as Thumb functions. This is because these labels, whilst
16170 they exist inside Thumb code, are not the entry points for
16171 possible ARM->Thumb calls. Also, these labels can be used
16172 as part of a computed goto or switch statement. eg gcc
16173 can generate code that looks like this:
16175 ldr r2, [pc, .Laaa]
16185 The first instruction loads the address of the jump table.
16186 The second instruction converts a table index into a byte offset.
16187 The third instruction gets the jump address out of the table.
16188 The fourth instruction performs the jump.
16190 If the address stored at .Laaa is that of a symbol which has the
16191 Thumb_Func bit set, then the linker will arrange for this address
16192 to have the bottom bit set, which in turn would mean that the
16193 address computation performed by the third instruction would end
16194 up with the bottom bit set. Since the ARM is capable of unaligned
16195 word loads, the instruction would then load the incorrect address
16196 out of the jump table, and chaos would ensue. */
16197 if (label_is_thumb_function_name
16198 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16199 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16201 /* When the address of a Thumb function is taken the bottom
16202 bit of that address should be set. This will allow
16203 interworking between Arm and Thumb functions to work
16206 THUMB_SET_FUNC (sym
, 1);
16208 label_is_thumb_function_name
= FALSE
;
16211 dwarf2_emit_label (sym
);
16215 arm_data_in_code (void)
16217 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16219 *input_line_pointer
= '/';
16220 input_line_pointer
+= 5;
16221 *input_line_pointer
= 0;
16229 arm_canonicalize_symbol_name (char * name
)
16233 if (thumb_mode
&& (len
= strlen (name
)) > 5
16234 && streq (name
+ len
- 5, "/data"))
16235 *(name
+ len
- 5) = 0;
16240 /* Table of all register names defined by default. The user can
16241 define additional names with .req. Note that all register names
16242 should appear in both upper and lowercase variants. Some registers
16243 also have mixed-case names. */
16245 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16246 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16247 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16248 #define REGSET(p,t) \
16249 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16250 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16251 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16252 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16253 #define REGSETH(p,t) \
16254 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16255 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16256 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16257 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16258 #define REGSET2(p,t) \
16259 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16260 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16261 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16262 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16263 #define SPLRBANK(base,bank,t) \
16264 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16265 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16266 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16267 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16268 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16269 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16271 static const struct reg_entry reg_names
[] =
16273 /* ARM integer registers. */
16274 REGSET(r
, RN
), REGSET(R
, RN
),
16276 /* ATPCS synonyms. */
16277 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16278 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16279 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16281 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16282 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16283 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16285 /* Well-known aliases. */
16286 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16287 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16289 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16290 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16292 /* Coprocessor numbers. */
16293 REGSET(p
, CP
), REGSET(P
, CP
),
16295 /* Coprocessor register numbers. The "cr" variants are for backward
16297 REGSET(c
, CN
), REGSET(C
, CN
),
16298 REGSET(cr
, CN
), REGSET(CR
, CN
),
16300 /* ARM banked registers. */
16301 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16302 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16303 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16304 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16305 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16306 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16307 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16309 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16310 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16311 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16312 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16313 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16314 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16315 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16316 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16318 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16319 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16320 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16321 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16322 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16323 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16324 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16325 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16326 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16328 /* FPA registers. */
16329 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16330 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16332 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16333 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16335 /* VFP SP registers. */
16336 REGSET(s
,VFS
), REGSET(S
,VFS
),
16337 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16339 /* VFP DP Registers. */
16340 REGSET(d
,VFD
), REGSET(D
,VFD
),
16341 /* Extra Neon DP registers. */
16342 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16344 /* Neon QP registers. */
16345 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16347 /* VFP control registers. */
16348 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16349 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16350 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16351 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16352 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16353 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16355 /* Maverick DSP coprocessor registers. */
16356 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16357 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16359 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16360 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16361 REGDEF(dspsc
,0,DSPSC
),
16363 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16364 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16365 REGDEF(DSPSC
,0,DSPSC
),
16367 /* iWMMXt data registers - p0, c0-15. */
16368 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16370 /* iWMMXt control registers - p1, c0-3. */
16371 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16372 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16373 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16374 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16376 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16377 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16378 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16379 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16380 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16382 /* XScale accumulator registers. */
16383 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16389 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16390 within psr_required_here. */
16391 static const struct asm_psr psrs
[] =
16393 /* Backward compatibility notation. Note that "all" is no longer
16394 truly all possible PSR bits. */
16395 {"all", PSR_c
| PSR_f
},
16399 /* Individual flags. */
16406 /* Combinations of flags. */
16407 {"fs", PSR_f
| PSR_s
},
16408 {"fx", PSR_f
| PSR_x
},
16409 {"fc", PSR_f
| PSR_c
},
16410 {"sf", PSR_s
| PSR_f
},
16411 {"sx", PSR_s
| PSR_x
},
16412 {"sc", PSR_s
| PSR_c
},
16413 {"xf", PSR_x
| PSR_f
},
16414 {"xs", PSR_x
| PSR_s
},
16415 {"xc", PSR_x
| PSR_c
},
16416 {"cf", PSR_c
| PSR_f
},
16417 {"cs", PSR_c
| PSR_s
},
16418 {"cx", PSR_c
| PSR_x
},
16419 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16420 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16421 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16422 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16423 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16424 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16425 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16426 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16427 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16428 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16429 {"scf", PSR_s
| PSR_c
| PSR_f
},
16430 {"scx", PSR_s
| PSR_c
| PSR_x
},
16431 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16432 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16433 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16434 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16435 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16436 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16437 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16438 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16439 {"csf", PSR_c
| PSR_s
| PSR_f
},
16440 {"csx", PSR_c
| PSR_s
| PSR_x
},
16441 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16442 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16443 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16444 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16445 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16446 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16447 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16448 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16449 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16450 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16451 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16452 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16453 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16454 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16455 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16456 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16457 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16458 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16459 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16460 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16461 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16462 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16463 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16464 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16465 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16466 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16470 {"nzcvqg", PSR_s
| PSR_f
}
16473 /* Table of V7M psr names. */
16474 static const struct asm_psr v7m_psrs
[] =
16476 {"apsr", 0 }, {"APSR", 0 },
16477 {"iapsr", 1 }, {"IAPSR", 1 },
16478 {"eapsr", 2 }, {"EAPSR", 2 },
16479 {"psr", 3 }, {"PSR", 3 },
16480 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16481 {"ipsr", 5 }, {"IPSR", 5 },
16482 {"epsr", 6 }, {"EPSR", 6 },
16483 {"iepsr", 7 }, {"IEPSR", 7 },
16484 {"msp", 8 }, {"MSP", 8 },
16485 {"psp", 9 }, {"PSP", 9 },
16486 {"primask", 16}, {"PRIMASK", 16},
16487 {"basepri", 17}, {"BASEPRI", 17},
16488 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16489 {"faultmask", 19}, {"FAULTMASK", 19},
16490 {"control", 20}, {"CONTROL", 20}
16493 /* Table of all shift-in-operand names. */
16494 static const struct asm_shift_name shift_names
[] =
16496 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16497 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16498 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16499 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16500 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16501 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16504 /* Table of all explicit relocation names. */
16506 static struct reloc_entry reloc_names
[] =
16508 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16509 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16510 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16511 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16512 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16513 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16514 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16515 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16516 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16517 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16518 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16519 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16523 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16524 static const struct asm_cond conds
[] =
16528 {"cs", 0x2}, {"hs", 0x2},
16529 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16543 static struct asm_barrier_opt barrier_opt_names
[] =
16545 { "sy", 0xf }, { "SY", 0xf },
16546 { "un", 0x7 }, { "UN", 0x7 },
16547 { "st", 0xe }, { "ST", 0xe },
16548 { "unst", 0x6 }, { "UNST", 0x6 },
16549 { "ish", 0xb }, { "ISH", 0xb },
16550 { "sh", 0xb }, { "SH", 0xb },
16551 { "ishst", 0xa }, { "ISHST", 0xa },
16552 { "shst", 0xa }, { "SHST", 0xa },
16553 { "nsh", 0x7 }, { "NSH", 0x7 },
16554 { "nshst", 0x6 }, { "NSHST", 0x6 },
16555 { "osh", 0x3 }, { "OSH", 0x3 },
16556 { "oshst", 0x2 }, { "OSHST", 0x2 }
16559 /* Table of ARM-format instructions. */
16561 /* Macros for gluing together operand strings. N.B. In all cases
16562 other than OPS0, the trailing OP_stop comes from default
16563 zero-initialization of the unspecified elements of the array. */
16564 #define OPS0() { OP_stop, }
16565 #define OPS1(a) { OP_##a, }
16566 #define OPS2(a,b) { OP_##a,OP_##b, }
16567 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16568 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16569 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16570 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16572 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16573 This is useful when mixing operands for ARM and THUMB, i.e. using the
16574 MIX_ARM_THUMB_OPERANDS macro.
16575 In order to use these macros, prefix the number of operands with _
16577 #define OPS_1(a) { a, }
16578 #define OPS_2(a,b) { a,b, }
16579 #define OPS_3(a,b,c) { a,b,c, }
16580 #define OPS_4(a,b,c,d) { a,b,c,d, }
16581 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16582 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16584 /* These macros abstract out the exact format of the mnemonic table and
16585 save some repeated characters. */
16587 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16588 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16589 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16590 THUMB_VARIANT, do_##ae, do_##te }
16592 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16593 a T_MNEM_xyz enumerator. */
16594 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16595 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16596 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16597 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16599 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16600 infix after the third character. */
16601 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16602 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16603 THUMB_VARIANT, do_##ae, do_##te }
16604 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16605 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16606 THUMB_VARIANT, do_##ae, do_##te }
16607 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16608 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16609 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16610 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16611 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16612 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16613 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16614 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16616 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16617 appear in the condition table. */
16618 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16619 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16620 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16622 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16623 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16624 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16625 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16626 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16627 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16628 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16629 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16630 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16631 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16632 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16633 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16634 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16635 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16636 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16637 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16638 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16639 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16640 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16641 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16643 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16644 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16645 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16646 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16648 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16649 field is still 0xE. Many of the Thumb variants can be executed
16650 conditionally, so this is checked separately. */
16651 #define TUE(mnem, op, top, nops, ops, ae, te) \
16652 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16653 THUMB_VARIANT, do_##ae, do_##te }
16655 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16656 condition code field. */
16657 #define TUF(mnem, op, top, nops, ops, ae, te) \
16658 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16659 THUMB_VARIANT, do_##ae, do_##te }
16661 /* ARM-only variants of all the above. */
16662 #define CE(mnem, op, nops, ops, ae) \
16663 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16665 #define C3(mnem, op, nops, ops, ae) \
16666 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16668 /* Legacy mnemonics that always have conditional infix after the third
16670 #define CL(mnem, op, nops, ops, ae) \
16671 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16672 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16674 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16675 #define cCE(mnem, op, nops, ops, ae) \
16676 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16678 /* Legacy coprocessor instructions where conditional infix and conditional
16679 suffix are ambiguous. For consistency this includes all FPA instructions,
16680 not just the potentially ambiguous ones. */
16681 #define cCL(mnem, op, nops, ops, ae) \
16682 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16683 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16685 /* Coprocessor, takes either a suffix or a position-3 infix
16686 (for an FPA corner case). */
16687 #define C3E(mnem, op, nops, ops, ae) \
16688 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16689 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16691 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16692 { m1 #m2 m3, OPS##nops ops, \
16693 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16694 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16696 #define CM(m1, m2, op, nops, ops, ae) \
16697 xCM_ (m1, , m2, op, nops, ops, ae), \
16698 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16699 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16700 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16701 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16702 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16703 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16704 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16705 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16706 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16707 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16708 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16709 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16710 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16711 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16712 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16713 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16714 xCM_ (m1, le, m2, op, nops, ops, ae), \
16715 xCM_ (m1, al, m2, op, nops, ops, ae)
16717 #define UE(mnem, op, nops, ops, ae) \
16718 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16720 #define UF(mnem, op, nops, ops, ae) \
16721 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16723 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16724 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16725 use the same encoding function for each. */
16726 #define NUF(mnem, op, nops, ops, enc) \
16727 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16728 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16730 /* Neon data processing, version which indirects through neon_enc_tab for
16731 the various overloaded versions of opcodes. */
16732 #define nUF(mnem, op, nops, ops, enc) \
16733 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16734 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16736 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16738 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16739 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16740 THUMB_VARIANT, do_##enc, do_##enc }
16742 #define NCE(mnem, op, nops, ops, enc) \
16743 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16745 #define NCEF(mnem, op, nops, ops, enc) \
16746 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16748 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16749 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16750 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16751 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16753 #define nCE(mnem, op, nops, ops, enc) \
16754 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16756 #define nCEF(mnem, op, nops, ops, enc) \
16757 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16761 static const struct asm_opcode insns
[] =
16763 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16764 #define THUMB_VARIANT &arm_ext_v4t
16765 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16766 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16767 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16768 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16769 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16770 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16771 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16772 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16773 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16774 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16775 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16776 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16777 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16778 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16779 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16780 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16782 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16783 for setting PSR flag bits. They are obsolete in V6 and do not
16784 have Thumb equivalents. */
16785 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16786 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16787 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16788 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16789 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16790 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16791 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16792 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16793 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16795 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16796 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16797 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16798 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16800 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16801 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16802 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16804 OP_ADDRGLDR
),ldst
, t_ldst
),
16805 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16807 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16808 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16809 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16810 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16811 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16812 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16814 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16815 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16816 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16817 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16820 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16821 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16822 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16824 /* Thumb-compatibility pseudo ops. */
16825 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16826 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16827 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16828 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16829 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16830 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16831 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16832 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16833 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16834 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16835 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16836 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16838 /* These may simplify to neg. */
16839 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16840 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16842 #undef THUMB_VARIANT
16843 #define THUMB_VARIANT & arm_ext_v6
16845 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16847 /* V1 instructions with no Thumb analogue prior to V6T2. */
16848 #undef THUMB_VARIANT
16849 #define THUMB_VARIANT & arm_ext_v6t2
16851 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16852 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16853 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16855 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16856 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16857 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16858 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16860 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16861 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16863 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16864 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16866 /* V1 instructions with no Thumb analogue at all. */
16867 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16868 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16870 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16871 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16872 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16873 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16874 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16875 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16876 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16877 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16880 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16881 #undef THUMB_VARIANT
16882 #define THUMB_VARIANT & arm_ext_v4t
16884 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16885 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16887 #undef THUMB_VARIANT
16888 #define THUMB_VARIANT & arm_ext_v6t2
16890 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16891 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16893 /* Generic coprocessor instructions. */
16894 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16895 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16896 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16897 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16898 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16899 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16900 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16903 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16905 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16906 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16909 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16910 #undef THUMB_VARIANT
16911 #define THUMB_VARIANT & arm_ext_msr
16913 TCE("mrs", 1000000, f3e08000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16914 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16917 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16918 #undef THUMB_VARIANT
16919 #define THUMB_VARIANT & arm_ext_v6t2
16921 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16922 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16923 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16924 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16925 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16926 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16927 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16928 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16931 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16932 #undef THUMB_VARIANT
16933 #define THUMB_VARIANT & arm_ext_v4t
16935 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16936 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16937 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16938 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16939 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16940 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16943 #define ARM_VARIANT & arm_ext_v4t_5
16945 /* ARM Architecture 4T. */
16946 /* Note: bx (and blx) are required on V5, even if the processor does
16947 not support Thumb. */
16948 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16951 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16952 #undef THUMB_VARIANT
16953 #define THUMB_VARIANT & arm_ext_v5t
16955 /* Note: blx has 2 variants; the .value coded here is for
16956 BLX(2). Only this variant has conditional execution. */
16957 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16958 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16960 #undef THUMB_VARIANT
16961 #define THUMB_VARIANT & arm_ext_v6t2
16963 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16964 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16965 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16966 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16967 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16968 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16969 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16970 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16973 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16974 #undef THUMB_VARIANT
16975 #define THUMB_VARIANT &arm_ext_v5exp
16977 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16978 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16979 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16980 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16982 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16983 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16985 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16986 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16987 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16988 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16990 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16991 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16992 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16993 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16995 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16996 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16998 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16999 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17000 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17001 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17004 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17005 #undef THUMB_VARIANT
17006 #define THUMB_VARIANT &arm_ext_v6t2
17008 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17009 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17011 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17012 ADDRGLDRS
), ldrd
, t_ldstd
),
17014 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17015 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17018 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17020 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17023 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17024 #undef THUMB_VARIANT
17025 #define THUMB_VARIANT & arm_ext_v6
17027 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17028 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17029 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17030 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17031 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17032 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17033 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17034 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17035 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17036 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17038 #undef THUMB_VARIANT
17039 #define THUMB_VARIANT & arm_ext_v6t2
17041 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17042 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17044 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17045 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17047 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17048 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17050 /* ARM V6 not included in V7M. */
17051 #undef THUMB_VARIANT
17052 #define THUMB_VARIANT & arm_ext_v6_notm
17053 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17054 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17055 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17056 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17057 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17058 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17059 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17060 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17061 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17062 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17063 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17064 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17066 /* ARM V6 not included in V7M (eg. integer SIMD). */
17067 #undef THUMB_VARIANT
17068 #define THUMB_VARIANT & arm_ext_v6_dsp
17069 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17070 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17071 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17072 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17073 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17074 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17075 /* Old name for QASX. */
17076 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17077 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17078 /* Old name for QSAX. */
17079 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17080 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17081 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17082 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17083 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17084 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17085 /* Old name for SASX. */
17086 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17087 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17088 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17089 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17090 /* Old name for SHASX. */
17091 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17092 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17093 /* Old name for SHSAX. */
17094 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17095 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17096 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17097 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17098 /* Old name for SSAX. */
17099 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17100 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17101 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17102 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17103 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17104 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17105 /* Old name for UASX. */
17106 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17107 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17108 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17109 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17110 /* Old name for UHASX. */
17111 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17112 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17113 /* Old name for UHSAX. */
17114 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17115 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17116 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17117 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17118 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17119 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17120 /* Old name for UQASX. */
17121 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17122 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17123 /* Old name for UQSAX. */
17124 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17125 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17126 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17127 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17128 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17129 /* Old name for USAX. */
17130 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17131 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17132 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17133 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17134 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17135 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17136 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17137 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17138 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17139 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17140 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17141 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17142 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17143 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17144 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17145 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17146 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17147 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17148 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17149 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17150 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17151 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17152 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17153 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17154 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17155 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17156 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17157 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17158 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17159 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17160 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17161 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17162 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17163 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17166 #define ARM_VARIANT & arm_ext_v6k
17167 #undef THUMB_VARIANT
17168 #define THUMB_VARIANT & arm_ext_v6k
17170 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17171 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17172 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17173 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17175 #undef THUMB_VARIANT
17176 #define THUMB_VARIANT & arm_ext_v6_notm
17177 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17179 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17180 RRnpcb
), strexd
, t_strexd
),
17182 #undef THUMB_VARIANT
17183 #define THUMB_VARIANT & arm_ext_v6t2
17184 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17186 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17188 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17190 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17192 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17195 #define ARM_VARIANT & arm_ext_sec
17196 #undef THUMB_VARIANT
17197 #define THUMB_VARIANT & arm_ext_sec
17199 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17202 #define ARM_VARIANT & arm_ext_virt
17203 #undef THUMB_VARIANT
17204 #define THUMB_VARIANT & arm_ext_virt
17206 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17207 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17210 #define ARM_VARIANT & arm_ext_v6t2
17211 #undef THUMB_VARIANT
17212 #define THUMB_VARIANT & arm_ext_v6t2
17214 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17215 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17216 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17217 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17219 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17220 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17221 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17222 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17224 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17225 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17226 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17227 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17229 /* Thumb-only instructions. */
17231 #define ARM_VARIANT NULL
17232 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17233 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17235 /* ARM does not really have an IT instruction, so always allow it.
17236 The opcode is copied from Thumb in order to allow warnings in
17237 -mimplicit-it=[never | arm] modes. */
17239 #define ARM_VARIANT & arm_ext_v1
17241 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17242 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17243 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17244 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17245 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17246 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17247 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17248 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17249 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17250 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17251 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17252 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17253 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17254 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17255 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17256 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17257 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17258 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17260 /* Thumb2 only instructions. */
17262 #define ARM_VARIANT NULL
17264 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17265 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17266 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17267 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17268 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17269 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17271 /* Hardware division instructions. */
17273 #define ARM_VARIANT & arm_ext_adiv
17274 #undef THUMB_VARIANT
17275 #define THUMB_VARIANT & arm_ext_div
17277 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17278 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17280 /* ARM V6M/V7 instructions. */
17282 #define ARM_VARIANT & arm_ext_barrier
17283 #undef THUMB_VARIANT
17284 #define THUMB_VARIANT & arm_ext_barrier
17286 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17287 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17288 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17290 /* ARM V7 instructions. */
17292 #define ARM_VARIANT & arm_ext_v7
17293 #undef THUMB_VARIANT
17294 #define THUMB_VARIANT & arm_ext_v7
17296 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17297 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17300 #define ARM_VARIANT & arm_ext_mp
17301 #undef THUMB_VARIANT
17302 #define THUMB_VARIANT & arm_ext_mp
17304 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17307 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17309 cCE("wfs", e200110
, 1, (RR
), rd
),
17310 cCE("rfs", e300110
, 1, (RR
), rd
),
17311 cCE("wfc", e400110
, 1, (RR
), rd
),
17312 cCE("rfc", e500110
, 1, (RR
), rd
),
17314 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17315 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17316 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17317 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17319 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17320 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17321 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17322 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17324 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17325 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17326 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17327 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17328 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17329 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17330 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17331 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17332 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17333 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17334 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17335 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17337 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17338 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17339 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17340 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17341 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17342 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17343 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17344 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17345 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17346 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17347 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17348 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17350 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17351 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17352 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17353 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17354 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17355 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17356 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17357 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17358 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17359 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17360 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17361 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17363 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17364 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17365 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17366 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17367 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17368 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17369 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17370 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17371 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17372 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17373 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17374 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17376 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17377 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17378 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17379 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17380 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17381 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17382 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17383 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17384 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17385 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17386 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17387 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17389 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17390 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17391 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17392 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17393 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17394 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17395 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17396 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17397 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17398 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17399 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17400 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17402 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17403 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17404 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17405 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17406 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17407 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17408 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17409 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17410 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17411 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17412 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17413 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17415 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17416 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17417 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17418 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17419 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17420 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17421 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17422 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17423 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17424 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17425 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17426 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17428 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17429 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17430 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17431 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17432 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17433 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17434 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17435 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17436 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17437 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17438 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17439 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17441 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17442 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17443 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17444 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17445 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17446 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17447 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17448 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17449 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17450 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17451 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17452 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17454 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17455 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17456 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17457 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17458 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17459 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17460 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17461 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17462 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17463 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17464 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17465 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17467 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17468 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17469 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17470 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17471 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17472 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17473 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17474 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17475 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17476 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17477 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17478 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17480 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17481 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17482 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17483 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17484 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17485 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17486 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17487 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17488 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17489 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17490 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17491 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17493 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17494 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17495 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17496 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17497 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17498 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17499 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17500 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17501 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17502 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17503 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17504 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17506 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17507 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17508 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17509 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17510 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17511 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17512 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17513 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17514 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17515 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17516 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17517 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17519 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17520 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17521 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17522 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17523 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17524 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17525 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17526 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17527 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17528 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17529 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17530 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17532 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17533 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17534 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17535 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17536 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17537 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17538 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17539 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17540 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17541 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17542 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17543 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17545 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17546 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17547 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17548 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17549 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17550 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17551 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17552 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17553 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17554 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17555 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17556 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17558 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17559 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17560 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17561 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17562 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17563 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17564 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17565 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17566 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17567 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17568 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17569 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17571 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17572 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17573 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17574 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17575 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17576 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17577 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17578 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17579 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17580 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17581 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17582 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17584 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17585 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17586 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17587 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17588 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17589 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17590 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17591 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17592 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17593 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17594 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17595 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17597 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17598 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17599 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17600 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17601 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17602 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17603 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17604 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17605 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17606 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17607 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17608 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17610 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17611 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17612 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17613 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17614 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17615 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17616 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17617 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17618 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17619 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17620 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17621 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17623 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17624 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17625 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17626 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17627 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17628 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17629 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17630 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17631 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17632 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17633 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17634 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17636 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17637 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17638 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17639 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17640 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17641 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17642 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17643 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17644 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17645 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17646 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17647 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17649 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17650 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17651 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17652 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17653 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17654 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17655 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17656 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17657 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17658 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17659 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17660 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17662 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17663 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17664 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17665 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17666 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17667 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17668 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17669 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17670 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17671 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17672 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17673 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17675 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17676 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17677 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17678 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17679 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17680 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17681 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17682 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17683 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17684 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17685 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17686 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17688 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17689 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17690 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17691 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17692 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17693 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17694 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17695 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17696 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17697 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17698 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17699 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17701 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17702 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17703 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17704 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17706 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17707 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17708 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17709 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17710 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17711 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17712 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17713 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17714 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17715 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17716 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17717 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17719 /* The implementation of the FIX instruction is broken on some
17720 assemblers, in that it accepts a precision specifier as well as a
17721 rounding specifier, despite the fact that this is meaningless.
17722 To be more compatible, we accept it as well, though of course it
17723 does not set any bits. */
17724 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17725 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17726 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17727 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17728 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17729 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17730 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17731 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17732 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17733 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17734 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17735 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17736 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17738 /* Instructions that were new with the real FPA, call them V2. */
17740 #define ARM_VARIANT & fpu_fpa_ext_v2
17742 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17743 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17744 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17745 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17746 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17747 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17750 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17752 /* Moves and type conversions. */
17753 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17754 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17755 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17756 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17757 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17758 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17759 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17760 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17761 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17762 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17763 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17764 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17765 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17766 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17768 /* Memory operations. */
17769 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17770 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17771 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17772 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17773 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17774 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17775 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17776 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17777 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17778 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17779 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17780 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17781 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17782 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17783 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17784 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17785 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17786 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17788 /* Monadic operations. */
17789 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17790 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17791 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17793 /* Dyadic operations. */
17794 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17795 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17796 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17797 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17798 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17799 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17800 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17801 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17802 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17805 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17806 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17807 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17808 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17810 /* Double precision load/store are still present on single precision
17811 implementations. */
17812 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17813 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17814 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17815 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17816 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17817 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17818 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17819 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17820 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17821 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17824 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17826 /* Moves and type conversions. */
17827 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17828 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17829 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17830 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17831 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17832 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17833 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17834 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17835 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17836 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17837 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17838 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17839 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17841 /* Monadic operations. */
17842 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17843 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17844 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17846 /* Dyadic operations. */
17847 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17848 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17849 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17850 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17851 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17852 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17853 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17854 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17855 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17858 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17859 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17860 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17861 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17864 #define ARM_VARIANT & fpu_vfp_ext_v2
17866 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17867 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17868 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17869 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17871 /* Instructions which may belong to either the Neon or VFP instruction sets.
17872 Individual encoder functions perform additional architecture checks. */
17874 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17875 #undef THUMB_VARIANT
17876 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17878 /* These mnemonics are unique to VFP. */
17879 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17880 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17881 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17882 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17883 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17884 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17885 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17886 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17887 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17888 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17890 /* Mnemonics shared by Neon and VFP. */
17891 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17892 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17893 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17895 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17896 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17898 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17899 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17901 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17902 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17903 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17904 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17905 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17906 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17907 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17908 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17910 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17911 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17912 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17913 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17916 /* NOTE: All VMOV encoding is special-cased! */
17917 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17918 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17920 #undef THUMB_VARIANT
17921 #define THUMB_VARIANT & fpu_neon_ext_v1
17923 #define ARM_VARIANT & fpu_neon_ext_v1
17925 /* Data processing with three registers of the same length. */
17926 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17927 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17928 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17929 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17930 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17931 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17932 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17933 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17934 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17935 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17936 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17937 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17938 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17939 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17940 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17941 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17942 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17943 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17944 /* If not immediate, fall back to neon_dyadic_i64_su.
17945 shl_imm should accept I8 I16 I32 I64,
17946 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17947 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17948 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17949 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17950 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17951 /* Logic ops, types optional & ignored. */
17952 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17953 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17954 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17955 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17956 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17957 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17958 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17959 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17960 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17961 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17962 /* Bitfield ops, untyped. */
17963 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17964 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17965 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17966 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17967 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17968 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17969 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17970 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17971 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17972 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17973 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17974 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17975 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17976 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17977 back to neon_dyadic_if_su. */
17978 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17979 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17980 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17981 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17982 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17983 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17984 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17985 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17986 /* Comparison. Type I8 I16 I32 F32. */
17987 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17988 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17989 /* As above, D registers only. */
17990 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17991 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17992 /* Int and float variants, signedness unimportant. */
17993 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17994 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17995 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17996 /* Add/sub take types I8 I16 I32 I64 F32. */
17997 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17998 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17999 /* vtst takes sizes 8, 16, 32. */
18000 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18001 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18002 /* VMUL takes I8 I16 I32 F32 P8. */
18003 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18004 /* VQD{R}MULH takes S16 S32. */
18005 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18006 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18007 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18008 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18009 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18010 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18011 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18012 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18013 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18014 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18015 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18016 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18017 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18018 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18019 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18020 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18022 /* Two address, int/float. Types S8 S16 S32 F32. */
18023 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18024 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18026 /* Data processing with two registers and a shift amount. */
18027 /* Right shifts, and variants with rounding.
18028 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18029 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18030 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18031 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18032 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18033 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18034 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18035 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18036 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18037 /* Shift and insert. Sizes accepted 8 16 32 64. */
18038 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18039 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18040 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18041 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18042 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18043 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18044 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18045 /* Right shift immediate, saturating & narrowing, with rounding variants.
18046 Types accepted S16 S32 S64 U16 U32 U64. */
18047 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18048 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18049 /* As above, unsigned. Types accepted S16 S32 S64. */
18050 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18051 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18052 /* Right shift narrowing. Types accepted I16 I32 I64. */
18053 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18054 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18055 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18056 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18057 /* CVT with optional immediate for fixed-point variant. */
18058 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18060 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18061 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18063 /* Data processing, three registers of different lengths. */
18064 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18065 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18066 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18067 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18068 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18069 /* If not scalar, fall back to neon_dyadic_long.
18070 Vector types as above, scalar types S16 S32 U16 U32. */
18071 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18072 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18073 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18074 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18075 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18076 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18077 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18078 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18079 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18080 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18081 /* Saturating doubling multiplies. Types S16 S32. */
18082 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18083 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18084 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18085 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18086 S16 S32 U16 U32. */
18087 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18089 /* Extract. Size 8. */
18090 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18091 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18093 /* Two registers, miscellaneous. */
18094 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18095 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18096 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18097 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18098 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18099 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18100 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18101 /* Vector replicate. Sizes 8 16 32. */
18102 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18103 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18104 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18105 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18106 /* VMOVN. Types I16 I32 I64. */
18107 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18108 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18109 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18110 /* VQMOVUN. Types S16 S32 S64. */
18111 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18112 /* VZIP / VUZP. Sizes 8 16 32. */
18113 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18114 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18115 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18116 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18117 /* VQABS / VQNEG. Types S8 S16 S32. */
18118 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18119 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18120 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18121 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18122 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18123 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18124 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18125 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18126 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18127 /* Reciprocal estimates. Types U32 F32. */
18128 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18129 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18130 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18131 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18132 /* VCLS. Types S8 S16 S32. */
18133 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18134 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18135 /* VCLZ. Types I8 I16 I32. */
18136 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18137 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18138 /* VCNT. Size 8. */
18139 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18140 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18141 /* Two address, untyped. */
18142 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18143 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18144 /* VTRN. Sizes 8 16 32. */
18145 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18146 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18148 /* Table lookup. Size 8. */
18149 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18150 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18152 #undef THUMB_VARIANT
18153 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18155 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18157 /* Neon element/structure load/store. */
18158 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18159 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18160 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18161 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18162 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18163 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18164 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18165 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18167 #undef THUMB_VARIANT
18168 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18170 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18171 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18172 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18173 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18174 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18175 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18176 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18177 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18178 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18179 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18181 #undef THUMB_VARIANT
18182 #define THUMB_VARIANT & fpu_vfp_ext_v3
18184 #define ARM_VARIANT & fpu_vfp_ext_v3
18186 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18187 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18188 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18189 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18190 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18191 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18192 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18193 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18194 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18197 #define ARM_VARIANT &fpu_vfp_ext_fma
18198 #undef THUMB_VARIANT
18199 #define THUMB_VARIANT &fpu_vfp_ext_fma
18200 /* Mnemonics shared by Neon and VFP. These are included in the
18201 VFP FMA variant; NEON and VFP FMA always includes the NEON
18202 FMA instructions. */
18203 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18204 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18205 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18206 the v form should always be used. */
18207 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18208 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18209 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18210 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18211 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18212 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18214 #undef THUMB_VARIANT
18216 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18218 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18219 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18220 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18221 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18222 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18223 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18224 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18225 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18228 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18230 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18231 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18232 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18233 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18234 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18235 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18236 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18237 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18238 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18239 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18240 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18241 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18242 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18243 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18244 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18245 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18246 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18247 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18248 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18249 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18250 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18251 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18252 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18253 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18254 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18255 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18256 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18257 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18258 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18259 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18260 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18261 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18262 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18263 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18264 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18265 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18266 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18267 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18268 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18269 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18270 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18271 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18272 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18273 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18274 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18275 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18276 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18277 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18278 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18279 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18280 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18281 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18282 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18283 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18284 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18285 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18286 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18287 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18288 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18289 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18290 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18291 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18292 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18293 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18294 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18295 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18296 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18297 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18298 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18299 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18300 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18301 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18302 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18303 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18304 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18305 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18306 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18307 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18308 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18309 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18310 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18311 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18312 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18313 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18314 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18315 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18316 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18317 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18318 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18319 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18320 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18321 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18322 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18323 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18324 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18325 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18326 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18327 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18328 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18329 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18330 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18331 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18332 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18333 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18334 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18335 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18336 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18337 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18338 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18339 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18340 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18341 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18342 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18343 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18344 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18345 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18346 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18347 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18348 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18349 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18350 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18351 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18352 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18353 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18354 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18355 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18356 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18357 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18358 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18359 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18360 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18361 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18362 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18363 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18364 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18365 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18366 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18367 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18368 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18369 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18370 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18371 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18372 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18373 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18374 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18375 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18376 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18377 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18378 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18379 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18380 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18381 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18382 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18383 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18384 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18385 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18386 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18387 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18388 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18389 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18390 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18391 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18394 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18396 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18397 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18398 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18399 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18400 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18401 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18402 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18403 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18404 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18405 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18406 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18407 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18408 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18409 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18410 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18411 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18412 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18413 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18414 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18415 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18416 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18417 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18418 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18419 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18420 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18421 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18422 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18423 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18424 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18425 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18426 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18427 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18428 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18429 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18430 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18431 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18432 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18433 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18434 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18435 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18436 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18437 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18438 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18439 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18440 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18441 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18442 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18443 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18444 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18445 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18446 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18447 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18448 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18449 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18450 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18451 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18452 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18455 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18457 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18458 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18459 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18460 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18461 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18462 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18463 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18464 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18465 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18466 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18467 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18468 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18469 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18470 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18471 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18472 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18473 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18474 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18475 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18476 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18477 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18478 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18479 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18480 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18481 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18482 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18483 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18484 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18485 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18486 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18487 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18488 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18489 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18490 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18491 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18492 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18493 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18494 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18495 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18496 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18497 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18498 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18499 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18500 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18501 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18502 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18503 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18504 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18505 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18506 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18507 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18508 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18509 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18510 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18511 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18512 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18513 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18514 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18515 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18516 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18517 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18518 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18519 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18520 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18521 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18522 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18523 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18524 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18525 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18526 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18527 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18528 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18529 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18530 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18531 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18532 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18535 #undef THUMB_VARIANT
18562 /* MD interface: bits in the object file. */
18564 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18565 for use in the a.out file, and stores them in the array pointed to by buf.
18566 This knows about the endian-ness of the target machine and does
18567 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18568 2 (short) and 4 (long) Floating numbers are put out as a series of
18569 LITTLENUMS (shorts, here at least). */
18572 md_number_to_chars (char * buf
, valueT val
, int n
)
18574 if (target_big_endian
)
18575 number_to_chars_bigendian (buf
, val
, n
);
18577 number_to_chars_littleendian (buf
, val
, n
);
18581 md_chars_to_number (char * buf
, int n
)
18584 unsigned char * where
= (unsigned char *) buf
;
18586 if (target_big_endian
)
18591 result
|= (*where
++ & 255);
18599 result
|= (where
[n
] & 255);
18606 /* MD interface: Sections. */
18608 /* Estimate the size of a frag before relaxing. Assume everything fits in
18612 md_estimate_size_before_relax (fragS
* fragp
,
18613 segT segtype ATTRIBUTE_UNUSED
)
18619 /* Convert a machine dependent frag. */
18622 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18624 unsigned long insn
;
18625 unsigned long old_op
;
18633 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18635 old_op
= bfd_get_16(abfd
, buf
);
18636 if (fragp
->fr_symbol
)
18638 exp
.X_op
= O_symbol
;
18639 exp
.X_add_symbol
= fragp
->fr_symbol
;
18643 exp
.X_op
= O_constant
;
18645 exp
.X_add_number
= fragp
->fr_offset
;
18646 opcode
= fragp
->fr_subtype
;
18649 case T_MNEM_ldr_pc
:
18650 case T_MNEM_ldr_pc2
:
18651 case T_MNEM_ldr_sp
:
18652 case T_MNEM_str_sp
:
18659 if (fragp
->fr_var
== 4)
18661 insn
= THUMB_OP32 (opcode
);
18662 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18664 insn
|= (old_op
& 0x700) << 4;
18668 insn
|= (old_op
& 7) << 12;
18669 insn
|= (old_op
& 0x38) << 13;
18671 insn
|= 0x00000c00;
18672 put_thumb32_insn (buf
, insn
);
18673 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18677 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18679 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18682 if (fragp
->fr_var
== 4)
18684 insn
= THUMB_OP32 (opcode
);
18685 insn
|= (old_op
& 0xf0) << 4;
18686 put_thumb32_insn (buf
, insn
);
18687 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18691 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18692 exp
.X_add_number
-= 4;
18700 if (fragp
->fr_var
== 4)
18702 int r0off
= (opcode
== T_MNEM_mov
18703 || opcode
== T_MNEM_movs
) ? 0 : 8;
18704 insn
= THUMB_OP32 (opcode
);
18705 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18706 insn
|= (old_op
& 0x700) << r0off
;
18707 put_thumb32_insn (buf
, insn
);
18708 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18712 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18717 if (fragp
->fr_var
== 4)
18719 insn
= THUMB_OP32(opcode
);
18720 put_thumb32_insn (buf
, insn
);
18721 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18724 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18728 if (fragp
->fr_var
== 4)
18730 insn
= THUMB_OP32(opcode
);
18731 insn
|= (old_op
& 0xf00) << 14;
18732 put_thumb32_insn (buf
, insn
);
18733 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18736 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18739 case T_MNEM_add_sp
:
18740 case T_MNEM_add_pc
:
18741 case T_MNEM_inc_sp
:
18742 case T_MNEM_dec_sp
:
18743 if (fragp
->fr_var
== 4)
18745 /* ??? Choose between add and addw. */
18746 insn
= THUMB_OP32 (opcode
);
18747 insn
|= (old_op
& 0xf0) << 4;
18748 put_thumb32_insn (buf
, insn
);
18749 if (opcode
== T_MNEM_add_pc
)
18750 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18752 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18755 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18763 if (fragp
->fr_var
== 4)
18765 insn
= THUMB_OP32 (opcode
);
18766 insn
|= (old_op
& 0xf0) << 4;
18767 insn
|= (old_op
& 0xf) << 16;
18768 put_thumb32_insn (buf
, insn
);
18769 if (insn
& (1 << 20))
18770 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18772 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18775 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18781 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18782 (enum bfd_reloc_code_real
) reloc_type
);
18783 fixp
->fx_file
= fragp
->fr_file
;
18784 fixp
->fx_line
= fragp
->fr_line
;
18785 fragp
->fr_fix
+= fragp
->fr_var
;
18788 /* Return the size of a relaxable immediate operand instruction.
18789 SHIFT and SIZE specify the form of the allowable immediate. */
18791 relax_immediate (fragS
*fragp
, int size
, int shift
)
18797 /* ??? Should be able to do better than this. */
18798 if (fragp
->fr_symbol
)
18801 low
= (1 << shift
) - 1;
18802 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18803 offset
= fragp
->fr_offset
;
18804 /* Force misaligned offsets to 32-bit variant. */
18807 if (offset
& ~mask
)
18812 /* Get the address of a symbol during relaxation. */
18814 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18820 sym
= fragp
->fr_symbol
;
18821 sym_frag
= symbol_get_frag (sym
);
18822 know (S_GET_SEGMENT (sym
) != absolute_section
18823 || sym_frag
== &zero_address_frag
);
18824 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18826 /* If frag has yet to be reached on this pass, assume it will
18827 move by STRETCH just as we did. If this is not so, it will
18828 be because some frag between grows, and that will force
18832 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18836 /* Adjust stretch for any alignment frag. Note that if have
18837 been expanding the earlier code, the symbol may be
18838 defined in what appears to be an earlier frag. FIXME:
18839 This doesn't handle the fr_subtype field, which specifies
18840 a maximum number of bytes to skip when doing an
18842 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18844 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18847 stretch
= - ((- stretch
)
18848 & ~ ((1 << (int) f
->fr_offset
) - 1));
18850 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18862 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18865 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18870 /* Assume worst case for symbols not known to be in the same section. */
18871 if (fragp
->fr_symbol
== NULL
18872 || !S_IS_DEFINED (fragp
->fr_symbol
)
18873 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18874 || S_IS_WEAK (fragp
->fr_symbol
))
18877 val
= relaxed_symbol_addr (fragp
, stretch
);
18878 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18879 addr
= (addr
+ 4) & ~3;
18880 /* Force misaligned targets to 32-bit variant. */
18884 if (val
< 0 || val
> 1020)
18889 /* Return the size of a relaxable add/sub immediate instruction. */
18891 relax_addsub (fragS
*fragp
, asection
*sec
)
18896 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18897 op
= bfd_get_16(sec
->owner
, buf
);
18898 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18899 return relax_immediate (fragp
, 8, 0);
18901 return relax_immediate (fragp
, 3, 0);
18905 /* Return the size of a relaxable branch instruction. BITS is the
18906 size of the offset field in the narrow instruction. */
18909 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18915 /* Assume worst case for symbols not known to be in the same section. */
18916 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18917 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18918 || S_IS_WEAK (fragp
->fr_symbol
))
18922 if (S_IS_DEFINED (fragp
->fr_symbol
)
18923 && ARM_IS_FUNC (fragp
->fr_symbol
))
18927 val
= relaxed_symbol_addr (fragp
, stretch
);
18928 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18931 /* Offset is a signed value *2 */
18933 if (val
>= limit
|| val
< -limit
)
18939 /* Relax a machine dependent frag. This returns the amount by which
18940 the current size of the frag should change. */
18943 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18948 oldsize
= fragp
->fr_var
;
18949 switch (fragp
->fr_subtype
)
18951 case T_MNEM_ldr_pc2
:
18952 newsize
= relax_adr (fragp
, sec
, stretch
);
18954 case T_MNEM_ldr_pc
:
18955 case T_MNEM_ldr_sp
:
18956 case T_MNEM_str_sp
:
18957 newsize
= relax_immediate (fragp
, 8, 2);
18961 newsize
= relax_immediate (fragp
, 5, 2);
18965 newsize
= relax_immediate (fragp
, 5, 1);
18969 newsize
= relax_immediate (fragp
, 5, 0);
18972 newsize
= relax_adr (fragp
, sec
, stretch
);
18978 newsize
= relax_immediate (fragp
, 8, 0);
18981 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18984 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18986 case T_MNEM_add_sp
:
18987 case T_MNEM_add_pc
:
18988 newsize
= relax_immediate (fragp
, 8, 2);
18990 case T_MNEM_inc_sp
:
18991 case T_MNEM_dec_sp
:
18992 newsize
= relax_immediate (fragp
, 7, 2);
18998 newsize
= relax_addsub (fragp
, sec
);
19004 fragp
->fr_var
= newsize
;
19005 /* Freeze wide instructions that are at or before the same location as
19006 in the previous pass. This avoids infinite loops.
19007 Don't freeze them unconditionally because targets may be artificially
19008 misaligned by the expansion of preceding frags. */
19009 if (stretch
<= 0 && newsize
> 2)
19011 md_convert_frag (sec
->owner
, sec
, fragp
);
19015 return newsize
- oldsize
;
19018 /* Round up a section size to the appropriate boundary. */
19021 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19024 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19025 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19027 /* For a.out, force the section size to be aligned. If we don't do
19028 this, BFD will align it for us, but it will not write out the
19029 final bytes of the section. This may be a bug in BFD, but it is
19030 easier to fix it here since that is how the other a.out targets
19034 align
= bfd_get_section_alignment (stdoutput
, segment
);
19035 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19042 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19043 of an rs_align_code fragment. */
19046 arm_handle_align (fragS
* fragP
)
19048 static char const arm_noop
[2][2][4] =
19051 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19052 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19055 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19056 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19059 static char const thumb_noop
[2][2][2] =
19062 {0xc0, 0x46}, /* LE */
19063 {0x46, 0xc0}, /* BE */
19066 {0x00, 0xbf}, /* LE */
19067 {0xbf, 0x00} /* BE */
19070 static char const wide_thumb_noop
[2][4] =
19071 { /* Wide Thumb-2 */
19072 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19073 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19076 unsigned bytes
, fix
, noop_size
;
19079 const char *narrow_noop
= NULL
;
19084 if (fragP
->fr_type
!= rs_align_code
)
19087 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19088 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19091 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19092 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19094 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19096 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19098 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19100 narrow_noop
= thumb_noop
[1][target_big_endian
];
19101 noop
= wide_thumb_noop
[target_big_endian
];
19104 noop
= thumb_noop
[0][target_big_endian
];
19112 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19113 [target_big_endian
];
19120 fragP
->fr_var
= noop_size
;
19122 if (bytes
& (noop_size
- 1))
19124 fix
= bytes
& (noop_size
- 1);
19126 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19128 memset (p
, 0, fix
);
19135 if (bytes
& noop_size
)
19137 /* Insert a narrow noop. */
19138 memcpy (p
, narrow_noop
, noop_size
);
19140 bytes
-= noop_size
;
19144 /* Use wide noops for the remainder */
19148 while (bytes
>= noop_size
)
19150 memcpy (p
, noop
, noop_size
);
19152 bytes
-= noop_size
;
19156 fragP
->fr_fix
+= fix
;
19159 /* Called from md_do_align. Used to create an alignment
19160 frag in a code section. */
19163 arm_frag_align_code (int n
, int max
)
19167 /* We assume that there will never be a requirement
19168 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19169 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19174 _("alignments greater than %d bytes not supported in .text sections."),
19175 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19176 as_fatal ("%s", err_msg
);
19179 p
= frag_var (rs_align_code
,
19180 MAX_MEM_FOR_RS_ALIGN_CODE
,
19182 (relax_substateT
) max
,
19189 /* Perform target specific initialisation of a frag.
19190 Note - despite the name this initialisation is not done when the frag
19191 is created, but only when its type is assigned. A frag can be created
19192 and used a long time before its type is set, so beware of assuming that
19193 this initialisationis performed first. */
19197 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19199 /* Record whether this frag is in an ARM or a THUMB area. */
19200 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19203 #else /* OBJ_ELF is defined. */
19205 arm_init_frag (fragS
* fragP
, int max_chars
)
19207 /* If the current ARM vs THUMB mode has not already
19208 been recorded into this frag then do so now. */
19209 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19211 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19213 /* Record a mapping symbol for alignment frags. We will delete this
19214 later if the alignment ends up empty. */
19215 switch (fragP
->fr_type
)
19218 case rs_align_test
:
19220 mapping_state_2 (MAP_DATA
, max_chars
);
19222 case rs_align_code
:
19223 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19231 /* When we change sections we need to issue a new mapping symbol. */
19234 arm_elf_change_section (void)
19236 /* Link an unlinked unwind index table section to the .text section. */
19237 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19238 && elf_linked_to_section (now_seg
) == NULL
)
19239 elf_linked_to_section (now_seg
) = text_section
;
19243 arm_elf_section_type (const char * str
, size_t len
)
19245 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19246 return SHT_ARM_EXIDX
;
19251 /* Code to deal with unwinding tables. */
19253 static void add_unwind_adjustsp (offsetT
);
19255 /* Generate any deferred unwind frame offset. */
19258 flush_pending_unwind (void)
19262 offset
= unwind
.pending_offset
;
19263 unwind
.pending_offset
= 0;
19265 add_unwind_adjustsp (offset
);
19268 /* Add an opcode to this list for this function. Two-byte opcodes should
19269 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19273 add_unwind_opcode (valueT op
, int length
)
19275 /* Add any deferred stack adjustment. */
19276 if (unwind
.pending_offset
)
19277 flush_pending_unwind ();
19279 unwind
.sp_restored
= 0;
19281 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19283 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19284 if (unwind
.opcodes
)
19285 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19286 unwind
.opcode_alloc
);
19288 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19293 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19295 unwind
.opcode_count
++;
19299 /* Add unwind opcodes to adjust the stack pointer. */
19302 add_unwind_adjustsp (offsetT offset
)
19306 if (offset
> 0x200)
19308 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19313 /* Long form: 0xb2, uleb128. */
19314 /* This might not fit in a word so add the individual bytes,
19315 remembering the list is built in reverse order. */
19316 o
= (valueT
) ((offset
- 0x204) >> 2);
19318 add_unwind_opcode (0, 1);
19320 /* Calculate the uleb128 encoding of the offset. */
19324 bytes
[n
] = o
& 0x7f;
19330 /* Add the insn. */
19332 add_unwind_opcode (bytes
[n
- 1], 1);
19333 add_unwind_opcode (0xb2, 1);
19335 else if (offset
> 0x100)
19337 /* Two short opcodes. */
19338 add_unwind_opcode (0x3f, 1);
19339 op
= (offset
- 0x104) >> 2;
19340 add_unwind_opcode (op
, 1);
19342 else if (offset
> 0)
19344 /* Short opcode. */
19345 op
= (offset
- 4) >> 2;
19346 add_unwind_opcode (op
, 1);
19348 else if (offset
< 0)
19351 while (offset
> 0x100)
19353 add_unwind_opcode (0x7f, 1);
19356 op
= ((offset
- 4) >> 2) | 0x40;
19357 add_unwind_opcode (op
, 1);
19361 /* Finish the list of unwind opcodes for this function. */
19363 finish_unwind_opcodes (void)
19367 if (unwind
.fp_used
)
19369 /* Adjust sp as necessary. */
19370 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19371 flush_pending_unwind ();
19373 /* After restoring sp from the frame pointer. */
19374 op
= 0x90 | unwind
.fp_reg
;
19375 add_unwind_opcode (op
, 1);
19378 flush_pending_unwind ();
19382 /* Start an exception table entry. If idx is nonzero this is an index table
19386 start_unwind_section (const segT text_seg
, int idx
)
19388 const char * text_name
;
19389 const char * prefix
;
19390 const char * prefix_once
;
19391 const char * group_name
;
19395 size_t sec_name_len
;
19402 prefix
= ELF_STRING_ARM_unwind
;
19403 prefix_once
= ELF_STRING_ARM_unwind_once
;
19404 type
= SHT_ARM_EXIDX
;
19408 prefix
= ELF_STRING_ARM_unwind_info
;
19409 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19410 type
= SHT_PROGBITS
;
19413 text_name
= segment_name (text_seg
);
19414 if (streq (text_name
, ".text"))
19417 if (strncmp (text_name
, ".gnu.linkonce.t.",
19418 strlen (".gnu.linkonce.t.")) == 0)
19420 prefix
= prefix_once
;
19421 text_name
+= strlen (".gnu.linkonce.t.");
19424 prefix_len
= strlen (prefix
);
19425 text_len
= strlen (text_name
);
19426 sec_name_len
= prefix_len
+ text_len
;
19427 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19428 memcpy (sec_name
, prefix
, prefix_len
);
19429 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19430 sec_name
[prefix_len
+ text_len
] = '\0';
19436 /* Handle COMDAT group. */
19437 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19439 group_name
= elf_group_name (text_seg
);
19440 if (group_name
== NULL
)
19442 as_bad (_("Group section `%s' has no group signature"),
19443 segment_name (text_seg
));
19444 ignore_rest_of_line ();
19447 flags
|= SHF_GROUP
;
19451 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19453 /* Set the section link for index tables. */
19455 elf_linked_to_section (now_seg
) = text_seg
;
19459 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19460 personality routine data. Returns zero, or the index table value for
19461 and inline entry. */
19464 create_unwind_entry (int have_data
)
19469 /* The current word of data. */
19471 /* The number of bytes left in this word. */
19474 finish_unwind_opcodes ();
19476 /* Remember the current text section. */
19477 unwind
.saved_seg
= now_seg
;
19478 unwind
.saved_subseg
= now_subseg
;
19480 start_unwind_section (now_seg
, 0);
19482 if (unwind
.personality_routine
== NULL
)
19484 if (unwind
.personality_index
== -2)
19487 as_bad (_("handlerdata in cantunwind frame"));
19488 return 1; /* EXIDX_CANTUNWIND. */
19491 /* Use a default personality routine if none is specified. */
19492 if (unwind
.personality_index
== -1)
19494 if (unwind
.opcode_count
> 3)
19495 unwind
.personality_index
= 1;
19497 unwind
.personality_index
= 0;
19500 /* Space for the personality routine entry. */
19501 if (unwind
.personality_index
== 0)
19503 if (unwind
.opcode_count
> 3)
19504 as_bad (_("too many unwind opcodes for personality routine 0"));
19508 /* All the data is inline in the index table. */
19511 while (unwind
.opcode_count
> 0)
19513 unwind
.opcode_count
--;
19514 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19518 /* Pad with "finish" opcodes. */
19520 data
= (data
<< 8) | 0xb0;
19527 /* We get two opcodes "free" in the first word. */
19528 size
= unwind
.opcode_count
- 2;
19531 /* An extra byte is required for the opcode count. */
19532 size
= unwind
.opcode_count
+ 1;
19534 size
= (size
+ 3) >> 2;
19536 as_bad (_("too many unwind opcodes"));
19538 frag_align (2, 0, 0);
19539 record_alignment (now_seg
, 2);
19540 unwind
.table_entry
= expr_build_dot ();
19542 /* Allocate the table entry. */
19543 ptr
= frag_more ((size
<< 2) + 4);
19544 where
= frag_now_fix () - ((size
<< 2) + 4);
19546 switch (unwind
.personality_index
)
19549 /* ??? Should this be a PLT generating relocation? */
19550 /* Custom personality routine. */
19551 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19552 BFD_RELOC_ARM_PREL31
);
19557 /* Set the first byte to the number of additional words. */
19562 /* ABI defined personality routines. */
19564 /* Three opcodes bytes are packed into the first word. */
19571 /* The size and first two opcode bytes go in the first word. */
19572 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19577 /* Should never happen. */
19581 /* Pack the opcodes into words (MSB first), reversing the list at the same
19583 while (unwind
.opcode_count
> 0)
19587 md_number_to_chars (ptr
, data
, 4);
19592 unwind
.opcode_count
--;
19594 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19597 /* Finish off the last word. */
19600 /* Pad with "finish" opcodes. */
19602 data
= (data
<< 8) | 0xb0;
19604 md_number_to_chars (ptr
, data
, 4);
19609 /* Add an empty descriptor if there is no user-specified data. */
19610 ptr
= frag_more (4);
19611 md_number_to_chars (ptr
, 0, 4);
19618 /* Initialize the DWARF-2 unwind information for this procedure. */
19621 tc_arm_frame_initial_instructions (void)
19623 cfi_add_CFA_def_cfa (REG_SP
, 0);
19625 #endif /* OBJ_ELF */
19627 /* Convert REGNAME to a DWARF-2 register number. */
19630 tc_arm_regname_to_dw2regnum (char *regname
)
19632 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19642 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19646 exp
.X_op
= O_secrel
;
19647 exp
.X_add_symbol
= symbol
;
19648 exp
.X_add_number
= 0;
19649 emit_expr (&exp
, size
);
19653 /* MD interface: Symbol and relocation handling. */
19655 /* Return the address within the segment that a PC-relative fixup is
19656 relative to. For ARM, PC-relative fixups applied to instructions
19657 are generally relative to the location of the fixup plus 8 bytes.
19658 Thumb branches are offset by 4, and Thumb loads relative to PC
19659 require special handling. */
19662 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19664 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19666 /* If this is pc-relative and we are going to emit a relocation
19667 then we just want to put out any pipeline compensation that the linker
19668 will need. Otherwise we want to use the calculated base.
19669 For WinCE we skip the bias for externals as well, since this
19670 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19672 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19673 || (arm_force_relocation (fixP
)
19675 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19681 switch (fixP
->fx_r_type
)
19683 /* PC relative addressing on the Thumb is slightly odd as the
19684 bottom two bits of the PC are forced to zero for the
19685 calculation. This happens *after* application of the
19686 pipeline offset. However, Thumb adrl already adjusts for
19687 this, so we need not do it again. */
19688 case BFD_RELOC_ARM_THUMB_ADD
:
19691 case BFD_RELOC_ARM_THUMB_OFFSET
:
19692 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19693 case BFD_RELOC_ARM_T32_ADD_PC12
:
19694 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19695 return (base
+ 4) & ~3;
19697 /* Thumb branches are simply offset by +4. */
19698 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19699 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19700 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19701 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19702 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19705 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19707 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19708 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19709 && ARM_IS_FUNC (fixP
->fx_addsy
)
19710 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19711 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19714 /* BLX is like branches above, but forces the low two bits of PC to
19716 case BFD_RELOC_THUMB_PCREL_BLX
:
19718 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19719 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19720 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19721 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19722 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19723 return (base
+ 4) & ~3;
19725 /* ARM mode branches are offset by +8. However, the Windows CE
19726 loader expects the relocation not to take this into account. */
19727 case BFD_RELOC_ARM_PCREL_BLX
:
19729 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19730 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19731 && ARM_IS_FUNC (fixP
->fx_addsy
)
19732 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19733 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19736 case BFD_RELOC_ARM_PCREL_CALL
:
19738 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19739 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19740 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19741 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19742 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19745 case BFD_RELOC_ARM_PCREL_BRANCH
:
19746 case BFD_RELOC_ARM_PCREL_JUMP
:
19747 case BFD_RELOC_ARM_PLT32
:
19749 /* When handling fixups immediately, because we have already
19750 discovered the value of a symbol, or the address of the frag involved
19751 we must account for the offset by +8, as the OS loader will never see the reloc.
19752 see fixup_segment() in write.c
19753 The S_IS_EXTERNAL test handles the case of global symbols.
19754 Those need the calculated base, not just the pipe compensation the linker will need. */
19756 && fixP
->fx_addsy
!= NULL
19757 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19758 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19766 /* ARM mode loads relative to PC are also offset by +8. Unlike
19767 branches, the Windows CE loader *does* expect the relocation
19768 to take this into account. */
19769 case BFD_RELOC_ARM_OFFSET_IMM
:
19770 case BFD_RELOC_ARM_OFFSET_IMM8
:
19771 case BFD_RELOC_ARM_HWLITERAL
:
19772 case BFD_RELOC_ARM_LITERAL
:
19773 case BFD_RELOC_ARM_CP_OFF_IMM
:
19777 /* Other PC-relative relocations are un-offset. */
19783 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19784 Otherwise we have no need to default values of symbols. */
19787 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19790 if (name
[0] == '_' && name
[1] == 'G'
19791 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19795 if (symbol_find (name
))
19796 as_bad (_("GOT already in the symbol table"));
19798 GOT_symbol
= symbol_new (name
, undefined_section
,
19799 (valueT
) 0, & zero_address_frag
);
19809 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19810 computed as two separate immediate values, added together. We
19811 already know that this value cannot be computed by just one ARM
19814 static unsigned int
19815 validate_immediate_twopart (unsigned int val
,
19816 unsigned int * highpart
)
19821 for (i
= 0; i
< 32; i
+= 2)
19822 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19828 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19830 else if (a
& 0xff0000)
19832 if (a
& 0xff000000)
19834 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19838 gas_assert (a
& 0xff000000);
19839 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19842 return (a
& 0xff) | (i
<< 7);
19849 validate_offset_imm (unsigned int val
, int hwse
)
19851 if ((hwse
&& val
> 255) || val
> 4095)
19856 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19857 negative immediate constant by altering the instruction. A bit of
19862 by inverting the second operand, and
19865 by negating the second operand. */
19868 negate_data_op (unsigned long * instruction
,
19869 unsigned long value
)
19872 unsigned long negated
, inverted
;
19874 negated
= encode_arm_immediate (-value
);
19875 inverted
= encode_arm_immediate (~value
);
19877 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19880 /* First negates. */
19881 case OPCODE_SUB
: /* ADD <-> SUB */
19882 new_inst
= OPCODE_ADD
;
19887 new_inst
= OPCODE_SUB
;
19891 case OPCODE_CMP
: /* CMP <-> CMN */
19892 new_inst
= OPCODE_CMN
;
19897 new_inst
= OPCODE_CMP
;
19901 /* Now Inverted ops. */
19902 case OPCODE_MOV
: /* MOV <-> MVN */
19903 new_inst
= OPCODE_MVN
;
19908 new_inst
= OPCODE_MOV
;
19912 case OPCODE_AND
: /* AND <-> BIC */
19913 new_inst
= OPCODE_BIC
;
19918 new_inst
= OPCODE_AND
;
19922 case OPCODE_ADC
: /* ADC <-> SBC */
19923 new_inst
= OPCODE_SBC
;
19928 new_inst
= OPCODE_ADC
;
19932 /* We cannot do anything. */
19937 if (value
== (unsigned) FAIL
)
19940 *instruction
&= OPCODE_MASK
;
19941 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19945 /* Like negate_data_op, but for Thumb-2. */
19947 static unsigned int
19948 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19952 unsigned int negated
, inverted
;
19954 negated
= encode_thumb32_immediate (-value
);
19955 inverted
= encode_thumb32_immediate (~value
);
19957 rd
= (*instruction
>> 8) & 0xf;
19958 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19961 /* ADD <-> SUB. Includes CMP <-> CMN. */
19962 case T2_OPCODE_SUB
:
19963 new_inst
= T2_OPCODE_ADD
;
19967 case T2_OPCODE_ADD
:
19968 new_inst
= T2_OPCODE_SUB
;
19972 /* ORR <-> ORN. Includes MOV <-> MVN. */
19973 case T2_OPCODE_ORR
:
19974 new_inst
= T2_OPCODE_ORN
;
19978 case T2_OPCODE_ORN
:
19979 new_inst
= T2_OPCODE_ORR
;
19983 /* AND <-> BIC. TST has no inverted equivalent. */
19984 case T2_OPCODE_AND
:
19985 new_inst
= T2_OPCODE_BIC
;
19992 case T2_OPCODE_BIC
:
19993 new_inst
= T2_OPCODE_AND
;
19998 case T2_OPCODE_ADC
:
19999 new_inst
= T2_OPCODE_SBC
;
20003 case T2_OPCODE_SBC
:
20004 new_inst
= T2_OPCODE_ADC
;
20008 /* We cannot do anything. */
20013 if (value
== (unsigned int)FAIL
)
20016 *instruction
&= T2_OPCODE_MASK
;
20017 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20021 /* Read a 32-bit thumb instruction from buf. */
20022 static unsigned long
20023 get_thumb32_insn (char * buf
)
20025 unsigned long insn
;
20026 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20027 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20033 /* We usually want to set the low bit on the address of thumb function
20034 symbols. In particular .word foo - . should have the low bit set.
20035 Generic code tries to fold the difference of two symbols to
20036 a constant. Prevent this and force a relocation when the first symbols
20037 is a thumb function. */
20040 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20042 if (op
== O_subtract
20043 && l
->X_op
== O_symbol
20044 && r
->X_op
== O_symbol
20045 && THUMB_IS_FUNC (l
->X_add_symbol
))
20047 l
->X_op
= O_subtract
;
20048 l
->X_op_symbol
= r
->X_add_symbol
;
20049 l
->X_add_number
-= r
->X_add_number
;
20053 /* Process as normal. */
20057 /* Encode Thumb2 unconditional branches and calls. The encoding
20058 for the 2 are identical for the immediate values. */
20061 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20063 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20066 addressT S
, I1
, I2
, lo
, hi
;
20068 S
= (value
>> 24) & 0x01;
20069 I1
= (value
>> 23) & 0x01;
20070 I2
= (value
>> 22) & 0x01;
20071 hi
= (value
>> 12) & 0x3ff;
20072 lo
= (value
>> 1) & 0x7ff;
20073 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20074 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20075 newval
|= (S
<< 10) | hi
;
20076 newval2
&= ~T2I1I2MASK
;
20077 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20078 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20079 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20083 md_apply_fix (fixS
* fixP
,
20087 offsetT value
= * valP
;
20089 unsigned int newimm
;
20090 unsigned long temp
;
20092 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20094 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20096 /* Note whether this will delete the relocation. */
20098 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20101 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20102 consistency with the behaviour on 32-bit hosts. Remember value
20104 value
&= 0xffffffff;
20105 value
^= 0x80000000;
20106 value
-= 0x80000000;
20109 fixP
->fx_addnumber
= value
;
20111 /* Same treatment for fixP->fx_offset. */
20112 fixP
->fx_offset
&= 0xffffffff;
20113 fixP
->fx_offset
^= 0x80000000;
20114 fixP
->fx_offset
-= 0x80000000;
20116 switch (fixP
->fx_r_type
)
20118 case BFD_RELOC_NONE
:
20119 /* This will need to go in the object file. */
20123 case BFD_RELOC_ARM_IMMEDIATE
:
20124 /* We claim that this fixup has been processed here,
20125 even if in fact we generate an error because we do
20126 not have a reloc for it, so tc_gen_reloc will reject it. */
20129 if (fixP
->fx_addsy
)
20131 const char *msg
= 0;
20133 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20134 msg
= _("undefined symbol %s used as an immediate value");
20135 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20136 msg
= _("symbol %s is in a different section");
20137 else if (S_IS_WEAK (fixP
->fx_addsy
))
20138 msg
= _("symbol %s is weak and may be overridden later");
20142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20143 msg
, S_GET_NAME (fixP
->fx_addsy
));
20148 newimm
= encode_arm_immediate (value
);
20149 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20151 /* If the instruction will fail, see if we can fix things up by
20152 changing the opcode. */
20153 if (newimm
== (unsigned int) FAIL
20154 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20156 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20157 _("invalid constant (%lx) after fixup"),
20158 (unsigned long) value
);
20162 newimm
|= (temp
& 0xfffff000);
20163 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20166 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20168 unsigned int highpart
= 0;
20169 unsigned int newinsn
= 0xe1a00000; /* nop. */
20171 if (fixP
->fx_addsy
)
20173 const char *msg
= 0;
20175 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20176 msg
= _("undefined symbol %s used as an immediate value");
20177 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20178 msg
= _("symbol %s is in a different section");
20179 else if (S_IS_WEAK (fixP
->fx_addsy
))
20180 msg
= _("symbol %s is weak and may be overridden later");
20184 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20185 msg
, S_GET_NAME (fixP
->fx_addsy
));
20190 newimm
= encode_arm_immediate (value
);
20191 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20193 /* If the instruction will fail, see if we can fix things up by
20194 changing the opcode. */
20195 if (newimm
== (unsigned int) FAIL
20196 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20198 /* No ? OK - try using two ADD instructions to generate
20200 newimm
= validate_immediate_twopart (value
, & highpart
);
20202 /* Yes - then make sure that the second instruction is
20204 if (newimm
!= (unsigned int) FAIL
)
20206 /* Still No ? Try using a negated value. */
20207 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20208 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20209 /* Otherwise - give up. */
20212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20213 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20218 /* Replace the first operand in the 2nd instruction (which
20219 is the PC) with the destination register. We have
20220 already added in the PC in the first instruction and we
20221 do not want to do it again. */
20222 newinsn
&= ~ 0xf0000;
20223 newinsn
|= ((newinsn
& 0x0f000) << 4);
20226 newimm
|= (temp
& 0xfffff000);
20227 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20229 highpart
|= (newinsn
& 0xfffff000);
20230 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20234 case BFD_RELOC_ARM_OFFSET_IMM
:
20235 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20238 case BFD_RELOC_ARM_LITERAL
:
20244 if (validate_offset_imm (value
, 0) == FAIL
)
20246 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20248 _("invalid literal constant: pool needs to be closer"));
20250 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20251 _("bad immediate value for offset (%ld)"),
20256 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20257 newval
&= 0xff7ff000;
20258 newval
|= value
| (sign
? INDEX_UP
: 0);
20259 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20262 case BFD_RELOC_ARM_OFFSET_IMM8
:
20263 case BFD_RELOC_ARM_HWLITERAL
:
20269 if (validate_offset_imm (value
, 1) == FAIL
)
20271 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20273 _("invalid literal constant: pool needs to be closer"));
20275 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20280 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20281 newval
&= 0xff7ff0f0;
20282 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20283 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20286 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20287 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20289 _("bad immediate value for offset (%ld)"), (long) value
);
20292 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20294 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20297 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20298 /* This is a complicated relocation used for all varieties of Thumb32
20299 load/store instruction with immediate offset:
20301 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20302 *4, optional writeback(W)
20303 (doubleword load/store)
20305 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20306 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20307 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20308 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20309 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20311 Uppercase letters indicate bits that are already encoded at
20312 this point. Lowercase letters are our problem. For the
20313 second block of instructions, the secondary opcode nybble
20314 (bits 8..11) is present, and bit 23 is zero, even if this is
20315 a PC-relative operation. */
20316 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20318 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20320 if ((newval
& 0xf0000000) == 0xe0000000)
20322 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20324 newval
|= (1 << 23);
20327 if (value
% 4 != 0)
20329 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20330 _("offset not a multiple of 4"));
20336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20337 _("offset out of range"));
20342 else if ((newval
& 0x000f0000) == 0x000f0000)
20344 /* PC-relative, 12-bit offset. */
20346 newval
|= (1 << 23);
20351 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20352 _("offset out of range"));
20357 else if ((newval
& 0x00000100) == 0x00000100)
20359 /* Writeback: 8-bit, +/- offset. */
20361 newval
|= (1 << 9);
20366 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20367 _("offset out of range"));
20372 else if ((newval
& 0x00000f00) == 0x00000e00)
20374 /* T-instruction: positive 8-bit offset. */
20375 if (value
< 0 || value
> 0xff)
20377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20378 _("offset out of range"));
20386 /* Positive 12-bit or negative 8-bit offset. */
20390 newval
|= (1 << 23);
20400 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20401 _("offset out of range"));
20408 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20409 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20412 case BFD_RELOC_ARM_SHIFT_IMM
:
20413 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20414 if (((unsigned long) value
) > 32
20416 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20419 _("shift expression is too large"));
20424 /* Shifts of zero must be done as lsl. */
20426 else if (value
== 32)
20428 newval
&= 0xfffff07f;
20429 newval
|= (value
& 0x1f) << 7;
20430 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20433 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20434 case BFD_RELOC_ARM_T32_ADD_IMM
:
20435 case BFD_RELOC_ARM_T32_IMM12
:
20436 case BFD_RELOC_ARM_T32_ADD_PC12
:
20437 /* We claim that this fixup has been processed here,
20438 even if in fact we generate an error because we do
20439 not have a reloc for it, so tc_gen_reloc will reject it. */
20443 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20445 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20446 _("undefined symbol %s used as an immediate value"),
20447 S_GET_NAME (fixP
->fx_addsy
));
20451 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20453 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20456 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20457 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20459 newimm
= encode_thumb32_immediate (value
);
20460 if (newimm
== (unsigned int) FAIL
)
20461 newimm
= thumb32_negate_data_op (&newval
, value
);
20463 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20464 && newimm
== (unsigned int) FAIL
)
20466 /* Turn add/sum into addw/subw. */
20467 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20468 newval
= (newval
& 0xfeffffff) | 0x02000000;
20469 /* No flat 12-bit imm encoding for addsw/subsw. */
20470 if ((newval
& 0x00100000) == 0)
20472 /* 12 bit immediate for addw/subw. */
20476 newval
^= 0x00a00000;
20479 newimm
= (unsigned int) FAIL
;
20485 if (newimm
== (unsigned int)FAIL
)
20487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20488 _("invalid constant (%lx) after fixup"),
20489 (unsigned long) value
);
20493 newval
|= (newimm
& 0x800) << 15;
20494 newval
|= (newimm
& 0x700) << 4;
20495 newval
|= (newimm
& 0x0ff);
20497 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20498 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20501 case BFD_RELOC_ARM_SMC
:
20502 if (((unsigned long) value
) > 0xffff)
20503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20504 _("invalid smc expression"));
20505 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20506 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20507 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20510 case BFD_RELOC_ARM_HVC
:
20511 if (((unsigned long) value
) > 0xffff)
20512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20513 _("invalid hvc expression"));
20514 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20515 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20516 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20519 case BFD_RELOC_ARM_SWI
:
20520 if (fixP
->tc_fix_data
!= 0)
20522 if (((unsigned long) value
) > 0xff)
20523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20524 _("invalid swi expression"));
20525 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20527 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20531 if (((unsigned long) value
) > 0x00ffffff)
20532 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20533 _("invalid swi expression"));
20534 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20536 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20540 case BFD_RELOC_ARM_MULTI
:
20541 if (((unsigned long) value
) > 0xffff)
20542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20543 _("invalid expression in load/store multiple"));
20544 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20545 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20549 case BFD_RELOC_ARM_PCREL_CALL
:
20551 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20553 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20554 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20555 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20556 /* Flip the bl to blx. This is a simple flip
20557 bit here because we generate PCREL_CALL for
20558 unconditional bls. */
20560 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20561 newval
= newval
| 0x10000000;
20562 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20568 goto arm_branch_common
;
20570 case BFD_RELOC_ARM_PCREL_JUMP
:
20571 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20573 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20574 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20575 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20577 /* This would map to a bl<cond>, b<cond>,
20578 b<always> to a Thumb function. We
20579 need to force a relocation for this particular
20581 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20585 case BFD_RELOC_ARM_PLT32
:
20587 case BFD_RELOC_ARM_PCREL_BRANCH
:
20589 goto arm_branch_common
;
20591 case BFD_RELOC_ARM_PCREL_BLX
:
20594 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20596 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20597 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20598 && ARM_IS_FUNC (fixP
->fx_addsy
))
20600 /* Flip the blx to a bl and warn. */
20601 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20602 newval
= 0xeb000000;
20603 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20604 _("blx to '%s' an ARM ISA state function changed to bl"),
20606 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20612 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20613 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20617 /* We are going to store value (shifted right by two) in the
20618 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20619 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20620 also be be clear. */
20622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20623 _("misaligned branch destination"));
20624 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20625 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20626 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20627 _("branch out of range"));
20629 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20631 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20632 newval
|= (value
>> 2) & 0x00ffffff;
20633 /* Set the H bit on BLX instructions. */
20637 newval
|= 0x01000000;
20639 newval
&= ~0x01000000;
20641 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20645 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20646 /* CBZ can only branch forward. */
20648 /* Attempts to use CBZ to branch to the next instruction
20649 (which, strictly speaking, are prohibited) will be turned into
20652 FIXME: It may be better to remove the instruction completely and
20653 perform relaxation. */
20656 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20657 newval
= 0xbf00; /* NOP encoding T1 */
20658 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20663 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20664 _("branch out of range"));
20666 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20668 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20669 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20670 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20675 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20676 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20677 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20678 _("branch out of range"));
20680 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20682 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20683 newval
|= (value
& 0x1ff) >> 1;
20684 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20688 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20689 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20691 _("branch out of range"));
20693 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20695 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20696 newval
|= (value
& 0xfff) >> 1;
20697 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20701 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20703 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20704 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20705 && S_IS_DEFINED (fixP
->fx_addsy
)
20706 && ARM_IS_FUNC (fixP
->fx_addsy
)
20707 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20709 /* Force a relocation for a branch 20 bits wide. */
20712 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20714 _("conditional branch out of range"));
20716 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20719 addressT S
, J1
, J2
, lo
, hi
;
20721 S
= (value
& 0x00100000) >> 20;
20722 J2
= (value
& 0x00080000) >> 19;
20723 J1
= (value
& 0x00040000) >> 18;
20724 hi
= (value
& 0x0003f000) >> 12;
20725 lo
= (value
& 0x00000ffe) >> 1;
20727 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20728 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20729 newval
|= (S
<< 10) | hi
;
20730 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20731 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20732 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20736 case BFD_RELOC_THUMB_PCREL_BLX
:
20738 /* If there is a blx from a thumb state function to
20739 another thumb function flip this to a bl and warn
20743 && S_IS_DEFINED (fixP
->fx_addsy
)
20744 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20745 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20746 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20748 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20749 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20750 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20752 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20753 newval
= newval
| 0x1000;
20754 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20755 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20760 goto thumb_bl_common
;
20762 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20764 /* A bl from Thumb state ISA to an internal ARM state function
20765 is converted to a blx. */
20767 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20768 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20769 && S_IS_DEFINED (fixP
->fx_addsy
)
20770 && ARM_IS_FUNC (fixP
->fx_addsy
)
20771 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20773 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20774 newval
= newval
& ~0x1000;
20775 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20776 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20783 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20784 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20785 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20788 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20789 /* For a BLX instruction, make sure that the relocation is rounded up
20790 to a word boundary. This follows the semantics of the instruction
20791 which specifies that bit 1 of the target address will come from bit
20792 1 of the base address. */
20793 value
= (value
+ 1) & ~ 1;
20796 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20798 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20801 _("branch out of range"));
20803 else if ((value
& ~0x1ffffff)
20804 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20807 _("Thumb2 branch out of range"));
20811 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20812 encode_thumb2_b_bl_offset (buf
, value
);
20816 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20817 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20818 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20819 _("branch out of range"));
20821 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20822 encode_thumb2_b_bl_offset (buf
, value
);
20827 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20828 md_number_to_chars (buf
, value
, 1);
20832 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20833 md_number_to_chars (buf
, value
, 2);
20837 case BFD_RELOC_ARM_TLS_GD32
:
20838 case BFD_RELOC_ARM_TLS_LE32
:
20839 case BFD_RELOC_ARM_TLS_IE32
:
20840 case BFD_RELOC_ARM_TLS_LDM32
:
20841 case BFD_RELOC_ARM_TLS_LDO32
:
20842 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20845 case BFD_RELOC_ARM_GOT32
:
20846 case BFD_RELOC_ARM_GOTOFF
:
20847 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20848 md_number_to_chars (buf
, 0, 4);
20851 case BFD_RELOC_ARM_GOT_PREL
:
20852 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20853 md_number_to_chars (buf
, value
, 4);
20856 case BFD_RELOC_ARM_TARGET2
:
20857 /* TARGET2 is not partial-inplace, so we need to write the
20858 addend here for REL targets, because it won't be written out
20859 during reloc processing later. */
20860 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20861 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20865 case BFD_RELOC_RVA
:
20867 case BFD_RELOC_ARM_TARGET1
:
20868 case BFD_RELOC_ARM_ROSEGREL32
:
20869 case BFD_RELOC_ARM_SBREL32
:
20870 case BFD_RELOC_32_PCREL
:
20872 case BFD_RELOC_32_SECREL
:
20874 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20876 /* For WinCE we only do this for pcrel fixups. */
20877 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20879 md_number_to_chars (buf
, value
, 4);
20883 case BFD_RELOC_ARM_PREL31
:
20884 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20886 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20887 if ((value
^ (value
>> 1)) & 0x40000000)
20889 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20890 _("rel31 relocation overflow"));
20892 newval
|= value
& 0x7fffffff;
20893 md_number_to_chars (buf
, newval
, 4);
20898 case BFD_RELOC_ARM_CP_OFF_IMM
:
20899 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20900 if (value
< -1023 || value
> 1023 || (value
& 3))
20901 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20902 _("co-processor offset out of range"));
20907 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20908 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20909 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20911 newval
= get_thumb32_insn (buf
);
20912 newval
&= 0xff7fff00;
20913 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20914 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20915 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20916 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20918 put_thumb32_insn (buf
, newval
);
20921 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20922 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20923 if (value
< -255 || value
> 255)
20924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20925 _("co-processor offset out of range"));
20927 goto cp_off_common
;
20929 case BFD_RELOC_ARM_THUMB_OFFSET
:
20930 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20931 /* Exactly what ranges, and where the offset is inserted depends
20932 on the type of instruction, we can establish this from the
20934 switch (newval
>> 12)
20936 case 4: /* PC load. */
20937 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20938 forced to zero for these loads; md_pcrel_from has already
20939 compensated for this. */
20941 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20942 _("invalid offset, target not word aligned (0x%08lX)"),
20943 (((unsigned long) fixP
->fx_frag
->fr_address
20944 + (unsigned long) fixP
->fx_where
) & ~3)
20945 + (unsigned long) value
);
20947 if (value
& ~0x3fc)
20948 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20949 _("invalid offset, value too big (0x%08lX)"),
20952 newval
|= value
>> 2;
20955 case 9: /* SP load/store. */
20956 if (value
& ~0x3fc)
20957 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20958 _("invalid offset, value too big (0x%08lX)"),
20960 newval
|= value
>> 2;
20963 case 6: /* Word load/store. */
20965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20966 _("invalid offset, value too big (0x%08lX)"),
20968 newval
|= value
<< 4; /* 6 - 2. */
20971 case 7: /* Byte load/store. */
20973 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20974 _("invalid offset, value too big (0x%08lX)"),
20976 newval
|= value
<< 6;
20979 case 8: /* Halfword load/store. */
20981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20982 _("invalid offset, value too big (0x%08lX)"),
20984 newval
|= value
<< 5; /* 6 - 1. */
20988 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20989 "Unable to process relocation for thumb opcode: %lx",
20990 (unsigned long) newval
);
20993 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20996 case BFD_RELOC_ARM_THUMB_ADD
:
20997 /* This is a complicated relocation, since we use it for all of
20998 the following immediate relocations:
21002 9bit ADD/SUB SP word-aligned
21003 10bit ADD PC/SP word-aligned
21005 The type of instruction being processed is encoded in the
21012 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21014 int rd
= (newval
>> 4) & 0xf;
21015 int rs
= newval
& 0xf;
21016 int subtract
= !!(newval
& 0x8000);
21018 /* Check for HI regs, only very restricted cases allowed:
21019 Adjusting SP, and using PC or SP to get an address. */
21020 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21021 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21022 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21023 _("invalid Hi register with immediate"));
21025 /* If value is negative, choose the opposite instruction. */
21029 subtract
= !subtract
;
21031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21032 _("immediate value out of range"));
21037 if (value
& ~0x1fc)
21038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21039 _("invalid immediate for stack address calculation"));
21040 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21041 newval
|= value
>> 2;
21043 else if (rs
== REG_PC
|| rs
== REG_SP
)
21045 if (subtract
|| value
& ~0x3fc)
21046 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21047 _("invalid immediate for address calculation (value = 0x%08lX)"),
21048 (unsigned long) value
);
21049 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21051 newval
|= value
>> 2;
21056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21057 _("immediate value out of range"));
21058 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21059 newval
|= (rd
<< 8) | value
;
21064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21065 _("immediate value out of range"));
21066 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21067 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21070 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21073 case BFD_RELOC_ARM_THUMB_IMM
:
21074 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21075 if (value
< 0 || value
> 255)
21076 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21077 _("invalid immediate: %ld is out of range"),
21080 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21083 case BFD_RELOC_ARM_THUMB_SHIFT
:
21084 /* 5bit shift value (0..32). LSL cannot take 32. */
21085 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21086 temp
= newval
& 0xf800;
21087 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21088 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21089 _("invalid shift value: %ld"), (long) value
);
21090 /* Shifts of zero must be encoded as LSL. */
21092 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21093 /* Shifts of 32 are encoded as zero. */
21094 else if (value
== 32)
21096 newval
|= value
<< 6;
21097 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21100 case BFD_RELOC_VTABLE_INHERIT
:
21101 case BFD_RELOC_VTABLE_ENTRY
:
21105 case BFD_RELOC_ARM_MOVW
:
21106 case BFD_RELOC_ARM_MOVT
:
21107 case BFD_RELOC_ARM_THUMB_MOVW
:
21108 case BFD_RELOC_ARM_THUMB_MOVT
:
21109 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21111 /* REL format relocations are limited to a 16-bit addend. */
21112 if (!fixP
->fx_done
)
21114 if (value
< -0x8000 || value
> 0x7fff)
21115 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21116 _("offset out of range"));
21118 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21119 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21124 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21125 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21127 newval
= get_thumb32_insn (buf
);
21128 newval
&= 0xfbf08f00;
21129 newval
|= (value
& 0xf000) << 4;
21130 newval
|= (value
& 0x0800) << 15;
21131 newval
|= (value
& 0x0700) << 4;
21132 newval
|= (value
& 0x00ff);
21133 put_thumb32_insn (buf
, newval
);
21137 newval
= md_chars_to_number (buf
, 4);
21138 newval
&= 0xfff0f000;
21139 newval
|= value
& 0x0fff;
21140 newval
|= (value
& 0xf000) << 4;
21141 md_number_to_chars (buf
, newval
, 4);
21146 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21147 case BFD_RELOC_ARM_ALU_PC_G0
:
21148 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21149 case BFD_RELOC_ARM_ALU_PC_G1
:
21150 case BFD_RELOC_ARM_ALU_PC_G2
:
21151 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21152 case BFD_RELOC_ARM_ALU_SB_G0
:
21153 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21154 case BFD_RELOC_ARM_ALU_SB_G1
:
21155 case BFD_RELOC_ARM_ALU_SB_G2
:
21156 gas_assert (!fixP
->fx_done
);
21157 if (!seg
->use_rela_p
)
21160 bfd_vma encoded_addend
;
21161 bfd_vma addend_abs
= abs (value
);
21163 /* Check that the absolute value of the addend can be
21164 expressed as an 8-bit constant plus a rotation. */
21165 encoded_addend
= encode_arm_immediate (addend_abs
);
21166 if (encoded_addend
== (unsigned int) FAIL
)
21167 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21168 _("the offset 0x%08lX is not representable"),
21169 (unsigned long) addend_abs
);
21171 /* Extract the instruction. */
21172 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21174 /* If the addend is positive, use an ADD instruction.
21175 Otherwise use a SUB. Take care not to destroy the S bit. */
21176 insn
&= 0xff1fffff;
21182 /* Place the encoded addend into the first 12 bits of the
21184 insn
&= 0xfffff000;
21185 insn
|= encoded_addend
;
21187 /* Update the instruction. */
21188 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21192 case BFD_RELOC_ARM_LDR_PC_G0
:
21193 case BFD_RELOC_ARM_LDR_PC_G1
:
21194 case BFD_RELOC_ARM_LDR_PC_G2
:
21195 case BFD_RELOC_ARM_LDR_SB_G0
:
21196 case BFD_RELOC_ARM_LDR_SB_G1
:
21197 case BFD_RELOC_ARM_LDR_SB_G2
:
21198 gas_assert (!fixP
->fx_done
);
21199 if (!seg
->use_rela_p
)
21202 bfd_vma addend_abs
= abs (value
);
21204 /* Check that the absolute value of the addend can be
21205 encoded in 12 bits. */
21206 if (addend_abs
>= 0x1000)
21207 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21208 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21209 (unsigned long) addend_abs
);
21211 /* Extract the instruction. */
21212 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21214 /* If the addend is negative, clear bit 23 of the instruction.
21215 Otherwise set it. */
21217 insn
&= ~(1 << 23);
21221 /* Place the absolute value of the addend into the first 12 bits
21222 of the instruction. */
21223 insn
&= 0xfffff000;
21224 insn
|= addend_abs
;
21226 /* Update the instruction. */
21227 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21231 case BFD_RELOC_ARM_LDRS_PC_G0
:
21232 case BFD_RELOC_ARM_LDRS_PC_G1
:
21233 case BFD_RELOC_ARM_LDRS_PC_G2
:
21234 case BFD_RELOC_ARM_LDRS_SB_G0
:
21235 case BFD_RELOC_ARM_LDRS_SB_G1
:
21236 case BFD_RELOC_ARM_LDRS_SB_G2
:
21237 gas_assert (!fixP
->fx_done
);
21238 if (!seg
->use_rela_p
)
21241 bfd_vma addend_abs
= abs (value
);
21243 /* Check that the absolute value of the addend can be
21244 encoded in 8 bits. */
21245 if (addend_abs
>= 0x100)
21246 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21247 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21248 (unsigned long) addend_abs
);
21250 /* Extract the instruction. */
21251 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21253 /* If the addend is negative, clear bit 23 of the instruction.
21254 Otherwise set it. */
21256 insn
&= ~(1 << 23);
21260 /* Place the first four bits of the absolute value of the addend
21261 into the first 4 bits of the instruction, and the remaining
21262 four into bits 8 .. 11. */
21263 insn
&= 0xfffff0f0;
21264 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21266 /* Update the instruction. */
21267 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21271 case BFD_RELOC_ARM_LDC_PC_G0
:
21272 case BFD_RELOC_ARM_LDC_PC_G1
:
21273 case BFD_RELOC_ARM_LDC_PC_G2
:
21274 case BFD_RELOC_ARM_LDC_SB_G0
:
21275 case BFD_RELOC_ARM_LDC_SB_G1
:
21276 case BFD_RELOC_ARM_LDC_SB_G2
:
21277 gas_assert (!fixP
->fx_done
);
21278 if (!seg
->use_rela_p
)
21281 bfd_vma addend_abs
= abs (value
);
21283 /* Check that the absolute value of the addend is a multiple of
21284 four and, when divided by four, fits in 8 bits. */
21285 if (addend_abs
& 0x3)
21286 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21287 _("bad offset 0x%08lX (must be word-aligned)"),
21288 (unsigned long) addend_abs
);
21290 if ((addend_abs
>> 2) > 0xff)
21291 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21292 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21293 (unsigned long) addend_abs
);
21295 /* Extract the instruction. */
21296 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21298 /* If the addend is negative, clear bit 23 of the instruction.
21299 Otherwise set it. */
21301 insn
&= ~(1 << 23);
21305 /* Place the addend (divided by four) into the first eight
21306 bits of the instruction. */
21307 insn
&= 0xfffffff0;
21308 insn
|= addend_abs
>> 2;
21310 /* Update the instruction. */
21311 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21315 case BFD_RELOC_ARM_V4BX
:
21316 /* This will need to go in the object file. */
21320 case BFD_RELOC_UNUSED
:
21322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21323 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21327 /* Translate internal representation of relocation info to BFD target
21331 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21334 bfd_reloc_code_real_type code
;
21336 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21338 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21339 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21340 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21342 if (fixp
->fx_pcrel
)
21344 if (section
->use_rela_p
)
21345 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21347 fixp
->fx_offset
= reloc
->address
;
21349 reloc
->addend
= fixp
->fx_offset
;
21351 switch (fixp
->fx_r_type
)
21354 if (fixp
->fx_pcrel
)
21356 code
= BFD_RELOC_8_PCREL
;
21361 if (fixp
->fx_pcrel
)
21363 code
= BFD_RELOC_16_PCREL
;
21368 if (fixp
->fx_pcrel
)
21370 code
= BFD_RELOC_32_PCREL
;
21374 case BFD_RELOC_ARM_MOVW
:
21375 if (fixp
->fx_pcrel
)
21377 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21381 case BFD_RELOC_ARM_MOVT
:
21382 if (fixp
->fx_pcrel
)
21384 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21388 case BFD_RELOC_ARM_THUMB_MOVW
:
21389 if (fixp
->fx_pcrel
)
21391 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21395 case BFD_RELOC_ARM_THUMB_MOVT
:
21396 if (fixp
->fx_pcrel
)
21398 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21402 case BFD_RELOC_NONE
:
21403 case BFD_RELOC_ARM_PCREL_BRANCH
:
21404 case BFD_RELOC_ARM_PCREL_BLX
:
21405 case BFD_RELOC_RVA
:
21406 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21407 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21408 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21409 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21410 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21411 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21412 case BFD_RELOC_VTABLE_ENTRY
:
21413 case BFD_RELOC_VTABLE_INHERIT
:
21415 case BFD_RELOC_32_SECREL
:
21417 code
= fixp
->fx_r_type
;
21420 case BFD_RELOC_THUMB_PCREL_BLX
:
21422 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21423 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21426 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21429 case BFD_RELOC_ARM_LITERAL
:
21430 case BFD_RELOC_ARM_HWLITERAL
:
21431 /* If this is called then the a literal has
21432 been referenced across a section boundary. */
21433 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21434 _("literal referenced across section boundary"));
21438 case BFD_RELOC_ARM_GOT32
:
21439 case BFD_RELOC_ARM_GOTOFF
:
21440 case BFD_RELOC_ARM_GOT_PREL
:
21441 case BFD_RELOC_ARM_PLT32
:
21442 case BFD_RELOC_ARM_TARGET1
:
21443 case BFD_RELOC_ARM_ROSEGREL32
:
21444 case BFD_RELOC_ARM_SBREL32
:
21445 case BFD_RELOC_ARM_PREL31
:
21446 case BFD_RELOC_ARM_TARGET2
:
21447 case BFD_RELOC_ARM_TLS_LE32
:
21448 case BFD_RELOC_ARM_TLS_LDO32
:
21449 case BFD_RELOC_ARM_PCREL_CALL
:
21450 case BFD_RELOC_ARM_PCREL_JUMP
:
21451 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21452 case BFD_RELOC_ARM_ALU_PC_G0
:
21453 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21454 case BFD_RELOC_ARM_ALU_PC_G1
:
21455 case BFD_RELOC_ARM_ALU_PC_G2
:
21456 case BFD_RELOC_ARM_LDR_PC_G0
:
21457 case BFD_RELOC_ARM_LDR_PC_G1
:
21458 case BFD_RELOC_ARM_LDR_PC_G2
:
21459 case BFD_RELOC_ARM_LDRS_PC_G0
:
21460 case BFD_RELOC_ARM_LDRS_PC_G1
:
21461 case BFD_RELOC_ARM_LDRS_PC_G2
:
21462 case BFD_RELOC_ARM_LDC_PC_G0
:
21463 case BFD_RELOC_ARM_LDC_PC_G1
:
21464 case BFD_RELOC_ARM_LDC_PC_G2
:
21465 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21466 case BFD_RELOC_ARM_ALU_SB_G0
:
21467 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21468 case BFD_RELOC_ARM_ALU_SB_G1
:
21469 case BFD_RELOC_ARM_ALU_SB_G2
:
21470 case BFD_RELOC_ARM_LDR_SB_G0
:
21471 case BFD_RELOC_ARM_LDR_SB_G1
:
21472 case BFD_RELOC_ARM_LDR_SB_G2
:
21473 case BFD_RELOC_ARM_LDRS_SB_G0
:
21474 case BFD_RELOC_ARM_LDRS_SB_G1
:
21475 case BFD_RELOC_ARM_LDRS_SB_G2
:
21476 case BFD_RELOC_ARM_LDC_SB_G0
:
21477 case BFD_RELOC_ARM_LDC_SB_G1
:
21478 case BFD_RELOC_ARM_LDC_SB_G2
:
21479 case BFD_RELOC_ARM_V4BX
:
21480 code
= fixp
->fx_r_type
;
21483 case BFD_RELOC_ARM_TLS_GD32
:
21484 case BFD_RELOC_ARM_TLS_IE32
:
21485 case BFD_RELOC_ARM_TLS_LDM32
:
21486 /* BFD will include the symbol's address in the addend.
21487 But we don't want that, so subtract it out again here. */
21488 if (!S_IS_COMMON (fixp
->fx_addsy
))
21489 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21490 code
= fixp
->fx_r_type
;
21494 case BFD_RELOC_ARM_IMMEDIATE
:
21495 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21496 _("internal relocation (type: IMMEDIATE) not fixed up"));
21499 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21500 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21501 _("ADRL used for a symbol not defined in the same file"));
21504 case BFD_RELOC_ARM_OFFSET_IMM
:
21505 if (section
->use_rela_p
)
21507 code
= fixp
->fx_r_type
;
21511 if (fixp
->fx_addsy
!= NULL
21512 && !S_IS_DEFINED (fixp
->fx_addsy
)
21513 && S_IS_LOCAL (fixp
->fx_addsy
))
21515 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21516 _("undefined local label `%s'"),
21517 S_GET_NAME (fixp
->fx_addsy
));
21521 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21522 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21529 switch (fixp
->fx_r_type
)
21531 case BFD_RELOC_NONE
: type
= "NONE"; break;
21532 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21533 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21534 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21535 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21536 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21537 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21538 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21539 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21540 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21541 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21542 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21543 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21544 default: type
= _("<unknown>"); break;
21546 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21547 _("cannot represent %s relocation in this object file format"),
21554 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21556 && fixp
->fx_addsy
== GOT_symbol
)
21558 code
= BFD_RELOC_ARM_GOTPC
;
21559 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21563 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21565 if (reloc
->howto
== NULL
)
21567 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21568 _("cannot represent %s relocation in this object file format"),
21569 bfd_get_reloc_code_name (code
));
21573 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21574 vtable entry to be used in the relocation's section offset. */
21575 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21576 reloc
->address
= fixp
->fx_offset
;
21581 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21584 cons_fix_new_arm (fragS
* frag
,
21589 bfd_reloc_code_real_type type
;
21593 FIXME: @@ Should look at CPU word size. */
21597 type
= BFD_RELOC_8
;
21600 type
= BFD_RELOC_16
;
21604 type
= BFD_RELOC_32
;
21607 type
= BFD_RELOC_64
;
21612 if (exp
->X_op
== O_secrel
)
21614 exp
->X_op
= O_symbol
;
21615 type
= BFD_RELOC_32_SECREL
;
21619 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21622 #if defined (OBJ_COFF)
21624 arm_validate_fix (fixS
* fixP
)
21626 /* If the destination of the branch is a defined symbol which does not have
21627 the THUMB_FUNC attribute, then we must be calling a function which has
21628 the (interfacearm) attribute. We look for the Thumb entry point to that
21629 function and change the branch to refer to that function instead. */
21630 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21631 && fixP
->fx_addsy
!= NULL
21632 && S_IS_DEFINED (fixP
->fx_addsy
)
21633 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21635 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21642 arm_force_relocation (struct fix
* fixp
)
21644 #if defined (OBJ_COFF) && defined (TE_PE)
21645 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21649 /* In case we have a call or a branch to a function in ARM ISA mode from
21650 a thumb function or vice-versa force the relocation. These relocations
21651 are cleared off for some cores that might have blx and simple transformations
21655 switch (fixp
->fx_r_type
)
21657 case BFD_RELOC_ARM_PCREL_JUMP
:
21658 case BFD_RELOC_ARM_PCREL_CALL
:
21659 case BFD_RELOC_THUMB_PCREL_BLX
:
21660 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21664 case BFD_RELOC_ARM_PCREL_BLX
:
21665 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21666 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21667 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21668 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21677 /* Resolve these relocations even if the symbol is extern or weak. */
21678 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21679 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21680 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21681 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21682 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21683 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21684 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21687 /* Always leave these relocations for the linker. */
21688 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21689 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21690 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21693 /* Always generate relocations against function symbols. */
21694 if (fixp
->fx_r_type
== BFD_RELOC_32
21696 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21699 return generic_force_reloc (fixp
);
21702 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21703 /* Relocations against function names must be left unadjusted,
21704 so that the linker can use this information to generate interworking
21705 stubs. The MIPS version of this function
21706 also prevents relocations that are mips-16 specific, but I do not
21707 know why it does this.
21710 There is one other problem that ought to be addressed here, but
21711 which currently is not: Taking the address of a label (rather
21712 than a function) and then later jumping to that address. Such
21713 addresses also ought to have their bottom bit set (assuming that
21714 they reside in Thumb code), but at the moment they will not. */
21717 arm_fix_adjustable (fixS
* fixP
)
21719 if (fixP
->fx_addsy
== NULL
)
21722 /* Preserve relocations against symbols with function type. */
21723 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21726 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21727 && fixP
->fx_subsy
== NULL
)
21730 /* We need the symbol name for the VTABLE entries. */
21731 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21732 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21735 /* Don't allow symbols to be discarded on GOT related relocs. */
21736 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21737 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21738 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21739 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21740 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21741 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21742 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21743 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21744 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21747 /* Similarly for group relocations. */
21748 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21749 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21750 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21753 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21754 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21755 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21756 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21757 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21758 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21759 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21760 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21761 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21766 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21771 elf32_arm_target_format (void)
21774 return (target_big_endian
21775 ? "elf32-bigarm-symbian"
21776 : "elf32-littlearm-symbian");
21777 #elif defined (TE_VXWORKS)
21778 return (target_big_endian
21779 ? "elf32-bigarm-vxworks"
21780 : "elf32-littlearm-vxworks");
21782 if (target_big_endian
)
21783 return "elf32-bigarm";
21785 return "elf32-littlearm";
21790 armelf_frob_symbol (symbolS
* symp
,
21793 elf_frob_symbol (symp
, puntp
);
21797 /* MD interface: Finalization. */
21802 literal_pool
* pool
;
21804 /* Ensure that all the IT blocks are properly closed. */
21805 check_it_blocks_finished ();
21807 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21809 /* Put it at the end of the relevant section. */
21810 subseg_set (pool
->section
, pool
->sub_section
);
21812 arm_elf_change_section ();
21819 /* Remove any excess mapping symbols generated for alignment frags in
21820 SEC. We may have created a mapping symbol before a zero byte
21821 alignment; remove it if there's a mapping symbol after the
21824 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21825 void *dummy ATTRIBUTE_UNUSED
)
21827 segment_info_type
*seginfo
= seg_info (sec
);
21830 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21833 for (fragp
= seginfo
->frchainP
->frch_root
;
21835 fragp
= fragp
->fr_next
)
21837 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21838 fragS
*next
= fragp
->fr_next
;
21840 /* Variable-sized frags have been converted to fixed size by
21841 this point. But if this was variable-sized to start with,
21842 there will be a fixed-size frag after it. So don't handle
21844 if (sym
== NULL
|| next
== NULL
)
21847 if (S_GET_VALUE (sym
) < next
->fr_address
)
21848 /* Not at the end of this frag. */
21850 know (S_GET_VALUE (sym
) == next
->fr_address
);
21854 if (next
->tc_frag_data
.first_map
!= NULL
)
21856 /* Next frag starts with a mapping symbol. Discard this
21858 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21862 if (next
->fr_next
== NULL
)
21864 /* This mapping symbol is at the end of the section. Discard
21866 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21867 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21871 /* As long as we have empty frags without any mapping symbols,
21873 /* If the next frag is non-empty and does not start with a
21874 mapping symbol, then this mapping symbol is required. */
21875 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21878 next
= next
->fr_next
;
21880 while (next
!= NULL
);
21885 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21889 arm_adjust_symtab (void)
21894 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21896 if (ARM_IS_THUMB (sym
))
21898 if (THUMB_IS_FUNC (sym
))
21900 /* Mark the symbol as a Thumb function. */
21901 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21902 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21903 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21905 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21906 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21908 as_bad (_("%s: unexpected function type: %d"),
21909 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21911 else switch (S_GET_STORAGE_CLASS (sym
))
21914 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21917 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21920 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21928 if (ARM_IS_INTERWORK (sym
))
21929 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21936 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21938 if (ARM_IS_THUMB (sym
))
21940 elf_symbol_type
* elf_sym
;
21942 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21943 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21945 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21946 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21948 /* If it's a .thumb_func, declare it as so,
21949 otherwise tag label as .code 16. */
21950 if (THUMB_IS_FUNC (sym
))
21951 elf_sym
->internal_elf_sym
.st_info
=
21952 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21953 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21954 elf_sym
->internal_elf_sym
.st_info
=
21955 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21960 /* Remove any overlapping mapping symbols generated by alignment frags. */
21961 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21962 /* Now do generic ELF adjustments. */
21963 elf_adjust_symtab ();
21967 /* MD interface: Initialization. */
21970 set_constant_flonums (void)
21974 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21975 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21979 /* Auto-select Thumb mode if it's the only available instruction set for the
21980 given architecture. */
21983 autoselect_thumb_from_cpu_variant (void)
21985 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21986 opcode_select (16);
21995 if ( (arm_ops_hsh
= hash_new ()) == NULL
21996 || (arm_cond_hsh
= hash_new ()) == NULL
21997 || (arm_shift_hsh
= hash_new ()) == NULL
21998 || (arm_psr_hsh
= hash_new ()) == NULL
21999 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22000 || (arm_reg_hsh
= hash_new ()) == NULL
22001 || (arm_reloc_hsh
= hash_new ()) == NULL
22002 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22003 as_fatal (_("virtual memory exhausted"));
22005 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22006 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22007 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22008 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22009 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22010 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22011 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22012 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22013 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22014 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22015 (void *) (v7m_psrs
+ i
));
22016 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22017 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22019 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22021 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22022 (void *) (barrier_opt_names
+ i
));
22024 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22025 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22028 set_constant_flonums ();
22030 /* Set the cpu variant based on the command-line options. We prefer
22031 -mcpu= over -march= if both are set (as for GCC); and we prefer
22032 -mfpu= over any other way of setting the floating point unit.
22033 Use of legacy options with new options are faulted. */
22036 if (mcpu_cpu_opt
|| march_cpu_opt
)
22037 as_bad (_("use of old and new-style options to set CPU type"));
22039 mcpu_cpu_opt
= legacy_cpu
;
22041 else if (!mcpu_cpu_opt
)
22042 mcpu_cpu_opt
= march_cpu_opt
;
22047 as_bad (_("use of old and new-style options to set FPU type"));
22049 mfpu_opt
= legacy_fpu
;
22051 else if (!mfpu_opt
)
22053 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22054 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22055 /* Some environments specify a default FPU. If they don't, infer it
22056 from the processor. */
22058 mfpu_opt
= mcpu_fpu_opt
;
22060 mfpu_opt
= march_fpu_opt
;
22062 mfpu_opt
= &fpu_default
;
22068 if (mcpu_cpu_opt
!= NULL
)
22069 mfpu_opt
= &fpu_default
;
22070 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22071 mfpu_opt
= &fpu_arch_vfp_v2
;
22073 mfpu_opt
= &fpu_arch_fpa
;
22079 mcpu_cpu_opt
= &cpu_default
;
22080 selected_cpu
= cpu_default
;
22084 selected_cpu
= *mcpu_cpu_opt
;
22086 mcpu_cpu_opt
= &arm_arch_any
;
22089 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22091 autoselect_thumb_from_cpu_variant ();
22093 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22095 #if defined OBJ_COFF || defined OBJ_ELF
22097 unsigned int flags
= 0;
22099 #if defined OBJ_ELF
22100 flags
= meabi_flags
;
22102 switch (meabi_flags
)
22104 case EF_ARM_EABI_UNKNOWN
:
22106 /* Set the flags in the private structure. */
22107 if (uses_apcs_26
) flags
|= F_APCS26
;
22108 if (support_interwork
) flags
|= F_INTERWORK
;
22109 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22110 if (pic_code
) flags
|= F_PIC
;
22111 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22112 flags
|= F_SOFT_FLOAT
;
22114 switch (mfloat_abi_opt
)
22116 case ARM_FLOAT_ABI_SOFT
:
22117 case ARM_FLOAT_ABI_SOFTFP
:
22118 flags
|= F_SOFT_FLOAT
;
22121 case ARM_FLOAT_ABI_HARD
:
22122 if (flags
& F_SOFT_FLOAT
)
22123 as_bad (_("hard-float conflicts with specified fpu"));
22127 /* Using pure-endian doubles (even if soft-float). */
22128 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22129 flags
|= F_VFP_FLOAT
;
22131 #if defined OBJ_ELF
22132 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22133 flags
|= EF_ARM_MAVERICK_FLOAT
;
22136 case EF_ARM_EABI_VER4
:
22137 case EF_ARM_EABI_VER5
:
22138 /* No additional flags to set. */
22145 bfd_set_private_flags (stdoutput
, flags
);
22147 /* We have run out flags in the COFF header to encode the
22148 status of ATPCS support, so instead we create a dummy,
22149 empty, debug section called .arm.atpcs. */
22154 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22158 bfd_set_section_flags
22159 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22160 bfd_set_section_size (stdoutput
, sec
, 0);
22161 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22167 /* Record the CPU type as well. */
22168 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22169 mach
= bfd_mach_arm_iWMMXt2
;
22170 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22171 mach
= bfd_mach_arm_iWMMXt
;
22172 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22173 mach
= bfd_mach_arm_XScale
;
22174 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22175 mach
= bfd_mach_arm_ep9312
;
22176 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22177 mach
= bfd_mach_arm_5TE
;
22178 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22180 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22181 mach
= bfd_mach_arm_5T
;
22183 mach
= bfd_mach_arm_5
;
22185 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22187 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22188 mach
= bfd_mach_arm_4T
;
22190 mach
= bfd_mach_arm_4
;
22192 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22193 mach
= bfd_mach_arm_3M
;
22194 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22195 mach
= bfd_mach_arm_3
;
22196 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22197 mach
= bfd_mach_arm_2a
;
22198 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22199 mach
= bfd_mach_arm_2
;
22201 mach
= bfd_mach_arm_unknown
;
22203 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22206 /* Command line processing. */
22209 Invocation line includes a switch not recognized by the base assembler.
22210 See if it's a processor-specific option.
22212 This routine is somewhat complicated by the need for backwards
22213 compatibility (since older releases of gcc can't be changed).
22214 The new options try to make the interface as compatible as
22217 New options (supported) are:
22219 -mcpu=<cpu name> Assemble for selected processor
22220 -march=<architecture name> Assemble for selected architecture
22221 -mfpu=<fpu architecture> Assemble for selected FPU.
22222 -EB/-mbig-endian Big-endian
22223 -EL/-mlittle-endian Little-endian
22224 -k Generate PIC code
22225 -mthumb Start in Thumb mode
22226 -mthumb-interwork Code supports ARM/Thumb interworking
22228 -m[no-]warn-deprecated Warn about deprecated features
22230 For now we will also provide support for:
22232 -mapcs-32 32-bit Program counter
22233 -mapcs-26 26-bit Program counter
22234 -macps-float Floats passed in FP registers
22235 -mapcs-reentrant Reentrant code
22237 (sometime these will probably be replaced with -mapcs=<list of options>
22238 and -matpcs=<list of options>)
22240 The remaining options are only supported for back-wards compatibility.
22241 Cpu variants, the arm part is optional:
22242 -m[arm]1 Currently not supported.
22243 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22244 -m[arm]3 Arm 3 processor
22245 -m[arm]6[xx], Arm 6 processors
22246 -m[arm]7[xx][t][[d]m] Arm 7 processors
22247 -m[arm]8[10] Arm 8 processors
22248 -m[arm]9[20][tdmi] Arm 9 processors
22249 -mstrongarm[110[0]] StrongARM processors
22250 -mxscale XScale processors
22251 -m[arm]v[2345[t[e]]] Arm architectures
22252 -mall All (except the ARM1)
22254 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22255 -mfpe-old (No float load/store multiples)
22256 -mvfpxd VFP Single precision
22258 -mno-fpu Disable all floating point instructions
22260 The following CPU names are recognized:
22261 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22262 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22263 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22264 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22265 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22266 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22267 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22271 const char * md_shortopts
= "m:k";
22273 #ifdef ARM_BI_ENDIAN
22274 #define OPTION_EB (OPTION_MD_BASE + 0)
22275 #define OPTION_EL (OPTION_MD_BASE + 1)
22277 #if TARGET_BYTES_BIG_ENDIAN
22278 #define OPTION_EB (OPTION_MD_BASE + 0)
22280 #define OPTION_EL (OPTION_MD_BASE + 1)
22283 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22285 struct option md_longopts
[] =
22288 {"EB", no_argument
, NULL
, OPTION_EB
},
22291 {"EL", no_argument
, NULL
, OPTION_EL
},
22293 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22294 {NULL
, no_argument
, NULL
, 0}
22297 size_t md_longopts_size
= sizeof (md_longopts
);
22299 struct arm_option_table
22301 char *option
; /* Option name to match. */
22302 char *help
; /* Help information. */
22303 int *var
; /* Variable to change. */
22304 int value
; /* What to change it to. */
22305 char *deprecated
; /* If non-null, print this message. */
22308 struct arm_option_table arm_opts
[] =
22310 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22311 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22312 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22313 &support_interwork
, 1, NULL
},
22314 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22315 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22316 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22318 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22319 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22320 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22321 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22324 /* These are recognized by the assembler, but have no affect on code. */
22325 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22326 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22328 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22329 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22330 &warn_on_deprecated
, 0, NULL
},
22331 {NULL
, NULL
, NULL
, 0, NULL
}
22334 struct arm_legacy_option_table
22336 char *option
; /* Option name to match. */
22337 const arm_feature_set
**var
; /* Variable to change. */
22338 const arm_feature_set value
; /* What to change it to. */
22339 char *deprecated
; /* If non-null, print this message. */
22342 const struct arm_legacy_option_table arm_legacy_opts
[] =
22344 /* DON'T add any new processors to this list -- we want the whole list
22345 to go away... Add them to the processors table instead. */
22346 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22347 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22348 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22349 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22350 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22351 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22352 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22353 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22354 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22355 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22356 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22357 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22358 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22359 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22360 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22361 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22362 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22363 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22364 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22365 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22366 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22367 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22368 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22369 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22370 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22371 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22372 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22373 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22374 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22375 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22376 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22377 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22378 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22379 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22380 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22381 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22382 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22383 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22384 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22385 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22386 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22387 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22388 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22389 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22390 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22391 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22392 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22393 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22394 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22395 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22396 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22397 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22398 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22399 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22400 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22401 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22402 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22403 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22404 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22405 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22406 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22407 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22408 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22409 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22410 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22411 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22412 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22413 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22414 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22415 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22416 N_("use -mcpu=strongarm110")},
22417 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22418 N_("use -mcpu=strongarm1100")},
22419 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22420 N_("use -mcpu=strongarm1110")},
22421 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22422 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22423 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22425 /* Architecture variants -- don't add any more to this list either. */
22426 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22427 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22428 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22429 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22430 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22431 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22432 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22433 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22434 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22435 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22436 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22437 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22438 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22439 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22440 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22441 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22442 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22443 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22445 /* Floating point variants -- don't add any more to this list either. */
22446 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22447 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22448 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22449 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22450 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22452 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22455 struct arm_cpu_option_table
22458 const arm_feature_set value
;
22459 /* For some CPUs we assume an FPU unless the user explicitly sets
22461 const arm_feature_set default_fpu
;
22462 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22464 const char *canonical_name
;
22467 /* This list should, at a minimum, contain all the cpu names
22468 recognized by GCC. */
22469 static const struct arm_cpu_option_table arm_cpus
[] =
22471 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22472 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22473 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22474 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22475 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22476 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22477 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22478 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22479 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22480 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22481 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22482 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22483 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22484 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22485 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22486 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22487 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22488 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22489 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22490 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22491 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22492 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22493 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22494 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22495 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22496 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22497 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22498 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22499 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22500 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22501 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22502 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22503 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22504 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22505 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22506 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22507 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22508 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22509 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22510 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22511 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22512 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22513 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22514 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22515 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22516 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22517 /* For V5 or later processors we default to using VFP; but the user
22518 should really set the FPU type explicitly. */
22519 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22520 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22521 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22522 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22523 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22524 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22525 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22526 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22527 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22528 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22529 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22530 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22531 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22532 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22533 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22534 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22535 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22536 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22537 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22538 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22539 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22540 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22541 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22542 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22543 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22544 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22545 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22546 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22547 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22548 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22549 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22550 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22551 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22552 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22553 FPU_NONE
, "Cortex-A5"},
22554 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22555 ARM_FEATURE (0, FPU_VFP_V3
22556 | FPU_NEON_EXT_V1
),
22558 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22559 ARM_FEATURE (0, FPU_VFP_V3
22560 | FPU_NEON_EXT_V1
),
22562 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22563 FPU_ARCH_NEON_VFP_V4
,
22565 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22566 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22568 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22569 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22570 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22571 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22572 /* ??? XSCALE is really an architecture. */
22573 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22574 /* ??? iwmmxt is not a processor. */
22575 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22576 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22577 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22579 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22580 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22583 struct arm_arch_option_table
22586 const arm_feature_set value
;
22587 const arm_feature_set default_fpu
;
22590 /* This list should, at a minimum, contain all the architecture names
22591 recognized by GCC. */
22592 static const struct arm_arch_option_table arm_archs
[] =
22594 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22595 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22596 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22597 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22598 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22599 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22600 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22601 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22602 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22603 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22604 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22605 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22606 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22607 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22608 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22609 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22610 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22611 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22612 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22613 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22614 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22615 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22616 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22617 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22618 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22619 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22620 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22621 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22622 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22623 /* The official spelling of the ARMv7 profile variants is the dashed form.
22624 Accept the non-dashed form for compatibility with old toolchains. */
22625 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22626 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22627 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22628 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22629 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22630 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22631 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22632 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22633 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22634 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22635 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22638 /* ISA extensions in the co-processor and main instruction set space. */
22639 struct arm_option_extension_value_table
22642 const arm_feature_set value
;
22643 const arm_feature_set allowed_archs
;
22646 /* The following table must be in alphabetical order with a NULL last entry.
22648 static const struct arm_option_extension_value_table arm_extensions
[] =
22650 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22651 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22652 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
22653 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
22654 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
22655 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
22656 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
22657 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
22658 ARM_FEATURE (ARM_EXT_V6M
, 0)},
22659 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
22660 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
22661 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
22662 ARM_FEATURE (ARM_EXT_V7A
, 0)},
22663 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
22664 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22667 /* ISA floating-point and Advanced SIMD extensions. */
22668 struct arm_option_fpu_value_table
22671 const arm_feature_set value
;
22674 /* This list should, at a minimum, contain all the fpu names
22675 recognized by GCC. */
22676 static const struct arm_option_fpu_value_table arm_fpus
[] =
22678 {"softfpa", FPU_NONE
},
22679 {"fpe", FPU_ARCH_FPE
},
22680 {"fpe2", FPU_ARCH_FPE
},
22681 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22682 {"fpa", FPU_ARCH_FPA
},
22683 {"fpa10", FPU_ARCH_FPA
},
22684 {"fpa11", FPU_ARCH_FPA
},
22685 {"arm7500fe", FPU_ARCH_FPA
},
22686 {"softvfp", FPU_ARCH_VFP
},
22687 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22688 {"vfp", FPU_ARCH_VFP_V2
},
22689 {"vfp9", FPU_ARCH_VFP_V2
},
22690 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22691 {"vfp10", FPU_ARCH_VFP_V2
},
22692 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22693 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22694 {"vfpv2", FPU_ARCH_VFP_V2
},
22695 {"vfpv3", FPU_ARCH_VFP_V3
},
22696 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22697 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22698 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22699 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22700 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22701 {"arm1020t", FPU_ARCH_VFP_V1
},
22702 {"arm1020e", FPU_ARCH_VFP_V2
},
22703 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22704 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22705 {"maverick", FPU_ARCH_MAVERICK
},
22706 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22707 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22708 {"vfpv4", FPU_ARCH_VFP_V4
},
22709 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22710 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22711 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22712 {NULL
, ARM_ARCH_NONE
}
22715 struct arm_option_value_table
22721 static const struct arm_option_value_table arm_float_abis
[] =
22723 {"hard", ARM_FLOAT_ABI_HARD
},
22724 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22725 {"soft", ARM_FLOAT_ABI_SOFT
},
22730 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22731 static const struct arm_option_value_table arm_eabis
[] =
22733 {"gnu", EF_ARM_EABI_UNKNOWN
},
22734 {"4", EF_ARM_EABI_VER4
},
22735 {"5", EF_ARM_EABI_VER5
},
22740 struct arm_long_option_table
22742 char * option
; /* Substring to match. */
22743 char * help
; /* Help information. */
22744 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22745 char * deprecated
; /* If non-null, print this message. */
22749 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22751 arm_feature_set
*ext_set
= (arm_feature_set
*)
22752 xmalloc (sizeof (arm_feature_set
));
22754 /* We insist on extensions being specified in alphabetical order, and with
22755 extensions being added before being removed. We achieve this by having
22756 the global ARM_EXTENSIONS table in alphabetical order, and using the
22757 ADDING_VALUE variable to indicate whether we are adding an extension (1)
22758 or removing it (0) and only allowing it to change in the order
22760 const struct arm_option_extension_value_table
* opt
= NULL
;
22761 int adding_value
= -1;
22763 /* Copy the feature set, so that we can modify it. */
22764 *ext_set
= **opt_p
;
22767 while (str
!= NULL
&& *str
!= 0)
22774 as_bad (_("invalid architectural extension"));
22779 ext
= strchr (str
, '+');
22782 optlen
= ext
- str
;
22784 optlen
= strlen (str
);
22787 && strncmp (str
, "no", 2) == 0)
22789 if (adding_value
!= 0)
22792 opt
= arm_extensions
;
22798 else if (optlen
> 0)
22800 if (adding_value
== -1)
22803 opt
= arm_extensions
;
22805 else if (adding_value
!= 1)
22807 as_bad (_("must specify extensions to add before specifying "
22808 "those to remove"));
22815 as_bad (_("missing architectural extension"));
22819 gas_assert (adding_value
!= -1);
22820 gas_assert (opt
!= NULL
);
22822 /* Scan over the options table trying to find an exact match. */
22823 for (; opt
->name
!= NULL
; opt
++)
22824 if (strncmp (opt
->name
, str
, optlen
) == 0
22825 && strlen (opt
->name
) == optlen
)
22827 /* Check we can apply the extension to this architecture. */
22828 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
22830 as_bad (_("extension does not apply to the base architecture"));
22834 /* Add or remove the extension. */
22836 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22838 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
22843 if (opt
->name
== NULL
)
22845 /* Did we fail to find an extension because it wasn't specified in
22846 alphabetical order, or because it does not exist? */
22848 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22849 if (strncmp (opt
->name
, str
, optlen
) == 0)
22852 if (opt
->name
== NULL
)
22853 as_bad (_("unknown architectural extension `%s'"), str
);
22855 as_bad (_("architectural extensions must be specified in "
22856 "alphabetical order"));
22862 /* We should skip the extension we've just matched the next time
22874 arm_parse_cpu (char * str
)
22876 const struct arm_cpu_option_table
* opt
;
22877 char * ext
= strchr (str
, '+');
22881 optlen
= ext
- str
;
22883 optlen
= strlen (str
);
22887 as_bad (_("missing cpu name `%s'"), str
);
22891 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22892 if (strncmp (opt
->name
, str
, optlen
) == 0)
22894 mcpu_cpu_opt
= &opt
->value
;
22895 mcpu_fpu_opt
= &opt
->default_fpu
;
22896 if (opt
->canonical_name
)
22897 strcpy (selected_cpu_name
, opt
->canonical_name
);
22902 for (i
= 0; i
< optlen
; i
++)
22903 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22904 selected_cpu_name
[i
] = 0;
22908 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22913 as_bad (_("unknown cpu `%s'"), str
);
22918 arm_parse_arch (char * str
)
22920 const struct arm_arch_option_table
*opt
;
22921 char *ext
= strchr (str
, '+');
22925 optlen
= ext
- str
;
22927 optlen
= strlen (str
);
22931 as_bad (_("missing architecture name `%s'"), str
);
22935 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22936 if (strncmp (opt
->name
, str
, optlen
) == 0)
22938 march_cpu_opt
= &opt
->value
;
22939 march_fpu_opt
= &opt
->default_fpu
;
22940 strcpy (selected_cpu_name
, opt
->name
);
22943 return arm_parse_extension (ext
, &march_cpu_opt
);
22948 as_bad (_("unknown architecture `%s'\n"), str
);
22953 arm_parse_fpu (char * str
)
22955 const struct arm_option_fpu_value_table
* opt
;
22957 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22958 if (streq (opt
->name
, str
))
22960 mfpu_opt
= &opt
->value
;
22964 as_bad (_("unknown floating point format `%s'\n"), str
);
22969 arm_parse_float_abi (char * str
)
22971 const struct arm_option_value_table
* opt
;
22973 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22974 if (streq (opt
->name
, str
))
22976 mfloat_abi_opt
= opt
->value
;
22980 as_bad (_("unknown floating point abi `%s'\n"), str
);
22986 arm_parse_eabi (char * str
)
22988 const struct arm_option_value_table
*opt
;
22990 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22991 if (streq (opt
->name
, str
))
22993 meabi_flags
= opt
->value
;
22996 as_bad (_("unknown EABI `%s'\n"), str
);
23002 arm_parse_it_mode (char * str
)
23004 bfd_boolean ret
= TRUE
;
23006 if (streq ("arm", str
))
23007 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23008 else if (streq ("thumb", str
))
23009 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23010 else if (streq ("always", str
))
23011 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23012 else if (streq ("never", str
))
23013 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23016 as_bad (_("unknown implicit IT mode `%s', should be "\
23017 "arm, thumb, always, or never."), str
);
23024 struct arm_long_option_table arm_long_opts
[] =
23026 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23027 arm_parse_cpu
, NULL
},
23028 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23029 arm_parse_arch
, NULL
},
23030 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23031 arm_parse_fpu
, NULL
},
23032 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23033 arm_parse_float_abi
, NULL
},
23035 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23036 arm_parse_eabi
, NULL
},
23038 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23039 arm_parse_it_mode
, NULL
},
23040 {NULL
, NULL
, 0, NULL
}
23044 md_parse_option (int c
, char * arg
)
23046 struct arm_option_table
*opt
;
23047 const struct arm_legacy_option_table
*fopt
;
23048 struct arm_long_option_table
*lopt
;
23054 target_big_endian
= 1;
23060 target_big_endian
= 0;
23064 case OPTION_FIX_V4BX
:
23069 /* Listing option. Just ignore these, we don't support additional
23074 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23076 if (c
== opt
->option
[0]
23077 && ((arg
== NULL
&& opt
->option
[1] == 0)
23078 || streq (arg
, opt
->option
+ 1)))
23080 /* If the option is deprecated, tell the user. */
23081 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23082 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23083 arg
? arg
: "", _(opt
->deprecated
));
23085 if (opt
->var
!= NULL
)
23086 *opt
->var
= opt
->value
;
23092 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23094 if (c
== fopt
->option
[0]
23095 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23096 || streq (arg
, fopt
->option
+ 1)))
23098 /* If the option is deprecated, tell the user. */
23099 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23100 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23101 arg
? arg
: "", _(fopt
->deprecated
));
23103 if (fopt
->var
!= NULL
)
23104 *fopt
->var
= &fopt
->value
;
23110 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23112 /* These options are expected to have an argument. */
23113 if (c
== lopt
->option
[0]
23115 && strncmp (arg
, lopt
->option
+ 1,
23116 strlen (lopt
->option
+ 1)) == 0)
23118 /* If the option is deprecated, tell the user. */
23119 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23120 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23121 _(lopt
->deprecated
));
23123 /* Call the sup-option parser. */
23124 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23135 md_show_usage (FILE * fp
)
23137 struct arm_option_table
*opt
;
23138 struct arm_long_option_table
*lopt
;
23140 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23142 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23143 if (opt
->help
!= NULL
)
23144 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23146 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23147 if (lopt
->help
!= NULL
)
23148 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23152 -EB assemble code for a big-endian cpu\n"));
23157 -EL assemble code for a little-endian cpu\n"));
23161 --fix-v4bx Allow BX in ARMv4 code\n"));
23169 arm_feature_set flags
;
23170 } cpu_arch_ver_table
;
23172 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23173 least features first. */
23174 static const cpu_arch_ver_table cpu_arch_ver
[] =
23180 {4, ARM_ARCH_V5TE
},
23181 {5, ARM_ARCH_V5TEJ
},
23185 {11, ARM_ARCH_V6M
},
23186 {12, ARM_ARCH_V6SM
},
23187 {8, ARM_ARCH_V6T2
},
23188 {10, ARM_ARCH_V7A
},
23189 {10, ARM_ARCH_V7R
},
23190 {10, ARM_ARCH_V7M
},
23194 /* Set an attribute if it has not already been set by the user. */
23196 aeabi_set_attribute_int (int tag
, int value
)
23199 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23200 || !attributes_set_explicitly
[tag
])
23201 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23205 aeabi_set_attribute_string (int tag
, const char *value
)
23208 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23209 || !attributes_set_explicitly
[tag
])
23210 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23213 /* Set the public EABI object attributes. */
23215 aeabi_set_public_attributes (void)
23219 arm_feature_set flags
;
23220 arm_feature_set tmp
;
23221 const cpu_arch_ver_table
*p
;
23223 /* Choose the architecture based on the capabilities of the requested cpu
23224 (if any) and/or the instructions actually used. */
23225 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23226 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23227 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23228 /*Allow the user to override the reported architecture. */
23231 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23232 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23237 for (p
= cpu_arch_ver
; p
->val
; p
++)
23239 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23242 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23246 /* The table lookup above finds the last architecture to contribute
23247 a new feature. Unfortunately, Tag13 is a subset of the union of
23248 v6T2 and v7-M, so it is never seen as contributing a new feature.
23249 We can not search for the last entry which is entirely used,
23250 because if no CPU is specified we build up only those flags
23251 actually used. Perhaps we should separate out the specified
23252 and implicit cases. Avoid taking this path for -march=all by
23253 checking for contradictory v7-A / v7-M features. */
23255 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23256 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23257 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23260 /* Tag_CPU_name. */
23261 if (selected_cpu_name
[0])
23265 q
= selected_cpu_name
;
23266 if (strncmp (q
, "armv", 4) == 0)
23271 for (i
= 0; q
[i
]; i
++)
23272 q
[i
] = TOUPPER (q
[i
]);
23274 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23277 /* Tag_CPU_arch. */
23278 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23280 /* Tag_CPU_arch_profile. */
23281 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23282 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23283 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23284 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23285 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23286 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23288 /* Tag_ARM_ISA_use. */
23289 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23291 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23293 /* Tag_THUMB_ISA_use. */
23294 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23296 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23297 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23299 /* Tag_VFP_arch. */
23300 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23301 aeabi_set_attribute_int (Tag_VFP_arch
,
23302 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23304 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23305 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23306 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23307 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23308 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23309 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23310 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23311 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23312 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23314 /* Tag_ABI_HardFP_use. */
23315 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23316 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23317 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23319 /* Tag_WMMX_arch. */
23320 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23321 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23322 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23323 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23325 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23326 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23327 aeabi_set_attribute_int
23328 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23331 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23332 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23333 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23336 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23337 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23338 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23339 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23341 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23343 /* Tag_MP_extension_use. */
23344 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23345 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23347 /* Tag Virtualization_use. */
23348 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23350 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23353 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23356 /* Add the default contents for the .ARM.attributes section. */
23360 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23363 aeabi_set_public_attributes ();
23365 #endif /* OBJ_ELF */
23368 /* Parse a .cpu directive. */
23371 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23373 const struct arm_cpu_option_table
*opt
;
23377 name
= input_line_pointer
;
23378 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23379 input_line_pointer
++;
23380 saved_char
= *input_line_pointer
;
23381 *input_line_pointer
= 0;
23383 /* Skip the first "all" entry. */
23384 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23385 if (streq (opt
->name
, name
))
23387 mcpu_cpu_opt
= &opt
->value
;
23388 selected_cpu
= opt
->value
;
23389 if (opt
->canonical_name
)
23390 strcpy (selected_cpu_name
, opt
->canonical_name
);
23394 for (i
= 0; opt
->name
[i
]; i
++)
23395 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23396 selected_cpu_name
[i
] = 0;
23398 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23399 *input_line_pointer
= saved_char
;
23400 demand_empty_rest_of_line ();
23403 as_bad (_("unknown cpu `%s'"), name
);
23404 *input_line_pointer
= saved_char
;
23405 ignore_rest_of_line ();
23409 /* Parse a .arch directive. */
23412 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23414 const struct arm_arch_option_table
*opt
;
23418 name
= input_line_pointer
;
23419 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23420 input_line_pointer
++;
23421 saved_char
= *input_line_pointer
;
23422 *input_line_pointer
= 0;
23424 /* Skip the first "all" entry. */
23425 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23426 if (streq (opt
->name
, name
))
23428 mcpu_cpu_opt
= &opt
->value
;
23429 selected_cpu
= opt
->value
;
23430 strcpy (selected_cpu_name
, opt
->name
);
23431 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23432 *input_line_pointer
= saved_char
;
23433 demand_empty_rest_of_line ();
23437 as_bad (_("unknown architecture `%s'\n"), name
);
23438 *input_line_pointer
= saved_char
;
23439 ignore_rest_of_line ();
23443 /* Parse a .object_arch directive. */
23446 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23448 const struct arm_arch_option_table
*opt
;
23452 name
= input_line_pointer
;
23453 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23454 input_line_pointer
++;
23455 saved_char
= *input_line_pointer
;
23456 *input_line_pointer
= 0;
23458 /* Skip the first "all" entry. */
23459 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23460 if (streq (opt
->name
, name
))
23462 object_arch
= &opt
->value
;
23463 *input_line_pointer
= saved_char
;
23464 demand_empty_rest_of_line ();
23468 as_bad (_("unknown architecture `%s'\n"), name
);
23469 *input_line_pointer
= saved_char
;
23470 ignore_rest_of_line ();
23473 /* Parse a .arch_extension directive. */
23476 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23478 const struct arm_option_extension_value_table
*opt
;
23481 int adding_value
= 1;
23483 name
= input_line_pointer
;
23484 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23485 input_line_pointer
++;
23486 saved_char
= *input_line_pointer
;
23487 *input_line_pointer
= 0;
23489 if (strlen (name
) >= 2
23490 && strncmp (name
, "no", 2) == 0)
23496 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23497 if (streq (opt
->name
, name
))
23499 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23501 as_bad (_("architectural extension `%s' is not allowed for the "
23502 "current base architecture"), name
);
23507 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23509 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23511 mcpu_cpu_opt
= &selected_cpu
;
23512 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23513 *input_line_pointer
= saved_char
;
23514 demand_empty_rest_of_line ();
23518 if (opt
->name
== NULL
)
23519 as_bad (_("unknown architecture `%s'\n"), name
);
23521 *input_line_pointer
= saved_char
;
23522 ignore_rest_of_line ();
23525 /* Parse a .fpu directive. */
23528 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23530 const struct arm_option_fpu_value_table
*opt
;
23534 name
= input_line_pointer
;
23535 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23536 input_line_pointer
++;
23537 saved_char
= *input_line_pointer
;
23538 *input_line_pointer
= 0;
23540 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23541 if (streq (opt
->name
, name
))
23543 mfpu_opt
= &opt
->value
;
23544 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23545 *input_line_pointer
= saved_char
;
23546 demand_empty_rest_of_line ();
23550 as_bad (_("unknown floating point format `%s'\n"), name
);
23551 *input_line_pointer
= saved_char
;
23552 ignore_rest_of_line ();
23555 /* Copy symbol information. */
23558 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23560 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23564 /* Given a symbolic attribute NAME, return the proper integer value.
23565 Returns -1 if the attribute is not known. */
23568 arm_convert_symbolic_attribute (const char *name
)
23570 static const struct
23575 attribute_table
[] =
23577 /* When you modify this table you should
23578 also modify the list in doc/c-arm.texi. */
23579 #define T(tag) {#tag, tag}
23580 T (Tag_CPU_raw_name
),
23583 T (Tag_CPU_arch_profile
),
23584 T (Tag_ARM_ISA_use
),
23585 T (Tag_THUMB_ISA_use
),
23589 T (Tag_Advanced_SIMD_arch
),
23590 T (Tag_PCS_config
),
23591 T (Tag_ABI_PCS_R9_use
),
23592 T (Tag_ABI_PCS_RW_data
),
23593 T (Tag_ABI_PCS_RO_data
),
23594 T (Tag_ABI_PCS_GOT_use
),
23595 T (Tag_ABI_PCS_wchar_t
),
23596 T (Tag_ABI_FP_rounding
),
23597 T (Tag_ABI_FP_denormal
),
23598 T (Tag_ABI_FP_exceptions
),
23599 T (Tag_ABI_FP_user_exceptions
),
23600 T (Tag_ABI_FP_number_model
),
23601 T (Tag_ABI_align_needed
),
23602 T (Tag_ABI_align8_needed
),
23603 T (Tag_ABI_align_preserved
),
23604 T (Tag_ABI_align8_preserved
),
23605 T (Tag_ABI_enum_size
),
23606 T (Tag_ABI_HardFP_use
),
23607 T (Tag_ABI_VFP_args
),
23608 T (Tag_ABI_WMMX_args
),
23609 T (Tag_ABI_optimization_goals
),
23610 T (Tag_ABI_FP_optimization_goals
),
23611 T (Tag_compatibility
),
23612 T (Tag_CPU_unaligned_access
),
23613 T (Tag_FP_HP_extension
),
23614 T (Tag_VFP_HP_extension
),
23615 T (Tag_ABI_FP_16bit_format
),
23616 T (Tag_MPextension_use
),
23618 T (Tag_nodefaults
),
23619 T (Tag_also_compatible_with
),
23620 T (Tag_conformance
),
23622 T (Tag_Virtualization_use
),
23623 /* We deliberately do not include Tag_MPextension_use_legacy. */
23631 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23632 if (streq (name
, attribute_table
[i
].name
))
23633 return attribute_table
[i
].tag
;
23639 /* Apply sym value for relocations only in the case that
23640 they are for local symbols and you have the respective
23641 architectural feature for blx and simple switches. */
23643 arm_apply_sym_value (struct fix
* fixP
)
23646 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23647 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23649 switch (fixP
->fx_r_type
)
23651 case BFD_RELOC_ARM_PCREL_BLX
:
23652 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23653 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23657 case BFD_RELOC_ARM_PCREL_CALL
:
23658 case BFD_RELOC_THUMB_PCREL_BLX
:
23659 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23670 #endif /* OBJ_ELF */