1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
188 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_arch_any
= ARM_ANY
;
202 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
203 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
204 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
206 static const arm_feature_set arm_cext_iwmmxt2
=
207 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
208 static const arm_feature_set arm_cext_iwmmxt
=
209 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
210 static const arm_feature_set arm_cext_xscale
=
211 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
212 static const arm_feature_set arm_cext_maverick
=
213 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
214 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
215 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v1xd
=
217 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
218 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
219 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
221 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
222 static const arm_feature_set fpu_vfp_ext_d32
=
223 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
224 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
225 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
226 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
227 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
228 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
229 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
231 static int mfloat_abi_opt
= -1;
232 /* Record user cpu selection for object attributes. */
233 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
234 /* Must be long enough to hold any of the names in arm_cpus. */
235 static char selected_cpu_name
[16];
238 static int meabi_flags
= EABI_DEFAULT
;
240 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
243 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
248 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
253 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
254 symbolS
* GOT_symbol
;
257 /* 0: assemble for ARM,
258 1: assemble for Thumb,
259 2: assemble for Thumb even though target CPU does not support thumb
261 static int thumb_mode
= 0;
262 /* A value distinct from the possible values for thumb_mode that we
263 can use to record whether thumb_mode has been copied into the
264 tc_frag_data field of a frag. */
265 #define MODE_RECORDED (1 << 4)
267 /* Specifies the intrinsic IT insn behavior mode. */
268 enum implicit_it_mode
270 IMPLICIT_IT_MODE_NEVER
= 0x00,
271 IMPLICIT_IT_MODE_ARM
= 0x01,
272 IMPLICIT_IT_MODE_THUMB
= 0x02,
273 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
275 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
277 /* If unified_syntax is true, we are processing the new unified
278 ARM/Thumb syntax. Important differences from the old ARM mode:
280 - Immediate operands do not require a # prefix.
281 - Conditional affixes always appear at the end of the
282 instruction. (For backward compatibility, those instructions
283 that formerly had them in the middle, continue to accept them
285 - The IT instruction may appear, and if it does is validated
286 against subsequent conditional affixes. It does not generate
289 Important differences from the old Thumb mode:
291 - Immediate operands do not require a # prefix.
292 - Most of the V6T2 instructions are only available in unified mode.
293 - The .N and .W suffixes are recognized and honored (it is an error
294 if they cannot be honored).
295 - All instructions set the flags if and only if they have an 's' affix.
296 - Conditional affixes may be used. They are validated against
297 preceding IT instructions. Unlike ARM mode, you cannot use a
298 conditional affix except in the scope of an IT instruction. */
300 static bfd_boolean unified_syntax
= FALSE
;
315 enum neon_el_type type
;
319 #define NEON_MAX_TYPE_ELS 4
323 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
327 enum it_instruction_type
332 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
333 if inside, should be the last one. */
334 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
335 i.e. BKPT and NOP. */
336 IT_INSN
/* The IT insn has been parsed. */
342 unsigned long instruction
;
346 /* "uncond_value" is set to the value in place of the conditional field in
347 unconditional versions of the instruction, or -1 if nothing is
350 struct neon_type vectype
;
351 /* This does not indicate an actual NEON instruction, only that
352 the mnemonic accepts neon-style type suffixes. */
354 /* Set to the opcode if the instruction needs relaxation.
355 Zero if the instruction is not relaxed. */
359 bfd_reloc_code_real_type type
;
364 enum it_instruction_type it_insn_type
;
370 struct neon_type_el vectype
;
371 unsigned present
: 1; /* Operand present. */
372 unsigned isreg
: 1; /* Operand was a register. */
373 unsigned immisreg
: 1; /* .imm field is a second register. */
374 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
375 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
376 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
377 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
378 instructions. This allows us to disambiguate ARM <-> vector insns. */
379 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
380 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
381 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
382 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
383 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
384 unsigned writeback
: 1; /* Operand has trailing ! */
385 unsigned preind
: 1; /* Preindexed address. */
386 unsigned postind
: 1; /* Postindexed address. */
387 unsigned negative
: 1; /* Index register was negated. */
388 unsigned shifted
: 1; /* Shift applied to operation. */
389 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
393 static struct arm_it inst
;
395 #define NUM_FLOAT_VALS 8
397 const char * fp_const
[] =
399 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
402 /* Number of littlenums required to hold an extended precision number. */
403 #define MAX_LITTLENUMS 6
405 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
415 #define CP_T_X 0x00008000
416 #define CP_T_Y 0x00400000
418 #define CONDS_BIT 0x00100000
419 #define LOAD_BIT 0x00100000
421 #define DOUBLE_LOAD_FLAG 0x00000001
425 const char * template_name
;
429 #define COND_ALWAYS 0xE
433 const char * template_name
;
437 struct asm_barrier_opt
439 const char * template_name
;
443 /* The bit that distinguishes CPSR and SPSR. */
444 #define SPSR_BIT (1 << 22)
446 /* The individual PSR flag bits. */
447 #define PSR_c (1 << 16)
448 #define PSR_x (1 << 17)
449 #define PSR_s (1 << 18)
450 #define PSR_f (1 << 19)
455 bfd_reloc_code_real_type reloc
;
460 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
461 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
466 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
469 /* Bits for DEFINED field in neon_typed_alias. */
470 #define NTA_HASTYPE 1
471 #define NTA_HASINDEX 2
473 struct neon_typed_alias
475 unsigned char defined
;
477 struct neon_type_el eltype
;
480 /* ARM register categories. This includes coprocessor numbers and various
481 architecture extensions' registers. */
507 /* Structure for a hash table entry for a register.
508 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
509 information which states whether a vector type or index is specified (for a
510 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
514 unsigned char number
;
516 unsigned char builtin
;
517 struct neon_typed_alias
* neon
;
520 /* Diagnostics used when we don't get a register of the expected type. */
521 const char * const reg_expected_msgs
[] =
523 N_("ARM register expected"),
524 N_("bad or missing co-processor number"),
525 N_("co-processor register expected"),
526 N_("FPA register expected"),
527 N_("VFP single precision register expected"),
528 N_("VFP/Neon double precision register expected"),
529 N_("Neon quad precision register expected"),
530 N_("VFP single or double precision register expected"),
531 N_("Neon double or quad precision register expected"),
532 N_("VFP single, double or Neon quad precision register expected"),
533 N_("VFP system register expected"),
534 N_("Maverick MVF register expected"),
535 N_("Maverick MVD register expected"),
536 N_("Maverick MVFX register expected"),
537 N_("Maverick MVDX register expected"),
538 N_("Maverick MVAX register expected"),
539 N_("Maverick DSPSC register expected"),
540 N_("iWMMXt data register expected"),
541 N_("iWMMXt control register expected"),
542 N_("iWMMXt scalar register expected"),
543 N_("XScale accumulator register expected"),
546 /* Some well known registers that we refer to directly elsewhere. */
551 /* ARM instructions take 4bytes in the object file, Thumb instructions
557 /* Basic string to match. */
558 const char * template_name
;
560 /* Parameters to instruction. */
561 unsigned int operands
[8];
563 /* Conditional tag - see opcode_lookup. */
564 unsigned int tag
: 4;
566 /* Basic instruction code. */
567 unsigned int avalue
: 28;
569 /* Thumb-format instruction code. */
572 /* Which architecture variant provides this instruction. */
573 const arm_feature_set
* avariant
;
574 const arm_feature_set
* tvariant
;
576 /* Function to call to encode instruction in ARM format. */
577 void (* aencode
) (void);
579 /* Function to call to encode instruction in Thumb format. */
580 void (* tencode
) (void);
583 /* Defines for various bits that we will want to toggle. */
584 #define INST_IMMEDIATE 0x02000000
585 #define OFFSET_REG 0x02000000
586 #define HWOFFSET_IMM 0x00400000
587 #define SHIFT_BY_REG 0x00000010
588 #define PRE_INDEX 0x01000000
589 #define INDEX_UP 0x00800000
590 #define WRITE_BACK 0x00200000
591 #define LDM_TYPE_2_OR_3 0x00400000
592 #define CPSI_MMOD 0x00020000
594 #define LITERAL_MASK 0xf000f000
595 #define OPCODE_MASK 0xfe1fffff
596 #define V4_STR_BIT 0x00000020
598 #define T2_SUBS_PC_LR 0xf3de8f00
600 #define DATA_OP_SHIFT 21
602 #define T2_OPCODE_MASK 0xfe1fffff
603 #define T2_DATA_OP_SHIFT 21
605 /* Codes to distinguish the arithmetic instructions. */
616 #define OPCODE_CMP 10
617 #define OPCODE_CMN 11
618 #define OPCODE_ORR 12
619 #define OPCODE_MOV 13
620 #define OPCODE_BIC 14
621 #define OPCODE_MVN 15
623 #define T2_OPCODE_AND 0
624 #define T2_OPCODE_BIC 1
625 #define T2_OPCODE_ORR 2
626 #define T2_OPCODE_ORN 3
627 #define T2_OPCODE_EOR 4
628 #define T2_OPCODE_ADD 8
629 #define T2_OPCODE_ADC 10
630 #define T2_OPCODE_SBC 11
631 #define T2_OPCODE_SUB 13
632 #define T2_OPCODE_RSB 14
634 #define T_OPCODE_MUL 0x4340
635 #define T_OPCODE_TST 0x4200
636 #define T_OPCODE_CMN 0x42c0
637 #define T_OPCODE_NEG 0x4240
638 #define T_OPCODE_MVN 0x43c0
640 #define T_OPCODE_ADD_R3 0x1800
641 #define T_OPCODE_SUB_R3 0x1a00
642 #define T_OPCODE_ADD_HI 0x4400
643 #define T_OPCODE_ADD_ST 0xb000
644 #define T_OPCODE_SUB_ST 0xb080
645 #define T_OPCODE_ADD_SP 0xa800
646 #define T_OPCODE_ADD_PC 0xa000
647 #define T_OPCODE_ADD_I8 0x3000
648 #define T_OPCODE_SUB_I8 0x3800
649 #define T_OPCODE_ADD_I3 0x1c00
650 #define T_OPCODE_SUB_I3 0x1e00
652 #define T_OPCODE_ASR_R 0x4100
653 #define T_OPCODE_LSL_R 0x4080
654 #define T_OPCODE_LSR_R 0x40c0
655 #define T_OPCODE_ROR_R 0x41c0
656 #define T_OPCODE_ASR_I 0x1000
657 #define T_OPCODE_LSL_I 0x0000
658 #define T_OPCODE_LSR_I 0x0800
660 #define T_OPCODE_MOV_I8 0x2000
661 #define T_OPCODE_CMP_I8 0x2800
662 #define T_OPCODE_CMP_LR 0x4280
663 #define T_OPCODE_MOV_HR 0x4600
664 #define T_OPCODE_CMP_HR 0x4500
666 #define T_OPCODE_LDR_PC 0x4800
667 #define T_OPCODE_LDR_SP 0x9800
668 #define T_OPCODE_STR_SP 0x9000
669 #define T_OPCODE_LDR_IW 0x6800
670 #define T_OPCODE_STR_IW 0x6000
671 #define T_OPCODE_LDR_IH 0x8800
672 #define T_OPCODE_STR_IH 0x8000
673 #define T_OPCODE_LDR_IB 0x7800
674 #define T_OPCODE_STR_IB 0x7000
675 #define T_OPCODE_LDR_RW 0x5800
676 #define T_OPCODE_STR_RW 0x5000
677 #define T_OPCODE_LDR_RH 0x5a00
678 #define T_OPCODE_STR_RH 0x5200
679 #define T_OPCODE_LDR_RB 0x5c00
680 #define T_OPCODE_STR_RB 0x5400
682 #define T_OPCODE_PUSH 0xb400
683 #define T_OPCODE_POP 0xbc00
685 #define T_OPCODE_BRANCH 0xe000
687 #define THUMB_SIZE 2 /* Size of thumb instruction. */
688 #define THUMB_PP_PC_LR 0x0100
689 #define THUMB_LOAD_BIT 0x0800
690 #define THUMB2_LOAD_BIT 0x00100000
692 #define BAD_ARGS _("bad arguments to instruction")
693 #define BAD_SP _("r13 not allowed here")
694 #define BAD_PC _("r15 not allowed here")
695 #define BAD_COND _("instruction cannot be conditional")
696 #define BAD_OVERLAP _("registers may not be the same")
697 #define BAD_HIREG _("lo register required")
698 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
699 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
700 #define BAD_BRANCH _("branch must be last instruction in IT block")
701 #define BAD_NOT_IT _("instruction not allowed in IT block")
702 #define BAD_FPU _("selected FPU does not support instruction")
703 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
704 #define BAD_IT_COND _("incorrect condition in IT block")
705 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
706 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
707 #define BAD_PC_ADDRESSING \
708 _("cannot use register index with PC-relative addressing")
709 #define BAD_PC_WRITEBACK \
710 _("cannot use writeback with PC-relative addressing")
712 static struct hash_control
* arm_ops_hsh
;
713 static struct hash_control
* arm_cond_hsh
;
714 static struct hash_control
* arm_shift_hsh
;
715 static struct hash_control
* arm_psr_hsh
;
716 static struct hash_control
* arm_v7m_psr_hsh
;
717 static struct hash_control
* arm_reg_hsh
;
718 static struct hash_control
* arm_reloc_hsh
;
719 static struct hash_control
* arm_barrier_opt_hsh
;
721 /* Stuff needed to resolve the label ambiguity
730 symbolS
* last_label_seen
;
731 static int label_is_thumb_function_name
= FALSE
;
733 /* Literal pool structure. Held on a per-section
734 and per-sub-section basis. */
736 #define MAX_LITERAL_POOL_SIZE 1024
737 typedef struct literal_pool
739 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
740 unsigned int next_free_entry
;
745 struct literal_pool
* next
;
748 /* Pointer to a linked list of literal pools. */
749 literal_pool
* list_of_pools
= NULL
;
752 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
754 static struct current_it now_it
;
758 now_it_compatible (int cond
)
760 return (cond
& ~1) == (now_it
.cc
& ~1);
764 conditional_insn (void)
766 return inst
.cond
!= COND_ALWAYS
;
769 static int in_it_block (void);
771 static int handle_it_state (void);
773 static void force_automatic_it_block_close (void);
775 static void it_fsm_post_encode (void);
777 #define set_it_insn_type(type) \
780 inst.it_insn_type = type; \
781 if (handle_it_state () == FAIL) \
786 #define set_it_insn_type_nonvoid(type, failret) \
789 inst.it_insn_type = type; \
790 if (handle_it_state () == FAIL) \
795 #define set_it_insn_type_last() \
798 if (inst.cond == COND_ALWAYS) \
799 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
801 set_it_insn_type (INSIDE_IT_LAST_INSN); \
807 /* This array holds the chars that always start a comment. If the
808 pre-processor is disabled, these aren't very useful. */
809 const char comment_chars
[] = "@";
811 /* This array holds the chars that only start a comment at the beginning of
812 a line. If the line seems to have the form '# 123 filename'
813 .line and .file directives will appear in the pre-processed output. */
814 /* Note that input_file.c hand checks for '#' at the beginning of the
815 first line of the input file. This is because the compiler outputs
816 #NO_APP at the beginning of its output. */
817 /* Also note that comments like this one will always work. */
818 const char line_comment_chars
[] = "#";
820 const char line_separator_chars
[] = ";";
822 /* Chars that can be used to separate mant
823 from exp in floating point numbers. */
824 const char EXP_CHARS
[] = "eE";
826 /* Chars that mean this number is a floating point constant. */
830 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
832 /* Prefix characters that indicate the start of an immediate
834 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
836 /* Separator character handling. */
838 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
841 skip_past_char (char ** str
, char c
)
852 #define skip_past_comma(str) skip_past_char (str, ',')
854 /* Arithmetic expressions (possibly involving symbols). */
856 /* Return TRUE if anything in the expression is a bignum. */
859 walk_no_bignums (symbolS
* sp
)
861 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
864 if (symbol_get_value_expression (sp
)->X_add_symbol
)
866 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
867 || (symbol_get_value_expression (sp
)->X_op_symbol
868 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
874 static int in_my_get_expression
= 0;
876 /* Third argument to my_get_expression. */
877 #define GE_NO_PREFIX 0
878 #define GE_IMM_PREFIX 1
879 #define GE_OPT_PREFIX 2
880 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
881 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
882 #define GE_OPT_PREFIX_BIG 3
885 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
890 /* In unified syntax, all prefixes are optional. */
892 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
897 case GE_NO_PREFIX
: break;
899 if (!is_immediate_prefix (**str
))
901 inst
.error
= _("immediate expression requires a # prefix");
907 case GE_OPT_PREFIX_BIG
:
908 if (is_immediate_prefix (**str
))
914 memset (ep
, 0, sizeof (expressionS
));
916 save_in
= input_line_pointer
;
917 input_line_pointer
= *str
;
918 in_my_get_expression
= 1;
919 seg
= expression (ep
);
920 in_my_get_expression
= 0;
922 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
924 /* We found a bad or missing expression in md_operand(). */
925 *str
= input_line_pointer
;
926 input_line_pointer
= save_in
;
927 if (inst
.error
== NULL
)
928 inst
.error
= (ep
->X_op
== O_absent
929 ? _("missing expression") :_("bad expression"));
934 if (seg
!= absolute_section
935 && seg
!= text_section
936 && seg
!= data_section
937 && seg
!= bss_section
938 && seg
!= undefined_section
)
940 inst
.error
= _("bad segment");
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
949 /* Get rid of any bignums now, so that we don't generate an error for which
950 we can't establish a line number later on. Big numbers are never valid
951 in instructions, which is where this routine is always called. */
952 if (prefix_mode
!= GE_OPT_PREFIX_BIG
953 && (ep
->X_op
== O_big
955 && (walk_no_bignums (ep
->X_add_symbol
)
957 && walk_no_bignums (ep
->X_op_symbol
))))))
959 inst
.error
= _("invalid constant");
960 *str
= input_line_pointer
;
961 input_line_pointer
= save_in
;
965 *str
= input_line_pointer
;
966 input_line_pointer
= save_in
;
970 /* Turn a string in input_line_pointer into a floating point constant
971 of type TYPE, and store the appropriate bytes in *LITP. The number
972 of LITTLENUMS emitted is stored in *SIZEP. An error message is
973 returned, or NULL on OK.
975 Note that fp constants aren't represent in the normal way on the ARM.
976 In big endian mode, things are as expected. However, in little endian
977 mode fp constants are big-endian word-wise, and little-endian byte-wise
978 within the words. For example, (double) 1.1 in big endian mode is
979 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
980 the byte sequence 99 99 f1 3f 9a 99 99 99.
982 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
985 md_atof (int type
, char * litP
, int * sizeP
)
988 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1020 return _("Unrecognized or unsupported floating point constant");
1023 t
= atof_ieee (input_line_pointer
, type
, words
);
1025 input_line_pointer
= t
;
1026 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1028 if (target_big_endian
)
1030 for (i
= 0; i
< prec
; i
++)
1032 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1033 litP
+= sizeof (LITTLENUM_TYPE
);
1038 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1039 for (i
= prec
- 1; i
>= 0; i
--)
1041 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1042 litP
+= sizeof (LITTLENUM_TYPE
);
1045 /* For a 4 byte float the order of elements in `words' is 1 0.
1046 For an 8 byte float the order is 1 0 3 2. */
1047 for (i
= 0; i
< prec
; i
+= 2)
1049 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1050 sizeof (LITTLENUM_TYPE
));
1051 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1052 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1053 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1060 /* We handle all bad expressions here, so that we can report the faulty
1061 instruction in the error message. */
1063 md_operand (expressionS
* exp
)
1065 if (in_my_get_expression
)
1066 exp
->X_op
= O_illegal
;
1069 /* Immediate values. */
1071 /* Generic immediate-value read function for use in directives.
1072 Accepts anything that 'expression' can fold to a constant.
1073 *val receives the number. */
1076 immediate_for_directive (int *val
)
1079 exp
.X_op
= O_illegal
;
1081 if (is_immediate_prefix (*input_line_pointer
))
1083 input_line_pointer
++;
1087 if (exp
.X_op
!= O_constant
)
1089 as_bad (_("expected #constant"));
1090 ignore_rest_of_line ();
1093 *val
= exp
.X_add_number
;
1098 /* Register parsing. */
1100 /* Generic register parser. CCP points to what should be the
1101 beginning of a register name. If it is indeed a valid register
1102 name, advance CCP over it and return the reg_entry structure;
1103 otherwise return NULL. Does not issue diagnostics. */
1105 static struct reg_entry
*
1106 arm_reg_parse_multi (char **ccp
)
1110 struct reg_entry
*reg
;
1112 #ifdef REGISTER_PREFIX
1113 if (*start
!= REGISTER_PREFIX
)
1117 #ifdef OPTIONAL_REGISTER_PREFIX
1118 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1123 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1128 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1130 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1140 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1141 enum arm_reg_type type
)
1143 /* Alternative syntaxes are accepted for a few register classes. */
1150 /* Generic coprocessor register names are allowed for these. */
1151 if (reg
&& reg
->type
== REG_TYPE_CN
)
1156 /* For backward compatibility, a bare number is valid here. */
1158 unsigned long processor
= strtoul (start
, ccp
, 10);
1159 if (*ccp
!= start
&& processor
<= 15)
1163 case REG_TYPE_MMXWC
:
1164 /* WC includes WCG. ??? I'm not sure this is true for all
1165 instructions that take WC registers. */
1166 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1177 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1178 return value is the register number or FAIL. */
1181 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1184 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1187 /* Do not allow a scalar (reg+index) to parse as a register. */
1188 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1191 if (reg
&& reg
->type
== type
)
1194 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1201 /* Parse a Neon type specifier. *STR should point at the leading '.'
1202 character. Does no verification at this stage that the type fits the opcode
1209 Can all be legally parsed by this function.
1211 Fills in neon_type struct pointer with parsed information, and updates STR
1212 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1213 type, FAIL if not. */
1216 parse_neon_type (struct neon_type
*type
, char **str
)
1223 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1225 enum neon_el_type thistype
= NT_untyped
;
1226 unsigned thissize
= -1u;
1233 /* Just a size without an explicit type. */
1237 switch (TOLOWER (*ptr
))
1239 case 'i': thistype
= NT_integer
; break;
1240 case 'f': thistype
= NT_float
; break;
1241 case 'p': thistype
= NT_poly
; break;
1242 case 's': thistype
= NT_signed
; break;
1243 case 'u': thistype
= NT_unsigned
; break;
1245 thistype
= NT_float
;
1250 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1256 /* .f is an abbreviation for .f32. */
1257 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1262 thissize
= strtoul (ptr
, &ptr
, 10);
1264 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1267 as_bad (_("bad size %d in type specifier"), thissize
);
1275 type
->el
[type
->elems
].type
= thistype
;
1276 type
->el
[type
->elems
].size
= thissize
;
1281 /* Empty/missing type is not a successful parse. */
1282 if (type
->elems
== 0)
1290 /* Errors may be set multiple times during parsing or bit encoding
1291 (particularly in the Neon bits), but usually the earliest error which is set
1292 will be the most meaningful. Avoid overwriting it with later (cascading)
1293 errors by calling this function. */
1296 first_error (const char *err
)
1302 /* Parse a single type, e.g. ".s32", leading period included. */
1304 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1307 struct neon_type optype
;
1311 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1313 if (optype
.elems
== 1)
1314 *vectype
= optype
.el
[0];
1317 first_error (_("only one type should be specified for operand"));
1323 first_error (_("vector type expected"));
1335 /* Special meanings for indices (which have a range of 0-7), which will fit into
1338 #define NEON_ALL_LANES 15
1339 #define NEON_INTERLEAVE_LANES 14
1341 /* Parse either a register or a scalar, with an optional type. Return the
1342 register number, and optionally fill in the actual type of the register
1343 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1344 type/index information in *TYPEINFO. */
1347 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1348 enum arm_reg_type
*rtype
,
1349 struct neon_typed_alias
*typeinfo
)
1352 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1353 struct neon_typed_alias atype
;
1354 struct neon_type_el parsetype
;
1358 atype
.eltype
.type
= NT_invtype
;
1359 atype
.eltype
.size
= -1;
1361 /* Try alternate syntax for some types of register. Note these are mutually
1362 exclusive with the Neon syntax extensions. */
1365 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1373 /* Undo polymorphism when a set of register types may be accepted. */
1374 if ((type
== REG_TYPE_NDQ
1375 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1376 || (type
== REG_TYPE_VFSD
1377 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1378 || (type
== REG_TYPE_NSDQ
1379 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1380 || reg
->type
== REG_TYPE_NQ
))
1381 || (type
== REG_TYPE_MMXWC
1382 && (reg
->type
== REG_TYPE_MMXWCG
)))
1383 type
= (enum arm_reg_type
) reg
->type
;
1385 if (type
!= reg
->type
)
1391 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1393 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1395 first_error (_("can't redefine type for operand"));
1398 atype
.defined
|= NTA_HASTYPE
;
1399 atype
.eltype
= parsetype
;
1402 if (skip_past_char (&str
, '[') == SUCCESS
)
1404 if (type
!= REG_TYPE_VFD
)
1406 first_error (_("only D registers may be indexed"));
1410 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1412 first_error (_("can't change index for operand"));
1416 atype
.defined
|= NTA_HASINDEX
;
1418 if (skip_past_char (&str
, ']') == SUCCESS
)
1419 atype
.index
= NEON_ALL_LANES
;
1424 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1426 if (exp
.X_op
!= O_constant
)
1428 first_error (_("constant expression required"));
1432 if (skip_past_char (&str
, ']') == FAIL
)
1435 atype
.index
= exp
.X_add_number
;
1450 /* Like arm_reg_parse, but allow allow the following extra features:
1451 - If RTYPE is non-zero, return the (possibly restricted) type of the
1452 register (e.g. Neon double or quad reg when either has been requested).
1453 - If this is a Neon vector type with additional type information, fill
1454 in the struct pointed to by VECTYPE (if non-NULL).
1455 This function will fault on encountering a scalar. */
1458 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1459 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1461 struct neon_typed_alias atype
;
1463 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1468 /* Do not allow a scalar (reg+index) to parse as a register. */
1469 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1471 first_error (_("register operand expected, but got scalar"));
1476 *vectype
= atype
.eltype
;
1483 #define NEON_SCALAR_REG(X) ((X) >> 4)
1484 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1486 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1487 have enough information to be able to do a good job bounds-checking. So, we
1488 just do easy checks here, and do further checks later. */
1491 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1495 struct neon_typed_alias atype
;
1497 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1499 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1502 if (atype
.index
== NEON_ALL_LANES
)
1504 first_error (_("scalar must have an index"));
1507 else if (atype
.index
>= 64 / elsize
)
1509 first_error (_("scalar index out of range"));
1514 *type
= atype
.eltype
;
1518 return reg
* 16 + atype
.index
;
1521 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1524 parse_reg_list (char ** strp
)
1526 char * str
= * strp
;
1530 /* We come back here if we get ranges concatenated by '+' or '|'. */
1545 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1547 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1557 first_error (_("bad range in register list"));
1561 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1563 if (range
& (1 << i
))
1565 (_("Warning: duplicated register (r%d) in register list"),
1573 if (range
& (1 << reg
))
1574 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1576 else if (reg
<= cur_reg
)
1577 as_tsktsk (_("Warning: register range not in ascending order"));
1582 while (skip_past_comma (&str
) != FAIL
1583 || (in_range
= 1, *str
++ == '-'));
1588 first_error (_("missing `}'"));
1596 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1599 if (exp
.X_op
== O_constant
)
1601 if (exp
.X_add_number
1602 != (exp
.X_add_number
& 0x0000ffff))
1604 inst
.error
= _("invalid register mask");
1608 if ((range
& exp
.X_add_number
) != 0)
1610 int regno
= range
& exp
.X_add_number
;
1613 regno
= (1 << regno
) - 1;
1615 (_("Warning: duplicated register (r%d) in register list"),
1619 range
|= exp
.X_add_number
;
1623 if (inst
.reloc
.type
!= 0)
1625 inst
.error
= _("expression too complex");
1629 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1630 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1631 inst
.reloc
.pc_rel
= 0;
1635 if (*str
== '|' || *str
== '+')
1641 while (another_range
);
1647 /* Types of registers in a list. */
1656 /* Parse a VFP register list. If the string is invalid return FAIL.
1657 Otherwise return the number of registers, and set PBASE to the first
1658 register. Parses registers of type ETYPE.
1659 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1660 - Q registers can be used to specify pairs of D registers
1661 - { } can be omitted from around a singleton register list
1662 FIXME: This is not implemented, as it would require backtracking in
1665 This could be done (the meaning isn't really ambiguous), but doesn't
1666 fit in well with the current parsing framework.
1667 - 32 D registers may be used (also true for VFPv3).
1668 FIXME: Types are ignored in these register lists, which is probably a
1672 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1677 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1681 unsigned long mask
= 0;
1686 inst
.error
= _("expecting {");
1695 regtype
= REG_TYPE_VFS
;
1700 regtype
= REG_TYPE_VFD
;
1703 case REGLIST_NEON_D
:
1704 regtype
= REG_TYPE_NDQ
;
1708 if (etype
!= REGLIST_VFP_S
)
1710 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1711 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1715 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1718 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1725 base_reg
= max_regs
;
1729 int setmask
= 1, addregs
= 1;
1731 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1733 if (new_base
== FAIL
)
1735 first_error (_(reg_expected_msgs
[regtype
]));
1739 if (new_base
>= max_regs
)
1741 first_error (_("register out of range in list"));
1745 /* Note: a value of 2 * n is returned for the register Q<n>. */
1746 if (regtype
== REG_TYPE_NQ
)
1752 if (new_base
< base_reg
)
1753 base_reg
= new_base
;
1755 if (mask
& (setmask
<< new_base
))
1757 first_error (_("invalid register list"));
1761 if ((mask
>> new_base
) != 0 && ! warned
)
1763 as_tsktsk (_("register list not in ascending order"));
1767 mask
|= setmask
<< new_base
;
1770 if (*str
== '-') /* We have the start of a range expression */
1776 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1779 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1783 if (high_range
>= max_regs
)
1785 first_error (_("register out of range in list"));
1789 if (regtype
== REG_TYPE_NQ
)
1790 high_range
= high_range
+ 1;
1792 if (high_range
<= new_base
)
1794 inst
.error
= _("register range not in ascending order");
1798 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1800 if (mask
& (setmask
<< new_base
))
1802 inst
.error
= _("invalid register list");
1806 mask
|= setmask
<< new_base
;
1811 while (skip_past_comma (&str
) != FAIL
);
1815 /* Sanity check -- should have raised a parse error above. */
1816 if (count
== 0 || count
> max_regs
)
1821 /* Final test -- the registers must be consecutive. */
1823 for (i
= 0; i
< count
; i
++)
1825 if ((mask
& (1u << i
)) == 0)
1827 inst
.error
= _("non-contiguous register range");
1837 /* True if two alias types are the same. */
1840 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1848 if (a
->defined
!= b
->defined
)
1851 if ((a
->defined
& NTA_HASTYPE
) != 0
1852 && (a
->eltype
.type
!= b
->eltype
.type
1853 || a
->eltype
.size
!= b
->eltype
.size
))
1856 if ((a
->defined
& NTA_HASINDEX
) != 0
1857 && (a
->index
!= b
->index
))
1863 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1864 The base register is put in *PBASE.
1865 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1867 The register stride (minus one) is put in bit 4 of the return value.
1868 Bits [6:5] encode the list length (minus one).
1869 The type of the list elements is put in *ELTYPE, if non-NULL. */
1871 #define NEON_LANE(X) ((X) & 0xf)
1872 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1873 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1876 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1877 struct neon_type_el
*eltype
)
1884 int leading_brace
= 0;
1885 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1886 const char *const incr_error
= _("register stride must be 1 or 2");
1887 const char *const type_error
= _("mismatched element/structure types in list");
1888 struct neon_typed_alias firsttype
;
1890 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1895 struct neon_typed_alias atype
;
1896 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1900 first_error (_(reg_expected_msgs
[rtype
]));
1907 if (rtype
== REG_TYPE_NQ
)
1913 else if (reg_incr
== -1)
1915 reg_incr
= getreg
- base_reg
;
1916 if (reg_incr
< 1 || reg_incr
> 2)
1918 first_error (_(incr_error
));
1922 else if (getreg
!= base_reg
+ reg_incr
* count
)
1924 first_error (_(incr_error
));
1928 if (! neon_alias_types_same (&atype
, &firsttype
))
1930 first_error (_(type_error
));
1934 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1938 struct neon_typed_alias htype
;
1939 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1941 lane
= NEON_INTERLEAVE_LANES
;
1942 else if (lane
!= NEON_INTERLEAVE_LANES
)
1944 first_error (_(type_error
));
1949 else if (reg_incr
!= 1)
1951 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1955 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1958 first_error (_(reg_expected_msgs
[rtype
]));
1961 if (! neon_alias_types_same (&htype
, &firsttype
))
1963 first_error (_(type_error
));
1966 count
+= hireg
+ dregs
- getreg
;
1970 /* If we're using Q registers, we can't use [] or [n] syntax. */
1971 if (rtype
== REG_TYPE_NQ
)
1977 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1981 else if (lane
!= atype
.index
)
1983 first_error (_(type_error
));
1987 else if (lane
== -1)
1988 lane
= NEON_INTERLEAVE_LANES
;
1989 else if (lane
!= NEON_INTERLEAVE_LANES
)
1991 first_error (_(type_error
));
1996 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1998 /* No lane set by [x]. We must be interleaving structures. */
2000 lane
= NEON_INTERLEAVE_LANES
;
2003 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2004 || (count
> 1 && reg_incr
== -1))
2006 first_error (_("error parsing element/structure list"));
2010 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2012 first_error (_("expected }"));
2020 *eltype
= firsttype
.eltype
;
2025 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2028 /* Parse an explicit relocation suffix on an expression. This is
2029 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2030 arm_reloc_hsh contains no entries, so this function can only
2031 succeed if there is no () after the word. Returns -1 on error,
2032 BFD_RELOC_UNUSED if there wasn't any suffix. */
2034 parse_reloc (char **str
)
2036 struct reloc_entry
*r
;
2040 return BFD_RELOC_UNUSED
;
2045 while (*q
&& *q
!= ')' && *q
!= ',')
2050 if ((r
= (struct reloc_entry
*)
2051 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2058 /* Directives: register aliases. */
2060 static struct reg_entry
*
2061 insert_reg_alias (char *str
, int number
, int type
)
2063 struct reg_entry
*new_reg
;
2066 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2068 if (new_reg
->builtin
)
2069 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2071 /* Only warn about a redefinition if it's not defined as the
2073 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2074 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2079 name
= xstrdup (str
);
2080 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2082 new_reg
->name
= name
;
2083 new_reg
->number
= number
;
2084 new_reg
->type
= type
;
2085 new_reg
->builtin
= FALSE
;
2086 new_reg
->neon
= NULL
;
2088 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2095 insert_neon_reg_alias (char *str
, int number
, int type
,
2096 struct neon_typed_alias
*atype
)
2098 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2102 first_error (_("attempt to redefine typed alias"));
2108 reg
->neon
= (struct neon_typed_alias
*)
2109 xmalloc (sizeof (struct neon_typed_alias
));
2110 *reg
->neon
= *atype
;
2114 /* Look for the .req directive. This is of the form:
2116 new_register_name .req existing_register_name
2118 If we find one, or if it looks sufficiently like one that we want to
2119 handle any error here, return TRUE. Otherwise return FALSE. */
2122 create_register_alias (char * newname
, char *p
)
2124 struct reg_entry
*old
;
2125 char *oldname
, *nbuf
;
2128 /* The input scrubber ensures that whitespace after the mnemonic is
2129 collapsed to single spaces. */
2131 if (strncmp (oldname
, " .req ", 6) != 0)
2135 if (*oldname
== '\0')
2138 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2141 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2145 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2146 the desired alias name, and p points to its end. If not, then
2147 the desired alias name is in the global original_case_string. */
2148 #ifdef TC_CASE_SENSITIVE
2151 newname
= original_case_string
;
2152 nlen
= strlen (newname
);
2155 nbuf
= (char *) alloca (nlen
+ 1);
2156 memcpy (nbuf
, newname
, nlen
);
2159 /* Create aliases under the new name as stated; an all-lowercase
2160 version of the new name; and an all-uppercase version of the new
2162 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2164 for (p
= nbuf
; *p
; p
++)
2167 if (strncmp (nbuf
, newname
, nlen
))
2169 /* If this attempt to create an additional alias fails, do not bother
2170 trying to create the all-lower case alias. We will fail and issue
2171 a second, duplicate error message. This situation arises when the
2172 programmer does something like:
2175 The second .req creates the "Foo" alias but then fails to create
2176 the artificial FOO alias because it has already been created by the
2178 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2182 for (p
= nbuf
; *p
; p
++)
2185 if (strncmp (nbuf
, newname
, nlen
))
2186 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2192 /* Create a Neon typed/indexed register alias using directives, e.g.:
2197 These typed registers can be used instead of the types specified after the
2198 Neon mnemonic, so long as all operands given have types. Types can also be
2199 specified directly, e.g.:
2200 vadd d0.s32, d1.s32, d2.s32 */
2203 create_neon_reg_alias (char *newname
, char *p
)
2205 enum arm_reg_type basetype
;
2206 struct reg_entry
*basereg
;
2207 struct reg_entry mybasereg
;
2208 struct neon_type ntype
;
2209 struct neon_typed_alias typeinfo
;
2210 char *namebuf
, *nameend
;
2213 typeinfo
.defined
= 0;
2214 typeinfo
.eltype
.type
= NT_invtype
;
2215 typeinfo
.eltype
.size
= -1;
2216 typeinfo
.index
= -1;
2220 if (strncmp (p
, " .dn ", 5) == 0)
2221 basetype
= REG_TYPE_VFD
;
2222 else if (strncmp (p
, " .qn ", 5) == 0)
2223 basetype
= REG_TYPE_NQ
;
2232 basereg
= arm_reg_parse_multi (&p
);
2234 if (basereg
&& basereg
->type
!= basetype
)
2236 as_bad (_("bad type for register"));
2240 if (basereg
== NULL
)
2243 /* Try parsing as an integer. */
2244 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2245 if (exp
.X_op
!= O_constant
)
2247 as_bad (_("expression must be constant"));
2250 basereg
= &mybasereg
;
2251 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2257 typeinfo
= *basereg
->neon
;
2259 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2261 /* We got a type. */
2262 if (typeinfo
.defined
& NTA_HASTYPE
)
2264 as_bad (_("can't redefine the type of a register alias"));
2268 typeinfo
.defined
|= NTA_HASTYPE
;
2269 if (ntype
.elems
!= 1)
2271 as_bad (_("you must specify a single type only"));
2274 typeinfo
.eltype
= ntype
.el
[0];
2277 if (skip_past_char (&p
, '[') == SUCCESS
)
2280 /* We got a scalar index. */
2282 if (typeinfo
.defined
& NTA_HASINDEX
)
2284 as_bad (_("can't redefine the index of a scalar alias"));
2288 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2290 if (exp
.X_op
!= O_constant
)
2292 as_bad (_("scalar index must be constant"));
2296 typeinfo
.defined
|= NTA_HASINDEX
;
2297 typeinfo
.index
= exp
.X_add_number
;
2299 if (skip_past_char (&p
, ']') == FAIL
)
2301 as_bad (_("expecting ]"));
2306 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2307 the desired alias name, and p points to its end. If not, then
2308 the desired alias name is in the global original_case_string. */
2309 #ifdef TC_CASE_SENSITIVE
2310 namelen
= nameend
- newname
;
2312 newname
= original_case_string
;
2313 namelen
= strlen (newname
);
2316 namebuf
= (char *) alloca (namelen
+ 1);
2317 strncpy (namebuf
, newname
, namelen
);
2318 namebuf
[namelen
] = '\0';
2320 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2321 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2323 /* Insert name in all uppercase. */
2324 for (p
= namebuf
; *p
; p
++)
2327 if (strncmp (namebuf
, newname
, namelen
))
2328 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2329 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2331 /* Insert name in all lowercase. */
2332 for (p
= namebuf
; *p
; p
++)
2335 if (strncmp (namebuf
, newname
, namelen
))
2336 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2337 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2342 /* Should never be called, as .req goes between the alias and the
2343 register name, not at the beginning of the line. */
2346 s_req (int a ATTRIBUTE_UNUSED
)
2348 as_bad (_("invalid syntax for .req directive"));
2352 s_dn (int a ATTRIBUTE_UNUSED
)
2354 as_bad (_("invalid syntax for .dn directive"));
2358 s_qn (int a ATTRIBUTE_UNUSED
)
2360 as_bad (_("invalid syntax for .qn directive"));
2363 /* The .unreq directive deletes an alias which was previously defined
2364 by .req. For example:
2370 s_unreq (int a ATTRIBUTE_UNUSED
)
2375 name
= input_line_pointer
;
2377 while (*input_line_pointer
!= 0
2378 && *input_line_pointer
!= ' '
2379 && *input_line_pointer
!= '\n')
2380 ++input_line_pointer
;
2382 saved_char
= *input_line_pointer
;
2383 *input_line_pointer
= 0;
2386 as_bad (_("invalid syntax for .unreq directive"));
2389 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2393 as_bad (_("unknown register alias '%s'"), name
);
2394 else if (reg
->builtin
)
2395 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2402 hash_delete (arm_reg_hsh
, name
, FALSE
);
2403 free ((char *) reg
->name
);
2408 /* Also locate the all upper case and all lower case versions.
2409 Do not complain if we cannot find one or the other as it
2410 was probably deleted above. */
2412 nbuf
= strdup (name
);
2413 for (p
= nbuf
; *p
; p
++)
2415 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2418 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2419 free ((char *) reg
->name
);
2425 for (p
= nbuf
; *p
; p
++)
2427 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2430 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2431 free ((char *) reg
->name
);
2441 *input_line_pointer
= saved_char
;
2442 demand_empty_rest_of_line ();
2445 /* Directives: Instruction set selection. */
2448 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2449 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2450 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2451 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2453 /* Create a new mapping symbol for the transition to STATE. */
2456 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2459 const char * symname
;
2466 type
= BSF_NO_FLAGS
;
2470 type
= BSF_NO_FLAGS
;
2474 type
= BSF_NO_FLAGS
;
2480 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2481 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2486 THUMB_SET_FUNC (symbolP
, 0);
2487 ARM_SET_THUMB (symbolP
, 0);
2488 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2492 THUMB_SET_FUNC (symbolP
, 1);
2493 ARM_SET_THUMB (symbolP
, 1);
2494 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2502 /* Save the mapping symbols for future reference. Also check that
2503 we do not place two mapping symbols at the same offset within a
2504 frag. We'll handle overlap between frags in
2505 check_mapping_symbols.
2507 If .fill or other data filling directive generates zero sized data,
2508 the mapping symbol for the following code will have the same value
2509 as the one generated for the data filling directive. In this case,
2510 we replace the old symbol with the new one at the same address. */
2513 if (frag
->tc_frag_data
.first_map
!= NULL
)
2515 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2516 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2518 frag
->tc_frag_data
.first_map
= symbolP
;
2520 if (frag
->tc_frag_data
.last_map
!= NULL
)
2522 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2523 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2524 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2526 frag
->tc_frag_data
.last_map
= symbolP
;
2529 /* We must sometimes convert a region marked as code to data during
2530 code alignment, if an odd number of bytes have to be padded. The
2531 code mapping symbol is pushed to an aligned address. */
2534 insert_data_mapping_symbol (enum mstate state
,
2535 valueT value
, fragS
*frag
, offsetT bytes
)
2537 /* If there was already a mapping symbol, remove it. */
2538 if (frag
->tc_frag_data
.last_map
!= NULL
2539 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2541 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2545 know (frag
->tc_frag_data
.first_map
== symp
);
2546 frag
->tc_frag_data
.first_map
= NULL
;
2548 frag
->tc_frag_data
.last_map
= NULL
;
2549 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2552 make_mapping_symbol (MAP_DATA
, value
, frag
);
2553 make_mapping_symbol (state
, value
+ bytes
, frag
);
2556 static void mapping_state_2 (enum mstate state
, int max_chars
);
2558 /* Set the mapping state to STATE. Only call this when about to
2559 emit some STATE bytes to the file. */
2562 mapping_state (enum mstate state
)
2564 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2566 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2568 if (mapstate
== state
)
2569 /* The mapping symbol has already been emitted.
2570 There is nothing else to do. */
2572 else if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2573 /* This case will be evaluated later in the next else. */
2575 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2576 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2578 /* Only add the symbol if the offset is > 0:
2579 if we're at the first frag, check it's size > 0;
2580 if we're not at the first frag, then for sure
2581 the offset is > 0. */
2582 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2583 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2586 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2589 mapping_state_2 (state
, 0);
2593 /* Same as mapping_state, but MAX_CHARS bytes have already been
2594 allocated. Put the mapping symbol that far back. */
2597 mapping_state_2 (enum mstate state
, int max_chars
)
2599 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2601 if (!SEG_NORMAL (now_seg
))
2604 if (mapstate
== state
)
2605 /* The mapping symbol has already been emitted.
2606 There is nothing else to do. */
2609 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2610 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2613 #define mapping_state(x) ((void)0)
2614 #define mapping_state_2(x, y) ((void)0)
2617 /* Find the real, Thumb encoded start of a Thumb function. */
2621 find_real_start (symbolS
* symbolP
)
2624 const char * name
= S_GET_NAME (symbolP
);
2625 symbolS
* new_target
;
2627 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2628 #define STUB_NAME ".real_start_of"
2633 /* The compiler may generate BL instructions to local labels because
2634 it needs to perform a branch to a far away location. These labels
2635 do not have a corresponding ".real_start_of" label. We check
2636 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2637 the ".real_start_of" convention for nonlocal branches. */
2638 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2641 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2642 new_target
= symbol_find (real_start
);
2644 if (new_target
== NULL
)
2646 as_warn (_("Failed to find real start of function: %s\n"), name
);
2647 new_target
= symbolP
;
2655 opcode_select (int width
)
2662 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2663 as_bad (_("selected processor does not support THUMB opcodes"));
2666 /* No need to force the alignment, since we will have been
2667 coming from ARM mode, which is word-aligned. */
2668 record_alignment (now_seg
, 1);
2675 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2676 as_bad (_("selected processor does not support ARM opcodes"));
2681 frag_align (2, 0, 0);
2683 record_alignment (now_seg
, 1);
2688 as_bad (_("invalid instruction size selected (%d)"), width
);
2693 s_arm (int ignore ATTRIBUTE_UNUSED
)
2696 demand_empty_rest_of_line ();
2700 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2703 demand_empty_rest_of_line ();
2707 s_code (int unused ATTRIBUTE_UNUSED
)
2711 temp
= get_absolute_expression ();
2716 opcode_select (temp
);
2720 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2725 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2727 /* If we are not already in thumb mode go into it, EVEN if
2728 the target processor does not support thumb instructions.
2729 This is used by gcc/config/arm/lib1funcs.asm for example
2730 to compile interworking support functions even if the
2731 target processor should not support interworking. */
2735 record_alignment (now_seg
, 1);
2738 demand_empty_rest_of_line ();
2742 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2746 /* The following label is the name/address of the start of a Thumb function.
2747 We need to know this for the interworking support. */
2748 label_is_thumb_function_name
= TRUE
;
2751 /* Perform a .set directive, but also mark the alias as
2752 being a thumb function. */
2755 s_thumb_set (int equiv
)
2757 /* XXX the following is a duplicate of the code for s_set() in read.c
2758 We cannot just call that code as we need to get at the symbol that
2765 /* Especial apologies for the random logic:
2766 This just grew, and could be parsed much more simply!
2768 name
= input_line_pointer
;
2769 delim
= get_symbol_end ();
2770 end_name
= input_line_pointer
;
2773 if (*input_line_pointer
!= ',')
2776 as_bad (_("expected comma after name \"%s\""), name
);
2778 ignore_rest_of_line ();
2782 input_line_pointer
++;
2785 if (name
[0] == '.' && name
[1] == '\0')
2787 /* XXX - this should not happen to .thumb_set. */
2791 if ((symbolP
= symbol_find (name
)) == NULL
2792 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2795 /* When doing symbol listings, play games with dummy fragments living
2796 outside the normal fragment chain to record the file and line info
2798 if (listing
& LISTING_SYMBOLS
)
2800 extern struct list_info_struct
* listing_tail
;
2801 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2803 memset (dummy_frag
, 0, sizeof (fragS
));
2804 dummy_frag
->fr_type
= rs_fill
;
2805 dummy_frag
->line
= listing_tail
;
2806 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2807 dummy_frag
->fr_symbol
= symbolP
;
2811 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2814 /* "set" symbols are local unless otherwise specified. */
2815 SF_SET_LOCAL (symbolP
);
2816 #endif /* OBJ_COFF */
2817 } /* Make a new symbol. */
2819 symbol_table_insert (symbolP
);
2824 && S_IS_DEFINED (symbolP
)
2825 && S_GET_SEGMENT (symbolP
) != reg_section
)
2826 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2828 pseudo_set (symbolP
);
2830 demand_empty_rest_of_line ();
2832 /* XXX Now we come to the Thumb specific bit of code. */
2834 THUMB_SET_FUNC (symbolP
, 1);
2835 ARM_SET_THUMB (symbolP
, 1);
2836 #if defined OBJ_ELF || defined OBJ_COFF
2837 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2841 /* Directives: Mode selection. */
2843 /* .syntax [unified|divided] - choose the new unified syntax
2844 (same for Arm and Thumb encoding, modulo slight differences in what
2845 can be represented) or the old divergent syntax for each mode. */
2847 s_syntax (int unused ATTRIBUTE_UNUSED
)
2851 name
= input_line_pointer
;
2852 delim
= get_symbol_end ();
2854 if (!strcasecmp (name
, "unified"))
2855 unified_syntax
= TRUE
;
2856 else if (!strcasecmp (name
, "divided"))
2857 unified_syntax
= FALSE
;
2860 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2863 *input_line_pointer
= delim
;
2864 demand_empty_rest_of_line ();
2867 /* Directives: sectioning and alignment. */
2869 /* Same as s_align_ptwo but align 0 => align 2. */
2872 s_align (int unused ATTRIBUTE_UNUSED
)
2877 long max_alignment
= 15;
2879 temp
= get_absolute_expression ();
2880 if (temp
> max_alignment
)
2881 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2884 as_bad (_("alignment negative. 0 assumed."));
2888 if (*input_line_pointer
== ',')
2890 input_line_pointer
++;
2891 temp_fill
= get_absolute_expression ();
2903 /* Only make a frag if we HAVE to. */
2904 if (temp
&& !need_pass_2
)
2906 if (!fill_p
&& subseg_text_p (now_seg
))
2907 frag_align_code (temp
, 0);
2909 frag_align (temp
, (int) temp_fill
, 0);
2911 demand_empty_rest_of_line ();
2913 record_alignment (now_seg
, temp
);
2917 s_bss (int ignore ATTRIBUTE_UNUSED
)
2919 /* We don't support putting frags in the BSS segment, we fake it by
2920 marking in_bss, then looking at s_skip for clues. */
2921 subseg_set (bss_section
, 0);
2922 demand_empty_rest_of_line ();
2924 #ifdef md_elf_section_change_hook
2925 md_elf_section_change_hook ();
2930 s_even (int ignore ATTRIBUTE_UNUSED
)
2932 /* Never make frag if expect extra pass. */
2934 frag_align (1, 0, 0);
2936 record_alignment (now_seg
, 1);
2938 demand_empty_rest_of_line ();
2941 /* Directives: Literal pools. */
2943 static literal_pool
*
2944 find_literal_pool (void)
2946 literal_pool
* pool
;
2948 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2950 if (pool
->section
== now_seg
2951 && pool
->sub_section
== now_subseg
)
2958 static literal_pool
*
2959 find_or_make_literal_pool (void)
2961 /* Next literal pool ID number. */
2962 static unsigned int latest_pool_num
= 1;
2963 literal_pool
* pool
;
2965 pool
= find_literal_pool ();
2969 /* Create a new pool. */
2970 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
2974 pool
->next_free_entry
= 0;
2975 pool
->section
= now_seg
;
2976 pool
->sub_section
= now_subseg
;
2977 pool
->next
= list_of_pools
;
2978 pool
->symbol
= NULL
;
2980 /* Add it to the list. */
2981 list_of_pools
= pool
;
2984 /* New pools, and emptied pools, will have a NULL symbol. */
2985 if (pool
->symbol
== NULL
)
2987 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2988 (valueT
) 0, &zero_address_frag
);
2989 pool
->id
= latest_pool_num
++;
2996 /* Add the literal in the global 'inst'
2997 structure to the relevant literal pool. */
3000 add_to_lit_pool (void)
3002 literal_pool
* pool
;
3005 pool
= find_or_make_literal_pool ();
3007 /* Check if this literal value is already in the pool. */
3008 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3010 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3011 && (inst
.reloc
.exp
.X_op
== O_constant
)
3012 && (pool
->literals
[entry
].X_add_number
3013 == inst
.reloc
.exp
.X_add_number
)
3014 && (pool
->literals
[entry
].X_unsigned
3015 == inst
.reloc
.exp
.X_unsigned
))
3018 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3019 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3020 && (pool
->literals
[entry
].X_add_number
3021 == inst
.reloc
.exp
.X_add_number
)
3022 && (pool
->literals
[entry
].X_add_symbol
3023 == inst
.reloc
.exp
.X_add_symbol
)
3024 && (pool
->literals
[entry
].X_op_symbol
3025 == inst
.reloc
.exp
.X_op_symbol
))
3029 /* Do we need to create a new entry? */
3030 if (entry
== pool
->next_free_entry
)
3032 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3034 inst
.error
= _("literal pool overflow");
3038 pool
->literals
[entry
] = inst
.reloc
.exp
;
3039 pool
->next_free_entry
+= 1;
3042 inst
.reloc
.exp
.X_op
= O_symbol
;
3043 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3044 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3049 /* Can't use symbol_new here, so have to create a symbol and then at
3050 a later date assign it a value. Thats what these functions do. */
3053 symbol_locate (symbolS
* symbolP
,
3054 const char * name
, /* It is copied, the caller can modify. */
3055 segT segment
, /* Segment identifier (SEG_<something>). */
3056 valueT valu
, /* Symbol value. */
3057 fragS
* frag
) /* Associated fragment. */
3059 unsigned int name_length
;
3060 char * preserved_copy_of_name
;
3062 name_length
= strlen (name
) + 1; /* +1 for \0. */
3063 obstack_grow (¬es
, name
, name_length
);
3064 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3066 #ifdef tc_canonicalize_symbol_name
3067 preserved_copy_of_name
=
3068 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3071 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3073 S_SET_SEGMENT (symbolP
, segment
);
3074 S_SET_VALUE (symbolP
, valu
);
3075 symbol_clear_list_pointers (symbolP
);
3077 symbol_set_frag (symbolP
, frag
);
3079 /* Link to end of symbol chain. */
3081 extern int symbol_table_frozen
;
3083 if (symbol_table_frozen
)
3087 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3089 obj_symbol_new_hook (symbolP
);
3091 #ifdef tc_symbol_new_hook
3092 tc_symbol_new_hook (symbolP
);
3096 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3097 #endif /* DEBUG_SYMS */
3102 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3105 literal_pool
* pool
;
3108 pool
= find_literal_pool ();
3110 || pool
->symbol
== NULL
3111 || pool
->next_free_entry
== 0)
3114 mapping_state (MAP_DATA
);
3116 /* Align pool as you have word accesses.
3117 Only make a frag if we have to. */
3119 frag_align (2, 0, 0);
3121 record_alignment (now_seg
, 2);
3123 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3125 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3126 (valueT
) frag_now_fix (), frag_now
);
3127 symbol_table_insert (pool
->symbol
);
3129 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3131 #if defined OBJ_COFF || defined OBJ_ELF
3132 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3135 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3136 /* First output the expression in the instruction to the pool. */
3137 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3139 /* Mark the pool as empty. */
3140 pool
->next_free_entry
= 0;
3141 pool
->symbol
= NULL
;
3145 /* Forward declarations for functions below, in the MD interface
3147 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3148 static valueT
create_unwind_entry (int);
3149 static void start_unwind_section (const segT
, int);
3150 static void add_unwind_opcode (valueT
, int);
3151 static void flush_pending_unwind (void);
3153 /* Directives: Data. */
3156 s_arm_elf_cons (int nbytes
)
3160 #ifdef md_flush_pending_output
3161 md_flush_pending_output ();
3164 if (is_it_end_of_statement ())
3166 demand_empty_rest_of_line ();
3170 #ifdef md_cons_align
3171 md_cons_align (nbytes
);
3174 mapping_state (MAP_DATA
);
3178 char *base
= input_line_pointer
;
3182 if (exp
.X_op
!= O_symbol
)
3183 emit_expr (&exp
, (unsigned int) nbytes
);
3186 char *before_reloc
= input_line_pointer
;
3187 reloc
= parse_reloc (&input_line_pointer
);
3190 as_bad (_("unrecognized relocation suffix"));
3191 ignore_rest_of_line ();
3194 else if (reloc
== BFD_RELOC_UNUSED
)
3195 emit_expr (&exp
, (unsigned int) nbytes
);
3198 reloc_howto_type
*howto
= (reloc_howto_type
*)
3199 bfd_reloc_type_lookup (stdoutput
,
3200 (bfd_reloc_code_real_type
) reloc
);
3201 int size
= bfd_get_reloc_size (howto
);
3203 if (reloc
== BFD_RELOC_ARM_PLT32
)
3205 as_bad (_("(plt) is only valid on branch targets"));
3206 reloc
= BFD_RELOC_UNUSED
;
3211 as_bad (_("%s relocations do not fit in %d bytes"),
3212 howto
->name
, nbytes
);
3215 /* We've parsed an expression stopping at O_symbol.
3216 But there may be more expression left now that we
3217 have parsed the relocation marker. Parse it again.
3218 XXX Surely there is a cleaner way to do this. */
3219 char *p
= input_line_pointer
;
3221 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3222 memcpy (save_buf
, base
, input_line_pointer
- base
);
3223 memmove (base
+ (input_line_pointer
- before_reloc
),
3224 base
, before_reloc
- base
);
3226 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3228 memcpy (base
, save_buf
, p
- base
);
3230 offset
= nbytes
- size
;
3231 p
= frag_more ((int) nbytes
);
3232 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3233 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3238 while (*input_line_pointer
++ == ',');
3240 /* Put terminator back into stream. */
3241 input_line_pointer
--;
3242 demand_empty_rest_of_line ();
3245 /* Emit an expression containing a 32-bit thumb instruction.
3246 Implementation based on put_thumb32_insn. */
3249 emit_thumb32_expr (expressionS
* exp
)
3251 expressionS exp_high
= *exp
;
3253 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3254 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3255 exp
->X_add_number
&= 0xffff;
3256 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3259 /* Guess the instruction size based on the opcode. */
3262 thumb_insn_size (int opcode
)
3264 if ((unsigned int) opcode
< 0xe800u
)
3266 else if ((unsigned int) opcode
>= 0xe8000000u
)
3273 emit_insn (expressionS
*exp
, int nbytes
)
3277 if (exp
->X_op
== O_constant
)
3282 size
= thumb_insn_size (exp
->X_add_number
);
3286 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3288 as_bad (_(".inst.n operand too big. "\
3289 "Use .inst.w instead"));
3294 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3295 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3297 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3299 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3300 emit_thumb32_expr (exp
);
3302 emit_expr (exp
, (unsigned int) size
);
3304 it_fsm_post_encode ();
3308 as_bad (_("cannot determine Thumb instruction size. " \
3309 "Use .inst.n/.inst.w instead"));
3312 as_bad (_("constant expression required"));
3317 /* Like s_arm_elf_cons but do not use md_cons_align and
3318 set the mapping state to MAP_ARM/MAP_THUMB. */
3321 s_arm_elf_inst (int nbytes
)
3323 if (is_it_end_of_statement ())
3325 demand_empty_rest_of_line ();
3329 /* Calling mapping_state () here will not change ARM/THUMB,
3330 but will ensure not to be in DATA state. */
3333 mapping_state (MAP_THUMB
);
3338 as_bad (_("width suffixes are invalid in ARM mode"));
3339 ignore_rest_of_line ();
3345 mapping_state (MAP_ARM
);
3354 if (! emit_insn (& exp
, nbytes
))
3356 ignore_rest_of_line ();
3360 while (*input_line_pointer
++ == ',');
3362 /* Put terminator back into stream. */
3363 input_line_pointer
--;
3364 demand_empty_rest_of_line ();
3367 /* Parse a .rel31 directive. */
3370 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3377 if (*input_line_pointer
== '1')
3378 highbit
= 0x80000000;
3379 else if (*input_line_pointer
!= '0')
3380 as_bad (_("expected 0 or 1"));
3382 input_line_pointer
++;
3383 if (*input_line_pointer
!= ',')
3384 as_bad (_("missing comma"));
3385 input_line_pointer
++;
3387 #ifdef md_flush_pending_output
3388 md_flush_pending_output ();
3391 #ifdef md_cons_align
3395 mapping_state (MAP_DATA
);
3400 md_number_to_chars (p
, highbit
, 4);
3401 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3402 BFD_RELOC_ARM_PREL31
);
3404 demand_empty_rest_of_line ();
3407 /* Directives: AEABI stack-unwind tables. */
3409 /* Parse an unwind_fnstart directive. Simply records the current location. */
3412 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3414 demand_empty_rest_of_line ();
3415 if (unwind
.proc_start
)
3417 as_bad (_("duplicate .fnstart directive"));
3421 /* Mark the start of the function. */
3422 unwind
.proc_start
= expr_build_dot ();
3424 /* Reset the rest of the unwind info. */
3425 unwind
.opcode_count
= 0;
3426 unwind
.table_entry
= NULL
;
3427 unwind
.personality_routine
= NULL
;
3428 unwind
.personality_index
= -1;
3429 unwind
.frame_size
= 0;
3430 unwind
.fp_offset
= 0;
3431 unwind
.fp_reg
= REG_SP
;
3433 unwind
.sp_restored
= 0;
3437 /* Parse a handlerdata directive. Creates the exception handling table entry
3438 for the function. */
3441 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3443 demand_empty_rest_of_line ();
3444 if (!unwind
.proc_start
)
3445 as_bad (MISSING_FNSTART
);
3447 if (unwind
.table_entry
)
3448 as_bad (_("duplicate .handlerdata directive"));
3450 create_unwind_entry (1);
3453 /* Parse an unwind_fnend directive. Generates the index table entry. */
3456 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3461 unsigned int marked_pr_dependency
;
3463 demand_empty_rest_of_line ();
3465 if (!unwind
.proc_start
)
3467 as_bad (_(".fnend directive without .fnstart"));
3471 /* Add eh table entry. */
3472 if (unwind
.table_entry
== NULL
)
3473 val
= create_unwind_entry (0);
3477 /* Add index table entry. This is two words. */
3478 start_unwind_section (unwind
.saved_seg
, 1);
3479 frag_align (2, 0, 0);
3480 record_alignment (now_seg
, 2);
3482 ptr
= frag_more (8);
3483 where
= frag_now_fix () - 8;
3485 /* Self relative offset of the function start. */
3486 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3487 BFD_RELOC_ARM_PREL31
);
3489 /* Indicate dependency on EHABI-defined personality routines to the
3490 linker, if it hasn't been done already. */
3491 marked_pr_dependency
3492 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3493 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3494 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3496 static const char *const name
[] =
3498 "__aeabi_unwind_cpp_pr0",
3499 "__aeabi_unwind_cpp_pr1",
3500 "__aeabi_unwind_cpp_pr2"
3502 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3503 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3504 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3505 |= 1 << unwind
.personality_index
;
3509 /* Inline exception table entry. */
3510 md_number_to_chars (ptr
+ 4, val
, 4);
3512 /* Self relative offset of the table entry. */
3513 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3514 BFD_RELOC_ARM_PREL31
);
3516 /* Restore the original section. */
3517 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3519 unwind
.proc_start
= NULL
;
3523 /* Parse an unwind_cantunwind directive. */
3526 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3528 demand_empty_rest_of_line ();
3529 if (!unwind
.proc_start
)
3530 as_bad (MISSING_FNSTART
);
3532 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3533 as_bad (_("personality routine specified for cantunwind frame"));
3535 unwind
.personality_index
= -2;
3539 /* Parse a personalityindex directive. */
3542 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3546 if (!unwind
.proc_start
)
3547 as_bad (MISSING_FNSTART
);
3549 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3550 as_bad (_("duplicate .personalityindex directive"));
3554 if (exp
.X_op
!= O_constant
3555 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3557 as_bad (_("bad personality routine number"));
3558 ignore_rest_of_line ();
3562 unwind
.personality_index
= exp
.X_add_number
;
3564 demand_empty_rest_of_line ();
3568 /* Parse a personality directive. */
3571 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3575 if (!unwind
.proc_start
)
3576 as_bad (MISSING_FNSTART
);
3578 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3579 as_bad (_("duplicate .personality directive"));
3581 name
= input_line_pointer
;
3582 c
= get_symbol_end ();
3583 p
= input_line_pointer
;
3584 unwind
.personality_routine
= symbol_find_or_make (name
);
3586 demand_empty_rest_of_line ();
3590 /* Parse a directive saving core registers. */
3593 s_arm_unwind_save_core (void)
3599 range
= parse_reg_list (&input_line_pointer
);
3602 as_bad (_("expected register list"));
3603 ignore_rest_of_line ();
3607 demand_empty_rest_of_line ();
3609 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3610 into .unwind_save {..., sp...}. We aren't bothered about the value of
3611 ip because it is clobbered by calls. */
3612 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3613 && (range
& 0x3000) == 0x1000)
3615 unwind
.opcode_count
--;
3616 unwind
.sp_restored
= 0;
3617 range
= (range
| 0x2000) & ~0x1000;
3618 unwind
.pending_offset
= 0;
3624 /* See if we can use the short opcodes. These pop a block of up to 8
3625 registers starting with r4, plus maybe r14. */
3626 for (n
= 0; n
< 8; n
++)
3628 /* Break at the first non-saved register. */
3629 if ((range
& (1 << (n
+ 4))) == 0)
3632 /* See if there are any other bits set. */
3633 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3635 /* Use the long form. */
3636 op
= 0x8000 | ((range
>> 4) & 0xfff);
3637 add_unwind_opcode (op
, 2);
3641 /* Use the short form. */
3643 op
= 0xa8; /* Pop r14. */
3645 op
= 0xa0; /* Do not pop r14. */
3647 add_unwind_opcode (op
, 1);
3654 op
= 0xb100 | (range
& 0xf);
3655 add_unwind_opcode (op
, 2);
3658 /* Record the number of bytes pushed. */
3659 for (n
= 0; n
< 16; n
++)
3661 if (range
& (1 << n
))
3662 unwind
.frame_size
+= 4;
3667 /* Parse a directive saving FPA registers. */
3670 s_arm_unwind_save_fpa (int reg
)
3676 /* Get Number of registers to transfer. */
3677 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3680 exp
.X_op
= O_illegal
;
3682 if (exp
.X_op
!= O_constant
)
3684 as_bad (_("expected , <constant>"));
3685 ignore_rest_of_line ();
3689 num_regs
= exp
.X_add_number
;
3691 if (num_regs
< 1 || num_regs
> 4)
3693 as_bad (_("number of registers must be in the range [1:4]"));
3694 ignore_rest_of_line ();
3698 demand_empty_rest_of_line ();
3703 op
= 0xb4 | (num_regs
- 1);
3704 add_unwind_opcode (op
, 1);
3709 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3710 add_unwind_opcode (op
, 2);
3712 unwind
.frame_size
+= num_regs
* 12;
3716 /* Parse a directive saving VFP registers for ARMv6 and above. */
3719 s_arm_unwind_save_vfp_armv6 (void)
3724 int num_vfpv3_regs
= 0;
3725 int num_regs_below_16
;
3727 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3730 as_bad (_("expected register list"));
3731 ignore_rest_of_line ();
3735 demand_empty_rest_of_line ();
3737 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3738 than FSTMX/FLDMX-style ones). */
3740 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3742 num_vfpv3_regs
= count
;
3743 else if (start
+ count
> 16)
3744 num_vfpv3_regs
= start
+ count
- 16;
3746 if (num_vfpv3_regs
> 0)
3748 int start_offset
= start
> 16 ? start
- 16 : 0;
3749 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3750 add_unwind_opcode (op
, 2);
3753 /* Generate opcode for registers numbered in the range 0 .. 15. */
3754 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3755 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3756 if (num_regs_below_16
> 0)
3758 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3759 add_unwind_opcode (op
, 2);
3762 unwind
.frame_size
+= count
* 8;
3766 /* Parse a directive saving VFP registers for pre-ARMv6. */
3769 s_arm_unwind_save_vfp (void)
3775 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3778 as_bad (_("expected register list"));
3779 ignore_rest_of_line ();
3783 demand_empty_rest_of_line ();
3788 op
= 0xb8 | (count
- 1);
3789 add_unwind_opcode (op
, 1);
3794 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3795 add_unwind_opcode (op
, 2);
3797 unwind
.frame_size
+= count
* 8 + 4;
3801 /* Parse a directive saving iWMMXt data registers. */
3804 s_arm_unwind_save_mmxwr (void)
3812 if (*input_line_pointer
== '{')
3813 input_line_pointer
++;
3817 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3821 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3826 as_tsktsk (_("register list not in ascending order"));
3829 if (*input_line_pointer
== '-')
3831 input_line_pointer
++;
3832 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3835 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3838 else if (reg
>= hi_reg
)
3840 as_bad (_("bad register range"));
3843 for (; reg
< hi_reg
; reg
++)
3847 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3849 if (*input_line_pointer
== '}')
3850 input_line_pointer
++;
3852 demand_empty_rest_of_line ();
3854 /* Generate any deferred opcodes because we're going to be looking at
3856 flush_pending_unwind ();
3858 for (i
= 0; i
< 16; i
++)
3860 if (mask
& (1 << i
))
3861 unwind
.frame_size
+= 8;
3864 /* Attempt to combine with a previous opcode. We do this because gcc
3865 likes to output separate unwind directives for a single block of
3867 if (unwind
.opcode_count
> 0)
3869 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3870 if ((i
& 0xf8) == 0xc0)
3873 /* Only merge if the blocks are contiguous. */
3876 if ((mask
& 0xfe00) == (1 << 9))
3878 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3879 unwind
.opcode_count
--;
3882 else if (i
== 6 && unwind
.opcode_count
>= 2)
3884 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3888 op
= 0xffff << (reg
- 1);
3890 && ((mask
& op
) == (1u << (reg
- 1))))
3892 op
= (1 << (reg
+ i
+ 1)) - 1;
3893 op
&= ~((1 << reg
) - 1);
3895 unwind
.opcode_count
-= 2;
3902 /* We want to generate opcodes in the order the registers have been
3903 saved, ie. descending order. */
3904 for (reg
= 15; reg
>= -1; reg
--)
3906 /* Save registers in blocks. */
3908 || !(mask
& (1 << reg
)))
3910 /* We found an unsaved reg. Generate opcodes to save the
3917 op
= 0xc0 | (hi_reg
- 10);
3918 add_unwind_opcode (op
, 1);
3923 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3924 add_unwind_opcode (op
, 2);
3933 ignore_rest_of_line ();
3937 s_arm_unwind_save_mmxwcg (void)
3944 if (*input_line_pointer
== '{')
3945 input_line_pointer
++;
3949 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3953 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3959 as_tsktsk (_("register list not in ascending order"));
3962 if (*input_line_pointer
== '-')
3964 input_line_pointer
++;
3965 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3968 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3971 else if (reg
>= hi_reg
)
3973 as_bad (_("bad register range"));
3976 for (; reg
< hi_reg
; reg
++)
3980 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3982 if (*input_line_pointer
== '}')
3983 input_line_pointer
++;
3985 demand_empty_rest_of_line ();
3987 /* Generate any deferred opcodes because we're going to be looking at
3989 flush_pending_unwind ();
3991 for (reg
= 0; reg
< 16; reg
++)
3993 if (mask
& (1 << reg
))
3994 unwind
.frame_size
+= 4;
3997 add_unwind_opcode (op
, 2);
4000 ignore_rest_of_line ();
4004 /* Parse an unwind_save directive.
4005 If the argument is non-zero, this is a .vsave directive. */
4008 s_arm_unwind_save (int arch_v6
)
4011 struct reg_entry
*reg
;
4012 bfd_boolean had_brace
= FALSE
;
4014 if (!unwind
.proc_start
)
4015 as_bad (MISSING_FNSTART
);
4017 /* Figure out what sort of save we have. */
4018 peek
= input_line_pointer
;
4026 reg
= arm_reg_parse_multi (&peek
);
4030 as_bad (_("register expected"));
4031 ignore_rest_of_line ();
4040 as_bad (_("FPA .unwind_save does not take a register list"));
4041 ignore_rest_of_line ();
4044 input_line_pointer
= peek
;
4045 s_arm_unwind_save_fpa (reg
->number
);
4048 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4051 s_arm_unwind_save_vfp_armv6 ();
4053 s_arm_unwind_save_vfp ();
4055 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4056 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4059 as_bad (_(".unwind_save does not support this kind of register"));
4060 ignore_rest_of_line ();
4065 /* Parse an unwind_movsp directive. */
4068 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4074 if (!unwind
.proc_start
)
4075 as_bad (MISSING_FNSTART
);
4077 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4080 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4081 ignore_rest_of_line ();
4085 /* Optional constant. */
4086 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4088 if (immediate_for_directive (&offset
) == FAIL
)
4094 demand_empty_rest_of_line ();
4096 if (reg
== REG_SP
|| reg
== REG_PC
)
4098 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4102 if (unwind
.fp_reg
!= REG_SP
)
4103 as_bad (_("unexpected .unwind_movsp directive"));
4105 /* Generate opcode to restore the value. */
4107 add_unwind_opcode (op
, 1);
4109 /* Record the information for later. */
4110 unwind
.fp_reg
= reg
;
4111 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4112 unwind
.sp_restored
= 1;
4115 /* Parse an unwind_pad directive. */
4118 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4122 if (!unwind
.proc_start
)
4123 as_bad (MISSING_FNSTART
);
4125 if (immediate_for_directive (&offset
) == FAIL
)
4130 as_bad (_("stack increment must be multiple of 4"));
4131 ignore_rest_of_line ();
4135 /* Don't generate any opcodes, just record the details for later. */
4136 unwind
.frame_size
+= offset
;
4137 unwind
.pending_offset
+= offset
;
4139 demand_empty_rest_of_line ();
4142 /* Parse an unwind_setfp directive. */
4145 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4151 if (!unwind
.proc_start
)
4152 as_bad (MISSING_FNSTART
);
4154 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4155 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4158 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4160 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4162 as_bad (_("expected <reg>, <reg>"));
4163 ignore_rest_of_line ();
4167 /* Optional constant. */
4168 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4170 if (immediate_for_directive (&offset
) == FAIL
)
4176 demand_empty_rest_of_line ();
4178 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4180 as_bad (_("register must be either sp or set by a previous"
4181 "unwind_movsp directive"));
4185 /* Don't generate any opcodes, just record the information for later. */
4186 unwind
.fp_reg
= fp_reg
;
4188 if (sp_reg
== REG_SP
)
4189 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4191 unwind
.fp_offset
-= offset
;
4194 /* Parse an unwind_raw directive. */
4197 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4200 /* This is an arbitrary limit. */
4201 unsigned char op
[16];
4204 if (!unwind
.proc_start
)
4205 as_bad (MISSING_FNSTART
);
4208 if (exp
.X_op
== O_constant
4209 && skip_past_comma (&input_line_pointer
) != FAIL
)
4211 unwind
.frame_size
+= exp
.X_add_number
;
4215 exp
.X_op
= O_illegal
;
4217 if (exp
.X_op
!= O_constant
)
4219 as_bad (_("expected <offset>, <opcode>"));
4220 ignore_rest_of_line ();
4226 /* Parse the opcode. */
4231 as_bad (_("unwind opcode too long"));
4232 ignore_rest_of_line ();
4234 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4236 as_bad (_("invalid unwind opcode"));
4237 ignore_rest_of_line ();
4240 op
[count
++] = exp
.X_add_number
;
4242 /* Parse the next byte. */
4243 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4249 /* Add the opcode bytes in reverse order. */
4251 add_unwind_opcode (op
[count
], 1);
4253 demand_empty_rest_of_line ();
4257 /* Parse a .eabi_attribute directive. */
4260 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4262 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4264 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4265 attributes_set_explicitly
[tag
] = 1;
4267 #endif /* OBJ_ELF */
4269 static void s_arm_arch (int);
4270 static void s_arm_object_arch (int);
4271 static void s_arm_cpu (int);
4272 static void s_arm_fpu (int);
4277 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4284 if (exp
.X_op
== O_symbol
)
4285 exp
.X_op
= O_secrel
;
4287 emit_expr (&exp
, 4);
4289 while (*input_line_pointer
++ == ',');
4291 input_line_pointer
--;
4292 demand_empty_rest_of_line ();
4296 /* This table describes all the machine specific pseudo-ops the assembler
4297 has to support. The fields are:
4298 pseudo-op name without dot
4299 function to call to execute this pseudo-op
4300 Integer arg to pass to the function. */
4302 const pseudo_typeS md_pseudo_table
[] =
4304 /* Never called because '.req' does not start a line. */
4305 { "req", s_req
, 0 },
4306 /* Following two are likewise never called. */
4309 { "unreq", s_unreq
, 0 },
4310 { "bss", s_bss
, 0 },
4311 { "align", s_align
, 0 },
4312 { "arm", s_arm
, 0 },
4313 { "thumb", s_thumb
, 0 },
4314 { "code", s_code
, 0 },
4315 { "force_thumb", s_force_thumb
, 0 },
4316 { "thumb_func", s_thumb_func
, 0 },
4317 { "thumb_set", s_thumb_set
, 0 },
4318 { "even", s_even
, 0 },
4319 { "ltorg", s_ltorg
, 0 },
4320 { "pool", s_ltorg
, 0 },
4321 { "syntax", s_syntax
, 0 },
4322 { "cpu", s_arm_cpu
, 0 },
4323 { "arch", s_arm_arch
, 0 },
4324 { "object_arch", s_arm_object_arch
, 0 },
4325 { "fpu", s_arm_fpu
, 0 },
4327 { "word", s_arm_elf_cons
, 4 },
4328 { "long", s_arm_elf_cons
, 4 },
4329 { "inst.n", s_arm_elf_inst
, 2 },
4330 { "inst.w", s_arm_elf_inst
, 4 },
4331 { "inst", s_arm_elf_inst
, 0 },
4332 { "rel31", s_arm_rel31
, 0 },
4333 { "fnstart", s_arm_unwind_fnstart
, 0 },
4334 { "fnend", s_arm_unwind_fnend
, 0 },
4335 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4336 { "personality", s_arm_unwind_personality
, 0 },
4337 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4338 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4339 { "save", s_arm_unwind_save
, 0 },
4340 { "vsave", s_arm_unwind_save
, 1 },
4341 { "movsp", s_arm_unwind_movsp
, 0 },
4342 { "pad", s_arm_unwind_pad
, 0 },
4343 { "setfp", s_arm_unwind_setfp
, 0 },
4344 { "unwind_raw", s_arm_unwind_raw
, 0 },
4345 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4349 /* These are used for dwarf. */
4353 /* These are used for dwarf2. */
4354 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4355 { "loc", dwarf2_directive_loc
, 0 },
4356 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4358 { "extend", float_cons
, 'x' },
4359 { "ldouble", float_cons
, 'x' },
4360 { "packed", float_cons
, 'p' },
4362 {"secrel32", pe_directive_secrel
, 0},
4367 /* Parser functions used exclusively in instruction operands. */
4369 /* Generic immediate-value read function for use in insn parsing.
4370 STR points to the beginning of the immediate (the leading #);
4371 VAL receives the value; if the value is outside [MIN, MAX]
4372 issue an error. PREFIX_OPT is true if the immediate prefix is
4376 parse_immediate (char **str
, int *val
, int min
, int max
,
4377 bfd_boolean prefix_opt
)
4380 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4381 if (exp
.X_op
!= O_constant
)
4383 inst
.error
= _("constant expression required");
4387 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4389 inst
.error
= _("immediate value out of range");
4393 *val
= exp
.X_add_number
;
4397 /* Less-generic immediate-value read function with the possibility of loading a
4398 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4399 instructions. Puts the result directly in inst.operands[i]. */
4402 parse_big_immediate (char **str
, int i
)
4407 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4409 if (exp
.X_op
== O_constant
)
4411 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4412 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4413 O_constant. We have to be careful not to break compilation for
4414 32-bit X_add_number, though. */
4415 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4417 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4418 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4419 inst
.operands
[i
].regisimm
= 1;
4422 else if (exp
.X_op
== O_big
4423 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4424 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4426 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4427 /* Bignums have their least significant bits in
4428 generic_bignum[0]. Make sure we put 32 bits in imm and
4429 32 bits in reg, in a (hopefully) portable way. */
4430 gas_assert (parts
!= 0);
4431 inst
.operands
[i
].imm
= 0;
4432 for (j
= 0; j
< parts
; j
++, idx
++)
4433 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4434 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4435 inst
.operands
[i
].reg
= 0;
4436 for (j
= 0; j
< parts
; j
++, idx
++)
4437 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4438 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4439 inst
.operands
[i
].regisimm
= 1;
4449 /* Returns the pseudo-register number of an FPA immediate constant,
4450 or FAIL if there isn't a valid constant here. */
4453 parse_fpa_immediate (char ** str
)
4455 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4461 /* First try and match exact strings, this is to guarantee
4462 that some formats will work even for cross assembly. */
4464 for (i
= 0; fp_const
[i
]; i
++)
4466 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4470 *str
+= strlen (fp_const
[i
]);
4471 if (is_end_of_line
[(unsigned char) **str
])
4477 /* Just because we didn't get a match doesn't mean that the constant
4478 isn't valid, just that it is in a format that we don't
4479 automatically recognize. Try parsing it with the standard
4480 expression routines. */
4482 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4484 /* Look for a raw floating point number. */
4485 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4486 && is_end_of_line
[(unsigned char) *save_in
])
4488 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4490 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4492 if (words
[j
] != fp_values
[i
][j
])
4496 if (j
== MAX_LITTLENUMS
)
4504 /* Try and parse a more complex expression, this will probably fail
4505 unless the code uses a floating point prefix (eg "0f"). */
4506 save_in
= input_line_pointer
;
4507 input_line_pointer
= *str
;
4508 if (expression (&exp
) == absolute_section
4509 && exp
.X_op
== O_big
4510 && exp
.X_add_number
< 0)
4512 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4514 if (gen_to_words (words
, 5, (long) 15) == 0)
4516 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4518 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4520 if (words
[j
] != fp_values
[i
][j
])
4524 if (j
== MAX_LITTLENUMS
)
4526 *str
= input_line_pointer
;
4527 input_line_pointer
= save_in
;
4534 *str
= input_line_pointer
;
4535 input_line_pointer
= save_in
;
4536 inst
.error
= _("invalid FPA immediate expression");
4540 /* Returns 1 if a number has "quarter-precision" float format
4541 0baBbbbbbc defgh000 00000000 00000000. */
4544 is_quarter_float (unsigned imm
)
4546 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4547 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4550 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4551 0baBbbbbbc defgh000 00000000 00000000.
4552 The zero and minus-zero cases need special handling, since they can't be
4553 encoded in the "quarter-precision" float format, but can nonetheless be
4554 loaded as integer constants. */
4557 parse_qfloat_immediate (char **ccp
, int *immed
)
4561 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4562 int found_fpchar
= 0;
4564 skip_past_char (&str
, '#');
4566 /* We must not accidentally parse an integer as a floating-point number. Make
4567 sure that the value we parse is not an integer by checking for special
4568 characters '.' or 'e'.
4569 FIXME: This is a horrible hack, but doing better is tricky because type
4570 information isn't in a very usable state at parse time. */
4572 skip_whitespace (fpnum
);
4574 if (strncmp (fpnum
, "0x", 2) == 0)
4578 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4579 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4589 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4591 unsigned fpword
= 0;
4594 /* Our FP word must be 32 bits (single-precision FP). */
4595 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4597 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4601 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4614 /* Shift operands. */
4617 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4620 struct asm_shift_name
4623 enum shift_kind kind
;
4626 /* Third argument to parse_shift. */
4627 enum parse_shift_mode
4629 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4630 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4631 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4632 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4633 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4636 /* Parse a <shift> specifier on an ARM data processing instruction.
4637 This has three forms:
4639 (LSL|LSR|ASL|ASR|ROR) Rs
4640 (LSL|LSR|ASL|ASR|ROR) #imm
4643 Note that ASL is assimilated to LSL in the instruction encoding, and
4644 RRX to ROR #0 (which cannot be written as such). */
4647 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4649 const struct asm_shift_name
*shift_name
;
4650 enum shift_kind shift
;
4655 for (p
= *str
; ISALPHA (*p
); p
++)
4660 inst
.error
= _("shift expression expected");
4664 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4667 if (shift_name
== NULL
)
4669 inst
.error
= _("shift expression expected");
4673 shift
= shift_name
->kind
;
4677 case NO_SHIFT_RESTRICT
:
4678 case SHIFT_IMMEDIATE
: break;
4680 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4681 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4683 inst
.error
= _("'LSL' or 'ASR' required");
4688 case SHIFT_LSL_IMMEDIATE
:
4689 if (shift
!= SHIFT_LSL
)
4691 inst
.error
= _("'LSL' required");
4696 case SHIFT_ASR_IMMEDIATE
:
4697 if (shift
!= SHIFT_ASR
)
4699 inst
.error
= _("'ASR' required");
4707 if (shift
!= SHIFT_RRX
)
4709 /* Whitespace can appear here if the next thing is a bare digit. */
4710 skip_whitespace (p
);
4712 if (mode
== NO_SHIFT_RESTRICT
4713 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4715 inst
.operands
[i
].imm
= reg
;
4716 inst
.operands
[i
].immisreg
= 1;
4718 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4721 inst
.operands
[i
].shift_kind
= shift
;
4722 inst
.operands
[i
].shifted
= 1;
4727 /* Parse a <shifter_operand> for an ARM data processing instruction:
4730 #<immediate>, <rotate>
4734 where <shift> is defined by parse_shift above, and <rotate> is a
4735 multiple of 2 between 0 and 30. Validation of immediate operands
4736 is deferred to md_apply_fix. */
4739 parse_shifter_operand (char **str
, int i
)
4744 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4746 inst
.operands
[i
].reg
= value
;
4747 inst
.operands
[i
].isreg
= 1;
4749 /* parse_shift will override this if appropriate */
4750 inst
.reloc
.exp
.X_op
= O_constant
;
4751 inst
.reloc
.exp
.X_add_number
= 0;
4753 if (skip_past_comma (str
) == FAIL
)
4756 /* Shift operation on register. */
4757 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4760 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4763 if (skip_past_comma (str
) == SUCCESS
)
4765 /* #x, y -- ie explicit rotation by Y. */
4766 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4769 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4771 inst
.error
= _("constant expression expected");
4775 value
= exp
.X_add_number
;
4776 if (value
< 0 || value
> 30 || value
% 2 != 0)
4778 inst
.error
= _("invalid rotation");
4781 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4783 inst
.error
= _("invalid constant");
4787 /* Convert to decoded value. md_apply_fix will put it back. */
4788 inst
.reloc
.exp
.X_add_number
4789 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4790 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4793 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4794 inst
.reloc
.pc_rel
= 0;
4798 /* Group relocation information. Each entry in the table contains the
4799 textual name of the relocation as may appear in assembler source
4800 and must end with a colon.
4801 Along with this textual name are the relocation codes to be used if
4802 the corresponding instruction is an ALU instruction (ADD or SUB only),
4803 an LDR, an LDRS, or an LDC. */
4805 struct group_reloc_table_entry
4816 /* Varieties of non-ALU group relocation. */
4823 static struct group_reloc_table_entry group_reloc_table
[] =
4824 { /* Program counter relative: */
4826 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4831 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4832 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4833 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4834 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4836 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4841 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4842 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4843 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4844 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4846 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4847 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4848 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4849 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4850 /* Section base relative */
4852 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4857 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4858 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4859 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4860 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4862 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4867 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4868 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4869 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4870 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4872 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4873 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4874 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4875 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4877 /* Given the address of a pointer pointing to the textual name of a group
4878 relocation as may appear in assembler source, attempt to find its details
4879 in group_reloc_table. The pointer will be updated to the character after
4880 the trailing colon. On failure, FAIL will be returned; SUCCESS
4881 otherwise. On success, *entry will be updated to point at the relevant
4882 group_reloc_table entry. */
4885 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4888 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4890 int length
= strlen (group_reloc_table
[i
].name
);
4892 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4893 && (*str
)[length
] == ':')
4895 *out
= &group_reloc_table
[i
];
4896 *str
+= (length
+ 1);
4904 /* Parse a <shifter_operand> for an ARM data processing instruction
4905 (as for parse_shifter_operand) where group relocations are allowed:
4908 #<immediate>, <rotate>
4909 #:<group_reloc>:<expression>
4913 where <group_reloc> is one of the strings defined in group_reloc_table.
4914 The hashes are optional.
4916 Everything else is as for parse_shifter_operand. */
4918 static parse_operand_result
4919 parse_shifter_operand_group_reloc (char **str
, int i
)
4921 /* Determine if we have the sequence of characters #: or just :
4922 coming next. If we do, then we check for a group relocation.
4923 If we don't, punt the whole lot to parse_shifter_operand. */
4925 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4926 || (*str
)[0] == ':')
4928 struct group_reloc_table_entry
*entry
;
4930 if ((*str
)[0] == '#')
4935 /* Try to parse a group relocation. Anything else is an error. */
4936 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4938 inst
.error
= _("unknown group relocation");
4939 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4942 /* We now have the group relocation table entry corresponding to
4943 the name in the assembler source. Next, we parse the expression. */
4944 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4945 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4947 /* Record the relocation type (always the ALU variant here). */
4948 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
4949 gas_assert (inst
.reloc
.type
!= 0);
4951 return PARSE_OPERAND_SUCCESS
;
4954 return parse_shifter_operand (str
, i
) == SUCCESS
4955 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4957 /* Never reached. */
4960 /* Parse a Neon alignment expression. Information is written to
4961 inst.operands[i]. We assume the initial ':' has been skipped.
4963 align .imm = align << 8, .immisalign=1, .preind=0 */
4964 static parse_operand_result
4965 parse_neon_alignment (char **str
, int i
)
4970 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4972 if (exp
.X_op
!= O_constant
)
4974 inst
.error
= _("alignment must be constant");
4975 return PARSE_OPERAND_FAIL
;
4978 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4979 inst
.operands
[i
].immisalign
= 1;
4980 /* Alignments are not pre-indexes. */
4981 inst
.operands
[i
].preind
= 0;
4984 return PARSE_OPERAND_SUCCESS
;
4987 /* Parse all forms of an ARM address expression. Information is written
4988 to inst.operands[i] and/or inst.reloc.
4990 Preindexed addressing (.preind=1):
4992 [Rn, #offset] .reg=Rn .reloc.exp=offset
4993 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4994 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4995 .shift_kind=shift .reloc.exp=shift_imm
4997 These three may have a trailing ! which causes .writeback to be set also.
4999 Postindexed addressing (.postind=1, .writeback=1):
5001 [Rn], #offset .reg=Rn .reloc.exp=offset
5002 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5003 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5004 .shift_kind=shift .reloc.exp=shift_imm
5006 Unindexed addressing (.preind=0, .postind=0):
5008 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5012 [Rn]{!} shorthand for [Rn,#0]{!}
5013 =immediate .isreg=0 .reloc.exp=immediate
5014 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5016 It is the caller's responsibility to check for addressing modes not
5017 supported by the instruction, and to set inst.reloc.type. */
5019 static parse_operand_result
5020 parse_address_main (char **str
, int i
, int group_relocations
,
5021 group_reloc_type group_type
)
5026 if (skip_past_char (&p
, '[') == FAIL
)
5028 if (skip_past_char (&p
, '=') == FAIL
)
5030 /* Bare address - translate to PC-relative offset. */
5031 inst
.reloc
.pc_rel
= 1;
5032 inst
.operands
[i
].reg
= REG_PC
;
5033 inst
.operands
[i
].isreg
= 1;
5034 inst
.operands
[i
].preind
= 1;
5036 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5038 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5039 return PARSE_OPERAND_FAIL
;
5042 return PARSE_OPERAND_SUCCESS
;
5045 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5047 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5048 return PARSE_OPERAND_FAIL
;
5050 inst
.operands
[i
].reg
= reg
;
5051 inst
.operands
[i
].isreg
= 1;
5053 if (skip_past_comma (&p
) == SUCCESS
)
5055 inst
.operands
[i
].preind
= 1;
5058 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5060 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5062 inst
.operands
[i
].imm
= reg
;
5063 inst
.operands
[i
].immisreg
= 1;
5065 if (skip_past_comma (&p
) == SUCCESS
)
5066 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5067 return PARSE_OPERAND_FAIL
;
5069 else if (skip_past_char (&p
, ':') == SUCCESS
)
5071 /* FIXME: '@' should be used here, but it's filtered out by generic
5072 code before we get to see it here. This may be subject to
5074 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5076 if (result
!= PARSE_OPERAND_SUCCESS
)
5081 if (inst
.operands
[i
].negative
)
5083 inst
.operands
[i
].negative
= 0;
5087 if (group_relocations
5088 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5090 struct group_reloc_table_entry
*entry
;
5092 /* Skip over the #: or : sequence. */
5098 /* Try to parse a group relocation. Anything else is an
5100 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5102 inst
.error
= _("unknown group relocation");
5103 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5106 /* We now have the group relocation table entry corresponding to
5107 the name in the assembler source. Next, we parse the
5109 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5110 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5112 /* Record the relocation type. */
5116 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5120 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5124 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5131 if (inst
.reloc
.type
== 0)
5133 inst
.error
= _("this group relocation is not allowed on this instruction");
5134 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5138 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5139 return PARSE_OPERAND_FAIL
;
5142 else if (skip_past_char (&p
, ':') == SUCCESS
)
5144 /* FIXME: '@' should be used here, but it's filtered out by generic code
5145 before we get to see it here. This may be subject to change. */
5146 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5148 if (result
!= PARSE_OPERAND_SUCCESS
)
5152 if (skip_past_char (&p
, ']') == FAIL
)
5154 inst
.error
= _("']' expected");
5155 return PARSE_OPERAND_FAIL
;
5158 if (skip_past_char (&p
, '!') == SUCCESS
)
5159 inst
.operands
[i
].writeback
= 1;
5161 else if (skip_past_comma (&p
) == SUCCESS
)
5163 if (skip_past_char (&p
, '{') == SUCCESS
)
5165 /* [Rn], {expr} - unindexed, with option */
5166 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5167 0, 255, TRUE
) == FAIL
)
5168 return PARSE_OPERAND_FAIL
;
5170 if (skip_past_char (&p
, '}') == FAIL
)
5172 inst
.error
= _("'}' expected at end of 'option' field");
5173 return PARSE_OPERAND_FAIL
;
5175 if (inst
.operands
[i
].preind
)
5177 inst
.error
= _("cannot combine index with option");
5178 return PARSE_OPERAND_FAIL
;
5181 return PARSE_OPERAND_SUCCESS
;
5185 inst
.operands
[i
].postind
= 1;
5186 inst
.operands
[i
].writeback
= 1;
5188 if (inst
.operands
[i
].preind
)
5190 inst
.error
= _("cannot combine pre- and post-indexing");
5191 return PARSE_OPERAND_FAIL
;
5195 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5197 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5199 /* We might be using the immediate for alignment already. If we
5200 are, OR the register number into the low-order bits. */
5201 if (inst
.operands
[i
].immisalign
)
5202 inst
.operands
[i
].imm
|= reg
;
5204 inst
.operands
[i
].imm
= reg
;
5205 inst
.operands
[i
].immisreg
= 1;
5207 if (skip_past_comma (&p
) == SUCCESS
)
5208 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5209 return PARSE_OPERAND_FAIL
;
5213 if (inst
.operands
[i
].negative
)
5215 inst
.operands
[i
].negative
= 0;
5218 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5219 return PARSE_OPERAND_FAIL
;
5224 /* If at this point neither .preind nor .postind is set, we have a
5225 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5226 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5228 inst
.operands
[i
].preind
= 1;
5229 inst
.reloc
.exp
.X_op
= O_constant
;
5230 inst
.reloc
.exp
.X_add_number
= 0;
5233 return PARSE_OPERAND_SUCCESS
;
5237 parse_address (char **str
, int i
)
5239 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5243 static parse_operand_result
5244 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5246 return parse_address_main (str
, i
, 1, type
);
5249 /* Parse an operand for a MOVW or MOVT instruction. */
5251 parse_half (char **str
)
5256 skip_past_char (&p
, '#');
5257 if (strncasecmp (p
, ":lower16:", 9) == 0)
5258 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5259 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5260 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5262 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5265 skip_whitespace (p
);
5268 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5271 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5273 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5275 inst
.error
= _("constant expression expected");
5278 if (inst
.reloc
.exp
.X_add_number
< 0
5279 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5281 inst
.error
= _("immediate value out of range");
5289 /* Miscellaneous. */
5291 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5292 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5294 parse_psr (char **str
)
5297 unsigned long psr_field
;
5298 const struct asm_psr
*psr
;
5301 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5302 feature for ease of use and backwards compatibility. */
5304 if (strncasecmp (p
, "SPSR", 4) == 0)
5305 psr_field
= SPSR_BIT
;
5306 else if (strncasecmp (p
, "CPSR", 4) == 0)
5313 while (ISALNUM (*p
) || *p
== '_');
5315 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5327 /* A suffix follows. */
5333 while (ISALNUM (*p
) || *p
== '_');
5335 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5340 psr_field
|= psr
->field
;
5345 goto error
; /* Garbage after "[CS]PSR". */
5347 psr_field
|= (PSR_c
| PSR_f
);
5353 inst
.error
= _("flag for {c}psr instruction expected");
5357 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5358 value suitable for splatting into the AIF field of the instruction. */
5361 parse_cps_flags (char **str
)
5370 case '\0': case ',':
5373 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5374 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5375 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5378 inst
.error
= _("unrecognized CPS flag");
5383 if (saw_a_flag
== 0)
5385 inst
.error
= _("missing CPS flags");
5393 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5394 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5397 parse_endian_specifier (char **str
)
5402 if (strncasecmp (s
, "BE", 2))
5404 else if (strncasecmp (s
, "LE", 2))
5408 inst
.error
= _("valid endian specifiers are be or le");
5412 if (ISALNUM (s
[2]) || s
[2] == '_')
5414 inst
.error
= _("valid endian specifiers are be or le");
5419 return little_endian
;
5422 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5423 value suitable for poking into the rotate field of an sxt or sxta
5424 instruction, or FAIL on error. */
5427 parse_ror (char **str
)
5432 if (strncasecmp (s
, "ROR", 3) == 0)
5436 inst
.error
= _("missing rotation field after comma");
5440 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5445 case 0: *str
= s
; return 0x0;
5446 case 8: *str
= s
; return 0x1;
5447 case 16: *str
= s
; return 0x2;
5448 case 24: *str
= s
; return 0x3;
5451 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5456 /* Parse a conditional code (from conds[] below). The value returned is in the
5457 range 0 .. 14, or FAIL. */
5459 parse_cond (char **str
)
5462 const struct asm_cond
*c
;
5464 /* Condition codes are always 2 characters, so matching up to
5465 3 characters is sufficient. */
5470 while (ISALPHA (*q
) && n
< 3)
5472 cond
[n
] = TOLOWER (*q
);
5477 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5480 inst
.error
= _("condition required");
5488 /* Parse an option for a barrier instruction. Returns the encoding for the
5491 parse_barrier (char **str
)
5494 const struct asm_barrier_opt
*o
;
5497 while (ISALPHA (*q
))
5500 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5509 /* Parse the operands of a table branch instruction. Similar to a memory
5512 parse_tb (char **str
)
5517 if (skip_past_char (&p
, '[') == FAIL
)
5519 inst
.error
= _("'[' expected");
5523 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5525 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5528 inst
.operands
[0].reg
= reg
;
5530 if (skip_past_comma (&p
) == FAIL
)
5532 inst
.error
= _("',' expected");
5536 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5538 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5541 inst
.operands
[0].imm
= reg
;
5543 if (skip_past_comma (&p
) == SUCCESS
)
5545 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5547 if (inst
.reloc
.exp
.X_add_number
!= 1)
5549 inst
.error
= _("invalid shift");
5552 inst
.operands
[0].shifted
= 1;
5555 if (skip_past_char (&p
, ']') == FAIL
)
5557 inst
.error
= _("']' expected");
5564 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5565 information on the types the operands can take and how they are encoded.
5566 Up to four operands may be read; this function handles setting the
5567 ".present" field for each read operand itself.
5568 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5569 else returns FAIL. */
5572 parse_neon_mov (char **str
, int *which_operand
)
5574 int i
= *which_operand
, val
;
5575 enum arm_reg_type rtype
;
5577 struct neon_type_el optype
;
5579 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5581 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5582 inst
.operands
[i
].reg
= val
;
5583 inst
.operands
[i
].isscalar
= 1;
5584 inst
.operands
[i
].vectype
= optype
;
5585 inst
.operands
[i
++].present
= 1;
5587 if (skip_past_comma (&ptr
) == FAIL
)
5590 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5593 inst
.operands
[i
].reg
= val
;
5594 inst
.operands
[i
].isreg
= 1;
5595 inst
.operands
[i
].present
= 1;
5597 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5600 /* Cases 0, 1, 2, 3, 5 (D only). */
5601 if (skip_past_comma (&ptr
) == FAIL
)
5604 inst
.operands
[i
].reg
= val
;
5605 inst
.operands
[i
].isreg
= 1;
5606 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5607 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5608 inst
.operands
[i
].isvec
= 1;
5609 inst
.operands
[i
].vectype
= optype
;
5610 inst
.operands
[i
++].present
= 1;
5612 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5614 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5615 Case 13: VMOV <Sd>, <Rm> */
5616 inst
.operands
[i
].reg
= val
;
5617 inst
.operands
[i
].isreg
= 1;
5618 inst
.operands
[i
].present
= 1;
5620 if (rtype
== REG_TYPE_NQ
)
5622 first_error (_("can't use Neon quad register here"));
5625 else if (rtype
!= REG_TYPE_VFS
)
5628 if (skip_past_comma (&ptr
) == FAIL
)
5630 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5632 inst
.operands
[i
].reg
= val
;
5633 inst
.operands
[i
].isreg
= 1;
5634 inst
.operands
[i
].present
= 1;
5637 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5640 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5641 Case 1: VMOV<c><q> <Dd>, <Dm>
5642 Case 8: VMOV.F32 <Sd>, <Sm>
5643 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5645 inst
.operands
[i
].reg
= val
;
5646 inst
.operands
[i
].isreg
= 1;
5647 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5648 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5649 inst
.operands
[i
].isvec
= 1;
5650 inst
.operands
[i
].vectype
= optype
;
5651 inst
.operands
[i
].present
= 1;
5653 if (skip_past_comma (&ptr
) == SUCCESS
)
5658 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5661 inst
.operands
[i
].reg
= val
;
5662 inst
.operands
[i
].isreg
= 1;
5663 inst
.operands
[i
++].present
= 1;
5665 if (skip_past_comma (&ptr
) == FAIL
)
5668 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5671 inst
.operands
[i
].reg
= val
;
5672 inst
.operands
[i
].isreg
= 1;
5673 inst
.operands
[i
++].present
= 1;
5676 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5677 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5678 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5679 Case 10: VMOV.F32 <Sd>, #<imm>
5680 Case 11: VMOV.F64 <Dd>, #<imm> */
5681 inst
.operands
[i
].immisfloat
= 1;
5682 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5683 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5684 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5688 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5692 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5695 inst
.operands
[i
].reg
= val
;
5696 inst
.operands
[i
].isreg
= 1;
5697 inst
.operands
[i
++].present
= 1;
5699 if (skip_past_comma (&ptr
) == FAIL
)
5702 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5704 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5705 inst
.operands
[i
].reg
= val
;
5706 inst
.operands
[i
].isscalar
= 1;
5707 inst
.operands
[i
].present
= 1;
5708 inst
.operands
[i
].vectype
= optype
;
5710 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5712 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5713 inst
.operands
[i
].reg
= val
;
5714 inst
.operands
[i
].isreg
= 1;
5715 inst
.operands
[i
++].present
= 1;
5717 if (skip_past_comma (&ptr
) == FAIL
)
5720 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5723 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5727 inst
.operands
[i
].reg
= val
;
5728 inst
.operands
[i
].isreg
= 1;
5729 inst
.operands
[i
].isvec
= 1;
5730 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5731 inst
.operands
[i
].vectype
= optype
;
5732 inst
.operands
[i
].present
= 1;
5734 if (rtype
== REG_TYPE_VFS
)
5738 if (skip_past_comma (&ptr
) == FAIL
)
5740 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5743 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5746 inst
.operands
[i
].reg
= val
;
5747 inst
.operands
[i
].isreg
= 1;
5748 inst
.operands
[i
].isvec
= 1;
5749 inst
.operands
[i
].issingle
= 1;
5750 inst
.operands
[i
].vectype
= optype
;
5751 inst
.operands
[i
].present
= 1;
5754 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5758 inst
.operands
[i
].reg
= val
;
5759 inst
.operands
[i
].isreg
= 1;
5760 inst
.operands
[i
].isvec
= 1;
5761 inst
.operands
[i
].issingle
= 1;
5762 inst
.operands
[i
].vectype
= optype
;
5763 inst
.operands
[i
++].present
= 1;
5768 first_error (_("parse error"));
5772 /* Successfully parsed the operands. Update args. */
5778 first_error (_("expected comma"));
5782 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5786 /* Use this macro when the operand constraints are different
5787 for ARM and THUMB (e.g. ldrd). */
5788 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
5789 ((arm_operand) | ((thumb_operand) << 16))
5791 /* Matcher codes for parse_operands. */
5792 enum operand_parse_code
5794 OP_stop
, /* end of line */
5796 OP_RR
, /* ARM register */
5797 OP_RRnpc
, /* ARM register, not r15 */
5798 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
5799 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5800 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
5801 optional trailing ! */
5802 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5803 OP_RCP
, /* Coprocessor number */
5804 OP_RCN
, /* Coprocessor register */
5805 OP_RF
, /* FPA register */
5806 OP_RVS
, /* VFP single precision register */
5807 OP_RVD
, /* VFP double precision register (0..15) */
5808 OP_RND
, /* Neon double precision register (0..31) */
5809 OP_RNQ
, /* Neon quad precision register */
5810 OP_RVSD
, /* VFP single or double precision register */
5811 OP_RNDQ
, /* Neon double or quad precision register */
5812 OP_RNSDQ
, /* Neon single, double or quad precision register */
5813 OP_RNSC
, /* Neon scalar D[X] */
5814 OP_RVC
, /* VFP control register */
5815 OP_RMF
, /* Maverick F register */
5816 OP_RMD
, /* Maverick D register */
5817 OP_RMFX
, /* Maverick FX register */
5818 OP_RMDX
, /* Maverick DX register */
5819 OP_RMAX
, /* Maverick AX register */
5820 OP_RMDS
, /* Maverick DSPSC register */
5821 OP_RIWR
, /* iWMMXt wR register */
5822 OP_RIWC
, /* iWMMXt wC register */
5823 OP_RIWG
, /* iWMMXt wCG register */
5824 OP_RXA
, /* XScale accumulator register */
5826 OP_REGLST
, /* ARM register list */
5827 OP_VRSLST
, /* VFP single-precision register list */
5828 OP_VRDLST
, /* VFP double-precision register list */
5829 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5830 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5831 OP_NSTRLST
, /* Neon element/structure list */
5833 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5834 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5835 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5836 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5837 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5838 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5839 OP_VMOV
, /* Neon VMOV operands. */
5840 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
5841 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5842 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5844 OP_I0
, /* immediate zero */
5845 OP_I7
, /* immediate value 0 .. 7 */
5846 OP_I15
, /* 0 .. 15 */
5847 OP_I16
, /* 1 .. 16 */
5848 OP_I16z
, /* 0 .. 16 */
5849 OP_I31
, /* 0 .. 31 */
5850 OP_I31w
, /* 0 .. 31, optional trailing ! */
5851 OP_I32
, /* 1 .. 32 */
5852 OP_I32z
, /* 0 .. 32 */
5853 OP_I63
, /* 0 .. 63 */
5854 OP_I63s
, /* -64 .. 63 */
5855 OP_I64
, /* 1 .. 64 */
5856 OP_I64z
, /* 0 .. 64 */
5857 OP_I255
, /* 0 .. 255 */
5859 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5860 OP_I7b
, /* 0 .. 7 */
5861 OP_I15b
, /* 0 .. 15 */
5862 OP_I31b
, /* 0 .. 31 */
5864 OP_SH
, /* shifter operand */
5865 OP_SHG
, /* shifter operand with possible group relocation */
5866 OP_ADDR
, /* Memory address expression (any mode) */
5867 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5868 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5869 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5870 OP_EXP
, /* arbitrary expression */
5871 OP_EXPi
, /* same, with optional immediate prefix */
5872 OP_EXPr
, /* same, with optional relocation suffix */
5873 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5875 OP_CPSF
, /* CPS flags */
5876 OP_ENDI
, /* Endianness specifier */
5877 OP_PSR
, /* CPSR/SPSR mask for msr */
5878 OP_COND
, /* conditional code */
5879 OP_TB
, /* Table branch. */
5881 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5882 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5884 OP_RRnpc_I0
, /* ARM register or literal 0 */
5885 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5886 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5887 OP_RF_IF
, /* FPA register or immediate */
5888 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5889 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5891 /* Optional operands. */
5892 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5893 OP_oI31b
, /* 0 .. 31 */
5894 OP_oI32b
, /* 1 .. 32 */
5895 OP_oIffffb
, /* 0 .. 65535 */
5896 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5898 OP_oRR
, /* ARM register */
5899 OP_oRRnpc
, /* ARM register, not the PC */
5900 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
5901 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5902 OP_oRND
, /* Optional Neon double precision register */
5903 OP_oRNQ
, /* Optional Neon quad precision register */
5904 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5905 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5906 OP_oSHll
, /* LSL immediate */
5907 OP_oSHar
, /* ASR immediate */
5908 OP_oSHllar
, /* LSL or ASR immediate */
5909 OP_oROR
, /* ROR 0/8/16/24 */
5910 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
5912 /* Some pre-defined mixed (ARM/THUMB) operands. */
5913 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
5914 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
5915 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
5917 OP_FIRST_OPTIONAL
= OP_oI7b
5920 /* Generic instruction operand parser. This does no encoding and no
5921 semantic validation; it merely squirrels values away in the inst
5922 structure. Returns SUCCESS or FAIL depending on whether the
5923 specified grammar matched. */
5925 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
5927 unsigned const int *upat
= pattern
;
5928 char *backtrack_pos
= 0;
5929 const char *backtrack_error
= 0;
5930 int i
, val
, backtrack_index
= 0;
5931 enum arm_reg_type rtype
;
5932 parse_operand_result result
;
5933 unsigned int op_parse_code
;
5935 #define po_char_or_fail(chr) \
5938 if (skip_past_char (&str, chr) == FAIL) \
5943 #define po_reg_or_fail(regtype) \
5946 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5947 & inst.operands[i].vectype); \
5950 first_error (_(reg_expected_msgs[regtype])); \
5953 inst.operands[i].reg = val; \
5954 inst.operands[i].isreg = 1; \
5955 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5956 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5957 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5958 || rtype == REG_TYPE_VFD \
5959 || rtype == REG_TYPE_NQ); \
5963 #define po_reg_or_goto(regtype, label) \
5966 val = arm_typed_reg_parse (& str, regtype, & rtype, \
5967 & inst.operands[i].vectype); \
5971 inst.operands[i].reg = val; \
5972 inst.operands[i].isreg = 1; \
5973 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5974 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5975 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5976 || rtype == REG_TYPE_VFD \
5977 || rtype == REG_TYPE_NQ); \
5981 #define po_imm_or_fail(min, max, popt) \
5984 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5986 inst.operands[i].imm = val; \
5990 #define po_scalar_or_goto(elsz, label) \
5993 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
5996 inst.operands[i].reg = val; \
5997 inst.operands[i].isscalar = 1; \
6001 #define po_misc_or_fail(expr) \
6009 #define po_misc_or_fail_no_backtrack(expr) \
6013 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6014 backtrack_pos = 0; \
6015 if (result != PARSE_OPERAND_SUCCESS) \
6020 #define po_barrier_or_imm(str) \
6023 val = parse_barrier (&str); \
6026 if (ISALPHA (*str)) \
6033 if ((inst.instruction & 0xf0) == 0x60 \
6036 /* ISB can only take SY as an option. */ \
6037 inst.error = _("invalid barrier type"); \
6044 skip_whitespace (str
);
6046 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6048 op_parse_code
= upat
[i
];
6049 if (op_parse_code
>= 1<<16)
6050 op_parse_code
= thumb
? (op_parse_code
>> 16)
6051 : (op_parse_code
& ((1<<16)-1));
6053 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6055 /* Remember where we are in case we need to backtrack. */
6056 gas_assert (!backtrack_pos
);
6057 backtrack_pos
= str
;
6058 backtrack_error
= inst
.error
;
6059 backtrack_index
= i
;
6062 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6063 po_char_or_fail (',');
6065 switch (op_parse_code
)
6073 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6074 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6075 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6076 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6077 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6078 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6080 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6082 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6084 /* Also accept generic coprocessor regs for unknown registers. */
6086 po_reg_or_fail (REG_TYPE_CN
);
6088 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6089 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6090 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6091 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6092 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6093 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6094 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6095 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6096 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6097 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6099 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6101 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6102 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6104 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6106 /* Neon scalar. Using an element size of 8 means that some invalid
6107 scalars are accepted here, so deal with those in later code. */
6108 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6112 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6115 po_imm_or_fail (0, 0, TRUE
);
6120 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6125 po_scalar_or_goto (8, try_rr
);
6128 po_reg_or_fail (REG_TYPE_RN
);
6134 po_scalar_or_goto (8, try_nsdq
);
6137 po_reg_or_fail (REG_TYPE_NSDQ
);
6143 po_scalar_or_goto (8, try_ndq
);
6146 po_reg_or_fail (REG_TYPE_NDQ
);
6152 po_scalar_or_goto (8, try_vfd
);
6155 po_reg_or_fail (REG_TYPE_VFD
);
6160 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6161 not careful then bad things might happen. */
6162 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6167 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6170 /* There's a possibility of getting a 64-bit immediate here, so
6171 we need special handling. */
6172 if (parse_big_immediate (&str
, i
) == FAIL
)
6174 inst
.error
= _("immediate value is out of range");
6182 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6185 po_imm_or_fail (0, 63, TRUE
);
6190 po_char_or_fail ('[');
6191 po_reg_or_fail (REG_TYPE_RN
);
6192 po_char_or_fail (']');
6198 po_reg_or_fail (REG_TYPE_RN
);
6199 if (skip_past_char (&str
, '!') == SUCCESS
)
6200 inst
.operands
[i
].writeback
= 1;
6204 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6205 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6206 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6207 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6208 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6209 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6210 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6211 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6212 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6213 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6214 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6215 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6217 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6219 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6220 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6222 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6223 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6224 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6226 /* Immediate variants */
6228 po_char_or_fail ('{');
6229 po_imm_or_fail (0, 255, TRUE
);
6230 po_char_or_fail ('}');
6234 /* The expression parser chokes on a trailing !, so we have
6235 to find it first and zap it. */
6238 while (*s
&& *s
!= ',')
6243 inst
.operands
[i
].writeback
= 1;
6245 po_imm_or_fail (0, 31, TRUE
);
6253 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6258 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6263 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6265 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6267 val
= parse_reloc (&str
);
6270 inst
.error
= _("unrecognized relocation suffix");
6273 else if (val
!= BFD_RELOC_UNUSED
)
6275 inst
.operands
[i
].imm
= val
;
6276 inst
.operands
[i
].hasreloc
= 1;
6281 /* Operand for MOVW or MOVT. */
6283 po_misc_or_fail (parse_half (&str
));
6286 /* Register or expression. */
6287 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6288 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6290 /* Register or immediate. */
6291 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6292 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6294 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6296 if (!is_immediate_prefix (*str
))
6299 val
= parse_fpa_immediate (&str
);
6302 /* FPA immediates are encoded as registers 8-15.
6303 parse_fpa_immediate has already applied the offset. */
6304 inst
.operands
[i
].reg
= val
;
6305 inst
.operands
[i
].isreg
= 1;
6308 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6309 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6311 /* Two kinds of register. */
6314 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6316 || (rege
->type
!= REG_TYPE_MMXWR
6317 && rege
->type
!= REG_TYPE_MMXWC
6318 && rege
->type
!= REG_TYPE_MMXWCG
))
6320 inst
.error
= _("iWMMXt data or control register expected");
6323 inst
.operands
[i
].reg
= rege
->number
;
6324 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6330 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6332 || (rege
->type
!= REG_TYPE_MMXWC
6333 && rege
->type
!= REG_TYPE_MMXWCG
))
6335 inst
.error
= _("iWMMXt control register expected");
6338 inst
.operands
[i
].reg
= rege
->number
;
6339 inst
.operands
[i
].isreg
= 1;
6344 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6345 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6346 case OP_oROR
: val
= parse_ror (&str
); break;
6347 case OP_PSR
: val
= parse_psr (&str
); break;
6348 case OP_COND
: val
= parse_cond (&str
); break;
6349 case OP_oBARRIER_I15
:
6350 po_barrier_or_imm (str
); break;
6352 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6357 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
6358 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
6361 val
= parse_psr (&str
);
6365 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6368 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6370 if (strncasecmp (str
, "APSR_", 5) == 0)
6377 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6378 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6379 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6380 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6381 default: found
= 16;
6385 inst
.operands
[i
].isvec
= 1;
6386 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6387 inst
.operands
[i
].reg
= REG_PC
;
6394 po_misc_or_fail (parse_tb (&str
));
6397 /* Register lists. */
6399 val
= parse_reg_list (&str
);
6402 inst
.operands
[1].writeback
= 1;
6408 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6412 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6416 /* Allow Q registers too. */
6417 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6422 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6424 inst
.operands
[i
].issingle
= 1;
6429 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6434 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6435 &inst
.operands
[i
].vectype
);
6438 /* Addressing modes */
6440 po_misc_or_fail (parse_address (&str
, i
));
6444 po_misc_or_fail_no_backtrack (
6445 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6449 po_misc_or_fail_no_backtrack (
6450 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6454 po_misc_or_fail_no_backtrack (
6455 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6459 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6463 po_misc_or_fail_no_backtrack (
6464 parse_shifter_operand_group_reloc (&str
, i
));
6468 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6472 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6476 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6480 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6483 /* Various value-based sanity checks and shared operations. We
6484 do not signal immediate failures for the register constraints;
6485 this allows a syntax error to take precedence. */
6486 switch (op_parse_code
)
6494 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6495 inst
.error
= BAD_PC
;
6500 if (inst
.operands
[i
].isreg
)
6502 if (inst
.operands
[i
].reg
== REG_PC
)
6503 inst
.error
= BAD_PC
;
6504 else if (inst
.operands
[i
].reg
== REG_SP
)
6505 inst
.error
= BAD_SP
;
6510 if (inst
.operands
[i
].isreg
6511 && inst
.operands
[i
].reg
== REG_PC
6512 && (inst
.operands
[i
].writeback
|| thumb
))
6513 inst
.error
= BAD_PC
;
6522 case OP_oBARRIER_I15
:
6531 inst
.operands
[i
].imm
= val
;
6538 /* If we get here, this operand was successfully parsed. */
6539 inst
.operands
[i
].present
= 1;
6543 inst
.error
= BAD_ARGS
;
6548 /* The parse routine should already have set inst.error, but set a
6549 default here just in case. */
6551 inst
.error
= _("syntax error");
6555 /* Do not backtrack over a trailing optional argument that
6556 absorbed some text. We will only fail again, with the
6557 'garbage following instruction' error message, which is
6558 probably less helpful than the current one. */
6559 if (backtrack_index
== i
&& backtrack_pos
!= str
6560 && upat
[i
+1] == OP_stop
)
6563 inst
.error
= _("syntax error");
6567 /* Try again, skipping the optional argument at backtrack_pos. */
6568 str
= backtrack_pos
;
6569 inst
.error
= backtrack_error
;
6570 inst
.operands
[backtrack_index
].present
= 0;
6571 i
= backtrack_index
;
6575 /* Check that we have parsed all the arguments. */
6576 if (*str
!= '\0' && !inst
.error
)
6577 inst
.error
= _("garbage following instruction");
6579 return inst
.error
? FAIL
: SUCCESS
;
6582 #undef po_char_or_fail
6583 #undef po_reg_or_fail
6584 #undef po_reg_or_goto
6585 #undef po_imm_or_fail
6586 #undef po_scalar_or_fail
6587 #undef po_barrier_or_imm
6589 /* Shorthand macro for instruction encoding functions issuing errors. */
6590 #define constraint(expr, err) \
6601 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6602 instructions are unpredictable if these registers are used. This
6603 is the BadReg predicate in ARM's Thumb-2 documentation. */
6604 #define reject_bad_reg(reg) \
6606 if (reg == REG_SP || reg == REG_PC) \
6608 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6613 /* If REG is R13 (the stack pointer), warn that its use is
6615 #define warn_deprecated_sp(reg) \
6617 if (warn_on_deprecated && reg == REG_SP) \
6618 as_warn (_("use of r13 is deprecated")); \
6621 /* Functions for operand encoding. ARM, then Thumb. */
6623 #define rotate_left(v, n) (v << n | v >> (32 - n))
6625 /* If VAL can be encoded in the immediate field of an ARM instruction,
6626 return the encoded form. Otherwise, return FAIL. */
6629 encode_arm_immediate (unsigned int val
)
6633 for (i
= 0; i
< 32; i
+= 2)
6634 if ((a
= rotate_left (val
, i
)) <= 0xff)
6635 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6640 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6641 return the encoded form. Otherwise, return FAIL. */
6643 encode_thumb32_immediate (unsigned int val
)
6650 for (i
= 1; i
<= 24; i
++)
6653 if ((val
& ~(0xff << i
)) == 0)
6654 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6658 if (val
== ((a
<< 16) | a
))
6660 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6664 if (val
== ((a
<< 16) | a
))
6665 return 0x200 | (a
>> 8);
6669 /* Encode a VFP SP or DP register number into inst.instruction. */
6672 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6674 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6677 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6680 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6683 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6688 first_error (_("D register out of range for selected VFP version"));
6696 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6700 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6704 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6708 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6712 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6716 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6724 /* Encode a <shift> in an ARM-format instruction. The immediate,
6725 if any, is handled by md_apply_fix. */
6727 encode_arm_shift (int i
)
6729 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6730 inst
.instruction
|= SHIFT_ROR
<< 5;
6733 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6734 if (inst
.operands
[i
].immisreg
)
6736 inst
.instruction
|= SHIFT_BY_REG
;
6737 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6740 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6745 encode_arm_shifter_operand (int i
)
6747 if (inst
.operands
[i
].isreg
)
6749 inst
.instruction
|= inst
.operands
[i
].reg
;
6750 encode_arm_shift (i
);
6753 inst
.instruction
|= INST_IMMEDIATE
;
6756 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6758 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6760 gas_assert (inst
.operands
[i
].isreg
);
6761 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6763 if (inst
.operands
[i
].preind
)
6767 inst
.error
= _("instruction does not accept preindexed addressing");
6770 inst
.instruction
|= PRE_INDEX
;
6771 if (inst
.operands
[i
].writeback
)
6772 inst
.instruction
|= WRITE_BACK
;
6775 else if (inst
.operands
[i
].postind
)
6777 gas_assert (inst
.operands
[i
].writeback
);
6779 inst
.instruction
|= WRITE_BACK
;
6781 else /* unindexed - only for coprocessor */
6783 inst
.error
= _("instruction does not accept unindexed addressing");
6787 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6788 && (((inst
.instruction
& 0x000f0000) >> 16)
6789 == ((inst
.instruction
& 0x0000f000) >> 12)))
6790 as_warn ((inst
.instruction
& LOAD_BIT
)
6791 ? _("destination register same as write-back base")
6792 : _("source register same as write-back base"));
6795 /* inst.operands[i] was set up by parse_address. Encode it into an
6796 ARM-format mode 2 load or store instruction. If is_t is true,
6797 reject forms that cannot be used with a T instruction (i.e. not
6800 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6802 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
6804 encode_arm_addr_mode_common (i
, is_t
);
6806 if (inst
.operands
[i
].immisreg
)
6808 constraint ((inst
.operands
[i
].imm
== REG_PC
6809 || (is_pc
&& inst
.operands
[i
].writeback
)),
6811 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6812 inst
.instruction
|= inst
.operands
[i
].imm
;
6813 if (!inst
.operands
[i
].negative
)
6814 inst
.instruction
|= INDEX_UP
;
6815 if (inst
.operands
[i
].shifted
)
6817 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6818 inst
.instruction
|= SHIFT_ROR
<< 5;
6821 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6822 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6826 else /* immediate offset in inst.reloc */
6828 if (is_pc
&& !inst
.reloc
.pc_rel
)
6830 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
6832 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
6833 cannot use PC in addressing.
6834 PC cannot be used in writeback addressing, either. */
6835 constraint ((is_t
|| inst
.operands
[i
].writeback
),
6838 /* Use of PC in str is deprecated for ARMv7. */
6839 if (warn_on_deprecated
6841 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
6842 as_warn (_("use of PC in this instruction is deprecated"));
6845 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6846 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6850 /* inst.operands[i] was set up by parse_address. Encode it into an
6851 ARM-format mode 3 load or store instruction. Reject forms that
6852 cannot be used with such instructions. If is_t is true, reject
6853 forms that cannot be used with a T instruction (i.e. not
6856 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6858 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6860 inst
.error
= _("instruction does not accept scaled register index");
6864 encode_arm_addr_mode_common (i
, is_t
);
6866 if (inst
.operands
[i
].immisreg
)
6868 constraint ((inst
.operands
[i
].imm
== REG_PC
6869 || inst
.operands
[i
].reg
== REG_PC
),
6871 inst
.instruction
|= inst
.operands
[i
].imm
;
6872 if (!inst
.operands
[i
].negative
)
6873 inst
.instruction
|= INDEX_UP
;
6875 else /* immediate offset in inst.reloc */
6877 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
6878 && inst
.operands
[i
].writeback
),
6880 inst
.instruction
|= HWOFFSET_IMM
;
6881 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6882 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6886 /* inst.operands[i] was set up by parse_address. Encode it into an
6887 ARM-format instruction. Reject all forms which cannot be encoded
6888 into a coprocessor load/store instruction. If wb_ok is false,
6889 reject use of writeback; if unind_ok is false, reject use of
6890 unindexed addressing. If reloc_override is not 0, use it instead
6891 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6892 (in which case it is preserved). */
6895 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6897 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6899 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6901 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6903 gas_assert (!inst
.operands
[i
].writeback
);
6906 inst
.error
= _("instruction does not support unindexed addressing");
6909 inst
.instruction
|= inst
.operands
[i
].imm
;
6910 inst
.instruction
|= INDEX_UP
;
6914 if (inst
.operands
[i
].preind
)
6915 inst
.instruction
|= PRE_INDEX
;
6917 if (inst
.operands
[i
].writeback
)
6919 if (inst
.operands
[i
].reg
== REG_PC
)
6921 inst
.error
= _("pc may not be used with write-back");
6926 inst
.error
= _("instruction does not support writeback");
6929 inst
.instruction
|= WRITE_BACK
;
6933 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
6934 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6935 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6936 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6939 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6941 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6947 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6948 Determine whether it can be performed with a move instruction; if
6949 it can, convert inst.instruction to that move instruction and
6950 return TRUE; if it can't, convert inst.instruction to a literal-pool
6951 load and return FALSE. If this is not a valid thing to do in the
6952 current context, set inst.error and return TRUE.
6954 inst.operands[i] describes the destination register. */
6957 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6962 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6966 if ((inst
.instruction
& tbit
) == 0)
6968 inst
.error
= _("invalid pseudo operation");
6971 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6973 inst
.error
= _("constant expression expected");
6976 if (inst
.reloc
.exp
.X_op
== O_constant
)
6980 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6982 /* This can be done with a mov(1) instruction. */
6983 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6984 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6990 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6993 /* This can be done with a mov instruction. */
6994 inst
.instruction
&= LITERAL_MASK
;
6995 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6996 inst
.instruction
|= value
& 0xfff;
7000 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7003 /* This can be done with a mvn instruction. */
7004 inst
.instruction
&= LITERAL_MASK
;
7005 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7006 inst
.instruction
|= value
& 0xfff;
7012 if (add_to_lit_pool () == FAIL
)
7014 inst
.error
= _("literal pool insertion failed");
7017 inst
.operands
[1].reg
= REG_PC
;
7018 inst
.operands
[1].isreg
= 1;
7019 inst
.operands
[1].preind
= 1;
7020 inst
.reloc
.pc_rel
= 1;
7021 inst
.reloc
.type
= (thumb_p
7022 ? BFD_RELOC_ARM_THUMB_OFFSET
7024 ? BFD_RELOC_ARM_HWLITERAL
7025 : BFD_RELOC_ARM_LITERAL
));
7029 /* Functions for instruction encoding, sorted by sub-architecture.
7030 First some generics; their names are taken from the conventional
7031 bit positions for register arguments in ARM format instructions. */
7041 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7047 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7048 inst
.instruction
|= inst
.operands
[1].reg
;
7054 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7055 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7061 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7062 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7068 unsigned Rn
= inst
.operands
[2].reg
;
7069 /* Enforce restrictions on SWP instruction. */
7070 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7072 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7073 _("Rn must not overlap other operands"));
7075 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7076 if (warn_on_deprecated
7077 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7078 as_warn (_("swp{b} use is deprecated for this architecture"));
7081 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7082 inst
.instruction
|= inst
.operands
[1].reg
;
7083 inst
.instruction
|= Rn
<< 16;
7089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7090 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7091 inst
.instruction
|= inst
.operands
[2].reg
;
7097 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7098 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7099 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7100 || inst
.reloc
.exp
.X_add_number
!= 0),
7102 inst
.instruction
|= inst
.operands
[0].reg
;
7103 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7104 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7110 inst
.instruction
|= inst
.operands
[0].imm
;
7116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7117 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7120 /* ARM instructions, in alphabetical order by function name (except
7121 that wrapper functions appear immediately after the function they
7124 /* This is a pseudo-op of the form "adr rd, label" to be converted
7125 into a relative address of the form "add rd, pc, #label-.-8". */
7130 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7132 /* Frag hacking will turn this into a sub instruction if the offset turns
7133 out to be negative. */
7134 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7135 inst
.reloc
.pc_rel
= 1;
7136 inst
.reloc
.exp
.X_add_number
-= 8;
7139 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7140 into a relative address of the form:
7141 add rd, pc, #low(label-.-8)"
7142 add rd, rd, #high(label-.-8)" */
7147 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7149 /* Frag hacking will turn this into a sub instruction if the offset turns
7150 out to be negative. */
7151 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7152 inst
.reloc
.pc_rel
= 1;
7153 inst
.size
= INSN_SIZE
* 2;
7154 inst
.reloc
.exp
.X_add_number
-= 8;
7160 if (!inst
.operands
[1].present
)
7161 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7162 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7163 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7164 encode_arm_shifter_operand (2);
7170 if (inst
.operands
[0].present
)
7172 constraint ((inst
.instruction
& 0xf0) != 0x40
7173 && inst
.operands
[0].imm
> 0xf
7174 && inst
.operands
[0].imm
< 0x0,
7175 _("bad barrier type"));
7176 inst
.instruction
|= inst
.operands
[0].imm
;
7179 inst
.instruction
|= 0xf;
7185 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7186 constraint (msb
> 32, _("bit-field extends past end of register"));
7187 /* The instruction encoding stores the LSB and MSB,
7188 not the LSB and width. */
7189 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7190 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7191 inst
.instruction
|= (msb
- 1) << 16;
7199 /* #0 in second position is alternative syntax for bfc, which is
7200 the same instruction but with REG_PC in the Rm field. */
7201 if (!inst
.operands
[1].isreg
)
7202 inst
.operands
[1].reg
= REG_PC
;
7204 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7205 constraint (msb
> 32, _("bit-field extends past end of register"));
7206 /* The instruction encoding stores the LSB and MSB,
7207 not the LSB and width. */
7208 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7209 inst
.instruction
|= inst
.operands
[1].reg
;
7210 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7211 inst
.instruction
|= (msb
- 1) << 16;
7217 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7218 _("bit-field extends past end of register"));
7219 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7220 inst
.instruction
|= inst
.operands
[1].reg
;
7221 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7222 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7225 /* ARM V5 breakpoint instruction (argument parse)
7226 BKPT <16 bit unsigned immediate>
7227 Instruction is not conditional.
7228 The bit pattern given in insns[] has the COND_ALWAYS condition,
7229 and it is an error if the caller tried to override that. */
7234 /* Top 12 of 16 bits to bits 19:8. */
7235 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7237 /* Bottom 4 of 16 bits to bits 3:0. */
7238 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7242 encode_branch (int default_reloc
)
7244 if (inst
.operands
[0].hasreloc
)
7246 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
7247 _("the only suffix valid here is '(plt)'"));
7248 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
7252 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7254 inst
.reloc
.pc_rel
= 1;
7261 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7262 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7265 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7272 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7274 if (inst
.cond
== COND_ALWAYS
)
7275 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7277 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7281 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7284 /* ARM V5 branch-link-exchange instruction (argument parse)
7285 BLX <target_addr> ie BLX(1)
7286 BLX{<condition>} <Rm> ie BLX(2)
7287 Unfortunately, there are two different opcodes for this mnemonic.
7288 So, the insns[].value is not used, and the code here zaps values
7289 into inst.instruction.
7290 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7295 if (inst
.operands
[0].isreg
)
7297 /* Arg is a register; the opcode provided by insns[] is correct.
7298 It is not illegal to do "blx pc", just useless. */
7299 if (inst
.operands
[0].reg
== REG_PC
)
7300 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7302 inst
.instruction
|= inst
.operands
[0].reg
;
7306 /* Arg is an address; this instruction cannot be executed
7307 conditionally, and the opcode must be adjusted.
7308 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7309 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7310 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7311 inst
.instruction
= 0xfa000000;
7312 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7319 bfd_boolean want_reloc
;
7321 if (inst
.operands
[0].reg
== REG_PC
)
7322 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7324 inst
.instruction
|= inst
.operands
[0].reg
;
7325 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7326 it is for ARMv4t or earlier. */
7327 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7328 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7332 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7337 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7341 /* ARM v5TEJ. Jump to Jazelle code. */
7346 if (inst
.operands
[0].reg
== REG_PC
)
7347 as_tsktsk (_("use of r15 in bxj is not really useful"));
7349 inst
.instruction
|= inst
.operands
[0].reg
;
7352 /* Co-processor data operation:
7353 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7354 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7358 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7359 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7360 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7361 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7362 inst
.instruction
|= inst
.operands
[4].reg
;
7363 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7369 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7370 encode_arm_shifter_operand (1);
7373 /* Transfer between coprocessor and ARM registers.
7374 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7379 No special properties. */
7386 Rd
= inst
.operands
[2].reg
;
7389 if (inst
.instruction
== 0xee000010
7390 || inst
.instruction
== 0xfe000010)
7392 reject_bad_reg (Rd
);
7395 constraint (Rd
== REG_SP
, BAD_SP
);
7400 if (inst
.instruction
== 0xe000010)
7401 constraint (Rd
== REG_PC
, BAD_PC
);
7405 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7406 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7407 inst
.instruction
|= Rd
<< 12;
7408 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7409 inst
.instruction
|= inst
.operands
[4].reg
;
7410 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7413 /* Transfer between coprocessor register and pair of ARM registers.
7414 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7419 Two XScale instructions are special cases of these:
7421 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7422 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7424 Result unpredictable if Rd or Rn is R15. */
7431 Rd
= inst
.operands
[2].reg
;
7432 Rn
= inst
.operands
[3].reg
;
7436 reject_bad_reg (Rd
);
7437 reject_bad_reg (Rn
);
7441 constraint (Rd
== REG_PC
, BAD_PC
);
7442 constraint (Rn
== REG_PC
, BAD_PC
);
7445 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7446 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7447 inst
.instruction
|= Rd
<< 12;
7448 inst
.instruction
|= Rn
<< 16;
7449 inst
.instruction
|= inst
.operands
[4].reg
;
7455 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7456 if (inst
.operands
[1].present
)
7458 inst
.instruction
|= CPSI_MMOD
;
7459 inst
.instruction
|= inst
.operands
[1].imm
;
7466 inst
.instruction
|= inst
.operands
[0].imm
;
7472 /* There is no IT instruction in ARM mode. We
7473 process it to do the validation as if in
7474 thumb mode, just in case the code gets
7475 assembled for thumb using the unified syntax. */
7480 set_it_insn_type (IT_INSN
);
7481 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7482 now_it
.cc
= inst
.operands
[0].imm
;
7489 int base_reg
= inst
.operands
[0].reg
;
7490 int range
= inst
.operands
[1].imm
;
7492 inst
.instruction
|= base_reg
<< 16;
7493 inst
.instruction
|= range
;
7495 if (inst
.operands
[1].writeback
)
7496 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7498 if (inst
.operands
[0].writeback
)
7500 inst
.instruction
|= WRITE_BACK
;
7501 /* Check for unpredictable uses of writeback. */
7502 if (inst
.instruction
& LOAD_BIT
)
7504 /* Not allowed in LDM type 2. */
7505 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7506 && ((range
& (1 << REG_PC
)) == 0))
7507 as_warn (_("writeback of base register is UNPREDICTABLE"));
7508 /* Only allowed if base reg not in list for other types. */
7509 else if (range
& (1 << base_reg
))
7510 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7514 /* Not allowed for type 2. */
7515 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7516 as_warn (_("writeback of base register is UNPREDICTABLE"));
7517 /* Only allowed if base reg not in list, or first in list. */
7518 else if ((range
& (1 << base_reg
))
7519 && (range
& ((1 << base_reg
) - 1)))
7520 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7525 /* ARMv5TE load-consecutive (argument parse)
7534 constraint (inst
.operands
[0].reg
% 2 != 0,
7535 _("first destination register must be even"));
7536 constraint (inst
.operands
[1].present
7537 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7538 _("can only load two consecutive registers"));
7539 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7540 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7542 if (!inst
.operands
[1].present
)
7543 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7545 if (inst
.instruction
& LOAD_BIT
)
7547 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7548 register and the first register written; we have to diagnose
7549 overlap between the base and the second register written here. */
7551 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7552 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7553 as_warn (_("base register written back, and overlaps "
7554 "second destination register"));
7556 /* For an index-register load, the index register must not overlap the
7557 destination (even if not write-back). */
7558 else if (inst
.operands
[2].immisreg
7559 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7560 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7561 as_warn (_("index register overlaps destination register"));
7564 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7565 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7571 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7572 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7573 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7574 || inst
.operands
[1].negative
7575 /* This can arise if the programmer has written
7577 or if they have mistakenly used a register name as the last
7580 It is very difficult to distinguish between these two cases
7581 because "rX" might actually be a label. ie the register
7582 name has been occluded by a symbol of the same name. So we
7583 just generate a general 'bad addressing mode' type error
7584 message and leave it up to the programmer to discover the
7585 true cause and fix their mistake. */
7586 || (inst
.operands
[1].reg
== REG_PC
),
7589 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7590 || inst
.reloc
.exp
.X_add_number
!= 0,
7591 _("offset must be zero in ARM encoding"));
7593 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7595 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7596 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7597 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7603 constraint (inst
.operands
[0].reg
% 2 != 0,
7604 _("even register required"));
7605 constraint (inst
.operands
[1].present
7606 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7607 _("can only load two consecutive registers"));
7608 /* If op 1 were present and equal to PC, this function wouldn't
7609 have been called in the first place. */
7610 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7612 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7613 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7619 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7620 if (!inst
.operands
[1].isreg
)
7621 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7623 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7629 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7631 if (inst
.operands
[1].preind
)
7633 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7634 || inst
.reloc
.exp
.X_add_number
!= 0,
7635 _("this instruction requires a post-indexed address"));
7637 inst
.operands
[1].preind
= 0;
7638 inst
.operands
[1].postind
= 1;
7639 inst
.operands
[1].writeback
= 1;
7641 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7642 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7645 /* Halfword and signed-byte load/store operations. */
7650 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7652 if (!inst
.operands
[1].isreg
)
7653 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7655 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7661 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7663 if (inst
.operands
[1].preind
)
7665 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7666 || inst
.reloc
.exp
.X_add_number
!= 0,
7667 _("this instruction requires a post-indexed address"));
7669 inst
.operands
[1].preind
= 0;
7670 inst
.operands
[1].postind
= 1;
7671 inst
.operands
[1].writeback
= 1;
7673 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7674 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7677 /* Co-processor register load/store.
7678 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7682 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7683 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7684 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7690 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7691 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7692 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7693 && !(inst
.instruction
& 0x00400000))
7694 as_tsktsk (_("Rd and Rm should be different in mla"));
7696 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7697 inst
.instruction
|= inst
.operands
[1].reg
;
7698 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7699 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7705 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7706 encode_arm_shifter_operand (1);
7709 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7716 top
= (inst
.instruction
& 0x00400000) != 0;
7717 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7718 _(":lower16: not allowed this instruction"));
7719 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7720 _(":upper16: not allowed instruction"));
7721 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7722 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7724 imm
= inst
.reloc
.exp
.X_add_number
;
7725 /* The value is in two pieces: 0:11, 16:19. */
7726 inst
.instruction
|= (imm
& 0x00000fff);
7727 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7731 static void do_vfp_nsyn_opcode (const char *);
7734 do_vfp_nsyn_mrs (void)
7736 if (inst
.operands
[0].isvec
)
7738 if (inst
.operands
[1].reg
!= 1)
7739 first_error (_("operand 1 must be FPSCR"));
7740 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7741 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7742 do_vfp_nsyn_opcode ("fmstat");
7744 else if (inst
.operands
[1].isvec
)
7745 do_vfp_nsyn_opcode ("fmrx");
7753 do_vfp_nsyn_msr (void)
7755 if (inst
.operands
[0].isvec
)
7756 do_vfp_nsyn_opcode ("fmxr");
7766 unsigned Rt
= inst
.operands
[0].reg
;
7768 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
7770 inst
.error
= BAD_SP
;
7774 /* APSR_ sets isvec. All other refs to PC are illegal. */
7775 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
7777 inst
.error
= BAD_PC
;
7781 if (inst
.operands
[1].reg
!= 1)
7782 first_error (_("operand 1 must be FPSCR"));
7784 inst
.instruction
|= (Rt
<< 12);
7790 unsigned Rt
= inst
.operands
[1].reg
;
7793 reject_bad_reg (Rt
);
7794 else if (Rt
== REG_PC
)
7796 inst
.error
= BAD_PC
;
7800 if (inst
.operands
[0].reg
!= 1)
7801 first_error (_("operand 0 must be FPSCR"));
7803 inst
.instruction
|= (Rt
<< 12);
7809 if (do_vfp_nsyn_mrs () == SUCCESS
)
7812 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7813 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7815 _("'CPSR' or 'SPSR' expected"));
7816 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7817 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7818 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7821 /* Two possible forms:
7822 "{C|S}PSR_<field>, Rm",
7823 "{C|S}PSR_f, #expression". */
7828 if (do_vfp_nsyn_msr () == SUCCESS
)
7831 inst
.instruction
|= inst
.operands
[0].imm
;
7832 if (inst
.operands
[1].isreg
)
7833 inst
.instruction
|= inst
.operands
[1].reg
;
7836 inst
.instruction
|= INST_IMMEDIATE
;
7837 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7838 inst
.reloc
.pc_rel
= 0;
7845 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
7847 if (!inst
.operands
[2].present
)
7848 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7849 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7850 inst
.instruction
|= inst
.operands
[1].reg
;
7851 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7853 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7854 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7855 as_tsktsk (_("Rd and Rm should be different in mul"));
7858 /* Long Multiply Parser
7859 UMULL RdLo, RdHi, Rm, Rs
7860 SMULL RdLo, RdHi, Rm, Rs
7861 UMLAL RdLo, RdHi, Rm, Rs
7862 SMLAL RdLo, RdHi, Rm, Rs. */
7867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7868 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7869 inst
.instruction
|= inst
.operands
[2].reg
;
7870 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7872 /* rdhi and rdlo must be different. */
7873 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7874 as_tsktsk (_("rdhi and rdlo must be different"));
7876 /* rdhi, rdlo and rm must all be different before armv6. */
7877 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7878 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7879 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7880 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7886 if (inst
.operands
[0].present
7887 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
7889 /* Architectural NOP hints are CPSR sets with no bits selected. */
7890 inst
.instruction
&= 0xf0000000;
7891 inst
.instruction
|= 0x0320f000;
7892 if (inst
.operands
[0].present
)
7893 inst
.instruction
|= inst
.operands
[0].imm
;
7897 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7898 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7899 Condition defaults to COND_ALWAYS.
7900 Error if Rd, Rn or Rm are R15. */
7905 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7906 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7907 inst
.instruction
|= inst
.operands
[2].reg
;
7908 if (inst
.operands
[3].present
)
7909 encode_arm_shift (3);
7912 /* ARM V6 PKHTB (Argument Parse). */
7917 if (!inst
.operands
[3].present
)
7919 /* If the shift specifier is omitted, turn the instruction
7920 into pkhbt rd, rm, rn. */
7921 inst
.instruction
&= 0xfff00010;
7922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7923 inst
.instruction
|= inst
.operands
[1].reg
;
7924 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7928 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7929 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7930 inst
.instruction
|= inst
.operands
[2].reg
;
7931 encode_arm_shift (3);
7935 /* ARMv5TE: Preload-Cache
7939 Syntactically, like LDR with B=1, W=0, L=1. */
7944 constraint (!inst
.operands
[0].isreg
,
7945 _("'[' expected after PLD mnemonic"));
7946 constraint (inst
.operands
[0].postind
,
7947 _("post-indexed expression used in preload instruction"));
7948 constraint (inst
.operands
[0].writeback
,
7949 _("writeback used in preload instruction"));
7950 constraint (!inst
.operands
[0].preind
,
7951 _("unindexed addressing used in preload instruction"));
7952 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7955 /* ARMv7: PLI <addr_mode> */
7959 constraint (!inst
.operands
[0].isreg
,
7960 _("'[' expected after PLI mnemonic"));
7961 constraint (inst
.operands
[0].postind
,
7962 _("post-indexed expression used in preload instruction"));
7963 constraint (inst
.operands
[0].writeback
,
7964 _("writeback used in preload instruction"));
7965 constraint (!inst
.operands
[0].preind
,
7966 _("unindexed addressing used in preload instruction"));
7967 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7968 inst
.instruction
&= ~PRE_INDEX
;
7974 inst
.operands
[1] = inst
.operands
[0];
7975 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7976 inst
.operands
[0].isreg
= 1;
7977 inst
.operands
[0].writeback
= 1;
7978 inst
.operands
[0].reg
= REG_SP
;
7982 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7983 word at the specified address and the following word
7985 Unconditionally executed.
7986 Error if Rn is R15. */
7991 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7992 if (inst
.operands
[0].writeback
)
7993 inst
.instruction
|= WRITE_BACK
;
7996 /* ARM V6 ssat (argument parse). */
8001 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8002 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8003 inst
.instruction
|= inst
.operands
[2].reg
;
8005 if (inst
.operands
[3].present
)
8006 encode_arm_shift (3);
8009 /* ARM V6 usat (argument parse). */
8014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8015 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8016 inst
.instruction
|= inst
.operands
[2].reg
;
8018 if (inst
.operands
[3].present
)
8019 encode_arm_shift (3);
8022 /* ARM V6 ssat16 (argument parse). */
8027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8028 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8029 inst
.instruction
|= inst
.operands
[2].reg
;
8035 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8036 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8037 inst
.instruction
|= inst
.operands
[2].reg
;
8040 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8041 preserving the other bits.
8043 setend <endian_specifier>, where <endian_specifier> is either
8049 if (inst
.operands
[0].imm
)
8050 inst
.instruction
|= 0x200;
8056 unsigned int Rm
= (inst
.operands
[1].present
8057 ? inst
.operands
[1].reg
8058 : inst
.operands
[0].reg
);
8060 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8061 inst
.instruction
|= Rm
;
8062 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8064 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8065 inst
.instruction
|= SHIFT_BY_REG
;
8068 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8074 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8075 inst
.reloc
.pc_rel
= 0;
8081 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8082 inst
.reloc
.pc_rel
= 0;
8085 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8086 SMLAxy{cond} Rd,Rm,Rs,Rn
8087 SMLAWy{cond} Rd,Rm,Rs,Rn
8088 Error if any register is R15. */
8093 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8094 inst
.instruction
|= inst
.operands
[1].reg
;
8095 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8096 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8099 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8100 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8101 Error if any register is R15.
8102 Warning if Rdlo == Rdhi. */
8107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8108 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8109 inst
.instruction
|= inst
.operands
[2].reg
;
8110 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8112 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8113 as_tsktsk (_("rdhi and rdlo must be different"));
8116 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8117 SMULxy{cond} Rd,Rm,Rs
8118 Error if any register is R15. */
8123 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8124 inst
.instruction
|= inst
.operands
[1].reg
;
8125 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8128 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8129 the same for both ARM and Thumb-2. */
8136 if (inst
.operands
[0].present
)
8138 reg
= inst
.operands
[0].reg
;
8139 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8144 inst
.instruction
|= reg
<< 16;
8145 inst
.instruction
|= inst
.operands
[1].imm
;
8146 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8147 inst
.instruction
|= WRITE_BACK
;
8150 /* ARM V6 strex (argument parse). */
8155 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8156 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8157 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8158 || inst
.operands
[2].negative
8159 /* See comment in do_ldrex(). */
8160 || (inst
.operands
[2].reg
== REG_PC
),
8163 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8164 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8166 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8167 || inst
.reloc
.exp
.X_add_number
!= 0,
8168 _("offset must be zero in ARM encoding"));
8170 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8171 inst
.instruction
|= inst
.operands
[1].reg
;
8172 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8173 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8179 constraint (inst
.operands
[1].reg
% 2 != 0,
8180 _("even register required"));
8181 constraint (inst
.operands
[2].present
8182 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8183 _("can only store two consecutive registers"));
8184 /* If op 2 were present and equal to PC, this function wouldn't
8185 have been called in the first place. */
8186 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8188 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8189 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8190 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8193 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8194 inst
.instruction
|= inst
.operands
[1].reg
;
8195 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8198 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8199 extends it to 32-bits, and adds the result to a value in another
8200 register. You can specify a rotation by 0, 8, 16, or 24 bits
8201 before extracting the 16-bit value.
8202 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8203 Condition defaults to COND_ALWAYS.
8204 Error if any register uses R15. */
8209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8210 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8211 inst
.instruction
|= inst
.operands
[2].reg
;
8212 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8217 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8218 Condition defaults to COND_ALWAYS.
8219 Error if any register uses R15. */
8224 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8225 inst
.instruction
|= inst
.operands
[1].reg
;
8226 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8229 /* VFP instructions. In a logical order: SP variant first, monad
8230 before dyad, arithmetic then move then load/store. */
8233 do_vfp_sp_monadic (void)
8235 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8236 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8240 do_vfp_sp_dyadic (void)
8242 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8243 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8244 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8248 do_vfp_sp_compare_z (void)
8250 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8254 do_vfp_dp_sp_cvt (void)
8256 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8257 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8261 do_vfp_sp_dp_cvt (void)
8263 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8264 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8268 do_vfp_reg_from_sp (void)
8270 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8271 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8275 do_vfp_reg2_from_sp2 (void)
8277 constraint (inst
.operands
[2].imm
!= 2,
8278 _("only two consecutive VFP SP registers allowed here"));
8279 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8280 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8281 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8285 do_vfp_sp_from_reg (void)
8287 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8288 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8292 do_vfp_sp2_from_reg2 (void)
8294 constraint (inst
.operands
[0].imm
!= 2,
8295 _("only two consecutive VFP SP registers allowed here"));
8296 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8297 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8298 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8302 do_vfp_sp_ldst (void)
8304 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8305 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8309 do_vfp_dp_ldst (void)
8311 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8312 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8317 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8319 if (inst
.operands
[0].writeback
)
8320 inst
.instruction
|= WRITE_BACK
;
8322 constraint (ldstm_type
!= VFP_LDSTMIA
,
8323 _("this addressing mode requires base-register writeback"));
8324 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8325 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8326 inst
.instruction
|= inst
.operands
[1].imm
;
8330 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8334 if (inst
.operands
[0].writeback
)
8335 inst
.instruction
|= WRITE_BACK
;
8337 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8338 _("this addressing mode requires base-register writeback"));
8340 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8341 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8343 count
= inst
.operands
[1].imm
<< 1;
8344 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8347 inst
.instruction
|= count
;
8351 do_vfp_sp_ldstmia (void)
8353 vfp_sp_ldstm (VFP_LDSTMIA
);
8357 do_vfp_sp_ldstmdb (void)
8359 vfp_sp_ldstm (VFP_LDSTMDB
);
8363 do_vfp_dp_ldstmia (void)
8365 vfp_dp_ldstm (VFP_LDSTMIA
);
8369 do_vfp_dp_ldstmdb (void)
8371 vfp_dp_ldstm (VFP_LDSTMDB
);
8375 do_vfp_xp_ldstmia (void)
8377 vfp_dp_ldstm (VFP_LDSTMIAX
);
8381 do_vfp_xp_ldstmdb (void)
8383 vfp_dp_ldstm (VFP_LDSTMDBX
);
8387 do_vfp_dp_rd_rm (void)
8389 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8390 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8394 do_vfp_dp_rn_rd (void)
8396 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8397 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8401 do_vfp_dp_rd_rn (void)
8403 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8404 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8408 do_vfp_dp_rd_rn_rm (void)
8410 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8411 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8412 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8418 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8422 do_vfp_dp_rm_rd_rn (void)
8424 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8425 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8426 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8429 /* VFPv3 instructions. */
8431 do_vfp_sp_const (void)
8433 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8434 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8435 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8439 do_vfp_dp_const (void)
8441 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8442 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8443 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8447 vfp_conv (int srcsize
)
8449 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
8450 inst
.instruction
|= (immbits
& 1) << 5;
8451 inst
.instruction
|= (immbits
>> 1);
8455 do_vfp_sp_conv_16 (void)
8457 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8462 do_vfp_dp_conv_16 (void)
8464 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8469 do_vfp_sp_conv_32 (void)
8471 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8476 do_vfp_dp_conv_32 (void)
8478 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8482 /* FPA instructions. Also in a logical order. */
8487 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8488 inst
.instruction
|= inst
.operands
[1].reg
;
8492 do_fpa_ldmstm (void)
8494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8495 switch (inst
.operands
[1].imm
)
8497 case 1: inst
.instruction
|= CP_T_X
; break;
8498 case 2: inst
.instruction
|= CP_T_Y
; break;
8499 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8504 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8506 /* The instruction specified "ea" or "fd", so we can only accept
8507 [Rn]{!}. The instruction does not really support stacking or
8508 unstacking, so we have to emulate these by setting appropriate
8509 bits and offsets. */
8510 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8511 || inst
.reloc
.exp
.X_add_number
!= 0,
8512 _("this instruction does not support indexing"));
8514 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8515 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8517 if (!(inst
.instruction
& INDEX_UP
))
8518 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8520 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8522 inst
.operands
[2].preind
= 0;
8523 inst
.operands
[2].postind
= 1;
8527 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8530 /* iWMMXt instructions: strictly in alphabetical order. */
8533 do_iwmmxt_tandorc (void)
8535 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8539 do_iwmmxt_textrc (void)
8541 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8542 inst
.instruction
|= inst
.operands
[1].imm
;
8546 do_iwmmxt_textrm (void)
8548 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8549 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8550 inst
.instruction
|= inst
.operands
[2].imm
;
8554 do_iwmmxt_tinsr (void)
8556 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8557 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8558 inst
.instruction
|= inst
.operands
[2].imm
;
8562 do_iwmmxt_tmia (void)
8564 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8565 inst
.instruction
|= inst
.operands
[1].reg
;
8566 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8570 do_iwmmxt_waligni (void)
8572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8573 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8574 inst
.instruction
|= inst
.operands
[2].reg
;
8575 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8579 do_iwmmxt_wmerge (void)
8581 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8582 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8583 inst
.instruction
|= inst
.operands
[2].reg
;
8584 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8588 do_iwmmxt_wmov (void)
8590 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8591 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8592 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8593 inst
.instruction
|= inst
.operands
[1].reg
;
8597 do_iwmmxt_wldstbh (void)
8600 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8602 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8604 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8605 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8609 do_iwmmxt_wldstw (void)
8611 /* RIWR_RIWC clears .isreg for a control register. */
8612 if (!inst
.operands
[0].isreg
)
8614 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8615 inst
.instruction
|= 0xf0000000;
8618 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8619 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8623 do_iwmmxt_wldstd (void)
8625 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8626 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8627 && inst
.operands
[1].immisreg
)
8629 inst
.instruction
&= ~0x1a000ff;
8630 inst
.instruction
|= (0xf << 28);
8631 if (inst
.operands
[1].preind
)
8632 inst
.instruction
|= PRE_INDEX
;
8633 if (!inst
.operands
[1].negative
)
8634 inst
.instruction
|= INDEX_UP
;
8635 if (inst
.operands
[1].writeback
)
8636 inst
.instruction
|= WRITE_BACK
;
8637 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8638 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8639 inst
.instruction
|= inst
.operands
[1].imm
;
8642 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8646 do_iwmmxt_wshufh (void)
8648 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8649 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8650 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8651 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8655 do_iwmmxt_wzero (void)
8657 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8658 inst
.instruction
|= inst
.operands
[0].reg
;
8659 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8660 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8664 do_iwmmxt_wrwrwr_or_imm5 (void)
8666 if (inst
.operands
[2].isreg
)
8669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8670 _("immediate operand requires iWMMXt2"));
8672 if (inst
.operands
[2].imm
== 0)
8674 switch ((inst
.instruction
>> 20) & 0xf)
8680 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8681 inst
.operands
[2].imm
= 16;
8682 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8688 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8689 inst
.operands
[2].imm
= 32;
8690 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8697 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8699 wrn
= (inst
.instruction
>> 16) & 0xf;
8700 inst
.instruction
&= 0xff0fff0f;
8701 inst
.instruction
|= wrn
;
8702 /* Bail out here; the instruction is now assembled. */
8707 /* Map 32 -> 0, etc. */
8708 inst
.operands
[2].imm
&= 0x1f;
8709 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8713 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8714 operations first, then control, shift, and load/store. */
8716 /* Insns like "foo X,Y,Z". */
8719 do_mav_triple (void)
8721 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8722 inst
.instruction
|= inst
.operands
[1].reg
;
8723 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8726 /* Insns like "foo W,X,Y,Z".
8727 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8732 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8733 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8734 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8735 inst
.instruction
|= inst
.operands
[3].reg
;
8738 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8742 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8745 /* Maverick shift immediate instructions.
8746 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8747 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8752 int imm
= inst
.operands
[2].imm
;
8754 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8755 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8757 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8758 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8759 Bit 4 should be 0. */
8760 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8762 inst
.instruction
|= imm
;
8765 /* XScale instructions. Also sorted arithmetic before move. */
8767 /* Xscale multiply-accumulate (argument parse)
8770 MIAxycc acc0,Rm,Rs. */
8775 inst
.instruction
|= inst
.operands
[1].reg
;
8776 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8779 /* Xscale move-accumulator-register (argument parse)
8781 MARcc acc0,RdLo,RdHi. */
8786 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8787 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8790 /* Xscale move-register-accumulator (argument parse)
8792 MRAcc RdLo,RdHi,acc0. */
8797 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8798 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8799 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8802 /* Encoding functions relevant only to Thumb. */
8804 /* inst.operands[i] is a shifted-register operand; encode
8805 it into inst.instruction in the format used by Thumb32. */
8808 encode_thumb32_shifted_operand (int i
)
8810 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8811 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8813 constraint (inst
.operands
[i
].immisreg
,
8814 _("shift by register not allowed in thumb mode"));
8815 inst
.instruction
|= inst
.operands
[i
].reg
;
8816 if (shift
== SHIFT_RRX
)
8817 inst
.instruction
|= SHIFT_ROR
<< 4;
8820 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8821 _("expression too complex"));
8823 constraint (value
> 32
8824 || (value
== 32 && (shift
== SHIFT_LSL
8825 || shift
== SHIFT_ROR
)),
8826 _("shift expression is too large"));
8830 else if (value
== 32)
8833 inst
.instruction
|= shift
<< 4;
8834 inst
.instruction
|= (value
& 0x1c) << 10;
8835 inst
.instruction
|= (value
& 0x03) << 6;
8840 /* inst.operands[i] was set up by parse_address. Encode it into a
8841 Thumb32 format load or store instruction. Reject forms that cannot
8842 be used with such instructions. If is_t is true, reject forms that
8843 cannot be used with a T instruction; if is_d is true, reject forms
8844 that cannot be used with a D instruction. If it is a store insn,
8848 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8850 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8852 constraint (!inst
.operands
[i
].isreg
,
8853 _("Instruction does not support =N addresses"));
8855 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8856 if (inst
.operands
[i
].immisreg
)
8858 constraint (is_pc
, BAD_PC_ADDRESSING
);
8859 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8860 constraint (inst
.operands
[i
].negative
,
8861 _("Thumb does not support negative register indexing"));
8862 constraint (inst
.operands
[i
].postind
,
8863 _("Thumb does not support register post-indexing"));
8864 constraint (inst
.operands
[i
].writeback
,
8865 _("Thumb does not support register indexing with writeback"));
8866 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8867 _("Thumb supports only LSL in shifted register indexing"));
8869 inst
.instruction
|= inst
.operands
[i
].imm
;
8870 if (inst
.operands
[i
].shifted
)
8872 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8873 _("expression too complex"));
8874 constraint (inst
.reloc
.exp
.X_add_number
< 0
8875 || inst
.reloc
.exp
.X_add_number
> 3,
8876 _("shift out of range"));
8877 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8879 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8881 else if (inst
.operands
[i
].preind
)
8883 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
8884 constraint (is_t
&& inst
.operands
[i
].writeback
,
8885 _("cannot use writeback with this instruction"));
8886 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
8887 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
8891 inst
.instruction
|= 0x01000000;
8892 if (inst
.operands
[i
].writeback
)
8893 inst
.instruction
|= 0x00200000;
8897 inst
.instruction
|= 0x00000c00;
8898 if (inst
.operands
[i
].writeback
)
8899 inst
.instruction
|= 0x00000100;
8901 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8903 else if (inst
.operands
[i
].postind
)
8905 gas_assert (inst
.operands
[i
].writeback
);
8906 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8907 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8910 inst
.instruction
|= 0x00200000;
8912 inst
.instruction
|= 0x00000900;
8913 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8915 else /* unindexed - only for coprocessor */
8916 inst
.error
= _("instruction does not accept unindexed addressing");
8919 /* Table of Thumb instructions which exist in both 16- and 32-bit
8920 encodings (the latter only in post-V6T2 cores). The index is the
8921 value used in the insns table below. When there is more than one
8922 possible 16-bit encoding for the instruction, this table always
8924 Also contains several pseudo-instructions used during relaxation. */
8925 #define T16_32_TAB \
8926 X(_adc, 4140, eb400000), \
8927 X(_adcs, 4140, eb500000), \
8928 X(_add, 1c00, eb000000), \
8929 X(_adds, 1c00, eb100000), \
8930 X(_addi, 0000, f1000000), \
8931 X(_addis, 0000, f1100000), \
8932 X(_add_pc,000f, f20f0000), \
8933 X(_add_sp,000d, f10d0000), \
8934 X(_adr, 000f, f20f0000), \
8935 X(_and, 4000, ea000000), \
8936 X(_ands, 4000, ea100000), \
8937 X(_asr, 1000, fa40f000), \
8938 X(_asrs, 1000, fa50f000), \
8939 X(_b, e000, f000b000), \
8940 X(_bcond, d000, f0008000), \
8941 X(_bic, 4380, ea200000), \
8942 X(_bics, 4380, ea300000), \
8943 X(_cmn, 42c0, eb100f00), \
8944 X(_cmp, 2800, ebb00f00), \
8945 X(_cpsie, b660, f3af8400), \
8946 X(_cpsid, b670, f3af8600), \
8947 X(_cpy, 4600, ea4f0000), \
8948 X(_dec_sp,80dd, f1ad0d00), \
8949 X(_eor, 4040, ea800000), \
8950 X(_eors, 4040, ea900000), \
8951 X(_inc_sp,00dd, f10d0d00), \
8952 X(_ldmia, c800, e8900000), \
8953 X(_ldr, 6800, f8500000), \
8954 X(_ldrb, 7800, f8100000), \
8955 X(_ldrh, 8800, f8300000), \
8956 X(_ldrsb, 5600, f9100000), \
8957 X(_ldrsh, 5e00, f9300000), \
8958 X(_ldr_pc,4800, f85f0000), \
8959 X(_ldr_pc2,4800, f85f0000), \
8960 X(_ldr_sp,9800, f85d0000), \
8961 X(_lsl, 0000, fa00f000), \
8962 X(_lsls, 0000, fa10f000), \
8963 X(_lsr, 0800, fa20f000), \
8964 X(_lsrs, 0800, fa30f000), \
8965 X(_mov, 2000, ea4f0000), \
8966 X(_movs, 2000, ea5f0000), \
8967 X(_mul, 4340, fb00f000), \
8968 X(_muls, 4340, ffffffff), /* no 32b muls */ \
8969 X(_mvn, 43c0, ea6f0000), \
8970 X(_mvns, 43c0, ea7f0000), \
8971 X(_neg, 4240, f1c00000), /* rsb #0 */ \
8972 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
8973 X(_orr, 4300, ea400000), \
8974 X(_orrs, 4300, ea500000), \
8975 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8976 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
8977 X(_rev, ba00, fa90f080), \
8978 X(_rev16, ba40, fa90f090), \
8979 X(_revsh, bac0, fa90f0b0), \
8980 X(_ror, 41c0, fa60f000), \
8981 X(_rors, 41c0, fa70f000), \
8982 X(_sbc, 4180, eb600000), \
8983 X(_sbcs, 4180, eb700000), \
8984 X(_stmia, c000, e8800000), \
8985 X(_str, 6000, f8400000), \
8986 X(_strb, 7000, f8000000), \
8987 X(_strh, 8000, f8200000), \
8988 X(_str_sp,9000, f84d0000), \
8989 X(_sub, 1e00, eba00000), \
8990 X(_subs, 1e00, ebb00000), \
8991 X(_subi, 8000, f1a00000), \
8992 X(_subis, 8000, f1b00000), \
8993 X(_sxtb, b240, fa4ff080), \
8994 X(_sxth, b200, fa0ff080), \
8995 X(_tst, 4200, ea100f00), \
8996 X(_uxtb, b2c0, fa5ff080), \
8997 X(_uxth, b280, fa1ff080), \
8998 X(_nop, bf00, f3af8000), \
8999 X(_yield, bf10, f3af8001), \
9000 X(_wfe, bf20, f3af8002), \
9001 X(_wfi, bf30, f3af8003), \
9002 X(_sev, bf40, f3af8004),
9004 /* To catch errors in encoding functions, the codes are all offset by
9005 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9006 as 16-bit instructions. */
9007 #define X(a,b,c) T_MNEM##a
9008 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9011 #define X(a,b,c) 0x##b
9012 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9013 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9016 #define X(a,b,c) 0x##c
9017 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9018 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9019 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9023 /* Thumb instruction encoders, in alphabetical order. */
9028 do_t_add_sub_w (void)
9032 Rd
= inst
.operands
[0].reg
;
9033 Rn
= inst
.operands
[1].reg
;
9035 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9036 is the SP-{plus,minus}-immediate form of the instruction. */
9038 constraint (Rd
== REG_PC
, BAD_PC
);
9040 reject_bad_reg (Rd
);
9042 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9043 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9046 /* Parse an add or subtract instruction. We get here with inst.instruction
9047 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9054 Rd
= inst
.operands
[0].reg
;
9055 Rs
= (inst
.operands
[1].present
9056 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9057 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9060 set_it_insn_type_last ();
9068 flags
= (inst
.instruction
== T_MNEM_adds
9069 || inst
.instruction
== T_MNEM_subs
);
9071 narrow
= !in_it_block ();
9073 narrow
= in_it_block ();
9074 if (!inst
.operands
[2].isreg
)
9078 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9080 add
= (inst
.instruction
== T_MNEM_add
9081 || inst
.instruction
== T_MNEM_adds
);
9083 if (inst
.size_req
!= 4)
9085 /* Attempt to use a narrow opcode, with relaxation if
9087 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9088 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9089 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9090 opcode
= T_MNEM_add_sp
;
9091 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9092 opcode
= T_MNEM_add_pc
;
9093 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9096 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9098 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9102 inst
.instruction
= THUMB_OP16(opcode
);
9103 inst
.instruction
|= (Rd
<< 4) | Rs
;
9104 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9105 if (inst
.size_req
!= 2)
9106 inst
.relax
= opcode
;
9109 constraint (inst
.size_req
== 2, BAD_HIREG
);
9111 if (inst
.size_req
== 4
9112 || (inst
.size_req
!= 2 && !opcode
))
9116 constraint (add
, BAD_PC
);
9117 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9118 _("only SUBS PC, LR, #const allowed"));
9119 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9120 _("expression too complex"));
9121 constraint (inst
.reloc
.exp
.X_add_number
< 0
9122 || inst
.reloc
.exp
.X_add_number
> 0xff,
9123 _("immediate value out of range"));
9124 inst
.instruction
= T2_SUBS_PC_LR
9125 | inst
.reloc
.exp
.X_add_number
;
9126 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9129 else if (Rs
== REG_PC
)
9131 /* Always use addw/subw. */
9132 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9133 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9137 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9138 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9141 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9143 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9145 inst
.instruction
|= Rd
<< 8;
9146 inst
.instruction
|= Rs
<< 16;
9151 Rn
= inst
.operands
[2].reg
;
9152 /* See if we can do this with a 16-bit instruction. */
9153 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9155 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9160 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9161 || inst
.instruction
== T_MNEM_add
)
9164 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9168 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9170 /* Thumb-1 cores (except v6-M) require at least one high
9171 register in a narrow non flag setting add. */
9172 if (Rd
> 7 || Rn
> 7
9173 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9174 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9181 inst
.instruction
= T_OPCODE_ADD_HI
;
9182 inst
.instruction
|= (Rd
& 8) << 4;
9183 inst
.instruction
|= (Rd
& 7);
9184 inst
.instruction
|= Rn
<< 3;
9190 constraint (Rd
== REG_PC
, BAD_PC
);
9191 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9192 constraint (Rs
== REG_PC
, BAD_PC
);
9193 reject_bad_reg (Rn
);
9195 /* If we get here, it can't be done in 16 bits. */
9196 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9197 _("shift must be constant"));
9198 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9199 inst
.instruction
|= Rd
<< 8;
9200 inst
.instruction
|= Rs
<< 16;
9201 encode_thumb32_shifted_operand (2);
9206 constraint (inst
.instruction
== T_MNEM_adds
9207 || inst
.instruction
== T_MNEM_subs
,
9210 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9212 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9213 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9216 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9218 inst
.instruction
|= (Rd
<< 4) | Rs
;
9219 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9223 Rn
= inst
.operands
[2].reg
;
9224 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9226 /* We now have Rd, Rs, and Rn set to registers. */
9227 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9229 /* Can't do this for SUB. */
9230 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9231 inst
.instruction
= T_OPCODE_ADD_HI
;
9232 inst
.instruction
|= (Rd
& 8) << 4;
9233 inst
.instruction
|= (Rd
& 7);
9235 inst
.instruction
|= Rn
<< 3;
9237 inst
.instruction
|= Rs
<< 3;
9239 constraint (1, _("dest must overlap one source register"));
9243 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9244 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9245 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9255 Rd
= inst
.operands
[0].reg
;
9256 reject_bad_reg (Rd
);
9258 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9260 /* Defer to section relaxation. */
9261 inst
.relax
= inst
.instruction
;
9262 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9263 inst
.instruction
|= Rd
<< 4;
9265 else if (unified_syntax
&& inst
.size_req
!= 2)
9267 /* Generate a 32-bit opcode. */
9268 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9269 inst
.instruction
|= Rd
<< 8;
9270 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9271 inst
.reloc
.pc_rel
= 1;
9275 /* Generate a 16-bit opcode. */
9276 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9277 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9278 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9279 inst
.reloc
.pc_rel
= 1;
9281 inst
.instruction
|= Rd
<< 4;
9285 /* Arithmetic instructions for which there is just one 16-bit
9286 instruction encoding, and it allows only two low registers.
9287 For maximal compatibility with ARM syntax, we allow three register
9288 operands even when Thumb-32 instructions are not available, as long
9289 as the first two are identical. For instance, both "sbc r0,r1" and
9290 "sbc r0,r0,r1" are allowed. */
9296 Rd
= inst
.operands
[0].reg
;
9297 Rs
= (inst
.operands
[1].present
9298 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9299 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9300 Rn
= inst
.operands
[2].reg
;
9302 reject_bad_reg (Rd
);
9303 reject_bad_reg (Rs
);
9304 if (inst
.operands
[2].isreg
)
9305 reject_bad_reg (Rn
);
9309 if (!inst
.operands
[2].isreg
)
9311 /* For an immediate, we always generate a 32-bit opcode;
9312 section relaxation will shrink it later if possible. */
9313 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9314 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9315 inst
.instruction
|= Rd
<< 8;
9316 inst
.instruction
|= Rs
<< 16;
9317 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9323 /* See if we can do this with a 16-bit instruction. */
9324 if (THUMB_SETS_FLAGS (inst
.instruction
))
9325 narrow
= !in_it_block ();
9327 narrow
= in_it_block ();
9329 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9331 if (inst
.operands
[2].shifted
)
9333 if (inst
.size_req
== 4)
9339 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9340 inst
.instruction
|= Rd
;
9341 inst
.instruction
|= Rn
<< 3;
9345 /* If we get here, it can't be done in 16 bits. */
9346 constraint (inst
.operands
[2].shifted
9347 && inst
.operands
[2].immisreg
,
9348 _("shift must be constant"));
9349 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9350 inst
.instruction
|= Rd
<< 8;
9351 inst
.instruction
|= Rs
<< 16;
9352 encode_thumb32_shifted_operand (2);
9357 /* On its face this is a lie - the instruction does set the
9358 flags. However, the only supported mnemonic in this mode
9360 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9362 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9363 _("unshifted register required"));
9364 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9365 constraint (Rd
!= Rs
,
9366 _("dest and source1 must be the same register"));
9368 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9369 inst
.instruction
|= Rd
;
9370 inst
.instruction
|= Rn
<< 3;
9374 /* Similarly, but for instructions where the arithmetic operation is
9375 commutative, so we can allow either of them to be different from
9376 the destination operand in a 16-bit instruction. For instance, all
9377 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9384 Rd
= inst
.operands
[0].reg
;
9385 Rs
= (inst
.operands
[1].present
9386 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9387 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9388 Rn
= inst
.operands
[2].reg
;
9390 reject_bad_reg (Rd
);
9391 reject_bad_reg (Rs
);
9392 if (inst
.operands
[2].isreg
)
9393 reject_bad_reg (Rn
);
9397 if (!inst
.operands
[2].isreg
)
9399 /* For an immediate, we always generate a 32-bit opcode;
9400 section relaxation will shrink it later if possible. */
9401 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9402 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9403 inst
.instruction
|= Rd
<< 8;
9404 inst
.instruction
|= Rs
<< 16;
9405 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9411 /* See if we can do this with a 16-bit instruction. */
9412 if (THUMB_SETS_FLAGS (inst
.instruction
))
9413 narrow
= !in_it_block ();
9415 narrow
= in_it_block ();
9417 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9419 if (inst
.operands
[2].shifted
)
9421 if (inst
.size_req
== 4)
9428 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9429 inst
.instruction
|= Rd
;
9430 inst
.instruction
|= Rn
<< 3;
9435 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9436 inst
.instruction
|= Rd
;
9437 inst
.instruction
|= Rs
<< 3;
9442 /* If we get here, it can't be done in 16 bits. */
9443 constraint (inst
.operands
[2].shifted
9444 && inst
.operands
[2].immisreg
,
9445 _("shift must be constant"));
9446 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9447 inst
.instruction
|= Rd
<< 8;
9448 inst
.instruction
|= Rs
<< 16;
9449 encode_thumb32_shifted_operand (2);
9454 /* On its face this is a lie - the instruction does set the
9455 flags. However, the only supported mnemonic in this mode
9457 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9459 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9460 _("unshifted register required"));
9461 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9463 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9464 inst
.instruction
|= Rd
;
9467 inst
.instruction
|= Rn
<< 3;
9469 inst
.instruction
|= Rs
<< 3;
9471 constraint (1, _("dest must overlap one source register"));
9478 if (inst
.operands
[0].present
)
9480 constraint ((inst
.instruction
& 0xf0) != 0x40
9481 && inst
.operands
[0].imm
> 0xf
9482 && inst
.operands
[0].imm
< 0x0,
9483 _("bad barrier type"));
9484 inst
.instruction
|= inst
.operands
[0].imm
;
9487 inst
.instruction
|= 0xf;
9494 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9495 constraint (msb
> 32, _("bit-field extends past end of register"));
9496 /* The instruction encoding stores the LSB and MSB,
9497 not the LSB and width. */
9498 Rd
= inst
.operands
[0].reg
;
9499 reject_bad_reg (Rd
);
9500 inst
.instruction
|= Rd
<< 8;
9501 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9502 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9503 inst
.instruction
|= msb
- 1;
9512 Rd
= inst
.operands
[0].reg
;
9513 reject_bad_reg (Rd
);
9515 /* #0 in second position is alternative syntax for bfc, which is
9516 the same instruction but with REG_PC in the Rm field. */
9517 if (!inst
.operands
[1].isreg
)
9521 Rn
= inst
.operands
[1].reg
;
9522 reject_bad_reg (Rn
);
9525 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9526 constraint (msb
> 32, _("bit-field extends past end of register"));
9527 /* The instruction encoding stores the LSB and MSB,
9528 not the LSB and width. */
9529 inst
.instruction
|= Rd
<< 8;
9530 inst
.instruction
|= Rn
<< 16;
9531 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9532 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9533 inst
.instruction
|= msb
- 1;
9541 Rd
= inst
.operands
[0].reg
;
9542 Rn
= inst
.operands
[1].reg
;
9544 reject_bad_reg (Rd
);
9545 reject_bad_reg (Rn
);
9547 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9548 _("bit-field extends past end of register"));
9549 inst
.instruction
|= Rd
<< 8;
9550 inst
.instruction
|= Rn
<< 16;
9551 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9552 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9553 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9556 /* ARM V5 Thumb BLX (argument parse)
9557 BLX <target_addr> which is BLX(1)
9558 BLX <Rm> which is BLX(2)
9559 Unfortunately, there are two different opcodes for this mnemonic.
9560 So, the insns[].value is not used, and the code here zaps values
9561 into inst.instruction.
9563 ??? How to take advantage of the additional two bits of displacement
9564 available in Thumb32 mode? Need new relocation? */
9569 set_it_insn_type_last ();
9571 if (inst
.operands
[0].isreg
)
9573 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9574 /* We have a register, so this is BLX(2). */
9575 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9579 /* No register. This must be BLX(1). */
9580 inst
.instruction
= 0xf000e800;
9581 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9582 inst
.reloc
.pc_rel
= 1;
9593 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9597 /* Conditional branches inside IT blocks are encoded as unconditional
9604 if (cond
!= COND_ALWAYS
)
9605 opcode
= T_MNEM_bcond
;
9607 opcode
= inst
.instruction
;
9609 if (unified_syntax
&& inst
.size_req
== 4)
9611 inst
.instruction
= THUMB_OP32(opcode
);
9612 if (cond
== COND_ALWAYS
)
9613 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9616 gas_assert (cond
!= 0xF);
9617 inst
.instruction
|= cond
<< 22;
9618 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9623 inst
.instruction
= THUMB_OP16(opcode
);
9624 if (cond
== COND_ALWAYS
)
9625 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9628 inst
.instruction
|= cond
<< 8;
9629 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9631 /* Allow section relaxation. */
9632 if (unified_syntax
&& inst
.size_req
!= 2)
9633 inst
.relax
= opcode
;
9636 inst
.reloc
.pc_rel
= 1;
9642 constraint (inst
.cond
!= COND_ALWAYS
,
9643 _("instruction is always unconditional"));
9644 if (inst
.operands
[0].present
)
9646 constraint (inst
.operands
[0].imm
> 255,
9647 _("immediate value out of range"));
9648 inst
.instruction
|= inst
.operands
[0].imm
;
9649 set_it_insn_type (NEUTRAL_IT_INSN
);
9654 do_t_branch23 (void)
9656 set_it_insn_type_last ();
9657 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9658 inst
.reloc
.pc_rel
= 1;
9660 #if defined(OBJ_COFF)
9661 /* If the destination of the branch is a defined symbol which does not have
9662 the THUMB_FUNC attribute, then we must be calling a function which has
9663 the (interfacearm) attribute. We look for the Thumb entry point to that
9664 function and change the branch to refer to that function instead. */
9665 if ( inst
.reloc
.exp
.X_op
== O_symbol
9666 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9667 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9668 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9669 inst
.reloc
.exp
.X_add_symbol
=
9670 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9677 set_it_insn_type_last ();
9678 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9679 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9680 should cause the alignment to be checked once it is known. This is
9681 because BX PC only works if the instruction is word aligned. */
9689 set_it_insn_type_last ();
9690 Rm
= inst
.operands
[0].reg
;
9691 reject_bad_reg (Rm
);
9692 inst
.instruction
|= Rm
<< 16;
9701 Rd
= inst
.operands
[0].reg
;
9702 Rm
= inst
.operands
[1].reg
;
9704 reject_bad_reg (Rd
);
9705 reject_bad_reg (Rm
);
9707 inst
.instruction
|= Rd
<< 8;
9708 inst
.instruction
|= Rm
<< 16;
9709 inst
.instruction
|= Rm
;
9715 set_it_insn_type (OUTSIDE_IT_INSN
);
9716 inst
.instruction
|= inst
.operands
[0].imm
;
9722 set_it_insn_type (OUTSIDE_IT_INSN
);
9724 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9725 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9727 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9728 inst
.instruction
= 0xf3af8000;
9729 inst
.instruction
|= imod
<< 9;
9730 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9731 if (inst
.operands
[1].present
)
9732 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9736 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9737 && (inst
.operands
[0].imm
& 4),
9738 _("selected processor does not support 'A' form "
9739 "of this instruction"));
9740 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9741 _("Thumb does not support the 2-argument "
9742 "form of this instruction"));
9743 inst
.instruction
|= inst
.operands
[0].imm
;
9747 /* THUMB CPY instruction (argument parse). */
9752 if (inst
.size_req
== 4)
9754 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9755 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9756 inst
.instruction
|= inst
.operands
[1].reg
;
9760 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9761 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9762 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9769 set_it_insn_type (OUTSIDE_IT_INSN
);
9770 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9771 inst
.instruction
|= inst
.operands
[0].reg
;
9772 inst
.reloc
.pc_rel
= 1;
9773 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9779 inst
.instruction
|= inst
.operands
[0].imm
;
9785 unsigned Rd
, Rn
, Rm
;
9787 Rd
= inst
.operands
[0].reg
;
9788 Rn
= (inst
.operands
[1].present
9789 ? inst
.operands
[1].reg
: Rd
);
9790 Rm
= inst
.operands
[2].reg
;
9792 reject_bad_reg (Rd
);
9793 reject_bad_reg (Rn
);
9794 reject_bad_reg (Rm
);
9796 inst
.instruction
|= Rd
<< 8;
9797 inst
.instruction
|= Rn
<< 16;
9798 inst
.instruction
|= Rm
;
9804 if (unified_syntax
&& inst
.size_req
== 4)
9805 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9807 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9813 unsigned int cond
= inst
.operands
[0].imm
;
9815 set_it_insn_type (IT_INSN
);
9816 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
9819 /* If the condition is a negative condition, invert the mask. */
9820 if ((cond
& 0x1) == 0x0)
9822 unsigned int mask
= inst
.instruction
& 0x000f;
9824 if ((mask
& 0x7) == 0)
9825 /* no conversion needed */;
9826 else if ((mask
& 0x3) == 0)
9828 else if ((mask
& 0x1) == 0)
9833 inst
.instruction
&= 0xfff0;
9834 inst
.instruction
|= mask
;
9837 inst
.instruction
|= cond
<< 4;
9840 /* Helper function used for both push/pop and ldm/stm. */
9842 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9846 load
= (inst
.instruction
& (1 << 20)) != 0;
9848 if (mask
& (1 << 13))
9849 inst
.error
= _("SP not allowed in register list");
9851 if ((mask
& (1 << base
)) != 0
9853 inst
.error
= _("having the base register in the register list when "
9854 "using write back is UNPREDICTABLE");
9858 if (mask
& (1 << 15))
9860 if (mask
& (1 << 14))
9861 inst
.error
= _("LR and PC should not both be in register list");
9863 set_it_insn_type_last ();
9868 if (mask
& (1 << 15))
9869 inst
.error
= _("PC not allowed in register list");
9872 if ((mask
& (mask
- 1)) == 0)
9874 /* Single register transfers implemented as str/ldr. */
9877 if (inst
.instruction
& (1 << 23))
9878 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9880 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9884 if (inst
.instruction
& (1 << 23))
9885 inst
.instruction
= 0x00800000; /* ia -> [base] */
9887 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9890 inst
.instruction
|= 0xf8400000;
9892 inst
.instruction
|= 0x00100000;
9894 mask
= ffs (mask
) - 1;
9898 inst
.instruction
|= WRITE_BACK
;
9900 inst
.instruction
|= mask
;
9901 inst
.instruction
|= base
<< 16;
9907 /* This really doesn't seem worth it. */
9908 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9909 _("expression too complex"));
9910 constraint (inst
.operands
[1].writeback
,
9911 _("Thumb load/store multiple does not support {reglist}^"));
9919 /* See if we can use a 16-bit instruction. */
9920 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9921 && inst
.size_req
!= 4
9922 && !(inst
.operands
[1].imm
& ~0xff))
9924 mask
= 1 << inst
.operands
[0].reg
;
9926 if (inst
.operands
[0].reg
<= 7
9927 && (inst
.instruction
== T_MNEM_stmia
9928 ? inst
.operands
[0].writeback
9929 : (inst
.operands
[0].writeback
9930 == !(inst
.operands
[1].imm
& mask
))))
9932 if (inst
.instruction
== T_MNEM_stmia
9933 && (inst
.operands
[1].imm
& mask
)
9934 && (inst
.operands
[1].imm
& (mask
- 1)))
9935 as_warn (_("value stored for r%d is UNKNOWN"),
9936 inst
.operands
[0].reg
);
9938 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9939 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9940 inst
.instruction
|= inst
.operands
[1].imm
;
9943 else if (inst
.operands
[0] .reg
== REG_SP
9944 && inst
.operands
[0].writeback
)
9946 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9947 ? T_MNEM_push
: T_MNEM_pop
);
9948 inst
.instruction
|= inst
.operands
[1].imm
;
9955 if (inst
.instruction
< 0xffff)
9956 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9958 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9959 inst
.operands
[0].writeback
);
9964 constraint (inst
.operands
[0].reg
> 7
9965 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9966 constraint (inst
.instruction
!= T_MNEM_ldmia
9967 && inst
.instruction
!= T_MNEM_stmia
,
9968 _("Thumb-2 instruction only valid in unified syntax"));
9969 if (inst
.instruction
== T_MNEM_stmia
)
9971 if (!inst
.operands
[0].writeback
)
9972 as_warn (_("this instruction will write back the base register"));
9973 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9974 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9975 as_warn (_("value stored for r%d is UNKNOWN"),
9976 inst
.operands
[0].reg
);
9980 if (!inst
.operands
[0].writeback
9981 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9982 as_warn (_("this instruction will write back the base register"));
9983 else if (inst
.operands
[0].writeback
9984 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9985 as_warn (_("this instruction will not write back the base register"));
9988 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9989 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9990 inst
.instruction
|= inst
.operands
[1].imm
;
9997 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9998 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9999 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10000 || inst
.operands
[1].negative
,
10003 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10005 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10006 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10007 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10013 if (!inst
.operands
[1].present
)
10015 constraint (inst
.operands
[0].reg
== REG_LR
,
10016 _("r14 not allowed as first register "
10017 "when second register is omitted"));
10018 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10020 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10023 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10024 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10025 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10031 unsigned long opcode
;
10034 if (inst
.operands
[0].isreg
10035 && !inst
.operands
[0].preind
10036 && inst
.operands
[0].reg
== REG_PC
)
10037 set_it_insn_type_last ();
10039 opcode
= inst
.instruction
;
10040 if (unified_syntax
)
10042 if (!inst
.operands
[1].isreg
)
10044 if (opcode
<= 0xffff)
10045 inst
.instruction
= THUMB_OP32 (opcode
);
10046 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10049 if (inst
.operands
[1].isreg
10050 && !inst
.operands
[1].writeback
10051 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10052 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10053 && opcode
<= 0xffff
10054 && inst
.size_req
!= 4)
10056 /* Insn may have a 16-bit form. */
10057 Rn
= inst
.operands
[1].reg
;
10058 if (inst
.operands
[1].immisreg
)
10060 inst
.instruction
= THUMB_OP16 (opcode
);
10062 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10064 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10065 reject_bad_reg (inst
.operands
[1].imm
);
10067 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10068 && opcode
!= T_MNEM_ldrsb
)
10069 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10070 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10077 if (inst
.reloc
.pc_rel
)
10078 opcode
= T_MNEM_ldr_pc2
;
10080 opcode
= T_MNEM_ldr_pc
;
10084 if (opcode
== T_MNEM_ldr
)
10085 opcode
= T_MNEM_ldr_sp
;
10087 opcode
= T_MNEM_str_sp
;
10089 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10093 inst
.instruction
= inst
.operands
[0].reg
;
10094 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10096 inst
.instruction
|= THUMB_OP16 (opcode
);
10097 if (inst
.size_req
== 2)
10098 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10100 inst
.relax
= opcode
;
10104 /* Definitely a 32-bit variant. */
10106 /* Do some validations regarding addressing modes. */
10107 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10108 && opcode
!= T_MNEM_str
)
10109 reject_bad_reg (inst
.operands
[1].imm
);
10111 inst
.instruction
= THUMB_OP32 (opcode
);
10112 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10113 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10117 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10119 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10121 /* Only [Rn,Rm] is acceptable. */
10122 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10123 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10124 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10125 || inst
.operands
[1].negative
,
10126 _("Thumb does not support this addressing mode"));
10127 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10131 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10132 if (!inst
.operands
[1].isreg
)
10133 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10136 constraint (!inst
.operands
[1].preind
10137 || inst
.operands
[1].shifted
10138 || inst
.operands
[1].writeback
,
10139 _("Thumb does not support this addressing mode"));
10140 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10142 constraint (inst
.instruction
& 0x0600,
10143 _("byte or halfword not valid for base register"));
10144 constraint (inst
.operands
[1].reg
== REG_PC
10145 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10146 _("r15 based store not allowed"));
10147 constraint (inst
.operands
[1].immisreg
,
10148 _("invalid base register for register offset"));
10150 if (inst
.operands
[1].reg
== REG_PC
)
10151 inst
.instruction
= T_OPCODE_LDR_PC
;
10152 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10153 inst
.instruction
= T_OPCODE_LDR_SP
;
10155 inst
.instruction
= T_OPCODE_STR_SP
;
10157 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10158 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10162 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10163 if (!inst
.operands
[1].immisreg
)
10165 /* Immediate offset. */
10166 inst
.instruction
|= inst
.operands
[0].reg
;
10167 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10168 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10172 /* Register offset. */
10173 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10174 constraint (inst
.operands
[1].negative
,
10175 _("Thumb does not support this addressing mode"));
10178 switch (inst
.instruction
)
10180 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10181 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10182 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10183 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10184 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10185 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10186 case 0x5600 /* ldrsb */:
10187 case 0x5e00 /* ldrsh */: break;
10191 inst
.instruction
|= inst
.operands
[0].reg
;
10192 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10193 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10199 if (!inst
.operands
[1].present
)
10201 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10202 constraint (inst
.operands
[0].reg
== REG_LR
,
10203 _("r14 not allowed here"));
10205 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10206 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10207 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10213 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10214 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10220 unsigned Rd
, Rn
, Rm
, Ra
;
10222 Rd
= inst
.operands
[0].reg
;
10223 Rn
= inst
.operands
[1].reg
;
10224 Rm
= inst
.operands
[2].reg
;
10225 Ra
= inst
.operands
[3].reg
;
10227 reject_bad_reg (Rd
);
10228 reject_bad_reg (Rn
);
10229 reject_bad_reg (Rm
);
10230 reject_bad_reg (Ra
);
10232 inst
.instruction
|= Rd
<< 8;
10233 inst
.instruction
|= Rn
<< 16;
10234 inst
.instruction
|= Rm
;
10235 inst
.instruction
|= Ra
<< 12;
10241 unsigned RdLo
, RdHi
, Rn
, Rm
;
10243 RdLo
= inst
.operands
[0].reg
;
10244 RdHi
= inst
.operands
[1].reg
;
10245 Rn
= inst
.operands
[2].reg
;
10246 Rm
= inst
.operands
[3].reg
;
10248 reject_bad_reg (RdLo
);
10249 reject_bad_reg (RdHi
);
10250 reject_bad_reg (Rn
);
10251 reject_bad_reg (Rm
);
10253 inst
.instruction
|= RdLo
<< 12;
10254 inst
.instruction
|= RdHi
<< 8;
10255 inst
.instruction
|= Rn
<< 16;
10256 inst
.instruction
|= Rm
;
10260 do_t_mov_cmp (void)
10264 Rn
= inst
.operands
[0].reg
;
10265 Rm
= inst
.operands
[1].reg
;
10268 set_it_insn_type_last ();
10270 if (unified_syntax
)
10272 int r0off
= (inst
.instruction
== T_MNEM_mov
10273 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10274 unsigned long opcode
;
10275 bfd_boolean narrow
;
10276 bfd_boolean low_regs
;
10278 low_regs
= (Rn
<= 7 && Rm
<= 7);
10279 opcode
= inst
.instruction
;
10280 if (in_it_block ())
10281 narrow
= opcode
!= T_MNEM_movs
;
10283 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10284 if (inst
.size_req
== 4
10285 || inst
.operands
[1].shifted
)
10288 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10289 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10290 && !inst
.operands
[1].shifted
10294 inst
.instruction
= T2_SUBS_PC_LR
;
10298 if (opcode
== T_MNEM_cmp
)
10300 constraint (Rn
== REG_PC
, BAD_PC
);
10303 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10305 warn_deprecated_sp (Rm
);
10306 /* R15 was documented as a valid choice for Rm in ARMv6,
10307 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10308 tools reject R15, so we do too. */
10309 constraint (Rm
== REG_PC
, BAD_PC
);
10312 reject_bad_reg (Rm
);
10314 else if (opcode
== T_MNEM_mov
10315 || opcode
== T_MNEM_movs
)
10317 if (inst
.operands
[1].isreg
)
10319 if (opcode
== T_MNEM_movs
)
10321 reject_bad_reg (Rn
);
10322 reject_bad_reg (Rm
);
10326 /* This is mov.n. */
10327 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10328 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10330 as_warn (_("Use of r%u as a source register is "
10331 "deprecated when r%u is the destination "
10332 "register."), Rm
, Rn
);
10337 /* This is mov.w. */
10338 constraint (Rn
== REG_PC
, BAD_PC
);
10339 constraint (Rm
== REG_PC
, BAD_PC
);
10340 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10344 reject_bad_reg (Rn
);
10347 if (!inst
.operands
[1].isreg
)
10349 /* Immediate operand. */
10350 if (!in_it_block () && opcode
== T_MNEM_mov
)
10352 if (low_regs
&& narrow
)
10354 inst
.instruction
= THUMB_OP16 (opcode
);
10355 inst
.instruction
|= Rn
<< 8;
10356 if (inst
.size_req
== 2)
10357 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10359 inst
.relax
= opcode
;
10363 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10364 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10365 inst
.instruction
|= Rn
<< r0off
;
10366 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10369 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10370 && (inst
.instruction
== T_MNEM_mov
10371 || inst
.instruction
== T_MNEM_movs
))
10373 /* Register shifts are encoded as separate shift instructions. */
10374 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10376 if (in_it_block ())
10381 if (inst
.size_req
== 4)
10384 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10390 switch (inst
.operands
[1].shift_kind
)
10393 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10396 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10399 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10402 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10408 inst
.instruction
= opcode
;
10411 inst
.instruction
|= Rn
;
10412 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10417 inst
.instruction
|= CONDS_BIT
;
10419 inst
.instruction
|= Rn
<< 8;
10420 inst
.instruction
|= Rm
<< 16;
10421 inst
.instruction
|= inst
.operands
[1].imm
;
10426 /* Some mov with immediate shift have narrow variants.
10427 Register shifts are handled above. */
10428 if (low_regs
&& inst
.operands
[1].shifted
10429 && (inst
.instruction
== T_MNEM_mov
10430 || inst
.instruction
== T_MNEM_movs
))
10432 if (in_it_block ())
10433 narrow
= (inst
.instruction
== T_MNEM_mov
);
10435 narrow
= (inst
.instruction
== T_MNEM_movs
);
10440 switch (inst
.operands
[1].shift_kind
)
10442 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10443 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10444 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10445 default: narrow
= FALSE
; break;
10451 inst
.instruction
|= Rn
;
10452 inst
.instruction
|= Rm
<< 3;
10453 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10457 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10458 inst
.instruction
|= Rn
<< r0off
;
10459 encode_thumb32_shifted_operand (1);
10463 switch (inst
.instruction
)
10466 inst
.instruction
= T_OPCODE_MOV_HR
;
10467 inst
.instruction
|= (Rn
& 0x8) << 4;
10468 inst
.instruction
|= (Rn
& 0x7);
10469 inst
.instruction
|= Rm
<< 3;
10473 /* We know we have low registers at this point.
10474 Generate LSLS Rd, Rs, #0. */
10475 inst
.instruction
= T_OPCODE_LSL_I
;
10476 inst
.instruction
|= Rn
;
10477 inst
.instruction
|= Rm
<< 3;
10483 inst
.instruction
= T_OPCODE_CMP_LR
;
10484 inst
.instruction
|= Rn
;
10485 inst
.instruction
|= Rm
<< 3;
10489 inst
.instruction
= T_OPCODE_CMP_HR
;
10490 inst
.instruction
|= (Rn
& 0x8) << 4;
10491 inst
.instruction
|= (Rn
& 0x7);
10492 inst
.instruction
|= Rm
<< 3;
10499 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10501 /* PR 10443: Do not silently ignore shifted operands. */
10502 constraint (inst
.operands
[1].shifted
,
10503 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10505 if (inst
.operands
[1].isreg
)
10507 if (Rn
< 8 && Rm
< 8)
10509 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10510 since a MOV instruction produces unpredictable results. */
10511 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10512 inst
.instruction
= T_OPCODE_ADD_I3
;
10514 inst
.instruction
= T_OPCODE_CMP_LR
;
10516 inst
.instruction
|= Rn
;
10517 inst
.instruction
|= Rm
<< 3;
10521 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10522 inst
.instruction
= T_OPCODE_MOV_HR
;
10524 inst
.instruction
= T_OPCODE_CMP_HR
;
10530 constraint (Rn
> 7,
10531 _("only lo regs allowed with immediate"));
10532 inst
.instruction
|= Rn
<< 8;
10533 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10544 top
= (inst
.instruction
& 0x00800000) != 0;
10545 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10547 constraint (top
, _(":lower16: not allowed this instruction"));
10548 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10550 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10552 constraint (!top
, _(":upper16: not allowed this instruction"));
10553 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10556 Rd
= inst
.operands
[0].reg
;
10557 reject_bad_reg (Rd
);
10559 inst
.instruction
|= Rd
<< 8;
10560 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10562 imm
= inst
.reloc
.exp
.X_add_number
;
10563 inst
.instruction
|= (imm
& 0xf000) << 4;
10564 inst
.instruction
|= (imm
& 0x0800) << 15;
10565 inst
.instruction
|= (imm
& 0x0700) << 4;
10566 inst
.instruction
|= (imm
& 0x00ff);
10571 do_t_mvn_tst (void)
10575 Rn
= inst
.operands
[0].reg
;
10576 Rm
= inst
.operands
[1].reg
;
10578 if (inst
.instruction
== T_MNEM_cmp
10579 || inst
.instruction
== T_MNEM_cmn
)
10580 constraint (Rn
== REG_PC
, BAD_PC
);
10582 reject_bad_reg (Rn
);
10583 reject_bad_reg (Rm
);
10585 if (unified_syntax
)
10587 int r0off
= (inst
.instruction
== T_MNEM_mvn
10588 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10589 bfd_boolean narrow
;
10591 if (inst
.size_req
== 4
10592 || inst
.instruction
> 0xffff
10593 || inst
.operands
[1].shifted
10594 || Rn
> 7 || Rm
> 7)
10596 else if (inst
.instruction
== T_MNEM_cmn
)
10598 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10599 narrow
= !in_it_block ();
10601 narrow
= in_it_block ();
10603 if (!inst
.operands
[1].isreg
)
10605 /* For an immediate, we always generate a 32-bit opcode;
10606 section relaxation will shrink it later if possible. */
10607 if (inst
.instruction
< 0xffff)
10608 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10609 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10610 inst
.instruction
|= Rn
<< r0off
;
10611 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10615 /* See if we can do this with a 16-bit instruction. */
10618 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10619 inst
.instruction
|= Rn
;
10620 inst
.instruction
|= Rm
<< 3;
10624 constraint (inst
.operands
[1].shifted
10625 && inst
.operands
[1].immisreg
,
10626 _("shift must be constant"));
10627 if (inst
.instruction
< 0xffff)
10628 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10629 inst
.instruction
|= Rn
<< r0off
;
10630 encode_thumb32_shifted_operand (1);
10636 constraint (inst
.instruction
> 0xffff
10637 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10638 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10639 _("unshifted register required"));
10640 constraint (Rn
> 7 || Rm
> 7,
10643 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10644 inst
.instruction
|= Rn
;
10645 inst
.instruction
|= Rm
<< 3;
10655 if (do_vfp_nsyn_mrs () == SUCCESS
)
10658 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10661 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10662 _("selected processor does not support "
10663 "requested special purpose register"));
10667 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10668 _("selected processor does not support "
10669 "requested special purpose register"));
10670 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10671 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10672 _("'CPSR' or 'SPSR' expected"));
10675 Rd
= inst
.operands
[0].reg
;
10676 reject_bad_reg (Rd
);
10678 inst
.instruction
|= Rd
<< 8;
10679 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10680 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10689 if (do_vfp_nsyn_msr () == SUCCESS
)
10692 constraint (!inst
.operands
[1].isreg
,
10693 _("Thumb encoding does not support an immediate here"));
10694 flags
= inst
.operands
[0].imm
;
10697 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10698 _("selected processor does not support "
10699 "requested special purpose register"));
10703 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10704 _("selected processor does not support "
10705 "requested special purpose register"));
10709 Rn
= inst
.operands
[1].reg
;
10710 reject_bad_reg (Rn
);
10712 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10713 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10714 inst
.instruction
|= (flags
& 0xff);
10715 inst
.instruction
|= Rn
<< 16;
10721 bfd_boolean narrow
;
10722 unsigned Rd
, Rn
, Rm
;
10724 if (!inst
.operands
[2].present
)
10725 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10727 Rd
= inst
.operands
[0].reg
;
10728 Rn
= inst
.operands
[1].reg
;
10729 Rm
= inst
.operands
[2].reg
;
10731 if (unified_syntax
)
10733 if (inst
.size_req
== 4
10739 else if (inst
.instruction
== T_MNEM_muls
)
10740 narrow
= !in_it_block ();
10742 narrow
= in_it_block ();
10746 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10747 constraint (Rn
> 7 || Rm
> 7,
10754 /* 16-bit MULS/Conditional MUL. */
10755 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10756 inst
.instruction
|= Rd
;
10759 inst
.instruction
|= Rm
<< 3;
10761 inst
.instruction
|= Rn
<< 3;
10763 constraint (1, _("dest must overlap one source register"));
10767 constraint (inst
.instruction
!= T_MNEM_mul
,
10768 _("Thumb-2 MUL must not set flags"));
10770 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10771 inst
.instruction
|= Rd
<< 8;
10772 inst
.instruction
|= Rn
<< 16;
10773 inst
.instruction
|= Rm
<< 0;
10775 reject_bad_reg (Rd
);
10776 reject_bad_reg (Rn
);
10777 reject_bad_reg (Rm
);
10784 unsigned RdLo
, RdHi
, Rn
, Rm
;
10786 RdLo
= inst
.operands
[0].reg
;
10787 RdHi
= inst
.operands
[1].reg
;
10788 Rn
= inst
.operands
[2].reg
;
10789 Rm
= inst
.operands
[3].reg
;
10791 reject_bad_reg (RdLo
);
10792 reject_bad_reg (RdHi
);
10793 reject_bad_reg (Rn
);
10794 reject_bad_reg (Rm
);
10796 inst
.instruction
|= RdLo
<< 12;
10797 inst
.instruction
|= RdHi
<< 8;
10798 inst
.instruction
|= Rn
<< 16;
10799 inst
.instruction
|= Rm
;
10802 as_tsktsk (_("rdhi and rdlo must be different"));
10808 set_it_insn_type (NEUTRAL_IT_INSN
);
10810 if (unified_syntax
)
10812 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10814 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10815 inst
.instruction
|= inst
.operands
[0].imm
;
10819 /* PR9722: Check for Thumb2 availability before
10820 generating a thumb2 nop instruction. */
10821 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
10823 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10824 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10827 inst
.instruction
= 0x46c0;
10832 constraint (inst
.operands
[0].present
,
10833 _("Thumb does not support NOP with hints"));
10834 inst
.instruction
= 0x46c0;
10841 if (unified_syntax
)
10843 bfd_boolean narrow
;
10845 if (THUMB_SETS_FLAGS (inst
.instruction
))
10846 narrow
= !in_it_block ();
10848 narrow
= in_it_block ();
10849 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10851 if (inst
.size_req
== 4)
10856 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10857 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10858 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10862 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10863 inst
.instruction
|= inst
.operands
[0].reg
;
10864 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10869 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10871 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10873 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10874 inst
.instruction
|= inst
.operands
[0].reg
;
10875 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10884 Rd
= inst
.operands
[0].reg
;
10885 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10887 reject_bad_reg (Rd
);
10888 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10889 reject_bad_reg (Rn
);
10891 inst
.instruction
|= Rd
<< 8;
10892 inst
.instruction
|= Rn
<< 16;
10894 if (!inst
.operands
[2].isreg
)
10896 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10897 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10903 Rm
= inst
.operands
[2].reg
;
10904 reject_bad_reg (Rm
);
10906 constraint (inst
.operands
[2].shifted
10907 && inst
.operands
[2].immisreg
,
10908 _("shift must be constant"));
10909 encode_thumb32_shifted_operand (2);
10916 unsigned Rd
, Rn
, Rm
;
10918 Rd
= inst
.operands
[0].reg
;
10919 Rn
= inst
.operands
[1].reg
;
10920 Rm
= inst
.operands
[2].reg
;
10922 reject_bad_reg (Rd
);
10923 reject_bad_reg (Rn
);
10924 reject_bad_reg (Rm
);
10926 inst
.instruction
|= Rd
<< 8;
10927 inst
.instruction
|= Rn
<< 16;
10928 inst
.instruction
|= Rm
;
10929 if (inst
.operands
[3].present
)
10931 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10932 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10933 _("expression too complex"));
10934 inst
.instruction
|= (val
& 0x1c) << 10;
10935 inst
.instruction
|= (val
& 0x03) << 6;
10942 if (!inst
.operands
[3].present
)
10946 inst
.instruction
&= ~0x00000020;
10948 /* PR 10168. Swap the Rm and Rn registers. */
10949 Rtmp
= inst
.operands
[1].reg
;
10950 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
10951 inst
.operands
[2].reg
= Rtmp
;
10959 if (inst
.operands
[0].immisreg
)
10960 reject_bad_reg (inst
.operands
[0].imm
);
10962 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10966 do_t_push_pop (void)
10970 constraint (inst
.operands
[0].writeback
,
10971 _("push/pop do not support {reglist}^"));
10972 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10973 _("expression too complex"));
10975 mask
= inst
.operands
[0].imm
;
10976 if ((mask
& ~0xff) == 0)
10977 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10978 else if ((inst
.instruction
== T_MNEM_push
10979 && (mask
& ~0xff) == 1 << REG_LR
)
10980 || (inst
.instruction
== T_MNEM_pop
10981 && (mask
& ~0xff) == 1 << REG_PC
))
10983 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10984 inst
.instruction
|= THUMB_PP_PC_LR
;
10985 inst
.instruction
|= mask
& 0xff;
10987 else if (unified_syntax
)
10989 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10990 encode_thumb2_ldmstm (13, mask
, TRUE
);
10994 inst
.error
= _("invalid register list to push/pop instruction");
11004 Rd
= inst
.operands
[0].reg
;
11005 Rm
= inst
.operands
[1].reg
;
11007 reject_bad_reg (Rd
);
11008 reject_bad_reg (Rm
);
11010 inst
.instruction
|= Rd
<< 8;
11011 inst
.instruction
|= Rm
<< 16;
11012 inst
.instruction
|= Rm
;
11020 Rd
= inst
.operands
[0].reg
;
11021 Rm
= inst
.operands
[1].reg
;
11023 reject_bad_reg (Rd
);
11024 reject_bad_reg (Rm
);
11026 if (Rd
<= 7 && Rm
<= 7
11027 && inst
.size_req
!= 4)
11029 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11030 inst
.instruction
|= Rd
;
11031 inst
.instruction
|= Rm
<< 3;
11033 else if (unified_syntax
)
11035 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11036 inst
.instruction
|= Rd
<< 8;
11037 inst
.instruction
|= Rm
<< 16;
11038 inst
.instruction
|= Rm
;
11041 inst
.error
= BAD_HIREG
;
11049 Rd
= inst
.operands
[0].reg
;
11050 Rm
= inst
.operands
[1].reg
;
11052 reject_bad_reg (Rd
);
11053 reject_bad_reg (Rm
);
11055 inst
.instruction
|= Rd
<< 8;
11056 inst
.instruction
|= Rm
;
11064 Rd
= inst
.operands
[0].reg
;
11065 Rs
= (inst
.operands
[1].present
11066 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11067 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11069 reject_bad_reg (Rd
);
11070 reject_bad_reg (Rs
);
11071 if (inst
.operands
[2].isreg
)
11072 reject_bad_reg (inst
.operands
[2].reg
);
11074 inst
.instruction
|= Rd
<< 8;
11075 inst
.instruction
|= Rs
<< 16;
11076 if (!inst
.operands
[2].isreg
)
11078 bfd_boolean narrow
;
11080 if ((inst
.instruction
& 0x00100000) != 0)
11081 narrow
= !in_it_block ();
11083 narrow
= in_it_block ();
11085 if (Rd
> 7 || Rs
> 7)
11088 if (inst
.size_req
== 4 || !unified_syntax
)
11091 if (inst
.reloc
.exp
.X_op
!= O_constant
11092 || inst
.reloc
.exp
.X_add_number
!= 0)
11095 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11096 relaxation, but it doesn't seem worth the hassle. */
11099 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11100 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11101 inst
.instruction
|= Rs
<< 3;
11102 inst
.instruction
|= Rd
;
11106 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11107 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11111 encode_thumb32_shifted_operand (2);
11117 set_it_insn_type (OUTSIDE_IT_INSN
);
11118 if (inst
.operands
[0].imm
)
11119 inst
.instruction
|= 0x8;
11125 if (!inst
.operands
[1].present
)
11126 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11128 if (unified_syntax
)
11130 bfd_boolean narrow
;
11133 switch (inst
.instruction
)
11136 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11138 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11140 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11142 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11146 if (THUMB_SETS_FLAGS (inst
.instruction
))
11147 narrow
= !in_it_block ();
11149 narrow
= in_it_block ();
11150 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11152 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11154 if (inst
.operands
[2].isreg
11155 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11156 || inst
.operands
[2].reg
> 7))
11158 if (inst
.size_req
== 4)
11161 reject_bad_reg (inst
.operands
[0].reg
);
11162 reject_bad_reg (inst
.operands
[1].reg
);
11166 if (inst
.operands
[2].isreg
)
11168 reject_bad_reg (inst
.operands
[2].reg
);
11169 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11170 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11171 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11172 inst
.instruction
|= inst
.operands
[2].reg
;
11176 inst
.operands
[1].shifted
= 1;
11177 inst
.operands
[1].shift_kind
= shift_kind
;
11178 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11179 ? T_MNEM_movs
: T_MNEM_mov
);
11180 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11181 encode_thumb32_shifted_operand (1);
11182 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11183 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11188 if (inst
.operands
[2].isreg
)
11190 switch (shift_kind
)
11192 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11193 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11194 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11195 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11199 inst
.instruction
|= inst
.operands
[0].reg
;
11200 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11204 switch (shift_kind
)
11206 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11207 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11208 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11211 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11212 inst
.instruction
|= inst
.operands
[0].reg
;
11213 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11219 constraint (inst
.operands
[0].reg
> 7
11220 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11221 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11223 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11225 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11226 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11227 _("source1 and dest must be same register"));
11229 switch (inst
.instruction
)
11231 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11232 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11233 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11234 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11238 inst
.instruction
|= inst
.operands
[0].reg
;
11239 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11243 switch (inst
.instruction
)
11245 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11246 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11247 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11248 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11251 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11252 inst
.instruction
|= inst
.operands
[0].reg
;
11253 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11261 unsigned Rd
, Rn
, Rm
;
11263 Rd
= inst
.operands
[0].reg
;
11264 Rn
= inst
.operands
[1].reg
;
11265 Rm
= inst
.operands
[2].reg
;
11267 reject_bad_reg (Rd
);
11268 reject_bad_reg (Rn
);
11269 reject_bad_reg (Rm
);
11271 inst
.instruction
|= Rd
<< 8;
11272 inst
.instruction
|= Rn
<< 16;
11273 inst
.instruction
|= Rm
;
11279 unsigned Rd
, Rn
, Rm
;
11281 Rd
= inst
.operands
[0].reg
;
11282 Rm
= inst
.operands
[1].reg
;
11283 Rn
= inst
.operands
[2].reg
;
11285 reject_bad_reg (Rd
);
11286 reject_bad_reg (Rn
);
11287 reject_bad_reg (Rm
);
11289 inst
.instruction
|= Rd
<< 8;
11290 inst
.instruction
|= Rn
<< 16;
11291 inst
.instruction
|= Rm
;
11297 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11298 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11299 _("expression too complex"));
11300 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11301 inst
.instruction
|= (value
& 0xf000) >> 12;
11302 inst
.instruction
|= (value
& 0x0ff0);
11303 inst
.instruction
|= (value
& 0x000f) << 16;
11307 do_t_ssat_usat (int bias
)
11311 Rd
= inst
.operands
[0].reg
;
11312 Rn
= inst
.operands
[2].reg
;
11314 reject_bad_reg (Rd
);
11315 reject_bad_reg (Rn
);
11317 inst
.instruction
|= Rd
<< 8;
11318 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11319 inst
.instruction
|= Rn
<< 16;
11321 if (inst
.operands
[3].present
)
11323 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11325 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11327 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11328 _("expression too complex"));
11330 if (shift_amount
!= 0)
11332 constraint (shift_amount
> 31,
11333 _("shift expression is too large"));
11335 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11336 inst
.instruction
|= 0x00200000; /* sh bit. */
11338 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11339 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11347 do_t_ssat_usat (1);
11355 Rd
= inst
.operands
[0].reg
;
11356 Rn
= inst
.operands
[2].reg
;
11358 reject_bad_reg (Rd
);
11359 reject_bad_reg (Rn
);
11361 inst
.instruction
|= Rd
<< 8;
11362 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11363 inst
.instruction
|= Rn
<< 16;
11369 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11370 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11371 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11372 || inst
.operands
[2].negative
,
11375 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11377 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11378 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11379 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11380 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11386 if (!inst
.operands
[2].present
)
11387 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11389 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11390 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11391 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11394 inst
.instruction
|= inst
.operands
[0].reg
;
11395 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11396 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11397 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11403 unsigned Rd
, Rn
, Rm
;
11405 Rd
= inst
.operands
[0].reg
;
11406 Rn
= inst
.operands
[1].reg
;
11407 Rm
= inst
.operands
[2].reg
;
11409 reject_bad_reg (Rd
);
11410 reject_bad_reg (Rn
);
11411 reject_bad_reg (Rm
);
11413 inst
.instruction
|= Rd
<< 8;
11414 inst
.instruction
|= Rn
<< 16;
11415 inst
.instruction
|= Rm
;
11416 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11424 Rd
= inst
.operands
[0].reg
;
11425 Rm
= inst
.operands
[1].reg
;
11427 reject_bad_reg (Rd
);
11428 reject_bad_reg (Rm
);
11430 if (inst
.instruction
<= 0xffff
11431 && inst
.size_req
!= 4
11432 && Rd
<= 7 && Rm
<= 7
11433 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11435 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11436 inst
.instruction
|= Rd
;
11437 inst
.instruction
|= Rm
<< 3;
11439 else if (unified_syntax
)
11441 if (inst
.instruction
<= 0xffff)
11442 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11443 inst
.instruction
|= Rd
<< 8;
11444 inst
.instruction
|= Rm
;
11445 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11449 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11450 _("Thumb encoding does not support rotation"));
11451 constraint (1, BAD_HIREG
);
11458 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11467 half
= (inst
.instruction
& 0x10) != 0;
11468 set_it_insn_type_last ();
11469 constraint (inst
.operands
[0].immisreg
,
11470 _("instruction requires register index"));
11472 Rn
= inst
.operands
[0].reg
;
11473 Rm
= inst
.operands
[0].imm
;
11475 constraint (Rn
== REG_SP
, BAD_SP
);
11476 reject_bad_reg (Rm
);
11478 constraint (!half
&& inst
.operands
[0].shifted
,
11479 _("instruction does not allow shifted index"));
11480 inst
.instruction
|= (Rn
<< 16) | Rm
;
11486 do_t_ssat_usat (0);
11494 Rd
= inst
.operands
[0].reg
;
11495 Rn
= inst
.operands
[2].reg
;
11497 reject_bad_reg (Rd
);
11498 reject_bad_reg (Rn
);
11500 inst
.instruction
|= Rd
<< 8;
11501 inst
.instruction
|= inst
.operands
[1].imm
;
11502 inst
.instruction
|= Rn
<< 16;
11505 /* Neon instruction encoder helpers. */
11507 /* Encodings for the different types for various Neon opcodes. */
11509 /* An "invalid" code for the following tables. */
11512 struct neon_tab_entry
11515 unsigned float_or_poly
;
11516 unsigned scalar_or_imm
;
11519 /* Map overloaded Neon opcodes to their respective encodings. */
11520 #define NEON_ENC_TAB \
11521 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11522 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11523 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11524 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11525 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11526 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11527 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11528 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11529 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11530 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11531 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11532 /* Register variants of the following two instructions are encoded as
11533 vcge / vcgt with the operands reversed. */ \
11534 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11535 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11536 X(vfma, N_INV, 0x0000c10, N_INV), \
11537 X(vfms, N_INV, 0x0200c10, N_INV), \
11538 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11539 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11540 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11541 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11542 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11543 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11544 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11545 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11546 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11547 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11548 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11549 X(vshl, 0x0000400, N_INV, 0x0800510), \
11550 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11551 X(vand, 0x0000110, N_INV, 0x0800030), \
11552 X(vbic, 0x0100110, N_INV, 0x0800030), \
11553 X(veor, 0x1000110, N_INV, N_INV), \
11554 X(vorn, 0x0300110, N_INV, 0x0800010), \
11555 X(vorr, 0x0200110, N_INV, 0x0800010), \
11556 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11557 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11558 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11559 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11560 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11561 X(vst1, 0x0000000, 0x0800000, N_INV), \
11562 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
11563 X(vst2, 0x0000100, 0x0800100, N_INV), \
11564 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
11565 X(vst3, 0x0000200, 0x0800200, N_INV), \
11566 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
11567 X(vst4, 0x0000300, 0x0800300, N_INV), \
11568 X(vmovn, 0x1b20200, N_INV, N_INV), \
11569 X(vtrn, 0x1b20080, N_INV, N_INV), \
11570 X(vqmovn, 0x1b20200, N_INV, N_INV), \
11571 X(vqmovun, 0x1b20240, N_INV, N_INV), \
11572 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
11573 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
11574 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
11575 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
11576 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
11577 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
11578 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
11579 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
11580 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
11584 #define X(OPC,I,F,S) N_MNEM_##OPC
11589 static const struct neon_tab_entry neon_enc_tab
[] =
11591 #define X(OPC,I,F,S) { (I), (F), (S) }
11596 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
11597 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11598 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11599 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11600 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11601 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11602 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11603 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
11604 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
11605 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
11606 #define NEON_ENC_SINGLE_(X) \
11607 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
11608 #define NEON_ENC_DOUBLE_(X) \
11609 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
11611 #define NEON_ENCODE(type, inst) \
11614 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
11615 inst.is_neon = 1; \
11619 #define check_neon_suffixes \
11622 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
11624 as_bad (_("invalid neon suffix for non neon instruction")); \
11630 /* Define shapes for instruction operands. The following mnemonic characters
11631 are used in this table:
11633 F - VFP S<n> register
11634 D - Neon D<n> register
11635 Q - Neon Q<n> register
11639 L - D<n> register list
11641 This table is used to generate various data:
11642 - enumerations of the form NS_DDR to be used as arguments to
11644 - a table classifying shapes into single, double, quad, mixed.
11645 - a table used to drive neon_select_shape. */
11647 #define NEON_SHAPE_DEF \
11648 X(3, (D, D, D), DOUBLE), \
11649 X(3, (Q, Q, Q), QUAD), \
11650 X(3, (D, D, I), DOUBLE), \
11651 X(3, (Q, Q, I), QUAD), \
11652 X(3, (D, D, S), DOUBLE), \
11653 X(3, (Q, Q, S), QUAD), \
11654 X(2, (D, D), DOUBLE), \
11655 X(2, (Q, Q), QUAD), \
11656 X(2, (D, S), DOUBLE), \
11657 X(2, (Q, S), QUAD), \
11658 X(2, (D, R), DOUBLE), \
11659 X(2, (Q, R), QUAD), \
11660 X(2, (D, I), DOUBLE), \
11661 X(2, (Q, I), QUAD), \
11662 X(3, (D, L, D), DOUBLE), \
11663 X(2, (D, Q), MIXED), \
11664 X(2, (Q, D), MIXED), \
11665 X(3, (D, Q, I), MIXED), \
11666 X(3, (Q, D, I), MIXED), \
11667 X(3, (Q, D, D), MIXED), \
11668 X(3, (D, Q, Q), MIXED), \
11669 X(3, (Q, Q, D), MIXED), \
11670 X(3, (Q, D, S), MIXED), \
11671 X(3, (D, Q, S), MIXED), \
11672 X(4, (D, D, D, I), DOUBLE), \
11673 X(4, (Q, Q, Q, I), QUAD), \
11674 X(2, (F, F), SINGLE), \
11675 X(3, (F, F, F), SINGLE), \
11676 X(2, (F, I), SINGLE), \
11677 X(2, (F, D), MIXED), \
11678 X(2, (D, F), MIXED), \
11679 X(3, (F, F, I), MIXED), \
11680 X(4, (R, R, F, F), SINGLE), \
11681 X(4, (F, F, R, R), SINGLE), \
11682 X(3, (D, R, R), DOUBLE), \
11683 X(3, (R, R, D), DOUBLE), \
11684 X(2, (S, R), SINGLE), \
11685 X(2, (R, S), SINGLE), \
11686 X(2, (F, R), SINGLE), \
11687 X(2, (R, F), SINGLE)
11689 #define S2(A,B) NS_##A##B
11690 #define S3(A,B,C) NS_##A##B##C
11691 #define S4(A,B,C,D) NS_##A##B##C##D
11693 #define X(N, L, C) S##N L
11706 enum neon_shape_class
11714 #define X(N, L, C) SC_##C
11716 static enum neon_shape_class neon_shape_class
[] =
11734 /* Register widths of above. */
11735 static unsigned neon_shape_el_size
[] =
11746 struct neon_shape_info
11749 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11752 #define S2(A,B) { SE_##A, SE_##B }
11753 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11754 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11756 #define X(N, L, C) { N, S##N L }
11758 static struct neon_shape_info neon_shape_tab
[] =
11768 /* Bit masks used in type checking given instructions.
11769 'N_EQK' means the type must be the same as (or based on in some way) the key
11770 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11771 set, various other bits can be set as well in order to modify the meaning of
11772 the type constraint. */
11774 enum neon_type_mask
11797 N_KEY
= 0x1000000, /* Key element (main type specifier). */
11798 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
11799 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11800 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
11801 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
11802 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
11803 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
11804 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
11805 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
11806 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
11808 N_MAX_NONSPECIAL
= N_F64
11811 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11813 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11814 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11815 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11816 #define N_SUF_32 (N_SU_32 | N_F32)
11817 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11818 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11820 /* Pass this as the first type argument to neon_check_type to ignore types
11822 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11824 /* Select a "shape" for the current instruction (describing register types or
11825 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11826 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11827 function of operand parsing, so this function doesn't need to be called.
11828 Shapes should be listed in order of decreasing length. */
11830 static enum neon_shape
11831 neon_select_shape (enum neon_shape shape
, ...)
11834 enum neon_shape first_shape
= shape
;
11836 /* Fix missing optional operands. FIXME: we don't know at this point how
11837 many arguments we should have, so this makes the assumption that we have
11838 > 1. This is true of all current Neon opcodes, I think, but may not be
11839 true in the future. */
11840 if (!inst
.operands
[1].present
)
11841 inst
.operands
[1] = inst
.operands
[0];
11843 va_start (ap
, shape
);
11845 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
11850 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11852 if (!inst
.operands
[j
].present
)
11858 switch (neon_shape_tab
[shape
].el
[j
])
11861 if (!(inst
.operands
[j
].isreg
11862 && inst
.operands
[j
].isvec
11863 && inst
.operands
[j
].issingle
11864 && !inst
.operands
[j
].isquad
))
11869 if (!(inst
.operands
[j
].isreg
11870 && inst
.operands
[j
].isvec
11871 && !inst
.operands
[j
].isquad
11872 && !inst
.operands
[j
].issingle
))
11877 if (!(inst
.operands
[j
].isreg
11878 && !inst
.operands
[j
].isvec
))
11883 if (!(inst
.operands
[j
].isreg
11884 && inst
.operands
[j
].isvec
11885 && inst
.operands
[j
].isquad
11886 && !inst
.operands
[j
].issingle
))
11891 if (!(!inst
.operands
[j
].isreg
11892 && !inst
.operands
[j
].isscalar
))
11897 if (!(!inst
.operands
[j
].isreg
11898 && inst
.operands
[j
].isscalar
))
11914 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11915 first_error (_("invalid instruction shape"));
11920 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11921 means the Q bit should be set). */
11924 neon_quad (enum neon_shape shape
)
11926 return neon_shape_class
[shape
] == SC_QUAD
;
11930 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11933 /* Allow modification to be made to types which are constrained to be
11934 based on the key element, based on bits set alongside N_EQK. */
11935 if ((typebits
& N_EQK
) != 0)
11937 if ((typebits
& N_HLF
) != 0)
11939 else if ((typebits
& N_DBL
) != 0)
11941 if ((typebits
& N_SGN
) != 0)
11942 *g_type
= NT_signed
;
11943 else if ((typebits
& N_UNS
) != 0)
11944 *g_type
= NT_unsigned
;
11945 else if ((typebits
& N_INT
) != 0)
11946 *g_type
= NT_integer
;
11947 else if ((typebits
& N_FLT
) != 0)
11948 *g_type
= NT_float
;
11949 else if ((typebits
& N_SIZ
) != 0)
11950 *g_type
= NT_untyped
;
11954 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11955 operand type, i.e. the single type specified in a Neon instruction when it
11956 is the only one given. */
11958 static struct neon_type_el
11959 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11961 struct neon_type_el dest
= *key
;
11963 gas_assert ((thisarg
& N_EQK
) != 0);
11965 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11970 /* Convert Neon type and size into compact bitmask representation. */
11972 static enum neon_type_mask
11973 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11980 case 8: return N_8
;
11981 case 16: return N_16
;
11982 case 32: return N_32
;
11983 case 64: return N_64
;
11991 case 8: return N_I8
;
11992 case 16: return N_I16
;
11993 case 32: return N_I32
;
11994 case 64: return N_I64
;
12002 case 16: return N_F16
;
12003 case 32: return N_F32
;
12004 case 64: return N_F64
;
12012 case 8: return N_P8
;
12013 case 16: return N_P16
;
12021 case 8: return N_S8
;
12022 case 16: return N_S16
;
12023 case 32: return N_S32
;
12024 case 64: return N_S64
;
12032 case 8: return N_U8
;
12033 case 16: return N_U16
;
12034 case 32: return N_U32
;
12035 case 64: return N_U64
;
12046 /* Convert compact Neon bitmask type representation to a type and size. Only
12047 handles the case where a single bit is set in the mask. */
12050 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12051 enum neon_type_mask mask
)
12053 if ((mask
& N_EQK
) != 0)
12056 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12058 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12060 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12062 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12067 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12069 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12070 *type
= NT_unsigned
;
12071 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12072 *type
= NT_integer
;
12073 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12074 *type
= NT_untyped
;
12075 else if ((mask
& (N_P8
| N_P16
)) != 0)
12077 else if ((mask
& (N_F32
| N_F64
)) != 0)
12085 /* Modify a bitmask of allowed types. This is only needed for type
12089 modify_types_allowed (unsigned allowed
, unsigned mods
)
12092 enum neon_el_type type
;
12098 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12100 if (el_type_of_type_chk (&type
, &size
,
12101 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12103 neon_modify_type_size (mods
, &type
, &size
);
12104 destmask
|= type_chk_of_el_type (type
, size
);
12111 /* Check type and return type classification.
12112 The manual states (paraphrase): If one datatype is given, it indicates the
12114 - the second operand, if there is one
12115 - the operand, if there is no second operand
12116 - the result, if there are no operands.
12117 This isn't quite good enough though, so we use a concept of a "key" datatype
12118 which is set on a per-instruction basis, which is the one which matters when
12119 only one data type is written.
12120 Note: this function has side-effects (e.g. filling in missing operands). All
12121 Neon instructions should call it before performing bit encoding. */
12123 static struct neon_type_el
12124 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12127 unsigned i
, pass
, key_el
= 0;
12128 unsigned types
[NEON_MAX_TYPE_ELS
];
12129 enum neon_el_type k_type
= NT_invtype
;
12130 unsigned k_size
= -1u;
12131 struct neon_type_el badtype
= {NT_invtype
, -1};
12132 unsigned key_allowed
= 0;
12134 /* Optional registers in Neon instructions are always (not) in operand 1.
12135 Fill in the missing operand here, if it was omitted. */
12136 if (els
> 1 && !inst
.operands
[1].present
)
12137 inst
.operands
[1] = inst
.operands
[0];
12139 /* Suck up all the varargs. */
12141 for (i
= 0; i
< els
; i
++)
12143 unsigned thisarg
= va_arg (ap
, unsigned);
12144 if (thisarg
== N_IGNORE_TYPE
)
12149 types
[i
] = thisarg
;
12150 if ((thisarg
& N_KEY
) != 0)
12155 if (inst
.vectype
.elems
> 0)
12156 for (i
= 0; i
< els
; i
++)
12157 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12159 first_error (_("types specified in both the mnemonic and operands"));
12163 /* Duplicate inst.vectype elements here as necessary.
12164 FIXME: No idea if this is exactly the same as the ARM assembler,
12165 particularly when an insn takes one register and one non-register
12167 if (inst
.vectype
.elems
== 1 && els
> 1)
12170 inst
.vectype
.elems
= els
;
12171 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12172 for (j
= 0; j
< els
; j
++)
12174 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12177 else if (inst
.vectype
.elems
== 0 && els
> 0)
12180 /* No types were given after the mnemonic, so look for types specified
12181 after each operand. We allow some flexibility here; as long as the
12182 "key" operand has a type, we can infer the others. */
12183 for (j
= 0; j
< els
; j
++)
12184 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12185 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12187 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12189 for (j
= 0; j
< els
; j
++)
12190 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12191 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12196 first_error (_("operand types can't be inferred"));
12200 else if (inst
.vectype
.elems
!= els
)
12202 first_error (_("type specifier has the wrong number of parts"));
12206 for (pass
= 0; pass
< 2; pass
++)
12208 for (i
= 0; i
< els
; i
++)
12210 unsigned thisarg
= types
[i
];
12211 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12212 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12213 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12214 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12216 /* Decay more-specific signed & unsigned types to sign-insensitive
12217 integer types if sign-specific variants are unavailable. */
12218 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12219 && (types_allowed
& N_SU_ALL
) == 0)
12220 g_type
= NT_integer
;
12222 /* If only untyped args are allowed, decay any more specific types to
12223 them. Some instructions only care about signs for some element
12224 sizes, so handle that properly. */
12225 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12226 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12227 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12228 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12229 g_type
= NT_untyped
;
12233 if ((thisarg
& N_KEY
) != 0)
12237 key_allowed
= thisarg
& ~N_KEY
;
12242 if ((thisarg
& N_VFP
) != 0)
12244 enum neon_shape_el regshape
;
12245 unsigned regwidth
, match
;
12247 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12250 first_error (_("invalid instruction shape"));
12253 regshape
= neon_shape_tab
[ns
].el
[i
];
12254 regwidth
= neon_shape_el_size
[regshape
];
12256 /* In VFP mode, operands must match register widths. If we
12257 have a key operand, use its width, else use the width of
12258 the current operand. */
12264 if (regwidth
!= match
)
12266 first_error (_("operand size must match register width"));
12271 if ((thisarg
& N_EQK
) == 0)
12273 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12275 if ((given_type
& types_allowed
) == 0)
12277 first_error (_("bad type in Neon instruction"));
12283 enum neon_el_type mod_k_type
= k_type
;
12284 unsigned mod_k_size
= k_size
;
12285 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12286 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12288 first_error (_("inconsistent types in Neon instruction"));
12296 return inst
.vectype
.el
[key_el
];
12299 /* Neon-style VFP instruction forwarding. */
12301 /* Thumb VFP instructions have 0xE in the condition field. */
12304 do_vfp_cond_or_thumb (void)
12309 inst
.instruction
|= 0xe0000000;
12311 inst
.instruction
|= inst
.cond
<< 28;
12314 /* Look up and encode a simple mnemonic, for use as a helper function for the
12315 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12316 etc. It is assumed that operand parsing has already been done, and that the
12317 operands are in the form expected by the given opcode (this isn't necessarily
12318 the same as the form in which they were parsed, hence some massaging must
12319 take place before this function is called).
12320 Checks current arch version against that in the looked-up opcode. */
12323 do_vfp_nsyn_opcode (const char *opname
)
12325 const struct asm_opcode
*opcode
;
12327 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12332 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12333 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12340 inst
.instruction
= opcode
->tvalue
;
12341 opcode
->tencode ();
12345 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12346 opcode
->aencode ();
12351 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12353 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12358 do_vfp_nsyn_opcode ("fadds");
12360 do_vfp_nsyn_opcode ("fsubs");
12365 do_vfp_nsyn_opcode ("faddd");
12367 do_vfp_nsyn_opcode ("fsubd");
12371 /* Check operand types to see if this is a VFP instruction, and if so call
12375 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12377 enum neon_shape rs
;
12378 struct neon_type_el et
;
12383 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12384 et
= neon_check_type (2, rs
,
12385 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12389 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12390 et
= neon_check_type (3, rs
,
12391 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12398 if (et
.type
!= NT_invtype
)
12409 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12411 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12416 do_vfp_nsyn_opcode ("fmacs");
12418 do_vfp_nsyn_opcode ("fnmacs");
12423 do_vfp_nsyn_opcode ("fmacd");
12425 do_vfp_nsyn_opcode ("fnmacd");
12430 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12432 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12437 do_vfp_nsyn_opcode ("ffmas");
12439 do_vfp_nsyn_opcode ("ffnmas");
12444 do_vfp_nsyn_opcode ("ffmad");
12446 do_vfp_nsyn_opcode ("ffnmad");
12451 do_vfp_nsyn_mul (enum neon_shape rs
)
12454 do_vfp_nsyn_opcode ("fmuls");
12456 do_vfp_nsyn_opcode ("fmuld");
12460 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12462 int is_neg
= (inst
.instruction
& 0x80) != 0;
12463 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12468 do_vfp_nsyn_opcode ("fnegs");
12470 do_vfp_nsyn_opcode ("fabss");
12475 do_vfp_nsyn_opcode ("fnegd");
12477 do_vfp_nsyn_opcode ("fabsd");
12481 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12482 insns belong to Neon, and are handled elsewhere. */
12485 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12487 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12491 do_vfp_nsyn_opcode ("fldmdbs");
12493 do_vfp_nsyn_opcode ("fldmias");
12498 do_vfp_nsyn_opcode ("fstmdbs");
12500 do_vfp_nsyn_opcode ("fstmias");
12505 do_vfp_nsyn_sqrt (void)
12507 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12508 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12511 do_vfp_nsyn_opcode ("fsqrts");
12513 do_vfp_nsyn_opcode ("fsqrtd");
12517 do_vfp_nsyn_div (void)
12519 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12520 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12521 N_F32
| N_F64
| N_KEY
| N_VFP
);
12524 do_vfp_nsyn_opcode ("fdivs");
12526 do_vfp_nsyn_opcode ("fdivd");
12530 do_vfp_nsyn_nmul (void)
12532 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12533 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12534 N_F32
| N_F64
| N_KEY
| N_VFP
);
12538 NEON_ENCODE (SINGLE
, inst
);
12539 do_vfp_sp_dyadic ();
12543 NEON_ENCODE (DOUBLE
, inst
);
12544 do_vfp_dp_rd_rn_rm ();
12546 do_vfp_cond_or_thumb ();
12550 do_vfp_nsyn_cmp (void)
12552 if (inst
.operands
[1].isreg
)
12554 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12555 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12559 NEON_ENCODE (SINGLE
, inst
);
12560 do_vfp_sp_monadic ();
12564 NEON_ENCODE (DOUBLE
, inst
);
12565 do_vfp_dp_rd_rm ();
12570 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
12571 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
12573 switch (inst
.instruction
& 0x0fffffff)
12576 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
12579 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
12587 NEON_ENCODE (SINGLE
, inst
);
12588 do_vfp_sp_compare_z ();
12592 NEON_ENCODE (DOUBLE
, inst
);
12596 do_vfp_cond_or_thumb ();
12600 nsyn_insert_sp (void)
12602 inst
.operands
[1] = inst
.operands
[0];
12603 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
12604 inst
.operands
[0].reg
= REG_SP
;
12605 inst
.operands
[0].isreg
= 1;
12606 inst
.operands
[0].writeback
= 1;
12607 inst
.operands
[0].present
= 1;
12611 do_vfp_nsyn_push (void)
12614 if (inst
.operands
[1].issingle
)
12615 do_vfp_nsyn_opcode ("fstmdbs");
12617 do_vfp_nsyn_opcode ("fstmdbd");
12621 do_vfp_nsyn_pop (void)
12624 if (inst
.operands
[1].issingle
)
12625 do_vfp_nsyn_opcode ("fldmias");
12627 do_vfp_nsyn_opcode ("fldmiad");
12630 /* Fix up Neon data-processing instructions, ORing in the correct bits for
12631 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
12634 neon_dp_fixup (struct arm_it
* insn
)
12636 unsigned int i
= insn
->instruction
;
12641 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
12652 insn
->instruction
= i
;
12655 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
12659 neon_logbits (unsigned x
)
12661 return ffs (x
) - 4;
12664 #define LOW4(R) ((R) & 0xf)
12665 #define HI1(R) (((R) >> 4) & 1)
12667 /* Encode insns with bit pattern:
12669 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12670 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
12672 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
12673 different meaning for some instruction. */
12676 neon_three_same (int isquad
, int ubit
, int size
)
12678 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12679 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12680 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12681 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12682 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12683 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12684 inst
.instruction
|= (isquad
!= 0) << 6;
12685 inst
.instruction
|= (ubit
!= 0) << 24;
12687 inst
.instruction
|= neon_logbits (size
) << 20;
12689 neon_dp_fixup (&inst
);
12692 /* Encode instructions of the form:
12694 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
12695 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
12697 Don't write size if SIZE == -1. */
12700 neon_two_same (int qbit
, int ubit
, int size
)
12702 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12703 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12704 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12705 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12706 inst
.instruction
|= (qbit
!= 0) << 6;
12707 inst
.instruction
|= (ubit
!= 0) << 24;
12710 inst
.instruction
|= neon_logbits (size
) << 18;
12712 neon_dp_fixup (&inst
);
12715 /* Neon instruction encoders, in approximate order of appearance. */
12718 do_neon_dyadic_i_su (void)
12720 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12721 struct neon_type_el et
= neon_check_type (3, rs
,
12722 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12723 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12727 do_neon_dyadic_i64_su (void)
12729 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12730 struct neon_type_el et
= neon_check_type (3, rs
,
12731 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12732 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12736 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12739 unsigned size
= et
.size
>> 3;
12740 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12741 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12742 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12743 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12744 inst
.instruction
|= (isquad
!= 0) << 6;
12745 inst
.instruction
|= immbits
<< 16;
12746 inst
.instruction
|= (size
>> 3) << 7;
12747 inst
.instruction
|= (size
& 0x7) << 19;
12749 inst
.instruction
|= (uval
!= 0) << 24;
12751 neon_dp_fixup (&inst
);
12755 do_neon_shl_imm (void)
12757 if (!inst
.operands
[2].isreg
)
12759 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12760 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12761 NEON_ENCODE (IMMED
, inst
);
12762 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12766 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12767 struct neon_type_el et
= neon_check_type (3, rs
,
12768 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12771 /* VSHL/VQSHL 3-register variants have syntax such as:
12773 whereas other 3-register operations encoded by neon_three_same have
12776 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12778 tmp
= inst
.operands
[2].reg
;
12779 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12780 inst
.operands
[1].reg
= tmp
;
12781 NEON_ENCODE (INTEGER
, inst
);
12782 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12787 do_neon_qshl_imm (void)
12789 if (!inst
.operands
[2].isreg
)
12791 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12792 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12794 NEON_ENCODE (IMMED
, inst
);
12795 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12796 inst
.operands
[2].imm
);
12800 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12801 struct neon_type_el et
= neon_check_type (3, rs
,
12802 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12805 /* See note in do_neon_shl_imm. */
12806 tmp
= inst
.operands
[2].reg
;
12807 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12808 inst
.operands
[1].reg
= tmp
;
12809 NEON_ENCODE (INTEGER
, inst
);
12810 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12815 do_neon_rshl (void)
12817 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12818 struct neon_type_el et
= neon_check_type (3, rs
,
12819 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12822 tmp
= inst
.operands
[2].reg
;
12823 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12824 inst
.operands
[1].reg
= tmp
;
12825 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12829 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12831 /* Handle .I8 pseudo-instructions. */
12834 /* Unfortunately, this will make everything apart from zero out-of-range.
12835 FIXME is this the intended semantics? There doesn't seem much point in
12836 accepting .I8 if so. */
12837 immediate
|= immediate
<< 8;
12843 if (immediate
== (immediate
& 0x000000ff))
12845 *immbits
= immediate
;
12848 else if (immediate
== (immediate
& 0x0000ff00))
12850 *immbits
= immediate
>> 8;
12853 else if (immediate
== (immediate
& 0x00ff0000))
12855 *immbits
= immediate
>> 16;
12858 else if (immediate
== (immediate
& 0xff000000))
12860 *immbits
= immediate
>> 24;
12863 if ((immediate
& 0xffff) != (immediate
>> 16))
12864 goto bad_immediate
;
12865 immediate
&= 0xffff;
12868 if (immediate
== (immediate
& 0x000000ff))
12870 *immbits
= immediate
;
12873 else if (immediate
== (immediate
& 0x0000ff00))
12875 *immbits
= immediate
>> 8;
12880 first_error (_("immediate value out of range"));
12884 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12888 neon_bits_same_in_bytes (unsigned imm
)
12890 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12891 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12892 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12893 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12896 /* For immediate of above form, return 0bABCD. */
12899 neon_squash_bits (unsigned imm
)
12901 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12902 | ((imm
& 0x01000000) >> 21);
12905 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12908 neon_qfloat_bits (unsigned imm
)
12910 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12913 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12914 the instruction. *OP is passed as the initial value of the op field, and
12915 may be set to a different value depending on the constant (i.e.
12916 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12917 MVN). If the immediate looks like a repeated pattern then also
12918 try smaller element sizes. */
12921 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12922 unsigned *immbits
, int *op
, int size
,
12923 enum neon_el_type type
)
12925 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12927 if (type
== NT_float
&& !float_p
)
12930 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12932 if (size
!= 32 || *op
== 1)
12934 *immbits
= neon_qfloat_bits (immlo
);
12940 if (neon_bits_same_in_bytes (immhi
)
12941 && neon_bits_same_in_bytes (immlo
))
12945 *immbits
= (neon_squash_bits (immhi
) << 4)
12946 | neon_squash_bits (immlo
);
12951 if (immhi
!= immlo
)
12957 if (immlo
== (immlo
& 0x000000ff))
12962 else if (immlo
== (immlo
& 0x0000ff00))
12964 *immbits
= immlo
>> 8;
12967 else if (immlo
== (immlo
& 0x00ff0000))
12969 *immbits
= immlo
>> 16;
12972 else if (immlo
== (immlo
& 0xff000000))
12974 *immbits
= immlo
>> 24;
12977 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12979 *immbits
= (immlo
>> 8) & 0xff;
12982 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12984 *immbits
= (immlo
>> 16) & 0xff;
12988 if ((immlo
& 0xffff) != (immlo
>> 16))
12995 if (immlo
== (immlo
& 0x000000ff))
13000 else if (immlo
== (immlo
& 0x0000ff00))
13002 *immbits
= immlo
>> 8;
13006 if ((immlo
& 0xff) != (immlo
>> 8))
13011 if (immlo
== (immlo
& 0x000000ff))
13013 /* Don't allow MVN with 8-bit immediate. */
13023 /* Write immediate bits [7:0] to the following locations:
13025 |28/24|23 19|18 16|15 4|3 0|
13026 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13028 This function is used by VMOV/VMVN/VORR/VBIC. */
13031 neon_write_immbits (unsigned immbits
)
13033 inst
.instruction
|= immbits
& 0xf;
13034 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13035 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13038 /* Invert low-order SIZE bits of XHI:XLO. */
13041 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13043 unsigned immlo
= xlo
? *xlo
: 0;
13044 unsigned immhi
= xhi
? *xhi
: 0;
13049 immlo
= (~immlo
) & 0xff;
13053 immlo
= (~immlo
) & 0xffff;
13057 immhi
= (~immhi
) & 0xffffffff;
13058 /* fall through. */
13061 immlo
= (~immlo
) & 0xffffffff;
13076 do_neon_logic (void)
13078 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13080 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13081 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13082 /* U bit and size field were set as part of the bitmask. */
13083 NEON_ENCODE (INTEGER
, inst
);
13084 neon_three_same (neon_quad (rs
), 0, -1);
13088 const int three_ops_form
= (inst
.operands
[2].present
13089 && !inst
.operands
[2].isreg
);
13090 const int immoperand
= (three_ops_form
? 2 : 1);
13091 enum neon_shape rs
= (three_ops_form
13092 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13093 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13094 struct neon_type_el et
= neon_check_type (2, rs
,
13095 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13096 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13100 if (et
.type
== NT_invtype
)
13103 if (three_ops_form
)
13104 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13105 _("first and second operands shall be the same register"));
13107 NEON_ENCODE (IMMED
, inst
);
13109 immbits
= inst
.operands
[immoperand
].imm
;
13112 /* .i64 is a pseudo-op, so the immediate must be a repeating
13114 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13115 inst
.operands
[immoperand
].reg
: 0))
13117 /* Set immbits to an invalid constant. */
13118 immbits
= 0xdeadbeef;
13125 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13129 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13133 /* Pseudo-instruction for VBIC. */
13134 neon_invert_size (&immbits
, 0, et
.size
);
13135 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13139 /* Pseudo-instruction for VORR. */
13140 neon_invert_size (&immbits
, 0, et
.size
);
13141 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13151 inst
.instruction
|= neon_quad (rs
) << 6;
13152 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13153 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13154 inst
.instruction
|= cmode
<< 8;
13155 neon_write_immbits (immbits
);
13157 neon_dp_fixup (&inst
);
13162 do_neon_bitfield (void)
13164 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13165 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13166 neon_three_same (neon_quad (rs
), 0, -1);
13170 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13173 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13174 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13176 if (et
.type
== NT_float
)
13178 NEON_ENCODE (FLOAT
, inst
);
13179 neon_three_same (neon_quad (rs
), 0, -1);
13183 NEON_ENCODE (INTEGER
, inst
);
13184 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13189 do_neon_dyadic_if_su (void)
13191 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13195 do_neon_dyadic_if_su_d (void)
13197 /* This version only allow D registers, but that constraint is enforced during
13198 operand parsing so we don't need to do anything extra here. */
13199 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13203 do_neon_dyadic_if_i_d (void)
13205 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13206 affected if we specify unsigned args. */
13207 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13210 enum vfp_or_neon_is_neon_bits
13213 NEON_CHECK_ARCH
= 2
13216 /* Call this function if an instruction which may have belonged to the VFP or
13217 Neon instruction sets, but turned out to be a Neon instruction (due to the
13218 operand types involved, etc.). We have to check and/or fix-up a couple of
13221 - Make sure the user hasn't attempted to make a Neon instruction
13223 - Alter the value in the condition code field if necessary.
13224 - Make sure that the arch supports Neon instructions.
13226 Which of these operations take place depends on bits from enum
13227 vfp_or_neon_is_neon_bits.
13229 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13230 current instruction's condition is COND_ALWAYS, the condition field is
13231 changed to inst.uncond_value. This is necessary because instructions shared
13232 between VFP and Neon may be conditional for the VFP variants only, and the
13233 unconditional Neon version must have, e.g., 0xF in the condition field. */
13236 vfp_or_neon_is_neon (unsigned check
)
13238 /* Conditions are always legal in Thumb mode (IT blocks). */
13239 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13241 if (inst
.cond
!= COND_ALWAYS
)
13243 first_error (_(BAD_COND
));
13246 if (inst
.uncond_value
!= -1)
13247 inst
.instruction
|= inst
.uncond_value
<< 28;
13250 if ((check
& NEON_CHECK_ARCH
)
13251 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13253 first_error (_(BAD_FPU
));
13261 do_neon_addsub_if_i (void)
13263 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13266 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13269 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13270 affected if we specify unsigned args. */
13271 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13274 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13276 V<op> A,B (A is operand 0, B is operand 2)
13281 so handle that case specially. */
13284 neon_exchange_operands (void)
13286 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13287 if (inst
.operands
[1].present
)
13289 /* Swap operands[1] and operands[2]. */
13290 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13291 inst
.operands
[1] = inst
.operands
[2];
13292 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13296 inst
.operands
[1] = inst
.operands
[2];
13297 inst
.operands
[2] = inst
.operands
[0];
13302 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13304 if (inst
.operands
[2].isreg
)
13307 neon_exchange_operands ();
13308 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13312 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13313 struct neon_type_el et
= neon_check_type (2, rs
,
13314 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13316 NEON_ENCODE (IMMED
, inst
);
13317 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13318 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13319 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13320 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13321 inst
.instruction
|= neon_quad (rs
) << 6;
13322 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13323 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13325 neon_dp_fixup (&inst
);
13332 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13336 do_neon_cmp_inv (void)
13338 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13344 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13347 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13348 scalars, which are encoded in 5 bits, M : Rm.
13349 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13350 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13354 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13356 unsigned regno
= NEON_SCALAR_REG (scalar
);
13357 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13362 if (regno
> 7 || elno
> 3)
13364 return regno
| (elno
<< 3);
13367 if (regno
> 15 || elno
> 1)
13369 return regno
| (elno
<< 4);
13373 first_error (_("scalar out of range for multiply instruction"));
13379 /* Encode multiply / multiply-accumulate scalar instructions. */
13382 neon_mul_mac (struct neon_type_el et
, int ubit
)
13386 /* Give a more helpful error message if we have an invalid type. */
13387 if (et
.type
== NT_invtype
)
13390 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13391 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13392 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13393 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13394 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13395 inst
.instruction
|= LOW4 (scalar
);
13396 inst
.instruction
|= HI1 (scalar
) << 5;
13397 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13398 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13399 inst
.instruction
|= (ubit
!= 0) << 24;
13401 neon_dp_fixup (&inst
);
13405 do_neon_mac_maybe_scalar (void)
13407 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13410 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13413 if (inst
.operands
[2].isscalar
)
13415 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13416 struct neon_type_el et
= neon_check_type (3, rs
,
13417 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13418 NEON_ENCODE (SCALAR
, inst
);
13419 neon_mul_mac (et
, neon_quad (rs
));
13423 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13424 affected if we specify unsigned args. */
13425 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13430 do_neon_fmac (void)
13432 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13435 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13438 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13444 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13445 struct neon_type_el et
= neon_check_type (3, rs
,
13446 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13447 neon_three_same (neon_quad (rs
), 0, et
.size
);
13450 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13451 same types as the MAC equivalents. The polynomial type for this instruction
13452 is encoded the same as the integer type. */
13457 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13460 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13463 if (inst
.operands
[2].isscalar
)
13464 do_neon_mac_maybe_scalar ();
13466 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13470 do_neon_qdmulh (void)
13472 if (inst
.operands
[2].isscalar
)
13474 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13475 struct neon_type_el et
= neon_check_type (3, rs
,
13476 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13477 NEON_ENCODE (SCALAR
, inst
);
13478 neon_mul_mac (et
, neon_quad (rs
));
13482 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13483 struct neon_type_el et
= neon_check_type (3, rs
,
13484 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13485 NEON_ENCODE (INTEGER
, inst
);
13486 /* The U bit (rounding) comes from bit mask. */
13487 neon_three_same (neon_quad (rs
), 0, et
.size
);
13492 do_neon_fcmp_absolute (void)
13494 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13495 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13496 /* Size field comes from bit mask. */
13497 neon_three_same (neon_quad (rs
), 1, -1);
13501 do_neon_fcmp_absolute_inv (void)
13503 neon_exchange_operands ();
13504 do_neon_fcmp_absolute ();
13508 do_neon_step (void)
13510 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13511 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13512 neon_three_same (neon_quad (rs
), 0, -1);
13516 do_neon_abs_neg (void)
13518 enum neon_shape rs
;
13519 struct neon_type_el et
;
13521 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13524 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13527 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13528 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13530 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13531 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13532 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13533 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13534 inst
.instruction
|= neon_quad (rs
) << 6;
13535 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13536 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13538 neon_dp_fixup (&inst
);
13544 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13545 struct neon_type_el et
= neon_check_type (2, rs
,
13546 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13547 int imm
= inst
.operands
[2].imm
;
13548 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13549 _("immediate out of range for insert"));
13550 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13556 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13557 struct neon_type_el et
= neon_check_type (2, rs
,
13558 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13559 int imm
= inst
.operands
[2].imm
;
13560 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13561 _("immediate out of range for insert"));
13562 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
13566 do_neon_qshlu_imm (void)
13568 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13569 struct neon_type_el et
= neon_check_type (2, rs
,
13570 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
13571 int imm
= inst
.operands
[2].imm
;
13572 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13573 _("immediate out of range for shift"));
13574 /* Only encodes the 'U present' variant of the instruction.
13575 In this case, signed types have OP (bit 8) set to 0.
13576 Unsigned types have OP set to 1. */
13577 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
13578 /* The rest of the bits are the same as other immediate shifts. */
13579 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13583 do_neon_qmovn (void)
13585 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13586 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13587 /* Saturating move where operands can be signed or unsigned, and the
13588 destination has the same signedness. */
13589 NEON_ENCODE (INTEGER
, inst
);
13590 if (et
.type
== NT_unsigned
)
13591 inst
.instruction
|= 0xc0;
13593 inst
.instruction
|= 0x80;
13594 neon_two_same (0, 1, et
.size
/ 2);
13598 do_neon_qmovun (void)
13600 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13601 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13602 /* Saturating move with unsigned results. Operands must be signed. */
13603 NEON_ENCODE (INTEGER
, inst
);
13604 neon_two_same (0, 1, et
.size
/ 2);
13608 do_neon_rshift_sat_narrow (void)
13610 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13611 or unsigned. If operands are unsigned, results must also be unsigned. */
13612 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13613 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
13614 int imm
= inst
.operands
[2].imm
;
13615 /* This gets the bounds check, size encoding and immediate bits calculation
13619 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
13620 VQMOVN.I<size> <Dd>, <Qm>. */
13623 inst
.operands
[2].present
= 0;
13624 inst
.instruction
= N_MNEM_vqmovn
;
13629 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13630 _("immediate out of range"));
13631 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
13635 do_neon_rshift_sat_narrow_u (void)
13637 /* FIXME: Types for narrowing. If operands are signed, results can be signed
13638 or unsigned. If operands are unsigned, results must also be unsigned. */
13639 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13640 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
13641 int imm
= inst
.operands
[2].imm
;
13642 /* This gets the bounds check, size encoding and immediate bits calculation
13646 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
13647 VQMOVUN.I<size> <Dd>, <Qm>. */
13650 inst
.operands
[2].present
= 0;
13651 inst
.instruction
= N_MNEM_vqmovun
;
13656 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13657 _("immediate out of range"));
13658 /* FIXME: The manual is kind of unclear about what value U should have in
13659 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
13661 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
13665 do_neon_movn (void)
13667 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
13668 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13669 NEON_ENCODE (INTEGER
, inst
);
13670 neon_two_same (0, 1, et
.size
/ 2);
13674 do_neon_rshift_narrow (void)
13676 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
13677 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
13678 int imm
= inst
.operands
[2].imm
;
13679 /* This gets the bounds check, size encoding and immediate bits calculation
13683 /* If immediate is zero then we are a pseudo-instruction for
13684 VMOVN.I<size> <Dd>, <Qm> */
13687 inst
.operands
[2].present
= 0;
13688 inst
.instruction
= N_MNEM_vmovn
;
13693 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13694 _("immediate out of range for narrowing operation"));
13695 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
13699 do_neon_shll (void)
13701 /* FIXME: Type checking when lengthening. */
13702 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
13703 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
13704 unsigned imm
= inst
.operands
[2].imm
;
13706 if (imm
== et
.size
)
13708 /* Maximum shift variant. */
13709 NEON_ENCODE (INTEGER
, inst
);
13710 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13711 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13712 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13713 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13714 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13716 neon_dp_fixup (&inst
);
13720 /* A more-specific type check for non-max versions. */
13721 et
= neon_check_type (2, NS_QDI
,
13722 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13723 NEON_ENCODE (IMMED
, inst
);
13724 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13728 /* Check the various types for the VCVT instruction, and return which version
13729 the current instruction is. */
13732 neon_cvt_flavour (enum neon_shape rs
)
13734 #define CVT_VAR(C,X,Y) \
13735 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13736 if (et.type != NT_invtype) \
13738 inst.error = NULL; \
13741 struct neon_type_el et
;
13742 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13743 || rs
== NS_FF
) ? N_VFP
: 0;
13744 /* The instruction versions which take an immediate take one register
13745 argument, which is extended to the width of the full register. Thus the
13746 "source" and "destination" registers must have the same width. Hack that
13747 here by making the size equal to the key (wider, in this case) operand. */
13748 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13750 CVT_VAR (0, N_S32
, N_F32
);
13751 CVT_VAR (1, N_U32
, N_F32
);
13752 CVT_VAR (2, N_F32
, N_S32
);
13753 CVT_VAR (3, N_F32
, N_U32
);
13754 /* Half-precision conversions. */
13755 CVT_VAR (4, N_F32
, N_F16
);
13756 CVT_VAR (5, N_F16
, N_F32
);
13760 /* VFP instructions. */
13761 CVT_VAR (6, N_F32
, N_F64
);
13762 CVT_VAR (7, N_F64
, N_F32
);
13763 CVT_VAR (8, N_S32
, N_F64
| key
);
13764 CVT_VAR (9, N_U32
, N_F64
| key
);
13765 CVT_VAR (10, N_F64
| key
, N_S32
);
13766 CVT_VAR (11, N_F64
| key
, N_U32
);
13767 /* VFP instructions with bitshift. */
13768 CVT_VAR (12, N_F32
| key
, N_S16
);
13769 CVT_VAR (13, N_F32
| key
, N_U16
);
13770 CVT_VAR (14, N_F64
| key
, N_S16
);
13771 CVT_VAR (15, N_F64
| key
, N_U16
);
13772 CVT_VAR (16, N_S16
, N_F32
| key
);
13773 CVT_VAR (17, N_U16
, N_F32
| key
);
13774 CVT_VAR (18, N_S16
, N_F64
| key
);
13775 CVT_VAR (19, N_U16
, N_F64
| key
);
13781 /* Neon-syntax VFP conversions. */
13784 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13786 const char *opname
= 0;
13788 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13790 /* Conversions with immediate bitshift. */
13791 const char *enc
[] =
13815 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13817 opname
= enc
[flavour
];
13818 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13819 _("operands 0 and 1 must be the same register"));
13820 inst
.operands
[1] = inst
.operands
[2];
13821 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13826 /* Conversions without bitshift. */
13827 const char *enc
[] =
13843 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13844 opname
= enc
[flavour
];
13848 do_vfp_nsyn_opcode (opname
);
13852 do_vfp_nsyn_cvtz (void)
13854 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13855 int flavour
= neon_cvt_flavour (rs
);
13856 const char *enc
[] =
13870 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13871 do_vfp_nsyn_opcode (enc
[flavour
]);
13875 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
13877 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13878 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13879 int flavour
= neon_cvt_flavour (rs
);
13881 /* PR11109: Handle round-to-zero for VCVT conversions. */
13883 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
13884 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
13885 && (rs
== NS_FD
|| rs
== NS_FF
))
13887 do_vfp_nsyn_cvtz ();
13891 /* VFP rather than Neon conversions. */
13894 do_vfp_nsyn_cvt (rs
, flavour
);
13904 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13906 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13909 /* Fixed-point conversion with #0 immediate is encoded as an
13910 integer conversion. */
13911 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13913 immbits
= 32 - inst
.operands
[2].imm
;
13914 NEON_ENCODE (IMMED
, inst
);
13916 inst
.instruction
|= enctab
[flavour
];
13917 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13918 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13919 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13920 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13921 inst
.instruction
|= neon_quad (rs
) << 6;
13922 inst
.instruction
|= 1 << 21;
13923 inst
.instruction
|= immbits
<< 16;
13925 neon_dp_fixup (&inst
);
13933 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13935 NEON_ENCODE (INTEGER
, inst
);
13937 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13941 inst
.instruction
|= enctab
[flavour
];
13943 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13944 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13945 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13946 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13947 inst
.instruction
|= neon_quad (rs
) << 6;
13948 inst
.instruction
|= 2 << 18;
13950 neon_dp_fixup (&inst
);
13954 /* Half-precision conversions for Advanced SIMD -- neon. */
13959 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13961 as_bad (_("operand size must match register width"));
13966 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13968 as_bad (_("operand size must match register width"));
13973 inst
.instruction
= 0x3b60600;
13975 inst
.instruction
= 0x3b60700;
13977 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13978 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13979 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13980 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13981 neon_dp_fixup (&inst
);
13985 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13986 do_vfp_nsyn_cvt (rs
, flavour
);
13991 do_neon_cvtr (void)
13993 do_neon_cvt_1 (FALSE
);
13999 do_neon_cvt_1 (TRUE
);
14003 do_neon_cvtb (void)
14005 inst
.instruction
= 0xeb20a40;
14007 /* The sizes are attached to the mnemonic. */
14008 if (inst
.vectype
.el
[0].type
!= NT_invtype
14009 && inst
.vectype
.el
[0].size
== 16)
14010 inst
.instruction
|= 0x00010000;
14012 /* Programmer's syntax: the sizes are attached to the operands. */
14013 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14014 && inst
.operands
[0].vectype
.size
== 16)
14015 inst
.instruction
|= 0x00010000;
14017 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14018 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14019 do_vfp_cond_or_thumb ();
14024 do_neon_cvtt (void)
14027 inst
.instruction
|= 0x80;
14031 neon_move_immediate (void)
14033 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14034 struct neon_type_el et
= neon_check_type (2, rs
,
14035 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14036 unsigned immlo
, immhi
= 0, immbits
;
14037 int op
, cmode
, float_p
;
14039 constraint (et
.type
== NT_invtype
,
14040 _("operand size must be specified for immediate VMOV"));
14042 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14043 op
= (inst
.instruction
& (1 << 5)) != 0;
14045 immlo
= inst
.operands
[1].imm
;
14046 if (inst
.operands
[1].regisimm
)
14047 immhi
= inst
.operands
[1].reg
;
14049 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14050 _("immediate has bits set outside the operand size"));
14052 float_p
= inst
.operands
[1].immisfloat
;
14054 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14055 et
.size
, et
.type
)) == FAIL
)
14057 /* Invert relevant bits only. */
14058 neon_invert_size (&immlo
, &immhi
, et
.size
);
14059 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14060 with one or the other; those cases are caught by
14061 neon_cmode_for_move_imm. */
14063 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14064 &op
, et
.size
, et
.type
)) == FAIL
)
14066 first_error (_("immediate out of range"));
14071 inst
.instruction
&= ~(1 << 5);
14072 inst
.instruction
|= op
<< 5;
14074 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14075 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14076 inst
.instruction
|= neon_quad (rs
) << 6;
14077 inst
.instruction
|= cmode
<< 8;
14079 neon_write_immbits (immbits
);
14085 if (inst
.operands
[1].isreg
)
14087 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14089 NEON_ENCODE (INTEGER
, inst
);
14090 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14091 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14092 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14093 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14094 inst
.instruction
|= neon_quad (rs
) << 6;
14098 NEON_ENCODE (IMMED
, inst
);
14099 neon_move_immediate ();
14102 neon_dp_fixup (&inst
);
14105 /* Encode instructions of form:
14107 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14108 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14111 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14113 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14114 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14115 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14116 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14117 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14118 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14119 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14120 inst
.instruction
|= neon_logbits (size
) << 20;
14122 neon_dp_fixup (&inst
);
14126 do_neon_dyadic_long (void)
14128 /* FIXME: Type checking for lengthening op. */
14129 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14130 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14131 neon_mixed_length (et
, et
.size
);
14135 do_neon_abal (void)
14137 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14138 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14139 neon_mixed_length (et
, et
.size
);
14143 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14145 if (inst
.operands
[2].isscalar
)
14147 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14148 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14149 NEON_ENCODE (SCALAR
, inst
);
14150 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14154 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14155 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14156 NEON_ENCODE (INTEGER
, inst
);
14157 neon_mixed_length (et
, et
.size
);
14162 do_neon_mac_maybe_scalar_long (void)
14164 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14168 do_neon_dyadic_wide (void)
14170 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14171 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14172 neon_mixed_length (et
, et
.size
);
14176 do_neon_dyadic_narrow (void)
14178 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14179 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14180 /* Operand sign is unimportant, and the U bit is part of the opcode,
14181 so force the operand type to integer. */
14182 et
.type
= NT_integer
;
14183 neon_mixed_length (et
, et
.size
/ 2);
14187 do_neon_mul_sat_scalar_long (void)
14189 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14193 do_neon_vmull (void)
14195 if (inst
.operands
[2].isscalar
)
14196 do_neon_mac_maybe_scalar_long ();
14199 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14200 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14201 if (et
.type
== NT_poly
)
14202 NEON_ENCODE (POLY
, inst
);
14204 NEON_ENCODE (INTEGER
, inst
);
14205 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14206 zero. Should be OK as-is. */
14207 neon_mixed_length (et
, et
.size
);
14214 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14215 struct neon_type_el et
= neon_check_type (3, rs
,
14216 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14217 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14219 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14220 _("shift out of range"));
14221 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14222 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14223 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14224 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14225 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14226 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14227 inst
.instruction
|= neon_quad (rs
) << 6;
14228 inst
.instruction
|= imm
<< 8;
14230 neon_dp_fixup (&inst
);
14236 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14237 struct neon_type_el et
= neon_check_type (2, rs
,
14238 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14239 unsigned op
= (inst
.instruction
>> 7) & 3;
14240 /* N (width of reversed regions) is encoded as part of the bitmask. We
14241 extract it here to check the elements to be reversed are smaller.
14242 Otherwise we'd get a reserved instruction. */
14243 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14244 gas_assert (elsize
!= 0);
14245 constraint (et
.size
>= elsize
,
14246 _("elements must be smaller than reversal region"));
14247 neon_two_same (neon_quad (rs
), 1, et
.size
);
14253 if (inst
.operands
[1].isscalar
)
14255 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14256 struct neon_type_el et
= neon_check_type (2, rs
,
14257 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14258 unsigned sizebits
= et
.size
>> 3;
14259 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14260 int logsize
= neon_logbits (et
.size
);
14261 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14263 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14266 NEON_ENCODE (SCALAR
, inst
);
14267 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14268 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14269 inst
.instruction
|= LOW4 (dm
);
14270 inst
.instruction
|= HI1 (dm
) << 5;
14271 inst
.instruction
|= neon_quad (rs
) << 6;
14272 inst
.instruction
|= x
<< 17;
14273 inst
.instruction
|= sizebits
<< 16;
14275 neon_dp_fixup (&inst
);
14279 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14280 struct neon_type_el et
= neon_check_type (2, rs
,
14281 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14282 /* Duplicate ARM register to lanes of vector. */
14283 NEON_ENCODE (ARMREG
, inst
);
14286 case 8: inst
.instruction
|= 0x400000; break;
14287 case 16: inst
.instruction
|= 0x000020; break;
14288 case 32: inst
.instruction
|= 0x000000; break;
14291 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14292 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14293 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14294 inst
.instruction
|= neon_quad (rs
) << 21;
14295 /* The encoding for this instruction is identical for the ARM and Thumb
14296 variants, except for the condition field. */
14297 do_vfp_cond_or_thumb ();
14301 /* VMOV has particularly many variations. It can be one of:
14302 0. VMOV<c><q> <Qd>, <Qm>
14303 1. VMOV<c><q> <Dd>, <Dm>
14304 (Register operations, which are VORR with Rm = Rn.)
14305 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14306 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14308 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14309 (ARM register to scalar.)
14310 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14311 (Two ARM registers to vector.)
14312 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14313 (Scalar to ARM register.)
14314 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14315 (Vector to two ARM registers.)
14316 8. VMOV.F32 <Sd>, <Sm>
14317 9. VMOV.F64 <Dd>, <Dm>
14318 (VFP register moves.)
14319 10. VMOV.F32 <Sd>, #imm
14320 11. VMOV.F64 <Dd>, #imm
14321 (VFP float immediate load.)
14322 12. VMOV <Rd>, <Sm>
14323 (VFP single to ARM reg.)
14324 13. VMOV <Sd>, <Rm>
14325 (ARM reg to VFP single.)
14326 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14327 (Two ARM regs to two VFP singles.)
14328 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14329 (Two VFP singles to two ARM regs.)
14331 These cases can be disambiguated using neon_select_shape, except cases 1/9
14332 and 3/11 which depend on the operand type too.
14334 All the encoded bits are hardcoded by this function.
14336 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14337 Cases 5, 7 may be used with VFPv2 and above.
14339 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14340 can specify a type where it doesn't make sense to, and is ignored). */
14345 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14346 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14348 struct neon_type_el et
;
14349 const char *ldconst
= 0;
14353 case NS_DD
: /* case 1/9. */
14354 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14355 /* It is not an error here if no type is given. */
14357 if (et
.type
== NT_float
&& et
.size
== 64)
14359 do_vfp_nsyn_opcode ("fcpyd");
14362 /* fall through. */
14364 case NS_QQ
: /* case 0/1. */
14366 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14368 /* The architecture manual I have doesn't explicitly state which
14369 value the U bit should have for register->register moves, but
14370 the equivalent VORR instruction has U = 0, so do that. */
14371 inst
.instruction
= 0x0200110;
14372 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14373 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14374 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14375 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14376 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14377 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14378 inst
.instruction
|= neon_quad (rs
) << 6;
14380 neon_dp_fixup (&inst
);
14384 case NS_DI
: /* case 3/11. */
14385 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14387 if (et
.type
== NT_float
&& et
.size
== 64)
14389 /* case 11 (fconstd). */
14390 ldconst
= "fconstd";
14391 goto encode_fconstd
;
14393 /* fall through. */
14395 case NS_QI
: /* case 2/3. */
14396 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14398 inst
.instruction
= 0x0800010;
14399 neon_move_immediate ();
14400 neon_dp_fixup (&inst
);
14403 case NS_SR
: /* case 4. */
14405 unsigned bcdebits
= 0;
14407 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14408 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14410 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14411 logsize
= neon_logbits (et
.size
);
14413 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14415 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14416 && et
.size
!= 32, _(BAD_FPU
));
14417 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14418 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14422 case 8: bcdebits
= 0x8; break;
14423 case 16: bcdebits
= 0x1; break;
14424 case 32: bcdebits
= 0x0; break;
14428 bcdebits
|= x
<< logsize
;
14430 inst
.instruction
= 0xe000b10;
14431 do_vfp_cond_or_thumb ();
14432 inst
.instruction
|= LOW4 (dn
) << 16;
14433 inst
.instruction
|= HI1 (dn
) << 7;
14434 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14435 inst
.instruction
|= (bcdebits
& 3) << 5;
14436 inst
.instruction
|= (bcdebits
>> 2) << 21;
14440 case NS_DRR
: /* case 5 (fmdrr). */
14441 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14444 inst
.instruction
= 0xc400b10;
14445 do_vfp_cond_or_thumb ();
14446 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14447 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14448 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14449 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14452 case NS_RS
: /* case 6. */
14455 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14456 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14457 unsigned abcdebits
= 0;
14459 et
= neon_check_type (2, NS_NULL
,
14460 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14461 logsize
= neon_logbits (et
.size
);
14463 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14465 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14466 && et
.size
!= 32, _(BAD_FPU
));
14467 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14468 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14472 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14473 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14474 case 32: abcdebits
= 0x00; break;
14478 abcdebits
|= x
<< logsize
;
14479 inst
.instruction
= 0xe100b10;
14480 do_vfp_cond_or_thumb ();
14481 inst
.instruction
|= LOW4 (dn
) << 16;
14482 inst
.instruction
|= HI1 (dn
) << 7;
14483 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14484 inst
.instruction
|= (abcdebits
& 3) << 5;
14485 inst
.instruction
|= (abcdebits
>> 2) << 21;
14489 case NS_RRD
: /* case 7 (fmrrd). */
14490 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14493 inst
.instruction
= 0xc500b10;
14494 do_vfp_cond_or_thumb ();
14495 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14496 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14497 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14498 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14501 case NS_FF
: /* case 8 (fcpys). */
14502 do_vfp_nsyn_opcode ("fcpys");
14505 case NS_FI
: /* case 10 (fconsts). */
14506 ldconst
= "fconsts";
14508 if (is_quarter_float (inst
.operands
[1].imm
))
14510 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14511 do_vfp_nsyn_opcode (ldconst
);
14514 first_error (_("immediate out of range"));
14517 case NS_RF
: /* case 12 (fmrs). */
14518 do_vfp_nsyn_opcode ("fmrs");
14521 case NS_FR
: /* case 13 (fmsr). */
14522 do_vfp_nsyn_opcode ("fmsr");
14525 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14526 (one of which is a list), but we have parsed four. Do some fiddling to
14527 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14529 case NS_RRFF
: /* case 14 (fmrrs). */
14530 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14531 _("VFP registers must be adjacent"));
14532 inst
.operands
[2].imm
= 2;
14533 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14534 do_vfp_nsyn_opcode ("fmrrs");
14537 case NS_FFRR
: /* case 15 (fmsrr). */
14538 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14539 _("VFP registers must be adjacent"));
14540 inst
.operands
[1] = inst
.operands
[2];
14541 inst
.operands
[2] = inst
.operands
[3];
14542 inst
.operands
[0].imm
= 2;
14543 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14544 do_vfp_nsyn_opcode ("fmsrr");
14553 do_neon_rshift_round_imm (void)
14555 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14556 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14557 int imm
= inst
.operands
[2].imm
;
14559 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
14562 inst
.operands
[2].present
= 0;
14567 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14568 _("immediate out of range for shift"));
14569 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
14574 do_neon_movl (void)
14576 struct neon_type_el et
= neon_check_type (2, NS_QD
,
14577 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14578 unsigned sizebits
= et
.size
>> 3;
14579 inst
.instruction
|= sizebits
<< 19;
14580 neon_two_same (0, et
.type
== NT_unsigned
, -1);
14586 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14587 struct neon_type_el et
= neon_check_type (2, rs
,
14588 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14589 NEON_ENCODE (INTEGER
, inst
);
14590 neon_two_same (neon_quad (rs
), 1, et
.size
);
14594 do_neon_zip_uzp (void)
14596 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14597 struct neon_type_el et
= neon_check_type (2, rs
,
14598 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14599 if (rs
== NS_DD
&& et
.size
== 32)
14601 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
14602 inst
.instruction
= N_MNEM_vtrn
;
14606 neon_two_same (neon_quad (rs
), 1, et
.size
);
14610 do_neon_sat_abs_neg (void)
14612 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14613 struct neon_type_el et
= neon_check_type (2, rs
,
14614 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14615 neon_two_same (neon_quad (rs
), 1, et
.size
);
14619 do_neon_pair_long (void)
14621 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14622 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
14623 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
14624 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
14625 neon_two_same (neon_quad (rs
), 1, et
.size
);
14629 do_neon_recip_est (void)
14631 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14632 struct neon_type_el et
= neon_check_type (2, rs
,
14633 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
14634 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14635 neon_two_same (neon_quad (rs
), 1, et
.size
);
14641 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14642 struct neon_type_el et
= neon_check_type (2, rs
,
14643 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
14644 neon_two_same (neon_quad (rs
), 1, et
.size
);
14650 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14651 struct neon_type_el et
= neon_check_type (2, rs
,
14652 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
14653 neon_two_same (neon_quad (rs
), 1, et
.size
);
14659 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14660 struct neon_type_el et
= neon_check_type (2, rs
,
14661 N_EQK
| N_INT
, N_8
| N_KEY
);
14662 neon_two_same (neon_quad (rs
), 1, et
.size
);
14668 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14669 neon_two_same (neon_quad (rs
), 1, -1);
14673 do_neon_tbl_tbx (void)
14675 unsigned listlenbits
;
14676 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
14678 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
14680 first_error (_("bad list length for table lookup"));
14684 listlenbits
= inst
.operands
[1].imm
- 1;
14685 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14686 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14687 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14688 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14689 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14690 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14691 inst
.instruction
|= listlenbits
<< 8;
14693 neon_dp_fixup (&inst
);
14697 do_neon_ldm_stm (void)
14699 /* P, U and L bits are part of bitmask. */
14700 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
14701 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
14703 if (inst
.operands
[1].issingle
)
14705 do_vfp_nsyn_ldm_stm (is_dbmode
);
14709 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
14710 _("writeback (!) must be used for VLDMDB and VSTMDB"));
14712 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14713 _("register list must contain at least 1 and at most 16 "
14716 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14717 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
14718 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14719 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
14721 inst
.instruction
|= offsetbits
;
14723 do_vfp_cond_or_thumb ();
14727 do_neon_ldr_str (void)
14729 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
14731 if (inst
.operands
[0].issingle
)
14734 do_vfp_nsyn_opcode ("flds");
14736 do_vfp_nsyn_opcode ("fsts");
14741 do_vfp_nsyn_opcode ("fldd");
14743 do_vfp_nsyn_opcode ("fstd");
14747 /* "interleave" version also handles non-interleaving register VLD1/VST1
14751 do_neon_ld_st_interleave (void)
14753 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14754 N_8
| N_16
| N_32
| N_64
);
14755 unsigned alignbits
= 0;
14757 /* The bits in this table go:
14758 0: register stride of one (0) or two (1)
14759 1,2: register list length, minus one (1, 2, 3, 4).
14760 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14761 We use -1 for invalid entries. */
14762 const int typetable
[] =
14764 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14765 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14766 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14767 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14771 if (et
.type
== NT_invtype
)
14774 if (inst
.operands
[1].immisalign
)
14775 switch (inst
.operands
[1].imm
>> 8)
14777 case 64: alignbits
= 1; break;
14779 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
14780 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14781 goto bad_alignment
;
14785 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
14786 goto bad_alignment
;
14791 first_error (_("bad alignment"));
14795 inst
.instruction
|= alignbits
<< 4;
14796 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14798 /* Bits [4:6] of the immediate in a list specifier encode register stride
14799 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14800 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14801 up the right value for "type" in a table based on this value and the given
14802 list style, then stick it back. */
14803 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14804 | (((inst
.instruction
>> 8) & 3) << 3);
14806 typebits
= typetable
[idx
];
14808 constraint (typebits
== -1, _("bad list type for instruction"));
14810 inst
.instruction
&= ~0xf00;
14811 inst
.instruction
|= typebits
<< 8;
14814 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14815 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14816 otherwise. The variable arguments are a list of pairs of legal (size, align)
14817 values, terminated with -1. */
14820 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14823 int result
= FAIL
, thissize
, thisalign
;
14825 if (!inst
.operands
[1].immisalign
)
14831 va_start (ap
, do_align
);
14835 thissize
= va_arg (ap
, int);
14836 if (thissize
== -1)
14838 thisalign
= va_arg (ap
, int);
14840 if (size
== thissize
&& align
== thisalign
)
14843 while (result
!= SUCCESS
);
14847 if (result
== SUCCESS
)
14850 first_error (_("unsupported alignment for instruction"));
14856 do_neon_ld_st_lane (void)
14858 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14859 int align_good
, do_align
= 0;
14860 int logsize
= neon_logbits (et
.size
);
14861 int align
= inst
.operands
[1].imm
>> 8;
14862 int n
= (inst
.instruction
>> 8) & 3;
14863 int max_el
= 64 / et
.size
;
14865 if (et
.type
== NT_invtype
)
14868 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14869 _("bad list length"));
14870 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14871 _("scalar index out of range"));
14872 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14874 _("stride of 2 unavailable when element size is 8"));
14878 case 0: /* VLD1 / VST1. */
14879 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14881 if (align_good
== FAIL
)
14885 unsigned alignbits
= 0;
14888 case 16: alignbits
= 0x1; break;
14889 case 32: alignbits
= 0x3; break;
14892 inst
.instruction
|= alignbits
<< 4;
14896 case 1: /* VLD2 / VST2. */
14897 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14899 if (align_good
== FAIL
)
14902 inst
.instruction
|= 1 << 4;
14905 case 2: /* VLD3 / VST3. */
14906 constraint (inst
.operands
[1].immisalign
,
14907 _("can't use alignment with this instruction"));
14910 case 3: /* VLD4 / VST4. */
14911 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14912 16, 64, 32, 64, 32, 128, -1);
14913 if (align_good
== FAIL
)
14917 unsigned alignbits
= 0;
14920 case 8: alignbits
= 0x1; break;
14921 case 16: alignbits
= 0x1; break;
14922 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14925 inst
.instruction
|= alignbits
<< 4;
14932 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14933 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14934 inst
.instruction
|= 1 << (4 + logsize
);
14936 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14937 inst
.instruction
|= logsize
<< 10;
14940 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14943 do_neon_ld_dup (void)
14945 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14946 int align_good
, do_align
= 0;
14948 if (et
.type
== NT_invtype
)
14951 switch ((inst
.instruction
>> 8) & 3)
14953 case 0: /* VLD1. */
14954 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14955 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14956 &do_align
, 16, 16, 32, 32, -1);
14957 if (align_good
== FAIL
)
14959 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14962 case 2: inst
.instruction
|= 1 << 5; break;
14963 default: first_error (_("bad list length")); return;
14965 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14968 case 1: /* VLD2. */
14969 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14970 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14971 if (align_good
== FAIL
)
14973 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14974 _("bad list length"));
14975 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14976 inst
.instruction
|= 1 << 5;
14977 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14980 case 2: /* VLD3. */
14981 constraint (inst
.operands
[1].immisalign
,
14982 _("can't use alignment with this instruction"));
14983 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14984 _("bad list length"));
14985 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14986 inst
.instruction
|= 1 << 5;
14987 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14990 case 3: /* VLD4. */
14992 int align
= inst
.operands
[1].imm
>> 8;
14993 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14994 16, 64, 32, 64, 32, 128, -1);
14995 if (align_good
== FAIL
)
14997 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14998 _("bad list length"));
14999 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15000 inst
.instruction
|= 1 << 5;
15001 if (et
.size
== 32 && align
== 128)
15002 inst
.instruction
|= 0x3 << 6;
15004 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15011 inst
.instruction
|= do_align
<< 4;
15014 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15015 apart from bits [11:4]. */
15018 do_neon_ldx_stx (void)
15020 if (inst
.operands
[1].isreg
)
15021 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15023 switch (NEON_LANE (inst
.operands
[0].imm
))
15025 case NEON_INTERLEAVE_LANES
:
15026 NEON_ENCODE (INTERLV
, inst
);
15027 do_neon_ld_st_interleave ();
15030 case NEON_ALL_LANES
:
15031 NEON_ENCODE (DUP
, inst
);
15036 NEON_ENCODE (LANE
, inst
);
15037 do_neon_ld_st_lane ();
15040 /* L bit comes from bit mask. */
15041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15042 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15043 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15045 if (inst
.operands
[1].postind
)
15047 int postreg
= inst
.operands
[1].imm
& 0xf;
15048 constraint (!inst
.operands
[1].immisreg
,
15049 _("post-index must be a register"));
15050 constraint (postreg
== 0xd || postreg
== 0xf,
15051 _("bad register for post-index"));
15052 inst
.instruction
|= postreg
;
15054 else if (inst
.operands
[1].writeback
)
15056 inst
.instruction
|= 0xd;
15059 inst
.instruction
|= 0xf;
15062 inst
.instruction
|= 0xf9000000;
15064 inst
.instruction
|= 0xf4000000;
15067 /* Overall per-instruction processing. */
15069 /* We need to be able to fix up arbitrary expressions in some statements.
15070 This is so that we can handle symbols that are an arbitrary distance from
15071 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15072 which returns part of an address in a form which will be valid for
15073 a data instruction. We do this by pushing the expression into a symbol
15074 in the expr_section, and creating a fix for that. */
15077 fix_new_arm (fragS
* frag
,
15092 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15093 (enum bfd_reloc_code_real
) reloc
);
15097 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15098 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15102 /* Mark whether the fix is to a THUMB instruction, or an ARM
15104 new_fix
->tc_fix_data
= thumb_mode
;
15107 /* Create a frg for an instruction requiring relaxation. */
15109 output_relax_insn (void)
15115 /* The size of the instruction is unknown, so tie the debug info to the
15116 start of the instruction. */
15117 dwarf2_emit_insn (0);
15119 switch (inst
.reloc
.exp
.X_op
)
15122 sym
= inst
.reloc
.exp
.X_add_symbol
;
15123 offset
= inst
.reloc
.exp
.X_add_number
;
15127 offset
= inst
.reloc
.exp
.X_add_number
;
15130 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15134 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15135 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15136 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15139 /* Write a 32-bit thumb instruction to buf. */
15141 put_thumb32_insn (char * buf
, unsigned long insn
)
15143 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15144 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15148 output_inst (const char * str
)
15154 as_bad ("%s -- `%s'", inst
.error
, str
);
15159 output_relax_insn ();
15162 if (inst
.size
== 0)
15165 to
= frag_more (inst
.size
);
15166 /* PR 9814: Record the thumb mode into the current frag so that we know
15167 what type of NOP padding to use, if necessary. We override any previous
15168 setting so that if the mode has changed then the NOPS that we use will
15169 match the encoding of the last instruction in the frag. */
15170 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15172 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15174 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15175 put_thumb32_insn (to
, inst
.instruction
);
15177 else if (inst
.size
> INSN_SIZE
)
15179 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15180 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15181 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15184 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15186 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15187 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15188 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15191 dwarf2_emit_insn (inst
.size
);
15195 output_it_inst (int cond
, int mask
, char * to
)
15197 unsigned long instruction
= 0xbf00;
15200 instruction
|= mask
;
15201 instruction
|= cond
<< 4;
15205 to
= frag_more (2);
15207 dwarf2_emit_insn (2);
15211 md_number_to_chars (to
, instruction
, 2);
15216 /* Tag values used in struct asm_opcode's tag field. */
15219 OT_unconditional
, /* Instruction cannot be conditionalized.
15220 The ARM condition field is still 0xE. */
15221 OT_unconditionalF
, /* Instruction cannot be conditionalized
15222 and carries 0xF in its ARM condition field. */
15223 OT_csuffix
, /* Instruction takes a conditional suffix. */
15224 OT_csuffixF
, /* Some forms of the instruction take a conditional
15225 suffix, others place 0xF where the condition field
15227 OT_cinfix3
, /* Instruction takes a conditional infix,
15228 beginning at character index 3. (In
15229 unified mode, it becomes a suffix.) */
15230 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15231 tsts, cmps, cmns, and teqs. */
15232 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15233 character index 3, even in unified mode. Used for
15234 legacy instructions where suffix and infix forms
15235 may be ambiguous. */
15236 OT_csuf_or_in3
, /* Instruction takes either a conditional
15237 suffix or an infix at character index 3. */
15238 OT_odd_infix_unc
, /* This is the unconditional variant of an
15239 instruction that takes a conditional infix
15240 at an unusual position. In unified mode,
15241 this variant will accept a suffix. */
15242 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15243 are the conditional variants of instructions that
15244 take conditional infixes in unusual positions.
15245 The infix appears at character index
15246 (tag - OT_odd_infix_0). These are not accepted
15247 in unified mode. */
15250 /* Subroutine of md_assemble, responsible for looking up the primary
15251 opcode from the mnemonic the user wrote. STR points to the
15252 beginning of the mnemonic.
15254 This is not simply a hash table lookup, because of conditional
15255 variants. Most instructions have conditional variants, which are
15256 expressed with a _conditional affix_ to the mnemonic. If we were
15257 to encode each conditional variant as a literal string in the opcode
15258 table, it would have approximately 20,000 entries.
15260 Most mnemonics take this affix as a suffix, and in unified syntax,
15261 'most' is upgraded to 'all'. However, in the divided syntax, some
15262 instructions take the affix as an infix, notably the s-variants of
15263 the arithmetic instructions. Of those instructions, all but six
15264 have the infix appear after the third character of the mnemonic.
15266 Accordingly, the algorithm for looking up primary opcodes given
15269 1. Look up the identifier in the opcode table.
15270 If we find a match, go to step U.
15272 2. Look up the last two characters of the identifier in the
15273 conditions table. If we find a match, look up the first N-2
15274 characters of the identifier in the opcode table. If we
15275 find a match, go to step CE.
15277 3. Look up the fourth and fifth characters of the identifier in
15278 the conditions table. If we find a match, extract those
15279 characters from the identifier, and look up the remaining
15280 characters in the opcode table. If we find a match, go
15285 U. Examine the tag field of the opcode structure, in case this is
15286 one of the six instructions with its conditional infix in an
15287 unusual place. If it is, the tag tells us where to find the
15288 infix; look it up in the conditions table and set inst.cond
15289 accordingly. Otherwise, this is an unconditional instruction.
15290 Again set inst.cond accordingly. Return the opcode structure.
15292 CE. Examine the tag field to make sure this is an instruction that
15293 should receive a conditional suffix. If it is not, fail.
15294 Otherwise, set inst.cond from the suffix we already looked up,
15295 and return the opcode structure.
15297 CM. Examine the tag field to make sure this is an instruction that
15298 should receive a conditional infix after the third character.
15299 If it is not, fail. Otherwise, undo the edits to the current
15300 line of input and proceed as for case CE. */
15302 static const struct asm_opcode
*
15303 opcode_lookup (char **str
)
15307 const struct asm_opcode
*opcode
;
15308 const struct asm_cond
*cond
;
15311 /* Scan up to the end of the mnemonic, which must end in white space,
15312 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15313 for (base
= end
= *str
; *end
!= '\0'; end
++)
15314 if (*end
== ' ' || *end
== '.')
15320 /* Handle a possible width suffix and/or Neon type suffix. */
15325 /* The .w and .n suffixes are only valid if the unified syntax is in
15327 if (unified_syntax
&& end
[1] == 'w')
15329 else if (unified_syntax
&& end
[1] == 'n')
15334 inst
.vectype
.elems
= 0;
15336 *str
= end
+ offset
;
15338 if (end
[offset
] == '.')
15340 /* See if we have a Neon type suffix (possible in either unified or
15341 non-unified ARM syntax mode). */
15342 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15345 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15351 /* Look for unaffixed or special-case affixed mnemonic. */
15352 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15357 if (opcode
->tag
< OT_odd_infix_0
)
15359 inst
.cond
= COND_ALWAYS
;
15363 if (warn_on_deprecated
&& unified_syntax
)
15364 as_warn (_("conditional infixes are deprecated in unified syntax"));
15365 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15366 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15369 inst
.cond
= cond
->value
;
15373 /* Cannot have a conditional suffix on a mnemonic of less than two
15375 if (end
- base
< 3)
15378 /* Look for suffixed mnemonic. */
15380 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15381 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15383 if (opcode
&& cond
)
15386 switch (opcode
->tag
)
15388 case OT_cinfix3_legacy
:
15389 /* Ignore conditional suffixes matched on infix only mnemonics. */
15393 case OT_cinfix3_deprecated
:
15394 case OT_odd_infix_unc
:
15395 if (!unified_syntax
)
15397 /* else fall through */
15401 case OT_csuf_or_in3
:
15402 inst
.cond
= cond
->value
;
15405 case OT_unconditional
:
15406 case OT_unconditionalF
:
15408 inst
.cond
= cond
->value
;
15411 /* Delayed diagnostic. */
15412 inst
.error
= BAD_COND
;
15413 inst
.cond
= COND_ALWAYS
;
15422 /* Cannot have a usual-position infix on a mnemonic of less than
15423 six characters (five would be a suffix). */
15424 if (end
- base
< 6)
15427 /* Look for infixed mnemonic in the usual position. */
15429 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15433 memcpy (save
, affix
, 2);
15434 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15435 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15437 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15438 memcpy (affix
, save
, 2);
15441 && (opcode
->tag
== OT_cinfix3
15442 || opcode
->tag
== OT_cinfix3_deprecated
15443 || opcode
->tag
== OT_csuf_or_in3
15444 || opcode
->tag
== OT_cinfix3_legacy
))
15447 if (warn_on_deprecated
&& unified_syntax
15448 && (opcode
->tag
== OT_cinfix3
15449 || opcode
->tag
== OT_cinfix3_deprecated
))
15450 as_warn (_("conditional infixes are deprecated in unified syntax"));
15452 inst
.cond
= cond
->value
;
15459 /* This function generates an initial IT instruction, leaving its block
15460 virtually open for the new instructions. Eventually,
15461 the mask will be updated by now_it_add_mask () each time
15462 a new instruction needs to be included in the IT block.
15463 Finally, the block is closed with close_automatic_it_block ().
15464 The block closure can be requested either from md_assemble (),
15465 a tencode (), or due to a label hook. */
15468 new_automatic_it_block (int cond
)
15470 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15471 now_it
.mask
= 0x18;
15473 now_it
.block_length
= 1;
15474 mapping_state (MAP_THUMB
);
15475 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15478 /* Close an automatic IT block.
15479 See comments in new_automatic_it_block (). */
15482 close_automatic_it_block (void)
15484 now_it
.mask
= 0x10;
15485 now_it
.block_length
= 0;
15488 /* Update the mask of the current automatically-generated IT
15489 instruction. See comments in new_automatic_it_block (). */
15492 now_it_add_mask (int cond
)
15494 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15495 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15496 | ((bitvalue) << (nbit)))
15497 const int resulting_bit
= (cond
& 1);
15499 now_it
.mask
&= 0xf;
15500 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15502 (5 - now_it
.block_length
));
15503 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15505 ((5 - now_it
.block_length
) - 1) );
15506 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15509 #undef SET_BIT_VALUE
15512 /* The IT blocks handling machinery is accessed through the these functions:
15513 it_fsm_pre_encode () from md_assemble ()
15514 set_it_insn_type () optional, from the tencode functions
15515 set_it_insn_type_last () ditto
15516 in_it_block () ditto
15517 it_fsm_post_encode () from md_assemble ()
15518 force_automatic_it_block_close () from label habdling functions
15521 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15522 initializing the IT insn type with a generic initial value depending
15523 on the inst.condition.
15524 2) During the tencode function, two things may happen:
15525 a) The tencode function overrides the IT insn type by
15526 calling either set_it_insn_type (type) or set_it_insn_type_last ().
15527 b) The tencode function queries the IT block state by
15528 calling in_it_block () (i.e. to determine narrow/not narrow mode).
15530 Both set_it_insn_type and in_it_block run the internal FSM state
15531 handling function (handle_it_state), because: a) setting the IT insn
15532 type may incur in an invalid state (exiting the function),
15533 and b) querying the state requires the FSM to be updated.
15534 Specifically we want to avoid creating an IT block for conditional
15535 branches, so it_fsm_pre_encode is actually a guess and we can't
15536 determine whether an IT block is required until the tencode () routine
15537 has decided what type of instruction this actually it.
15538 Because of this, if set_it_insn_type and in_it_block have to be used,
15539 set_it_insn_type has to be called first.
15541 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
15542 determines the insn IT type depending on the inst.cond code.
15543 When a tencode () routine encodes an instruction that can be
15544 either outside an IT block, or, in the case of being inside, has to be
15545 the last one, set_it_insn_type_last () will determine the proper
15546 IT instruction type based on the inst.cond code. Otherwise,
15547 set_it_insn_type can be called for overriding that logic or
15548 for covering other cases.
15550 Calling handle_it_state () may not transition the IT block state to
15551 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
15552 still queried. Instead, if the FSM determines that the state should
15553 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
15554 after the tencode () function: that's what it_fsm_post_encode () does.
15556 Since in_it_block () calls the state handling function to get an
15557 updated state, an error may occur (due to invalid insns combination).
15558 In that case, inst.error is set.
15559 Therefore, inst.error has to be checked after the execution of
15560 the tencode () routine.
15562 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
15563 any pending state change (if any) that didn't take place in
15564 handle_it_state () as explained above. */
15567 it_fsm_pre_encode (void)
15569 if (inst
.cond
!= COND_ALWAYS
)
15570 inst
.it_insn_type
= INSIDE_IT_INSN
;
15572 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
15574 now_it
.state_handled
= 0;
15577 /* IT state FSM handling function. */
15580 handle_it_state (void)
15582 now_it
.state_handled
= 1;
15584 switch (now_it
.state
)
15586 case OUTSIDE_IT_BLOCK
:
15587 switch (inst
.it_insn_type
)
15589 case OUTSIDE_IT_INSN
:
15592 case INSIDE_IT_INSN
:
15593 case INSIDE_IT_LAST_INSN
:
15594 if (thumb_mode
== 0)
15597 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
15598 as_tsktsk (_("Warning: conditional outside an IT block"\
15603 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
15604 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
15606 /* Automatically generate the IT instruction. */
15607 new_automatic_it_block (inst
.cond
);
15608 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
15609 close_automatic_it_block ();
15613 inst
.error
= BAD_OUT_IT
;
15619 case IF_INSIDE_IT_LAST_INSN
:
15620 case NEUTRAL_IT_INSN
:
15624 now_it
.state
= MANUAL_IT_BLOCK
;
15625 now_it
.block_length
= 0;
15630 case AUTOMATIC_IT_BLOCK
:
15631 /* Three things may happen now:
15632 a) We should increment current it block size;
15633 b) We should close current it block (closing insn or 4 insns);
15634 c) We should close current it block and start a new one (due
15635 to incompatible conditions or
15636 4 insns-length block reached). */
15638 switch (inst
.it_insn_type
)
15640 case OUTSIDE_IT_INSN
:
15641 /* The closure of the block shall happen immediatelly,
15642 so any in_it_block () call reports the block as closed. */
15643 force_automatic_it_block_close ();
15646 case INSIDE_IT_INSN
:
15647 case INSIDE_IT_LAST_INSN
:
15648 case IF_INSIDE_IT_LAST_INSN
:
15649 now_it
.block_length
++;
15651 if (now_it
.block_length
> 4
15652 || !now_it_compatible (inst
.cond
))
15654 force_automatic_it_block_close ();
15655 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
15656 new_automatic_it_block (inst
.cond
);
15660 now_it_add_mask (inst
.cond
);
15663 if (now_it
.state
== AUTOMATIC_IT_BLOCK
15664 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
15665 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
15666 close_automatic_it_block ();
15669 case NEUTRAL_IT_INSN
:
15670 now_it
.block_length
++;
15672 if (now_it
.block_length
> 4)
15673 force_automatic_it_block_close ();
15675 now_it_add_mask (now_it
.cc
& 1);
15679 close_automatic_it_block ();
15680 now_it
.state
= MANUAL_IT_BLOCK
;
15685 case MANUAL_IT_BLOCK
:
15687 /* Check conditional suffixes. */
15688 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
15691 now_it
.mask
&= 0x1f;
15692 is_last
= (now_it
.mask
== 0x10);
15694 switch (inst
.it_insn_type
)
15696 case OUTSIDE_IT_INSN
:
15697 inst
.error
= BAD_NOT_IT
;
15700 case INSIDE_IT_INSN
:
15701 if (cond
!= inst
.cond
)
15703 inst
.error
= BAD_IT_COND
;
15708 case INSIDE_IT_LAST_INSN
:
15709 case IF_INSIDE_IT_LAST_INSN
:
15710 if (cond
!= inst
.cond
)
15712 inst
.error
= BAD_IT_COND
;
15717 inst
.error
= BAD_BRANCH
;
15722 case NEUTRAL_IT_INSN
:
15723 /* The BKPT instruction is unconditional even in an IT block. */
15727 inst
.error
= BAD_IT_IT
;
15738 it_fsm_post_encode (void)
15742 if (!now_it
.state_handled
)
15743 handle_it_state ();
15745 is_last
= (now_it
.mask
== 0x10);
15748 now_it
.state
= OUTSIDE_IT_BLOCK
;
15754 force_automatic_it_block_close (void)
15756 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
15758 close_automatic_it_block ();
15759 now_it
.state
= OUTSIDE_IT_BLOCK
;
15767 if (!now_it
.state_handled
)
15768 handle_it_state ();
15770 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
15774 md_assemble (char *str
)
15777 const struct asm_opcode
* opcode
;
15779 /* Align the previous label if needed. */
15780 if (last_label_seen
!= NULL
)
15782 symbol_set_frag (last_label_seen
, frag_now
);
15783 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
15784 S_SET_SEGMENT (last_label_seen
, now_seg
);
15787 memset (&inst
, '\0', sizeof (inst
));
15788 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
15790 opcode
= opcode_lookup (&p
);
15793 /* It wasn't an instruction, but it might be a register alias of
15794 the form alias .req reg, or a Neon .dn/.qn directive. */
15795 if (! create_register_alias (str
, p
)
15796 && ! create_neon_reg_alias (str
, p
))
15797 as_bad (_("bad instruction `%s'"), str
);
15802 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
15803 as_warn (_("s suffix on comparison instruction is deprecated"));
15805 /* The value which unconditional instructions should have in place of the
15806 condition field. */
15807 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
15811 arm_feature_set variant
;
15813 variant
= cpu_variant
;
15814 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
15815 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
15816 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
15817 /* Check that this instruction is supported for this CPU. */
15818 if (!opcode
->tvariant
15819 || (thumb_mode
== 1
15820 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
15822 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
15825 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
15826 && opcode
->tencode
!= do_t_branch
)
15828 as_bad (_("Thumb does not support conditional execution"));
15832 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
15834 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
15835 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
15836 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
15838 /* Two things are addressed here.
15839 1) Implicit require narrow instructions on Thumb-1.
15840 This avoids relaxation accidentally introducing Thumb-2
15842 2) Reject wide instructions in non Thumb-2 cores. */
15843 if (inst
.size_req
== 0)
15845 else if (inst
.size_req
== 4)
15847 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
15853 inst
.instruction
= opcode
->tvalue
;
15855 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
15857 /* Prepare the it_insn_type for those encodings that don't set
15859 it_fsm_pre_encode ();
15861 opcode
->tencode ();
15863 it_fsm_post_encode ();
15866 if (!(inst
.error
|| inst
.relax
))
15868 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
15869 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
15870 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
15872 as_bad (_("cannot honor width suffix -- `%s'"), str
);
15877 /* Something has gone badly wrong if we try to relax a fixed size
15879 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
15881 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15882 *opcode
->tvariant
);
15883 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
15884 set those bits when Thumb-2 32-bit instructions are seen. ie.
15885 anything other than bl/blx and v6-M instructions.
15886 This is overly pessimistic for relaxable instructions. */
15887 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
15889 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
15890 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
15891 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
15894 check_neon_suffixes
;
15898 mapping_state (MAP_THUMB
);
15901 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
15905 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
15906 is_bx
= (opcode
->aencode
== do_bx
);
15908 /* Check that this instruction is supported for this CPU. */
15909 if (!(is_bx
&& fix_v4bx
)
15910 && !(opcode
->avariant
&&
15911 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
15913 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
15918 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
15922 inst
.instruction
= opcode
->avalue
;
15923 if (opcode
->tag
== OT_unconditionalF
)
15924 inst
.instruction
|= 0xF << 28;
15926 inst
.instruction
|= inst
.cond
<< 28;
15927 inst
.size
= INSN_SIZE
;
15928 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
15930 it_fsm_pre_encode ();
15931 opcode
->aencode ();
15932 it_fsm_post_encode ();
15934 /* Arm mode bx is marked as both v4T and v5 because it's still required
15935 on a hypothetical non-thumb v5 core. */
15937 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
15939 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
15940 *opcode
->avariant
);
15942 check_neon_suffixes
;
15946 mapping_state (MAP_ARM
);
15951 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
15959 check_it_blocks_finished (void)
15964 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
15965 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
15966 == MANUAL_IT_BLOCK
)
15968 as_warn (_("section '%s' finished with an open IT block."),
15972 if (now_it
.state
== MANUAL_IT_BLOCK
)
15973 as_warn (_("file finished with an open IT block."));
15977 /* Various frobbings of labels and their addresses. */
15980 arm_start_line_hook (void)
15982 last_label_seen
= NULL
;
15986 arm_frob_label (symbolS
* sym
)
15988 last_label_seen
= sym
;
15990 ARM_SET_THUMB (sym
, thumb_mode
);
15992 #if defined OBJ_COFF || defined OBJ_ELF
15993 ARM_SET_INTERWORK (sym
, support_interwork
);
15996 force_automatic_it_block_close ();
15998 /* Note - do not allow local symbols (.Lxxx) to be labelled
15999 as Thumb functions. This is because these labels, whilst
16000 they exist inside Thumb code, are not the entry points for
16001 possible ARM->Thumb calls. Also, these labels can be used
16002 as part of a computed goto or switch statement. eg gcc
16003 can generate code that looks like this:
16005 ldr r2, [pc, .Laaa]
16015 The first instruction loads the address of the jump table.
16016 The second instruction converts a table index into a byte offset.
16017 The third instruction gets the jump address out of the table.
16018 The fourth instruction performs the jump.
16020 If the address stored at .Laaa is that of a symbol which has the
16021 Thumb_Func bit set, then the linker will arrange for this address
16022 to have the bottom bit set, which in turn would mean that the
16023 address computation performed by the third instruction would end
16024 up with the bottom bit set. Since the ARM is capable of unaligned
16025 word loads, the instruction would then load the incorrect address
16026 out of the jump table, and chaos would ensue. */
16027 if (label_is_thumb_function_name
16028 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16029 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16031 /* When the address of a Thumb function is taken the bottom
16032 bit of that address should be set. This will allow
16033 interworking between Arm and Thumb functions to work
16036 THUMB_SET_FUNC (sym
, 1);
16038 label_is_thumb_function_name
= FALSE
;
16041 dwarf2_emit_label (sym
);
16045 arm_data_in_code (void)
16047 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16049 *input_line_pointer
= '/';
16050 input_line_pointer
+= 5;
16051 *input_line_pointer
= 0;
16059 arm_canonicalize_symbol_name (char * name
)
16063 if (thumb_mode
&& (len
= strlen (name
)) > 5
16064 && streq (name
+ len
- 5, "/data"))
16065 *(name
+ len
- 5) = 0;
16070 /* Table of all register names defined by default. The user can
16071 define additional names with .req. Note that all register names
16072 should appear in both upper and lowercase variants. Some registers
16073 also have mixed-case names. */
16075 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16076 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16077 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16078 #define REGSET(p,t) \
16079 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16080 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16081 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16082 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16083 #define REGSETH(p,t) \
16084 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16085 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16086 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16087 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16088 #define REGSET2(p,t) \
16089 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16090 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16091 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16092 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16094 static const struct reg_entry reg_names
[] =
16096 /* ARM integer registers. */
16097 REGSET(r
, RN
), REGSET(R
, RN
),
16099 /* ATPCS synonyms. */
16100 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16101 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16102 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16104 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16105 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16106 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16108 /* Well-known aliases. */
16109 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16110 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16112 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16113 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16115 /* Coprocessor numbers. */
16116 REGSET(p
, CP
), REGSET(P
, CP
),
16118 /* Coprocessor register numbers. The "cr" variants are for backward
16120 REGSET(c
, CN
), REGSET(C
, CN
),
16121 REGSET(cr
, CN
), REGSET(CR
, CN
),
16123 /* FPA registers. */
16124 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16125 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16127 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16128 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16130 /* VFP SP registers. */
16131 REGSET(s
,VFS
), REGSET(S
,VFS
),
16132 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16134 /* VFP DP Registers. */
16135 REGSET(d
,VFD
), REGSET(D
,VFD
),
16136 /* Extra Neon DP registers. */
16137 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16139 /* Neon QP registers. */
16140 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16142 /* VFP control registers. */
16143 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16144 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16145 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16146 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16147 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16148 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16150 /* Maverick DSP coprocessor registers. */
16151 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16152 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16154 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16155 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16156 REGDEF(dspsc
,0,DSPSC
),
16158 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16159 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16160 REGDEF(DSPSC
,0,DSPSC
),
16162 /* iWMMXt data registers - p0, c0-15. */
16163 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16165 /* iWMMXt control registers - p1, c0-3. */
16166 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16167 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16168 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16169 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16171 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16172 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16173 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16174 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16175 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16177 /* XScale accumulator registers. */
16178 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16184 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16185 within psr_required_here. */
16186 static const struct asm_psr psrs
[] =
16188 /* Backward compatibility notation. Note that "all" is no longer
16189 truly all possible PSR bits. */
16190 {"all", PSR_c
| PSR_f
},
16194 /* Individual flags. */
16199 /* Combinations of flags. */
16200 {"fs", PSR_f
| PSR_s
},
16201 {"fx", PSR_f
| PSR_x
},
16202 {"fc", PSR_f
| PSR_c
},
16203 {"sf", PSR_s
| PSR_f
},
16204 {"sx", PSR_s
| PSR_x
},
16205 {"sc", PSR_s
| PSR_c
},
16206 {"xf", PSR_x
| PSR_f
},
16207 {"xs", PSR_x
| PSR_s
},
16208 {"xc", PSR_x
| PSR_c
},
16209 {"cf", PSR_c
| PSR_f
},
16210 {"cs", PSR_c
| PSR_s
},
16211 {"cx", PSR_c
| PSR_x
},
16212 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16213 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16214 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16215 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16216 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16217 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16218 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16219 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16220 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16221 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16222 {"scf", PSR_s
| PSR_c
| PSR_f
},
16223 {"scx", PSR_s
| PSR_c
| PSR_x
},
16224 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16225 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16226 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16227 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16228 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16229 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16230 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16231 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16232 {"csf", PSR_c
| PSR_s
| PSR_f
},
16233 {"csx", PSR_c
| PSR_s
| PSR_x
},
16234 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16235 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16236 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16237 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16238 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16239 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16240 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16241 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16242 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16243 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16244 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16245 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16246 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16247 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16248 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16249 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16250 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16251 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16252 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16253 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16254 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16255 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16256 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16257 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16258 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16259 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16262 /* Table of V7M psr names. */
16263 static const struct asm_psr v7m_psrs
[] =
16265 {"apsr", 0 }, {"APSR", 0 },
16266 {"iapsr", 1 }, {"IAPSR", 1 },
16267 {"eapsr", 2 }, {"EAPSR", 2 },
16268 {"psr", 3 }, {"PSR", 3 },
16269 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16270 {"ipsr", 5 }, {"IPSR", 5 },
16271 {"epsr", 6 }, {"EPSR", 6 },
16272 {"iepsr", 7 }, {"IEPSR", 7 },
16273 {"msp", 8 }, {"MSP", 8 },
16274 {"psp", 9 }, {"PSP", 9 },
16275 {"primask", 16}, {"PRIMASK", 16},
16276 {"basepri", 17}, {"BASEPRI", 17},
16277 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16278 {"faultmask", 19}, {"FAULTMASK", 19},
16279 {"control", 20}, {"CONTROL", 20}
16282 /* Table of all shift-in-operand names. */
16283 static const struct asm_shift_name shift_names
[] =
16285 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16286 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16287 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16288 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16289 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16290 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16293 /* Table of all explicit relocation names. */
16295 static struct reloc_entry reloc_names
[] =
16297 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16298 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16299 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16300 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16301 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16302 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16303 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16304 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16305 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16306 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16307 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16308 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
}
16312 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16313 static const struct asm_cond conds
[] =
16317 {"cs", 0x2}, {"hs", 0x2},
16318 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16332 static struct asm_barrier_opt barrier_opt_names
[] =
16334 { "sy", 0xf }, { "SY", 0xf },
16335 { "un", 0x7 }, { "UN", 0x7 },
16336 { "st", 0xe }, { "ST", 0xe },
16337 { "unst", 0x6 }, { "UNST", 0x6 },
16338 { "ish", 0xb }, { "ISH", 0xb },
16339 { "sh", 0xb }, { "SH", 0xb },
16340 { "ishst", 0xa }, { "ISHST", 0xa },
16341 { "shst", 0xa }, { "SHST", 0xa },
16342 { "nsh", 0x7 }, { "NSH", 0x7 },
16343 { "nshst", 0x6 }, { "NSHST", 0x6 },
16344 { "osh", 0x3 }, { "OSH", 0x3 },
16345 { "oshst", 0x2 }, { "OSHST", 0x2 }
16348 /* Table of ARM-format instructions. */
16350 /* Macros for gluing together operand strings. N.B. In all cases
16351 other than OPS0, the trailing OP_stop comes from default
16352 zero-initialization of the unspecified elements of the array. */
16353 #define OPS0() { OP_stop, }
16354 #define OPS1(a) { OP_##a, }
16355 #define OPS2(a,b) { OP_##a,OP_##b, }
16356 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16357 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16358 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16359 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16361 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16362 This is useful when mixing operands for ARM and THUMB, i.e. using the
16363 MIX_ARM_THUMB_OPERANDS macro.
16364 In order to use these macros, prefix the number of operands with _
16366 #define OPS_1(a) { a, }
16367 #define OPS_2(a,b) { a,b, }
16368 #define OPS_3(a,b,c) { a,b,c, }
16369 #define OPS_4(a,b,c,d) { a,b,c,d, }
16370 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16371 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16373 /* These macros abstract out the exact format of the mnemonic table and
16374 save some repeated characters. */
16376 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16377 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16378 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16379 THUMB_VARIANT, do_##ae, do_##te }
16381 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16382 a T_MNEM_xyz enumerator. */
16383 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16384 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16385 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16386 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16388 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16389 infix after the third character. */
16390 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16391 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16392 THUMB_VARIANT, do_##ae, do_##te }
16393 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16394 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16395 THUMB_VARIANT, do_##ae, do_##te }
16396 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16397 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16398 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16399 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16400 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16401 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16402 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16403 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16405 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16406 appear in the condition table. */
16407 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16408 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16409 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16411 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16412 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16413 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16414 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16415 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16416 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16417 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16418 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16419 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16420 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16421 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16422 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16423 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16424 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16425 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16426 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16427 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16428 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16429 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16430 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16432 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16433 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16434 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16435 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16437 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16438 field is still 0xE. Many of the Thumb variants can be executed
16439 conditionally, so this is checked separately. */
16440 #define TUE(mnem, op, top, nops, ops, ae, te) \
16441 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16442 THUMB_VARIANT, do_##ae, do_##te }
16444 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16445 condition code field. */
16446 #define TUF(mnem, op, top, nops, ops, ae, te) \
16447 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16448 THUMB_VARIANT, do_##ae, do_##te }
16450 /* ARM-only variants of all the above. */
16451 #define CE(mnem, op, nops, ops, ae) \
16452 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16454 #define C3(mnem, op, nops, ops, ae) \
16455 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16457 /* Legacy mnemonics that always have conditional infix after the third
16459 #define CL(mnem, op, nops, ops, ae) \
16460 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16461 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16463 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16464 #define cCE(mnem, op, nops, ops, ae) \
16465 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16467 /* Legacy coprocessor instructions where conditional infix and conditional
16468 suffix are ambiguous. For consistency this includes all FPA instructions,
16469 not just the potentially ambiguous ones. */
16470 #define cCL(mnem, op, nops, ops, ae) \
16471 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16472 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16474 /* Coprocessor, takes either a suffix or a position-3 infix
16475 (for an FPA corner case). */
16476 #define C3E(mnem, op, nops, ops, ae) \
16477 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16478 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16480 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16481 { m1 #m2 m3, OPS##nops ops, \
16482 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16483 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16485 #define CM(m1, m2, op, nops, ops, ae) \
16486 xCM_ (m1, , m2, op, nops, ops, ae), \
16487 xCM_ (m1, eq, m2, op, nops, ops, ae), \
16488 xCM_ (m1, ne, m2, op, nops, ops, ae), \
16489 xCM_ (m1, cs, m2, op, nops, ops, ae), \
16490 xCM_ (m1, hs, m2, op, nops, ops, ae), \
16491 xCM_ (m1, cc, m2, op, nops, ops, ae), \
16492 xCM_ (m1, ul, m2, op, nops, ops, ae), \
16493 xCM_ (m1, lo, m2, op, nops, ops, ae), \
16494 xCM_ (m1, mi, m2, op, nops, ops, ae), \
16495 xCM_ (m1, pl, m2, op, nops, ops, ae), \
16496 xCM_ (m1, vs, m2, op, nops, ops, ae), \
16497 xCM_ (m1, vc, m2, op, nops, ops, ae), \
16498 xCM_ (m1, hi, m2, op, nops, ops, ae), \
16499 xCM_ (m1, ls, m2, op, nops, ops, ae), \
16500 xCM_ (m1, ge, m2, op, nops, ops, ae), \
16501 xCM_ (m1, lt, m2, op, nops, ops, ae), \
16502 xCM_ (m1, gt, m2, op, nops, ops, ae), \
16503 xCM_ (m1, le, m2, op, nops, ops, ae), \
16504 xCM_ (m1, al, m2, op, nops, ops, ae)
16506 #define UE(mnem, op, nops, ops, ae) \
16507 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16509 #define UF(mnem, op, nops, ops, ae) \
16510 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
16512 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
16513 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
16514 use the same encoding function for each. */
16515 #define NUF(mnem, op, nops, ops, enc) \
16516 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
16517 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16519 /* Neon data processing, version which indirects through neon_enc_tab for
16520 the various overloaded versions of opcodes. */
16521 #define nUF(mnem, op, nops, ops, enc) \
16522 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
16523 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16525 /* Neon insn with conditional suffix for the ARM version, non-overloaded
16527 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
16528 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
16529 THUMB_VARIANT, do_##enc, do_##enc }
16531 #define NCE(mnem, op, nops, ops, enc) \
16532 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16534 #define NCEF(mnem, op, nops, ops, enc) \
16535 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16537 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
16538 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
16539 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
16540 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
16542 #define nCE(mnem, op, nops, ops, enc) \
16543 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
16545 #define nCEF(mnem, op, nops, ops, enc) \
16546 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
16550 static const struct asm_opcode insns
[] =
16552 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
16553 #define THUMB_VARIANT &arm_ext_v4t
16554 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16555 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16556 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16557 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16558 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16559 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
16560 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16561 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
16562 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16563 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16564 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16565 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16566 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16567 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
16568 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16569 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
16571 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
16572 for setting PSR flag bits. They are obsolete in V6 and do not
16573 have Thumb equivalents. */
16574 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16575 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16576 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
16577 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16578 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
16579 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
16580 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16581 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16582 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
16584 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16585 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
16586 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16587 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
16589 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
16590 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16591 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
16593 OP_ADDRGLDR
),ldst
, t_ldst
),
16594 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
16596 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16597 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16598 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16599 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16600 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16601 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16603 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16604 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
16605 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
16606 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
16609 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
16610 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
16611 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
16613 /* Thumb-compatibility pseudo ops. */
16614 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16615 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16616 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16617 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16618 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16619 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16620 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16621 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
16622 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
16623 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
16624 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
16625 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
16627 /* These may simplify to neg. */
16628 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16629 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
16631 #undef THUMB_VARIANT
16632 #define THUMB_VARIANT & arm_ext_v6
16634 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
16636 /* V1 instructions with no Thumb analogue prior to V6T2. */
16637 #undef THUMB_VARIANT
16638 #define THUMB_VARIANT & arm_ext_v6t2
16640 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16641 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
16642 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
16644 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16645 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16646 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
16647 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
16649 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16650 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16652 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16653 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
16655 /* V1 instructions with no Thumb analogue at all. */
16656 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
16657 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
16659 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16660 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
16661 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16662 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
16663 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16664 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
16665 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16666 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
16669 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
16670 #undef THUMB_VARIANT
16671 #define THUMB_VARIANT & arm_ext_v4t
16673 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16674 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
16676 #undef THUMB_VARIANT
16677 #define THUMB_VARIANT & arm_ext_v6t2
16679 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16680 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
16682 /* Generic coprocessor instructions. */
16683 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16684 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16685 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16686 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16687 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16688 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16689 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16692 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
16694 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16695 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
16698 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
16699 #undef THUMB_VARIANT
16700 #define THUMB_VARIANT & arm_ext_msr
16702 TCE("mrs", 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
16703 TCE("msr", 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
16706 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
16707 #undef THUMB_VARIANT
16708 #define THUMB_VARIANT & arm_ext_v6t2
16710 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16711 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16712 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16713 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16714 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16715 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16716 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
16717 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
16720 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
16721 #undef THUMB_VARIANT
16722 #define THUMB_VARIANT & arm_ext_v4t
16724 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16725 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16726 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16727 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16728 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16729 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
16732 #define ARM_VARIANT & arm_ext_v4t_5
16734 /* ARM Architecture 4T. */
16735 /* Note: bx (and blx) are required on V5, even if the processor does
16736 not support Thumb. */
16737 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
16740 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
16741 #undef THUMB_VARIANT
16742 #define THUMB_VARIANT & arm_ext_v5t
16744 /* Note: blx has 2 variants; the .value coded here is for
16745 BLX(2). Only this variant has conditional execution. */
16746 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
16747 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
16749 #undef THUMB_VARIANT
16750 #define THUMB_VARIANT & arm_ext_v6t2
16752 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
16753 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16754 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16755 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16756 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
16757 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
16758 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16759 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
16762 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
16763 #undef THUMB_VARIANT
16764 #define THUMB_VARIANT &arm_ext_v5exp
16766 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16767 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16768 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16769 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16771 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16772 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
16774 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16775 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16776 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16777 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
16779 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16780 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16781 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16782 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16784 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16785 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16787 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16788 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16789 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16790 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
16793 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
16794 #undef THUMB_VARIANT
16795 #define THUMB_VARIANT &arm_ext_v6t2
16797 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
16798 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
16800 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
16801 ADDRGLDRS
), ldrd
, t_ldstd
),
16803 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16804 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16807 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
16809 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
16812 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
16813 #undef THUMB_VARIANT
16814 #define THUMB_VARIANT & arm_ext_v6
16816 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16817 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
16818 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16819 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16820 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
16821 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16822 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16823 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16824 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16825 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
16827 #undef THUMB_VARIANT
16828 #define THUMB_VARIANT & arm_ext_v6t2
16830 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
16831 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16833 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16834 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
16836 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
16837 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
16839 /* ARM V6 not included in V7M. */
16840 #undef THUMB_VARIANT
16841 #define THUMB_VARIANT & arm_ext_v6_notm
16842 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16843 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
16844 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
16845 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16846 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
16847 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
16848 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
16849 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
16850 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
16851 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
16852 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
16853 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
16855 /* ARM V6 not included in V7M (eg. integer SIMD). */
16856 #undef THUMB_VARIANT
16857 #define THUMB_VARIANT & arm_ext_v6_dsp
16858 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
16859 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
16860 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
16861 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16862 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16863 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16864 /* Old name for QASX. */
16865 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16866 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16867 /* Old name for QSAX. */
16868 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16869 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16870 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16871 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16872 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16873 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16874 /* Old name for SASX. */
16875 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16876 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16877 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16878 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16879 /* Old name for SHASX. */
16880 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16881 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16882 /* Old name for SHSAX. */
16883 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16884 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16885 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16886 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16887 /* Old name for SSAX. */
16888 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16889 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16890 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16891 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16892 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16893 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16894 /* Old name for UASX. */
16895 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16896 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16897 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16898 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16899 /* Old name for UHASX. */
16900 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16901 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16902 /* Old name for UHSAX. */
16903 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16904 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16905 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16906 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16907 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16908 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16909 /* Old name for UQASX. */
16910 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16911 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16912 /* Old name for UQSAX. */
16913 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16914 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16915 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16916 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16917 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16918 /* Old name for USAX. */
16919 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16920 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16921 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16922 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16923 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16924 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16925 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16926 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16927 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
16928 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
16929 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
16930 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16931 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16932 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16933 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16934 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16935 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16936 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16937 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
16938 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16939 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16940 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16941 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16942 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16943 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16944 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16945 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16946 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16947 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16948 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
16949 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
16950 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
16951 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
16952 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
16955 #define ARM_VARIANT & arm_ext_v6k
16956 #undef THUMB_VARIANT
16957 #define THUMB_VARIANT & arm_ext_v6k
16959 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
16960 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
16961 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
16962 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
16964 #undef THUMB_VARIANT
16965 #define THUMB_VARIANT & arm_ext_v6_notm
16966 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
16968 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
16969 RRnpcb
), strexd
, t_strexd
),
16971 #undef THUMB_VARIANT
16972 #define THUMB_VARIANT & arm_ext_v6t2
16973 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
16975 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
16977 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16979 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
16981 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
16984 #define ARM_VARIANT & arm_ext_v6z
16986 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
16989 #define ARM_VARIANT & arm_ext_v6t2
16991 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
16992 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
16993 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16994 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
16996 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
16997 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16998 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
16999 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17001 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17002 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17003 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17004 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17006 /* Thumb-only instructions. */
17008 #define ARM_VARIANT NULL
17009 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17010 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17012 /* ARM does not really have an IT instruction, so always allow it.
17013 The opcode is copied from Thumb in order to allow warnings in
17014 -mimplicit-it=[never | arm] modes. */
17016 #define ARM_VARIANT & arm_ext_v1
17018 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17019 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17020 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17021 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17022 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17023 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17024 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17025 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17026 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17027 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17028 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17029 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17030 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17031 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17032 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17033 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17034 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17035 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17037 /* Thumb2 only instructions. */
17039 #define ARM_VARIANT NULL
17041 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17042 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17043 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17044 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17045 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17046 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17048 /* Thumb-2 hardware division instructions (R and M profiles only). */
17049 #undef THUMB_VARIANT
17050 #define THUMB_VARIANT & arm_ext_div
17052 TCE("sdiv", 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17053 TCE("udiv", 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
17055 /* ARM V6M/V7 instructions. */
17057 #define ARM_VARIANT & arm_ext_barrier
17058 #undef THUMB_VARIANT
17059 #define THUMB_VARIANT & arm_ext_barrier
17061 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17062 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17063 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17065 /* ARM V7 instructions. */
17067 #define ARM_VARIANT & arm_ext_v7
17068 #undef THUMB_VARIANT
17069 #define THUMB_VARIANT & arm_ext_v7
17071 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17072 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17075 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17077 cCE("wfs", e200110
, 1, (RR
), rd
),
17078 cCE("rfs", e300110
, 1, (RR
), rd
),
17079 cCE("wfc", e400110
, 1, (RR
), rd
),
17080 cCE("rfc", e500110
, 1, (RR
), rd
),
17082 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17083 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17084 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17085 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17087 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17088 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17089 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17090 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17092 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17093 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17094 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17095 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17096 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17097 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17098 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17099 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17100 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17101 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17102 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17103 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17105 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17106 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17107 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17108 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17109 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17110 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17111 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17112 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17113 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17114 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17115 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17116 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17118 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17119 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17120 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17121 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17122 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17123 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17124 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17125 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17126 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17127 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17128 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17129 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17131 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17132 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17133 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17134 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17135 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17136 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17137 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17138 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17139 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17140 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17141 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17142 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17144 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17145 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17146 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17147 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17148 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17149 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17150 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17151 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17152 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17153 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17154 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17155 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17157 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17158 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17159 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17160 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17161 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17162 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17163 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17164 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17165 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17166 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17167 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17168 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17170 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17171 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17172 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17173 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17174 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17175 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17176 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17177 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17178 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17179 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17180 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17181 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17183 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17184 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17185 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17186 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17187 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17188 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17189 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17190 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17191 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17192 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17193 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17194 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17196 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17197 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17198 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17199 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17200 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17201 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17202 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17203 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17204 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17205 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17206 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17207 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17209 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17210 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17211 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17212 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17213 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17214 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17215 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17216 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17217 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17218 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17219 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17220 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17222 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17223 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17224 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17225 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17226 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17227 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17228 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17229 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17230 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17231 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17232 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17233 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17235 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17236 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17237 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17238 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17239 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17240 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17241 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17242 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17243 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17244 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17245 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17246 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17248 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17249 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17250 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17251 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17252 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17253 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17254 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17255 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17256 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17257 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17258 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17259 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17261 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17262 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17263 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17264 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17265 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17266 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17267 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17268 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17269 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17270 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17271 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17272 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17274 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17275 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17276 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17277 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17278 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17279 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17280 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17281 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17282 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17283 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17284 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17285 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17287 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17288 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17289 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17290 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17291 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17292 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17293 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17294 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17295 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17296 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17297 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17298 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17300 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17301 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17302 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17303 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17304 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17305 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17306 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17307 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17308 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17309 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17310 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17311 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17313 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17314 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17315 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17316 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17317 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17318 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17319 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17320 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17321 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17322 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17323 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17324 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17326 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17327 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17328 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17329 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17330 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17331 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17332 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17333 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17334 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17335 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17336 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17337 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17339 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17340 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17341 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17342 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17343 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17344 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17345 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17346 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17347 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17348 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17349 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17350 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17352 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17353 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17354 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17355 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17356 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17357 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17358 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17359 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17360 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17361 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17362 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17363 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17365 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17366 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17367 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17368 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17369 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17370 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17371 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17372 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17373 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17374 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17375 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17376 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17378 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17379 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17380 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17381 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17382 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17383 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17384 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17385 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17386 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17387 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17388 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17389 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17391 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17392 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17393 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17394 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17395 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17396 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17397 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17398 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17399 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17400 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17401 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17402 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17404 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17405 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17406 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17407 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17408 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17409 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17410 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17411 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17412 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17413 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17414 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17415 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17417 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17418 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17419 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17420 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17421 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17422 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17423 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17424 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17425 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17426 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17427 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17428 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17430 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17431 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17432 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17433 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17434 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17435 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17436 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17437 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17438 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17439 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17440 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17441 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17443 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17444 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17445 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17446 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17447 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17448 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17449 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17450 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17451 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17452 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17453 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17454 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17456 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17457 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17458 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17459 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17460 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17461 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17462 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17463 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17464 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17465 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17466 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17467 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17469 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17470 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17471 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17472 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
17474 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
17475 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
17476 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
17477 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
17478 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
17479 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
17480 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
17481 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
17482 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
17483 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
17484 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
17485 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
17487 /* The implementation of the FIX instruction is broken on some
17488 assemblers, in that it accepts a precision specifier as well as a
17489 rounding specifier, despite the fact that this is meaningless.
17490 To be more compatible, we accept it as well, though of course it
17491 does not set any bits. */
17492 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
17493 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
17494 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
17495 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
17496 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
17497 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
17498 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
17499 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
17500 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
17501 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
17502 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
17503 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
17504 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
17506 /* Instructions that were new with the real FPA, call them V2. */
17508 #define ARM_VARIANT & fpu_fpa_ext_v2
17510 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17511 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17512 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17513 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17514 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17515 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
17518 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
17520 /* Moves and type conversions. */
17521 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17522 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
17523 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
17524 cCE("fmstat", ef1fa10
, 0, (), noargs
),
17525 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
17526 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
17527 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17528 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17529 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17530 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17531 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17532 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17533 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
17534 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
17536 /* Memory operations. */
17537 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17538 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
17539 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17540 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17541 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17542 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17543 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17544 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17545 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17546 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17547 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17548 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
17549 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17550 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
17551 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17552 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
17553 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17554 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
17556 /* Monadic operations. */
17557 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17558 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17559 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17561 /* Dyadic operations. */
17562 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17563 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17564 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17565 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17566 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17567 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17568 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17569 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17570 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17573 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17574 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
17575 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
17576 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
17578 /* Double precision load/store are still present on single precision
17579 implementations. */
17580 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17581 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
17582 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17583 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17584 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17585 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17586 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17587 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
17588 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17589 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
17592 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
17594 /* Moves and type conversions. */
17595 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17596 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17597 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17598 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17599 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
17600 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17601 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
17602 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17603 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
17604 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17605 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17606 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17607 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
17609 /* Monadic operations. */
17610 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17611 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17612 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17614 /* Dyadic operations. */
17615 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17616 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17617 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17618 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17619 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17620 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17621 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17622 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17623 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17626 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17627 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
17628 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
17629 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
17632 #define ARM_VARIANT & fpu_vfp_ext_v2
17634 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
17635 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
17636 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
17637 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
17639 /* Instructions which may belong to either the Neon or VFP instruction sets.
17640 Individual encoder functions perform additional architecture checks. */
17642 #define ARM_VARIANT & fpu_vfp_ext_v1xd
17643 #undef THUMB_VARIANT
17644 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
17646 /* These mnemonics are unique to VFP. */
17647 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
17648 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
17649 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17650 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17651 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17652 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17653 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
17654 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
17655 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
17656 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
17658 /* Mnemonics shared by Neon and VFP. */
17659 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
17660 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17661 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
17663 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17664 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
17666 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17667 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
17669 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17670 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17671 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17672 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17673 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17674 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
17675 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17676 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
17678 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
17679 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
17680 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
17681 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
17684 /* NOTE: All VMOV encoding is special-cased! */
17685 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
17686 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
17688 #undef THUMB_VARIANT
17689 #define THUMB_VARIANT & fpu_neon_ext_v1
17691 #define ARM_VARIANT & fpu_neon_ext_v1
17693 /* Data processing with three registers of the same length. */
17694 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
17695 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
17696 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
17697 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17698 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17699 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17700 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17701 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
17702 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
17703 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
17704 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17705 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17706 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
17707 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
17708 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17709 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17710 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
17711 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
17712 /* If not immediate, fall back to neon_dyadic_i64_su.
17713 shl_imm should accept I8 I16 I32 I64,
17714 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
17715 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
17716 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
17717 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
17718 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
17719 /* Logic ops, types optional & ignored. */
17720 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17721 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17722 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17723 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17724 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17725 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17726 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
17727 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
17728 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
17729 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
17730 /* Bitfield ops, untyped. */
17731 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17732 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17733 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17734 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17735 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
17736 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
17737 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
17738 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17739 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17740 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17741 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17742 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
17743 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
17744 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
17745 back to neon_dyadic_if_su. */
17746 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17747 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17748 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
17749 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
17750 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17751 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17752 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
17753 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
17754 /* Comparison. Type I8 I16 I32 F32. */
17755 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
17756 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
17757 /* As above, D registers only. */
17758 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17759 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
17760 /* Int and float variants, signedness unimportant. */
17761 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17762 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
17763 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
17764 /* Add/sub take types I8 I16 I32 I64 F32. */
17765 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17766 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
17767 /* vtst takes sizes 8, 16, 32. */
17768 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
17769 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
17770 /* VMUL takes I8 I16 I32 F32 P8. */
17771 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
17772 /* VQD{R}MULH takes S16 S32. */
17773 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17774 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17775 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
17776 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
17777 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17778 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17779 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
17780 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
17781 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17782 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17783 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
17784 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
17785 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17786 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17787 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
17788 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
17790 /* Two address, int/float. Types S8 S16 S32 F32. */
17791 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17792 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
17794 /* Data processing with two registers and a shift amount. */
17795 /* Right shifts, and variants with rounding.
17796 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
17797 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17798 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17799 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
17800 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
17801 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17802 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17803 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
17804 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
17805 /* Shift and insert. Sizes accepted 8 16 32 64. */
17806 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
17807 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
17808 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
17809 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
17810 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
17811 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
17812 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
17813 /* Right shift immediate, saturating & narrowing, with rounding variants.
17814 Types accepted S16 S32 S64 U16 U32 U64. */
17815 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17816 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
17817 /* As above, unsigned. Types accepted S16 S32 S64. */
17818 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17819 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
17820 /* Right shift narrowing. Types accepted I16 I32 I64. */
17821 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17822 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
17823 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
17824 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
17825 /* CVT with optional immediate for fixed-point variant. */
17826 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
17828 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
17829 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
17831 /* Data processing, three registers of different lengths. */
17832 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
17833 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
17834 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17835 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17836 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
17837 /* If not scalar, fall back to neon_dyadic_long.
17838 Vector types as above, scalar types S16 S32 U16 U32. */
17839 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17840 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
17841 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
17842 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17843 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
17844 /* Dyadic, narrowing insns. Types I16 I32 I64. */
17845 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17846 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17847 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17848 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
17849 /* Saturating doubling multiplies. Types S16 S32. */
17850 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17851 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17852 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
17853 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
17854 S16 S32 U16 U32. */
17855 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
17857 /* Extract. Size 8. */
17858 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
17859 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
17861 /* Two registers, miscellaneous. */
17862 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
17863 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
17864 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
17865 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
17866 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
17867 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
17868 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
17869 /* Vector replicate. Sizes 8 16 32. */
17870 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
17871 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
17872 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
17873 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
17874 /* VMOVN. Types I16 I32 I64. */
17875 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
17876 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
17877 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
17878 /* VQMOVUN. Types S16 S32 S64. */
17879 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
17880 /* VZIP / VUZP. Sizes 8 16 32. */
17881 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17882 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17883 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
17884 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
17885 /* VQABS / VQNEG. Types S8 S16 S32. */
17886 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17887 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17888 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
17889 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
17890 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
17891 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17892 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
17893 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
17894 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
17895 /* Reciprocal estimates. Types U32 F32. */
17896 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17897 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
17898 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
17899 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
17900 /* VCLS. Types S8 S16 S32. */
17901 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
17902 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
17903 /* VCLZ. Types I8 I16 I32. */
17904 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
17905 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
17906 /* VCNT. Size 8. */
17907 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
17908 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
17909 /* Two address, untyped. */
17910 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
17911 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
17912 /* VTRN. Sizes 8 16 32. */
17913 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
17914 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
17916 /* Table lookup. Size 8. */
17917 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17918 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
17920 #undef THUMB_VARIANT
17921 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
17923 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
17925 /* Neon element/structure load/store. */
17926 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17927 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17928 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17929 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17930 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17931 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17932 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17933 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
17935 #undef THUMB_VARIANT
17936 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
17938 #define ARM_VARIANT &fpu_vfp_ext_v3xd
17939 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
17940 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17941 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17942 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17943 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17944 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17945 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17946 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
17947 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
17949 #undef THUMB_VARIANT
17950 #define THUMB_VARIANT & fpu_vfp_ext_v3
17952 #define ARM_VARIANT & fpu_vfp_ext_v3
17954 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
17955 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17956 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17957 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17958 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17959 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17960 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17961 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
17962 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
17965 #define ARM_VARIANT &fpu_vfp_ext_fma
17966 #undef THUMB_VARIANT
17967 #define THUMB_VARIANT &fpu_vfp_ext_fma
17968 /* Mnemonics shared by Neon and VFP. These are included in the
17969 VFP FMA variant; NEON and VFP FMA always includes the NEON
17970 FMA instructions. */
17971 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17972 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
17973 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
17974 the v form should always be used. */
17975 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17976 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
17977 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17978 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
17979 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17980 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
17982 #undef THUMB_VARIANT
17984 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
17986 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17987 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17988 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17989 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17990 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17991 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
17992 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
17993 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
17996 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
17998 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
17999 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18000 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18001 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18002 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18003 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18004 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18005 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18006 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18007 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18008 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18009 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18010 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18011 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18012 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18013 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18014 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18015 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18016 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18017 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18018 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18019 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18020 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18021 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18022 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18023 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18024 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18025 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18026 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18027 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18028 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18029 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18030 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18031 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18032 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18033 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18034 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18035 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18036 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18037 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18038 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18039 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18040 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18041 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18042 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18043 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18044 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18045 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18046 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18047 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18048 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18049 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18050 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18051 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18052 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18053 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18054 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18055 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18056 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18057 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18058 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18059 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18060 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18061 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18062 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18063 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18064 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18065 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18066 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18067 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18068 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18069 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18070 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18071 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18072 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18073 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18074 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18075 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18076 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18077 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18078 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18079 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18080 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18081 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18082 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18083 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18084 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18085 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18086 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18087 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18088 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18089 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18090 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18091 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18092 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18093 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18094 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18095 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18096 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18097 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18098 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18099 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18100 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18101 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18102 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18103 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18104 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18105 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18106 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18107 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18108 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18109 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18110 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18111 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18112 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18113 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18114 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18115 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18116 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18117 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18118 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18119 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18120 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18121 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18122 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18123 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18124 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18125 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18126 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18127 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18128 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18129 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18130 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18131 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18132 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18133 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18134 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18135 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18136 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18137 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18138 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18139 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18140 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18141 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18142 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18143 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18144 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18145 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18146 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18147 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18148 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18149 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18150 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18151 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18152 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18153 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18154 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18155 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18156 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18157 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18158 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18159 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18162 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18164 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18165 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18166 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18167 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18168 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18169 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18170 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18171 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18172 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18173 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18174 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18175 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18176 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18177 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18178 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18179 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18180 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18181 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18182 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18183 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18184 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18185 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18186 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18187 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18188 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18189 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18190 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18191 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18192 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18193 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18194 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18195 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18196 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18197 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18198 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18199 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18200 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18201 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18202 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18203 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18204 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18205 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18206 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18207 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18208 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18209 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18210 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18211 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18212 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18213 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18214 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18215 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18216 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18217 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18218 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18219 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18220 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18223 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18225 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18226 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18227 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18228 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18229 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18230 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18231 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18232 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18233 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18234 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18235 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18236 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18237 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18238 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18239 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18240 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18241 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18242 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18243 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18244 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18245 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18246 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18247 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18248 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18249 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18250 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18251 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18252 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18253 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18254 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18255 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18256 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18257 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18258 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18259 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18260 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18261 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18262 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18263 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18264 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18265 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18266 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18267 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18268 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18269 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18270 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18271 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18272 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18273 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18274 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18275 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18276 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18277 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18278 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18279 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18280 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18281 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18282 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18283 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18284 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18285 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18286 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18287 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18288 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18289 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18290 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18291 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18292 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18293 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18294 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18295 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18296 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18297 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18298 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18299 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18300 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18303 #undef THUMB_VARIANT
18330 /* MD interface: bits in the object file. */
18332 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18333 for use in the a.out file, and stores them in the array pointed to by buf.
18334 This knows about the endian-ness of the target machine and does
18335 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18336 2 (short) and 4 (long) Floating numbers are put out as a series of
18337 LITTLENUMS (shorts, here at least). */
18340 md_number_to_chars (char * buf
, valueT val
, int n
)
18342 if (target_big_endian
)
18343 number_to_chars_bigendian (buf
, val
, n
);
18345 number_to_chars_littleendian (buf
, val
, n
);
18349 md_chars_to_number (char * buf
, int n
)
18352 unsigned char * where
= (unsigned char *) buf
;
18354 if (target_big_endian
)
18359 result
|= (*where
++ & 255);
18367 result
|= (where
[n
] & 255);
18374 /* MD interface: Sections. */
18376 /* Estimate the size of a frag before relaxing. Assume everything fits in
18380 md_estimate_size_before_relax (fragS
* fragp
,
18381 segT segtype ATTRIBUTE_UNUSED
)
18387 /* Convert a machine dependent frag. */
18390 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18392 unsigned long insn
;
18393 unsigned long old_op
;
18401 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18403 old_op
= bfd_get_16(abfd
, buf
);
18404 if (fragp
->fr_symbol
)
18406 exp
.X_op
= O_symbol
;
18407 exp
.X_add_symbol
= fragp
->fr_symbol
;
18411 exp
.X_op
= O_constant
;
18413 exp
.X_add_number
= fragp
->fr_offset
;
18414 opcode
= fragp
->fr_subtype
;
18417 case T_MNEM_ldr_pc
:
18418 case T_MNEM_ldr_pc2
:
18419 case T_MNEM_ldr_sp
:
18420 case T_MNEM_str_sp
:
18427 if (fragp
->fr_var
== 4)
18429 insn
= THUMB_OP32 (opcode
);
18430 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18432 insn
|= (old_op
& 0x700) << 4;
18436 insn
|= (old_op
& 7) << 12;
18437 insn
|= (old_op
& 0x38) << 13;
18439 insn
|= 0x00000c00;
18440 put_thumb32_insn (buf
, insn
);
18441 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18445 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18447 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18450 if (fragp
->fr_var
== 4)
18452 insn
= THUMB_OP32 (opcode
);
18453 insn
|= (old_op
& 0xf0) << 4;
18454 put_thumb32_insn (buf
, insn
);
18455 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18459 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18460 exp
.X_add_number
-= 4;
18468 if (fragp
->fr_var
== 4)
18470 int r0off
= (opcode
== T_MNEM_mov
18471 || opcode
== T_MNEM_movs
) ? 0 : 8;
18472 insn
= THUMB_OP32 (opcode
);
18473 insn
= (insn
& 0xe1ffffff) | 0x10000000;
18474 insn
|= (old_op
& 0x700) << r0off
;
18475 put_thumb32_insn (buf
, insn
);
18476 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18480 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
18485 if (fragp
->fr_var
== 4)
18487 insn
= THUMB_OP32(opcode
);
18488 put_thumb32_insn (buf
, insn
);
18489 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
18492 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
18496 if (fragp
->fr_var
== 4)
18498 insn
= THUMB_OP32(opcode
);
18499 insn
|= (old_op
& 0xf00) << 14;
18500 put_thumb32_insn (buf
, insn
);
18501 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
18504 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
18507 case T_MNEM_add_sp
:
18508 case T_MNEM_add_pc
:
18509 case T_MNEM_inc_sp
:
18510 case T_MNEM_dec_sp
:
18511 if (fragp
->fr_var
== 4)
18513 /* ??? Choose between add and addw. */
18514 insn
= THUMB_OP32 (opcode
);
18515 insn
|= (old_op
& 0xf0) << 4;
18516 put_thumb32_insn (buf
, insn
);
18517 if (opcode
== T_MNEM_add_pc
)
18518 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
18520 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18523 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18531 if (fragp
->fr_var
== 4)
18533 insn
= THUMB_OP32 (opcode
);
18534 insn
|= (old_op
& 0xf0) << 4;
18535 insn
|= (old_op
& 0xf) << 16;
18536 put_thumb32_insn (buf
, insn
);
18537 if (insn
& (1 << 20))
18538 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
18540 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
18543 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18549 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
18550 (enum bfd_reloc_code_real
) reloc_type
);
18551 fixp
->fx_file
= fragp
->fr_file
;
18552 fixp
->fx_line
= fragp
->fr_line
;
18553 fragp
->fr_fix
+= fragp
->fr_var
;
18556 /* Return the size of a relaxable immediate operand instruction.
18557 SHIFT and SIZE specify the form of the allowable immediate. */
18559 relax_immediate (fragS
*fragp
, int size
, int shift
)
18565 /* ??? Should be able to do better than this. */
18566 if (fragp
->fr_symbol
)
18569 low
= (1 << shift
) - 1;
18570 mask
= (1 << (shift
+ size
)) - (1 << shift
);
18571 offset
= fragp
->fr_offset
;
18572 /* Force misaligned offsets to 32-bit variant. */
18575 if (offset
& ~mask
)
18580 /* Get the address of a symbol during relaxation. */
18582 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
18588 sym
= fragp
->fr_symbol
;
18589 sym_frag
= symbol_get_frag (sym
);
18590 know (S_GET_SEGMENT (sym
) != absolute_section
18591 || sym_frag
== &zero_address_frag
);
18592 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
18594 /* If frag has yet to be reached on this pass, assume it will
18595 move by STRETCH just as we did. If this is not so, it will
18596 be because some frag between grows, and that will force
18600 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
18604 /* Adjust stretch for any alignment frag. Note that if have
18605 been expanding the earlier code, the symbol may be
18606 defined in what appears to be an earlier frag. FIXME:
18607 This doesn't handle the fr_subtype field, which specifies
18608 a maximum number of bytes to skip when doing an
18610 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
18612 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
18615 stretch
= - ((- stretch
)
18616 & ~ ((1 << (int) f
->fr_offset
) - 1));
18618 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
18630 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
18633 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
18638 /* Assume worst case for symbols not known to be in the same section. */
18639 if (fragp
->fr_symbol
== NULL
18640 || !S_IS_DEFINED (fragp
->fr_symbol
)
18641 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18642 || S_IS_WEAK (fragp
->fr_symbol
))
18645 val
= relaxed_symbol_addr (fragp
, stretch
);
18646 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
18647 addr
= (addr
+ 4) & ~3;
18648 /* Force misaligned targets to 32-bit variant. */
18652 if (val
< 0 || val
> 1020)
18657 /* Return the size of a relaxable add/sub immediate instruction. */
18659 relax_addsub (fragS
*fragp
, asection
*sec
)
18664 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18665 op
= bfd_get_16(sec
->owner
, buf
);
18666 if ((op
& 0xf) == ((op
>> 4) & 0xf))
18667 return relax_immediate (fragp
, 8, 0);
18669 return relax_immediate (fragp
, 3, 0);
18673 /* Return the size of a relaxable branch instruction. BITS is the
18674 size of the offset field in the narrow instruction. */
18677 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
18683 /* Assume worst case for symbols not known to be in the same section. */
18684 if (!S_IS_DEFINED (fragp
->fr_symbol
)
18685 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
18686 || S_IS_WEAK (fragp
->fr_symbol
))
18690 if (S_IS_DEFINED (fragp
->fr_symbol
)
18691 && ARM_IS_FUNC (fragp
->fr_symbol
))
18695 val
= relaxed_symbol_addr (fragp
, stretch
);
18696 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
18699 /* Offset is a signed value *2 */
18701 if (val
>= limit
|| val
< -limit
)
18707 /* Relax a machine dependent frag. This returns the amount by which
18708 the current size of the frag should change. */
18711 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
18716 oldsize
= fragp
->fr_var
;
18717 switch (fragp
->fr_subtype
)
18719 case T_MNEM_ldr_pc2
:
18720 newsize
= relax_adr (fragp
, sec
, stretch
);
18722 case T_MNEM_ldr_pc
:
18723 case T_MNEM_ldr_sp
:
18724 case T_MNEM_str_sp
:
18725 newsize
= relax_immediate (fragp
, 8, 2);
18729 newsize
= relax_immediate (fragp
, 5, 2);
18733 newsize
= relax_immediate (fragp
, 5, 1);
18737 newsize
= relax_immediate (fragp
, 5, 0);
18740 newsize
= relax_adr (fragp
, sec
, stretch
);
18746 newsize
= relax_immediate (fragp
, 8, 0);
18749 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
18752 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
18754 case T_MNEM_add_sp
:
18755 case T_MNEM_add_pc
:
18756 newsize
= relax_immediate (fragp
, 8, 2);
18758 case T_MNEM_inc_sp
:
18759 case T_MNEM_dec_sp
:
18760 newsize
= relax_immediate (fragp
, 7, 2);
18766 newsize
= relax_addsub (fragp
, sec
);
18772 fragp
->fr_var
= newsize
;
18773 /* Freeze wide instructions that are at or before the same location as
18774 in the previous pass. This avoids infinite loops.
18775 Don't freeze them unconditionally because targets may be artificially
18776 misaligned by the expansion of preceding frags. */
18777 if (stretch
<= 0 && newsize
> 2)
18779 md_convert_frag (sec
->owner
, sec
, fragp
);
18783 return newsize
- oldsize
;
18786 /* Round up a section size to the appropriate boundary. */
18789 md_section_align (segT segment ATTRIBUTE_UNUSED
,
18792 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
18793 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
18795 /* For a.out, force the section size to be aligned. If we don't do
18796 this, BFD will align it for us, but it will not write out the
18797 final bytes of the section. This may be a bug in BFD, but it is
18798 easier to fix it here since that is how the other a.out targets
18802 align
= bfd_get_section_alignment (stdoutput
, segment
);
18803 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
18810 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
18811 of an rs_align_code fragment. */
18814 arm_handle_align (fragS
* fragP
)
18816 static char const arm_noop
[2][2][4] =
18819 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
18820 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
18823 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
18824 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
18827 static char const thumb_noop
[2][2][2] =
18830 {0xc0, 0x46}, /* LE */
18831 {0x46, 0xc0}, /* BE */
18834 {0x00, 0xbf}, /* LE */
18835 {0xbf, 0x00} /* BE */
18838 static char const wide_thumb_noop
[2][4] =
18839 { /* Wide Thumb-2 */
18840 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
18841 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
18844 unsigned bytes
, fix
, noop_size
;
18847 const char *narrow_noop
= NULL
;
18852 if (fragP
->fr_type
!= rs_align_code
)
18855 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
18856 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
18859 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18860 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
18862 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
18864 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
18866 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
18868 narrow_noop
= thumb_noop
[1][target_big_endian
];
18869 noop
= wide_thumb_noop
[target_big_endian
];
18872 noop
= thumb_noop
[0][target_big_endian
];
18880 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
18881 [target_big_endian
];
18888 fragP
->fr_var
= noop_size
;
18890 if (bytes
& (noop_size
- 1))
18892 fix
= bytes
& (noop_size
- 1);
18894 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
18896 memset (p
, 0, fix
);
18903 if (bytes
& noop_size
)
18905 /* Insert a narrow noop. */
18906 memcpy (p
, narrow_noop
, noop_size
);
18908 bytes
-= noop_size
;
18912 /* Use wide noops for the remainder */
18916 while (bytes
>= noop_size
)
18918 memcpy (p
, noop
, noop_size
);
18920 bytes
-= noop_size
;
18924 fragP
->fr_fix
+= fix
;
18927 /* Called from md_do_align. Used to create an alignment
18928 frag in a code section. */
18931 arm_frag_align_code (int n
, int max
)
18935 /* We assume that there will never be a requirement
18936 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
18937 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
18942 _("alignments greater than %d bytes not supported in .text sections."),
18943 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
18944 as_fatal ("%s", err_msg
);
18947 p
= frag_var (rs_align_code
,
18948 MAX_MEM_FOR_RS_ALIGN_CODE
,
18950 (relax_substateT
) max
,
18957 /* Perform target specific initialisation of a frag.
18958 Note - despite the name this initialisation is not done when the frag
18959 is created, but only when its type is assigned. A frag can be created
18960 and used a long time before its type is set, so beware of assuming that
18961 this initialisationis performed first. */
18965 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
18967 /* Record whether this frag is in an ARM or a THUMB area. */
18968 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18971 #else /* OBJ_ELF is defined. */
18973 arm_init_frag (fragS
* fragP
, int max_chars
)
18975 /* If the current ARM vs THUMB mode has not already
18976 been recorded into this frag then do so now. */
18977 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
18979 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
18981 /* Record a mapping symbol for alignment frags. We will delete this
18982 later if the alignment ends up empty. */
18983 switch (fragP
->fr_type
)
18986 case rs_align_test
:
18988 mapping_state_2 (MAP_DATA
, max_chars
);
18990 case rs_align_code
:
18991 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
18999 /* When we change sections we need to issue a new mapping symbol. */
19002 arm_elf_change_section (void)
19004 /* Link an unlinked unwind index table section to the .text section. */
19005 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19006 && elf_linked_to_section (now_seg
) == NULL
)
19007 elf_linked_to_section (now_seg
) = text_section
;
19011 arm_elf_section_type (const char * str
, size_t len
)
19013 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19014 return SHT_ARM_EXIDX
;
19019 /* Code to deal with unwinding tables. */
19021 static void add_unwind_adjustsp (offsetT
);
19023 /* Generate any deferred unwind frame offset. */
19026 flush_pending_unwind (void)
19030 offset
= unwind
.pending_offset
;
19031 unwind
.pending_offset
= 0;
19033 add_unwind_adjustsp (offset
);
19036 /* Add an opcode to this list for this function. Two-byte opcodes should
19037 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19041 add_unwind_opcode (valueT op
, int length
)
19043 /* Add any deferred stack adjustment. */
19044 if (unwind
.pending_offset
)
19045 flush_pending_unwind ();
19047 unwind
.sp_restored
= 0;
19049 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19051 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19052 if (unwind
.opcodes
)
19053 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19054 unwind
.opcode_alloc
);
19056 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19061 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19063 unwind
.opcode_count
++;
19067 /* Add unwind opcodes to adjust the stack pointer. */
19070 add_unwind_adjustsp (offsetT offset
)
19074 if (offset
> 0x200)
19076 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19081 /* Long form: 0xb2, uleb128. */
19082 /* This might not fit in a word so add the individual bytes,
19083 remembering the list is built in reverse order. */
19084 o
= (valueT
) ((offset
- 0x204) >> 2);
19086 add_unwind_opcode (0, 1);
19088 /* Calculate the uleb128 encoding of the offset. */
19092 bytes
[n
] = o
& 0x7f;
19098 /* Add the insn. */
19100 add_unwind_opcode (bytes
[n
- 1], 1);
19101 add_unwind_opcode (0xb2, 1);
19103 else if (offset
> 0x100)
19105 /* Two short opcodes. */
19106 add_unwind_opcode (0x3f, 1);
19107 op
= (offset
- 0x104) >> 2;
19108 add_unwind_opcode (op
, 1);
19110 else if (offset
> 0)
19112 /* Short opcode. */
19113 op
= (offset
- 4) >> 2;
19114 add_unwind_opcode (op
, 1);
19116 else if (offset
< 0)
19119 while (offset
> 0x100)
19121 add_unwind_opcode (0x7f, 1);
19124 op
= ((offset
- 4) >> 2) | 0x40;
19125 add_unwind_opcode (op
, 1);
19129 /* Finish the list of unwind opcodes for this function. */
19131 finish_unwind_opcodes (void)
19135 if (unwind
.fp_used
)
19137 /* Adjust sp as necessary. */
19138 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19139 flush_pending_unwind ();
19141 /* After restoring sp from the frame pointer. */
19142 op
= 0x90 | unwind
.fp_reg
;
19143 add_unwind_opcode (op
, 1);
19146 flush_pending_unwind ();
19150 /* Start an exception table entry. If idx is nonzero this is an index table
19154 start_unwind_section (const segT text_seg
, int idx
)
19156 const char * text_name
;
19157 const char * prefix
;
19158 const char * prefix_once
;
19159 const char * group_name
;
19163 size_t sec_name_len
;
19170 prefix
= ELF_STRING_ARM_unwind
;
19171 prefix_once
= ELF_STRING_ARM_unwind_once
;
19172 type
= SHT_ARM_EXIDX
;
19176 prefix
= ELF_STRING_ARM_unwind_info
;
19177 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19178 type
= SHT_PROGBITS
;
19181 text_name
= segment_name (text_seg
);
19182 if (streq (text_name
, ".text"))
19185 if (strncmp (text_name
, ".gnu.linkonce.t.",
19186 strlen (".gnu.linkonce.t.")) == 0)
19188 prefix
= prefix_once
;
19189 text_name
+= strlen (".gnu.linkonce.t.");
19192 prefix_len
= strlen (prefix
);
19193 text_len
= strlen (text_name
);
19194 sec_name_len
= prefix_len
+ text_len
;
19195 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19196 memcpy (sec_name
, prefix
, prefix_len
);
19197 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19198 sec_name
[prefix_len
+ text_len
] = '\0';
19204 /* Handle COMDAT group. */
19205 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19207 group_name
= elf_group_name (text_seg
);
19208 if (group_name
== NULL
)
19210 as_bad (_("Group section `%s' has no group signature"),
19211 segment_name (text_seg
));
19212 ignore_rest_of_line ();
19215 flags
|= SHF_GROUP
;
19219 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19221 /* Set the section link for index tables. */
19223 elf_linked_to_section (now_seg
) = text_seg
;
19227 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19228 personality routine data. Returns zero, or the index table value for
19229 and inline entry. */
19232 create_unwind_entry (int have_data
)
19237 /* The current word of data. */
19239 /* The number of bytes left in this word. */
19242 finish_unwind_opcodes ();
19244 /* Remember the current text section. */
19245 unwind
.saved_seg
= now_seg
;
19246 unwind
.saved_subseg
= now_subseg
;
19248 start_unwind_section (now_seg
, 0);
19250 if (unwind
.personality_routine
== NULL
)
19252 if (unwind
.personality_index
== -2)
19255 as_bad (_("handlerdata in cantunwind frame"));
19256 return 1; /* EXIDX_CANTUNWIND. */
19259 /* Use a default personality routine if none is specified. */
19260 if (unwind
.personality_index
== -1)
19262 if (unwind
.opcode_count
> 3)
19263 unwind
.personality_index
= 1;
19265 unwind
.personality_index
= 0;
19268 /* Space for the personality routine entry. */
19269 if (unwind
.personality_index
== 0)
19271 if (unwind
.opcode_count
> 3)
19272 as_bad (_("too many unwind opcodes for personality routine 0"));
19276 /* All the data is inline in the index table. */
19279 while (unwind
.opcode_count
> 0)
19281 unwind
.opcode_count
--;
19282 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19286 /* Pad with "finish" opcodes. */
19288 data
= (data
<< 8) | 0xb0;
19295 /* We get two opcodes "free" in the first word. */
19296 size
= unwind
.opcode_count
- 2;
19299 /* An extra byte is required for the opcode count. */
19300 size
= unwind
.opcode_count
+ 1;
19302 size
= (size
+ 3) >> 2;
19304 as_bad (_("too many unwind opcodes"));
19306 frag_align (2, 0, 0);
19307 record_alignment (now_seg
, 2);
19308 unwind
.table_entry
= expr_build_dot ();
19310 /* Allocate the table entry. */
19311 ptr
= frag_more ((size
<< 2) + 4);
19312 where
= frag_now_fix () - ((size
<< 2) + 4);
19314 switch (unwind
.personality_index
)
19317 /* ??? Should this be a PLT generating relocation? */
19318 /* Custom personality routine. */
19319 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19320 BFD_RELOC_ARM_PREL31
);
19325 /* Set the first byte to the number of additional words. */
19330 /* ABI defined personality routines. */
19332 /* Three opcodes bytes are packed into the first word. */
19339 /* The size and first two opcode bytes go in the first word. */
19340 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19345 /* Should never happen. */
19349 /* Pack the opcodes into words (MSB first), reversing the list at the same
19351 while (unwind
.opcode_count
> 0)
19355 md_number_to_chars (ptr
, data
, 4);
19360 unwind
.opcode_count
--;
19362 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19365 /* Finish off the last word. */
19368 /* Pad with "finish" opcodes. */
19370 data
= (data
<< 8) | 0xb0;
19372 md_number_to_chars (ptr
, data
, 4);
19377 /* Add an empty descriptor if there is no user-specified data. */
19378 ptr
= frag_more (4);
19379 md_number_to_chars (ptr
, 0, 4);
19386 /* Initialize the DWARF-2 unwind information for this procedure. */
19389 tc_arm_frame_initial_instructions (void)
19391 cfi_add_CFA_def_cfa (REG_SP
, 0);
19393 #endif /* OBJ_ELF */
19395 /* Convert REGNAME to a DWARF-2 register number. */
19398 tc_arm_regname_to_dw2regnum (char *regname
)
19400 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19410 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19414 exp
.X_op
= O_secrel
;
19415 exp
.X_add_symbol
= symbol
;
19416 exp
.X_add_number
= 0;
19417 emit_expr (&exp
, size
);
19421 /* MD interface: Symbol and relocation handling. */
19423 /* Return the address within the segment that a PC-relative fixup is
19424 relative to. For ARM, PC-relative fixups applied to instructions
19425 are generally relative to the location of the fixup plus 8 bytes.
19426 Thumb branches are offset by 4, and Thumb loads relative to PC
19427 require special handling. */
19430 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19432 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19434 /* If this is pc-relative and we are going to emit a relocation
19435 then we just want to put out any pipeline compensation that the linker
19436 will need. Otherwise we want to use the calculated base.
19437 For WinCE we skip the bias for externals as well, since this
19438 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19440 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19441 || (arm_force_relocation (fixP
)
19443 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19449 switch (fixP
->fx_r_type
)
19451 /* PC relative addressing on the Thumb is slightly odd as the
19452 bottom two bits of the PC are forced to zero for the
19453 calculation. This happens *after* application of the
19454 pipeline offset. However, Thumb adrl already adjusts for
19455 this, so we need not do it again. */
19456 case BFD_RELOC_ARM_THUMB_ADD
:
19459 case BFD_RELOC_ARM_THUMB_OFFSET
:
19460 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
19461 case BFD_RELOC_ARM_T32_ADD_PC12
:
19462 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19463 return (base
+ 4) & ~3;
19465 /* Thumb branches are simply offset by +4. */
19466 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19467 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19468 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19469 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19470 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19473 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19475 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19476 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19477 && ARM_IS_FUNC (fixP
->fx_addsy
)
19478 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19479 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19482 /* BLX is like branches above, but forces the low two bits of PC to
19484 case BFD_RELOC_THUMB_PCREL_BLX
:
19486 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19487 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19488 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19489 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19490 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19491 return (base
+ 4) & ~3;
19493 /* ARM mode branches are offset by +8. However, the Windows CE
19494 loader expects the relocation not to take this into account. */
19495 case BFD_RELOC_ARM_PCREL_BLX
:
19497 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19498 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19499 && ARM_IS_FUNC (fixP
->fx_addsy
)
19500 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19501 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19504 case BFD_RELOC_ARM_PCREL_CALL
:
19506 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19507 && (!S_IS_EXTERNAL (fixP
->fx_addsy
))
19508 && THUMB_IS_FUNC (fixP
->fx_addsy
)
19509 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
19510 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19513 case BFD_RELOC_ARM_PCREL_BRANCH
:
19514 case BFD_RELOC_ARM_PCREL_JUMP
:
19515 case BFD_RELOC_ARM_PLT32
:
19517 /* When handling fixups immediately, because we have already
19518 discovered the value of a symbol, or the address of the frag involved
19519 we must account for the offset by +8, as the OS loader will never see the reloc.
19520 see fixup_segment() in write.c
19521 The S_IS_EXTERNAL test handles the case of global symbols.
19522 Those need the calculated base, not just the pipe compensation the linker will need. */
19524 && fixP
->fx_addsy
!= NULL
19525 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
19526 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
19534 /* ARM mode loads relative to PC are also offset by +8. Unlike
19535 branches, the Windows CE loader *does* expect the relocation
19536 to take this into account. */
19537 case BFD_RELOC_ARM_OFFSET_IMM
:
19538 case BFD_RELOC_ARM_OFFSET_IMM8
:
19539 case BFD_RELOC_ARM_HWLITERAL
:
19540 case BFD_RELOC_ARM_LITERAL
:
19541 case BFD_RELOC_ARM_CP_OFF_IMM
:
19545 /* Other PC-relative relocations are un-offset. */
19551 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
19552 Otherwise we have no need to default values of symbols. */
19555 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
19558 if (name
[0] == '_' && name
[1] == 'G'
19559 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
19563 if (symbol_find (name
))
19564 as_bad (_("GOT already in the symbol table"));
19566 GOT_symbol
= symbol_new (name
, undefined_section
,
19567 (valueT
) 0, & zero_address_frag
);
19577 /* Subroutine of md_apply_fix. Check to see if an immediate can be
19578 computed as two separate immediate values, added together. We
19579 already know that this value cannot be computed by just one ARM
19582 static unsigned int
19583 validate_immediate_twopart (unsigned int val
,
19584 unsigned int * highpart
)
19589 for (i
= 0; i
< 32; i
+= 2)
19590 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
19596 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
19598 else if (a
& 0xff0000)
19600 if (a
& 0xff000000)
19602 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
19606 gas_assert (a
& 0xff000000);
19607 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
19610 return (a
& 0xff) | (i
<< 7);
19617 validate_offset_imm (unsigned int val
, int hwse
)
19619 if ((hwse
&& val
> 255) || val
> 4095)
19624 /* Subroutine of md_apply_fix. Do those data_ops which can take a
19625 negative immediate constant by altering the instruction. A bit of
19630 by inverting the second operand, and
19633 by negating the second operand. */
19636 negate_data_op (unsigned long * instruction
,
19637 unsigned long value
)
19640 unsigned long negated
, inverted
;
19642 negated
= encode_arm_immediate (-value
);
19643 inverted
= encode_arm_immediate (~value
);
19645 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
19648 /* First negates. */
19649 case OPCODE_SUB
: /* ADD <-> SUB */
19650 new_inst
= OPCODE_ADD
;
19655 new_inst
= OPCODE_SUB
;
19659 case OPCODE_CMP
: /* CMP <-> CMN */
19660 new_inst
= OPCODE_CMN
;
19665 new_inst
= OPCODE_CMP
;
19669 /* Now Inverted ops. */
19670 case OPCODE_MOV
: /* MOV <-> MVN */
19671 new_inst
= OPCODE_MVN
;
19676 new_inst
= OPCODE_MOV
;
19680 case OPCODE_AND
: /* AND <-> BIC */
19681 new_inst
= OPCODE_BIC
;
19686 new_inst
= OPCODE_AND
;
19690 case OPCODE_ADC
: /* ADC <-> SBC */
19691 new_inst
= OPCODE_SBC
;
19696 new_inst
= OPCODE_ADC
;
19700 /* We cannot do anything. */
19705 if (value
== (unsigned) FAIL
)
19708 *instruction
&= OPCODE_MASK
;
19709 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
19713 /* Like negate_data_op, but for Thumb-2. */
19715 static unsigned int
19716 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
19720 unsigned int negated
, inverted
;
19722 negated
= encode_thumb32_immediate (-value
);
19723 inverted
= encode_thumb32_immediate (~value
);
19725 rd
= (*instruction
>> 8) & 0xf;
19726 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
19729 /* ADD <-> SUB. Includes CMP <-> CMN. */
19730 case T2_OPCODE_SUB
:
19731 new_inst
= T2_OPCODE_ADD
;
19735 case T2_OPCODE_ADD
:
19736 new_inst
= T2_OPCODE_SUB
;
19740 /* ORR <-> ORN. Includes MOV <-> MVN. */
19741 case T2_OPCODE_ORR
:
19742 new_inst
= T2_OPCODE_ORN
;
19746 case T2_OPCODE_ORN
:
19747 new_inst
= T2_OPCODE_ORR
;
19751 /* AND <-> BIC. TST has no inverted equivalent. */
19752 case T2_OPCODE_AND
:
19753 new_inst
= T2_OPCODE_BIC
;
19760 case T2_OPCODE_BIC
:
19761 new_inst
= T2_OPCODE_AND
;
19766 case T2_OPCODE_ADC
:
19767 new_inst
= T2_OPCODE_SBC
;
19771 case T2_OPCODE_SBC
:
19772 new_inst
= T2_OPCODE_ADC
;
19776 /* We cannot do anything. */
19781 if (value
== (unsigned int)FAIL
)
19784 *instruction
&= T2_OPCODE_MASK
;
19785 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
19789 /* Read a 32-bit thumb instruction from buf. */
19790 static unsigned long
19791 get_thumb32_insn (char * buf
)
19793 unsigned long insn
;
19794 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
19795 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19801 /* We usually want to set the low bit on the address of thumb function
19802 symbols. In particular .word foo - . should have the low bit set.
19803 Generic code tries to fold the difference of two symbols to
19804 a constant. Prevent this and force a relocation when the first symbols
19805 is a thumb function. */
19808 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
19810 if (op
== O_subtract
19811 && l
->X_op
== O_symbol
19812 && r
->X_op
== O_symbol
19813 && THUMB_IS_FUNC (l
->X_add_symbol
))
19815 l
->X_op
= O_subtract
;
19816 l
->X_op_symbol
= r
->X_add_symbol
;
19817 l
->X_add_number
-= r
->X_add_number
;
19821 /* Process as normal. */
19825 /* Encode Thumb2 unconditional branches and calls. The encoding
19826 for the 2 are identical for the immediate values. */
19829 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
19831 #define T2I1I2MASK ((1 << 13) | (1 << 11))
19834 addressT S
, I1
, I2
, lo
, hi
;
19836 S
= (value
>> 24) & 0x01;
19837 I1
= (value
>> 23) & 0x01;
19838 I2
= (value
>> 22) & 0x01;
19839 hi
= (value
>> 12) & 0x3ff;
19840 lo
= (value
>> 1) & 0x7ff;
19841 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19842 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19843 newval
|= (S
<< 10) | hi
;
19844 newval2
&= ~T2I1I2MASK
;
19845 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
19846 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19847 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19851 md_apply_fix (fixS
* fixP
,
19855 offsetT value
= * valP
;
19857 unsigned int newimm
;
19858 unsigned long temp
;
19860 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
19862 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
19864 /* Note whether this will delete the relocation. */
19866 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
19869 /* On a 64-bit host, silently truncate 'value' to 32 bits for
19870 consistency with the behaviour on 32-bit hosts. Remember value
19872 value
&= 0xffffffff;
19873 value
^= 0x80000000;
19874 value
-= 0x80000000;
19877 fixP
->fx_addnumber
= value
;
19879 /* Same treatment for fixP->fx_offset. */
19880 fixP
->fx_offset
&= 0xffffffff;
19881 fixP
->fx_offset
^= 0x80000000;
19882 fixP
->fx_offset
-= 0x80000000;
19884 switch (fixP
->fx_r_type
)
19886 case BFD_RELOC_NONE
:
19887 /* This will need to go in the object file. */
19891 case BFD_RELOC_ARM_IMMEDIATE
:
19892 /* We claim that this fixup has been processed here,
19893 even if in fact we generate an error because we do
19894 not have a reloc for it, so tc_gen_reloc will reject it. */
19897 if (fixP
->fx_addsy
)
19899 const char *msg
= 0;
19901 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19902 msg
= _("undefined symbol %s used as an immediate value");
19903 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19904 msg
= _("symbol %s is in a different section");
19905 else if (S_IS_WEAK (fixP
->fx_addsy
))
19906 msg
= _("symbol %s is weak and may be overridden later");
19910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19911 msg
, S_GET_NAME (fixP
->fx_addsy
));
19916 newimm
= encode_arm_immediate (value
);
19917 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19919 /* If the instruction will fail, see if we can fix things up by
19920 changing the opcode. */
19921 if (newimm
== (unsigned int) FAIL
19922 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
19924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19925 _("invalid constant (%lx) after fixup"),
19926 (unsigned long) value
);
19930 newimm
|= (temp
& 0xfffff000);
19931 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19934 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19936 unsigned int highpart
= 0;
19937 unsigned int newinsn
= 0xe1a00000; /* nop. */
19939 if (fixP
->fx_addsy
)
19941 const char *msg
= 0;
19943 if (! S_IS_DEFINED (fixP
->fx_addsy
))
19944 msg
= _("undefined symbol %s used as an immediate value");
19945 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19946 msg
= _("symbol %s is in a different section");
19947 else if (S_IS_WEAK (fixP
->fx_addsy
))
19948 msg
= _("symbol %s is weak and may be overridden later");
19952 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19953 msg
, S_GET_NAME (fixP
->fx_addsy
));
19958 newimm
= encode_arm_immediate (value
);
19959 temp
= md_chars_to_number (buf
, INSN_SIZE
);
19961 /* If the instruction will fail, see if we can fix things up by
19962 changing the opcode. */
19963 if (newimm
== (unsigned int) FAIL
19964 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
19966 /* No ? OK - try using two ADD instructions to generate
19968 newimm
= validate_immediate_twopart (value
, & highpart
);
19970 /* Yes - then make sure that the second instruction is
19972 if (newimm
!= (unsigned int) FAIL
)
19974 /* Still No ? Try using a negated value. */
19975 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
19976 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
19977 /* Otherwise - give up. */
19980 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19981 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
19986 /* Replace the first operand in the 2nd instruction (which
19987 is the PC) with the destination register. We have
19988 already added in the PC in the first instruction and we
19989 do not want to do it again. */
19990 newinsn
&= ~ 0xf0000;
19991 newinsn
|= ((newinsn
& 0x0f000) << 4);
19994 newimm
|= (temp
& 0xfffff000);
19995 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
19997 highpart
|= (newinsn
& 0xfffff000);
19998 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20002 case BFD_RELOC_ARM_OFFSET_IMM
:
20003 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20006 case BFD_RELOC_ARM_LITERAL
:
20012 if (validate_offset_imm (value
, 0) == FAIL
)
20014 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20016 _("invalid literal constant: pool needs to be closer"));
20018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20019 _("bad immediate value for offset (%ld)"),
20024 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20025 newval
&= 0xff7ff000;
20026 newval
|= value
| (sign
? INDEX_UP
: 0);
20027 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20030 case BFD_RELOC_ARM_OFFSET_IMM8
:
20031 case BFD_RELOC_ARM_HWLITERAL
:
20037 if (validate_offset_imm (value
, 1) == FAIL
)
20039 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20040 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20041 _("invalid literal constant: pool needs to be closer"));
20043 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20048 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20049 newval
&= 0xff7ff0f0;
20050 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20051 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20054 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20055 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20056 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20057 _("bad immediate value for offset (%ld)"), (long) value
);
20060 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20062 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20065 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20066 /* This is a complicated relocation used for all varieties of Thumb32
20067 load/store instruction with immediate offset:
20069 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20070 *4, optional writeback(W)
20071 (doubleword load/store)
20073 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20074 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20075 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20076 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20077 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20079 Uppercase letters indicate bits that are already encoded at
20080 this point. Lowercase letters are our problem. For the
20081 second block of instructions, the secondary opcode nybble
20082 (bits 8..11) is present, and bit 23 is zero, even if this is
20083 a PC-relative operation. */
20084 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20086 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20088 if ((newval
& 0xf0000000) == 0xe0000000)
20090 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20092 newval
|= (1 << 23);
20095 if (value
% 4 != 0)
20097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20098 _("offset not a multiple of 4"));
20104 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20105 _("offset out of range"));
20110 else if ((newval
& 0x000f0000) == 0x000f0000)
20112 /* PC-relative, 12-bit offset. */
20114 newval
|= (1 << 23);
20119 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20120 _("offset out of range"));
20125 else if ((newval
& 0x00000100) == 0x00000100)
20127 /* Writeback: 8-bit, +/- offset. */
20129 newval
|= (1 << 9);
20134 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20135 _("offset out of range"));
20140 else if ((newval
& 0x00000f00) == 0x00000e00)
20142 /* T-instruction: positive 8-bit offset. */
20143 if (value
< 0 || value
> 0xff)
20145 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20146 _("offset out of range"));
20154 /* Positive 12-bit or negative 8-bit offset. */
20158 newval
|= (1 << 23);
20168 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20169 _("offset out of range"));
20176 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20177 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20180 case BFD_RELOC_ARM_SHIFT_IMM
:
20181 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20182 if (((unsigned long) value
) > 32
20184 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20186 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20187 _("shift expression is too large"));
20192 /* Shifts of zero must be done as lsl. */
20194 else if (value
== 32)
20196 newval
&= 0xfffff07f;
20197 newval
|= (value
& 0x1f) << 7;
20198 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20201 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20202 case BFD_RELOC_ARM_T32_ADD_IMM
:
20203 case BFD_RELOC_ARM_T32_IMM12
:
20204 case BFD_RELOC_ARM_T32_ADD_PC12
:
20205 /* We claim that this fixup has been processed here,
20206 even if in fact we generate an error because we do
20207 not have a reloc for it, so tc_gen_reloc will reject it. */
20211 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20213 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20214 _("undefined symbol %s used as an immediate value"),
20215 S_GET_NAME (fixP
->fx_addsy
));
20219 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20221 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20224 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20225 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20227 newimm
= encode_thumb32_immediate (value
);
20228 if (newimm
== (unsigned int) FAIL
)
20229 newimm
= thumb32_negate_data_op (&newval
, value
);
20231 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20232 && newimm
== (unsigned int) FAIL
)
20234 /* Turn add/sum into addw/subw. */
20235 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20236 newval
= (newval
& 0xfeffffff) | 0x02000000;
20238 /* 12 bit immediate for addw/subw. */
20242 newval
^= 0x00a00000;
20245 newimm
= (unsigned int) FAIL
;
20250 if (newimm
== (unsigned int)FAIL
)
20252 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20253 _("invalid constant (%lx) after fixup"),
20254 (unsigned long) value
);
20258 newval
|= (newimm
& 0x800) << 15;
20259 newval
|= (newimm
& 0x700) << 4;
20260 newval
|= (newimm
& 0x0ff);
20262 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20263 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20266 case BFD_RELOC_ARM_SMC
:
20267 if (((unsigned long) value
) > 0xffff)
20268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20269 _("invalid smc expression"));
20270 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20271 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20272 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20275 case BFD_RELOC_ARM_SWI
:
20276 if (fixP
->tc_fix_data
!= 0)
20278 if (((unsigned long) value
) > 0xff)
20279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20280 _("invalid swi expression"));
20281 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20283 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20287 if (((unsigned long) value
) > 0x00ffffff)
20288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20289 _("invalid swi expression"));
20290 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20292 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20296 case BFD_RELOC_ARM_MULTI
:
20297 if (((unsigned long) value
) > 0xffff)
20298 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20299 _("invalid expression in load/store multiple"));
20300 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20301 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20305 case BFD_RELOC_ARM_PCREL_CALL
:
20307 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20309 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20310 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20311 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20312 /* Flip the bl to blx. This is a simple flip
20313 bit here because we generate PCREL_CALL for
20314 unconditional bls. */
20316 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20317 newval
= newval
| 0x10000000;
20318 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20324 goto arm_branch_common
;
20326 case BFD_RELOC_ARM_PCREL_JUMP
:
20327 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20329 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20330 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20331 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20333 /* This would map to a bl<cond>, b<cond>,
20334 b<always> to a Thumb function. We
20335 need to force a relocation for this particular
20337 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20341 case BFD_RELOC_ARM_PLT32
:
20343 case BFD_RELOC_ARM_PCREL_BRANCH
:
20345 goto arm_branch_common
;
20347 case BFD_RELOC_ARM_PCREL_BLX
:
20350 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20352 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20353 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20354 && ARM_IS_FUNC (fixP
->fx_addsy
))
20356 /* Flip the blx to a bl and warn. */
20357 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20358 newval
= 0xeb000000;
20359 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20360 _("blx to '%s' an ARM ISA state function changed to bl"),
20362 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20368 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20369 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20373 /* We are going to store value (shifted right by two) in the
20374 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20375 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20376 also be be clear. */
20378 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20379 _("misaligned branch destination"));
20380 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20381 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20382 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20383 _("branch out of range"));
20385 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20387 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20388 newval
|= (value
>> 2) & 0x00ffffff;
20389 /* Set the H bit on BLX instructions. */
20393 newval
|= 0x01000000;
20395 newval
&= ~0x01000000;
20397 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20401 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20402 /* CBZ can only branch forward. */
20404 /* Attempts to use CBZ to branch to the next instruction
20405 (which, strictly speaking, are prohibited) will be turned into
20408 FIXME: It may be better to remove the instruction completely and
20409 perform relaxation. */
20412 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20413 newval
= 0xbf00; /* NOP encoding T1 */
20414 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20420 _("branch out of range"));
20422 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20424 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20425 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20426 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20431 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20432 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20433 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20434 _("branch out of range"));
20436 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20438 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20439 newval
|= (value
& 0x1ff) >> 1;
20440 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20444 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
20445 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
20446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20447 _("branch out of range"));
20449 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20451 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20452 newval
|= (value
& 0xfff) >> 1;
20453 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20457 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20459 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20460 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20461 && S_IS_DEFINED (fixP
->fx_addsy
)
20462 && ARM_IS_FUNC (fixP
->fx_addsy
)
20463 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20465 /* Force a relocation for a branch 20 bits wide. */
20468 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
20469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20470 _("conditional branch out of range"));
20472 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20475 addressT S
, J1
, J2
, lo
, hi
;
20477 S
= (value
& 0x00100000) >> 20;
20478 J2
= (value
& 0x00080000) >> 19;
20479 J1
= (value
& 0x00040000) >> 18;
20480 hi
= (value
& 0x0003f000) >> 12;
20481 lo
= (value
& 0x00000ffe) >> 1;
20483 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20484 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20485 newval
|= (S
<< 10) | hi
;
20486 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
20487 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20488 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20492 case BFD_RELOC_THUMB_PCREL_BLX
:
20494 /* If there is a blx from a thumb state function to
20495 another thumb function flip this to a bl and warn
20499 && S_IS_DEFINED (fixP
->fx_addsy
)
20500 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20501 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20502 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20504 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20505 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20506 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
20508 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20509 newval
= newval
| 0x1000;
20510 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20511 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20516 goto thumb_bl_common
;
20518 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20520 /* A bl from Thumb state ISA to an internal ARM state function
20521 is converted to a blx. */
20523 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20524 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
20525 && S_IS_DEFINED (fixP
->fx_addsy
)
20526 && ARM_IS_FUNC (fixP
->fx_addsy
)
20527 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20529 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20530 newval
= newval
& ~0x1000;
20531 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
20532 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
20539 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
20540 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20541 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
20544 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
20545 /* For a BLX instruction, make sure that the relocation is rounded up
20546 to a word boundary. This follows the semantics of the instruction
20547 which specifies that bit 1 of the target address will come from bit
20548 1 of the base address. */
20549 value
= (value
+ 1) & ~ 1;
20552 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
20554 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
20556 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20557 _("branch out of range"));
20559 else if ((value
& ~0x1ffffff)
20560 && ((value
& ~0x1ffffff) != ~0x1ffffff))
20562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20563 _("Thumb2 branch out of range"));
20567 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20568 encode_thumb2_b_bl_offset (buf
, value
);
20572 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20573 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
20574 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20575 _("branch out of range"));
20577 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20578 encode_thumb2_b_bl_offset (buf
, value
);
20583 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20584 md_number_to_chars (buf
, value
, 1);
20588 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20589 md_number_to_chars (buf
, value
, 2);
20593 case BFD_RELOC_ARM_TLS_GD32
:
20594 case BFD_RELOC_ARM_TLS_LE32
:
20595 case BFD_RELOC_ARM_TLS_IE32
:
20596 case BFD_RELOC_ARM_TLS_LDM32
:
20597 case BFD_RELOC_ARM_TLS_LDO32
:
20598 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
20601 case BFD_RELOC_ARM_GOT32
:
20602 case BFD_RELOC_ARM_GOTOFF
:
20603 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20604 md_number_to_chars (buf
, 0, 4);
20607 case BFD_RELOC_ARM_GOT_PREL
:
20608 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20609 md_number_to_chars (buf
, value
, 4);
20612 case BFD_RELOC_ARM_TARGET2
:
20613 /* TARGET2 is not partial-inplace, so we need to write the
20614 addend here for REL targets, because it won't be written out
20615 during reloc processing later. */
20616 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20617 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
20621 case BFD_RELOC_RVA
:
20623 case BFD_RELOC_ARM_TARGET1
:
20624 case BFD_RELOC_ARM_ROSEGREL32
:
20625 case BFD_RELOC_ARM_SBREL32
:
20626 case BFD_RELOC_32_PCREL
:
20628 case BFD_RELOC_32_SECREL
:
20630 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20632 /* For WinCE we only do this for pcrel fixups. */
20633 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
20635 md_number_to_chars (buf
, value
, 4);
20639 case BFD_RELOC_ARM_PREL31
:
20640 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20642 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
20643 if ((value
^ (value
>> 1)) & 0x40000000)
20645 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20646 _("rel31 relocation overflow"));
20648 newval
|= value
& 0x7fffffff;
20649 md_number_to_chars (buf
, newval
, 4);
20654 case BFD_RELOC_ARM_CP_OFF_IMM
:
20655 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20656 if (value
< -1023 || value
> 1023 || (value
& 3))
20657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20658 _("co-processor offset out of range"));
20663 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20664 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20665 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20667 newval
= get_thumb32_insn (buf
);
20668 newval
&= 0xff7fff00;
20669 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
20670 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
20671 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
20672 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20674 put_thumb32_insn (buf
, newval
);
20677 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
20678 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
20679 if (value
< -255 || value
> 255)
20680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20681 _("co-processor offset out of range"));
20683 goto cp_off_common
;
20685 case BFD_RELOC_ARM_THUMB_OFFSET
:
20686 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20687 /* Exactly what ranges, and where the offset is inserted depends
20688 on the type of instruction, we can establish this from the
20690 switch (newval
>> 12)
20692 case 4: /* PC load. */
20693 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
20694 forced to zero for these loads; md_pcrel_from has already
20695 compensated for this. */
20697 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20698 _("invalid offset, target not word aligned (0x%08lX)"),
20699 (((unsigned long) fixP
->fx_frag
->fr_address
20700 + (unsigned long) fixP
->fx_where
) & ~3)
20701 + (unsigned long) value
);
20703 if (value
& ~0x3fc)
20704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20705 _("invalid offset, value too big (0x%08lX)"),
20708 newval
|= value
>> 2;
20711 case 9: /* SP load/store. */
20712 if (value
& ~0x3fc)
20713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20714 _("invalid offset, value too big (0x%08lX)"),
20716 newval
|= value
>> 2;
20719 case 6: /* Word load/store. */
20721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20722 _("invalid offset, value too big (0x%08lX)"),
20724 newval
|= value
<< 4; /* 6 - 2. */
20727 case 7: /* Byte load/store. */
20729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20730 _("invalid offset, value too big (0x%08lX)"),
20732 newval
|= value
<< 6;
20735 case 8: /* Halfword load/store. */
20737 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20738 _("invalid offset, value too big (0x%08lX)"),
20740 newval
|= value
<< 5; /* 6 - 1. */
20744 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20745 "Unable to process relocation for thumb opcode: %lx",
20746 (unsigned long) newval
);
20749 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20752 case BFD_RELOC_ARM_THUMB_ADD
:
20753 /* This is a complicated relocation, since we use it for all of
20754 the following immediate relocations:
20758 9bit ADD/SUB SP word-aligned
20759 10bit ADD PC/SP word-aligned
20761 The type of instruction being processed is encoded in the
20768 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20770 int rd
= (newval
>> 4) & 0xf;
20771 int rs
= newval
& 0xf;
20772 int subtract
= !!(newval
& 0x8000);
20774 /* Check for HI regs, only very restricted cases allowed:
20775 Adjusting SP, and using PC or SP to get an address. */
20776 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
20777 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
20778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20779 _("invalid Hi register with immediate"));
20781 /* If value is negative, choose the opposite instruction. */
20785 subtract
= !subtract
;
20787 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20788 _("immediate value out of range"));
20793 if (value
& ~0x1fc)
20794 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20795 _("invalid immediate for stack address calculation"));
20796 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
20797 newval
|= value
>> 2;
20799 else if (rs
== REG_PC
|| rs
== REG_SP
)
20801 if (subtract
|| value
& ~0x3fc)
20802 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20803 _("invalid immediate for address calculation (value = 0x%08lX)"),
20804 (unsigned long) value
);
20805 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
20807 newval
|= value
>> 2;
20812 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20813 _("immediate value out of range"));
20814 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
20815 newval
|= (rd
<< 8) | value
;
20820 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20821 _("immediate value out of range"));
20822 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
20823 newval
|= rd
| (rs
<< 3) | (value
<< 6);
20826 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20829 case BFD_RELOC_ARM_THUMB_IMM
:
20830 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20831 if (value
< 0 || value
> 255)
20832 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20833 _("invalid immediate: %ld is out of range"),
20836 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20839 case BFD_RELOC_ARM_THUMB_SHIFT
:
20840 /* 5bit shift value (0..32). LSL cannot take 32. */
20841 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
20842 temp
= newval
& 0xf800;
20843 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
20844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20845 _("invalid shift value: %ld"), (long) value
);
20846 /* Shifts of zero must be encoded as LSL. */
20848 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
20849 /* Shifts of 32 are encoded as zero. */
20850 else if (value
== 32)
20852 newval
|= value
<< 6;
20853 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20856 case BFD_RELOC_VTABLE_INHERIT
:
20857 case BFD_RELOC_VTABLE_ENTRY
:
20861 case BFD_RELOC_ARM_MOVW
:
20862 case BFD_RELOC_ARM_MOVT
:
20863 case BFD_RELOC_ARM_THUMB_MOVW
:
20864 case BFD_RELOC_ARM_THUMB_MOVT
:
20865 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20867 /* REL format relocations are limited to a 16-bit addend. */
20868 if (!fixP
->fx_done
)
20870 if (value
< -0x8000 || value
> 0x7fff)
20871 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20872 _("offset out of range"));
20874 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
20875 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20880 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20881 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
20883 newval
= get_thumb32_insn (buf
);
20884 newval
&= 0xfbf08f00;
20885 newval
|= (value
& 0xf000) << 4;
20886 newval
|= (value
& 0x0800) << 15;
20887 newval
|= (value
& 0x0700) << 4;
20888 newval
|= (value
& 0x00ff);
20889 put_thumb32_insn (buf
, newval
);
20893 newval
= md_chars_to_number (buf
, 4);
20894 newval
&= 0xfff0f000;
20895 newval
|= value
& 0x0fff;
20896 newval
|= (value
& 0xf000) << 4;
20897 md_number_to_chars (buf
, newval
, 4);
20902 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
20903 case BFD_RELOC_ARM_ALU_PC_G0
:
20904 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
20905 case BFD_RELOC_ARM_ALU_PC_G1
:
20906 case BFD_RELOC_ARM_ALU_PC_G2
:
20907 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
20908 case BFD_RELOC_ARM_ALU_SB_G0
:
20909 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
20910 case BFD_RELOC_ARM_ALU_SB_G1
:
20911 case BFD_RELOC_ARM_ALU_SB_G2
:
20912 gas_assert (!fixP
->fx_done
);
20913 if (!seg
->use_rela_p
)
20916 bfd_vma encoded_addend
;
20917 bfd_vma addend_abs
= abs (value
);
20919 /* Check that the absolute value of the addend can be
20920 expressed as an 8-bit constant plus a rotation. */
20921 encoded_addend
= encode_arm_immediate (addend_abs
);
20922 if (encoded_addend
== (unsigned int) FAIL
)
20923 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20924 _("the offset 0x%08lX is not representable"),
20925 (unsigned long) addend_abs
);
20927 /* Extract the instruction. */
20928 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20930 /* If the addend is positive, use an ADD instruction.
20931 Otherwise use a SUB. Take care not to destroy the S bit. */
20932 insn
&= 0xff1fffff;
20938 /* Place the encoded addend into the first 12 bits of the
20940 insn
&= 0xfffff000;
20941 insn
|= encoded_addend
;
20943 /* Update the instruction. */
20944 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20948 case BFD_RELOC_ARM_LDR_PC_G0
:
20949 case BFD_RELOC_ARM_LDR_PC_G1
:
20950 case BFD_RELOC_ARM_LDR_PC_G2
:
20951 case BFD_RELOC_ARM_LDR_SB_G0
:
20952 case BFD_RELOC_ARM_LDR_SB_G1
:
20953 case BFD_RELOC_ARM_LDR_SB_G2
:
20954 gas_assert (!fixP
->fx_done
);
20955 if (!seg
->use_rela_p
)
20958 bfd_vma addend_abs
= abs (value
);
20960 /* Check that the absolute value of the addend can be
20961 encoded in 12 bits. */
20962 if (addend_abs
>= 0x1000)
20963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20964 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
20965 (unsigned long) addend_abs
);
20967 /* Extract the instruction. */
20968 insn
= md_chars_to_number (buf
, INSN_SIZE
);
20970 /* If the addend is negative, clear bit 23 of the instruction.
20971 Otherwise set it. */
20973 insn
&= ~(1 << 23);
20977 /* Place the absolute value of the addend into the first 12 bits
20978 of the instruction. */
20979 insn
&= 0xfffff000;
20980 insn
|= addend_abs
;
20982 /* Update the instruction. */
20983 md_number_to_chars (buf
, insn
, INSN_SIZE
);
20987 case BFD_RELOC_ARM_LDRS_PC_G0
:
20988 case BFD_RELOC_ARM_LDRS_PC_G1
:
20989 case BFD_RELOC_ARM_LDRS_PC_G2
:
20990 case BFD_RELOC_ARM_LDRS_SB_G0
:
20991 case BFD_RELOC_ARM_LDRS_SB_G1
:
20992 case BFD_RELOC_ARM_LDRS_SB_G2
:
20993 gas_assert (!fixP
->fx_done
);
20994 if (!seg
->use_rela_p
)
20997 bfd_vma addend_abs
= abs (value
);
20999 /* Check that the absolute value of the addend can be
21000 encoded in 8 bits. */
21001 if (addend_abs
>= 0x100)
21002 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21003 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21004 (unsigned long) addend_abs
);
21006 /* Extract the instruction. */
21007 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21009 /* If the addend is negative, clear bit 23 of the instruction.
21010 Otherwise set it. */
21012 insn
&= ~(1 << 23);
21016 /* Place the first four bits of the absolute value of the addend
21017 into the first 4 bits of the instruction, and the remaining
21018 four into bits 8 .. 11. */
21019 insn
&= 0xfffff0f0;
21020 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21022 /* Update the instruction. */
21023 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21027 case BFD_RELOC_ARM_LDC_PC_G0
:
21028 case BFD_RELOC_ARM_LDC_PC_G1
:
21029 case BFD_RELOC_ARM_LDC_PC_G2
:
21030 case BFD_RELOC_ARM_LDC_SB_G0
:
21031 case BFD_RELOC_ARM_LDC_SB_G1
:
21032 case BFD_RELOC_ARM_LDC_SB_G2
:
21033 gas_assert (!fixP
->fx_done
);
21034 if (!seg
->use_rela_p
)
21037 bfd_vma addend_abs
= abs (value
);
21039 /* Check that the absolute value of the addend is a multiple of
21040 four and, when divided by four, fits in 8 bits. */
21041 if (addend_abs
& 0x3)
21042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21043 _("bad offset 0x%08lX (must be word-aligned)"),
21044 (unsigned long) addend_abs
);
21046 if ((addend_abs
>> 2) > 0xff)
21047 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21048 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21049 (unsigned long) addend_abs
);
21051 /* Extract the instruction. */
21052 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21054 /* If the addend is negative, clear bit 23 of the instruction.
21055 Otherwise set it. */
21057 insn
&= ~(1 << 23);
21061 /* Place the addend (divided by four) into the first eight
21062 bits of the instruction. */
21063 insn
&= 0xfffffff0;
21064 insn
|= addend_abs
>> 2;
21066 /* Update the instruction. */
21067 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21071 case BFD_RELOC_ARM_V4BX
:
21072 /* This will need to go in the object file. */
21076 case BFD_RELOC_UNUSED
:
21078 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21079 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21083 /* Translate internal representation of relocation info to BFD target
21087 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21090 bfd_reloc_code_real_type code
;
21092 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21094 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21095 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21096 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21098 if (fixp
->fx_pcrel
)
21100 if (section
->use_rela_p
)
21101 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21103 fixp
->fx_offset
= reloc
->address
;
21105 reloc
->addend
= fixp
->fx_offset
;
21107 switch (fixp
->fx_r_type
)
21110 if (fixp
->fx_pcrel
)
21112 code
= BFD_RELOC_8_PCREL
;
21117 if (fixp
->fx_pcrel
)
21119 code
= BFD_RELOC_16_PCREL
;
21124 if (fixp
->fx_pcrel
)
21126 code
= BFD_RELOC_32_PCREL
;
21130 case BFD_RELOC_ARM_MOVW
:
21131 if (fixp
->fx_pcrel
)
21133 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21137 case BFD_RELOC_ARM_MOVT
:
21138 if (fixp
->fx_pcrel
)
21140 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21144 case BFD_RELOC_ARM_THUMB_MOVW
:
21145 if (fixp
->fx_pcrel
)
21147 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21151 case BFD_RELOC_ARM_THUMB_MOVT
:
21152 if (fixp
->fx_pcrel
)
21154 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21158 case BFD_RELOC_NONE
:
21159 case BFD_RELOC_ARM_PCREL_BRANCH
:
21160 case BFD_RELOC_ARM_PCREL_BLX
:
21161 case BFD_RELOC_RVA
:
21162 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21163 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21164 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21165 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21166 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21167 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21168 case BFD_RELOC_VTABLE_ENTRY
:
21169 case BFD_RELOC_VTABLE_INHERIT
:
21171 case BFD_RELOC_32_SECREL
:
21173 code
= fixp
->fx_r_type
;
21176 case BFD_RELOC_THUMB_PCREL_BLX
:
21178 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21179 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21182 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21185 case BFD_RELOC_ARM_LITERAL
:
21186 case BFD_RELOC_ARM_HWLITERAL
:
21187 /* If this is called then the a literal has
21188 been referenced across a section boundary. */
21189 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21190 _("literal referenced across section boundary"));
21194 case BFD_RELOC_ARM_GOT32
:
21195 case BFD_RELOC_ARM_GOTOFF
:
21196 case BFD_RELOC_ARM_GOT_PREL
:
21197 case BFD_RELOC_ARM_PLT32
:
21198 case BFD_RELOC_ARM_TARGET1
:
21199 case BFD_RELOC_ARM_ROSEGREL32
:
21200 case BFD_RELOC_ARM_SBREL32
:
21201 case BFD_RELOC_ARM_PREL31
:
21202 case BFD_RELOC_ARM_TARGET2
:
21203 case BFD_RELOC_ARM_TLS_LE32
:
21204 case BFD_RELOC_ARM_TLS_LDO32
:
21205 case BFD_RELOC_ARM_PCREL_CALL
:
21206 case BFD_RELOC_ARM_PCREL_JUMP
:
21207 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21208 case BFD_RELOC_ARM_ALU_PC_G0
:
21209 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21210 case BFD_RELOC_ARM_ALU_PC_G1
:
21211 case BFD_RELOC_ARM_ALU_PC_G2
:
21212 case BFD_RELOC_ARM_LDR_PC_G0
:
21213 case BFD_RELOC_ARM_LDR_PC_G1
:
21214 case BFD_RELOC_ARM_LDR_PC_G2
:
21215 case BFD_RELOC_ARM_LDRS_PC_G0
:
21216 case BFD_RELOC_ARM_LDRS_PC_G1
:
21217 case BFD_RELOC_ARM_LDRS_PC_G2
:
21218 case BFD_RELOC_ARM_LDC_PC_G0
:
21219 case BFD_RELOC_ARM_LDC_PC_G1
:
21220 case BFD_RELOC_ARM_LDC_PC_G2
:
21221 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21222 case BFD_RELOC_ARM_ALU_SB_G0
:
21223 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21224 case BFD_RELOC_ARM_ALU_SB_G1
:
21225 case BFD_RELOC_ARM_ALU_SB_G2
:
21226 case BFD_RELOC_ARM_LDR_SB_G0
:
21227 case BFD_RELOC_ARM_LDR_SB_G1
:
21228 case BFD_RELOC_ARM_LDR_SB_G2
:
21229 case BFD_RELOC_ARM_LDRS_SB_G0
:
21230 case BFD_RELOC_ARM_LDRS_SB_G1
:
21231 case BFD_RELOC_ARM_LDRS_SB_G2
:
21232 case BFD_RELOC_ARM_LDC_SB_G0
:
21233 case BFD_RELOC_ARM_LDC_SB_G1
:
21234 case BFD_RELOC_ARM_LDC_SB_G2
:
21235 case BFD_RELOC_ARM_V4BX
:
21236 code
= fixp
->fx_r_type
;
21239 case BFD_RELOC_ARM_TLS_GD32
:
21240 case BFD_RELOC_ARM_TLS_IE32
:
21241 case BFD_RELOC_ARM_TLS_LDM32
:
21242 /* BFD will include the symbol's address in the addend.
21243 But we don't want that, so subtract it out again here. */
21244 if (!S_IS_COMMON (fixp
->fx_addsy
))
21245 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21246 code
= fixp
->fx_r_type
;
21250 case BFD_RELOC_ARM_IMMEDIATE
:
21251 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21252 _("internal relocation (type: IMMEDIATE) not fixed up"));
21255 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21256 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21257 _("ADRL used for a symbol not defined in the same file"));
21260 case BFD_RELOC_ARM_OFFSET_IMM
:
21261 if (section
->use_rela_p
)
21263 code
= fixp
->fx_r_type
;
21267 if (fixp
->fx_addsy
!= NULL
21268 && !S_IS_DEFINED (fixp
->fx_addsy
)
21269 && S_IS_LOCAL (fixp
->fx_addsy
))
21271 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21272 _("undefined local label `%s'"),
21273 S_GET_NAME (fixp
->fx_addsy
));
21277 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21278 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21285 switch (fixp
->fx_r_type
)
21287 case BFD_RELOC_NONE
: type
= "NONE"; break;
21288 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21289 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21290 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21291 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21292 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21293 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21294 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21295 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21296 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21297 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21298 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21299 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21300 default: type
= _("<unknown>"); break;
21302 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21303 _("cannot represent %s relocation in this object file format"),
21310 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21312 && fixp
->fx_addsy
== GOT_symbol
)
21314 code
= BFD_RELOC_ARM_GOTPC
;
21315 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21319 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21321 if (reloc
->howto
== NULL
)
21323 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21324 _("cannot represent %s relocation in this object file format"),
21325 bfd_get_reloc_code_name (code
));
21329 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21330 vtable entry to be used in the relocation's section offset. */
21331 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21332 reloc
->address
= fixp
->fx_offset
;
21337 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21340 cons_fix_new_arm (fragS
* frag
,
21345 bfd_reloc_code_real_type type
;
21349 FIXME: @@ Should look at CPU word size. */
21353 type
= BFD_RELOC_8
;
21356 type
= BFD_RELOC_16
;
21360 type
= BFD_RELOC_32
;
21363 type
= BFD_RELOC_64
;
21368 if (exp
->X_op
== O_secrel
)
21370 exp
->X_op
= O_symbol
;
21371 type
= BFD_RELOC_32_SECREL
;
21375 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21378 #if defined (OBJ_COFF)
21380 arm_validate_fix (fixS
* fixP
)
21382 /* If the destination of the branch is a defined symbol which does not have
21383 the THUMB_FUNC attribute, then we must be calling a function which has
21384 the (interfacearm) attribute. We look for the Thumb entry point to that
21385 function and change the branch to refer to that function instead. */
21386 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21387 && fixP
->fx_addsy
!= NULL
21388 && S_IS_DEFINED (fixP
->fx_addsy
)
21389 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21391 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21398 arm_force_relocation (struct fix
* fixp
)
21400 #if defined (OBJ_COFF) && defined (TE_PE)
21401 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21405 /* In case we have a call or a branch to a function in ARM ISA mode from
21406 a thumb function or vice-versa force the relocation. These relocations
21407 are cleared off for some cores that might have blx and simple transformations
21411 switch (fixp
->fx_r_type
)
21413 case BFD_RELOC_ARM_PCREL_JUMP
:
21414 case BFD_RELOC_ARM_PCREL_CALL
:
21415 case BFD_RELOC_THUMB_PCREL_BLX
:
21416 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
21420 case BFD_RELOC_ARM_PCREL_BLX
:
21421 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21422 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21423 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21424 if (ARM_IS_FUNC (fixp
->fx_addsy
))
21433 /* Resolve these relocations even if the symbol is extern or weak. */
21434 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
21435 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
21436 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
21437 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
21438 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
21439 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
21440 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
21443 /* Always leave these relocations for the linker. */
21444 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21445 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21446 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21449 /* Always generate relocations against function symbols. */
21450 if (fixp
->fx_r_type
== BFD_RELOC_32
21452 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
21455 return generic_force_reloc (fixp
);
21458 #if defined (OBJ_ELF) || defined (OBJ_COFF)
21459 /* Relocations against function names must be left unadjusted,
21460 so that the linker can use this information to generate interworking
21461 stubs. The MIPS version of this function
21462 also prevents relocations that are mips-16 specific, but I do not
21463 know why it does this.
21466 There is one other problem that ought to be addressed here, but
21467 which currently is not: Taking the address of a label (rather
21468 than a function) and then later jumping to that address. Such
21469 addresses also ought to have their bottom bit set (assuming that
21470 they reside in Thumb code), but at the moment they will not. */
21473 arm_fix_adjustable (fixS
* fixP
)
21475 if (fixP
->fx_addsy
== NULL
)
21478 /* Preserve relocations against symbols with function type. */
21479 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
21482 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
21483 && fixP
->fx_subsy
== NULL
)
21486 /* We need the symbol name for the VTABLE entries. */
21487 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
21488 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21491 /* Don't allow symbols to be discarded on GOT related relocs. */
21492 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
21493 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
21494 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
21495 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
21496 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
21497 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
21498 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
21499 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
21500 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
21503 /* Similarly for group relocations. */
21504 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
21505 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
21506 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
21509 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
21510 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
21511 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21512 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
21513 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
21514 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21515 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
21516 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
21517 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
21522 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
21527 elf32_arm_target_format (void)
21530 return (target_big_endian
21531 ? "elf32-bigarm-symbian"
21532 : "elf32-littlearm-symbian");
21533 #elif defined (TE_VXWORKS)
21534 return (target_big_endian
21535 ? "elf32-bigarm-vxworks"
21536 : "elf32-littlearm-vxworks");
21538 if (target_big_endian
)
21539 return "elf32-bigarm";
21541 return "elf32-littlearm";
21546 armelf_frob_symbol (symbolS
* symp
,
21549 elf_frob_symbol (symp
, puntp
);
21553 /* MD interface: Finalization. */
21558 literal_pool
* pool
;
21560 /* Ensure that all the IT blocks are properly closed. */
21561 check_it_blocks_finished ();
21563 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
21565 /* Put it at the end of the relevant section. */
21566 subseg_set (pool
->section
, pool
->sub_section
);
21568 arm_elf_change_section ();
21575 /* Remove any excess mapping symbols generated for alignment frags in
21576 SEC. We may have created a mapping symbol before a zero byte
21577 alignment; remove it if there's a mapping symbol after the
21580 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
21581 void *dummy ATTRIBUTE_UNUSED
)
21583 segment_info_type
*seginfo
= seg_info (sec
);
21586 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
21589 for (fragp
= seginfo
->frchainP
->frch_root
;
21591 fragp
= fragp
->fr_next
)
21593 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
21594 fragS
*next
= fragp
->fr_next
;
21596 /* Variable-sized frags have been converted to fixed size by
21597 this point. But if this was variable-sized to start with,
21598 there will be a fixed-size frag after it. So don't handle
21600 if (sym
== NULL
|| next
== NULL
)
21603 if (S_GET_VALUE (sym
) < next
->fr_address
)
21604 /* Not at the end of this frag. */
21606 know (S_GET_VALUE (sym
) == next
->fr_address
);
21610 if (next
->tc_frag_data
.first_map
!= NULL
)
21612 /* Next frag starts with a mapping symbol. Discard this
21614 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21618 if (next
->fr_next
== NULL
)
21620 /* This mapping symbol is at the end of the section. Discard
21622 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
21623 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
21627 /* As long as we have empty frags without any mapping symbols,
21629 /* If the next frag is non-empty and does not start with a
21630 mapping symbol, then this mapping symbol is required. */
21631 if (next
->fr_address
!= next
->fr_next
->fr_address
)
21634 next
= next
->fr_next
;
21636 while (next
!= NULL
);
21641 /* Adjust the symbol table. This marks Thumb symbols as distinct from
21645 arm_adjust_symtab (void)
21650 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21652 if (ARM_IS_THUMB (sym
))
21654 if (THUMB_IS_FUNC (sym
))
21656 /* Mark the symbol as a Thumb function. */
21657 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
21658 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
21659 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
21661 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
21662 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
21664 as_bad (_("%s: unexpected function type: %d"),
21665 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
21667 else switch (S_GET_STORAGE_CLASS (sym
))
21670 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
21673 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
21676 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
21684 if (ARM_IS_INTERWORK (sym
))
21685 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
21692 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
21694 if (ARM_IS_THUMB (sym
))
21696 elf_symbol_type
* elf_sym
;
21698 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
21699 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
21701 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
21702 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
21704 /* If it's a .thumb_func, declare it as so,
21705 otherwise tag label as .code 16. */
21706 if (THUMB_IS_FUNC (sym
))
21707 elf_sym
->internal_elf_sym
.st_info
=
21708 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
21709 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21710 elf_sym
->internal_elf_sym
.st_info
=
21711 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
21716 /* Remove any overlapping mapping symbols generated by alignment frags. */
21717 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
21721 /* MD interface: Initialization. */
21724 set_constant_flonums (void)
21728 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
21729 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
21733 /* Auto-select Thumb mode if it's the only available instruction set for the
21734 given architecture. */
21737 autoselect_thumb_from_cpu_variant (void)
21739 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
21740 opcode_select (16);
21749 if ( (arm_ops_hsh
= hash_new ()) == NULL
21750 || (arm_cond_hsh
= hash_new ()) == NULL
21751 || (arm_shift_hsh
= hash_new ()) == NULL
21752 || (arm_psr_hsh
= hash_new ()) == NULL
21753 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
21754 || (arm_reg_hsh
= hash_new ()) == NULL
21755 || (arm_reloc_hsh
= hash_new ()) == NULL
21756 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
21757 as_fatal (_("virtual memory exhausted"));
21759 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
21760 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
21761 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
21762 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
21763 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
21764 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
21765 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
21766 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
21767 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
21768 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
21769 (void *) (v7m_psrs
+ i
));
21770 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
21771 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
21773 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
21775 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
21776 (void *) (barrier_opt_names
+ i
));
21778 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
21779 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
21782 set_constant_flonums ();
21784 /* Set the cpu variant based on the command-line options. We prefer
21785 -mcpu= over -march= if both are set (as for GCC); and we prefer
21786 -mfpu= over any other way of setting the floating point unit.
21787 Use of legacy options with new options are faulted. */
21790 if (mcpu_cpu_opt
|| march_cpu_opt
)
21791 as_bad (_("use of old and new-style options to set CPU type"));
21793 mcpu_cpu_opt
= legacy_cpu
;
21795 else if (!mcpu_cpu_opt
)
21796 mcpu_cpu_opt
= march_cpu_opt
;
21801 as_bad (_("use of old and new-style options to set FPU type"));
21803 mfpu_opt
= legacy_fpu
;
21805 else if (!mfpu_opt
)
21807 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
21808 || defined (TE_NetBSD) || defined (TE_VXWORKS))
21809 /* Some environments specify a default FPU. If they don't, infer it
21810 from the processor. */
21812 mfpu_opt
= mcpu_fpu_opt
;
21814 mfpu_opt
= march_fpu_opt
;
21816 mfpu_opt
= &fpu_default
;
21822 if (mcpu_cpu_opt
!= NULL
)
21823 mfpu_opt
= &fpu_default
;
21824 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
21825 mfpu_opt
= &fpu_arch_vfp_v2
;
21827 mfpu_opt
= &fpu_arch_fpa
;
21833 mcpu_cpu_opt
= &cpu_default
;
21834 selected_cpu
= cpu_default
;
21838 selected_cpu
= *mcpu_cpu_opt
;
21840 mcpu_cpu_opt
= &arm_arch_any
;
21843 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21845 autoselect_thumb_from_cpu_variant ();
21847 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
21849 #if defined OBJ_COFF || defined OBJ_ELF
21851 unsigned int flags
= 0;
21853 #if defined OBJ_ELF
21854 flags
= meabi_flags
;
21856 switch (meabi_flags
)
21858 case EF_ARM_EABI_UNKNOWN
:
21860 /* Set the flags in the private structure. */
21861 if (uses_apcs_26
) flags
|= F_APCS26
;
21862 if (support_interwork
) flags
|= F_INTERWORK
;
21863 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
21864 if (pic_code
) flags
|= F_PIC
;
21865 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
21866 flags
|= F_SOFT_FLOAT
;
21868 switch (mfloat_abi_opt
)
21870 case ARM_FLOAT_ABI_SOFT
:
21871 case ARM_FLOAT_ABI_SOFTFP
:
21872 flags
|= F_SOFT_FLOAT
;
21875 case ARM_FLOAT_ABI_HARD
:
21876 if (flags
& F_SOFT_FLOAT
)
21877 as_bad (_("hard-float conflicts with specified fpu"));
21881 /* Using pure-endian doubles (even if soft-float). */
21882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
21883 flags
|= F_VFP_FLOAT
;
21885 #if defined OBJ_ELF
21886 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
21887 flags
|= EF_ARM_MAVERICK_FLOAT
;
21890 case EF_ARM_EABI_VER4
:
21891 case EF_ARM_EABI_VER5
:
21892 /* No additional flags to set. */
21899 bfd_set_private_flags (stdoutput
, flags
);
21901 /* We have run out flags in the COFF header to encode the
21902 status of ATPCS support, so instead we create a dummy,
21903 empty, debug section called .arm.atpcs. */
21908 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
21912 bfd_set_section_flags
21913 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
21914 bfd_set_section_size (stdoutput
, sec
, 0);
21915 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
21921 /* Record the CPU type as well. */
21922 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
21923 mach
= bfd_mach_arm_iWMMXt2
;
21924 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
21925 mach
= bfd_mach_arm_iWMMXt
;
21926 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
21927 mach
= bfd_mach_arm_XScale
;
21928 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
21929 mach
= bfd_mach_arm_ep9312
;
21930 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
21931 mach
= bfd_mach_arm_5TE
;
21932 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
21934 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21935 mach
= bfd_mach_arm_5T
;
21937 mach
= bfd_mach_arm_5
;
21939 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
21941 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
21942 mach
= bfd_mach_arm_4T
;
21944 mach
= bfd_mach_arm_4
;
21946 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
21947 mach
= bfd_mach_arm_3M
;
21948 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
21949 mach
= bfd_mach_arm_3
;
21950 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
21951 mach
= bfd_mach_arm_2a
;
21952 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
21953 mach
= bfd_mach_arm_2
;
21955 mach
= bfd_mach_arm_unknown
;
21957 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
21960 /* Command line processing. */
21963 Invocation line includes a switch not recognized by the base assembler.
21964 See if it's a processor-specific option.
21966 This routine is somewhat complicated by the need for backwards
21967 compatibility (since older releases of gcc can't be changed).
21968 The new options try to make the interface as compatible as
21971 New options (supported) are:
21973 -mcpu=<cpu name> Assemble for selected processor
21974 -march=<architecture name> Assemble for selected architecture
21975 -mfpu=<fpu architecture> Assemble for selected FPU.
21976 -EB/-mbig-endian Big-endian
21977 -EL/-mlittle-endian Little-endian
21978 -k Generate PIC code
21979 -mthumb Start in Thumb mode
21980 -mthumb-interwork Code supports ARM/Thumb interworking
21982 -m[no-]warn-deprecated Warn about deprecated features
21984 For now we will also provide support for:
21986 -mapcs-32 32-bit Program counter
21987 -mapcs-26 26-bit Program counter
21988 -macps-float Floats passed in FP registers
21989 -mapcs-reentrant Reentrant code
21991 (sometime these will probably be replaced with -mapcs=<list of options>
21992 and -matpcs=<list of options>)
21994 The remaining options are only supported for back-wards compatibility.
21995 Cpu variants, the arm part is optional:
21996 -m[arm]1 Currently not supported.
21997 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
21998 -m[arm]3 Arm 3 processor
21999 -m[arm]6[xx], Arm 6 processors
22000 -m[arm]7[xx][t][[d]m] Arm 7 processors
22001 -m[arm]8[10] Arm 8 processors
22002 -m[arm]9[20][tdmi] Arm 9 processors
22003 -mstrongarm[110[0]] StrongARM processors
22004 -mxscale XScale processors
22005 -m[arm]v[2345[t[e]]] Arm architectures
22006 -mall All (except the ARM1)
22008 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22009 -mfpe-old (No float load/store multiples)
22010 -mvfpxd VFP Single precision
22012 -mno-fpu Disable all floating point instructions
22014 The following CPU names are recognized:
22015 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22016 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22017 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22018 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22019 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22020 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22021 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22025 const char * md_shortopts
= "m:k";
22027 #ifdef ARM_BI_ENDIAN
22028 #define OPTION_EB (OPTION_MD_BASE + 0)
22029 #define OPTION_EL (OPTION_MD_BASE + 1)
22031 #if TARGET_BYTES_BIG_ENDIAN
22032 #define OPTION_EB (OPTION_MD_BASE + 0)
22034 #define OPTION_EL (OPTION_MD_BASE + 1)
22037 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22039 struct option md_longopts
[] =
22042 {"EB", no_argument
, NULL
, OPTION_EB
},
22045 {"EL", no_argument
, NULL
, OPTION_EL
},
22047 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22048 {NULL
, no_argument
, NULL
, 0}
22051 size_t md_longopts_size
= sizeof (md_longopts
);
22053 struct arm_option_table
22055 char *option
; /* Option name to match. */
22056 char *help
; /* Help information. */
22057 int *var
; /* Variable to change. */
22058 int value
; /* What to change it to. */
22059 char *deprecated
; /* If non-null, print this message. */
22062 struct arm_option_table arm_opts
[] =
22064 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22065 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22066 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22067 &support_interwork
, 1, NULL
},
22068 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22069 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22070 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22072 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22073 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22074 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22075 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22078 /* These are recognized by the assembler, but have no affect on code. */
22079 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22080 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22082 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22083 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22084 &warn_on_deprecated
, 0, NULL
},
22085 {NULL
, NULL
, NULL
, 0, NULL
}
22088 struct arm_legacy_option_table
22090 char *option
; /* Option name to match. */
22091 const arm_feature_set
**var
; /* Variable to change. */
22092 const arm_feature_set value
; /* What to change it to. */
22093 char *deprecated
; /* If non-null, print this message. */
22096 const struct arm_legacy_option_table arm_legacy_opts
[] =
22098 /* DON'T add any new processors to this list -- we want the whole list
22099 to go away... Add them to the processors table instead. */
22100 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22101 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22102 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22103 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22104 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22105 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22106 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22107 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22108 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22109 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22110 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22111 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22112 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22113 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22114 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22115 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22116 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22117 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22118 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22119 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22120 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22121 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22122 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22123 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22124 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22125 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22126 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22127 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22128 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22129 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22130 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22131 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22132 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22133 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22134 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22135 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22136 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22137 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22138 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22139 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22140 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22141 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22142 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22143 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22144 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22145 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22146 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22147 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22148 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22149 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22150 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22151 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22152 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22153 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22154 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22155 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22156 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22157 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22158 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22159 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22160 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22161 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22162 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22163 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22164 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22165 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22166 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22167 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22168 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22169 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22170 N_("use -mcpu=strongarm110")},
22171 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22172 N_("use -mcpu=strongarm1100")},
22173 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22174 N_("use -mcpu=strongarm1110")},
22175 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22176 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22177 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22179 /* Architecture variants -- don't add any more to this list either. */
22180 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22181 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22182 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22183 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22184 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22185 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22186 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22187 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22188 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22189 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22190 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22191 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22192 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22193 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22194 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22195 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22196 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22197 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22199 /* Floating point variants -- don't add any more to this list either. */
22200 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22201 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22202 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22203 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22204 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22206 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22209 struct arm_cpu_option_table
22212 const arm_feature_set value
;
22213 /* For some CPUs we assume an FPU unless the user explicitly sets
22215 const arm_feature_set default_fpu
;
22216 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22218 const char *canonical_name
;
22221 /* This list should, at a minimum, contain all the cpu names
22222 recognized by GCC. */
22223 static const struct arm_cpu_option_table arm_cpus
[] =
22225 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22226 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22227 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22228 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22229 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22230 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22231 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22232 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22233 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22234 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22235 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22236 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22237 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22238 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22239 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22240 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22241 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22242 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22243 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22244 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22245 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22246 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22247 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22248 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22249 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22250 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22251 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22252 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22253 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22254 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22255 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22256 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22257 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22258 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22259 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22260 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22261 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22262 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22263 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22264 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22265 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22266 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22267 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22268 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22269 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22270 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22271 /* For V5 or later processors we default to using VFP; but the user
22272 should really set the FPU type explicitly. */
22273 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22274 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22275 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22276 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22277 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22278 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22279 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22280 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22281 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22282 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22283 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22284 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22285 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22286 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22287 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22288 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22289 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22290 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22291 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22292 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22293 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22294 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
22295 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22296 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22297 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22298 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22299 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22300 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
22301 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
22302 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22303 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22304 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22305 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22306 {"cortex-a5", ARM_ARCH_V7A
, FPU_NONE
, NULL
},
22307 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22308 | FPU_NEON_EXT_V1
),
22310 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE (0, FPU_VFP_V3
22311 | FPU_NEON_EXT_V1
),
22313 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
22314 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
, NULL
},
22315 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, NULL
},
22316 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
22317 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22318 {"cortex-m0", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
22319 /* ??? XSCALE is really an architecture. */
22320 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22321 /* ??? iwmmxt is not a processor. */
22322 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22323 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22324 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22326 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22327 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22330 struct arm_arch_option_table
22333 const arm_feature_set value
;
22334 const arm_feature_set default_fpu
;
22337 /* This list should, at a minimum, contain all the architecture names
22338 recognized by GCC. */
22339 static const struct arm_arch_option_table arm_archs
[] =
22341 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22342 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22343 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22344 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22345 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22346 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22347 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22348 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22349 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22350 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22351 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22352 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22353 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22354 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22355 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22356 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22357 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22358 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22359 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22360 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22361 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22362 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22363 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22364 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22365 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22366 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22367 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22368 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22369 /* The official spelling of the ARMv7 profile variants is the dashed form.
22370 Accept the non-dashed form for compatibility with old toolchains. */
22371 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22372 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22373 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22374 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22375 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22376 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22377 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22378 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22379 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22380 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22381 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22384 /* ISA extensions in the co-processor space. */
22385 struct arm_option_cpu_value_table
22388 const arm_feature_set value
;
22391 static const struct arm_option_cpu_value_table arm_extensions
[] =
22393 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
22394 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
22395 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
22396 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
22397 {NULL
, ARM_ARCH_NONE
}
22400 /* This list should, at a minimum, contain all the fpu names
22401 recognized by GCC. */
22402 static const struct arm_option_cpu_value_table arm_fpus
[] =
22404 {"softfpa", FPU_NONE
},
22405 {"fpe", FPU_ARCH_FPE
},
22406 {"fpe2", FPU_ARCH_FPE
},
22407 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
22408 {"fpa", FPU_ARCH_FPA
},
22409 {"fpa10", FPU_ARCH_FPA
},
22410 {"fpa11", FPU_ARCH_FPA
},
22411 {"arm7500fe", FPU_ARCH_FPA
},
22412 {"softvfp", FPU_ARCH_VFP
},
22413 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
22414 {"vfp", FPU_ARCH_VFP_V2
},
22415 {"vfp9", FPU_ARCH_VFP_V2
},
22416 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
22417 {"vfp10", FPU_ARCH_VFP_V2
},
22418 {"vfp10-r0", FPU_ARCH_VFP_V1
},
22419 {"vfpxd", FPU_ARCH_VFP_V1xD
},
22420 {"vfpv2", FPU_ARCH_VFP_V2
},
22421 {"vfpv3", FPU_ARCH_VFP_V3
},
22422 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
22423 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
22424 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
22425 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
22426 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
22427 {"arm1020t", FPU_ARCH_VFP_V1
},
22428 {"arm1020e", FPU_ARCH_VFP_V2
},
22429 {"arm1136jfs", FPU_ARCH_VFP_V2
},
22430 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
22431 {"maverick", FPU_ARCH_MAVERICK
},
22432 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
22433 {"neon-fp16", FPU_ARCH_NEON_FP16
},
22434 {"vfpv4", FPU_ARCH_VFP_V4
},
22435 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
22436 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
22437 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
22438 {NULL
, ARM_ARCH_NONE
}
22441 struct arm_option_value_table
22447 static const struct arm_option_value_table arm_float_abis
[] =
22449 {"hard", ARM_FLOAT_ABI_HARD
},
22450 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
22451 {"soft", ARM_FLOAT_ABI_SOFT
},
22456 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
22457 static const struct arm_option_value_table arm_eabis
[] =
22459 {"gnu", EF_ARM_EABI_UNKNOWN
},
22460 {"4", EF_ARM_EABI_VER4
},
22461 {"5", EF_ARM_EABI_VER5
},
22466 struct arm_long_option_table
22468 char * option
; /* Substring to match. */
22469 char * help
; /* Help information. */
22470 int (* func
) (char * subopt
); /* Function to decode sub-option. */
22471 char * deprecated
; /* If non-null, print this message. */
22475 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
22477 arm_feature_set
*ext_set
= (arm_feature_set
*)
22478 xmalloc (sizeof (arm_feature_set
));
22480 /* Copy the feature set, so that we can modify it. */
22481 *ext_set
= **opt_p
;
22484 while (str
!= NULL
&& *str
!= 0)
22486 const struct arm_option_cpu_value_table
* opt
;
22492 as_bad (_("invalid architectural extension"));
22497 ext
= strchr (str
, '+');
22500 optlen
= ext
- str
;
22502 optlen
= strlen (str
);
22506 as_bad (_("missing architectural extension"));
22510 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
22511 if (strncmp (opt
->name
, str
, optlen
) == 0)
22513 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
22517 if (opt
->name
== NULL
)
22519 as_bad (_("unknown architectural extension `%s'"), str
);
22530 arm_parse_cpu (char * str
)
22532 const struct arm_cpu_option_table
* opt
;
22533 char * ext
= strchr (str
, '+');
22537 optlen
= ext
- str
;
22539 optlen
= strlen (str
);
22543 as_bad (_("missing cpu name `%s'"), str
);
22547 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
22548 if (strncmp (opt
->name
, str
, optlen
) == 0)
22550 mcpu_cpu_opt
= &opt
->value
;
22551 mcpu_fpu_opt
= &opt
->default_fpu
;
22552 if (opt
->canonical_name
)
22553 strcpy (selected_cpu_name
, opt
->canonical_name
);
22558 for (i
= 0; i
< optlen
; i
++)
22559 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
22560 selected_cpu_name
[i
] = 0;
22564 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
22569 as_bad (_("unknown cpu `%s'"), str
);
22574 arm_parse_arch (char * str
)
22576 const struct arm_arch_option_table
*opt
;
22577 char *ext
= strchr (str
, '+');
22581 optlen
= ext
- str
;
22583 optlen
= strlen (str
);
22587 as_bad (_("missing architecture name `%s'"), str
);
22591 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
22592 if (streq (opt
->name
, str
))
22594 march_cpu_opt
= &opt
->value
;
22595 march_fpu_opt
= &opt
->default_fpu
;
22596 strcpy (selected_cpu_name
, opt
->name
);
22599 return arm_parse_extension (ext
, &march_cpu_opt
);
22604 as_bad (_("unknown architecture `%s'\n"), str
);
22609 arm_parse_fpu (char * str
)
22611 const struct arm_option_cpu_value_table
* opt
;
22613 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
22614 if (streq (opt
->name
, str
))
22616 mfpu_opt
= &opt
->value
;
22620 as_bad (_("unknown floating point format `%s'\n"), str
);
22625 arm_parse_float_abi (char * str
)
22627 const struct arm_option_value_table
* opt
;
22629 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
22630 if (streq (opt
->name
, str
))
22632 mfloat_abi_opt
= opt
->value
;
22636 as_bad (_("unknown floating point abi `%s'\n"), str
);
22642 arm_parse_eabi (char * str
)
22644 const struct arm_option_value_table
*opt
;
22646 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
22647 if (streq (opt
->name
, str
))
22649 meabi_flags
= opt
->value
;
22652 as_bad (_("unknown EABI `%s'\n"), str
);
22658 arm_parse_it_mode (char * str
)
22660 bfd_boolean ret
= TRUE
;
22662 if (streq ("arm", str
))
22663 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
22664 else if (streq ("thumb", str
))
22665 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
22666 else if (streq ("always", str
))
22667 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
22668 else if (streq ("never", str
))
22669 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
22672 as_bad (_("unknown implicit IT mode `%s', should be "\
22673 "arm, thumb, always, or never."), str
);
22680 struct arm_long_option_table arm_long_opts
[] =
22682 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
22683 arm_parse_cpu
, NULL
},
22684 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
22685 arm_parse_arch
, NULL
},
22686 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
22687 arm_parse_fpu
, NULL
},
22688 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
22689 arm_parse_float_abi
, NULL
},
22691 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
22692 arm_parse_eabi
, NULL
},
22694 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
22695 arm_parse_it_mode
, NULL
},
22696 {NULL
, NULL
, 0, NULL
}
22700 md_parse_option (int c
, char * arg
)
22702 struct arm_option_table
*opt
;
22703 const struct arm_legacy_option_table
*fopt
;
22704 struct arm_long_option_table
*lopt
;
22710 target_big_endian
= 1;
22716 target_big_endian
= 0;
22720 case OPTION_FIX_V4BX
:
22725 /* Listing option. Just ignore these, we don't support additional
22730 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22732 if (c
== opt
->option
[0]
22733 && ((arg
== NULL
&& opt
->option
[1] == 0)
22734 || streq (arg
, opt
->option
+ 1)))
22736 /* If the option is deprecated, tell the user. */
22737 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
22738 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22739 arg
? arg
: "", _(opt
->deprecated
));
22741 if (opt
->var
!= NULL
)
22742 *opt
->var
= opt
->value
;
22748 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
22750 if (c
== fopt
->option
[0]
22751 && ((arg
== NULL
&& fopt
->option
[1] == 0)
22752 || streq (arg
, fopt
->option
+ 1)))
22754 /* If the option is deprecated, tell the user. */
22755 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
22756 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
22757 arg
? arg
: "", _(fopt
->deprecated
));
22759 if (fopt
->var
!= NULL
)
22760 *fopt
->var
= &fopt
->value
;
22766 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22768 /* These options are expected to have an argument. */
22769 if (c
== lopt
->option
[0]
22771 && strncmp (arg
, lopt
->option
+ 1,
22772 strlen (lopt
->option
+ 1)) == 0)
22774 /* If the option is deprecated, tell the user. */
22775 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
22776 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
22777 _(lopt
->deprecated
));
22779 /* Call the sup-option parser. */
22780 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
22791 md_show_usage (FILE * fp
)
22793 struct arm_option_table
*opt
;
22794 struct arm_long_option_table
*lopt
;
22796 fprintf (fp
, _(" ARM-specific assembler options:\n"));
22798 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
22799 if (opt
->help
!= NULL
)
22800 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
22802 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
22803 if (lopt
->help
!= NULL
)
22804 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
22808 -EB assemble code for a big-endian cpu\n"));
22813 -EL assemble code for a little-endian cpu\n"));
22817 --fix-v4bx Allow BX in ARMv4 code\n"));
22825 arm_feature_set flags
;
22826 } cpu_arch_ver_table
;
22828 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
22829 least features first. */
22830 static const cpu_arch_ver_table cpu_arch_ver
[] =
22836 {4, ARM_ARCH_V5TE
},
22837 {5, ARM_ARCH_V5TEJ
},
22841 {11, ARM_ARCH_V6M
},
22842 {8, ARM_ARCH_V6T2
},
22843 {10, ARM_ARCH_V7A
},
22844 {10, ARM_ARCH_V7R
},
22845 {10, ARM_ARCH_V7M
},
22849 /* Set an attribute if it has not already been set by the user. */
22851 aeabi_set_attribute_int (int tag
, int value
)
22854 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22855 || !attributes_set_explicitly
[tag
])
22856 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
22860 aeabi_set_attribute_string (int tag
, const char *value
)
22863 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
22864 || !attributes_set_explicitly
[tag
])
22865 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
22868 /* Set the public EABI object attributes. */
22870 aeabi_set_public_attributes (void)
22873 arm_feature_set flags
;
22874 arm_feature_set tmp
;
22875 const cpu_arch_ver_table
*p
;
22877 /* Choose the architecture based on the capabilities of the requested cpu
22878 (if any) and/or the instructions actually used. */
22879 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
22880 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
22881 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
22882 /*Allow the user to override the reported architecture. */
22885 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
22886 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
22891 for (p
= cpu_arch_ver
; p
->val
; p
++)
22893 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
22896 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
22900 /* The table lookup above finds the last architecture to contribute
22901 a new feature. Unfortunately, Tag13 is a subset of the union of
22902 v6T2 and v7-M, so it is never seen as contributing a new feature.
22903 We can not search for the last entry which is entirely used,
22904 because if no CPU is specified we build up only those flags
22905 actually used. Perhaps we should separate out the specified
22906 and implicit cases. Avoid taking this path for -march=all by
22907 checking for contradictory v7-A / v7-M features. */
22909 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
22910 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
22911 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
22914 /* Tag_CPU_name. */
22915 if (selected_cpu_name
[0])
22919 q
= selected_cpu_name
;
22920 if (strncmp (q
, "armv", 4) == 0)
22925 for (i
= 0; q
[i
]; i
++)
22926 q
[i
] = TOUPPER (q
[i
]);
22928 aeabi_set_attribute_string (Tag_CPU_name
, q
);
22931 /* Tag_CPU_arch. */
22932 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
22934 /* Tag_CPU_arch_profile. */
22935 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
22936 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
22937 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
22938 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
22939 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
22940 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
22942 /* Tag_ARM_ISA_use. */
22943 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
22945 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
22947 /* Tag_THUMB_ISA_use. */
22948 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
22950 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
22951 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
22953 /* Tag_VFP_arch. */
22954 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
22955 aeabi_set_attribute_int (Tag_VFP_arch
,
22956 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
22958 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
22959 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
22960 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
22961 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
22962 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
22963 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
22964 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
22965 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
22966 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
22968 /* Tag_ABI_HardFP_use. */
22969 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
22970 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
22971 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
22973 /* Tag_WMMX_arch. */
22974 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
22975 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
22976 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
22977 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
22979 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
22980 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
22981 aeabi_set_attribute_int
22982 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
22985 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
22986 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
22987 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
22990 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
22991 aeabi_set_attribute_int (Tag_DIV_use
, 0);
22992 /* Fill this in when gas supports v7a sdiv/udiv.
22993 else if (... v7a with div extension used ...)
22994 aeabi_set_attribute_int (Tag_DIV_use, 2); */
22996 aeabi_set_attribute_int (Tag_DIV_use
, 1);
22999 /* Add the default contents for the .ARM.attributes section. */
23003 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23006 aeabi_set_public_attributes ();
23008 #endif /* OBJ_ELF */
23011 /* Parse a .cpu directive. */
23014 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23016 const struct arm_cpu_option_table
*opt
;
23020 name
= input_line_pointer
;
23021 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23022 input_line_pointer
++;
23023 saved_char
= *input_line_pointer
;
23024 *input_line_pointer
= 0;
23026 /* Skip the first "all" entry. */
23027 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23028 if (streq (opt
->name
, name
))
23030 mcpu_cpu_opt
= &opt
->value
;
23031 selected_cpu
= opt
->value
;
23032 if (opt
->canonical_name
)
23033 strcpy (selected_cpu_name
, opt
->canonical_name
);
23037 for (i
= 0; opt
->name
[i
]; i
++)
23038 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23039 selected_cpu_name
[i
] = 0;
23041 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23042 *input_line_pointer
= saved_char
;
23043 demand_empty_rest_of_line ();
23046 as_bad (_("unknown cpu `%s'"), name
);
23047 *input_line_pointer
= saved_char
;
23048 ignore_rest_of_line ();
23052 /* Parse a .arch directive. */
23055 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23057 const struct arm_arch_option_table
*opt
;
23061 name
= input_line_pointer
;
23062 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23063 input_line_pointer
++;
23064 saved_char
= *input_line_pointer
;
23065 *input_line_pointer
= 0;
23067 /* Skip the first "all" entry. */
23068 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23069 if (streq (opt
->name
, name
))
23071 mcpu_cpu_opt
= &opt
->value
;
23072 selected_cpu
= opt
->value
;
23073 strcpy (selected_cpu_name
, opt
->name
);
23074 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23075 *input_line_pointer
= saved_char
;
23076 demand_empty_rest_of_line ();
23080 as_bad (_("unknown architecture `%s'\n"), name
);
23081 *input_line_pointer
= saved_char
;
23082 ignore_rest_of_line ();
23086 /* Parse a .object_arch directive. */
23089 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23091 const struct arm_arch_option_table
*opt
;
23095 name
= input_line_pointer
;
23096 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23097 input_line_pointer
++;
23098 saved_char
= *input_line_pointer
;
23099 *input_line_pointer
= 0;
23101 /* Skip the first "all" entry. */
23102 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23103 if (streq (opt
->name
, name
))
23105 object_arch
= &opt
->value
;
23106 *input_line_pointer
= saved_char
;
23107 demand_empty_rest_of_line ();
23111 as_bad (_("unknown architecture `%s'\n"), name
);
23112 *input_line_pointer
= saved_char
;
23113 ignore_rest_of_line ();
23116 /* Parse a .fpu directive. */
23119 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23121 const struct arm_option_cpu_value_table
*opt
;
23125 name
= input_line_pointer
;
23126 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23127 input_line_pointer
++;
23128 saved_char
= *input_line_pointer
;
23129 *input_line_pointer
= 0;
23131 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23132 if (streq (opt
->name
, name
))
23134 mfpu_opt
= &opt
->value
;
23135 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23136 *input_line_pointer
= saved_char
;
23137 demand_empty_rest_of_line ();
23141 as_bad (_("unknown floating point format `%s'\n"), name
);
23142 *input_line_pointer
= saved_char
;
23143 ignore_rest_of_line ();
23146 /* Copy symbol information. */
23149 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23151 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23155 /* Given a symbolic attribute NAME, return the proper integer value.
23156 Returns -1 if the attribute is not known. */
23159 arm_convert_symbolic_attribute (const char *name
)
23161 static const struct
23166 attribute_table
[] =
23168 /* When you modify this table you should
23169 also modify the list in doc/c-arm.texi. */
23170 #define T(tag) {#tag, tag}
23171 T (Tag_CPU_raw_name
),
23174 T (Tag_CPU_arch_profile
),
23175 T (Tag_ARM_ISA_use
),
23176 T (Tag_THUMB_ISA_use
),
23180 T (Tag_Advanced_SIMD_arch
),
23181 T (Tag_PCS_config
),
23182 T (Tag_ABI_PCS_R9_use
),
23183 T (Tag_ABI_PCS_RW_data
),
23184 T (Tag_ABI_PCS_RO_data
),
23185 T (Tag_ABI_PCS_GOT_use
),
23186 T (Tag_ABI_PCS_wchar_t
),
23187 T (Tag_ABI_FP_rounding
),
23188 T (Tag_ABI_FP_denormal
),
23189 T (Tag_ABI_FP_exceptions
),
23190 T (Tag_ABI_FP_user_exceptions
),
23191 T (Tag_ABI_FP_number_model
),
23192 T (Tag_ABI_align_needed
),
23193 T (Tag_ABI_align8_needed
),
23194 T (Tag_ABI_align_preserved
),
23195 T (Tag_ABI_align8_preserved
),
23196 T (Tag_ABI_enum_size
),
23197 T (Tag_ABI_HardFP_use
),
23198 T (Tag_ABI_VFP_args
),
23199 T (Tag_ABI_WMMX_args
),
23200 T (Tag_ABI_optimization_goals
),
23201 T (Tag_ABI_FP_optimization_goals
),
23202 T (Tag_compatibility
),
23203 T (Tag_CPU_unaligned_access
),
23204 T (Tag_FP_HP_extension
),
23205 T (Tag_VFP_HP_extension
),
23206 T (Tag_ABI_FP_16bit_format
),
23207 T (Tag_MPextension_use
),
23209 T (Tag_nodefaults
),
23210 T (Tag_also_compatible_with
),
23211 T (Tag_conformance
),
23213 T (Tag_Virtualization_use
),
23214 /* We deliberately do not include Tag_MPextension_use_legacy. */
23222 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23223 if (streq (name
, attribute_table
[i
].name
))
23224 return attribute_table
[i
].tag
;
23230 /* Apply sym value for relocations only in the case that
23231 they are for local symbols and you have the respective
23232 architectural feature for blx and simple switches. */
23234 arm_apply_sym_value (struct fix
* fixP
)
23237 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23238 && !S_IS_EXTERNAL (fixP
->fx_addsy
))
23240 switch (fixP
->fx_r_type
)
23242 case BFD_RELOC_ARM_PCREL_BLX
:
23243 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23244 if (ARM_IS_FUNC (fixP
->fx_addsy
))
23248 case BFD_RELOC_ARM_PCREL_CALL
:
23249 case BFD_RELOC_THUMB_PCREL_BLX
:
23250 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
23261 #endif /* OBJ_ELF */