1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2020 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
39 #include "dw2gencfi.h"
42 #include "dwarf2dbg.h"
45 /* Must be at least the size of the largest unwind opcode (currently two). */
46 #define ARM_OPCODE_CHUNK_SIZE 8
48 /* This structure holds the unwinding state. */
53 symbolS
* table_entry
;
54 symbolS
* personality_routine
;
55 int personality_index
;
56 /* The segment containing the function. */
59 /* Opcodes generated from this function. */
60 unsigned char * opcodes
;
63 /* The number of bytes pushed to the stack. */
65 /* We don't add stack adjustment opcodes immediately so that we can merge
66 multiple adjustments. We can also omit the final adjustment
67 when using a frame pointer. */
68 offsetT pending_offset
;
69 /* These two fields are set by both unwind_movsp and unwind_setfp. They
70 hold the reg+offset to use when restoring sp from a frame pointer. */
73 /* Nonzero if an unwind_setfp directive has been seen. */
75 /* Nonzero if the last opcode restores sp from fp_reg. */
76 unsigned sp_restored
:1;
79 /* Whether --fdpic was given. */
84 /* Results from operand parsing worker functions. */
88 PARSE_OPERAND_SUCCESS
,
90 PARSE_OPERAND_FAIL_NO_BACKTRACK
91 } parse_operand_result
;
100 /* Types of processor to assemble for. */
102 /* The code that was here used to select a default CPU depending on compiler
103 pre-defines which were only present when doing native builds, thus
104 changing gas' default behaviour depending upon the build host.
106 If you have a target that requires a default CPU option then the you
107 should define CPU_DEFAULT here. */
110 /* Perform range checks on positive and negative overflows by checking if the
111 VALUE given fits within the range of an BITS sized immediate. */
112 static bfd_boolean
out_of_range_p (offsetT value
, offsetT bits
)
114 gas_assert (bits
< (offsetT
)(sizeof (value
) * 8));
115 return (value
& ~((1 << bits
)-1))
116 && ((value
& ~((1 << bits
)-1)) != ~((1 << bits
)-1));
121 # define FPU_DEFAULT FPU_ARCH_FPA
122 # elif defined (TE_NetBSD)
124 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
126 /* Legacy a.out format. */
127 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
129 # elif defined (TE_VXWORKS)
130 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
132 /* For backwards compatibility, default to FPA. */
133 # define FPU_DEFAULT FPU_ARCH_FPA
135 #endif /* ifndef FPU_DEFAULT */
137 #define streq(a, b) (strcmp (a, b) == 0)
139 /* Current set of feature bits available (CPU+FPU). Different from
140 selected_cpu + selected_fpu in case of autodetection since the CPU
141 feature bits are then all set. */
142 static arm_feature_set cpu_variant
;
143 /* Feature bits used in each execution state. Used to set build attribute
144 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
145 static arm_feature_set arm_arch_used
;
146 static arm_feature_set thumb_arch_used
;
148 /* Flags stored in private area of BFD structure. */
149 static int uses_apcs_26
= FALSE
;
150 static int atpcs
= FALSE
;
151 static int support_interwork
= FALSE
;
152 static int uses_apcs_float
= FALSE
;
153 static int pic_code
= FALSE
;
154 static int fix_v4bx
= FALSE
;
155 /* Warn on using deprecated features. */
156 static int warn_on_deprecated
= TRUE
;
157 static int warn_on_restrict_it
= FALSE
;
159 /* Understand CodeComposer Studio assembly syntax. */
160 bfd_boolean codecomposer_syntax
= FALSE
;
162 /* Variables that we set while parsing command-line options. Once all
163 options have been read we re-process these values to set the real
166 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
167 instead of -mcpu=arm1). */
168 static const arm_feature_set
*legacy_cpu
= NULL
;
169 static const arm_feature_set
*legacy_fpu
= NULL
;
171 /* CPU, extension and FPU feature bits selected by -mcpu. */
172 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
173 static arm_feature_set
*mcpu_ext_opt
= NULL
;
174 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
176 /* CPU, extension and FPU feature bits selected by -march. */
177 static const arm_feature_set
*march_cpu_opt
= NULL
;
178 static arm_feature_set
*march_ext_opt
= NULL
;
179 static const arm_feature_set
*march_fpu_opt
= NULL
;
181 /* Feature bits selected by -mfpu. */
182 static const arm_feature_set
*mfpu_opt
= NULL
;
184 /* Constants for known architecture features. */
185 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
186 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
187 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
188 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
189 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
190 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
191 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
193 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
195 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
198 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
201 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
202 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
203 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
204 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
205 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
206 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
207 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
208 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
209 static const arm_feature_set arm_ext_v4t_5
=
210 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
211 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
212 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
213 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
214 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
215 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
216 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
217 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
218 /* Only for compatability of hint instructions. */
219 static const arm_feature_set arm_ext_v6k_v6t2
=
220 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
221 static const arm_feature_set arm_ext_v6_notm
=
222 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
223 static const arm_feature_set arm_ext_v6_dsp
=
224 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
225 static const arm_feature_set arm_ext_barrier
=
226 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
227 static const arm_feature_set arm_ext_msr
=
228 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
229 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
230 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
231 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
232 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
234 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
236 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
237 static const arm_feature_set arm_ext_m
=
238 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
239 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
240 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
241 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
242 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
243 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
244 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
245 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
246 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
247 static const arm_feature_set arm_ext_v8m_main
=
248 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
249 static const arm_feature_set arm_ext_v8_1m_main
=
250 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
251 /* Instructions in ARMv8-M only found in M profile architectures. */
252 static const arm_feature_set arm_ext_v8m_m_only
=
253 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
254 static const arm_feature_set arm_ext_v6t2_v8m
=
255 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
256 /* Instructions shared between ARMv8-A and ARMv8-M. */
257 static const arm_feature_set arm_ext_atomics
=
258 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
260 /* DSP instructions Tag_DSP_extension refers to. */
261 static const arm_feature_set arm_ext_dsp
=
262 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
264 static const arm_feature_set arm_ext_ras
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
266 /* FP16 instructions. */
267 static const arm_feature_set arm_ext_fp16
=
268 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
269 static const arm_feature_set arm_ext_fp16_fml
=
270 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
271 static const arm_feature_set arm_ext_v8_2
=
272 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
273 static const arm_feature_set arm_ext_v8_3
=
274 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
275 static const arm_feature_set arm_ext_sb
=
276 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
277 static const arm_feature_set arm_ext_predres
=
278 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
279 static const arm_feature_set arm_ext_bf16
=
280 ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
);
281 static const arm_feature_set arm_ext_i8mm
=
282 ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
);
283 static const arm_feature_set arm_ext_crc
=
284 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
);
285 static const arm_feature_set arm_ext_cde
=
286 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE
);
287 static const arm_feature_set arm_ext_cde0
=
288 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE0
);
289 static const arm_feature_set arm_ext_cde1
=
290 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE1
);
291 static const arm_feature_set arm_ext_cde2
=
292 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE2
);
293 static const arm_feature_set arm_ext_cde3
=
294 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE3
);
295 static const arm_feature_set arm_ext_cde4
=
296 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE4
);
297 static const arm_feature_set arm_ext_cde5
=
298 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE5
);
299 static const arm_feature_set arm_ext_cde6
=
300 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE6
);
301 static const arm_feature_set arm_ext_cde7
=
302 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE7
);
304 static const arm_feature_set arm_arch_any
= ARM_ANY
;
305 static const arm_feature_set fpu_any
= FPU_ANY
;
306 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
307 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
308 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
310 static const arm_feature_set arm_cext_iwmmxt2
=
311 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
312 static const arm_feature_set arm_cext_iwmmxt
=
313 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
314 static const arm_feature_set arm_cext_xscale
=
315 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
316 static const arm_feature_set arm_cext_maverick
=
317 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
318 static const arm_feature_set fpu_fpa_ext_v1
=
319 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
320 static const arm_feature_set fpu_fpa_ext_v2
=
321 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
322 static const arm_feature_set fpu_vfp_ext_v1xd
=
323 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
324 static const arm_feature_set fpu_vfp_ext_v1
=
325 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
326 static const arm_feature_set fpu_vfp_ext_v2
=
327 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
328 static const arm_feature_set fpu_vfp_ext_v3xd
=
329 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
330 static const arm_feature_set fpu_vfp_ext_v3
=
331 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
332 static const arm_feature_set fpu_vfp_ext_d32
=
333 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
334 static const arm_feature_set fpu_neon_ext_v1
=
335 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
336 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
337 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
338 static const arm_feature_set mve_ext
=
339 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
);
340 static const arm_feature_set mve_fp_ext
=
341 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE_FP
);
342 /* Note: This has more than one bit set, which means using it with
343 mark_feature_used (which returns if *any* of the bits are set in the current
344 cpu variant) can give surprising results. */
345 static const arm_feature_set armv8m_fp
=
346 ARM_FEATURE_COPROC (FPU_VFP_V5_SP_D16
);
348 static const arm_feature_set fpu_vfp_fp16
=
349 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
350 static const arm_feature_set fpu_neon_ext_fma
=
351 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
353 static const arm_feature_set fpu_vfp_ext_fma
=
354 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
355 static const arm_feature_set fpu_vfp_ext_armv8
=
356 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
357 static const arm_feature_set fpu_vfp_ext_armv8xd
=
358 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
359 static const arm_feature_set fpu_neon_ext_armv8
=
360 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
361 static const arm_feature_set fpu_crypto_ext_armv8
=
362 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
363 static const arm_feature_set fpu_neon_ext_v8_1
=
364 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
365 static const arm_feature_set fpu_neon_ext_dotprod
=
366 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
368 static int mfloat_abi_opt
= -1;
369 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
371 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
372 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
374 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
375 /* Feature bits selected by the last -mcpu/-march or by the combination of the
376 last .cpu/.arch directive .arch_extension directives since that
378 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
379 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
380 static arm_feature_set selected_fpu
= FPU_NONE
;
381 /* Feature bits selected by the last .object_arch directive. */
382 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
383 /* Must be long enough to hold any of the names in arm_cpus. */
384 static const struct arm_ext_table
* selected_ctx_ext_table
= NULL
;
385 static char selected_cpu_name
[20];
387 extern FLONUM_TYPE generic_floating_point_number
;
389 /* Return if no cpu was selected on command-line. */
391 no_cpu_selected (void)
393 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
398 static int meabi_flags
= EABI_DEFAULT
;
400 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
403 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
408 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
413 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
414 symbolS
* GOT_symbol
;
417 /* 0: assemble for ARM,
418 1: assemble for Thumb,
419 2: assemble for Thumb even though target CPU does not support thumb
421 static int thumb_mode
= 0;
422 /* A value distinct from the possible values for thumb_mode that we
423 can use to record whether thumb_mode has been copied into the
424 tc_frag_data field of a frag. */
425 #define MODE_RECORDED (1 << 4)
427 /* Specifies the intrinsic IT insn behavior mode. */
428 enum implicit_it_mode
430 IMPLICIT_IT_MODE_NEVER
= 0x00,
431 IMPLICIT_IT_MODE_ARM
= 0x01,
432 IMPLICIT_IT_MODE_THUMB
= 0x02,
433 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
435 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
437 /* If unified_syntax is true, we are processing the new unified
438 ARM/Thumb syntax. Important differences from the old ARM mode:
440 - Immediate operands do not require a # prefix.
441 - Conditional affixes always appear at the end of the
442 instruction. (For backward compatibility, those instructions
443 that formerly had them in the middle, continue to accept them
445 - The IT instruction may appear, and if it does is validated
446 against subsequent conditional affixes. It does not generate
449 Important differences from the old Thumb mode:
451 - Immediate operands do not require a # prefix.
452 - Most of the V6T2 instructions are only available in unified mode.
453 - The .N and .W suffixes are recognized and honored (it is an error
454 if they cannot be honored).
455 - All instructions set the flags if and only if they have an 's' affix.
456 - Conditional affixes may be used. They are validated against
457 preceding IT instructions. Unlike ARM mode, you cannot use a
458 conditional affix except in the scope of an IT instruction. */
460 static bfd_boolean unified_syntax
= FALSE
;
462 /* An immediate operand can start with #, and ld*, st*, pld operands
463 can contain [ and ]. We need to tell APP not to elide whitespace
464 before a [, which can appear as the first operand for pld.
465 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
466 const char arm_symbol_chars
[] = "#[]{}";
482 enum neon_el_type type
;
486 #define NEON_MAX_TYPE_ELS 5
490 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
494 enum pred_instruction_type
500 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
501 if inside, should be the last one. */
502 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
503 i.e. BKPT and NOP. */
504 IT_INSN
, /* The IT insn has been parsed. */
505 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
506 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
507 a predication code. */
508 MVE_UNPREDICABLE_INSN
, /* MVE instruction that is non-predicable. */
509 NEUTRAL_IT_NO_VPT_INSN
, /* Instruction that can be either inside or outside
510 an IT block, but must not be in a VPT block. */
513 /* The maximum number of operands we need. */
514 #define ARM_IT_MAX_OPERANDS 6
515 #define ARM_IT_MAX_RELOCS 3
520 unsigned long instruction
;
524 /* "uncond_value" is set to the value in place of the conditional field in
525 unconditional versions of the instruction, or -1 if nothing is
528 struct neon_type vectype
;
529 /* This does not indicate an actual NEON instruction, only that
530 the mnemonic accepts neon-style type suffixes. */
532 /* Set to the opcode if the instruction needs relaxation.
533 Zero if the instruction is not relaxed. */
537 bfd_reloc_code_real_type type
;
540 } relocs
[ARM_IT_MAX_RELOCS
];
542 enum pred_instruction_type pred_insn_type
;
548 struct neon_type_el vectype
;
549 unsigned present
: 1; /* Operand present. */
550 unsigned isreg
: 1; /* Operand was a register. */
551 unsigned immisreg
: 2; /* .imm field is a second register.
552 0: imm, 1: gpr, 2: MVE Q-register. */
553 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
557 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
558 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
559 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
560 instructions. This allows us to disambiguate ARM <-> vector insns. */
561 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
562 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
563 unsigned isquad
: 1; /* Operand is SIMD quad register. */
564 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
565 unsigned iszr
: 1; /* Operand is ZR register. */
566 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
567 unsigned writeback
: 1; /* Operand has trailing ! */
568 unsigned preind
: 1; /* Preindexed address. */
569 unsigned postind
: 1; /* Postindexed address. */
570 unsigned negative
: 1; /* Index register was negated. */
571 unsigned shifted
: 1; /* Shift applied to operation. */
572 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
573 } operands
[ARM_IT_MAX_OPERANDS
];
576 static struct arm_it inst
;
578 #define NUM_FLOAT_VALS 8
580 const char * fp_const
[] =
582 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
585 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
595 #define CP_T_X 0x00008000
596 #define CP_T_Y 0x00400000
598 #define CONDS_BIT 0x00100000
599 #define LOAD_BIT 0x00100000
601 #define DOUBLE_LOAD_FLAG 0x00000001
605 const char * template_name
;
609 #define COND_ALWAYS 0xE
613 const char * template_name
;
617 struct asm_barrier_opt
619 const char * template_name
;
621 const arm_feature_set arch
;
624 /* The bit that distinguishes CPSR and SPSR. */
625 #define SPSR_BIT (1 << 22)
627 /* The individual PSR flag bits. */
628 #define PSR_c (1 << 16)
629 #define PSR_x (1 << 17)
630 #define PSR_s (1 << 18)
631 #define PSR_f (1 << 19)
636 bfd_reloc_code_real_type reloc
;
641 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
642 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
647 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
650 /* Bits for DEFINED field in neon_typed_alias. */
651 #define NTA_HASTYPE 1
652 #define NTA_HASINDEX 2
654 struct neon_typed_alias
656 unsigned char defined
;
658 struct neon_type_el eltype
;
661 /* ARM register categories. This includes coprocessor numbers and various
662 architecture extensions' registers. Each entry should have an error message
663 in reg_expected_msgs below. */
693 /* Structure for a hash table entry for a register.
694 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
695 information which states whether a vector type or index is specified (for a
696 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
702 unsigned char builtin
;
703 struct neon_typed_alias
* neon
;
706 /* Diagnostics used when we don't get a register of the expected type. */
707 const char * const reg_expected_msgs
[] =
709 [REG_TYPE_RN
] = N_("ARM register expected"),
710 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
711 [REG_TYPE_CN
] = N_("co-processor register expected"),
712 [REG_TYPE_FN
] = N_("FPA register expected"),
713 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
714 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
715 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
716 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
717 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
718 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
719 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
721 [REG_TYPE_VFC
] = N_("VFP system register expected"),
722 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
723 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
724 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
725 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
726 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
727 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
728 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
729 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
730 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
731 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
732 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
733 [REG_TYPE_RNB
] = N_("")
736 /* Some well known registers that we refer to directly elsewhere. */
742 /* ARM instructions take 4bytes in the object file, Thumb instructions
748 /* Basic string to match. */
749 const char * template_name
;
751 /* Parameters to instruction. */
752 unsigned int operands
[8];
754 /* Conditional tag - see opcode_lookup. */
755 unsigned int tag
: 4;
757 /* Basic instruction code. */
760 /* Thumb-format instruction code. */
763 /* Which architecture variant provides this instruction. */
764 const arm_feature_set
* avariant
;
765 const arm_feature_set
* tvariant
;
767 /* Function to call to encode instruction in ARM format. */
768 void (* aencode
) (void);
770 /* Function to call to encode instruction in Thumb format. */
771 void (* tencode
) (void);
773 /* Indicates whether this instruction may be vector predicated. */
774 unsigned int mayBeVecPred
: 1;
777 /* Defines for various bits that we will want to toggle. */
778 #define INST_IMMEDIATE 0x02000000
779 #define OFFSET_REG 0x02000000
780 #define HWOFFSET_IMM 0x00400000
781 #define SHIFT_BY_REG 0x00000010
782 #define PRE_INDEX 0x01000000
783 #define INDEX_UP 0x00800000
784 #define WRITE_BACK 0x00200000
785 #define LDM_TYPE_2_OR_3 0x00400000
786 #define CPSI_MMOD 0x00020000
788 #define LITERAL_MASK 0xf000f000
789 #define OPCODE_MASK 0xfe1fffff
790 #define V4_STR_BIT 0x00000020
791 #define VLDR_VMOV_SAME 0x0040f000
793 #define T2_SUBS_PC_LR 0xf3de8f00
795 #define DATA_OP_SHIFT 21
796 #define SBIT_SHIFT 20
798 #define T2_OPCODE_MASK 0xfe1fffff
799 #define T2_DATA_OP_SHIFT 21
800 #define T2_SBIT_SHIFT 20
802 #define A_COND_MASK 0xf0000000
803 #define A_PUSH_POP_OP_MASK 0x0fff0000
805 /* Opcodes for pushing/poping registers to/from the stack. */
806 #define A1_OPCODE_PUSH 0x092d0000
807 #define A2_OPCODE_PUSH 0x052d0004
808 #define A2_OPCODE_POP 0x049d0004
810 /* Codes to distinguish the arithmetic instructions. */
821 #define OPCODE_CMP 10
822 #define OPCODE_CMN 11
823 #define OPCODE_ORR 12
824 #define OPCODE_MOV 13
825 #define OPCODE_BIC 14
826 #define OPCODE_MVN 15
828 #define T2_OPCODE_AND 0
829 #define T2_OPCODE_BIC 1
830 #define T2_OPCODE_ORR 2
831 #define T2_OPCODE_ORN 3
832 #define T2_OPCODE_EOR 4
833 #define T2_OPCODE_ADD 8
834 #define T2_OPCODE_ADC 10
835 #define T2_OPCODE_SBC 11
836 #define T2_OPCODE_SUB 13
837 #define T2_OPCODE_RSB 14
839 #define T_OPCODE_MUL 0x4340
840 #define T_OPCODE_TST 0x4200
841 #define T_OPCODE_CMN 0x42c0
842 #define T_OPCODE_NEG 0x4240
843 #define T_OPCODE_MVN 0x43c0
845 #define T_OPCODE_ADD_R3 0x1800
846 #define T_OPCODE_SUB_R3 0x1a00
847 #define T_OPCODE_ADD_HI 0x4400
848 #define T_OPCODE_ADD_ST 0xb000
849 #define T_OPCODE_SUB_ST 0xb080
850 #define T_OPCODE_ADD_SP 0xa800
851 #define T_OPCODE_ADD_PC 0xa000
852 #define T_OPCODE_ADD_I8 0x3000
853 #define T_OPCODE_SUB_I8 0x3800
854 #define T_OPCODE_ADD_I3 0x1c00
855 #define T_OPCODE_SUB_I3 0x1e00
857 #define T_OPCODE_ASR_R 0x4100
858 #define T_OPCODE_LSL_R 0x4080
859 #define T_OPCODE_LSR_R 0x40c0
860 #define T_OPCODE_ROR_R 0x41c0
861 #define T_OPCODE_ASR_I 0x1000
862 #define T_OPCODE_LSL_I 0x0000
863 #define T_OPCODE_LSR_I 0x0800
865 #define T_OPCODE_MOV_I8 0x2000
866 #define T_OPCODE_CMP_I8 0x2800
867 #define T_OPCODE_CMP_LR 0x4280
868 #define T_OPCODE_MOV_HR 0x4600
869 #define T_OPCODE_CMP_HR 0x4500
871 #define T_OPCODE_LDR_PC 0x4800
872 #define T_OPCODE_LDR_SP 0x9800
873 #define T_OPCODE_STR_SP 0x9000
874 #define T_OPCODE_LDR_IW 0x6800
875 #define T_OPCODE_STR_IW 0x6000
876 #define T_OPCODE_LDR_IH 0x8800
877 #define T_OPCODE_STR_IH 0x8000
878 #define T_OPCODE_LDR_IB 0x7800
879 #define T_OPCODE_STR_IB 0x7000
880 #define T_OPCODE_LDR_RW 0x5800
881 #define T_OPCODE_STR_RW 0x5000
882 #define T_OPCODE_LDR_RH 0x5a00
883 #define T_OPCODE_STR_RH 0x5200
884 #define T_OPCODE_LDR_RB 0x5c00
885 #define T_OPCODE_STR_RB 0x5400
887 #define T_OPCODE_PUSH 0xb400
888 #define T_OPCODE_POP 0xbc00
890 #define T_OPCODE_BRANCH 0xe000
892 #define THUMB_SIZE 2 /* Size of thumb instruction. */
893 #define THUMB_PP_PC_LR 0x0100
894 #define THUMB_LOAD_BIT 0x0800
895 #define THUMB2_LOAD_BIT 0x00100000
897 #define BAD_SYNTAX _("syntax error")
898 #define BAD_ARGS _("bad arguments to instruction")
899 #define BAD_SP _("r13 not allowed here")
900 #define BAD_PC _("r15 not allowed here")
901 #define BAD_ODD _("Odd register not allowed here")
902 #define BAD_EVEN _("Even register not allowed here")
903 #define BAD_COND _("instruction cannot be conditional")
904 #define BAD_OVERLAP _("registers may not be the same")
905 #define BAD_HIREG _("lo register required")
906 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
907 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
908 #define BAD_BRANCH _("branch must be last instruction in IT block")
909 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
910 #define BAD_NO_VPT _("instruction not allowed in VPT block")
911 #define BAD_NOT_IT _("instruction not allowed in IT block")
912 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
913 #define BAD_FPU _("selected FPU does not support instruction")
914 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
915 #define BAD_OUT_VPT \
916 _("vector predicated instruction should be in VPT/VPST block")
917 #define BAD_IT_COND _("incorrect condition in IT block")
918 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
919 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
920 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
921 #define BAD_PC_ADDRESSING \
922 _("cannot use register index with PC-relative addressing")
923 #define BAD_PC_WRITEBACK \
924 _("cannot use writeback with PC-relative addressing")
925 #define BAD_RANGE _("branch out of range")
926 #define BAD_FP16 _("selected processor does not support fp16 instruction")
927 #define BAD_BF16 _("selected processor does not support bf16 instruction")
928 #define BAD_CDE _("selected processor does not support cde instruction")
929 #define BAD_CDE_COPROC _("coprocessor for insn is not enabled for cde")
930 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
931 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
932 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
934 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
936 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
938 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
940 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
941 #define BAD_MVE_AUTO \
942 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
943 " use a valid -march or -mcpu option.")
944 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
945 "and source operands makes instruction UNPREDICTABLE")
946 #define BAD_EL_TYPE _("bad element type for instruction")
947 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
949 static struct hash_control
* arm_ops_hsh
;
950 static struct hash_control
* arm_cond_hsh
;
951 static struct hash_control
* arm_vcond_hsh
;
952 static struct hash_control
* arm_shift_hsh
;
953 static struct hash_control
* arm_psr_hsh
;
954 static struct hash_control
* arm_v7m_psr_hsh
;
955 static struct hash_control
* arm_reg_hsh
;
956 static struct hash_control
* arm_reloc_hsh
;
957 static struct hash_control
* arm_barrier_opt_hsh
;
959 /* Stuff needed to resolve the label ambiguity
968 symbolS
* last_label_seen
;
969 static int label_is_thumb_function_name
= FALSE
;
971 /* Literal pool structure. Held on a per-section
972 and per-sub-section basis. */
974 #define MAX_LITERAL_POOL_SIZE 1024
975 typedef struct literal_pool
977 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
978 unsigned int next_free_entry
;
984 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
986 struct literal_pool
* next
;
987 unsigned int alignment
;
990 /* Pointer to a linked list of literal pools. */
991 literal_pool
* list_of_pools
= NULL
;
993 typedef enum asmfunc_states
996 WAITING_ASMFUNC_NAME
,
1000 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
1003 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
1005 static struct current_pred now_pred
;
1009 now_pred_compatible (int cond
)
1011 return (cond
& ~1) == (now_pred
.cc
& ~1);
1015 conditional_insn (void)
1017 return inst
.cond
!= COND_ALWAYS
;
1020 static int in_pred_block (void);
1022 static int handle_pred_state (void);
1024 static void force_automatic_it_block_close (void);
1026 static void it_fsm_post_encode (void);
1028 #define set_pred_insn_type(type) \
1031 inst.pred_insn_type = type; \
1032 if (handle_pred_state () == FAIL) \
1037 #define set_pred_insn_type_nonvoid(type, failret) \
1040 inst.pred_insn_type = type; \
1041 if (handle_pred_state () == FAIL) \
1046 #define set_pred_insn_type_last() \
1049 if (inst.cond == COND_ALWAYS) \
1050 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1052 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1056 /* Toggle value[pos]. */
1057 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1061 /* This array holds the chars that always start a comment. If the
1062 pre-processor is disabled, these aren't very useful. */
1063 char arm_comment_chars
[] = "@";
1065 /* This array holds the chars that only start a comment at the beginning of
1066 a line. If the line seems to have the form '# 123 filename'
1067 .line and .file directives will appear in the pre-processed output. */
1068 /* Note that input_file.c hand checks for '#' at the beginning of the
1069 first line of the input file. This is because the compiler outputs
1070 #NO_APP at the beginning of its output. */
1071 /* Also note that comments like this one will always work. */
1072 const char line_comment_chars
[] = "#";
1074 char arm_line_separator_chars
[] = ";";
1076 /* Chars that can be used to separate mant
1077 from exp in floating point numbers. */
1078 const char EXP_CHARS
[] = "eE";
1080 /* Chars that mean this number is a floating point constant. */
1081 /* As in 0f12.456 */
1082 /* or 0d1.2345e12 */
1084 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1086 /* Prefix characters that indicate the start of an immediate
1088 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1090 /* Separator character handling. */
1092 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1094 enum fp_16bit_format
1096 ARM_FP16_FORMAT_IEEE
= 0x1,
1097 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1098 ARM_FP16_FORMAT_DEFAULT
= 0x3
1101 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1105 skip_past_char (char ** str
, char c
)
1107 /* PR gas/14987: Allow for whitespace before the expected character. */
1108 skip_whitespace (*str
);
1119 #define skip_past_comma(str) skip_past_char (str, ',')
1121 /* Arithmetic expressions (possibly involving symbols). */
1123 /* Return TRUE if anything in the expression is a bignum. */
1126 walk_no_bignums (symbolS
* sp
)
1128 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1131 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1133 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1134 || (symbol_get_value_expression (sp
)->X_op_symbol
1135 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1141 static bfd_boolean in_my_get_expression
= FALSE
;
1143 /* Third argument to my_get_expression. */
1144 #define GE_NO_PREFIX 0
1145 #define GE_IMM_PREFIX 1
1146 #define GE_OPT_PREFIX 2
1147 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1148 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1149 #define GE_OPT_PREFIX_BIG 3
1152 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1156 /* In unified syntax, all prefixes are optional. */
1158 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1161 switch (prefix_mode
)
1163 case GE_NO_PREFIX
: break;
1165 if (!is_immediate_prefix (**str
))
1167 inst
.error
= _("immediate expression requires a # prefix");
1173 case GE_OPT_PREFIX_BIG
:
1174 if (is_immediate_prefix (**str
))
1181 memset (ep
, 0, sizeof (expressionS
));
1183 save_in
= input_line_pointer
;
1184 input_line_pointer
= *str
;
1185 in_my_get_expression
= TRUE
;
1187 in_my_get_expression
= FALSE
;
1189 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1191 /* We found a bad or missing expression in md_operand(). */
1192 *str
= input_line_pointer
;
1193 input_line_pointer
= save_in
;
1194 if (inst
.error
== NULL
)
1195 inst
.error
= (ep
->X_op
== O_absent
1196 ? _("missing expression") :_("bad expression"));
1200 /* Get rid of any bignums now, so that we don't generate an error for which
1201 we can't establish a line number later on. Big numbers are never valid
1202 in instructions, which is where this routine is always called. */
1203 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1204 && (ep
->X_op
== O_big
1205 || (ep
->X_add_symbol
1206 && (walk_no_bignums (ep
->X_add_symbol
)
1208 && walk_no_bignums (ep
->X_op_symbol
))))))
1210 inst
.error
= _("invalid constant");
1211 *str
= input_line_pointer
;
1212 input_line_pointer
= save_in
;
1216 *str
= input_line_pointer
;
1217 input_line_pointer
= save_in
;
1221 /* Turn a string in input_line_pointer into a floating point constant
1222 of type TYPE, and store the appropriate bytes in *LITP. The number
1223 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1224 returned, or NULL on OK.
1226 Note that fp constants aren't represent in the normal way on the ARM.
1227 In big endian mode, things are as expected. However, in little endian
1228 mode fp constants are big-endian word-wise, and little-endian byte-wise
1229 within the words. For example, (double) 1.1 in big endian mode is
1230 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1231 the byte sequence 99 99 f1 3f 9a 99 99 99.
1233 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1236 md_atof (int type
, char * litP
, int * sizeP
)
1239 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1250 /* If this is a bfloat16, then parse it slightly differently, as it
1251 does not follow the IEEE specification for floating point numbers
1255 FLONUM_TYPE generic_float
;
1257 t
= atof_ieee_detail (input_line_pointer
, 1, 8, words
, &generic_float
);
1260 input_line_pointer
= t
;
1262 return _("invalid floating point number");
1264 switch (generic_float
.sign
)
1277 /* bfloat16 has two types of NaN - quiet and signalling.
1278 Quiet NaN has bit[6] == 1 && faction != 0, whereas
1279 signalling NaN's have bit[0] == 0 && fraction != 0.
1280 Chosen this specific encoding as it is the same form
1281 as used by other IEEE 754 encodings in GAS. */
1292 md_number_to_chars (litP
, (valueT
) words
[0], sizeof (LITTLENUM_TYPE
));
1322 return _("Unrecognized or unsupported floating point constant");
1325 t
= atof_ieee (input_line_pointer
, type
, words
);
1327 input_line_pointer
= t
;
1328 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1330 if (target_big_endian
|| prec
== 1)
1331 for (i
= 0; i
< prec
; i
++)
1333 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1334 litP
+= sizeof (LITTLENUM_TYPE
);
1336 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1337 for (i
= prec
- 1; i
>= 0; i
--)
1339 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1340 litP
+= sizeof (LITTLENUM_TYPE
);
1343 /* For a 4 byte float the order of elements in `words' is 1 0.
1344 For an 8 byte float the order is 1 0 3 2. */
1345 for (i
= 0; i
< prec
; i
+= 2)
1347 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1348 sizeof (LITTLENUM_TYPE
));
1349 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1350 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1351 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1357 /* We handle all bad expressions here, so that we can report the faulty
1358 instruction in the error message. */
1361 md_operand (expressionS
* exp
)
1363 if (in_my_get_expression
)
1364 exp
->X_op
= O_illegal
;
1367 /* Immediate values. */
1370 /* Generic immediate-value read function for use in directives.
1371 Accepts anything that 'expression' can fold to a constant.
1372 *val receives the number. */
1375 immediate_for_directive (int *val
)
1378 exp
.X_op
= O_illegal
;
1380 if (is_immediate_prefix (*input_line_pointer
))
1382 input_line_pointer
++;
1386 if (exp
.X_op
!= O_constant
)
1388 as_bad (_("expected #constant"));
1389 ignore_rest_of_line ();
1392 *val
= exp
.X_add_number
;
1397 /* Register parsing. */
1399 /* Generic register parser. CCP points to what should be the
1400 beginning of a register name. If it is indeed a valid register
1401 name, advance CCP over it and return the reg_entry structure;
1402 otherwise return NULL. Does not issue diagnostics. */
1404 static struct reg_entry
*
1405 arm_reg_parse_multi (char **ccp
)
1409 struct reg_entry
*reg
;
1411 skip_whitespace (start
);
1413 #ifdef REGISTER_PREFIX
1414 if (*start
!= REGISTER_PREFIX
)
1418 #ifdef OPTIONAL_REGISTER_PREFIX
1419 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1424 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1429 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1431 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1441 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1442 enum arm_reg_type type
)
1444 /* Alternative syntaxes are accepted for a few register classes. */
1451 /* Generic coprocessor register names are allowed for these. */
1452 if (reg
&& reg
->type
== REG_TYPE_CN
)
1457 /* For backward compatibility, a bare number is valid here. */
1459 unsigned long processor
= strtoul (start
, ccp
, 10);
1460 if (*ccp
!= start
&& processor
<= 15)
1465 case REG_TYPE_MMXWC
:
1466 /* WC includes WCG. ??? I'm not sure this is true for all
1467 instructions that take WC registers. */
1468 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1479 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1480 return value is the register number or FAIL. */
1483 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1486 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1489 /* Do not allow a scalar (reg+index) to parse as a register. */
1490 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1493 if (reg
&& reg
->type
== type
)
1496 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1503 /* Parse a Neon type specifier. *STR should point at the leading '.'
1504 character. Does no verification at this stage that the type fits the opcode
1511 Can all be legally parsed by this function.
1513 Fills in neon_type struct pointer with parsed information, and updates STR
1514 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1515 type, FAIL if not. */
1518 parse_neon_type (struct neon_type
*type
, char **str
)
1525 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1527 enum neon_el_type thistype
= NT_untyped
;
1528 unsigned thissize
= -1u;
1535 /* Just a size without an explicit type. */
1539 switch (TOLOWER (*ptr
))
1541 case 'i': thistype
= NT_integer
; break;
1542 case 'f': thistype
= NT_float
; break;
1543 case 'p': thistype
= NT_poly
; break;
1544 case 's': thistype
= NT_signed
; break;
1545 case 'u': thistype
= NT_unsigned
; break;
1547 thistype
= NT_float
;
1552 thistype
= NT_bfloat
;
1553 switch (TOLOWER (*(++ptr
)))
1557 thissize
= strtoul (ptr
, &ptr
, 10);
1560 as_bad (_("bad size %d in type specifier"), thissize
);
1564 case '0': case '1': case '2': case '3': case '4':
1565 case '5': case '6': case '7': case '8': case '9':
1567 as_bad (_("unexpected type character `b' -- did you mean `bf'?"));
1574 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1580 /* .f is an abbreviation for .f32. */
1581 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1586 thissize
= strtoul (ptr
, &ptr
, 10);
1588 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1591 as_bad (_("bad size %d in type specifier"), thissize
);
1599 type
->el
[type
->elems
].type
= thistype
;
1600 type
->el
[type
->elems
].size
= thissize
;
1605 /* Empty/missing type is not a successful parse. */
1606 if (type
->elems
== 0)
1614 /* Errors may be set multiple times during parsing or bit encoding
1615 (particularly in the Neon bits), but usually the earliest error which is set
1616 will be the most meaningful. Avoid overwriting it with later (cascading)
1617 errors by calling this function. */
1620 first_error (const char *err
)
1626 /* Parse a single type, e.g. ".s32", leading period included. */
1628 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1631 struct neon_type optype
;
1635 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1637 if (optype
.elems
== 1)
1638 *vectype
= optype
.el
[0];
1641 first_error (_("only one type should be specified for operand"));
1647 first_error (_("vector type expected"));
1659 /* Special meanings for indices (which have a range of 0-7), which will fit into
1662 #define NEON_ALL_LANES 15
1663 #define NEON_INTERLEAVE_LANES 14
1665 /* Record a use of the given feature. */
1667 record_feature_use (const arm_feature_set
*feature
)
1670 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1672 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1675 /* If the given feature available in the selected CPU, mark it as used.
1676 Returns TRUE iff feature is available. */
1678 mark_feature_used (const arm_feature_set
*feature
)
1681 /* Do not support the use of MVE only instructions when in auto-detection or
1683 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1684 && ARM_CPU_IS_ANY (cpu_variant
))
1686 first_error (BAD_MVE_AUTO
);
1689 /* Ensure the option is valid on the current architecture. */
1690 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1693 /* Add the appropriate architecture feature for the barrier option used.
1695 record_feature_use (feature
);
1700 /* Parse either a register or a scalar, with an optional type. Return the
1701 register number, and optionally fill in the actual type of the register
1702 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1703 type/index information in *TYPEINFO. */
1706 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1707 enum arm_reg_type
*rtype
,
1708 struct neon_typed_alias
*typeinfo
)
1711 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1712 struct neon_typed_alias atype
;
1713 struct neon_type_el parsetype
;
1717 atype
.eltype
.type
= NT_invtype
;
1718 atype
.eltype
.size
= -1;
1720 /* Try alternate syntax for some types of register. Note these are mutually
1721 exclusive with the Neon syntax extensions. */
1724 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1732 /* Undo polymorphism when a set of register types may be accepted. */
1733 if ((type
== REG_TYPE_NDQ
1734 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1735 || (type
== REG_TYPE_VFSD
1736 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1737 || (type
== REG_TYPE_NSDQ
1738 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1739 || reg
->type
== REG_TYPE_NQ
))
1740 || (type
== REG_TYPE_NSD
1741 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1742 || (type
== REG_TYPE_MMXWC
1743 && (reg
->type
== REG_TYPE_MMXWCG
)))
1744 type
= (enum arm_reg_type
) reg
->type
;
1746 if (type
== REG_TYPE_MQ
)
1748 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1751 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1754 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1756 first_error (_("expected MVE register [q0..q7]"));
1761 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1762 && (type
== REG_TYPE_NQ
))
1766 if (type
!= reg
->type
)
1772 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1774 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1776 first_error (_("can't redefine type for operand"));
1779 atype
.defined
|= NTA_HASTYPE
;
1780 atype
.eltype
= parsetype
;
1783 if (skip_past_char (&str
, '[') == SUCCESS
)
1785 if (type
!= REG_TYPE_VFD
1786 && !(type
== REG_TYPE_VFS
1787 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1788 && !(type
== REG_TYPE_NQ
1789 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1791 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1792 first_error (_("only D and Q registers may be indexed"));
1794 first_error (_("only D registers may be indexed"));
1798 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1800 first_error (_("can't change index for operand"));
1804 atype
.defined
|= NTA_HASINDEX
;
1806 if (skip_past_char (&str
, ']') == SUCCESS
)
1807 atype
.index
= NEON_ALL_LANES
;
1812 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1814 if (exp
.X_op
!= O_constant
)
1816 first_error (_("constant expression required"));
1820 if (skip_past_char (&str
, ']') == FAIL
)
1823 atype
.index
= exp
.X_add_number
;
1838 /* Like arm_reg_parse, but also allow the following extra features:
1839 - If RTYPE is non-zero, return the (possibly restricted) type of the
1840 register (e.g. Neon double or quad reg when either has been requested).
1841 - If this is a Neon vector type with additional type information, fill
1842 in the struct pointed to by VECTYPE (if non-NULL).
1843 This function will fault on encountering a scalar. */
1846 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1847 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1849 struct neon_typed_alias atype
;
1851 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1856 /* Do not allow regname(... to parse as a register. */
1860 /* Do not allow a scalar (reg+index) to parse as a register. */
1861 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1863 first_error (_("register operand expected, but got scalar"));
1868 *vectype
= atype
.eltype
;
1875 #define NEON_SCALAR_REG(X) ((X) >> 4)
1876 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1878 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1879 have enough information to be able to do a good job bounds-checking. So, we
1880 just do easy checks here, and do further checks later. */
1883 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1884 arm_reg_type reg_type
)
1888 struct neon_typed_alias atype
;
1891 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1909 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1912 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1914 first_error (_("scalar must have an index"));
1917 else if (atype
.index
>= reg_size
/ elsize
)
1919 first_error (_("scalar index out of range"));
1924 *type
= atype
.eltype
;
1928 return reg
* 16 + atype
.index
;
1931 /* Types of registers in a list. */
1944 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1947 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1953 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1955 /* We come back here if we get ranges concatenated by '+' or '|'. */
1958 skip_whitespace (str
);
1971 const char apsr_str
[] = "apsr";
1972 int apsr_str_len
= strlen (apsr_str
);
1974 reg
= arm_reg_parse (&str
, REG_TYPE_RN
);
1975 if (etype
== REGLIST_CLRM
)
1977 if (reg
== REG_SP
|| reg
== REG_PC
)
1979 else if (reg
== FAIL
1980 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1981 && !ISALPHA (*(str
+ apsr_str_len
)))
1984 str
+= apsr_str_len
;
1989 first_error (_("r0-r12, lr or APSR expected"));
1993 else /* etype == REGLIST_RN. */
1997 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
2008 first_error (_("bad range in register list"));
2012 for (i
= cur_reg
+ 1; i
< reg
; i
++)
2014 if (range
& (1 << i
))
2016 (_("Warning: duplicated register (r%d) in register list"),
2024 if (range
& (1 << reg
))
2025 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
2027 else if (reg
<= cur_reg
)
2028 as_tsktsk (_("Warning: register range not in ascending order"));
2033 while (skip_past_comma (&str
) != FAIL
2034 || (in_range
= 1, *str
++ == '-'));
2037 if (skip_past_char (&str
, '}') == FAIL
)
2039 first_error (_("missing `}'"));
2043 else if (etype
== REGLIST_RN
)
2047 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
2050 if (exp
.X_op
== O_constant
)
2052 if (exp
.X_add_number
2053 != (exp
.X_add_number
& 0x0000ffff))
2055 inst
.error
= _("invalid register mask");
2059 if ((range
& exp
.X_add_number
) != 0)
2061 int regno
= range
& exp
.X_add_number
;
2064 regno
= (1 << regno
) - 1;
2066 (_("Warning: duplicated register (r%d) in register list"),
2070 range
|= exp
.X_add_number
;
2074 if (inst
.relocs
[0].type
!= 0)
2076 inst
.error
= _("expression too complex");
2080 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
2081 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
2082 inst
.relocs
[0].pc_rel
= 0;
2086 if (*str
== '|' || *str
== '+')
2092 while (another_range
);
2098 /* Parse a VFP register list. If the string is invalid return FAIL.
2099 Otherwise return the number of registers, and set PBASE to the first
2100 register. Parses registers of type ETYPE.
2101 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
2102 - Q registers can be used to specify pairs of D registers
2103 - { } can be omitted from around a singleton register list
2104 FIXME: This is not implemented, as it would require backtracking in
2107 This could be done (the meaning isn't really ambiguous), but doesn't
2108 fit in well with the current parsing framework.
2109 - 32 D registers may be used (also true for VFPv3).
2110 FIXME: Types are ignored in these register lists, which is probably a
2114 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2115 bfd_boolean
*partial_match
)
2120 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2124 unsigned long mask
= 0;
2126 bfd_boolean vpr_seen
= FALSE
;
2127 bfd_boolean expect_vpr
=
2128 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2130 if (skip_past_char (&str
, '{') == FAIL
)
2132 inst
.error
= _("expecting {");
2139 case REGLIST_VFP_S_VPR
:
2140 regtype
= REG_TYPE_VFS
;
2145 case REGLIST_VFP_D_VPR
:
2146 regtype
= REG_TYPE_VFD
;
2149 case REGLIST_NEON_D
:
2150 regtype
= REG_TYPE_NDQ
;
2157 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2159 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2160 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2164 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2167 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2174 base_reg
= max_regs
;
2175 *partial_match
= FALSE
;
2179 int setmask
= 1, addregs
= 1;
2180 const char vpr_str
[] = "vpr";
2181 int vpr_str_len
= strlen (vpr_str
);
2183 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2187 if (new_base
== FAIL
2188 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2189 && !ISALPHA (*(str
+ vpr_str_len
))
2195 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2199 first_error (_("VPR expected last"));
2202 else if (new_base
== FAIL
)
2204 if (regtype
== REG_TYPE_VFS
)
2205 first_error (_("VFP single precision register or VPR "
2207 else /* regtype == REG_TYPE_VFD. */
2208 first_error (_("VFP/Neon double precision register or VPR "
2213 else if (new_base
== FAIL
)
2215 first_error (_(reg_expected_msgs
[regtype
]));
2219 *partial_match
= TRUE
;
2223 if (new_base
>= max_regs
)
2225 first_error (_("register out of range in list"));
2229 /* Note: a value of 2 * n is returned for the register Q<n>. */
2230 if (regtype
== REG_TYPE_NQ
)
2236 if (new_base
< base_reg
)
2237 base_reg
= new_base
;
2239 if (mask
& (setmask
<< new_base
))
2241 first_error (_("invalid register list"));
2245 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2247 as_tsktsk (_("register list not in ascending order"));
2251 mask
|= setmask
<< new_base
;
2254 if (*str
== '-') /* We have the start of a range expression */
2260 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2263 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2267 if (high_range
>= max_regs
)
2269 first_error (_("register out of range in list"));
2273 if (regtype
== REG_TYPE_NQ
)
2274 high_range
= high_range
+ 1;
2276 if (high_range
<= new_base
)
2278 inst
.error
= _("register range not in ascending order");
2282 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2284 if (mask
& (setmask
<< new_base
))
2286 inst
.error
= _("invalid register list");
2290 mask
|= setmask
<< new_base
;
2295 while (skip_past_comma (&str
) != FAIL
);
2299 /* Sanity check -- should have raised a parse error above. */
2300 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2305 if (expect_vpr
&& !vpr_seen
)
2307 first_error (_("VPR expected last"));
2311 /* Final test -- the registers must be consecutive. */
2313 for (i
= 0; i
< count
; i
++)
2315 if ((mask
& (1u << i
)) == 0)
2317 inst
.error
= _("non-contiguous register range");
2327 /* True if two alias types are the same. */
2330 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2338 if (a
->defined
!= b
->defined
)
2341 if ((a
->defined
& NTA_HASTYPE
) != 0
2342 && (a
->eltype
.type
!= b
->eltype
.type
2343 || a
->eltype
.size
!= b
->eltype
.size
))
2346 if ((a
->defined
& NTA_HASINDEX
) != 0
2347 && (a
->index
!= b
->index
))
2353 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2354 The base register is put in *PBASE.
2355 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2357 The register stride (minus one) is put in bit 4 of the return value.
2358 Bits [6:5] encode the list length (minus one).
2359 The type of the list elements is put in *ELTYPE, if non-NULL. */
2361 #define NEON_LANE(X) ((X) & 0xf)
2362 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2363 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2366 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2368 struct neon_type_el
*eltype
)
2375 int leading_brace
= 0;
2376 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2377 const char *const incr_error
= mve
? _("register stride must be 1") :
2378 _("register stride must be 1 or 2");
2379 const char *const type_error
= _("mismatched element/structure types in list");
2380 struct neon_typed_alias firsttype
;
2381 firsttype
.defined
= 0;
2382 firsttype
.eltype
.type
= NT_invtype
;
2383 firsttype
.eltype
.size
= -1;
2384 firsttype
.index
= -1;
2386 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2391 struct neon_typed_alias atype
;
2393 rtype
= REG_TYPE_MQ
;
2394 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2398 first_error (_(reg_expected_msgs
[rtype
]));
2405 if (rtype
== REG_TYPE_NQ
)
2411 else if (reg_incr
== -1)
2413 reg_incr
= getreg
- base_reg
;
2414 if (reg_incr
< 1 || reg_incr
> 2)
2416 first_error (_(incr_error
));
2420 else if (getreg
!= base_reg
+ reg_incr
* count
)
2422 first_error (_(incr_error
));
2426 if (! neon_alias_types_same (&atype
, &firsttype
))
2428 first_error (_(type_error
));
2432 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2436 struct neon_typed_alias htype
;
2437 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2439 lane
= NEON_INTERLEAVE_LANES
;
2440 else if (lane
!= NEON_INTERLEAVE_LANES
)
2442 first_error (_(type_error
));
2447 else if (reg_incr
!= 1)
2449 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2453 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2456 first_error (_(reg_expected_msgs
[rtype
]));
2459 if (! neon_alias_types_same (&htype
, &firsttype
))
2461 first_error (_(type_error
));
2464 count
+= hireg
+ dregs
- getreg
;
2468 /* If we're using Q registers, we can't use [] or [n] syntax. */
2469 if (rtype
== REG_TYPE_NQ
)
2475 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2479 else if (lane
!= atype
.index
)
2481 first_error (_(type_error
));
2485 else if (lane
== -1)
2486 lane
= NEON_INTERLEAVE_LANES
;
2487 else if (lane
!= NEON_INTERLEAVE_LANES
)
2489 first_error (_(type_error
));
2494 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2496 /* No lane set by [x]. We must be interleaving structures. */
2498 lane
= NEON_INTERLEAVE_LANES
;
2501 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2502 || (count
> 1 && reg_incr
== -1))
2504 first_error (_("error parsing element/structure list"));
2508 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2510 first_error (_("expected }"));
2518 *eltype
= firsttype
.eltype
;
2523 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2526 /* Parse an explicit relocation suffix on an expression. This is
2527 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2528 arm_reloc_hsh contains no entries, so this function can only
2529 succeed if there is no () after the word. Returns -1 on error,
2530 BFD_RELOC_UNUSED if there wasn't any suffix. */
2533 parse_reloc (char **str
)
2535 struct reloc_entry
*r
;
2539 return BFD_RELOC_UNUSED
;
2544 while (*q
&& *q
!= ')' && *q
!= ',')
2549 if ((r
= (struct reloc_entry
*)
2550 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2557 /* Directives: register aliases. */
2559 static struct reg_entry
*
2560 insert_reg_alias (char *str
, unsigned number
, int type
)
2562 struct reg_entry
*new_reg
;
2565 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2567 if (new_reg
->builtin
)
2568 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2570 /* Only warn about a redefinition if it's not defined as the
2572 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2573 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2578 name
= xstrdup (str
);
2579 new_reg
= XNEW (struct reg_entry
);
2581 new_reg
->name
= name
;
2582 new_reg
->number
= number
;
2583 new_reg
->type
= type
;
2584 new_reg
->builtin
= FALSE
;
2585 new_reg
->neon
= NULL
;
2587 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2594 insert_neon_reg_alias (char *str
, int number
, int type
,
2595 struct neon_typed_alias
*atype
)
2597 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2601 first_error (_("attempt to redefine typed alias"));
2607 reg
->neon
= XNEW (struct neon_typed_alias
);
2608 *reg
->neon
= *atype
;
2612 /* Look for the .req directive. This is of the form:
2614 new_register_name .req existing_register_name
2616 If we find one, or if it looks sufficiently like one that we want to
2617 handle any error here, return TRUE. Otherwise return FALSE. */
2620 create_register_alias (char * newname
, char *p
)
2622 struct reg_entry
*old
;
2623 char *oldname
, *nbuf
;
2626 /* The input scrubber ensures that whitespace after the mnemonic is
2627 collapsed to single spaces. */
2629 if (strncmp (oldname
, " .req ", 6) != 0)
2633 if (*oldname
== '\0')
2636 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2639 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2643 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2644 the desired alias name, and p points to its end. If not, then
2645 the desired alias name is in the global original_case_string. */
2646 #ifdef TC_CASE_SENSITIVE
2649 newname
= original_case_string
;
2650 nlen
= strlen (newname
);
2653 nbuf
= xmemdup0 (newname
, nlen
);
2655 /* Create aliases under the new name as stated; an all-lowercase
2656 version of the new name; and an all-uppercase version of the new
2658 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2660 for (p
= nbuf
; *p
; p
++)
2663 if (strncmp (nbuf
, newname
, nlen
))
2665 /* If this attempt to create an additional alias fails, do not bother
2666 trying to create the all-lower case alias. We will fail and issue
2667 a second, duplicate error message. This situation arises when the
2668 programmer does something like:
2671 The second .req creates the "Foo" alias but then fails to create
2672 the artificial FOO alias because it has already been created by the
2674 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2681 for (p
= nbuf
; *p
; p
++)
2684 if (strncmp (nbuf
, newname
, nlen
))
2685 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2692 /* Create a Neon typed/indexed register alias using directives, e.g.:
2697 These typed registers can be used instead of the types specified after the
2698 Neon mnemonic, so long as all operands given have types. Types can also be
2699 specified directly, e.g.:
2700 vadd d0.s32, d1.s32, d2.s32 */
2703 create_neon_reg_alias (char *newname
, char *p
)
2705 enum arm_reg_type basetype
;
2706 struct reg_entry
*basereg
;
2707 struct reg_entry mybasereg
;
2708 struct neon_type ntype
;
2709 struct neon_typed_alias typeinfo
;
2710 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2713 typeinfo
.defined
= 0;
2714 typeinfo
.eltype
.type
= NT_invtype
;
2715 typeinfo
.eltype
.size
= -1;
2716 typeinfo
.index
= -1;
2720 if (strncmp (p
, " .dn ", 5) == 0)
2721 basetype
= REG_TYPE_VFD
;
2722 else if (strncmp (p
, " .qn ", 5) == 0)
2723 basetype
= REG_TYPE_NQ
;
2732 basereg
= arm_reg_parse_multi (&p
);
2734 if (basereg
&& basereg
->type
!= basetype
)
2736 as_bad (_("bad type for register"));
2740 if (basereg
== NULL
)
2743 /* Try parsing as an integer. */
2744 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2745 if (exp
.X_op
!= O_constant
)
2747 as_bad (_("expression must be constant"));
2750 basereg
= &mybasereg
;
2751 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2757 typeinfo
= *basereg
->neon
;
2759 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2761 /* We got a type. */
2762 if (typeinfo
.defined
& NTA_HASTYPE
)
2764 as_bad (_("can't redefine the type of a register alias"));
2768 typeinfo
.defined
|= NTA_HASTYPE
;
2769 if (ntype
.elems
!= 1)
2771 as_bad (_("you must specify a single type only"));
2774 typeinfo
.eltype
= ntype
.el
[0];
2777 if (skip_past_char (&p
, '[') == SUCCESS
)
2780 /* We got a scalar index. */
2782 if (typeinfo
.defined
& NTA_HASINDEX
)
2784 as_bad (_("can't redefine the index of a scalar alias"));
2788 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2790 if (exp
.X_op
!= O_constant
)
2792 as_bad (_("scalar index must be constant"));
2796 typeinfo
.defined
|= NTA_HASINDEX
;
2797 typeinfo
.index
= exp
.X_add_number
;
2799 if (skip_past_char (&p
, ']') == FAIL
)
2801 as_bad (_("expecting ]"));
2806 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2807 the desired alias name, and p points to its end. If not, then
2808 the desired alias name is in the global original_case_string. */
2809 #ifdef TC_CASE_SENSITIVE
2810 namelen
= nameend
- newname
;
2812 newname
= original_case_string
;
2813 namelen
= strlen (newname
);
2816 namebuf
= xmemdup0 (newname
, namelen
);
2818 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2819 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2821 /* Insert name in all uppercase. */
2822 for (p
= namebuf
; *p
; p
++)
2825 if (strncmp (namebuf
, newname
, namelen
))
2826 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2827 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2829 /* Insert name in all lowercase. */
2830 for (p
= namebuf
; *p
; p
++)
2833 if (strncmp (namebuf
, newname
, namelen
))
2834 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2835 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2841 /* Should never be called, as .req goes between the alias and the
2842 register name, not at the beginning of the line. */
2845 s_req (int a ATTRIBUTE_UNUSED
)
2847 as_bad (_("invalid syntax for .req directive"));
2851 s_dn (int a ATTRIBUTE_UNUSED
)
2853 as_bad (_("invalid syntax for .dn directive"));
2857 s_qn (int a ATTRIBUTE_UNUSED
)
2859 as_bad (_("invalid syntax for .qn directive"));
2862 /* The .unreq directive deletes an alias which was previously defined
2863 by .req. For example:
2869 s_unreq (int a ATTRIBUTE_UNUSED
)
2874 name
= input_line_pointer
;
2876 while (*input_line_pointer
!= 0
2877 && *input_line_pointer
!= ' '
2878 && *input_line_pointer
!= '\n')
2879 ++input_line_pointer
;
2881 saved_char
= *input_line_pointer
;
2882 *input_line_pointer
= 0;
2885 as_bad (_("invalid syntax for .unreq directive"));
2888 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2892 as_bad (_("unknown register alias '%s'"), name
);
2893 else if (reg
->builtin
)
2894 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2901 hash_delete (arm_reg_hsh
, name
, FALSE
);
2902 free ((char *) reg
->name
);
2907 /* Also locate the all upper case and all lower case versions.
2908 Do not complain if we cannot find one or the other as it
2909 was probably deleted above. */
2911 nbuf
= strdup (name
);
2912 for (p
= nbuf
; *p
; p
++)
2914 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2917 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2918 free ((char *) reg
->name
);
2924 for (p
= nbuf
; *p
; p
++)
2926 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2929 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2930 free ((char *) reg
->name
);
2940 *input_line_pointer
= saved_char
;
2941 demand_empty_rest_of_line ();
2944 /* Directives: Instruction set selection. */
2947 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2948 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2949 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2950 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2952 /* Create a new mapping symbol for the transition to STATE. */
2955 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2958 const char * symname
;
2965 type
= BSF_NO_FLAGS
;
2969 type
= BSF_NO_FLAGS
;
2973 type
= BSF_NO_FLAGS
;
2979 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2980 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2985 THUMB_SET_FUNC (symbolP
, 0);
2986 ARM_SET_THUMB (symbolP
, 0);
2987 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2991 THUMB_SET_FUNC (symbolP
, 1);
2992 ARM_SET_THUMB (symbolP
, 1);
2993 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3001 /* Save the mapping symbols for future reference. Also check that
3002 we do not place two mapping symbols at the same offset within a
3003 frag. We'll handle overlap between frags in
3004 check_mapping_symbols.
3006 If .fill or other data filling directive generates zero sized data,
3007 the mapping symbol for the following code will have the same value
3008 as the one generated for the data filling directive. In this case,
3009 we replace the old symbol with the new one at the same address. */
3012 if (frag
->tc_frag_data
.first_map
!= NULL
)
3014 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
3015 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
3017 frag
->tc_frag_data
.first_map
= symbolP
;
3019 if (frag
->tc_frag_data
.last_map
!= NULL
)
3021 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
3022 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
3023 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
3025 frag
->tc_frag_data
.last_map
= symbolP
;
3028 /* We must sometimes convert a region marked as code to data during
3029 code alignment, if an odd number of bytes have to be padded. The
3030 code mapping symbol is pushed to an aligned address. */
3033 insert_data_mapping_symbol (enum mstate state
,
3034 valueT value
, fragS
*frag
, offsetT bytes
)
3036 /* If there was already a mapping symbol, remove it. */
3037 if (frag
->tc_frag_data
.last_map
!= NULL
3038 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
3040 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
3044 know (frag
->tc_frag_data
.first_map
== symp
);
3045 frag
->tc_frag_data
.first_map
= NULL
;
3047 frag
->tc_frag_data
.last_map
= NULL
;
3048 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
3051 make_mapping_symbol (MAP_DATA
, value
, frag
);
3052 make_mapping_symbol (state
, value
+ bytes
, frag
);
3055 static void mapping_state_2 (enum mstate state
, int max_chars
);
3057 /* Set the mapping state to STATE. Only call this when about to
3058 emit some STATE bytes to the file. */
3060 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
3062 mapping_state (enum mstate state
)
3064 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3066 if (mapstate
== state
)
3067 /* The mapping symbol has already been emitted.
3068 There is nothing else to do. */
3071 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
3073 All ARM instructions require 4-byte alignment.
3074 (Almost) all Thumb instructions require 2-byte alignment.
3076 When emitting instructions into any section, mark the section
3079 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
3080 but themselves require 2-byte alignment; this applies to some
3081 PC- relative forms. However, these cases will involve implicit
3082 literal pool generation or an explicit .align >=2, both of
3083 which will cause the section to me marked with sufficient
3084 alignment. Thus, we don't handle those cases here. */
3085 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
3087 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
3088 /* This case will be evaluated later. */
3091 mapping_state_2 (state
, 0);
3094 /* Same as mapping_state, but MAX_CHARS bytes have already been
3095 allocated. Put the mapping symbol that far back. */
3098 mapping_state_2 (enum mstate state
, int max_chars
)
3100 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
3102 if (!SEG_NORMAL (now_seg
))
3105 if (mapstate
== state
)
3106 /* The mapping symbol has already been emitted.
3107 There is nothing else to do. */
3110 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3111 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3113 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3114 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3117 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3120 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3121 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3125 #define mapping_state(x) ((void)0)
3126 #define mapping_state_2(x, y) ((void)0)
3129 /* Find the real, Thumb encoded start of a Thumb function. */
3133 find_real_start (symbolS
* symbolP
)
3136 const char * name
= S_GET_NAME (symbolP
);
3137 symbolS
* new_target
;
3139 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3140 #define STUB_NAME ".real_start_of"
3145 /* The compiler may generate BL instructions to local labels because
3146 it needs to perform a branch to a far away location. These labels
3147 do not have a corresponding ".real_start_of" label. We check
3148 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3149 the ".real_start_of" convention for nonlocal branches. */
3150 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3153 real_start
= concat (STUB_NAME
, name
, NULL
);
3154 new_target
= symbol_find (real_start
);
3157 if (new_target
== NULL
)
3159 as_warn (_("Failed to find real start of function: %s\n"), name
);
3160 new_target
= symbolP
;
3168 opcode_select (int width
)
3175 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3176 as_bad (_("selected processor does not support THUMB opcodes"));
3179 /* No need to force the alignment, since we will have been
3180 coming from ARM mode, which is word-aligned. */
3181 record_alignment (now_seg
, 1);
3188 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3189 as_bad (_("selected processor does not support ARM opcodes"));
3194 frag_align (2, 0, 0);
3196 record_alignment (now_seg
, 1);
3201 as_bad (_("invalid instruction size selected (%d)"), width
);
3206 s_arm (int ignore ATTRIBUTE_UNUSED
)
3209 demand_empty_rest_of_line ();
3213 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3216 demand_empty_rest_of_line ();
3220 s_code (int unused ATTRIBUTE_UNUSED
)
3224 temp
= get_absolute_expression ();
3229 opcode_select (temp
);
3233 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3238 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3240 /* If we are not already in thumb mode go into it, EVEN if
3241 the target processor does not support thumb instructions.
3242 This is used by gcc/config/arm/lib1funcs.asm for example
3243 to compile interworking support functions even if the
3244 target processor should not support interworking. */
3248 record_alignment (now_seg
, 1);
3251 demand_empty_rest_of_line ();
3255 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3259 /* The following label is the name/address of the start of a Thumb function.
3260 We need to know this for the interworking support. */
3261 label_is_thumb_function_name
= TRUE
;
3264 /* Perform a .set directive, but also mark the alias as
3265 being a thumb function. */
3268 s_thumb_set (int equiv
)
3270 /* XXX the following is a duplicate of the code for s_set() in read.c
3271 We cannot just call that code as we need to get at the symbol that
3278 /* Especial apologies for the random logic:
3279 This just grew, and could be parsed much more simply!
3281 delim
= get_symbol_name (& name
);
3282 end_name
= input_line_pointer
;
3283 (void) restore_line_pointer (delim
);
3285 if (*input_line_pointer
!= ',')
3288 as_bad (_("expected comma after name \"%s\""), name
);
3290 ignore_rest_of_line ();
3294 input_line_pointer
++;
3297 if (name
[0] == '.' && name
[1] == '\0')
3299 /* XXX - this should not happen to .thumb_set. */
3303 if ((symbolP
= symbol_find (name
)) == NULL
3304 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3307 /* When doing symbol listings, play games with dummy fragments living
3308 outside the normal fragment chain to record the file and line info
3310 if (listing
& LISTING_SYMBOLS
)
3312 extern struct list_info_struct
* listing_tail
;
3313 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3315 memset (dummy_frag
, 0, sizeof (fragS
));
3316 dummy_frag
->fr_type
= rs_fill
;
3317 dummy_frag
->line
= listing_tail
;
3318 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3319 dummy_frag
->fr_symbol
= symbolP
;
3323 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3326 /* "set" symbols are local unless otherwise specified. */
3327 SF_SET_LOCAL (symbolP
);
3328 #endif /* OBJ_COFF */
3329 } /* Make a new symbol. */
3331 symbol_table_insert (symbolP
);
3336 && S_IS_DEFINED (symbolP
)
3337 && S_GET_SEGMENT (symbolP
) != reg_section
)
3338 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3340 pseudo_set (symbolP
);
3342 demand_empty_rest_of_line ();
3344 /* XXX Now we come to the Thumb specific bit of code. */
3346 THUMB_SET_FUNC (symbolP
, 1);
3347 ARM_SET_THUMB (symbolP
, 1);
3348 #if defined OBJ_ELF || defined OBJ_COFF
3349 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3353 /* Directives: Mode selection. */
3355 /* .syntax [unified|divided] - choose the new unified syntax
3356 (same for Arm and Thumb encoding, modulo slight differences in what
3357 can be represented) or the old divergent syntax for each mode. */
3359 s_syntax (int unused ATTRIBUTE_UNUSED
)
3363 delim
= get_symbol_name (& name
);
3365 if (!strcasecmp (name
, "unified"))
3366 unified_syntax
= TRUE
;
3367 else if (!strcasecmp (name
, "divided"))
3368 unified_syntax
= FALSE
;
3371 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3374 (void) restore_line_pointer (delim
);
3375 demand_empty_rest_of_line ();
3378 /* Directives: sectioning and alignment. */
3381 s_bss (int ignore ATTRIBUTE_UNUSED
)
3383 /* We don't support putting frags in the BSS segment, we fake it by
3384 marking in_bss, then looking at s_skip for clues. */
3385 subseg_set (bss_section
, 0);
3386 demand_empty_rest_of_line ();
3388 #ifdef md_elf_section_change_hook
3389 md_elf_section_change_hook ();
3394 s_even (int ignore ATTRIBUTE_UNUSED
)
3396 /* Never make frag if expect extra pass. */
3398 frag_align (1, 0, 0);
3400 record_alignment (now_seg
, 1);
3402 demand_empty_rest_of_line ();
3405 /* Directives: CodeComposer Studio. */
3407 /* .ref (for CodeComposer Studio syntax only). */
3409 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3411 if (codecomposer_syntax
)
3412 ignore_rest_of_line ();
3414 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3417 /* If name is not NULL, then it is used for marking the beginning of a
3418 function, whereas if it is NULL then it means the function end. */
3420 asmfunc_debug (const char * name
)
3422 static const char * last_name
= NULL
;
3426 gas_assert (last_name
== NULL
);
3429 if (debug_type
== DEBUG_STABS
)
3430 stabs_generate_asm_func (name
, name
);
3434 gas_assert (last_name
!= NULL
);
3436 if (debug_type
== DEBUG_STABS
)
3437 stabs_generate_asm_endfunc (last_name
, last_name
);
3444 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3446 if (codecomposer_syntax
)
3448 switch (asmfunc_state
)
3450 case OUTSIDE_ASMFUNC
:
3451 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3454 case WAITING_ASMFUNC_NAME
:
3455 as_bad (_(".asmfunc repeated."));
3458 case WAITING_ENDASMFUNC
:
3459 as_bad (_(".asmfunc without function."));
3462 demand_empty_rest_of_line ();
3465 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3469 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3471 if (codecomposer_syntax
)
3473 switch (asmfunc_state
)
3475 case OUTSIDE_ASMFUNC
:
3476 as_bad (_(".endasmfunc without a .asmfunc."));
3479 case WAITING_ASMFUNC_NAME
:
3480 as_bad (_(".endasmfunc without function."));
3483 case WAITING_ENDASMFUNC
:
3484 asmfunc_state
= OUTSIDE_ASMFUNC
;
3485 asmfunc_debug (NULL
);
3488 demand_empty_rest_of_line ();
3491 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3495 s_ccs_def (int name
)
3497 if (codecomposer_syntax
)
3500 as_bad (_(".def pseudo-op only available with -mccs flag."));
3503 /* Directives: Literal pools. */
3505 static literal_pool
*
3506 find_literal_pool (void)
3508 literal_pool
* pool
;
3510 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3512 if (pool
->section
== now_seg
3513 && pool
->sub_section
== now_subseg
)
3520 static literal_pool
*
3521 find_or_make_literal_pool (void)
3523 /* Next literal pool ID number. */
3524 static unsigned int latest_pool_num
= 1;
3525 literal_pool
* pool
;
3527 pool
= find_literal_pool ();
3531 /* Create a new pool. */
3532 pool
= XNEW (literal_pool
);
3536 pool
->next_free_entry
= 0;
3537 pool
->section
= now_seg
;
3538 pool
->sub_section
= now_subseg
;
3539 pool
->next
= list_of_pools
;
3540 pool
->symbol
= NULL
;
3541 pool
->alignment
= 2;
3543 /* Add it to the list. */
3544 list_of_pools
= pool
;
3547 /* New pools, and emptied pools, will have a NULL symbol. */
3548 if (pool
->symbol
== NULL
)
3550 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3551 (valueT
) 0, &zero_address_frag
);
3552 pool
->id
= latest_pool_num
++;
3559 /* Add the literal in the global 'inst'
3560 structure to the relevant literal pool. */
3563 add_to_lit_pool (unsigned int nbytes
)
3565 #define PADDING_SLOT 0x1
3566 #define LIT_ENTRY_SIZE_MASK 0xFF
3567 literal_pool
* pool
;
3568 unsigned int entry
, pool_size
= 0;
3569 bfd_boolean padding_slot_p
= FALSE
;
3575 imm1
= inst
.operands
[1].imm
;
3576 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3577 : inst
.relocs
[0].exp
.X_unsigned
? 0
3578 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3579 if (target_big_endian
)
3582 imm2
= inst
.operands
[1].imm
;
3586 pool
= find_or_make_literal_pool ();
3588 /* Check if this literal value is already in the pool. */
3589 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3593 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3594 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3595 && (pool
->literals
[entry
].X_add_number
3596 == inst
.relocs
[0].exp
.X_add_number
)
3597 && (pool
->literals
[entry
].X_md
== nbytes
)
3598 && (pool
->literals
[entry
].X_unsigned
3599 == inst
.relocs
[0].exp
.X_unsigned
))
3602 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3603 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3604 && (pool
->literals
[entry
].X_add_number
3605 == inst
.relocs
[0].exp
.X_add_number
)
3606 && (pool
->literals
[entry
].X_add_symbol
3607 == inst
.relocs
[0].exp
.X_add_symbol
)
3608 && (pool
->literals
[entry
].X_op_symbol
3609 == inst
.relocs
[0].exp
.X_op_symbol
)
3610 && (pool
->literals
[entry
].X_md
== nbytes
))
3613 else if ((nbytes
== 8)
3614 && !(pool_size
& 0x7)
3615 && ((entry
+ 1) != pool
->next_free_entry
)
3616 && (pool
->literals
[entry
].X_op
== O_constant
)
3617 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3618 && (pool
->literals
[entry
].X_unsigned
3619 == inst
.relocs
[0].exp
.X_unsigned
)
3620 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3621 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3622 && (pool
->literals
[entry
+ 1].X_unsigned
3623 == inst
.relocs
[0].exp
.X_unsigned
))
3626 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3627 if (padding_slot_p
&& (nbytes
== 4))
3633 /* Do we need to create a new entry? */
3634 if (entry
== pool
->next_free_entry
)
3636 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3638 inst
.error
= _("literal pool overflow");
3644 /* For 8-byte entries, we align to an 8-byte boundary,
3645 and split it into two 4-byte entries, because on 32-bit
3646 host, 8-byte constants are treated as big num, thus
3647 saved in "generic_bignum" which will be overwritten
3648 by later assignments.
3650 We also need to make sure there is enough space for
3653 We also check to make sure the literal operand is a
3655 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3656 || inst
.relocs
[0].exp
.X_op
== O_big
))
3658 inst
.error
= _("invalid type for literal pool");
3661 else if (pool_size
& 0x7)
3663 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3665 inst
.error
= _("literal pool overflow");
3669 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3670 pool
->literals
[entry
].X_op
= O_constant
;
3671 pool
->literals
[entry
].X_add_number
= 0;
3672 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3673 pool
->next_free_entry
+= 1;
3676 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3678 inst
.error
= _("literal pool overflow");
3682 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3683 pool
->literals
[entry
].X_op
= O_constant
;
3684 pool
->literals
[entry
].X_add_number
= imm1
;
3685 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3686 pool
->literals
[entry
++].X_md
= 4;
3687 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3688 pool
->literals
[entry
].X_op
= O_constant
;
3689 pool
->literals
[entry
].X_add_number
= imm2
;
3690 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3691 pool
->literals
[entry
].X_md
= 4;
3692 pool
->alignment
= 3;
3693 pool
->next_free_entry
+= 1;
3697 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3698 pool
->literals
[entry
].X_md
= 4;
3702 /* PR ld/12974: Record the location of the first source line to reference
3703 this entry in the literal pool. If it turns out during linking that the
3704 symbol does not exist we will be able to give an accurate line number for
3705 the (first use of the) missing reference. */
3706 if (debug_type
== DEBUG_DWARF2
)
3707 dwarf2_where (pool
->locs
+ entry
);
3709 pool
->next_free_entry
+= 1;
3711 else if (padding_slot_p
)
3713 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3714 pool
->literals
[entry
].X_md
= nbytes
;
3717 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3718 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3719 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3725 tc_start_label_without_colon (void)
3727 bfd_boolean ret
= TRUE
;
3729 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3731 const char *label
= input_line_pointer
;
3733 while (!is_end_of_line
[(int) label
[-1]])
3738 as_bad (_("Invalid label '%s'"), label
);
3742 asmfunc_debug (label
);
3744 asmfunc_state
= WAITING_ENDASMFUNC
;
3750 /* Can't use symbol_new here, so have to create a symbol and then at
3751 a later date assign it a value. That's what these functions do. */
3754 symbol_locate (symbolS
* symbolP
,
3755 const char * name
, /* It is copied, the caller can modify. */
3756 segT segment
, /* Segment identifier (SEG_<something>). */
3757 valueT valu
, /* Symbol value. */
3758 fragS
* frag
) /* Associated fragment. */
3761 char * preserved_copy_of_name
;
3763 name_length
= strlen (name
) + 1; /* +1 for \0. */
3764 obstack_grow (¬es
, name
, name_length
);
3765 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3767 #ifdef tc_canonicalize_symbol_name
3768 preserved_copy_of_name
=
3769 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3772 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3774 S_SET_SEGMENT (symbolP
, segment
);
3775 S_SET_VALUE (symbolP
, valu
);
3776 symbol_clear_list_pointers (symbolP
);
3778 symbol_set_frag (symbolP
, frag
);
3780 /* Link to end of symbol chain. */
3782 extern int symbol_table_frozen
;
3784 if (symbol_table_frozen
)
3788 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3790 obj_symbol_new_hook (symbolP
);
3792 #ifdef tc_symbol_new_hook
3793 tc_symbol_new_hook (symbolP
);
3797 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3798 #endif /* DEBUG_SYMS */
3802 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3805 literal_pool
* pool
;
3808 pool
= find_literal_pool ();
3810 || pool
->symbol
== NULL
3811 || pool
->next_free_entry
== 0)
3814 /* Align pool as you have word accesses.
3815 Only make a frag if we have to. */
3817 frag_align (pool
->alignment
, 0, 0);
3819 record_alignment (now_seg
, 2);
3822 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3823 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3825 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3827 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3828 (valueT
) frag_now_fix (), frag_now
);
3829 symbol_table_insert (pool
->symbol
);
3831 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3833 #if defined OBJ_COFF || defined OBJ_ELF
3834 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3837 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3840 if (debug_type
== DEBUG_DWARF2
)
3841 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3843 /* First output the expression in the instruction to the pool. */
3844 emit_expr (&(pool
->literals
[entry
]),
3845 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3848 /* Mark the pool as empty. */
3849 pool
->next_free_entry
= 0;
3850 pool
->symbol
= NULL
;
3854 /* Forward declarations for functions below, in the MD interface
3856 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3857 static valueT
create_unwind_entry (int);
3858 static void start_unwind_section (const segT
, int);
3859 static void add_unwind_opcode (valueT
, int);
3860 static void flush_pending_unwind (void);
3862 /* Directives: Data. */
3865 s_arm_elf_cons (int nbytes
)
3869 #ifdef md_flush_pending_output
3870 md_flush_pending_output ();
3873 if (is_it_end_of_statement ())
3875 demand_empty_rest_of_line ();
3879 #ifdef md_cons_align
3880 md_cons_align (nbytes
);
3883 mapping_state (MAP_DATA
);
3887 char *base
= input_line_pointer
;
3891 if (exp
.X_op
!= O_symbol
)
3892 emit_expr (&exp
, (unsigned int) nbytes
);
3895 char *before_reloc
= input_line_pointer
;
3896 reloc
= parse_reloc (&input_line_pointer
);
3899 as_bad (_("unrecognized relocation suffix"));
3900 ignore_rest_of_line ();
3903 else if (reloc
== BFD_RELOC_UNUSED
)
3904 emit_expr (&exp
, (unsigned int) nbytes
);
3907 reloc_howto_type
*howto
= (reloc_howto_type
*)
3908 bfd_reloc_type_lookup (stdoutput
,
3909 (bfd_reloc_code_real_type
) reloc
);
3910 int size
= bfd_get_reloc_size (howto
);
3912 if (reloc
== BFD_RELOC_ARM_PLT32
)
3914 as_bad (_("(plt) is only valid on branch targets"));
3915 reloc
= BFD_RELOC_UNUSED
;
3920 as_bad (ngettext ("%s relocations do not fit in %d byte",
3921 "%s relocations do not fit in %d bytes",
3923 howto
->name
, nbytes
);
3926 /* We've parsed an expression stopping at O_symbol.
3927 But there may be more expression left now that we
3928 have parsed the relocation marker. Parse it again.
3929 XXX Surely there is a cleaner way to do this. */
3930 char *p
= input_line_pointer
;
3932 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3934 memcpy (save_buf
, base
, input_line_pointer
- base
);
3935 memmove (base
+ (input_line_pointer
- before_reloc
),
3936 base
, before_reloc
- base
);
3938 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3940 memcpy (base
, save_buf
, p
- base
);
3942 offset
= nbytes
- size
;
3943 p
= frag_more (nbytes
);
3944 memset (p
, 0, nbytes
);
3945 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3946 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3952 while (*input_line_pointer
++ == ',');
3954 /* Put terminator back into stream. */
3955 input_line_pointer
--;
3956 demand_empty_rest_of_line ();
3959 /* Emit an expression containing a 32-bit thumb instruction.
3960 Implementation based on put_thumb32_insn. */
3963 emit_thumb32_expr (expressionS
* exp
)
3965 expressionS exp_high
= *exp
;
3967 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3968 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3969 exp
->X_add_number
&= 0xffff;
3970 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3973 /* Guess the instruction size based on the opcode. */
3976 thumb_insn_size (int opcode
)
3978 if ((unsigned int) opcode
< 0xe800u
)
3980 else if ((unsigned int) opcode
>= 0xe8000000u
)
3987 emit_insn (expressionS
*exp
, int nbytes
)
3991 if (exp
->X_op
== O_constant
)
3996 size
= thumb_insn_size (exp
->X_add_number
);
4000 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
4002 as_bad (_(".inst.n operand too big. "\
4003 "Use .inst.w instead"));
4008 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
4009 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
4011 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
4013 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
4014 emit_thumb32_expr (exp
);
4016 emit_expr (exp
, (unsigned int) size
);
4018 it_fsm_post_encode ();
4022 as_bad (_("cannot determine Thumb instruction size. " \
4023 "Use .inst.n/.inst.w instead"));
4026 as_bad (_("constant expression required"));
4031 /* Like s_arm_elf_cons but do not use md_cons_align and
4032 set the mapping state to MAP_ARM/MAP_THUMB. */
4035 s_arm_elf_inst (int nbytes
)
4037 if (is_it_end_of_statement ())
4039 demand_empty_rest_of_line ();
4043 /* Calling mapping_state () here will not change ARM/THUMB,
4044 but will ensure not to be in DATA state. */
4047 mapping_state (MAP_THUMB
);
4052 as_bad (_("width suffixes are invalid in ARM mode"));
4053 ignore_rest_of_line ();
4059 mapping_state (MAP_ARM
);
4068 if (! emit_insn (& exp
, nbytes
))
4070 ignore_rest_of_line ();
4074 while (*input_line_pointer
++ == ',');
4076 /* Put terminator back into stream. */
4077 input_line_pointer
--;
4078 demand_empty_rest_of_line ();
4081 /* Parse a .rel31 directive. */
4084 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
4091 if (*input_line_pointer
== '1')
4092 highbit
= 0x80000000;
4093 else if (*input_line_pointer
!= '0')
4094 as_bad (_("expected 0 or 1"));
4096 input_line_pointer
++;
4097 if (*input_line_pointer
!= ',')
4098 as_bad (_("missing comma"));
4099 input_line_pointer
++;
4101 #ifdef md_flush_pending_output
4102 md_flush_pending_output ();
4105 #ifdef md_cons_align
4109 mapping_state (MAP_DATA
);
4114 md_number_to_chars (p
, highbit
, 4);
4115 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4116 BFD_RELOC_ARM_PREL31
);
4118 demand_empty_rest_of_line ();
4121 /* Directives: AEABI stack-unwind tables. */
4123 /* Parse an unwind_fnstart directive. Simply records the current location. */
4126 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4128 demand_empty_rest_of_line ();
4129 if (unwind
.proc_start
)
4131 as_bad (_("duplicate .fnstart directive"));
4135 /* Mark the start of the function. */
4136 unwind
.proc_start
= expr_build_dot ();
4138 /* Reset the rest of the unwind info. */
4139 unwind
.opcode_count
= 0;
4140 unwind
.table_entry
= NULL
;
4141 unwind
.personality_routine
= NULL
;
4142 unwind
.personality_index
= -1;
4143 unwind
.frame_size
= 0;
4144 unwind
.fp_offset
= 0;
4145 unwind
.fp_reg
= REG_SP
;
4147 unwind
.sp_restored
= 0;
4151 /* Parse a handlerdata directive. Creates the exception handling table entry
4152 for the function. */
4155 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4157 demand_empty_rest_of_line ();
4158 if (!unwind
.proc_start
)
4159 as_bad (MISSING_FNSTART
);
4161 if (unwind
.table_entry
)
4162 as_bad (_("duplicate .handlerdata directive"));
4164 create_unwind_entry (1);
4167 /* Parse an unwind_fnend directive. Generates the index table entry. */
4170 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4175 unsigned int marked_pr_dependency
;
4177 demand_empty_rest_of_line ();
4179 if (!unwind
.proc_start
)
4181 as_bad (_(".fnend directive without .fnstart"));
4185 /* Add eh table entry. */
4186 if (unwind
.table_entry
== NULL
)
4187 val
= create_unwind_entry (0);
4191 /* Add index table entry. This is two words. */
4192 start_unwind_section (unwind
.saved_seg
, 1);
4193 frag_align (2, 0, 0);
4194 record_alignment (now_seg
, 2);
4196 ptr
= frag_more (8);
4198 where
= frag_now_fix () - 8;
4200 /* Self relative offset of the function start. */
4201 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4202 BFD_RELOC_ARM_PREL31
);
4204 /* Indicate dependency on EHABI-defined personality routines to the
4205 linker, if it hasn't been done already. */
4206 marked_pr_dependency
4207 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4208 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4209 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4211 static const char *const name
[] =
4213 "__aeabi_unwind_cpp_pr0",
4214 "__aeabi_unwind_cpp_pr1",
4215 "__aeabi_unwind_cpp_pr2"
4217 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4218 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4219 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4220 |= 1 << unwind
.personality_index
;
4224 /* Inline exception table entry. */
4225 md_number_to_chars (ptr
+ 4, val
, 4);
4227 /* Self relative offset of the table entry. */
4228 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4229 BFD_RELOC_ARM_PREL31
);
4231 /* Restore the original section. */
4232 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4234 unwind
.proc_start
= NULL
;
4238 /* Parse an unwind_cantunwind directive. */
4241 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4243 demand_empty_rest_of_line ();
4244 if (!unwind
.proc_start
)
4245 as_bad (MISSING_FNSTART
);
4247 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4248 as_bad (_("personality routine specified for cantunwind frame"));
4250 unwind
.personality_index
= -2;
4254 /* Parse a personalityindex directive. */
4257 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4261 if (!unwind
.proc_start
)
4262 as_bad (MISSING_FNSTART
);
4264 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4265 as_bad (_("duplicate .personalityindex directive"));
4269 if (exp
.X_op
!= O_constant
4270 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4272 as_bad (_("bad personality routine number"));
4273 ignore_rest_of_line ();
4277 unwind
.personality_index
= exp
.X_add_number
;
4279 demand_empty_rest_of_line ();
4283 /* Parse a personality directive. */
4286 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4290 if (!unwind
.proc_start
)
4291 as_bad (MISSING_FNSTART
);
4293 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4294 as_bad (_("duplicate .personality directive"));
4296 c
= get_symbol_name (& name
);
4297 p
= input_line_pointer
;
4299 ++ input_line_pointer
;
4300 unwind
.personality_routine
= symbol_find_or_make (name
);
4302 demand_empty_rest_of_line ();
4306 /* Parse a directive saving core registers. */
4309 s_arm_unwind_save_core (void)
4315 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4318 as_bad (_("expected register list"));
4319 ignore_rest_of_line ();
4323 demand_empty_rest_of_line ();
4325 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4326 into .unwind_save {..., sp...}. We aren't bothered about the value of
4327 ip because it is clobbered by calls. */
4328 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4329 && (range
& 0x3000) == 0x1000)
4331 unwind
.opcode_count
--;
4332 unwind
.sp_restored
= 0;
4333 range
= (range
| 0x2000) & ~0x1000;
4334 unwind
.pending_offset
= 0;
4340 /* See if we can use the short opcodes. These pop a block of up to 8
4341 registers starting with r4, plus maybe r14. */
4342 for (n
= 0; n
< 8; n
++)
4344 /* Break at the first non-saved register. */
4345 if ((range
& (1 << (n
+ 4))) == 0)
4348 /* See if there are any other bits set. */
4349 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4351 /* Use the long form. */
4352 op
= 0x8000 | ((range
>> 4) & 0xfff);
4353 add_unwind_opcode (op
, 2);
4357 /* Use the short form. */
4359 op
= 0xa8; /* Pop r14. */
4361 op
= 0xa0; /* Do not pop r14. */
4363 add_unwind_opcode (op
, 1);
4370 op
= 0xb100 | (range
& 0xf);
4371 add_unwind_opcode (op
, 2);
4374 /* Record the number of bytes pushed. */
4375 for (n
= 0; n
< 16; n
++)
4377 if (range
& (1 << n
))
4378 unwind
.frame_size
+= 4;
4383 /* Parse a directive saving FPA registers. */
4386 s_arm_unwind_save_fpa (int reg
)
4392 /* Get Number of registers to transfer. */
4393 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4396 exp
.X_op
= O_illegal
;
4398 if (exp
.X_op
!= O_constant
)
4400 as_bad (_("expected , <constant>"));
4401 ignore_rest_of_line ();
4405 num_regs
= exp
.X_add_number
;
4407 if (num_regs
< 1 || num_regs
> 4)
4409 as_bad (_("number of registers must be in the range [1:4]"));
4410 ignore_rest_of_line ();
4414 demand_empty_rest_of_line ();
4419 op
= 0xb4 | (num_regs
- 1);
4420 add_unwind_opcode (op
, 1);
4425 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4426 add_unwind_opcode (op
, 2);
4428 unwind
.frame_size
+= num_regs
* 12;
4432 /* Parse a directive saving VFP registers for ARMv6 and above. */
4435 s_arm_unwind_save_vfp_armv6 (void)
4440 int num_vfpv3_regs
= 0;
4441 int num_regs_below_16
;
4442 bfd_boolean partial_match
;
4444 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4448 as_bad (_("expected register list"));
4449 ignore_rest_of_line ();
4453 demand_empty_rest_of_line ();
4455 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4456 than FSTMX/FLDMX-style ones). */
4458 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4460 num_vfpv3_regs
= count
;
4461 else if (start
+ count
> 16)
4462 num_vfpv3_regs
= start
+ count
- 16;
4464 if (num_vfpv3_regs
> 0)
4466 int start_offset
= start
> 16 ? start
- 16 : 0;
4467 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4468 add_unwind_opcode (op
, 2);
4471 /* Generate opcode for registers numbered in the range 0 .. 15. */
4472 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4473 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4474 if (num_regs_below_16
> 0)
4476 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4477 add_unwind_opcode (op
, 2);
4480 unwind
.frame_size
+= count
* 8;
4484 /* Parse a directive saving VFP registers for pre-ARMv6. */
4487 s_arm_unwind_save_vfp (void)
4492 bfd_boolean partial_match
;
4494 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4498 as_bad (_("expected register list"));
4499 ignore_rest_of_line ();
4503 demand_empty_rest_of_line ();
4508 op
= 0xb8 | (count
- 1);
4509 add_unwind_opcode (op
, 1);
4514 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4515 add_unwind_opcode (op
, 2);
4517 unwind
.frame_size
+= count
* 8 + 4;
4521 /* Parse a directive saving iWMMXt data registers. */
4524 s_arm_unwind_save_mmxwr (void)
4532 if (*input_line_pointer
== '{')
4533 input_line_pointer
++;
4537 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4541 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4546 as_tsktsk (_("register list not in ascending order"));
4549 if (*input_line_pointer
== '-')
4551 input_line_pointer
++;
4552 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4555 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4558 else if (reg
>= hi_reg
)
4560 as_bad (_("bad register range"));
4563 for (; reg
< hi_reg
; reg
++)
4567 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4569 skip_past_char (&input_line_pointer
, '}');
4571 demand_empty_rest_of_line ();
4573 /* Generate any deferred opcodes because we're going to be looking at
4575 flush_pending_unwind ();
4577 for (i
= 0; i
< 16; i
++)
4579 if (mask
& (1 << i
))
4580 unwind
.frame_size
+= 8;
4583 /* Attempt to combine with a previous opcode. We do this because gcc
4584 likes to output separate unwind directives for a single block of
4586 if (unwind
.opcode_count
> 0)
4588 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4589 if ((i
& 0xf8) == 0xc0)
4592 /* Only merge if the blocks are contiguous. */
4595 if ((mask
& 0xfe00) == (1 << 9))
4597 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4598 unwind
.opcode_count
--;
4601 else if (i
== 6 && unwind
.opcode_count
>= 2)
4603 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4607 op
= 0xffff << (reg
- 1);
4609 && ((mask
& op
) == (1u << (reg
- 1))))
4611 op
= (1 << (reg
+ i
+ 1)) - 1;
4612 op
&= ~((1 << reg
) - 1);
4614 unwind
.opcode_count
-= 2;
4621 /* We want to generate opcodes in the order the registers have been
4622 saved, ie. descending order. */
4623 for (reg
= 15; reg
>= -1; reg
--)
4625 /* Save registers in blocks. */
4627 || !(mask
& (1 << reg
)))
4629 /* We found an unsaved reg. Generate opcodes to save the
4636 op
= 0xc0 | (hi_reg
- 10);
4637 add_unwind_opcode (op
, 1);
4642 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4643 add_unwind_opcode (op
, 2);
4652 ignore_rest_of_line ();
4656 s_arm_unwind_save_mmxwcg (void)
4663 if (*input_line_pointer
== '{')
4664 input_line_pointer
++;
4666 skip_whitespace (input_line_pointer
);
4670 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4674 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4680 as_tsktsk (_("register list not in ascending order"));
4683 if (*input_line_pointer
== '-')
4685 input_line_pointer
++;
4686 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4689 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4692 else if (reg
>= hi_reg
)
4694 as_bad (_("bad register range"));
4697 for (; reg
< hi_reg
; reg
++)
4701 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4703 skip_past_char (&input_line_pointer
, '}');
4705 demand_empty_rest_of_line ();
4707 /* Generate any deferred opcodes because we're going to be looking at
4709 flush_pending_unwind ();
4711 for (reg
= 0; reg
< 16; reg
++)
4713 if (mask
& (1 << reg
))
4714 unwind
.frame_size
+= 4;
4717 add_unwind_opcode (op
, 2);
4720 ignore_rest_of_line ();
4724 /* Parse an unwind_save directive.
4725 If the argument is non-zero, this is a .vsave directive. */
4728 s_arm_unwind_save (int arch_v6
)
4731 struct reg_entry
*reg
;
4732 bfd_boolean had_brace
= FALSE
;
4734 if (!unwind
.proc_start
)
4735 as_bad (MISSING_FNSTART
);
4737 /* Figure out what sort of save we have. */
4738 peek
= input_line_pointer
;
4746 reg
= arm_reg_parse_multi (&peek
);
4750 as_bad (_("register expected"));
4751 ignore_rest_of_line ();
4760 as_bad (_("FPA .unwind_save does not take a register list"));
4761 ignore_rest_of_line ();
4764 input_line_pointer
= peek
;
4765 s_arm_unwind_save_fpa (reg
->number
);
4769 s_arm_unwind_save_core ();
4774 s_arm_unwind_save_vfp_armv6 ();
4776 s_arm_unwind_save_vfp ();
4779 case REG_TYPE_MMXWR
:
4780 s_arm_unwind_save_mmxwr ();
4783 case REG_TYPE_MMXWCG
:
4784 s_arm_unwind_save_mmxwcg ();
4788 as_bad (_(".unwind_save does not support this kind of register"));
4789 ignore_rest_of_line ();
4794 /* Parse an unwind_movsp directive. */
4797 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4803 if (!unwind
.proc_start
)
4804 as_bad (MISSING_FNSTART
);
4806 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4809 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4810 ignore_rest_of_line ();
4814 /* Optional constant. */
4815 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4817 if (immediate_for_directive (&offset
) == FAIL
)
4823 demand_empty_rest_of_line ();
4825 if (reg
== REG_SP
|| reg
== REG_PC
)
4827 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4831 if (unwind
.fp_reg
!= REG_SP
)
4832 as_bad (_("unexpected .unwind_movsp directive"));
4834 /* Generate opcode to restore the value. */
4836 add_unwind_opcode (op
, 1);
4838 /* Record the information for later. */
4839 unwind
.fp_reg
= reg
;
4840 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4841 unwind
.sp_restored
= 1;
4844 /* Parse an unwind_pad directive. */
4847 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4851 if (!unwind
.proc_start
)
4852 as_bad (MISSING_FNSTART
);
4854 if (immediate_for_directive (&offset
) == FAIL
)
4859 as_bad (_("stack increment must be multiple of 4"));
4860 ignore_rest_of_line ();
4864 /* Don't generate any opcodes, just record the details for later. */
4865 unwind
.frame_size
+= offset
;
4866 unwind
.pending_offset
+= offset
;
4868 demand_empty_rest_of_line ();
4871 /* Parse an unwind_setfp directive. */
4874 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4880 if (!unwind
.proc_start
)
4881 as_bad (MISSING_FNSTART
);
4883 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4884 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4887 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4889 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4891 as_bad (_("expected <reg>, <reg>"));
4892 ignore_rest_of_line ();
4896 /* Optional constant. */
4897 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4899 if (immediate_for_directive (&offset
) == FAIL
)
4905 demand_empty_rest_of_line ();
4907 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4909 as_bad (_("register must be either sp or set by a previous"
4910 "unwind_movsp directive"));
4914 /* Don't generate any opcodes, just record the information for later. */
4915 unwind
.fp_reg
= fp_reg
;
4917 if (sp_reg
== REG_SP
)
4918 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4920 unwind
.fp_offset
-= offset
;
4923 /* Parse an unwind_raw directive. */
4926 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4929 /* This is an arbitrary limit. */
4930 unsigned char op
[16];
4933 if (!unwind
.proc_start
)
4934 as_bad (MISSING_FNSTART
);
4937 if (exp
.X_op
== O_constant
4938 && skip_past_comma (&input_line_pointer
) != FAIL
)
4940 unwind
.frame_size
+= exp
.X_add_number
;
4944 exp
.X_op
= O_illegal
;
4946 if (exp
.X_op
!= O_constant
)
4948 as_bad (_("expected <offset>, <opcode>"));
4949 ignore_rest_of_line ();
4955 /* Parse the opcode. */
4960 as_bad (_("unwind opcode too long"));
4961 ignore_rest_of_line ();
4963 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4965 as_bad (_("invalid unwind opcode"));
4966 ignore_rest_of_line ();
4969 op
[count
++] = exp
.X_add_number
;
4971 /* Parse the next byte. */
4972 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4978 /* Add the opcode bytes in reverse order. */
4980 add_unwind_opcode (op
[count
], 1);
4982 demand_empty_rest_of_line ();
4986 /* Parse a .eabi_attribute directive. */
4989 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4991 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4993 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4994 attributes_set_explicitly
[tag
] = 1;
4997 /* Emit a tls fix for the symbol. */
5000 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
5004 #ifdef md_flush_pending_output
5005 md_flush_pending_output ();
5008 #ifdef md_cons_align
5012 /* Since we're just labelling the code, there's no need to define a
5015 p
= obstack_next_free (&frchain_now
->frch_obstack
);
5016 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
5017 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
5018 : BFD_RELOC_ARM_TLS_DESCSEQ
);
5020 #endif /* OBJ_ELF */
5022 static void s_arm_arch (int);
5023 static void s_arm_object_arch (int);
5024 static void s_arm_cpu (int);
5025 static void s_arm_fpu (int);
5026 static void s_arm_arch_extension (int);
5031 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
5038 if (exp
.X_op
== O_symbol
)
5039 exp
.X_op
= O_secrel
;
5041 emit_expr (&exp
, 4);
5043 while (*input_line_pointer
++ == ',');
5045 input_line_pointer
--;
5046 demand_empty_rest_of_line ();
5051 arm_is_largest_exponent_ok (int precision
)
5053 /* precision == 1 ensures that this will only return
5054 true for 16 bit floats. */
5055 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
5059 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
5063 enum fp_16bit_format new_format
;
5065 new_format
= ARM_FP16_FORMAT_DEFAULT
;
5067 name
= input_line_pointer
;
5068 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
5069 input_line_pointer
++;
5071 saved_char
= *input_line_pointer
;
5072 *input_line_pointer
= 0;
5074 if (strcasecmp (name
, "ieee") == 0)
5075 new_format
= ARM_FP16_FORMAT_IEEE
;
5076 else if (strcasecmp (name
, "alternative") == 0)
5077 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
5080 as_bad (_("unrecognised float16 format \"%s\""), name
);
5084 /* Only set fp16_format if it is still the default (aka not already
5086 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
5087 fp16_format
= new_format
;
5090 if (new_format
!= fp16_format
)
5091 as_warn (_("float16 format cannot be set more than once, ignoring."));
5095 *input_line_pointer
= saved_char
;
5096 ignore_rest_of_line ();
5099 /* This table describes all the machine specific pseudo-ops the assembler
5100 has to support. The fields are:
5101 pseudo-op name without dot
5102 function to call to execute this pseudo-op
5103 Integer arg to pass to the function. */
5105 const pseudo_typeS md_pseudo_table
[] =
5107 /* Never called because '.req' does not start a line. */
5108 { "req", s_req
, 0 },
5109 /* Following two are likewise never called. */
5112 { "unreq", s_unreq
, 0 },
5113 { "bss", s_bss
, 0 },
5114 { "align", s_align_ptwo
, 2 },
5115 { "arm", s_arm
, 0 },
5116 { "thumb", s_thumb
, 0 },
5117 { "code", s_code
, 0 },
5118 { "force_thumb", s_force_thumb
, 0 },
5119 { "thumb_func", s_thumb_func
, 0 },
5120 { "thumb_set", s_thumb_set
, 0 },
5121 { "even", s_even
, 0 },
5122 { "ltorg", s_ltorg
, 0 },
5123 { "pool", s_ltorg
, 0 },
5124 { "syntax", s_syntax
, 0 },
5125 { "cpu", s_arm_cpu
, 0 },
5126 { "arch", s_arm_arch
, 0 },
5127 { "object_arch", s_arm_object_arch
, 0 },
5128 { "fpu", s_arm_fpu
, 0 },
5129 { "arch_extension", s_arm_arch_extension
, 0 },
5131 { "word", s_arm_elf_cons
, 4 },
5132 { "long", s_arm_elf_cons
, 4 },
5133 { "inst.n", s_arm_elf_inst
, 2 },
5134 { "inst.w", s_arm_elf_inst
, 4 },
5135 { "inst", s_arm_elf_inst
, 0 },
5136 { "rel31", s_arm_rel31
, 0 },
5137 { "fnstart", s_arm_unwind_fnstart
, 0 },
5138 { "fnend", s_arm_unwind_fnend
, 0 },
5139 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5140 { "personality", s_arm_unwind_personality
, 0 },
5141 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5142 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5143 { "save", s_arm_unwind_save
, 0 },
5144 { "vsave", s_arm_unwind_save
, 1 },
5145 { "movsp", s_arm_unwind_movsp
, 0 },
5146 { "pad", s_arm_unwind_pad
, 0 },
5147 { "setfp", s_arm_unwind_setfp
, 0 },
5148 { "unwind_raw", s_arm_unwind_raw
, 0 },
5149 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5150 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5154 /* These are used for dwarf. */
5158 /* These are used for dwarf2. */
5159 { "file", dwarf2_directive_file
, 0 },
5160 { "loc", dwarf2_directive_loc
, 0 },
5161 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5163 { "extend", float_cons
, 'x' },
5164 { "ldouble", float_cons
, 'x' },
5165 { "packed", float_cons
, 'p' },
5166 { "bfloat16", float_cons
, 'b' },
5168 {"secrel32", pe_directive_secrel
, 0},
5171 /* These are for compatibility with CodeComposer Studio. */
5172 {"ref", s_ccs_ref
, 0},
5173 {"def", s_ccs_def
, 0},
5174 {"asmfunc", s_ccs_asmfunc
, 0},
5175 {"endasmfunc", s_ccs_endasmfunc
, 0},
5177 {"float16", float_cons
, 'h' },
5178 {"float16_format", set_fp16_format
, 0 },
5183 /* Parser functions used exclusively in instruction operands. */
5185 /* Generic immediate-value read function for use in insn parsing.
5186 STR points to the beginning of the immediate (the leading #);
5187 VAL receives the value; if the value is outside [MIN, MAX]
5188 issue an error. PREFIX_OPT is true if the immediate prefix is
5192 parse_immediate (char **str
, int *val
, int min
, int max
,
5193 bfd_boolean prefix_opt
)
5197 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5198 if (exp
.X_op
!= O_constant
)
5200 inst
.error
= _("constant expression required");
5204 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5206 inst
.error
= _("immediate value out of range");
5210 *val
= exp
.X_add_number
;
5214 /* Less-generic immediate-value read function with the possibility of loading a
5215 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5216 instructions. Puts the result directly in inst.operands[i]. */
5219 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5220 bfd_boolean allow_symbol_p
)
5223 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5226 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5228 if (exp_p
->X_op
== O_constant
)
5230 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5231 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5232 O_constant. We have to be careful not to break compilation for
5233 32-bit X_add_number, though. */
5234 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5236 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5237 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5239 inst
.operands
[i
].regisimm
= 1;
5242 else if (exp_p
->X_op
== O_big
5243 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5245 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5247 /* Bignums have their least significant bits in
5248 generic_bignum[0]. Make sure we put 32 bits in imm and
5249 32 bits in reg, in a (hopefully) portable way. */
5250 gas_assert (parts
!= 0);
5252 /* Make sure that the number is not too big.
5253 PR 11972: Bignums can now be sign-extended to the
5254 size of a .octa so check that the out of range bits
5255 are all zero or all one. */
5256 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5258 LITTLENUM_TYPE m
= -1;
5260 if (generic_bignum
[parts
* 2] != 0
5261 && generic_bignum
[parts
* 2] != m
)
5264 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5265 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5269 inst
.operands
[i
].imm
= 0;
5270 for (j
= 0; j
< parts
; j
++, idx
++)
5271 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5272 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5273 inst
.operands
[i
].reg
= 0;
5274 for (j
= 0; j
< parts
; j
++, idx
++)
5275 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5276 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5277 inst
.operands
[i
].regisimm
= 1;
5279 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5287 /* Returns the pseudo-register number of an FPA immediate constant,
5288 or FAIL if there isn't a valid constant here. */
5291 parse_fpa_immediate (char ** str
)
5293 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5299 /* First try and match exact strings, this is to guarantee
5300 that some formats will work even for cross assembly. */
5302 for (i
= 0; fp_const
[i
]; i
++)
5304 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5308 *str
+= strlen (fp_const
[i
]);
5309 if (is_end_of_line
[(unsigned char) **str
])
5315 /* Just because we didn't get a match doesn't mean that the constant
5316 isn't valid, just that it is in a format that we don't
5317 automatically recognize. Try parsing it with the standard
5318 expression routines. */
5320 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5322 /* Look for a raw floating point number. */
5323 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5324 && is_end_of_line
[(unsigned char) *save_in
])
5326 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5328 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5330 if (words
[j
] != fp_values
[i
][j
])
5334 if (j
== MAX_LITTLENUMS
)
5342 /* Try and parse a more complex expression, this will probably fail
5343 unless the code uses a floating point prefix (eg "0f"). */
5344 save_in
= input_line_pointer
;
5345 input_line_pointer
= *str
;
5346 if (expression (&exp
) == absolute_section
5347 && exp
.X_op
== O_big
5348 && exp
.X_add_number
< 0)
5350 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5352 #define X_PRECISION 5
5353 #define E_PRECISION 15L
5354 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5356 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5358 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5360 if (words
[j
] != fp_values
[i
][j
])
5364 if (j
== MAX_LITTLENUMS
)
5366 *str
= input_line_pointer
;
5367 input_line_pointer
= save_in
;
5374 *str
= input_line_pointer
;
5375 input_line_pointer
= save_in
;
5376 inst
.error
= _("invalid FPA immediate expression");
5380 /* Returns 1 if a number has "quarter-precision" float format
5381 0baBbbbbbc defgh000 00000000 00000000. */
5384 is_quarter_float (unsigned imm
)
5386 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5387 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5391 /* Detect the presence of a floating point or integer zero constant,
5395 parse_ifimm_zero (char **in
)
5399 if (!is_immediate_prefix (**in
))
5401 /* In unified syntax, all prefixes are optional. */
5402 if (!unified_syntax
)
5408 /* Accept #0x0 as a synonym for #0. */
5409 if (strncmp (*in
, "0x", 2) == 0)
5412 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5417 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5418 &generic_floating_point_number
);
5421 && generic_floating_point_number
.sign
== '+'
5422 && (generic_floating_point_number
.low
5423 > generic_floating_point_number
.leader
))
5429 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5430 0baBbbbbbc defgh000 00000000 00000000.
5431 The zero and minus-zero cases need special handling, since they can't be
5432 encoded in the "quarter-precision" float format, but can nonetheless be
5433 loaded as integer constants. */
5436 parse_qfloat_immediate (char **ccp
, int *immed
)
5440 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5441 int found_fpchar
= 0;
5443 skip_past_char (&str
, '#');
5445 /* We must not accidentally parse an integer as a floating-point number. Make
5446 sure that the value we parse is not an integer by checking for special
5447 characters '.' or 'e'.
5448 FIXME: This is a horrible hack, but doing better is tricky because type
5449 information isn't in a very usable state at parse time. */
5451 skip_whitespace (fpnum
);
5453 if (strncmp (fpnum
, "0x", 2) == 0)
5457 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5458 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5468 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5470 unsigned fpword
= 0;
5473 /* Our FP word must be 32 bits (single-precision FP). */
5474 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5476 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5480 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5493 /* Shift operands. */
5496 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5499 struct asm_shift_name
5502 enum shift_kind kind
;
5505 /* Third argument to parse_shift. */
5506 enum parse_shift_mode
5508 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5509 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5510 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5511 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5512 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5513 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5516 /* Parse a <shift> specifier on an ARM data processing instruction.
5517 This has three forms:
5519 (LSL|LSR|ASL|ASR|ROR) Rs
5520 (LSL|LSR|ASL|ASR|ROR) #imm
5523 Note that ASL is assimilated to LSL in the instruction encoding, and
5524 RRX to ROR #0 (which cannot be written as such). */
5527 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5529 const struct asm_shift_name
*shift_name
;
5530 enum shift_kind shift
;
5535 for (p
= *str
; ISALPHA (*p
); p
++)
5540 inst
.error
= _("shift expression expected");
5544 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5547 if (shift_name
== NULL
)
5549 inst
.error
= _("shift expression expected");
5553 shift
= shift_name
->kind
;
5557 case NO_SHIFT_RESTRICT
:
5558 case SHIFT_IMMEDIATE
:
5559 if (shift
== SHIFT_UXTW
)
5561 inst
.error
= _("'UXTW' not allowed here");
5566 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5567 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5569 inst
.error
= _("'LSL' or 'ASR' required");
5574 case SHIFT_LSL_IMMEDIATE
:
5575 if (shift
!= SHIFT_LSL
)
5577 inst
.error
= _("'LSL' required");
5582 case SHIFT_ASR_IMMEDIATE
:
5583 if (shift
!= SHIFT_ASR
)
5585 inst
.error
= _("'ASR' required");
5589 case SHIFT_UXTW_IMMEDIATE
:
5590 if (shift
!= SHIFT_UXTW
)
5592 inst
.error
= _("'UXTW' required");
5600 if (shift
!= SHIFT_RRX
)
5602 /* Whitespace can appear here if the next thing is a bare digit. */
5603 skip_whitespace (p
);
5605 if (mode
== NO_SHIFT_RESTRICT
5606 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5608 inst
.operands
[i
].imm
= reg
;
5609 inst
.operands
[i
].immisreg
= 1;
5611 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5614 inst
.operands
[i
].shift_kind
= shift
;
5615 inst
.operands
[i
].shifted
= 1;
5620 /* Parse a <shifter_operand> for an ARM data processing instruction:
5623 #<immediate>, <rotate>
5627 where <shift> is defined by parse_shift above, and <rotate> is a
5628 multiple of 2 between 0 and 30. Validation of immediate operands
5629 is deferred to md_apply_fix. */
5632 parse_shifter_operand (char **str
, int i
)
5637 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5639 inst
.operands
[i
].reg
= value
;
5640 inst
.operands
[i
].isreg
= 1;
5642 /* parse_shift will override this if appropriate */
5643 inst
.relocs
[0].exp
.X_op
= O_constant
;
5644 inst
.relocs
[0].exp
.X_add_number
= 0;
5646 if (skip_past_comma (str
) == FAIL
)
5649 /* Shift operation on register. */
5650 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5653 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5656 if (skip_past_comma (str
) == SUCCESS
)
5658 /* #x, y -- ie explicit rotation by Y. */
5659 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5662 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5664 inst
.error
= _("constant expression expected");
5668 value
= exp
.X_add_number
;
5669 if (value
< 0 || value
> 30 || value
% 2 != 0)
5671 inst
.error
= _("invalid rotation");
5674 if (inst
.relocs
[0].exp
.X_add_number
< 0
5675 || inst
.relocs
[0].exp
.X_add_number
> 255)
5677 inst
.error
= _("invalid constant");
5681 /* Encode as specified. */
5682 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5686 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5687 inst
.relocs
[0].pc_rel
= 0;
5691 /* Group relocation information. Each entry in the table contains the
5692 textual name of the relocation as may appear in assembler source
5693 and must end with a colon.
5694 Along with this textual name are the relocation codes to be used if
5695 the corresponding instruction is an ALU instruction (ADD or SUB only),
5696 an LDR, an LDRS, or an LDC. */
5698 struct group_reloc_table_entry
5709 /* Varieties of non-ALU group relocation. */
5717 static struct group_reloc_table_entry group_reloc_table
[] =
5718 { /* Program counter relative: */
5720 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5725 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5726 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5727 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5728 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5730 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5735 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5736 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5737 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5738 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5740 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5741 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5742 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5743 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5744 /* Section base relative */
5746 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5751 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5752 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5753 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5754 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5756 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5761 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5762 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5763 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5764 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5766 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5767 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5768 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5769 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5770 /* Absolute thumb alu relocations. */
5772 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5777 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5782 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5787 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5792 /* Given the address of a pointer pointing to the textual name of a group
5793 relocation as may appear in assembler source, attempt to find its details
5794 in group_reloc_table. The pointer will be updated to the character after
5795 the trailing colon. On failure, FAIL will be returned; SUCCESS
5796 otherwise. On success, *entry will be updated to point at the relevant
5797 group_reloc_table entry. */
5800 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5803 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5805 int length
= strlen (group_reloc_table
[i
].name
);
5807 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5808 && (*str
)[length
] == ':')
5810 *out
= &group_reloc_table
[i
];
5811 *str
+= (length
+ 1);
5819 /* Parse a <shifter_operand> for an ARM data processing instruction
5820 (as for parse_shifter_operand) where group relocations are allowed:
5823 #<immediate>, <rotate>
5824 #:<group_reloc>:<expression>
5828 where <group_reloc> is one of the strings defined in group_reloc_table.
5829 The hashes are optional.
5831 Everything else is as for parse_shifter_operand. */
5833 static parse_operand_result
5834 parse_shifter_operand_group_reloc (char **str
, int i
)
5836 /* Determine if we have the sequence of characters #: or just :
5837 coming next. If we do, then we check for a group relocation.
5838 If we don't, punt the whole lot to parse_shifter_operand. */
5840 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5841 || (*str
)[0] == ':')
5843 struct group_reloc_table_entry
*entry
;
5845 if ((*str
)[0] == '#')
5850 /* Try to parse a group relocation. Anything else is an error. */
5851 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5853 inst
.error
= _("unknown group relocation");
5854 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5857 /* We now have the group relocation table entry corresponding to
5858 the name in the assembler source. Next, we parse the expression. */
5859 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5860 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5862 /* Record the relocation type (always the ALU variant here). */
5863 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5864 gas_assert (inst
.relocs
[0].type
!= 0);
5866 return PARSE_OPERAND_SUCCESS
;
5869 return parse_shifter_operand (str
, i
) == SUCCESS
5870 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5872 /* Never reached. */
5875 /* Parse a Neon alignment expression. Information is written to
5876 inst.operands[i]. We assume the initial ':' has been skipped.
5878 align .imm = align << 8, .immisalign=1, .preind=0 */
5879 static parse_operand_result
5880 parse_neon_alignment (char **str
, int i
)
5885 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5887 if (exp
.X_op
!= O_constant
)
5889 inst
.error
= _("alignment must be constant");
5890 return PARSE_OPERAND_FAIL
;
5893 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5894 inst
.operands
[i
].immisalign
= 1;
5895 /* Alignments are not pre-indexes. */
5896 inst
.operands
[i
].preind
= 0;
5899 return PARSE_OPERAND_SUCCESS
;
5902 /* Parse all forms of an ARM address expression. Information is written
5903 to inst.operands[i] and/or inst.relocs[0].
5905 Preindexed addressing (.preind=1):
5907 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5908 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5909 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5910 .shift_kind=shift .relocs[0].exp=shift_imm
5912 These three may have a trailing ! which causes .writeback to be set also.
5914 Postindexed addressing (.postind=1, .writeback=1):
5916 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5917 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5918 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5919 .shift_kind=shift .relocs[0].exp=shift_imm
5921 Unindexed addressing (.preind=0, .postind=0):
5923 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5927 [Rn]{!} shorthand for [Rn,#0]{!}
5928 =immediate .isreg=0 .relocs[0].exp=immediate
5929 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5931 It is the caller's responsibility to check for addressing modes not
5932 supported by the instruction, and to set inst.relocs[0].type. */
5934 static parse_operand_result
5935 parse_address_main (char **str
, int i
, int group_relocations
,
5936 group_reloc_type group_type
)
5941 if (skip_past_char (&p
, '[') == FAIL
)
5943 if (skip_past_char (&p
, '=') == FAIL
)
5945 /* Bare address - translate to PC-relative offset. */
5946 inst
.relocs
[0].pc_rel
= 1;
5947 inst
.operands
[i
].reg
= REG_PC
;
5948 inst
.operands
[i
].isreg
= 1;
5949 inst
.operands
[i
].preind
= 1;
5951 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5952 return PARSE_OPERAND_FAIL
;
5954 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5955 /*allow_symbol_p=*/TRUE
))
5956 return PARSE_OPERAND_FAIL
;
5959 return PARSE_OPERAND_SUCCESS
;
5962 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5963 skip_whitespace (p
);
5965 if (group_type
== GROUP_MVE
)
5967 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5968 struct neon_type_el et
;
5969 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5971 inst
.operands
[i
].isquad
= 1;
5973 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5975 inst
.error
= BAD_ADDR_MODE
;
5976 return PARSE_OPERAND_FAIL
;
5979 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5981 if (group_type
== GROUP_MVE
)
5982 inst
.error
= BAD_ADDR_MODE
;
5984 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5985 return PARSE_OPERAND_FAIL
;
5987 inst
.operands
[i
].reg
= reg
;
5988 inst
.operands
[i
].isreg
= 1;
5990 if (skip_past_comma (&p
) == SUCCESS
)
5992 inst
.operands
[i
].preind
= 1;
5995 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5997 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5998 struct neon_type_el et
;
5999 if (group_type
== GROUP_MVE
6000 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6002 inst
.operands
[i
].immisreg
= 2;
6003 inst
.operands
[i
].imm
= reg
;
6005 if (skip_past_comma (&p
) == SUCCESS
)
6007 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
6009 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
6010 inst
.relocs
[0].exp
.X_add_number
= 0;
6013 return PARSE_OPERAND_FAIL
;
6016 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6018 inst
.operands
[i
].imm
= reg
;
6019 inst
.operands
[i
].immisreg
= 1;
6021 if (skip_past_comma (&p
) == SUCCESS
)
6022 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6023 return PARSE_OPERAND_FAIL
;
6025 else if (skip_past_char (&p
, ':') == SUCCESS
)
6027 /* FIXME: '@' should be used here, but it's filtered out by generic
6028 code before we get to see it here. This may be subject to
6030 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6032 if (result
!= PARSE_OPERAND_SUCCESS
)
6037 if (inst
.operands
[i
].negative
)
6039 inst
.operands
[i
].negative
= 0;
6043 if (group_relocations
6044 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
6046 struct group_reloc_table_entry
*entry
;
6048 /* Skip over the #: or : sequence. */
6054 /* Try to parse a group relocation. Anything else is an
6056 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
6058 inst
.error
= _("unknown group relocation");
6059 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6062 /* We now have the group relocation table entry corresponding to
6063 the name in the assembler source. Next, we parse the
6065 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6066 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6068 /* Record the relocation type. */
6073 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
6078 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
6083 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
6090 if (inst
.relocs
[0].type
== 0)
6092 inst
.error
= _("this group relocation is not allowed on this instruction");
6093 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
6100 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6101 return PARSE_OPERAND_FAIL
;
6102 /* If the offset is 0, find out if it's a +0 or -0. */
6103 if (inst
.relocs
[0].exp
.X_op
== O_constant
6104 && inst
.relocs
[0].exp
.X_add_number
== 0)
6106 skip_whitespace (q
);
6110 skip_whitespace (q
);
6113 inst
.operands
[i
].negative
= 1;
6118 else if (skip_past_char (&p
, ':') == SUCCESS
)
6120 /* FIXME: '@' should be used here, but it's filtered out by generic code
6121 before we get to see it here. This may be subject to change. */
6122 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6124 if (result
!= PARSE_OPERAND_SUCCESS
)
6128 if (skip_past_char (&p
, ']') == FAIL
)
6130 inst
.error
= _("']' expected");
6131 return PARSE_OPERAND_FAIL
;
6134 if (skip_past_char (&p
, '!') == SUCCESS
)
6135 inst
.operands
[i
].writeback
= 1;
6137 else if (skip_past_comma (&p
) == SUCCESS
)
6139 if (skip_past_char (&p
, '{') == SUCCESS
)
6141 /* [Rn], {expr} - unindexed, with option */
6142 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6143 0, 255, TRUE
) == FAIL
)
6144 return PARSE_OPERAND_FAIL
;
6146 if (skip_past_char (&p
, '}') == FAIL
)
6148 inst
.error
= _("'}' expected at end of 'option' field");
6149 return PARSE_OPERAND_FAIL
;
6151 if (inst
.operands
[i
].preind
)
6153 inst
.error
= _("cannot combine index with option");
6154 return PARSE_OPERAND_FAIL
;
6157 return PARSE_OPERAND_SUCCESS
;
6161 inst
.operands
[i
].postind
= 1;
6162 inst
.operands
[i
].writeback
= 1;
6164 if (inst
.operands
[i
].preind
)
6166 inst
.error
= _("cannot combine pre- and post-indexing");
6167 return PARSE_OPERAND_FAIL
;
6171 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6173 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6174 struct neon_type_el et
;
6175 if (group_type
== GROUP_MVE
6176 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6178 inst
.operands
[i
].immisreg
= 2;
6179 inst
.operands
[i
].imm
= reg
;
6181 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6183 /* We might be using the immediate for alignment already. If we
6184 are, OR the register number into the low-order bits. */
6185 if (inst
.operands
[i
].immisalign
)
6186 inst
.operands
[i
].imm
|= reg
;
6188 inst
.operands
[i
].imm
= reg
;
6189 inst
.operands
[i
].immisreg
= 1;
6191 if (skip_past_comma (&p
) == SUCCESS
)
6192 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6193 return PARSE_OPERAND_FAIL
;
6199 if (inst
.operands
[i
].negative
)
6201 inst
.operands
[i
].negative
= 0;
6204 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6205 return PARSE_OPERAND_FAIL
;
6206 /* If the offset is 0, find out if it's a +0 or -0. */
6207 if (inst
.relocs
[0].exp
.X_op
== O_constant
6208 && inst
.relocs
[0].exp
.X_add_number
== 0)
6210 skip_whitespace (q
);
6214 skip_whitespace (q
);
6217 inst
.operands
[i
].negative
= 1;
6223 /* If at this point neither .preind nor .postind is set, we have a
6224 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6225 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6227 inst
.operands
[i
].preind
= 1;
6228 inst
.relocs
[0].exp
.X_op
= O_constant
;
6229 inst
.relocs
[0].exp
.X_add_number
= 0;
6232 return PARSE_OPERAND_SUCCESS
;
6236 parse_address (char **str
, int i
)
6238 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6242 static parse_operand_result
6243 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6245 return parse_address_main (str
, i
, 1, type
);
6248 /* Parse an operand for a MOVW or MOVT instruction. */
6250 parse_half (char **str
)
6255 skip_past_char (&p
, '#');
6256 if (strncasecmp (p
, ":lower16:", 9) == 0)
6257 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6258 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6259 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6261 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6264 skip_whitespace (p
);
6267 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6270 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6272 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6274 inst
.error
= _("constant expression expected");
6277 if (inst
.relocs
[0].exp
.X_add_number
< 0
6278 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6280 inst
.error
= _("immediate value out of range");
6288 /* Miscellaneous. */
6290 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6291 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6293 parse_psr (char **str
, bfd_boolean lhs
)
6296 unsigned long psr_field
;
6297 const struct asm_psr
*psr
;
6299 bfd_boolean is_apsr
= FALSE
;
6300 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6302 /* PR gas/12698: If the user has specified -march=all then m_profile will
6303 be TRUE, but we want to ignore it in this case as we are building for any
6304 CPU type, including non-m variants. */
6305 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6308 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6309 feature for ease of use and backwards compatibility. */
6311 if (strncasecmp (p
, "SPSR", 4) == 0)
6314 goto unsupported_psr
;
6316 psr_field
= SPSR_BIT
;
6318 else if (strncasecmp (p
, "CPSR", 4) == 0)
6321 goto unsupported_psr
;
6325 else if (strncasecmp (p
, "APSR", 4) == 0)
6327 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6328 and ARMv7-R architecture CPUs. */
6337 while (ISALNUM (*p
) || *p
== '_');
6339 if (strncasecmp (start
, "iapsr", 5) == 0
6340 || strncasecmp (start
, "eapsr", 5) == 0
6341 || strncasecmp (start
, "xpsr", 4) == 0
6342 || strncasecmp (start
, "psr", 3) == 0)
6343 p
= start
+ strcspn (start
, "rR") + 1;
6345 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6351 /* If APSR is being written, a bitfield may be specified. Note that
6352 APSR itself is handled above. */
6353 if (psr
->field
<= 3)
6355 psr_field
= psr
->field
;
6361 /* M-profile MSR instructions have the mask field set to "10", except
6362 *PSR variants which modify APSR, which may use a different mask (and
6363 have been handled already). Do that by setting the PSR_f field
6365 return psr
->field
| (lhs
? PSR_f
: 0);
6368 goto unsupported_psr
;
6374 /* A suffix follows. */
6380 while (ISALNUM (*p
) || *p
== '_');
6384 /* APSR uses a notation for bits, rather than fields. */
6385 unsigned int nzcvq_bits
= 0;
6386 unsigned int g_bit
= 0;
6389 for (bit
= start
; bit
!= p
; bit
++)
6391 switch (TOLOWER (*bit
))
6394 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6398 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6402 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6406 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6410 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6414 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6418 inst
.error
= _("unexpected bit specified after APSR");
6423 if (nzcvq_bits
== 0x1f)
6428 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6430 inst
.error
= _("selected processor does not "
6431 "support DSP extension");
6438 if ((nzcvq_bits
& 0x20) != 0
6439 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6440 || (g_bit
& 0x2) != 0)
6442 inst
.error
= _("bad bitmask specified after APSR");
6448 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6453 psr_field
|= psr
->field
;
6459 goto error
; /* Garbage after "[CS]PSR". */
6461 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6462 is deprecated, but allow it anyway. */
6466 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6469 else if (!m_profile
)
6470 /* These bits are never right for M-profile devices: don't set them
6471 (only code paths which read/write APSR reach here). */
6472 psr_field
|= (PSR_c
| PSR_f
);
6478 inst
.error
= _("selected processor does not support requested special "
6479 "purpose register");
6483 inst
.error
= _("flag for {c}psr instruction expected");
6488 parse_sys_vldr_vstr (char **str
)
6497 {"FPSCR", 0x1, 0x0},
6498 {"FPSCR_nzcvqc", 0x2, 0x0},
6501 {"FPCXTNS", 0x6, 0x1},
6502 {"FPCXTS", 0x7, 0x1}
6504 char *op_end
= strchr (*str
, ',');
6505 size_t op_strlen
= op_end
- *str
;
6507 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6509 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6511 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6520 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6521 value suitable for splatting into the AIF field of the instruction. */
6524 parse_cps_flags (char **str
)
6533 case '\0': case ',':
6536 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6537 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6538 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6541 inst
.error
= _("unrecognized CPS flag");
6546 if (saw_a_flag
== 0)
6548 inst
.error
= _("missing CPS flags");
6556 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6557 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6560 parse_endian_specifier (char **str
)
6565 if (strncasecmp (s
, "BE", 2))
6567 else if (strncasecmp (s
, "LE", 2))
6571 inst
.error
= _("valid endian specifiers are be or le");
6575 if (ISALNUM (s
[2]) || s
[2] == '_')
6577 inst
.error
= _("valid endian specifiers are be or le");
6582 return little_endian
;
6585 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6586 value suitable for poking into the rotate field of an sxt or sxta
6587 instruction, or FAIL on error. */
6590 parse_ror (char **str
)
6595 if (strncasecmp (s
, "ROR", 3) == 0)
6599 inst
.error
= _("missing rotation field after comma");
6603 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6608 case 0: *str
= s
; return 0x0;
6609 case 8: *str
= s
; return 0x1;
6610 case 16: *str
= s
; return 0x2;
6611 case 24: *str
= s
; return 0x3;
6614 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6619 /* Parse a conditional code (from conds[] below). The value returned is in the
6620 range 0 .. 14, or FAIL. */
6622 parse_cond (char **str
)
6625 const struct asm_cond
*c
;
6627 /* Condition codes are always 2 characters, so matching up to
6628 3 characters is sufficient. */
6633 while (ISALPHA (*q
) && n
< 3)
6635 cond
[n
] = TOLOWER (*q
);
6640 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6643 inst
.error
= _("condition required");
6651 /* Parse an option for a barrier instruction. Returns the encoding for the
6654 parse_barrier (char **str
)
6657 const struct asm_barrier_opt
*o
;
6660 while (ISALPHA (*q
))
6663 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6668 if (!mark_feature_used (&o
->arch
))
6675 /* Parse the operands of a table branch instruction. Similar to a memory
6678 parse_tb (char **str
)
6683 if (skip_past_char (&p
, '[') == FAIL
)
6685 inst
.error
= _("'[' expected");
6689 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6691 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6694 inst
.operands
[0].reg
= reg
;
6696 if (skip_past_comma (&p
) == FAIL
)
6698 inst
.error
= _("',' expected");
6702 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6704 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6707 inst
.operands
[0].imm
= reg
;
6709 if (skip_past_comma (&p
) == SUCCESS
)
6711 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6713 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6715 inst
.error
= _("invalid shift");
6718 inst
.operands
[0].shifted
= 1;
6721 if (skip_past_char (&p
, ']') == FAIL
)
6723 inst
.error
= _("']' expected");
6730 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6731 information on the types the operands can take and how they are encoded.
6732 Up to four operands may be read; this function handles setting the
6733 ".present" field for each read operand itself.
6734 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6735 else returns FAIL. */
6738 parse_neon_mov (char **str
, int *which_operand
)
6740 int i
= *which_operand
, val
;
6741 enum arm_reg_type rtype
;
6743 struct neon_type_el optype
;
6745 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6747 /* Cases 17 or 19. */
6748 inst
.operands
[i
].reg
= val
;
6749 inst
.operands
[i
].isvec
= 1;
6750 inst
.operands
[i
].isscalar
= 2;
6751 inst
.operands
[i
].vectype
= optype
;
6752 inst
.operands
[i
++].present
= 1;
6754 if (skip_past_comma (&ptr
) == FAIL
)
6757 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6759 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6760 inst
.operands
[i
].reg
= val
;
6761 inst
.operands
[i
].isreg
= 1;
6762 inst
.operands
[i
].present
= 1;
6764 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6766 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6767 inst
.operands
[i
].reg
= val
;
6768 inst
.operands
[i
].isvec
= 1;
6769 inst
.operands
[i
].isscalar
= 2;
6770 inst
.operands
[i
].vectype
= optype
;
6771 inst
.operands
[i
++].present
= 1;
6773 if (skip_past_comma (&ptr
) == FAIL
)
6776 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6779 inst
.operands
[i
].reg
= val
;
6780 inst
.operands
[i
].isreg
= 1;
6781 inst
.operands
[i
++].present
= 1;
6783 if (skip_past_comma (&ptr
) == FAIL
)
6786 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6789 inst
.operands
[i
].reg
= val
;
6790 inst
.operands
[i
].isreg
= 1;
6791 inst
.operands
[i
].present
= 1;
6795 first_error (_("expected ARM or MVE vector register"));
6799 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6801 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6802 inst
.operands
[i
].reg
= val
;
6803 inst
.operands
[i
].isscalar
= 1;
6804 inst
.operands
[i
].vectype
= optype
;
6805 inst
.operands
[i
++].present
= 1;
6807 if (skip_past_comma (&ptr
) == FAIL
)
6810 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6813 inst
.operands
[i
].reg
= val
;
6814 inst
.operands
[i
].isreg
= 1;
6815 inst
.operands
[i
].present
= 1;
6817 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6819 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6822 /* Cases 0, 1, 2, 3, 5 (D only). */
6823 if (skip_past_comma (&ptr
) == FAIL
)
6826 inst
.operands
[i
].reg
= val
;
6827 inst
.operands
[i
].isreg
= 1;
6828 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6829 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6830 inst
.operands
[i
].isvec
= 1;
6831 inst
.operands
[i
].vectype
= optype
;
6832 inst
.operands
[i
++].present
= 1;
6834 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6836 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6837 Case 13: VMOV <Sd>, <Rm> */
6838 inst
.operands
[i
].reg
= val
;
6839 inst
.operands
[i
].isreg
= 1;
6840 inst
.operands
[i
].present
= 1;
6842 if (rtype
== REG_TYPE_NQ
)
6844 first_error (_("can't use Neon quad register here"));
6847 else if (rtype
!= REG_TYPE_VFS
)
6850 if (skip_past_comma (&ptr
) == FAIL
)
6852 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6854 inst
.operands
[i
].reg
= val
;
6855 inst
.operands
[i
].isreg
= 1;
6856 inst
.operands
[i
].present
= 1;
6859 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6861 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
,
6864 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6865 Case 1: VMOV<c><q> <Dd>, <Dm>
6866 Case 8: VMOV.F32 <Sd>, <Sm>
6867 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6869 inst
.operands
[i
].reg
= val
;
6870 inst
.operands
[i
].isreg
= 1;
6871 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6872 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6873 inst
.operands
[i
].isvec
= 1;
6874 inst
.operands
[i
].vectype
= optype
;
6875 inst
.operands
[i
].present
= 1;
6877 if (skip_past_comma (&ptr
) == SUCCESS
)
6882 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6885 inst
.operands
[i
].reg
= val
;
6886 inst
.operands
[i
].isreg
= 1;
6887 inst
.operands
[i
++].present
= 1;
6889 if (skip_past_comma (&ptr
) == FAIL
)
6892 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6895 inst
.operands
[i
].reg
= val
;
6896 inst
.operands
[i
].isreg
= 1;
6897 inst
.operands
[i
].present
= 1;
6900 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6901 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6902 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6903 Case 10: VMOV.F32 <Sd>, #<imm>
6904 Case 11: VMOV.F64 <Dd>, #<imm> */
6905 inst
.operands
[i
].immisfloat
= 1;
6906 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6908 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6909 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6913 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6917 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6919 /* Cases 6, 7, 16, 18. */
6920 inst
.operands
[i
].reg
= val
;
6921 inst
.operands
[i
].isreg
= 1;
6922 inst
.operands
[i
++].present
= 1;
6924 if (skip_past_comma (&ptr
) == FAIL
)
6927 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6929 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6930 inst
.operands
[i
].reg
= val
;
6931 inst
.operands
[i
].isscalar
= 2;
6932 inst
.operands
[i
].present
= 1;
6933 inst
.operands
[i
].vectype
= optype
;
6935 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6937 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6938 inst
.operands
[i
].reg
= val
;
6939 inst
.operands
[i
].isscalar
= 1;
6940 inst
.operands
[i
].present
= 1;
6941 inst
.operands
[i
].vectype
= optype
;
6943 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6945 inst
.operands
[i
].reg
= val
;
6946 inst
.operands
[i
].isreg
= 1;
6947 inst
.operands
[i
++].present
= 1;
6949 if (skip_past_comma (&ptr
) == FAIL
)
6952 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6955 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6957 inst
.operands
[i
].reg
= val
;
6958 inst
.operands
[i
].isreg
= 1;
6959 inst
.operands
[i
].isvec
= 1;
6960 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6961 inst
.operands
[i
].vectype
= optype
;
6962 inst
.operands
[i
].present
= 1;
6964 if (rtype
== REG_TYPE_VFS
)
6968 if (skip_past_comma (&ptr
) == FAIL
)
6970 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6973 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6976 inst
.operands
[i
].reg
= val
;
6977 inst
.operands
[i
].isreg
= 1;
6978 inst
.operands
[i
].isvec
= 1;
6979 inst
.operands
[i
].issingle
= 1;
6980 inst
.operands
[i
].vectype
= optype
;
6981 inst
.operands
[i
].present
= 1;
6986 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6989 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6990 inst
.operands
[i
].reg
= val
;
6991 inst
.operands
[i
].isvec
= 1;
6992 inst
.operands
[i
].isscalar
= 2;
6993 inst
.operands
[i
].vectype
= optype
;
6994 inst
.operands
[i
++].present
= 1;
6996 if (skip_past_comma (&ptr
) == FAIL
)
6999 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
7002 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
7005 inst
.operands
[i
].reg
= val
;
7006 inst
.operands
[i
].isvec
= 1;
7007 inst
.operands
[i
].isscalar
= 2;
7008 inst
.operands
[i
].vectype
= optype
;
7009 inst
.operands
[i
].present
= 1;
7013 first_error (_("VFP single, double or MVE vector register"
7019 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
7023 inst
.operands
[i
].reg
= val
;
7024 inst
.operands
[i
].isreg
= 1;
7025 inst
.operands
[i
].isvec
= 1;
7026 inst
.operands
[i
].issingle
= 1;
7027 inst
.operands
[i
].vectype
= optype
;
7028 inst
.operands
[i
].present
= 1;
7033 first_error (_("parse error"));
7037 /* Successfully parsed the operands. Update args. */
7043 first_error (_("expected comma"));
7047 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
7051 /* Use this macro when the operand constraints are different
7052 for ARM and THUMB (e.g. ldrd). */
7053 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
7054 ((arm_operand) | ((thumb_operand) << 16))
7056 /* Matcher codes for parse_operands. */
7057 enum operand_parse_code
7059 OP_stop
, /* end of line */
7061 OP_RR
, /* ARM register */
7062 OP_RRnpc
, /* ARM register, not r15 */
7063 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
7064 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
7065 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
7066 optional trailing ! */
7067 OP_RRw
, /* ARM register, not r15, optional trailing ! */
7068 OP_RCP
, /* Coprocessor number */
7069 OP_RCN
, /* Coprocessor register */
7070 OP_RF
, /* FPA register */
7071 OP_RVS
, /* VFP single precision register */
7072 OP_RVD
, /* VFP double precision register (0..15) */
7073 OP_RND
, /* Neon double precision register (0..31) */
7074 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
7075 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
7077 OP_RNQ
, /* Neon quad precision register */
7078 OP_RNQMQ
, /* Neon quad or MVE vector register. */
7079 OP_RVSD
, /* VFP single or double precision register */
7080 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
7081 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
7082 OP_RNSD
, /* Neon single or double precision register */
7083 OP_RNDQ
, /* Neon double or quad precision register */
7084 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
7085 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
7086 OP_RNSDQ
, /* Neon single, double or quad precision register */
7087 OP_RNSC
, /* Neon scalar D[X] */
7088 OP_RVC
, /* VFP control register */
7089 OP_RMF
, /* Maverick F register */
7090 OP_RMD
, /* Maverick D register */
7091 OP_RMFX
, /* Maverick FX register */
7092 OP_RMDX
, /* Maverick DX register */
7093 OP_RMAX
, /* Maverick AX register */
7094 OP_RMDS
, /* Maverick DSPSC register */
7095 OP_RIWR
, /* iWMMXt wR register */
7096 OP_RIWC
, /* iWMMXt wC register */
7097 OP_RIWG
, /* iWMMXt wCG register */
7098 OP_RXA
, /* XScale accumulator register */
7100 OP_RNSDMQ
, /* Neon single, double or MVE vector register */
7101 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
7103 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
7105 OP_RMQ
, /* MVE vector register. */
7106 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
7107 OP_RMQRR
, /* MVE vector or ARM register. */
7109 /* New operands for Armv8.1-M Mainline. */
7110 OP_LR
, /* ARM LR register */
7111 OP_RRe
, /* ARM register, only even numbered. */
7112 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7113 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7114 OP_RR_ZR
, /* ARM register or ZR but no PC */
7116 OP_REGLST
, /* ARM register list */
7117 OP_CLRMLST
, /* CLRM register list */
7118 OP_VRSLST
, /* VFP single-precision register list */
7119 OP_VRDLST
, /* VFP double-precision register list */
7120 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7121 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7122 OP_NSTRLST
, /* Neon element/structure list */
7123 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7124 OP_MSTRLST2
, /* MVE vector list with two elements. */
7125 OP_MSTRLST4
, /* MVE vector list with four elements. */
7127 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7128 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7129 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7130 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7132 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7133 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7134 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7135 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7137 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7138 scalar, or ARM register. */
7139 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7140 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7141 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7143 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7144 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7145 OP_VMOV
, /* Neon VMOV operands. */
7146 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7147 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7149 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7150 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7152 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7153 OP_VLDR
, /* VLDR operand. */
7155 OP_I0
, /* immediate zero */
7156 OP_I7
, /* immediate value 0 .. 7 */
7157 OP_I15
, /* 0 .. 15 */
7158 OP_I16
, /* 1 .. 16 */
7159 OP_I16z
, /* 0 .. 16 */
7160 OP_I31
, /* 0 .. 31 */
7161 OP_I31w
, /* 0 .. 31, optional trailing ! */
7162 OP_I32
, /* 1 .. 32 */
7163 OP_I32z
, /* 0 .. 32 */
7164 OP_I48_I64
, /* 48 or 64 */
7165 OP_I63
, /* 0 .. 63 */
7166 OP_I63s
, /* -64 .. 63 */
7167 OP_I64
, /* 1 .. 64 */
7168 OP_I64z
, /* 0 .. 64 */
7169 OP_I127
, /* 0 .. 127 */
7170 OP_I255
, /* 0 .. 255 */
7171 OP_I511
, /* 0 .. 511 */
7172 OP_I4095
, /* 0 .. 4095 */
7173 OP_I8191
, /* 0 .. 8191 */
7174 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7175 OP_I7b
, /* 0 .. 7 */
7176 OP_I15b
, /* 0 .. 15 */
7177 OP_I31b
, /* 0 .. 31 */
7179 OP_SH
, /* shifter operand */
7180 OP_SHG
, /* shifter operand with possible group relocation */
7181 OP_ADDR
, /* Memory address expression (any mode) */
7182 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7183 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7184 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7185 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7186 OP_EXP
, /* arbitrary expression */
7187 OP_EXPi
, /* same, with optional immediate prefix */
7188 OP_EXPr
, /* same, with optional relocation suffix */
7189 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7190 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7191 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7192 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7194 OP_CPSF
, /* CPS flags */
7195 OP_ENDI
, /* Endianness specifier */
7196 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7197 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7198 OP_COND
, /* conditional code */
7199 OP_TB
, /* Table branch. */
7201 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7203 OP_RRnpc_I0
, /* ARM register or literal 0 */
7204 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7205 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7206 OP_RF_IF
, /* FPA register or immediate */
7207 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7208 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7210 /* Optional operands. */
7211 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7212 OP_oI31b
, /* 0 .. 31 */
7213 OP_oI32b
, /* 1 .. 32 */
7214 OP_oI32z
, /* 0 .. 32 */
7215 OP_oIffffb
, /* 0 .. 65535 */
7216 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7218 OP_oRR
, /* ARM register */
7219 OP_oLR
, /* ARM LR register */
7220 OP_oRRnpc
, /* ARM register, not the PC */
7221 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7222 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7223 OP_oRND
, /* Optional Neon double precision register */
7224 OP_oRNQ
, /* Optional Neon quad precision register */
7225 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7226 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7227 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7228 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7230 OP_oSHll
, /* LSL immediate */
7231 OP_oSHar
, /* ASR immediate */
7232 OP_oSHllar
, /* LSL or ASR immediate */
7233 OP_oROR
, /* ROR 0/8/16/24 */
7234 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7236 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7238 /* Some pre-defined mixed (ARM/THUMB) operands. */
7239 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7240 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7241 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7243 OP_FIRST_OPTIONAL
= OP_oI7b
7246 /* Generic instruction operand parser. This does no encoding and no
7247 semantic validation; it merely squirrels values away in the inst
7248 structure. Returns SUCCESS or FAIL depending on whether the
7249 specified grammar matched. */
7251 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7253 unsigned const int *upat
= pattern
;
7254 char *backtrack_pos
= 0;
7255 const char *backtrack_error
= 0;
7256 int i
, val
= 0, backtrack_index
= 0;
7257 enum arm_reg_type rtype
;
7258 parse_operand_result result
;
7259 unsigned int op_parse_code
;
7260 bfd_boolean partial_match
;
7262 #define po_char_or_fail(chr) \
7265 if (skip_past_char (&str, chr) == FAIL) \
7270 #define po_reg_or_fail(regtype) \
7273 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7274 & inst.operands[i].vectype); \
7277 first_error (_(reg_expected_msgs[regtype])); \
7280 inst.operands[i].reg = val; \
7281 inst.operands[i].isreg = 1; \
7282 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7283 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7284 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7285 || rtype == REG_TYPE_VFD \
7286 || rtype == REG_TYPE_NQ); \
7287 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7291 #define po_reg_or_goto(regtype, label) \
7294 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7295 & inst.operands[i].vectype); \
7299 inst.operands[i].reg = val; \
7300 inst.operands[i].isreg = 1; \
7301 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7302 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7303 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7304 || rtype == REG_TYPE_VFD \
7305 || rtype == REG_TYPE_NQ); \
7306 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7310 #define po_imm_or_fail(min, max, popt) \
7313 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7315 inst.operands[i].imm = val; \
7319 #define po_imm1_or_imm2_or_fail(imm1, imm2, popt) \
7323 my_get_expression (&exp, &str, popt); \
7324 if (exp.X_op != O_constant) \
7326 inst.error = _("constant expression required"); \
7329 if (exp.X_add_number != imm1 && exp.X_add_number != imm2) \
7331 inst.error = _("immediate value 48 or 64 expected"); \
7334 inst.operands[i].imm = exp.X_add_number; \
7338 #define po_scalar_or_goto(elsz, label, reg_type) \
7341 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7345 inst.operands[i].reg = val; \
7346 inst.operands[i].isscalar = 1; \
7350 #define po_misc_or_fail(expr) \
7358 #define po_misc_or_fail_no_backtrack(expr) \
7362 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7363 backtrack_pos = 0; \
7364 if (result != PARSE_OPERAND_SUCCESS) \
7369 #define po_barrier_or_imm(str) \
7372 val = parse_barrier (&str); \
7373 if (val == FAIL && ! ISALPHA (*str)) \
7376 /* ISB can only take SY as an option. */ \
7377 || ((inst.instruction & 0xf0) == 0x60 \
7380 inst.error = _("invalid barrier type"); \
7381 backtrack_pos = 0; \
7387 skip_whitespace (str
);
7389 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7391 op_parse_code
= upat
[i
];
7392 if (op_parse_code
>= 1<<16)
7393 op_parse_code
= thumb
? (op_parse_code
>> 16)
7394 : (op_parse_code
& ((1<<16)-1));
7396 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7398 /* Remember where we are in case we need to backtrack. */
7399 backtrack_pos
= str
;
7400 backtrack_error
= inst
.error
;
7401 backtrack_index
= i
;
7404 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7405 po_char_or_fail (',');
7407 switch (op_parse_code
)
7419 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7420 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7421 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7422 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7423 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7424 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7427 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7431 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7434 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7436 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7438 /* Also accept generic coprocessor regs for unknown registers. */
7440 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7442 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7443 existing register with a value of 0, this seems like the
7444 best way to parse P0. */
7446 if (strncasecmp (str
, "P0", 2) == 0)
7449 inst
.operands
[i
].isreg
= 1;
7450 inst
.operands
[i
].reg
= 13;
7455 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7456 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7457 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7458 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7459 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7460 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7461 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7462 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7463 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7464 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7467 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7470 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7471 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7473 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7478 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7482 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7484 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7487 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7489 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7492 po_reg_or_goto (REG_TYPE_NSD
, try_mq2
);
7495 po_reg_or_fail (REG_TYPE_MQ
);
7498 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7500 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7505 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7508 po_reg_or_fail (REG_TYPE_NSDQ
);
7512 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7516 po_reg_or_fail (REG_TYPE_MQ
);
7518 /* Neon scalar. Using an element size of 8 means that some invalid
7519 scalars are accepted here, so deal with those in later code. */
7520 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7524 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7527 po_imm_or_fail (0, 0, TRUE
);
7532 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7536 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7541 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7544 if (parse_ifimm_zero (&str
))
7545 inst
.operands
[i
].imm
= 0;
7549 = _("only floating point zero is allowed as immediate value");
7557 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7560 po_reg_or_fail (REG_TYPE_RN
);
7564 case OP_RNSDQ_RNSC_MQ_RR
:
7565 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7568 case OP_RNSDQ_RNSC_MQ
:
7569 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7574 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7578 po_reg_or_fail (REG_TYPE_NSDQ
);
7585 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7588 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7591 po_reg_or_fail (REG_TYPE_NSD
);
7595 case OP_RNDQMQ_RNSC_RR
:
7596 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7599 case OP_RNDQ_RNSC_RR
:
7600 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7602 case OP_RNDQMQ_RNSC
:
7603 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7608 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7611 po_reg_or_fail (REG_TYPE_NDQ
);
7617 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7620 po_reg_or_fail (REG_TYPE_VFD
);
7625 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7626 not careful then bad things might happen. */
7627 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7630 case OP_RNDQMQ_Ibig
:
7631 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7636 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7639 /* There's a possibility of getting a 64-bit immediate here, so
7640 we need special handling. */
7641 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7644 inst
.error
= _("immediate value is out of range");
7650 case OP_RNDQMQ_I63b_RR
:
7651 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7654 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7659 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7662 po_imm_or_fail (0, 63, TRUE
);
7667 po_char_or_fail ('[');
7668 po_reg_or_fail (REG_TYPE_RN
);
7669 po_char_or_fail (']');
7675 po_reg_or_fail (REG_TYPE_RN
);
7676 if (skip_past_char (&str
, '!') == SUCCESS
)
7677 inst
.operands
[i
].writeback
= 1;
7681 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7682 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7683 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7684 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7685 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7686 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7687 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7688 case OP_I48_I64
: po_imm1_or_imm2_or_fail (48, 64, FALSE
); break;
7689 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7690 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7691 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7692 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7693 case OP_I127
: po_imm_or_fail ( 0, 127, FALSE
); break;
7694 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7695 case OP_I511
: po_imm_or_fail ( 0, 511, FALSE
); break;
7696 case OP_I4095
: po_imm_or_fail ( 0, 4095, FALSE
); break;
7697 case OP_I8191
: po_imm_or_fail ( 0, 8191, FALSE
); break;
7698 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7700 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7701 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7703 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7704 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7705 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7706 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7708 /* Immediate variants */
7710 po_char_or_fail ('{');
7711 po_imm_or_fail (0, 255, TRUE
);
7712 po_char_or_fail ('}');
7716 /* The expression parser chokes on a trailing !, so we have
7717 to find it first and zap it. */
7720 while (*s
&& *s
!= ',')
7725 inst
.operands
[i
].writeback
= 1;
7727 po_imm_or_fail (0, 31, TRUE
);
7735 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7740 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7745 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7747 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7749 val
= parse_reloc (&str
);
7752 inst
.error
= _("unrecognized relocation suffix");
7755 else if (val
!= BFD_RELOC_UNUSED
)
7757 inst
.operands
[i
].imm
= val
;
7758 inst
.operands
[i
].hasreloc
= 1;
7764 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7766 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7768 inst
.operands
[i
].hasreloc
= 1;
7770 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7772 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7773 inst
.operands
[i
].hasreloc
= 0;
7777 /* Operand for MOVW or MOVT. */
7779 po_misc_or_fail (parse_half (&str
));
7782 /* Register or expression. */
7783 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7784 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7786 /* Register or immediate. */
7787 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7788 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7790 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7791 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7793 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7795 if (!is_immediate_prefix (*str
))
7798 val
= parse_fpa_immediate (&str
);
7801 /* FPA immediates are encoded as registers 8-15.
7802 parse_fpa_immediate has already applied the offset. */
7803 inst
.operands
[i
].reg
= val
;
7804 inst
.operands
[i
].isreg
= 1;
7807 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7808 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7810 /* Two kinds of register. */
7813 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7815 || (rege
->type
!= REG_TYPE_MMXWR
7816 && rege
->type
!= REG_TYPE_MMXWC
7817 && rege
->type
!= REG_TYPE_MMXWCG
))
7819 inst
.error
= _("iWMMXt data or control register expected");
7822 inst
.operands
[i
].reg
= rege
->number
;
7823 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7829 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7831 || (rege
->type
!= REG_TYPE_MMXWC
7832 && rege
->type
!= REG_TYPE_MMXWCG
))
7834 inst
.error
= _("iWMMXt control register expected");
7837 inst
.operands
[i
].reg
= rege
->number
;
7838 inst
.operands
[i
].isreg
= 1;
7843 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7844 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7845 case OP_oROR
: val
= parse_ror (&str
); break;
7847 case OP_COND
: val
= parse_cond (&str
); break;
7848 case OP_oBARRIER_I15
:
7849 po_barrier_or_imm (str
); break;
7851 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7857 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7858 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7860 inst
.error
= _("Banked registers are not available with this "
7866 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7870 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7873 val
= parse_sys_vldr_vstr (&str
);
7877 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7880 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7882 if (strncasecmp (str
, "APSR_", 5) == 0)
7889 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7890 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7891 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7892 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7893 default: found
= 16;
7897 inst
.operands
[i
].isvec
= 1;
7898 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7899 inst
.operands
[i
].reg
= REG_PC
;
7906 po_misc_or_fail (parse_tb (&str
));
7909 /* Register lists. */
7911 val
= parse_reg_list (&str
, REGLIST_RN
);
7914 inst
.operands
[i
].writeback
= 1;
7920 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7924 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7929 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7934 /* Allow Q registers too. */
7935 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7936 REGLIST_NEON_D
, &partial_match
);
7940 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7941 REGLIST_VFP_S
, &partial_match
);
7942 inst
.operands
[i
].issingle
= 1;
7947 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7948 REGLIST_VFP_D_VPR
, &partial_match
);
7949 if (val
== FAIL
&& !partial_match
)
7952 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7953 REGLIST_VFP_S_VPR
, &partial_match
);
7954 inst
.operands
[i
].issingle
= 1;
7959 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7960 REGLIST_NEON_D
, &partial_match
);
7965 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7966 1, &inst
.operands
[i
].vectype
);
7967 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7971 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7972 0, &inst
.operands
[i
].vectype
);
7975 /* Addressing modes */
7977 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7981 po_misc_or_fail (parse_address (&str
, i
));
7985 po_misc_or_fail_no_backtrack (
7986 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7990 po_misc_or_fail_no_backtrack (
7991 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7995 po_misc_or_fail_no_backtrack (
7996 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
8000 po_misc_or_fail (parse_shifter_operand (&str
, i
));
8004 po_misc_or_fail_no_backtrack (
8005 parse_shifter_operand_group_reloc (&str
, i
));
8009 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
8013 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
8017 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
8022 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
8027 po_reg_or_goto (REG_TYPE_RN
, ZR
);
8030 po_reg_or_fail (REG_TYPE_ZR
);
8034 as_fatal (_("unhandled operand code %d"), op_parse_code
);
8037 /* Various value-based sanity checks and shared operations. We
8038 do not signal immediate failures for the register constraints;
8039 this allows a syntax error to take precedence. */
8040 switch (op_parse_code
)
8048 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
8049 inst
.error
= BAD_PC
;
8054 case OP_RRnpcsp_I32
:
8055 if (inst
.operands
[i
].isreg
)
8057 if (inst
.operands
[i
].reg
== REG_PC
)
8058 inst
.error
= BAD_PC
;
8059 else if (inst
.operands
[i
].reg
== REG_SP
8060 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
8061 relaxed since ARMv8-A. */
8062 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8065 inst
.error
= BAD_SP
;
8071 if (inst
.operands
[i
].isreg
8072 && inst
.operands
[i
].reg
== REG_PC
8073 && (inst
.operands
[i
].writeback
|| thumb
))
8074 inst
.error
= BAD_PC
;
8079 if (inst
.operands
[i
].isreg
)
8089 case OP_oBARRIER_I15
:
8102 inst
.operands
[i
].imm
= val
;
8107 if (inst
.operands
[i
].reg
!= REG_LR
)
8108 inst
.error
= _("operand must be LR register");
8114 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
8115 inst
.error
= BAD_PC
;
8119 if (inst
.operands
[i
].isreg
8120 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
8121 inst
.error
= BAD_ODD
;
8125 if (inst
.operands
[i
].isreg
)
8127 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
8128 inst
.error
= BAD_EVEN
;
8129 else if (inst
.operands
[i
].reg
== REG_SP
)
8130 as_tsktsk (MVE_BAD_SP
);
8131 else if (inst
.operands
[i
].reg
== REG_PC
)
8132 inst
.error
= BAD_PC
;
8140 /* If we get here, this operand was successfully parsed. */
8141 inst
.operands
[i
].present
= 1;
8145 inst
.error
= BAD_ARGS
;
8150 /* The parse routine should already have set inst.error, but set a
8151 default here just in case. */
8153 inst
.error
= BAD_SYNTAX
;
8157 /* Do not backtrack over a trailing optional argument that
8158 absorbed some text. We will only fail again, with the
8159 'garbage following instruction' error message, which is
8160 probably less helpful than the current one. */
8161 if (backtrack_index
== i
&& backtrack_pos
!= str
8162 && upat
[i
+1] == OP_stop
)
8165 inst
.error
= BAD_SYNTAX
;
8169 /* Try again, skipping the optional argument at backtrack_pos. */
8170 str
= backtrack_pos
;
8171 inst
.error
= backtrack_error
;
8172 inst
.operands
[backtrack_index
].present
= 0;
8173 i
= backtrack_index
;
8177 /* Check that we have parsed all the arguments. */
8178 if (*str
!= '\0' && !inst
.error
)
8179 inst
.error
= _("garbage following instruction");
8181 return inst
.error
? FAIL
: SUCCESS
;
8184 #undef po_char_or_fail
8185 #undef po_reg_or_fail
8186 #undef po_reg_or_goto
8187 #undef po_imm_or_fail
8188 #undef po_scalar_or_fail
8189 #undef po_barrier_or_imm
8191 /* Shorthand macro for instruction encoding functions issuing errors. */
8192 #define constraint(expr, err) \
8203 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8204 instructions are unpredictable if these registers are used. This
8205 is the BadReg predicate in ARM's Thumb-2 documentation.
8207 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8208 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8209 #define reject_bad_reg(reg) \
8211 if (reg == REG_PC) \
8213 inst.error = BAD_PC; \
8216 else if (reg == REG_SP \
8217 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8219 inst.error = BAD_SP; \
8224 /* If REG is R13 (the stack pointer), warn that its use is
8226 #define warn_deprecated_sp(reg) \
8228 if (warn_on_deprecated && reg == REG_SP) \
8229 as_tsktsk (_("use of r13 is deprecated")); \
8232 /* Functions for operand encoding. ARM, then Thumb. */
8234 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8236 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8238 The only binary encoding difference is the Coprocessor number. Coprocessor
8239 9 is used for half-precision calculations or conversions. The format of the
8240 instruction is the same as the equivalent Coprocessor 10 instruction that
8241 exists for Single-Precision operation. */
8244 do_scalar_fp16_v82_encode (void)
8246 if (inst
.cond
< COND_ALWAYS
)
8247 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8248 " the behaviour is UNPREDICTABLE"));
8249 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8252 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8253 mark_feature_used (&arm_ext_fp16
);
8256 /* If VAL can be encoded in the immediate field of an ARM instruction,
8257 return the encoded form. Otherwise, return FAIL. */
8260 encode_arm_immediate (unsigned int val
)
8267 for (i
= 2; i
< 32; i
+= 2)
8268 if ((a
= rotate_left (val
, i
)) <= 0xff)
8269 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8274 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8275 return the encoded form. Otherwise, return FAIL. */
8277 encode_thumb32_immediate (unsigned int val
)
8284 for (i
= 1; i
<= 24; i
++)
8287 if ((val
& ~(0xff << i
)) == 0)
8288 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8292 if (val
== ((a
<< 16) | a
))
8294 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8298 if (val
== ((a
<< 16) | a
))
8299 return 0x200 | (a
>> 8);
8303 /* Encode a VFP SP or DP register number into inst.instruction. */
8306 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8308 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8311 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8314 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8317 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8322 first_error (_("D register out of range for selected VFP version"));
8330 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8334 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8338 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8342 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8346 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8350 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8358 /* Encode a <shift> in an ARM-format instruction. The immediate,
8359 if any, is handled by md_apply_fix. */
8361 encode_arm_shift (int i
)
8363 /* register-shifted register. */
8364 if (inst
.operands
[i
].immisreg
)
8367 for (op_index
= 0; op_index
<= i
; ++op_index
)
8369 /* Check the operand only when it's presented. In pre-UAL syntax,
8370 if the destination register is the same as the first operand, two
8371 register form of the instruction can be used. */
8372 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8373 && inst
.operands
[op_index
].reg
== REG_PC
)
8374 as_warn (UNPRED_REG ("r15"));
8377 if (inst
.operands
[i
].imm
== REG_PC
)
8378 as_warn (UNPRED_REG ("r15"));
8381 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8382 inst
.instruction
|= SHIFT_ROR
<< 5;
8385 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8386 if (inst
.operands
[i
].immisreg
)
8388 inst
.instruction
|= SHIFT_BY_REG
;
8389 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8392 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8397 encode_arm_shifter_operand (int i
)
8399 if (inst
.operands
[i
].isreg
)
8401 inst
.instruction
|= inst
.operands
[i
].reg
;
8402 encode_arm_shift (i
);
8406 inst
.instruction
|= INST_IMMEDIATE
;
8407 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8408 inst
.instruction
|= inst
.operands
[i
].imm
;
8412 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8414 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8417 Generate an error if the operand is not a register. */
8418 constraint (!inst
.operands
[i
].isreg
,
8419 _("Instruction does not support =N addresses"));
8421 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8423 if (inst
.operands
[i
].preind
)
8427 inst
.error
= _("instruction does not accept preindexed addressing");
8430 inst
.instruction
|= PRE_INDEX
;
8431 if (inst
.operands
[i
].writeback
)
8432 inst
.instruction
|= WRITE_BACK
;
8435 else if (inst
.operands
[i
].postind
)
8437 gas_assert (inst
.operands
[i
].writeback
);
8439 inst
.instruction
|= WRITE_BACK
;
8441 else /* unindexed - only for coprocessor */
8443 inst
.error
= _("instruction does not accept unindexed addressing");
8447 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8448 && (((inst
.instruction
& 0x000f0000) >> 16)
8449 == ((inst
.instruction
& 0x0000f000) >> 12)))
8450 as_warn ((inst
.instruction
& LOAD_BIT
)
8451 ? _("destination register same as write-back base")
8452 : _("source register same as write-back base"));
8455 /* inst.operands[i] was set up by parse_address. Encode it into an
8456 ARM-format mode 2 load or store instruction. If is_t is true,
8457 reject forms that cannot be used with a T instruction (i.e. not
8460 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8462 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8464 encode_arm_addr_mode_common (i
, is_t
);
8466 if (inst
.operands
[i
].immisreg
)
8468 constraint ((inst
.operands
[i
].imm
== REG_PC
8469 || (is_pc
&& inst
.operands
[i
].writeback
)),
8471 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8472 inst
.instruction
|= inst
.operands
[i
].imm
;
8473 if (!inst
.operands
[i
].negative
)
8474 inst
.instruction
|= INDEX_UP
;
8475 if (inst
.operands
[i
].shifted
)
8477 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8478 inst
.instruction
|= SHIFT_ROR
<< 5;
8481 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8482 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8486 else /* immediate offset in inst.relocs[0] */
8488 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8490 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8492 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8493 cannot use PC in addressing.
8494 PC cannot be used in writeback addressing, either. */
8495 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8498 /* Use of PC in str is deprecated for ARMv7. */
8499 if (warn_on_deprecated
8501 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8502 as_tsktsk (_("use of PC in this instruction is deprecated"));
8505 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8507 /* Prefer + for zero encoded value. */
8508 if (!inst
.operands
[i
].negative
)
8509 inst
.instruction
|= INDEX_UP
;
8510 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8515 /* inst.operands[i] was set up by parse_address. Encode it into an
8516 ARM-format mode 3 load or store instruction. Reject forms that
8517 cannot be used with such instructions. If is_t is true, reject
8518 forms that cannot be used with a T instruction (i.e. not
8521 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8523 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8525 inst
.error
= _("instruction does not accept scaled register index");
8529 encode_arm_addr_mode_common (i
, is_t
);
8531 if (inst
.operands
[i
].immisreg
)
8533 constraint ((inst
.operands
[i
].imm
== REG_PC
8534 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8536 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8538 inst
.instruction
|= inst
.operands
[i
].imm
;
8539 if (!inst
.operands
[i
].negative
)
8540 inst
.instruction
|= INDEX_UP
;
8542 else /* immediate offset in inst.relocs[0] */
8544 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8545 && inst
.operands
[i
].writeback
),
8547 inst
.instruction
|= HWOFFSET_IMM
;
8548 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8550 /* Prefer + for zero encoded value. */
8551 if (!inst
.operands
[i
].negative
)
8552 inst
.instruction
|= INDEX_UP
;
8554 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8559 /* Write immediate bits [7:0] to the following locations:
8561 |28/24|23 19|18 16|15 4|3 0|
8562 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8564 This function is used by VMOV/VMVN/VORR/VBIC. */
8567 neon_write_immbits (unsigned immbits
)
8569 inst
.instruction
|= immbits
& 0xf;
8570 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8571 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8574 /* Invert low-order SIZE bits of XHI:XLO. */
8577 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8579 unsigned immlo
= xlo
? *xlo
: 0;
8580 unsigned immhi
= xhi
? *xhi
: 0;
8585 immlo
= (~immlo
) & 0xff;
8589 immlo
= (~immlo
) & 0xffff;
8593 immhi
= (~immhi
) & 0xffffffff;
8597 immlo
= (~immlo
) & 0xffffffff;
8611 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8615 neon_bits_same_in_bytes (unsigned imm
)
8617 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8618 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8619 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8620 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8623 /* For immediate of above form, return 0bABCD. */
8626 neon_squash_bits (unsigned imm
)
8628 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8629 | ((imm
& 0x01000000) >> 21);
8632 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8635 neon_qfloat_bits (unsigned imm
)
8637 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8640 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8641 the instruction. *OP is passed as the initial value of the op field, and
8642 may be set to a different value depending on the constant (i.e.
8643 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8644 MVN). If the immediate looks like a repeated pattern then also
8645 try smaller element sizes. */
8648 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8649 unsigned *immbits
, int *op
, int size
,
8650 enum neon_el_type type
)
8652 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8654 if (type
== NT_float
&& !float_p
)
8657 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8659 if (size
!= 32 || *op
== 1)
8661 *immbits
= neon_qfloat_bits (immlo
);
8667 if (neon_bits_same_in_bytes (immhi
)
8668 && neon_bits_same_in_bytes (immlo
))
8672 *immbits
= (neon_squash_bits (immhi
) << 4)
8673 | neon_squash_bits (immlo
);
8684 if (immlo
== (immlo
& 0x000000ff))
8689 else if (immlo
== (immlo
& 0x0000ff00))
8691 *immbits
= immlo
>> 8;
8694 else if (immlo
== (immlo
& 0x00ff0000))
8696 *immbits
= immlo
>> 16;
8699 else if (immlo
== (immlo
& 0xff000000))
8701 *immbits
= immlo
>> 24;
8704 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8706 *immbits
= (immlo
>> 8) & 0xff;
8709 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8711 *immbits
= (immlo
>> 16) & 0xff;
8715 if ((immlo
& 0xffff) != (immlo
>> 16))
8722 if (immlo
== (immlo
& 0x000000ff))
8727 else if (immlo
== (immlo
& 0x0000ff00))
8729 *immbits
= immlo
>> 8;
8733 if ((immlo
& 0xff) != (immlo
>> 8))
8738 if (immlo
== (immlo
& 0x000000ff))
8740 /* Don't allow MVN with 8-bit immediate. */
8750 #if defined BFD_HOST_64_BIT
8751 /* Returns TRUE if double precision value V may be cast
8752 to single precision without loss of accuracy. */
8755 is_double_a_single (bfd_int64_t v
)
8757 int exp
= (int)((v
>> 52) & 0x7FF);
8758 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8760 return (exp
== 0 || exp
== 0x7FF
8761 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8762 && (mantissa
& 0x1FFFFFFFl
) == 0;
8765 /* Returns a double precision value casted to single precision
8766 (ignoring the least significant bits in exponent and mantissa). */
8769 double_to_single (bfd_int64_t v
)
8771 int sign
= (int) ((v
>> 63) & 1l);
8772 int exp
= (int) ((v
>> 52) & 0x7FF);
8773 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8779 exp
= exp
- 1023 + 127;
8788 /* No denormalized numbers. */
8794 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8796 #endif /* BFD_HOST_64_BIT */
8805 static void do_vfp_nsyn_opcode (const char *);
8807 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8808 Determine whether it can be performed with a move instruction; if
8809 it can, convert inst.instruction to that move instruction and
8810 return TRUE; if it can't, convert inst.instruction to a literal-pool
8811 load and return FALSE. If this is not a valid thing to do in the
8812 current context, set inst.error and return TRUE.
8814 inst.operands[i] describes the destination register. */
8817 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8820 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8821 bfd_boolean arm_p
= (t
== CONST_ARM
);
8824 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8828 if ((inst
.instruction
& tbit
) == 0)
8830 inst
.error
= _("invalid pseudo operation");
8834 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8835 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8836 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8838 inst
.error
= _("constant expression expected");
8842 if (inst
.relocs
[0].exp
.X_op
== O_constant
8843 || inst
.relocs
[0].exp
.X_op
== O_big
)
8845 #if defined BFD_HOST_64_BIT
8850 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8852 LITTLENUM_TYPE w
[X_PRECISION
];
8855 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8857 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8859 /* FIXME: Should we check words w[2..5] ? */
8864 #if defined BFD_HOST_64_BIT
8866 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8867 << LITTLENUM_NUMBER_OF_BITS
)
8868 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8869 << LITTLENUM_NUMBER_OF_BITS
)
8870 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8871 << LITTLENUM_NUMBER_OF_BITS
)
8872 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8874 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8875 | (l
[0] & LITTLENUM_MASK
);
8879 v
= inst
.relocs
[0].exp
.X_add_number
;
8881 if (!inst
.operands
[i
].issingle
)
8885 /* LDR should not use lead in a flag-setting instruction being
8886 chosen so we do not check whether movs can be used. */
8888 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8889 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8890 && inst
.operands
[i
].reg
!= 13
8891 && inst
.operands
[i
].reg
!= 15)
8893 /* Check if on thumb2 it can be done with a mov.w, mvn or
8894 movw instruction. */
8895 unsigned int newimm
;
8896 bfd_boolean isNegated
;
8898 newimm
= encode_thumb32_immediate (v
);
8899 if (newimm
!= (unsigned int) FAIL
)
8903 newimm
= encode_thumb32_immediate (~v
);
8904 if (newimm
!= (unsigned int) FAIL
)
8908 /* The number can be loaded with a mov.w or mvn
8910 if (newimm
!= (unsigned int) FAIL
8911 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8913 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8914 | (inst
.operands
[i
].reg
<< 8));
8915 /* Change to MOVN. */
8916 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8917 inst
.instruction
|= (newimm
& 0x800) << 15;
8918 inst
.instruction
|= (newimm
& 0x700) << 4;
8919 inst
.instruction
|= (newimm
& 0x0ff);
8922 /* The number can be loaded with a movw instruction. */
8923 else if ((v
& ~0xFFFF) == 0
8924 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8926 int imm
= v
& 0xFFFF;
8928 inst
.instruction
= 0xf2400000; /* MOVW. */
8929 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8930 inst
.instruction
|= (imm
& 0xf000) << 4;
8931 inst
.instruction
|= (imm
& 0x0800) << 15;
8932 inst
.instruction
|= (imm
& 0x0700) << 4;
8933 inst
.instruction
|= (imm
& 0x00ff);
8934 /* In case this replacement is being done on Armv8-M
8935 Baseline we need to make sure to disable the
8936 instruction size check, as otherwise GAS will reject
8937 the use of this T32 instruction. */
8945 int value
= encode_arm_immediate (v
);
8949 /* This can be done with a mov instruction. */
8950 inst
.instruction
&= LITERAL_MASK
;
8951 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8952 inst
.instruction
|= value
& 0xfff;
8956 value
= encode_arm_immediate (~ v
);
8959 /* This can be done with a mvn instruction. */
8960 inst
.instruction
&= LITERAL_MASK
;
8961 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8962 inst
.instruction
|= value
& 0xfff;
8966 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8969 unsigned immbits
= 0;
8970 unsigned immlo
= inst
.operands
[1].imm
;
8971 unsigned immhi
= inst
.operands
[1].regisimm
8972 ? inst
.operands
[1].reg
8973 : inst
.relocs
[0].exp
.X_unsigned
8975 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8976 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8977 &op
, 64, NT_invtype
);
8981 neon_invert_size (&immlo
, &immhi
, 64);
8983 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8984 &op
, 64, NT_invtype
);
8989 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8995 /* Fill other bits in vmov encoding for both thumb and arm. */
8997 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8999 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
9000 neon_write_immbits (immbits
);
9008 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
9009 if (inst
.operands
[i
].issingle
9010 && is_quarter_float (inst
.operands
[1].imm
)
9011 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
9013 inst
.operands
[1].imm
=
9014 neon_qfloat_bits (v
);
9015 do_vfp_nsyn_opcode ("fconsts");
9019 /* If our host does not support a 64-bit type then we cannot perform
9020 the following optimization. This mean that there will be a
9021 discrepancy between the output produced by an assembler built for
9022 a 32-bit-only host and the output produced from a 64-bit host, but
9023 this cannot be helped. */
9024 #if defined BFD_HOST_64_BIT
9025 else if (!inst
.operands
[1].issingle
9026 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
9028 if (is_double_a_single (v
)
9029 && is_quarter_float (double_to_single (v
)))
9031 inst
.operands
[1].imm
=
9032 neon_qfloat_bits (double_to_single (v
));
9033 do_vfp_nsyn_opcode ("fconstd");
9041 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
9042 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
9045 inst
.operands
[1].reg
= REG_PC
;
9046 inst
.operands
[1].isreg
= 1;
9047 inst
.operands
[1].preind
= 1;
9048 inst
.relocs
[0].pc_rel
= 1;
9049 inst
.relocs
[0].type
= (thumb_p
9050 ? BFD_RELOC_ARM_THUMB_OFFSET
9052 ? BFD_RELOC_ARM_HWLITERAL
9053 : BFD_RELOC_ARM_LITERAL
));
9057 /* inst.operands[i] was set up by parse_address. Encode it into an
9058 ARM-format instruction. Reject all forms which cannot be encoded
9059 into a coprocessor load/store instruction. If wb_ok is false,
9060 reject use of writeback; if unind_ok is false, reject use of
9061 unindexed addressing. If reloc_override is not 0, use it instead
9062 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
9063 (in which case it is preserved). */
9066 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
9068 if (!inst
.operands
[i
].isreg
)
9071 if (! inst
.operands
[0].isvec
)
9073 inst
.error
= _("invalid co-processor operand");
9076 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
9080 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9082 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
9084 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
9086 gas_assert (!inst
.operands
[i
].writeback
);
9089 inst
.error
= _("instruction does not support unindexed addressing");
9092 inst
.instruction
|= inst
.operands
[i
].imm
;
9093 inst
.instruction
|= INDEX_UP
;
9097 if (inst
.operands
[i
].preind
)
9098 inst
.instruction
|= PRE_INDEX
;
9100 if (inst
.operands
[i
].writeback
)
9102 if (inst
.operands
[i
].reg
== REG_PC
)
9104 inst
.error
= _("pc may not be used with write-back");
9109 inst
.error
= _("instruction does not support writeback");
9112 inst
.instruction
|= WRITE_BACK
;
9116 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
9117 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
9118 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
9119 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
9122 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
9124 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
9127 /* Prefer + for zero encoded value. */
9128 if (!inst
.operands
[i
].negative
)
9129 inst
.instruction
|= INDEX_UP
;
9134 /* Functions for instruction encoding, sorted by sub-architecture.
9135 First some generics; their names are taken from the conventional
9136 bit positions for register arguments in ARM format instructions. */
9146 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9152 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9158 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9159 inst
.instruction
|= inst
.operands
[1].reg
;
9165 inst
.instruction
|= inst
.operands
[0].reg
;
9166 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9172 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9173 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9179 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9180 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9186 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9191 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9193 if (ARM_CPU_IS_ANY (cpu_variant
))
9195 as_tsktsk ("%s", msg
);
9198 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9210 unsigned Rn
= inst
.operands
[2].reg
;
9211 /* Enforce restrictions on SWP instruction. */
9212 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9214 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9215 _("Rn must not overlap other operands"));
9217 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9219 if (!check_obsolete (&arm_ext_v8
,
9220 _("swp{b} use is obsoleted for ARMv8 and later"))
9221 && warn_on_deprecated
9222 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9223 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9227 inst
.instruction
|= inst
.operands
[1].reg
;
9228 inst
.instruction
|= Rn
<< 16;
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9235 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9236 inst
.instruction
|= inst
.operands
[2].reg
;
9242 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9243 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9244 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9245 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9247 inst
.instruction
|= inst
.operands
[0].reg
;
9248 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9249 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9255 inst
.instruction
|= inst
.operands
[0].imm
;
9261 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9262 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9265 /* ARM instructions, in alphabetical order by function name (except
9266 that wrapper functions appear immediately after the function they
9269 /* This is a pseudo-op of the form "adr rd, label" to be converted
9270 into a relative address of the form "add rd, pc, #label-.-8". */
9275 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9277 /* Frag hacking will turn this into a sub instruction if the offset turns
9278 out to be negative. */
9279 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9280 inst
.relocs
[0].pc_rel
= 1;
9281 inst
.relocs
[0].exp
.X_add_number
-= 8;
9283 if (support_interwork
9284 && inst
.relocs
[0].exp
.X_op
== O_symbol
9285 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9286 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9287 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9288 inst
.relocs
[0].exp
.X_add_number
|= 1;
9291 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9292 into a relative address of the form:
9293 add rd, pc, #low(label-.-8)"
9294 add rd, rd, #high(label-.-8)" */
9299 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9301 /* Frag hacking will turn this into a sub instruction if the offset turns
9302 out to be negative. */
9303 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9304 inst
.relocs
[0].pc_rel
= 1;
9305 inst
.size
= INSN_SIZE
* 2;
9306 inst
.relocs
[0].exp
.X_add_number
-= 8;
9308 if (support_interwork
9309 && inst
.relocs
[0].exp
.X_op
== O_symbol
9310 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9311 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9312 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9313 inst
.relocs
[0].exp
.X_add_number
|= 1;
9319 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9320 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9322 if (!inst
.operands
[1].present
)
9323 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9324 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9325 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9326 encode_arm_shifter_operand (2);
9332 if (inst
.operands
[0].present
)
9333 inst
.instruction
|= inst
.operands
[0].imm
;
9335 inst
.instruction
|= 0xf;
9341 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9342 constraint (msb
> 32, _("bit-field extends past end of register"));
9343 /* The instruction encoding stores the LSB and MSB,
9344 not the LSB and width. */
9345 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9346 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9347 inst
.instruction
|= (msb
- 1) << 16;
9355 /* #0 in second position is alternative syntax for bfc, which is
9356 the same instruction but with REG_PC in the Rm field. */
9357 if (!inst
.operands
[1].isreg
)
9358 inst
.operands
[1].reg
= REG_PC
;
9360 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9361 constraint (msb
> 32, _("bit-field extends past end of register"));
9362 /* The instruction encoding stores the LSB and MSB,
9363 not the LSB and width. */
9364 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9365 inst
.instruction
|= inst
.operands
[1].reg
;
9366 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9367 inst
.instruction
|= (msb
- 1) << 16;
9373 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9374 _("bit-field extends past end of register"));
9375 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9376 inst
.instruction
|= inst
.operands
[1].reg
;
9377 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9378 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9381 /* ARM V5 breakpoint instruction (argument parse)
9382 BKPT <16 bit unsigned immediate>
9383 Instruction is not conditional.
9384 The bit pattern given in insns[] has the COND_ALWAYS condition,
9385 and it is an error if the caller tried to override that. */
9390 /* Top 12 of 16 bits to bits 19:8. */
9391 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9393 /* Bottom 4 of 16 bits to bits 3:0. */
9394 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9398 encode_branch (int default_reloc
)
9400 if (inst
.operands
[0].hasreloc
)
9402 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9403 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9404 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9405 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9406 ? BFD_RELOC_ARM_PLT32
9407 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9410 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9411 inst
.relocs
[0].pc_rel
= 1;
9418 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9419 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9422 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9429 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9431 if (inst
.cond
== COND_ALWAYS
)
9432 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9434 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9438 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9441 /* ARM V5 branch-link-exchange instruction (argument parse)
9442 BLX <target_addr> ie BLX(1)
9443 BLX{<condition>} <Rm> ie BLX(2)
9444 Unfortunately, there are two different opcodes for this mnemonic.
9445 So, the insns[].value is not used, and the code here zaps values
9446 into inst.instruction.
9447 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9452 if (inst
.operands
[0].isreg
)
9454 /* Arg is a register; the opcode provided by insns[] is correct.
9455 It is not illegal to do "blx pc", just useless. */
9456 if (inst
.operands
[0].reg
== REG_PC
)
9457 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9459 inst
.instruction
|= inst
.operands
[0].reg
;
9463 /* Arg is an address; this instruction cannot be executed
9464 conditionally, and the opcode must be adjusted.
9465 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9466 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9467 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9468 inst
.instruction
= 0xfa000000;
9469 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9476 bfd_boolean want_reloc
;
9478 if (inst
.operands
[0].reg
== REG_PC
)
9479 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9481 inst
.instruction
|= inst
.operands
[0].reg
;
9482 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9483 it is for ARMv4t or earlier. */
9484 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9485 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9486 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9490 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9495 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9499 /* ARM v5TEJ. Jump to Jazelle code. */
9504 if (inst
.operands
[0].reg
== REG_PC
)
9505 as_tsktsk (_("use of r15 in bxj is not really useful"));
9507 inst
.instruction
|= inst
.operands
[0].reg
;
9510 /* Co-processor data operation:
9511 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9512 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9516 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9517 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9518 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9519 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9520 inst
.instruction
|= inst
.operands
[4].reg
;
9521 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9527 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9528 encode_arm_shifter_operand (1);
9531 /* Transfer between coprocessor and ARM registers.
9532 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9537 No special properties. */
9539 struct deprecated_coproc_regs_s
9546 arm_feature_set deprecated
;
9547 arm_feature_set obsoleted
;
9548 const char *dep_msg
;
9549 const char *obs_msg
;
9552 #define DEPR_ACCESS_V8 \
9553 N_("This coprocessor register access is deprecated in ARMv8")
9555 /* Table of all deprecated coprocessor registers. */
9556 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9558 {15, 0, 7, 10, 5, /* CP15DMB. */
9559 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9560 DEPR_ACCESS_V8
, NULL
},
9561 {15, 0, 7, 10, 4, /* CP15DSB. */
9562 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9563 DEPR_ACCESS_V8
, NULL
},
9564 {15, 0, 7, 5, 4, /* CP15ISB. */
9565 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9566 DEPR_ACCESS_V8
, NULL
},
9567 {14, 6, 1, 0, 0, /* TEEHBR. */
9568 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9569 DEPR_ACCESS_V8
, NULL
},
9570 {14, 6, 0, 0, 0, /* TEECR. */
9571 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9572 DEPR_ACCESS_V8
, NULL
},
9575 #undef DEPR_ACCESS_V8
9577 static const size_t deprecated_coproc_reg_count
=
9578 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9586 Rd
= inst
.operands
[2].reg
;
9589 if (inst
.instruction
== 0xee000010
9590 || inst
.instruction
== 0xfe000010)
9592 reject_bad_reg (Rd
);
9593 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9595 constraint (Rd
== REG_SP
, BAD_SP
);
9600 if (inst
.instruction
== 0xe000010)
9601 constraint (Rd
== REG_PC
, BAD_PC
);
9604 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9606 const struct deprecated_coproc_regs_s
*r
=
9607 deprecated_coproc_regs
+ i
;
9609 if (inst
.operands
[0].reg
== r
->cp
9610 && inst
.operands
[1].imm
== r
->opc1
9611 && inst
.operands
[3].reg
== r
->crn
9612 && inst
.operands
[4].reg
== r
->crm
9613 && inst
.operands
[5].imm
== r
->opc2
)
9615 if (! ARM_CPU_IS_ANY (cpu_variant
)
9616 && warn_on_deprecated
9617 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9618 as_tsktsk ("%s", r
->dep_msg
);
9622 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9623 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9624 inst
.instruction
|= Rd
<< 12;
9625 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9626 inst
.instruction
|= inst
.operands
[4].reg
;
9627 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9630 /* Transfer between coprocessor register and pair of ARM registers.
9631 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9636 Two XScale instructions are special cases of these:
9638 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9639 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9641 Result unpredictable if Rd or Rn is R15. */
9648 Rd
= inst
.operands
[2].reg
;
9649 Rn
= inst
.operands
[3].reg
;
9653 reject_bad_reg (Rd
);
9654 reject_bad_reg (Rn
);
9658 constraint (Rd
== REG_PC
, BAD_PC
);
9659 constraint (Rn
== REG_PC
, BAD_PC
);
9662 /* Only check the MRRC{2} variants. */
9663 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9665 /* If Rd == Rn, error that the operation is
9666 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9667 constraint (Rd
== Rn
, BAD_OVERLAP
);
9670 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9671 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9672 inst
.instruction
|= Rd
<< 12;
9673 inst
.instruction
|= Rn
<< 16;
9674 inst
.instruction
|= inst
.operands
[4].reg
;
9680 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9681 if (inst
.operands
[1].present
)
9683 inst
.instruction
|= CPSI_MMOD
;
9684 inst
.instruction
|= inst
.operands
[1].imm
;
9691 inst
.instruction
|= inst
.operands
[0].imm
;
9697 unsigned Rd
, Rn
, Rm
;
9699 Rd
= inst
.operands
[0].reg
;
9700 Rn
= (inst
.operands
[1].present
9701 ? inst
.operands
[1].reg
: Rd
);
9702 Rm
= inst
.operands
[2].reg
;
9704 constraint ((Rd
== REG_PC
), BAD_PC
);
9705 constraint ((Rn
== REG_PC
), BAD_PC
);
9706 constraint ((Rm
== REG_PC
), BAD_PC
);
9708 inst
.instruction
|= Rd
<< 16;
9709 inst
.instruction
|= Rn
<< 0;
9710 inst
.instruction
|= Rm
<< 8;
9716 /* There is no IT instruction in ARM mode. We
9717 process it to do the validation as if in
9718 thumb mode, just in case the code gets
9719 assembled for thumb using the unified syntax. */
9724 set_pred_insn_type (IT_INSN
);
9725 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9726 now_pred
.cc
= inst
.operands
[0].imm
;
9730 /* If there is only one register in the register list,
9731 then return its register number. Otherwise return -1. */
9733 only_one_reg_in_list (int range
)
9735 int i
= ffs (range
) - 1;
9736 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9740 encode_ldmstm(int from_push_pop_mnem
)
9742 int base_reg
= inst
.operands
[0].reg
;
9743 int range
= inst
.operands
[1].imm
;
9746 inst
.instruction
|= base_reg
<< 16;
9747 inst
.instruction
|= range
;
9749 if (inst
.operands
[1].writeback
)
9750 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9752 if (inst
.operands
[0].writeback
)
9754 inst
.instruction
|= WRITE_BACK
;
9755 /* Check for unpredictable uses of writeback. */
9756 if (inst
.instruction
& LOAD_BIT
)
9758 /* Not allowed in LDM type 2. */
9759 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9760 && ((range
& (1 << REG_PC
)) == 0))
9761 as_warn (_("writeback of base register is UNPREDICTABLE"));
9762 /* Only allowed if base reg not in list for other types. */
9763 else if (range
& (1 << base_reg
))
9764 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9768 /* Not allowed for type 2. */
9769 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9770 as_warn (_("writeback of base register is UNPREDICTABLE"));
9771 /* Only allowed if base reg not in list, or first in list. */
9772 else if ((range
& (1 << base_reg
))
9773 && (range
& ((1 << base_reg
) - 1)))
9774 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9778 /* If PUSH/POP has only one register, then use the A2 encoding. */
9779 one_reg
= only_one_reg_in_list (range
);
9780 if (from_push_pop_mnem
&& one_reg
>= 0)
9782 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9784 if (is_push
&& one_reg
== 13 /* SP */)
9785 /* PR 22483: The A2 encoding cannot be used when
9786 pushing the stack pointer as this is UNPREDICTABLE. */
9789 inst
.instruction
&= A_COND_MASK
;
9790 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9791 inst
.instruction
|= one_reg
<< 12;
9798 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9801 /* ARMv5TE load-consecutive (argument parse)
9810 constraint (inst
.operands
[0].reg
% 2 != 0,
9811 _("first transfer register must be even"));
9812 constraint (inst
.operands
[1].present
9813 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9814 _("can only transfer two consecutive registers"));
9815 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9816 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9818 if (!inst
.operands
[1].present
)
9819 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9821 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9822 register and the first register written; we have to diagnose
9823 overlap between the base and the second register written here. */
9825 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9826 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9827 as_warn (_("base register written back, and overlaps "
9828 "second transfer register"));
9830 if (!(inst
.instruction
& V4_STR_BIT
))
9832 /* For an index-register load, the index register must not overlap the
9833 destination (even if not write-back). */
9834 if (inst
.operands
[2].immisreg
9835 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9836 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9837 as_warn (_("index register overlaps transfer register"));
9839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9840 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9846 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9847 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9848 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9849 || inst
.operands
[1].negative
9850 /* This can arise if the programmer has written
9852 or if they have mistakenly used a register name as the last
9855 It is very difficult to distinguish between these two cases
9856 because "rX" might actually be a label. ie the register
9857 name has been occluded by a symbol of the same name. So we
9858 just generate a general 'bad addressing mode' type error
9859 message and leave it up to the programmer to discover the
9860 true cause and fix their mistake. */
9861 || (inst
.operands
[1].reg
== REG_PC
),
9864 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9865 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9866 _("offset must be zero in ARM encoding"));
9868 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9870 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9871 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9872 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9878 constraint (inst
.operands
[0].reg
% 2 != 0,
9879 _("even register required"));
9880 constraint (inst
.operands
[1].present
9881 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9882 _("can only load two consecutive registers"));
9883 /* If op 1 were present and equal to PC, this function wouldn't
9884 have been called in the first place. */
9885 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9887 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9888 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9891 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9892 which is not a multiple of four is UNPREDICTABLE. */
9894 check_ldr_r15_aligned (void)
9896 constraint (!(inst
.operands
[1].immisreg
)
9897 && (inst
.operands
[0].reg
== REG_PC
9898 && inst
.operands
[1].reg
== REG_PC
9899 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9900 _("ldr to register 15 must be 4-byte aligned"));
9906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9907 if (!inst
.operands
[1].isreg
)
9908 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9910 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9911 check_ldr_r15_aligned ();
9917 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9919 if (inst
.operands
[1].preind
)
9921 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9922 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9923 _("this instruction requires a post-indexed address"));
9925 inst
.operands
[1].preind
= 0;
9926 inst
.operands
[1].postind
= 1;
9927 inst
.operands
[1].writeback
= 1;
9929 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9930 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9933 /* Halfword and signed-byte load/store operations. */
9938 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9939 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9940 if (!inst
.operands
[1].isreg
)
9941 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9943 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9949 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9951 if (inst
.operands
[1].preind
)
9953 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9954 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9955 _("this instruction requires a post-indexed address"));
9957 inst
.operands
[1].preind
= 0;
9958 inst
.operands
[1].postind
= 1;
9959 inst
.operands
[1].writeback
= 1;
9961 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9962 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9965 /* Co-processor register load/store.
9966 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9970 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9971 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9972 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9978 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9979 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9980 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9981 && !(inst
.instruction
& 0x00400000))
9982 as_tsktsk (_("Rd and Rm should be different in mla"));
9984 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9985 inst
.instruction
|= inst
.operands
[1].reg
;
9986 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9987 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9993 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9994 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9996 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9997 encode_arm_shifter_operand (1);
10000 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
10007 top
= (inst
.instruction
& 0x00400000) != 0;
10008 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
10009 _(":lower16: not allowed in this instruction"));
10010 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
10011 _(":upper16: not allowed in this instruction"));
10012 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10013 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
10015 imm
= inst
.relocs
[0].exp
.X_add_number
;
10016 /* The value is in two pieces: 0:11, 16:19. */
10017 inst
.instruction
|= (imm
& 0x00000fff);
10018 inst
.instruction
|= (imm
& 0x0000f000) << 4;
10023 do_vfp_nsyn_mrs (void)
10025 if (inst
.operands
[0].isvec
)
10027 if (inst
.operands
[1].reg
!= 1)
10028 first_error (_("operand 1 must be FPSCR"));
10029 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
10030 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
10031 do_vfp_nsyn_opcode ("fmstat");
10033 else if (inst
.operands
[1].isvec
)
10034 do_vfp_nsyn_opcode ("fmrx");
10042 do_vfp_nsyn_msr (void)
10044 if (inst
.operands
[0].isvec
)
10045 do_vfp_nsyn_opcode ("fmxr");
10055 unsigned Rt
= inst
.operands
[0].reg
;
10057 if (thumb_mode
&& Rt
== REG_SP
)
10059 inst
.error
= BAD_SP
;
10063 switch (inst
.operands
[1].reg
)
10065 /* MVFR2 is only valid for Armv8-A. */
10067 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10071 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10072 case 1: /* fpscr. */
10073 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10074 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10078 case 14: /* fpcxt_ns. */
10079 case 15: /* fpcxt_s. */
10080 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10081 _("selected processor does not support instruction"));
10084 case 2: /* fpscr_nzcvqc. */
10085 case 12: /* vpr. */
10087 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10088 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10089 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10090 _("selected processor does not support instruction"));
10091 if (inst
.operands
[0].reg
!= 2
10092 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10093 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10100 /* APSR_ sets isvec. All other refs to PC are illegal. */
10101 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
10103 inst
.error
= BAD_PC
;
10107 /* If we get through parsing the register name, we just insert the number
10108 generated into the instruction without further validation. */
10109 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
10110 inst
.instruction
|= (Rt
<< 12);
10116 unsigned Rt
= inst
.operands
[1].reg
;
10119 reject_bad_reg (Rt
);
10120 else if (Rt
== REG_PC
)
10122 inst
.error
= BAD_PC
;
10126 switch (inst
.operands
[0].reg
)
10128 /* MVFR2 is only valid for Armv8-A. */
10130 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
10134 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
10135 case 1: /* fpcr. */
10136 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10137 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10141 case 14: /* fpcxt_ns. */
10142 case 15: /* fpcxt_s. */
10143 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10144 _("selected processor does not support instruction"));
10147 case 2: /* fpscr_nzcvqc. */
10148 case 12: /* vpr. */
10150 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10151 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10152 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10153 _("selected processor does not support instruction"));
10154 if (inst
.operands
[0].reg
!= 2
10155 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10156 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10163 /* If we get through parsing the register name, we just insert the number
10164 generated into the instruction without further validation. */
10165 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10166 inst
.instruction
|= (Rt
<< 12);
10174 if (do_vfp_nsyn_mrs () == SUCCESS
)
10177 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10178 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10180 if (inst
.operands
[1].isreg
)
10182 br
= inst
.operands
[1].reg
;
10183 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10184 as_bad (_("bad register for mrs"));
10188 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10189 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10191 _("'APSR', 'CPSR' or 'SPSR' expected"));
10192 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10195 inst
.instruction
|= br
;
10198 /* Two possible forms:
10199 "{C|S}PSR_<field>, Rm",
10200 "{C|S}PSR_f, #expression". */
10205 if (do_vfp_nsyn_msr () == SUCCESS
)
10208 inst
.instruction
|= inst
.operands
[0].imm
;
10209 if (inst
.operands
[1].isreg
)
10210 inst
.instruction
|= inst
.operands
[1].reg
;
10213 inst
.instruction
|= INST_IMMEDIATE
;
10214 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10215 inst
.relocs
[0].pc_rel
= 0;
10222 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10224 if (!inst
.operands
[2].present
)
10225 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10226 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10227 inst
.instruction
|= inst
.operands
[1].reg
;
10228 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10230 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10231 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10232 as_tsktsk (_("Rd and Rm should be different in mul"));
10235 /* Long Multiply Parser
10236 UMULL RdLo, RdHi, Rm, Rs
10237 SMULL RdLo, RdHi, Rm, Rs
10238 UMLAL RdLo, RdHi, Rm, Rs
10239 SMLAL RdLo, RdHi, Rm, Rs. */
10244 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10245 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10246 inst
.instruction
|= inst
.operands
[2].reg
;
10247 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10249 /* rdhi and rdlo must be different. */
10250 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10251 as_tsktsk (_("rdhi and rdlo must be different"));
10253 /* rdhi, rdlo and rm must all be different before armv6. */
10254 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10255 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10256 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10257 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10263 if (inst
.operands
[0].present
10264 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10266 /* Architectural NOP hints are CPSR sets with no bits selected. */
10267 inst
.instruction
&= 0xf0000000;
10268 inst
.instruction
|= 0x0320f000;
10269 if (inst
.operands
[0].present
)
10270 inst
.instruction
|= inst
.operands
[0].imm
;
10274 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10275 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10276 Condition defaults to COND_ALWAYS.
10277 Error if Rd, Rn or Rm are R15. */
10282 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10283 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10284 inst
.instruction
|= inst
.operands
[2].reg
;
10285 if (inst
.operands
[3].present
)
10286 encode_arm_shift (3);
10289 /* ARM V6 PKHTB (Argument Parse). */
10294 if (!inst
.operands
[3].present
)
10296 /* If the shift specifier is omitted, turn the instruction
10297 into pkhbt rd, rm, rn. */
10298 inst
.instruction
&= 0xfff00010;
10299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10300 inst
.instruction
|= inst
.operands
[1].reg
;
10301 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10306 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10307 inst
.instruction
|= inst
.operands
[2].reg
;
10308 encode_arm_shift (3);
10312 /* ARMv5TE: Preload-Cache
10313 MP Extensions: Preload for write
10317 Syntactically, like LDR with B=1, W=0, L=1. */
10322 constraint (!inst
.operands
[0].isreg
,
10323 _("'[' expected after PLD mnemonic"));
10324 constraint (inst
.operands
[0].postind
,
10325 _("post-indexed expression used in preload instruction"));
10326 constraint (inst
.operands
[0].writeback
,
10327 _("writeback used in preload instruction"));
10328 constraint (!inst
.operands
[0].preind
,
10329 _("unindexed addressing used in preload instruction"));
10330 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10333 /* ARMv7: PLI <addr_mode> */
10337 constraint (!inst
.operands
[0].isreg
,
10338 _("'[' expected after PLI mnemonic"));
10339 constraint (inst
.operands
[0].postind
,
10340 _("post-indexed expression used in preload instruction"));
10341 constraint (inst
.operands
[0].writeback
,
10342 _("writeback used in preload instruction"));
10343 constraint (!inst
.operands
[0].preind
,
10344 _("unindexed addressing used in preload instruction"));
10345 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10346 inst
.instruction
&= ~PRE_INDEX
;
10352 constraint (inst
.operands
[0].writeback
,
10353 _("push/pop do not support {reglist}^"));
10354 inst
.operands
[1] = inst
.operands
[0];
10355 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10356 inst
.operands
[0].isreg
= 1;
10357 inst
.operands
[0].writeback
= 1;
10358 inst
.operands
[0].reg
= REG_SP
;
10359 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10362 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10363 word at the specified address and the following word
10365 Unconditionally executed.
10366 Error if Rn is R15. */
10371 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10372 if (inst
.operands
[0].writeback
)
10373 inst
.instruction
|= WRITE_BACK
;
10376 /* ARM V6 ssat (argument parse). */
10381 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10382 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10383 inst
.instruction
|= inst
.operands
[2].reg
;
10385 if (inst
.operands
[3].present
)
10386 encode_arm_shift (3);
10389 /* ARM V6 usat (argument parse). */
10394 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10395 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10396 inst
.instruction
|= inst
.operands
[2].reg
;
10398 if (inst
.operands
[3].present
)
10399 encode_arm_shift (3);
10402 /* ARM V6 ssat16 (argument parse). */
10407 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10408 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10409 inst
.instruction
|= inst
.operands
[2].reg
;
10415 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10416 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10417 inst
.instruction
|= inst
.operands
[2].reg
;
10420 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10421 preserving the other bits.
10423 setend <endian_specifier>, where <endian_specifier> is either
10429 if (warn_on_deprecated
10430 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10431 as_tsktsk (_("setend use is deprecated for ARMv8"));
10433 if (inst
.operands
[0].imm
)
10434 inst
.instruction
|= 0x200;
10440 unsigned int Rm
= (inst
.operands
[1].present
10441 ? inst
.operands
[1].reg
10442 : inst
.operands
[0].reg
);
10444 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10445 inst
.instruction
|= Rm
;
10446 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10448 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10449 inst
.instruction
|= SHIFT_BY_REG
;
10450 /* PR 12854: Error on extraneous shifts. */
10451 constraint (inst
.operands
[2].shifted
,
10452 _("extraneous shift as part of operand to shift insn"));
10455 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10461 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10462 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10464 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10465 inst
.relocs
[0].pc_rel
= 0;
10471 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10472 inst
.relocs
[0].pc_rel
= 0;
10478 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10479 inst
.relocs
[0].pc_rel
= 0;
10485 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10486 _("selected processor does not support SETPAN instruction"));
10488 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10494 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10495 _("selected processor does not support SETPAN instruction"));
10497 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10500 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10501 SMLAxy{cond} Rd,Rm,Rs,Rn
10502 SMLAWy{cond} Rd,Rm,Rs,Rn
10503 Error if any register is R15. */
10508 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10509 inst
.instruction
|= inst
.operands
[1].reg
;
10510 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10511 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10514 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10515 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10516 Error if any register is R15.
10517 Warning if Rdlo == Rdhi. */
10522 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10523 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10524 inst
.instruction
|= inst
.operands
[2].reg
;
10525 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10527 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10528 as_tsktsk (_("rdhi and rdlo must be different"));
10531 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10532 SMULxy{cond} Rd,Rm,Rs
10533 Error if any register is R15. */
10538 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10539 inst
.instruction
|= inst
.operands
[1].reg
;
10540 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10543 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10544 the same for both ARM and Thumb-2. */
10551 if (inst
.operands
[0].present
)
10553 reg
= inst
.operands
[0].reg
;
10554 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10559 inst
.instruction
|= reg
<< 16;
10560 inst
.instruction
|= inst
.operands
[1].imm
;
10561 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10562 inst
.instruction
|= WRITE_BACK
;
10565 /* ARM V6 strex (argument parse). */
10570 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10571 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10572 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10573 || inst
.operands
[2].negative
10574 /* See comment in do_ldrex(). */
10575 || (inst
.operands
[2].reg
== REG_PC
),
10578 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10579 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10581 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10582 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10583 _("offset must be zero in ARM encoding"));
10585 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10586 inst
.instruction
|= inst
.operands
[1].reg
;
10587 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10588 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10592 do_t_strexbh (void)
10594 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10595 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10596 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10597 || inst
.operands
[2].negative
,
10600 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10601 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10609 constraint (inst
.operands
[1].reg
% 2 != 0,
10610 _("even register required"));
10611 constraint (inst
.operands
[2].present
10612 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10613 _("can only store two consecutive registers"));
10614 /* If op 2 were present and equal to PC, this function wouldn't
10615 have been called in the first place. */
10616 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10618 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10619 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10620 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10623 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10624 inst
.instruction
|= inst
.operands
[1].reg
;
10625 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10632 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10633 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10641 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10642 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10647 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10648 extends it to 32-bits, and adds the result to a value in another
10649 register. You can specify a rotation by 0, 8, 16, or 24 bits
10650 before extracting the 16-bit value.
10651 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10652 Condition defaults to COND_ALWAYS.
10653 Error if any register uses R15. */
10658 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10659 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10660 inst
.instruction
|= inst
.operands
[2].reg
;
10661 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10666 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10667 Condition defaults to COND_ALWAYS.
10668 Error if any register uses R15. */
10673 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10674 inst
.instruction
|= inst
.operands
[1].reg
;
10675 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10678 /* VFP instructions. In a logical order: SP variant first, monad
10679 before dyad, arithmetic then move then load/store. */
10682 do_vfp_sp_monadic (void)
10684 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10685 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10688 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10689 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10693 do_vfp_sp_dyadic (void)
10695 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10696 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10697 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10701 do_vfp_sp_compare_z (void)
10703 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10707 do_vfp_dp_sp_cvt (void)
10709 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10710 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10714 do_vfp_sp_dp_cvt (void)
10716 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10717 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10721 do_vfp_reg_from_sp (void)
10723 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10724 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10727 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10728 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10732 do_vfp_reg2_from_sp2 (void)
10734 constraint (inst
.operands
[2].imm
!= 2,
10735 _("only two consecutive VFP SP registers allowed here"));
10736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10737 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10738 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10742 do_vfp_sp_from_reg (void)
10744 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10745 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10748 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10749 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10753 do_vfp_sp2_from_reg2 (void)
10755 constraint (inst
.operands
[0].imm
!= 2,
10756 _("only two consecutive VFP SP registers allowed here"));
10757 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10758 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10759 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10763 do_vfp_sp_ldst (void)
10765 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10766 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10770 do_vfp_dp_ldst (void)
10772 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10773 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10778 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10780 if (inst
.operands
[0].writeback
)
10781 inst
.instruction
|= WRITE_BACK
;
10783 constraint (ldstm_type
!= VFP_LDSTMIA
,
10784 _("this addressing mode requires base-register writeback"));
10785 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10786 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10787 inst
.instruction
|= inst
.operands
[1].imm
;
10791 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10795 if (inst
.operands
[0].writeback
)
10796 inst
.instruction
|= WRITE_BACK
;
10798 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10799 _("this addressing mode requires base-register writeback"));
10801 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10802 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10804 count
= inst
.operands
[1].imm
<< 1;
10805 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10808 inst
.instruction
|= count
;
10812 do_vfp_sp_ldstmia (void)
10814 vfp_sp_ldstm (VFP_LDSTMIA
);
10818 do_vfp_sp_ldstmdb (void)
10820 vfp_sp_ldstm (VFP_LDSTMDB
);
10824 do_vfp_dp_ldstmia (void)
10826 vfp_dp_ldstm (VFP_LDSTMIA
);
10830 do_vfp_dp_ldstmdb (void)
10832 vfp_dp_ldstm (VFP_LDSTMDB
);
10836 do_vfp_xp_ldstmia (void)
10838 vfp_dp_ldstm (VFP_LDSTMIAX
);
10842 do_vfp_xp_ldstmdb (void)
10844 vfp_dp_ldstm (VFP_LDSTMDBX
);
10848 do_vfp_dp_rd_rm (void)
10850 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10851 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10854 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10855 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10859 do_vfp_dp_rn_rd (void)
10861 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10862 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10866 do_vfp_dp_rd_rn (void)
10868 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10869 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10873 do_vfp_dp_rd_rn_rm (void)
10875 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10876 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10879 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10880 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10881 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10885 do_vfp_dp_rd (void)
10887 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10891 do_vfp_dp_rm_rd_rn (void)
10893 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10894 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10897 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10898 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10899 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10902 /* VFPv3 instructions. */
10904 do_vfp_sp_const (void)
10906 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10907 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10908 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10912 do_vfp_dp_const (void)
10914 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10915 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10916 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10920 vfp_conv (int srcsize
)
10922 int immbits
= srcsize
- inst
.operands
[1].imm
;
10924 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10926 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10927 i.e. immbits must be in range 0 - 16. */
10928 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10931 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10933 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10934 i.e. immbits must be in range 0 - 31. */
10935 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10939 inst
.instruction
|= (immbits
& 1) << 5;
10940 inst
.instruction
|= (immbits
>> 1);
10944 do_vfp_sp_conv_16 (void)
10946 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10951 do_vfp_dp_conv_16 (void)
10953 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10958 do_vfp_sp_conv_32 (void)
10960 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10965 do_vfp_dp_conv_32 (void)
10967 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10971 /* FPA instructions. Also in a logical order. */
10976 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10977 inst
.instruction
|= inst
.operands
[1].reg
;
10981 do_fpa_ldmstm (void)
10983 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10984 switch (inst
.operands
[1].imm
)
10986 case 1: inst
.instruction
|= CP_T_X
; break;
10987 case 2: inst
.instruction
|= CP_T_Y
; break;
10988 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10993 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10995 /* The instruction specified "ea" or "fd", so we can only accept
10996 [Rn]{!}. The instruction does not really support stacking or
10997 unstacking, so we have to emulate these by setting appropriate
10998 bits and offsets. */
10999 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
11000 || inst
.relocs
[0].exp
.X_add_number
!= 0,
11001 _("this instruction does not support indexing"));
11003 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
11004 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
11006 if (!(inst
.instruction
& INDEX_UP
))
11007 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
11009 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
11011 inst
.operands
[2].preind
= 0;
11012 inst
.operands
[2].postind
= 1;
11016 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
11019 /* iWMMXt instructions: strictly in alphabetical order. */
11022 do_iwmmxt_tandorc (void)
11024 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
11028 do_iwmmxt_textrc (void)
11030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11031 inst
.instruction
|= inst
.operands
[1].imm
;
11035 do_iwmmxt_textrm (void)
11037 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11038 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11039 inst
.instruction
|= inst
.operands
[2].imm
;
11043 do_iwmmxt_tinsr (void)
11045 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11046 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11047 inst
.instruction
|= inst
.operands
[2].imm
;
11051 do_iwmmxt_tmia (void)
11053 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11054 inst
.instruction
|= inst
.operands
[1].reg
;
11055 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11059 do_iwmmxt_waligni (void)
11061 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11062 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11063 inst
.instruction
|= inst
.operands
[2].reg
;
11064 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
11068 do_iwmmxt_wmerge (void)
11070 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11071 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11072 inst
.instruction
|= inst
.operands
[2].reg
;
11073 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
11077 do_iwmmxt_wmov (void)
11079 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
11080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11081 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11082 inst
.instruction
|= inst
.operands
[1].reg
;
11086 do_iwmmxt_wldstbh (void)
11089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11091 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
11093 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
11094 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
11098 do_iwmmxt_wldstw (void)
11100 /* RIWR_RIWC clears .isreg for a control register. */
11101 if (!inst
.operands
[0].isreg
)
11103 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
11104 inst
.instruction
|= 0xf0000000;
11107 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11108 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
11112 do_iwmmxt_wldstd (void)
11114 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11115 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
11116 && inst
.operands
[1].immisreg
)
11118 inst
.instruction
&= ~0x1a000ff;
11119 inst
.instruction
|= (0xfU
<< 28);
11120 if (inst
.operands
[1].preind
)
11121 inst
.instruction
|= PRE_INDEX
;
11122 if (!inst
.operands
[1].negative
)
11123 inst
.instruction
|= INDEX_UP
;
11124 if (inst
.operands
[1].writeback
)
11125 inst
.instruction
|= WRITE_BACK
;
11126 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11127 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11128 inst
.instruction
|= inst
.operands
[1].imm
;
11131 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
11135 do_iwmmxt_wshufh (void)
11137 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11138 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11139 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
11140 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11144 do_iwmmxt_wzero (void)
11146 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11147 inst
.instruction
|= inst
.operands
[0].reg
;
11148 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11149 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11153 do_iwmmxt_wrwrwr_or_imm5 (void)
11155 if (inst
.operands
[2].isreg
)
11158 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11159 _("immediate operand requires iWMMXt2"));
11161 if (inst
.operands
[2].imm
== 0)
11163 switch ((inst
.instruction
>> 20) & 0xf)
11169 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11170 inst
.operands
[2].imm
= 16;
11171 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11177 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11178 inst
.operands
[2].imm
= 32;
11179 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11186 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11188 wrn
= (inst
.instruction
>> 16) & 0xf;
11189 inst
.instruction
&= 0xff0fff0f;
11190 inst
.instruction
|= wrn
;
11191 /* Bail out here; the instruction is now assembled. */
11196 /* Map 32 -> 0, etc. */
11197 inst
.operands
[2].imm
&= 0x1f;
11198 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11202 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11203 operations first, then control, shift, and load/store. */
11205 /* Insns like "foo X,Y,Z". */
11208 do_mav_triple (void)
11210 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11211 inst
.instruction
|= inst
.operands
[1].reg
;
11212 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11215 /* Insns like "foo W,X,Y,Z".
11216 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11221 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11222 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11223 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11224 inst
.instruction
|= inst
.operands
[3].reg
;
11227 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11229 do_mav_dspsc (void)
11231 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11234 /* Maverick shift immediate instructions.
11235 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11236 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11239 do_mav_shift (void)
11241 int imm
= inst
.operands
[2].imm
;
11243 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11244 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11246 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11247 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11248 Bit 4 should be 0. */
11249 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11251 inst
.instruction
|= imm
;
11254 /* XScale instructions. Also sorted arithmetic before move. */
11256 /* Xscale multiply-accumulate (argument parse)
11259 MIAxycc acc0,Rm,Rs. */
11264 inst
.instruction
|= inst
.operands
[1].reg
;
11265 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11268 /* Xscale move-accumulator-register (argument parse)
11270 MARcc acc0,RdLo,RdHi. */
11275 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11276 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11279 /* Xscale move-register-accumulator (argument parse)
11281 MRAcc RdLo,RdHi,acc0. */
11286 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11288 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11291 /* Encoding functions relevant only to Thumb. */
11293 /* inst.operands[i] is a shifted-register operand; encode
11294 it into inst.instruction in the format used by Thumb32. */
11297 encode_thumb32_shifted_operand (int i
)
11299 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11300 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11302 constraint (inst
.operands
[i
].immisreg
,
11303 _("shift by register not allowed in thumb mode"));
11304 inst
.instruction
|= inst
.operands
[i
].reg
;
11305 if (shift
== SHIFT_RRX
)
11306 inst
.instruction
|= SHIFT_ROR
<< 4;
11309 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11310 _("expression too complex"));
11312 constraint (value
> 32
11313 || (value
== 32 && (shift
== SHIFT_LSL
11314 || shift
== SHIFT_ROR
)),
11315 _("shift expression is too large"));
11319 else if (value
== 32)
11322 inst
.instruction
|= shift
<< 4;
11323 inst
.instruction
|= (value
& 0x1c) << 10;
11324 inst
.instruction
|= (value
& 0x03) << 6;
11329 /* inst.operands[i] was set up by parse_address. Encode it into a
11330 Thumb32 format load or store instruction. Reject forms that cannot
11331 be used with such instructions. If is_t is true, reject forms that
11332 cannot be used with a T instruction; if is_d is true, reject forms
11333 that cannot be used with a D instruction. If it is a store insn,
11334 reject PC in Rn. */
11337 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11339 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11341 constraint (!inst
.operands
[i
].isreg
,
11342 _("Instruction does not support =N addresses"));
11344 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11345 if (inst
.operands
[i
].immisreg
)
11347 constraint (is_pc
, BAD_PC_ADDRESSING
);
11348 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11349 constraint (inst
.operands
[i
].negative
,
11350 _("Thumb does not support negative register indexing"));
11351 constraint (inst
.operands
[i
].postind
,
11352 _("Thumb does not support register post-indexing"));
11353 constraint (inst
.operands
[i
].writeback
,
11354 _("Thumb does not support register indexing with writeback"));
11355 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11356 _("Thumb supports only LSL in shifted register indexing"));
11358 inst
.instruction
|= inst
.operands
[i
].imm
;
11359 if (inst
.operands
[i
].shifted
)
11361 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11362 _("expression too complex"));
11363 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11364 || inst
.relocs
[0].exp
.X_add_number
> 3,
11365 _("shift out of range"));
11366 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11368 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11370 else if (inst
.operands
[i
].preind
)
11372 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11373 constraint (is_t
&& inst
.operands
[i
].writeback
,
11374 _("cannot use writeback with this instruction"));
11375 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11376 BAD_PC_ADDRESSING
);
11380 inst
.instruction
|= 0x01000000;
11381 if (inst
.operands
[i
].writeback
)
11382 inst
.instruction
|= 0x00200000;
11386 inst
.instruction
|= 0x00000c00;
11387 if (inst
.operands
[i
].writeback
)
11388 inst
.instruction
|= 0x00000100;
11390 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11392 else if (inst
.operands
[i
].postind
)
11394 gas_assert (inst
.operands
[i
].writeback
);
11395 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11396 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11399 inst
.instruction
|= 0x00200000;
11401 inst
.instruction
|= 0x00000900;
11402 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11404 else /* unindexed - only for coprocessor */
11405 inst
.error
= _("instruction does not accept unindexed addressing");
11408 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11409 encodings (the latter only in post-V6T2 cores). The index is the
11410 value used in the insns table below. When there is more than one
11411 possible 16-bit encoding for the instruction, this table always
11413 Also contains several pseudo-instructions used during relaxation. */
11414 #define T16_32_TAB \
11415 X(_adc, 4140, eb400000), \
11416 X(_adcs, 4140, eb500000), \
11417 X(_add, 1c00, eb000000), \
11418 X(_adds, 1c00, eb100000), \
11419 X(_addi, 0000, f1000000), \
11420 X(_addis, 0000, f1100000), \
11421 X(_add_pc,000f, f20f0000), \
11422 X(_add_sp,000d, f10d0000), \
11423 X(_adr, 000f, f20f0000), \
11424 X(_and, 4000, ea000000), \
11425 X(_ands, 4000, ea100000), \
11426 X(_asr, 1000, fa40f000), \
11427 X(_asrs, 1000, fa50f000), \
11428 X(_b, e000, f000b000), \
11429 X(_bcond, d000, f0008000), \
11430 X(_bf, 0000, f040e001), \
11431 X(_bfcsel,0000, f000e001), \
11432 X(_bfx, 0000, f060e001), \
11433 X(_bfl, 0000, f000c001), \
11434 X(_bflx, 0000, f070e001), \
11435 X(_bic, 4380, ea200000), \
11436 X(_bics, 4380, ea300000), \
11437 X(_cinc, 0000, ea509000), \
11438 X(_cinv, 0000, ea50a000), \
11439 X(_cmn, 42c0, eb100f00), \
11440 X(_cmp, 2800, ebb00f00), \
11441 X(_cneg, 0000, ea50b000), \
11442 X(_cpsie, b660, f3af8400), \
11443 X(_cpsid, b670, f3af8600), \
11444 X(_cpy, 4600, ea4f0000), \
11445 X(_csel, 0000, ea508000), \
11446 X(_cset, 0000, ea5f900f), \
11447 X(_csetm, 0000, ea5fa00f), \
11448 X(_csinc, 0000, ea509000), \
11449 X(_csinv, 0000, ea50a000), \
11450 X(_csneg, 0000, ea50b000), \
11451 X(_dec_sp,80dd, f1ad0d00), \
11452 X(_dls, 0000, f040e001), \
11453 X(_dlstp, 0000, f000e001), \
11454 X(_eor, 4040, ea800000), \
11455 X(_eors, 4040, ea900000), \
11456 X(_inc_sp,00dd, f10d0d00), \
11457 X(_lctp, 0000, f00fe001), \
11458 X(_ldmia, c800, e8900000), \
11459 X(_ldr, 6800, f8500000), \
11460 X(_ldrb, 7800, f8100000), \
11461 X(_ldrh, 8800, f8300000), \
11462 X(_ldrsb, 5600, f9100000), \
11463 X(_ldrsh, 5e00, f9300000), \
11464 X(_ldr_pc,4800, f85f0000), \
11465 X(_ldr_pc2,4800, f85f0000), \
11466 X(_ldr_sp,9800, f85d0000), \
11467 X(_le, 0000, f00fc001), \
11468 X(_letp, 0000, f01fc001), \
11469 X(_lsl, 0000, fa00f000), \
11470 X(_lsls, 0000, fa10f000), \
11471 X(_lsr, 0800, fa20f000), \
11472 X(_lsrs, 0800, fa30f000), \
11473 X(_mov, 2000, ea4f0000), \
11474 X(_movs, 2000, ea5f0000), \
11475 X(_mul, 4340, fb00f000), \
11476 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11477 X(_mvn, 43c0, ea6f0000), \
11478 X(_mvns, 43c0, ea7f0000), \
11479 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11480 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11481 X(_orr, 4300, ea400000), \
11482 X(_orrs, 4300, ea500000), \
11483 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11484 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11485 X(_rev, ba00, fa90f080), \
11486 X(_rev16, ba40, fa90f090), \
11487 X(_revsh, bac0, fa90f0b0), \
11488 X(_ror, 41c0, fa60f000), \
11489 X(_rors, 41c0, fa70f000), \
11490 X(_sbc, 4180, eb600000), \
11491 X(_sbcs, 4180, eb700000), \
11492 X(_stmia, c000, e8800000), \
11493 X(_str, 6000, f8400000), \
11494 X(_strb, 7000, f8000000), \
11495 X(_strh, 8000, f8200000), \
11496 X(_str_sp,9000, f84d0000), \
11497 X(_sub, 1e00, eba00000), \
11498 X(_subs, 1e00, ebb00000), \
11499 X(_subi, 8000, f1a00000), \
11500 X(_subis, 8000, f1b00000), \
11501 X(_sxtb, b240, fa4ff080), \
11502 X(_sxth, b200, fa0ff080), \
11503 X(_tst, 4200, ea100f00), \
11504 X(_uxtb, b2c0, fa5ff080), \
11505 X(_uxth, b280, fa1ff080), \
11506 X(_nop, bf00, f3af8000), \
11507 X(_yield, bf10, f3af8001), \
11508 X(_wfe, bf20, f3af8002), \
11509 X(_wfi, bf30, f3af8003), \
11510 X(_wls, 0000, f040c001), \
11511 X(_wlstp, 0000, f000c001), \
11512 X(_sev, bf40, f3af8004), \
11513 X(_sevl, bf50, f3af8005), \
11514 X(_udf, de00, f7f0a000)
11516 /* To catch errors in encoding functions, the codes are all offset by
11517 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11518 as 16-bit instructions. */
11519 #define X(a,b,c) T_MNEM##a
11520 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11523 #define X(a,b,c) 0x##b
11524 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11525 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11528 #define X(a,b,c) 0x##c
11529 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11530 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11531 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11535 /* Thumb instruction encoders, in alphabetical order. */
11537 /* ADDW or SUBW. */
11540 do_t_add_sub_w (void)
11544 Rd
= inst
.operands
[0].reg
;
11545 Rn
= inst
.operands
[1].reg
;
11547 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11548 is the SP-{plus,minus}-immediate form of the instruction. */
11550 constraint (Rd
== REG_PC
, BAD_PC
);
11552 reject_bad_reg (Rd
);
11554 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11555 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11558 /* Parse an add or subtract instruction. We get here with inst.instruction
11559 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11562 do_t_add_sub (void)
11566 Rd
= inst
.operands
[0].reg
;
11567 Rs
= (inst
.operands
[1].present
11568 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11569 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11572 set_pred_insn_type_last ();
11574 if (unified_syntax
)
11577 bfd_boolean narrow
;
11580 flags
= (inst
.instruction
== T_MNEM_adds
11581 || inst
.instruction
== T_MNEM_subs
);
11583 narrow
= !in_pred_block ();
11585 narrow
= in_pred_block ();
11586 if (!inst
.operands
[2].isreg
)
11590 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11591 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11593 add
= (inst
.instruction
== T_MNEM_add
11594 || inst
.instruction
== T_MNEM_adds
);
11596 if (inst
.size_req
!= 4)
11598 /* Attempt to use a narrow opcode, with relaxation if
11600 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11601 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11602 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11603 opcode
= T_MNEM_add_sp
;
11604 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11605 opcode
= T_MNEM_add_pc
;
11606 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11609 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11611 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11615 inst
.instruction
= THUMB_OP16(opcode
);
11616 inst
.instruction
|= (Rd
<< 4) | Rs
;
11617 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11618 || (inst
.relocs
[0].type
11619 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11621 if (inst
.size_req
== 2)
11622 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11624 inst
.relax
= opcode
;
11628 constraint (inst
.size_req
== 2, BAD_HIREG
);
11630 if (inst
.size_req
== 4
11631 || (inst
.size_req
!= 2 && !opcode
))
11633 constraint ((inst
.relocs
[0].type
11634 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11635 && (inst
.relocs
[0].type
11636 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11637 THUMB1_RELOC_ONLY
);
11640 constraint (add
, BAD_PC
);
11641 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11642 _("only SUBS PC, LR, #const allowed"));
11643 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11644 _("expression too complex"));
11645 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11646 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11647 _("immediate value out of range"));
11648 inst
.instruction
= T2_SUBS_PC_LR
11649 | inst
.relocs
[0].exp
.X_add_number
;
11650 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11653 else if (Rs
== REG_PC
)
11655 /* Always use addw/subw. */
11656 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11657 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11661 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11662 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11665 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11667 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11669 inst
.instruction
|= Rd
<< 8;
11670 inst
.instruction
|= Rs
<< 16;
11675 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11676 unsigned int shift
= inst
.operands
[2].shift_kind
;
11678 Rn
= inst
.operands
[2].reg
;
11679 /* See if we can do this with a 16-bit instruction. */
11680 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11682 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11687 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11688 || inst
.instruction
== T_MNEM_add
)
11690 : T_OPCODE_SUB_R3
);
11691 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11695 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11697 /* Thumb-1 cores (except v6-M) require at least one high
11698 register in a narrow non flag setting add. */
11699 if (Rd
> 7 || Rn
> 7
11700 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11701 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11708 inst
.instruction
= T_OPCODE_ADD_HI
;
11709 inst
.instruction
|= (Rd
& 8) << 4;
11710 inst
.instruction
|= (Rd
& 7);
11711 inst
.instruction
|= Rn
<< 3;
11717 constraint (Rd
== REG_PC
, BAD_PC
);
11718 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11719 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11720 constraint (Rs
== REG_PC
, BAD_PC
);
11721 reject_bad_reg (Rn
);
11723 /* If we get here, it can't be done in 16 bits. */
11724 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11725 _("shift must be constant"));
11726 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11727 inst
.instruction
|= Rd
<< 8;
11728 inst
.instruction
|= Rs
<< 16;
11729 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11730 _("shift value over 3 not allowed in thumb mode"));
11731 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11732 _("only LSL shift allowed in thumb mode"));
11733 encode_thumb32_shifted_operand (2);
11738 constraint (inst
.instruction
== T_MNEM_adds
11739 || inst
.instruction
== T_MNEM_subs
,
11742 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11744 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11745 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11748 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11749 ? 0x0000 : 0x8000);
11750 inst
.instruction
|= (Rd
<< 4) | Rs
;
11751 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11755 Rn
= inst
.operands
[2].reg
;
11756 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11758 /* We now have Rd, Rs, and Rn set to registers. */
11759 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11761 /* Can't do this for SUB. */
11762 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11763 inst
.instruction
= T_OPCODE_ADD_HI
;
11764 inst
.instruction
|= (Rd
& 8) << 4;
11765 inst
.instruction
|= (Rd
& 7);
11767 inst
.instruction
|= Rn
<< 3;
11769 inst
.instruction
|= Rs
<< 3;
11771 constraint (1, _("dest must overlap one source register"));
11775 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11776 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11777 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11787 Rd
= inst
.operands
[0].reg
;
11788 reject_bad_reg (Rd
);
11790 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11792 /* Defer to section relaxation. */
11793 inst
.relax
= inst
.instruction
;
11794 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11795 inst
.instruction
|= Rd
<< 4;
11797 else if (unified_syntax
&& inst
.size_req
!= 2)
11799 /* Generate a 32-bit opcode. */
11800 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11801 inst
.instruction
|= Rd
<< 8;
11802 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11803 inst
.relocs
[0].pc_rel
= 1;
11807 /* Generate a 16-bit opcode. */
11808 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11809 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11810 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11811 inst
.relocs
[0].pc_rel
= 1;
11812 inst
.instruction
|= Rd
<< 4;
11815 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11816 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11817 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11818 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11819 inst
.relocs
[0].exp
.X_add_number
+= 1;
11822 /* Arithmetic instructions for which there is just one 16-bit
11823 instruction encoding, and it allows only two low registers.
11824 For maximal compatibility with ARM syntax, we allow three register
11825 operands even when Thumb-32 instructions are not available, as long
11826 as the first two are identical. For instance, both "sbc r0,r1" and
11827 "sbc r0,r0,r1" are allowed. */
11833 Rd
= inst
.operands
[0].reg
;
11834 Rs
= (inst
.operands
[1].present
11835 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11836 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11837 Rn
= inst
.operands
[2].reg
;
11839 reject_bad_reg (Rd
);
11840 reject_bad_reg (Rs
);
11841 if (inst
.operands
[2].isreg
)
11842 reject_bad_reg (Rn
);
11844 if (unified_syntax
)
11846 if (!inst
.operands
[2].isreg
)
11848 /* For an immediate, we always generate a 32-bit opcode;
11849 section relaxation will shrink it later if possible. */
11850 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11851 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11852 inst
.instruction
|= Rd
<< 8;
11853 inst
.instruction
|= Rs
<< 16;
11854 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11858 bfd_boolean narrow
;
11860 /* See if we can do this with a 16-bit instruction. */
11861 if (THUMB_SETS_FLAGS (inst
.instruction
))
11862 narrow
= !in_pred_block ();
11864 narrow
= in_pred_block ();
11866 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11868 if (inst
.operands
[2].shifted
)
11870 if (inst
.size_req
== 4)
11876 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11877 inst
.instruction
|= Rd
;
11878 inst
.instruction
|= Rn
<< 3;
11882 /* If we get here, it can't be done in 16 bits. */
11883 constraint (inst
.operands
[2].shifted
11884 && inst
.operands
[2].immisreg
,
11885 _("shift must be constant"));
11886 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11887 inst
.instruction
|= Rd
<< 8;
11888 inst
.instruction
|= Rs
<< 16;
11889 encode_thumb32_shifted_operand (2);
11894 /* On its face this is a lie - the instruction does set the
11895 flags. However, the only supported mnemonic in this mode
11896 says it doesn't. */
11897 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11899 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11900 _("unshifted register required"));
11901 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11902 constraint (Rd
!= Rs
,
11903 _("dest and source1 must be the same register"));
11905 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11906 inst
.instruction
|= Rd
;
11907 inst
.instruction
|= Rn
<< 3;
11911 /* Similarly, but for instructions where the arithmetic operation is
11912 commutative, so we can allow either of them to be different from
11913 the destination operand in a 16-bit instruction. For instance, all
11914 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11921 Rd
= inst
.operands
[0].reg
;
11922 Rs
= (inst
.operands
[1].present
11923 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11924 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11925 Rn
= inst
.operands
[2].reg
;
11927 reject_bad_reg (Rd
);
11928 reject_bad_reg (Rs
);
11929 if (inst
.operands
[2].isreg
)
11930 reject_bad_reg (Rn
);
11932 if (unified_syntax
)
11934 if (!inst
.operands
[2].isreg
)
11936 /* For an immediate, we always generate a 32-bit opcode;
11937 section relaxation will shrink it later if possible. */
11938 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11939 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11940 inst
.instruction
|= Rd
<< 8;
11941 inst
.instruction
|= Rs
<< 16;
11942 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11946 bfd_boolean narrow
;
11948 /* See if we can do this with a 16-bit instruction. */
11949 if (THUMB_SETS_FLAGS (inst
.instruction
))
11950 narrow
= !in_pred_block ();
11952 narrow
= in_pred_block ();
11954 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11956 if (inst
.operands
[2].shifted
)
11958 if (inst
.size_req
== 4)
11965 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11966 inst
.instruction
|= Rd
;
11967 inst
.instruction
|= Rn
<< 3;
11972 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11973 inst
.instruction
|= Rd
;
11974 inst
.instruction
|= Rs
<< 3;
11979 /* If we get here, it can't be done in 16 bits. */
11980 constraint (inst
.operands
[2].shifted
11981 && inst
.operands
[2].immisreg
,
11982 _("shift must be constant"));
11983 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11984 inst
.instruction
|= Rd
<< 8;
11985 inst
.instruction
|= Rs
<< 16;
11986 encode_thumb32_shifted_operand (2);
11991 /* On its face this is a lie - the instruction does set the
11992 flags. However, the only supported mnemonic in this mode
11993 says it doesn't. */
11994 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11996 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11997 _("unshifted register required"));
11998 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
12000 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12001 inst
.instruction
|= Rd
;
12004 inst
.instruction
|= Rn
<< 3;
12006 inst
.instruction
|= Rs
<< 3;
12008 constraint (1, _("dest must overlap one source register"));
12016 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
12017 constraint (msb
> 32, _("bit-field extends past end of register"));
12018 /* The instruction encoding stores the LSB and MSB,
12019 not the LSB and width. */
12020 Rd
= inst
.operands
[0].reg
;
12021 reject_bad_reg (Rd
);
12022 inst
.instruction
|= Rd
<< 8;
12023 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
12024 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
12025 inst
.instruction
|= msb
- 1;
12034 Rd
= inst
.operands
[0].reg
;
12035 reject_bad_reg (Rd
);
12037 /* #0 in second position is alternative syntax for bfc, which is
12038 the same instruction but with REG_PC in the Rm field. */
12039 if (!inst
.operands
[1].isreg
)
12043 Rn
= inst
.operands
[1].reg
;
12044 reject_bad_reg (Rn
);
12047 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
12048 constraint (msb
> 32, _("bit-field extends past end of register"));
12049 /* The instruction encoding stores the LSB and MSB,
12050 not the LSB and width. */
12051 inst
.instruction
|= Rd
<< 8;
12052 inst
.instruction
|= Rn
<< 16;
12053 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12054 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12055 inst
.instruction
|= msb
- 1;
12063 Rd
= inst
.operands
[0].reg
;
12064 Rn
= inst
.operands
[1].reg
;
12066 reject_bad_reg (Rd
);
12067 reject_bad_reg (Rn
);
12069 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
12070 _("bit-field extends past end of register"));
12071 inst
.instruction
|= Rd
<< 8;
12072 inst
.instruction
|= Rn
<< 16;
12073 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
12074 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
12075 inst
.instruction
|= inst
.operands
[3].imm
- 1;
12078 /* ARM V5 Thumb BLX (argument parse)
12079 BLX <target_addr> which is BLX(1)
12080 BLX <Rm> which is BLX(2)
12081 Unfortunately, there are two different opcodes for this mnemonic.
12082 So, the insns[].value is not used, and the code here zaps values
12083 into inst.instruction.
12085 ??? How to take advantage of the additional two bits of displacement
12086 available in Thumb32 mode? Need new relocation? */
12091 set_pred_insn_type_last ();
12093 if (inst
.operands
[0].isreg
)
12095 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
12096 /* We have a register, so this is BLX(2). */
12097 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12101 /* No register. This must be BLX(1). */
12102 inst
.instruction
= 0xf000e800;
12103 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
12112 bfd_reloc_code_real_type reloc
;
12115 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
12117 if (in_pred_block ())
12119 /* Conditional branches inside IT blocks are encoded as unconditional
12121 cond
= COND_ALWAYS
;
12126 if (cond
!= COND_ALWAYS
)
12127 opcode
= T_MNEM_bcond
;
12129 opcode
= inst
.instruction
;
12132 && (inst
.size_req
== 4
12133 || (inst
.size_req
!= 2
12134 && (inst
.operands
[0].hasreloc
12135 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
12137 inst
.instruction
= THUMB_OP32(opcode
);
12138 if (cond
== COND_ALWAYS
)
12139 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
12142 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
12143 _("selected architecture does not support "
12144 "wide conditional branch instruction"));
12146 gas_assert (cond
!= 0xF);
12147 inst
.instruction
|= cond
<< 22;
12148 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12153 inst
.instruction
= THUMB_OP16(opcode
);
12154 if (cond
== COND_ALWAYS
)
12155 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12158 inst
.instruction
|= cond
<< 8;
12159 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12161 /* Allow section relaxation. */
12162 if (unified_syntax
&& inst
.size_req
!= 2)
12163 inst
.relax
= opcode
;
12165 inst
.relocs
[0].type
= reloc
;
12166 inst
.relocs
[0].pc_rel
= 1;
12169 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12170 between the two is the maximum immediate allowed - which is passed in
12173 do_t_bkpt_hlt1 (int range
)
12175 constraint (inst
.cond
!= COND_ALWAYS
,
12176 _("instruction is always unconditional"));
12177 if (inst
.operands
[0].present
)
12179 constraint (inst
.operands
[0].imm
> range
,
12180 _("immediate value out of range"));
12181 inst
.instruction
|= inst
.operands
[0].imm
;
12184 set_pred_insn_type (NEUTRAL_IT_INSN
);
12190 do_t_bkpt_hlt1 (63);
12196 do_t_bkpt_hlt1 (255);
12200 do_t_branch23 (void)
12202 set_pred_insn_type_last ();
12203 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12205 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12206 this file. We used to simply ignore the PLT reloc type here --
12207 the branch encoding is now needed to deal with TLSCALL relocs.
12208 So if we see a PLT reloc now, put it back to how it used to be to
12209 keep the preexisting behaviour. */
12210 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12211 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12213 #if defined(OBJ_COFF)
12214 /* If the destination of the branch is a defined symbol which does not have
12215 the THUMB_FUNC attribute, then we must be calling a function which has
12216 the (interfacearm) attribute. We look for the Thumb entry point to that
12217 function and change the branch to refer to that function instead. */
12218 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12219 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12220 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12221 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12222 inst
.relocs
[0].exp
.X_add_symbol
12223 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12230 set_pred_insn_type_last ();
12231 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12232 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12233 should cause the alignment to be checked once it is known. This is
12234 because BX PC only works if the instruction is word aligned. */
12242 set_pred_insn_type_last ();
12243 Rm
= inst
.operands
[0].reg
;
12244 reject_bad_reg (Rm
);
12245 inst
.instruction
|= Rm
<< 16;
12254 Rd
= inst
.operands
[0].reg
;
12255 Rm
= inst
.operands
[1].reg
;
12257 reject_bad_reg (Rd
);
12258 reject_bad_reg (Rm
);
12260 inst
.instruction
|= Rd
<< 8;
12261 inst
.instruction
|= Rm
<< 16;
12262 inst
.instruction
|= Rm
;
12265 /* For the Armv8.1-M conditional instructions. */
12269 unsigned Rd
, Rn
, Rm
;
12272 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12274 Rd
= inst
.operands
[0].reg
;
12275 switch (inst
.instruction
)
12281 Rn
= inst
.operands
[1].reg
;
12282 Rm
= inst
.operands
[2].reg
;
12283 cond
= inst
.operands
[3].imm
;
12284 constraint (Rn
== REG_SP
, BAD_SP
);
12285 constraint (Rm
== REG_SP
, BAD_SP
);
12291 Rn
= inst
.operands
[1].reg
;
12292 cond
= inst
.operands
[2].imm
;
12293 /* Invert the last bit to invert the cond. */
12294 cond
= TOGGLE_BIT (cond
, 0);
12295 constraint (Rn
== REG_SP
, BAD_SP
);
12301 cond
= inst
.operands
[1].imm
;
12302 /* Invert the last bit to invert the cond. */
12303 cond
= TOGGLE_BIT (cond
, 0);
12311 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12312 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12313 inst
.instruction
|= Rd
<< 8;
12314 inst
.instruction
|= Rn
<< 16;
12315 inst
.instruction
|= Rm
;
12316 inst
.instruction
|= cond
<< 4;
12322 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12328 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12329 inst
.instruction
|= inst
.operands
[0].imm
;
12335 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12337 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12338 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12340 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12341 inst
.instruction
= 0xf3af8000;
12342 inst
.instruction
|= imod
<< 9;
12343 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12344 if (inst
.operands
[1].present
)
12345 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12349 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12350 && (inst
.operands
[0].imm
& 4),
12351 _("selected processor does not support 'A' form "
12352 "of this instruction"));
12353 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12354 _("Thumb does not support the 2-argument "
12355 "form of this instruction"));
12356 inst
.instruction
|= inst
.operands
[0].imm
;
12360 /* THUMB CPY instruction (argument parse). */
12365 if (inst
.size_req
== 4)
12367 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12368 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12369 inst
.instruction
|= inst
.operands
[1].reg
;
12373 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12374 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12375 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12382 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12383 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12384 inst
.instruction
|= inst
.operands
[0].reg
;
12385 inst
.relocs
[0].pc_rel
= 1;
12386 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12392 inst
.instruction
|= inst
.operands
[0].imm
;
12398 unsigned Rd
, Rn
, Rm
;
12400 Rd
= inst
.operands
[0].reg
;
12401 Rn
= (inst
.operands
[1].present
12402 ? inst
.operands
[1].reg
: Rd
);
12403 Rm
= inst
.operands
[2].reg
;
12405 reject_bad_reg (Rd
);
12406 reject_bad_reg (Rn
);
12407 reject_bad_reg (Rm
);
12409 inst
.instruction
|= Rd
<< 8;
12410 inst
.instruction
|= Rn
<< 16;
12411 inst
.instruction
|= Rm
;
12417 if (unified_syntax
&& inst
.size_req
== 4)
12418 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12420 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12426 unsigned int cond
= inst
.operands
[0].imm
;
12428 set_pred_insn_type (IT_INSN
);
12429 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12430 now_pred
.cc
= cond
;
12431 now_pred
.warn_deprecated
= FALSE
;
12432 now_pred
.type
= SCALAR_PRED
;
12434 /* If the condition is a negative condition, invert the mask. */
12435 if ((cond
& 0x1) == 0x0)
12437 unsigned int mask
= inst
.instruction
& 0x000f;
12439 if ((mask
& 0x7) == 0)
12441 /* No conversion needed. */
12442 now_pred
.block_length
= 1;
12444 else if ((mask
& 0x3) == 0)
12447 now_pred
.block_length
= 2;
12449 else if ((mask
& 0x1) == 0)
12452 now_pred
.block_length
= 3;
12457 now_pred
.block_length
= 4;
12460 inst
.instruction
&= 0xfff0;
12461 inst
.instruction
|= mask
;
12464 inst
.instruction
|= cond
<< 4;
12467 /* Helper function used for both push/pop and ldm/stm. */
12469 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12470 bfd_boolean writeback
)
12472 bfd_boolean load
, store
;
12474 gas_assert (base
!= -1 || !do_io
);
12475 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12476 store
= do_io
&& !load
;
12478 if (mask
& (1 << 13))
12479 inst
.error
= _("SP not allowed in register list");
12481 if (do_io
&& (mask
& (1 << base
)) != 0
12483 inst
.error
= _("having the base register in the register list when "
12484 "using write back is UNPREDICTABLE");
12488 if (mask
& (1 << 15))
12490 if (mask
& (1 << 14))
12491 inst
.error
= _("LR and PC should not both be in register list");
12493 set_pred_insn_type_last ();
12498 if (mask
& (1 << 15))
12499 inst
.error
= _("PC not allowed in register list");
12502 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12504 /* Single register transfers implemented as str/ldr. */
12507 if (inst
.instruction
& (1 << 23))
12508 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12510 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12514 if (inst
.instruction
& (1 << 23))
12515 inst
.instruction
= 0x00800000; /* ia -> [base] */
12517 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12520 inst
.instruction
|= 0xf8400000;
12522 inst
.instruction
|= 0x00100000;
12524 mask
= ffs (mask
) - 1;
12527 else if (writeback
)
12528 inst
.instruction
|= WRITE_BACK
;
12530 inst
.instruction
|= mask
;
12532 inst
.instruction
|= base
<< 16;
12538 /* This really doesn't seem worth it. */
12539 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12540 _("expression too complex"));
12541 constraint (inst
.operands
[1].writeback
,
12542 _("Thumb load/store multiple does not support {reglist}^"));
12544 if (unified_syntax
)
12546 bfd_boolean narrow
;
12550 /* See if we can use a 16-bit instruction. */
12551 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12552 && inst
.size_req
!= 4
12553 && !(inst
.operands
[1].imm
& ~0xff))
12555 mask
= 1 << inst
.operands
[0].reg
;
12557 if (inst
.operands
[0].reg
<= 7)
12559 if (inst
.instruction
== T_MNEM_stmia
12560 ? inst
.operands
[0].writeback
12561 : (inst
.operands
[0].writeback
12562 == !(inst
.operands
[1].imm
& mask
)))
12564 if (inst
.instruction
== T_MNEM_stmia
12565 && (inst
.operands
[1].imm
& mask
)
12566 && (inst
.operands
[1].imm
& (mask
- 1)))
12567 as_warn (_("value stored for r%d is UNKNOWN"),
12568 inst
.operands
[0].reg
);
12570 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12571 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12572 inst
.instruction
|= inst
.operands
[1].imm
;
12575 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12577 /* This means 1 register in reg list one of 3 situations:
12578 1. Instruction is stmia, but without writeback.
12579 2. lmdia without writeback, but with Rn not in
12581 3. ldmia with writeback, but with Rn in reglist.
12582 Case 3 is UNPREDICTABLE behaviour, so we handle
12583 case 1 and 2 which can be converted into a 16-bit
12584 str or ldr. The SP cases are handled below. */
12585 unsigned long opcode
;
12586 /* First, record an error for Case 3. */
12587 if (inst
.operands
[1].imm
& mask
12588 && inst
.operands
[0].writeback
)
12590 _("having the base register in the register list when "
12591 "using write back is UNPREDICTABLE");
12593 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12595 inst
.instruction
= THUMB_OP16 (opcode
);
12596 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12597 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12601 else if (inst
.operands
[0] .reg
== REG_SP
)
12603 if (inst
.operands
[0].writeback
)
12606 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12607 ? T_MNEM_push
: T_MNEM_pop
);
12608 inst
.instruction
|= inst
.operands
[1].imm
;
12611 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12614 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12615 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12616 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12624 if (inst
.instruction
< 0xffff)
12625 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12627 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12628 inst
.operands
[1].imm
,
12629 inst
.operands
[0].writeback
);
12634 constraint (inst
.operands
[0].reg
> 7
12635 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12636 constraint (inst
.instruction
!= T_MNEM_ldmia
12637 && inst
.instruction
!= T_MNEM_stmia
,
12638 _("Thumb-2 instruction only valid in unified syntax"));
12639 if (inst
.instruction
== T_MNEM_stmia
)
12641 if (!inst
.operands
[0].writeback
)
12642 as_warn (_("this instruction will write back the base register"));
12643 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12644 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12645 as_warn (_("value stored for r%d is UNKNOWN"),
12646 inst
.operands
[0].reg
);
12650 if (!inst
.operands
[0].writeback
12651 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12652 as_warn (_("this instruction will write back the base register"));
12653 else if (inst
.operands
[0].writeback
12654 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12655 as_warn (_("this instruction will not write back the base register"));
12658 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12659 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12660 inst
.instruction
|= inst
.operands
[1].imm
;
12667 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12668 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12669 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12670 || inst
.operands
[1].negative
,
12673 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12676 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12677 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12683 if (!inst
.operands
[1].present
)
12685 constraint (inst
.operands
[0].reg
== REG_LR
,
12686 _("r14 not allowed as first register "
12687 "when second register is omitted"));
12688 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12690 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12693 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12694 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12695 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12701 unsigned long opcode
;
12704 if (inst
.operands
[0].isreg
12705 && !inst
.operands
[0].preind
12706 && inst
.operands
[0].reg
== REG_PC
)
12707 set_pred_insn_type_last ();
12709 opcode
= inst
.instruction
;
12710 if (unified_syntax
)
12712 if (!inst
.operands
[1].isreg
)
12714 if (opcode
<= 0xffff)
12715 inst
.instruction
= THUMB_OP32 (opcode
);
12716 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12719 if (inst
.operands
[1].isreg
12720 && !inst
.operands
[1].writeback
12721 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12722 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12723 && opcode
<= 0xffff
12724 && inst
.size_req
!= 4)
12726 /* Insn may have a 16-bit form. */
12727 Rn
= inst
.operands
[1].reg
;
12728 if (inst
.operands
[1].immisreg
)
12730 inst
.instruction
= THUMB_OP16 (opcode
);
12732 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12734 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12735 reject_bad_reg (inst
.operands
[1].imm
);
12737 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12738 && opcode
!= T_MNEM_ldrsb
)
12739 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12740 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12747 if (inst
.relocs
[0].pc_rel
)
12748 opcode
= T_MNEM_ldr_pc2
;
12750 opcode
= T_MNEM_ldr_pc
;
12754 if (opcode
== T_MNEM_ldr
)
12755 opcode
= T_MNEM_ldr_sp
;
12757 opcode
= T_MNEM_str_sp
;
12759 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12763 inst
.instruction
= inst
.operands
[0].reg
;
12764 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12766 inst
.instruction
|= THUMB_OP16 (opcode
);
12767 if (inst
.size_req
== 2)
12768 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12770 inst
.relax
= opcode
;
12774 /* Definitely a 32-bit variant. */
12776 /* Warning for Erratum 752419. */
12777 if (opcode
== T_MNEM_ldr
12778 && inst
.operands
[0].reg
== REG_SP
12779 && inst
.operands
[1].writeback
== 1
12780 && !inst
.operands
[1].immisreg
)
12782 if (no_cpu_selected ()
12783 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12784 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12785 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12786 as_warn (_("This instruction may be unpredictable "
12787 "if executed on M-profile cores "
12788 "with interrupts enabled."));
12791 /* Do some validations regarding addressing modes. */
12792 if (inst
.operands
[1].immisreg
)
12793 reject_bad_reg (inst
.operands
[1].imm
);
12795 constraint (inst
.operands
[1].writeback
== 1
12796 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12799 inst
.instruction
= THUMB_OP32 (opcode
);
12800 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12801 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12802 check_ldr_r15_aligned ();
12806 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12808 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12810 /* Only [Rn,Rm] is acceptable. */
12811 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12812 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12813 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12814 || inst
.operands
[1].negative
,
12815 _("Thumb does not support this addressing mode"));
12816 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12820 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12821 if (!inst
.operands
[1].isreg
)
12822 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12825 constraint (!inst
.operands
[1].preind
12826 || inst
.operands
[1].shifted
12827 || inst
.operands
[1].writeback
,
12828 _("Thumb does not support this addressing mode"));
12829 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12831 constraint (inst
.instruction
& 0x0600,
12832 _("byte or halfword not valid for base register"));
12833 constraint (inst
.operands
[1].reg
== REG_PC
12834 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12835 _("r15 based store not allowed"));
12836 constraint (inst
.operands
[1].immisreg
,
12837 _("invalid base register for register offset"));
12839 if (inst
.operands
[1].reg
== REG_PC
)
12840 inst
.instruction
= T_OPCODE_LDR_PC
;
12841 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12842 inst
.instruction
= T_OPCODE_LDR_SP
;
12844 inst
.instruction
= T_OPCODE_STR_SP
;
12846 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12847 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12851 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12852 if (!inst
.operands
[1].immisreg
)
12854 /* Immediate offset. */
12855 inst
.instruction
|= inst
.operands
[0].reg
;
12856 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12857 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12861 /* Register offset. */
12862 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12863 constraint (inst
.operands
[1].negative
,
12864 _("Thumb does not support this addressing mode"));
12867 switch (inst
.instruction
)
12869 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12870 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12871 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12872 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12873 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12874 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12875 case 0x5600 /* ldrsb */:
12876 case 0x5e00 /* ldrsh */: break;
12880 inst
.instruction
|= inst
.operands
[0].reg
;
12881 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12882 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12888 if (!inst
.operands
[1].present
)
12890 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12891 constraint (inst
.operands
[0].reg
== REG_LR
,
12892 _("r14 not allowed here"));
12893 constraint (inst
.operands
[0].reg
== REG_R12
,
12894 _("r12 not allowed here"));
12897 if (inst
.operands
[2].writeback
12898 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12899 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12900 as_warn (_("base register written back, and overlaps "
12901 "one of transfer registers"));
12903 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12904 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12905 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12911 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12912 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12918 unsigned Rd
, Rn
, Rm
, Ra
;
12920 Rd
= inst
.operands
[0].reg
;
12921 Rn
= inst
.operands
[1].reg
;
12922 Rm
= inst
.operands
[2].reg
;
12923 Ra
= inst
.operands
[3].reg
;
12925 reject_bad_reg (Rd
);
12926 reject_bad_reg (Rn
);
12927 reject_bad_reg (Rm
);
12928 reject_bad_reg (Ra
);
12930 inst
.instruction
|= Rd
<< 8;
12931 inst
.instruction
|= Rn
<< 16;
12932 inst
.instruction
|= Rm
;
12933 inst
.instruction
|= Ra
<< 12;
12939 unsigned RdLo
, RdHi
, Rn
, Rm
;
12941 RdLo
= inst
.operands
[0].reg
;
12942 RdHi
= inst
.operands
[1].reg
;
12943 Rn
= inst
.operands
[2].reg
;
12944 Rm
= inst
.operands
[3].reg
;
12946 reject_bad_reg (RdLo
);
12947 reject_bad_reg (RdHi
);
12948 reject_bad_reg (Rn
);
12949 reject_bad_reg (Rm
);
12951 inst
.instruction
|= RdLo
<< 12;
12952 inst
.instruction
|= RdHi
<< 8;
12953 inst
.instruction
|= Rn
<< 16;
12954 inst
.instruction
|= Rm
;
12958 do_t_mov_cmp (void)
12962 Rn
= inst
.operands
[0].reg
;
12963 Rm
= inst
.operands
[1].reg
;
12966 set_pred_insn_type_last ();
12968 if (unified_syntax
)
12970 int r0off
= (inst
.instruction
== T_MNEM_mov
12971 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12972 unsigned long opcode
;
12973 bfd_boolean narrow
;
12974 bfd_boolean low_regs
;
12976 low_regs
= (Rn
<= 7 && Rm
<= 7);
12977 opcode
= inst
.instruction
;
12978 if (in_pred_block ())
12979 narrow
= opcode
!= T_MNEM_movs
;
12981 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12982 if (inst
.size_req
== 4
12983 || inst
.operands
[1].shifted
)
12986 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12987 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12988 && !inst
.operands
[1].shifted
12992 inst
.instruction
= T2_SUBS_PC_LR
;
12996 if (opcode
== T_MNEM_cmp
)
12998 constraint (Rn
== REG_PC
, BAD_PC
);
13001 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
13003 warn_deprecated_sp (Rm
);
13004 /* R15 was documented as a valid choice for Rm in ARMv6,
13005 but as UNPREDICTABLE in ARMv7. ARM's proprietary
13006 tools reject R15, so we do too. */
13007 constraint (Rm
== REG_PC
, BAD_PC
);
13010 reject_bad_reg (Rm
);
13012 else if (opcode
== T_MNEM_mov
13013 || opcode
== T_MNEM_movs
)
13015 if (inst
.operands
[1].isreg
)
13017 if (opcode
== T_MNEM_movs
)
13019 reject_bad_reg (Rn
);
13020 reject_bad_reg (Rm
);
13024 /* This is mov.n. */
13025 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
13026 && (Rm
== REG_SP
|| Rm
== REG_PC
))
13028 as_tsktsk (_("Use of r%u as a source register is "
13029 "deprecated when r%u is the destination "
13030 "register."), Rm
, Rn
);
13035 /* This is mov.w. */
13036 constraint (Rn
== REG_PC
, BAD_PC
);
13037 constraint (Rm
== REG_PC
, BAD_PC
);
13038 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13039 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
13043 reject_bad_reg (Rn
);
13046 if (!inst
.operands
[1].isreg
)
13048 /* Immediate operand. */
13049 if (!in_pred_block () && opcode
== T_MNEM_mov
)
13051 if (low_regs
&& narrow
)
13053 inst
.instruction
= THUMB_OP16 (opcode
);
13054 inst
.instruction
|= Rn
<< 8;
13055 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
13056 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
13058 if (inst
.size_req
== 2)
13059 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13061 inst
.relax
= opcode
;
13066 constraint ((inst
.relocs
[0].type
13067 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
13068 && (inst
.relocs
[0].type
13069 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
13070 THUMB1_RELOC_ONLY
);
13072 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13073 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13074 inst
.instruction
|= Rn
<< r0off
;
13075 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13078 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
13079 && (inst
.instruction
== T_MNEM_mov
13080 || inst
.instruction
== T_MNEM_movs
))
13082 /* Register shifts are encoded as separate shift instructions. */
13083 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
13085 if (in_pred_block ())
13090 if (inst
.size_req
== 4)
13093 if (!low_regs
|| inst
.operands
[1].imm
> 7)
13099 switch (inst
.operands
[1].shift_kind
)
13102 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
13105 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
13108 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
13111 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
13117 inst
.instruction
= opcode
;
13120 inst
.instruction
|= Rn
;
13121 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
13126 inst
.instruction
|= CONDS_BIT
;
13128 inst
.instruction
|= Rn
<< 8;
13129 inst
.instruction
|= Rm
<< 16;
13130 inst
.instruction
|= inst
.operands
[1].imm
;
13135 /* Some mov with immediate shift have narrow variants.
13136 Register shifts are handled above. */
13137 if (low_regs
&& inst
.operands
[1].shifted
13138 && (inst
.instruction
== T_MNEM_mov
13139 || inst
.instruction
== T_MNEM_movs
))
13141 if (in_pred_block ())
13142 narrow
= (inst
.instruction
== T_MNEM_mov
);
13144 narrow
= (inst
.instruction
== T_MNEM_movs
);
13149 switch (inst
.operands
[1].shift_kind
)
13151 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13152 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13153 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13154 default: narrow
= FALSE
; break;
13160 inst
.instruction
|= Rn
;
13161 inst
.instruction
|= Rm
<< 3;
13162 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13166 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13167 inst
.instruction
|= Rn
<< r0off
;
13168 encode_thumb32_shifted_operand (1);
13172 switch (inst
.instruction
)
13175 /* In v4t or v5t a move of two lowregs produces unpredictable
13176 results. Don't allow this. */
13179 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13180 "MOV Rd, Rs with two low registers is not "
13181 "permitted on this architecture");
13182 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13186 inst
.instruction
= T_OPCODE_MOV_HR
;
13187 inst
.instruction
|= (Rn
& 0x8) << 4;
13188 inst
.instruction
|= (Rn
& 0x7);
13189 inst
.instruction
|= Rm
<< 3;
13193 /* We know we have low registers at this point.
13194 Generate LSLS Rd, Rs, #0. */
13195 inst
.instruction
= T_OPCODE_LSL_I
;
13196 inst
.instruction
|= Rn
;
13197 inst
.instruction
|= Rm
<< 3;
13203 inst
.instruction
= T_OPCODE_CMP_LR
;
13204 inst
.instruction
|= Rn
;
13205 inst
.instruction
|= Rm
<< 3;
13209 inst
.instruction
= T_OPCODE_CMP_HR
;
13210 inst
.instruction
|= (Rn
& 0x8) << 4;
13211 inst
.instruction
|= (Rn
& 0x7);
13212 inst
.instruction
|= Rm
<< 3;
13219 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13221 /* PR 10443: Do not silently ignore shifted operands. */
13222 constraint (inst
.operands
[1].shifted
,
13223 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13225 if (inst
.operands
[1].isreg
)
13227 if (Rn
< 8 && Rm
< 8)
13229 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13230 since a MOV instruction produces unpredictable results. */
13231 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13232 inst
.instruction
= T_OPCODE_ADD_I3
;
13234 inst
.instruction
= T_OPCODE_CMP_LR
;
13236 inst
.instruction
|= Rn
;
13237 inst
.instruction
|= Rm
<< 3;
13241 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13242 inst
.instruction
= T_OPCODE_MOV_HR
;
13244 inst
.instruction
= T_OPCODE_CMP_HR
;
13250 constraint (Rn
> 7,
13251 _("only lo regs allowed with immediate"));
13252 inst
.instruction
|= Rn
<< 8;
13253 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13264 top
= (inst
.instruction
& 0x00800000) != 0;
13265 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13267 constraint (top
, _(":lower16: not allowed in this instruction"));
13268 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13270 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13272 constraint (!top
, _(":upper16: not allowed in this instruction"));
13273 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13276 Rd
= inst
.operands
[0].reg
;
13277 reject_bad_reg (Rd
);
13279 inst
.instruction
|= Rd
<< 8;
13280 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13282 imm
= inst
.relocs
[0].exp
.X_add_number
;
13283 inst
.instruction
|= (imm
& 0xf000) << 4;
13284 inst
.instruction
|= (imm
& 0x0800) << 15;
13285 inst
.instruction
|= (imm
& 0x0700) << 4;
13286 inst
.instruction
|= (imm
& 0x00ff);
13291 do_t_mvn_tst (void)
13295 Rn
= inst
.operands
[0].reg
;
13296 Rm
= inst
.operands
[1].reg
;
13298 if (inst
.instruction
== T_MNEM_cmp
13299 || inst
.instruction
== T_MNEM_cmn
)
13300 constraint (Rn
== REG_PC
, BAD_PC
);
13302 reject_bad_reg (Rn
);
13303 reject_bad_reg (Rm
);
13305 if (unified_syntax
)
13307 int r0off
= (inst
.instruction
== T_MNEM_mvn
13308 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13309 bfd_boolean narrow
;
13311 if (inst
.size_req
== 4
13312 || inst
.instruction
> 0xffff
13313 || inst
.operands
[1].shifted
13314 || Rn
> 7 || Rm
> 7)
13316 else if (inst
.instruction
== T_MNEM_cmn
13317 || inst
.instruction
== T_MNEM_tst
)
13319 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13320 narrow
= !in_pred_block ();
13322 narrow
= in_pred_block ();
13324 if (!inst
.operands
[1].isreg
)
13326 /* For an immediate, we always generate a 32-bit opcode;
13327 section relaxation will shrink it later if possible. */
13328 if (inst
.instruction
< 0xffff)
13329 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13330 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13331 inst
.instruction
|= Rn
<< r0off
;
13332 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13336 /* See if we can do this with a 16-bit instruction. */
13339 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13340 inst
.instruction
|= Rn
;
13341 inst
.instruction
|= Rm
<< 3;
13345 constraint (inst
.operands
[1].shifted
13346 && inst
.operands
[1].immisreg
,
13347 _("shift must be constant"));
13348 if (inst
.instruction
< 0xffff)
13349 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13350 inst
.instruction
|= Rn
<< r0off
;
13351 encode_thumb32_shifted_operand (1);
13357 constraint (inst
.instruction
> 0xffff
13358 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13359 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13360 _("unshifted register required"));
13361 constraint (Rn
> 7 || Rm
> 7,
13364 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13365 inst
.instruction
|= Rn
;
13366 inst
.instruction
|= Rm
<< 3;
13375 if (do_vfp_nsyn_mrs () == SUCCESS
)
13378 Rd
= inst
.operands
[0].reg
;
13379 reject_bad_reg (Rd
);
13380 inst
.instruction
|= Rd
<< 8;
13382 if (inst
.operands
[1].isreg
)
13384 unsigned br
= inst
.operands
[1].reg
;
13385 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13386 as_bad (_("bad register for mrs"));
13388 inst
.instruction
|= br
& (0xf << 16);
13389 inst
.instruction
|= (br
& 0x300) >> 4;
13390 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13394 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13396 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13398 /* PR gas/12698: The constraint is only applied for m_profile.
13399 If the user has specified -march=all, we want to ignore it as
13400 we are building for any CPU type, including non-m variants. */
13401 bfd_boolean m_profile
=
13402 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13403 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13404 "not support requested special purpose register"));
13407 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13409 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13410 _("'APSR', 'CPSR' or 'SPSR' expected"));
13412 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13413 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13414 inst
.instruction
|= 0xf0000;
13424 if (do_vfp_nsyn_msr () == SUCCESS
)
13427 constraint (!inst
.operands
[1].isreg
,
13428 _("Thumb encoding does not support an immediate here"));
13430 if (inst
.operands
[0].isreg
)
13431 flags
= (int)(inst
.operands
[0].reg
);
13433 flags
= inst
.operands
[0].imm
;
13435 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13437 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13439 /* PR gas/12698: The constraint is only applied for m_profile.
13440 If the user has specified -march=all, we want to ignore it as
13441 we are building for any CPU type, including non-m variants. */
13442 bfd_boolean m_profile
=
13443 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13444 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13445 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13446 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13447 && bits
!= PSR_f
)) && m_profile
,
13448 _("selected processor does not support requested special "
13449 "purpose register"));
13452 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13453 "requested special purpose register"));
13455 Rn
= inst
.operands
[1].reg
;
13456 reject_bad_reg (Rn
);
13458 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13459 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13460 inst
.instruction
|= (flags
& 0x300) >> 4;
13461 inst
.instruction
|= (flags
& 0xff);
13462 inst
.instruction
|= Rn
<< 16;
13468 bfd_boolean narrow
;
13469 unsigned Rd
, Rn
, Rm
;
13471 if (!inst
.operands
[2].present
)
13472 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13474 Rd
= inst
.operands
[0].reg
;
13475 Rn
= inst
.operands
[1].reg
;
13476 Rm
= inst
.operands
[2].reg
;
13478 if (unified_syntax
)
13480 if (inst
.size_req
== 4
13486 else if (inst
.instruction
== T_MNEM_muls
)
13487 narrow
= !in_pred_block ();
13489 narrow
= in_pred_block ();
13493 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13494 constraint (Rn
> 7 || Rm
> 7,
13501 /* 16-bit MULS/Conditional MUL. */
13502 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13503 inst
.instruction
|= Rd
;
13506 inst
.instruction
|= Rm
<< 3;
13508 inst
.instruction
|= Rn
<< 3;
13510 constraint (1, _("dest must overlap one source register"));
13514 constraint (inst
.instruction
!= T_MNEM_mul
,
13515 _("Thumb-2 MUL must not set flags"));
13517 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13518 inst
.instruction
|= Rd
<< 8;
13519 inst
.instruction
|= Rn
<< 16;
13520 inst
.instruction
|= Rm
<< 0;
13522 reject_bad_reg (Rd
);
13523 reject_bad_reg (Rn
);
13524 reject_bad_reg (Rm
);
13531 unsigned RdLo
, RdHi
, Rn
, Rm
;
13533 RdLo
= inst
.operands
[0].reg
;
13534 RdHi
= inst
.operands
[1].reg
;
13535 Rn
= inst
.operands
[2].reg
;
13536 Rm
= inst
.operands
[3].reg
;
13538 reject_bad_reg (RdLo
);
13539 reject_bad_reg (RdHi
);
13540 reject_bad_reg (Rn
);
13541 reject_bad_reg (Rm
);
13543 inst
.instruction
|= RdLo
<< 12;
13544 inst
.instruction
|= RdHi
<< 8;
13545 inst
.instruction
|= Rn
<< 16;
13546 inst
.instruction
|= Rm
;
13549 as_tsktsk (_("rdhi and rdlo must be different"));
13555 set_pred_insn_type (NEUTRAL_IT_INSN
);
13557 if (unified_syntax
)
13559 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13561 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13562 inst
.instruction
|= inst
.operands
[0].imm
;
13566 /* PR9722: Check for Thumb2 availability before
13567 generating a thumb2 nop instruction. */
13568 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13570 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13571 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13574 inst
.instruction
= 0x46c0;
13579 constraint (inst
.operands
[0].present
,
13580 _("Thumb does not support NOP with hints"));
13581 inst
.instruction
= 0x46c0;
13588 if (unified_syntax
)
13590 bfd_boolean narrow
;
13592 if (THUMB_SETS_FLAGS (inst
.instruction
))
13593 narrow
= !in_pred_block ();
13595 narrow
= in_pred_block ();
13596 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13598 if (inst
.size_req
== 4)
13603 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13604 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13605 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13609 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13610 inst
.instruction
|= inst
.operands
[0].reg
;
13611 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13616 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13618 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13620 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13621 inst
.instruction
|= inst
.operands
[0].reg
;
13622 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13631 Rd
= inst
.operands
[0].reg
;
13632 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13634 reject_bad_reg (Rd
);
13635 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13636 reject_bad_reg (Rn
);
13638 inst
.instruction
|= Rd
<< 8;
13639 inst
.instruction
|= Rn
<< 16;
13641 if (!inst
.operands
[2].isreg
)
13643 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13644 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13650 Rm
= inst
.operands
[2].reg
;
13651 reject_bad_reg (Rm
);
13653 constraint (inst
.operands
[2].shifted
13654 && inst
.operands
[2].immisreg
,
13655 _("shift must be constant"));
13656 encode_thumb32_shifted_operand (2);
13663 unsigned Rd
, Rn
, Rm
;
13665 Rd
= inst
.operands
[0].reg
;
13666 Rn
= inst
.operands
[1].reg
;
13667 Rm
= inst
.operands
[2].reg
;
13669 reject_bad_reg (Rd
);
13670 reject_bad_reg (Rn
);
13671 reject_bad_reg (Rm
);
13673 inst
.instruction
|= Rd
<< 8;
13674 inst
.instruction
|= Rn
<< 16;
13675 inst
.instruction
|= Rm
;
13676 if (inst
.operands
[3].present
)
13678 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13679 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13680 _("expression too complex"));
13681 inst
.instruction
|= (val
& 0x1c) << 10;
13682 inst
.instruction
|= (val
& 0x03) << 6;
13689 if (!inst
.operands
[3].present
)
13693 inst
.instruction
&= ~0x00000020;
13695 /* PR 10168. Swap the Rm and Rn registers. */
13696 Rtmp
= inst
.operands
[1].reg
;
13697 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13698 inst
.operands
[2].reg
= Rtmp
;
13706 if (inst
.operands
[0].immisreg
)
13707 reject_bad_reg (inst
.operands
[0].imm
);
13709 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13713 do_t_push_pop (void)
13717 constraint (inst
.operands
[0].writeback
,
13718 _("push/pop do not support {reglist}^"));
13719 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13720 _("expression too complex"));
13722 mask
= inst
.operands
[0].imm
;
13723 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13724 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13725 else if (inst
.size_req
!= 4
13726 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13727 ? REG_LR
: REG_PC
)))
13729 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13730 inst
.instruction
|= THUMB_PP_PC_LR
;
13731 inst
.instruction
|= mask
& 0xff;
13733 else if (unified_syntax
)
13735 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13736 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13740 inst
.error
= _("invalid register list to push/pop instruction");
13748 if (unified_syntax
)
13749 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13752 inst
.error
= _("invalid register list to push/pop instruction");
13758 do_t_vscclrm (void)
13760 if (inst
.operands
[0].issingle
)
13762 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13763 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13764 inst
.instruction
|= inst
.operands
[0].imm
;
13768 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13769 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13770 inst
.instruction
|= 1 << 8;
13771 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13780 Rd
= inst
.operands
[0].reg
;
13781 Rm
= inst
.operands
[1].reg
;
13783 reject_bad_reg (Rd
);
13784 reject_bad_reg (Rm
);
13786 inst
.instruction
|= Rd
<< 8;
13787 inst
.instruction
|= Rm
<< 16;
13788 inst
.instruction
|= Rm
;
13796 Rd
= inst
.operands
[0].reg
;
13797 Rm
= inst
.operands
[1].reg
;
13799 reject_bad_reg (Rd
);
13800 reject_bad_reg (Rm
);
13802 if (Rd
<= 7 && Rm
<= 7
13803 && inst
.size_req
!= 4)
13805 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13806 inst
.instruction
|= Rd
;
13807 inst
.instruction
|= Rm
<< 3;
13809 else if (unified_syntax
)
13811 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13812 inst
.instruction
|= Rd
<< 8;
13813 inst
.instruction
|= Rm
<< 16;
13814 inst
.instruction
|= Rm
;
13817 inst
.error
= BAD_HIREG
;
13825 Rd
= inst
.operands
[0].reg
;
13826 Rm
= inst
.operands
[1].reg
;
13828 reject_bad_reg (Rd
);
13829 reject_bad_reg (Rm
);
13831 inst
.instruction
|= Rd
<< 8;
13832 inst
.instruction
|= Rm
;
13840 Rd
= inst
.operands
[0].reg
;
13841 Rs
= (inst
.operands
[1].present
13842 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13843 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13845 reject_bad_reg (Rd
);
13846 reject_bad_reg (Rs
);
13847 if (inst
.operands
[2].isreg
)
13848 reject_bad_reg (inst
.operands
[2].reg
);
13850 inst
.instruction
|= Rd
<< 8;
13851 inst
.instruction
|= Rs
<< 16;
13852 if (!inst
.operands
[2].isreg
)
13854 bfd_boolean narrow
;
13856 if ((inst
.instruction
& 0x00100000) != 0)
13857 narrow
= !in_pred_block ();
13859 narrow
= in_pred_block ();
13861 if (Rd
> 7 || Rs
> 7)
13864 if (inst
.size_req
== 4 || !unified_syntax
)
13867 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13868 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13871 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13872 relaxation, but it doesn't seem worth the hassle. */
13875 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13876 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13877 inst
.instruction
|= Rs
<< 3;
13878 inst
.instruction
|= Rd
;
13882 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13883 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13887 encode_thumb32_shifted_operand (2);
13893 if (warn_on_deprecated
13894 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13895 as_tsktsk (_("setend use is deprecated for ARMv8"));
13897 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13898 if (inst
.operands
[0].imm
)
13899 inst
.instruction
|= 0x8;
13905 if (!inst
.operands
[1].present
)
13906 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13908 if (unified_syntax
)
13910 bfd_boolean narrow
;
13913 switch (inst
.instruction
)
13916 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13918 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13920 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13922 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13926 if (THUMB_SETS_FLAGS (inst
.instruction
))
13927 narrow
= !in_pred_block ();
13929 narrow
= in_pred_block ();
13930 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13932 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13934 if (inst
.operands
[2].isreg
13935 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13936 || inst
.operands
[2].reg
> 7))
13938 if (inst
.size_req
== 4)
13941 reject_bad_reg (inst
.operands
[0].reg
);
13942 reject_bad_reg (inst
.operands
[1].reg
);
13946 if (inst
.operands
[2].isreg
)
13948 reject_bad_reg (inst
.operands
[2].reg
);
13949 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13950 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13951 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13952 inst
.instruction
|= inst
.operands
[2].reg
;
13954 /* PR 12854: Error on extraneous shifts. */
13955 constraint (inst
.operands
[2].shifted
,
13956 _("extraneous shift as part of operand to shift insn"));
13960 inst
.operands
[1].shifted
= 1;
13961 inst
.operands
[1].shift_kind
= shift_kind
;
13962 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13963 ? T_MNEM_movs
: T_MNEM_mov
);
13964 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13965 encode_thumb32_shifted_operand (1);
13966 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13967 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13972 if (inst
.operands
[2].isreg
)
13974 switch (shift_kind
)
13976 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13977 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13978 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13979 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13983 inst
.instruction
|= inst
.operands
[0].reg
;
13984 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13986 /* PR 12854: Error on extraneous shifts. */
13987 constraint (inst
.operands
[2].shifted
,
13988 _("extraneous shift as part of operand to shift insn"));
13992 switch (shift_kind
)
13994 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13995 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13996 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13999 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14000 inst
.instruction
|= inst
.operands
[0].reg
;
14001 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14007 constraint (inst
.operands
[0].reg
> 7
14008 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
14009 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
14011 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
14013 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
14014 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14015 _("source1 and dest must be same register"));
14017 switch (inst
.instruction
)
14019 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
14020 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
14021 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
14022 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
14026 inst
.instruction
|= inst
.operands
[0].reg
;
14027 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
14029 /* PR 12854: Error on extraneous shifts. */
14030 constraint (inst
.operands
[2].shifted
,
14031 _("extraneous shift as part of operand to shift insn"));
14035 switch (inst
.instruction
)
14037 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
14038 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
14039 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
14040 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
14043 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
14044 inst
.instruction
|= inst
.operands
[0].reg
;
14045 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
14053 unsigned Rd
, Rn
, Rm
;
14055 Rd
= inst
.operands
[0].reg
;
14056 Rn
= inst
.operands
[1].reg
;
14057 Rm
= inst
.operands
[2].reg
;
14059 reject_bad_reg (Rd
);
14060 reject_bad_reg (Rn
);
14061 reject_bad_reg (Rm
);
14063 inst
.instruction
|= Rd
<< 8;
14064 inst
.instruction
|= Rn
<< 16;
14065 inst
.instruction
|= Rm
;
14071 unsigned Rd
, Rn
, Rm
;
14073 Rd
= inst
.operands
[0].reg
;
14074 Rm
= inst
.operands
[1].reg
;
14075 Rn
= inst
.operands
[2].reg
;
14077 reject_bad_reg (Rd
);
14078 reject_bad_reg (Rn
);
14079 reject_bad_reg (Rm
);
14081 inst
.instruction
|= Rd
<< 8;
14082 inst
.instruction
|= Rn
<< 16;
14083 inst
.instruction
|= Rm
;
14089 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14090 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
14091 _("SMC is not permitted on this architecture"));
14092 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14093 _("expression too complex"));
14094 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
14096 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14097 inst
.instruction
|= (value
& 0x000f) << 16;
14099 /* PR gas/15623: SMC instructions must be last in an IT block. */
14100 set_pred_insn_type_last ();
14106 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
14108 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14109 inst
.instruction
|= (value
& 0x0fff);
14110 inst
.instruction
|= (value
& 0xf000) << 4;
14114 do_t_ssat_usat (int bias
)
14118 Rd
= inst
.operands
[0].reg
;
14119 Rn
= inst
.operands
[2].reg
;
14121 reject_bad_reg (Rd
);
14122 reject_bad_reg (Rn
);
14124 inst
.instruction
|= Rd
<< 8;
14125 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
14126 inst
.instruction
|= Rn
<< 16;
14128 if (inst
.operands
[3].present
)
14130 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
14132 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
14134 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
14135 _("expression too complex"));
14137 if (shift_amount
!= 0)
14139 constraint (shift_amount
> 31,
14140 _("shift expression is too large"));
14142 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
14143 inst
.instruction
|= 0x00200000; /* sh bit. */
14145 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14146 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14154 do_t_ssat_usat (1);
14162 Rd
= inst
.operands
[0].reg
;
14163 Rn
= inst
.operands
[2].reg
;
14165 reject_bad_reg (Rd
);
14166 reject_bad_reg (Rn
);
14168 inst
.instruction
|= Rd
<< 8;
14169 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14170 inst
.instruction
|= Rn
<< 16;
14176 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14177 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14178 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14179 || inst
.operands
[2].negative
,
14182 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14184 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14185 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14186 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14187 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14193 if (!inst
.operands
[2].present
)
14194 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14196 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14197 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14198 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14201 inst
.instruction
|= inst
.operands
[0].reg
;
14202 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14203 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14204 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14210 unsigned Rd
, Rn
, Rm
;
14212 Rd
= inst
.operands
[0].reg
;
14213 Rn
= inst
.operands
[1].reg
;
14214 Rm
= inst
.operands
[2].reg
;
14216 reject_bad_reg (Rd
);
14217 reject_bad_reg (Rn
);
14218 reject_bad_reg (Rm
);
14220 inst
.instruction
|= Rd
<< 8;
14221 inst
.instruction
|= Rn
<< 16;
14222 inst
.instruction
|= Rm
;
14223 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14231 Rd
= inst
.operands
[0].reg
;
14232 Rm
= inst
.operands
[1].reg
;
14234 reject_bad_reg (Rd
);
14235 reject_bad_reg (Rm
);
14237 if (inst
.instruction
<= 0xffff
14238 && inst
.size_req
!= 4
14239 && Rd
<= 7 && Rm
<= 7
14240 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14242 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14243 inst
.instruction
|= Rd
;
14244 inst
.instruction
|= Rm
<< 3;
14246 else if (unified_syntax
)
14248 if (inst
.instruction
<= 0xffff)
14249 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14250 inst
.instruction
|= Rd
<< 8;
14251 inst
.instruction
|= Rm
;
14252 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14256 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14257 _("Thumb encoding does not support rotation"));
14258 constraint (1, BAD_HIREG
);
14265 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14274 half
= (inst
.instruction
& 0x10) != 0;
14275 set_pred_insn_type_last ();
14276 constraint (inst
.operands
[0].immisreg
,
14277 _("instruction requires register index"));
14279 Rn
= inst
.operands
[0].reg
;
14280 Rm
= inst
.operands
[0].imm
;
14282 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14283 constraint (Rn
== REG_SP
, BAD_SP
);
14284 reject_bad_reg (Rm
);
14286 constraint (!half
&& inst
.operands
[0].shifted
,
14287 _("instruction does not allow shifted index"));
14288 inst
.instruction
|= (Rn
<< 16) | Rm
;
14294 if (!inst
.operands
[0].present
)
14295 inst
.operands
[0].imm
= 0;
14297 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14299 constraint (inst
.size_req
== 2,
14300 _("immediate value out of range"));
14301 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14302 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14303 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14307 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14308 inst
.instruction
|= inst
.operands
[0].imm
;
14311 set_pred_insn_type (NEUTRAL_IT_INSN
);
14318 do_t_ssat_usat (0);
14326 Rd
= inst
.operands
[0].reg
;
14327 Rn
= inst
.operands
[2].reg
;
14329 reject_bad_reg (Rd
);
14330 reject_bad_reg (Rn
);
14332 inst
.instruction
|= Rd
<< 8;
14333 inst
.instruction
|= inst
.operands
[1].imm
;
14334 inst
.instruction
|= Rn
<< 16;
14337 /* Checking the range of the branch offset (VAL) with NBITS bits
14338 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14340 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14342 gas_assert (nbits
> 0 && nbits
<= 32);
14345 int cmp
= (1 << (nbits
- 1));
14346 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14351 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14357 /* For branches in Armv8.1-M Mainline. */
14359 do_t_branch_future (void)
14361 unsigned long insn
= inst
.instruction
;
14363 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14364 if (inst
.operands
[0].hasreloc
== 0)
14366 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14367 as_bad (BAD_BRANCH_OFF
);
14369 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14373 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14374 inst
.relocs
[0].pc_rel
= 1;
14380 if (inst
.operands
[1].hasreloc
== 0)
14382 int val
= inst
.operands
[1].imm
;
14383 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14384 as_bad (BAD_BRANCH_OFF
);
14386 int immA
= (val
& 0x0001f000) >> 12;
14387 int immB
= (val
& 0x00000ffc) >> 2;
14388 int immC
= (val
& 0x00000002) >> 1;
14389 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14393 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14394 inst
.relocs
[1].pc_rel
= 1;
14399 if (inst
.operands
[1].hasreloc
== 0)
14401 int val
= inst
.operands
[1].imm
;
14402 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14403 as_bad (BAD_BRANCH_OFF
);
14405 int immA
= (val
& 0x0007f000) >> 12;
14406 int immB
= (val
& 0x00000ffc) >> 2;
14407 int immC
= (val
& 0x00000002) >> 1;
14408 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14412 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14413 inst
.relocs
[1].pc_rel
= 1;
14417 case T_MNEM_bfcsel
:
14419 if (inst
.operands
[1].hasreloc
== 0)
14421 int val
= inst
.operands
[1].imm
;
14422 int immA
= (val
& 0x00001000) >> 12;
14423 int immB
= (val
& 0x00000ffc) >> 2;
14424 int immC
= (val
& 0x00000002) >> 1;
14425 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14429 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14430 inst
.relocs
[1].pc_rel
= 1;
14434 if (inst
.operands
[2].hasreloc
== 0)
14436 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14437 int val2
= inst
.operands
[2].imm
;
14438 int val0
= inst
.operands
[0].imm
& 0x1f;
14439 int diff
= val2
- val0
;
14441 inst
.instruction
|= 1 << 17; /* T bit. */
14442 else if (diff
!= 2)
14443 as_bad (_("out of range label-relative fixup value"));
14447 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14448 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14449 inst
.relocs
[2].pc_rel
= 1;
14453 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14454 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14459 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14466 /* Helper function for do_t_loloop to handle relocations. */
14468 v8_1_loop_reloc (int is_le
)
14470 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14472 int value
= inst
.relocs
[0].exp
.X_add_number
;
14473 value
= (is_le
) ? -value
: value
;
14475 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14476 as_bad (BAD_BRANCH_OFF
);
14480 immh
= (value
& 0x00000ffc) >> 2;
14481 imml
= (value
& 0x00000002) >> 1;
14483 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14487 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14488 inst
.relocs
[0].pc_rel
= 1;
14492 /* For shifts with four operands in MVE. */
14494 do_mve_scalar_shift1 (void)
14496 unsigned int value
= inst
.operands
[2].imm
;
14498 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14499 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14501 /* Setting the bit for saturation. */
14502 inst
.instruction
|= ((value
== 64) ? 0: 1) << 7;
14504 /* Assuming Rm is already checked not to be 11x1. */
14505 constraint (inst
.operands
[3].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14506 constraint (inst
.operands
[3].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14507 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
14510 /* For shifts in MVE. */
14512 do_mve_scalar_shift (void)
14514 if (!inst
.operands
[2].present
)
14516 inst
.operands
[2] = inst
.operands
[1];
14517 inst
.operands
[1].reg
= 0xf;
14520 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14521 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14523 if (inst
.operands
[2].isreg
)
14525 /* Assuming Rm is already checked not to be 11x1. */
14526 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14527 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14528 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14532 /* Assuming imm is already checked as [1,32]. */
14533 unsigned int value
= inst
.operands
[2].imm
;
14534 inst
.instruction
|= (value
& 0x1c) << 10;
14535 inst
.instruction
|= (value
& 0x03) << 6;
14536 /* Change last 4 bits from 0xd to 0xf. */
14537 inst
.instruction
|= 0x2;
14541 /* MVE instruction encoder helpers. */
14542 #define M_MNEM_vabav 0xee800f01
14543 #define M_MNEM_vmladav 0xeef00e00
14544 #define M_MNEM_vmladava 0xeef00e20
14545 #define M_MNEM_vmladavx 0xeef01e00
14546 #define M_MNEM_vmladavax 0xeef01e20
14547 #define M_MNEM_vmlsdav 0xeef00e01
14548 #define M_MNEM_vmlsdava 0xeef00e21
14549 #define M_MNEM_vmlsdavx 0xeef01e01
14550 #define M_MNEM_vmlsdavax 0xeef01e21
14551 #define M_MNEM_vmullt 0xee011e00
14552 #define M_MNEM_vmullb 0xee010e00
14553 #define M_MNEM_vctp 0xf000e801
14554 #define M_MNEM_vst20 0xfc801e00
14555 #define M_MNEM_vst21 0xfc801e20
14556 #define M_MNEM_vst40 0xfc801e01
14557 #define M_MNEM_vst41 0xfc801e21
14558 #define M_MNEM_vst42 0xfc801e41
14559 #define M_MNEM_vst43 0xfc801e61
14560 #define M_MNEM_vld20 0xfc901e00
14561 #define M_MNEM_vld21 0xfc901e20
14562 #define M_MNEM_vld40 0xfc901e01
14563 #define M_MNEM_vld41 0xfc901e21
14564 #define M_MNEM_vld42 0xfc901e41
14565 #define M_MNEM_vld43 0xfc901e61
14566 #define M_MNEM_vstrb 0xec000e00
14567 #define M_MNEM_vstrh 0xec000e10
14568 #define M_MNEM_vstrw 0xec000e40
14569 #define M_MNEM_vstrd 0xec000e50
14570 #define M_MNEM_vldrb 0xec100e00
14571 #define M_MNEM_vldrh 0xec100e10
14572 #define M_MNEM_vldrw 0xec100e40
14573 #define M_MNEM_vldrd 0xec100e50
14574 #define M_MNEM_vmovlt 0xeea01f40
14575 #define M_MNEM_vmovlb 0xeea00f40
14576 #define M_MNEM_vmovnt 0xfe311e81
14577 #define M_MNEM_vmovnb 0xfe310e81
14578 #define M_MNEM_vadc 0xee300f00
14579 #define M_MNEM_vadci 0xee301f00
14580 #define M_MNEM_vbrsr 0xfe011e60
14581 #define M_MNEM_vaddlv 0xee890f00
14582 #define M_MNEM_vaddlva 0xee890f20
14583 #define M_MNEM_vaddv 0xeef10f00
14584 #define M_MNEM_vaddva 0xeef10f20
14585 #define M_MNEM_vddup 0xee011f6e
14586 #define M_MNEM_vdwdup 0xee011f60
14587 #define M_MNEM_vidup 0xee010f6e
14588 #define M_MNEM_viwdup 0xee010f60
14589 #define M_MNEM_vmaxv 0xeee20f00
14590 #define M_MNEM_vmaxav 0xeee00f00
14591 #define M_MNEM_vminv 0xeee20f80
14592 #define M_MNEM_vminav 0xeee00f80
14593 #define M_MNEM_vmlaldav 0xee800e00
14594 #define M_MNEM_vmlaldava 0xee800e20
14595 #define M_MNEM_vmlaldavx 0xee801e00
14596 #define M_MNEM_vmlaldavax 0xee801e20
14597 #define M_MNEM_vmlsldav 0xee800e01
14598 #define M_MNEM_vmlsldava 0xee800e21
14599 #define M_MNEM_vmlsldavx 0xee801e01
14600 #define M_MNEM_vmlsldavax 0xee801e21
14601 #define M_MNEM_vrmlaldavhx 0xee801f00
14602 #define M_MNEM_vrmlaldavhax 0xee801f20
14603 #define M_MNEM_vrmlsldavh 0xfe800e01
14604 #define M_MNEM_vrmlsldavha 0xfe800e21
14605 #define M_MNEM_vrmlsldavhx 0xfe801e01
14606 #define M_MNEM_vrmlsldavhax 0xfe801e21
14607 #define M_MNEM_vqmovnt 0xee331e01
14608 #define M_MNEM_vqmovnb 0xee330e01
14609 #define M_MNEM_vqmovunt 0xee311e81
14610 #define M_MNEM_vqmovunb 0xee310e81
14611 #define M_MNEM_vshrnt 0xee801fc1
14612 #define M_MNEM_vshrnb 0xee800fc1
14613 #define M_MNEM_vrshrnt 0xfe801fc1
14614 #define M_MNEM_vqshrnt 0xee801f40
14615 #define M_MNEM_vqshrnb 0xee800f40
14616 #define M_MNEM_vqshrunt 0xee801fc0
14617 #define M_MNEM_vqshrunb 0xee800fc0
14618 #define M_MNEM_vrshrnb 0xfe800fc1
14619 #define M_MNEM_vqrshrnt 0xee801f41
14620 #define M_MNEM_vqrshrnb 0xee800f41
14621 #define M_MNEM_vqrshrunt 0xfe801fc0
14622 #define M_MNEM_vqrshrunb 0xfe800fc0
14624 /* Bfloat16 instruction encoder helpers. */
14625 #define B_MNEM_vfmat 0xfc300850
14626 #define B_MNEM_vfmab 0xfc300810
14628 /* Neon instruction encoder helpers. */
14630 /* Encodings for the different types for various Neon opcodes. */
14632 /* An "invalid" code for the following tables. */
14635 struct neon_tab_entry
14638 unsigned float_or_poly
;
14639 unsigned scalar_or_imm
;
14642 /* Map overloaded Neon opcodes to their respective encodings. */
14643 #define NEON_ENC_TAB \
14644 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14645 X(vabdl, 0x0800700, N_INV, N_INV), \
14646 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14647 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14648 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14649 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14650 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14651 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14652 X(vaddl, 0x0800000, N_INV, N_INV), \
14653 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14654 X(vsubl, 0x0800200, N_INV, N_INV), \
14655 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14656 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14657 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14658 /* Register variants of the following two instructions are encoded as
14659 vcge / vcgt with the operands reversed. */ \
14660 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14661 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14662 X(vfma, N_INV, 0x0000c10, N_INV), \
14663 X(vfms, N_INV, 0x0200c10, N_INV), \
14664 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14665 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14666 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14667 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14668 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14669 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14670 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14671 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14672 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14673 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14674 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14675 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14676 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14677 X(vshl, 0x0000400, N_INV, 0x0800510), \
14678 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14679 X(vand, 0x0000110, N_INV, 0x0800030), \
14680 X(vbic, 0x0100110, N_INV, 0x0800030), \
14681 X(veor, 0x1000110, N_INV, N_INV), \
14682 X(vorn, 0x0300110, N_INV, 0x0800010), \
14683 X(vorr, 0x0200110, N_INV, 0x0800010), \
14684 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14685 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14686 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14687 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14688 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14689 X(vst1, 0x0000000, 0x0800000, N_INV), \
14690 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14691 X(vst2, 0x0000100, 0x0800100, N_INV), \
14692 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14693 X(vst3, 0x0000200, 0x0800200, N_INV), \
14694 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14695 X(vst4, 0x0000300, 0x0800300, N_INV), \
14696 X(vmovn, 0x1b20200, N_INV, N_INV), \
14697 X(vtrn, 0x1b20080, N_INV, N_INV), \
14698 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14699 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14700 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14701 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14702 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14703 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14704 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14705 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14706 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14707 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14708 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14709 X(vseleq, 0xe000a00, N_INV, N_INV), \
14710 X(vselvs, 0xe100a00, N_INV, N_INV), \
14711 X(vselge, 0xe200a00, N_INV, N_INV), \
14712 X(vselgt, 0xe300a00, N_INV, N_INV), \
14713 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14714 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14715 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14716 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14717 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14718 X(aes, 0x3b00300, N_INV, N_INV), \
14719 X(sha3op, 0x2000c00, N_INV, N_INV), \
14720 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14721 X(sha2op, 0x3ba0380, N_INV, N_INV)
14725 #define X(OPC,I,F,S) N_MNEM_##OPC
14730 static const struct neon_tab_entry neon_enc_tab
[] =
14732 #define X(OPC,I,F,S) { (I), (F), (S) }
14737 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14738 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14739 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14740 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14741 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14742 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14743 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14744 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14745 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14746 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14747 #define NEON_ENC_SINGLE_(X) \
14748 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14749 #define NEON_ENC_DOUBLE_(X) \
14750 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14751 #define NEON_ENC_FPV8_(X) \
14752 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14754 #define NEON_ENCODE(type, inst) \
14757 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14758 inst.is_neon = 1; \
14762 #define check_neon_suffixes \
14765 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14767 as_bad (_("invalid neon suffix for non neon instruction")); \
14773 /* Define shapes for instruction operands. The following mnemonic characters
14774 are used in this table:
14776 F - VFP S<n> register
14777 D - Neon D<n> register
14778 Q - Neon Q<n> register
14782 L - D<n> register list
14784 This table is used to generate various data:
14785 - enumerations of the form NS_DDR to be used as arguments to
14787 - a table classifying shapes into single, double, quad, mixed.
14788 - a table used to drive neon_select_shape. */
14790 #define NEON_SHAPE_DEF \
14791 X(4, (R, R, Q, Q), QUAD), \
14792 X(4, (Q, R, R, I), QUAD), \
14793 X(4, (R, R, S, S), QUAD), \
14794 X(4, (S, S, R, R), QUAD), \
14795 X(3, (Q, R, I), QUAD), \
14796 X(3, (I, Q, Q), QUAD), \
14797 X(3, (I, Q, R), QUAD), \
14798 X(3, (R, Q, Q), QUAD), \
14799 X(3, (D, D, D), DOUBLE), \
14800 X(3, (Q, Q, Q), QUAD), \
14801 X(3, (D, D, I), DOUBLE), \
14802 X(3, (Q, Q, I), QUAD), \
14803 X(3, (D, D, S), DOUBLE), \
14804 X(3, (Q, Q, S), QUAD), \
14805 X(3, (Q, Q, R), QUAD), \
14806 X(3, (R, R, Q), QUAD), \
14807 X(2, (R, Q), QUAD), \
14808 X(2, (D, D), DOUBLE), \
14809 X(2, (Q, Q), QUAD), \
14810 X(2, (D, S), DOUBLE), \
14811 X(2, (Q, S), QUAD), \
14812 X(2, (D, R), DOUBLE), \
14813 X(2, (Q, R), QUAD), \
14814 X(2, (D, I), DOUBLE), \
14815 X(2, (Q, I), QUAD), \
14816 X(3, (P, F, I), SINGLE), \
14817 X(3, (P, D, I), DOUBLE), \
14818 X(3, (P, Q, I), QUAD), \
14819 X(4, (P, F, F, I), SINGLE), \
14820 X(4, (P, D, D, I), DOUBLE), \
14821 X(4, (P, Q, Q, I), QUAD), \
14822 X(5, (P, F, F, F, I), SINGLE), \
14823 X(5, (P, D, D, D, I), DOUBLE), \
14824 X(5, (P, Q, Q, Q, I), QUAD), \
14825 X(3, (D, L, D), DOUBLE), \
14826 X(2, (D, Q), MIXED), \
14827 X(2, (Q, D), MIXED), \
14828 X(3, (D, Q, I), MIXED), \
14829 X(3, (Q, D, I), MIXED), \
14830 X(3, (Q, D, D), MIXED), \
14831 X(3, (D, Q, Q), MIXED), \
14832 X(3, (Q, Q, D), MIXED), \
14833 X(3, (Q, D, S), MIXED), \
14834 X(3, (D, Q, S), MIXED), \
14835 X(4, (D, D, D, I), DOUBLE), \
14836 X(4, (Q, Q, Q, I), QUAD), \
14837 X(4, (D, D, S, I), DOUBLE), \
14838 X(4, (Q, Q, S, I), QUAD), \
14839 X(2, (F, F), SINGLE), \
14840 X(3, (F, F, F), SINGLE), \
14841 X(2, (F, I), SINGLE), \
14842 X(2, (F, D), MIXED), \
14843 X(2, (D, F), MIXED), \
14844 X(3, (F, F, I), MIXED), \
14845 X(4, (R, R, F, F), SINGLE), \
14846 X(4, (F, F, R, R), SINGLE), \
14847 X(3, (D, R, R), DOUBLE), \
14848 X(3, (R, R, D), DOUBLE), \
14849 X(2, (S, R), SINGLE), \
14850 X(2, (R, S), SINGLE), \
14851 X(2, (F, R), SINGLE), \
14852 X(2, (R, F), SINGLE), \
14853 /* Used for MVE tail predicated loop instructions. */\
14854 X(2, (R, R), QUAD), \
14855 /* Half float shape supported so far. */\
14856 X (2, (H, D), MIXED), \
14857 X (2, (D, H), MIXED), \
14858 X (2, (H, F), MIXED), \
14859 X (2, (F, H), MIXED), \
14860 X (2, (H, H), HALF), \
14861 X (2, (H, R), HALF), \
14862 X (2, (R, H), HALF), \
14863 X (2, (H, I), HALF), \
14864 X (3, (H, H, H), HALF), \
14865 X (3, (H, F, I), MIXED), \
14866 X (3, (F, H, I), MIXED), \
14867 X (3, (D, H, H), MIXED), \
14868 X (3, (D, H, S), MIXED)
14870 #define S2(A,B) NS_##A##B
14871 #define S3(A,B,C) NS_##A##B##C
14872 #define S4(A,B,C,D) NS_##A##B##C##D
14873 #define S5(A,B,C,D,E) NS_##A##B##C##D##E
14875 #define X(N, L, C) S##N L
14889 enum neon_shape_class
14898 #define X(N, L, C) SC_##C
14900 static enum neon_shape_class neon_shape_class
[] =
14920 /* Register widths of above. */
14921 static unsigned neon_shape_el_size
[] =
14934 struct neon_shape_info
14937 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14940 #define S2(A,B) { SE_##A, SE_##B }
14941 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14942 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14943 #define S5(A,B,C,D,E) { SE_##A, SE_##B, SE_##C, SE_##D, SE_##E }
14945 #define X(N, L, C) { N, S##N L }
14947 static struct neon_shape_info neon_shape_tab
[] =
14958 /* Bit masks used in type checking given instructions.
14959 'N_EQK' means the type must be the same as (or based on in some way) the key
14960 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14961 set, various other bits can be set as well in order to modify the meaning of
14962 the type constraint. */
14964 enum neon_type_mask
14988 N_BF16
= 0x0400000,
14989 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14990 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14991 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14992 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14993 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14994 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14995 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14996 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14997 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14998 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14999 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
15001 N_MAX_NONSPECIAL
= N_P64
15004 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
15006 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
15007 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15008 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
15009 #define N_S_32 (N_S8 | N_S16 | N_S32)
15010 #define N_F_16_32 (N_F16 | N_F32)
15011 #define N_SUF_32 (N_SU_32 | N_F_16_32)
15012 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
15013 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
15014 #define N_F_ALL (N_F16 | N_F32 | N_F64)
15015 #define N_I_MVE (N_I8 | N_I16 | N_I32)
15016 #define N_F_MVE (N_F16 | N_F32)
15017 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
15019 /* Pass this as the first type argument to neon_check_type to ignore types
15021 #define N_IGNORE_TYPE (N_KEY | N_EQK)
15023 /* Select a "shape" for the current instruction (describing register types or
15024 sizes) from a list of alternatives. Return NS_NULL if the current instruction
15025 doesn't fit. For non-polymorphic shapes, checking is usually done as a
15026 function of operand parsing, so this function doesn't need to be called.
15027 Shapes should be listed in order of decreasing length. */
15029 static enum neon_shape
15030 neon_select_shape (enum neon_shape shape
, ...)
15033 enum neon_shape first_shape
= shape
;
15035 /* Fix missing optional operands. FIXME: we don't know at this point how
15036 many arguments we should have, so this makes the assumption that we have
15037 > 1. This is true of all current Neon opcodes, I think, but may not be
15038 true in the future. */
15039 if (!inst
.operands
[1].present
)
15040 inst
.operands
[1] = inst
.operands
[0];
15042 va_start (ap
, shape
);
15044 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
15049 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
15051 if (!inst
.operands
[j
].present
)
15057 switch (neon_shape_tab
[shape
].el
[j
])
15059 /* If a .f16, .16, .u16, .s16 type specifier is given over
15060 a VFP single precision register operand, it's essentially
15061 means only half of the register is used.
15063 If the type specifier is given after the mnemonics, the
15064 information is stored in inst.vectype. If the type specifier
15065 is given after register operand, the information is stored
15066 in inst.operands[].vectype.
15068 When there is only one type specifier, and all the register
15069 operands are the same type of hardware register, the type
15070 specifier applies to all register operands.
15072 If no type specifier is given, the shape is inferred from
15073 operand information.
15076 vadd.f16 s0, s1, s2: NS_HHH
15077 vabs.f16 s0, s1: NS_HH
15078 vmov.f16 s0, r1: NS_HR
15079 vmov.f16 r0, s1: NS_RH
15080 vcvt.f16 r0, s1: NS_RH
15081 vcvt.f16.s32 s2, s2, #29: NS_HFI
15082 vcvt.f16.s32 s2, s2: NS_HF
15085 if (!(inst
.operands
[j
].isreg
15086 && inst
.operands
[j
].isvec
15087 && inst
.operands
[j
].issingle
15088 && !inst
.operands
[j
].isquad
15089 && ((inst
.vectype
.elems
== 1
15090 && inst
.vectype
.el
[0].size
== 16)
15091 || (inst
.vectype
.elems
> 1
15092 && inst
.vectype
.el
[j
].size
== 16)
15093 || (inst
.vectype
.elems
== 0
15094 && inst
.operands
[j
].vectype
.type
!= NT_invtype
15095 && inst
.operands
[j
].vectype
.size
== 16))))
15100 if (!(inst
.operands
[j
].isreg
15101 && inst
.operands
[j
].isvec
15102 && inst
.operands
[j
].issingle
15103 && !inst
.operands
[j
].isquad
15104 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
15105 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
15106 || (inst
.vectype
.elems
== 0
15107 && (inst
.operands
[j
].vectype
.size
== 32
15108 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
15113 if (!(inst
.operands
[j
].isreg
15114 && inst
.operands
[j
].isvec
15115 && !inst
.operands
[j
].isquad
15116 && !inst
.operands
[j
].issingle
))
15121 if (!(inst
.operands
[j
].isreg
15122 && !inst
.operands
[j
].isvec
))
15127 if (!(inst
.operands
[j
].isreg
15128 && inst
.operands
[j
].isvec
15129 && inst
.operands
[j
].isquad
15130 && !inst
.operands
[j
].issingle
))
15135 if (!(!inst
.operands
[j
].isreg
15136 && !inst
.operands
[j
].isscalar
))
15141 if (!(!inst
.operands
[j
].isreg
15142 && inst
.operands
[j
].isscalar
))
15153 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
15154 /* We've matched all the entries in the shape table, and we don't
15155 have any left over operands which have not been matched. */
15161 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
15162 first_error (_("invalid instruction shape"));
15167 /* True if SHAPE is predominantly a quadword operation (most of the time, this
15168 means the Q bit should be set). */
15171 neon_quad (enum neon_shape shape
)
15173 return neon_shape_class
[shape
] == SC_QUAD
;
15177 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
15180 /* Allow modification to be made to types which are constrained to be
15181 based on the key element, based on bits set alongside N_EQK. */
15182 if ((typebits
& N_EQK
) != 0)
15184 if ((typebits
& N_HLF
) != 0)
15186 else if ((typebits
& N_DBL
) != 0)
15188 if ((typebits
& N_SGN
) != 0)
15189 *g_type
= NT_signed
;
15190 else if ((typebits
& N_UNS
) != 0)
15191 *g_type
= NT_unsigned
;
15192 else if ((typebits
& N_INT
) != 0)
15193 *g_type
= NT_integer
;
15194 else if ((typebits
& N_FLT
) != 0)
15195 *g_type
= NT_float
;
15196 else if ((typebits
& N_SIZ
) != 0)
15197 *g_type
= NT_untyped
;
15201 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15202 operand type, i.e. the single type specified in a Neon instruction when it
15203 is the only one given. */
15205 static struct neon_type_el
15206 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15208 struct neon_type_el dest
= *key
;
15210 gas_assert ((thisarg
& N_EQK
) != 0);
15212 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15217 /* Convert Neon type and size into compact bitmask representation. */
15219 static enum neon_type_mask
15220 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15227 case 8: return N_8
;
15228 case 16: return N_16
;
15229 case 32: return N_32
;
15230 case 64: return N_64
;
15238 case 8: return N_I8
;
15239 case 16: return N_I16
;
15240 case 32: return N_I32
;
15241 case 64: return N_I64
;
15249 case 16: return N_F16
;
15250 case 32: return N_F32
;
15251 case 64: return N_F64
;
15259 case 8: return N_P8
;
15260 case 16: return N_P16
;
15261 case 64: return N_P64
;
15269 case 8: return N_S8
;
15270 case 16: return N_S16
;
15271 case 32: return N_S32
;
15272 case 64: return N_S64
;
15280 case 8: return N_U8
;
15281 case 16: return N_U16
;
15282 case 32: return N_U32
;
15283 case 64: return N_U64
;
15289 if (size
== 16) return N_BF16
;
15298 /* Convert compact Neon bitmask type representation to a type and size. Only
15299 handles the case where a single bit is set in the mask. */
15302 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15303 enum neon_type_mask mask
)
15305 if ((mask
& N_EQK
) != 0)
15308 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15310 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
| N_BF16
))
15313 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15315 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15320 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15322 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15323 *type
= NT_unsigned
;
15324 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15325 *type
= NT_integer
;
15326 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15327 *type
= NT_untyped
;
15328 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15330 else if ((mask
& (N_F_ALL
)) != 0)
15332 else if ((mask
& (N_BF16
)) != 0)
15340 /* Modify a bitmask of allowed types. This is only needed for type
15344 modify_types_allowed (unsigned allowed
, unsigned mods
)
15347 enum neon_el_type type
;
15353 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15355 if (el_type_of_type_chk (&type
, &size
,
15356 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15358 neon_modify_type_size (mods
, &type
, &size
);
15359 destmask
|= type_chk_of_el_type (type
, size
);
15366 /* Check type and return type classification.
15367 The manual states (paraphrase): If one datatype is given, it indicates the
15369 - the second operand, if there is one
15370 - the operand, if there is no second operand
15371 - the result, if there are no operands.
15372 This isn't quite good enough though, so we use a concept of a "key" datatype
15373 which is set on a per-instruction basis, which is the one which matters when
15374 only one data type is written.
15375 Note: this function has side-effects (e.g. filling in missing operands). All
15376 Neon instructions should call it before performing bit encoding. */
15378 static struct neon_type_el
15379 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15382 unsigned i
, pass
, key_el
= 0;
15383 unsigned types
[NEON_MAX_TYPE_ELS
];
15384 enum neon_el_type k_type
= NT_invtype
;
15385 unsigned k_size
= -1u;
15386 struct neon_type_el badtype
= {NT_invtype
, -1};
15387 unsigned key_allowed
= 0;
15389 /* Optional registers in Neon instructions are always (not) in operand 1.
15390 Fill in the missing operand here, if it was omitted. */
15391 if (els
> 1 && !inst
.operands
[1].present
)
15392 inst
.operands
[1] = inst
.operands
[0];
15394 /* Suck up all the varargs. */
15396 for (i
= 0; i
< els
; i
++)
15398 unsigned thisarg
= va_arg (ap
, unsigned);
15399 if (thisarg
== N_IGNORE_TYPE
)
15404 types
[i
] = thisarg
;
15405 if ((thisarg
& N_KEY
) != 0)
15410 if (inst
.vectype
.elems
> 0)
15411 for (i
= 0; i
< els
; i
++)
15412 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15414 first_error (_("types specified in both the mnemonic and operands"));
15418 /* Duplicate inst.vectype elements here as necessary.
15419 FIXME: No idea if this is exactly the same as the ARM assembler,
15420 particularly when an insn takes one register and one non-register
15422 if (inst
.vectype
.elems
== 1 && els
> 1)
15425 inst
.vectype
.elems
= els
;
15426 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15427 for (j
= 0; j
< els
; j
++)
15429 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15432 else if (inst
.vectype
.elems
== 0 && els
> 0)
15435 /* No types were given after the mnemonic, so look for types specified
15436 after each operand. We allow some flexibility here; as long as the
15437 "key" operand has a type, we can infer the others. */
15438 for (j
= 0; j
< els
; j
++)
15439 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15440 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15442 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15444 for (j
= 0; j
< els
; j
++)
15445 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15446 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15451 first_error (_("operand types can't be inferred"));
15455 else if (inst
.vectype
.elems
!= els
)
15457 first_error (_("type specifier has the wrong number of parts"));
15461 for (pass
= 0; pass
< 2; pass
++)
15463 for (i
= 0; i
< els
; i
++)
15465 unsigned thisarg
= types
[i
];
15466 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15467 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15468 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15469 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15471 /* Decay more-specific signed & unsigned types to sign-insensitive
15472 integer types if sign-specific variants are unavailable. */
15473 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15474 && (types_allowed
& N_SU_ALL
) == 0)
15475 g_type
= NT_integer
;
15477 /* If only untyped args are allowed, decay any more specific types to
15478 them. Some instructions only care about signs for some element
15479 sizes, so handle that properly. */
15480 if (((types_allowed
& N_UNT
) == 0)
15481 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15482 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15483 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15484 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15485 g_type
= NT_untyped
;
15489 if ((thisarg
& N_KEY
) != 0)
15493 key_allowed
= thisarg
& ~N_KEY
;
15495 /* Check architecture constraint on FP16 extension. */
15497 && k_type
== NT_float
15498 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15500 inst
.error
= _(BAD_FP16
);
15507 if ((thisarg
& N_VFP
) != 0)
15509 enum neon_shape_el regshape
;
15510 unsigned regwidth
, match
;
15512 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15515 first_error (_("invalid instruction shape"));
15518 regshape
= neon_shape_tab
[ns
].el
[i
];
15519 regwidth
= neon_shape_el_size
[regshape
];
15521 /* In VFP mode, operands must match register widths. If we
15522 have a key operand, use its width, else use the width of
15523 the current operand. */
15529 /* FP16 will use a single precision register. */
15530 if (regwidth
== 32 && match
== 16)
15532 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15536 inst
.error
= _(BAD_FP16
);
15541 if (regwidth
!= match
)
15543 first_error (_("operand size must match register width"));
15548 if ((thisarg
& N_EQK
) == 0)
15550 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15552 if ((given_type
& types_allowed
) == 0)
15554 first_error (BAD_SIMD_TYPE
);
15560 enum neon_el_type mod_k_type
= k_type
;
15561 unsigned mod_k_size
= k_size
;
15562 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15563 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15565 first_error (_("inconsistent types in Neon instruction"));
15573 return inst
.vectype
.el
[key_el
];
15576 /* Neon-style VFP instruction forwarding. */
15578 /* Thumb VFP instructions have 0xE in the condition field. */
15581 do_vfp_cond_or_thumb (void)
15586 inst
.instruction
|= 0xe0000000;
15588 inst
.instruction
|= inst
.cond
<< 28;
15591 /* Look up and encode a simple mnemonic, for use as a helper function for the
15592 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15593 etc. It is assumed that operand parsing has already been done, and that the
15594 operands are in the form expected by the given opcode (this isn't necessarily
15595 the same as the form in which they were parsed, hence some massaging must
15596 take place before this function is called).
15597 Checks current arch version against that in the looked-up opcode. */
15600 do_vfp_nsyn_opcode (const char *opname
)
15602 const struct asm_opcode
*opcode
;
15604 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15609 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15610 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15617 inst
.instruction
= opcode
->tvalue
;
15618 opcode
->tencode ();
15622 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15623 opcode
->aencode ();
15628 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15630 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15632 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15635 do_vfp_nsyn_opcode ("fadds");
15637 do_vfp_nsyn_opcode ("fsubs");
15639 /* ARMv8.2 fp16 instruction. */
15641 do_scalar_fp16_v82_encode ();
15646 do_vfp_nsyn_opcode ("faddd");
15648 do_vfp_nsyn_opcode ("fsubd");
15652 /* Check operand types to see if this is a VFP instruction, and if so call
15656 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15658 enum neon_shape rs
;
15659 struct neon_type_el et
;
15664 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15665 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15669 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15670 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15671 N_F_ALL
| N_KEY
| N_VFP
);
15678 if (et
.type
!= NT_invtype
)
15689 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15691 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15693 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15696 do_vfp_nsyn_opcode ("fmacs");
15698 do_vfp_nsyn_opcode ("fnmacs");
15700 /* ARMv8.2 fp16 instruction. */
15702 do_scalar_fp16_v82_encode ();
15707 do_vfp_nsyn_opcode ("fmacd");
15709 do_vfp_nsyn_opcode ("fnmacd");
15714 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15716 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15718 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15721 do_vfp_nsyn_opcode ("ffmas");
15723 do_vfp_nsyn_opcode ("ffnmas");
15725 /* ARMv8.2 fp16 instruction. */
15727 do_scalar_fp16_v82_encode ();
15732 do_vfp_nsyn_opcode ("ffmad");
15734 do_vfp_nsyn_opcode ("ffnmad");
15739 do_vfp_nsyn_mul (enum neon_shape rs
)
15741 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15743 do_vfp_nsyn_opcode ("fmuls");
15745 /* ARMv8.2 fp16 instruction. */
15747 do_scalar_fp16_v82_encode ();
15750 do_vfp_nsyn_opcode ("fmuld");
15754 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15756 int is_neg
= (inst
.instruction
& 0x80) != 0;
15757 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15759 if (rs
== NS_FF
|| rs
== NS_HH
)
15762 do_vfp_nsyn_opcode ("fnegs");
15764 do_vfp_nsyn_opcode ("fabss");
15766 /* ARMv8.2 fp16 instruction. */
15768 do_scalar_fp16_v82_encode ();
15773 do_vfp_nsyn_opcode ("fnegd");
15775 do_vfp_nsyn_opcode ("fabsd");
15779 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15780 insns belong to Neon, and are handled elsewhere. */
15783 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15785 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15789 do_vfp_nsyn_opcode ("fldmdbs");
15791 do_vfp_nsyn_opcode ("fldmias");
15796 do_vfp_nsyn_opcode ("fstmdbs");
15798 do_vfp_nsyn_opcode ("fstmias");
15803 do_vfp_nsyn_sqrt (void)
15805 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15806 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15808 if (rs
== NS_FF
|| rs
== NS_HH
)
15810 do_vfp_nsyn_opcode ("fsqrts");
15812 /* ARMv8.2 fp16 instruction. */
15814 do_scalar_fp16_v82_encode ();
15817 do_vfp_nsyn_opcode ("fsqrtd");
15821 do_vfp_nsyn_div (void)
15823 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15824 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15825 N_F_ALL
| N_KEY
| N_VFP
);
15827 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15829 do_vfp_nsyn_opcode ("fdivs");
15831 /* ARMv8.2 fp16 instruction. */
15833 do_scalar_fp16_v82_encode ();
15836 do_vfp_nsyn_opcode ("fdivd");
15840 do_vfp_nsyn_nmul (void)
15842 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15843 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15844 N_F_ALL
| N_KEY
| N_VFP
);
15846 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15848 NEON_ENCODE (SINGLE
, inst
);
15849 do_vfp_sp_dyadic ();
15851 /* ARMv8.2 fp16 instruction. */
15853 do_scalar_fp16_v82_encode ();
15857 NEON_ENCODE (DOUBLE
, inst
);
15858 do_vfp_dp_rd_rn_rm ();
15860 do_vfp_cond_or_thumb ();
15864 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15868 neon_logbits (unsigned x
)
15870 return ffs (x
) - 4;
15873 #define LOW4(R) ((R) & 0xf)
15874 #define HI1(R) (((R) >> 4) & 1)
15875 #define LOW1(R) ((R) & 0x1)
15876 #define HI4(R) (((R) >> 1) & 0xf)
15879 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15884 first_error (BAD_EL_TYPE
);
15887 switch (inst
.operands
[0].imm
)
15890 first_error (_("invalid condition"));
15912 /* only accept eq and ne. */
15913 if (inst
.operands
[0].imm
> 1)
15915 first_error (_("invalid condition"));
15918 return inst
.operands
[0].imm
;
15920 if (inst
.operands
[0].imm
== 0x2)
15922 else if (inst
.operands
[0].imm
== 0x8)
15926 first_error (_("invalid condition"));
15930 switch (inst
.operands
[0].imm
)
15933 first_error (_("invalid condition"));
15949 /* Should be unreachable. */
15953 /* For VCTP (create vector tail predicate) in MVE. */
15958 unsigned size
= 0x0;
15960 if (inst
.cond
> COND_ALWAYS
)
15961 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15963 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15965 /* This is a typical MVE instruction which has no type but have size 8, 16,
15966 32 and 64. For instructions with no type, inst.vectype.el[j].type is set
15967 to NT_untyped and size is updated in inst.vectype.el[j].size. */
15968 if ((inst
.operands
[0].present
) && (inst
.vectype
.el
[0].type
== NT_untyped
))
15969 dt
= inst
.vectype
.el
[0].size
;
15971 /* Setting this does not indicate an actual NEON instruction, but only
15972 indicates that the mnemonic accepts neon-style type suffixes. */
15986 first_error (_("Type is not allowed for this instruction"));
15988 inst
.instruction
|= size
<< 20;
15989 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15995 /* We are dealing with a vector predicated block. */
15996 if (inst
.operands
[0].present
)
15998 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15999 struct neon_type_el et
16000 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16003 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16005 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16007 if (et
.type
== NT_invtype
)
16010 if (et
.type
== NT_float
)
16012 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16014 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
16015 inst
.instruction
|= (et
.size
== 16) << 28;
16016 inst
.instruction
|= 0x3 << 20;
16020 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
16022 inst
.instruction
|= 1 << 28;
16023 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16026 if (inst
.operands
[2].isquad
)
16028 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16029 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16030 inst
.instruction
|= (fcond
& 0x2) >> 1;
16034 if (inst
.operands
[2].reg
== REG_SP
)
16035 as_tsktsk (MVE_BAD_SP
);
16036 inst
.instruction
|= 1 << 6;
16037 inst
.instruction
|= (fcond
& 0x2) << 4;
16038 inst
.instruction
|= inst
.operands
[2].reg
;
16040 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16041 inst
.instruction
|= (fcond
& 0x4) << 10;
16042 inst
.instruction
|= (fcond
& 0x1) << 7;
16045 set_pred_insn_type (VPT_INSN
);
16047 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
16048 | ((inst
.instruction
& 0xe000) >> 13);
16049 now_pred
.warn_deprecated
= FALSE
;
16050 now_pred
.type
= VECTOR_PRED
;
16057 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
16058 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
16059 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
16060 if (!inst
.operands
[2].present
)
16061 first_error (_("MVE vector or ARM register expected"));
16062 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
16064 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
16065 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
16066 && inst
.operands
[1].isquad
)
16068 inst
.instruction
= N_MNEM_vcmp
;
16072 if (inst
.cond
> COND_ALWAYS
)
16073 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16075 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16077 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
16078 struct neon_type_el et
16079 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
16082 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
16083 && !inst
.operands
[2].iszr
, BAD_PC
);
16085 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
16087 inst
.instruction
= 0xee010f00;
16088 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16089 inst
.instruction
|= (fcond
& 0x4) << 10;
16090 inst
.instruction
|= (fcond
& 0x1) << 7;
16091 if (et
.type
== NT_float
)
16093 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
16095 inst
.instruction
|= (et
.size
== 16) << 28;
16096 inst
.instruction
|= 0x3 << 20;
16100 inst
.instruction
|= 1 << 28;
16101 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16103 if (inst
.operands
[2].isquad
)
16105 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16106 inst
.instruction
|= (fcond
& 0x2) >> 1;
16107 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16111 if (inst
.operands
[2].reg
== REG_SP
)
16112 as_tsktsk (MVE_BAD_SP
);
16113 inst
.instruction
|= 1 << 6;
16114 inst
.instruction
|= (fcond
& 0x2) << 4;
16115 inst
.instruction
|= inst
.operands
[2].reg
;
16123 do_mve_vmaxa_vmina (void)
16125 if (inst
.cond
> COND_ALWAYS
)
16126 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16128 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16130 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16131 struct neon_type_el et
16132 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
16134 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16135 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16136 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16137 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16138 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16143 do_mve_vfmas (void)
16145 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16146 struct neon_type_el et
16147 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
16149 if (inst
.cond
> COND_ALWAYS
)
16150 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16152 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16154 if (inst
.operands
[2].reg
== REG_SP
)
16155 as_tsktsk (MVE_BAD_SP
);
16156 else if (inst
.operands
[2].reg
== REG_PC
)
16157 as_tsktsk (MVE_BAD_PC
);
16159 inst
.instruction
|= (et
.size
== 16) << 28;
16160 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16161 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16162 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16163 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16164 inst
.instruction
|= inst
.operands
[2].reg
;
16169 do_mve_viddup (void)
16171 if (inst
.cond
> COND_ALWAYS
)
16172 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16174 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16176 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
16177 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
16178 _("immediate must be either 1, 2, 4 or 8"));
16180 enum neon_shape rs
;
16181 struct neon_type_el et
;
16183 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
16185 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
16186 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
16191 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
16192 if (inst
.operands
[2].reg
== REG_SP
)
16193 as_tsktsk (MVE_BAD_SP
);
16194 else if (inst
.operands
[2].reg
== REG_PC
)
16195 first_error (BAD_PC
);
16197 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
16198 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
16199 Rm
= inst
.operands
[2].reg
>> 1;
16201 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16202 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16203 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16204 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16205 inst
.instruction
|= (imm
> 2) << 7;
16206 inst
.instruction
|= Rm
<< 1;
16207 inst
.instruction
|= (imm
== 2 || imm
== 8);
16212 do_mve_vmlas (void)
16214 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
16215 struct neon_type_el et
16216 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16218 if (inst
.operands
[2].reg
== REG_PC
)
16219 as_tsktsk (MVE_BAD_PC
);
16220 else if (inst
.operands
[2].reg
== REG_SP
)
16221 as_tsktsk (MVE_BAD_SP
);
16223 if (inst
.cond
> COND_ALWAYS
)
16224 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16226 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16228 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16229 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16230 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16231 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16232 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16233 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16234 inst
.instruction
|= inst
.operands
[2].reg
;
16239 do_mve_vshll (void)
16241 struct neon_type_el et
16242 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16244 if (inst
.cond
> COND_ALWAYS
)
16245 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16247 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16249 int imm
= inst
.operands
[2].imm
;
16250 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16251 _("immediate value out of range"));
16253 if ((unsigned)imm
== et
.size
)
16255 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16256 inst
.instruction
|= 0x110001;
16260 inst
.instruction
|= (et
.size
+ imm
) << 16;
16261 inst
.instruction
|= 0x800140;
16264 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16265 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16266 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16267 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16268 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16273 do_mve_vshlc (void)
16275 if (inst
.cond
> COND_ALWAYS
)
16276 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16278 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16280 if (inst
.operands
[1].reg
== REG_PC
)
16281 as_tsktsk (MVE_BAD_PC
);
16282 else if (inst
.operands
[1].reg
== REG_SP
)
16283 as_tsktsk (MVE_BAD_SP
);
16285 int imm
= inst
.operands
[2].imm
;
16286 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16288 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16289 inst
.instruction
|= (imm
& 0x1f) << 16;
16290 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16291 inst
.instruction
|= inst
.operands
[1].reg
;
16296 do_mve_vshrn (void)
16299 switch (inst
.instruction
)
16301 case M_MNEM_vshrnt
:
16302 case M_MNEM_vshrnb
:
16303 case M_MNEM_vrshrnt
:
16304 case M_MNEM_vrshrnb
:
16305 types
= N_I16
| N_I32
;
16307 case M_MNEM_vqshrnt
:
16308 case M_MNEM_vqshrnb
:
16309 case M_MNEM_vqrshrnt
:
16310 case M_MNEM_vqrshrnb
:
16311 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16313 case M_MNEM_vqshrunt
:
16314 case M_MNEM_vqshrunb
:
16315 case M_MNEM_vqrshrunt
:
16316 case M_MNEM_vqrshrunb
:
16317 types
= N_S16
| N_S32
;
16323 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16325 if (inst
.cond
> COND_ALWAYS
)
16326 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16328 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16330 unsigned Qd
= inst
.operands
[0].reg
;
16331 unsigned Qm
= inst
.operands
[1].reg
;
16332 unsigned imm
= inst
.operands
[2].imm
;
16333 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16335 ? _("immediate operand expected in the range [1,8]")
16336 : _("immediate operand expected in the range [1,16]"));
16338 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16339 inst
.instruction
|= HI1 (Qd
) << 22;
16340 inst
.instruction
|= (et
.size
- imm
) << 16;
16341 inst
.instruction
|= LOW4 (Qd
) << 12;
16342 inst
.instruction
|= HI1 (Qm
) << 5;
16343 inst
.instruction
|= LOW4 (Qm
);
16348 do_mve_vqmovn (void)
16350 struct neon_type_el et
;
16351 if (inst
.instruction
== M_MNEM_vqmovnt
16352 || inst
.instruction
== M_MNEM_vqmovnb
)
16353 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16354 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16356 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16358 if (inst
.cond
> COND_ALWAYS
)
16359 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16361 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16363 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16364 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16365 inst
.instruction
|= (et
.size
== 32) << 18;
16366 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16367 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16368 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16373 do_mve_vpsel (void)
16375 neon_select_shape (NS_QQQ
, NS_NULL
);
16377 if (inst
.cond
> COND_ALWAYS
)
16378 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16380 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16382 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16383 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16384 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16385 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16386 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16387 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16392 do_mve_vpnot (void)
16394 if (inst
.cond
> COND_ALWAYS
)
16395 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16397 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16401 do_mve_vmaxnma_vminnma (void)
16403 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16404 struct neon_type_el et
16405 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16407 if (inst
.cond
> COND_ALWAYS
)
16408 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16410 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16412 inst
.instruction
|= (et
.size
== 16) << 28;
16413 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16414 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16415 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16416 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16421 do_mve_vcmul (void)
16423 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16424 struct neon_type_el et
16425 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16427 if (inst
.cond
> COND_ALWAYS
)
16428 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16430 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16432 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16433 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16434 _("immediate out of range"));
16436 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16437 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16438 as_tsktsk (BAD_MVE_SRCDEST
);
16440 inst
.instruction
|= (et
.size
== 32) << 28;
16441 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16442 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16443 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16444 inst
.instruction
|= (rot
> 90) << 12;
16445 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16446 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16447 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16448 inst
.instruction
|= (rot
== 90 || rot
== 270);
16452 /* To handle the Low Overhead Loop instructions
16453 in Armv8.1-M Mainline and MVE. */
16457 unsigned long insn
= inst
.instruction
;
16459 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16461 if (insn
== T_MNEM_lctp
)
16464 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16466 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16468 struct neon_type_el et
16469 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16470 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16477 constraint (!inst
.operands
[0].present
,
16479 /* fall through. */
16482 if (!inst
.operands
[0].present
)
16483 inst
.instruction
|= 1 << 21;
16485 v8_1_loop_reloc (TRUE
);
16490 v8_1_loop_reloc (FALSE
);
16491 /* fall through. */
16494 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16496 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16497 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16498 else if (inst
.operands
[1].reg
== REG_PC
)
16499 as_tsktsk (MVE_BAD_PC
);
16500 if (inst
.operands
[1].reg
== REG_SP
)
16501 as_tsktsk (MVE_BAD_SP
);
16503 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16513 do_vfp_nsyn_cmp (void)
16515 enum neon_shape rs
;
16516 if (!inst
.operands
[0].isreg
)
16523 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16524 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16528 if (inst
.operands
[1].isreg
)
16530 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16531 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16533 if (rs
== NS_FF
|| rs
== NS_HH
)
16535 NEON_ENCODE (SINGLE
, inst
);
16536 do_vfp_sp_monadic ();
16540 NEON_ENCODE (DOUBLE
, inst
);
16541 do_vfp_dp_rd_rm ();
16546 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16547 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16549 switch (inst
.instruction
& 0x0fffffff)
16552 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16555 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16561 if (rs
== NS_FI
|| rs
== NS_HI
)
16563 NEON_ENCODE (SINGLE
, inst
);
16564 do_vfp_sp_compare_z ();
16568 NEON_ENCODE (DOUBLE
, inst
);
16572 do_vfp_cond_or_thumb ();
16574 /* ARMv8.2 fp16 instruction. */
16575 if (rs
== NS_HI
|| rs
== NS_HH
)
16576 do_scalar_fp16_v82_encode ();
16580 nsyn_insert_sp (void)
16582 inst
.operands
[1] = inst
.operands
[0];
16583 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16584 inst
.operands
[0].reg
= REG_SP
;
16585 inst
.operands
[0].isreg
= 1;
16586 inst
.operands
[0].writeback
= 1;
16587 inst
.operands
[0].present
= 1;
16590 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16591 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16594 neon_dp_fixup (struct arm_it
* insn
)
16596 unsigned int i
= insn
->instruction
;
16601 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16612 insn
->instruction
= i
;
16616 mve_encode_qqr (int size
, int U
, int fp
)
16618 if (inst
.operands
[2].reg
== REG_SP
)
16619 as_tsktsk (MVE_BAD_SP
);
16620 else if (inst
.operands
[2].reg
== REG_PC
)
16621 as_tsktsk (MVE_BAD_PC
);
16626 if (((unsigned)inst
.instruction
) == 0xd00)
16627 inst
.instruction
= 0xee300f40;
16629 else if (((unsigned)inst
.instruction
) == 0x200d00)
16630 inst
.instruction
= 0xee301f40;
16632 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16633 inst
.instruction
= 0xee310e60;
16635 /* Setting size which is 1 for F16 and 0 for F32. */
16636 inst
.instruction
|= (size
== 16) << 28;
16641 if (((unsigned)inst
.instruction
) == 0x800)
16642 inst
.instruction
= 0xee010f40;
16644 else if (((unsigned)inst
.instruction
) == 0x1000800)
16645 inst
.instruction
= 0xee011f40;
16647 else if (((unsigned)inst
.instruction
) == 0)
16648 inst
.instruction
= 0xee000f40;
16650 else if (((unsigned)inst
.instruction
) == 0x200)
16651 inst
.instruction
= 0xee001f40;
16653 else if (((unsigned)inst
.instruction
) == 0x900)
16654 inst
.instruction
= 0xee010e40;
16656 else if (((unsigned)inst
.instruction
) == 0x910)
16657 inst
.instruction
= 0xee011e60;
16659 else if (((unsigned)inst
.instruction
) == 0x10)
16660 inst
.instruction
= 0xee000f60;
16662 else if (((unsigned)inst
.instruction
) == 0x210)
16663 inst
.instruction
= 0xee001f60;
16665 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16666 inst
.instruction
= 0xee000e40;
16668 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16669 inst
.instruction
= 0xee010e60;
16671 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16672 inst
.instruction
= 0xfe010e60;
16675 inst
.instruction
|= U
<< 28;
16677 /* Setting bits for size. */
16678 inst
.instruction
|= neon_logbits (size
) << 20;
16680 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16681 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16682 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16683 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16684 inst
.instruction
|= inst
.operands
[2].reg
;
16689 mve_encode_rqq (unsigned bit28
, unsigned size
)
16691 inst
.instruction
|= bit28
<< 28;
16692 inst
.instruction
|= neon_logbits (size
) << 20;
16693 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16695 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16696 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16697 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16702 mve_encode_qqq (int ubit
, int size
)
16705 inst
.instruction
|= (ubit
!= 0) << 28;
16706 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16707 inst
.instruction
|= neon_logbits (size
) << 20;
16708 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16709 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16710 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16711 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16712 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16718 mve_encode_rq (unsigned bit28
, unsigned size
)
16720 inst
.instruction
|= bit28
<< 28;
16721 inst
.instruction
|= neon_logbits (size
) << 18;
16722 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16723 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16728 mve_encode_rrqq (unsigned U
, unsigned size
)
16730 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16732 inst
.instruction
|= U
<< 28;
16733 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16734 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16735 inst
.instruction
|= (size
== 32) << 16;
16736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16737 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16738 inst
.instruction
|= inst
.operands
[3].reg
;
16742 /* Helper function for neon_three_same handling the operands. */
16744 neon_three_args (int isquad
)
16746 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16747 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16748 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16749 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16750 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16751 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16752 inst
.instruction
|= (isquad
!= 0) << 6;
16756 /* Encode insns with bit pattern:
16758 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16759 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16761 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16762 different meaning for some instruction. */
16765 neon_three_same (int isquad
, int ubit
, int size
)
16767 neon_three_args (isquad
);
16768 inst
.instruction
|= (ubit
!= 0) << 24;
16770 inst
.instruction
|= neon_logbits (size
) << 20;
16772 neon_dp_fixup (&inst
);
16775 /* Encode instructions of the form:
16777 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16778 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16780 Don't write size if SIZE == -1. */
16783 neon_two_same (int qbit
, int ubit
, int size
)
16785 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16786 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16787 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16788 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16789 inst
.instruction
|= (qbit
!= 0) << 6;
16790 inst
.instruction
|= (ubit
!= 0) << 24;
16793 inst
.instruction
|= neon_logbits (size
) << 18;
16795 neon_dp_fixup (&inst
);
16798 enum vfp_or_neon_is_neon_bits
16801 NEON_CHECK_ARCH
= 2,
16802 NEON_CHECK_ARCH8
= 4
16805 /* Call this function if an instruction which may have belonged to the VFP or
16806 Neon instruction sets, but turned out to be a Neon instruction (due to the
16807 operand types involved, etc.). We have to check and/or fix-up a couple of
16810 - Make sure the user hasn't attempted to make a Neon instruction
16812 - Alter the value in the condition code field if necessary.
16813 - Make sure that the arch supports Neon instructions.
16815 Which of these operations take place depends on bits from enum
16816 vfp_or_neon_is_neon_bits.
16818 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16819 current instruction's condition is COND_ALWAYS, the condition field is
16820 changed to inst.uncond_value. This is necessary because instructions shared
16821 between VFP and Neon may be conditional for the VFP variants only, and the
16822 unconditional Neon version must have, e.g., 0xF in the condition field. */
16825 vfp_or_neon_is_neon (unsigned check
)
16827 /* Conditions are always legal in Thumb mode (IT blocks). */
16828 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16830 if (inst
.cond
!= COND_ALWAYS
)
16832 first_error (_(BAD_COND
));
16835 if (inst
.uncond_value
!= -1)
16836 inst
.instruction
|= inst
.uncond_value
<< 28;
16840 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16841 || ((check
& NEON_CHECK_ARCH8
)
16842 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16844 first_error (_(BAD_FPU
));
16852 /* Return TRUE if the SIMD instruction is available for the current
16853 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16854 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16855 vfp_or_neon_is_neon for the NEON specific checks. */
16858 check_simd_pred_availability (int fp
, unsigned check
)
16860 if (inst
.cond
> COND_ALWAYS
)
16862 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16864 inst
.error
= BAD_FPU
;
16867 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16869 else if (inst
.cond
< COND_ALWAYS
)
16871 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16872 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16873 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16878 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16879 && vfp_or_neon_is_neon (check
) == FAIL
)
16882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16883 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16888 /* Neon instruction encoders, in approximate order of appearance. */
16891 do_neon_dyadic_i_su (void)
16893 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16896 enum neon_shape rs
;
16897 struct neon_type_el et
;
16898 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16899 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16901 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16903 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16907 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16909 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16913 do_neon_dyadic_i64_su (void)
16915 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16917 enum neon_shape rs
;
16918 struct neon_type_el et
;
16919 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16921 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16922 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16926 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16927 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16930 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16932 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16936 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16939 unsigned size
= et
.size
>> 3;
16940 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16941 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16942 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16943 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16944 inst
.instruction
|= (isquad
!= 0) << 6;
16945 inst
.instruction
|= immbits
<< 16;
16946 inst
.instruction
|= (size
>> 3) << 7;
16947 inst
.instruction
|= (size
& 0x7) << 19;
16949 inst
.instruction
|= (uval
!= 0) << 24;
16951 neon_dp_fixup (&inst
);
16957 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16960 if (!inst
.operands
[2].isreg
)
16962 enum neon_shape rs
;
16963 struct neon_type_el et
;
16964 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16966 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16967 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16971 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16972 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16974 int imm
= inst
.operands
[2].imm
;
16976 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16977 _("immediate out of range for shift"));
16978 NEON_ENCODE (IMMED
, inst
);
16979 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16983 enum neon_shape rs
;
16984 struct neon_type_el et
;
16985 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16987 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16988 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16992 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16993 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16999 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17000 _("invalid instruction shape"));
17001 if (inst
.operands
[2].reg
== REG_SP
)
17002 as_tsktsk (MVE_BAD_SP
);
17003 else if (inst
.operands
[2].reg
== REG_PC
)
17004 as_tsktsk (MVE_BAD_PC
);
17006 inst
.instruction
= 0xee311e60;
17007 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17008 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17009 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17010 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17011 inst
.instruction
|= inst
.operands
[2].reg
;
17018 /* VSHL/VQSHL 3-register variants have syntax such as:
17020 whereas other 3-register operations encoded by neon_three_same have
17023 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
17024 operands[2].reg here. */
17025 tmp
= inst
.operands
[2].reg
;
17026 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17027 inst
.operands
[1].reg
= tmp
;
17028 NEON_ENCODE (INTEGER
, inst
);
17029 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17035 do_neon_qshl (void)
17037 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17040 if (!inst
.operands
[2].isreg
)
17042 enum neon_shape rs
;
17043 struct neon_type_el et
;
17044 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17046 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
17047 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
17051 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17052 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
17054 int imm
= inst
.operands
[2].imm
;
17056 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
17057 _("immediate out of range for shift"));
17058 NEON_ENCODE (IMMED
, inst
);
17059 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
17063 enum neon_shape rs
;
17064 struct neon_type_el et
;
17066 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17068 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17069 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
17073 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17074 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
17079 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17080 _("invalid instruction shape"));
17081 if (inst
.operands
[2].reg
== REG_SP
)
17082 as_tsktsk (MVE_BAD_SP
);
17083 else if (inst
.operands
[2].reg
== REG_PC
)
17084 as_tsktsk (MVE_BAD_PC
);
17086 inst
.instruction
= 0xee311ee0;
17087 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17088 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17089 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17090 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17091 inst
.instruction
|= inst
.operands
[2].reg
;
17098 /* See note in do_neon_shl. */
17099 tmp
= inst
.operands
[2].reg
;
17100 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17101 inst
.operands
[1].reg
= tmp
;
17102 NEON_ENCODE (INTEGER
, inst
);
17103 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17109 do_neon_rshl (void)
17111 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17114 enum neon_shape rs
;
17115 struct neon_type_el et
;
17116 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17118 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17119 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17123 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17124 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
17131 if (inst
.operands
[2].reg
== REG_PC
)
17132 as_tsktsk (MVE_BAD_PC
);
17133 else if (inst
.operands
[2].reg
== REG_SP
)
17134 as_tsktsk (MVE_BAD_SP
);
17136 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17137 _("invalid instruction shape"));
17139 if (inst
.instruction
== 0x0000510)
17140 /* We are dealing with vqrshl. */
17141 inst
.instruction
= 0xee331ee0;
17143 /* We are dealing with vrshl. */
17144 inst
.instruction
= 0xee331e60;
17146 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17147 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17148 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17149 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17150 inst
.instruction
|= inst
.operands
[2].reg
;
17155 tmp
= inst
.operands
[2].reg
;
17156 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
17157 inst
.operands
[1].reg
= tmp
;
17158 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
17163 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
17165 /* Handle .I8 pseudo-instructions. */
17168 /* Unfortunately, this will make everything apart from zero out-of-range.
17169 FIXME is this the intended semantics? There doesn't seem much point in
17170 accepting .I8 if so. */
17171 immediate
|= immediate
<< 8;
17177 if (immediate
== (immediate
& 0x000000ff))
17179 *immbits
= immediate
;
17182 else if (immediate
== (immediate
& 0x0000ff00))
17184 *immbits
= immediate
>> 8;
17187 else if (immediate
== (immediate
& 0x00ff0000))
17189 *immbits
= immediate
>> 16;
17192 else if (immediate
== (immediate
& 0xff000000))
17194 *immbits
= immediate
>> 24;
17197 if ((immediate
& 0xffff) != (immediate
>> 16))
17198 goto bad_immediate
;
17199 immediate
&= 0xffff;
17202 if (immediate
== (immediate
& 0x000000ff))
17204 *immbits
= immediate
;
17207 else if (immediate
== (immediate
& 0x0000ff00))
17209 *immbits
= immediate
>> 8;
17214 first_error (_("immediate value out of range"));
17219 do_neon_logic (void)
17221 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17223 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17225 && !check_simd_pred_availability (FALSE
,
17226 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17228 else if (rs
!= NS_QQQ
17229 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17230 first_error (BAD_FPU
);
17232 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17233 /* U bit and size field were set as part of the bitmask. */
17234 NEON_ENCODE (INTEGER
, inst
);
17235 neon_three_same (neon_quad (rs
), 0, -1);
17239 const int three_ops_form
= (inst
.operands
[2].present
17240 && !inst
.operands
[2].isreg
);
17241 const int immoperand
= (three_ops_form
? 2 : 1);
17242 enum neon_shape rs
= (three_ops_form
17243 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17244 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17245 /* Because neon_select_shape makes the second operand a copy of the first
17246 if the second operand is not present. */
17248 && !check_simd_pred_availability (FALSE
,
17249 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17251 else if (rs
!= NS_QQI
17252 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17253 first_error (BAD_FPU
);
17255 struct neon_type_el et
;
17256 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17257 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17259 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17262 if (et
.type
== NT_invtype
)
17264 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17269 if (three_ops_form
)
17270 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17271 _("first and second operands shall be the same register"));
17273 NEON_ENCODE (IMMED
, inst
);
17275 immbits
= inst
.operands
[immoperand
].imm
;
17278 /* .i64 is a pseudo-op, so the immediate must be a repeating
17280 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17281 inst
.operands
[immoperand
].reg
: 0))
17283 /* Set immbits to an invalid constant. */
17284 immbits
= 0xdeadbeef;
17291 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17295 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17299 /* Pseudo-instruction for VBIC. */
17300 neon_invert_size (&immbits
, 0, et
.size
);
17301 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17305 /* Pseudo-instruction for VORR. */
17306 neon_invert_size (&immbits
, 0, et
.size
);
17307 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17317 inst
.instruction
|= neon_quad (rs
) << 6;
17318 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17319 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17320 inst
.instruction
|= cmode
<< 8;
17321 neon_write_immbits (immbits
);
17323 neon_dp_fixup (&inst
);
17328 do_neon_bitfield (void)
17330 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17331 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17332 neon_three_same (neon_quad (rs
), 0, -1);
17336 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17339 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17340 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17342 if (et
.type
== NT_float
)
17344 NEON_ENCODE (FLOAT
, inst
);
17346 mve_encode_qqr (et
.size
, 0, 1);
17348 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17352 NEON_ENCODE (INTEGER
, inst
);
17354 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17356 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17362 do_neon_dyadic_if_su_d (void)
17364 /* This version only allow D registers, but that constraint is enforced during
17365 operand parsing so we don't need to do anything extra here. */
17366 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17370 do_neon_dyadic_if_i_d (void)
17372 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17373 affected if we specify unsigned args. */
17374 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17378 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17380 constraint (size
< 32, BAD_ADDR_MODE
);
17381 constraint (size
!= elsize
, BAD_EL_TYPE
);
17382 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17383 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17384 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17385 _("destination register and offset register may not be the"
17388 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17395 constraint ((imm
% (size
/ 8) != 0)
17396 || imm
> (0x7f << neon_logbits (size
)),
17397 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17398 " range of +/-[0,508]")
17399 : _("immediate must be a multiple of 8 in the"
17400 " range of +/-[0,1016]"));
17401 inst
.instruction
|= 0x11 << 24;
17402 inst
.instruction
|= add
<< 23;
17403 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17404 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17405 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17406 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17407 inst
.instruction
|= 1 << 12;
17408 inst
.instruction
|= (size
== 64) << 8;
17409 inst
.instruction
&= 0xffffff00;
17410 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17411 inst
.instruction
|= imm
>> neon_logbits (size
);
17415 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17417 unsigned os
= inst
.operands
[1].imm
>> 5;
17418 unsigned type
= inst
.vectype
.el
[0].type
;
17419 constraint (os
!= 0 && size
== 8,
17420 _("can not shift offsets when accessing less than half-word"));
17421 constraint (os
&& os
!= neon_logbits (size
),
17422 _("shift immediate must be 1, 2 or 3 for half-word, word"
17423 " or double-word accesses respectively"));
17424 if (inst
.operands
[1].reg
== REG_PC
)
17425 as_tsktsk (MVE_BAD_PC
);
17430 constraint (elsize
>= 64, BAD_EL_TYPE
);
17433 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17437 constraint (elsize
!= size
, BAD_EL_TYPE
);
17442 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17446 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17447 _("destination register and offset register may not be"
17449 constraint (size
== elsize
&& type
== NT_signed
, BAD_EL_TYPE
);
17450 constraint (size
!= elsize
&& type
!= NT_unsigned
&& type
!= NT_signed
,
17452 inst
.instruction
|= ((size
== elsize
) || (type
== NT_unsigned
)) << 28;
17456 constraint (type
!= NT_untyped
, BAD_EL_TYPE
);
17459 inst
.instruction
|= 1 << 23;
17460 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17461 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17462 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17463 inst
.instruction
|= neon_logbits (elsize
) << 7;
17464 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17465 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17466 inst
.instruction
|= !!os
;
17470 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17472 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17474 constraint (size
>= 64, BAD_ADDR_MODE
);
17478 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17481 constraint (elsize
!= size
, BAD_EL_TYPE
);
17488 constraint (elsize
!= size
&& type
!= NT_unsigned
17489 && type
!= NT_signed
, BAD_EL_TYPE
);
17493 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17496 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17504 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17509 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17512 constraint (1, _("immediate must be a multiple of 2 in the"
17513 " range of +/-[0,254]"));
17516 constraint (1, _("immediate must be a multiple of 4 in the"
17517 " range of +/-[0,508]"));
17522 if (size
!= elsize
)
17524 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17525 constraint (inst
.operands
[0].reg
> 14,
17526 _("MVE vector register in the range [Q0..Q7] expected"));
17527 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17528 inst
.instruction
|= (size
== 16) << 19;
17529 inst
.instruction
|= neon_logbits (elsize
) << 7;
17533 if (inst
.operands
[1].reg
== REG_PC
)
17534 as_tsktsk (MVE_BAD_PC
);
17535 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17536 as_tsktsk (MVE_BAD_SP
);
17537 inst
.instruction
|= 1 << 12;
17538 inst
.instruction
|= neon_logbits (size
) << 7;
17540 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17541 inst
.instruction
|= add
<< 23;
17542 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17543 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17544 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17545 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17546 inst
.instruction
&= 0xffffff80;
17547 inst
.instruction
|= imm
>> neon_logbits (size
);
17552 do_mve_vstr_vldr (void)
17557 if (inst
.cond
> COND_ALWAYS
)
17558 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17560 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17562 switch (inst
.instruction
)
17569 /* fall through. */
17575 /* fall through. */
17581 /* fall through. */
17587 /* fall through. */
17592 unsigned elsize
= inst
.vectype
.el
[0].size
;
17594 if (inst
.operands
[1].isquad
)
17596 /* We are dealing with [Q, imm]{!} cases. */
17597 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17601 if (inst
.operands
[1].immisreg
== 2)
17603 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17604 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17606 else if (!inst
.operands
[1].immisreg
)
17608 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17609 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17612 constraint (1, BAD_ADDR_MODE
);
17619 do_mve_vst_vld (void)
17621 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17624 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17625 || inst
.relocs
[0].exp
.X_add_number
!= 0
17626 || inst
.operands
[1].immisreg
!= 0,
17628 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17629 if (inst
.operands
[1].reg
== REG_PC
)
17630 as_tsktsk (MVE_BAD_PC
);
17631 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17632 as_tsktsk (MVE_BAD_SP
);
17635 /* These instructions are one of the "exceptions" mentioned in
17636 handle_pred_state. They are MVE instructions that are not VPT compatible
17637 and do not accept a VPT code, thus appending such a code is a syntax
17639 if (inst
.cond
> COND_ALWAYS
)
17640 first_error (BAD_SYNTAX
);
17641 /* If we append a scalar condition code we can set this to
17642 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17643 else if (inst
.cond
< COND_ALWAYS
)
17644 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17646 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17648 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17649 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17650 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17651 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17652 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17657 do_mve_vaddlv (void)
17659 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17660 struct neon_type_el et
17661 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17663 if (et
.type
== NT_invtype
)
17664 first_error (BAD_EL_TYPE
);
17666 if (inst
.cond
> COND_ALWAYS
)
17667 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17669 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17671 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17673 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17674 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17675 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17676 inst
.instruction
|= inst
.operands
[2].reg
;
17681 do_neon_dyadic_if_su (void)
17683 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17684 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17687 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17688 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17689 && et
.type
== NT_float
17690 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17692 if (!check_simd_pred_availability (et
.type
== NT_float
,
17693 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17696 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17700 do_neon_addsub_if_i (void)
17702 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17703 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17706 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17707 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17708 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17710 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17711 /* If we are parsing Q registers and the element types match MVE, which NEON
17712 also supports, then we must check whether this is an instruction that can
17713 be used by both MVE/NEON. This distinction can be made based on whether
17714 they are predicated or not. */
17715 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17717 if (!check_simd_pred_availability (et
.type
== NT_float
,
17718 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17723 /* If they are either in a D register or are using an unsupported. */
17725 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17729 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17730 affected if we specify unsigned args. */
17731 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17734 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17736 V<op> A,B (A is operand 0, B is operand 2)
17741 so handle that case specially. */
17744 neon_exchange_operands (void)
17746 if (inst
.operands
[1].present
)
17748 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17750 /* Swap operands[1] and operands[2]. */
17751 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17752 inst
.operands
[1] = inst
.operands
[2];
17753 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17758 inst
.operands
[1] = inst
.operands
[2];
17759 inst
.operands
[2] = inst
.operands
[0];
17764 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17766 if (inst
.operands
[2].isreg
)
17769 neon_exchange_operands ();
17770 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17774 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17775 struct neon_type_el et
= neon_check_type (2, rs
,
17776 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17778 NEON_ENCODE (IMMED
, inst
);
17779 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17780 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17781 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17782 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17783 inst
.instruction
|= neon_quad (rs
) << 6;
17784 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17785 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17787 neon_dp_fixup (&inst
);
17794 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17798 do_neon_cmp_inv (void)
17800 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17806 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17809 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17810 scalars, which are encoded in 5 bits, M : Rm.
17811 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17812 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17815 Dot Product instructions are similar to multiply instructions except elsize
17816 should always be 32.
17818 This function translates SCALAR, which is GAS's internal encoding of indexed
17819 scalar register, to raw encoding. There is also register and index range
17820 check based on ELSIZE. */
17823 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17825 unsigned regno
= NEON_SCALAR_REG (scalar
);
17826 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17831 if (regno
> 7 || elno
> 3)
17833 return regno
| (elno
<< 3);
17836 if (regno
> 15 || elno
> 1)
17838 return regno
| (elno
<< 4);
17842 first_error (_("scalar out of range for multiply instruction"));
17848 /* Encode multiply / multiply-accumulate scalar instructions. */
17851 neon_mul_mac (struct neon_type_el et
, int ubit
)
17855 /* Give a more helpful error message if we have an invalid type. */
17856 if (et
.type
== NT_invtype
)
17859 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17860 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17861 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17862 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17863 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17864 inst
.instruction
|= LOW4 (scalar
);
17865 inst
.instruction
|= HI1 (scalar
) << 5;
17866 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17867 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17868 inst
.instruction
|= (ubit
!= 0) << 24;
17870 neon_dp_fixup (&inst
);
17874 do_neon_mac_maybe_scalar (void)
17876 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17879 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17882 if (inst
.operands
[2].isscalar
)
17884 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17885 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17886 struct neon_type_el et
= neon_check_type (3, rs
,
17887 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17888 NEON_ENCODE (SCALAR
, inst
);
17889 neon_mul_mac (et
, neon_quad (rs
));
17891 else if (!inst
.operands
[2].isvec
)
17893 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17895 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17896 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17898 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17902 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17903 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17904 affected if we specify unsigned args. */
17905 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17910 do_bfloat_vfma (void)
17912 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
17913 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
17914 enum neon_shape rs
;
17917 if (inst
.instruction
!= B_MNEM_vfmab
)
17920 inst
.instruction
= B_MNEM_vfmat
;
17923 if (inst
.operands
[2].isscalar
)
17925 rs
= neon_select_shape (NS_QQS
, NS_NULL
);
17926 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17928 inst
.instruction
|= (1 << 25);
17929 int index
= inst
.operands
[2].reg
& 0xf;
17930 constraint (!(index
< 4), _("index must be in the range 0 to 3"));
17931 inst
.operands
[2].reg
>>= 4;
17932 constraint (!(inst
.operands
[2].reg
< 8),
17933 _("indexed register must be less than 8"));
17934 neon_three_args (t_bit
);
17935 inst
.instruction
|= ((index
& 1) << 3);
17936 inst
.instruction
|= ((index
& 2) << 4);
17940 rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17941 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
17942 neon_three_args (t_bit
);
17948 do_neon_fmac (void)
17950 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17951 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17954 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17957 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17959 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17960 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17966 if (inst
.operands
[2].reg
== REG_SP
)
17967 as_tsktsk (MVE_BAD_SP
);
17968 else if (inst
.operands
[2].reg
== REG_PC
)
17969 as_tsktsk (MVE_BAD_PC
);
17971 inst
.instruction
= 0xee310e40;
17972 inst
.instruction
|= (et
.size
== 16) << 28;
17973 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17974 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17975 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17976 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17977 inst
.instruction
|= inst
.operands
[2].reg
;
17984 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17987 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17993 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_bf16
) &&
17994 inst
.cond
== COND_ALWAYS
)
17996 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17997 inst
.instruction
= N_MNEM_vfma
;
17998 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18000 return do_neon_fmac();
18011 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18012 struct neon_type_el et
= neon_check_type (3, rs
,
18013 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18014 neon_three_same (neon_quad (rs
), 0, et
.size
);
18017 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
18018 same types as the MAC equivalents. The polynomial type for this instruction
18019 is encoded the same as the integer type. */
18024 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
18027 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18030 if (inst
.operands
[2].isscalar
)
18032 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18033 do_neon_mac_maybe_scalar ();
18037 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18039 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18040 struct neon_type_el et
18041 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
18042 if (et
.type
== NT_float
)
18043 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
18046 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
18050 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
18051 neon_dyadic_misc (NT_poly
,
18052 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
18058 do_neon_qdmulh (void)
18060 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18063 if (inst
.operands
[2].isscalar
)
18065 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
18066 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18067 struct neon_type_el et
= neon_check_type (3, rs
,
18068 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18069 NEON_ENCODE (SCALAR
, inst
);
18070 neon_mul_mac (et
, neon_quad (rs
));
18074 enum neon_shape rs
;
18075 struct neon_type_el et
;
18076 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18078 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
18079 et
= neon_check_type (3, rs
,
18080 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18084 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18085 et
= neon_check_type (3, rs
,
18086 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18089 NEON_ENCODE (INTEGER
, inst
);
18091 mve_encode_qqr (et
.size
, 0, 0);
18093 /* The U bit (rounding) comes from bit mask. */
18094 neon_three_same (neon_quad (rs
), 0, et
.size
);
18099 do_mve_vaddv (void)
18101 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18102 struct neon_type_el et
18103 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
18105 if (et
.type
== NT_invtype
)
18106 first_error (BAD_EL_TYPE
);
18108 if (inst
.cond
> COND_ALWAYS
)
18109 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18111 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18113 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
18115 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18119 do_mve_vhcadd (void)
18121 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
18122 struct neon_type_el et
18123 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18125 if (inst
.cond
> COND_ALWAYS
)
18126 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18128 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18130 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
18131 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
18133 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
18134 as_tsktsk (_("Warning: 32-bit element size and same first and third "
18135 "operand makes instruction UNPREDICTABLE"));
18137 mve_encode_qqq (0, et
.size
);
18138 inst
.instruction
|= (rot
== 270) << 12;
18143 do_mve_vqdmull (void)
18145 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
18146 struct neon_type_el et
18147 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18150 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18151 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
18152 as_tsktsk (BAD_MVE_SRCDEST
);
18154 if (inst
.cond
> COND_ALWAYS
)
18155 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18157 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18161 mve_encode_qqq (et
.size
== 32, 64);
18162 inst
.instruction
|= 1;
18166 mve_encode_qqr (64, et
.size
== 32, 0);
18167 inst
.instruction
|= 0x3 << 5;
18174 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18175 struct neon_type_el et
18176 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
18178 if (et
.type
== NT_invtype
)
18179 first_error (BAD_EL_TYPE
);
18181 if (inst
.cond
> COND_ALWAYS
)
18182 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18184 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18186 mve_encode_qqq (0, 64);
18190 do_mve_vbrsr (void)
18192 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18193 struct neon_type_el et
18194 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18196 if (inst
.cond
> COND_ALWAYS
)
18197 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18199 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18201 mve_encode_qqr (et
.size
, 0, 0);
18207 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
18209 if (inst
.cond
> COND_ALWAYS
)
18210 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18212 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18214 mve_encode_qqq (1, 64);
18218 do_mve_vmulh (void)
18220 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18221 struct neon_type_el et
18222 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18224 if (inst
.cond
> COND_ALWAYS
)
18225 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18227 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18229 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18233 do_mve_vqdmlah (void)
18235 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18236 struct neon_type_el et
18237 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18239 if (inst
.cond
> COND_ALWAYS
)
18240 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18242 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18244 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18248 do_mve_vqdmladh (void)
18250 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
18251 struct neon_type_el et
18252 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18254 if (inst
.cond
> COND_ALWAYS
)
18255 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18257 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18259 mve_encode_qqq (0, et
.size
);
18264 do_mve_vmull (void)
18267 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18268 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18269 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18270 && inst
.cond
== COND_ALWAYS
18271 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18276 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18277 N_SUF_32
| N_F64
| N_P8
18278 | N_P16
| N_I_MVE
| N_KEY
);
18279 if (((et
.type
== NT_poly
) && et
.size
== 8
18280 && ARM_CPU_IS_ANY (cpu_variant
))
18281 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18288 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18289 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18290 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18292 /* We are dealing with MVE's vmullt. */
18294 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18295 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18296 as_tsktsk (BAD_MVE_SRCDEST
);
18298 if (inst
.cond
> COND_ALWAYS
)
18299 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18301 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18303 if (et
.type
== NT_poly
)
18304 mve_encode_qqq (neon_logbits (et
.size
), 64);
18306 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18311 inst
.instruction
= N_MNEM_vmul
;
18314 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18319 do_mve_vabav (void)
18321 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18326 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18329 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18330 | N_S16
| N_S32
| N_U8
| N_U16
18333 if (inst
.cond
> COND_ALWAYS
)
18334 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18336 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18338 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18342 do_mve_vmladav (void)
18344 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18345 struct neon_type_el et
= neon_check_type (3, rs
,
18346 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18348 if (et
.type
== NT_unsigned
18349 && (inst
.instruction
== M_MNEM_vmladavx
18350 || inst
.instruction
== M_MNEM_vmladavax
18351 || inst
.instruction
== M_MNEM_vmlsdav
18352 || inst
.instruction
== M_MNEM_vmlsdava
18353 || inst
.instruction
== M_MNEM_vmlsdavx
18354 || inst
.instruction
== M_MNEM_vmlsdavax
))
18355 first_error (BAD_SIMD_TYPE
);
18357 constraint (inst
.operands
[2].reg
> 14,
18358 _("MVE vector register in the range [Q0..Q7] expected"));
18360 if (inst
.cond
> COND_ALWAYS
)
18361 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18363 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18365 if (inst
.instruction
== M_MNEM_vmlsdav
18366 || inst
.instruction
== M_MNEM_vmlsdava
18367 || inst
.instruction
== M_MNEM_vmlsdavx
18368 || inst
.instruction
== M_MNEM_vmlsdavax
)
18369 inst
.instruction
|= (et
.size
== 8) << 28;
18371 inst
.instruction
|= (et
.size
== 8) << 8;
18373 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18374 inst
.instruction
|= (et
.size
== 32) << 16;
18378 do_mve_vmlaldav (void)
18380 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18381 struct neon_type_el et
18382 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18383 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18385 if (et
.type
== NT_unsigned
18386 && (inst
.instruction
== M_MNEM_vmlsldav
18387 || inst
.instruction
== M_MNEM_vmlsldava
18388 || inst
.instruction
== M_MNEM_vmlsldavx
18389 || inst
.instruction
== M_MNEM_vmlsldavax
))
18390 first_error (BAD_SIMD_TYPE
);
18392 if (inst
.cond
> COND_ALWAYS
)
18393 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18395 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18397 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18401 do_mve_vrmlaldavh (void)
18403 struct neon_type_el et
;
18404 if (inst
.instruction
== M_MNEM_vrmlsldavh
18405 || inst
.instruction
== M_MNEM_vrmlsldavha
18406 || inst
.instruction
== M_MNEM_vrmlsldavhx
18407 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18409 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18410 if (inst
.operands
[1].reg
== REG_SP
)
18411 as_tsktsk (MVE_BAD_SP
);
18415 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18416 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18417 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18419 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18420 N_U32
| N_S32
| N_KEY
);
18421 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18422 with vmax/min instructions, making the use of SP in assembly really
18423 nonsensical, so instead of issuing a warning like we do for other uses
18424 of SP for the odd register operand we error out. */
18425 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18428 /* Make sure we still check the second operand is an odd one and that PC is
18429 disallowed. This because we are parsing for any GPR operand, to be able
18430 to distinguish between giving a warning or an error for SP as described
18432 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18433 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18435 if (inst
.cond
> COND_ALWAYS
)
18436 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18438 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18440 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18445 do_mve_vmaxnmv (void)
18447 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18448 struct neon_type_el et
18449 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18451 if (inst
.cond
> COND_ALWAYS
)
18452 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18454 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18456 if (inst
.operands
[0].reg
== REG_SP
)
18457 as_tsktsk (MVE_BAD_SP
);
18458 else if (inst
.operands
[0].reg
== REG_PC
)
18459 as_tsktsk (MVE_BAD_PC
);
18461 mve_encode_rq (et
.size
== 16, 64);
18465 do_mve_vmaxv (void)
18467 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18468 struct neon_type_el et
;
18470 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18471 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18473 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18475 if (inst
.cond
> COND_ALWAYS
)
18476 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18478 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18480 if (inst
.operands
[0].reg
== REG_SP
)
18481 as_tsktsk (MVE_BAD_SP
);
18482 else if (inst
.operands
[0].reg
== REG_PC
)
18483 as_tsktsk (MVE_BAD_PC
);
18485 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18490 do_neon_qrdmlah (void)
18492 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18494 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18496 /* Check we're on the correct architecture. */
18497 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18499 = _("instruction form not available on this architecture.");
18500 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18502 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18503 record_feature_use (&fpu_neon_ext_v8_1
);
18505 if (inst
.operands
[2].isscalar
)
18507 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18508 struct neon_type_el et
= neon_check_type (3, rs
,
18509 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18510 NEON_ENCODE (SCALAR
, inst
);
18511 neon_mul_mac (et
, neon_quad (rs
));
18515 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18516 struct neon_type_el et
= neon_check_type (3, rs
,
18517 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18518 NEON_ENCODE (INTEGER
, inst
);
18519 /* The U bit (rounding) comes from bit mask. */
18520 neon_three_same (neon_quad (rs
), 0, et
.size
);
18525 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18526 struct neon_type_el et
18527 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18529 NEON_ENCODE (INTEGER
, inst
);
18530 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18535 do_neon_fcmp_absolute (void)
18537 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18538 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18539 N_F_16_32
| N_KEY
);
18540 /* Size field comes from bit mask. */
18541 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18545 do_neon_fcmp_absolute_inv (void)
18547 neon_exchange_operands ();
18548 do_neon_fcmp_absolute ();
18552 do_neon_step (void)
18554 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18555 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18556 N_F_16_32
| N_KEY
);
18557 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18561 do_neon_abs_neg (void)
18563 enum neon_shape rs
;
18564 struct neon_type_el et
;
18566 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18569 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18570 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18572 if (!check_simd_pred_availability (et
.type
== NT_float
,
18573 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18576 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18577 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18578 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18579 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18580 inst
.instruction
|= neon_quad (rs
) << 6;
18581 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18582 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18584 neon_dp_fixup (&inst
);
18590 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18593 enum neon_shape rs
;
18594 struct neon_type_el et
;
18595 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18597 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18598 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18602 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18603 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18607 int imm
= inst
.operands
[2].imm
;
18608 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18609 _("immediate out of range for insert"));
18610 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18616 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18619 enum neon_shape rs
;
18620 struct neon_type_el et
;
18621 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18623 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18624 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18628 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18629 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18632 int imm
= inst
.operands
[2].imm
;
18633 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18634 _("immediate out of range for insert"));
18635 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18639 do_neon_qshlu_imm (void)
18641 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18644 enum neon_shape rs
;
18645 struct neon_type_el et
;
18646 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18648 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18649 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18653 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18654 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18655 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18658 int imm
= inst
.operands
[2].imm
;
18659 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18660 _("immediate out of range for shift"));
18661 /* Only encodes the 'U present' variant of the instruction.
18662 In this case, signed types have OP (bit 8) set to 0.
18663 Unsigned types have OP set to 1. */
18664 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18665 /* The rest of the bits are the same as other immediate shifts. */
18666 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18670 do_neon_qmovn (void)
18672 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18673 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18674 /* Saturating move where operands can be signed or unsigned, and the
18675 destination has the same signedness. */
18676 NEON_ENCODE (INTEGER
, inst
);
18677 if (et
.type
== NT_unsigned
)
18678 inst
.instruction
|= 0xc0;
18680 inst
.instruction
|= 0x80;
18681 neon_two_same (0, 1, et
.size
/ 2);
18685 do_neon_qmovun (void)
18687 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18688 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18689 /* Saturating move with unsigned results. Operands must be signed. */
18690 NEON_ENCODE (INTEGER
, inst
);
18691 neon_two_same (0, 1, et
.size
/ 2);
18695 do_neon_rshift_sat_narrow (void)
18697 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18698 or unsigned. If operands are unsigned, results must also be unsigned. */
18699 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18700 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18701 int imm
= inst
.operands
[2].imm
;
18702 /* This gets the bounds check, size encoding and immediate bits calculation
18706 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18707 VQMOVN.I<size> <Dd>, <Qm>. */
18710 inst
.operands
[2].present
= 0;
18711 inst
.instruction
= N_MNEM_vqmovn
;
18716 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18717 _("immediate out of range"));
18718 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18722 do_neon_rshift_sat_narrow_u (void)
18724 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18725 or unsigned. If operands are unsigned, results must also be unsigned. */
18726 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18727 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18728 int imm
= inst
.operands
[2].imm
;
18729 /* This gets the bounds check, size encoding and immediate bits calculation
18733 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18734 VQMOVUN.I<size> <Dd>, <Qm>. */
18737 inst
.operands
[2].present
= 0;
18738 inst
.instruction
= N_MNEM_vqmovun
;
18743 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18744 _("immediate out of range"));
18745 /* FIXME: The manual is kind of unclear about what value U should have in
18746 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18748 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18752 do_neon_movn (void)
18754 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18755 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18756 NEON_ENCODE (INTEGER
, inst
);
18757 neon_two_same (0, 1, et
.size
/ 2);
18761 do_neon_rshift_narrow (void)
18763 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18764 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18765 int imm
= inst
.operands
[2].imm
;
18766 /* This gets the bounds check, size encoding and immediate bits calculation
18770 /* If immediate is zero then we are a pseudo-instruction for
18771 VMOVN.I<size> <Dd>, <Qm> */
18774 inst
.operands
[2].present
= 0;
18775 inst
.instruction
= N_MNEM_vmovn
;
18780 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18781 _("immediate out of range for narrowing operation"));
18782 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18786 do_neon_shll (void)
18788 /* FIXME: Type checking when lengthening. */
18789 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18790 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18791 unsigned imm
= inst
.operands
[2].imm
;
18793 if (imm
== et
.size
)
18795 /* Maximum shift variant. */
18796 NEON_ENCODE (INTEGER
, inst
);
18797 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18798 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18799 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18800 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18801 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18803 neon_dp_fixup (&inst
);
18807 /* A more-specific type check for non-max versions. */
18808 et
= neon_check_type (2, NS_QDI
,
18809 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18810 NEON_ENCODE (IMMED
, inst
);
18811 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18815 /* Check the various types for the VCVT instruction, and return which version
18816 the current instruction is. */
18818 #define CVT_FLAVOUR_VAR \
18819 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18820 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18821 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18822 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18823 /* Half-precision conversions. */ \
18824 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18825 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18826 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18827 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18828 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18829 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18830 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18831 Compared with single/double precision variants, only the co-processor \
18832 field is different, so the encoding flow is reused here. */ \
18833 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18834 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18835 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18836 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18837 CVT_VAR (bf16_f32, N_BF16, N_F32, whole_reg, NULL, NULL, NULL) \
18838 /* VFP instructions. */ \
18839 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18840 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18841 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18842 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18843 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18844 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18845 /* VFP instructions with bitshift. */ \
18846 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18847 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18848 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18849 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18850 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18851 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18852 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18853 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18855 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18856 neon_cvt_flavour_##C,
18858 /* The different types of conversions we can do. */
18859 enum neon_cvt_flavour
18862 neon_cvt_flavour_invalid
,
18863 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18868 static enum neon_cvt_flavour
18869 get_neon_cvt_flavour (enum neon_shape rs
)
18871 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18872 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18873 if (et.type != NT_invtype) \
18875 inst.error = NULL; \
18876 return (neon_cvt_flavour_##C); \
18879 struct neon_type_el et
;
18880 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18881 || rs
== NS_FF
) ? N_VFP
: 0;
18882 /* The instruction versions which take an immediate take one register
18883 argument, which is extended to the width of the full register. Thus the
18884 "source" and "destination" registers must have the same width. Hack that
18885 here by making the size equal to the key (wider, in this case) operand. */
18886 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18890 return neon_cvt_flavour_invalid
;
18905 /* Neon-syntax VFP conversions. */
18908 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18910 const char *opname
= 0;
18912 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18913 || rs
== NS_FHI
|| rs
== NS_HFI
)
18915 /* Conversions with immediate bitshift. */
18916 const char *enc
[] =
18918 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18924 if (flavour
< (int) ARRAY_SIZE (enc
))
18926 opname
= enc
[flavour
];
18927 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18928 _("operands 0 and 1 must be the same register"));
18929 inst
.operands
[1] = inst
.operands
[2];
18930 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18935 /* Conversions without bitshift. */
18936 const char *enc
[] =
18938 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18944 if (flavour
< (int) ARRAY_SIZE (enc
))
18945 opname
= enc
[flavour
];
18949 do_vfp_nsyn_opcode (opname
);
18951 /* ARMv8.2 fp16 VCVT instruction. */
18952 if (flavour
== neon_cvt_flavour_s32_f16
18953 || flavour
== neon_cvt_flavour_u32_f16
18954 || flavour
== neon_cvt_flavour_f16_u32
18955 || flavour
== neon_cvt_flavour_f16_s32
)
18956 do_scalar_fp16_v82_encode ();
18960 do_vfp_nsyn_cvtz (void)
18962 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18963 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18964 const char *enc
[] =
18966 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18972 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18973 do_vfp_nsyn_opcode (enc
[flavour
]);
18977 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18978 enum neon_cvt_mode mode
)
18983 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18984 D register operands. */
18985 if (flavour
== neon_cvt_flavour_s32_f64
18986 || flavour
== neon_cvt_flavour_u32_f64
)
18987 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18990 if (flavour
== neon_cvt_flavour_s32_f16
18991 || flavour
== neon_cvt_flavour_u32_f16
)
18992 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18995 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18999 case neon_cvt_flavour_s32_f64
:
19003 case neon_cvt_flavour_s32_f32
:
19007 case neon_cvt_flavour_s32_f16
:
19011 case neon_cvt_flavour_u32_f64
:
19015 case neon_cvt_flavour_u32_f32
:
19019 case neon_cvt_flavour_u32_f16
:
19024 first_error (_("invalid instruction shape"));
19030 case neon_cvt_mode_a
: rm
= 0; break;
19031 case neon_cvt_mode_n
: rm
= 1; break;
19032 case neon_cvt_mode_p
: rm
= 2; break;
19033 case neon_cvt_mode_m
: rm
= 3; break;
19034 default: first_error (_("invalid rounding mode")); return;
19037 NEON_ENCODE (FPV8
, inst
);
19038 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
19039 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
19040 inst
.instruction
|= sz
<< 8;
19042 /* ARMv8.2 fp16 VCVT instruction. */
19043 if (flavour
== neon_cvt_flavour_s32_f16
19044 ||flavour
== neon_cvt_flavour_u32_f16
)
19045 do_scalar_fp16_v82_encode ();
19046 inst
.instruction
|= op
<< 7;
19047 inst
.instruction
|= rm
<< 16;
19048 inst
.instruction
|= 0xf0000000;
19049 inst
.is_neon
= TRUE
;
19053 do_neon_cvt_1 (enum neon_cvt_mode mode
)
19055 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
19056 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
19057 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
19059 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19061 if (flavour
== neon_cvt_flavour_invalid
)
19064 /* PR11109: Handle round-to-zero for VCVT conversions. */
19065 if (mode
== neon_cvt_mode_z
19066 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
19067 && (flavour
== neon_cvt_flavour_s16_f16
19068 || flavour
== neon_cvt_flavour_u16_f16
19069 || flavour
== neon_cvt_flavour_s32_f32
19070 || flavour
== neon_cvt_flavour_u32_f32
19071 || flavour
== neon_cvt_flavour_s32_f64
19072 || flavour
== neon_cvt_flavour_u32_f64
)
19073 && (rs
== NS_FD
|| rs
== NS_FF
))
19075 do_vfp_nsyn_cvtz ();
19079 /* ARMv8.2 fp16 VCVT conversions. */
19080 if (mode
== neon_cvt_mode_z
19081 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
19082 && (flavour
== neon_cvt_flavour_s32_f16
19083 || flavour
== neon_cvt_flavour_u32_f16
)
19086 do_vfp_nsyn_cvtz ();
19087 do_scalar_fp16_v82_encode ();
19091 /* VFP rather than Neon conversions. */
19092 if (flavour
>= neon_cvt_flavour_first_fp
)
19094 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19095 do_vfp_nsyn_cvt (rs
, flavour
);
19097 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19105 if (mode
== neon_cvt_mode_z
19106 && (flavour
== neon_cvt_flavour_f16_s16
19107 || flavour
== neon_cvt_flavour_f16_u16
19108 || flavour
== neon_cvt_flavour_s16_f16
19109 || flavour
== neon_cvt_flavour_u16_f16
19110 || flavour
== neon_cvt_flavour_f32_u32
19111 || flavour
== neon_cvt_flavour_f32_s32
19112 || flavour
== neon_cvt_flavour_s32_f32
19113 || flavour
== neon_cvt_flavour_u32_f32
))
19115 if (!check_simd_pred_availability (TRUE
,
19116 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19119 else if (mode
== neon_cvt_mode_n
)
19121 /* We are dealing with vcvt with the 'ne' condition. */
19123 inst
.instruction
= N_MNEM_vcvt
;
19124 do_neon_cvt_1 (neon_cvt_mode_z
);
19127 /* fall through. */
19131 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
19132 0x0000100, 0x1000100, 0x0, 0x1000000};
19134 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19135 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19138 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19140 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
19141 _("immediate value out of range"));
19144 case neon_cvt_flavour_f16_s16
:
19145 case neon_cvt_flavour_f16_u16
:
19146 case neon_cvt_flavour_s16_f16
:
19147 case neon_cvt_flavour_u16_f16
:
19148 constraint (inst
.operands
[2].imm
> 16,
19149 _("immediate value out of range"));
19151 case neon_cvt_flavour_f32_u32
:
19152 case neon_cvt_flavour_f32_s32
:
19153 case neon_cvt_flavour_s32_f32
:
19154 case neon_cvt_flavour_u32_f32
:
19155 constraint (inst
.operands
[2].imm
> 32,
19156 _("immediate value out of range"));
19159 inst
.error
= BAD_FPU
;
19164 /* Fixed-point conversion with #0 immediate is encoded as an
19165 integer conversion. */
19166 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
19168 NEON_ENCODE (IMMED
, inst
);
19169 if (flavour
!= neon_cvt_flavour_invalid
)
19170 inst
.instruction
|= enctab
[flavour
];
19171 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19172 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19173 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19174 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19175 inst
.instruction
|= neon_quad (rs
) << 6;
19176 inst
.instruction
|= 1 << 21;
19177 if (flavour
< neon_cvt_flavour_s16_f16
)
19179 inst
.instruction
|= 1 << 21;
19180 immbits
= 32 - inst
.operands
[2].imm
;
19181 inst
.instruction
|= immbits
<< 16;
19185 inst
.instruction
|= 3 << 20;
19186 immbits
= 16 - inst
.operands
[2].imm
;
19187 inst
.instruction
|= immbits
<< 16;
19188 inst
.instruction
&= ~(1 << 9);
19191 neon_dp_fixup (&inst
);
19196 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
19197 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
19198 && (flavour
== neon_cvt_flavour_s16_f16
19199 || flavour
== neon_cvt_flavour_u16_f16
19200 || flavour
== neon_cvt_flavour_s32_f32
19201 || flavour
== neon_cvt_flavour_u32_f32
))
19203 if (!check_simd_pred_availability (TRUE
,
19204 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19207 else if (mode
== neon_cvt_mode_z
19208 && (flavour
== neon_cvt_flavour_f16_s16
19209 || flavour
== neon_cvt_flavour_f16_u16
19210 || flavour
== neon_cvt_flavour_s16_f16
19211 || flavour
== neon_cvt_flavour_u16_f16
19212 || flavour
== neon_cvt_flavour_f32_u32
19213 || flavour
== neon_cvt_flavour_f32_s32
19214 || flavour
== neon_cvt_flavour_s32_f32
19215 || flavour
== neon_cvt_flavour_u32_f32
))
19217 if (!check_simd_pred_availability (TRUE
,
19218 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19221 /* fall through. */
19223 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
19226 NEON_ENCODE (FLOAT
, inst
);
19227 if (!check_simd_pred_availability (TRUE
,
19228 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
19231 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19232 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19233 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19234 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19235 inst
.instruction
|= neon_quad (rs
) << 6;
19236 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
19237 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
19238 inst
.instruction
|= mode
<< 8;
19239 if (flavour
== neon_cvt_flavour_u16_f16
19240 || flavour
== neon_cvt_flavour_s16_f16
)
19241 /* Mask off the original size bits and reencode them. */
19242 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
19245 inst
.instruction
|= 0xfc000000;
19247 inst
.instruction
|= 0xf0000000;
19253 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
19254 0x100, 0x180, 0x0, 0x080};
19256 NEON_ENCODE (INTEGER
, inst
);
19258 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
19260 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19264 if (flavour
!= neon_cvt_flavour_invalid
)
19265 inst
.instruction
|= enctab
[flavour
];
19267 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19268 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19269 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19270 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19271 inst
.instruction
|= neon_quad (rs
) << 6;
19272 if (flavour
>= neon_cvt_flavour_s16_f16
19273 && flavour
<= neon_cvt_flavour_f16_u16
)
19274 /* Half precision. */
19275 inst
.instruction
|= 1 << 18;
19277 inst
.instruction
|= 2 << 18;
19279 neon_dp_fixup (&inst
);
19284 /* Half-precision conversions for Advanced SIMD -- neon. */
19287 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19291 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19293 as_bad (_("operand size must match register width"));
19298 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19300 as_bad (_("operand size must match register width"));
19306 if (flavour
== neon_cvt_flavour_bf16_f32
)
19308 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH8
) == FAIL
)
19310 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19311 /* VCVT.bf16.f32. */
19312 inst
.instruction
= 0x11b60640;
19315 /* VCVT.f16.f32. */
19316 inst
.instruction
= 0x3b60600;
19319 /* VCVT.f32.f16. */
19320 inst
.instruction
= 0x3b60700;
19322 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19323 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19324 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19325 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19326 neon_dp_fixup (&inst
);
19330 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19331 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19332 do_vfp_nsyn_cvt (rs
, flavour
);
19334 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19339 do_neon_cvtr (void)
19341 do_neon_cvt_1 (neon_cvt_mode_x
);
19347 do_neon_cvt_1 (neon_cvt_mode_z
);
19351 do_neon_cvta (void)
19353 do_neon_cvt_1 (neon_cvt_mode_a
);
19357 do_neon_cvtn (void)
19359 do_neon_cvt_1 (neon_cvt_mode_n
);
19363 do_neon_cvtp (void)
19365 do_neon_cvt_1 (neon_cvt_mode_p
);
19369 do_neon_cvtm (void)
19371 do_neon_cvt_1 (neon_cvt_mode_m
);
19375 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19378 mark_feature_used (&fpu_vfp_ext_armv8
);
19380 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19381 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19382 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19383 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19384 inst
.instruction
|= to
? 0x10000 : 0;
19385 inst
.instruction
|= t
? 0x80 : 0;
19386 inst
.instruction
|= is_double
? 0x100 : 0;
19387 do_vfp_cond_or_thumb ();
19391 do_neon_cvttb_1 (bfd_boolean t
)
19393 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19394 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19398 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19400 int single_to_half
= 0;
19401 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19404 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19406 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19407 && (flavour
== neon_cvt_flavour_u16_f16
19408 || flavour
== neon_cvt_flavour_s16_f16
19409 || flavour
== neon_cvt_flavour_f16_s16
19410 || flavour
== neon_cvt_flavour_f16_u16
19411 || flavour
== neon_cvt_flavour_u32_f32
19412 || flavour
== neon_cvt_flavour_s32_f32
19413 || flavour
== neon_cvt_flavour_f32_s32
19414 || flavour
== neon_cvt_flavour_f32_u32
))
19417 inst
.instruction
= N_MNEM_vcvt
;
19418 set_pred_insn_type (INSIDE_VPT_INSN
);
19419 do_neon_cvt_1 (neon_cvt_mode_z
);
19422 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19423 single_to_half
= 1;
19424 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19426 first_error (BAD_FPU
);
19430 inst
.instruction
= 0xee3f0e01;
19431 inst
.instruction
|= single_to_half
<< 28;
19432 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19433 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19434 inst
.instruction
|= t
<< 12;
19435 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19436 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19439 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19442 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19444 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19447 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19449 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19451 /* The VCVTB and VCVTT instructions with D-register operands
19452 don't work for SP only targets. */
19453 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19457 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19459 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19461 /* The VCVTB and VCVTT instructions with D-register operands
19462 don't work for SP only targets. */
19463 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19467 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19469 else if (neon_check_type (2, rs
, N_BF16
| N_VFP
, N_F32
).type
!= NT_invtype
)
19471 constraint (!mark_feature_used (&arm_ext_bf16
), _(BAD_BF16
));
19473 inst
.instruction
|= (1 << 8);
19474 inst
.instruction
&= ~(1 << 9);
19475 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19482 do_neon_cvtb (void)
19484 do_neon_cvttb_1 (FALSE
);
19489 do_neon_cvtt (void)
19491 do_neon_cvttb_1 (TRUE
);
19495 neon_move_immediate (void)
19497 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19498 struct neon_type_el et
= neon_check_type (2, rs
,
19499 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19500 unsigned immlo
, immhi
= 0, immbits
;
19501 int op
, cmode
, float_p
;
19503 constraint (et
.type
== NT_invtype
,
19504 _("operand size must be specified for immediate VMOV"));
19506 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19507 op
= (inst
.instruction
& (1 << 5)) != 0;
19509 immlo
= inst
.operands
[1].imm
;
19510 if (inst
.operands
[1].regisimm
)
19511 immhi
= inst
.operands
[1].reg
;
19513 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19514 _("immediate has bits set outside the operand size"));
19516 float_p
= inst
.operands
[1].immisfloat
;
19518 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19519 et
.size
, et
.type
)) == FAIL
)
19521 /* Invert relevant bits only. */
19522 neon_invert_size (&immlo
, &immhi
, et
.size
);
19523 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19524 with one or the other; those cases are caught by
19525 neon_cmode_for_move_imm. */
19527 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19528 &op
, et
.size
, et
.type
)) == FAIL
)
19530 first_error (_("immediate out of range"));
19535 inst
.instruction
&= ~(1 << 5);
19536 inst
.instruction
|= op
<< 5;
19538 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19539 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19540 inst
.instruction
|= neon_quad (rs
) << 6;
19541 inst
.instruction
|= cmode
<< 8;
19543 neon_write_immbits (immbits
);
19549 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19552 if (inst
.operands
[1].isreg
)
19554 enum neon_shape rs
;
19555 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19556 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19558 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19560 NEON_ENCODE (INTEGER
, inst
);
19561 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19562 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19563 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19564 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19565 inst
.instruction
|= neon_quad (rs
) << 6;
19569 NEON_ENCODE (IMMED
, inst
);
19570 neon_move_immediate ();
19573 neon_dp_fixup (&inst
);
19575 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19577 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19581 /* Encode instructions of form:
19583 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19584 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19587 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19589 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19591 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19592 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19593 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19594 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19595 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19596 inst
.instruction
|= neon_logbits (size
) << 20;
19598 neon_dp_fixup (&inst
);
19602 do_neon_dyadic_long (void)
19604 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19607 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19610 NEON_ENCODE (INTEGER
, inst
);
19611 /* FIXME: Type checking for lengthening op. */
19612 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19613 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19614 neon_mixed_length (et
, et
.size
);
19616 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19617 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19619 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19620 in an IT block with le/lt conditions. */
19622 if (inst
.cond
== 0xf)
19624 else if (inst
.cond
== 0x10)
19627 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19629 if (inst
.instruction
== N_MNEM_vaddl
)
19631 inst
.instruction
= N_MNEM_vadd
;
19632 do_neon_addsub_if_i ();
19634 else if (inst
.instruction
== N_MNEM_vsubl
)
19636 inst
.instruction
= N_MNEM_vsub
;
19637 do_neon_addsub_if_i ();
19639 else if (inst
.instruction
== N_MNEM_vabdl
)
19641 inst
.instruction
= N_MNEM_vabd
;
19642 do_neon_dyadic_if_su ();
19646 first_error (BAD_FPU
);
19650 do_neon_abal (void)
19652 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19653 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19654 neon_mixed_length (et
, et
.size
);
19658 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19660 if (inst
.operands
[2].isscalar
)
19662 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19663 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19664 NEON_ENCODE (SCALAR
, inst
);
19665 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19669 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19670 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19671 NEON_ENCODE (INTEGER
, inst
);
19672 neon_mixed_length (et
, et
.size
);
19677 do_neon_mac_maybe_scalar_long (void)
19679 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19682 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19683 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19686 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19688 unsigned regno
= NEON_SCALAR_REG (scalar
);
19689 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19693 if (regno
> 7 || elno
> 3)
19696 return ((regno
& 0x7)
19697 | ((elno
& 0x1) << 3)
19698 | (((elno
>> 1) & 0x1) << 5));
19702 if (regno
> 15 || elno
> 1)
19705 return (((regno
& 0x1) << 5)
19706 | ((regno
>> 1) & 0x7)
19707 | ((elno
& 0x1) << 3));
19711 first_error (_("scalar out of range for multiply instruction"));
19716 do_neon_fmac_maybe_scalar_long (int subtype
)
19718 enum neon_shape rs
;
19720 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19721 field (bits[21:20]) has different meaning. For scalar index variant, it's
19722 used to differentiate add and subtract, otherwise it's with fixed value
19726 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19727 be a scalar index register. */
19728 if (inst
.operands
[2].isscalar
)
19730 high8
= 0xfe000000;
19733 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19737 high8
= 0xfc000000;
19740 inst
.instruction
|= (0x1 << 23);
19741 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19745 if (inst
.cond
!= COND_ALWAYS
)
19746 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19747 "behaviour is UNPREDICTABLE"));
19749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19752 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19755 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19756 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19757 so we simply pass -1 as size. */
19758 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19759 neon_three_same (quad_p
, 0, size
);
19761 /* Undo neon_dp_fixup. Redo the high eight bits. */
19762 inst
.instruction
&= 0x00ffffff;
19763 inst
.instruction
|= high8
;
19765 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19766 whether the instruction is in Q form and whether Vm is a scalar indexed
19768 if (inst
.operands
[2].isscalar
)
19771 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19772 inst
.instruction
&= 0xffffffd0;
19773 inst
.instruction
|= rm
;
19777 /* Redo Rn as well. */
19778 inst
.instruction
&= 0xfff0ff7f;
19779 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19780 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19785 /* Redo Rn and Rm. */
19786 inst
.instruction
&= 0xfff0ff50;
19787 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19788 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19789 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19790 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19795 do_neon_vfmal (void)
19797 return do_neon_fmac_maybe_scalar_long (0);
19801 do_neon_vfmsl (void)
19803 return do_neon_fmac_maybe_scalar_long (1);
19807 do_neon_dyadic_wide (void)
19809 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19810 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19811 neon_mixed_length (et
, et
.size
);
19815 do_neon_dyadic_narrow (void)
19817 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19818 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19819 /* Operand sign is unimportant, and the U bit is part of the opcode,
19820 so force the operand type to integer. */
19821 et
.type
= NT_integer
;
19822 neon_mixed_length (et
, et
.size
/ 2);
19826 do_neon_mul_sat_scalar_long (void)
19828 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19832 do_neon_vmull (void)
19834 if (inst
.operands
[2].isscalar
)
19835 do_neon_mac_maybe_scalar_long ();
19838 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19839 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19841 if (et
.type
== NT_poly
)
19842 NEON_ENCODE (POLY
, inst
);
19844 NEON_ENCODE (INTEGER
, inst
);
19846 /* For polynomial encoding the U bit must be zero, and the size must
19847 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19848 obviously, as 0b10). */
19851 /* Check we're on the correct architecture. */
19852 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19854 _("Instruction form not available on this architecture.");
19859 neon_mixed_length (et
, et
.size
);
19866 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19867 struct neon_type_el et
= neon_check_type (3, rs
,
19868 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19869 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19871 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19872 _("shift out of range"));
19873 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19874 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19875 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19876 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19877 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19878 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19879 inst
.instruction
|= neon_quad (rs
) << 6;
19880 inst
.instruction
|= imm
<< 8;
19882 neon_dp_fixup (&inst
);
19888 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19891 enum neon_shape rs
;
19892 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19893 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19895 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19897 struct neon_type_el et
= neon_check_type (2, rs
,
19898 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19900 unsigned op
= (inst
.instruction
>> 7) & 3;
19901 /* N (width of reversed regions) is encoded as part of the bitmask. We
19902 extract it here to check the elements to be reversed are smaller.
19903 Otherwise we'd get a reserved instruction. */
19904 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19907 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19908 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19909 " operands makes instruction UNPREDICTABLE"));
19911 gas_assert (elsize
!= 0);
19912 constraint (et
.size
>= elsize
,
19913 _("elements must be smaller than reversal region"));
19914 neon_two_same (neon_quad (rs
), 1, et
.size
);
19920 if (inst
.operands
[1].isscalar
)
19922 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19924 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19925 struct neon_type_el et
= neon_check_type (2, rs
,
19926 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19927 unsigned sizebits
= et
.size
>> 3;
19928 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19929 int logsize
= neon_logbits (et
.size
);
19930 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19932 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19935 NEON_ENCODE (SCALAR
, inst
);
19936 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19937 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19938 inst
.instruction
|= LOW4 (dm
);
19939 inst
.instruction
|= HI1 (dm
) << 5;
19940 inst
.instruction
|= neon_quad (rs
) << 6;
19941 inst
.instruction
|= x
<< 17;
19942 inst
.instruction
|= sizebits
<< 16;
19944 neon_dp_fixup (&inst
);
19948 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19949 struct neon_type_el et
= neon_check_type (2, rs
,
19950 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19953 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19957 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19960 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19962 if (inst
.operands
[1].reg
== REG_SP
)
19963 as_tsktsk (MVE_BAD_SP
);
19964 else if (inst
.operands
[1].reg
== REG_PC
)
19965 as_tsktsk (MVE_BAD_PC
);
19968 /* Duplicate ARM register to lanes of vector. */
19969 NEON_ENCODE (ARMREG
, inst
);
19972 case 8: inst
.instruction
|= 0x400000; break;
19973 case 16: inst
.instruction
|= 0x000020; break;
19974 case 32: inst
.instruction
|= 0x000000; break;
19977 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19978 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19979 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19980 inst
.instruction
|= neon_quad (rs
) << 21;
19981 /* The encoding for this instruction is identical for the ARM and Thumb
19982 variants, except for the condition field. */
19983 do_vfp_cond_or_thumb ();
19988 do_mve_mov (int toQ
)
19990 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19992 if (inst
.cond
> COND_ALWAYS
)
19993 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19995 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
20004 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
20005 _("Index one must be [2,3] and index two must be two less than"
20007 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
20008 _("General purpose registers may not be the same"));
20009 constraint (inst
.operands
[Rt
].reg
== REG_SP
20010 || inst
.operands
[Rt2
].reg
== REG_SP
,
20012 constraint (inst
.operands
[Rt
].reg
== REG_PC
20013 || inst
.operands
[Rt2
].reg
== REG_PC
,
20016 inst
.instruction
= 0xec000f00;
20017 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
20018 inst
.instruction
|= !!toQ
<< 20;
20019 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
20020 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
20021 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
20022 inst
.instruction
|= inst
.operands
[Rt
].reg
;
20028 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20031 if (inst
.cond
> COND_ALWAYS
)
20032 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20034 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
20036 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
20039 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20040 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
20041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20042 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20043 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20048 /* VMOV has particularly many variations. It can be one of:
20049 0. VMOV<c><q> <Qd>, <Qm>
20050 1. VMOV<c><q> <Dd>, <Dm>
20051 (Register operations, which are VORR with Rm = Rn.)
20052 2. VMOV<c><q>.<dt> <Qd>, #<imm>
20053 3. VMOV<c><q>.<dt> <Dd>, #<imm>
20055 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
20056 (ARM register to scalar.)
20057 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
20058 (Two ARM registers to vector.)
20059 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
20060 (Scalar to ARM register.)
20061 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
20062 (Vector to two ARM registers.)
20063 8. VMOV.F32 <Sd>, <Sm>
20064 9. VMOV.F64 <Dd>, <Dm>
20065 (VFP register moves.)
20066 10. VMOV.F32 <Sd>, #imm
20067 11. VMOV.F64 <Dd>, #imm
20068 (VFP float immediate load.)
20069 12. VMOV <Rd>, <Sm>
20070 (VFP single to ARM reg.)
20071 13. VMOV <Sd>, <Rm>
20072 (ARM reg to VFP single.)
20073 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
20074 (Two ARM regs to two VFP singles.)
20075 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
20076 (Two VFP singles to two ARM regs.)
20077 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
20078 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
20079 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
20080 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
20082 These cases can be disambiguated using neon_select_shape, except cases 1/9
20083 and 3/11 which depend on the operand type too.
20085 All the encoded bits are hardcoded by this function.
20087 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
20088 Cases 5, 7 may be used with VFPv2 and above.
20090 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
20091 can specify a type where it doesn't make sense to, and is ignored). */
20096 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
20097 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
20098 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
20099 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
20101 struct neon_type_el et
;
20102 const char *ldconst
= 0;
20106 case NS_DD
: /* case 1/9. */
20107 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20108 /* It is not an error here if no type is given. */
20111 /* In MVE we interpret the following instructions as same, so ignoring
20112 the following type (float) and size (64) checks.
20113 a: VMOV<c><q> <Dd>, <Dm>
20114 b: VMOV<c><q>.F64 <Dd>, <Dm>. */
20115 if ((et
.type
== NT_float
&& et
.size
== 64)
20116 || (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
20118 do_vfp_nsyn_opcode ("fcpyd");
20121 /* fall through. */
20123 case NS_QQ
: /* case 0/1. */
20125 if (!check_simd_pred_availability (FALSE
,
20126 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20128 /* The architecture manual I have doesn't explicitly state which
20129 value the U bit should have for register->register moves, but
20130 the equivalent VORR instruction has U = 0, so do that. */
20131 inst
.instruction
= 0x0200110;
20132 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20133 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20134 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20135 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20136 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20137 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20138 inst
.instruction
|= neon_quad (rs
) << 6;
20140 neon_dp_fixup (&inst
);
20144 case NS_DI
: /* case 3/11. */
20145 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
20147 if (et
.type
== NT_float
&& et
.size
== 64)
20149 /* case 11 (fconstd). */
20150 ldconst
= "fconstd";
20151 goto encode_fconstd
;
20153 /* fall through. */
20155 case NS_QI
: /* case 2/3. */
20156 if (!check_simd_pred_availability (FALSE
,
20157 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20159 inst
.instruction
= 0x0800010;
20160 neon_move_immediate ();
20161 neon_dp_fixup (&inst
);
20164 case NS_SR
: /* case 4. */
20166 unsigned bcdebits
= 0;
20168 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
20169 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
20171 /* .<size> is optional here, defaulting to .32. */
20172 if (inst
.vectype
.elems
== 0
20173 && inst
.operands
[0].vectype
.type
== NT_invtype
20174 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20176 inst
.vectype
.el
[0].type
= NT_untyped
;
20177 inst
.vectype
.el
[0].size
= 32;
20178 inst
.vectype
.elems
= 1;
20181 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
20182 logsize
= neon_logbits (et
.size
);
20186 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20187 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
20192 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20193 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20197 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20199 if (inst
.operands
[1].reg
== REG_SP
)
20200 as_tsktsk (MVE_BAD_SP
);
20201 else if (inst
.operands
[1].reg
== REG_PC
)
20202 as_tsktsk (MVE_BAD_PC
);
20204 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
20206 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20207 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20212 case 8: bcdebits
= 0x8; break;
20213 case 16: bcdebits
= 0x1; break;
20214 case 32: bcdebits
= 0x0; break;
20218 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20220 inst
.instruction
= 0xe000b10;
20221 do_vfp_cond_or_thumb ();
20222 inst
.instruction
|= LOW4 (dn
) << 16;
20223 inst
.instruction
|= HI1 (dn
) << 7;
20224 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20225 inst
.instruction
|= (bcdebits
& 3) << 5;
20226 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
20227 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20231 case NS_DRR
: /* case 5 (fmdrr). */
20232 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20233 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20236 inst
.instruction
= 0xc400b10;
20237 do_vfp_cond_or_thumb ();
20238 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
20239 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
20240 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
20241 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
20244 case NS_RS
: /* case 6. */
20247 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
20248 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
20249 unsigned abcdebits
= 0;
20251 /* .<dt> is optional here, defaulting to .32. */
20252 if (inst
.vectype
.elems
== 0
20253 && inst
.operands
[0].vectype
.type
== NT_invtype
20254 && inst
.operands
[1].vectype
.type
== NT_invtype
)
20256 inst
.vectype
.el
[0].type
= NT_untyped
;
20257 inst
.vectype
.el
[0].size
= 32;
20258 inst
.vectype
.elems
= 1;
20261 et
= neon_check_type (2, NS_NULL
,
20262 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
20263 logsize
= neon_logbits (et
.size
);
20267 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
20268 && vfp_or_neon_is_neon (NEON_CHECK_CC
20269 | NEON_CHECK_ARCH
) == FAIL
)
20274 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
20275 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20279 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20281 if (inst
.operands
[0].reg
== REG_SP
)
20282 as_tsktsk (MVE_BAD_SP
);
20283 else if (inst
.operands
[0].reg
== REG_PC
)
20284 as_tsktsk (MVE_BAD_PC
);
20287 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
20289 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20290 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20294 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20295 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20296 case 32: abcdebits
= 0x00; break;
20300 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20301 inst
.instruction
= 0xe100b10;
20302 do_vfp_cond_or_thumb ();
20303 inst
.instruction
|= LOW4 (dn
) << 16;
20304 inst
.instruction
|= HI1 (dn
) << 7;
20305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20306 inst
.instruction
|= (abcdebits
& 3) << 5;
20307 inst
.instruction
|= (abcdebits
>> 2) << 21;
20308 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20312 case NS_RRD
: /* case 7 (fmrrd). */
20313 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20314 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20317 inst
.instruction
= 0xc500b10;
20318 do_vfp_cond_or_thumb ();
20319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20320 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20321 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20322 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20325 case NS_FF
: /* case 8 (fcpys). */
20326 do_vfp_nsyn_opcode ("fcpys");
20330 case NS_FI
: /* case 10 (fconsts). */
20331 ldconst
= "fconsts";
20333 if (!inst
.operands
[1].immisfloat
)
20336 /* Immediate has to fit in 8 bits so float is enough. */
20337 float imm
= (float) inst
.operands
[1].imm
;
20338 memcpy (&new_imm
, &imm
, sizeof (float));
20339 /* But the assembly may have been written to provide an integer
20340 bit pattern that equates to a float, so check that the
20341 conversion has worked. */
20342 if (is_quarter_float (new_imm
))
20344 if (is_quarter_float (inst
.operands
[1].imm
))
20345 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20347 inst
.operands
[1].imm
= new_imm
;
20348 inst
.operands
[1].immisfloat
= 1;
20352 if (is_quarter_float (inst
.operands
[1].imm
))
20354 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20355 do_vfp_nsyn_opcode (ldconst
);
20357 /* ARMv8.2 fp16 vmov.f16 instruction. */
20359 do_scalar_fp16_v82_encode ();
20362 first_error (_("immediate out of range"));
20366 case NS_RF
: /* case 12 (fmrs). */
20367 do_vfp_nsyn_opcode ("fmrs");
20368 /* ARMv8.2 fp16 vmov.f16 instruction. */
20370 do_scalar_fp16_v82_encode ();
20374 case NS_FR
: /* case 13 (fmsr). */
20375 do_vfp_nsyn_opcode ("fmsr");
20376 /* ARMv8.2 fp16 vmov.f16 instruction. */
20378 do_scalar_fp16_v82_encode ();
20388 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20389 (one of which is a list), but we have parsed four. Do some fiddling to
20390 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20392 case NS_RRFF
: /* case 14 (fmrrs). */
20393 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20394 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20396 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20397 _("VFP registers must be adjacent"));
20398 inst
.operands
[2].imm
= 2;
20399 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20400 do_vfp_nsyn_opcode ("fmrrs");
20403 case NS_FFRR
: /* case 15 (fmsrr). */
20404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20405 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20407 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20408 _("VFP registers must be adjacent"));
20409 inst
.operands
[1] = inst
.operands
[2];
20410 inst
.operands
[2] = inst
.operands
[3];
20411 inst
.operands
[0].imm
= 2;
20412 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20413 do_vfp_nsyn_opcode ("fmsrr");
20417 /* neon_select_shape has determined that the instruction
20418 shape is wrong and has already set the error message. */
20429 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20430 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20431 && !inst
.operands
[2].present
))
20433 inst
.instruction
= 0;
20436 set_pred_insn_type (INSIDE_IT_INSN
);
20441 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20444 if (inst
.cond
!= COND_ALWAYS
)
20445 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20447 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20448 | N_S16
| N_U16
| N_KEY
);
20450 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20451 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20452 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20453 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20454 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20455 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20460 do_neon_rshift_round_imm (void)
20462 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20465 enum neon_shape rs
;
20466 struct neon_type_el et
;
20468 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20470 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20471 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20475 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20476 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20478 int imm
= inst
.operands
[2].imm
;
20480 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20483 inst
.operands
[2].present
= 0;
20488 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20489 _("immediate out of range for shift"));
20490 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20495 do_neon_movhf (void)
20497 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20498 constraint (rs
!= NS_HH
, _("invalid suffix"));
20500 if (inst
.cond
!= COND_ALWAYS
)
20504 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20505 " the behaviour is UNPREDICTABLE"));
20509 inst
.error
= BAD_COND
;
20514 do_vfp_sp_monadic ();
20517 inst
.instruction
|= 0xf0000000;
20521 do_neon_movl (void)
20523 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20524 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20525 unsigned sizebits
= et
.size
>> 3;
20526 inst
.instruction
|= sizebits
<< 19;
20527 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20533 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20534 struct neon_type_el et
= neon_check_type (2, rs
,
20535 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20536 NEON_ENCODE (INTEGER
, inst
);
20537 neon_two_same (neon_quad (rs
), 1, et
.size
);
20541 do_neon_zip_uzp (void)
20543 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20544 struct neon_type_el et
= neon_check_type (2, rs
,
20545 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20546 if (rs
== NS_DD
&& et
.size
== 32)
20548 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20549 inst
.instruction
= N_MNEM_vtrn
;
20553 neon_two_same (neon_quad (rs
), 1, et
.size
);
20557 do_neon_sat_abs_neg (void)
20559 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20562 enum neon_shape rs
;
20563 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20564 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20566 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20567 struct neon_type_el et
= neon_check_type (2, rs
,
20568 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20569 neon_two_same (neon_quad (rs
), 1, et
.size
);
20573 do_neon_pair_long (void)
20575 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20576 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20577 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20578 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20579 neon_two_same (neon_quad (rs
), 1, et
.size
);
20583 do_neon_recip_est (void)
20585 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20586 struct neon_type_el et
= neon_check_type (2, rs
,
20587 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20588 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20589 neon_two_same (neon_quad (rs
), 1, et
.size
);
20595 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20598 enum neon_shape rs
;
20599 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20600 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20602 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20604 struct neon_type_el et
= neon_check_type (2, rs
,
20605 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20606 neon_two_same (neon_quad (rs
), 1, et
.size
);
20612 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20615 enum neon_shape rs
;
20616 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20617 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20619 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20621 struct neon_type_el et
= neon_check_type (2, rs
,
20622 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20623 neon_two_same (neon_quad (rs
), 1, et
.size
);
20629 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20630 struct neon_type_el et
= neon_check_type (2, rs
,
20631 N_EQK
| N_INT
, N_8
| N_KEY
);
20632 neon_two_same (neon_quad (rs
), 1, et
.size
);
20638 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20639 neon_two_same (neon_quad (rs
), 1, -1);
20643 do_neon_tbl_tbx (void)
20645 unsigned listlenbits
;
20646 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20648 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20650 first_error (_("bad list length for table lookup"));
20654 listlenbits
= inst
.operands
[1].imm
- 1;
20655 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20656 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20657 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20658 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20659 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20660 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20661 inst
.instruction
|= listlenbits
<< 8;
20663 neon_dp_fixup (&inst
);
20667 do_neon_ldm_stm (void)
20669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
20670 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20672 /* P, U and L bits are part of bitmask. */
20673 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20674 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20676 if (inst
.operands
[1].issingle
)
20678 do_vfp_nsyn_ldm_stm (is_dbmode
);
20682 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20683 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20685 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20686 _("register list must contain at least 1 and at most 16 "
20689 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20690 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20691 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20692 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20694 inst
.instruction
|= offsetbits
;
20696 do_vfp_cond_or_thumb ();
20700 do_vfp_nsyn_pop (void)
20703 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20704 return do_vfp_nsyn_opcode ("vldm");
20707 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20710 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20711 _("register list must contain at least 1 and at most 16 "
20714 if (inst
.operands
[1].issingle
)
20715 do_vfp_nsyn_opcode ("fldmias");
20717 do_vfp_nsyn_opcode ("fldmiad");
20721 do_vfp_nsyn_push (void)
20724 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)) {
20725 return do_vfp_nsyn_opcode ("vstmdb");
20728 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
20731 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20732 _("register list must contain at least 1 and at most 16 "
20735 if (inst
.operands
[1].issingle
)
20736 do_vfp_nsyn_opcode ("fstmdbs");
20738 do_vfp_nsyn_opcode ("fstmdbd");
20743 do_neon_ldr_str (void)
20745 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20747 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20748 And is UNPREDICTABLE in thumb mode. */
20750 && inst
.operands
[1].reg
== REG_PC
20751 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20754 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20755 else if (warn_on_deprecated
)
20756 as_tsktsk (_("Use of PC here is deprecated"));
20759 if (inst
.operands
[0].issingle
)
20762 do_vfp_nsyn_opcode ("flds");
20764 do_vfp_nsyn_opcode ("fsts");
20766 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20767 if (inst
.vectype
.el
[0].size
== 16)
20768 do_scalar_fp16_v82_encode ();
20773 do_vfp_nsyn_opcode ("fldd");
20775 do_vfp_nsyn_opcode ("fstd");
20780 do_t_vldr_vstr_sysreg (void)
20782 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20783 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20785 /* Use of PC is UNPREDICTABLE. */
20786 if (inst
.operands
[1].reg
== REG_PC
)
20787 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20789 if (inst
.operands
[1].immisreg
)
20790 inst
.error
= _("instruction does not accept register index");
20792 if (!inst
.operands
[1].isreg
)
20793 inst
.error
= _("instruction does not accept PC-relative addressing");
20795 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20796 inst
.error
= _("immediate value out of range");
20798 inst
.instruction
= 0xec000f80;
20800 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20801 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20802 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20803 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20807 do_vldr_vstr (void)
20809 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20811 /* VLDR/VSTR (System Register). */
20814 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20815 as_bad (_("Instruction not permitted on this architecture"));
20817 do_t_vldr_vstr_sysreg ();
20822 if (!mark_feature_used (&fpu_vfp_ext_v1xd
)
20823 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20824 as_bad (_("Instruction not permitted on this architecture"));
20825 do_neon_ldr_str ();
20829 /* "interleave" version also handles non-interleaving register VLD1/VST1
20833 do_neon_ld_st_interleave (void)
20835 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20836 N_8
| N_16
| N_32
| N_64
);
20837 unsigned alignbits
= 0;
20839 /* The bits in this table go:
20840 0: register stride of one (0) or two (1)
20841 1,2: register list length, minus one (1, 2, 3, 4).
20842 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20843 We use -1 for invalid entries. */
20844 const int typetable
[] =
20846 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20847 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20848 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20849 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20853 if (et
.type
== NT_invtype
)
20856 if (inst
.operands
[1].immisalign
)
20857 switch (inst
.operands
[1].imm
>> 8)
20859 case 64: alignbits
= 1; break;
20861 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20862 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20863 goto bad_alignment
;
20867 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20868 goto bad_alignment
;
20873 first_error (_("bad alignment"));
20877 inst
.instruction
|= alignbits
<< 4;
20878 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20880 /* Bits [4:6] of the immediate in a list specifier encode register stride
20881 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20882 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20883 up the right value for "type" in a table based on this value and the given
20884 list style, then stick it back. */
20885 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20886 | (((inst
.instruction
>> 8) & 3) << 3);
20888 typebits
= typetable
[idx
];
20890 constraint (typebits
== -1, _("bad list type for instruction"));
20891 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20894 inst
.instruction
&= ~0xf00;
20895 inst
.instruction
|= typebits
<< 8;
20898 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20899 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20900 otherwise. The variable arguments are a list of pairs of legal (size, align)
20901 values, terminated with -1. */
20904 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20907 int result
= FAIL
, thissize
, thisalign
;
20909 if (!inst
.operands
[1].immisalign
)
20915 va_start (ap
, do_alignment
);
20919 thissize
= va_arg (ap
, int);
20920 if (thissize
== -1)
20922 thisalign
= va_arg (ap
, int);
20924 if (size
== thissize
&& align
== thisalign
)
20927 while (result
!= SUCCESS
);
20931 if (result
== SUCCESS
)
20934 first_error (_("unsupported alignment for instruction"));
20940 do_neon_ld_st_lane (void)
20942 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20943 int align_good
, do_alignment
= 0;
20944 int logsize
= neon_logbits (et
.size
);
20945 int align
= inst
.operands
[1].imm
>> 8;
20946 int n
= (inst
.instruction
>> 8) & 3;
20947 int max_el
= 64 / et
.size
;
20949 if (et
.type
== NT_invtype
)
20952 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20953 _("bad list length"));
20954 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20955 _("scalar index out of range"));
20956 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20958 _("stride of 2 unavailable when element size is 8"));
20962 case 0: /* VLD1 / VST1. */
20963 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20965 if (align_good
== FAIL
)
20969 unsigned alignbits
= 0;
20972 case 16: alignbits
= 0x1; break;
20973 case 32: alignbits
= 0x3; break;
20976 inst
.instruction
|= alignbits
<< 4;
20980 case 1: /* VLD2 / VST2. */
20981 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20982 16, 32, 32, 64, -1);
20983 if (align_good
== FAIL
)
20986 inst
.instruction
|= 1 << 4;
20989 case 2: /* VLD3 / VST3. */
20990 constraint (inst
.operands
[1].immisalign
,
20991 _("can't use alignment with this instruction"));
20994 case 3: /* VLD4 / VST4. */
20995 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20996 16, 64, 32, 64, 32, 128, -1);
20997 if (align_good
== FAIL
)
21001 unsigned alignbits
= 0;
21004 case 8: alignbits
= 0x1; break;
21005 case 16: alignbits
= 0x1; break;
21006 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
21009 inst
.instruction
|= alignbits
<< 4;
21016 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
21017 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21018 inst
.instruction
|= 1 << (4 + logsize
);
21020 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
21021 inst
.instruction
|= logsize
<< 10;
21024 /* Encode single n-element structure to all lanes VLD<n> instructions. */
21027 do_neon_ld_dup (void)
21029 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
21030 int align_good
, do_alignment
= 0;
21032 if (et
.type
== NT_invtype
)
21035 switch ((inst
.instruction
>> 8) & 3)
21037 case 0: /* VLD1. */
21038 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
21039 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21040 &do_alignment
, 16, 16, 32, 32, -1);
21041 if (align_good
== FAIL
)
21043 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
21046 case 2: inst
.instruction
|= 1 << 5; break;
21047 default: first_error (_("bad list length")); return;
21049 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21052 case 1: /* VLD2. */
21053 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
21054 &do_alignment
, 8, 16, 16, 32, 32, 64,
21056 if (align_good
== FAIL
)
21058 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
21059 _("bad list length"));
21060 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21061 inst
.instruction
|= 1 << 5;
21062 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21065 case 2: /* VLD3. */
21066 constraint (inst
.operands
[1].immisalign
,
21067 _("can't use alignment with this instruction"));
21068 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
21069 _("bad list length"));
21070 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21071 inst
.instruction
|= 1 << 5;
21072 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21075 case 3: /* VLD4. */
21077 int align
= inst
.operands
[1].imm
>> 8;
21078 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
21079 16, 64, 32, 64, 32, 128, -1);
21080 if (align_good
== FAIL
)
21082 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
21083 _("bad list length"));
21084 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
21085 inst
.instruction
|= 1 << 5;
21086 if (et
.size
== 32 && align
== 128)
21087 inst
.instruction
|= 0x3 << 6;
21089 inst
.instruction
|= neon_logbits (et
.size
) << 6;
21096 inst
.instruction
|= do_alignment
<< 4;
21099 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
21100 apart from bits [11:4]. */
21103 do_neon_ldx_stx (void)
21105 if (inst
.operands
[1].isreg
)
21106 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
21108 switch (NEON_LANE (inst
.operands
[0].imm
))
21110 case NEON_INTERLEAVE_LANES
:
21111 NEON_ENCODE (INTERLV
, inst
);
21112 do_neon_ld_st_interleave ();
21115 case NEON_ALL_LANES
:
21116 NEON_ENCODE (DUP
, inst
);
21117 if (inst
.instruction
== N_INV
)
21119 first_error ("only loads support such operands");
21126 NEON_ENCODE (LANE
, inst
);
21127 do_neon_ld_st_lane ();
21130 /* L bit comes from bit mask. */
21131 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21133 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
21135 if (inst
.operands
[1].postind
)
21137 int postreg
= inst
.operands
[1].imm
& 0xf;
21138 constraint (!inst
.operands
[1].immisreg
,
21139 _("post-index must be a register"));
21140 constraint (postreg
== 0xd || postreg
== 0xf,
21141 _("bad register for post-index"));
21142 inst
.instruction
|= postreg
;
21146 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
21147 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
21148 || inst
.relocs
[0].exp
.X_add_number
!= 0,
21151 if (inst
.operands
[1].writeback
)
21153 inst
.instruction
|= 0xd;
21156 inst
.instruction
|= 0xf;
21160 inst
.instruction
|= 0xf9000000;
21162 inst
.instruction
|= 0xf4000000;
21167 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
21169 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21170 D register operands. */
21171 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21172 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21175 NEON_ENCODE (FPV8
, inst
);
21177 if (rs
== NS_FFF
|| rs
== NS_HHH
)
21179 do_vfp_sp_dyadic ();
21181 /* ARMv8.2 fp16 instruction. */
21183 do_scalar_fp16_v82_encode ();
21186 do_vfp_dp_rd_rn_rm ();
21189 inst
.instruction
|= 0x100;
21191 inst
.instruction
|= 0xf0000000;
21197 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21199 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
21200 first_error (_("invalid instruction shape"));
21206 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21207 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21209 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
21212 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21215 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
21219 do_vrint_1 (enum neon_cvt_mode mode
)
21221 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
21222 struct neon_type_el et
;
21227 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
21228 D register operands. */
21229 if (neon_shape_class
[rs
] == SC_DOUBLE
)
21230 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21233 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
21235 if (et
.type
!= NT_invtype
)
21237 /* VFP encodings. */
21238 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
21239 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
21240 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21242 NEON_ENCODE (FPV8
, inst
);
21243 if (rs
== NS_FF
|| rs
== NS_HH
)
21244 do_vfp_sp_monadic ();
21246 do_vfp_dp_rd_rm ();
21250 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
21251 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
21252 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
21253 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
21254 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
21255 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
21256 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
21260 inst
.instruction
|= (rs
== NS_DD
) << 8;
21261 do_vfp_cond_or_thumb ();
21263 /* ARMv8.2 fp16 vrint instruction. */
21265 do_scalar_fp16_v82_encode ();
21269 /* Neon encodings (or something broken...). */
21271 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
21273 if (et
.type
== NT_invtype
)
21276 if (!check_simd_pred_availability (TRUE
,
21277 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
21280 NEON_ENCODE (FLOAT
, inst
);
21282 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21283 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21284 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21285 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21286 inst
.instruction
|= neon_quad (rs
) << 6;
21287 /* Mask off the original size bits and reencode them. */
21288 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
21289 | neon_logbits (et
.size
) << 18);
21293 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
21294 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
21295 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
21296 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
21297 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
21298 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
21299 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
21304 inst
.instruction
|= 0xfc000000;
21306 inst
.instruction
|= 0xf0000000;
21313 do_vrint_1 (neon_cvt_mode_x
);
21319 do_vrint_1 (neon_cvt_mode_z
);
21325 do_vrint_1 (neon_cvt_mode_r
);
21331 do_vrint_1 (neon_cvt_mode_a
);
21337 do_vrint_1 (neon_cvt_mode_n
);
21343 do_vrint_1 (neon_cvt_mode_p
);
21349 do_vrint_1 (neon_cvt_mode_m
);
21353 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21355 unsigned regno
= NEON_SCALAR_REG (opnd
);
21356 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21358 if (elsize
== 16 && elno
< 2 && regno
< 16)
21359 return regno
| (elno
<< 4);
21360 else if (elsize
== 32 && elno
== 0)
21363 first_error (_("scalar out of range"));
21370 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21371 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21372 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21373 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21374 _("expression too complex"));
21375 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21376 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21377 _("immediate out of range"));
21380 if (!check_simd_pred_availability (TRUE
,
21381 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21384 if (inst
.operands
[2].isscalar
)
21386 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21387 first_error (_("invalid instruction shape"));
21388 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21389 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21390 N_KEY
| N_F16
| N_F32
).size
;
21391 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21393 inst
.instruction
= 0xfe000800;
21394 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21395 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21396 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21397 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21398 inst
.instruction
|= LOW4 (m
);
21399 inst
.instruction
|= HI1 (m
) << 5;
21400 inst
.instruction
|= neon_quad (rs
) << 6;
21401 inst
.instruction
|= rot
<< 20;
21402 inst
.instruction
|= (size
== 32) << 23;
21406 enum neon_shape rs
;
21407 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21408 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21410 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21412 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21413 N_KEY
| N_F16
| N_F32
).size
;
21414 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21415 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21416 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21417 as_tsktsk (BAD_MVE_SRCDEST
);
21419 neon_three_same (neon_quad (rs
), 0, -1);
21420 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21421 inst
.instruction
|= 0xfc200800;
21422 inst
.instruction
|= rot
<< 23;
21423 inst
.instruction
|= (size
== 32) << 20;
21430 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21431 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21432 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21433 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21434 _("expression too complex"));
21436 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21437 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21438 enum neon_shape rs
;
21439 struct neon_type_el et
;
21440 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21442 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21443 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21447 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21448 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21450 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21451 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21452 "operand makes instruction UNPREDICTABLE"));
21455 if (et
.type
== NT_invtype
)
21458 if (!check_simd_pred_availability (et
.type
== NT_float
,
21459 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21462 if (et
.type
== NT_float
)
21464 neon_three_same (neon_quad (rs
), 0, -1);
21465 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21466 inst
.instruction
|= 0xfc800800;
21467 inst
.instruction
|= (rot
== 270) << 24;
21468 inst
.instruction
|= (et
.size
== 32) << 20;
21472 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21473 inst
.instruction
= 0xfe000f00;
21474 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21475 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21476 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21477 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21478 inst
.instruction
|= (rot
== 270) << 12;
21479 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21480 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21481 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21486 /* Dot Product instructions encoding support. */
21489 do_neon_dotproduct (int unsigned_p
)
21491 enum neon_shape rs
;
21492 unsigned scalar_oprd2
= 0;
21495 if (inst
.cond
!= COND_ALWAYS
)
21496 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21497 "is UNPREDICTABLE"));
21499 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21502 /* Dot Product instructions are in three-same D/Q register format or the third
21503 operand can be a scalar index register. */
21504 if (inst
.operands
[2].isscalar
)
21506 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21507 high8
= 0xfe000000;
21508 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21512 high8
= 0xfc000000;
21513 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21517 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21519 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21521 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21522 Product instruction, so we pass 0 as the "ubit" parameter. And the
21523 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21524 neon_three_same (neon_quad (rs
), 0, 32);
21526 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21527 different NEON three-same encoding. */
21528 inst
.instruction
&= 0x00ffffff;
21529 inst
.instruction
|= high8
;
21530 /* Encode 'U' bit which indicates signedness. */
21531 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21532 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21533 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21534 the instruction encoding. */
21535 if (inst
.operands
[2].isscalar
)
21537 inst
.instruction
&= 0xffffffd0;
21538 inst
.instruction
|= LOW4 (scalar_oprd2
);
21539 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21543 /* Dot Product instructions for signed integer. */
21546 do_neon_dotproduct_s (void)
21548 return do_neon_dotproduct (0);
21551 /* Dot Product instructions for unsigned integer. */
21554 do_neon_dotproduct_u (void)
21556 return do_neon_dotproduct (1);
21562 enum neon_shape rs
;
21563 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21564 if (inst
.operands
[2].isscalar
)
21566 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21567 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21569 inst
.instruction
|= (1 << 25);
21570 int index
= inst
.operands
[2].reg
& 0xf;
21571 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21572 inst
.operands
[2].reg
>>= 4;
21573 constraint (!(inst
.operands
[2].reg
< 16),
21574 _("indexed register must be less than 16"));
21575 neon_three_args (rs
== NS_QQS
);
21576 inst
.instruction
|= (index
<< 5);
21580 inst
.instruction
|= (1 << 21);
21581 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21582 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21583 neon_three_args (rs
== NS_QQQ
);
21590 enum neon_shape rs
;
21591 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21592 if (inst
.operands
[2].isscalar
)
21594 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21595 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21597 inst
.instruction
|= (1 << 25);
21598 int index
= inst
.operands
[2].reg
& 0xf;
21599 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
21600 inst
.operands
[2].reg
>>= 4;
21601 constraint (!(inst
.operands
[2].reg
< 16),
21602 _("indexed register must be less than 16"));
21603 neon_three_args (rs
== NS_QQS
);
21604 inst
.instruction
|= (index
<< 5);
21611 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21612 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_KEY
);
21614 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21616 neon_three_args (1);
21623 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
21624 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_U8
| N_KEY
);
21626 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21628 neon_three_args (1);
21633 check_cde_operand (size_t index
, int is_dual
)
21635 unsigned Rx
= inst
.operands
[index
].reg
;
21636 bfd_boolean isvec
= inst
.operands
[index
].isvec
;
21637 if (is_dual
== 0 && thumb_mode
)
21639 !((Rx
<= 14 && Rx
!= 13) || (Rx
== REG_PC
&& isvec
)),
21640 _("Register must be r0-r14 except r13, or APSR_nzcv."));
21642 constraint ( !((Rx
<= 10 && Rx
% 2 == 0 )),
21643 _("Register must be an even register between r0-r10."));
21647 cde_coproc_enabled (unsigned coproc
)
21651 case 0: return mark_feature_used (&arm_ext_cde0
);
21652 case 1: return mark_feature_used (&arm_ext_cde1
);
21653 case 2: return mark_feature_used (&arm_ext_cde2
);
21654 case 3: return mark_feature_used (&arm_ext_cde3
);
21655 case 4: return mark_feature_used (&arm_ext_cde4
);
21656 case 5: return mark_feature_used (&arm_ext_cde5
);
21657 case 6: return mark_feature_used (&arm_ext_cde6
);
21658 case 7: return mark_feature_used (&arm_ext_cde7
);
21659 default: return FALSE
;
21663 #define cde_coproc_pos 8
21665 cde_handle_coproc (void)
21667 unsigned coproc
= inst
.operands
[0].reg
;
21668 constraint (coproc
> 7, _("CDE Coprocessor must be in range 0-7"));
21669 constraint (!(cde_coproc_enabled (coproc
)), BAD_CDE_COPROC
);
21670 inst
.instruction
|= coproc
<< cde_coproc_pos
;
21672 #undef cde_coproc_pos
21675 cxn_handle_predication (bfd_boolean is_accum
)
21677 /* This function essentially checks for a suffix, not whether the instruction
21678 is inside an IT block or not.
21679 The CX* instructions should never have a conditional suffix -- this is not
21680 mentioned in the syntax. */
21681 if (conditional_insn ())
21682 inst
.error
= BAD_SYNTAX
;
21683 /* Here we ensure that if the current element */
21685 set_pred_insn_type (NEUTRAL_IT_NO_VPT_INSN
);
21687 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21691 do_custom_instruction_1 (int is_dual
, bfd_boolean is_accum
)
21694 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21698 Rd
= inst
.operands
[1].reg
;
21699 check_cde_operand (1, is_dual
);
21703 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21704 _("cx1d requires consecutive destination registers."));
21705 imm
= inst
.operands
[3].imm
;
21707 else if (is_dual
== 0)
21708 imm
= inst
.operands
[2].imm
;
21712 inst
.instruction
|= Rd
<< 12;
21713 inst
.instruction
|= (imm
& 0x1F80) << 9;
21714 inst
.instruction
|= (imm
& 0x0040) << 1;
21715 inst
.instruction
|= (imm
& 0x003f);
21717 cde_handle_coproc ();
21718 cxn_handle_predication (is_accum
);
21722 do_custom_instruction_2 (int is_dual
, bfd_boolean is_accum
)
21725 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21727 unsigned imm
, Rd
, Rn
;
21729 Rd
= inst
.operands
[1].reg
;
21733 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21734 _("cx2d requires consecutive destination registers."));
21735 imm
= inst
.operands
[4].imm
;
21736 Rn
= inst
.operands
[3].reg
;
21738 else if (is_dual
== 0)
21740 imm
= inst
.operands
[3].imm
;
21741 Rn
= inst
.operands
[2].reg
;
21746 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21747 check_cde_operand (1, is_dual
);
21749 inst
.instruction
|= Rd
<< 12;
21750 inst
.instruction
|= Rn
<< 16;
21752 inst
.instruction
|= (imm
& 0x0380) << 13;
21753 inst
.instruction
|= (imm
& 0x0040) << 1;
21754 inst
.instruction
|= (imm
& 0x003f);
21756 cde_handle_coproc ();
21757 cxn_handle_predication (is_accum
);
21761 do_custom_instruction_3 (int is_dual
, bfd_boolean is_accum
)
21764 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
21766 unsigned imm
, Rd
, Rn
, Rm
;
21768 Rd
= inst
.operands
[1].reg
;
21772 constraint (inst
.operands
[2].reg
!= Rd
+ 1,
21773 _("cx3d requires consecutive destination registers."));
21774 imm
= inst
.operands
[5].imm
;
21775 Rn
= inst
.operands
[3].reg
;
21776 Rm
= inst
.operands
[4].reg
;
21778 else if (is_dual
== 0)
21780 imm
= inst
.operands
[4].imm
;
21781 Rn
= inst
.operands
[2].reg
;
21782 Rm
= inst
.operands
[3].reg
;
21787 check_cde_operand (1, is_dual
);
21788 check_cde_operand (2 + is_dual
, /* is_dual = */0);
21789 check_cde_operand (3 + is_dual
, /* is_dual = */0);
21791 inst
.instruction
|= Rd
;
21792 inst
.instruction
|= Rn
<< 16;
21793 inst
.instruction
|= Rm
<< 12;
21795 inst
.instruction
|= (imm
& 0x0038) << 17;
21796 inst
.instruction
|= (imm
& 0x0004) << 5;
21797 inst
.instruction
|= (imm
& 0x0003) << 4;
21799 cde_handle_coproc ();
21800 cxn_handle_predication (is_accum
);
21806 return do_custom_instruction_1 (0, 0);
21812 return do_custom_instruction_1 (0, 1);
21818 return do_custom_instruction_1 (1, 0);
21824 return do_custom_instruction_1 (1, 1);
21830 return do_custom_instruction_2 (0, 0);
21836 return do_custom_instruction_2 (0, 1);
21842 return do_custom_instruction_2 (1, 0);
21848 return do_custom_instruction_2 (1, 1);
21854 return do_custom_instruction_3 (0, 0);
21860 return do_custom_instruction_3 (0, 1);
21866 return do_custom_instruction_3 (1, 0);
21872 return do_custom_instruction_3 (1, 1);
21876 vcx_assign_vec_d (unsigned regnum
)
21878 inst
.instruction
|= HI4 (regnum
) << 12;
21879 inst
.instruction
|= LOW1 (regnum
) << 22;
21883 vcx_assign_vec_m (unsigned regnum
)
21885 inst
.instruction
|= HI4 (regnum
);
21886 inst
.instruction
|= LOW1 (regnum
) << 5;
21890 vcx_assign_vec_n (unsigned regnum
)
21892 inst
.instruction
|= HI4 (regnum
) << 16;
21893 inst
.instruction
|= LOW1 (regnum
) << 7;
21896 enum vcx_reg_type
{
21902 static enum vcx_reg_type
21903 vcx_get_reg_type (enum neon_shape ns
)
21905 gas_assert (ns
== NS_PQI
21913 || ns
== NS_PFFFI
);
21914 if (ns
== NS_PQI
|| ns
== NS_PQQI
|| ns
== NS_PQQQI
)
21916 if (ns
== NS_PDI
|| ns
== NS_PDDI
|| ns
== NS_PDDDI
)
21921 #define vcx_size_pos 24
21922 #define vcx_vec_pos 6
21924 vcx_handle_shape (enum vcx_reg_type reg_type
)
21927 if (reg_type
== q_reg
)
21928 inst
.instruction
|= 1 << vcx_vec_pos
;
21929 else if (reg_type
== d_reg
)
21930 inst
.instruction
|= 1 << vcx_size_pos
;
21934 The documentation says that the Q registers are encoded as 2*N in the D:Vd
21935 bits (or equivalent for N and M registers).
21936 Similarly the D registers are encoded as N in D:Vd bits.
21937 While the S registers are encoded as N in the Vd:D bits.
21939 Taking into account the maximum values of these registers we can see a
21940 nicer pattern for calculation:
21941 Q -> 7, D -> 15, S -> 31
21943 If we say that everything is encoded in the Vd:D bits, then we can say
21944 that Q is encoded as 4*N, and D is encoded as 2*N.
21945 This way the bits will end up the same, and calculation is simpler.
21946 (calculation is now:
21947 1. Multiply by a number determined by the register letter.
21948 2. Encode resulting number in Vd:D bits.)
21950 This is made a little more complicated by automatic handling of 'Q'
21951 registers elsewhere, which means the register number is already 2*N where
21952 N is the number the user wrote after the register letter.
21957 #undef vcx_size_pos
21960 vcx_ensure_register_in_range (unsigned R
, enum vcx_reg_type reg_type
)
21962 if (reg_type
== q_reg
)
21964 gas_assert (R
% 2 == 0);
21965 constraint (R
>= 16, _("'q' register must be in range 0-7"));
21967 else if (reg_type
== d_reg
)
21968 constraint (R
>= 16, _("'d' register must be in range 0-15"));
21970 constraint (R
>= 32, _("'s' register must be in range 0-31"));
21973 static void (*vcx_assign_vec
[3]) (unsigned) = {
21980 vcx_handle_register_arguments (unsigned num_registers
,
21981 enum vcx_reg_type reg_type
)
21984 unsigned reg_mult
= vcx_handle_shape (reg_type
);
21985 for (i
= 0; i
< num_registers
; i
++)
21987 R
= inst
.operands
[i
+1].reg
;
21988 vcx_ensure_register_in_range (R
, reg_type
);
21989 if (num_registers
== 3 && i
> 0)
21992 vcx_assign_vec
[1] (R
* reg_mult
);
21994 vcx_assign_vec
[2] (R
* reg_mult
);
21997 vcx_assign_vec
[i
](R
* reg_mult
);
22002 vcx_handle_insn_block (enum vcx_reg_type reg_type
)
22004 if (reg_type
== q_reg
)
22005 if (inst
.cond
> COND_ALWAYS
)
22006 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
22008 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
22009 else if (inst
.cond
== COND_ALWAYS
)
22010 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22012 inst
.error
= BAD_NOT_IT
;
22016 vcx_handle_common_checks (unsigned num_args
, enum neon_shape rs
)
22018 constraint (!mark_feature_used (&arm_ext_cde
), _(BAD_CDE
));
22019 cde_handle_coproc ();
22020 enum vcx_reg_type reg_type
= vcx_get_reg_type (rs
);
22021 vcx_handle_register_arguments (num_args
, reg_type
);
22022 vcx_handle_insn_block (reg_type
);
22023 if (reg_type
== q_reg
)
22024 constraint (!mark_feature_used (&mve_ext
),
22025 _("vcx instructions with Q registers require MVE"));
22027 constraint (!(ARM_FSET_CPU_SUBSET (armv8m_fp
, cpu_variant
)
22028 && mark_feature_used (&armv8m_fp
))
22029 && !mark_feature_used (&mve_ext
),
22030 _("vcx instructions with S or D registers require either MVE"
22031 " or Armv8-M floating point etension."));
22037 enum neon_shape rs
= neon_select_shape (NS_PQI
, NS_PDI
, NS_PFI
, NS_NULL
);
22038 vcx_handle_common_checks (1, rs
);
22040 unsigned imm
= inst
.operands
[2].imm
;
22041 inst
.instruction
|= (imm
& 0x03f);
22042 inst
.instruction
|= (imm
& 0x040) << 1;
22043 inst
.instruction
|= (imm
& 0x780) << 9;
22045 constraint (imm
>= 2048,
22046 _("vcx1 with S or D registers takes immediate within 0-2047"));
22047 inst
.instruction
|= (imm
& 0x800) << 13;
22053 enum neon_shape rs
= neon_select_shape (NS_PQQI
, NS_PDDI
, NS_PFFI
, NS_NULL
);
22054 vcx_handle_common_checks (2, rs
);
22056 unsigned imm
= inst
.operands
[3].imm
;
22057 inst
.instruction
|= (imm
& 0x01) << 4;
22058 inst
.instruction
|= (imm
& 0x02) << 6;
22059 inst
.instruction
|= (imm
& 0x3c) << 14;
22061 constraint (imm
>= 64,
22062 _("vcx2 with S or D registers takes immediate within 0-63"));
22063 inst
.instruction
|= (imm
& 0x40) << 18;
22069 enum neon_shape rs
= neon_select_shape (NS_PQQQI
, NS_PDDDI
, NS_PFFFI
, NS_NULL
);
22070 vcx_handle_common_checks (3, rs
);
22072 unsigned imm
= inst
.operands
[4].imm
;
22073 inst
.instruction
|= (imm
& 0x1) << 4;
22074 inst
.instruction
|= (imm
& 0x6) << 19;
22075 if (rs
!= NS_PQQQI
)
22076 constraint (imm
>= 8,
22077 _("vcx2 with S or D registers takes immediate within 0-7"));
22078 inst
.instruction
|= (imm
& 0x8) << 21;
22081 /* Crypto v1 instructions. */
22083 do_crypto_2op_1 (unsigned elttype
, int op
)
22085 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22087 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
22093 NEON_ENCODE (INTEGER
, inst
);
22094 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
22095 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
22096 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
22097 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
22099 inst
.instruction
|= op
<< 6;
22102 inst
.instruction
|= 0xfc000000;
22104 inst
.instruction
|= 0xf0000000;
22108 do_crypto_3op_1 (int u
, int op
)
22110 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22112 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
22113 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
22118 NEON_ENCODE (INTEGER
, inst
);
22119 neon_three_same (1, u
, 8 << op
);
22125 do_crypto_2op_1 (N_8
, 0);
22131 do_crypto_2op_1 (N_8
, 1);
22137 do_crypto_2op_1 (N_8
, 2);
22143 do_crypto_2op_1 (N_8
, 3);
22149 do_crypto_3op_1 (0, 0);
22155 do_crypto_3op_1 (0, 1);
22161 do_crypto_3op_1 (0, 2);
22167 do_crypto_3op_1 (0, 3);
22173 do_crypto_3op_1 (1, 0);
22179 do_crypto_3op_1 (1, 1);
22183 do_sha256su1 (void)
22185 do_crypto_3op_1 (1, 2);
22191 do_crypto_2op_1 (N_32
, -1);
22197 do_crypto_2op_1 (N_32
, 0);
22201 do_sha256su0 (void)
22203 do_crypto_2op_1 (N_32
, 1);
22207 do_crc32_1 (unsigned int poly
, unsigned int sz
)
22209 unsigned int Rd
= inst
.operands
[0].reg
;
22210 unsigned int Rn
= inst
.operands
[1].reg
;
22211 unsigned int Rm
= inst
.operands
[2].reg
;
22213 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22214 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
22215 inst
.instruction
|= LOW4 (Rn
) << 16;
22216 inst
.instruction
|= LOW4 (Rm
);
22217 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
22218 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
22220 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
22221 as_warn (UNPRED_REG ("r15"));
22263 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
22265 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
22266 do_vfp_sp_dp_cvt ();
22267 do_vfp_cond_or_thumb ();
22273 enum neon_shape rs
;
22274 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22275 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22276 if (inst
.operands
[2].isscalar
)
22278 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
22279 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22281 inst
.instruction
|= (1 << 25);
22282 int index
= inst
.operands
[2].reg
& 0xf;
22283 constraint ((index
!= 1 && index
!= 0), _("index must be 0 or 1"));
22284 inst
.operands
[2].reg
>>= 4;
22285 constraint (!(inst
.operands
[2].reg
< 16),
22286 _("indexed register must be less than 16"));
22287 neon_three_args (rs
== NS_QQS
);
22288 inst
.instruction
|= (index
<< 5);
22292 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
22293 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22294 neon_three_args (rs
== NS_QQQ
);
22301 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
22302 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_BF16
| N_KEY
);
22304 constraint (!mark_feature_used (&fpu_neon_ext_armv8
), _(BAD_FPU
));
22305 set_pred_insn_type (OUTSIDE_PRED_INSN
);
22307 neon_three_args (1);
22311 /* Overall per-instruction processing. */
22313 /* We need to be able to fix up arbitrary expressions in some statements.
22314 This is so that we can handle symbols that are an arbitrary distance from
22315 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
22316 which returns part of an address in a form which will be valid for
22317 a data instruction. We do this by pushing the expression into a symbol
22318 in the expr_section, and creating a fix for that. */
22321 fix_new_arm (fragS
* frag
,
22335 /* Create an absolute valued symbol, so we have something to
22336 refer to in the object file. Unfortunately for us, gas's
22337 generic expression parsing will already have folded out
22338 any use of .set foo/.type foo %function that may have
22339 been used to set type information of the target location,
22340 that's being specified symbolically. We have to presume
22341 the user knows what they are doing. */
22345 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
22347 symbol
= symbol_find_or_make (name
);
22348 S_SET_SEGMENT (symbol
, absolute_section
);
22349 symbol_set_frag (symbol
, &zero_address_frag
);
22350 S_SET_VALUE (symbol
, exp
->X_add_number
);
22351 exp
->X_op
= O_symbol
;
22352 exp
->X_add_symbol
= symbol
;
22353 exp
->X_add_number
= 0;
22359 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
22360 (enum bfd_reloc_code_real
) reloc
);
22364 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
22365 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
22369 /* Mark whether the fix is to a THUMB instruction, or an ARM
22371 new_fix
->tc_fix_data
= thumb_mode
;
22374 /* Create a frg for an instruction requiring relaxation. */
22376 output_relax_insn (void)
22382 /* The size of the instruction is unknown, so tie the debug info to the
22383 start of the instruction. */
22384 dwarf2_emit_insn (0);
22386 switch (inst
.relocs
[0].exp
.X_op
)
22389 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
22390 offset
= inst
.relocs
[0].exp
.X_add_number
;
22394 offset
= inst
.relocs
[0].exp
.X_add_number
;
22397 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
22401 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
22402 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
22403 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
22406 /* Write a 32-bit thumb instruction to buf. */
22408 put_thumb32_insn (char * buf
, unsigned long insn
)
22410 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
22411 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
22415 output_inst (const char * str
)
22421 as_bad ("%s -- `%s'", inst
.error
, str
);
22426 output_relax_insn ();
22429 if (inst
.size
== 0)
22432 to
= frag_more (inst
.size
);
22433 /* PR 9814: Record the thumb mode into the current frag so that we know
22434 what type of NOP padding to use, if necessary. We override any previous
22435 setting so that if the mode has changed then the NOPS that we use will
22436 match the encoding of the last instruction in the frag. */
22437 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22439 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
22441 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
22442 put_thumb32_insn (to
, inst
.instruction
);
22444 else if (inst
.size
> INSN_SIZE
)
22446 gas_assert (inst
.size
== (2 * INSN_SIZE
));
22447 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
22448 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
22451 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
22454 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22456 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
22457 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
22458 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
22459 inst
.relocs
[r
].type
);
22462 dwarf2_emit_insn (inst
.size
);
22466 output_it_inst (int cond
, int mask
, char * to
)
22468 unsigned long instruction
= 0xbf00;
22471 instruction
|= mask
;
22472 instruction
|= cond
<< 4;
22476 to
= frag_more (2);
22478 dwarf2_emit_insn (2);
22482 md_number_to_chars (to
, instruction
, 2);
22487 /* Tag values used in struct asm_opcode's tag field. */
22490 OT_unconditional
, /* Instruction cannot be conditionalized.
22491 The ARM condition field is still 0xE. */
22492 OT_unconditionalF
, /* Instruction cannot be conditionalized
22493 and carries 0xF in its ARM condition field. */
22494 OT_csuffix
, /* Instruction takes a conditional suffix. */
22495 OT_csuffixF
, /* Some forms of the instruction take a scalar
22496 conditional suffix, others place 0xF where the
22497 condition field would be, others take a vector
22498 conditional suffix. */
22499 OT_cinfix3
, /* Instruction takes a conditional infix,
22500 beginning at character index 3. (In
22501 unified mode, it becomes a suffix.) */
22502 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
22503 tsts, cmps, cmns, and teqs. */
22504 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
22505 character index 3, even in unified mode. Used for
22506 legacy instructions where suffix and infix forms
22507 may be ambiguous. */
22508 OT_csuf_or_in3
, /* Instruction takes either a conditional
22509 suffix or an infix at character index 3. */
22510 OT_odd_infix_unc
, /* This is the unconditional variant of an
22511 instruction that takes a conditional infix
22512 at an unusual position. In unified mode,
22513 this variant will accept a suffix. */
22514 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
22515 are the conditional variants of instructions that
22516 take conditional infixes in unusual positions.
22517 The infix appears at character index
22518 (tag - OT_odd_infix_0). These are not accepted
22519 in unified mode. */
22522 /* Subroutine of md_assemble, responsible for looking up the primary
22523 opcode from the mnemonic the user wrote. STR points to the
22524 beginning of the mnemonic.
22526 This is not simply a hash table lookup, because of conditional
22527 variants. Most instructions have conditional variants, which are
22528 expressed with a _conditional affix_ to the mnemonic. If we were
22529 to encode each conditional variant as a literal string in the opcode
22530 table, it would have approximately 20,000 entries.
22532 Most mnemonics take this affix as a suffix, and in unified syntax,
22533 'most' is upgraded to 'all'. However, in the divided syntax, some
22534 instructions take the affix as an infix, notably the s-variants of
22535 the arithmetic instructions. Of those instructions, all but six
22536 have the infix appear after the third character of the mnemonic.
22538 Accordingly, the algorithm for looking up primary opcodes given
22541 1. Look up the identifier in the opcode table.
22542 If we find a match, go to step U.
22544 2. Look up the last two characters of the identifier in the
22545 conditions table. If we find a match, look up the first N-2
22546 characters of the identifier in the opcode table. If we
22547 find a match, go to step CE.
22549 3. Look up the fourth and fifth characters of the identifier in
22550 the conditions table. If we find a match, extract those
22551 characters from the identifier, and look up the remaining
22552 characters in the opcode table. If we find a match, go
22557 U. Examine the tag field of the opcode structure, in case this is
22558 one of the six instructions with its conditional infix in an
22559 unusual place. If it is, the tag tells us where to find the
22560 infix; look it up in the conditions table and set inst.cond
22561 accordingly. Otherwise, this is an unconditional instruction.
22562 Again set inst.cond accordingly. Return the opcode structure.
22564 CE. Examine the tag field to make sure this is an instruction that
22565 should receive a conditional suffix. If it is not, fail.
22566 Otherwise, set inst.cond from the suffix we already looked up,
22567 and return the opcode structure.
22569 CM. Examine the tag field to make sure this is an instruction that
22570 should receive a conditional infix after the third character.
22571 If it is not, fail. Otherwise, undo the edits to the current
22572 line of input and proceed as for case CE. */
22574 static const struct asm_opcode
*
22575 opcode_lookup (char **str
)
22579 const struct asm_opcode
*opcode
;
22580 const struct asm_cond
*cond
;
22583 /* Scan up to the end of the mnemonic, which must end in white space,
22584 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
22585 for (base
= end
= *str
; *end
!= '\0'; end
++)
22586 if (*end
== ' ' || *end
== '.')
22592 /* Handle a possible width suffix and/or Neon type suffix. */
22597 /* The .w and .n suffixes are only valid if the unified syntax is in
22599 if (unified_syntax
&& end
[1] == 'w')
22601 else if (unified_syntax
&& end
[1] == 'n')
22606 inst
.vectype
.elems
= 0;
22608 *str
= end
+ offset
;
22610 if (end
[offset
] == '.')
22612 /* See if we have a Neon type suffix (possible in either unified or
22613 non-unified ARM syntax mode). */
22614 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
22617 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
22623 /* Look for unaffixed or special-case affixed mnemonic. */
22624 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22629 if (opcode
->tag
< OT_odd_infix_0
)
22631 inst
.cond
= COND_ALWAYS
;
22635 if (warn_on_deprecated
&& unified_syntax
)
22636 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22637 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
22638 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22641 inst
.cond
= cond
->value
;
22644 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
22646 /* Cannot have a conditional suffix on a mnemonic of less than a character.
22648 if (end
- base
< 2)
22651 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
22652 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22654 /* If this opcode can not be vector predicated then don't accept it with a
22655 vector predication code. */
22656 if (opcode
&& !opcode
->mayBeVecPred
)
22659 if (!opcode
|| !cond
)
22661 /* Cannot have a conditional suffix on a mnemonic of less than two
22663 if (end
- base
< 3)
22666 /* Look for suffixed mnemonic. */
22668 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22669 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22673 if (opcode
&& cond
)
22676 switch (opcode
->tag
)
22678 case OT_cinfix3_legacy
:
22679 /* Ignore conditional suffixes matched on infix only mnemonics. */
22683 case OT_cinfix3_deprecated
:
22684 case OT_odd_infix_unc
:
22685 if (!unified_syntax
)
22687 /* Fall through. */
22691 case OT_csuf_or_in3
:
22692 inst
.cond
= cond
->value
;
22695 case OT_unconditional
:
22696 case OT_unconditionalF
:
22698 inst
.cond
= cond
->value
;
22701 /* Delayed diagnostic. */
22702 inst
.error
= BAD_COND
;
22703 inst
.cond
= COND_ALWAYS
;
22712 /* Cannot have a usual-position infix on a mnemonic of less than
22713 six characters (five would be a suffix). */
22714 if (end
- base
< 6)
22717 /* Look for infixed mnemonic in the usual position. */
22719 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
22723 memcpy (save
, affix
, 2);
22724 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
22725 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
22727 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
22728 memcpy (affix
, save
, 2);
22731 && (opcode
->tag
== OT_cinfix3
22732 || opcode
->tag
== OT_cinfix3_deprecated
22733 || opcode
->tag
== OT_csuf_or_in3
22734 || opcode
->tag
== OT_cinfix3_legacy
))
22737 if (warn_on_deprecated
&& unified_syntax
22738 && (opcode
->tag
== OT_cinfix3
22739 || opcode
->tag
== OT_cinfix3_deprecated
))
22740 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
22742 inst
.cond
= cond
->value
;
22749 /* This function generates an initial IT instruction, leaving its block
22750 virtually open for the new instructions. Eventually,
22751 the mask will be updated by now_pred_add_mask () each time
22752 a new instruction needs to be included in the IT block.
22753 Finally, the block is closed with close_automatic_it_block ().
22754 The block closure can be requested either from md_assemble (),
22755 a tencode (), or due to a label hook. */
22758 new_automatic_it_block (int cond
)
22760 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
22761 now_pred
.mask
= 0x18;
22762 now_pred
.cc
= cond
;
22763 now_pred
.block_length
= 1;
22764 mapping_state (MAP_THUMB
);
22765 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
22766 now_pred
.warn_deprecated
= FALSE
;
22767 now_pred
.insn_cond
= TRUE
;
22770 /* Close an automatic IT block.
22771 See comments in new_automatic_it_block (). */
22774 close_automatic_it_block (void)
22776 now_pred
.mask
= 0x10;
22777 now_pred
.block_length
= 0;
22780 /* Update the mask of the current automatically-generated IT
22781 instruction. See comments in new_automatic_it_block (). */
22784 now_pred_add_mask (int cond
)
22786 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
22787 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
22788 | ((bitvalue) << (nbit)))
22789 const int resulting_bit
= (cond
& 1);
22791 now_pred
.mask
&= 0xf;
22792 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22794 (5 - now_pred
.block_length
));
22795 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
22797 ((5 - now_pred
.block_length
) - 1));
22798 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
22801 #undef SET_BIT_VALUE
22804 /* The IT blocks handling machinery is accessed through the these functions:
22805 it_fsm_pre_encode () from md_assemble ()
22806 set_pred_insn_type () optional, from the tencode functions
22807 set_pred_insn_type_last () ditto
22808 in_pred_block () ditto
22809 it_fsm_post_encode () from md_assemble ()
22810 force_automatic_it_block_close () from label handling functions
22813 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
22814 initializing the IT insn type with a generic initial value depending
22815 on the inst.condition.
22816 2) During the tencode function, two things may happen:
22817 a) The tencode function overrides the IT insn type by
22818 calling either set_pred_insn_type (type) or
22819 set_pred_insn_type_last ().
22820 b) The tencode function queries the IT block state by
22821 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
22823 Both set_pred_insn_type and in_pred_block run the internal FSM state
22824 handling function (handle_pred_state), because: a) setting the IT insn
22825 type may incur in an invalid state (exiting the function),
22826 and b) querying the state requires the FSM to be updated.
22827 Specifically we want to avoid creating an IT block for conditional
22828 branches, so it_fsm_pre_encode is actually a guess and we can't
22829 determine whether an IT block is required until the tencode () routine
22830 has decided what type of instruction this actually it.
22831 Because of this, if set_pred_insn_type and in_pred_block have to be
22832 used, set_pred_insn_type has to be called first.
22834 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
22835 that determines the insn IT type depending on the inst.cond code.
22836 When a tencode () routine encodes an instruction that can be
22837 either outside an IT block, or, in the case of being inside, has to be
22838 the last one, set_pred_insn_type_last () will determine the proper
22839 IT instruction type based on the inst.cond code. Otherwise,
22840 set_pred_insn_type can be called for overriding that logic or
22841 for covering other cases.
22843 Calling handle_pred_state () may not transition the IT block state to
22844 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
22845 still queried. Instead, if the FSM determines that the state should
22846 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
22847 after the tencode () function: that's what it_fsm_post_encode () does.
22849 Since in_pred_block () calls the state handling function to get an
22850 updated state, an error may occur (due to invalid insns combination).
22851 In that case, inst.error is set.
22852 Therefore, inst.error has to be checked after the execution of
22853 the tencode () routine.
22855 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
22856 any pending state change (if any) that didn't take place in
22857 handle_pred_state () as explained above. */
22860 it_fsm_pre_encode (void)
22862 if (inst
.cond
!= COND_ALWAYS
)
22863 inst
.pred_insn_type
= INSIDE_IT_INSN
;
22865 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
22867 now_pred
.state_handled
= 0;
22870 /* IT state FSM handling function. */
22871 /* MVE instructions and non-MVE instructions are handled differently because of
22872 the introduction of VPT blocks.
22873 Specifications say that any non-MVE instruction inside a VPT block is
22874 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
22875 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
22876 few exceptions we have MVE_UNPREDICABLE_INSN.
22877 The error messages provided depending on the different combinations possible
22878 are described in the cases below:
22879 For 'most' MVE instructions:
22880 1) In an IT block, with an IT code: syntax error
22881 2) In an IT block, with a VPT code: error: must be in a VPT block
22882 3) In an IT block, with no code: warning: UNPREDICTABLE
22883 4) In a VPT block, with an IT code: syntax error
22884 5) In a VPT block, with a VPT code: OK!
22885 6) In a VPT block, with no code: error: missing code
22886 7) Outside a pred block, with an IT code: error: syntax error
22887 8) Outside a pred block, with a VPT code: error: should be in a VPT block
22888 9) Outside a pred block, with no code: OK!
22889 For non-MVE instructions:
22890 10) In an IT block, with an IT code: OK!
22891 11) In an IT block, with a VPT code: syntax error
22892 12) In an IT block, with no code: error: missing code
22893 13) In a VPT block, with an IT code: error: should be in an IT block
22894 14) In a VPT block, with a VPT code: syntax error
22895 15) In a VPT block, with no code: UNPREDICTABLE
22896 16) Outside a pred block, with an IT code: error: should be in an IT block
22897 17) Outside a pred block, with a VPT code: syntax error
22898 18) Outside a pred block, with no code: OK!
22903 handle_pred_state (void)
22905 now_pred
.state_handled
= 1;
22906 now_pred
.insn_cond
= FALSE
;
22908 switch (now_pred
.state
)
22910 case OUTSIDE_PRED_BLOCK
:
22911 switch (inst
.pred_insn_type
)
22913 case MVE_UNPREDICABLE_INSN
:
22914 case MVE_OUTSIDE_PRED_INSN
:
22915 if (inst
.cond
< COND_ALWAYS
)
22917 /* Case 7: Outside a pred block, with an IT code: error: syntax
22919 inst
.error
= BAD_SYNTAX
;
22922 /* Case 9: Outside a pred block, with no code: OK! */
22924 case OUTSIDE_PRED_INSN
:
22925 if (inst
.cond
> COND_ALWAYS
)
22927 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22929 inst
.error
= BAD_SYNTAX
;
22932 /* Case 18: Outside a pred block, with no code: OK! */
22935 case INSIDE_VPT_INSN
:
22936 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22938 inst
.error
= BAD_OUT_VPT
;
22941 case INSIDE_IT_INSN
:
22942 case INSIDE_IT_LAST_INSN
:
22943 if (inst
.cond
< COND_ALWAYS
)
22945 /* Case 16: Outside a pred block, with an IT code: error: should
22946 be in an IT block. */
22947 if (thumb_mode
== 0)
22950 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22951 as_tsktsk (_("Warning: conditional outside an IT block"\
22956 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22957 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22959 /* Automatically generate the IT instruction. */
22960 new_automatic_it_block (inst
.cond
);
22961 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22962 close_automatic_it_block ();
22966 inst
.error
= BAD_OUT_IT
;
22972 else if (inst
.cond
> COND_ALWAYS
)
22974 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22976 inst
.error
= BAD_SYNTAX
;
22981 case IF_INSIDE_IT_LAST_INSN
:
22982 case NEUTRAL_IT_INSN
:
22983 case NEUTRAL_IT_NO_VPT_INSN
:
22987 if (inst
.cond
!= COND_ALWAYS
)
22988 first_error (BAD_SYNTAX
);
22989 now_pred
.state
= MANUAL_PRED_BLOCK
;
22990 now_pred
.block_length
= 0;
22991 now_pred
.type
= VECTOR_PRED
;
22995 now_pred
.state
= MANUAL_PRED_BLOCK
;
22996 now_pred
.block_length
= 0;
22997 now_pred
.type
= SCALAR_PRED
;
23002 case AUTOMATIC_PRED_BLOCK
:
23003 /* Three things may happen now:
23004 a) We should increment current it block size;
23005 b) We should close current it block (closing insn or 4 insns);
23006 c) We should close current it block and start a new one (due
23007 to incompatible conditions or
23008 4 insns-length block reached). */
23010 switch (inst
.pred_insn_type
)
23012 case INSIDE_VPT_INSN
:
23014 case MVE_UNPREDICABLE_INSN
:
23015 case MVE_OUTSIDE_PRED_INSN
:
23017 case OUTSIDE_PRED_INSN
:
23018 /* The closure of the block shall happen immediately,
23019 so any in_pred_block () call reports the block as closed. */
23020 force_automatic_it_block_close ();
23023 case INSIDE_IT_INSN
:
23024 case INSIDE_IT_LAST_INSN
:
23025 case IF_INSIDE_IT_LAST_INSN
:
23026 now_pred
.block_length
++;
23028 if (now_pred
.block_length
> 4
23029 || !now_pred_compatible (inst
.cond
))
23031 force_automatic_it_block_close ();
23032 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
23033 new_automatic_it_block (inst
.cond
);
23037 now_pred
.insn_cond
= TRUE
;
23038 now_pred_add_mask (inst
.cond
);
23041 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
23042 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
23043 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
23044 close_automatic_it_block ();
23047 case NEUTRAL_IT_NO_VPT_INSN
:
23048 if (now_pred
.type
== VECTOR_PRED
)
23050 inst
.error
= BAD_NO_VPT
;
23054 case NEUTRAL_IT_INSN
:
23055 now_pred
.block_length
++;
23056 now_pred
.insn_cond
= TRUE
;
23058 if (now_pred
.block_length
> 4)
23059 force_automatic_it_block_close ();
23061 now_pred_add_mask (now_pred
.cc
& 1);
23065 close_automatic_it_block ();
23066 now_pred
.state
= MANUAL_PRED_BLOCK
;
23071 case MANUAL_PRED_BLOCK
:
23074 if (now_pred
.type
== SCALAR_PRED
)
23076 /* Check conditional suffixes. */
23077 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
23078 now_pred
.mask
<<= 1;
23079 now_pred
.mask
&= 0x1f;
23080 is_last
= (now_pred
.mask
== 0x10);
23084 now_pred
.cc
^= (now_pred
.mask
>> 4);
23085 cond
= now_pred
.cc
+ 0xf;
23086 now_pred
.mask
<<= 1;
23087 now_pred
.mask
&= 0x1f;
23088 is_last
= now_pred
.mask
== 0x10;
23090 now_pred
.insn_cond
= TRUE
;
23092 switch (inst
.pred_insn_type
)
23094 case OUTSIDE_PRED_INSN
:
23095 if (now_pred
.type
== SCALAR_PRED
)
23097 if (inst
.cond
== COND_ALWAYS
)
23099 /* Case 12: In an IT block, with no code: error: missing
23101 inst
.error
= BAD_NOT_IT
;
23104 else if (inst
.cond
> COND_ALWAYS
)
23106 /* Case 11: In an IT block, with a VPT code: syntax error.
23108 inst
.error
= BAD_SYNTAX
;
23111 else if (thumb_mode
)
23113 /* This is for some special cases where a non-MVE
23114 instruction is not allowed in an IT block, such as cbz,
23115 but are put into one with a condition code.
23116 You could argue this should be a syntax error, but we
23117 gave the 'not allowed in IT block' diagnostic in the
23118 past so we will keep doing so. */
23119 inst
.error
= BAD_NOT_IT
;
23126 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
23127 as_tsktsk (MVE_NOT_VPT
);
23130 case MVE_OUTSIDE_PRED_INSN
:
23131 if (now_pred
.type
== SCALAR_PRED
)
23133 if (inst
.cond
== COND_ALWAYS
)
23135 /* Case 3: In an IT block, with no code: warning:
23137 as_tsktsk (MVE_NOT_IT
);
23140 else if (inst
.cond
< COND_ALWAYS
)
23142 /* Case 1: In an IT block, with an IT code: syntax error.
23144 inst
.error
= BAD_SYNTAX
;
23152 if (inst
.cond
< COND_ALWAYS
)
23154 /* Case 4: In a VPT block, with an IT code: syntax error.
23156 inst
.error
= BAD_SYNTAX
;
23159 else if (inst
.cond
== COND_ALWAYS
)
23161 /* Case 6: In a VPT block, with no code: error: missing
23163 inst
.error
= BAD_NOT_VPT
;
23171 case MVE_UNPREDICABLE_INSN
:
23172 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
23174 case INSIDE_IT_INSN
:
23175 if (inst
.cond
> COND_ALWAYS
)
23177 /* Case 11: In an IT block, with a VPT code: syntax error. */
23178 /* Case 14: In a VPT block, with a VPT code: syntax error. */
23179 inst
.error
= BAD_SYNTAX
;
23182 else if (now_pred
.type
== SCALAR_PRED
)
23184 /* Case 10: In an IT block, with an IT code: OK! */
23185 if (cond
!= inst
.cond
)
23187 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
23194 /* Case 13: In a VPT block, with an IT code: error: should be
23196 inst
.error
= BAD_OUT_IT
;
23201 case INSIDE_VPT_INSN
:
23202 if (now_pred
.type
== SCALAR_PRED
)
23204 /* Case 2: In an IT block, with a VPT code: error: must be in a
23206 inst
.error
= BAD_OUT_VPT
;
23209 /* Case 5: In a VPT block, with a VPT code: OK! */
23210 else if (cond
!= inst
.cond
)
23212 inst
.error
= BAD_VPT_COND
;
23216 case INSIDE_IT_LAST_INSN
:
23217 case IF_INSIDE_IT_LAST_INSN
:
23218 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
23220 /* Case 4: In a VPT block, with an IT code: syntax error. */
23221 /* Case 11: In an IT block, with a VPT code: syntax error. */
23222 inst
.error
= BAD_SYNTAX
;
23225 else if (cond
!= inst
.cond
)
23227 inst
.error
= BAD_IT_COND
;
23232 inst
.error
= BAD_BRANCH
;
23237 case NEUTRAL_IT_NO_VPT_INSN
:
23238 if (now_pred
.type
== VECTOR_PRED
)
23240 inst
.error
= BAD_NO_VPT
;
23244 case NEUTRAL_IT_INSN
:
23245 /* The BKPT instruction is unconditional even in a IT or VPT
23250 if (now_pred
.type
== SCALAR_PRED
)
23252 inst
.error
= BAD_IT_IT
;
23255 /* fall through. */
23257 if (inst
.cond
== COND_ALWAYS
)
23259 /* Executing a VPT/VPST instruction inside an IT block or a
23260 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
23262 if (now_pred
.type
== SCALAR_PRED
)
23263 as_tsktsk (MVE_NOT_IT
);
23265 as_tsktsk (MVE_NOT_VPT
);
23270 /* VPT/VPST do not accept condition codes. */
23271 inst
.error
= BAD_SYNTAX
;
23282 struct depr_insn_mask
23284 unsigned long pattern
;
23285 unsigned long mask
;
23286 const char* description
;
23289 /* List of 16-bit instruction patterns deprecated in an IT block in
23291 static const struct depr_insn_mask depr_it_insns
[] = {
23292 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
23293 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
23294 { 0xa000, 0xb800, N_("ADR") },
23295 { 0x4800, 0xf800, N_("Literal loads") },
23296 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
23297 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
23298 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
23299 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
23300 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
23305 it_fsm_post_encode (void)
23309 if (!now_pred
.state_handled
)
23310 handle_pred_state ();
23312 if (now_pred
.insn_cond
23313 && warn_on_restrict_it
23314 && !now_pred
.warn_deprecated
23315 && warn_on_deprecated
23316 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
23317 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
23319 if (inst
.instruction
>= 0x10000)
23321 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
23322 "performance deprecated in ARMv8-A and ARMv8-R"));
23323 now_pred
.warn_deprecated
= TRUE
;
23327 const struct depr_insn_mask
*p
= depr_it_insns
;
23329 while (p
->mask
!= 0)
23331 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
23333 as_tsktsk (_("IT blocks containing 16-bit Thumb "
23334 "instructions of the following class are "
23335 "performance deprecated in ARMv8-A and "
23336 "ARMv8-R: %s"), p
->description
);
23337 now_pred
.warn_deprecated
= TRUE
;
23345 if (now_pred
.block_length
> 1)
23347 as_tsktsk (_("IT blocks containing more than one conditional "
23348 "instruction are performance deprecated in ARMv8-A and "
23350 now_pred
.warn_deprecated
= TRUE
;
23354 is_last
= (now_pred
.mask
== 0x10);
23357 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23363 force_automatic_it_block_close (void)
23365 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
23367 close_automatic_it_block ();
23368 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
23374 in_pred_block (void)
23376 if (!now_pred
.state_handled
)
23377 handle_pred_state ();
23379 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
23382 /* Whether OPCODE only has T32 encoding. Since this function is only used by
23383 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
23384 here, hence the "known" in the function name. */
23387 known_t32_only_insn (const struct asm_opcode
*opcode
)
23389 /* Original Thumb-1 wide instruction. */
23390 if (opcode
->tencode
== do_t_blx
23391 || opcode
->tencode
== do_t_branch23
23392 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
23393 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
23396 /* Wide-only instruction added to ARMv8-M Baseline. */
23397 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
23398 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
23399 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
23400 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
23406 /* Whether wide instruction variant can be used if available for a valid OPCODE
23410 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
23412 if (known_t32_only_insn (opcode
))
23415 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
23416 of variant T3 of B.W is checked in do_t_branch. */
23417 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23418 && opcode
->tencode
== do_t_branch
)
23421 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
23422 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
23423 && opcode
->tencode
== do_t_mov_cmp
23424 /* Make sure CMP instruction is not affected. */
23425 && opcode
->aencode
== do_mov
)
23428 /* Wide instruction variants of all instructions with narrow *and* wide
23429 variants become available with ARMv6t2. Other opcodes are either
23430 narrow-only or wide-only and are thus available if OPCODE is valid. */
23431 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
23434 /* OPCODE with narrow only instruction variant or wide variant not
23440 md_assemble (char *str
)
23443 const struct asm_opcode
* opcode
;
23445 /* Align the previous label if needed. */
23446 if (last_label_seen
!= NULL
)
23448 symbol_set_frag (last_label_seen
, frag_now
);
23449 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
23450 S_SET_SEGMENT (last_label_seen
, now_seg
);
23453 memset (&inst
, '\0', sizeof (inst
));
23455 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
23456 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
23458 opcode
= opcode_lookup (&p
);
23461 /* It wasn't an instruction, but it might be a register alias of
23462 the form alias .req reg, or a Neon .dn/.qn directive. */
23463 if (! create_register_alias (str
, p
)
23464 && ! create_neon_reg_alias (str
, p
))
23465 as_bad (_("bad instruction `%s'"), str
);
23470 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
23471 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
23473 /* The value which unconditional instructions should have in place of the
23474 condition field. */
23475 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
23479 arm_feature_set variant
;
23481 variant
= cpu_variant
;
23482 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
23483 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
23484 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
23485 /* Check that this instruction is supported for this CPU. */
23486 if (!opcode
->tvariant
23487 || (thumb_mode
== 1
23488 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
23490 if (opcode
->tencode
== do_t_swi
)
23491 as_bad (_("SVC is not permitted on this architecture"));
23493 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
23496 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
23497 && opcode
->tencode
!= do_t_branch
)
23499 as_bad (_("Thumb does not support conditional execution"));
23503 /* Two things are addressed here:
23504 1) Implicit require narrow instructions on Thumb-1.
23505 This avoids relaxation accidentally introducing Thumb-2
23507 2) Reject wide instructions in non Thumb-2 cores.
23509 Only instructions with narrow and wide variants need to be handled
23510 but selecting all non wide-only instructions is easier. */
23511 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
23512 && !t32_insn_ok (variant
, opcode
))
23514 if (inst
.size_req
== 0)
23516 else if (inst
.size_req
== 4)
23518 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
23519 as_bad (_("selected processor does not support 32bit wide "
23520 "variant of instruction `%s'"), str
);
23522 as_bad (_("selected processor does not support `%s' in "
23523 "Thumb-2 mode"), str
);
23528 inst
.instruction
= opcode
->tvalue
;
23530 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
23532 /* Prepare the pred_insn_type for those encodings that don't set
23534 it_fsm_pre_encode ();
23536 opcode
->tencode ();
23538 it_fsm_post_encode ();
23541 if (!(inst
.error
|| inst
.relax
))
23543 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
23544 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
23545 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
23547 as_bad (_("cannot honor width suffix -- `%s'"), str
);
23552 /* Something has gone badly wrong if we try to relax a fixed size
23554 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
23556 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23557 *opcode
->tvariant
);
23558 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
23559 set those bits when Thumb-2 32-bit instructions are seen. The impact
23560 of relaxable instructions will be considered later after we finish all
23562 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
23563 variant
= arm_arch_none
;
23565 variant
= cpu_variant
;
23566 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
23567 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
23570 check_neon_suffixes
;
23574 mapping_state (MAP_THUMB
);
23577 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23581 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
23582 is_bx
= (opcode
->aencode
== do_bx
);
23584 /* Check that this instruction is supported for this CPU. */
23585 if (!(is_bx
&& fix_v4bx
)
23586 && !(opcode
->avariant
&&
23587 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
23589 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
23594 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
23598 inst
.instruction
= opcode
->avalue
;
23599 if (opcode
->tag
== OT_unconditionalF
)
23600 inst
.instruction
|= 0xFU
<< 28;
23602 inst
.instruction
|= inst
.cond
<< 28;
23603 inst
.size
= INSN_SIZE
;
23604 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
23606 it_fsm_pre_encode ();
23607 opcode
->aencode ();
23608 it_fsm_post_encode ();
23610 /* Arm mode bx is marked as both v4T and v5 because it's still required
23611 on a hypothetical non-thumb v5 core. */
23613 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
23615 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
23616 *opcode
->avariant
);
23618 check_neon_suffixes
;
23622 mapping_state (MAP_ARM
);
23627 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
23635 check_pred_blocks_finished (void)
23640 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
23641 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
23642 == MANUAL_PRED_BLOCK
)
23644 if (now_pred
.type
== SCALAR_PRED
)
23645 as_warn (_("section '%s' finished with an open IT block."),
23648 as_warn (_("section '%s' finished with an open VPT/VPST block."),
23652 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
23654 if (now_pred
.type
== SCALAR_PRED
)
23655 as_warn (_("file finished with an open IT block."));
23657 as_warn (_("file finished with an open VPT/VPST block."));
23662 /* Various frobbings of labels and their addresses. */
23665 arm_start_line_hook (void)
23667 last_label_seen
= NULL
;
23671 arm_frob_label (symbolS
* sym
)
23673 last_label_seen
= sym
;
23675 ARM_SET_THUMB (sym
, thumb_mode
);
23677 #if defined OBJ_COFF || defined OBJ_ELF
23678 ARM_SET_INTERWORK (sym
, support_interwork
);
23681 force_automatic_it_block_close ();
23683 /* Note - do not allow local symbols (.Lxxx) to be labelled
23684 as Thumb functions. This is because these labels, whilst
23685 they exist inside Thumb code, are not the entry points for
23686 possible ARM->Thumb calls. Also, these labels can be used
23687 as part of a computed goto or switch statement. eg gcc
23688 can generate code that looks like this:
23690 ldr r2, [pc, .Laaa]
23700 The first instruction loads the address of the jump table.
23701 The second instruction converts a table index into a byte offset.
23702 The third instruction gets the jump address out of the table.
23703 The fourth instruction performs the jump.
23705 If the address stored at .Laaa is that of a symbol which has the
23706 Thumb_Func bit set, then the linker will arrange for this address
23707 to have the bottom bit set, which in turn would mean that the
23708 address computation performed by the third instruction would end
23709 up with the bottom bit set. Since the ARM is capable of unaligned
23710 word loads, the instruction would then load the incorrect address
23711 out of the jump table, and chaos would ensue. */
23712 if (label_is_thumb_function_name
23713 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
23714 && (bfd_section_flags (now_seg
) & SEC_CODE
) != 0)
23716 /* When the address of a Thumb function is taken the bottom
23717 bit of that address should be set. This will allow
23718 interworking between Arm and Thumb functions to work
23721 THUMB_SET_FUNC (sym
, 1);
23723 label_is_thumb_function_name
= FALSE
;
23726 dwarf2_emit_label (sym
);
23730 arm_data_in_code (void)
23732 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
23734 *input_line_pointer
= '/';
23735 input_line_pointer
+= 5;
23736 *input_line_pointer
= 0;
23744 arm_canonicalize_symbol_name (char * name
)
23748 if (thumb_mode
&& (len
= strlen (name
)) > 5
23749 && streq (name
+ len
- 5, "/data"))
23750 *(name
+ len
- 5) = 0;
23755 /* Table of all register names defined by default. The user can
23756 define additional names with .req. Note that all register names
23757 should appear in both upper and lowercase variants. Some registers
23758 also have mixed-case names. */
23760 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
23761 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
23762 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
23763 #define REGSET(p,t) \
23764 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
23765 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
23766 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
23767 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
23768 #define REGSETH(p,t) \
23769 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
23770 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
23771 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
23772 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
23773 #define REGSET2(p,t) \
23774 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
23775 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
23776 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
23777 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
23778 #define SPLRBANK(base,bank,t) \
23779 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
23780 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
23781 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
23782 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
23783 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
23784 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
23786 static const struct reg_entry reg_names
[] =
23788 /* ARM integer registers. */
23789 REGSET(r
, RN
), REGSET(R
, RN
),
23791 /* ATPCS synonyms. */
23792 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
23793 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
23794 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
23796 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
23797 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
23798 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
23800 /* Well-known aliases. */
23801 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
23802 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
23804 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
23805 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
23807 /* Defining the new Zero register from ARMv8.1-M. */
23811 /* Coprocessor numbers. */
23812 REGSET(p
, CP
), REGSET(P
, CP
),
23814 /* Coprocessor register numbers. The "cr" variants are for backward
23816 REGSET(c
, CN
), REGSET(C
, CN
),
23817 REGSET(cr
, CN
), REGSET(CR
, CN
),
23819 /* ARM banked registers. */
23820 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
23821 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
23822 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
23823 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
23824 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
23825 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
23826 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
23828 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
23829 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
23830 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
23831 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
23832 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
23833 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
23834 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
23835 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
23837 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
23838 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
23839 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
23840 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
23841 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
23842 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
23843 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
23844 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23845 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
23847 /* FPA registers. */
23848 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
23849 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
23851 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
23852 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
23854 /* VFP SP registers. */
23855 REGSET(s
,VFS
), REGSET(S
,VFS
),
23856 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
23858 /* VFP DP Registers. */
23859 REGSET(d
,VFD
), REGSET(D
,VFD
),
23860 /* Extra Neon DP registers. */
23861 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
23863 /* Neon QP registers. */
23864 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
23866 /* VFP control registers. */
23867 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
23868 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
23869 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
23870 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
23871 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
23872 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
23873 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
23874 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
23875 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
23876 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
23877 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
23879 /* Maverick DSP coprocessor registers. */
23880 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
23881 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
23883 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
23884 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
23885 REGDEF(dspsc
,0,DSPSC
),
23887 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
23888 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
23889 REGDEF(DSPSC
,0,DSPSC
),
23891 /* iWMMXt data registers - p0, c0-15. */
23892 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
23894 /* iWMMXt control registers - p1, c0-3. */
23895 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
23896 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
23897 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
23898 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
23900 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
23901 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
23902 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
23903 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
23904 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
23906 /* XScale accumulator registers. */
23907 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
23913 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
23914 within psr_required_here. */
23915 static const struct asm_psr psrs
[] =
23917 /* Backward compatibility notation. Note that "all" is no longer
23918 truly all possible PSR bits. */
23919 {"all", PSR_c
| PSR_f
},
23923 /* Individual flags. */
23929 /* Combinations of flags. */
23930 {"fs", PSR_f
| PSR_s
},
23931 {"fx", PSR_f
| PSR_x
},
23932 {"fc", PSR_f
| PSR_c
},
23933 {"sf", PSR_s
| PSR_f
},
23934 {"sx", PSR_s
| PSR_x
},
23935 {"sc", PSR_s
| PSR_c
},
23936 {"xf", PSR_x
| PSR_f
},
23937 {"xs", PSR_x
| PSR_s
},
23938 {"xc", PSR_x
| PSR_c
},
23939 {"cf", PSR_c
| PSR_f
},
23940 {"cs", PSR_c
| PSR_s
},
23941 {"cx", PSR_c
| PSR_x
},
23942 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23943 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23944 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23945 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23946 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23947 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23948 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23949 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23950 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23951 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23952 {"scf", PSR_s
| PSR_c
| PSR_f
},
23953 {"scx", PSR_s
| PSR_c
| PSR_x
},
23954 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23955 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23956 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23957 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23958 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23959 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23960 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23961 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23962 {"csf", PSR_c
| PSR_s
| PSR_f
},
23963 {"csx", PSR_c
| PSR_s
| PSR_x
},
23964 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23965 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23966 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23967 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23968 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23969 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23970 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23971 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23972 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23973 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23974 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23975 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23976 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23977 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23978 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23979 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23980 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23981 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23982 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23983 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23984 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23985 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23986 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23987 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23988 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23989 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23992 /* Table of V7M psr names. */
23993 static const struct asm_psr v7m_psrs
[] =
23995 {"apsr", 0x0 }, {"APSR", 0x0 },
23996 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23997 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23998 {"psr", 0x3 }, {"PSR", 0x3 },
23999 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
24000 {"ipsr", 0x5 }, {"IPSR", 0x5 },
24001 {"epsr", 0x6 }, {"EPSR", 0x6 },
24002 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
24003 {"msp", 0x8 }, {"MSP", 0x8 },
24004 {"psp", 0x9 }, {"PSP", 0x9 },
24005 {"msplim", 0xa }, {"MSPLIM", 0xa },
24006 {"psplim", 0xb }, {"PSPLIM", 0xb },
24007 {"primask", 0x10}, {"PRIMASK", 0x10},
24008 {"basepri", 0x11}, {"BASEPRI", 0x11},
24009 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
24010 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
24011 {"control", 0x14}, {"CONTROL", 0x14},
24012 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
24013 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
24014 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
24015 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
24016 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
24017 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
24018 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
24019 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
24020 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
24023 /* Table of all shift-in-operand names. */
24024 static const struct asm_shift_name shift_names
[] =
24026 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
24027 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
24028 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
24029 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
24030 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
24031 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
24032 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
24035 /* Table of all explicit relocation names. */
24037 static struct reloc_entry reloc_names
[] =
24039 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
24040 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
24041 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
24042 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
24043 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
24044 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
24045 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
24046 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
24047 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
24048 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
24049 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
24050 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
24051 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
24052 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
24053 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
24054 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
24055 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
24056 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
24057 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
24058 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
24059 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24060 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
24061 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
24062 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
24063 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
24064 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
24065 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
24069 /* Table of all conditional affixes. */
24070 static const struct asm_cond conds
[] =
24074 {"cs", 0x2}, {"hs", 0x2},
24075 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
24088 static const struct asm_cond vconds
[] =
24094 #define UL_BARRIER(L,U,CODE,FEAT) \
24095 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
24096 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
24098 static struct asm_barrier_opt barrier_opt_names
[] =
24100 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
24101 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
24102 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
24103 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
24104 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
24105 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
24106 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
24107 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
24108 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
24109 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
24110 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
24111 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
24112 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
24113 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
24114 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
24115 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
24120 /* Table of ARM-format instructions. */
24122 /* Macros for gluing together operand strings. N.B. In all cases
24123 other than OPS0, the trailing OP_stop comes from default
24124 zero-initialization of the unspecified elements of the array. */
24125 #define OPS0() { OP_stop, }
24126 #define OPS1(a) { OP_##a, }
24127 #define OPS2(a,b) { OP_##a,OP_##b, }
24128 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
24129 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
24130 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
24131 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
24133 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
24134 This is useful when mixing operands for ARM and THUMB, i.e. using the
24135 MIX_ARM_THUMB_OPERANDS macro.
24136 In order to use these macros, prefix the number of operands with _
24138 #define OPS_1(a) { a, }
24139 #define OPS_2(a,b) { a,b, }
24140 #define OPS_3(a,b,c) { a,b,c, }
24141 #define OPS_4(a,b,c,d) { a,b,c,d, }
24142 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
24143 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
24145 /* These macros abstract out the exact format of the mnemonic table and
24146 save some repeated characters. */
24148 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
24149 #define TxCE(mnem, op, top, nops, ops, ae, te) \
24150 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
24151 THUMB_VARIANT, do_##ae, do_##te, 0 }
24153 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
24154 a T_MNEM_xyz enumerator. */
24155 #define TCE(mnem, aop, top, nops, ops, ae, te) \
24156 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
24157 #define tCE(mnem, aop, top, nops, ops, ae, te) \
24158 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24160 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
24161 infix after the third character. */
24162 #define TxC3(mnem, op, top, nops, ops, ae, te) \
24163 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
24164 THUMB_VARIANT, do_##ae, do_##te, 0 }
24165 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
24166 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
24167 THUMB_VARIANT, do_##ae, do_##te, 0 }
24168 #define TC3(mnem, aop, top, nops, ops, ae, te) \
24169 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
24170 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
24171 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
24172 #define tC3(mnem, aop, top, nops, ops, ae, te) \
24173 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24174 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
24175 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
24177 /* Mnemonic that cannot be conditionalized. The ARM condition-code
24178 field is still 0xE. Many of the Thumb variants can be executed
24179 conditionally, so this is checked separately. */
24180 #define TUE(mnem, op, top, nops, ops, ae, te) \
24181 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24182 THUMB_VARIANT, do_##ae, do_##te, 0 }
24184 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
24185 Used by mnemonics that have very minimal differences in the encoding for
24186 ARM and Thumb variants and can be handled in a common function. */
24187 #define TUEc(mnem, op, top, nops, ops, en) \
24188 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
24189 THUMB_VARIANT, do_##en, do_##en, 0 }
24191 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
24192 condition code field. */
24193 #define TUF(mnem, op, top, nops, ops, ae, te) \
24194 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
24195 THUMB_VARIANT, do_##ae, do_##te, 0 }
24197 /* ARM-only variants of all the above. */
24198 #define CE(mnem, op, nops, ops, ae) \
24199 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24201 #define C3(mnem, op, nops, ops, ae) \
24202 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24204 /* Thumb-only variants of TCE and TUE. */
24205 #define ToC(mnem, top, nops, ops, te) \
24206 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24209 #define ToU(mnem, top, nops, ops, te) \
24210 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
24213 /* T_MNEM_xyz enumerator variants of ToC. */
24214 #define toC(mnem, top, nops, ops, te) \
24215 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
24218 /* T_MNEM_xyz enumerator variants of ToU. */
24219 #define toU(mnem, top, nops, ops, te) \
24220 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
24223 /* Legacy mnemonics that always have conditional infix after the third
24225 #define CL(mnem, op, nops, ops, ae) \
24226 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24227 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24229 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
24230 #define cCE(mnem, op, nops, ops, ae) \
24231 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24233 /* mov instructions that are shared between coprocessor and MVE. */
24234 #define mcCE(mnem, op, nops, ops, ae) \
24235 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
24237 /* Legacy coprocessor instructions where conditional infix and conditional
24238 suffix are ambiguous. For consistency this includes all FPA instructions,
24239 not just the potentially ambiguous ones. */
24240 #define cCL(mnem, op, nops, ops, ae) \
24241 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
24242 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24244 /* Coprocessor, takes either a suffix or a position-3 infix
24245 (for an FPA corner case). */
24246 #define C3E(mnem, op, nops, ops, ae) \
24247 { mnem, OPS##nops ops, OT_csuf_or_in3, \
24248 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
24250 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
24251 { m1 #m2 m3, OPS##nops ops, \
24252 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
24253 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24255 #define CM(m1, m2, op, nops, ops, ae) \
24256 xCM_ (m1, , m2, op, nops, ops, ae), \
24257 xCM_ (m1, eq, m2, op, nops, ops, ae), \
24258 xCM_ (m1, ne, m2, op, nops, ops, ae), \
24259 xCM_ (m1, cs, m2, op, nops, ops, ae), \
24260 xCM_ (m1, hs, m2, op, nops, ops, ae), \
24261 xCM_ (m1, cc, m2, op, nops, ops, ae), \
24262 xCM_ (m1, ul, m2, op, nops, ops, ae), \
24263 xCM_ (m1, lo, m2, op, nops, ops, ae), \
24264 xCM_ (m1, mi, m2, op, nops, ops, ae), \
24265 xCM_ (m1, pl, m2, op, nops, ops, ae), \
24266 xCM_ (m1, vs, m2, op, nops, ops, ae), \
24267 xCM_ (m1, vc, m2, op, nops, ops, ae), \
24268 xCM_ (m1, hi, m2, op, nops, ops, ae), \
24269 xCM_ (m1, ls, m2, op, nops, ops, ae), \
24270 xCM_ (m1, ge, m2, op, nops, ops, ae), \
24271 xCM_ (m1, lt, m2, op, nops, ops, ae), \
24272 xCM_ (m1, gt, m2, op, nops, ops, ae), \
24273 xCM_ (m1, le, m2, op, nops, ops, ae), \
24274 xCM_ (m1, al, m2, op, nops, ops, ae)
24276 #define UE(mnem, op, nops, ops, ae) \
24277 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24279 #define UF(mnem, op, nops, ops, ae) \
24280 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
24282 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
24283 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
24284 use the same encoding function for each. */
24285 #define NUF(mnem, op, nops, ops, enc) \
24286 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24287 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24289 /* Neon data processing, version which indirects through neon_enc_tab for
24290 the various overloaded versions of opcodes. */
24291 #define nUF(mnem, op, nops, ops, enc) \
24292 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24293 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
24295 /* Neon insn with conditional suffix for the ARM version, non-overloaded
24297 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24298 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
24299 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24301 #define NCE(mnem, op, nops, ops, enc) \
24302 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24304 #define NCEF(mnem, op, nops, ops, enc) \
24305 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24307 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
24308 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
24309 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
24310 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
24312 #define nCE(mnem, op, nops, ops, enc) \
24313 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
24315 #define nCEF(mnem, op, nops, ops, enc) \
24316 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
24319 #define mCEF(mnem, op, nops, ops, enc) \
24320 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
24321 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24324 /* nCEF but for MVE predicated instructions. */
24325 #define mnCEF(mnem, op, nops, ops, enc) \
24326 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24328 /* nCE but for MVE predicated instructions. */
24329 #define mnCE(mnem, op, nops, ops, enc) \
24330 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24332 /* NUF but for potentially MVE predicated instructions. */
24333 #define MNUF(mnem, op, nops, ops, enc) \
24334 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
24335 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24337 /* nUF but for potentially MVE predicated instructions. */
24338 #define mnUF(mnem, op, nops, ops, enc) \
24339 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
24340 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
24342 /* ToC but for potentially MVE predicated instructions. */
24343 #define mToC(mnem, top, nops, ops, te) \
24344 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
24347 /* NCE but for MVE predicated instructions. */
24348 #define MNCE(mnem, op, nops, ops, enc) \
24349 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
24351 /* NCEF but for MVE predicated instructions. */
24352 #define MNCEF(mnem, op, nops, ops, enc) \
24353 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
24356 static const struct asm_opcode insns
[] =
24358 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
24359 #define THUMB_VARIANT & arm_ext_v4t
24360 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24361 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24362 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24363 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24364 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24365 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
24366 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24367 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
24368 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24369 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24370 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24371 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24372 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24373 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
24374 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24375 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
24377 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
24378 for setting PSR flag bits. They are obsolete in V6 and do not
24379 have Thumb equivalents. */
24380 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24381 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24382 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
24383 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24384 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
24385 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
24386 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24387 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24388 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
24390 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
24391 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
24392 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24393 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
24395 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
24396 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24397 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
24399 OP_ADDRGLDR
),ldst
, t_ldst
),
24400 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
24402 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24403 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24404 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24405 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24406 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24407 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24409 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
24410 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
24413 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
24414 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
24415 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
24416 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
24418 /* Thumb-compatibility pseudo ops. */
24419 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24420 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24421 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24422 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24423 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24424 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24425 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24426 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
24427 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
24428 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
24429 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
24430 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
24432 /* These may simplify to neg. */
24433 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24434 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
24436 #undef THUMB_VARIANT
24437 #define THUMB_VARIANT & arm_ext_os
24439 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24440 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
24442 #undef THUMB_VARIANT
24443 #define THUMB_VARIANT & arm_ext_v6
24445 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
24447 /* V1 instructions with no Thumb analogue prior to V6T2. */
24448 #undef THUMB_VARIANT
24449 #define THUMB_VARIANT & arm_ext_v6t2
24451 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24452 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
24453 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
24455 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24456 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24457 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
24458 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
24460 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24461 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24463 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24464 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
24466 /* V1 instructions with no Thumb analogue at all. */
24467 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
24468 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
24470 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24471 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
24472 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24473 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
24474 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24475 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
24476 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24477 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
24480 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
24481 #undef THUMB_VARIANT
24482 #define THUMB_VARIANT & arm_ext_v4t
24484 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24485 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
24487 #undef THUMB_VARIANT
24488 #define THUMB_VARIANT & arm_ext_v6t2
24490 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24491 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
24493 /* Generic coprocessor instructions. */
24494 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24495 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24496 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24497 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24498 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24499 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24500 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24503 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
24505 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24506 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
24509 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
24510 #undef THUMB_VARIANT
24511 #define THUMB_VARIANT & arm_ext_msr
24513 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
24514 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
24517 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
24518 #undef THUMB_VARIANT
24519 #define THUMB_VARIANT & arm_ext_v6t2
24521 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24522 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24523 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24524 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24525 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24526 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24527 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
24528 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
24531 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
24532 #undef THUMB_VARIANT
24533 #define THUMB_VARIANT & arm_ext_v4t
24535 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24536 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24537 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24538 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24539 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24540 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
24543 #define ARM_VARIANT & arm_ext_v4t_5
24545 /* ARM Architecture 4T. */
24546 /* Note: bx (and blx) are required on V5, even if the processor does
24547 not support Thumb. */
24548 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
24551 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
24552 #undef THUMB_VARIANT
24553 #define THUMB_VARIANT & arm_ext_v5t
24555 /* Note: blx has 2 variants; the .value coded here is for
24556 BLX(2). Only this variant has conditional execution. */
24557 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
24558 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
24560 #undef THUMB_VARIANT
24561 #define THUMB_VARIANT & arm_ext_v6t2
24563 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
24564 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24565 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24566 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24567 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
24568 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
24569 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24570 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
24573 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
24574 #undef THUMB_VARIANT
24575 #define THUMB_VARIANT & arm_ext_v5exp
24577 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24578 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24579 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24580 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24582 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24583 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
24585 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24586 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24587 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24588 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
24590 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24591 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24592 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24593 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24595 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24596 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24598 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24599 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24600 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24601 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
24604 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
24605 #undef THUMB_VARIANT
24606 #define THUMB_VARIANT & arm_ext_v6t2
24608 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
24609 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
24611 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
24612 ADDRGLDRS
), ldrd
, t_ldstd
),
24614 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24615 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24618 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
24620 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
24623 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
24624 #undef THUMB_VARIANT
24625 #define THUMB_VARIANT & arm_ext_v6
24627 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24628 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
24629 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24630 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24631 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
24632 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24633 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24634 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24635 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24636 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
24638 #undef THUMB_VARIANT
24639 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24641 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
24642 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24644 #undef THUMB_VARIANT
24645 #define THUMB_VARIANT & arm_ext_v6t2
24647 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24648 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
24650 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
24651 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
24653 /* ARM V6 not included in V7M. */
24654 #undef THUMB_VARIANT
24655 #define THUMB_VARIANT & arm_ext_v6_notm
24656 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24657 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24658 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
24659 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
24660 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24661 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
24662 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
24663 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
24664 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
24665 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24666 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24667 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
24668 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24669 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
24670 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
24671 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
24672 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24673 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
24674 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
24676 /* ARM V6 not included in V7M (eg. integer SIMD). */
24677 #undef THUMB_VARIANT
24678 #define THUMB_VARIANT & arm_ext_v6_dsp
24679 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
24680 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
24681 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24682 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24683 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24684 /* Old name for QASX. */
24685 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24686 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24687 /* Old name for QSAX. */
24688 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24689 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24690 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24691 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24692 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24693 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24694 /* Old name for SASX. */
24695 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24696 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24697 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24698 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24699 /* Old name for SHASX. */
24700 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24701 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24702 /* Old name for SHSAX. */
24703 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24704 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24705 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24706 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24707 /* Old name for SSAX. */
24708 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24709 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24710 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24711 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24712 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24713 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24714 /* Old name for UASX. */
24715 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24716 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24717 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24718 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24719 /* Old name for UHASX. */
24720 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24721 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24722 /* Old name for UHSAX. */
24723 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24724 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24725 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24726 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24727 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24728 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24729 /* Old name for UQASX. */
24730 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24731 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24732 /* Old name for UQSAX. */
24733 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24734 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24735 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24736 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24737 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24738 /* Old name for USAX. */
24739 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24740 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24741 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24742 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24743 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24744 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24745 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24746 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24747 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
24748 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
24749 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
24750 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24751 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24752 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24753 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24754 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24755 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24756 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24757 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
24758 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24759 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24760 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24761 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24762 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24763 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24764 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24765 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24766 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24767 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24768 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
24769 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
24770 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
24771 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
24772 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
24775 #define ARM_VARIANT & arm_ext_v6k_v6t2
24776 #undef THUMB_VARIANT
24777 #define THUMB_VARIANT & arm_ext_v6k_v6t2
24779 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
24780 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
24781 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
24782 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
24784 #undef THUMB_VARIANT
24785 #define THUMB_VARIANT & arm_ext_v6_notm
24786 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
24788 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
24789 RRnpcb
), strexd
, t_strexd
),
24791 #undef THUMB_VARIANT
24792 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24793 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
24795 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
24797 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24799 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
24801 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
24804 #define ARM_VARIANT & arm_ext_sec
24805 #undef THUMB_VARIANT
24806 #define THUMB_VARIANT & arm_ext_sec
24808 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
24811 #define ARM_VARIANT & arm_ext_virt
24812 #undef THUMB_VARIANT
24813 #define THUMB_VARIANT & arm_ext_virt
24815 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
24816 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
24819 #define ARM_VARIANT & arm_ext_pan
24820 #undef THUMB_VARIANT
24821 #define THUMB_VARIANT & arm_ext_pan
24823 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
24826 #define ARM_VARIANT & arm_ext_v6t2
24827 #undef THUMB_VARIANT
24828 #define THUMB_VARIANT & arm_ext_v6t2
24830 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
24831 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
24832 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24833 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
24835 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
24836 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
24838 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24839 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24840 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24841 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
24844 #define ARM_VARIANT & arm_ext_v3
24845 #undef THUMB_VARIANT
24846 #define THUMB_VARIANT & arm_ext_v6t2
24848 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
24849 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
24850 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
24853 #define ARM_VARIANT & arm_ext_v6t2
24854 #undef THUMB_VARIANT
24855 #define THUMB_VARIANT & arm_ext_v6t2_v8m
24856 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24857 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
24859 /* Thumb-only instructions. */
24861 #define ARM_VARIANT NULL
24862 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
24863 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
24865 /* ARM does not really have an IT instruction, so always allow it.
24866 The opcode is copied from Thumb in order to allow warnings in
24867 -mimplicit-it=[never | arm] modes. */
24869 #define ARM_VARIANT & arm_ext_v1
24870 #undef THUMB_VARIANT
24871 #define THUMB_VARIANT & arm_ext_v6t2
24873 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
24874 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
24875 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
24876 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
24877 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
24878 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
24879 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
24880 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
24881 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
24882 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
24883 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
24884 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
24885 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
24886 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
24887 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
24888 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
24889 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24890 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
24892 /* Thumb2 only instructions. */
24894 #define ARM_VARIANT NULL
24896 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24897 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
24898 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24899 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
24900 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
24901 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
24903 /* Hardware division instructions. */
24905 #define ARM_VARIANT & arm_ext_adiv
24906 #undef THUMB_VARIANT
24907 #define THUMB_VARIANT & arm_ext_div
24909 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24910 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
24912 /* ARM V6M/V7 instructions. */
24914 #define ARM_VARIANT & arm_ext_barrier
24915 #undef THUMB_VARIANT
24916 #define THUMB_VARIANT & arm_ext_barrier
24918 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24919 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24920 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24922 /* ARM V7 instructions. */
24924 #define ARM_VARIANT & arm_ext_v7
24925 #undef THUMB_VARIANT
24926 #define THUMB_VARIANT & arm_ext_v7
24928 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24929 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24932 #define ARM_VARIANT & arm_ext_mp
24933 #undef THUMB_VARIANT
24934 #define THUMB_VARIANT & arm_ext_mp
24936 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24938 /* AArchv8 instructions. */
24940 #define ARM_VARIANT & arm_ext_v8
24942 /* Instructions shared between armv8-a and armv8-m. */
24943 #undef THUMB_VARIANT
24944 #define THUMB_VARIANT & arm_ext_atomics
24946 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24947 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24948 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24949 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24950 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24951 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24952 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24953 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24954 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24955 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24957 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24959 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24961 #undef THUMB_VARIANT
24962 #define THUMB_VARIANT & arm_ext_v8
24964 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24965 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24967 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24970 /* Defined in V8 but is in undefined encoding space for earlier
24971 architectures. However earlier architectures are required to treat
24972 this instuction as a semihosting trap as well. Hence while not explicitly
24973 defined as such, it is in fact correct to define the instruction for all
24975 #undef THUMB_VARIANT
24976 #define THUMB_VARIANT & arm_ext_v1
24978 #define ARM_VARIANT & arm_ext_v1
24979 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24981 /* ARMv8 T32 only. */
24983 #define ARM_VARIANT NULL
24984 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24985 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24986 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24988 /* FP for ARMv8. */
24990 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24991 #undef THUMB_VARIANT
24992 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24994 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24995 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24996 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24997 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24998 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24999 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
25000 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
25001 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
25002 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
25003 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
25004 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
25006 /* Crypto v1 extensions. */
25008 #define ARM_VARIANT & fpu_crypto_ext_armv8
25009 #undef THUMB_VARIANT
25010 #define THUMB_VARIANT & fpu_crypto_ext_armv8
25012 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
25013 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
25014 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
25015 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
25016 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
25017 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
25018 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
25019 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
25020 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
25021 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
25022 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
25023 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
25024 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
25025 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
25028 #define ARM_VARIANT & arm_ext_crc
25029 #undef THUMB_VARIANT
25030 #define THUMB_VARIANT & arm_ext_crc
25031 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
25032 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
25033 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
25034 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
25035 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
25036 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
25038 /* ARMv8.2 RAS extension. */
25040 #define ARM_VARIANT & arm_ext_ras
25041 #undef THUMB_VARIANT
25042 #define THUMB_VARIANT & arm_ext_ras
25043 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
25046 #define ARM_VARIANT & arm_ext_v8_3
25047 #undef THUMB_VARIANT
25048 #define THUMB_VARIANT & arm_ext_v8_3
25049 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
25052 #define ARM_VARIANT & fpu_neon_ext_dotprod
25053 #undef THUMB_VARIANT
25054 #define THUMB_VARIANT & fpu_neon_ext_dotprod
25055 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
25056 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
25059 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
25060 #undef THUMB_VARIANT
25061 #define THUMB_VARIANT NULL
25063 cCE("wfs", e200110
, 1, (RR
), rd
),
25064 cCE("rfs", e300110
, 1, (RR
), rd
),
25065 cCE("wfc", e400110
, 1, (RR
), rd
),
25066 cCE("rfc", e500110
, 1, (RR
), rd
),
25068 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25069 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25070 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25071 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25073 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25074 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25075 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25076 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
25078 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
25079 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
25080 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
25081 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
25082 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
25083 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
25084 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
25085 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
25086 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
25087 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
25088 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
25089 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
25091 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
25092 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
25093 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
25094 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
25095 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
25096 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
25097 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
25098 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
25099 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
25100 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
25101 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
25102 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
25104 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
25105 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
25106 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
25107 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
25108 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
25109 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
25110 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
25111 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
25112 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
25113 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
25114 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
25115 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
25117 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
25118 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
25119 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
25120 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
25121 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
25122 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
25123 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
25124 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
25125 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
25126 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
25127 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
25128 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
25130 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
25131 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
25132 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
25133 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
25134 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
25135 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
25136 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
25137 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
25138 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
25139 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
25140 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
25141 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
25143 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
25144 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
25145 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
25146 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
25147 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
25148 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
25149 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
25150 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
25151 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
25152 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
25153 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
25154 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
25156 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
25157 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
25158 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
25159 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
25160 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
25161 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
25162 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
25163 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
25164 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
25165 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
25166 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
25167 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
25169 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
25170 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
25171 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
25172 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
25173 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
25174 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
25175 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
25176 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
25177 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
25178 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
25179 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
25180 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
25182 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
25183 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
25184 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
25185 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
25186 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
25187 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
25188 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
25189 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
25190 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
25191 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
25192 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
25193 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
25195 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
25196 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
25197 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
25198 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
25199 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
25200 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
25201 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
25202 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
25203 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
25204 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
25205 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
25206 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
25208 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
25209 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
25210 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
25211 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
25212 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
25213 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
25214 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
25215 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
25216 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
25217 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
25218 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
25219 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
25221 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
25222 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
25223 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
25224 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
25225 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
25226 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
25227 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
25228 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
25229 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
25230 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
25231 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
25232 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
25234 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
25235 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
25236 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
25237 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
25238 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
25239 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
25240 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
25241 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
25242 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
25243 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
25244 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
25245 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
25247 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
25248 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
25249 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
25250 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
25251 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
25252 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
25253 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
25254 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
25255 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
25256 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
25257 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
25258 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
25260 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
25261 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
25262 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
25263 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
25264 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
25265 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
25266 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
25267 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
25268 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
25269 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
25270 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
25271 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
25273 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
25274 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
25275 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
25276 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
25277 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
25278 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
25279 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
25280 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
25281 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
25282 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
25283 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
25284 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
25286 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25287 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25288 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25289 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25290 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25291 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25292 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25293 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25294 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25295 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25296 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25297 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25299 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25300 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25301 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25302 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25303 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25304 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25305 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25306 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25307 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25308 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25309 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25310 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25312 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25313 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25314 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25315 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25316 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25317 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25318 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25319 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25320 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25321 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25322 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25323 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25325 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25326 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25327 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25328 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25329 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25330 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25331 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25332 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25333 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25334 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25335 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25336 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25338 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25339 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25340 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25341 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25342 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25343 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25344 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25345 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25346 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25347 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25348 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25349 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25351 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25352 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25353 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25354 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25355 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25356 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25357 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25358 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25359 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25360 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25361 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25362 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25364 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25365 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25366 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25367 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25368 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25369 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25370 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25371 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25372 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25373 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25374 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25375 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25377 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25378 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25379 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25380 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25381 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25382 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25383 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25384 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25385 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25386 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25387 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25388 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25390 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25391 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25392 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25393 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25394 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25395 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25396 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25397 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25398 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25399 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25400 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25401 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25403 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25404 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25405 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25406 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25407 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25408 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25409 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25410 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25411 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25412 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25413 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25414 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25416 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25417 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25418 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25419 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25420 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25421 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25422 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25423 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25424 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25425 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25426 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25427 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25429 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25430 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25431 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25432 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25433 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25434 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25435 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25436 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25437 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25438 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25439 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25440 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25442 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25443 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25444 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25445 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25446 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25447 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25448 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25449 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25450 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25451 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25452 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25453 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
25455 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25456 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25457 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25458 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
25460 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
25461 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
25462 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
25463 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
25464 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
25465 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
25466 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
25467 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
25468 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
25469 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
25470 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
25471 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
25473 /* The implementation of the FIX instruction is broken on some
25474 assemblers, in that it accepts a precision specifier as well as a
25475 rounding specifier, despite the fact that this is meaningless.
25476 To be more compatible, we accept it as well, though of course it
25477 does not set any bits. */
25478 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
25479 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
25480 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
25481 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
25482 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
25483 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
25484 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
25485 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
25486 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
25487 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
25488 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
25489 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
25490 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
25492 /* Instructions that were new with the real FPA, call them V2. */
25494 #define ARM_VARIANT & fpu_fpa_ext_v2
25496 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25497 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25498 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25499 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25500 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25501 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
25504 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
25505 #undef THUMB_VARIANT
25506 #define THUMB_VARIANT & arm_ext_v6t2
25507 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
25508 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
25509 mcCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25510 mcCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
25511 mcCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25512 mcCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
25514 /* Memory operations. */
25515 mcCE(fldmias
, c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25516 mcCE(fldmdbs
, d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25517 mcCE(fstmias
, c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25518 mcCE(fstmdbs
, d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25519 #undef THUMB_VARIANT
25521 /* Moves and type conversions. */
25522 cCE("fmstat", ef1fa10
, 0, (), noargs
),
25523 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25524 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25525 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25526 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25527 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25528 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25529 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
25530 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
25532 /* Memory operations. */
25533 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25534 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25535 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25536 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25537 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25538 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25539 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
25540 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
25541 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25542 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
25543 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25544 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
25546 /* Monadic operations. */
25547 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25548 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25549 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25551 /* Dyadic operations. */
25552 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25553 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25554 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25555 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25556 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25557 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25558 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25559 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25560 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25563 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25564 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
25565 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25566 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
25568 /* Double precision load/store are still present on single precision
25569 implementations. */
25570 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25571 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25572 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25573 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25574 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25575 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
25576 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25577 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
25580 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
25582 /* Moves and type conversions. */
25583 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25584 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25585 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25586 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
25587 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25588 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
25589 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25590 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
25591 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25592 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25593 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25594 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
25596 /* Monadic operations. */
25597 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25598 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25599 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25601 /* Dyadic operations. */
25602 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25603 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25604 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25605 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25606 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25607 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25608 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25609 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25610 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25613 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25614 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
25615 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25616 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
25618 /* Instructions which may belong to either the Neon or VFP instruction sets.
25619 Individual encoder functions perform additional architecture checks. */
25621 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25622 #undef THUMB_VARIANT
25623 #define THUMB_VARIANT & arm_ext_v6t2
25625 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25626 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25627 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25628 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25629 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25630 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
25632 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
25633 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
25635 #undef THUMB_VARIANT
25636 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
25638 /* These mnemonics are unique to VFP. */
25639 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
25640 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
25641 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25642 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25643 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25644 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
25646 /* Mnemonics shared by Neon and VFP. */
25647 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
25649 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
25650 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
25651 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
25652 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
25655 /* NOTE: All VMOV encoding is special-cased! */
25656 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
25658 #undef THUMB_VARIANT
25659 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
25660 by different feature bits. Since we are setting the Thumb guard, we can
25661 require Thumb-1 which makes it a nop guard and set the right feature bit in
25662 do_vldr_vstr (). */
25663 #define THUMB_VARIANT & arm_ext_v4t
25664 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25665 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
25668 #define ARM_VARIANT & arm_ext_fp16
25669 #undef THUMB_VARIANT
25670 #define THUMB_VARIANT & arm_ext_fp16
25671 /* New instructions added from v8.2, allowing the extraction and insertion of
25672 the upper 16 bits of a 32-bit vector register. */
25673 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
25674 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
25676 /* New backported fma/fms instructions optional in v8.2. */
25677 NUF (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
25678 NUF (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
25680 #undef THUMB_VARIANT
25681 #define THUMB_VARIANT & fpu_neon_ext_v1
25683 #define ARM_VARIANT & fpu_neon_ext_v1
25685 /* Data processing with three registers of the same length. */
25686 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
25687 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
25688 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
25689 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25690 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25691 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
25692 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
25693 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25694 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
25695 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25696 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
25697 /* If not immediate, fall back to neon_dyadic_i64_su.
25698 shl should accept I8 I16 I32 I64,
25699 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
25700 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
25701 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
25702 /* Logic ops, types optional & ignored. */
25703 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25704 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25705 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25706 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
25707 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
25708 /* Bitfield ops, untyped. */
25709 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25710 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25711 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25712 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25713 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
25714 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
25715 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
25716 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25717 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25718 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
25719 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
25720 back to neon_dyadic_if_su. */
25721 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25722 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25723 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
25724 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
25725 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25726 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25727 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
25728 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
25729 /* Comparison. Type I8 I16 I32 F32. */
25730 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
25731 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
25732 /* As above, D registers only. */
25733 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25734 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
25735 /* Int and float variants, signedness unimportant. */
25736 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25737 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
25738 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
25739 /* Add/sub take types I8 I16 I32 I64 F32. */
25740 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25741 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
25742 /* vtst takes sizes 8, 16, 32. */
25743 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
25744 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
25745 /* VMUL takes I8 I16 I32 F32 P8. */
25746 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
25747 /* VQD{R}MULH takes S16 S32. */
25748 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25749 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
25750 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25751 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25752 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
25753 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
25754 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25755 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25756 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
25757 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
25758 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25759 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25760 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
25761 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
25762 /* ARM v8.1 extension. */
25763 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25764 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
25765 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
25767 /* Two address, int/float. Types S8 S16 S32 F32. */
25768 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25769 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
25771 /* Data processing with two registers and a shift amount. */
25772 /* Right shifts, and variants with rounding.
25773 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
25774 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25775 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
25776 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25777 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25778 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
25779 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
25780 /* Shift and insert. Sizes accepted 8 16 32 64. */
25781 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
25782 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
25783 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
25784 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
25785 /* Right shift immediate, saturating & narrowing, with rounding variants.
25786 Types accepted S16 S32 S64 U16 U32 U64. */
25787 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25788 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
25789 /* As above, unsigned. Types accepted S16 S32 S64. */
25790 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25791 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
25792 /* Right shift narrowing. Types accepted I16 I32 I64. */
25793 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25794 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
25795 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
25796 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
25797 /* CVT with optional immediate for fixed-point variant. */
25798 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
25800 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
25802 /* Data processing, three registers of different lengths. */
25803 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
25804 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
25805 /* If not scalar, fall back to neon_dyadic_long.
25806 Vector types as above, scalar types S16 S32 U16 U32. */
25807 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25808 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
25809 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
25810 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25811 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
25812 /* Dyadic, narrowing insns. Types I16 I32 I64. */
25813 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25814 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25815 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25816 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
25817 /* Saturating doubling multiplies. Types S16 S32. */
25818 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25819 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25820 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
25821 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
25822 S16 S32 U16 U32. */
25823 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
25825 /* Extract. Size 8. */
25826 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
25827 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
25829 /* Two registers, miscellaneous. */
25830 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
25831 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
25832 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
25833 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
25834 /* Vector replicate. Sizes 8 16 32. */
25835 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
25836 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
25837 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
25838 /* VMOVN. Types I16 I32 I64. */
25839 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
25840 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
25841 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
25842 /* VQMOVUN. Types S16 S32 S64. */
25843 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
25844 /* VZIP / VUZP. Sizes 8 16 32. */
25845 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25846 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25847 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
25848 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
25849 /* VQABS / VQNEG. Types S8 S16 S32. */
25850 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25851 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
25852 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
25853 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25854 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
25855 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
25856 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
25857 /* Reciprocal estimates. Types U32 F16 F32. */
25858 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25859 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
25860 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
25861 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
25862 /* VCLS. Types S8 S16 S32. */
25863 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
25864 /* VCLZ. Types I8 I16 I32. */
25865 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
25866 /* VCNT. Size 8. */
25867 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
25868 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
25869 /* Two address, untyped. */
25870 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
25871 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
25872 /* VTRN. Sizes 8 16 32. */
25873 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
25874 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
25876 /* Table lookup. Size 8. */
25877 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25878 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
25880 #undef THUMB_VARIANT
25881 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
25883 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
25885 /* Neon element/structure load/store. */
25886 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25887 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25888 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25889 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25890 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25891 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25892 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25893 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
25895 #undef THUMB_VARIANT
25896 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
25898 #define ARM_VARIANT & fpu_vfp_ext_v3xd
25899 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
25900 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25901 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25902 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25903 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25904 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25905 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25906 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
25907 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
25909 #undef THUMB_VARIANT
25910 #define THUMB_VARIANT & fpu_vfp_ext_v3
25912 #define ARM_VARIANT & fpu_vfp_ext_v3
25914 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
25915 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25916 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25917 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25918 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25919 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25920 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25921 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25922 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25925 #define ARM_VARIANT & fpu_vfp_ext_fma
25926 #undef THUMB_VARIANT
25927 #define THUMB_VARIANT & fpu_vfp_ext_fma
25928 /* Mnemonics shared by Neon, VFP, MVE and BF16. These are included in the
25929 VFP FMA variant; NEON and VFP FMA always includes the NEON
25930 FMA instructions. */
25931 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25932 TUF ("vfmat", c300850
, fc300850
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), mve_vfma
, mve_vfma
),
25933 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25935 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25936 the v form should always be used. */
25937 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25938 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25939 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25940 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25941 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25942 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25944 #undef THUMB_VARIANT
25946 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25948 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25949 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25950 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25951 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25952 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25953 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25954 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25955 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25958 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25960 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25961 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25962 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25963 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25964 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25965 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25966 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25967 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25968 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25969 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25970 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25971 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25972 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25973 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25974 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25975 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25976 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25977 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25978 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25979 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25980 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25981 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25982 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25983 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25984 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25985 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25986 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25987 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25988 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25989 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25990 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25991 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25992 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25993 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25994 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25995 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25996 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25997 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25998 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25999 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26000 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26001 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26002 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26003 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26004 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26005 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26006 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
26007 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26008 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26009 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26010 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26011 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26012 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26013 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26014 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26015 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26016 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26017 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26018 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26019 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26020 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26021 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26022 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26023 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26024 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26025 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26026 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26027 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26028 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26029 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26030 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26031 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26032 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26033 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26034 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26035 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26036 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26037 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26038 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26039 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26040 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26041 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26042 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26043 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26044 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26045 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26046 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26047 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26048 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
26049 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26050 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26051 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26052 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26053 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26054 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26055 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26056 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26057 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26058 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26059 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26060 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26061 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26062 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26063 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26064 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26065 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26066 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26067 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26068 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26069 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26070 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
26071 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26072 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26073 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26074 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26075 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26076 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26077 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26078 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26079 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26080 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26081 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26082 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26083 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26084 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26085 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26086 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26087 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
26088 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
26089 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26090 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
26091 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
26092 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
26093 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26094 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26095 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26096 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26097 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26098 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26099 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26100 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26101 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26102 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26103 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26104 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26105 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26106 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26107 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
26108 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26109 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26110 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26111 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26112 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26113 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26114 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26115 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26116 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
26117 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26118 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26119 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26120 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26121 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
26124 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
26126 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
26127 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
26128 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
26129 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26130 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26131 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
26132 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26133 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26134 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26135 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26136 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26137 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26138 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26139 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26140 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26141 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26142 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26143 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26144 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26145 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26146 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
26147 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26148 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26149 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26150 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26151 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26152 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26153 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26154 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26155 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26156 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26157 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26158 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26159 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26160 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26161 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26162 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26163 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26164 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26165 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26166 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26167 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26168 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26169 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26170 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26171 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26172 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26173 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26174 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26175 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26176 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26177 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26178 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26179 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26180 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26181 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26182 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
26185 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
26187 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26188 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26189 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26190 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26191 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
26192 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
26193 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
26194 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
26195 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
26196 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
26197 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
26198 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
26199 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
26200 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
26201 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
26202 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
26203 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
26204 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
26205 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
26206 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
26207 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
26208 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
26209 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
26210 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
26211 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
26212 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
26213 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
26214 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
26215 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
26216 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
26217 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
26218 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
26219 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
26220 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
26221 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
26222 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
26223 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
26224 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
26225 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
26226 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
26227 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
26228 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
26229 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
26230 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
26231 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
26232 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
26233 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
26234 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
26235 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
26236 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
26237 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
26238 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
26239 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
26240 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
26241 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26242 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26243 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26244 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26245 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
26246 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
26247 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
26248 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
26249 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
26250 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
26251 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26252 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26253 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26254 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26255 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26256 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
26257 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26258 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
26259 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26260 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
26261 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26262 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
26264 /* ARMv8.5-A instructions. */
26266 #define ARM_VARIANT & arm_ext_sb
26267 #undef THUMB_VARIANT
26268 #define THUMB_VARIANT & arm_ext_sb
26269 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
26272 #define ARM_VARIANT & arm_ext_predres
26273 #undef THUMB_VARIANT
26274 #define THUMB_VARIANT & arm_ext_predres
26275 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
26276 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
26277 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
26279 /* ARMv8-M instructions. */
26281 #define ARM_VARIANT NULL
26282 #undef THUMB_VARIANT
26283 #define THUMB_VARIANT & arm_ext_v8m
26284 ToU("sg", e97fe97f
, 0, (), noargs
),
26285 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
26286 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
26287 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
26288 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
26289 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
26290 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
26292 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
26293 instructions behave as nop if no VFP is present. */
26294 #undef THUMB_VARIANT
26295 #define THUMB_VARIANT & arm_ext_v8m_main
26296 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
26297 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
26299 /* Armv8.1-M Mainline instructions. */
26300 #undef THUMB_VARIANT
26301 #define THUMB_VARIANT & arm_ext_v8_1m_main
26302 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26303 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26304 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
26305 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26306 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
26307 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
26308 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26309 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26310 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
26312 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
26313 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
26314 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26315 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
26316 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
26318 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
26319 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
26320 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
26322 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
26323 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
26325 #undef THUMB_VARIANT
26326 #define THUMB_VARIANT & mve_ext
26327 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26328 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26329 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
26330 ToC("uqrshll", ea51010d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26331 ToC("sqrshrl", ea51012d
, 4, (RRe
, RRo
, I48_I64
, RRnpcsp
), mve_scalar_shift1
),
26332 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26333 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26334 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26335 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
26336 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26337 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
26338 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26339 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26340 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26341 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
26343 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26344 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26345 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26346 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26347 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26348 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26349 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26350 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26351 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26352 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26353 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26354 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26355 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26356 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26357 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
26359 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
26360 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
26361 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
26362 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
26363 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
26364 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
26365 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
26366 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
26367 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
26368 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
26369 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
26370 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
26371 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
26372 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
26373 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
26375 /* MVE and MVE FP only. */
26376 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
26377 mCEF(vctp
, _vctp
, 1, (RRnpc
), mve_vctp
),
26378 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26379 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
26380 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26381 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
26382 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
26383 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
26384 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26385 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26386 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26387 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26388 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26389 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26390 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26391 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26392 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26393 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
26395 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26396 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26397 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26398 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26399 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26400 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26401 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26402 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
26403 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26404 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26405 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26406 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
26407 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26408 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26409 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26410 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26411 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26412 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26413 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26414 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
26416 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
26417 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
26418 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
26419 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26420 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
26421 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
26422 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
26423 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26424 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26425 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
26426 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
26427 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26428 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
26429 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
26430 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
26431 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
26432 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
26434 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26435 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26436 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26437 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26438 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26439 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26440 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26441 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26442 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26443 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
26444 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26445 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26446 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26447 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26448 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26449 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26450 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26451 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26452 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26453 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
26455 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
26456 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26457 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
26458 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
26459 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
26461 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26462 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26463 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26464 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26465 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26466 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26467 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26468 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
26469 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26470 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26471 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
26472 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26473 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
26474 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26475 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26476 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26477 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
26479 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26480 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26481 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26482 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26483 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26484 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26485 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26486 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26487 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26488 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26489 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26490 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
26492 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
26493 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26494 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
26496 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
26497 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
26498 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
26499 toU("lctp", _lctp
, 0, (), t_loloop
),
26501 #undef THUMB_VARIANT
26502 #define THUMB_VARIANT & mve_fp_ext
26503 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
26504 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
26505 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26506 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
26507 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26508 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26509 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26510 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
26513 #define ARM_VARIANT & fpu_vfp_ext_v1
26514 #undef THUMB_VARIANT
26515 #define THUMB_VARIANT & arm_ext_v6t2
26516 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
26517 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
26519 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
26522 #define ARM_VARIANT & fpu_vfp_ext_v1xd
26524 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
26525 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
26526 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
26527 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
26529 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
26530 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26531 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
26533 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26534 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
26536 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
26537 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
26539 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26540 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
26543 #define ARM_VARIANT & fpu_vfp_ext_v2
26545 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
26546 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
26547 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
26548 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
26551 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
26552 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
26553 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
26554 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
26555 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
26556 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26557 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
26560 #define ARM_VARIANT & fpu_neon_ext_v1
26561 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26562 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
26563 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
26564 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
26565 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26566 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26567 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26568 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
26569 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
26570 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
26571 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
26572 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
26573 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26574 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
26575 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
26576 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26577 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
26578 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26579 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
26580 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
26581 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26582 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
26583 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
26584 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26585 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
26586 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26587 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
26588 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26589 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
26590 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
26591 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
26592 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26593 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26594 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
26595 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
26596 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
26597 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
26600 #define ARM_VARIANT & arm_ext_v8_3
26601 #undef THUMB_VARIANT
26602 #define THUMB_VARIANT & arm_ext_v6t2_v8m
26603 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
26604 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
26607 #define ARM_VARIANT &arm_ext_bf16
26608 #undef THUMB_VARIANT
26609 #define THUMB_VARIANT &arm_ext_bf16
26610 TUF ("vdot", c000d00
, fc000d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vdot
, vdot
),
26611 TUF ("vmmla", c000c40
, fc000c40
, 3, (RNQ
, RNQ
, RNQ
), vmmla
, vmmla
),
26612 TUF ("vfmab", c300810
, fc300810
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), bfloat_vfma
, bfloat_vfma
),
26615 #define ARM_VARIANT &arm_ext_i8mm
26616 #undef THUMB_VARIANT
26617 #define THUMB_VARIANT &arm_ext_i8mm
26618 TUF ("vsmmla", c200c40
, fc200c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26619 TUF ("vummla", c200c50
, fc200c50
, 3, (RNQ
, RNQ
, RNQ
), vummla
, vummla
),
26620 TUF ("vusmmla", ca00c40
, fca00c40
, 3, (RNQ
, RNQ
, RNQ
), vsmmla
, vsmmla
),
26621 TUF ("vusdot", c800d00
, fc800d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), vusdot
, vusdot
),
26622 TUF ("vsudot", c800d10
, fc800d10
, 3, (RNDQ
, RNDQ
, RNSC
), vsudot
, vsudot
),
26625 #undef THUMB_VARIANT
26626 #define THUMB_VARIANT &arm_ext_cde
26627 ToC ("cx1", ee000000
, 3, (RCP
, APSR_RR
, I8191
), cx1
),
26628 ToC ("cx1a", fe000000
, 3, (RCP
, APSR_RR
, I8191
), cx1a
),
26629 ToC ("cx1d", ee000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1d
),
26630 ToC ("cx1da", fe000040
, 4, (RCP
, RR
, APSR_RR
, I8191
), cx1da
),
26632 ToC ("cx2", ee400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2
),
26633 ToC ("cx2a", fe400000
, 4, (RCP
, APSR_RR
, APSR_RR
, I511
), cx2a
),
26634 ToC ("cx2d", ee400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2d
),
26635 ToC ("cx2da", fe400040
, 5, (RCP
, RR
, APSR_RR
, APSR_RR
, I511
), cx2da
),
26637 ToC ("cx3", ee800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3
),
26638 ToC ("cx3a", fe800000
, 5, (RCP
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3a
),
26639 ToC ("cx3d", ee800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3d
),
26640 ToC ("cx3da", fe800040
, 6, (RCP
, RR
, APSR_RR
, APSR_RR
, APSR_RR
, I63
), cx3da
),
26642 mToC ("vcx1", ec200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26643 mToC ("vcx1a", fc200000
, 3, (RCP
, RNSDMQ
, I4095
), vcx1
),
26645 mToC ("vcx2", ec300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26646 mToC ("vcx2a", fc300000
, 4, (RCP
, RNSDMQ
, RNSDMQ
, I127
), vcx2
),
26648 mToC ("vcx3", ec800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26649 mToC ("vcx3a", fc800000
, 5, (RCP
, RNSDMQ
, RNSDMQ
, RNSDMQ
, I15
), vcx3
),
26653 #undef THUMB_VARIANT
26685 /* MD interface: bits in the object file. */
26687 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
26688 for use in the a.out file, and stores them in the array pointed to by buf.
26689 This knows about the endian-ness of the target machine and does
26690 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
26691 2 (short) and 4 (long) Floating numbers are put out as a series of
26692 LITTLENUMS (shorts, here at least). */
26695 md_number_to_chars (char * buf
, valueT val
, int n
)
26697 if (target_big_endian
)
26698 number_to_chars_bigendian (buf
, val
, n
);
26700 number_to_chars_littleendian (buf
, val
, n
);
26704 md_chars_to_number (char * buf
, int n
)
26707 unsigned char * where
= (unsigned char *) buf
;
26709 if (target_big_endian
)
26714 result
|= (*where
++ & 255);
26722 result
|= (where
[n
] & 255);
26729 /* MD interface: Sections. */
26731 /* Calculate the maximum variable size (i.e., excluding fr_fix)
26732 that an rs_machine_dependent frag may reach. */
26735 arm_frag_max_var (fragS
*fragp
)
26737 /* We only use rs_machine_dependent for variable-size Thumb instructions,
26738 which are either THUMB_SIZE (2) or INSN_SIZE (4).
26740 Note that we generate relaxable instructions even for cases that don't
26741 really need it, like an immediate that's a trivial constant. So we're
26742 overestimating the instruction size for some of those cases. Rather
26743 than putting more intelligence here, it would probably be better to
26744 avoid generating a relaxation frag in the first place when it can be
26745 determined up front that a short instruction will suffice. */
26747 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
26751 /* Estimate the size of a frag before relaxing. Assume everything fits in
26755 md_estimate_size_before_relax (fragS
* fragp
,
26756 segT segtype ATTRIBUTE_UNUSED
)
26762 /* Convert a machine dependent frag. */
26765 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
26767 unsigned long insn
;
26768 unsigned long old_op
;
26776 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26778 old_op
= bfd_get_16(abfd
, buf
);
26779 if (fragp
->fr_symbol
)
26781 exp
.X_op
= O_symbol
;
26782 exp
.X_add_symbol
= fragp
->fr_symbol
;
26786 exp
.X_op
= O_constant
;
26788 exp
.X_add_number
= fragp
->fr_offset
;
26789 opcode
= fragp
->fr_subtype
;
26792 case T_MNEM_ldr_pc
:
26793 case T_MNEM_ldr_pc2
:
26794 case T_MNEM_ldr_sp
:
26795 case T_MNEM_str_sp
:
26802 if (fragp
->fr_var
== 4)
26804 insn
= THUMB_OP32 (opcode
);
26805 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
26807 insn
|= (old_op
& 0x700) << 4;
26811 insn
|= (old_op
& 7) << 12;
26812 insn
|= (old_op
& 0x38) << 13;
26814 insn
|= 0x00000c00;
26815 put_thumb32_insn (buf
, insn
);
26816 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
26820 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
26822 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
26825 if (fragp
->fr_var
== 4)
26827 insn
= THUMB_OP32 (opcode
);
26828 insn
|= (old_op
& 0xf0) << 4;
26829 put_thumb32_insn (buf
, insn
);
26830 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
26834 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26835 exp
.X_add_number
-= 4;
26843 if (fragp
->fr_var
== 4)
26845 int r0off
= (opcode
== T_MNEM_mov
26846 || opcode
== T_MNEM_movs
) ? 0 : 8;
26847 insn
= THUMB_OP32 (opcode
);
26848 insn
= (insn
& 0xe1ffffff) | 0x10000000;
26849 insn
|= (old_op
& 0x700) << r0off
;
26850 put_thumb32_insn (buf
, insn
);
26851 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26855 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
26860 if (fragp
->fr_var
== 4)
26862 insn
= THUMB_OP32(opcode
);
26863 put_thumb32_insn (buf
, insn
);
26864 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
26867 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
26871 if (fragp
->fr_var
== 4)
26873 insn
= THUMB_OP32(opcode
);
26874 insn
|= (old_op
& 0xf00) << 14;
26875 put_thumb32_insn (buf
, insn
);
26876 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
26879 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
26882 case T_MNEM_add_sp
:
26883 case T_MNEM_add_pc
:
26884 case T_MNEM_inc_sp
:
26885 case T_MNEM_dec_sp
:
26886 if (fragp
->fr_var
== 4)
26888 /* ??? Choose between add and addw. */
26889 insn
= THUMB_OP32 (opcode
);
26890 insn
|= (old_op
& 0xf0) << 4;
26891 put_thumb32_insn (buf
, insn
);
26892 if (opcode
== T_MNEM_add_pc
)
26893 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
26895 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26898 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26906 if (fragp
->fr_var
== 4)
26908 insn
= THUMB_OP32 (opcode
);
26909 insn
|= (old_op
& 0xf0) << 4;
26910 insn
|= (old_op
& 0xf) << 16;
26911 put_thumb32_insn (buf
, insn
);
26912 if (insn
& (1 << 20))
26913 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
26915 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
26918 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
26924 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
26925 (enum bfd_reloc_code_real
) reloc_type
);
26926 fixp
->fx_file
= fragp
->fr_file
;
26927 fixp
->fx_line
= fragp
->fr_line
;
26928 fragp
->fr_fix
+= fragp
->fr_var
;
26930 /* Set whether we use thumb-2 ISA based on final relaxation results. */
26931 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
26932 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
26933 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
26936 /* Return the size of a relaxable immediate operand instruction.
26937 SHIFT and SIZE specify the form of the allowable immediate. */
26939 relax_immediate (fragS
*fragp
, int size
, int shift
)
26945 /* ??? Should be able to do better than this. */
26946 if (fragp
->fr_symbol
)
26949 low
= (1 << shift
) - 1;
26950 mask
= (1 << (shift
+ size
)) - (1 << shift
);
26951 offset
= fragp
->fr_offset
;
26952 /* Force misaligned offsets to 32-bit variant. */
26955 if (offset
& ~mask
)
26960 /* Get the address of a symbol during relaxation. */
26962 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
26968 sym
= fragp
->fr_symbol
;
26969 sym_frag
= symbol_get_frag (sym
);
26970 know (S_GET_SEGMENT (sym
) != absolute_section
26971 || sym_frag
== &zero_address_frag
);
26972 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26974 /* If frag has yet to be reached on this pass, assume it will
26975 move by STRETCH just as we did. If this is not so, it will
26976 be because some frag between grows, and that will force
26980 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26984 /* Adjust stretch for any alignment frag. Note that if have
26985 been expanding the earlier code, the symbol may be
26986 defined in what appears to be an earlier frag. FIXME:
26987 This doesn't handle the fr_subtype field, which specifies
26988 a maximum number of bytes to skip when doing an
26990 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26992 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26995 stretch
= - ((- stretch
)
26996 & ~ ((1 << (int) f
->fr_offset
) - 1));
26998 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
27010 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
27013 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
27018 /* Assume worst case for symbols not known to be in the same section. */
27019 if (fragp
->fr_symbol
== NULL
27020 || !S_IS_DEFINED (fragp
->fr_symbol
)
27021 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27022 || S_IS_WEAK (fragp
->fr_symbol
))
27025 val
= relaxed_symbol_addr (fragp
, stretch
);
27026 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
27027 addr
= (addr
+ 4) & ~3;
27028 /* Force misaligned targets to 32-bit variant. */
27032 if (val
< 0 || val
> 1020)
27037 /* Return the size of a relaxable add/sub immediate instruction. */
27039 relax_addsub (fragS
*fragp
, asection
*sec
)
27044 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
27045 op
= bfd_get_16(sec
->owner
, buf
);
27046 if ((op
& 0xf) == ((op
>> 4) & 0xf))
27047 return relax_immediate (fragp
, 8, 0);
27049 return relax_immediate (fragp
, 3, 0);
27052 /* Return TRUE iff the definition of symbol S could be pre-empted
27053 (overridden) at link or load time. */
27055 symbol_preemptible (symbolS
*s
)
27057 /* Weak symbols can always be pre-empted. */
27061 /* Non-global symbols cannot be pre-empted. */
27062 if (! S_IS_EXTERNAL (s
))
27066 /* In ELF, a global symbol can be marked protected, or private. In that
27067 case it can't be pre-empted (other definitions in the same link unit
27068 would violate the ODR). */
27069 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
27073 /* Other global symbols might be pre-empted. */
27077 /* Return the size of a relaxable branch instruction. BITS is the
27078 size of the offset field in the narrow instruction. */
27081 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
27087 /* Assume worst case for symbols not known to be in the same section. */
27088 if (!S_IS_DEFINED (fragp
->fr_symbol
)
27089 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
27090 || S_IS_WEAK (fragp
->fr_symbol
))
27094 /* A branch to a function in ARM state will require interworking. */
27095 if (S_IS_DEFINED (fragp
->fr_symbol
)
27096 && ARM_IS_FUNC (fragp
->fr_symbol
))
27100 if (symbol_preemptible (fragp
->fr_symbol
))
27103 val
= relaxed_symbol_addr (fragp
, stretch
);
27104 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
27107 /* Offset is a signed value *2 */
27109 if (val
>= limit
|| val
< -limit
)
27115 /* Relax a machine dependent frag. This returns the amount by which
27116 the current size of the frag should change. */
27119 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
27124 oldsize
= fragp
->fr_var
;
27125 switch (fragp
->fr_subtype
)
27127 case T_MNEM_ldr_pc2
:
27128 newsize
= relax_adr (fragp
, sec
, stretch
);
27130 case T_MNEM_ldr_pc
:
27131 case T_MNEM_ldr_sp
:
27132 case T_MNEM_str_sp
:
27133 newsize
= relax_immediate (fragp
, 8, 2);
27137 newsize
= relax_immediate (fragp
, 5, 2);
27141 newsize
= relax_immediate (fragp
, 5, 1);
27145 newsize
= relax_immediate (fragp
, 5, 0);
27148 newsize
= relax_adr (fragp
, sec
, stretch
);
27154 newsize
= relax_immediate (fragp
, 8, 0);
27157 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
27160 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
27162 case T_MNEM_add_sp
:
27163 case T_MNEM_add_pc
:
27164 newsize
= relax_immediate (fragp
, 8, 2);
27166 case T_MNEM_inc_sp
:
27167 case T_MNEM_dec_sp
:
27168 newsize
= relax_immediate (fragp
, 7, 2);
27174 newsize
= relax_addsub (fragp
, sec
);
27180 fragp
->fr_var
= newsize
;
27181 /* Freeze wide instructions that are at or before the same location as
27182 in the previous pass. This avoids infinite loops.
27183 Don't freeze them unconditionally because targets may be artificially
27184 misaligned by the expansion of preceding frags. */
27185 if (stretch
<= 0 && newsize
> 2)
27187 md_convert_frag (sec
->owner
, sec
, fragp
);
27191 return newsize
- oldsize
;
27194 /* Round up a section size to the appropriate boundary. */
27197 md_section_align (segT segment ATTRIBUTE_UNUSED
,
27203 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
27204 of an rs_align_code fragment. */
27207 arm_handle_align (fragS
* fragP
)
27209 static unsigned char const arm_noop
[2][2][4] =
27212 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
27213 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
27216 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
27217 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
27220 static unsigned char const thumb_noop
[2][2][2] =
27223 {0xc0, 0x46}, /* LE */
27224 {0x46, 0xc0}, /* BE */
27227 {0x00, 0xbf}, /* LE */
27228 {0xbf, 0x00} /* BE */
27231 static unsigned char const wide_thumb_noop
[2][4] =
27232 { /* Wide Thumb-2 */
27233 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
27234 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
27237 unsigned bytes
, fix
, noop_size
;
27239 const unsigned char * noop
;
27240 const unsigned char *narrow_noop
= NULL
;
27245 if (fragP
->fr_type
!= rs_align_code
)
27248 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
27249 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
27252 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27253 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
27255 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
27257 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
27259 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27260 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
27262 narrow_noop
= thumb_noop
[1][target_big_endian
];
27263 noop
= wide_thumb_noop
[target_big_endian
];
27266 noop
= thumb_noop
[0][target_big_endian
];
27274 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
27275 ? selected_cpu
: arm_arch_none
,
27277 [target_big_endian
];
27284 fragP
->fr_var
= noop_size
;
27286 if (bytes
& (noop_size
- 1))
27288 fix
= bytes
& (noop_size
- 1);
27290 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
27292 memset (p
, 0, fix
);
27299 if (bytes
& noop_size
)
27301 /* Insert a narrow noop. */
27302 memcpy (p
, narrow_noop
, noop_size
);
27304 bytes
-= noop_size
;
27308 /* Use wide noops for the remainder */
27312 while (bytes
>= noop_size
)
27314 memcpy (p
, noop
, noop_size
);
27316 bytes
-= noop_size
;
27320 fragP
->fr_fix
+= fix
;
27323 /* Called from md_do_align. Used to create an alignment
27324 frag in a code section. */
27327 arm_frag_align_code (int n
, int max
)
27331 /* We assume that there will never be a requirement
27332 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
27333 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
27338 _("alignments greater than %d bytes not supported in .text sections."),
27339 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
27340 as_fatal ("%s", err_msg
);
27343 p
= frag_var (rs_align_code
,
27344 MAX_MEM_FOR_RS_ALIGN_CODE
,
27346 (relax_substateT
) max
,
27353 /* Perform target specific initialisation of a frag.
27354 Note - despite the name this initialisation is not done when the frag
27355 is created, but only when its type is assigned. A frag can be created
27356 and used a long time before its type is set, so beware of assuming that
27357 this initialisation is performed first. */
27361 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
27363 /* Record whether this frag is in an ARM or a THUMB area. */
27364 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27367 #else /* OBJ_ELF is defined. */
27369 arm_init_frag (fragS
* fragP
, int max_chars
)
27371 bfd_boolean frag_thumb_mode
;
27373 /* If the current ARM vs THUMB mode has not already
27374 been recorded into this frag then do so now. */
27375 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
27376 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
27378 /* PR 21809: Do not set a mapping state for debug sections
27379 - it just confuses other tools. */
27380 if (bfd_section_flags (now_seg
) & SEC_DEBUGGING
)
27383 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
27385 /* Record a mapping symbol for alignment frags. We will delete this
27386 later if the alignment ends up empty. */
27387 switch (fragP
->fr_type
)
27390 case rs_align_test
:
27392 mapping_state_2 (MAP_DATA
, max_chars
);
27394 case rs_align_code
:
27395 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
27402 /* When we change sections we need to issue a new mapping symbol. */
27405 arm_elf_change_section (void)
27407 /* Link an unlinked unwind index table section to the .text section. */
27408 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
27409 && elf_linked_to_section (now_seg
) == NULL
)
27410 elf_linked_to_section (now_seg
) = text_section
;
27414 arm_elf_section_type (const char * str
, size_t len
)
27416 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
27417 return SHT_ARM_EXIDX
;
27422 /* Code to deal with unwinding tables. */
27424 static void add_unwind_adjustsp (offsetT
);
27426 /* Generate any deferred unwind frame offset. */
27429 flush_pending_unwind (void)
27433 offset
= unwind
.pending_offset
;
27434 unwind
.pending_offset
= 0;
27436 add_unwind_adjustsp (offset
);
27439 /* Add an opcode to this list for this function. Two-byte opcodes should
27440 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
27444 add_unwind_opcode (valueT op
, int length
)
27446 /* Add any deferred stack adjustment. */
27447 if (unwind
.pending_offset
)
27448 flush_pending_unwind ();
27450 unwind
.sp_restored
= 0;
27452 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
27454 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
27455 if (unwind
.opcodes
)
27456 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
27457 unwind
.opcode_alloc
);
27459 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
27464 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
27466 unwind
.opcode_count
++;
27470 /* Add unwind opcodes to adjust the stack pointer. */
27473 add_unwind_adjustsp (offsetT offset
)
27477 if (offset
> 0x200)
27479 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
27484 /* Long form: 0xb2, uleb128. */
27485 /* This might not fit in a word so add the individual bytes,
27486 remembering the list is built in reverse order. */
27487 o
= (valueT
) ((offset
- 0x204) >> 2);
27489 add_unwind_opcode (0, 1);
27491 /* Calculate the uleb128 encoding of the offset. */
27495 bytes
[n
] = o
& 0x7f;
27501 /* Add the insn. */
27503 add_unwind_opcode (bytes
[n
- 1], 1);
27504 add_unwind_opcode (0xb2, 1);
27506 else if (offset
> 0x100)
27508 /* Two short opcodes. */
27509 add_unwind_opcode (0x3f, 1);
27510 op
= (offset
- 0x104) >> 2;
27511 add_unwind_opcode (op
, 1);
27513 else if (offset
> 0)
27515 /* Short opcode. */
27516 op
= (offset
- 4) >> 2;
27517 add_unwind_opcode (op
, 1);
27519 else if (offset
< 0)
27522 while (offset
> 0x100)
27524 add_unwind_opcode (0x7f, 1);
27527 op
= ((offset
- 4) >> 2) | 0x40;
27528 add_unwind_opcode (op
, 1);
27532 /* Finish the list of unwind opcodes for this function. */
27535 finish_unwind_opcodes (void)
27539 if (unwind
.fp_used
)
27541 /* Adjust sp as necessary. */
27542 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
27543 flush_pending_unwind ();
27545 /* After restoring sp from the frame pointer. */
27546 op
= 0x90 | unwind
.fp_reg
;
27547 add_unwind_opcode (op
, 1);
27550 flush_pending_unwind ();
27554 /* Start an exception table entry. If idx is nonzero this is an index table
27558 start_unwind_section (const segT text_seg
, int idx
)
27560 const char * text_name
;
27561 const char * prefix
;
27562 const char * prefix_once
;
27563 struct elf_section_match match
;
27571 prefix
= ELF_STRING_ARM_unwind
;
27572 prefix_once
= ELF_STRING_ARM_unwind_once
;
27573 type
= SHT_ARM_EXIDX
;
27577 prefix
= ELF_STRING_ARM_unwind_info
;
27578 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
27579 type
= SHT_PROGBITS
;
27582 text_name
= segment_name (text_seg
);
27583 if (streq (text_name
, ".text"))
27586 if (strncmp (text_name
, ".gnu.linkonce.t.",
27587 strlen (".gnu.linkonce.t.")) == 0)
27589 prefix
= prefix_once
;
27590 text_name
+= strlen (".gnu.linkonce.t.");
27593 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
27597 memset (&match
, 0, sizeof (match
));
27599 /* Handle COMDAT group. */
27600 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
27602 match
.group_name
= elf_group_name (text_seg
);
27603 if (match
.group_name
== NULL
)
27605 as_bad (_("Group section `%s' has no group signature"),
27606 segment_name (text_seg
));
27607 ignore_rest_of_line ();
27610 flags
|= SHF_GROUP
;
27614 obj_elf_change_section (sec_name
, type
, flags
, 0, &match
,
27617 /* Set the section link for index tables. */
27619 elf_linked_to_section (now_seg
) = text_seg
;
27623 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
27624 personality routine data. Returns zero, or the index table value for
27625 an inline entry. */
27628 create_unwind_entry (int have_data
)
27633 /* The current word of data. */
27635 /* The number of bytes left in this word. */
27638 finish_unwind_opcodes ();
27640 /* Remember the current text section. */
27641 unwind
.saved_seg
= now_seg
;
27642 unwind
.saved_subseg
= now_subseg
;
27644 start_unwind_section (now_seg
, 0);
27646 if (unwind
.personality_routine
== NULL
)
27648 if (unwind
.personality_index
== -2)
27651 as_bad (_("handlerdata in cantunwind frame"));
27652 return 1; /* EXIDX_CANTUNWIND. */
27655 /* Use a default personality routine if none is specified. */
27656 if (unwind
.personality_index
== -1)
27658 if (unwind
.opcode_count
> 3)
27659 unwind
.personality_index
= 1;
27661 unwind
.personality_index
= 0;
27664 /* Space for the personality routine entry. */
27665 if (unwind
.personality_index
== 0)
27667 if (unwind
.opcode_count
> 3)
27668 as_bad (_("too many unwind opcodes for personality routine 0"));
27672 /* All the data is inline in the index table. */
27675 while (unwind
.opcode_count
> 0)
27677 unwind
.opcode_count
--;
27678 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27682 /* Pad with "finish" opcodes. */
27684 data
= (data
<< 8) | 0xb0;
27691 /* We get two opcodes "free" in the first word. */
27692 size
= unwind
.opcode_count
- 2;
27696 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
27697 if (unwind
.personality_index
!= -1)
27699 as_bad (_("attempt to recreate an unwind entry"));
27703 /* An extra byte is required for the opcode count. */
27704 size
= unwind
.opcode_count
+ 1;
27707 size
= (size
+ 3) >> 2;
27709 as_bad (_("too many unwind opcodes"));
27711 frag_align (2, 0, 0);
27712 record_alignment (now_seg
, 2);
27713 unwind
.table_entry
= expr_build_dot ();
27715 /* Allocate the table entry. */
27716 ptr
= frag_more ((size
<< 2) + 4);
27717 /* PR 13449: Zero the table entries in case some of them are not used. */
27718 memset (ptr
, 0, (size
<< 2) + 4);
27719 where
= frag_now_fix () - ((size
<< 2) + 4);
27721 switch (unwind
.personality_index
)
27724 /* ??? Should this be a PLT generating relocation? */
27725 /* Custom personality routine. */
27726 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
27727 BFD_RELOC_ARM_PREL31
);
27732 /* Set the first byte to the number of additional words. */
27733 data
= size
> 0 ? size
- 1 : 0;
27737 /* ABI defined personality routines. */
27739 /* Three opcodes bytes are packed into the first word. */
27746 /* The size and first two opcode bytes go in the first word. */
27747 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
27752 /* Should never happen. */
27756 /* Pack the opcodes into words (MSB first), reversing the list at the same
27758 while (unwind
.opcode_count
> 0)
27762 md_number_to_chars (ptr
, data
, 4);
27767 unwind
.opcode_count
--;
27769 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
27772 /* Finish off the last word. */
27775 /* Pad with "finish" opcodes. */
27777 data
= (data
<< 8) | 0xb0;
27779 md_number_to_chars (ptr
, data
, 4);
27784 /* Add an empty descriptor if there is no user-specified data. */
27785 ptr
= frag_more (4);
27786 md_number_to_chars (ptr
, 0, 4);
27793 /* Initialize the DWARF-2 unwind information for this procedure. */
27796 tc_arm_frame_initial_instructions (void)
27798 cfi_add_CFA_def_cfa (REG_SP
, 0);
27800 #endif /* OBJ_ELF */
27802 /* Convert REGNAME to a DWARF-2 register number. */
27805 tc_arm_regname_to_dw2regnum (char *regname
)
27807 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
27811 /* PR 16694: Allow VFP registers as well. */
27812 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
27816 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
27825 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
27829 exp
.X_op
= O_secrel
;
27830 exp
.X_add_symbol
= symbol
;
27831 exp
.X_add_number
= 0;
27832 emit_expr (&exp
, size
);
27836 /* MD interface: Symbol and relocation handling. */
27838 /* Return the address within the segment that a PC-relative fixup is
27839 relative to. For ARM, PC-relative fixups applied to instructions
27840 are generally relative to the location of the fixup plus 8 bytes.
27841 Thumb branches are offset by 4, and Thumb loads relative to PC
27842 require special handling. */
27845 md_pcrel_from_section (fixS
* fixP
, segT seg
)
27847 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27849 /* If this is pc-relative and we are going to emit a relocation
27850 then we just want to put out any pipeline compensation that the linker
27851 will need. Otherwise we want to use the calculated base.
27852 For WinCE we skip the bias for externals as well, since this
27853 is how the MS ARM-CE assembler behaves and we want to be compatible. */
27855 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27856 || (arm_force_relocation (fixP
)
27858 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
27864 switch (fixP
->fx_r_type
)
27866 /* PC relative addressing on the Thumb is slightly odd as the
27867 bottom two bits of the PC are forced to zero for the
27868 calculation. This happens *after* application of the
27869 pipeline offset. However, Thumb adrl already adjusts for
27870 this, so we need not do it again. */
27871 case BFD_RELOC_ARM_THUMB_ADD
:
27874 case BFD_RELOC_ARM_THUMB_OFFSET
:
27875 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27876 case BFD_RELOC_ARM_T32_ADD_PC12
:
27877 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
27878 return (base
+ 4) & ~3;
27880 /* Thumb branches are simply offset by +4. */
27881 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
27882 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
27883 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
27884 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
27885 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
27886 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
27887 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
27888 case BFD_RELOC_ARM_THUMB_BF17
:
27889 case BFD_RELOC_ARM_THUMB_BF19
:
27890 case BFD_RELOC_ARM_THUMB_BF13
:
27891 case BFD_RELOC_ARM_THUMB_LOOP12
:
27894 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27896 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27897 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27898 && ARM_IS_FUNC (fixP
->fx_addsy
)
27899 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27900 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27903 /* BLX is like branches above, but forces the low two bits of PC to
27905 case BFD_RELOC_THUMB_PCREL_BLX
:
27907 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27908 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27909 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27910 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27911 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27912 return (base
+ 4) & ~3;
27914 /* ARM mode branches are offset by +8. However, the Windows CE
27915 loader expects the relocation not to take this into account. */
27916 case BFD_RELOC_ARM_PCREL_BLX
:
27918 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27919 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27920 && ARM_IS_FUNC (fixP
->fx_addsy
)
27921 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27922 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27925 case BFD_RELOC_ARM_PCREL_CALL
:
27927 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27928 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27929 && THUMB_IS_FUNC (fixP
->fx_addsy
)
27930 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
27931 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
27934 case BFD_RELOC_ARM_PCREL_BRANCH
:
27935 case BFD_RELOC_ARM_PCREL_JUMP
:
27936 case BFD_RELOC_ARM_PLT32
:
27938 /* When handling fixups immediately, because we have already
27939 discovered the value of a symbol, or the address of the frag involved
27940 we must account for the offset by +8, as the OS loader will never see the reloc.
27941 see fixup_segment() in write.c
27942 The S_IS_EXTERNAL test handles the case of global symbols.
27943 Those need the calculated base, not just the pipe compensation the linker will need. */
27945 && fixP
->fx_addsy
!= NULL
27946 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27947 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
27955 /* ARM mode loads relative to PC are also offset by +8. Unlike
27956 branches, the Windows CE loader *does* expect the relocation
27957 to take this into account. */
27958 case BFD_RELOC_ARM_OFFSET_IMM
:
27959 case BFD_RELOC_ARM_OFFSET_IMM8
:
27960 case BFD_RELOC_ARM_HWLITERAL
:
27961 case BFD_RELOC_ARM_LITERAL
:
27962 case BFD_RELOC_ARM_CP_OFF_IMM
:
27966 /* Other PC-relative relocations are un-offset. */
27972 static bfd_boolean flag_warn_syms
= TRUE
;
27975 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27977 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27978 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27979 does mean that the resulting code might be very confusing to the reader.
27980 Also this warning can be triggered if the user omits an operand before
27981 an immediate address, eg:
27985 GAS treats this as an assignment of the value of the symbol foo to a
27986 symbol LDR, and so (without this code) it will not issue any kind of
27987 warning or error message.
27989 Note - ARM instructions are case-insensitive but the strings in the hash
27990 table are all stored in lower case, so we must first ensure that name is
27992 if (flag_warn_syms
&& arm_ops_hsh
)
27994 char * nbuf
= strdup (name
);
27997 for (p
= nbuf
; *p
; p
++)
27999 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
28001 static struct hash_control
* already_warned
= NULL
;
28003 if (already_warned
== NULL
)
28004 already_warned
= hash_new ();
28005 /* Only warn about the symbol once. To keep the code
28006 simple we let hash_insert do the lookup for us. */
28007 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
28008 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
28017 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
28018 Otherwise we have no need to default values of symbols. */
28021 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
28024 if (name
[0] == '_' && name
[1] == 'G'
28025 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
28029 if (symbol_find (name
))
28030 as_bad (_("GOT already in the symbol table"));
28032 GOT_symbol
= symbol_new (name
, undefined_section
,
28033 (valueT
) 0, & zero_address_frag
);
28043 /* Subroutine of md_apply_fix. Check to see if an immediate can be
28044 computed as two separate immediate values, added together. We
28045 already know that this value cannot be computed by just one ARM
28048 static unsigned int
28049 validate_immediate_twopart (unsigned int val
,
28050 unsigned int * highpart
)
28055 for (i
= 0; i
< 32; i
+= 2)
28056 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
28062 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
28064 else if (a
& 0xff0000)
28066 if (a
& 0xff000000)
28068 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
28072 gas_assert (a
& 0xff000000);
28073 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
28076 return (a
& 0xff) | (i
<< 7);
28083 validate_offset_imm (unsigned int val
, int hwse
)
28085 if ((hwse
&& val
> 255) || val
> 4095)
28090 /* Subroutine of md_apply_fix. Do those data_ops which can take a
28091 negative immediate constant by altering the instruction. A bit of
28096 by inverting the second operand, and
28099 by negating the second operand. */
28102 negate_data_op (unsigned long * instruction
,
28103 unsigned long value
)
28106 unsigned long negated
, inverted
;
28108 negated
= encode_arm_immediate (-value
);
28109 inverted
= encode_arm_immediate (~value
);
28111 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
28114 /* First negates. */
28115 case OPCODE_SUB
: /* ADD <-> SUB */
28116 new_inst
= OPCODE_ADD
;
28121 new_inst
= OPCODE_SUB
;
28125 case OPCODE_CMP
: /* CMP <-> CMN */
28126 new_inst
= OPCODE_CMN
;
28131 new_inst
= OPCODE_CMP
;
28135 /* Now Inverted ops. */
28136 case OPCODE_MOV
: /* MOV <-> MVN */
28137 new_inst
= OPCODE_MVN
;
28142 new_inst
= OPCODE_MOV
;
28146 case OPCODE_AND
: /* AND <-> BIC */
28147 new_inst
= OPCODE_BIC
;
28152 new_inst
= OPCODE_AND
;
28156 case OPCODE_ADC
: /* ADC <-> SBC */
28157 new_inst
= OPCODE_SBC
;
28162 new_inst
= OPCODE_ADC
;
28166 /* We cannot do anything. */
28171 if (value
== (unsigned) FAIL
)
28174 *instruction
&= OPCODE_MASK
;
28175 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
28179 /* Like negate_data_op, but for Thumb-2. */
28181 static unsigned int
28182 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
28186 unsigned int negated
, inverted
;
28188 negated
= encode_thumb32_immediate (-value
);
28189 inverted
= encode_thumb32_immediate (~value
);
28191 rd
= (*instruction
>> 8) & 0xf;
28192 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
28195 /* ADD <-> SUB. Includes CMP <-> CMN. */
28196 case T2_OPCODE_SUB
:
28197 new_inst
= T2_OPCODE_ADD
;
28201 case T2_OPCODE_ADD
:
28202 new_inst
= T2_OPCODE_SUB
;
28206 /* ORR <-> ORN. Includes MOV <-> MVN. */
28207 case T2_OPCODE_ORR
:
28208 new_inst
= T2_OPCODE_ORN
;
28212 case T2_OPCODE_ORN
:
28213 new_inst
= T2_OPCODE_ORR
;
28217 /* AND <-> BIC. TST has no inverted equivalent. */
28218 case T2_OPCODE_AND
:
28219 new_inst
= T2_OPCODE_BIC
;
28226 case T2_OPCODE_BIC
:
28227 new_inst
= T2_OPCODE_AND
;
28232 case T2_OPCODE_ADC
:
28233 new_inst
= T2_OPCODE_SBC
;
28237 case T2_OPCODE_SBC
:
28238 new_inst
= T2_OPCODE_ADC
;
28242 /* We cannot do anything. */
28247 if (value
== (unsigned int)FAIL
)
28250 *instruction
&= T2_OPCODE_MASK
;
28251 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
28255 /* Read a 32-bit thumb instruction from buf. */
28257 static unsigned long
28258 get_thumb32_insn (char * buf
)
28260 unsigned long insn
;
28261 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
28262 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28267 /* We usually want to set the low bit on the address of thumb function
28268 symbols. In particular .word foo - . should have the low bit set.
28269 Generic code tries to fold the difference of two symbols to
28270 a constant. Prevent this and force a relocation when the first symbols
28271 is a thumb function. */
28274 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
28276 if (op
== O_subtract
28277 && l
->X_op
== O_symbol
28278 && r
->X_op
== O_symbol
28279 && THUMB_IS_FUNC (l
->X_add_symbol
))
28281 l
->X_op
= O_subtract
;
28282 l
->X_op_symbol
= r
->X_add_symbol
;
28283 l
->X_add_number
-= r
->X_add_number
;
28287 /* Process as normal. */
28291 /* Encode Thumb2 unconditional branches and calls. The encoding
28292 for the 2 are identical for the immediate values. */
28295 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
28297 #define T2I1I2MASK ((1 << 13) | (1 << 11))
28300 addressT S
, I1
, I2
, lo
, hi
;
28302 S
= (value
>> 24) & 0x01;
28303 I1
= (value
>> 23) & 0x01;
28304 I2
= (value
>> 22) & 0x01;
28305 hi
= (value
>> 12) & 0x3ff;
28306 lo
= (value
>> 1) & 0x7ff;
28307 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28308 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28309 newval
|= (S
<< 10) | hi
;
28310 newval2
&= ~T2I1I2MASK
;
28311 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
28312 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28313 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28317 md_apply_fix (fixS
* fixP
,
28321 offsetT value
= * valP
;
28323 unsigned int newimm
;
28324 unsigned long temp
;
28326 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
28328 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
28330 /* Note whether this will delete the relocation. */
28332 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
28335 /* On a 64-bit host, silently truncate 'value' to 32 bits for
28336 consistency with the behaviour on 32-bit hosts. Remember value
28338 value
&= 0xffffffff;
28339 value
^= 0x80000000;
28340 value
-= 0x80000000;
28343 fixP
->fx_addnumber
= value
;
28345 /* Same treatment for fixP->fx_offset. */
28346 fixP
->fx_offset
&= 0xffffffff;
28347 fixP
->fx_offset
^= 0x80000000;
28348 fixP
->fx_offset
-= 0x80000000;
28350 switch (fixP
->fx_r_type
)
28352 case BFD_RELOC_NONE
:
28353 /* This will need to go in the object file. */
28357 case BFD_RELOC_ARM_IMMEDIATE
:
28358 /* We claim that this fixup has been processed here,
28359 even if in fact we generate an error because we do
28360 not have a reloc for it, so tc_gen_reloc will reject it. */
28363 if (fixP
->fx_addsy
)
28365 const char *msg
= 0;
28367 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28368 msg
= _("undefined symbol %s used as an immediate value");
28369 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28370 msg
= _("symbol %s is in a different section");
28371 else if (S_IS_WEAK (fixP
->fx_addsy
))
28372 msg
= _("symbol %s is weak and may be overridden later");
28376 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28377 msg
, S_GET_NAME (fixP
->fx_addsy
));
28382 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28384 /* If the offset is negative, we should use encoding A2 for ADR. */
28385 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
28386 newimm
= negate_data_op (&temp
, value
);
28389 newimm
= encode_arm_immediate (value
);
28391 /* If the instruction will fail, see if we can fix things up by
28392 changing the opcode. */
28393 if (newimm
== (unsigned int) FAIL
)
28394 newimm
= negate_data_op (&temp
, value
);
28395 /* MOV accepts both ARM modified immediate (A1 encoding) and
28396 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
28397 When disassembling, MOV is preferred when there is no encoding
28399 if (newimm
== (unsigned int) FAIL
28400 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
28401 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
28402 && !((temp
>> SBIT_SHIFT
) & 0x1)
28403 && value
>= 0 && value
<= 0xffff)
28405 /* Clear bits[23:20] to change encoding from A1 to A2. */
28406 temp
&= 0xff0fffff;
28407 /* Encoding high 4bits imm. Code below will encode the remaining
28409 temp
|= (value
& 0x0000f000) << 4;
28410 newimm
= value
& 0x00000fff;
28414 if (newimm
== (unsigned int) FAIL
)
28416 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28417 _("invalid constant (%lx) after fixup"),
28418 (unsigned long) value
);
28422 newimm
|= (temp
& 0xfffff000);
28423 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28426 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
28428 unsigned int highpart
= 0;
28429 unsigned int newinsn
= 0xe1a00000; /* nop. */
28431 if (fixP
->fx_addsy
)
28433 const char *msg
= 0;
28435 if (! S_IS_DEFINED (fixP
->fx_addsy
))
28436 msg
= _("undefined symbol %s used as an immediate value");
28437 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
28438 msg
= _("symbol %s is in a different section");
28439 else if (S_IS_WEAK (fixP
->fx_addsy
))
28440 msg
= _("symbol %s is weak and may be overridden later");
28444 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28445 msg
, S_GET_NAME (fixP
->fx_addsy
));
28450 newimm
= encode_arm_immediate (value
);
28451 temp
= md_chars_to_number (buf
, INSN_SIZE
);
28453 /* If the instruction will fail, see if we can fix things up by
28454 changing the opcode. */
28455 if (newimm
== (unsigned int) FAIL
28456 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
28458 /* No ? OK - try using two ADD instructions to generate
28460 newimm
= validate_immediate_twopart (value
, & highpart
);
28462 /* Yes - then make sure that the second instruction is
28464 if (newimm
!= (unsigned int) FAIL
)
28466 /* Still No ? Try using a negated value. */
28467 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
28468 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
28469 /* Otherwise - give up. */
28472 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28473 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
28478 /* Replace the first operand in the 2nd instruction (which
28479 is the PC) with the destination register. We have
28480 already added in the PC in the first instruction and we
28481 do not want to do it again. */
28482 newinsn
&= ~ 0xf0000;
28483 newinsn
|= ((newinsn
& 0x0f000) << 4);
28486 newimm
|= (temp
& 0xfffff000);
28487 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
28489 highpart
|= (newinsn
& 0xfffff000);
28490 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
28494 case BFD_RELOC_ARM_OFFSET_IMM
:
28495 if (!fixP
->fx_done
&& seg
->use_rela_p
)
28497 /* Fall through. */
28499 case BFD_RELOC_ARM_LITERAL
:
28505 if (validate_offset_imm (value
, 0) == FAIL
)
28507 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
28508 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28509 _("invalid literal constant: pool needs to be closer"));
28511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28512 _("bad immediate value for offset (%ld)"),
28517 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28519 newval
&= 0xfffff000;
28522 newval
&= 0xff7ff000;
28523 newval
|= value
| (sign
? INDEX_UP
: 0);
28525 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28528 case BFD_RELOC_ARM_OFFSET_IMM8
:
28529 case BFD_RELOC_ARM_HWLITERAL
:
28535 if (validate_offset_imm (value
, 1) == FAIL
)
28537 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
28538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28539 _("invalid literal constant: pool needs to be closer"));
28541 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28542 _("bad immediate value for 8-bit offset (%ld)"),
28547 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28549 newval
&= 0xfffff0f0;
28552 newval
&= 0xff7ff0f0;
28553 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
28555 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28558 case BFD_RELOC_ARM_T32_OFFSET_U8
:
28559 if (value
< 0 || value
> 1020 || value
% 4 != 0)
28560 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28561 _("bad immediate value for offset (%ld)"), (long) value
);
28564 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
28566 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
28569 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
28570 /* This is a complicated relocation used for all varieties of Thumb32
28571 load/store instruction with immediate offset:
28573 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
28574 *4, optional writeback(W)
28575 (doubleword load/store)
28577 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
28578 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
28579 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
28580 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
28581 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
28583 Uppercase letters indicate bits that are already encoded at
28584 this point. Lowercase letters are our problem. For the
28585 second block of instructions, the secondary opcode nybble
28586 (bits 8..11) is present, and bit 23 is zero, even if this is
28587 a PC-relative operation. */
28588 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28590 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
28592 if ((newval
& 0xf0000000) == 0xe0000000)
28594 /* Doubleword load/store: 8-bit offset, scaled by 4. */
28596 newval
|= (1 << 23);
28599 if (value
% 4 != 0)
28601 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28602 _("offset not a multiple of 4"));
28608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28609 _("offset out of range"));
28614 else if ((newval
& 0x000f0000) == 0x000f0000)
28616 /* PC-relative, 12-bit offset. */
28618 newval
|= (1 << 23);
28623 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28624 _("offset out of range"));
28629 else if ((newval
& 0x00000100) == 0x00000100)
28631 /* Writeback: 8-bit, +/- offset. */
28633 newval
|= (1 << 9);
28638 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28639 _("offset out of range"));
28644 else if ((newval
& 0x00000f00) == 0x00000e00)
28646 /* T-instruction: positive 8-bit offset. */
28647 if (value
< 0 || value
> 0xff)
28649 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28650 _("offset out of range"));
28658 /* Positive 12-bit or negative 8-bit offset. */
28662 newval
|= (1 << 23);
28672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28673 _("offset out of range"));
28680 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
28681 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
28684 case BFD_RELOC_ARM_SHIFT_IMM
:
28685 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28686 if (((unsigned long) value
) > 32
28688 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
28690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28691 _("shift expression is too large"));
28696 /* Shifts of zero must be done as lsl. */
28698 else if (value
== 32)
28700 newval
&= 0xfffff07f;
28701 newval
|= (value
& 0x1f) << 7;
28702 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28705 case BFD_RELOC_ARM_T32_IMMEDIATE
:
28706 case BFD_RELOC_ARM_T32_ADD_IMM
:
28707 case BFD_RELOC_ARM_T32_IMM12
:
28708 case BFD_RELOC_ARM_T32_ADD_PC12
:
28709 /* We claim that this fixup has been processed here,
28710 even if in fact we generate an error because we do
28711 not have a reloc for it, so tc_gen_reloc will reject it. */
28715 && ! S_IS_DEFINED (fixP
->fx_addsy
))
28717 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28718 _("undefined symbol %s used as an immediate value"),
28719 S_GET_NAME (fixP
->fx_addsy
));
28723 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28725 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
28728 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
28729 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
28730 Thumb2 modified immediate encoding (T2). */
28731 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
28732 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28734 newimm
= encode_thumb32_immediate (value
);
28735 if (newimm
== (unsigned int) FAIL
)
28736 newimm
= thumb32_negate_data_op (&newval
, value
);
28738 if (newimm
== (unsigned int) FAIL
)
28740 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
28742 /* Turn add/sum into addw/subw. */
28743 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
28744 newval
= (newval
& 0xfeffffff) | 0x02000000;
28745 /* No flat 12-bit imm encoding for addsw/subsw. */
28746 if ((newval
& 0x00100000) == 0)
28748 /* 12 bit immediate for addw/subw. */
28752 newval
^= 0x00a00000;
28755 newimm
= (unsigned int) FAIL
;
28762 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
28763 UINT16 (T3 encoding), MOVW only accepts UINT16. When
28764 disassembling, MOV is preferred when there is no encoding
28766 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
28767 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
28768 but with the Rn field [19:16] set to 1111. */
28769 && (((newval
>> 16) & 0xf) == 0xf)
28770 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
28771 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
28772 && value
>= 0 && value
<= 0xffff)
28774 /* Toggle bit[25] to change encoding from T2 to T3. */
28776 /* Clear bits[19:16]. */
28777 newval
&= 0xfff0ffff;
28778 /* Encoding high 4bits imm. Code below will encode the
28779 remaining low 12bits. */
28780 newval
|= (value
& 0x0000f000) << 4;
28781 newimm
= value
& 0x00000fff;
28786 if (newimm
== (unsigned int)FAIL
)
28788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28789 _("invalid constant (%lx) after fixup"),
28790 (unsigned long) value
);
28794 newval
|= (newimm
& 0x800) << 15;
28795 newval
|= (newimm
& 0x700) << 4;
28796 newval
|= (newimm
& 0x0ff);
28798 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
28799 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
28802 case BFD_RELOC_ARM_SMC
:
28803 if (((unsigned long) value
) > 0xf)
28804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28805 _("invalid smc expression"));
28807 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28808 newval
|= (value
& 0xf);
28809 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28812 case BFD_RELOC_ARM_HVC
:
28813 if (((unsigned long) value
) > 0xffff)
28814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28815 _("invalid hvc expression"));
28816 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28817 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
28818 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28821 case BFD_RELOC_ARM_SWI
:
28822 if (fixP
->tc_fix_data
!= 0)
28824 if (((unsigned long) value
) > 0xff)
28825 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28826 _("invalid swi expression"));
28827 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28829 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28833 if (((unsigned long) value
) > 0x00ffffff)
28834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28835 _("invalid swi expression"));
28836 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28838 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28842 case BFD_RELOC_ARM_MULTI
:
28843 if (((unsigned long) value
) > 0xffff)
28844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28845 _("invalid expression in load/store multiple"));
28846 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
28847 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28851 case BFD_RELOC_ARM_PCREL_CALL
:
28853 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28855 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28856 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28857 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28858 /* Flip the bl to blx. This is a simple flip
28859 bit here because we generate PCREL_CALL for
28860 unconditional bls. */
28862 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28863 newval
= newval
| 0x10000000;
28864 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28870 goto arm_branch_common
;
28872 case BFD_RELOC_ARM_PCREL_JUMP
:
28873 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28875 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28876 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28877 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28879 /* This would map to a bl<cond>, b<cond>,
28880 b<always> to a Thumb function. We
28881 need to force a relocation for this particular
28883 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28886 /* Fall through. */
28888 case BFD_RELOC_ARM_PLT32
:
28890 case BFD_RELOC_ARM_PCREL_BRANCH
:
28892 goto arm_branch_common
;
28894 case BFD_RELOC_ARM_PCREL_BLX
:
28897 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
28899 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28900 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28901 && ARM_IS_FUNC (fixP
->fx_addsy
))
28903 /* Flip the blx to a bl and warn. */
28904 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28905 newval
= 0xeb000000;
28906 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28907 _("blx to '%s' an ARM ISA state function changed to bl"),
28909 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28915 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
28916 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
28920 /* We are going to store value (shifted right by two) in the
28921 instruction, in a 24 bit, signed field. Bits 26 through 32 either
28922 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
28925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28926 _("misaligned branch destination"));
28927 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
28928 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
28929 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28931 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28933 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28934 newval
|= (value
>> 2) & 0x00ffffff;
28935 /* Set the H bit on BLX instructions. */
28939 newval
|= 0x01000000;
28941 newval
&= ~0x01000000;
28943 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28947 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
28948 /* CBZ can only branch forward. */
28950 /* Attempts to use CBZ to branch to the next instruction
28951 (which, strictly speaking, are prohibited) will be turned into
28954 FIXME: It may be better to remove the instruction completely and
28955 perform relaxation. */
28958 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28959 newval
= 0xbf00; /* NOP encoding T1 */
28960 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28965 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28967 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28969 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28970 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28971 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28976 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28977 if (out_of_range_p (value
, 8))
28978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28980 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28982 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28983 newval
|= (value
& 0x1ff) >> 1;
28984 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28988 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28989 if (out_of_range_p (value
, 11))
28990 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28992 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28994 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28995 newval
|= (value
& 0xfff) >> 1;
28996 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29000 /* This relocation is misnamed, it should be BRANCH21. */
29001 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29003 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29004 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29005 && ARM_IS_FUNC (fixP
->fx_addsy
)
29006 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29008 /* Force a relocation for a branch 20 bits wide. */
29011 if (out_of_range_p (value
, 20))
29012 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29013 _("conditional branch out of range"));
29015 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29018 addressT S
, J1
, J2
, lo
, hi
;
29020 S
= (value
& 0x00100000) >> 20;
29021 J2
= (value
& 0x00080000) >> 19;
29022 J1
= (value
& 0x00040000) >> 18;
29023 hi
= (value
& 0x0003f000) >> 12;
29024 lo
= (value
& 0x00000ffe) >> 1;
29026 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29027 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29028 newval
|= (S
<< 10) | hi
;
29029 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
29030 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29031 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29035 case BFD_RELOC_THUMB_PCREL_BLX
:
29036 /* If there is a blx from a thumb state function to
29037 another thumb function flip this to a bl and warn
29041 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29042 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29043 && THUMB_IS_FUNC (fixP
->fx_addsy
))
29045 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
29046 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
29047 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
29049 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29050 newval
= newval
| 0x1000;
29051 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29052 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29057 goto thumb_bl_common
;
29059 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29060 /* A bl from Thumb state ISA to an internal ARM state function
29061 is converted to a blx. */
29063 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29064 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29065 && ARM_IS_FUNC (fixP
->fx_addsy
)
29066 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
29068 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29069 newval
= newval
& ~0x1000;
29070 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
29071 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
29077 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29078 /* For a BLX instruction, make sure that the relocation is rounded up
29079 to a word boundary. This follows the semantics of the instruction
29080 which specifies that bit 1 of the target address will come from bit
29081 1 of the base address. */
29082 value
= (value
+ 3) & ~ 3;
29085 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
29086 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
29087 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29090 if (out_of_range_p (value
, 22))
29092 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
29093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29094 else if (out_of_range_p (value
, 24))
29095 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29096 _("Thumb2 branch out of range"));
29099 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29100 encode_thumb2_b_bl_offset (buf
, value
);
29104 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29105 if (out_of_range_p (value
, 24))
29106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
29108 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29109 encode_thumb2_b_bl_offset (buf
, value
);
29114 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29119 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29120 md_number_to_chars (buf
, value
, 2);
29124 case BFD_RELOC_ARM_TLS_CALL
:
29125 case BFD_RELOC_ARM_THM_TLS_CALL
:
29126 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29127 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29128 case BFD_RELOC_ARM_TLS_GOTDESC
:
29129 case BFD_RELOC_ARM_TLS_GD32
:
29130 case BFD_RELOC_ARM_TLS_LE32
:
29131 case BFD_RELOC_ARM_TLS_IE32
:
29132 case BFD_RELOC_ARM_TLS_LDM32
:
29133 case BFD_RELOC_ARM_TLS_LDO32
:
29134 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29137 /* Same handling as above, but with the arm_fdpic guard. */
29138 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29139 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29140 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29143 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
29147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29148 _("Relocation supported only in FDPIC mode"));
29152 case BFD_RELOC_ARM_GOT32
:
29153 case BFD_RELOC_ARM_GOTOFF
:
29156 case BFD_RELOC_ARM_GOT_PREL
:
29157 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29158 md_number_to_chars (buf
, value
, 4);
29161 case BFD_RELOC_ARM_TARGET2
:
29162 /* TARGET2 is not partial-inplace, so we need to write the
29163 addend here for REL targets, because it won't be written out
29164 during reloc processing later. */
29165 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29166 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
29169 /* Relocations for FDPIC. */
29170 case BFD_RELOC_ARM_GOTFUNCDESC
:
29171 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29172 case BFD_RELOC_ARM_FUNCDESC
:
29175 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29176 md_number_to_chars (buf
, 0, 4);
29180 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29181 _("Relocation supported only in FDPIC mode"));
29186 case BFD_RELOC_RVA
:
29188 case BFD_RELOC_ARM_TARGET1
:
29189 case BFD_RELOC_ARM_ROSEGREL32
:
29190 case BFD_RELOC_ARM_SBREL32
:
29191 case BFD_RELOC_32_PCREL
:
29193 case BFD_RELOC_32_SECREL
:
29195 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29197 /* For WinCE we only do this for pcrel fixups. */
29198 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
29200 md_number_to_chars (buf
, value
, 4);
29204 case BFD_RELOC_ARM_PREL31
:
29205 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29207 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
29208 if ((value
^ (value
>> 1)) & 0x40000000)
29210 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29211 _("rel31 relocation overflow"));
29213 newval
|= value
& 0x7fffffff;
29214 md_number_to_chars (buf
, newval
, 4);
29219 case BFD_RELOC_ARM_CP_OFF_IMM
:
29220 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
29221 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
29222 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
29223 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29225 newval
= get_thumb32_insn (buf
);
29226 if ((newval
& 0x0f200f00) == 0x0d000900)
29228 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
29229 has permitted values that are multiples of 2, in the range 0
29231 if (value
< -510 || value
> 510 || (value
& 1))
29232 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29233 _("co-processor offset out of range"));
29235 else if ((newval
& 0xfe001f80) == 0xec000f80)
29237 if (value
< -511 || value
> 512 || (value
& 3))
29238 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29239 _("co-processor offset out of range"));
29241 else if (value
< -1023 || value
> 1023 || (value
& 3))
29242 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29243 _("co-processor offset out of range"));
29248 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29249 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29250 newval
= md_chars_to_number (buf
, INSN_SIZE
);
29252 newval
= get_thumb32_insn (buf
);
29255 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29256 newval
&= 0xffffff80;
29258 newval
&= 0xffffff00;
29262 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
29263 newval
&= 0xff7fff80;
29265 newval
&= 0xff7fff00;
29266 if ((newval
& 0x0f200f00) == 0x0d000900)
29268 /* This is a fp16 vstr/vldr.
29270 It requires the immediate offset in the instruction is shifted
29271 left by 1 to be a half-word offset.
29273 Here, left shift by 1 first, and later right shift by 2
29274 should get the right offset. */
29277 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
29279 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29280 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
29281 md_number_to_chars (buf
, newval
, INSN_SIZE
);
29283 put_thumb32_insn (buf
, newval
);
29286 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
29287 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
29288 if (value
< -255 || value
> 255)
29289 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29290 _("co-processor offset out of range"));
29292 goto cp_off_common
;
29294 case BFD_RELOC_ARM_THUMB_OFFSET
:
29295 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29296 /* Exactly what ranges, and where the offset is inserted depends
29297 on the type of instruction, we can establish this from the
29299 switch (newval
>> 12)
29301 case 4: /* PC load. */
29302 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
29303 forced to zero for these loads; md_pcrel_from has already
29304 compensated for this. */
29306 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29307 _("invalid offset, target not word aligned (0x%08lX)"),
29308 (((unsigned long) fixP
->fx_frag
->fr_address
29309 + (unsigned long) fixP
->fx_where
) & ~3)
29310 + (unsigned long) value
);
29312 if (value
& ~0x3fc)
29313 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29314 _("invalid offset, value too big (0x%08lX)"),
29317 newval
|= value
>> 2;
29320 case 9: /* SP load/store. */
29321 if (value
& ~0x3fc)
29322 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29323 _("invalid offset, value too big (0x%08lX)"),
29325 newval
|= value
>> 2;
29328 case 6: /* Word load/store. */
29330 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29331 _("invalid offset, value too big (0x%08lX)"),
29333 newval
|= value
<< 4; /* 6 - 2. */
29336 case 7: /* Byte load/store. */
29338 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29339 _("invalid offset, value too big (0x%08lX)"),
29341 newval
|= value
<< 6;
29344 case 8: /* Halfword load/store. */
29346 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29347 _("invalid offset, value too big (0x%08lX)"),
29349 newval
|= value
<< 5; /* 6 - 1. */
29353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29354 "Unable to process relocation for thumb opcode: %lx",
29355 (unsigned long) newval
);
29358 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29361 case BFD_RELOC_ARM_THUMB_ADD
:
29362 /* This is a complicated relocation, since we use it for all of
29363 the following immediate relocations:
29367 9bit ADD/SUB SP word-aligned
29368 10bit ADD PC/SP word-aligned
29370 The type of instruction being processed is encoded in the
29377 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29379 int rd
= (newval
>> 4) & 0xf;
29380 int rs
= newval
& 0xf;
29381 int subtract
= !!(newval
& 0x8000);
29383 /* Check for HI regs, only very restricted cases allowed:
29384 Adjusting SP, and using PC or SP to get an address. */
29385 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
29386 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
29387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29388 _("invalid Hi register with immediate"));
29390 /* If value is negative, choose the opposite instruction. */
29394 subtract
= !subtract
;
29396 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29397 _("immediate value out of range"));
29402 if (value
& ~0x1fc)
29403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29404 _("invalid immediate for stack address calculation"));
29405 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
29406 newval
|= value
>> 2;
29408 else if (rs
== REG_PC
|| rs
== REG_SP
)
29410 /* PR gas/18541. If the addition is for a defined symbol
29411 within range of an ADR instruction then accept it. */
29414 && fixP
->fx_addsy
!= NULL
)
29418 if (! S_IS_DEFINED (fixP
->fx_addsy
)
29419 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
29420 || S_IS_WEAK (fixP
->fx_addsy
))
29422 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29423 _("address calculation needs a strongly defined nearby symbol"));
29427 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
29429 /* Round up to the next 4-byte boundary. */
29434 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
29438 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29439 _("symbol too far away"));
29449 if (subtract
|| value
& ~0x3fc)
29450 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29451 _("invalid immediate for address calculation (value = 0x%08lX)"),
29452 (unsigned long) (subtract
? - value
: value
));
29453 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
29455 newval
|= value
>> 2;
29460 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29461 _("immediate value out of range"));
29462 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
29463 newval
|= (rd
<< 8) | value
;
29468 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29469 _("immediate value out of range"));
29470 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
29471 newval
|= rd
| (rs
<< 3) | (value
<< 6);
29474 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29477 case BFD_RELOC_ARM_THUMB_IMM
:
29478 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29479 if (value
< 0 || value
> 255)
29480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29481 _("invalid immediate: %ld is out of range"),
29484 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29487 case BFD_RELOC_ARM_THUMB_SHIFT
:
29488 /* 5bit shift value (0..32). LSL cannot take 32. */
29489 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
29490 temp
= newval
& 0xf800;
29491 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
29492 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29493 _("invalid shift value: %ld"), (long) value
);
29494 /* Shifts of zero must be encoded as LSL. */
29496 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
29497 /* Shifts of 32 are encoded as zero. */
29498 else if (value
== 32)
29500 newval
|= value
<< 6;
29501 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29504 case BFD_RELOC_VTABLE_INHERIT
:
29505 case BFD_RELOC_VTABLE_ENTRY
:
29509 case BFD_RELOC_ARM_MOVW
:
29510 case BFD_RELOC_ARM_MOVT
:
29511 case BFD_RELOC_ARM_THUMB_MOVW
:
29512 case BFD_RELOC_ARM_THUMB_MOVT
:
29513 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29515 /* REL format relocations are limited to a 16-bit addend. */
29516 if (!fixP
->fx_done
)
29518 if (value
< -0x8000 || value
> 0x7fff)
29519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29520 _("offset out of range"));
29522 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29523 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29528 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29529 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
29531 newval
= get_thumb32_insn (buf
);
29532 newval
&= 0xfbf08f00;
29533 newval
|= (value
& 0xf000) << 4;
29534 newval
|= (value
& 0x0800) << 15;
29535 newval
|= (value
& 0x0700) << 4;
29536 newval
|= (value
& 0x00ff);
29537 put_thumb32_insn (buf
, newval
);
29541 newval
= md_chars_to_number (buf
, 4);
29542 newval
&= 0xfff0f000;
29543 newval
|= value
& 0x0fff;
29544 newval
|= (value
& 0xf000) << 4;
29545 md_number_to_chars (buf
, newval
, 4);
29550 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29551 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29552 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29553 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29554 gas_assert (!fixP
->fx_done
);
29557 bfd_boolean is_mov
;
29558 bfd_vma encoded_addend
= value
;
29560 /* Check that addend can be encoded in instruction. */
29561 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
29562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29563 _("the offset 0x%08lX is not representable"),
29564 (unsigned long) encoded_addend
);
29566 /* Extract the instruction. */
29567 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
29568 is_mov
= (insn
& 0xf800) == 0x2000;
29573 if (!seg
->use_rela_p
)
29574 insn
|= encoded_addend
;
29580 /* Extract the instruction. */
29581 /* Encoding is the following
29586 /* The following conditions must be true :
29591 rd
= (insn
>> 4) & 0xf;
29593 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
29594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29595 _("Unable to process relocation for thumb opcode: %lx"),
29596 (unsigned long) insn
);
29598 /* Encode as ADD immediate8 thumb 1 code. */
29599 insn
= 0x3000 | (rd
<< 8);
29601 /* Place the encoded addend into the first 8 bits of the
29603 if (!seg
->use_rela_p
)
29604 insn
|= encoded_addend
;
29607 /* Update the instruction. */
29608 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
29612 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29613 case BFD_RELOC_ARM_ALU_PC_G0
:
29614 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29615 case BFD_RELOC_ARM_ALU_PC_G1
:
29616 case BFD_RELOC_ARM_ALU_PC_G2
:
29617 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29618 case BFD_RELOC_ARM_ALU_SB_G0
:
29619 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29620 case BFD_RELOC_ARM_ALU_SB_G1
:
29621 case BFD_RELOC_ARM_ALU_SB_G2
:
29622 gas_assert (!fixP
->fx_done
);
29623 if (!seg
->use_rela_p
)
29626 bfd_vma encoded_addend
;
29627 bfd_vma addend_abs
= llabs (value
);
29629 /* Check that the absolute value of the addend can be
29630 expressed as an 8-bit constant plus a rotation. */
29631 encoded_addend
= encode_arm_immediate (addend_abs
);
29632 if (encoded_addend
== (unsigned int) FAIL
)
29633 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29634 _("the offset 0x%08lX is not representable"),
29635 (unsigned long) addend_abs
);
29637 /* Extract the instruction. */
29638 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29640 /* If the addend is positive, use an ADD instruction.
29641 Otherwise use a SUB. Take care not to destroy the S bit. */
29642 insn
&= 0xff1fffff;
29648 /* Place the encoded addend into the first 12 bits of the
29650 insn
&= 0xfffff000;
29651 insn
|= encoded_addend
;
29653 /* Update the instruction. */
29654 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29658 case BFD_RELOC_ARM_LDR_PC_G0
:
29659 case BFD_RELOC_ARM_LDR_PC_G1
:
29660 case BFD_RELOC_ARM_LDR_PC_G2
:
29661 case BFD_RELOC_ARM_LDR_SB_G0
:
29662 case BFD_RELOC_ARM_LDR_SB_G1
:
29663 case BFD_RELOC_ARM_LDR_SB_G2
:
29664 gas_assert (!fixP
->fx_done
);
29665 if (!seg
->use_rela_p
)
29668 bfd_vma addend_abs
= llabs (value
);
29670 /* Check that the absolute value of the addend can be
29671 encoded in 12 bits. */
29672 if (addend_abs
>= 0x1000)
29673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29674 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
29675 (unsigned long) addend_abs
);
29677 /* Extract the instruction. */
29678 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29680 /* If the addend is negative, clear bit 23 of the instruction.
29681 Otherwise set it. */
29683 insn
&= ~(1 << 23);
29687 /* Place the absolute value of the addend into the first 12 bits
29688 of the instruction. */
29689 insn
&= 0xfffff000;
29690 insn
|= addend_abs
;
29692 /* Update the instruction. */
29693 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29697 case BFD_RELOC_ARM_LDRS_PC_G0
:
29698 case BFD_RELOC_ARM_LDRS_PC_G1
:
29699 case BFD_RELOC_ARM_LDRS_PC_G2
:
29700 case BFD_RELOC_ARM_LDRS_SB_G0
:
29701 case BFD_RELOC_ARM_LDRS_SB_G1
:
29702 case BFD_RELOC_ARM_LDRS_SB_G2
:
29703 gas_assert (!fixP
->fx_done
);
29704 if (!seg
->use_rela_p
)
29707 bfd_vma addend_abs
= llabs (value
);
29709 /* Check that the absolute value of the addend can be
29710 encoded in 8 bits. */
29711 if (addend_abs
>= 0x100)
29712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29713 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
29714 (unsigned long) addend_abs
);
29716 /* Extract the instruction. */
29717 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29719 /* If the addend is negative, clear bit 23 of the instruction.
29720 Otherwise set it. */
29722 insn
&= ~(1 << 23);
29726 /* Place the first four bits of the absolute value of the addend
29727 into the first 4 bits of the instruction, and the remaining
29728 four into bits 8 .. 11. */
29729 insn
&= 0xfffff0f0;
29730 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
29732 /* Update the instruction. */
29733 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29737 case BFD_RELOC_ARM_LDC_PC_G0
:
29738 case BFD_RELOC_ARM_LDC_PC_G1
:
29739 case BFD_RELOC_ARM_LDC_PC_G2
:
29740 case BFD_RELOC_ARM_LDC_SB_G0
:
29741 case BFD_RELOC_ARM_LDC_SB_G1
:
29742 case BFD_RELOC_ARM_LDC_SB_G2
:
29743 gas_assert (!fixP
->fx_done
);
29744 if (!seg
->use_rela_p
)
29747 bfd_vma addend_abs
= llabs (value
);
29749 /* Check that the absolute value of the addend is a multiple of
29750 four and, when divided by four, fits in 8 bits. */
29751 if (addend_abs
& 0x3)
29752 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29753 _("bad offset 0x%08lX (must be word-aligned)"),
29754 (unsigned long) addend_abs
);
29756 if ((addend_abs
>> 2) > 0xff)
29757 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29758 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
29759 (unsigned long) addend_abs
);
29761 /* Extract the instruction. */
29762 insn
= md_chars_to_number (buf
, INSN_SIZE
);
29764 /* If the addend is negative, clear bit 23 of the instruction.
29765 Otherwise set it. */
29767 insn
&= ~(1 << 23);
29771 /* Place the addend (divided by four) into the first eight
29772 bits of the instruction. */
29773 insn
&= 0xfffffff0;
29774 insn
|= addend_abs
>> 2;
29776 /* Update the instruction. */
29777 md_number_to_chars (buf
, insn
, INSN_SIZE
);
29781 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29783 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29784 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29785 && ARM_IS_FUNC (fixP
->fx_addsy
)
29786 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29788 /* Force a relocation for a branch 5 bits wide. */
29791 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
29792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29795 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29797 addressT boff
= value
>> 1;
29799 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29800 newval
|= (boff
<< 7);
29801 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29805 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29807 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29808 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29809 && ARM_IS_FUNC (fixP
->fx_addsy
)
29810 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29814 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
29815 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29816 _("branch out of range"));
29818 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29820 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29822 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
29823 addressT diff
= value
- boff
;
29827 newval
|= 1 << 1; /* T bit. */
29829 else if (diff
!= 2)
29831 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29832 _("out of range label-relative fixup value"));
29834 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29838 case BFD_RELOC_ARM_THUMB_BF17
:
29840 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29841 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29842 && ARM_IS_FUNC (fixP
->fx_addsy
)
29843 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29845 /* Force a relocation for a branch 17 bits wide. */
29849 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
29850 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29853 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29856 addressT immA
, immB
, immC
;
29858 immA
= (value
& 0x0001f000) >> 12;
29859 immB
= (value
& 0x00000ffc) >> 2;
29860 immC
= (value
& 0x00000002) >> 1;
29862 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29863 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29865 newval2
|= (immC
<< 11) | (immB
<< 1);
29866 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29867 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29871 case BFD_RELOC_ARM_THUMB_BF19
:
29873 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29874 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29875 && ARM_IS_FUNC (fixP
->fx_addsy
)
29876 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29878 /* Force a relocation for a branch 19 bits wide. */
29882 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
29883 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29886 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29889 addressT immA
, immB
, immC
;
29891 immA
= (value
& 0x0007f000) >> 12;
29892 immB
= (value
& 0x00000ffc) >> 2;
29893 immC
= (value
& 0x00000002) >> 1;
29895 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29896 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29898 newval2
|= (immC
<< 11) | (immB
<< 1);
29899 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29900 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29904 case BFD_RELOC_ARM_THUMB_BF13
:
29906 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29907 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29908 && ARM_IS_FUNC (fixP
->fx_addsy
)
29909 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29911 /* Force a relocation for a branch 13 bits wide. */
29915 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
29916 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29919 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29922 addressT immA
, immB
, immC
;
29924 immA
= (value
& 0x00001000) >> 12;
29925 immB
= (value
& 0x00000ffc) >> 2;
29926 immC
= (value
& 0x00000002) >> 1;
29928 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
29929 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29931 newval2
|= (immC
<< 11) | (immB
<< 1);
29932 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
29933 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
29937 case BFD_RELOC_ARM_THUMB_LOOP12
:
29939 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
29940 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
29941 && ARM_IS_FUNC (fixP
->fx_addsy
)
29942 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
29944 /* Force a relocation for a branch 12 bits wide. */
29948 bfd_vma insn
= get_thumb32_insn (buf
);
29949 /* le lr, <label>, le <label> or letp lr, <label> */
29950 if (((insn
& 0xffffffff) == 0xf00fc001)
29951 || ((insn
& 0xffffffff) == 0xf02fc001)
29952 || ((insn
& 0xffffffff) == 0xf01fc001))
29955 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
29956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29958 if (fixP
->fx_done
|| !seg
->use_rela_p
)
29960 addressT imml
, immh
;
29962 immh
= (value
& 0x00000ffc) >> 2;
29963 imml
= (value
& 0x00000002) >> 1;
29965 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
29966 newval
|= (imml
<< 11) | (immh
<< 1);
29967 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29971 case BFD_RELOC_ARM_V4BX
:
29972 /* This will need to go in the object file. */
29976 case BFD_RELOC_UNUSED
:
29978 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29979 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29983 /* Translate internal representation of relocation info to BFD target
29987 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29990 bfd_reloc_code_real_type code
;
29992 reloc
= XNEW (arelent
);
29994 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29995 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29996 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29998 if (fixp
->fx_pcrel
)
30000 if (section
->use_rela_p
)
30001 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
30003 fixp
->fx_offset
= reloc
->address
;
30005 reloc
->addend
= fixp
->fx_offset
;
30007 switch (fixp
->fx_r_type
)
30010 if (fixp
->fx_pcrel
)
30012 code
= BFD_RELOC_8_PCREL
;
30015 /* Fall through. */
30018 if (fixp
->fx_pcrel
)
30020 code
= BFD_RELOC_16_PCREL
;
30023 /* Fall through. */
30026 if (fixp
->fx_pcrel
)
30028 code
= BFD_RELOC_32_PCREL
;
30031 /* Fall through. */
30033 case BFD_RELOC_ARM_MOVW
:
30034 if (fixp
->fx_pcrel
)
30036 code
= BFD_RELOC_ARM_MOVW_PCREL
;
30039 /* Fall through. */
30041 case BFD_RELOC_ARM_MOVT
:
30042 if (fixp
->fx_pcrel
)
30044 code
= BFD_RELOC_ARM_MOVT_PCREL
;
30047 /* Fall through. */
30049 case BFD_RELOC_ARM_THUMB_MOVW
:
30050 if (fixp
->fx_pcrel
)
30052 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
30055 /* Fall through. */
30057 case BFD_RELOC_ARM_THUMB_MOVT
:
30058 if (fixp
->fx_pcrel
)
30060 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
30063 /* Fall through. */
30065 case BFD_RELOC_NONE
:
30066 case BFD_RELOC_ARM_PCREL_BRANCH
:
30067 case BFD_RELOC_ARM_PCREL_BLX
:
30068 case BFD_RELOC_RVA
:
30069 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
30070 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
30071 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
30072 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30073 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30074 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30075 case BFD_RELOC_VTABLE_ENTRY
:
30076 case BFD_RELOC_VTABLE_INHERIT
:
30078 case BFD_RELOC_32_SECREL
:
30080 code
= fixp
->fx_r_type
;
30083 case BFD_RELOC_THUMB_PCREL_BLX
:
30085 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
30086 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
30089 code
= BFD_RELOC_THUMB_PCREL_BLX
;
30092 case BFD_RELOC_ARM_LITERAL
:
30093 case BFD_RELOC_ARM_HWLITERAL
:
30094 /* If this is called then the a literal has
30095 been referenced across a section boundary. */
30096 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30097 _("literal referenced across section boundary"));
30101 case BFD_RELOC_ARM_TLS_CALL
:
30102 case BFD_RELOC_ARM_THM_TLS_CALL
:
30103 case BFD_RELOC_ARM_TLS_DESCSEQ
:
30104 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
30105 case BFD_RELOC_ARM_GOT32
:
30106 case BFD_RELOC_ARM_GOTOFF
:
30107 case BFD_RELOC_ARM_GOT_PREL
:
30108 case BFD_RELOC_ARM_PLT32
:
30109 case BFD_RELOC_ARM_TARGET1
:
30110 case BFD_RELOC_ARM_ROSEGREL32
:
30111 case BFD_RELOC_ARM_SBREL32
:
30112 case BFD_RELOC_ARM_PREL31
:
30113 case BFD_RELOC_ARM_TARGET2
:
30114 case BFD_RELOC_ARM_TLS_LDO32
:
30115 case BFD_RELOC_ARM_PCREL_CALL
:
30116 case BFD_RELOC_ARM_PCREL_JUMP
:
30117 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
30118 case BFD_RELOC_ARM_ALU_PC_G0
:
30119 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
30120 case BFD_RELOC_ARM_ALU_PC_G1
:
30121 case BFD_RELOC_ARM_ALU_PC_G2
:
30122 case BFD_RELOC_ARM_LDR_PC_G0
:
30123 case BFD_RELOC_ARM_LDR_PC_G1
:
30124 case BFD_RELOC_ARM_LDR_PC_G2
:
30125 case BFD_RELOC_ARM_LDRS_PC_G0
:
30126 case BFD_RELOC_ARM_LDRS_PC_G1
:
30127 case BFD_RELOC_ARM_LDRS_PC_G2
:
30128 case BFD_RELOC_ARM_LDC_PC_G0
:
30129 case BFD_RELOC_ARM_LDC_PC_G1
:
30130 case BFD_RELOC_ARM_LDC_PC_G2
:
30131 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
30132 case BFD_RELOC_ARM_ALU_SB_G0
:
30133 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
30134 case BFD_RELOC_ARM_ALU_SB_G1
:
30135 case BFD_RELOC_ARM_ALU_SB_G2
:
30136 case BFD_RELOC_ARM_LDR_SB_G0
:
30137 case BFD_RELOC_ARM_LDR_SB_G1
:
30138 case BFD_RELOC_ARM_LDR_SB_G2
:
30139 case BFD_RELOC_ARM_LDRS_SB_G0
:
30140 case BFD_RELOC_ARM_LDRS_SB_G1
:
30141 case BFD_RELOC_ARM_LDRS_SB_G2
:
30142 case BFD_RELOC_ARM_LDC_SB_G0
:
30143 case BFD_RELOC_ARM_LDC_SB_G1
:
30144 case BFD_RELOC_ARM_LDC_SB_G2
:
30145 case BFD_RELOC_ARM_V4BX
:
30146 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
30147 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
30148 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
30149 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
30150 case BFD_RELOC_ARM_GOTFUNCDESC
:
30151 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
30152 case BFD_RELOC_ARM_FUNCDESC
:
30153 case BFD_RELOC_ARM_THUMB_BF17
:
30154 case BFD_RELOC_ARM_THUMB_BF19
:
30155 case BFD_RELOC_ARM_THUMB_BF13
:
30156 code
= fixp
->fx_r_type
;
30159 case BFD_RELOC_ARM_TLS_GOTDESC
:
30160 case BFD_RELOC_ARM_TLS_GD32
:
30161 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
30162 case BFD_RELOC_ARM_TLS_LE32
:
30163 case BFD_RELOC_ARM_TLS_IE32
:
30164 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
30165 case BFD_RELOC_ARM_TLS_LDM32
:
30166 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
30167 /* BFD will include the symbol's address in the addend.
30168 But we don't want that, so subtract it out again here. */
30169 if (!S_IS_COMMON (fixp
->fx_addsy
))
30170 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
30171 code
= fixp
->fx_r_type
;
30175 case BFD_RELOC_ARM_IMMEDIATE
:
30176 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30177 _("internal relocation (type: IMMEDIATE) not fixed up"));
30180 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
30181 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30182 _("ADRL used for a symbol not defined in the same file"));
30185 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
30186 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
30187 case BFD_RELOC_ARM_THUMB_LOOP12
:
30188 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30189 _("%s used for a symbol not defined in the same file"),
30190 bfd_get_reloc_code_name (fixp
->fx_r_type
));
30193 case BFD_RELOC_ARM_OFFSET_IMM
:
30194 if (section
->use_rela_p
)
30196 code
= fixp
->fx_r_type
;
30200 if (fixp
->fx_addsy
!= NULL
30201 && !S_IS_DEFINED (fixp
->fx_addsy
)
30202 && S_IS_LOCAL (fixp
->fx_addsy
))
30204 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30205 _("undefined local label `%s'"),
30206 S_GET_NAME (fixp
->fx_addsy
));
30210 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30211 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
30218 switch (fixp
->fx_r_type
)
30220 case BFD_RELOC_NONE
: type
= "NONE"; break;
30221 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
30222 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
30223 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
30224 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
30225 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
30226 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
30227 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
30228 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
30229 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
30230 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
30231 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
30232 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
30233 default: type
= _("<unknown>"); break;
30235 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30236 _("cannot represent %s relocation in this object file format"),
30243 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
30245 && fixp
->fx_addsy
== GOT_symbol
)
30247 code
= BFD_RELOC_ARM_GOTPC
;
30248 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
30252 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
30254 if (reloc
->howto
== NULL
)
30256 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
30257 _("cannot represent %s relocation in this object file format"),
30258 bfd_get_reloc_code_name (code
));
30262 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
30263 vtable entry to be used in the relocation's section offset. */
30264 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30265 reloc
->address
= fixp
->fx_offset
;
30270 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
30273 cons_fix_new_arm (fragS
* frag
,
30277 bfd_reloc_code_real_type reloc
)
30282 FIXME: @@ Should look at CPU word size. */
30286 reloc
= BFD_RELOC_8
;
30289 reloc
= BFD_RELOC_16
;
30293 reloc
= BFD_RELOC_32
;
30296 reloc
= BFD_RELOC_64
;
30301 if (exp
->X_op
== O_secrel
)
30303 exp
->X_op
= O_symbol
;
30304 reloc
= BFD_RELOC_32_SECREL
;
30308 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
30311 #if defined (OBJ_COFF)
30313 arm_validate_fix (fixS
* fixP
)
30315 /* If the destination of the branch is a defined symbol which does not have
30316 the THUMB_FUNC attribute, then we must be calling a function which has
30317 the (interfacearm) attribute. We look for the Thumb entry point to that
30318 function and change the branch to refer to that function instead. */
30319 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
30320 && fixP
->fx_addsy
!= NULL
30321 && S_IS_DEFINED (fixP
->fx_addsy
)
30322 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
30324 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
30331 arm_force_relocation (struct fix
* fixp
)
30333 #if defined (OBJ_COFF) && defined (TE_PE)
30334 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
30338 /* In case we have a call or a branch to a function in ARM ISA mode from
30339 a thumb function or vice-versa force the relocation. These relocations
30340 are cleared off for some cores that might have blx and simple transformations
30344 switch (fixp
->fx_r_type
)
30346 case BFD_RELOC_ARM_PCREL_JUMP
:
30347 case BFD_RELOC_ARM_PCREL_CALL
:
30348 case BFD_RELOC_THUMB_PCREL_BLX
:
30349 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
30353 case BFD_RELOC_ARM_PCREL_BLX
:
30354 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
30355 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
30356 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
30357 if (ARM_IS_FUNC (fixp
->fx_addsy
))
30366 /* Resolve these relocations even if the symbol is extern or weak.
30367 Technically this is probably wrong due to symbol preemption.
30368 In practice these relocations do not have enough range to be useful
30369 at dynamic link time, and some code (e.g. in the Linux kernel)
30370 expects these references to be resolved. */
30371 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
30372 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
30373 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
30374 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
30375 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
30376 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
30377 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
30378 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
30379 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
30380 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
30381 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
30382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
30383 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
30384 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
30387 /* Always leave these relocations for the linker. */
30388 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30389 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30390 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30393 /* Always generate relocations against function symbols. */
30394 if (fixp
->fx_r_type
== BFD_RELOC_32
30396 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
30399 return generic_force_reloc (fixp
);
30402 #if defined (OBJ_ELF) || defined (OBJ_COFF)
30403 /* Relocations against function names must be left unadjusted,
30404 so that the linker can use this information to generate interworking
30405 stubs. The MIPS version of this function
30406 also prevents relocations that are mips-16 specific, but I do not
30407 know why it does this.
30410 There is one other problem that ought to be addressed here, but
30411 which currently is not: Taking the address of a label (rather
30412 than a function) and then later jumping to that address. Such
30413 addresses also ought to have their bottom bit set (assuming that
30414 they reside in Thumb code), but at the moment they will not. */
30417 arm_fix_adjustable (fixS
* fixP
)
30419 if (fixP
->fx_addsy
== NULL
)
30422 /* Preserve relocations against symbols with function type. */
30423 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
30426 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
30427 && fixP
->fx_subsy
== NULL
)
30430 /* We need the symbol name for the VTABLE entries. */
30431 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
30432 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
30435 /* Don't allow symbols to be discarded on GOT related relocs. */
30436 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
30437 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
30438 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
30439 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
30440 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
30441 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
30442 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
30443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
30444 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
30445 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
30446 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
30447 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
30448 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
30449 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
30450 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
30451 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
30452 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
30455 /* Similarly for group relocations. */
30456 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
30457 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
30458 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
30461 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
30462 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
30463 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
30464 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
30465 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
30466 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
30467 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
30468 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
30469 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
30472 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
30473 offsets, so keep these symbols. */
30474 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
30475 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
30480 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
30484 elf32_arm_target_format (void)
30487 return (target_big_endian
30488 ? "elf32-bigarm-symbian"
30489 : "elf32-littlearm-symbian");
30490 #elif defined (TE_VXWORKS)
30491 return (target_big_endian
30492 ? "elf32-bigarm-vxworks"
30493 : "elf32-littlearm-vxworks");
30494 #elif defined (TE_NACL)
30495 return (target_big_endian
30496 ? "elf32-bigarm-nacl"
30497 : "elf32-littlearm-nacl");
30501 if (target_big_endian
)
30502 return "elf32-bigarm-fdpic";
30504 return "elf32-littlearm-fdpic";
30508 if (target_big_endian
)
30509 return "elf32-bigarm";
30511 return "elf32-littlearm";
30517 armelf_frob_symbol (symbolS
* symp
,
30520 elf_frob_symbol (symp
, puntp
);
30524 /* MD interface: Finalization. */
30529 literal_pool
* pool
;
30531 /* Ensure that all the predication blocks are properly closed. */
30532 check_pred_blocks_finished ();
30534 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
30536 /* Put it at the end of the relevant section. */
30537 subseg_set (pool
->section
, pool
->sub_section
);
30539 arm_elf_change_section ();
30546 /* Remove any excess mapping symbols generated for alignment frags in
30547 SEC. We may have created a mapping symbol before a zero byte
30548 alignment; remove it if there's a mapping symbol after the
30551 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
30552 void *dummy ATTRIBUTE_UNUSED
)
30554 segment_info_type
*seginfo
= seg_info (sec
);
30557 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
30560 for (fragp
= seginfo
->frchainP
->frch_root
;
30562 fragp
= fragp
->fr_next
)
30564 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
30565 fragS
*next
= fragp
->fr_next
;
30567 /* Variable-sized frags have been converted to fixed size by
30568 this point. But if this was variable-sized to start with,
30569 there will be a fixed-size frag after it. So don't handle
30571 if (sym
== NULL
|| next
== NULL
)
30574 if (S_GET_VALUE (sym
) < next
->fr_address
)
30575 /* Not at the end of this frag. */
30577 know (S_GET_VALUE (sym
) == next
->fr_address
);
30581 if (next
->tc_frag_data
.first_map
!= NULL
)
30583 /* Next frag starts with a mapping symbol. Discard this
30585 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30589 if (next
->fr_next
== NULL
)
30591 /* This mapping symbol is at the end of the section. Discard
30593 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
30594 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
30598 /* As long as we have empty frags without any mapping symbols,
30600 /* If the next frag is non-empty and does not start with a
30601 mapping symbol, then this mapping symbol is required. */
30602 if (next
->fr_address
!= next
->fr_next
->fr_address
)
30605 next
= next
->fr_next
;
30607 while (next
!= NULL
);
30612 /* Adjust the symbol table. This marks Thumb symbols as distinct from
30616 arm_adjust_symtab (void)
30621 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30623 if (ARM_IS_THUMB (sym
))
30625 if (THUMB_IS_FUNC (sym
))
30627 /* Mark the symbol as a Thumb function. */
30628 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
30629 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
30630 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
30632 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
30633 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
30635 as_bad (_("%s: unexpected function type: %d"),
30636 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
30638 else switch (S_GET_STORAGE_CLASS (sym
))
30641 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
30644 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
30647 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
30655 if (ARM_IS_INTERWORK (sym
))
30656 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
30663 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
30665 if (ARM_IS_THUMB (sym
))
30667 elf_symbol_type
* elf_sym
;
30669 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
30670 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
30672 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
30673 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
30675 /* If it's a .thumb_func, declare it as so,
30676 otherwise tag label as .code 16. */
30677 if (THUMB_IS_FUNC (sym
))
30678 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
30679 ST_BRANCH_TO_THUMB
);
30680 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
30681 elf_sym
->internal_elf_sym
.st_info
=
30682 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
30687 /* Remove any overlapping mapping symbols generated by alignment frags. */
30688 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
30689 /* Now do generic ELF adjustments. */
30690 elf_adjust_symtab ();
30694 /* MD interface: Initialization. */
30697 set_constant_flonums (void)
30701 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
30702 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
30706 /* Auto-select Thumb mode if it's the only available instruction set for the
30707 given architecture. */
30710 autoselect_thumb_from_cpu_variant (void)
30712 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
30713 opcode_select (16);
30722 if ( (arm_ops_hsh
= hash_new ()) == NULL
30723 || (arm_cond_hsh
= hash_new ()) == NULL
30724 || (arm_vcond_hsh
= hash_new ()) == NULL
30725 || (arm_shift_hsh
= hash_new ()) == NULL
30726 || (arm_psr_hsh
= hash_new ()) == NULL
30727 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
30728 || (arm_reg_hsh
= hash_new ()) == NULL
30729 || (arm_reloc_hsh
= hash_new ()) == NULL
30730 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
30731 as_fatal (_("virtual memory exhausted"));
30733 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
30734 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
30735 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
30736 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
30737 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
30738 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
30739 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
30740 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
30741 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
30742 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
30743 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
30744 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
30745 (void *) (v7m_psrs
+ i
));
30746 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
30747 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
30749 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
30751 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
30752 (void *) (barrier_opt_names
+ i
));
30754 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
30756 struct reloc_entry
* entry
= reloc_names
+ i
;
30758 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
30759 /* This makes encode_branch() use the EABI versions of this relocation. */
30760 entry
->reloc
= BFD_RELOC_UNUSED
;
30762 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
30766 set_constant_flonums ();
30768 /* Set the cpu variant based on the command-line options. We prefer
30769 -mcpu= over -march= if both are set (as for GCC); and we prefer
30770 -mfpu= over any other way of setting the floating point unit.
30771 Use of legacy options with new options are faulted. */
30774 if (mcpu_cpu_opt
|| march_cpu_opt
)
30775 as_bad (_("use of old and new-style options to set CPU type"));
30777 selected_arch
= *legacy_cpu
;
30779 else if (mcpu_cpu_opt
)
30781 selected_arch
= *mcpu_cpu_opt
;
30782 selected_ext
= *mcpu_ext_opt
;
30784 else if (march_cpu_opt
)
30786 selected_arch
= *march_cpu_opt
;
30787 selected_ext
= *march_ext_opt
;
30789 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
30794 as_bad (_("use of old and new-style options to set FPU type"));
30796 selected_fpu
= *legacy_fpu
;
30799 selected_fpu
= *mfpu_opt
;
30802 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
30803 || defined (TE_NetBSD) || defined (TE_VXWORKS))
30804 /* Some environments specify a default FPU. If they don't, infer it
30805 from the processor. */
30807 selected_fpu
= *mcpu_fpu_opt
;
30808 else if (march_fpu_opt
)
30809 selected_fpu
= *march_fpu_opt
;
30811 selected_fpu
= fpu_default
;
30815 if (ARM_FEATURE_ZERO (selected_fpu
))
30817 if (!no_cpu_selected ())
30818 selected_fpu
= fpu_default
;
30820 selected_fpu
= fpu_arch_fpa
;
30824 if (ARM_FEATURE_ZERO (selected_arch
))
30826 selected_arch
= cpu_default
;
30827 selected_cpu
= selected_arch
;
30829 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30831 /* Autodection of feature mode: allow all features in cpu_variant but leave
30832 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
30833 after all instruction have been processed and we can decide what CPU
30834 should be selected. */
30835 if (ARM_FEATURE_ZERO (selected_arch
))
30836 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
30838 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
30841 autoselect_thumb_from_cpu_variant ();
30843 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
30845 #if defined OBJ_COFF || defined OBJ_ELF
30847 unsigned int flags
= 0;
30849 #if defined OBJ_ELF
30850 flags
= meabi_flags
;
30852 switch (meabi_flags
)
30854 case EF_ARM_EABI_UNKNOWN
:
30856 /* Set the flags in the private structure. */
30857 if (uses_apcs_26
) flags
|= F_APCS26
;
30858 if (support_interwork
) flags
|= F_INTERWORK
;
30859 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
30860 if (pic_code
) flags
|= F_PIC
;
30861 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
30862 flags
|= F_SOFT_FLOAT
;
30864 switch (mfloat_abi_opt
)
30866 case ARM_FLOAT_ABI_SOFT
:
30867 case ARM_FLOAT_ABI_SOFTFP
:
30868 flags
|= F_SOFT_FLOAT
;
30871 case ARM_FLOAT_ABI_HARD
:
30872 if (flags
& F_SOFT_FLOAT
)
30873 as_bad (_("hard-float conflicts with specified fpu"));
30877 /* Using pure-endian doubles (even if soft-float). */
30878 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
30879 flags
|= F_VFP_FLOAT
;
30881 #if defined OBJ_ELF
30882 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
30883 flags
|= EF_ARM_MAVERICK_FLOAT
;
30886 case EF_ARM_EABI_VER4
:
30887 case EF_ARM_EABI_VER5
:
30888 /* No additional flags to set. */
30895 bfd_set_private_flags (stdoutput
, flags
);
30897 /* We have run out flags in the COFF header to encode the
30898 status of ATPCS support, so instead we create a dummy,
30899 empty, debug section called .arm.atpcs. */
30904 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
30908 bfd_set_section_flags (sec
, SEC_READONLY
| SEC_DEBUGGING
);
30909 bfd_set_section_size (sec
, 0);
30910 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
30916 /* Record the CPU type as well. */
30917 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
30918 mach
= bfd_mach_arm_iWMMXt2
;
30919 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
30920 mach
= bfd_mach_arm_iWMMXt
;
30921 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
30922 mach
= bfd_mach_arm_XScale
;
30923 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
30924 mach
= bfd_mach_arm_ep9312
;
30925 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
30926 mach
= bfd_mach_arm_5TE
;
30927 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
30929 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30930 mach
= bfd_mach_arm_5T
;
30932 mach
= bfd_mach_arm_5
;
30934 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
30936 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
30937 mach
= bfd_mach_arm_4T
;
30939 mach
= bfd_mach_arm_4
;
30941 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
30942 mach
= bfd_mach_arm_3M
;
30943 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
30944 mach
= bfd_mach_arm_3
;
30945 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
30946 mach
= bfd_mach_arm_2a
;
30947 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
30948 mach
= bfd_mach_arm_2
;
30950 mach
= bfd_mach_arm_unknown
;
30952 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
30955 /* Command line processing. */
30958 Invocation line includes a switch not recognized by the base assembler.
30959 See if it's a processor-specific option.
30961 This routine is somewhat complicated by the need for backwards
30962 compatibility (since older releases of gcc can't be changed).
30963 The new options try to make the interface as compatible as
30966 New options (supported) are:
30968 -mcpu=<cpu name> Assemble for selected processor
30969 -march=<architecture name> Assemble for selected architecture
30970 -mfpu=<fpu architecture> Assemble for selected FPU.
30971 -EB/-mbig-endian Big-endian
30972 -EL/-mlittle-endian Little-endian
30973 -k Generate PIC code
30974 -mthumb Start in Thumb mode
30975 -mthumb-interwork Code supports ARM/Thumb interworking
30977 -m[no-]warn-deprecated Warn about deprecated features
30978 -m[no-]warn-syms Warn when symbols match instructions
30980 For now we will also provide support for:
30982 -mapcs-32 32-bit Program counter
30983 -mapcs-26 26-bit Program counter
30984 -macps-float Floats passed in FP registers
30985 -mapcs-reentrant Reentrant code
30987 (sometime these will probably be replaced with -mapcs=<list of options>
30988 and -matpcs=<list of options>)
30990 The remaining options are only supported for back-wards compatibility.
30991 Cpu variants, the arm part is optional:
30992 -m[arm]1 Currently not supported.
30993 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30994 -m[arm]3 Arm 3 processor
30995 -m[arm]6[xx], Arm 6 processors
30996 -m[arm]7[xx][t][[d]m] Arm 7 processors
30997 -m[arm]8[10] Arm 8 processors
30998 -m[arm]9[20][tdmi] Arm 9 processors
30999 -mstrongarm[110[0]] StrongARM processors
31000 -mxscale XScale processors
31001 -m[arm]v[2345[t[e]]] Arm architectures
31002 -mall All (except the ARM1)
31004 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
31005 -mfpe-old (No float load/store multiples)
31006 -mvfpxd VFP Single precision
31008 -mno-fpu Disable all floating point instructions
31010 The following CPU names are recognized:
31011 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
31012 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
31013 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
31014 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
31015 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
31016 arm10t arm10e, arm1020t, arm1020e, arm10200e,
31017 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
31021 const char * md_shortopts
= "m:k";
31023 #ifdef ARM_BI_ENDIAN
31024 #define OPTION_EB (OPTION_MD_BASE + 0)
31025 #define OPTION_EL (OPTION_MD_BASE + 1)
31027 #if TARGET_BYTES_BIG_ENDIAN
31028 #define OPTION_EB (OPTION_MD_BASE + 0)
31030 #define OPTION_EL (OPTION_MD_BASE + 1)
31033 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
31034 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
31036 struct option md_longopts
[] =
31039 {"EB", no_argument
, NULL
, OPTION_EB
},
31042 {"EL", no_argument
, NULL
, OPTION_EL
},
31044 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
31046 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
31048 {NULL
, no_argument
, NULL
, 0}
31051 size_t md_longopts_size
= sizeof (md_longopts
);
31053 struct arm_option_table
31055 const char * option
; /* Option name to match. */
31056 const char * help
; /* Help information. */
31057 int * var
; /* Variable to change. */
31058 int value
; /* What to change it to. */
31059 const char * deprecated
; /* If non-null, print this message. */
31062 struct arm_option_table arm_opts
[] =
31064 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
31065 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
31066 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
31067 &support_interwork
, 1, NULL
},
31068 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
31069 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
31070 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
31072 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
31073 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
31074 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
31075 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
31078 /* These are recognized by the assembler, but have no affect on code. */
31079 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
31080 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
31082 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
31083 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
31084 &warn_on_deprecated
, 0, NULL
},
31086 {"mwarn-restrict-it", N_("warn about performance deprecated IT instructions"
31087 " in ARMv8-A and ARMv8-R"), &warn_on_restrict_it
, 1, NULL
},
31088 {"mno-warn-restrict-it", NULL
, &warn_on_restrict_it
, 0, NULL
},
31090 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
31091 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
31092 {NULL
, NULL
, NULL
, 0, NULL
}
31095 struct arm_legacy_option_table
31097 const char * option
; /* Option name to match. */
31098 const arm_feature_set
** var
; /* Variable to change. */
31099 const arm_feature_set value
; /* What to change it to. */
31100 const char * deprecated
; /* If non-null, print this message. */
31103 const struct arm_legacy_option_table arm_legacy_opts
[] =
31105 /* DON'T add any new processors to this list -- we want the whole list
31106 to go away... Add them to the processors table instead. */
31107 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31108 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
31109 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31110 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
31111 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31112 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
31113 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31114 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
31115 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31116 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
31117 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31118 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
31119 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31120 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
31121 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31122 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
31123 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31124 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
31125 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31126 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
31127 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31128 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
31129 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31130 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
31131 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31132 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
31133 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31134 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
31135 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31136 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
31137 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31138 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
31139 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31140 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
31141 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31142 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
31143 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31144 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
31145 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31146 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
31147 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31148 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
31149 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31150 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
31151 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31152 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
31153 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31154 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31155 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31156 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
31157 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31158 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
31159 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31160 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
31161 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31162 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
31163 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31164 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
31165 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31166 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
31167 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31168 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
31169 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31170 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
31171 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31172 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
31173 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31174 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
31175 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
31176 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
31177 N_("use -mcpu=strongarm110")},
31178 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
31179 N_("use -mcpu=strongarm1100")},
31180 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
31181 N_("use -mcpu=strongarm1110")},
31182 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
31183 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
31184 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
31186 /* Architecture variants -- don't add any more to this list either. */
31187 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31188 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
31189 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31190 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
31191 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31192 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
31193 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31194 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
31195 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31196 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
31197 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31198 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
31199 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31200 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
31201 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31202 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
31203 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31204 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
31206 /* Floating point variants -- don't add any more to this list either. */
31207 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
31208 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
31209 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
31210 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
31211 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
31213 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
31216 struct arm_cpu_option_table
31220 const arm_feature_set value
;
31221 const arm_feature_set ext
;
31222 /* For some CPUs we assume an FPU unless the user explicitly sets
31224 const arm_feature_set default_fpu
;
31225 /* The canonical name of the CPU, or NULL to use NAME converted to upper
31227 const char * canonical_name
;
31230 /* This list should, at a minimum, contain all the cpu names
31231 recognized by GCC. */
31232 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
31234 static const struct arm_cpu_option_table arm_cpus
[] =
31236 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
31239 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
31242 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
31245 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
31248 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
31251 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
31254 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
31257 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
31260 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
31263 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
31266 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
31269 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
31272 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
31275 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
31278 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
31281 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
31284 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
31287 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
31290 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
31293 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
31296 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
31299 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
31302 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
31305 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
31308 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
31311 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
31314 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
31317 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
31320 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
31323 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
31326 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
31329 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
31332 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
31335 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
31338 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
31341 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
31344 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
31347 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
31350 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
31353 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
31356 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
31359 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
31362 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
31365 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
31368 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
31371 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
31375 /* For V5 or later processors we default to using VFP; but the user
31376 should really set the FPU type explicitly. */
31377 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
31380 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
31383 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31386 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
31389 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
31392 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
31395 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
31398 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
31401 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
31404 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
31407 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
31410 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
31413 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
31416 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
31419 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
31422 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
31425 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
31428 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
31431 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
31434 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
31437 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
31440 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
31443 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
31446 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
31449 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
31452 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
31455 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
31458 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
31461 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
31464 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
31467 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
31470 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
31473 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
31476 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
31479 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
31482 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
31485 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
31486 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31488 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
31490 FPU_ARCH_NEON_VFP_V4
),
31491 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
31492 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31493 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31494 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
31495 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31496 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
31497 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
31499 FPU_ARCH_NEON_VFP_V4
),
31500 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
31502 FPU_ARCH_NEON_VFP_V4
),
31503 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
31505 FPU_ARCH_NEON_VFP_V4
),
31506 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
31507 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31508 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31509 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
31510 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31511 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31512 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
31513 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31514 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31515 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
31516 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31517 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31518 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
31519 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31520 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31521 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
31522 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31523 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31524 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
31525 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31526 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31527 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
31528 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31529 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31530 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
31531 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31532 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31533 ARM_CPU_OPT ("cortex-a76ae", "Cortex-A76AE", ARM_ARCH_V8_2A
,
31534 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31535 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31536 ARM_CPU_OPT ("cortex-a77", "Cortex-A77", ARM_ARCH_V8_2A
,
31537 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31538 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31539 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
31540 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31541 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31542 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
31545 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
31547 FPU_ARCH_VFP_V3D16
),
31548 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
31549 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31551 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
31552 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31553 FPU_ARCH_VFP_V3D16
),
31554 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
31555 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
31556 FPU_ARCH_VFP_V3D16
),
31557 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
31558 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31559 FPU_ARCH_NEON_VFP_ARMV8
),
31560 ARM_CPU_OPT ("cortex-m35p", "Cortex-M35P", ARM_ARCH_V8M_MAIN
,
31561 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31563 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
31564 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31566 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
31569 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
31572 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
31575 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
31578 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
31581 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
31584 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
31587 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
31588 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31589 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31590 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
31591 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31592 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
31593 /* ??? XSCALE is really an architecture. */
31594 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
31598 /* ??? iwmmxt is not a processor. */
31599 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
31602 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
31605 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
31610 ARM_CPU_OPT ("ep9312", "ARM920T",
31611 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
31612 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
31614 /* Marvell processors. */
31615 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
31616 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31617 FPU_ARCH_VFP_V3D16
),
31618 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
31619 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
31620 FPU_ARCH_NEON_VFP_V4
),
31622 /* APM X-Gene family. */
31623 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
31625 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31626 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
31627 ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
),
31628 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
31630 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31634 struct arm_ext_table
31638 const arm_feature_set merge
;
31639 const arm_feature_set clear
;
31642 struct arm_arch_option_table
31646 const arm_feature_set value
;
31647 const arm_feature_set default_fpu
;
31648 const struct arm_ext_table
* ext_table
;
31651 /* Used to add support for +E and +noE extension. */
31652 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
31653 /* Used to add support for a +E extension. */
31654 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
31655 /* Used to add support for a +noE extension. */
31656 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
31658 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
31659 ~0 & ~FPU_ENDIAN_PURE)
31661 static const struct arm_ext_table armv5te_ext_table
[] =
31663 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
31664 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31667 static const struct arm_ext_table armv7_ext_table
[] =
31669 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31670 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31673 static const struct arm_ext_table armv7ve_ext_table
[] =
31675 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
31676 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
31677 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31678 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31679 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31680 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
31681 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31683 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
31684 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31686 /* Aliases for +simd. */
31687 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31689 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31690 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31691 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31693 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31696 static const struct arm_ext_table armv7a_ext_table
[] =
31698 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31699 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31700 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
31701 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31702 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
31703 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
31704 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
31706 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
31707 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
31709 /* Aliases for +simd. */
31710 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31711 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
31713 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
31714 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
31716 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
31717 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
31718 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31721 static const struct arm_ext_table armv7r_ext_table
[] =
31723 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
31724 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
31725 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
31726 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
31727 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
31728 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
31729 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
31730 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
31731 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31734 static const struct arm_ext_table armv7em_ext_table
[] =
31736 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
31737 /* Alias for +fp, used to be known as fpv4-sp-d16. */
31738 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
31739 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
31740 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31741 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
31742 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31745 static const struct arm_ext_table armv8a_ext_table
[] =
31747 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31748 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31749 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31750 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31752 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31753 should use the +simd option to turn on FP. */
31754 ARM_REMOVE ("fp", ALL_FP
),
31755 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31756 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31757 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31761 static const struct arm_ext_table armv81a_ext_table
[] =
31763 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31764 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31765 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31767 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31768 should use the +simd option to turn on FP. */
31769 ARM_REMOVE ("fp", ALL_FP
),
31770 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31771 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31772 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31775 static const struct arm_ext_table armv82a_ext_table
[] =
31777 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
31778 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
31779 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
31780 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31781 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31782 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
31783 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31784 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31786 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31787 should use the +simd option to turn on FP. */
31788 ARM_REMOVE ("fp", ALL_FP
),
31789 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31790 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31791 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31794 static const struct arm_ext_table armv84a_ext_table
[] =
31796 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31797 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31798 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31799 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31800 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31801 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31803 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31804 should use the +simd option to turn on FP. */
31805 ARM_REMOVE ("fp", ALL_FP
),
31806 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
31807 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
31808 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31811 static const struct arm_ext_table armv85a_ext_table
[] =
31813 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
31814 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
31815 ARM_ADD ("bf16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_BF16
)),
31816 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31817 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
31818 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31820 /* Armv8-a does not allow an FP implementation without SIMD, so the user
31821 should use the +simd option to turn on FP. */
31822 ARM_REMOVE ("fp", ALL_FP
),
31823 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31826 static const struct arm_ext_table armv86a_ext_table
[] =
31828 ARM_ADD ("i8mm", ARM_FEATURE_CORE_HIGH (ARM_EXT2_I8MM
)),
31829 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31832 #define CDE_EXTENSIONS \
31833 ARM_ADD ("cdecp0", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE0)), \
31834 ARM_ADD ("cdecp1", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE1)), \
31835 ARM_ADD ("cdecp2", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE2)), \
31836 ARM_ADD ("cdecp3", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE3)), \
31837 ARM_ADD ("cdecp4", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE4)), \
31838 ARM_ADD ("cdecp5", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE5)), \
31839 ARM_ADD ("cdecp6", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE6)), \
31840 ARM_ADD ("cdecp7", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CDE | ARM_EXT2_CDE7))
31842 static const struct arm_ext_table armv8m_main_ext_table
[] =
31844 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31845 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31846 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
31847 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
31849 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31853 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
31855 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
),
31856 ARM_FEATURE_CORE_LOW (ARM_AEXT_V8M_MAIN_DSP
)),
31858 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31859 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
31862 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
31863 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31864 ARM_EXT ("mve", ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
, ARM_EXT2_MVE
, 0),
31865 ARM_FEATURE_CORE_HIGH (ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
)),
31867 ARM_FEATURE (ARM_AEXT_V8M_MAIN_DSP
,
31868 ARM_EXT2_FP16_INST
| ARM_EXT2_MVE
| ARM_EXT2_MVE_FP
,
31869 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
31871 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31874 #undef CDE_EXTENSIONS
31876 static const struct arm_ext_table armv8r_ext_table
[] =
31878 ARM_ADD ("crc", ARM_FEATURE_CORE_HIGH (ARM_EXT2_CRC
)),
31879 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
31880 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31881 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
31882 ARM_REMOVE ("fp", ALL_FP
),
31883 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
31884 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
31887 /* This list should, at a minimum, contain all the architecture names
31888 recognized by GCC. */
31889 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
31890 #define ARM_ARCH_OPT2(N, V, DF, ext) \
31891 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
31893 static const struct arm_arch_option_table arm_archs
[] =
31895 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
31896 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
31897 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
31898 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31899 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
31900 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
31901 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
31902 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
31903 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
31904 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
31905 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
31906 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
31907 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
31908 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
31909 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
31910 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
31911 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
31912 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31913 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
31914 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
31915 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
31916 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
31917 kept to preserve existing behaviour. */
31918 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31919 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
31920 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
31921 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
31922 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
31923 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
31924 kept to preserve existing behaviour. */
31925 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31926 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
31927 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
31928 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
31929 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
31930 /* The official spelling of the ARMv7 profile variants is the dashed form.
31931 Accept the non-dashed form for compatibility with old toolchains. */
31932 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31933 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
31934 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31935 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31936 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
31937 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
31938 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
31939 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
31940 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
31941 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
31943 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
31945 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
31946 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
31947 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
31948 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
31949 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
31950 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
31951 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
31952 ARM_ARCH_OPT2 ("armv8.6-a", ARM_ARCH_V8_6A
, FPU_ARCH_VFP
, armv86a
),
31953 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
31954 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
31955 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
31956 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
31958 #undef ARM_ARCH_OPT
31960 /* ISA extensions in the co-processor and main instruction set space. */
31962 struct arm_option_extension_value_table
31966 const arm_feature_set merge_value
;
31967 const arm_feature_set clear_value
;
31968 /* List of architectures for which an extension is available. ARM_ARCH_NONE
31969 indicates that an extension is available for all architectures while
31970 ARM_ANY marks an empty entry. */
31971 const arm_feature_set allowed_archs
[2];
31974 /* The following table must be in alphabetical order with a NULL last entry. */
31976 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
31977 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
31979 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
31980 use the context sensitive approach using arm_ext_table's. */
31981 static const struct arm_option_extension_value_table arm_extensions
[] =
31983 ARM_EXT_OPT ("crc", ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31984 ARM_FEATURE_CORE_HIGH(ARM_EXT2_CRC
),
31985 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31986 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
31987 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
31988 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31989 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
31990 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
31992 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31993 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
31994 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
31995 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
31996 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31997 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
31998 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
32000 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32001 | ARM_EXT2_FP16_FML
),
32002 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
32003 | ARM_EXT2_FP16_FML
),
32005 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32006 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
32007 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32008 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32009 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
32010 Thumb divide instruction. Due to this having the same name as the
32011 previous entry, this will be ignored when doing command-line parsing and
32012 only considered by build attribute selection code. */
32013 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32014 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
32015 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
32016 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
32017 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
32018 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
32019 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
32020 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
32021 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
32022 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32023 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
32024 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
32025 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
32026 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32027 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
32028 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
32029 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
32030 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
32031 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32032 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32033 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
32035 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
32036 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
32037 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32038 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
32039 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
32040 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
32041 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32042 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
32044 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32045 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
32046 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
32047 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32048 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
32049 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
32050 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
32051 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
32053 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
32054 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
32055 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
32056 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
32057 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
32061 /* ISA floating-point and Advanced SIMD extensions. */
32062 struct arm_option_fpu_value_table
32065 const arm_feature_set value
;
32068 /* This list should, at a minimum, contain all the fpu names
32069 recognized by GCC. */
32070 static const struct arm_option_fpu_value_table arm_fpus
[] =
32072 {"softfpa", FPU_NONE
},
32073 {"fpe", FPU_ARCH_FPE
},
32074 {"fpe2", FPU_ARCH_FPE
},
32075 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
32076 {"fpa", FPU_ARCH_FPA
},
32077 {"fpa10", FPU_ARCH_FPA
},
32078 {"fpa11", FPU_ARCH_FPA
},
32079 {"arm7500fe", FPU_ARCH_FPA
},
32080 {"softvfp", FPU_ARCH_VFP
},
32081 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
32082 {"vfp", FPU_ARCH_VFP_V2
},
32083 {"vfp9", FPU_ARCH_VFP_V2
},
32084 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
32085 {"vfp10", FPU_ARCH_VFP_V2
},
32086 {"vfp10-r0", FPU_ARCH_VFP_V1
},
32087 {"vfpxd", FPU_ARCH_VFP_V1xD
},
32088 {"vfpv2", FPU_ARCH_VFP_V2
},
32089 {"vfpv3", FPU_ARCH_VFP_V3
},
32090 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
32091 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
32092 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
32093 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
32094 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
32095 {"arm1020t", FPU_ARCH_VFP_V1
},
32096 {"arm1020e", FPU_ARCH_VFP_V2
},
32097 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
32098 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
32099 {"maverick", FPU_ARCH_MAVERICK
},
32100 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32101 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
32102 {"neon-fp16", FPU_ARCH_NEON_FP16
},
32103 {"vfpv4", FPU_ARCH_VFP_V4
},
32104 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
32105 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
32106 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
32107 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
32108 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
32109 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
32110 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
32111 {"crypto-neon-fp-armv8",
32112 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
32113 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
32114 {"crypto-neon-fp-armv8.1",
32115 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
32116 {NULL
, ARM_ARCH_NONE
}
32119 struct arm_option_value_table
32125 static const struct arm_option_value_table arm_float_abis
[] =
32127 {"hard", ARM_FLOAT_ABI_HARD
},
32128 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
32129 {"soft", ARM_FLOAT_ABI_SOFT
},
32134 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
32135 static const struct arm_option_value_table arm_eabis
[] =
32137 {"gnu", EF_ARM_EABI_UNKNOWN
},
32138 {"4", EF_ARM_EABI_VER4
},
32139 {"5", EF_ARM_EABI_VER5
},
32144 struct arm_long_option_table
32146 const char * option
; /* Substring to match. */
32147 const char * help
; /* Help information. */
32148 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
32149 const char * deprecated
; /* If non-null, print this message. */
32153 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
32154 arm_feature_set
*ext_set
,
32155 const struct arm_ext_table
*ext_table
)
32157 /* We insist on extensions being specified in alphabetical order, and with
32158 extensions being added before being removed. We achieve this by having
32159 the global ARM_EXTENSIONS table in alphabetical order, and using the
32160 ADDING_VALUE variable to indicate whether we are adding an extension (1)
32161 or removing it (0) and only allowing it to change in the order
32163 const struct arm_option_extension_value_table
* opt
= NULL
;
32164 const arm_feature_set arm_any
= ARM_ANY
;
32165 int adding_value
= -1;
32167 while (str
!= NULL
&& *str
!= 0)
32174 as_bad (_("invalid architectural extension"));
32179 ext
= strchr (str
, '+');
32184 len
= strlen (str
);
32186 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
32188 if (adding_value
!= 0)
32191 opt
= arm_extensions
;
32199 if (adding_value
== -1)
32202 opt
= arm_extensions
;
32204 else if (adding_value
!= 1)
32206 as_bad (_("must specify extensions to add before specifying "
32207 "those to remove"));
32214 as_bad (_("missing architectural extension"));
32218 gas_assert (adding_value
!= -1);
32219 gas_assert (opt
!= NULL
);
32221 if (ext_table
!= NULL
)
32223 const struct arm_ext_table
* ext_opt
= ext_table
;
32224 bfd_boolean found
= FALSE
;
32225 for (; ext_opt
->name
!= NULL
; ext_opt
++)
32226 if (ext_opt
->name_len
== len
32227 && strncmp (ext_opt
->name
, str
, len
) == 0)
32231 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
32232 /* TODO: Option not supported. When we remove the
32233 legacy table this case should error out. */
32236 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
32240 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
32241 /* TODO: Option not supported. When we remove the
32242 legacy table this case should error out. */
32244 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
32256 /* Scan over the options table trying to find an exact match. */
32257 for (; opt
->name
!= NULL
; opt
++)
32258 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32260 int i
, nb_allowed_archs
=
32261 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32262 /* Check we can apply the extension to this architecture. */
32263 for (i
= 0; i
< nb_allowed_archs
; i
++)
32266 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
32268 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
32271 if (i
== nb_allowed_archs
)
32273 as_bad (_("extension does not apply to the base architecture"));
32277 /* Add or remove the extension. */
32279 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
32281 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
32283 /* Allowing Thumb division instructions for ARMv7 in autodetection
32284 rely on this break so that duplicate extensions (extensions
32285 with the same name as a previous extension in the list) are not
32286 considered for command-line parsing. */
32290 if (opt
->name
== NULL
)
32292 /* Did we fail to find an extension because it wasn't specified in
32293 alphabetical order, or because it does not exist? */
32295 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32296 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32299 if (opt
->name
== NULL
)
32300 as_bad (_("unknown architectural extension `%s'"), str
);
32302 as_bad (_("architectural extensions must be specified in "
32303 "alphabetical order"));
32309 /* We should skip the extension we've just matched the next time
32321 arm_parse_fp16_opt (const char *str
)
32323 if (strcasecmp (str
, "ieee") == 0)
32324 fp16_format
= ARM_FP16_FORMAT_IEEE
;
32325 else if (strcasecmp (str
, "alternative") == 0)
32326 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
32329 as_bad (_("unrecognised float16 format \"%s\""), str
);
32337 arm_parse_cpu (const char *str
)
32339 const struct arm_cpu_option_table
*opt
;
32340 const char *ext
= strchr (str
, '+');
32346 len
= strlen (str
);
32350 as_bad (_("missing cpu name `%s'"), str
);
32354 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
32355 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32357 mcpu_cpu_opt
= &opt
->value
;
32358 if (mcpu_ext_opt
== NULL
)
32359 mcpu_ext_opt
= XNEW (arm_feature_set
);
32360 *mcpu_ext_opt
= opt
->ext
;
32361 mcpu_fpu_opt
= &opt
->default_fpu
;
32362 if (opt
->canonical_name
)
32364 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
32365 strcpy (selected_cpu_name
, opt
->canonical_name
);
32371 if (len
>= sizeof selected_cpu_name
)
32372 len
= (sizeof selected_cpu_name
) - 1;
32374 for (i
= 0; i
< len
; i
++)
32375 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32376 selected_cpu_name
[i
] = 0;
32380 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
32385 as_bad (_("unknown cpu `%s'"), str
);
32390 arm_parse_arch (const char *str
)
32392 const struct arm_arch_option_table
*opt
;
32393 const char *ext
= strchr (str
, '+');
32399 len
= strlen (str
);
32403 as_bad (_("missing architecture name `%s'"), str
);
32407 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
32408 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
32410 march_cpu_opt
= &opt
->value
;
32411 if (march_ext_opt
== NULL
)
32412 march_ext_opt
= XNEW (arm_feature_set
);
32413 *march_ext_opt
= arm_arch_none
;
32414 march_fpu_opt
= &opt
->default_fpu
;
32415 selected_ctx_ext_table
= opt
->ext_table
;
32416 strcpy (selected_cpu_name
, opt
->name
);
32419 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
32425 as_bad (_("unknown architecture `%s'\n"), str
);
32430 arm_parse_fpu (const char * str
)
32432 const struct arm_option_fpu_value_table
* opt
;
32434 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32435 if (streq (opt
->name
, str
))
32437 mfpu_opt
= &opt
->value
;
32441 as_bad (_("unknown floating point format `%s'\n"), str
);
32446 arm_parse_float_abi (const char * str
)
32448 const struct arm_option_value_table
* opt
;
32450 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
32451 if (streq (opt
->name
, str
))
32453 mfloat_abi_opt
= opt
->value
;
32457 as_bad (_("unknown floating point abi `%s'\n"), str
);
32463 arm_parse_eabi (const char * str
)
32465 const struct arm_option_value_table
*opt
;
32467 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
32468 if (streq (opt
->name
, str
))
32470 meabi_flags
= opt
->value
;
32473 as_bad (_("unknown EABI `%s'\n"), str
);
32479 arm_parse_it_mode (const char * str
)
32481 bfd_boolean ret
= TRUE
;
32483 if (streq ("arm", str
))
32484 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
32485 else if (streq ("thumb", str
))
32486 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
32487 else if (streq ("always", str
))
32488 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
32489 else if (streq ("never", str
))
32490 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
32493 as_bad (_("unknown implicit IT mode `%s', should be "\
32494 "arm, thumb, always, or never."), str
);
32502 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
32504 codecomposer_syntax
= TRUE
;
32505 arm_comment_chars
[0] = ';';
32506 arm_line_separator_chars
[0] = 0;
32510 struct arm_long_option_table arm_long_opts
[] =
32512 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
32513 arm_parse_cpu
, NULL
},
32514 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
32515 arm_parse_arch
, NULL
},
32516 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
32517 arm_parse_fpu
, NULL
},
32518 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
32519 arm_parse_float_abi
, NULL
},
32521 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
32522 arm_parse_eabi
, NULL
},
32524 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
32525 arm_parse_it_mode
, NULL
},
32526 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
32527 arm_ccs_mode
, NULL
},
32529 N_("[ieee|alternative]\n\
32530 set the encoding for half precision floating point "
32531 "numbers to IEEE\n\
32532 or Arm alternative format."),
32533 arm_parse_fp16_opt
, NULL
},
32534 {NULL
, NULL
, 0, NULL
}
32538 md_parse_option (int c
, const char * arg
)
32540 struct arm_option_table
*opt
;
32541 const struct arm_legacy_option_table
*fopt
;
32542 struct arm_long_option_table
*lopt
;
32548 target_big_endian
= 1;
32554 target_big_endian
= 0;
32558 case OPTION_FIX_V4BX
:
32566 #endif /* OBJ_ELF */
32569 /* Listing option. Just ignore these, we don't support additional
32574 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32576 if (c
== opt
->option
[0]
32577 && ((arg
== NULL
&& opt
->option
[1] == 0)
32578 || streq (arg
, opt
->option
+ 1)))
32580 /* If the option is deprecated, tell the user. */
32581 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
32582 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32583 arg
? arg
: "", _(opt
->deprecated
));
32585 if (opt
->var
!= NULL
)
32586 *opt
->var
= opt
->value
;
32592 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
32594 if (c
== fopt
->option
[0]
32595 && ((arg
== NULL
&& fopt
->option
[1] == 0)
32596 || streq (arg
, fopt
->option
+ 1)))
32598 /* If the option is deprecated, tell the user. */
32599 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
32600 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
32601 arg
? arg
: "", _(fopt
->deprecated
));
32603 if (fopt
->var
!= NULL
)
32604 *fopt
->var
= &fopt
->value
;
32610 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32612 /* These options are expected to have an argument. */
32613 if (c
== lopt
->option
[0]
32615 && strncmp (arg
, lopt
->option
+ 1,
32616 strlen (lopt
->option
+ 1)) == 0)
32618 /* If the option is deprecated, tell the user. */
32619 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
32620 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
32621 _(lopt
->deprecated
));
32623 /* Call the sup-option parser. */
32624 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
32635 md_show_usage (FILE * fp
)
32637 struct arm_option_table
*opt
;
32638 struct arm_long_option_table
*lopt
;
32640 fprintf (fp
, _(" ARM-specific assembler options:\n"));
32642 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
32643 if (opt
->help
!= NULL
)
32644 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
32646 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
32647 if (lopt
->help
!= NULL
)
32648 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
32652 -EB assemble code for a big-endian cpu\n"));
32657 -EL assemble code for a little-endian cpu\n"));
32661 --fix-v4bx Allow BX in ARMv4 code\n"));
32665 --fdpic generate an FDPIC object file\n"));
32666 #endif /* OBJ_ELF */
32674 arm_feature_set flags
;
32675 } cpu_arch_ver_table
;
32677 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
32678 chronologically for architectures, with an exception for ARMv6-M and
32679 ARMv6S-M due to legacy reasons. No new architecture should have a
32680 special case. This allows for build attribute selection results to be
32681 stable when new architectures are added. */
32682 static const cpu_arch_ver_table cpu_arch_ver
[] =
32684 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
32685 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
32686 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
32687 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
32688 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
32689 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
32690 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
32691 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
32692 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
32693 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
32694 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
32695 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
32696 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
32697 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
32698 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
32699 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
32700 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
32701 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
32702 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
32703 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
32704 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
32705 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
32706 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
32707 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
32709 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
32710 always selected build attributes to match those of ARMv6-M
32711 (resp. ARMv6S-M). However, due to these architectures being a strict
32712 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
32713 would be selected when fully respecting chronology of architectures.
32714 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
32715 move them before ARMv7 architectures. */
32716 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
32717 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
32719 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
32720 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
32721 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
32722 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
32723 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
32724 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
32725 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
32726 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
32727 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
32728 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
32729 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
32730 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
32731 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
32732 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
32733 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
32734 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
32735 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_6A
},
32736 {-1, ARM_ARCH_NONE
}
32739 /* Set an attribute if it has not already been set by the user. */
32742 aeabi_set_attribute_int (int tag
, int value
)
32745 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32746 || !attributes_set_explicitly
[tag
])
32747 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
32751 aeabi_set_attribute_string (int tag
, const char *value
)
32754 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
32755 || !attributes_set_explicitly
[tag
])
32756 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
32759 /* Return whether features in the *NEEDED feature set are available via
32760 extensions for the architecture whose feature set is *ARCH_FSET. */
32763 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
32764 const arm_feature_set
*needed
)
32766 int i
, nb_allowed_archs
;
32767 arm_feature_set ext_fset
;
32768 const struct arm_option_extension_value_table
*opt
;
32770 ext_fset
= arm_arch_none
;
32771 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32773 /* Extension does not provide any feature we need. */
32774 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
32778 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
32779 for (i
= 0; i
< nb_allowed_archs
; i
++)
32782 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
32785 /* Extension is available, add it. */
32786 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
32787 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
32791 /* Can we enable all features in *needed? */
32792 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
32795 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
32796 a given architecture feature set *ARCH_EXT_FSET including extension feature
32797 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
32798 - if true, check for an exact match of the architecture modulo extensions;
32799 - otherwise, select build attribute value of the first superset
32800 architecture released so that results remains stable when new architectures
32802 For -march/-mcpu=all the build attribute value of the most featureful
32803 architecture is returned. Tag_CPU_arch_profile result is returned in
32807 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
32808 const arm_feature_set
*ext_fset
,
32809 char *profile
, int exact_match
)
32811 arm_feature_set arch_fset
;
32812 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
32814 /* Select most featureful architecture with all its extensions if building
32815 for -march=all as the feature sets used to set build attributes. */
32816 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
32818 /* Force revisiting of decision for each new architecture. */
32819 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32821 return TAG_CPU_ARCH_V8
;
32824 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
32826 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
32828 arm_feature_set known_arch_fset
;
32830 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
32833 /* Base architecture match user-specified architecture and
32834 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
32835 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
32840 /* Base architecture match user-specified architecture only
32841 (eg. ARMv6-M in the same case as above). Record it in case we
32842 find a match with above condition. */
32843 else if (p_ver_ret
== NULL
32844 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
32850 /* Architecture has all features wanted. */
32851 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
32853 arm_feature_set added_fset
;
32855 /* Compute features added by this architecture over the one
32856 recorded in p_ver_ret. */
32857 if (p_ver_ret
!= NULL
)
32858 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
32860 /* First architecture that match incl. with extensions, or the
32861 only difference in features over the recorded match is
32862 features that were optional and are now mandatory. */
32863 if (p_ver_ret
== NULL
32864 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
32870 else if (p_ver_ret
== NULL
)
32872 arm_feature_set needed_ext_fset
;
32874 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
32876 /* Architecture has all features needed when using some
32877 extensions. Record it and continue searching in case there
32878 exist an architecture providing all needed features without
32879 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
32881 if (have_ext_for_needed_feat_p (&known_arch_fset
,
32888 if (p_ver_ret
== NULL
)
32892 /* Tag_CPU_arch_profile. */
32893 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
32894 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
32895 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
32896 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
32898 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
32900 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
32904 return p_ver_ret
->val
;
32907 /* Set the public EABI object attributes. */
32910 aeabi_set_public_attributes (void)
32912 char profile
= '\0';
32915 int fp16_optional
= 0;
32916 int skip_exact_match
= 0;
32917 arm_feature_set flags
, flags_arch
, flags_ext
;
32919 /* Autodetection mode, choose the architecture based the instructions
32921 if (no_cpu_selected ())
32923 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
32925 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
32926 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
32928 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
32929 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
32931 /* Code run during relaxation relies on selected_cpu being set. */
32932 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
32933 flags_ext
= arm_arch_none
;
32934 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
32935 selected_ext
= flags_ext
;
32936 selected_cpu
= flags
;
32938 /* Otherwise, choose the architecture based on the capabilities of the
32942 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
32943 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
32944 flags_ext
= selected_ext
;
32945 flags
= selected_cpu
;
32947 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
32949 /* Allow the user to override the reported architecture. */
32950 if (!ARM_FEATURE_ZERO (selected_object_arch
))
32952 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
32953 flags_ext
= arm_arch_none
;
32956 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
32958 /* When this function is run again after relaxation has happened there is no
32959 way to determine whether an architecture or CPU was specified by the user:
32960 - selected_cpu is set above for relaxation to work;
32961 - march_cpu_opt is not set if only -mcpu or .cpu is used;
32962 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
32963 Therefore, if not in -march=all case we first try an exact match and fall
32964 back to autodetection. */
32965 if (!skip_exact_match
)
32966 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
32968 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
32970 as_bad (_("no architecture contains all the instructions used\n"));
32972 /* Tag_CPU_name. */
32973 if (selected_cpu_name
[0])
32977 q
= selected_cpu_name
;
32978 if (strncmp (q
, "armv", 4) == 0)
32983 for (i
= 0; q
[i
]; i
++)
32984 q
[i
] = TOUPPER (q
[i
]);
32986 aeabi_set_attribute_string (Tag_CPU_name
, q
);
32989 /* Tag_CPU_arch. */
32990 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
32992 /* Tag_CPU_arch_profile. */
32993 if (profile
!= '\0')
32994 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
32996 /* Tag_DSP_extension. */
32997 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
32998 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
33000 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
33001 /* Tag_ARM_ISA_use. */
33002 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
33003 || ARM_FEATURE_ZERO (flags_arch
))
33004 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
33006 /* Tag_THUMB_ISA_use. */
33007 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
33008 || ARM_FEATURE_ZERO (flags_arch
))
33012 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33013 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
33015 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
33019 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
33022 /* Tag_VFP_arch. */
33023 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
33024 aeabi_set_attribute_int (Tag_VFP_arch
,
33025 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33027 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
33028 aeabi_set_attribute_int (Tag_VFP_arch
,
33029 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
33031 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
33034 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
33036 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
33038 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
33041 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
33042 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
33043 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
33044 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
33045 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
33047 /* Tag_ABI_HardFP_use. */
33048 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
33049 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
33050 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
33052 /* Tag_WMMX_arch. */
33053 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
33054 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
33055 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
33056 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
33058 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
33059 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
33060 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
33061 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
33062 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
33063 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
33065 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
33067 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
33071 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
33076 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
33077 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
33078 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
33079 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
33081 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
33082 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
33083 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
33087 We set Tag_DIV_use to two when integer divide instructions have been used
33088 in ARM state, or when Thumb integer divide instructions have been used,
33089 but we have no architecture profile set, nor have we any ARM instructions.
33091 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
33092 by the base architecture.
33094 For new architectures we will have to check these tests. */
33095 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
33096 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
33097 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
33098 aeabi_set_attribute_int (Tag_DIV_use
, 0);
33099 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
33100 || (profile
== '\0'
33101 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
33102 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
33103 aeabi_set_attribute_int (Tag_DIV_use
, 2);
33105 /* Tag_MP_extension_use. */
33106 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
33107 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
33109 /* Tag Virtualization_use. */
33110 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
33112 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
33115 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
33117 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
33118 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
33121 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
33122 finished and free extension feature bits which will not be used anymore. */
33125 arm_md_post_relax (void)
33127 aeabi_set_public_attributes ();
33128 XDELETE (mcpu_ext_opt
);
33129 mcpu_ext_opt
= NULL
;
33130 XDELETE (march_ext_opt
);
33131 march_ext_opt
= NULL
;
33134 /* Add the default contents for the .ARM.attributes section. */
33139 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
33142 aeabi_set_public_attributes ();
33144 #endif /* OBJ_ELF */
33146 /* Parse a .cpu directive. */
33149 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
33151 const struct arm_cpu_option_table
*opt
;
33155 name
= input_line_pointer
;
33156 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33157 input_line_pointer
++;
33158 saved_char
= *input_line_pointer
;
33159 *input_line_pointer
= 0;
33161 /* Skip the first "all" entry. */
33162 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
33163 if (streq (opt
->name
, name
))
33165 selected_arch
= opt
->value
;
33166 selected_ext
= opt
->ext
;
33167 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33168 if (opt
->canonical_name
)
33169 strcpy (selected_cpu_name
, opt
->canonical_name
);
33173 for (i
= 0; opt
->name
[i
]; i
++)
33174 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
33176 selected_cpu_name
[i
] = 0;
33178 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33180 *input_line_pointer
= saved_char
;
33181 demand_empty_rest_of_line ();
33184 as_bad (_("unknown cpu `%s'"), name
);
33185 *input_line_pointer
= saved_char
;
33186 ignore_rest_of_line ();
33189 /* Parse a .arch directive. */
33192 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
33194 const struct arm_arch_option_table
*opt
;
33198 name
= input_line_pointer
;
33199 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33200 input_line_pointer
++;
33201 saved_char
= *input_line_pointer
;
33202 *input_line_pointer
= 0;
33204 /* Skip the first "all" entry. */
33205 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33206 if (streq (opt
->name
, name
))
33208 selected_arch
= opt
->value
;
33209 selected_ctx_ext_table
= opt
->ext_table
;
33210 selected_ext
= arm_arch_none
;
33211 selected_cpu
= selected_arch
;
33212 strcpy (selected_cpu_name
, opt
->name
);
33213 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33214 *input_line_pointer
= saved_char
;
33215 demand_empty_rest_of_line ();
33219 as_bad (_("unknown architecture `%s'\n"), name
);
33220 *input_line_pointer
= saved_char
;
33221 ignore_rest_of_line ();
33224 /* Parse a .object_arch directive. */
33227 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
33229 const struct arm_arch_option_table
*opt
;
33233 name
= input_line_pointer
;
33234 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33235 input_line_pointer
++;
33236 saved_char
= *input_line_pointer
;
33237 *input_line_pointer
= 0;
33239 /* Skip the first "all" entry. */
33240 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
33241 if (streq (opt
->name
, name
))
33243 selected_object_arch
= opt
->value
;
33244 *input_line_pointer
= saved_char
;
33245 demand_empty_rest_of_line ();
33249 as_bad (_("unknown architecture `%s'\n"), name
);
33250 *input_line_pointer
= saved_char
;
33251 ignore_rest_of_line ();
33254 /* Parse a .arch_extension directive. */
33257 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
33259 const struct arm_option_extension_value_table
*opt
;
33262 int adding_value
= 1;
33264 name
= input_line_pointer
;
33265 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33266 input_line_pointer
++;
33267 saved_char
= *input_line_pointer
;
33268 *input_line_pointer
= 0;
33270 if (strlen (name
) >= 2
33271 && strncmp (name
, "no", 2) == 0)
33277 /* Check the context specific extension table */
33278 if (selected_ctx_ext_table
)
33280 const struct arm_ext_table
* ext_opt
;
33281 for (ext_opt
= selected_ctx_ext_table
; ext_opt
->name
!= NULL
; ext_opt
++)
33283 if (streq (ext_opt
->name
, name
))
33287 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
33288 /* TODO: Option not supported. When we remove the
33289 legacy table this case should error out. */
33291 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33295 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, ext_opt
->clear
);
33297 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33298 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33299 *input_line_pointer
= saved_char
;
33300 demand_empty_rest_of_line ();
33306 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
33307 if (streq (opt
->name
, name
))
33309 int i
, nb_allowed_archs
=
33310 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
33311 for (i
= 0; i
< nb_allowed_archs
; i
++)
33314 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
33316 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
33320 if (i
== nb_allowed_archs
)
33322 as_bad (_("architectural extension `%s' is not allowed for the "
33323 "current base architecture"), name
);
33328 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
33331 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
33333 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
33334 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33335 *input_line_pointer
= saved_char
;
33336 demand_empty_rest_of_line ();
33337 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
33338 on this return so that duplicate extensions (extensions with the
33339 same name as a previous extension in the list) are not considered
33340 for command-line parsing. */
33344 if (opt
->name
== NULL
)
33345 as_bad (_("unknown architecture extension `%s'\n"), name
);
33347 *input_line_pointer
= saved_char
;
33348 ignore_rest_of_line ();
33351 /* Parse a .fpu directive. */
33354 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
33356 const struct arm_option_fpu_value_table
*opt
;
33360 name
= input_line_pointer
;
33361 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
33362 input_line_pointer
++;
33363 saved_char
= *input_line_pointer
;
33364 *input_line_pointer
= 0;
33366 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
33367 if (streq (opt
->name
, name
))
33369 selected_fpu
= opt
->value
;
33370 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, fpu_any
);
33371 #ifndef CPU_DEFAULT
33372 if (no_cpu_selected ())
33373 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
33376 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
33377 *input_line_pointer
= saved_char
;
33378 demand_empty_rest_of_line ();
33382 as_bad (_("unknown floating point format `%s'\n"), name
);
33383 *input_line_pointer
= saved_char
;
33384 ignore_rest_of_line ();
33387 /* Copy symbol information. */
33390 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
33392 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
33396 /* Given a symbolic attribute NAME, return the proper integer value.
33397 Returns -1 if the attribute is not known. */
33400 arm_convert_symbolic_attribute (const char *name
)
33402 static const struct
33407 attribute_table
[] =
33409 /* When you modify this table you should
33410 also modify the list in doc/c-arm.texi. */
33411 #define T(tag) {#tag, tag}
33412 T (Tag_CPU_raw_name
),
33415 T (Tag_CPU_arch_profile
),
33416 T (Tag_ARM_ISA_use
),
33417 T (Tag_THUMB_ISA_use
),
33421 T (Tag_Advanced_SIMD_arch
),
33422 T (Tag_PCS_config
),
33423 T (Tag_ABI_PCS_R9_use
),
33424 T (Tag_ABI_PCS_RW_data
),
33425 T (Tag_ABI_PCS_RO_data
),
33426 T (Tag_ABI_PCS_GOT_use
),
33427 T (Tag_ABI_PCS_wchar_t
),
33428 T (Tag_ABI_FP_rounding
),
33429 T (Tag_ABI_FP_denormal
),
33430 T (Tag_ABI_FP_exceptions
),
33431 T (Tag_ABI_FP_user_exceptions
),
33432 T (Tag_ABI_FP_number_model
),
33433 T (Tag_ABI_align_needed
),
33434 T (Tag_ABI_align8_needed
),
33435 T (Tag_ABI_align_preserved
),
33436 T (Tag_ABI_align8_preserved
),
33437 T (Tag_ABI_enum_size
),
33438 T (Tag_ABI_HardFP_use
),
33439 T (Tag_ABI_VFP_args
),
33440 T (Tag_ABI_WMMX_args
),
33441 T (Tag_ABI_optimization_goals
),
33442 T (Tag_ABI_FP_optimization_goals
),
33443 T (Tag_compatibility
),
33444 T (Tag_CPU_unaligned_access
),
33445 T (Tag_FP_HP_extension
),
33446 T (Tag_VFP_HP_extension
),
33447 T (Tag_ABI_FP_16bit_format
),
33448 T (Tag_MPextension_use
),
33450 T (Tag_nodefaults
),
33451 T (Tag_also_compatible_with
),
33452 T (Tag_conformance
),
33454 T (Tag_Virtualization_use
),
33455 T (Tag_DSP_extension
),
33457 /* We deliberately do not include Tag_MPextension_use_legacy. */
33465 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
33466 if (streq (name
, attribute_table
[i
].name
))
33467 return attribute_table
[i
].tag
;
33472 /* Apply sym value for relocations only in the case that they are for
33473 local symbols in the same segment as the fixup and you have the
33474 respective architectural feature for blx and simple switches. */
33477 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
33480 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
33481 /* PR 17444: If the local symbol is in a different section then a reloc
33482 will always be generated for it, so applying the symbol value now
33483 will result in a double offset being stored in the relocation. */
33484 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
33485 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
33487 switch (fixP
->fx_r_type
)
33489 case BFD_RELOC_ARM_PCREL_BLX
:
33490 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
33491 if (ARM_IS_FUNC (fixP
->fx_addsy
))
33495 case BFD_RELOC_ARM_PCREL_CALL
:
33496 case BFD_RELOC_THUMB_PCREL_BLX
:
33497 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
33508 #endif /* OBJ_ELF */