1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000
3 Free Software Foundation, Inc.
4 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
5 Modified by David Taylor (dtaylor@armltd.co.uk)
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
29 /* Need TARGET_CPU. */
40 /* Types of processor to assemble for. */
41 #define ARM_1 0x00000001
42 #define ARM_2 0x00000002
43 #define ARM_3 0x00000004
45 #define ARM_6 0x00000008
46 #define ARM_7 ARM_6 /* Same core instruction set. */
47 #define ARM_8 ARM_6 /* Same core instruction set. */
48 #define ARM_9 ARM_6 /* Same core instruction set. */
49 #define ARM_CPU_MASK 0x0000000f
51 /* The following bitmasks control CPU extensions (ARM7 onwards): */
52 #define ARM_LONGMUL 0x00000010 /* Allow long multiplies. */
53 #define ARM_HALFWORD 0x00000020 /* Allow half word loads. */
54 #define ARM_THUMB 0x00000040 /* Allow BX instruction. */
55 #define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
57 /* Architectures are the sum of the base and extensions. */
58 #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD)
59 #define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_THUMB)
60 #define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5)
61 #define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_THUMB)
63 /* Some useful combinations: */
64 #define ARM_ANY 0x00ffffff
65 #define ARM_2UP (ARM_ANY - ARM_1)
66 #define ARM_ALL ARM_2UP /* Not arm1 only. */
67 #define ARM_3UP 0x00fffffc
68 #define ARM_6UP 0x00fffff8 /* Includes ARM7. */
70 #define FPU_CORE 0x80000000
71 #define FPU_FPA10 0x40000000
72 #define FPU_FPA11 0x40000000
75 /* Some useful combinations. */
76 #define FPU_ALL 0xff000000 /* Note this is ~ARM_ANY. */
77 #define FPU_MEMMULTI 0x7f000000 /* Not fpu_core. */
81 #define CPU_DEFAULT (ARM_ARCH_V4 | ARM_THUMB)
83 #define CPU_DEFAULT ARM_ALL
88 #define FPU_DEFAULT FPU_ALL
91 #define streq(a, b) (strcmp (a, b) == 0)
92 #define skip_whitespace(str) while (*(str) == ' ') ++(str)
94 static unsigned long cpu_variant
= CPU_DEFAULT
| FPU_DEFAULT
;
95 static int target_oabi
= 0;
97 #if defined OBJ_COFF || defined OBJ_ELF
98 /* Flags stored in private area of BFD structure. */
99 static boolean uses_apcs_26
= false;
100 static boolean support_interwork
= false;
101 static boolean uses_apcs_float
= false;
102 static boolean pic_code
= false;
105 /* This array holds the chars that always start a comment. If the
106 pre-processor is disabled, these aren't very useful. */
107 CONST
char comment_chars
[] = "@";
109 /* This array holds the chars that only start a comment at the beginning of
110 a line. If the line seems to have the form '# 123 filename'
111 .line and .file directives will appear in the pre-processed output. */
112 /* Note that input_file.c hand checks for '#' at the beginning of the
113 first line of the input file. This is because the compiler outputs
114 #NO_APP at the beginning of its output. */
115 /* Also note that comments like this one will always work. */
116 CONST
char line_comment_chars
[] = "#";
118 CONST
char line_separator_chars
[] = ";";
120 /* Chars that can be used to separate mant
121 from exp in floating point numbers. */
122 CONST
char EXP_CHARS
[] = "eE";
124 /* Chars that mean this number is a floating point constant. */
128 CONST
char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
130 /* Prefix characters that indicate the start of an immediate
132 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
135 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
139 /* Size of relocation record. */
140 CONST
int md_reloc_size
= 8;
142 /* 0: assemble for ARM,
143 1: assemble for Thumb,
144 2: assemble for Thumb even though target CPU does not support thumb
146 static int thumb_mode
= 0;
148 typedef struct arm_fix
156 unsigned long instruction
;
161 bfd_reloc_code_real_type type
;
171 CONST
char *template;
175 static CONST
struct asm_shift shift
[] =
191 #define NO_SHIFT_RESTRICT 1
192 #define SHIFT_RESTRICT 0
194 #define NUM_FLOAT_VALS 8
196 CONST
char *fp_const
[] =
198 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
201 /* Number of littlenums required to hold an extended precision number. */
202 #define MAX_LITTLENUMS 6
204 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
214 #define CP_T_X 0x00008000
215 #define CP_T_Y 0x00400000
216 #define CP_T_Pre 0x01000000
217 #define CP_T_UD 0x00800000
218 #define CP_T_WB 0x00200000
220 #define CONDS_BIT (0x00100000)
221 #define LOAD_BIT (0x00100000)
222 #define TRANS_BIT (0x00200000)
226 CONST
char *template;
230 /* This is to save a hash look-up in the common case. */
231 #define COND_ALWAYS 0xe0000000
233 static CONST
struct asm_cond conds
[] =
237 {"cs", 0x20000000}, {"hs", 0x20000000},
238 {"cc", 0x30000000}, {"ul", 0x30000000}, {"lo", 0x30000000},
253 /* Warning: If the top bit of the set_bits is set, then the standard
254 instruction bitmask is ignored, and the new bitmask is taken from
258 /* Basic flag string. */
259 CONST
char *template;
262 unsigned long set_bits
;
265 static CONST
struct asm_flg s_flag
[] =
271 static CONST
struct asm_flg ldr_flags
[] =
275 {"bt", 0x00400000 | TRANS_BIT
},
282 static CONST
struct asm_flg str_flags
[] =
286 {"bt", 0x00400000 | TRANS_BIT
},
291 static CONST
struct asm_flg byte_flag
[] =
297 static CONST
struct asm_flg cmp_flags
[] =
304 static CONST
struct asm_flg ldm_flags
[] =
317 static CONST
struct asm_flg stm_flags
[] =
330 static CONST
struct asm_flg lfm_flags
[] =
337 static CONST
struct asm_flg sfm_flags
[] =
344 static CONST
struct asm_flg round_flags
[] =
352 /* The implementation of the FIX instruction is broken on some assemblers,
353 in that it accepts a precision specifier as well as a rounding specifier,
354 despite the fact that this is meaningless. To be more compatible, we
355 accept it as well, though of course it does not set any bits. */
356 static CONST
struct asm_flg fix_flags
[] =
373 static CONST
struct asm_flg except_flag
[] =
379 static CONST
struct asm_flg cplong_flag
[] =
387 CONST
char *template;
392 /* The bit that distnguishes CPSR and SPSR. */
393 #define SPSR_BIT (1 << 22)
395 /* How many bits to shift the PSR_xxx bits up by. */
398 #define PSR_c (1 << 0)
399 #define PSR_x (1 << 1)
400 #define PSR_s (1 << 2)
401 #define PSR_f (1 << 3)
403 static CONST
struct asm_psr psrs
[] =
405 {"CPSR", true, PSR_c
| PSR_f
},
406 {"CPSR_all", true, PSR_c
| PSR_f
},
407 {"SPSR", false, PSR_c
| PSR_f
},
408 {"SPSR_all", false, PSR_c
| PSR_f
},
409 {"CPSR_flg", true, PSR_f
},
410 {"CPSR_f", true, PSR_f
},
411 {"SPSR_flg", false, PSR_f
},
412 {"SPSR_f", false, PSR_f
},
413 {"CPSR_c", true, PSR_c
},
414 {"CPSR_ctl", true, PSR_c
},
415 {"SPSR_c", false, PSR_c
},
416 {"SPSR_ctl", false, PSR_c
},
417 {"CPSR_x", true, PSR_x
},
418 {"CPSR_s", true, PSR_s
},
419 {"SPSR_x", false, PSR_x
},
420 {"SPSR_s", false, PSR_s
},
421 /* Combinations of flags. */
422 {"CPSR_fs", true, PSR_f
| PSR_s
},
423 {"CPSR_fx", true, PSR_f
| PSR_x
},
424 {"CPSR_fc", true, PSR_f
| PSR_c
},
425 {"CPSR_sf", true, PSR_s
| PSR_f
},
426 {"CPSR_sx", true, PSR_s
| PSR_x
},
427 {"CPSR_sc", true, PSR_s
| PSR_c
},
428 {"CPSR_xf", true, PSR_x
| PSR_f
},
429 {"CPSR_xs", true, PSR_x
| PSR_s
},
430 {"CPSR_xc", true, PSR_x
| PSR_c
},
431 {"CPSR_cf", true, PSR_c
| PSR_f
},
432 {"CPSR_cs", true, PSR_c
| PSR_s
},
433 {"CPSR_cx", true, PSR_c
| PSR_x
},
434 {"CPSR_fsx", true, PSR_f
| PSR_s
| PSR_x
},
435 {"CPSR_fsc", true, PSR_f
| PSR_s
| PSR_c
},
436 {"CPSR_fxs", true, PSR_f
| PSR_x
| PSR_s
},
437 {"CPSR_fxc", true, PSR_f
| PSR_x
| PSR_c
},
438 {"CPSR_fcs", true, PSR_f
| PSR_c
| PSR_s
},
439 {"CPSR_fcx", true, PSR_f
| PSR_c
| PSR_x
},
440 {"CPSR_sfx", true, PSR_s
| PSR_f
| PSR_x
},
441 {"CPSR_sfc", true, PSR_s
| PSR_f
| PSR_c
},
442 {"CPSR_sxf", true, PSR_s
| PSR_x
| PSR_f
},
443 {"CPSR_sxc", true, PSR_s
| PSR_x
| PSR_c
},
444 {"CPSR_scf", true, PSR_s
| PSR_c
| PSR_f
},
445 {"CPSR_scx", true, PSR_s
| PSR_c
| PSR_x
},
446 {"CPSR_xfs", true, PSR_x
| PSR_f
| PSR_s
},
447 {"CPSR_xfc", true, PSR_x
| PSR_f
| PSR_c
},
448 {"CPSR_xsf", true, PSR_x
| PSR_s
| PSR_f
},
449 {"CPSR_xsc", true, PSR_x
| PSR_s
| PSR_c
},
450 {"CPSR_xcf", true, PSR_x
| PSR_c
| PSR_f
},
451 {"CPSR_xcs", true, PSR_x
| PSR_c
| PSR_s
},
452 {"CPSR_cfs", true, PSR_c
| PSR_f
| PSR_s
},
453 {"CPSR_cfx", true, PSR_c
| PSR_f
| PSR_x
},
454 {"CPSR_csf", true, PSR_c
| PSR_s
| PSR_f
},
455 {"CPSR_csx", true, PSR_c
| PSR_s
| PSR_x
},
456 {"CPSR_cxf", true, PSR_c
| PSR_x
| PSR_f
},
457 {"CPSR_cxs", true, PSR_c
| PSR_x
| PSR_s
},
458 {"CPSR_fsxc", true, PSR_f
| PSR_s
| PSR_x
| PSR_c
},
459 {"CPSR_fscx", true, PSR_f
| PSR_s
| PSR_c
| PSR_x
},
460 {"CPSR_fxsc", true, PSR_f
| PSR_x
| PSR_s
| PSR_c
},
461 {"CPSR_fxcs", true, PSR_f
| PSR_x
| PSR_c
| PSR_s
},
462 {"CPSR_fcsx", true, PSR_f
| PSR_c
| PSR_s
| PSR_x
},
463 {"CPSR_fcxs", true, PSR_f
| PSR_c
| PSR_x
| PSR_s
},
464 {"CPSR_sfxc", true, PSR_s
| PSR_f
| PSR_x
| PSR_c
},
465 {"CPSR_sfcx", true, PSR_s
| PSR_f
| PSR_c
| PSR_x
},
466 {"CPSR_sxfc", true, PSR_s
| PSR_x
| PSR_f
| PSR_c
},
467 {"CPSR_sxcf", true, PSR_s
| PSR_x
| PSR_c
| PSR_f
},
468 {"CPSR_scfx", true, PSR_s
| PSR_c
| PSR_f
| PSR_x
},
469 {"CPSR_scxf", true, PSR_s
| PSR_c
| PSR_x
| PSR_f
},
470 {"CPSR_xfsc", true, PSR_x
| PSR_f
| PSR_s
| PSR_c
},
471 {"CPSR_xfcs", true, PSR_x
| PSR_f
| PSR_c
| PSR_s
},
472 {"CPSR_xsfc", true, PSR_x
| PSR_s
| PSR_f
| PSR_c
},
473 {"CPSR_xscf", true, PSR_x
| PSR_s
| PSR_c
| PSR_f
},
474 {"CPSR_xcfs", true, PSR_x
| PSR_c
| PSR_f
| PSR_s
},
475 {"CPSR_xcsf", true, PSR_x
| PSR_c
| PSR_s
| PSR_f
},
476 {"CPSR_cfsx", true, PSR_c
| PSR_f
| PSR_s
| PSR_x
},
477 {"CPSR_cfxs", true, PSR_c
| PSR_f
| PSR_x
| PSR_s
},
478 {"CPSR_csfx", true, PSR_c
| PSR_s
| PSR_f
| PSR_x
},
479 {"CPSR_csxf", true, PSR_c
| PSR_s
| PSR_x
| PSR_f
},
480 {"CPSR_cxfs", true, PSR_c
| PSR_x
| PSR_f
| PSR_s
},
481 {"CPSR_cxsf", true, PSR_c
| PSR_x
| PSR_s
| PSR_f
},
482 {"SPSR_fs", false, PSR_f
| PSR_s
},
483 {"SPSR_fx", false, PSR_f
| PSR_x
},
484 {"SPSR_fc", false, PSR_f
| PSR_c
},
485 {"SPSR_sf", false, PSR_s
| PSR_f
},
486 {"SPSR_sx", false, PSR_s
| PSR_x
},
487 {"SPSR_sc", false, PSR_s
| PSR_c
},
488 {"SPSR_xf", false, PSR_x
| PSR_f
},
489 {"SPSR_xs", false, PSR_x
| PSR_s
},
490 {"SPSR_xc", false, PSR_x
| PSR_c
},
491 {"SPSR_cf", false, PSR_c
| PSR_f
},
492 {"SPSR_cs", false, PSR_c
| PSR_s
},
493 {"SPSR_cx", false, PSR_c
| PSR_x
},
494 {"SPSR_fsx", false, PSR_f
| PSR_s
| PSR_x
},
495 {"SPSR_fsc", false, PSR_f
| PSR_s
| PSR_c
},
496 {"SPSR_fxs", false, PSR_f
| PSR_x
| PSR_s
},
497 {"SPSR_fxc", false, PSR_f
| PSR_x
| PSR_c
},
498 {"SPSR_fcs", false, PSR_f
| PSR_c
| PSR_s
},
499 {"SPSR_fcx", false, PSR_f
| PSR_c
| PSR_x
},
500 {"SPSR_sfx", false, PSR_s
| PSR_f
| PSR_x
},
501 {"SPSR_sfc", false, PSR_s
| PSR_f
| PSR_c
},
502 {"SPSR_sxf", false, PSR_s
| PSR_x
| PSR_f
},
503 {"SPSR_sxc", false, PSR_s
| PSR_x
| PSR_c
},
504 {"SPSR_scf", false, PSR_s
| PSR_c
| PSR_f
},
505 {"SPSR_scx", false, PSR_s
| PSR_c
| PSR_x
},
506 {"SPSR_xfs", false, PSR_x
| PSR_f
| PSR_s
},
507 {"SPSR_xfc", false, PSR_x
| PSR_f
| PSR_c
},
508 {"SPSR_xsf", false, PSR_x
| PSR_s
| PSR_f
},
509 {"SPSR_xsc", false, PSR_x
| PSR_s
| PSR_c
},
510 {"SPSR_xcf", false, PSR_x
| PSR_c
| PSR_f
},
511 {"SPSR_xcs", false, PSR_x
| PSR_c
| PSR_s
},
512 {"SPSR_cfs", false, PSR_c
| PSR_f
| PSR_s
},
513 {"SPSR_cfx", false, PSR_c
| PSR_f
| PSR_x
},
514 {"SPSR_csf", false, PSR_c
| PSR_s
| PSR_f
},
515 {"SPSR_csx", false, PSR_c
| PSR_s
| PSR_x
},
516 {"SPSR_cxf", false, PSR_c
| PSR_x
| PSR_f
},
517 {"SPSR_cxs", false, PSR_c
| PSR_x
| PSR_s
},
518 {"SPSR_fsxc", false, PSR_f
| PSR_s
| PSR_x
| PSR_c
},
519 {"SPSR_fscx", false, PSR_f
| PSR_s
| PSR_c
| PSR_x
},
520 {"SPSR_fxsc", false, PSR_f
| PSR_x
| PSR_s
| PSR_c
},
521 {"SPSR_fxcs", false, PSR_f
| PSR_x
| PSR_c
| PSR_s
},
522 {"SPSR_fcsx", false, PSR_f
| PSR_c
| PSR_s
| PSR_x
},
523 {"SPSR_fcxs", false, PSR_f
| PSR_c
| PSR_x
| PSR_s
},
524 {"SPSR_sfxc", false, PSR_s
| PSR_f
| PSR_x
| PSR_c
},
525 {"SPSR_sfcx", false, PSR_s
| PSR_f
| PSR_c
| PSR_x
},
526 {"SPSR_sxfc", false, PSR_s
| PSR_x
| PSR_f
| PSR_c
},
527 {"SPSR_sxcf", false, PSR_s
| PSR_x
| PSR_c
| PSR_f
},
528 {"SPSR_scfx", false, PSR_s
| PSR_c
| PSR_f
| PSR_x
},
529 {"SPSR_scxf", false, PSR_s
| PSR_c
| PSR_x
| PSR_f
},
530 {"SPSR_xfsc", false, PSR_x
| PSR_f
| PSR_s
| PSR_c
},
531 {"SPSR_xfcs", false, PSR_x
| PSR_f
| PSR_c
| PSR_s
},
532 {"SPSR_xsfc", false, PSR_x
| PSR_s
| PSR_f
| PSR_c
},
533 {"SPSR_xscf", false, PSR_x
| PSR_s
| PSR_c
| PSR_f
},
534 {"SPSR_xcfs", false, PSR_x
| PSR_c
| PSR_f
| PSR_s
},
535 {"SPSR_xcsf", false, PSR_x
| PSR_c
| PSR_s
| PSR_f
},
536 {"SPSR_cfsx", false, PSR_c
| PSR_f
| PSR_s
| PSR_x
},
537 {"SPSR_cfxs", false, PSR_c
| PSR_f
| PSR_x
| PSR_s
},
538 {"SPSR_csfx", false, PSR_c
| PSR_s
| PSR_f
| PSR_x
},
539 {"SPSR_csxf", false, PSR_c
| PSR_s
| PSR_x
| PSR_f
},
540 {"SPSR_cxfs", false, PSR_c
| PSR_x
| PSR_f
| PSR_s
},
541 {"SPSR_cxsf", false, PSR_c
| PSR_x
| PSR_s
| PSR_f
},
542 /* For backwards compatability with older toolchain we also
543 support lower case versions of some of these flags. */
544 {"cpsr", true, PSR_c
| PSR_f
},
545 {"cpsr_all", true, PSR_c
| PSR_f
},
546 {"spsr", false, PSR_c
| PSR_f
},
547 {"spsr_all", false, PSR_c
| PSR_f
},
548 {"cpsr_flg", true, PSR_f
},
549 {"cpsr_f", true, PSR_f
},
550 {"spsr_flg", false, PSR_f
},
551 {"spsr_f", false, PSR_f
},
552 {"cpsr_c", true, PSR_c
},
553 {"cpsr_ctl", true, PSR_c
},
554 {"spsr_c", false, PSR_c
},
555 {"spsr_ctl", false, PSR_c
}
558 /* Functions called by parser. */
559 /* ARM instructions. */
560 static void do_arit
PARAMS ((char *, unsigned long));
561 static void do_cmp
PARAMS ((char *, unsigned long));
562 static void do_mov
PARAMS ((char *, unsigned long));
563 static void do_ldst
PARAMS ((char *, unsigned long));
564 static void do_ldmstm
PARAMS ((char *, unsigned long));
565 static void do_branch
PARAMS ((char *, unsigned long));
566 static void do_swi
PARAMS ((char *, unsigned long));
567 /* Pseudo Op codes. */
568 static void do_adr
PARAMS ((char *, unsigned long));
569 static void do_adrl
PARAMS ((char *, unsigned long));
570 static void do_nop
PARAMS ((char *, unsigned long));
572 static void do_mul
PARAMS ((char *, unsigned long));
573 static void do_mla
PARAMS ((char *, unsigned long));
575 static void do_swap
PARAMS ((char *, unsigned long));
577 static void do_msr
PARAMS ((char *, unsigned long));
578 static void do_mrs
PARAMS ((char *, unsigned long));
580 static void do_mull
PARAMS ((char *, unsigned long));
582 static void do_bx
PARAMS ((char *, unsigned long));
584 /* Coprocessor Instructions. */
585 static void do_cdp
PARAMS ((char *, unsigned long));
586 static void do_lstc
PARAMS ((char *, unsigned long));
587 static void do_co_reg
PARAMS ((char *, unsigned long));
588 static void do_fp_ctrl
PARAMS ((char *, unsigned long));
589 static void do_fp_ldst
PARAMS ((char *, unsigned long));
590 static void do_fp_ldmstm
PARAMS ((char *, unsigned long));
591 static void do_fp_dyadic
PARAMS ((char *, unsigned long));
592 static void do_fp_monadic
PARAMS ((char *, unsigned long));
593 static void do_fp_cmp
PARAMS ((char *, unsigned long));
594 static void do_fp_from_reg
PARAMS ((char *, unsigned long));
595 static void do_fp_to_reg
PARAMS ((char *, unsigned long));
597 static void fix_new_arm
PARAMS ((fragS
*, int, short, expressionS
*, int, int));
598 static int arm_reg_parse
PARAMS ((char **));
599 static CONST
struct asm_psr
* arm_psr_parse
PARAMS ((char **));
600 static void symbol_locate
PARAMS ((symbolS
*, CONST
char *, segT
, valueT
, fragS
*));
601 static int add_to_lit_pool
PARAMS ((void));
602 static unsigned validate_immediate
PARAMS ((unsigned));
603 static unsigned validate_immediate_twopart
PARAMS ((unsigned int, unsigned int *));
604 static int validate_offset_imm
PARAMS ((unsigned int, int));
605 static void opcode_select
PARAMS ((int));
606 static void end_of_line
PARAMS ((char *));
607 static int reg_required_here
PARAMS ((char **, int));
608 static int psr_required_here
PARAMS ((char **));
609 static int co_proc_number
PARAMS ((char **));
610 static int cp_opc_expr
PARAMS ((char **, int, int));
611 static int cp_reg_required_here
PARAMS ((char **, int));
612 static int fp_reg_required_here
PARAMS ((char **, int));
613 static int cp_address_offset
PARAMS ((char **));
614 static int cp_address_required_here
PARAMS ((char **));
615 static int my_get_float_expression
PARAMS ((char **));
616 static int skip_past_comma
PARAMS ((char **));
617 static int walk_no_bignums
PARAMS ((symbolS
*));
618 static int negate_data_op
PARAMS ((unsigned long *, unsigned long));
619 static int data_op2
PARAMS ((char **));
620 static int fp_op2
PARAMS ((char **));
621 static long reg_list
PARAMS ((char **));
622 static void thumb_load_store
PARAMS ((char *, int, int));
623 static int decode_shift
PARAMS ((char **, int));
624 static int ldst_extend
PARAMS ((char **, int));
625 static void thumb_add_sub
PARAMS ((char *, int));
626 static void insert_reg
PARAMS ((int));
627 static void thumb_shift
PARAMS ((char *, int));
628 static void thumb_mov_compare
PARAMS ((char *, int));
629 static void set_constant_flonums
PARAMS ((void));
630 static valueT md_chars_to_number
PARAMS ((char *, int));
631 static void insert_reg_alias
PARAMS ((char *, int));
632 static void output_inst
PARAMS ((void));
634 static bfd_reloc_code_real_type arm_parse_reloc
PARAMS ((void));
637 /* ARM instructions take 4bytes in the object file, Thumb instructions
641 /* LONGEST_INST is the longest basic instruction name without conditions or
642 flags. ARM7M has 4 of length 5. */
644 #define LONGEST_INST 5
648 /* Basic string to match. */
649 CONST
char *template;
651 /* Basic instruction code. */
654 /* Compulsory suffix that must follow conds. If "", then the
655 instruction is not conditional and must have no suffix. */
656 CONST
char *comp_suffix
;
658 /* Bits to toggle if flag 'n' set. */
659 CONST
struct asm_flg
*flags
;
661 /* Which CPU variants this exists for. */
662 unsigned long variants
;
664 /* Function to call to parse args. */
665 void (*parms
) PARAMS ((char *, unsigned long));
668 static CONST
struct asm_opcode insns
[] =
670 /* ARM Instructions. */
671 {"and", 0x00000000, NULL
, s_flag
, ARM_ANY
, do_arit
},
672 {"eor", 0x00200000, NULL
, s_flag
, ARM_ANY
, do_arit
},
673 {"sub", 0x00400000, NULL
, s_flag
, ARM_ANY
, do_arit
},
674 {"rsb", 0x00600000, NULL
, s_flag
, ARM_ANY
, do_arit
},
675 {"add", 0x00800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
676 {"adc", 0x00a00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
677 {"sbc", 0x00c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
678 {"rsc", 0x00e00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
679 {"orr", 0x01800000, NULL
, s_flag
, ARM_ANY
, do_arit
},
680 {"bic", 0x01c00000, NULL
, s_flag
, ARM_ANY
, do_arit
},
681 {"tst", 0x01000000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
682 {"teq", 0x01200000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
683 {"cmp", 0x01400000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
684 {"cmn", 0x01600000, NULL
, cmp_flags
, ARM_ANY
, do_cmp
},
685 {"mov", 0x01a00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
686 {"mvn", 0x01e00000, NULL
, s_flag
, ARM_ANY
, do_mov
},
687 {"str", 0x04000000, NULL
, str_flags
, ARM_ANY
, do_ldst
},
688 {"ldr", 0x04100000, NULL
, ldr_flags
, ARM_ANY
, do_ldst
},
689 {"stm", 0x08000000, NULL
, stm_flags
, ARM_ANY
, do_ldmstm
},
690 {"ldm", 0x08100000, NULL
, ldm_flags
, ARM_ANY
, do_ldmstm
},
691 {"swi", 0x0f000000, NULL
, NULL
, ARM_ANY
, do_swi
},
693 {"bl", 0x0b000000, NULL
, NULL
, ARM_ANY
, do_branch
},
694 {"b", 0x0a000000, NULL
, NULL
, ARM_ANY
, do_branch
},
696 {"bl", 0x0bfffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
697 {"b", 0x0afffffe, NULL
, NULL
, ARM_ANY
, do_branch
},
701 {"adr", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adr
},
702 {"adrl", 0x028f0000, NULL
, NULL
, ARM_ANY
, do_adrl
},
703 {"nop", 0x01a00000, NULL
, NULL
, ARM_ANY
, do_nop
},
705 /* ARM 2 multiplies. */
706 {"mul", 0x00000090, NULL
, s_flag
, ARM_2UP
, do_mul
},
707 {"mla", 0x00200090, NULL
, s_flag
, ARM_2UP
, do_mla
},
709 /* ARM 3 - swp instructions. */
710 {"swp", 0x01000090, NULL
, byte_flag
, ARM_3UP
, do_swap
},
712 /* ARM 6 Coprocessor instructions. */
713 {"mrs", 0x010f0000, NULL
, NULL
, ARM_6UP
, do_mrs
},
714 {"msr", 0x0120f000, NULL
, NULL
, ARM_6UP
, do_msr
},
715 /* ScottB: our code uses 0x0128f000 for msr.
716 NickC: but this is wrong because the bits 16 through 19 are
717 handled by the PSR_xxx defines above. */
719 /* ARM 7M long multiplies - need signed/unsigned flags! */
720 {"smull", 0x00c00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
721 {"umull", 0x00800090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
722 {"smlal", 0x00e00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
723 {"umlal", 0x00a00090, NULL
, s_flag
, ARM_LONGMUL
, do_mull
},
725 /* ARM THUMB interworking. */
726 {"bx", 0x012fff10, NULL
, NULL
, ARM_THUMB
, do_bx
},
728 /* Floating point instructions. */
729 {"wfs", 0x0e200110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
730 {"rfs", 0x0e300110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
731 {"wfc", 0x0e400110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
732 {"rfc", 0x0e500110, NULL
, NULL
, FPU_ALL
, do_fp_ctrl
},
733 {"ldf", 0x0c100100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
734 {"stf", 0x0c000100, "sdep", NULL
, FPU_ALL
, do_fp_ldst
},
735 {"lfm", 0x0c100200, NULL
, lfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
736 {"sfm", 0x0c000200, NULL
, sfm_flags
, FPU_MEMMULTI
, do_fp_ldmstm
},
737 {"mvf", 0x0e008100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
738 {"mnf", 0x0e108100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
739 {"abs", 0x0e208100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
740 {"rnd", 0x0e308100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
741 {"sqt", 0x0e408100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
742 {"log", 0x0e508100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
743 {"lgn", 0x0e608100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
744 {"exp", 0x0e708100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
745 {"sin", 0x0e808100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
746 {"cos", 0x0e908100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
747 {"tan", 0x0ea08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
748 {"asn", 0x0eb08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
749 {"acs", 0x0ec08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
750 {"atn", 0x0ed08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
751 {"urd", 0x0ee08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
752 {"nrm", 0x0ef08100, "sde", round_flags
, FPU_ALL
, do_fp_monadic
},
753 {"adf", 0x0e000100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
754 {"suf", 0x0e200100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
755 {"rsf", 0x0e300100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
756 {"muf", 0x0e100100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
757 {"dvf", 0x0e400100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
758 {"rdf", 0x0e500100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
759 {"pow", 0x0e600100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
760 {"rpw", 0x0e700100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
761 {"rmf", 0x0e800100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
762 {"fml", 0x0e900100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
763 {"fdv", 0x0ea00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
764 {"frd", 0x0eb00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
765 {"pol", 0x0ec00100, "sde", round_flags
, FPU_ALL
, do_fp_dyadic
},
766 {"cmf", 0x0e90f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
767 {"cnf", 0x0eb0f110, NULL
, except_flag
, FPU_ALL
, do_fp_cmp
},
768 /* The FPA10 data sheet suggests that the 'E' of cmfe/cnfe should not
769 be an optional suffix, but part of the instruction. To be compatible,
771 {"cmfe", 0x0ed0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
772 {"cnfe", 0x0ef0f110, NULL
, NULL
, FPU_ALL
, do_fp_cmp
},
773 {"flt", 0x0e000110, "sde", round_flags
, FPU_ALL
, do_fp_from_reg
},
774 {"fix", 0x0e100110, NULL
, fix_flags
, FPU_ALL
, do_fp_to_reg
},
776 /* Generic copressor instructions. */
777 {"cdp", 0x0e000000, NULL
, NULL
, ARM_2UP
, do_cdp
},
778 {"ldc", 0x0c100000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
779 {"stc", 0x0c000000, NULL
, cplong_flag
, ARM_2UP
, do_lstc
},
780 {"mcr", 0x0e000010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
781 {"mrc", 0x0e100010, NULL
, NULL
, ARM_2UP
, do_co_reg
},
784 /* Defines for various bits that we will want to toggle. */
785 #define INST_IMMEDIATE 0x02000000
786 #define OFFSET_REG 0x02000000
787 #define HWOFFSET_IMM 0x00400000
788 #define SHIFT_BY_REG 0x00000010
789 #define PRE_INDEX 0x01000000
790 #define INDEX_UP 0x00800000
791 #define WRITE_BACK 0x00200000
792 #define LDM_TYPE_2_OR_3 0x00400000
794 #define LITERAL_MASK 0xf000f000
795 #define COND_MASK 0xf0000000
796 #define OPCODE_MASK 0xfe1fffff
797 #define DATA_OP_SHIFT 21
799 /* Codes to distinguish the arithmetic instructions. */
810 #define OPCODE_CMP 10
811 #define OPCODE_CMN 11
812 #define OPCODE_ORR 12
813 #define OPCODE_MOV 13
814 #define OPCODE_BIC 14
815 #define OPCODE_MVN 15
817 static void do_t_nop
PARAMS ((char *));
818 static void do_t_arit
PARAMS ((char *));
819 static void do_t_add
PARAMS ((char *));
820 static void do_t_asr
PARAMS ((char *));
821 static void do_t_branch9
PARAMS ((char *));
822 static void do_t_branch12
PARAMS ((char *));
823 static void do_t_branch23
PARAMS ((char *));
824 static void do_t_bx
PARAMS ((char *));
825 static void do_t_compare
PARAMS ((char *));
826 static void do_t_ldmstm
PARAMS ((char *));
827 static void do_t_ldr
PARAMS ((char *));
828 static void do_t_ldrb
PARAMS ((char *));
829 static void do_t_ldrh
PARAMS ((char *));
830 static void do_t_lds
PARAMS ((char *));
831 static void do_t_lsl
PARAMS ((char *));
832 static void do_t_lsr
PARAMS ((char *));
833 static void do_t_mov
PARAMS ((char *));
834 static void do_t_push_pop
PARAMS ((char *));
835 static void do_t_str
PARAMS ((char *));
836 static void do_t_strb
PARAMS ((char *));
837 static void do_t_strh
PARAMS ((char *));
838 static void do_t_sub
PARAMS ((char *));
839 static void do_t_swi
PARAMS ((char *));
840 static void do_t_adr
PARAMS ((char *));
842 #define T_OPCODE_MUL 0x4340
843 #define T_OPCODE_TST 0x4200
844 #define T_OPCODE_CMN 0x42c0
845 #define T_OPCODE_NEG 0x4240
846 #define T_OPCODE_MVN 0x43c0
848 #define T_OPCODE_ADD_R3 0x1800
849 #define T_OPCODE_SUB_R3 0x1a00
850 #define T_OPCODE_ADD_HI 0x4400
851 #define T_OPCODE_ADD_ST 0xb000
852 #define T_OPCODE_SUB_ST 0xb080
853 #define T_OPCODE_ADD_SP 0xa800
854 #define T_OPCODE_ADD_PC 0xa000
855 #define T_OPCODE_ADD_I8 0x3000
856 #define T_OPCODE_SUB_I8 0x3800
857 #define T_OPCODE_ADD_I3 0x1c00
858 #define T_OPCODE_SUB_I3 0x1e00
860 #define T_OPCODE_ASR_R 0x4100
861 #define T_OPCODE_LSL_R 0x4080
862 #define T_OPCODE_LSR_R 0x40c0
863 #define T_OPCODE_ASR_I 0x1000
864 #define T_OPCODE_LSL_I 0x0000
865 #define T_OPCODE_LSR_I 0x0800
867 #define T_OPCODE_MOV_I8 0x2000
868 #define T_OPCODE_CMP_I8 0x2800
869 #define T_OPCODE_CMP_LR 0x4280
870 #define T_OPCODE_MOV_HR 0x4600
871 #define T_OPCODE_CMP_HR 0x4500
873 #define T_OPCODE_LDR_PC 0x4800
874 #define T_OPCODE_LDR_SP 0x9800
875 #define T_OPCODE_STR_SP 0x9000
876 #define T_OPCODE_LDR_IW 0x6800
877 #define T_OPCODE_STR_IW 0x6000
878 #define T_OPCODE_LDR_IH 0x8800
879 #define T_OPCODE_STR_IH 0x8000
880 #define T_OPCODE_LDR_IB 0x7800
881 #define T_OPCODE_STR_IB 0x7000
882 #define T_OPCODE_LDR_RW 0x5800
883 #define T_OPCODE_STR_RW 0x5000
884 #define T_OPCODE_LDR_RH 0x5a00
885 #define T_OPCODE_STR_RH 0x5200
886 #define T_OPCODE_LDR_RB 0x5c00
887 #define T_OPCODE_STR_RB 0x5400
889 #define T_OPCODE_PUSH 0xb400
890 #define T_OPCODE_POP 0xbc00
892 #define T_OPCODE_BRANCH 0xe7fe
894 static int thumb_reg
PARAMS ((char ** str
, int hi_lo
));
896 #define THUMB_SIZE 2 /* Size of thumb instruction. */
897 #define THUMB_REG_LO 0x1
898 #define THUMB_REG_HI 0x2
899 #define THUMB_REG_ANY 0x3
901 #define THUMB_H1 0x0080
902 #define THUMB_H2 0x0040
909 #define THUMB_COMPARE 1
912 #define THUMB_STORE 1
914 #define THUMB_PP_PC_LR 0x0100
916 /* These three are used for immediate shifts, do not alter. */
918 #define THUMB_HALFWORD 1
923 /* Basic string to match. */
924 CONST
char *template;
926 /* Basic instruction code. */
931 /* Which CPU variants this exists for. */
932 unsigned long variants
;
934 /* Function to call to parse args. */
935 void (*parms
) PARAMS ((char *));
938 static CONST
struct thumb_opcode tinsns
[] =
940 {"adc", 0x4140, 2, ARM_THUMB
, do_t_arit
},
941 {"add", 0x0000, 2, ARM_THUMB
, do_t_add
},
942 {"and", 0x4000, 2, ARM_THUMB
, do_t_arit
},
943 {"asr", 0x0000, 2, ARM_THUMB
, do_t_asr
},
944 {"b", T_OPCODE_BRANCH
, 2, ARM_THUMB
, do_t_branch12
},
945 {"beq", 0xd0fe, 2, ARM_THUMB
, do_t_branch9
},
946 {"bne", 0xd1fe, 2, ARM_THUMB
, do_t_branch9
},
947 {"bcs", 0xd2fe, 2, ARM_THUMB
, do_t_branch9
},
948 {"bhs", 0xd2fe, 2, ARM_THUMB
, do_t_branch9
},
949 {"bcc", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
950 {"bul", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
951 {"blo", 0xd3fe, 2, ARM_THUMB
, do_t_branch9
},
952 {"bmi", 0xd4fe, 2, ARM_THUMB
, do_t_branch9
},
953 {"bpl", 0xd5fe, 2, ARM_THUMB
, do_t_branch9
},
954 {"bvs", 0xd6fe, 2, ARM_THUMB
, do_t_branch9
},
955 {"bvc", 0xd7fe, 2, ARM_THUMB
, do_t_branch9
},
956 {"bhi", 0xd8fe, 2, ARM_THUMB
, do_t_branch9
},
957 {"bls", 0xd9fe, 2, ARM_THUMB
, do_t_branch9
},
958 {"bge", 0xdafe, 2, ARM_THUMB
, do_t_branch9
},
959 {"blt", 0xdbfe, 2, ARM_THUMB
, do_t_branch9
},
960 {"bgt", 0xdcfe, 2, ARM_THUMB
, do_t_branch9
},
961 {"ble", 0xddfe, 2, ARM_THUMB
, do_t_branch9
},
962 {"bal", 0xdefe, 2, ARM_THUMB
, do_t_branch9
},
963 {"bic", 0x4380, 2, ARM_THUMB
, do_t_arit
},
964 {"bl", 0xf7fffffe, 4, ARM_THUMB
, do_t_branch23
},
965 {"bx", 0x4700, 2, ARM_THUMB
, do_t_bx
},
966 {"cmn", T_OPCODE_CMN
, 2, ARM_THUMB
, do_t_arit
},
967 {"cmp", 0x0000, 2, ARM_THUMB
, do_t_compare
},
968 {"eor", 0x4040, 2, ARM_THUMB
, do_t_arit
},
969 {"ldmia", 0xc800, 2, ARM_THUMB
, do_t_ldmstm
},
970 {"ldr", 0x0000, 2, ARM_THUMB
, do_t_ldr
},
971 {"ldrb", 0x0000, 2, ARM_THUMB
, do_t_ldrb
},
972 {"ldrh", 0x0000, 2, ARM_THUMB
, do_t_ldrh
},
973 {"ldrsb", 0x5600, 2, ARM_THUMB
, do_t_lds
},
974 {"ldrsh", 0x5e00, 2, ARM_THUMB
, do_t_lds
},
975 {"ldsb", 0x5600, 2, ARM_THUMB
, do_t_lds
},
976 {"ldsh", 0x5e00, 2, ARM_THUMB
, do_t_lds
},
977 {"lsl", 0x0000, 2, ARM_THUMB
, do_t_lsl
},
978 {"lsr", 0x0000, 2, ARM_THUMB
, do_t_lsr
},
979 {"mov", 0x0000, 2, ARM_THUMB
, do_t_mov
},
980 {"mul", T_OPCODE_MUL
, 2, ARM_THUMB
, do_t_arit
},
981 {"mvn", T_OPCODE_MVN
, 2, ARM_THUMB
, do_t_arit
},
982 {"neg", T_OPCODE_NEG
, 2, ARM_THUMB
, do_t_arit
},
983 {"orr", 0x4300, 2, ARM_THUMB
, do_t_arit
},
984 {"pop", 0xbc00, 2, ARM_THUMB
, do_t_push_pop
},
985 {"push", 0xb400, 2, ARM_THUMB
, do_t_push_pop
},
986 {"ror", 0x41c0, 2, ARM_THUMB
, do_t_arit
},
987 {"sbc", 0x4180, 2, ARM_THUMB
, do_t_arit
},
988 {"stmia", 0xc000, 2, ARM_THUMB
, do_t_ldmstm
},
989 {"str", 0x0000, 2, ARM_THUMB
, do_t_str
},
990 {"strb", 0x0000, 2, ARM_THUMB
, do_t_strb
},
991 {"strh", 0x0000, 2, ARM_THUMB
, do_t_strh
},
992 {"swi", 0xdf00, 2, ARM_THUMB
, do_t_swi
},
993 {"sub", 0x0000, 2, ARM_THUMB
, do_t_sub
},
994 {"tst", T_OPCODE_TST
, 2, ARM_THUMB
, do_t_arit
},
996 {"adr", 0x0000, 2, ARM_THUMB
, do_t_adr
},
997 {"nop", 0x46C0, 2, ARM_THUMB
, do_t_nop
}, /* mov r8,r8 */
1006 #define int_register(reg) ((reg) >= 0 && (reg) <= 15)
1007 #define cp_register(reg) ((reg) >= 32 && (reg) <= 47)
1008 #define fp_register(reg) ((reg) >= 16 && (reg) <= 23)
1014 /* These are the standard names. Users can add aliases with .req. */
1015 static CONST
struct reg_entry reg_table
[] =
1017 /* Processor Register Numbers. */
1018 {"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3},
1019 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7},
1020 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11},
1021 {"r12", 12}, {"r13", REG_SP
},{"r14", REG_LR
},{"r15", REG_PC
},
1022 /* APCS conventions. */
1023 {"a1", 0}, {"a2", 1}, {"a3", 2}, {"a4", 3},
1024 {"v1", 4}, {"v2", 5}, {"v3", 6}, {"v4", 7}, {"v5", 8},
1025 {"v6", 9}, {"sb", 9}, {"v7", 10}, {"sl", 10},
1026 {"fp", 11}, {"ip", 12}, {"sp", REG_SP
},{"lr", REG_LR
},{"pc", REG_PC
},
1027 /* ATPCS additions to APCS conventions. */
1028 {"wr", 7}, {"v8", 11},
1030 {"f0", 16}, {"f1", 17}, {"f2", 18}, {"f3", 19},
1031 {"f4", 20}, {"f5", 21}, {"f6", 22}, {"f7", 23},
1032 {"c0", 32}, {"c1", 33}, {"c2", 34}, {"c3", 35},
1033 {"c4", 36}, {"c5", 37}, {"c6", 38}, {"c7", 39},
1034 {"c8", 40}, {"c9", 41}, {"c10", 42}, {"c11", 43},
1035 {"c12", 44}, {"c13", 45}, {"c14", 46}, {"c15", 47},
1036 {"cr0", 32}, {"cr1", 33}, {"cr2", 34}, {"cr3", 35},
1037 {"cr4", 36}, {"cr5", 37}, {"cr6", 38}, {"cr7", 39},
1038 {"cr8", 40}, {"cr9", 41}, {"cr10", 42}, {"cr11", 43},
1039 {"cr12", 44}, {"cr13", 45}, {"cr14", 46}, {"cr15", 47},
1040 /* ATPCS additions to float register names. */
1041 {"s0",16}, {"s1",17}, {"s2",18}, {"s3",19},
1042 {"s4",20}, {"s5",21}, {"s6",22}, {"s7",23},
1043 {"d0",16}, {"d1",17}, {"d2",18}, {"d3",19},
1044 {"d4",20}, {"d5",21}, {"d6",22}, {"d7",23},
1045 /* FIXME: At some point we need to add VFP register names. */
1046 /* Array terminator. */
1050 #define BAD_ARGS _("Bad arguments to instruction")
1051 #define BAD_PC _("r15 not allowed here")
1052 #define BAD_FLAGS _("Instruction should not have flags")
1053 #define BAD_COND _("Instruction is not conditional")
1055 static struct hash_control
*arm_ops_hsh
= NULL
;
1056 static struct hash_control
*arm_tops_hsh
= NULL
;
1057 static struct hash_control
*arm_cond_hsh
= NULL
;
1058 static struct hash_control
*arm_shift_hsh
= NULL
;
1059 static struct hash_control
*arm_reg_hsh
= NULL
;
1060 static struct hash_control
*arm_psr_hsh
= NULL
;
1062 /* This table describes all the machine specific pseudo-ops the assembler
1063 has to support. The fields are:
1064 pseudo-op name without dot
1065 function to call to execute this pseudo-op
1066 Integer arg to pass to the function. */
1068 static void s_req
PARAMS ((int));
1069 static void s_align
PARAMS ((int));
1070 static void s_bss
PARAMS ((int));
1071 static void s_even
PARAMS ((int));
1072 static void s_ltorg
PARAMS ((int));
1073 static void s_arm
PARAMS ((int));
1074 static void s_thumb
PARAMS ((int));
1075 static void s_code
PARAMS ((int));
1076 static void s_force_thumb
PARAMS ((int));
1077 static void s_thumb_func
PARAMS ((int));
1078 static void s_thumb_set
PARAMS ((int));
1079 static void arm_s_text
PARAMS ((int));
1080 static void arm_s_data
PARAMS ((int));
1082 static void arm_s_section
PARAMS ((int));
1083 static void s_arm_elf_cons
PARAMS ((int));
1086 static int my_get_expression
PARAMS ((expressionS
*, char **));
1088 CONST pseudo_typeS md_pseudo_table
[] =
1090 { "req", s_req
, 0 }, /* Never called becasue '.req' does not start line. */
1091 { "bss", s_bss
, 0 },
1092 { "align", s_align
, 0 },
1093 { "arm", s_arm
, 0 },
1094 { "thumb", s_thumb
, 0 },
1095 { "code", s_code
, 0 },
1096 { "force_thumb", s_force_thumb
, 0 },
1097 { "thumb_func", s_thumb_func
, 0 },
1098 { "thumb_set", s_thumb_set
, 0 },
1099 { "even", s_even
, 0 },
1100 { "ltorg", s_ltorg
, 0 },
1101 { "pool", s_ltorg
, 0 },
1102 /* Allow for the effect of section changes. */
1103 { "text", arm_s_text
, 0 },
1104 { "data", arm_s_data
, 0 },
1106 { "section", arm_s_section
, 0 },
1107 { "section.s", arm_s_section
, 0 },
1108 { "sect", arm_s_section
, 0 },
1109 { "sect.s", arm_s_section
, 0 },
1110 { "word", s_arm_elf_cons
, 4 },
1111 { "long", s_arm_elf_cons
, 4 },
1115 { "extend", float_cons
, 'x' },
1116 { "ldouble", float_cons
, 'x' },
1117 { "packed", float_cons
, 'p' },
1121 /* Stuff needed to resolve the label ambiguity
1131 symbolS
*last_label_seen
;
1132 static int label_is_thumb_function_name
= false;
1134 /* Literal stuff. */
1136 #define MAX_LITERAL_POOL_SIZE 1024
1138 typedef struct literalS
1140 struct expressionS exp
;
1141 struct arm_it
*inst
;
1144 literalT literals
[MAX_LITERAL_POOL_SIZE
];
1146 /* Next free entry in the pool. */
1147 int next_literal_pool_place
= 0;
1149 /* Next literal pool number. */
1150 int lit_pool_num
= 1;
1152 symbolS
*current_poolP
= NULL
;
1159 if (current_poolP
== NULL
)
1160 current_poolP
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
1161 (valueT
) 0, &zero_address_frag
);
1163 /* Check if this literal value is already in the pool: */
1164 while (lit_count
< next_literal_pool_place
)
1166 if (literals
[lit_count
].exp
.X_op
== inst
.reloc
.exp
.X_op
1167 && inst
.reloc
.exp
.X_op
== O_constant
1168 && (literals
[lit_count
].exp
.X_add_number
1169 == inst
.reloc
.exp
.X_add_number
)
1170 && literals
[lit_count
].exp
.X_unsigned
== inst
.reloc
.exp
.X_unsigned
)
1175 if (lit_count
== next_literal_pool_place
) /* New entry. */
1177 if (next_literal_pool_place
> MAX_LITERAL_POOL_SIZE
)
1179 inst
.error
= _("Literal Pool Overflow");
1183 literals
[next_literal_pool_place
].exp
= inst
.reloc
.exp
;
1184 lit_count
= next_literal_pool_place
++;
1187 inst
.reloc
.exp
.X_op
= O_symbol
;
1188 inst
.reloc
.exp
.X_add_number
= (lit_count
) * 4 - 8;
1189 inst
.reloc
.exp
.X_add_symbol
= current_poolP
;
1194 /* Can't use symbol_new here, so have to create a symbol and then at
1195 a later date assign it a value. Thats what these functions do. */
1198 symbol_locate (symbolP
, name
, segment
, valu
, frag
)
1201 /* It is copied, the caller can modify. */
1204 /* Segment identifier (SEG_<something>). */
1210 /* Associated fragment. */
1213 unsigned int name_length
;
1214 char *preserved_copy_of_name
;
1217 name_length
= strlen (name
) + 1;
1218 obstack_grow (¬es
, name
, name_length
);
1219 preserved_copy_of_name
= obstack_finish (¬es
);
1220 #ifdef STRIP_UNDERSCORE
1221 if (preserved_copy_of_name
[0] == '_')
1222 preserved_copy_of_name
++;
1225 #ifdef tc_canonicalize_symbol_name
1226 preserved_copy_of_name
=
1227 tc_canonicalize_symbol_name (preserved_copy_of_name
);
1230 S_SET_NAME (symbolP
, preserved_copy_of_name
);
1232 S_SET_SEGMENT (symbolP
, segment
);
1233 S_SET_VALUE (symbolP
, valu
);
1234 symbol_clear_list_pointers(symbolP
);
1236 symbol_set_frag (symbolP
, frag
);
1238 /* Link to end of symbol chain. */
1240 extern int symbol_table_frozen
;
1241 if (symbol_table_frozen
)
1245 symbol_append (symbolP
, symbol_lastP
, &symbol_rootP
, &symbol_lastP
);
1247 obj_symbol_new_hook (symbolP
);
1249 #ifdef tc_symbol_new_hook
1250 tc_symbol_new_hook (symbolP
);
1254 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
1255 #endif /* DEBUG_SYMS */
1258 /* Check that an immediate is valid.
1259 If so, convert it to the right format. */
1262 validate_immediate (val
)
1268 #define rotate_left(v, n) (v << n | v >> (32 - n))
1270 for (i
= 0; i
< 32; i
+= 2)
1271 if ((a
= rotate_left (val
, i
)) <= 0xff)
1272 /* 12-bit pack: [shift-cnt,const]. */
1273 return a
| (i
<< 7);
1278 /* Check to see if an immediate can be computed as two seperate immediate
1279 values, added together. We already know that this value cannot be
1280 computed by just one ARM instruction. */
1283 validate_immediate_twopart (val
, highpart
)
1285 unsigned int *highpart
;
1290 for (i
= 0; i
< 32; i
+= 2)
1291 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
1297 *highpart
= (a
>> 8) | ((i
+ 24) << 7);
1299 else if (a
& 0xff0000)
1303 *highpart
= (a
>> 16) | ((i
+ 16) << 7);
1307 assert (a
& 0xff000000);
1308 *highpart
= (a
>> 24) | ((i
+ 8) << 7);
1311 return (a
& 0xff) | (i
<< 7);
1318 validate_offset_imm (val
, hwse
)
1322 if ((hwse
&& val
> 255) || val
> 4095)
1329 int a ATTRIBUTE_UNUSED
;
1331 as_bad (_("Invalid syntax for .req directive."));
1336 int ignore ATTRIBUTE_UNUSED
;
1338 /* We don't support putting frags in the BSS segment, we fake it by
1339 marking in_bss, then looking at s_skip for clues. */
1340 subseg_set (bss_section
, 0);
1341 demand_empty_rest_of_line ();
1346 int ignore ATTRIBUTE_UNUSED
;
1348 /* Never make frag if expect extra pass. */
1350 frag_align (1, 0, 0);
1352 record_alignment (now_seg
, 1);
1354 demand_empty_rest_of_line ();
1359 int ignored ATTRIBUTE_UNUSED
;
1364 if (current_poolP
== NULL
)
1367 /* Align pool as you have word accesses.
1368 Only make a frag if we have to. */
1370 frag_align (2, 0, 0);
1372 record_alignment (now_seg
, 2);
1374 sprintf (sym_name
, "$$lit_\002%x", lit_pool_num
++);
1376 symbol_locate (current_poolP
, sym_name
, now_seg
,
1377 (valueT
) frag_now_fix (), frag_now
);
1378 symbol_table_insert (current_poolP
);
1380 ARM_SET_THUMB (current_poolP
, thumb_mode
);
1382 #if defined OBJ_COFF || defined OBJ_ELF
1383 ARM_SET_INTERWORK (current_poolP
, support_interwork
);
1386 while (lit_count
< next_literal_pool_place
)
1387 /* First output the expression in the instruction to the pool. */
1388 emit_expr (&(literals
[lit_count
++].exp
), 4); /* .word */
1390 next_literal_pool_place
= 0;
1391 current_poolP
= NULL
;
1394 /* Same as s_align_ptwo but align 0 => align 2. */
1398 int unused ATTRIBUTE_UNUSED
;
1401 register long temp_fill
;
1402 long max_alignment
= 15;
1404 temp
= get_absolute_expression ();
1405 if (temp
> max_alignment
)
1406 as_bad (_("Alignment too large: %d. assumed."), temp
= max_alignment
);
1409 as_bad (_("Alignment negative. 0 assumed."));
1413 if (*input_line_pointer
== ',')
1415 input_line_pointer
++;
1416 temp_fill
= get_absolute_expression ();
1424 /* Only make a frag if we HAVE to. */
1425 if (temp
&& !need_pass_2
)
1426 frag_align (temp
, (int) temp_fill
, 0);
1427 demand_empty_rest_of_line ();
1429 record_alignment (now_seg
, temp
);
1433 s_force_thumb (ignore
)
1434 int ignore ATTRIBUTE_UNUSED
;
1436 /* If we are not already in thumb mode go into it, EVEN if
1437 the target processor does not support thumb instructions.
1438 This is used by gcc/config/arm/lib1funcs.asm for example
1439 to compile interworking support functions even if the
1440 target processor should not support interworking. */
1446 record_alignment (now_seg
, 1);
1449 demand_empty_rest_of_line ();
1453 s_thumb_func (ignore
)
1454 int ignore ATTRIBUTE_UNUSED
;
1459 /* The following label is the name/address of the start of a Thumb function.
1460 We need to know this for the interworking support. */
1461 label_is_thumb_function_name
= true;
1463 demand_empty_rest_of_line ();
1466 /* Perform a .set directive, but also mark the alias as
1467 being a thumb function. */
1473 /* XXX the following is a duplicate of the code for s_set() in read.c
1474 We cannot just call that code as we need to get at the symbol that
1476 register char *name
;
1477 register char delim
;
1478 register char *end_name
;
1479 register symbolS
*symbolP
;
1481 /* Especial apologies for the random logic: This just grew, and
1482 could be parsed much more simply! Dean in haste. */
1483 name
= input_line_pointer
;
1484 delim
= get_symbol_end ();
1485 end_name
= input_line_pointer
;
1490 if (*input_line_pointer
!= ',')
1493 as_bad (_("Expected comma after name \"%s\""), name
);
1495 ignore_rest_of_line ();
1499 input_line_pointer
++;
1502 if (name
[0] == '.' && name
[1] == '\0')
1504 /* XXX - this should not happen to .thumb_set. */
1508 if ((symbolP
= symbol_find (name
)) == NULL
1509 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
1512 /* When doing symbol listings, play games with dummy fragments living
1513 outside the normal fragment chain to record the file and line info
1515 if (listing
& LISTING_SYMBOLS
)
1517 extern struct list_info_struct
*listing_tail
;
1518 fragS
*dummy_frag
= (fragS
*) xmalloc (sizeof (fragS
));
1519 memset (dummy_frag
, 0, sizeof (fragS
));
1520 dummy_frag
->fr_type
= rs_fill
;
1521 dummy_frag
->line
= listing_tail
;
1522 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
1523 dummy_frag
->fr_symbol
= symbolP
;
1527 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
1530 /* "set" symbols are local unless otherwise specified. */
1531 SF_SET_LOCAL (symbolP
);
1532 #endif /* OBJ_COFF */
1533 } /* Make a new symbol. */
1535 symbol_table_insert (symbolP
);
1540 && S_IS_DEFINED (symbolP
)
1541 && S_GET_SEGMENT (symbolP
) != reg_section
)
1542 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
1544 pseudo_set (symbolP
);
1546 demand_empty_rest_of_line ();
1548 /* XXX Now we come to the Thumb specific bit of code. */
1550 THUMB_SET_FUNC (symbolP
, 1);
1551 ARM_SET_THUMB (symbolP
, 1);
1552 #if defined OBJ_ELF || defined OBJ_COFF
1553 ARM_SET_INTERWORK (symbolP
, support_interwork
);
1557 /* If we change section we must dump the literal pool first. */
1563 if (now_seg
!= text_section
)
1567 obj_elf_text (ignore
);
1577 if (flag_readonly_data_in_text
)
1579 if (now_seg
!= text_section
)
1582 else if (now_seg
!= data_section
)
1586 obj_elf_data (ignore
);
1594 arm_s_section (ignore
)
1599 obj_elf_section (ignore
);
1604 opcode_select (width
)
1612 if (! (cpu_variant
& ARM_THUMB
))
1613 as_bad (_("selected processor does not support THUMB opcodes"));
1615 /* No need to force the alignment, since we will have been
1616 coming from ARM mode, which is word-aligned. */
1617 record_alignment (now_seg
, 1);
1624 if ((cpu_variant
& ARM_ANY
) == ARM_THUMB
)
1625 as_bad (_("selected processor does not support ARM opcodes"));
1628 frag_align (2, 0, 0);
1629 record_alignment (now_seg
, 1);
1634 as_bad (_("invalid instruction size selected (%d)"), width
);
1640 int ignore ATTRIBUTE_UNUSED
;
1643 demand_empty_rest_of_line ();
1648 int ignore ATTRIBUTE_UNUSED
;
1651 demand_empty_rest_of_line ();
1656 int unused ATTRIBUTE_UNUSED
;
1660 temp
= get_absolute_expression ();
1665 opcode_select (temp
);
1669 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
1677 skip_whitespace (str
);
1680 inst
.error
= _("Garbage following instruction");
1684 skip_past_comma (str
)
1690 while ((c
= *p
) == ' ' || c
== ',')
1693 if (c
== ',' && comma
++)
1701 return comma
? SUCCESS
: FAIL
;
1704 /* A standard register must be given at this point.
1705 SHIFT is the place to put it in inst.instruction.
1706 Restore input start point on err.
1707 Return the reg#, or FAIL. */
1710 reg_required_here (str
, shift
)
1714 static char buff
[128]; /* XXX */
1718 if ((reg
= arm_reg_parse (str
)) != FAIL
&& int_register (reg
))
1721 inst
.instruction
|= reg
<< shift
;
1725 /* Restore the start point, we may have got a reg of the wrong class. */
1728 /* In the few cases where we might be able to accept something else
1729 this error can be overridden. */
1730 sprintf (buff
, _("Register expected, not '%.100s'"), start
);
1736 static CONST
struct asm_psr
*
1738 register char **ccp
;
1743 CONST
struct asm_psr
*psr
;
1747 /* Skip to the end of the next word in the input stream. */
1752 while (isalpha (c
) || c
== '_');
1754 /* Terminate the word. */
1757 /* Now locate the word in the psr hash table. */
1758 psr
= (CONST
struct asm_psr
*) hash_find (arm_psr_hsh
, start
);
1760 /* Restore the input stream. */
1763 /* If we found a valid match, advance the
1764 stream pointer past the end of the word. */
1770 /* Parse the input looking for a PSR flag. */
1773 psr_required_here (str
)
1777 CONST
struct asm_psr
*psr
;
1779 psr
= arm_psr_parse (str
);
1783 /* If this is the SPSR that is being modified, set the R bit. */
1785 inst
.instruction
|= SPSR_BIT
;
1787 /* Set the psr flags in the MSR instruction. */
1788 inst
.instruction
|= psr
->field
<< PSR_SHIFT
;
1793 /* In the few cases where we might be able to accept
1794 something else this error can be overridden. */
1795 inst
.error
= _("flag for {c}psr instruction expected");
1797 /* Restore the start point. */
1803 co_proc_number (str
)
1806 int processor
, pchar
;
1808 skip_whitespace (*str
);
1810 /* The data sheet seems to imply that just a number on its own is valid
1811 here, but the RISC iX assembler seems to accept a prefix 'p'. We will
1813 if (**str
== 'p' || **str
== 'P')
1817 if (pchar
>= '0' && pchar
<= '9')
1819 processor
= pchar
- '0';
1820 if (**str
>= '0' && **str
<= '9')
1822 processor
= processor
* 10 + *(*str
)++ - '0';
1825 inst
.error
= _("Illegal co-processor number");
1832 inst
.error
= _("Bad or missing co-processor number");
1836 inst
.instruction
|= processor
<< 8;
1841 cp_opc_expr (str
, where
, length
)
1848 skip_whitespace (*str
);
1850 memset (&expr
, '\0', sizeof (expr
));
1852 if (my_get_expression (&expr
, str
))
1854 if (expr
.X_op
!= O_constant
)
1856 inst
.error
= _("bad or missing expression");
1860 if ((expr
.X_add_number
& ((1 << length
) - 1)) != expr
.X_add_number
)
1862 inst
.error
= _("immediate co-processor expression too large");
1866 inst
.instruction
|= expr
.X_add_number
<< where
;
1871 cp_reg_required_here (str
, where
)
1878 if ((reg
= arm_reg_parse (str
)) != FAIL
&& cp_register (reg
))
1881 inst
.instruction
|= reg
<< where
;
1885 /* In the few cases where we might be able to accept something else
1886 this error can be overridden. */
1887 inst
.error
= _("Co-processor register expected");
1889 /* Restore the start point. */
1895 fp_reg_required_here (str
, where
)
1902 if ((reg
= arm_reg_parse (str
)) != FAIL
&& fp_register (reg
))
1905 inst
.instruction
|= reg
<< where
;
1909 /* In the few cases where we might be able to accept something else
1910 this error can be overridden. */
1911 inst
.error
= _("Floating point register expected");
1913 /* Restore the start point. */
1919 cp_address_offset (str
)
1924 skip_whitespace (*str
);
1926 if (! is_immediate_prefix (**str
))
1928 inst
.error
= _("immediate expression expected");
1934 if (my_get_expression (&inst
.reloc
.exp
, str
))
1937 if (inst
.reloc
.exp
.X_op
== O_constant
)
1939 offset
= inst
.reloc
.exp
.X_add_number
;
1943 inst
.error
= _("co-processor address must be word aligned");
1947 if (offset
> 1023 || offset
< -1023)
1949 inst
.error
= _("offset too large");
1954 inst
.instruction
|= INDEX_UP
;
1958 inst
.instruction
|= offset
>> 2;
1961 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
1967 cp_address_required_here (str
)
1979 skip_whitespace (p
);
1981 if ((reg
= reg_required_here (&p
, 16)) == FAIL
)
1984 skip_whitespace (p
);
1990 if (skip_past_comma (&p
) == SUCCESS
)
1993 write_back
= WRITE_BACK
;
1997 inst
.error
= _("pc may not be used in post-increment");
2001 if (cp_address_offset (&p
) == FAIL
)
2005 pre_inc
= PRE_INDEX
| INDEX_UP
;
2009 /* '['Rn, #expr']'[!] */
2011 if (skip_past_comma (&p
) == FAIL
)
2013 inst
.error
= _("pre-indexed expression expected");
2017 pre_inc
= PRE_INDEX
;
2019 if (cp_address_offset (&p
) == FAIL
)
2022 skip_whitespace (p
);
2026 inst
.error
= _("missing ]");
2030 skip_whitespace (p
);
2036 inst
.error
= _("pc may not be used with write-back");
2041 write_back
= WRITE_BACK
;
2047 if (my_get_expression (&inst
.reloc
.exp
, &p
))
2050 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
2051 inst
.reloc
.exp
.X_add_number
-= 8; /* PC rel adjust. */
2052 inst
.reloc
.pc_rel
= 1;
2053 inst
.instruction
|= (REG_PC
<< 16);
2054 pre_inc
= PRE_INDEX
;
2057 inst
.instruction
|= write_back
| pre_inc
;
2065 unsigned long flags
;
2067 /* Do nothing really. */
2068 inst
.instruction
|= flags
; /* This is pointless. */
2076 unsigned long flags
;
2080 /* Only one syntax. */
2081 skip_whitespace (str
);
2083 if (reg_required_here (&str
, 12) == FAIL
)
2085 inst
.error
= BAD_ARGS
;
2089 if (skip_past_comma (&str
) == FAIL
)
2091 inst
.error
= _("comma expected after register name");
2095 skip_whitespace (str
);
2097 if (strcmp (str
, "CPSR") == 0
2098 || strcmp (str
, "SPSR") == 0
2099 /* Lower case versions for backwards compatability. */
2100 || strcmp (str
, "cpsr") == 0
2101 || strcmp (str
, "spsr") == 0)
2104 /* This is for backwards compatability with older toolchains. */
2105 else if (strcmp (str
, "cpsr_all") == 0
2106 || strcmp (str
, "spsr_all") == 0)
2110 inst
.error
= _("{C|S}PSR expected");
2114 if (*str
== 's' || *str
== 'S')
2115 inst
.instruction
|= SPSR_BIT
;
2118 inst
.instruction
|= flags
;
2122 /* Two possible forms:
2123 "{C|S}PSR_<field>, Rm",
2124 "{C|S}PSR_f, #expression". */
2129 unsigned long flags
;
2131 skip_whitespace (str
);
2133 if (psr_required_here (&str
) == FAIL
)
2136 if (skip_past_comma (&str
) == FAIL
)
2138 inst
.error
= _("comma missing after psr flags");
2142 skip_whitespace (str
);
2144 if (reg_required_here (&str
, 0) != FAIL
)
2147 inst
.instruction
|= flags
;
2152 if (! is_immediate_prefix (*str
))
2155 _("only a register or immediate value can follow a psr flag");
2162 if (my_get_expression (&inst
.reloc
.exp
, &str
))
2165 _("only a register or immediate value can follow a psr flag");
2169 if (inst
.instruction
& ((PSR_c
| PSR_x
| PSR_s
) << PSR_SHIFT
))
2171 inst
.error
= _("can only set flag field with immediate value");
2175 flags
|= INST_IMMEDIATE
;
2177 if (inst
.reloc
.exp
.X_add_symbol
)
2179 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2180 inst
.reloc
.pc_rel
= 0;
2184 unsigned value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
2186 if (value
== (unsigned) FAIL
)
2188 inst
.error
= _("Invalid constant");
2192 inst
.instruction
|= value
;
2196 inst
.instruction
|= flags
;
2200 /* Long Multiply Parser
2201 UMULL RdLo, RdHi, Rm, Rs
2202 SMULL RdLo, RdHi, Rm, Rs
2203 UMLAL RdLo, RdHi, Rm, Rs
2204 SMLAL RdLo, RdHi, Rm, Rs
2208 do_mull (str
, flags
)
2210 unsigned long flags
;
2212 int rdlo
, rdhi
, rm
, rs
;
2214 /* Only one format "rdlo, rdhi, rm, rs". */
2215 skip_whitespace (str
);
2217 if ((rdlo
= reg_required_here (&str
, 12)) == FAIL
)
2219 inst
.error
= BAD_ARGS
;
2223 if (skip_past_comma (&str
) == FAIL
2224 || (rdhi
= reg_required_here (&str
, 16)) == FAIL
)
2226 inst
.error
= BAD_ARGS
;
2230 if (skip_past_comma (&str
) == FAIL
2231 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2233 inst
.error
= BAD_ARGS
;
2237 /* rdhi, rdlo and rm must all be different. */
2238 if (rdlo
== rdhi
|| rdlo
== rm
|| rdhi
== rm
)
2239 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
2241 if (skip_past_comma (&str
) == FAIL
2242 || (rs
= reg_required_here (&str
, 8)) == FAIL
)
2244 inst
.error
= BAD_ARGS
;
2248 if (rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
|| rdhi
== REG_PC
)
2250 inst
.error
= BAD_PC
;
2254 inst
.instruction
|= flags
;
2262 unsigned long flags
;
2266 /* Only one format "rd, rm, rs". */
2267 skip_whitespace (str
);
2269 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2271 inst
.error
= BAD_ARGS
;
2277 inst
.error
= BAD_PC
;
2281 if (skip_past_comma (&str
) == FAIL
2282 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2284 inst
.error
= BAD_ARGS
;
2290 inst
.error
= BAD_PC
;
2295 as_tsktsk (_("rd and rm should be different in mul"));
2297 if (skip_past_comma (&str
) == FAIL
2298 || (rm
= reg_required_here (&str
, 8)) == FAIL
)
2300 inst
.error
= BAD_ARGS
;
2306 inst
.error
= BAD_PC
;
2310 inst
.instruction
|= flags
;
2318 unsigned long flags
;
2322 /* Only one format "rd, rm, rs, rn". */
2323 skip_whitespace (str
);
2325 if ((rd
= reg_required_here (&str
, 16)) == FAIL
)
2327 inst
.error
= BAD_ARGS
;
2333 inst
.error
= BAD_PC
;
2337 if (skip_past_comma (&str
) == FAIL
2338 || (rm
= reg_required_here (&str
, 0)) == FAIL
)
2340 inst
.error
= BAD_ARGS
;
2346 inst
.error
= BAD_PC
;
2351 as_tsktsk (_("rd and rm should be different in mla"));
2353 if (skip_past_comma (&str
) == FAIL
2354 || (rd
= reg_required_here (&str
, 8)) == FAIL
2355 || skip_past_comma (&str
) == FAIL
2356 || (rm
= reg_required_here (&str
, 12)) == FAIL
)
2358 inst
.error
= BAD_ARGS
;
2362 if (rd
== REG_PC
|| rm
== REG_PC
)
2364 inst
.error
= BAD_PC
;
2368 inst
.instruction
|= flags
;
2373 /* Return the index into fp_values of a floating point number,
2374 or -1 if not in the table. */
2377 my_get_float_expression (str
)
2380 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
2386 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
2388 /* Look for a raw floating point number. */
2389 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
2390 && is_end_of_line
[(unsigned char) *save_in
])
2392 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2394 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2396 if (words
[j
] != fp_values
[i
][j
])
2400 if (j
== MAX_LITTLENUMS
)
2408 /* Try and parse a more complex expression, this will probably fail
2409 unless the code uses a floating point prefix (eg "0f"). */
2410 save_in
= input_line_pointer
;
2411 input_line_pointer
= *str
;
2412 if (expression (&exp
) == absolute_section
2413 && exp
.X_op
== O_big
2414 && exp
.X_add_number
< 0)
2416 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
2418 if (gen_to_words (words
, 5, (long) 15) == 0)
2420 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
2422 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
2424 if (words
[j
] != fp_values
[i
][j
])
2428 if (j
== MAX_LITTLENUMS
)
2430 *str
= input_line_pointer
;
2431 input_line_pointer
= save_in
;
2438 *str
= input_line_pointer
;
2439 input_line_pointer
= save_in
;
2443 /* Return true if anything in the expression is a bignum. */
2446 walk_no_bignums (sp
)
2449 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
2452 if (symbol_get_value_expression (sp
)->X_add_symbol
)
2454 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
2455 || (symbol_get_value_expression (sp
)->X_op_symbol
2456 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
2463 my_get_expression (ep
, str
)
2470 save_in
= input_line_pointer
;
2471 input_line_pointer
= *str
;
2472 seg
= expression (ep
);
2475 if (seg
!= absolute_section
2476 && seg
!= text_section
2477 && seg
!= data_section
2478 && seg
!= bss_section
2479 && seg
!= undefined_section
)
2481 inst
.error
= _("bad_segment");
2482 *str
= input_line_pointer
;
2483 input_line_pointer
= save_in
;
2488 /* Get rid of any bignums now, so that we don't generate an error for which
2489 we can't establish a line number later on. Big numbers are never valid
2490 in instructions, which is where this routine is always called. */
2491 if (ep
->X_op
== O_big
2492 || (ep
->X_add_symbol
2493 && (walk_no_bignums (ep
->X_add_symbol
)
2495 && walk_no_bignums (ep
->X_op_symbol
)))))
2497 inst
.error
= _("Invalid constant");
2498 *str
= input_line_pointer
;
2499 input_line_pointer
= save_in
;
2503 *str
= input_line_pointer
;
2504 input_line_pointer
= save_in
;
2508 /* UNRESTRICT should be one if <shift> <register> is permitted for this
2512 decode_shift (str
, unrestrict
)
2516 struct asm_shift
*shft
;
2520 skip_whitespace (*str
);
2522 for (p
= *str
; isalpha (*p
); p
++)
2527 inst
.error
= _("Shift expression expected");
2533 shft
= (struct asm_shift
*) hash_find (arm_shift_hsh
, *str
);
2537 if (!strncmp (*str
, "rrx", 3)
2538 || !strncmp (*str
, "RRX", 3))
2541 inst
.instruction
|= shft
->value
;
2545 skip_whitespace (p
);
2547 if (unrestrict
&& reg_required_here (&p
, 8) != FAIL
)
2549 inst
.instruction
|= shft
->value
| SHIFT_BY_REG
;
2553 else if (is_immediate_prefix (*p
))
2557 if (my_get_expression (&inst
.reloc
.exp
, &p
))
2560 /* Validate some simple #expressions. */
2561 if (inst
.reloc
.exp
.X_op
== O_constant
)
2563 unsigned num
= inst
.reloc
.exp
.X_add_number
;
2565 /* Reject operations greater than 32, or lsl #32. */
2566 if (num
> 32 || (num
== 32 && shft
->value
== 0))
2568 inst
.error
= _("Invalid immediate shift");
2572 /* Shifts of zero should be converted to lsl (which is
2580 /* Shifts of 32 are encoded as 0, for those shifts that
2585 inst
.instruction
|= (num
<< 7) | shft
->value
;
2590 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
2591 inst
.reloc
.pc_rel
= 0;
2592 inst
.instruction
|= shft
->value
;
2598 inst
.error
= (unrestrict
2599 ? _("shift requires register or #expression")
2600 : _("shift requires #expression"));
2606 inst
.error
= _("Shift expression expected");
2610 /* Do those data_ops which can take a negative immediate constant
2611 by altering the instuction. A bit of a hack really. */
2615 by inverting the second operand, and
2618 by negating the second operand.
2622 negate_data_op (instruction
, value
)
2623 unsigned long *instruction
;
2624 unsigned long value
;
2627 unsigned long negated
, inverted
;
2629 negated
= validate_immediate (-value
);
2630 inverted
= validate_immediate (~value
);
2632 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
2635 /* First negates. */
2636 case OPCODE_SUB
: /* ADD <-> SUB */
2637 new_inst
= OPCODE_ADD
;
2642 new_inst
= OPCODE_SUB
;
2646 case OPCODE_CMP
: /* CMP <-> CMN */
2647 new_inst
= OPCODE_CMN
;
2652 new_inst
= OPCODE_CMP
;
2656 /* Now Inverted ops. */
2657 case OPCODE_MOV
: /* MOV <-> MVN */
2658 new_inst
= OPCODE_MVN
;
2663 new_inst
= OPCODE_MOV
;
2667 case OPCODE_AND
: /* AND <-> BIC */
2668 new_inst
= OPCODE_BIC
;
2673 new_inst
= OPCODE_AND
;
2677 case OPCODE_ADC
: /* ADC <-> SBC */
2678 new_inst
= OPCODE_SBC
;
2683 new_inst
= OPCODE_ADC
;
2687 /* We cannot do anything. */
2692 if (value
== (unsigned) FAIL
)
2695 *instruction
&= OPCODE_MASK
;
2696 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
2707 skip_whitespace (*str
);
2709 if (reg_required_here (str
, 0) != FAIL
)
2711 if (skip_past_comma (str
) == SUCCESS
)
2712 /* Shift operation on register. */
2713 return decode_shift (str
, NO_SHIFT_RESTRICT
);
2719 /* Immediate expression. */
2720 if (is_immediate_prefix (**str
))
2725 if (my_get_expression (&inst
.reloc
.exp
, str
))
2728 if (inst
.reloc
.exp
.X_add_symbol
)
2730 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2731 inst
.reloc
.pc_rel
= 0;
2735 if (skip_past_comma (str
) == SUCCESS
)
2737 /* #x, y -- ie explicit rotation by Y. */
2738 if (my_get_expression (&expr
, str
))
2741 if (expr
.X_op
!= O_constant
)
2743 inst
.error
= _("Constant expression expected");
2747 /* Rotate must be a multiple of 2. */
2748 if (((unsigned) expr
.X_add_number
) > 30
2749 || (expr
.X_add_number
& 1) != 0
2750 || ((unsigned) inst
.reloc
.exp
.X_add_number
) > 255)
2752 inst
.error
= _("Invalid constant");
2755 inst
.instruction
|= INST_IMMEDIATE
;
2756 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
2757 inst
.instruction
|= expr
.X_add_number
<< 7;
2761 /* Implicit rotation, select a suitable one. */
2762 value
= validate_immediate (inst
.reloc
.exp
.X_add_number
);
2766 /* Can't be done. Perhaps the code reads something like
2767 "add Rd, Rn, #-n", where "sub Rd, Rn, #n" would be ok. */
2768 if ((value
= negate_data_op (&inst
.instruction
,
2769 inst
.reloc
.exp
.X_add_number
))
2772 inst
.error
= _("Invalid constant");
2777 inst
.instruction
|= value
;
2780 inst
.instruction
|= INST_IMMEDIATE
;
2785 inst
.error
= _("Register or shift expression expected");
2794 skip_whitespace (*str
);
2796 if (fp_reg_required_here (str
, 0) != FAIL
)
2800 /* Immediate expression. */
2801 if (*((*str
)++) == '#')
2807 skip_whitespace (*str
);
2809 /* First try and match exact strings, this is to guarantee
2810 that some formats will work even for cross assembly. */
2812 for (i
= 0; fp_const
[i
]; i
++)
2814 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
2818 *str
+= strlen (fp_const
[i
]);
2819 if (is_end_of_line
[(unsigned char) **str
])
2821 inst
.instruction
|= i
+ 8;
2828 /* Just because we didn't get a match doesn't mean that the
2829 constant isn't valid, just that it is in a format that we
2830 don't automatically recognize. Try parsing it with
2831 the standard expression routines. */
2832 if ((i
= my_get_float_expression (str
)) >= 0)
2834 inst
.instruction
|= i
+ 8;
2838 inst
.error
= _("Invalid floating point immediate expression");
2842 _("Floating point register or immediate expression expected");
2848 do_arit (str
, flags
)
2850 unsigned long flags
;
2852 skip_whitespace (str
);
2854 if (reg_required_here (&str
, 12) == FAIL
2855 || skip_past_comma (&str
) == FAIL
2856 || reg_required_here (&str
, 16) == FAIL
2857 || skip_past_comma (&str
) == FAIL
2858 || data_op2 (&str
) == FAIL
)
2861 inst
.error
= BAD_ARGS
;
2865 inst
.instruction
|= flags
;
2873 unsigned long flags
;
2875 /* This is a pseudo-op of the form "adr rd, label" to be converted
2876 into a relative address of the form "add rd, pc, #label-.-8". */
2877 skip_whitespace (str
);
2879 if (reg_required_here (&str
, 12) == FAIL
2880 || skip_past_comma (&str
) == FAIL
2881 || my_get_expression (&inst
.reloc
.exp
, &str
))
2884 inst
.error
= BAD_ARGS
;
2888 /* Frag hacking will turn this into a sub instruction if the offset turns
2889 out to be negative. */
2890 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
2891 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust. */
2892 inst
.reloc
.pc_rel
= 1;
2893 inst
.instruction
|= flags
;
2899 do_adrl (str
, flags
)
2901 unsigned long flags
;
2903 /* This is a pseudo-op of the form "adrl rd, label" to be converted
2904 into a relative address of the form:
2905 add rd, pc, #low(label-.-8)"
2906 add rd, rd, #high(label-.-8)" */
2908 skip_whitespace (str
);
2910 if (reg_required_here (&str
, 12) == FAIL
2911 || skip_past_comma (&str
) == FAIL
2912 || my_get_expression (&inst
.reloc
.exp
, &str
))
2915 inst
.error
= BAD_ARGS
;
2921 /* Frag hacking will turn this into a sub instruction if the offset turns
2922 out to be negative. */
2923 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
2924 inst
.reloc
.exp
.X_add_number
-= 8; /* PC relative adjust */
2925 inst
.reloc
.pc_rel
= 1;
2926 inst
.instruction
|= flags
;
2927 inst
.size
= INSN_SIZE
* 2;
2935 unsigned long flags
;
2937 skip_whitespace (str
);
2939 if (reg_required_here (&str
, 16) == FAIL
)
2942 inst
.error
= BAD_ARGS
;
2946 if (skip_past_comma (&str
) == FAIL
2947 || data_op2 (&str
) == FAIL
)
2950 inst
.error
= BAD_ARGS
;
2954 inst
.instruction
|= flags
;
2955 if ((flags
& 0x0000f000) == 0)
2956 inst
.instruction
|= CONDS_BIT
;
2965 unsigned long flags
;
2967 skip_whitespace (str
);
2969 if (reg_required_here (&str
, 12) == FAIL
)
2972 inst
.error
= BAD_ARGS
;
2976 if (skip_past_comma (&str
) == FAIL
2977 || data_op2 (&str
) == FAIL
)
2980 inst
.error
= BAD_ARGS
;
2984 inst
.instruction
|= flags
;
2990 ldst_extend (str
, hwse
)
3001 if (my_get_expression (&inst
.reloc
.exp
, str
))
3004 if (inst
.reloc
.exp
.X_op
== O_constant
)
3006 int value
= inst
.reloc
.exp
.X_add_number
;
3008 if ((hwse
&& (value
< -255 || value
> 255))
3009 || (value
< -4095 || value
> 4095))
3011 inst
.error
= _("address offset too large");
3021 /* Halfword and signextension instructions have the
3022 immediate value split across bits 11..8 and bits 3..0. */
3024 inst
.instruction
|= (add
| HWOFFSET_IMM
3025 | ((value
>> 4) << 8) | (value
& 0xF));
3027 inst
.instruction
|= add
| value
;
3033 inst
.instruction
|= HWOFFSET_IMM
;
3034 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
3037 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
3038 inst
.reloc
.pc_rel
= 0;
3051 if (reg_required_here (str
, 0) == FAIL
)
3055 inst
.instruction
|= add
;
3058 inst
.instruction
|= add
| OFFSET_REG
;
3059 if (skip_past_comma (str
) == SUCCESS
)
3060 return decode_shift (str
, SHIFT_RESTRICT
);
3068 do_ldst (str
, flags
)
3070 unsigned long flags
;
3077 /* This is not ideal, but it is the simplest way of dealing with the
3078 ARM7T halfword instructions (since they use a different
3079 encoding, but the same mnemonic): */
3080 halfword
= (flags
& 0x80000000) != 0;
3083 /* This is actually a load/store of a halfword, or a
3084 signed-extension load. */
3085 if ((cpu_variant
& ARM_HALFWORD
) == 0)
3088 = _("Processor does not support halfwords or signed bytes");
3092 inst
.instruction
= ((inst
.instruction
& COND_MASK
)
3093 | (flags
& ~COND_MASK
));
3098 skip_whitespace (str
);
3100 if ((conflict_reg
= reg_required_here (&str
, 12)) == FAIL
)
3103 inst
.error
= BAD_ARGS
;
3107 if (skip_past_comma (&str
) == FAIL
)
3109 inst
.error
= _("Address expected");
3119 skip_whitespace (str
);
3121 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3124 /* Conflicts can occur on stores as well as loads. */
3125 conflict_reg
= (conflict_reg
== reg
);
3127 skip_whitespace (str
);
3133 if (skip_past_comma (&str
) == SUCCESS
)
3135 /* [Rn],... (post inc) */
3136 if (ldst_extend (&str
, halfword
) == FAIL
)
3139 as_warn (_("%s register same as write-back base"),
3140 ((inst
.instruction
& LOAD_BIT
)
3141 ? _("destination") : _("source")));
3147 inst
.instruction
|= HWOFFSET_IMM
;
3149 skip_whitespace (str
);
3154 as_warn (_("%s register same as write-back base"),
3155 ((inst
.instruction
& LOAD_BIT
)
3156 ? _("destination") : _("source")));
3158 inst
.instruction
|= WRITE_BACK
;
3162 if (! (flags
& TRANS_BIT
))
3169 if (skip_past_comma (&str
) == FAIL
)
3171 inst
.error
= _("pre-indexed expression expected");
3176 if (ldst_extend (&str
, halfword
) == FAIL
)
3179 skip_whitespace (str
);
3183 inst
.error
= _("missing ]");
3187 skip_whitespace (str
);
3192 as_warn (_("%s register same as write-back base"),
3193 ((inst
.instruction
& LOAD_BIT
)
3194 ? _("destination") : _("source")));
3196 inst
.instruction
|= WRITE_BACK
;
3200 else if (*str
== '=')
3202 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
3205 skip_whitespace (str
);
3207 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3210 if (inst
.reloc
.exp
.X_op
!= O_constant
3211 && inst
.reloc
.exp
.X_op
!= O_symbol
)
3213 inst
.error
= _("Constant expression expected");
3217 if (inst
.reloc
.exp
.X_op
== O_constant
3218 && (value
= validate_immediate (inst
.reloc
.exp
.X_add_number
)) != FAIL
)
3220 /* This can be done with a mov instruction. */
3221 inst
.instruction
&= LITERAL_MASK
;
3222 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
3223 inst
.instruction
|= (flags
& COND_MASK
) | (value
& 0xfff);
3229 /* Insert into literal pool. */
3230 if (add_to_lit_pool () == FAIL
)
3233 inst
.error
= _("literal pool insertion failed");
3237 /* Change the instruction exp to point to the pool. */
3240 inst
.instruction
|= HWOFFSET_IMM
;
3241 inst
.reloc
.type
= BFD_RELOC_ARM_HWLITERAL
;
3244 inst
.reloc
.type
= BFD_RELOC_ARM_LITERAL
;
3245 inst
.reloc
.pc_rel
= 1;
3246 inst
.instruction
|= (REG_PC
<< 16);
3252 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3257 inst
.instruction
|= HWOFFSET_IMM
;
3258 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
3261 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
3263 /* PC rel adjust. */
3264 inst
.reloc
.exp
.X_add_number
-= 8;
3266 inst
.reloc
.pc_rel
= 1;
3267 inst
.instruction
|= (REG_PC
<< 16);
3271 if (pre_inc
&& (flags
& TRANS_BIT
))
3272 inst
.error
= _("Pre-increment instruction with translate");
3274 inst
.instruction
|= flags
| (pre_inc
? PRE_INDEX
: 0);
3287 /* We come back here if we get ranges concatenated by '+' or '|'. */
3302 skip_whitespace (str
);
3304 if ((reg
= reg_required_here (&str
, -1)) == FAIL
)
3313 inst
.error
= _("Bad range in register list");
3317 for (i
= cur_reg
+ 1; i
< reg
; i
++)
3319 if (range
& (1 << i
))
3321 (_("Warning: Duplicated register (r%d) in register list"),
3329 if (range
& (1 << reg
))
3330 as_tsktsk (_("Warning: Duplicated register (r%d) in register list"),
3332 else if (reg
<= cur_reg
)
3333 as_tsktsk (_("Warning: Register range not in ascending order"));
3338 while (skip_past_comma (&str
) != FAIL
3339 || (in_range
= 1, *str
++ == '-'));
3341 skip_whitespace (str
);
3345 inst
.error
= _("Missing `}'");
3353 if (my_get_expression (&expr
, &str
))
3356 if (expr
.X_op
== O_constant
)
3358 if (expr
.X_add_number
3359 != (expr
.X_add_number
& 0x0000ffff))
3361 inst
.error
= _("invalid register mask");
3365 if ((range
& expr
.X_add_number
) != 0)
3367 int regno
= range
& expr
.X_add_number
;
3370 regno
= (1 << regno
) - 1;
3372 (_("Warning: Duplicated register (r%d) in register list"),
3376 range
|= expr
.X_add_number
;
3380 if (inst
.reloc
.type
!= 0)
3382 inst
.error
= _("expression too complex");
3386 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
3387 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
3388 inst
.reloc
.pc_rel
= 0;
3392 skip_whitespace (str
);
3394 if (*str
== '|' || *str
== '+')
3400 while (another_range
);
3407 do_ldmstm (str
, flags
)
3409 unsigned long flags
;
3414 skip_whitespace (str
);
3416 if ((base_reg
= reg_required_here (&str
, 16)) == FAIL
)
3419 if (base_reg
== REG_PC
)
3421 inst
.error
= _("r15 not allowed as base register");
3425 skip_whitespace (str
);
3429 flags
|= WRITE_BACK
;
3433 if (skip_past_comma (&str
) == FAIL
3434 || (range
= reg_list (&str
)) == FAIL
)
3437 inst
.error
= BAD_ARGS
;
3444 flags
|= LDM_TYPE_2_OR_3
;
3447 inst
.instruction
|= flags
| range
;
3455 unsigned long flags
;
3457 skip_whitespace (str
);
3459 /* Allow optional leading '#'. */
3460 if (is_immediate_prefix (*str
))
3463 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3466 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
3467 inst
.reloc
.pc_rel
= 0;
3468 inst
.instruction
|= flags
;
3476 do_swap (str
, flags
)
3478 unsigned long flags
;
3482 skip_whitespace (str
);
3484 if ((reg
= reg_required_here (&str
, 12)) == FAIL
)
3489 inst
.error
= _("r15 not allowed in swap");
3493 if (skip_past_comma (&str
) == FAIL
3494 || (reg
= reg_required_here (&str
, 0)) == FAIL
)
3497 inst
.error
= BAD_ARGS
;
3503 inst
.error
= _("r15 not allowed in swap");
3507 if (skip_past_comma (&str
) == FAIL
3510 inst
.error
= BAD_ARGS
;
3514 skip_whitespace (str
);
3516 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3521 inst
.error
= BAD_PC
;
3525 skip_whitespace (str
);
3529 inst
.error
= _("missing ]");
3533 inst
.instruction
|= flags
;
3539 do_branch (str
, flags
)
3541 unsigned long flags ATTRIBUTE_UNUSED
;
3543 if (my_get_expression (&inst
.reloc
.exp
, &str
))
3550 /* ScottB: February 5, 1998 - Check to see of PLT32 reloc
3551 required for the instruction. */
3553 /* arm_parse_reloc () works on input_line_pointer.
3554 We actually want to parse the operands to the branch instruction
3555 passed in 'str'. Save the input pointer and restore it later. */
3556 save_in
= input_line_pointer
;
3557 input_line_pointer
= str
;
3558 if (inst
.reloc
.exp
.X_op
== O_symbol
3560 && arm_parse_reloc () == BFD_RELOC_ARM_PLT32
)
3562 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
3563 inst
.reloc
.pc_rel
= 0;
3564 /* Modify str to point to after parsed operands, otherwise
3565 end_of_line() will complain about the (PLT) left in str. */
3566 str
= input_line_pointer
;
3570 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
3571 inst
.reloc
.pc_rel
= 1;
3573 input_line_pointer
= save_in
;
3576 inst
.reloc
.type
= BFD_RELOC_ARM_PCREL_BRANCH
;
3577 inst
.reloc
.pc_rel
= 1;
3578 #endif /* OBJ_ELF */
3587 unsigned long flags ATTRIBUTE_UNUSED
;
3591 skip_whitespace (str
);
3593 if ((reg
= reg_required_here (&str
, 0)) == FAIL
)
3595 inst
.error
= BAD_ARGS
;
3600 inst
.error
= BAD_PC
;
3608 unsigned long flags ATTRIBUTE_UNUSED
;
3610 /* Co-processor data operation.
3611 Format: CDP{cond} CP#,<expr>,CRd,CRn,CRm{,<expr>} */
3612 skip_whitespace (str
);
3614 if (co_proc_number (&str
) == FAIL
)
3617 inst
.error
= BAD_ARGS
;
3621 if (skip_past_comma (&str
) == FAIL
3622 || cp_opc_expr (&str
, 20,4) == FAIL
)
3625 inst
.error
= BAD_ARGS
;
3629 if (skip_past_comma (&str
) == FAIL
3630 || cp_reg_required_here (&str
, 12) == FAIL
)
3633 inst
.error
= BAD_ARGS
;
3637 if (skip_past_comma (&str
) == FAIL
3638 || cp_reg_required_here (&str
, 16) == FAIL
)
3641 inst
.error
= BAD_ARGS
;
3645 if (skip_past_comma (&str
) == FAIL
3646 || cp_reg_required_here (&str
, 0) == FAIL
)
3649 inst
.error
= BAD_ARGS
;
3653 if (skip_past_comma (&str
) == SUCCESS
)
3655 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
3658 inst
.error
= BAD_ARGS
;
3668 do_lstc (str
, flags
)
3670 unsigned long flags
;
3672 /* Co-processor register load/store.
3673 Format: <LDC|STC{cond}[L] CP#,CRd,<address> */
3675 skip_whitespace (str
);
3677 if (co_proc_number (&str
) == FAIL
)
3680 inst
.error
= BAD_ARGS
;
3684 if (skip_past_comma (&str
) == FAIL
3685 || cp_reg_required_here (&str
, 12) == FAIL
)
3688 inst
.error
= BAD_ARGS
;
3692 if (skip_past_comma (&str
) == FAIL
3693 || cp_address_required_here (&str
) == FAIL
)
3696 inst
.error
= BAD_ARGS
;
3700 inst
.instruction
|= flags
;
3706 do_co_reg (str
, flags
)
3708 unsigned long flags
;
3710 /* Co-processor register transfer.
3711 Format: <MCR|MRC>{cond} CP#,<expr1>,Rd,CRn,CRm{,<expr2>} */
3713 skip_whitespace (str
);
3715 if (co_proc_number (&str
) == FAIL
)
3718 inst
.error
= BAD_ARGS
;
3722 if (skip_past_comma (&str
) == FAIL
3723 || cp_opc_expr (&str
, 21, 3) == FAIL
)
3726 inst
.error
= BAD_ARGS
;
3730 if (skip_past_comma (&str
) == FAIL
3731 || reg_required_here (&str
, 12) == FAIL
)
3734 inst
.error
= BAD_ARGS
;
3738 if (skip_past_comma (&str
) == FAIL
3739 || cp_reg_required_here (&str
, 16) == FAIL
)
3742 inst
.error
= BAD_ARGS
;
3746 if (skip_past_comma (&str
) == FAIL
3747 || cp_reg_required_here (&str
, 0) == FAIL
)
3750 inst
.error
= BAD_ARGS
;
3754 if (skip_past_comma (&str
) == SUCCESS
)
3756 if (cp_opc_expr (&str
, 5, 3) == FAIL
)
3759 inst
.error
= BAD_ARGS
;
3765 inst
.error
= BAD_COND
;
3773 do_fp_ctrl (str
, flags
)
3775 unsigned long flags ATTRIBUTE_UNUSED
;
3777 /* FP control registers.
3778 Format: <WFS|RFS|WFC|RFC>{cond} Rn */
3780 skip_whitespace (str
);
3782 if (reg_required_here (&str
, 12) == FAIL
)
3785 inst
.error
= BAD_ARGS
;
3794 do_fp_ldst (str
, flags
)
3796 unsigned long flags ATTRIBUTE_UNUSED
;
3798 skip_whitespace (str
);
3800 switch (inst
.suffix
)
3805 inst
.instruction
|= CP_T_X
;
3808 inst
.instruction
|= CP_T_Y
;
3811 inst
.instruction
|= CP_T_X
| CP_T_Y
;
3817 if (fp_reg_required_here (&str
, 12) == FAIL
)
3820 inst
.error
= BAD_ARGS
;
3824 if (skip_past_comma (&str
) == FAIL
3825 || cp_address_required_here (&str
) == FAIL
)
3828 inst
.error
= BAD_ARGS
;
3836 do_fp_ldmstm (str
, flags
)
3838 unsigned long flags
;
3842 skip_whitespace (str
);
3844 if (fp_reg_required_here (&str
, 12) == FAIL
)
3847 inst
.error
= BAD_ARGS
;
3851 /* Get Number of registers to transfer. */
3852 if (skip_past_comma (&str
) == FAIL
3853 || my_get_expression (&inst
.reloc
.exp
, &str
))
3856 inst
.error
= _("constant expression expected");
3860 if (inst
.reloc
.exp
.X_op
!= O_constant
)
3862 inst
.error
= _("Constant value required for number of registers");
3866 num_regs
= inst
.reloc
.exp
.X_add_number
;
3868 if (num_regs
< 1 || num_regs
> 4)
3870 inst
.error
= _("number of registers must be in the range [1:4]");
3877 inst
.instruction
|= CP_T_X
;
3880 inst
.instruction
|= CP_T_Y
;
3883 inst
.instruction
|= CP_T_Y
| CP_T_X
;
3897 /* The instruction specified "ea" or "fd", so we can only accept
3898 [Rn]{!}. The instruction does not really support stacking or
3899 unstacking, so we have to emulate these by setting appropriate
3900 bits and offsets. */
3901 if (skip_past_comma (&str
) == FAIL
3905 inst
.error
= BAD_ARGS
;
3910 skip_whitespace (str
);
3912 if ((reg
= reg_required_here (&str
, 16)) == FAIL
)
3915 skip_whitespace (str
);
3919 inst
.error
= BAD_ARGS
;
3931 _("R15 not allowed as base register with write-back");
3938 if (flags
& CP_T_Pre
)
3940 /* Pre-decrement. */
3941 offset
= 3 * num_regs
;
3947 /* Post-increment. */
3951 offset
= 3 * num_regs
;
3955 /* No write-back, so convert this into a standard pre-increment
3956 instruction -- aesthetically more pleasing. */
3957 flags
= CP_T_Pre
| CP_T_UD
;
3962 inst
.instruction
|= flags
| offset
;
3964 else if (skip_past_comma (&str
) == FAIL
3965 || cp_address_required_here (&str
) == FAIL
)
3968 inst
.error
= BAD_ARGS
;
3976 do_fp_dyadic (str
, flags
)
3978 unsigned long flags
;
3980 skip_whitespace (str
);
3982 switch (inst
.suffix
)
3987 inst
.instruction
|= 0x00000080;
3990 inst
.instruction
|= 0x00080000;
3996 if (fp_reg_required_here (&str
, 12) == FAIL
)
3999 inst
.error
= BAD_ARGS
;
4003 if (skip_past_comma (&str
) == FAIL
4004 || fp_reg_required_here (&str
, 16) == FAIL
)
4007 inst
.error
= BAD_ARGS
;
4011 if (skip_past_comma (&str
) == FAIL
4012 || fp_op2 (&str
) == FAIL
)
4015 inst
.error
= BAD_ARGS
;
4019 inst
.instruction
|= flags
;
4025 do_fp_monadic (str
, flags
)
4027 unsigned long flags
;
4029 skip_whitespace (str
);
4031 switch (inst
.suffix
)
4036 inst
.instruction
|= 0x00000080;
4039 inst
.instruction
|= 0x00080000;
4045 if (fp_reg_required_here (&str
, 12) == FAIL
)
4048 inst
.error
= BAD_ARGS
;
4052 if (skip_past_comma (&str
) == FAIL
4053 || fp_op2 (&str
) == FAIL
)
4056 inst
.error
= BAD_ARGS
;
4060 inst
.instruction
|= flags
;
4066 do_fp_cmp (str
, flags
)
4068 unsigned long flags
;
4070 skip_whitespace (str
);
4072 if (fp_reg_required_here (&str
, 16) == FAIL
)
4075 inst
.error
= BAD_ARGS
;
4079 if (skip_past_comma (&str
) == FAIL
4080 || fp_op2 (&str
) == FAIL
)
4083 inst
.error
= BAD_ARGS
;
4087 inst
.instruction
|= flags
;
4093 do_fp_from_reg (str
, flags
)
4095 unsigned long flags
;
4097 skip_whitespace (str
);
4099 switch (inst
.suffix
)
4104 inst
.instruction
|= 0x00000080;
4107 inst
.instruction
|= 0x00080000;
4113 if (fp_reg_required_here (&str
, 16) == FAIL
)
4116 inst
.error
= BAD_ARGS
;
4120 if (skip_past_comma (&str
) == FAIL
4121 || reg_required_here (&str
, 12) == FAIL
)
4124 inst
.error
= BAD_ARGS
;
4128 inst
.instruction
|= flags
;
4134 do_fp_to_reg (str
, flags
)
4136 unsigned long flags
;
4138 skip_whitespace (str
);
4140 if (reg_required_here (&str
, 12) == FAIL
)
4143 if (skip_past_comma (&str
) == FAIL
4144 || fp_reg_required_here (&str
, 0) == FAIL
)
4147 inst
.error
= BAD_ARGS
;
4151 inst
.instruction
|= flags
;
4156 /* Thumb specific routines. */
4158 /* Parse and validate that a register is of the right form, this saves
4159 repeated checking of this information in many similar cases.
4160 Unlike the 32-bit case we do not insert the register into the opcode
4161 here, since the position is often unknown until the full instruction
4165 thumb_reg (strp
, hi_lo
)
4171 if ((reg
= reg_required_here (strp
, -1)) == FAIL
)
4179 inst
.error
= _("lo register required");
4187 inst
.error
= _("hi register required");
4199 /* Parse an add or subtract instruction, SUBTRACT is non-zero if the opcode
4203 thumb_add_sub (str
, subtract
)
4207 int Rd
, Rs
, Rn
= FAIL
;
4209 skip_whitespace (str
);
4211 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
4212 || skip_past_comma (&str
) == FAIL
)
4215 inst
.error
= BAD_ARGS
;
4219 if (is_immediate_prefix (*str
))
4223 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4228 if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4231 if (skip_past_comma (&str
) == FAIL
)
4233 /* Two operand format, shuffle the registers
4234 and pretend there are 3. */
4238 else if (is_immediate_prefix (*str
))
4241 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4244 else if ((Rn
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4248 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4249 for the latter case, EXPR contains the immediate that was found. */
4252 /* All register format. */
4253 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
4257 inst
.error
= _("dest and source1 must be the same register");
4261 /* Can't do this for SUB. */
4264 inst
.error
= _("subtract valid only on lo regs");
4268 inst
.instruction
= (T_OPCODE_ADD_HI
4269 | (Rd
> 7 ? THUMB_H1
: 0)
4270 | (Rn
> 7 ? THUMB_H2
: 0));
4271 inst
.instruction
|= (Rd
& 7) | ((Rn
& 7) << 3);
4275 inst
.instruction
= subtract
? T_OPCODE_SUB_R3
: T_OPCODE_ADD_R3
;
4276 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
4281 /* Immediate expression, now things start to get nasty. */
4283 /* First deal with HI regs, only very restricted cases allowed:
4284 Adjusting SP, and using PC or SP to get an address. */
4285 if ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
4286 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
))
4288 inst
.error
= _("invalid Hi register with immediate");
4292 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4294 /* Value isn't known yet, all we can do is store all the fragments
4295 we know about in the instruction and let the reloc hacking
4297 inst
.instruction
= (subtract
? 0x8000 : 0) | (Rd
<< 4) | Rs
;
4298 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
4302 int offset
= inst
.reloc
.exp
.X_add_number
;
4312 /* Quick check, in case offset is MIN_INT. */
4315 inst
.error
= _("immediate value out of range");
4324 if (offset
& ~0x1fc)
4326 inst
.error
= _("invalid immediate value for stack adjust");
4329 inst
.instruction
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
4330 inst
.instruction
|= offset
>> 2;
4332 else if (Rs
== REG_PC
|| Rs
== REG_SP
)
4335 || (offset
& ~0x3fc))
4337 inst
.error
= _("invalid immediate for address calculation");
4340 inst
.instruction
= (Rs
== REG_PC
? T_OPCODE_ADD_PC
4342 inst
.instruction
|= (Rd
<< 8) | (offset
>> 2);
4348 inst
.error
= _("immediate value out of range");
4351 inst
.instruction
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
4352 inst
.instruction
|= (Rd
<< 8) | offset
;
4358 inst
.error
= _("immediate value out of range");
4361 inst
.instruction
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
4362 inst
.instruction
|= Rd
| (Rs
<< 3) | (offset
<< 6);
4371 thumb_shift (str
, shift
)
4375 int Rd
, Rs
, Rn
= FAIL
;
4377 skip_whitespace (str
);
4379 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4380 || skip_past_comma (&str
) == FAIL
)
4383 inst
.error
= BAD_ARGS
;
4387 if (is_immediate_prefix (*str
))
4389 /* Two operand immediate format, set Rs to Rd. */
4392 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4397 if ((Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4400 if (skip_past_comma (&str
) == FAIL
)
4402 /* Two operand format, shuffle the registers
4403 and pretend there are 3. */
4407 else if (is_immediate_prefix (*str
))
4410 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4413 else if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4417 /* We now have Rd and Rs set to registers, and Rn set to a register or FAIL;
4418 for the latter case, EXPR contains the immediate that was found. */
4424 inst
.error
= _("source1 and dest must be same register");
4430 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
4431 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
4432 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
4435 inst
.instruction
|= Rd
| (Rn
<< 3);
4441 case THUMB_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
4442 case THUMB_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
4443 case THUMB_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
4446 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4448 /* Value isn't known yet, create a dummy reloc and let reloc
4449 hacking fix it up. */
4451 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
4455 unsigned shift_value
= inst
.reloc
.exp
.X_add_number
;
4457 if (shift_value
> 32 || (shift_value
== 32 && shift
== THUMB_LSL
))
4459 inst
.error
= _("Invalid immediate for shift");
4463 /* Shifts of zero are handled by converting to LSL. */
4464 if (shift_value
== 0)
4465 inst
.instruction
= T_OPCODE_LSL_I
;
4467 /* Shifts of 32 are encoded as a shift of zero. */
4468 if (shift_value
== 32)
4471 inst
.instruction
|= shift_value
<< 6;
4474 inst
.instruction
|= Rd
| (Rs
<< 3);
4481 thumb_mov_compare (str
, move
)
4487 skip_whitespace (str
);
4489 if ((Rd
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
4490 || skip_past_comma (&str
) == FAIL
)
4493 inst
.error
= BAD_ARGS
;
4497 if (is_immediate_prefix (*str
))
4500 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4503 else if ((Rs
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4508 if (Rs
< 8 && Rd
< 8)
4510 if (move
== THUMB_MOVE
)
4511 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
4512 since a MOV instruction produces unpredictable results. */
4513 inst
.instruction
= T_OPCODE_ADD_I3
;
4515 inst
.instruction
= T_OPCODE_CMP_LR
;
4516 inst
.instruction
|= Rd
| (Rs
<< 3);
4520 if (move
== THUMB_MOVE
)
4521 inst
.instruction
= T_OPCODE_MOV_HR
;
4523 inst
.instruction
= T_OPCODE_CMP_HR
;
4526 inst
.instruction
|= THUMB_H1
;
4529 inst
.instruction
|= THUMB_H2
;
4531 inst
.instruction
|= (Rd
& 7) | ((Rs
& 7) << 3);
4538 inst
.error
= _("only lo regs allowed with immediate");
4542 if (move
== THUMB_MOVE
)
4543 inst
.instruction
= T_OPCODE_MOV_I8
;
4545 inst
.instruction
= T_OPCODE_CMP_I8
;
4547 inst
.instruction
|= Rd
<< 8;
4549 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4550 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
4553 unsigned value
= inst
.reloc
.exp
.X_add_number
;
4557 inst
.error
= _("invalid immediate");
4561 inst
.instruction
|= value
;
4569 thumb_load_store (str
, load_store
, size
)
4574 int Rd
, Rb
, Ro
= FAIL
;
4576 skip_whitespace (str
);
4578 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4579 || skip_past_comma (&str
) == FAIL
)
4582 inst
.error
= BAD_ARGS
;
4589 if ((Rb
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4592 if (skip_past_comma (&str
) != FAIL
)
4594 if (is_immediate_prefix (*str
))
4597 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4600 else if ((Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4605 inst
.reloc
.exp
.X_op
= O_constant
;
4606 inst
.reloc
.exp
.X_add_number
= 0;
4611 inst
.error
= _("expected ']'");
4616 else if (*str
== '=')
4618 /* Parse an "ldr Rd, =expr" instruction; this is another pseudo op. */
4621 skip_whitespace (str
);
4623 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4628 if (inst
.reloc
.exp
.X_op
!= O_constant
4629 && inst
.reloc
.exp
.X_op
!= O_symbol
)
4631 inst
.error
= "Constant expression expected";
4635 if (inst
.reloc
.exp
.X_op
== O_constant
4636 && ((inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0))
4638 /* This can be done with a mov instruction. */
4640 inst
.instruction
= T_OPCODE_MOV_I8
| (Rd
<< 8);
4641 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
4645 /* Insert into literal pool. */
4646 if (add_to_lit_pool () == FAIL
)
4649 inst
.error
= "literal pool insertion failed";
4653 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4654 inst
.reloc
.pc_rel
= 1;
4655 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
4656 /* Adjust ARM pipeline offset to Thumb. */
4657 inst
.reloc
.exp
.X_add_number
+= 4;
4663 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4666 inst
.instruction
= T_OPCODE_LDR_PC
| (Rd
<< 8);
4667 inst
.reloc
.pc_rel
= 1;
4668 inst
.reloc
.exp
.X_add_number
-= 4; /* Pipeline offset. */
4669 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4674 if (Rb
== REG_PC
|| Rb
== REG_SP
)
4676 if (size
!= THUMB_WORD
)
4678 inst
.error
= _("byte or halfword not valid for base register");
4681 else if (Rb
== REG_PC
&& load_store
!= THUMB_LOAD
)
4683 inst
.error
= _("R15 based store not allowed");
4686 else if (Ro
!= FAIL
)
4688 inst
.error
= _("Invalid base register for register offset");
4693 inst
.instruction
= T_OPCODE_LDR_PC
;
4694 else if (load_store
== THUMB_LOAD
)
4695 inst
.instruction
= T_OPCODE_LDR_SP
;
4697 inst
.instruction
= T_OPCODE_STR_SP
;
4699 inst
.instruction
|= Rd
<< 8;
4700 if (inst
.reloc
.exp
.X_op
== O_constant
)
4702 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
4704 if (offset
& ~0x3fc)
4706 inst
.error
= _("invalid offset");
4710 inst
.instruction
|= offset
>> 2;
4713 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4717 inst
.error
= _("invalid base register in load/store");
4720 else if (Ro
== FAIL
)
4722 /* Immediate offset. */
4723 if (size
== THUMB_WORD
)
4724 inst
.instruction
= (load_store
== THUMB_LOAD
4725 ? T_OPCODE_LDR_IW
: T_OPCODE_STR_IW
);
4726 else if (size
== THUMB_HALFWORD
)
4727 inst
.instruction
= (load_store
== THUMB_LOAD
4728 ? T_OPCODE_LDR_IH
: T_OPCODE_STR_IH
);
4730 inst
.instruction
= (load_store
== THUMB_LOAD
4731 ? T_OPCODE_LDR_IB
: T_OPCODE_STR_IB
);
4733 inst
.instruction
|= Rd
| (Rb
<< 3);
4735 if (inst
.reloc
.exp
.X_op
== O_constant
)
4737 unsigned offset
= inst
.reloc
.exp
.X_add_number
;
4739 if (offset
& ~(0x1f << size
))
4741 inst
.error
= _("Invalid offset");
4744 inst
.instruction
|= (offset
>> size
) << 6;
4747 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
4751 /* Register offset. */
4752 if (size
== THUMB_WORD
)
4753 inst
.instruction
= (load_store
== THUMB_LOAD
4754 ? T_OPCODE_LDR_RW
: T_OPCODE_STR_RW
);
4755 else if (size
== THUMB_HALFWORD
)
4756 inst
.instruction
= (load_store
== THUMB_LOAD
4757 ? T_OPCODE_LDR_RH
: T_OPCODE_STR_RH
);
4759 inst
.instruction
= (load_store
== THUMB_LOAD
4760 ? T_OPCODE_LDR_RB
: T_OPCODE_STR_RB
);
4762 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
4777 /* Handle the Format 4 instructions that do not have equivalents in other
4778 formats. That is, ADC, AND, EOR, SBC, ROR, TST, NEG, CMN, ORR, MUL,
4787 skip_whitespace (str
);
4789 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
4790 || skip_past_comma (&str
) == FAIL
4791 || (Rs
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4793 inst
.error
= BAD_ARGS
;
4797 if (skip_past_comma (&str
) != FAIL
)
4799 /* Three operand format not allowed for TST, CMN, NEG and MVN.
4800 (It isn't allowed for CMP either, but that isn't handled by this
4802 if (inst
.instruction
== T_OPCODE_TST
4803 || inst
.instruction
== T_OPCODE_CMN
4804 || inst
.instruction
== T_OPCODE_NEG
4805 || inst
.instruction
== T_OPCODE_MVN
)
4807 inst
.error
= BAD_ARGS
;
4811 if ((Rn
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4816 inst
.error
= _("dest and source1 one must be the same register");
4822 if (inst
.instruction
== T_OPCODE_MUL
4824 as_tsktsk (_("Rs and Rd must be different in MUL"));
4826 inst
.instruction
|= Rd
| (Rs
<< 3);
4834 thumb_add_sub (str
, 0);
4841 thumb_shift (str
, THUMB_ASR
);
4848 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4850 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
4851 inst
.reloc
.pc_rel
= 1;
4859 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4861 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
4862 inst
.reloc
.pc_rel
= 1;
4866 /* Find the real, Thumb encoded start of a Thumb function. */
4869 find_real_start (symbolP
)
4873 const char *name
= S_GET_NAME (symbolP
);
4874 symbolS
*new_target
;
4876 /* This definiton must agree with the one in gcc/config/arm/thumb.c. */
4877 #define STUB_NAME ".real_start_of"
4882 /* Names that start with '.' are local labels, not function entry points.
4883 The compiler may generate BL instructions to these labels because it
4884 needs to perform a branch to a far away location. */
4888 real_start
= malloc (strlen (name
) + strlen (STUB_NAME
) + 1);
4889 sprintf (real_start
, "%s%s", STUB_NAME
, name
);
4891 new_target
= symbol_find (real_start
);
4893 if (new_target
== NULL
)
4895 as_warn ("Failed to find real start of function: %s\n", name
);
4896 new_target
= symbolP
;
4908 if (my_get_expression (&inst
.reloc
.exp
, &str
))
4911 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
4912 inst
.reloc
.pc_rel
= 1;
4915 /* If the destination of the branch is a defined symbol which does not have
4916 the THUMB_FUNC attribute, then we must be calling a function which has
4917 the (interfacearm) attribute. We look for the Thumb entry point to that
4918 function and change the branch to refer to that function instead. */
4919 if (inst
.reloc
.exp
.X_op
== O_symbol
4920 && inst
.reloc
.exp
.X_add_symbol
!= NULL
4921 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
4922 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
4923 inst
.reloc
.exp
.X_add_symbol
=
4924 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
4933 skip_whitespace (str
);
4935 if ((reg
= thumb_reg (&str
, THUMB_REG_ANY
)) == FAIL
)
4938 /* This sets THUMB_H2 from the top bit of reg. */
4939 inst
.instruction
|= reg
<< 3;
4941 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
4942 should cause the alignment to be checked once it is known. This is
4943 because BX PC only works if the instruction is word aligned. */
4952 thumb_mov_compare (str
, THUMB_COMPARE
);
4962 skip_whitespace (str
);
4964 if ((Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
)
4968 as_warn (_("Inserted missing '!': load/store multiple always writes back base register"));
4972 if (skip_past_comma (&str
) == FAIL
4973 || (range
= reg_list (&str
)) == FAIL
)
4976 inst
.error
= BAD_ARGS
;
4980 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
4982 /* This really doesn't seem worth it. */
4983 inst
.reloc
.type
= BFD_RELOC_NONE
;
4984 inst
.error
= _("Expression too complex");
4990 inst
.error
= _("only lo-regs valid in load/store multiple");
4994 inst
.instruction
|= (Rb
<< 8) | range
;
5002 thumb_load_store (str
, THUMB_LOAD
, THUMB_WORD
);
5009 thumb_load_store (str
, THUMB_LOAD
, THUMB_BYTE
);
5016 thumb_load_store (str
, THUMB_LOAD
, THUMB_HALFWORD
);
5025 skip_whitespace (str
);
5027 if ((Rd
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
5028 || skip_past_comma (&str
) == FAIL
5030 || (Rb
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
5031 || skip_past_comma (&str
) == FAIL
5032 || (Ro
= thumb_reg (&str
, THUMB_REG_LO
)) == FAIL
5036 inst
.error
= _("Syntax: ldrs[b] Rd, [Rb, Ro]");
5040 inst
.instruction
|= Rd
| (Rb
<< 3) | (Ro
<< 6);
5048 thumb_shift (str
, THUMB_LSL
);
5055 thumb_shift (str
, THUMB_LSR
);
5062 thumb_mov_compare (str
, THUMB_MOVE
);
5071 skip_whitespace (str
);
5073 if ((range
= reg_list (&str
)) == FAIL
)
5076 inst
.error
= BAD_ARGS
;
5080 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
5082 /* This really doesn't seem worth it. */
5083 inst
.reloc
.type
= BFD_RELOC_NONE
;
5084 inst
.error
= _("Expression too complex");
5090 if ((inst
.instruction
== T_OPCODE_PUSH
5091 && (range
& ~0xff) == 1 << REG_LR
)
5092 || (inst
.instruction
== T_OPCODE_POP
5093 && (range
& ~0xff) == 1 << REG_PC
))
5095 inst
.instruction
|= THUMB_PP_PC_LR
;
5100 inst
.error
= _("invalid register list to push/pop instruction");
5105 inst
.instruction
|= range
;
5113 thumb_load_store (str
, THUMB_STORE
, THUMB_WORD
);
5120 thumb_load_store (str
, THUMB_STORE
, THUMB_BYTE
);
5127 thumb_load_store (str
, THUMB_STORE
, THUMB_HALFWORD
);
5134 thumb_add_sub (str
, 1);
5141 skip_whitespace (str
);
5143 if (my_get_expression (&inst
.reloc
.exp
, &str
))
5146 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
5157 /* This is a pseudo-op of the form "adr rd, label" to be converted
5158 into a relative address of the form "add rd, pc, #label-.-4". */
5159 skip_whitespace (str
);
5161 /* Store Rd in temporary location inside instruction. */
5162 if ((reg
= reg_required_here (&str
, 4)) == FAIL
5163 || (reg
> 7) /* For Thumb reg must be r0..r7. */
5164 || skip_past_comma (&str
) == FAIL
5165 || my_get_expression (&inst
.reloc
.exp
, &str
))
5168 inst
.error
= BAD_ARGS
;
5172 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
5173 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
5174 inst
.reloc
.pc_rel
= 1;
5175 inst
.instruction
|= REG_PC
; /* Rd is already placed into the instruction. */
5184 int len
= strlen (reg_table
[entry
].name
) + 2;
5185 char *buf
= (char *) xmalloc (len
);
5186 char *buf2
= (char *) xmalloc (len
);
5189 #ifdef REGISTER_PREFIX
5190 buf
[i
++] = REGISTER_PREFIX
;
5193 strcpy (buf
+ i
, reg_table
[entry
].name
);
5195 for (i
= 0; buf
[i
]; i
++)
5196 buf2
[i
] = islower (buf
[i
]) ? toupper (buf
[i
]) : buf
[i
];
5200 hash_insert (arm_reg_hsh
, buf
, (PTR
) ®_table
[entry
]);
5201 hash_insert (arm_reg_hsh
, buf2
, (PTR
) ®_table
[entry
]);
5205 insert_reg_alias (str
, regnum
)
5209 struct reg_entry
*new =
5210 (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
5211 char *name
= xmalloc (strlen (str
) + 1);
5215 new->number
= regnum
;
5217 hash_insert (arm_reg_hsh
, name
, (PTR
) new);
5221 set_constant_flonums ()
5225 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5226 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
5236 if ((arm_ops_hsh
= hash_new ()) == NULL
5237 || (arm_tops_hsh
= hash_new ()) == NULL
5238 || (arm_cond_hsh
= hash_new ()) == NULL
5239 || (arm_shift_hsh
= hash_new ()) == NULL
5240 || (arm_reg_hsh
= hash_new ()) == NULL
5241 || (arm_psr_hsh
= hash_new ()) == NULL
)
5242 as_fatal (_("Virtual memory exhausted"));
5244 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
5245 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
5246 for (i
= 0; i
< sizeof (tinsns
) / sizeof (struct thumb_opcode
); i
++)
5247 hash_insert (arm_tops_hsh
, tinsns
[i
].template, (PTR
) (tinsns
+ i
));
5248 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
5249 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
5250 for (i
= 0; i
< sizeof (shift
) / sizeof (struct asm_shift
); i
++)
5251 hash_insert (arm_shift_hsh
, shift
[i
].template, (PTR
) (shift
+ i
));
5252 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
5253 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
5255 for (i
= 0; reg_table
[i
].name
; i
++)
5258 set_constant_flonums ();
5260 #if defined OBJ_COFF || defined OBJ_ELF
5262 unsigned int flags
= 0;
5264 /* Set the flags in the private structure. */
5265 if (uses_apcs_26
) flags
|= F_APCS26
;
5266 if (support_interwork
) flags
|= F_INTERWORK
;
5267 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
5268 if (pic_code
) flags
|= F_PIC
;
5269 if ((cpu_variant
& FPU_ALL
) == FPU_NONE
) flags
|= F_SOFT_FLOAT
;
5271 bfd_set_private_flags (stdoutput
, flags
);
5275 /* Record the CPU type as well. */
5276 switch (cpu_variant
& ARM_CPU_MASK
)
5279 mach
= bfd_mach_arm_2
;
5282 case ARM_3
: /* Also ARM_250. */
5283 mach
= bfd_mach_arm_2a
;
5287 case ARM_6
| ARM_3
| ARM_2
: /* Actually no CPU type defined. */
5288 mach
= bfd_mach_arm_4
;
5291 case ARM_7
: /* Also ARM_6. */
5292 mach
= bfd_mach_arm_3
;
5296 /* Catch special cases. */
5297 if (cpu_variant
!= (FPU_DEFAULT
| CPU_DEFAULT
))
5299 if (cpu_variant
& (ARM_EXT_V5
& ARM_THUMB
))
5300 mach
= bfd_mach_arm_5T
;
5301 else if (cpu_variant
& ARM_EXT_V5
)
5302 mach
= bfd_mach_arm_5
;
5303 else if (cpu_variant
& ARM_THUMB
)
5304 mach
= bfd_mach_arm_4T
;
5305 else if ((cpu_variant
& ARM_ARCH_V4
) == ARM_ARCH_V4
)
5306 mach
= bfd_mach_arm_4
;
5307 else if (cpu_variant
& ARM_LONGMUL
)
5308 mach
= bfd_mach_arm_3M
;
5311 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
5314 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
5315 for use in the a.out file, and stores them in the array pointed to by buf.
5316 This knows about the endian-ness of the target machine and does
5317 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
5318 2 (short) and 4 (long) Floating numbers are put out as a series of
5319 LITTLENUMS (shorts, here at least). */
5322 md_number_to_chars (buf
, val
, n
)
5327 if (target_big_endian
)
5328 number_to_chars_bigendian (buf
, val
, n
);
5330 number_to_chars_littleendian (buf
, val
, n
);
5334 md_chars_to_number (buf
, n
)
5339 unsigned char *where
= (unsigned char *) buf
;
5341 if (target_big_endian
)
5346 result
|= (*where
++ & 255);
5354 result
|= (where
[n
] & 255);
5361 /* Turn a string in input_line_pointer into a floating point constant
5362 of type TYPE, and store the appropriate bytes in *LITP. The number
5363 of LITTLENUMS emitted is stored in *SIZEP. An error message is
5364 returned, or NULL on OK.
5366 Note that fp constants aren't represent in the normal way on the ARM.
5367 In big endian mode, things are as expected. However, in little endian
5368 mode fp constants are big-endian word-wise, and little-endian byte-wise
5369 within the words. For example, (double) 1.1 in big endian mode is
5370 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
5371 the byte sequence 99 99 f1 3f 9a 99 99 99.
5373 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
5376 md_atof (type
, litP
, sizeP
)
5382 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5414 return _("Bad call to MD_ATOF()");
5417 t
= atof_ieee (input_line_pointer
, type
, words
);
5419 input_line_pointer
= t
;
5422 if (target_big_endian
)
5424 for (i
= 0; i
< prec
; i
++)
5426 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
5432 /* For a 4 byte float the order of elements in `words' is 1 0. For an
5433 8 byte float the order is 1 0 3 2. */
5434 for (i
= 0; i
< prec
; i
+= 2)
5436 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
5437 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
5445 /* The knowledge of the PC's pipeline offset is built into the insns
5449 md_pcrel_from (fixP
)
5453 && S_GET_SEGMENT (fixP
->fx_addsy
) == undefined_section
5454 && fixP
->fx_subsy
== NULL
)
5457 if (fixP
->fx_pcrel
&& (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_ADD
))
5459 /* PC relative addressing on the Thumb is slightly odd
5460 as the bottom two bits of the PC are forced to zero
5461 for the calculation. */
5462 return (fixP
->fx_where
+ fixP
->fx_frag
->fr_address
) & ~3;
5466 /* The pattern was adjusted to accomodate CE's off-by-one fixups,
5467 so we un-adjust here to compensate for the accomodation. */
5468 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
+ 8;
5470 return fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
5474 /* Round up a section size to the appropriate boundary. */
5477 md_section_align (segment
, size
)
5478 segT segment ATTRIBUTE_UNUSED
;
5484 /* Round all sects to multiple of 4. */
5485 return (size
+ 3) & ~3;
5489 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
5490 Otherwise we have no need to default values of symbols. */
5493 md_undefined_symbol (name
)
5494 char *name ATTRIBUTE_UNUSED
;
5497 if (name
[0] == '_' && name
[1] == 'G'
5498 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
5502 if (symbol_find (name
))
5503 as_bad ("GOT already in the symbol table");
5505 GOT_symbol
= symbol_new (name
, undefined_section
,
5506 (valueT
) 0, &zero_address_frag
);
5516 /* arm_reg_parse () := if it looks like a register, return its token and
5517 advance the pointer. */
5521 register char **ccp
;
5526 struct reg_entry
*reg
;
5528 #ifdef REGISTER_PREFIX
5529 if (*start
!= REGISTER_PREFIX
)
5534 #ifdef OPTIONAL_REGISTER_PREFIX
5535 if (*p
== OPTIONAL_REGISTER_PREFIX
)
5539 if (!isalpha (*p
) || !is_name_beginner (*p
))
5543 while (isalpha (c
) || isdigit (c
) || c
== '_')
5547 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, start
);
5560 md_apply_fix3 (fixP
, val
, seg
)
5565 offsetT value
= *val
;
5567 unsigned int newimm
;
5570 char *buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
5571 arm_fix_data
*arm_data
= (arm_fix_data
*) fixP
->tc_fix_data
;
5573 assert (fixP
->fx_r_type
< BFD_RELOC_UNUSED
);
5575 /* Note whether this will delete the relocation. */
5577 /* Patch from REarnshaw to JDavis (disabled for the moment, since it
5578 doesn't work fully.) */
5579 if ((fixP
->fx_addsy
== 0 || symbol_constant_p (fixP
->fx_addsy
))
5582 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
5586 /* If this symbol is in a different section then we need to leave it for
5587 the linker to deal with. Unfortunately, md_pcrel_from can't tell,
5588 so we have to undo it's effects here. */
5591 if (fixP
->fx_addsy
!= NULL
5592 && S_IS_DEFINED (fixP
->fx_addsy
)
5593 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
5596 && (fixP
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
5597 || fixP
->fx_r_type
== BFD_RELOC_ARM_PCREL_BLX
5601 value
+= md_pcrel_from (fixP
);
5605 /* Remember value for emit_reloc. */
5606 fixP
->fx_addnumber
= value
;
5608 switch (fixP
->fx_r_type
)
5610 case BFD_RELOC_ARM_IMMEDIATE
:
5611 newimm
= validate_immediate (value
);
5612 temp
= md_chars_to_number (buf
, INSN_SIZE
);
5614 /* If the instruction will fail, see if we can fix things up by
5615 changing the opcode. */
5616 if (newimm
== (unsigned int) FAIL
5617 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
5619 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5620 _("invalid constant (%lx) after fixup"),
5621 (unsigned long) value
);
5625 newimm
|= (temp
& 0xfffff000);
5626 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
5629 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
5631 unsigned int highpart
= 0;
5632 unsigned int newinsn
= 0xe1a00000; /* nop. */
5633 newimm
= validate_immediate (value
);
5634 temp
= md_chars_to_number (buf
, INSN_SIZE
);
5636 /* If the instruction will fail, see if we can fix things up by
5637 changing the opcode. */
5638 if (newimm
== (unsigned int) FAIL
5639 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
5641 /* No ? OK - try using two ADD instructions to generate
5643 newimm
= validate_immediate_twopart (value
, &highpart
);
5645 /* Yes - then make sure that the second instruction is
5647 if (newimm
!= (unsigned int) FAIL
)
5649 /* Still No ? Try using a negated value. */
5650 else if (validate_immediate_twopart (- value
, &highpart
) != (unsigned int) FAIL
)
5651 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
5652 /* Otherwise - give up. */
5655 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5656 _("Unable to compute ADRL instructions for PC offset of 0x%x"),
5661 /* Replace the first operand in the 2nd instruction (which
5662 is the PC) with the destination register. We have
5663 already added in the PC in the first instruction and we
5664 do not want to do it again. */
5665 newinsn
&= ~0xf0000;
5666 newinsn
|= ((newinsn
& 0x0f000) << 4);
5669 newimm
|= (temp
& 0xfffff000);
5670 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
5672 highpart
|= (newinsn
& 0xfffff000);
5673 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
5677 case BFD_RELOC_ARM_OFFSET_IMM
:
5683 if (validate_offset_imm (value
, 0) == FAIL
)
5685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5686 _("bad immediate value for offset (%ld)"),
5691 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5692 newval
&= 0xff7ff000;
5693 newval
|= value
| (sign
? INDEX_UP
: 0);
5694 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5697 case BFD_RELOC_ARM_OFFSET_IMM8
:
5698 case BFD_RELOC_ARM_HWLITERAL
:
5704 if (validate_offset_imm (value
, 1) == FAIL
)
5706 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
5707 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5708 _("invalid literal constant: pool needs to be closer"));
5710 as_bad (_("bad immediate value for half-word offset (%ld)"),
5715 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5716 newval
&= 0xff7ff0f0;
5717 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
5718 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5721 case BFD_RELOC_ARM_LITERAL
:
5727 if (validate_offset_imm (value
, 0) == FAIL
)
5729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5730 _("invalid literal constant: pool needs to be closer"));
5734 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5735 newval
&= 0xff7ff000;
5736 newval
|= value
| (sign
? INDEX_UP
: 0);
5737 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5740 case BFD_RELOC_ARM_SHIFT_IMM
:
5741 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5742 if (((unsigned long) value
) > 32
5744 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
5746 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5747 _("shift expression is too large"));
5752 /* Shifts of zero must be done as lsl. */
5754 else if (value
== 32)
5756 newval
&= 0xfffff07f;
5757 newval
|= (value
& 0x1f) << 7;
5758 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5761 case BFD_RELOC_ARM_SWI
:
5762 if (arm_data
->thumb_mode
)
5764 if (((unsigned long) value
) > 0xff)
5765 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5766 _("Invalid swi expression"));
5767 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xff00;
5769 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5773 if (((unsigned long) value
) > 0x00ffffff)
5774 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5775 _("Invalid swi expression"));
5776 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff000000;
5778 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5782 case BFD_RELOC_ARM_MULTI
:
5783 if (((unsigned long) value
) > 0xffff)
5784 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5785 _("Invalid expression in load/store multiple"));
5786 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
5787 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5790 case BFD_RELOC_ARM_PCREL_BRANCH
:
5791 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5793 /* Sign-extend a 24-bit number. */
5794 #define SEXT24(x) ((((x) & 0xffffff) ^ (~0x7fffff)) + 0x800000)
5798 value
= fixP
->fx_offset
;
5801 /* We are going to store value (shifted right by two) in the
5802 instruction, in a 24 bit, signed field. Thus we need to check
5803 that none of the top 8 bits of the shifted value (top 7 bits of
5804 the unshifted, unsigned value) are set, or that they are all set. */
5805 if ((value
& ~((offsetT
) 0x1ffffff)) != 0
5806 && ((value
& ~((offsetT
) 0x1ffffff)) != ~((offsetT
) 0x1ffffff)))
5809 /* Normally we would be stuck at this point, since we cannot store
5810 the absolute address that is the destination of the branch in the
5811 24 bits of the branch instruction. If however, we happen to know
5812 that the destination of the branch is in the same section as the
5813 branch instruciton itself, then we can compute the relocation for
5814 ourselves and not have to bother the linker with it.
5816 FIXME: The tests for OBJ_ELF and ! target_oabi are only here
5817 because I have not worked out how to do this for OBJ_COFF or
5820 && fixP
->fx_addsy
!= NULL
5821 && S_IS_DEFINED (fixP
->fx_addsy
)
5822 && S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
5824 /* Get pc relative value to go into the branch. */
5827 /* Permit a backward branch provided that enough bits
5828 are set. Allow a forwards branch, provided that
5829 enough bits are clear. */
5830 if ((value
& ~((offsetT
) 0x1ffffff)) == ~((offsetT
) 0x1ffffff)
5831 || (value
& ~((offsetT
) 0x1ffffff)) == 0)
5835 if (! fixP
->fx_done
)
5837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5838 _("gas can't handle same-section branch dest >= 0x04000000"));
5842 value
+= SEXT24 (newval
);
5844 if ((value
& ~((offsetT
) 0xffffff)) != 0
5845 && ((value
& ~((offsetT
) 0xffffff)) != ~((offsetT
) 0xffffff)))
5846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5847 _("out of range branch"));
5849 newval
= (value
& 0x00ffffff) | (newval
& 0xff000000);
5850 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5853 case BFD_RELOC_ARM_PCREL_BLX
:
5856 newval
= md_chars_to_number (buf
, INSN_SIZE
);
5860 value
= fixP
->fx_offset
;
5862 hbit
= (value
>> 1) & 1;
5863 value
= (value
>> 2) & 0x00ffffff;
5864 value
= (value
+ (newval
& 0x00ffffff)) & 0x00ffffff;
5865 newval
= value
| (newval
& 0xfe000000) | (hbit
<< 24);
5866 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5870 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
5871 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5873 addressT diff
= (newval
& 0xff) << 1;
5878 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
5879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5880 _("Branch out of range"));
5881 newval
= (newval
& 0xff00) | ((value
& 0x1ff) >> 1);
5883 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5886 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
5887 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5889 addressT diff
= (newval
& 0x7ff) << 1;
5894 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
5895 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5896 _("Branch out of range"));
5897 newval
= (newval
& 0xf800) | ((value
& 0xfff) >> 1);
5899 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5902 case BFD_RELOC_THUMB_PCREL_BLX
:
5903 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
5908 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5909 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
5910 diff
= ((newval
& 0x7ff) << 12) | ((newval2
& 0x7ff) << 1);
5911 if (diff
& 0x400000)
5914 value
= fixP
->fx_offset
;
5917 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
5918 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5919 _("Branch with link out of range"));
5921 newval
= (newval
& 0xf800) | ((value
& 0x7fffff) >> 12);
5922 newval2
= (newval2
& 0xf800) | ((value
& 0xfff) >> 1);
5923 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
5924 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
5929 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5930 md_number_to_chars (buf
, value
, 1);
5932 else if (!target_oabi
)
5934 value
= fixP
->fx_offset
;
5935 md_number_to_chars (buf
, value
, 1);
5941 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5942 md_number_to_chars (buf
, value
, 2);
5944 else if (!target_oabi
)
5946 value
= fixP
->fx_offset
;
5947 md_number_to_chars (buf
, value
, 2);
5953 case BFD_RELOC_ARM_GOT32
:
5954 case BFD_RELOC_ARM_GOTOFF
:
5955 md_number_to_chars (buf
, 0, 4);
5961 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
5962 md_number_to_chars (buf
, value
, 4);
5964 else if (!target_oabi
)
5966 value
= fixP
->fx_offset
;
5967 md_number_to_chars (buf
, value
, 4);
5973 case BFD_RELOC_ARM_PLT32
:
5974 /* It appears the instruction is fully prepared at this point. */
5978 case BFD_RELOC_ARM_GOTPC
:
5979 md_number_to_chars (buf
, value
, 4);
5982 case BFD_RELOC_ARM_CP_OFF_IMM
:
5984 if (value
< -1023 || value
> 1023 || (value
& 3))
5985 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
5986 _("Illegal value for co-processor offset"));
5989 newval
= md_chars_to_number (buf
, INSN_SIZE
) & 0xff7fff00;
5990 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
5991 md_number_to_chars (buf
, newval
, INSN_SIZE
);
5994 case BFD_RELOC_ARM_THUMB_OFFSET
:
5995 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
5996 /* Exactly what ranges, and where the offset is inserted depends
5997 on the type of instruction, we can establish this from the
5999 switch (newval
>> 12)
6001 case 4: /* PC load. */
6002 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
6003 forced to zero for these loads, so we will need to round
6004 up the offset if the instruction address is not word
6005 aligned (since the final address produced must be, and
6006 we can only describe word-aligned immediate offsets). */
6008 if ((fixP
->fx_frag
->fr_address
+ fixP
->fx_where
+ value
) & 3)
6009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6010 _("Invalid offset, target not word aligned (0x%08X)"),
6011 (unsigned int) (fixP
->fx_frag
->fr_address
6012 + fixP
->fx_where
+ value
));
6014 if ((value
+ 2) & ~0x3fe)
6015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6016 _("Invalid offset, value too big (0x%08X)"), value
);
6018 /* Round up, since pc will be rounded down. */
6019 newval
|= (value
+ 2) >> 2;
6022 case 9: /* SP load/store. */
6024 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6025 _("Invalid offset, value too big (0x%08X)"), value
);
6026 newval
|= value
>> 2;
6029 case 6: /* Word load/store. */
6031 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6032 _("Invalid offset, value too big (0x%08X)"), value
);
6033 newval
|= value
<< 4; /* 6 - 2. */
6036 case 7: /* Byte load/store. */
6038 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6039 _("Invalid offset, value too big (0x%08X)"), value
);
6040 newval
|= value
<< 6;
6043 case 8: /* Halfword load/store. */
6045 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6046 _("Invalid offset, value too big (0x%08X)"), value
);
6047 newval
|= value
<< 5; /* 6 - 1. */
6051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6052 "Unable to process relocation for thumb opcode: %lx",
6053 (unsigned long) newval
);
6056 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
6059 case BFD_RELOC_ARM_THUMB_ADD
:
6060 /* This is a complicated relocation, since we use it for all of
6061 the following immediate relocations:
6065 9bit ADD/SUB SP word-aligned
6066 10bit ADD PC/SP word-aligned
6068 The type of instruction being processed is encoded in the
6075 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
6077 int rd
= (newval
>> 4) & 0xf;
6078 int rs
= newval
& 0xf;
6079 int subtract
= newval
& 0x8000;
6084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6085 _("Invalid immediate for stack address calculation"));
6086 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
6087 newval
|= value
>> 2;
6089 else if (rs
== REG_PC
|| rs
== REG_SP
)
6093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6094 _("Invalid immediate for address calculation (value = 0x%08lX)"),
6095 (unsigned long) value
);
6096 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
6098 newval
|= value
>> 2;
6103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6104 _("Invalid 8bit immediate"));
6105 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
6106 newval
|= (rd
<< 8) | value
;
6111 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6112 _("Invalid 3bit immediate"));
6113 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
6114 newval
|= rd
| (rs
<< 3) | (value
<< 6);
6117 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
6120 case BFD_RELOC_ARM_THUMB_IMM
:
6121 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
6122 switch (newval
>> 11)
6124 case 0x04: /* 8bit immediate MOV. */
6125 case 0x05: /* 8bit immediate CMP. */
6126 if (value
< 0 || value
> 255)
6127 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6128 _("Invalid immediate: %ld is too large"),
6136 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
6139 case BFD_RELOC_ARM_THUMB_SHIFT
:
6140 /* 5bit shift value (0..31). */
6141 if (value
< 0 || value
> 31)
6142 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6143 _("Illegal Thumb shift value: %ld"), (long) value
);
6144 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf03f;
6145 newval
|= value
<< 6;
6146 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
6149 case BFD_RELOC_VTABLE_INHERIT
:
6150 case BFD_RELOC_VTABLE_ENTRY
:
6154 case BFD_RELOC_NONE
:
6156 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
6157 _("Bad relocation fixup type (%d)"), fixP
->fx_r_type
);
6163 /* Translate internal representation of relocation info to BFD target
6167 tc_gen_reloc (section
, fixp
)
6168 asection
*section ATTRIBUTE_UNUSED
;
6172 bfd_reloc_code_real_type code
;
6174 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
6176 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
6177 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
6178 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
6180 /* @@ Why fx_addnumber sometimes and fx_offset other times? */
6182 if (fixp
->fx_pcrel
== 0)
6183 reloc
->addend
= fixp
->fx_offset
;
6185 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
6187 reloc
->addend
= fixp
->fx_offset
;
6190 switch (fixp
->fx_r_type
)
6195 code
= BFD_RELOC_8_PCREL
;
6202 code
= BFD_RELOC_16_PCREL
;
6209 code
= BFD_RELOC_32_PCREL
;
6213 case BFD_RELOC_ARM_PCREL_BRANCH
:
6214 case BFD_RELOC_ARM_PCREL_BLX
:
6216 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
6217 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
6218 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
6219 case BFD_RELOC_THUMB_PCREL_BLX
:
6220 case BFD_RELOC_VTABLE_ENTRY
:
6221 case BFD_RELOC_VTABLE_INHERIT
:
6222 code
= fixp
->fx_r_type
;
6225 case BFD_RELOC_ARM_LITERAL
:
6226 case BFD_RELOC_ARM_HWLITERAL
:
6227 /* If this is called then the a literal has been referenced across
6228 a section boundary - possibly due to an implicit dump. */
6229 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6230 _("Literal referenced across section boundary (Implicit dump?)"));
6234 case BFD_RELOC_ARM_GOT32
:
6235 case BFD_RELOC_ARM_GOTOFF
:
6236 case BFD_RELOC_ARM_PLT32
:
6237 code
= fixp
->fx_r_type
;
6241 case BFD_RELOC_ARM_IMMEDIATE
:
6242 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6243 _("Internal_relocation (type %d) not fixed up (IMMEDIATE)"),
6247 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
6248 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6249 _("ADRL used for a symbol not defined in the same file"),
6253 case BFD_RELOC_ARM_OFFSET_IMM
:
6254 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6255 _("Internal_relocation (type %d) not fixed up (OFFSET_IMM)"),
6262 switch (fixp
->fx_r_type
)
6264 case BFD_RELOC_ARM_IMMEDIATE
: type
= "IMMEDIATE"; break;
6265 case BFD_RELOC_ARM_OFFSET_IMM
: type
= "OFFSET_IMM"; break;
6266 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
6267 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
6268 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
6269 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
6270 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
6271 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
6272 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
6273 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
6274 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
6275 default: type
= _("<unknown>"); break;
6277 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6278 _("Can not represent %s relocation in this object file format (%d)"),
6279 type
, fixp
->fx_pcrel
);
6285 if (code
== BFD_RELOC_32_PCREL
6287 && fixp
->fx_addsy
== GOT_symbol
)
6289 code
= BFD_RELOC_ARM_GOTPC
;
6290 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
6294 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
6296 if (reloc
->howto
== NULL
)
6298 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
6299 _("Can not represent %s relocation in this object file format"),
6300 bfd_get_reloc_code_name (code
));
6304 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
6305 vtable entry to be used in the relocation's section offset. */
6306 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
6307 reloc
->address
= fixp
->fx_offset
;
6313 md_estimate_size_before_relax (fragP
, segtype
)
6314 fragS
*fragP ATTRIBUTE_UNUSED
;
6315 segT segtype ATTRIBUTE_UNUSED
;
6317 as_fatal (_("md_estimate_size_before_relax\n"));
6322 output_inst
PARAMS ((void))
6328 as_bad (inst
.error
);
6332 to
= frag_more (inst
.size
);
6334 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
6336 assert (inst
.size
== (2 * THUMB_SIZE
));
6337 md_number_to_chars (to
, inst
.instruction
>> 16, THUMB_SIZE
);
6338 md_number_to_chars (to
+ THUMB_SIZE
, inst
.instruction
, THUMB_SIZE
);
6340 else if (inst
.size
> INSN_SIZE
)
6342 assert (inst
.size
== (2 * INSN_SIZE
));
6343 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
6344 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
6347 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
6349 if (inst
.reloc
.type
!= BFD_RELOC_NONE
)
6350 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
6351 inst
.size
, &inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
6366 /* Align the instruction.
6367 This may not be the right thing to do but... */
6371 listing_prev_line (); /* Defined in listing.h. */
6373 /* Align the previous label if needed. */
6374 if (last_label_seen
!= NULL
)
6376 symbol_set_frag (last_label_seen
, frag_now
);
6377 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
6378 S_SET_SEGMENT (last_label_seen
, now_seg
);
6381 memset (&inst
, '\0', sizeof (inst
));
6382 inst
.reloc
.type
= BFD_RELOC_NONE
;
6384 skip_whitespace (str
);
6386 /* Scan up to the end of the op-code, which must end in white space or
6388 for (start
= p
= str
; *p
!= '\0'; p
++)
6394 as_bad (_("No operator -- statement `%s'\n"), str
);
6400 CONST
struct thumb_opcode
*opcode
;
6404 opcode
= (CONST
struct thumb_opcode
*) hash_find (arm_tops_hsh
, str
);
6409 /* Check that this instruction is supported for this CPU. */
6410 if (thumb_mode
== 1 && (opcode
->variants
& cpu_variant
) == 0)
6412 as_bad (_("selected processor does not support this opcode"));
6416 inst
.instruction
= opcode
->value
;
6417 inst
.size
= opcode
->size
;
6418 (*opcode
->parms
) (p
);
6425 CONST
struct asm_opcode
*opcode
;
6426 unsigned long cond_code
;
6428 inst
.size
= INSN_SIZE
;
6429 /* P now points to the end of the opcode, probably white space, but we
6430 have to break the opcode up in case it contains condionals and flags;
6431 keep trying with progressively smaller basic instructions until one
6432 matches, or we run out of opcode. */
6433 q
= (p
- str
> LONGEST_INST
) ? str
+ LONGEST_INST
: p
;
6435 for (; q
!= str
; q
--)
6440 opcode
= (CONST
struct asm_opcode
*) hash_find (arm_ops_hsh
, str
);
6443 if (opcode
&& opcode
->template)
6445 unsigned long flag_bits
= 0;
6448 /* Check that this instruction is supported for this CPU. */
6449 if ((opcode
->variants
& cpu_variant
) == 0)
6452 inst
.instruction
= opcode
->value
;
6453 if (q
== p
) /* Just a simple opcode. */
6455 if (opcode
->comp_suffix
)
6457 if (*opcode
->comp_suffix
!= '\0')
6458 as_bad (_("Opcode `%s' must have suffix from list: <%s>"),
6459 str
, opcode
->comp_suffix
);
6461 /* Not a conditional instruction. */
6462 (*opcode
->parms
) (q
, 0);
6466 /* A conditional instruction with default condition. */
6467 inst
.instruction
|= COND_ALWAYS
;
6468 (*opcode
->parms
) (q
, 0);
6474 /* Not just a simple opcode. Check if extra is a
6479 CONST
struct asm_cond
*cond
;
6483 cond
= (CONST
struct asm_cond
*) hash_find (arm_cond_hsh
, r
);
6487 if (cond
->value
== 0xf0000000)
6488 as_tsktsk (_("Warning: Use of the 'nv' conditional is deprecated\n"));
6490 cond_code
= cond
->value
;
6494 cond_code
= COND_ALWAYS
;
6497 cond_code
= COND_ALWAYS
;
6499 /* Apply the conditional, or complain it's not allowed. */
6500 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
== '\0')
6502 /* Instruction isn't conditional. */
6503 if (cond_code
!= COND_ALWAYS
)
6505 as_bad (_("Opcode `%s' is unconditional\n"), str
);
6510 /* Instruction is conditional: set the condition into it. */
6511 inst
.instruction
|= cond_code
;
6513 /* If there is a compulsory suffix, it should come here
6514 before any optional flags. */
6515 if (opcode
->comp_suffix
&& *opcode
->comp_suffix
!= '\0')
6517 CONST
char *s
= opcode
->comp_suffix
;
6529 as_bad (_("Opcode `%s' must have suffix from <%s>\n"),
6530 str
, opcode
->comp_suffix
);
6537 /* The remainder, if any should now be flags for the instruction;
6538 Scan these checking each one found with the opcode. */
6542 CONST
struct asm_flg
*flag
= opcode
->flags
;
6551 for (flagno
= 0; flag
[flagno
].template; flagno
++)
6553 if (streq (r
, flag
[flagno
].template))
6555 flag_bits
|= flag
[flagno
].set_bits
;
6561 if (! flag
[flagno
].template)
6568 (*opcode
->parms
) (p
, flag_bits
);
6578 /* It wasn't an instruction, but it might be a register alias of the form
6581 skip_whitespace (q
);
6586 if (*q
&& !strncmp (q
, ".req ", 4))
6589 char *copy_of_str
= str
;
6593 skip_whitespace (q
);
6595 for (r
= q
; *r
!= '\0'; r
++)
6605 regnum
= arm_reg_parse (&q
);
6608 reg
= arm_reg_parse (&str
);
6613 insert_reg_alias (str
, regnum
);
6615 as_warn (_("register '%s' does not exist\n"), q
);
6617 else if (regnum
!= FAIL
)
6620 as_warn (_("ignoring redefinition of register alias '%s'"),
6623 /* Do not warn about redefinitions to the same alias. */
6626 as_warn (_("ignoring redefinition of register alias '%s' to non-existant register '%s'"),
6630 as_warn (_("ignoring incomplete .req pseuso op"));
6637 as_bad (_("bad instruction `%s'"), start
);
6641 * Invocation line includes a switch not recognized by the base assembler.
6642 * See if it's a processor-specific option. These are:
6643 * Cpu variants, the arm part is optional:
6644 * -m[arm]1 Currently not supported.
6645 * -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
6646 * -m[arm]3 Arm 3 processor
6647 * -m[arm]6[xx], Arm 6 processors
6648 * -m[arm]7[xx][t][[d]m] Arm 7 processors
6649 * -m[arm]8[10] Arm 8 processors
6650 * -m[arm]9[20][tdmi] Arm 9 processors
6651 * -mstrongarm[110[0]] StrongARM processors
6652 * -m[arm]v[2345[t]] Arm architectures
6653 * -mall All (except the ARM1)
6655 * -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
6656 * -mfpe-old (No float load/store multiples)
6657 * -mno-fpu Disable all floating point instructions
6658 * Run-time endian selection:
6659 * -EB big endian cpu
6660 * -EL little endian cpu
6661 * ARM Procedure Calling Standard:
6662 * -mapcs-32 32 bit APCS
6663 * -mapcs-26 26 bit APCS
6664 * -mapcs-float Pass floats in float regs
6665 * -mapcs-reentrant Position independent code
6666 * -mthumb-interwork Code supports Arm/Thumb interworking
6667 * -moabi Old ELF ABI
6670 CONST
char *md_shortopts
= "m:k";
6672 struct option md_longopts
[] =
6674 #ifdef ARM_BI_ENDIAN
6675 #define OPTION_EB (OPTION_MD_BASE + 0)
6676 {"EB", no_argument
, NULL
, OPTION_EB
},
6677 #define OPTION_EL (OPTION_MD_BASE + 1)
6678 {"EL", no_argument
, NULL
, OPTION_EL
},
6680 #define OPTION_OABI (OPTION_MD_BASE +2)
6681 {"oabi", no_argument
, NULL
, OPTION_OABI
},
6684 {NULL
, no_argument
, NULL
, 0}
6687 size_t md_longopts_size
= sizeof (md_longopts
);
6690 md_parse_option (c
, arg
)
6698 #ifdef ARM_BI_ENDIAN
6700 target_big_endian
= 1;
6703 target_big_endian
= 0;
6711 if (streq (str
, "fpa10"))
6712 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA10
;
6713 else if (streq (str
, "fpa11"))
6714 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_FPA11
;
6715 else if (streq (str
, "fpe-old"))
6716 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_CORE
;
6722 if (streq (str
, "no-fpu"))
6723 cpu_variant
&= ~FPU_ALL
;
6728 if (streq (str
, "oabi"))
6734 /* Limit assembler to generating only Thumb instructions: */
6735 if (streq (str
, "thumb"))
6737 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_THUMB
;
6738 cpu_variant
= (cpu_variant
& ~FPU_ALL
) | FPU_NONE
;
6741 else if (streq (str
, "thumb-interwork"))
6743 if ((cpu_variant
& ARM_THUMB
) == 0)
6744 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V4T
;
6745 #if defined OBJ_COFF || defined OBJ_ELF
6746 support_interwork
= true;
6754 if (streq (str
, "all"))
6756 cpu_variant
= ARM_ALL
| FPU_ALL
;
6759 #if defined OBJ_COFF || defined OBJ_ELF
6760 if (! strncmp (str
, "apcs-", 5))
6762 /* GCC passes on all command line options starting "-mapcs-..."
6763 to us, so we must parse them here. */
6767 if (streq (str
, "32"))
6769 uses_apcs_26
= false;
6772 else if (streq (str
, "26"))
6774 uses_apcs_26
= true;
6777 else if (streq (str
, "frame"))
6779 /* Stack frames are being generated - does not affect
6783 else if (streq (str
, "stack-check"))
6785 /* Stack checking is being performed - does not affect
6786 linkage, but does require that the functions
6787 __rt_stkovf_split_small and __rt_stkovf_split_big be
6788 present in the final link. */
6792 else if (streq (str
, "float"))
6794 /* Floating point arguments are being passed in the floating
6795 point registers. This does affect linking, since this
6796 version of the APCS is incompatible with the version that
6797 passes floating points in the integer registers. */
6799 uses_apcs_float
= true;
6802 else if (streq (str
, "reentrant"))
6804 /* Reentrant code has been generated. This does affect
6805 linking, since there is no point in linking reentrant/
6806 position independent code with absolute position code. */
6811 as_bad (_("Unrecognised APCS switch -m%s"), arg
);
6815 /* Strip off optional "arm". */
6816 if (! strncmp (str
, "arm", 3))
6822 if (streq (str
, "1"))
6823 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_1
;
6829 if (streq (str
, "2"))
6830 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
6831 else if (streq (str
, "250"))
6832 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_250
;
6838 if (streq (str
, "3"))
6839 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
6845 switch (strtol (str
, NULL
, 10))
6852 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_6
;
6860 /* Eat the processor name. */
6861 switch (strtol (str
, &str
, 10))
6874 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
6880 cpu_variant
|= (ARM_THUMB
| ARM_ARCH_V4
);
6884 cpu_variant
|= ARM_LONGMUL
;
6887 case 'f': /* fe => fp enabled cpu. */
6893 case 'c': /* Left over from 710c processor name. */
6894 case 'd': /* Debug. */
6895 case 'i': /* Embedded ICE. */
6896 /* Included for completeness in ARM processor naming. */
6906 if (streq (str
, "8") || streq (str
, "810"))
6907 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
6908 | ARM_8
| ARM_ARCH_V4
| ARM_LONGMUL
;
6914 if (streq (str
, "9"))
6915 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
6916 | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6917 else if (streq (str
, "920"))
6918 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
6919 | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
;
6920 else if (streq (str
, "920t"))
6921 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
6922 | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6923 else if (streq (str
, "9tdmi"))
6924 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
6925 | ARM_9
| ARM_ARCH_V4
| ARM_LONGMUL
| ARM_THUMB
;
6931 if (streq (str
, "strongarm")
6932 || streq (str
, "strongarm110")
6933 || streq (str
, "strongarm1100"))
6934 cpu_variant
= (cpu_variant
& ~ARM_ANY
)
6935 | ARM_8
| ARM_ARCH_V4
| ARM_LONGMUL
;
6941 /* Select variant based on architecture rather than
6949 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_3
;
6952 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_2
;
6955 as_bad (_("Invalid architecture variant -m%s"), arg
);
6961 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_7
;
6965 case 'm': cpu_variant
|= ARM_LONGMUL
; break;
6968 as_bad (_("Invalid architecture variant -m%s"), arg
);
6974 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V4
;
6978 case 't': cpu_variant
|= ARM_THUMB
; break;
6981 as_bad (_("Invalid architecture variant -m%s"), arg
);
6987 cpu_variant
= (cpu_variant
& ~ARM_ANY
) | ARM_ARCH_V5
;
6990 case 't': cpu_variant
|= ARM_THUMB
; break;
6993 as_bad (_("Invalid architecture variant -m%s"), arg
);
6999 as_bad (_("Invalid architecture variant -m%s"), arg
);
7006 as_bad (_("Invalid processor variant -m%s"), arg
);
7012 #if defined OBJ_ELF || defined OBJ_COFF
7030 ARM Specific Assembler Options:\n\
7031 -m[arm][<processor name>] select processor variant\n\
7032 -m[arm]v[2|2a|3|3m|4|4t|5[t][e]] select architecture variant\n\
7033 -mthumb only allow Thumb instructions\n\
7034 -mthumb-interwork mark the assembled code as supporting interworking\n\
7035 -mall allow any instruction\n\
7036 -mfpa10, -mfpa11 select floating point architecture\n\
7037 -mfpe-old don't allow floating-point multiple instructions\n\
7038 -mno-fpu don't allow any floating-point instructions.\n\
7039 -k generate PIC code.\n"));
7040 #if defined OBJ_COFF || defined OBJ_ELF
7042 -mapcs-32, -mapcs-26 specify which ARM Procedure Calling Standard to use\n\
7043 -mapcs-float floating point args are passed in FP regs\n\
7044 -mapcs-reentrant the code is position independent/reentrant\n"));
7048 -moabi support the old ELF ABI\n"));
7050 #ifdef ARM_BI_ENDIAN
7052 -EB assemble code for a big endian cpu\n\
7053 -EL assemble code for a little endian cpu\n"));
7057 /* We need to be able to fix up arbitrary expressions in some statements.
7058 This is so that we can handle symbols that are an arbitrary distance from
7059 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
7060 which returns part of an address in a form which will be valid for
7061 a data instruction. We do this by pushing the expression into a symbol
7062 in the expr_section, and creating a fix for that. */
7065 fix_new_arm (frag
, where
, size
, exp
, pc_rel
, reloc
)
7074 arm_fix_data
*arm_data
;
7082 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
7086 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
7091 /* Mark whether the fix is to a THUMB instruction, or an ARM
7093 arm_data
= (arm_fix_data
*) obstack_alloc (¬es
, sizeof (arm_fix_data
));
7094 new_fix
->tc_fix_data
= (PTR
) arm_data
;
7095 arm_data
->thumb_mode
= thumb_mode
;
7100 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
7103 cons_fix_new_arm (frag
, where
, size
, exp
)
7109 bfd_reloc_code_real_type type
;
7113 FIXME: @@ Should look at CPU word size. */
7120 type
= BFD_RELOC_16
;
7124 type
= BFD_RELOC_32
;
7127 type
= BFD_RELOC_64
;
7131 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
7134 /* A good place to do this, although this was probably not intended
7135 for this kind of use. We need to dump the literal pool before
7136 references are made to a null symbol pointer. */
7141 if (current_poolP
== NULL
)
7144 /* Put it at the end of text section. */
7145 subseg_set (text_section
, 0);
7147 listing_prev_line ();
7151 arm_start_line_hook ()
7153 last_label_seen
= NULL
;
7157 arm_frob_label (sym
)
7160 last_label_seen
= sym
;
7162 ARM_SET_THUMB (sym
, thumb_mode
);
7164 #if defined OBJ_COFF || defined OBJ_ELF
7165 ARM_SET_INTERWORK (sym
, support_interwork
);
7168 if (label_is_thumb_function_name
)
7170 /* When the address of a Thumb function is taken the bottom
7171 bit of that address should be set. This will allow
7172 interworking between Arm and Thumb functions to work
7175 THUMB_SET_FUNC (sym
, 1);
7177 label_is_thumb_function_name
= false;
7181 /* Adjust the symbol table. This marks Thumb symbols as distinct from
7185 arm_adjust_symtab ()
7190 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
7192 if (ARM_IS_THUMB (sym
))
7194 if (THUMB_IS_FUNC (sym
))
7196 /* Mark the symbol as a Thumb function. */
7197 if (S_GET_STORAGE_CLASS (sym
) == C_STAT
7198 /* This can happen! */
7199 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
)
7200 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
7202 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
7203 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
7205 as_bad (_("%s: unexpected function type: %d"),
7206 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
7209 switch (S_GET_STORAGE_CLASS (sym
))
7212 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
7215 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
7218 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
7226 if (ARM_IS_INTERWORK (sym
))
7227 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
7234 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
7236 if (ARM_IS_THUMB (sym
))
7238 elf_symbol_type
*elf_sym
;
7240 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
7241 bind
= ELF_ST_BIND (elf_sym
);
7243 /* If it's a .thumb_func, declare it as so,
7244 otherwise tag label as .code 16. */
7245 if (THUMB_IS_FUNC (sym
))
7246 elf_sym
->internal_elf_sym
.st_info
=
7247 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
7249 elf_sym
->internal_elf_sym
.st_info
=
7250 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
7259 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
7261 *input_line_pointer
= '/';
7262 input_line_pointer
+= 5;
7263 *input_line_pointer
= 0;
7271 arm_canonicalize_symbol_name (name
)
7276 if (thumb_mode
&& (len
= strlen (name
)) > 5
7277 && streq (name
+ len
- 5, "/data"))
7278 *(name
+ len
- 5) = 0;
7284 arm_validate_fix (fixP
)
7287 /* If the destination of the branch is a defined symbol which does not have
7288 the THUMB_FUNC attribute, then we must be calling a function which has
7289 the (interfacearm) attribute. We look for the Thumb entry point to that
7290 function and change the branch to refer to that function instead. */
7291 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
7292 && fixP
->fx_addsy
!= NULL
7293 && S_IS_DEFINED (fixP
->fx_addsy
)
7294 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
7296 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
7304 /* Relocations against Thumb function names must be left unadjusted,
7305 so that the linker can use this information to correctly set the
7306 bottom bit of their addresses. The MIPS version of this function
7307 also prevents relocations that are mips-16 specific, but I do not
7308 know why it does this.
7311 There is one other problem that ought to be addressed here, but
7312 which currently is not: Taking the address of a label (rather
7313 than a function) and then later jumping to that address. Such
7314 addresses also ought to have their bottom bit set (assuming that
7315 they reside in Thumb code), but at the moment they will not. */
7318 arm_fix_adjustable (fixP
)
7321 if (fixP
->fx_addsy
== NULL
)
7324 /* Prevent all adjustments to global symbols. */
7325 if (S_IS_EXTERN (fixP
->fx_addsy
))
7328 if (S_IS_WEAK (fixP
->fx_addsy
))
7331 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
7332 && fixP
->fx_subsy
== NULL
)
7335 /* We need the symbol name for the VTABLE entries. */
7336 if (fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
7337 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
7344 elf32_arm_target_format ()
7346 if (target_big_endian
)
7349 return "elf32-bigarm-oabi";
7351 return "elf32-bigarm";
7356 return "elf32-littlearm-oabi";
7358 return "elf32-littlearm";
7363 armelf_frob_symbol (symp
, puntp
)
7367 elf_frob_symbol (symp
, puntp
);
7371 arm_force_relocation (fixp
)
7374 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
7375 || fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
7376 || fixp
->fx_r_type
== BFD_RELOC_ARM_PCREL_BRANCH
7377 || fixp
->fx_r_type
== BFD_RELOC_ARM_PCREL_BLX
7378 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
7379 || fixp
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
)
7385 static bfd_reloc_code_real_type
7395 bfd_reloc_code_real_type reloc
;
7399 #define MAP(str,reloc) { str, sizeof (str)-1, reloc }
7400 MAP ("(got)", BFD_RELOC_ARM_GOT32
),
7401 MAP ("(gotoff)", BFD_RELOC_ARM_GOTOFF
),
7402 /* ScottB: Jan 30, 1998 - Added support for parsing "var(PLT)"
7403 branch instructions generated by GCC for PLT relocs. */
7404 MAP ("(plt)", BFD_RELOC_ARM_PLT32
),
7405 { NULL
, 0, BFD_RELOC_UNUSED
}
7409 for (i
= 0, ip
= input_line_pointer
;
7410 i
< sizeof (id
) && (isalnum (*ip
) || ispunct (*ip
));
7412 id
[i
] = tolower (*ip
);
7414 for (i
= 0; reloc_map
[i
].str
; i
++)
7415 if (strncmp (id
, reloc_map
[i
].str
, reloc_map
[i
].len
) == 0)
7418 input_line_pointer
+= reloc_map
[i
].len
;
7420 return reloc_map
[i
].reloc
;
7424 s_arm_elf_cons (nbytes
)
7429 #ifdef md_flush_pending_output
7430 md_flush_pending_output ();
7433 if (is_it_end_of_statement ())
7435 demand_empty_rest_of_line ();
7439 #ifdef md_cons_align
7440 md_cons_align (nbytes
);
7445 bfd_reloc_code_real_type reloc
;
7449 if (exp
.X_op
== O_symbol
7450 && *input_line_pointer
== '('
7451 && (reloc
= arm_parse_reloc ()) != BFD_RELOC_UNUSED
)
7453 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
7454 int size
= bfd_get_reloc_size (howto
);
7457 as_bad ("%s relocations do not fit in %d bytes",
7458 howto
->name
, nbytes
);
7461 register char *p
= frag_more ((int) nbytes
);
7462 int offset
= nbytes
- size
;
7464 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
, size
,
7469 emit_expr (&exp
, (unsigned int) nbytes
);
7471 while (*input_line_pointer
++ == ',');
7473 /* Put terminator back into stream. */
7474 input_line_pointer
--;
7475 demand_empty_rest_of_line ();
7478 #endif /* OBJ_ELF */