1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2014 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_v8
= ARM_FEATURE (ARM_EXT_V8
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
202 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
203 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
204 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
205 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
207 static const arm_feature_set arm_arch_any
= ARM_ANY
;
208 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
210 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
211 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
213 static const arm_feature_set arm_cext_iwmmxt2
=
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
215 static const arm_feature_set arm_cext_iwmmxt
=
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
217 static const arm_feature_set arm_cext_xscale
=
218 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
219 static const arm_feature_set arm_cext_maverick
=
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
221 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
222 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v1xd
=
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
225 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
226 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
227 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
228 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
229 static const arm_feature_set fpu_vfp_ext_d32
=
230 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
231 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
233 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
234 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
235 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
236 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static const arm_feature_set fpu_vfp_ext_armv8
=
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8
);
239 static const arm_feature_set fpu_neon_ext_armv8
=
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8
);
241 static const arm_feature_set fpu_crypto_ext_armv8
=
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8
);
243 static const arm_feature_set crc_ext_armv8
=
244 ARM_FEATURE (0, CRC_EXT_ARMV8
);
246 static int mfloat_abi_opt
= -1;
247 /* Record user cpu selection for object attributes. */
248 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
249 /* Must be long enough to hold any of the names in arm_cpus. */
250 static char selected_cpu_name
[16];
252 /* Return if no cpu was selected on command-line. */
254 no_cpu_selected (void)
256 return selected_cpu
.core
== arm_arch_none
.core
257 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
262 static int meabi_flags
= EABI_DEFAULT
;
264 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
267 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
272 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
277 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
278 symbolS
* GOT_symbol
;
281 /* 0: assemble for ARM,
282 1: assemble for Thumb,
283 2: assemble for Thumb even though target CPU does not support thumb
285 static int thumb_mode
= 0;
286 /* A value distinct from the possible values for thumb_mode that we
287 can use to record whether thumb_mode has been copied into the
288 tc_frag_data field of a frag. */
289 #define MODE_RECORDED (1 << 4)
291 /* Specifies the intrinsic IT insn behavior mode. */
292 enum implicit_it_mode
294 IMPLICIT_IT_MODE_NEVER
= 0x00,
295 IMPLICIT_IT_MODE_ARM
= 0x01,
296 IMPLICIT_IT_MODE_THUMB
= 0x02,
297 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
299 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
301 /* If unified_syntax is true, we are processing the new unified
302 ARM/Thumb syntax. Important differences from the old ARM mode:
304 - Immediate operands do not require a # prefix.
305 - Conditional affixes always appear at the end of the
306 instruction. (For backward compatibility, those instructions
307 that formerly had them in the middle, continue to accept them
309 - The IT instruction may appear, and if it does is validated
310 against subsequent conditional affixes. It does not generate
313 Important differences from the old Thumb mode:
315 - Immediate operands do not require a # prefix.
316 - Most of the V6T2 instructions are only available in unified mode.
317 - The .N and .W suffixes are recognized and honored (it is an error
318 if they cannot be honored).
319 - All instructions set the flags if and only if they have an 's' affix.
320 - Conditional affixes may be used. They are validated against
321 preceding IT instructions. Unlike ARM mode, you cannot use a
322 conditional affix except in the scope of an IT instruction. */
324 static bfd_boolean unified_syntax
= FALSE
;
326 /* An immediate operand can start with #, and ld*, st*, pld operands
327 can contain [ and ]. We need to tell APP not to elide whitespace
328 before a [, which can appear as the first operand for pld.
329 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
330 const char arm_symbol_chars
[] = "#[]{}";
345 enum neon_el_type type
;
349 #define NEON_MAX_TYPE_ELS 4
353 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
357 enum it_instruction_type
362 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
363 if inside, should be the last one. */
364 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
365 i.e. BKPT and NOP. */
366 IT_INSN
/* The IT insn has been parsed. */
369 /* The maximum number of operands we need. */
370 #define ARM_IT_MAX_OPERANDS 6
375 unsigned long instruction
;
379 /* "uncond_value" is set to the value in place of the conditional field in
380 unconditional versions of the instruction, or -1 if nothing is
383 struct neon_type vectype
;
384 /* This does not indicate an actual NEON instruction, only that
385 the mnemonic accepts neon-style type suffixes. */
387 /* Set to the opcode if the instruction needs relaxation.
388 Zero if the instruction is not relaxed. */
392 bfd_reloc_code_real_type type
;
397 enum it_instruction_type it_insn_type
;
403 struct neon_type_el vectype
;
404 unsigned present
: 1; /* Operand present. */
405 unsigned isreg
: 1; /* Operand was a register. */
406 unsigned immisreg
: 1; /* .imm field is a second register. */
407 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
408 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
409 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
410 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
411 instructions. This allows us to disambiguate ARM <-> vector insns. */
412 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
413 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
414 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
415 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
416 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
417 unsigned writeback
: 1; /* Operand has trailing ! */
418 unsigned preind
: 1; /* Preindexed address. */
419 unsigned postind
: 1; /* Postindexed address. */
420 unsigned negative
: 1; /* Index register was negated. */
421 unsigned shifted
: 1; /* Shift applied to operation. */
422 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
423 } operands
[ARM_IT_MAX_OPERANDS
];
426 static struct arm_it inst
;
428 #define NUM_FLOAT_VALS 8
430 const char * fp_const
[] =
432 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
435 /* Number of littlenums required to hold an extended precision number. */
436 #define MAX_LITTLENUMS 6
438 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
448 #define CP_T_X 0x00008000
449 #define CP_T_Y 0x00400000
451 #define CONDS_BIT 0x00100000
452 #define LOAD_BIT 0x00100000
454 #define DOUBLE_LOAD_FLAG 0x00000001
458 const char * template_name
;
462 #define COND_ALWAYS 0xE
466 const char * template_name
;
470 struct asm_barrier_opt
472 const char * template_name
;
474 const arm_feature_set arch
;
477 /* The bit that distinguishes CPSR and SPSR. */
478 #define SPSR_BIT (1 << 22)
480 /* The individual PSR flag bits. */
481 #define PSR_c (1 << 16)
482 #define PSR_x (1 << 17)
483 #define PSR_s (1 << 18)
484 #define PSR_f (1 << 19)
489 bfd_reloc_code_real_type reloc
;
494 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
495 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
500 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
503 /* Bits for DEFINED field in neon_typed_alias. */
504 #define NTA_HASTYPE 1
505 #define NTA_HASINDEX 2
507 struct neon_typed_alias
509 unsigned char defined
;
511 struct neon_type_el eltype
;
514 /* ARM register categories. This includes coprocessor numbers and various
515 architecture extensions' registers. */
542 /* Structure for a hash table entry for a register.
543 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
544 information which states whether a vector type or index is specified (for a
545 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
551 unsigned char builtin
;
552 struct neon_typed_alias
* neon
;
555 /* Diagnostics used when we don't get a register of the expected type. */
556 const char * const reg_expected_msgs
[] =
558 N_("ARM register expected"),
559 N_("bad or missing co-processor number"),
560 N_("co-processor register expected"),
561 N_("FPA register expected"),
562 N_("VFP single precision register expected"),
563 N_("VFP/Neon double precision register expected"),
564 N_("Neon quad precision register expected"),
565 N_("VFP single or double precision register expected"),
566 N_("Neon double or quad precision register expected"),
567 N_("VFP single, double or Neon quad precision register expected"),
568 N_("VFP system register expected"),
569 N_("Maverick MVF register expected"),
570 N_("Maverick MVD register expected"),
571 N_("Maverick MVFX register expected"),
572 N_("Maverick MVDX register expected"),
573 N_("Maverick MVAX register expected"),
574 N_("Maverick DSPSC register expected"),
575 N_("iWMMXt data register expected"),
576 N_("iWMMXt control register expected"),
577 N_("iWMMXt scalar register expected"),
578 N_("XScale accumulator register expected"),
581 /* Some well known registers that we refer to directly elsewhere. */
587 /* ARM instructions take 4bytes in the object file, Thumb instructions
593 /* Basic string to match. */
594 const char * template_name
;
596 /* Parameters to instruction. */
597 unsigned int operands
[8];
599 /* Conditional tag - see opcode_lookup. */
600 unsigned int tag
: 4;
602 /* Basic instruction code. */
603 unsigned int avalue
: 28;
605 /* Thumb-format instruction code. */
608 /* Which architecture variant provides this instruction. */
609 const arm_feature_set
* avariant
;
610 const arm_feature_set
* tvariant
;
612 /* Function to call to encode instruction in ARM format. */
613 void (* aencode
) (void);
615 /* Function to call to encode instruction in Thumb format. */
616 void (* tencode
) (void);
619 /* Defines for various bits that we will want to toggle. */
620 #define INST_IMMEDIATE 0x02000000
621 #define OFFSET_REG 0x02000000
622 #define HWOFFSET_IMM 0x00400000
623 #define SHIFT_BY_REG 0x00000010
624 #define PRE_INDEX 0x01000000
625 #define INDEX_UP 0x00800000
626 #define WRITE_BACK 0x00200000
627 #define LDM_TYPE_2_OR_3 0x00400000
628 #define CPSI_MMOD 0x00020000
630 #define LITERAL_MASK 0xf000f000
631 #define OPCODE_MASK 0xfe1fffff
632 #define V4_STR_BIT 0x00000020
634 #define T2_SUBS_PC_LR 0xf3de8f00
636 #define DATA_OP_SHIFT 21
638 #define T2_OPCODE_MASK 0xfe1fffff
639 #define T2_DATA_OP_SHIFT 21
641 #define A_COND_MASK 0xf0000000
642 #define A_PUSH_POP_OP_MASK 0x0fff0000
644 /* Opcodes for pushing/poping registers to/from the stack. */
645 #define A1_OPCODE_PUSH 0x092d0000
646 #define A2_OPCODE_PUSH 0x052d0004
647 #define A2_OPCODE_POP 0x049d0004
649 /* Codes to distinguish the arithmetic instructions. */
660 #define OPCODE_CMP 10
661 #define OPCODE_CMN 11
662 #define OPCODE_ORR 12
663 #define OPCODE_MOV 13
664 #define OPCODE_BIC 14
665 #define OPCODE_MVN 15
667 #define T2_OPCODE_AND 0
668 #define T2_OPCODE_BIC 1
669 #define T2_OPCODE_ORR 2
670 #define T2_OPCODE_ORN 3
671 #define T2_OPCODE_EOR 4
672 #define T2_OPCODE_ADD 8
673 #define T2_OPCODE_ADC 10
674 #define T2_OPCODE_SBC 11
675 #define T2_OPCODE_SUB 13
676 #define T2_OPCODE_RSB 14
678 #define T_OPCODE_MUL 0x4340
679 #define T_OPCODE_TST 0x4200
680 #define T_OPCODE_CMN 0x42c0
681 #define T_OPCODE_NEG 0x4240
682 #define T_OPCODE_MVN 0x43c0
684 #define T_OPCODE_ADD_R3 0x1800
685 #define T_OPCODE_SUB_R3 0x1a00
686 #define T_OPCODE_ADD_HI 0x4400
687 #define T_OPCODE_ADD_ST 0xb000
688 #define T_OPCODE_SUB_ST 0xb080
689 #define T_OPCODE_ADD_SP 0xa800
690 #define T_OPCODE_ADD_PC 0xa000
691 #define T_OPCODE_ADD_I8 0x3000
692 #define T_OPCODE_SUB_I8 0x3800
693 #define T_OPCODE_ADD_I3 0x1c00
694 #define T_OPCODE_SUB_I3 0x1e00
696 #define T_OPCODE_ASR_R 0x4100
697 #define T_OPCODE_LSL_R 0x4080
698 #define T_OPCODE_LSR_R 0x40c0
699 #define T_OPCODE_ROR_R 0x41c0
700 #define T_OPCODE_ASR_I 0x1000
701 #define T_OPCODE_LSL_I 0x0000
702 #define T_OPCODE_LSR_I 0x0800
704 #define T_OPCODE_MOV_I8 0x2000
705 #define T_OPCODE_CMP_I8 0x2800
706 #define T_OPCODE_CMP_LR 0x4280
707 #define T_OPCODE_MOV_HR 0x4600
708 #define T_OPCODE_CMP_HR 0x4500
710 #define T_OPCODE_LDR_PC 0x4800
711 #define T_OPCODE_LDR_SP 0x9800
712 #define T_OPCODE_STR_SP 0x9000
713 #define T_OPCODE_LDR_IW 0x6800
714 #define T_OPCODE_STR_IW 0x6000
715 #define T_OPCODE_LDR_IH 0x8800
716 #define T_OPCODE_STR_IH 0x8000
717 #define T_OPCODE_LDR_IB 0x7800
718 #define T_OPCODE_STR_IB 0x7000
719 #define T_OPCODE_LDR_RW 0x5800
720 #define T_OPCODE_STR_RW 0x5000
721 #define T_OPCODE_LDR_RH 0x5a00
722 #define T_OPCODE_STR_RH 0x5200
723 #define T_OPCODE_LDR_RB 0x5c00
724 #define T_OPCODE_STR_RB 0x5400
726 #define T_OPCODE_PUSH 0xb400
727 #define T_OPCODE_POP 0xbc00
729 #define T_OPCODE_BRANCH 0xe000
731 #define THUMB_SIZE 2 /* Size of thumb instruction. */
732 #define THUMB_PP_PC_LR 0x0100
733 #define THUMB_LOAD_BIT 0x0800
734 #define THUMB2_LOAD_BIT 0x00100000
736 #define BAD_ARGS _("bad arguments to instruction")
737 #define BAD_SP _("r13 not allowed here")
738 #define BAD_PC _("r15 not allowed here")
739 #define BAD_COND _("instruction cannot be conditional")
740 #define BAD_OVERLAP _("registers may not be the same")
741 #define BAD_HIREG _("lo register required")
742 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
743 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
744 #define BAD_BRANCH _("branch must be last instruction in IT block")
745 #define BAD_NOT_IT _("instruction not allowed in IT block")
746 #define BAD_FPU _("selected FPU does not support instruction")
747 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
748 #define BAD_IT_COND _("incorrect condition in IT block")
749 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
750 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
751 #define BAD_PC_ADDRESSING \
752 _("cannot use register index with PC-relative addressing")
753 #define BAD_PC_WRITEBACK \
754 _("cannot use writeback with PC-relative addressing")
755 #define BAD_RANGE _("branch out of range")
756 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
758 static struct hash_control
* arm_ops_hsh
;
759 static struct hash_control
* arm_cond_hsh
;
760 static struct hash_control
* arm_shift_hsh
;
761 static struct hash_control
* arm_psr_hsh
;
762 static struct hash_control
* arm_v7m_psr_hsh
;
763 static struct hash_control
* arm_reg_hsh
;
764 static struct hash_control
* arm_reloc_hsh
;
765 static struct hash_control
* arm_barrier_opt_hsh
;
767 /* Stuff needed to resolve the label ambiguity
776 symbolS
* last_label_seen
;
777 static int label_is_thumb_function_name
= FALSE
;
779 /* Literal pool structure. Held on a per-section
780 and per-sub-section basis. */
782 #define MAX_LITERAL_POOL_SIZE 1024
783 typedef struct literal_pool
785 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
786 unsigned int next_free_entry
;
792 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
794 struct literal_pool
* next
;
797 /* Pointer to a linked list of literal pools. */
798 literal_pool
* list_of_pools
= NULL
;
800 typedef enum asmfunc_states
803 WAITING_ASMFUNC_NAME
,
807 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
810 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
812 static struct current_it now_it
;
816 now_it_compatible (int cond
)
818 return (cond
& ~1) == (now_it
.cc
& ~1);
822 conditional_insn (void)
824 return inst
.cond
!= COND_ALWAYS
;
827 static int in_it_block (void);
829 static int handle_it_state (void);
831 static void force_automatic_it_block_close (void);
833 static void it_fsm_post_encode (void);
835 #define set_it_insn_type(type) \
838 inst.it_insn_type = type; \
839 if (handle_it_state () == FAIL) \
844 #define set_it_insn_type_nonvoid(type, failret) \
847 inst.it_insn_type = type; \
848 if (handle_it_state () == FAIL) \
853 #define set_it_insn_type_last() \
856 if (inst.cond == COND_ALWAYS) \
857 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
859 set_it_insn_type (INSIDE_IT_LAST_INSN); \
865 /* This array holds the chars that always start a comment. If the
866 pre-processor is disabled, these aren't very useful. */
867 char arm_comment_chars
[] = "@";
869 /* This array holds the chars that only start a comment at the beginning of
870 a line. If the line seems to have the form '# 123 filename'
871 .line and .file directives will appear in the pre-processed output. */
872 /* Note that input_file.c hand checks for '#' at the beginning of the
873 first line of the input file. This is because the compiler outputs
874 #NO_APP at the beginning of its output. */
875 /* Also note that comments like this one will always work. */
876 const char line_comment_chars
[] = "#";
878 char arm_line_separator_chars
[] = ";";
880 /* Chars that can be used to separate mant
881 from exp in floating point numbers. */
882 const char EXP_CHARS
[] = "eE";
884 /* Chars that mean this number is a floating point constant. */
888 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
890 /* Prefix characters that indicate the start of an immediate
892 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
894 /* Separator character handling. */
896 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
899 skip_past_char (char ** str
, char c
)
901 /* PR gas/14987: Allow for whitespace before the expected character. */
902 skip_whitespace (*str
);
913 #define skip_past_comma(str) skip_past_char (str, ',')
915 /* Arithmetic expressions (possibly involving symbols). */
917 /* Return TRUE if anything in the expression is a bignum. */
920 walk_no_bignums (symbolS
* sp
)
922 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
925 if (symbol_get_value_expression (sp
)->X_add_symbol
)
927 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
928 || (symbol_get_value_expression (sp
)->X_op_symbol
929 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
935 static int in_my_get_expression
= 0;
937 /* Third argument to my_get_expression. */
938 #define GE_NO_PREFIX 0
939 #define GE_IMM_PREFIX 1
940 #define GE_OPT_PREFIX 2
941 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
942 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
943 #define GE_OPT_PREFIX_BIG 3
946 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
951 /* In unified syntax, all prefixes are optional. */
953 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
958 case GE_NO_PREFIX
: break;
960 if (!is_immediate_prefix (**str
))
962 inst
.error
= _("immediate expression requires a # prefix");
968 case GE_OPT_PREFIX_BIG
:
969 if (is_immediate_prefix (**str
))
975 memset (ep
, 0, sizeof (expressionS
));
977 save_in
= input_line_pointer
;
978 input_line_pointer
= *str
;
979 in_my_get_expression
= 1;
980 seg
= expression (ep
);
981 in_my_get_expression
= 0;
983 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
985 /* We found a bad or missing expression in md_operand(). */
986 *str
= input_line_pointer
;
987 input_line_pointer
= save_in
;
988 if (inst
.error
== NULL
)
989 inst
.error
= (ep
->X_op
== O_absent
990 ? _("missing expression") :_("bad expression"));
995 if (seg
!= absolute_section
996 && seg
!= text_section
997 && seg
!= data_section
998 && seg
!= bss_section
999 && seg
!= undefined_section
)
1001 inst
.error
= _("bad segment");
1002 *str
= input_line_pointer
;
1003 input_line_pointer
= save_in
;
1010 /* Get rid of any bignums now, so that we don't generate an error for which
1011 we can't establish a line number later on. Big numbers are never valid
1012 in instructions, which is where this routine is always called. */
1013 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1014 && (ep
->X_op
== O_big
1015 || (ep
->X_add_symbol
1016 && (walk_no_bignums (ep
->X_add_symbol
)
1018 && walk_no_bignums (ep
->X_op_symbol
))))))
1020 inst
.error
= _("invalid constant");
1021 *str
= input_line_pointer
;
1022 input_line_pointer
= save_in
;
1026 *str
= input_line_pointer
;
1027 input_line_pointer
= save_in
;
1031 /* Turn a string in input_line_pointer into a floating point constant
1032 of type TYPE, and store the appropriate bytes in *LITP. The number
1033 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1034 returned, or NULL on OK.
1036 Note that fp constants aren't represent in the normal way on the ARM.
1037 In big endian mode, things are as expected. However, in little endian
1038 mode fp constants are big-endian word-wise, and little-endian byte-wise
1039 within the words. For example, (double) 1.1 in big endian mode is
1040 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1041 the byte sequence 99 99 f1 3f 9a 99 99 99.
1043 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1046 md_atof (int type
, char * litP
, int * sizeP
)
1049 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1081 return _("Unrecognized or unsupported floating point constant");
1084 t
= atof_ieee (input_line_pointer
, type
, words
);
1086 input_line_pointer
= t
;
1087 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1089 if (target_big_endian
)
1091 for (i
= 0; i
< prec
; i
++)
1093 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1094 litP
+= sizeof (LITTLENUM_TYPE
);
1099 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1100 for (i
= prec
- 1; i
>= 0; i
--)
1102 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1103 litP
+= sizeof (LITTLENUM_TYPE
);
1106 /* For a 4 byte float the order of elements in `words' is 1 0.
1107 For an 8 byte float the order is 1 0 3 2. */
1108 for (i
= 0; i
< prec
; i
+= 2)
1110 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1111 sizeof (LITTLENUM_TYPE
));
1112 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1113 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1114 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1121 /* We handle all bad expressions here, so that we can report the faulty
1122 instruction in the error message. */
1124 md_operand (expressionS
* exp
)
1126 if (in_my_get_expression
)
1127 exp
->X_op
= O_illegal
;
1130 /* Immediate values. */
1132 /* Generic immediate-value read function for use in directives.
1133 Accepts anything that 'expression' can fold to a constant.
1134 *val receives the number. */
1137 immediate_for_directive (int *val
)
1140 exp
.X_op
= O_illegal
;
1142 if (is_immediate_prefix (*input_line_pointer
))
1144 input_line_pointer
++;
1148 if (exp
.X_op
!= O_constant
)
1150 as_bad (_("expected #constant"));
1151 ignore_rest_of_line ();
1154 *val
= exp
.X_add_number
;
1159 /* Register parsing. */
1161 /* Generic register parser. CCP points to what should be the
1162 beginning of a register name. If it is indeed a valid register
1163 name, advance CCP over it and return the reg_entry structure;
1164 otherwise return NULL. Does not issue diagnostics. */
1166 static struct reg_entry
*
1167 arm_reg_parse_multi (char **ccp
)
1171 struct reg_entry
*reg
;
1173 skip_whitespace (start
);
1175 #ifdef REGISTER_PREFIX
1176 if (*start
!= REGISTER_PREFIX
)
1180 #ifdef OPTIONAL_REGISTER_PREFIX
1181 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1186 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1191 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1193 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1203 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1204 enum arm_reg_type type
)
1206 /* Alternative syntaxes are accepted for a few register classes. */
1213 /* Generic coprocessor register names are allowed for these. */
1214 if (reg
&& reg
->type
== REG_TYPE_CN
)
1219 /* For backward compatibility, a bare number is valid here. */
1221 unsigned long processor
= strtoul (start
, ccp
, 10);
1222 if (*ccp
!= start
&& processor
<= 15)
1226 case REG_TYPE_MMXWC
:
1227 /* WC includes WCG. ??? I'm not sure this is true for all
1228 instructions that take WC registers. */
1229 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1240 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1241 return value is the register number or FAIL. */
1244 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1247 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1250 /* Do not allow a scalar (reg+index) to parse as a register. */
1251 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1254 if (reg
&& reg
->type
== type
)
1257 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1264 /* Parse a Neon type specifier. *STR should point at the leading '.'
1265 character. Does no verification at this stage that the type fits the opcode
1272 Can all be legally parsed by this function.
1274 Fills in neon_type struct pointer with parsed information, and updates STR
1275 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1276 type, FAIL if not. */
1279 parse_neon_type (struct neon_type
*type
, char **str
)
1286 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1288 enum neon_el_type thistype
= NT_untyped
;
1289 unsigned thissize
= -1u;
1296 /* Just a size without an explicit type. */
1300 switch (TOLOWER (*ptr
))
1302 case 'i': thistype
= NT_integer
; break;
1303 case 'f': thistype
= NT_float
; break;
1304 case 'p': thistype
= NT_poly
; break;
1305 case 's': thistype
= NT_signed
; break;
1306 case 'u': thistype
= NT_unsigned
; break;
1308 thistype
= NT_float
;
1313 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1319 /* .f is an abbreviation for .f32. */
1320 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1325 thissize
= strtoul (ptr
, &ptr
, 10);
1327 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1330 as_bad (_("bad size %d in type specifier"), thissize
);
1338 type
->el
[type
->elems
].type
= thistype
;
1339 type
->el
[type
->elems
].size
= thissize
;
1344 /* Empty/missing type is not a successful parse. */
1345 if (type
->elems
== 0)
1353 /* Errors may be set multiple times during parsing or bit encoding
1354 (particularly in the Neon bits), but usually the earliest error which is set
1355 will be the most meaningful. Avoid overwriting it with later (cascading)
1356 errors by calling this function. */
1359 first_error (const char *err
)
1365 /* Parse a single type, e.g. ".s32", leading period included. */
1367 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1370 struct neon_type optype
;
1374 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1376 if (optype
.elems
== 1)
1377 *vectype
= optype
.el
[0];
1380 first_error (_("only one type should be specified for operand"));
1386 first_error (_("vector type expected"));
1398 /* Special meanings for indices (which have a range of 0-7), which will fit into
1401 #define NEON_ALL_LANES 15
1402 #define NEON_INTERLEAVE_LANES 14
1404 /* Parse either a register or a scalar, with an optional type. Return the
1405 register number, and optionally fill in the actual type of the register
1406 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1407 type/index information in *TYPEINFO. */
1410 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1411 enum arm_reg_type
*rtype
,
1412 struct neon_typed_alias
*typeinfo
)
1415 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1416 struct neon_typed_alias atype
;
1417 struct neon_type_el parsetype
;
1421 atype
.eltype
.type
= NT_invtype
;
1422 atype
.eltype
.size
= -1;
1424 /* Try alternate syntax for some types of register. Note these are mutually
1425 exclusive with the Neon syntax extensions. */
1428 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1436 /* Undo polymorphism when a set of register types may be accepted. */
1437 if ((type
== REG_TYPE_NDQ
1438 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1439 || (type
== REG_TYPE_VFSD
1440 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1441 || (type
== REG_TYPE_NSDQ
1442 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1443 || reg
->type
== REG_TYPE_NQ
))
1444 || (type
== REG_TYPE_MMXWC
1445 && (reg
->type
== REG_TYPE_MMXWCG
)))
1446 type
= (enum arm_reg_type
) reg
->type
;
1448 if (type
!= reg
->type
)
1454 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1456 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1458 first_error (_("can't redefine type for operand"));
1461 atype
.defined
|= NTA_HASTYPE
;
1462 atype
.eltype
= parsetype
;
1465 if (skip_past_char (&str
, '[') == SUCCESS
)
1467 if (type
!= REG_TYPE_VFD
)
1469 first_error (_("only D registers may be indexed"));
1473 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1475 first_error (_("can't change index for operand"));
1479 atype
.defined
|= NTA_HASINDEX
;
1481 if (skip_past_char (&str
, ']') == SUCCESS
)
1482 atype
.index
= NEON_ALL_LANES
;
1487 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1489 if (exp
.X_op
!= O_constant
)
1491 first_error (_("constant expression required"));
1495 if (skip_past_char (&str
, ']') == FAIL
)
1498 atype
.index
= exp
.X_add_number
;
1513 /* Like arm_reg_parse, but allow allow the following extra features:
1514 - If RTYPE is non-zero, return the (possibly restricted) type of the
1515 register (e.g. Neon double or quad reg when either has been requested).
1516 - If this is a Neon vector type with additional type information, fill
1517 in the struct pointed to by VECTYPE (if non-NULL).
1518 This function will fault on encountering a scalar. */
1521 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1522 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1524 struct neon_typed_alias atype
;
1526 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1531 /* Do not allow regname(... to parse as a register. */
1535 /* Do not allow a scalar (reg+index) to parse as a register. */
1536 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1538 first_error (_("register operand expected, but got scalar"));
1543 *vectype
= atype
.eltype
;
1550 #define NEON_SCALAR_REG(X) ((X) >> 4)
1551 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1553 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1554 have enough information to be able to do a good job bounds-checking. So, we
1555 just do easy checks here, and do further checks later. */
1558 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1562 struct neon_typed_alias atype
;
1564 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1566 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1569 if (atype
.index
== NEON_ALL_LANES
)
1571 first_error (_("scalar must have an index"));
1574 else if (atype
.index
>= 64 / elsize
)
1576 first_error (_("scalar index out of range"));
1581 *type
= atype
.eltype
;
1585 return reg
* 16 + atype
.index
;
1588 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1591 parse_reg_list (char ** strp
)
1593 char * str
= * strp
;
1597 /* We come back here if we get ranges concatenated by '+' or '|'. */
1600 skip_whitespace (str
);
1614 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1616 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1626 first_error (_("bad range in register list"));
1630 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1632 if (range
& (1 << i
))
1634 (_("Warning: duplicated register (r%d) in register list"),
1642 if (range
& (1 << reg
))
1643 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1645 else if (reg
<= cur_reg
)
1646 as_tsktsk (_("Warning: register range not in ascending order"));
1651 while (skip_past_comma (&str
) != FAIL
1652 || (in_range
= 1, *str
++ == '-'));
1655 if (skip_past_char (&str
, '}') == FAIL
)
1657 first_error (_("missing `}'"));
1665 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1668 if (exp
.X_op
== O_constant
)
1670 if (exp
.X_add_number
1671 != (exp
.X_add_number
& 0x0000ffff))
1673 inst
.error
= _("invalid register mask");
1677 if ((range
& exp
.X_add_number
) != 0)
1679 int regno
= range
& exp
.X_add_number
;
1682 regno
= (1 << regno
) - 1;
1684 (_("Warning: duplicated register (r%d) in register list"),
1688 range
|= exp
.X_add_number
;
1692 if (inst
.reloc
.type
!= 0)
1694 inst
.error
= _("expression too complex");
1698 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1699 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1700 inst
.reloc
.pc_rel
= 0;
1704 if (*str
== '|' || *str
== '+')
1710 while (another_range
);
1716 /* Types of registers in a list. */
1725 /* Parse a VFP register list. If the string is invalid return FAIL.
1726 Otherwise return the number of registers, and set PBASE to the first
1727 register. Parses registers of type ETYPE.
1728 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1729 - Q registers can be used to specify pairs of D registers
1730 - { } can be omitted from around a singleton register list
1731 FIXME: This is not implemented, as it would require backtracking in
1734 This could be done (the meaning isn't really ambiguous), but doesn't
1735 fit in well with the current parsing framework.
1736 - 32 D registers may be used (also true for VFPv3).
1737 FIXME: Types are ignored in these register lists, which is probably a
1741 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1746 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1750 unsigned long mask
= 0;
1753 if (skip_past_char (&str
, '{') == FAIL
)
1755 inst
.error
= _("expecting {");
1762 regtype
= REG_TYPE_VFS
;
1767 regtype
= REG_TYPE_VFD
;
1770 case REGLIST_NEON_D
:
1771 regtype
= REG_TYPE_NDQ
;
1775 if (etype
!= REGLIST_VFP_S
)
1777 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1778 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1782 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1785 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1792 base_reg
= max_regs
;
1796 int setmask
= 1, addregs
= 1;
1798 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1800 if (new_base
== FAIL
)
1802 first_error (_(reg_expected_msgs
[regtype
]));
1806 if (new_base
>= max_regs
)
1808 first_error (_("register out of range in list"));
1812 /* Note: a value of 2 * n is returned for the register Q<n>. */
1813 if (regtype
== REG_TYPE_NQ
)
1819 if (new_base
< base_reg
)
1820 base_reg
= new_base
;
1822 if (mask
& (setmask
<< new_base
))
1824 first_error (_("invalid register list"));
1828 if ((mask
>> new_base
) != 0 && ! warned
)
1830 as_tsktsk (_("register list not in ascending order"));
1834 mask
|= setmask
<< new_base
;
1837 if (*str
== '-') /* We have the start of a range expression */
1843 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1846 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1850 if (high_range
>= max_regs
)
1852 first_error (_("register out of range in list"));
1856 if (regtype
== REG_TYPE_NQ
)
1857 high_range
= high_range
+ 1;
1859 if (high_range
<= new_base
)
1861 inst
.error
= _("register range not in ascending order");
1865 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1867 if (mask
& (setmask
<< new_base
))
1869 inst
.error
= _("invalid register list");
1873 mask
|= setmask
<< new_base
;
1878 while (skip_past_comma (&str
) != FAIL
);
1882 /* Sanity check -- should have raised a parse error above. */
1883 if (count
== 0 || count
> max_regs
)
1888 /* Final test -- the registers must be consecutive. */
1890 for (i
= 0; i
< count
; i
++)
1892 if ((mask
& (1u << i
)) == 0)
1894 inst
.error
= _("non-contiguous register range");
1904 /* True if two alias types are the same. */
1907 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1915 if (a
->defined
!= b
->defined
)
1918 if ((a
->defined
& NTA_HASTYPE
) != 0
1919 && (a
->eltype
.type
!= b
->eltype
.type
1920 || a
->eltype
.size
!= b
->eltype
.size
))
1923 if ((a
->defined
& NTA_HASINDEX
) != 0
1924 && (a
->index
!= b
->index
))
1930 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1931 The base register is put in *PBASE.
1932 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1934 The register stride (minus one) is put in bit 4 of the return value.
1935 Bits [6:5] encode the list length (minus one).
1936 The type of the list elements is put in *ELTYPE, if non-NULL. */
1938 #define NEON_LANE(X) ((X) & 0xf)
1939 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1940 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1943 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1944 struct neon_type_el
*eltype
)
1951 int leading_brace
= 0;
1952 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1953 const char *const incr_error
= _("register stride must be 1 or 2");
1954 const char *const type_error
= _("mismatched element/structure types in list");
1955 struct neon_typed_alias firsttype
;
1957 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1962 struct neon_typed_alias atype
;
1963 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1967 first_error (_(reg_expected_msgs
[rtype
]));
1974 if (rtype
== REG_TYPE_NQ
)
1980 else if (reg_incr
== -1)
1982 reg_incr
= getreg
- base_reg
;
1983 if (reg_incr
< 1 || reg_incr
> 2)
1985 first_error (_(incr_error
));
1989 else if (getreg
!= base_reg
+ reg_incr
* count
)
1991 first_error (_(incr_error
));
1995 if (! neon_alias_types_same (&atype
, &firsttype
))
1997 first_error (_(type_error
));
2001 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2005 struct neon_typed_alias htype
;
2006 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2008 lane
= NEON_INTERLEAVE_LANES
;
2009 else if (lane
!= NEON_INTERLEAVE_LANES
)
2011 first_error (_(type_error
));
2016 else if (reg_incr
!= 1)
2018 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2022 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2025 first_error (_(reg_expected_msgs
[rtype
]));
2028 if (! neon_alias_types_same (&htype
, &firsttype
))
2030 first_error (_(type_error
));
2033 count
+= hireg
+ dregs
- getreg
;
2037 /* If we're using Q registers, we can't use [] or [n] syntax. */
2038 if (rtype
== REG_TYPE_NQ
)
2044 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2048 else if (lane
!= atype
.index
)
2050 first_error (_(type_error
));
2054 else if (lane
== -1)
2055 lane
= NEON_INTERLEAVE_LANES
;
2056 else if (lane
!= NEON_INTERLEAVE_LANES
)
2058 first_error (_(type_error
));
2063 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2065 /* No lane set by [x]. We must be interleaving structures. */
2067 lane
= NEON_INTERLEAVE_LANES
;
2070 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2071 || (count
> 1 && reg_incr
== -1))
2073 first_error (_("error parsing element/structure list"));
2077 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2079 first_error (_("expected }"));
2087 *eltype
= firsttype
.eltype
;
2092 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2095 /* Parse an explicit relocation suffix on an expression. This is
2096 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2097 arm_reloc_hsh contains no entries, so this function can only
2098 succeed if there is no () after the word. Returns -1 on error,
2099 BFD_RELOC_UNUSED if there wasn't any suffix. */
2102 parse_reloc (char **str
)
2104 struct reloc_entry
*r
;
2108 return BFD_RELOC_UNUSED
;
2113 while (*q
&& *q
!= ')' && *q
!= ',')
2118 if ((r
= (struct reloc_entry
*)
2119 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2126 /* Directives: register aliases. */
2128 static struct reg_entry
*
2129 insert_reg_alias (char *str
, unsigned number
, int type
)
2131 struct reg_entry
*new_reg
;
2134 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2136 if (new_reg
->builtin
)
2137 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2139 /* Only warn about a redefinition if it's not defined as the
2141 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2142 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2147 name
= xstrdup (str
);
2148 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2150 new_reg
->name
= name
;
2151 new_reg
->number
= number
;
2152 new_reg
->type
= type
;
2153 new_reg
->builtin
= FALSE
;
2154 new_reg
->neon
= NULL
;
2156 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2163 insert_neon_reg_alias (char *str
, int number
, int type
,
2164 struct neon_typed_alias
*atype
)
2166 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2170 first_error (_("attempt to redefine typed alias"));
2176 reg
->neon
= (struct neon_typed_alias
*)
2177 xmalloc (sizeof (struct neon_typed_alias
));
2178 *reg
->neon
= *atype
;
2182 /* Look for the .req directive. This is of the form:
2184 new_register_name .req existing_register_name
2186 If we find one, or if it looks sufficiently like one that we want to
2187 handle any error here, return TRUE. Otherwise return FALSE. */
2190 create_register_alias (char * newname
, char *p
)
2192 struct reg_entry
*old
;
2193 char *oldname
, *nbuf
;
2196 /* The input scrubber ensures that whitespace after the mnemonic is
2197 collapsed to single spaces. */
2199 if (strncmp (oldname
, " .req ", 6) != 0)
2203 if (*oldname
== '\0')
2206 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2209 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2213 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2214 the desired alias name, and p points to its end. If not, then
2215 the desired alias name is in the global original_case_string. */
2216 #ifdef TC_CASE_SENSITIVE
2219 newname
= original_case_string
;
2220 nlen
= strlen (newname
);
2223 nbuf
= (char *) alloca (nlen
+ 1);
2224 memcpy (nbuf
, newname
, nlen
);
2227 /* Create aliases under the new name as stated; an all-lowercase
2228 version of the new name; and an all-uppercase version of the new
2230 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2232 for (p
= nbuf
; *p
; p
++)
2235 if (strncmp (nbuf
, newname
, nlen
))
2237 /* If this attempt to create an additional alias fails, do not bother
2238 trying to create the all-lower case alias. We will fail and issue
2239 a second, duplicate error message. This situation arises when the
2240 programmer does something like:
2243 The second .req creates the "Foo" alias but then fails to create
2244 the artificial FOO alias because it has already been created by the
2246 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2250 for (p
= nbuf
; *p
; p
++)
2253 if (strncmp (nbuf
, newname
, nlen
))
2254 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2260 /* Create a Neon typed/indexed register alias using directives, e.g.:
2265 These typed registers can be used instead of the types specified after the
2266 Neon mnemonic, so long as all operands given have types. Types can also be
2267 specified directly, e.g.:
2268 vadd d0.s32, d1.s32, d2.s32 */
2271 create_neon_reg_alias (char *newname
, char *p
)
2273 enum arm_reg_type basetype
;
2274 struct reg_entry
*basereg
;
2275 struct reg_entry mybasereg
;
2276 struct neon_type ntype
;
2277 struct neon_typed_alias typeinfo
;
2278 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2281 typeinfo
.defined
= 0;
2282 typeinfo
.eltype
.type
= NT_invtype
;
2283 typeinfo
.eltype
.size
= -1;
2284 typeinfo
.index
= -1;
2288 if (strncmp (p
, " .dn ", 5) == 0)
2289 basetype
= REG_TYPE_VFD
;
2290 else if (strncmp (p
, " .qn ", 5) == 0)
2291 basetype
= REG_TYPE_NQ
;
2300 basereg
= arm_reg_parse_multi (&p
);
2302 if (basereg
&& basereg
->type
!= basetype
)
2304 as_bad (_("bad type for register"));
2308 if (basereg
== NULL
)
2311 /* Try parsing as an integer. */
2312 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2313 if (exp
.X_op
!= O_constant
)
2315 as_bad (_("expression must be constant"));
2318 basereg
= &mybasereg
;
2319 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2325 typeinfo
= *basereg
->neon
;
2327 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2329 /* We got a type. */
2330 if (typeinfo
.defined
& NTA_HASTYPE
)
2332 as_bad (_("can't redefine the type of a register alias"));
2336 typeinfo
.defined
|= NTA_HASTYPE
;
2337 if (ntype
.elems
!= 1)
2339 as_bad (_("you must specify a single type only"));
2342 typeinfo
.eltype
= ntype
.el
[0];
2345 if (skip_past_char (&p
, '[') == SUCCESS
)
2348 /* We got a scalar index. */
2350 if (typeinfo
.defined
& NTA_HASINDEX
)
2352 as_bad (_("can't redefine the index of a scalar alias"));
2356 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2358 if (exp
.X_op
!= O_constant
)
2360 as_bad (_("scalar index must be constant"));
2364 typeinfo
.defined
|= NTA_HASINDEX
;
2365 typeinfo
.index
= exp
.X_add_number
;
2367 if (skip_past_char (&p
, ']') == FAIL
)
2369 as_bad (_("expecting ]"));
2374 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2375 the desired alias name, and p points to its end. If not, then
2376 the desired alias name is in the global original_case_string. */
2377 #ifdef TC_CASE_SENSITIVE
2378 namelen
= nameend
- newname
;
2380 newname
= original_case_string
;
2381 namelen
= strlen (newname
);
2384 namebuf
= (char *) alloca (namelen
+ 1);
2385 strncpy (namebuf
, newname
, namelen
);
2386 namebuf
[namelen
] = '\0';
2388 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2389 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2391 /* Insert name in all uppercase. */
2392 for (p
= namebuf
; *p
; p
++)
2395 if (strncmp (namebuf
, newname
, namelen
))
2396 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2397 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2399 /* Insert name in all lowercase. */
2400 for (p
= namebuf
; *p
; p
++)
2403 if (strncmp (namebuf
, newname
, namelen
))
2404 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2405 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2410 /* Should never be called, as .req goes between the alias and the
2411 register name, not at the beginning of the line. */
2414 s_req (int a ATTRIBUTE_UNUSED
)
2416 as_bad (_("invalid syntax for .req directive"));
2420 s_dn (int a ATTRIBUTE_UNUSED
)
2422 as_bad (_("invalid syntax for .dn directive"));
2426 s_qn (int a ATTRIBUTE_UNUSED
)
2428 as_bad (_("invalid syntax for .qn directive"));
2431 /* The .unreq directive deletes an alias which was previously defined
2432 by .req. For example:
2438 s_unreq (int a ATTRIBUTE_UNUSED
)
2443 name
= input_line_pointer
;
2445 while (*input_line_pointer
!= 0
2446 && *input_line_pointer
!= ' '
2447 && *input_line_pointer
!= '\n')
2448 ++input_line_pointer
;
2450 saved_char
= *input_line_pointer
;
2451 *input_line_pointer
= 0;
2454 as_bad (_("invalid syntax for .unreq directive"));
2457 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2461 as_bad (_("unknown register alias '%s'"), name
);
2462 else if (reg
->builtin
)
2463 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2470 hash_delete (arm_reg_hsh
, name
, FALSE
);
2471 free ((char *) reg
->name
);
2476 /* Also locate the all upper case and all lower case versions.
2477 Do not complain if we cannot find one or the other as it
2478 was probably deleted above. */
2480 nbuf
= strdup (name
);
2481 for (p
= nbuf
; *p
; p
++)
2483 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2486 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2487 free ((char *) reg
->name
);
2493 for (p
= nbuf
; *p
; p
++)
2495 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2498 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2499 free ((char *) reg
->name
);
2509 *input_line_pointer
= saved_char
;
2510 demand_empty_rest_of_line ();
2513 /* Directives: Instruction set selection. */
2516 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2517 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2518 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2519 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2521 /* Create a new mapping symbol for the transition to STATE. */
2524 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2527 const char * symname
;
2534 type
= BSF_NO_FLAGS
;
2538 type
= BSF_NO_FLAGS
;
2542 type
= BSF_NO_FLAGS
;
2548 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2549 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2554 THUMB_SET_FUNC (symbolP
, 0);
2555 ARM_SET_THUMB (symbolP
, 0);
2556 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2560 THUMB_SET_FUNC (symbolP
, 1);
2561 ARM_SET_THUMB (symbolP
, 1);
2562 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2570 /* Save the mapping symbols for future reference. Also check that
2571 we do not place two mapping symbols at the same offset within a
2572 frag. We'll handle overlap between frags in
2573 check_mapping_symbols.
2575 If .fill or other data filling directive generates zero sized data,
2576 the mapping symbol for the following code will have the same value
2577 as the one generated for the data filling directive. In this case,
2578 we replace the old symbol with the new one at the same address. */
2581 if (frag
->tc_frag_data
.first_map
!= NULL
)
2583 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2584 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2586 frag
->tc_frag_data
.first_map
= symbolP
;
2588 if (frag
->tc_frag_data
.last_map
!= NULL
)
2590 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2591 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2592 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2594 frag
->tc_frag_data
.last_map
= symbolP
;
2597 /* We must sometimes convert a region marked as code to data during
2598 code alignment, if an odd number of bytes have to be padded. The
2599 code mapping symbol is pushed to an aligned address. */
2602 insert_data_mapping_symbol (enum mstate state
,
2603 valueT value
, fragS
*frag
, offsetT bytes
)
2605 /* If there was already a mapping symbol, remove it. */
2606 if (frag
->tc_frag_data
.last_map
!= NULL
2607 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2609 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2613 know (frag
->tc_frag_data
.first_map
== symp
);
2614 frag
->tc_frag_data
.first_map
= NULL
;
2616 frag
->tc_frag_data
.last_map
= NULL
;
2617 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2620 make_mapping_symbol (MAP_DATA
, value
, frag
);
2621 make_mapping_symbol (state
, value
+ bytes
, frag
);
2624 static void mapping_state_2 (enum mstate state
, int max_chars
);
2626 /* Set the mapping state to STATE. Only call this when about to
2627 emit some STATE bytes to the file. */
2630 mapping_state (enum mstate state
)
2632 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2634 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2636 if (mapstate
== state
)
2637 /* The mapping symbol has already been emitted.
2638 There is nothing else to do. */
2641 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2643 All ARM instructions require 4-byte alignment.
2644 (Almost) all Thumb instructions require 2-byte alignment.
2646 When emitting instructions into any section, mark the section
2649 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2650 but themselves require 2-byte alignment; this applies to some
2651 PC- relative forms. However, these cases will invovle implicit
2652 literal pool generation or an explicit .align >=2, both of
2653 which will cause the section to me marked with sufficient
2654 alignment. Thus, we don't handle those cases here. */
2655 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2657 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2658 /* This case will be evaluated later in the next else. */
2660 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2661 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2663 /* Only add the symbol if the offset is > 0:
2664 if we're at the first frag, check it's size > 0;
2665 if we're not at the first frag, then for sure
2666 the offset is > 0. */
2667 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2668 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2671 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2674 mapping_state_2 (state
, 0);
2678 /* Same as mapping_state, but MAX_CHARS bytes have already been
2679 allocated. Put the mapping symbol that far back. */
2682 mapping_state_2 (enum mstate state
, int max_chars
)
2684 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2686 if (!SEG_NORMAL (now_seg
))
2689 if (mapstate
== state
)
2690 /* The mapping symbol has already been emitted.
2691 There is nothing else to do. */
2694 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2695 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2698 #define mapping_state(x) ((void)0)
2699 #define mapping_state_2(x, y) ((void)0)
2702 /* Find the real, Thumb encoded start of a Thumb function. */
2706 find_real_start (symbolS
* symbolP
)
2709 const char * name
= S_GET_NAME (symbolP
);
2710 symbolS
* new_target
;
2712 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2713 #define STUB_NAME ".real_start_of"
2718 /* The compiler may generate BL instructions to local labels because
2719 it needs to perform a branch to a far away location. These labels
2720 do not have a corresponding ".real_start_of" label. We check
2721 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2722 the ".real_start_of" convention for nonlocal branches. */
2723 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2726 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2727 new_target
= symbol_find (real_start
);
2729 if (new_target
== NULL
)
2731 as_warn (_("Failed to find real start of function: %s\n"), name
);
2732 new_target
= symbolP
;
2740 opcode_select (int width
)
2747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2748 as_bad (_("selected processor does not support THUMB opcodes"));
2751 /* No need to force the alignment, since we will have been
2752 coming from ARM mode, which is word-aligned. */
2753 record_alignment (now_seg
, 1);
2760 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2761 as_bad (_("selected processor does not support ARM opcodes"));
2766 frag_align (2, 0, 0);
2768 record_alignment (now_seg
, 1);
2773 as_bad (_("invalid instruction size selected (%d)"), width
);
2778 s_arm (int ignore ATTRIBUTE_UNUSED
)
2781 demand_empty_rest_of_line ();
2785 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2788 demand_empty_rest_of_line ();
2792 s_code (int unused ATTRIBUTE_UNUSED
)
2796 temp
= get_absolute_expression ();
2801 opcode_select (temp
);
2805 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2810 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2812 /* If we are not already in thumb mode go into it, EVEN if
2813 the target processor does not support thumb instructions.
2814 This is used by gcc/config/arm/lib1funcs.asm for example
2815 to compile interworking support functions even if the
2816 target processor should not support interworking. */
2820 record_alignment (now_seg
, 1);
2823 demand_empty_rest_of_line ();
2827 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2831 /* The following label is the name/address of the start of a Thumb function.
2832 We need to know this for the interworking support. */
2833 label_is_thumb_function_name
= TRUE
;
2836 /* Perform a .set directive, but also mark the alias as
2837 being a thumb function. */
2840 s_thumb_set (int equiv
)
2842 /* XXX the following is a duplicate of the code for s_set() in read.c
2843 We cannot just call that code as we need to get at the symbol that
2850 /* Especial apologies for the random logic:
2851 This just grew, and could be parsed much more simply!
2853 name
= input_line_pointer
;
2854 delim
= get_symbol_end ();
2855 end_name
= input_line_pointer
;
2858 if (*input_line_pointer
!= ',')
2861 as_bad (_("expected comma after name \"%s\""), name
);
2863 ignore_rest_of_line ();
2867 input_line_pointer
++;
2870 if (name
[0] == '.' && name
[1] == '\0')
2872 /* XXX - this should not happen to .thumb_set. */
2876 if ((symbolP
= symbol_find (name
)) == NULL
2877 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2880 /* When doing symbol listings, play games with dummy fragments living
2881 outside the normal fragment chain to record the file and line info
2883 if (listing
& LISTING_SYMBOLS
)
2885 extern struct list_info_struct
* listing_tail
;
2886 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2888 memset (dummy_frag
, 0, sizeof (fragS
));
2889 dummy_frag
->fr_type
= rs_fill
;
2890 dummy_frag
->line
= listing_tail
;
2891 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2892 dummy_frag
->fr_symbol
= symbolP
;
2896 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2899 /* "set" symbols are local unless otherwise specified. */
2900 SF_SET_LOCAL (symbolP
);
2901 #endif /* OBJ_COFF */
2902 } /* Make a new symbol. */
2904 symbol_table_insert (symbolP
);
2909 && S_IS_DEFINED (symbolP
)
2910 && S_GET_SEGMENT (symbolP
) != reg_section
)
2911 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2913 pseudo_set (symbolP
);
2915 demand_empty_rest_of_line ();
2917 /* XXX Now we come to the Thumb specific bit of code. */
2919 THUMB_SET_FUNC (symbolP
, 1);
2920 ARM_SET_THUMB (symbolP
, 1);
2921 #if defined OBJ_ELF || defined OBJ_COFF
2922 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2926 /* Directives: Mode selection. */
2928 /* .syntax [unified|divided] - choose the new unified syntax
2929 (same for Arm and Thumb encoding, modulo slight differences in what
2930 can be represented) or the old divergent syntax for each mode. */
2932 s_syntax (int unused ATTRIBUTE_UNUSED
)
2936 name
= input_line_pointer
;
2937 delim
= get_symbol_end ();
2939 if (!strcasecmp (name
, "unified"))
2940 unified_syntax
= TRUE
;
2941 else if (!strcasecmp (name
, "divided"))
2942 unified_syntax
= FALSE
;
2945 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2948 *input_line_pointer
= delim
;
2949 demand_empty_rest_of_line ();
2952 /* Directives: sectioning and alignment. */
2954 /* Same as s_align_ptwo but align 0 => align 2. */
2957 s_align (int unused ATTRIBUTE_UNUSED
)
2962 long max_alignment
= 15;
2964 temp
= get_absolute_expression ();
2965 if (temp
> max_alignment
)
2966 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2969 as_bad (_("alignment negative. 0 assumed."));
2973 if (*input_line_pointer
== ',')
2975 input_line_pointer
++;
2976 temp_fill
= get_absolute_expression ();
2988 /* Only make a frag if we HAVE to. */
2989 if (temp
&& !need_pass_2
)
2991 if (!fill_p
&& subseg_text_p (now_seg
))
2992 frag_align_code (temp
, 0);
2994 frag_align (temp
, (int) temp_fill
, 0);
2996 demand_empty_rest_of_line ();
2998 record_alignment (now_seg
, temp
);
3002 s_bss (int ignore ATTRIBUTE_UNUSED
)
3004 /* We don't support putting frags in the BSS segment, we fake it by
3005 marking in_bss, then looking at s_skip for clues. */
3006 subseg_set (bss_section
, 0);
3007 demand_empty_rest_of_line ();
3009 #ifdef md_elf_section_change_hook
3010 md_elf_section_change_hook ();
3015 s_even (int ignore ATTRIBUTE_UNUSED
)
3017 /* Never make frag if expect extra pass. */
3019 frag_align (1, 0, 0);
3021 record_alignment (now_seg
, 1);
3023 demand_empty_rest_of_line ();
3026 /* Directives: CodeComposer Studio. */
3028 /* .ref (for CodeComposer Studio syntax only). */
3030 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3032 if (codecomposer_syntax
)
3033 ignore_rest_of_line ();
3035 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3038 /* If name is not NULL, then it is used for marking the beginning of a
3039 function, wherease if it is NULL then it means the function end. */
3041 asmfunc_debug (const char * name
)
3043 static const char * last_name
= NULL
;
3047 gas_assert (last_name
== NULL
);
3050 if (debug_type
== DEBUG_STABS
)
3051 stabs_generate_asm_func (name
, name
);
3055 gas_assert (last_name
!= NULL
);
3057 if (debug_type
== DEBUG_STABS
)
3058 stabs_generate_asm_endfunc (last_name
, last_name
);
3065 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3067 if (codecomposer_syntax
)
3069 switch (asmfunc_state
)
3071 case OUTSIDE_ASMFUNC
:
3072 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3075 case WAITING_ASMFUNC_NAME
:
3076 as_bad (_(".asmfunc repeated."));
3079 case WAITING_ENDASMFUNC
:
3080 as_bad (_(".asmfunc without function."));
3083 demand_empty_rest_of_line ();
3086 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3090 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3092 if (codecomposer_syntax
)
3094 switch (asmfunc_state
)
3096 case OUTSIDE_ASMFUNC
:
3097 as_bad (_(".endasmfunc without a .asmfunc."));
3100 case WAITING_ASMFUNC_NAME
:
3101 as_bad (_(".endasmfunc without function."));
3104 case WAITING_ENDASMFUNC
:
3105 asmfunc_state
= OUTSIDE_ASMFUNC
;
3106 asmfunc_debug (NULL
);
3109 demand_empty_rest_of_line ();
3112 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3116 s_ccs_def (int name
)
3118 if (codecomposer_syntax
)
3121 as_bad (_(".def pseudo-op only available with -mccs flag."));
3124 /* Directives: Literal pools. */
3126 static literal_pool
*
3127 find_literal_pool (void)
3129 literal_pool
* pool
;
3131 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3133 if (pool
->section
== now_seg
3134 && pool
->sub_section
== now_subseg
)
3141 static literal_pool
*
3142 find_or_make_literal_pool (void)
3144 /* Next literal pool ID number. */
3145 static unsigned int latest_pool_num
= 1;
3146 literal_pool
* pool
;
3148 pool
= find_literal_pool ();
3152 /* Create a new pool. */
3153 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3157 pool
->next_free_entry
= 0;
3158 pool
->section
= now_seg
;
3159 pool
->sub_section
= now_subseg
;
3160 pool
->next
= list_of_pools
;
3161 pool
->symbol
= NULL
;
3163 /* Add it to the list. */
3164 list_of_pools
= pool
;
3167 /* New pools, and emptied pools, will have a NULL symbol. */
3168 if (pool
->symbol
== NULL
)
3170 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3171 (valueT
) 0, &zero_address_frag
);
3172 pool
->id
= latest_pool_num
++;
3179 /* Add the literal in the global 'inst'
3180 structure to the relevant literal pool. */
3183 add_to_lit_pool (void)
3185 literal_pool
* pool
;
3188 pool
= find_or_make_literal_pool ();
3190 /* Check if this literal value is already in the pool. */
3191 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3193 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3194 && (inst
.reloc
.exp
.X_op
== O_constant
)
3195 && (pool
->literals
[entry
].X_add_number
3196 == inst
.reloc
.exp
.X_add_number
)
3197 && (pool
->literals
[entry
].X_unsigned
3198 == inst
.reloc
.exp
.X_unsigned
))
3201 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3202 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3203 && (pool
->literals
[entry
].X_add_number
3204 == inst
.reloc
.exp
.X_add_number
)
3205 && (pool
->literals
[entry
].X_add_symbol
3206 == inst
.reloc
.exp
.X_add_symbol
)
3207 && (pool
->literals
[entry
].X_op_symbol
3208 == inst
.reloc
.exp
.X_op_symbol
))
3212 /* Do we need to create a new entry? */
3213 if (entry
== pool
->next_free_entry
)
3215 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3217 inst
.error
= _("literal pool overflow");
3221 pool
->literals
[entry
] = inst
.reloc
.exp
;
3223 /* PR ld/12974: Record the location of the first source line to reference
3224 this entry in the literal pool. If it turns out during linking that the
3225 symbol does not exist we will be able to give an accurate line number for
3226 the (first use of the) missing reference. */
3227 if (debug_type
== DEBUG_DWARF2
)
3228 dwarf2_where (pool
->locs
+ entry
);
3230 pool
->next_free_entry
+= 1;
3233 inst
.reloc
.exp
.X_op
= O_symbol
;
3234 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3235 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3241 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3243 bfd_boolean ret
= TRUE
;
3245 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3247 const char *label
= rest
;
3249 while (!is_end_of_line
[(int) label
[-1]])
3254 as_bad (_("Invalid label '%s'"), label
);
3258 asmfunc_debug (label
);
3260 asmfunc_state
= WAITING_ENDASMFUNC
;
3266 /* Can't use symbol_new here, so have to create a symbol and then at
3267 a later date assign it a value. Thats what these functions do. */
3270 symbol_locate (symbolS
* symbolP
,
3271 const char * name
, /* It is copied, the caller can modify. */
3272 segT segment
, /* Segment identifier (SEG_<something>). */
3273 valueT valu
, /* Symbol value. */
3274 fragS
* frag
) /* Associated fragment. */
3276 unsigned int name_length
;
3277 char * preserved_copy_of_name
;
3279 name_length
= strlen (name
) + 1; /* +1 for \0. */
3280 obstack_grow (¬es
, name
, name_length
);
3281 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3283 #ifdef tc_canonicalize_symbol_name
3284 preserved_copy_of_name
=
3285 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3288 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3290 S_SET_SEGMENT (symbolP
, segment
);
3291 S_SET_VALUE (symbolP
, valu
);
3292 symbol_clear_list_pointers (symbolP
);
3294 symbol_set_frag (symbolP
, frag
);
3296 /* Link to end of symbol chain. */
3298 extern int symbol_table_frozen
;
3300 if (symbol_table_frozen
)
3304 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3306 obj_symbol_new_hook (symbolP
);
3308 #ifdef tc_symbol_new_hook
3309 tc_symbol_new_hook (symbolP
);
3313 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3314 #endif /* DEBUG_SYMS */
3319 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3322 literal_pool
* pool
;
3325 pool
= find_literal_pool ();
3327 || pool
->symbol
== NULL
3328 || pool
->next_free_entry
== 0)
3331 mapping_state (MAP_DATA
);
3333 /* Align pool as you have word accesses.
3334 Only make a frag if we have to. */
3336 frag_align (2, 0, 0);
3338 record_alignment (now_seg
, 2);
3340 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3342 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3343 (valueT
) frag_now_fix (), frag_now
);
3344 symbol_table_insert (pool
->symbol
);
3346 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3348 #if defined OBJ_COFF || defined OBJ_ELF
3349 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3352 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3355 if (debug_type
== DEBUG_DWARF2
)
3356 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3358 /* First output the expression in the instruction to the pool. */
3359 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3362 /* Mark the pool as empty. */
3363 pool
->next_free_entry
= 0;
3364 pool
->symbol
= NULL
;
3368 /* Forward declarations for functions below, in the MD interface
3370 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3371 static valueT
create_unwind_entry (int);
3372 static void start_unwind_section (const segT
, int);
3373 static void add_unwind_opcode (valueT
, int);
3374 static void flush_pending_unwind (void);
3376 /* Directives: Data. */
3379 s_arm_elf_cons (int nbytes
)
3383 #ifdef md_flush_pending_output
3384 md_flush_pending_output ();
3387 if (is_it_end_of_statement ())
3389 demand_empty_rest_of_line ();
3393 #ifdef md_cons_align
3394 md_cons_align (nbytes
);
3397 mapping_state (MAP_DATA
);
3401 char *base
= input_line_pointer
;
3405 if (exp
.X_op
!= O_symbol
)
3406 emit_expr (&exp
, (unsigned int) nbytes
);
3409 char *before_reloc
= input_line_pointer
;
3410 reloc
= parse_reloc (&input_line_pointer
);
3413 as_bad (_("unrecognized relocation suffix"));
3414 ignore_rest_of_line ();
3417 else if (reloc
== BFD_RELOC_UNUSED
)
3418 emit_expr (&exp
, (unsigned int) nbytes
);
3421 reloc_howto_type
*howto
= (reloc_howto_type
*)
3422 bfd_reloc_type_lookup (stdoutput
,
3423 (bfd_reloc_code_real_type
) reloc
);
3424 int size
= bfd_get_reloc_size (howto
);
3426 if (reloc
== BFD_RELOC_ARM_PLT32
)
3428 as_bad (_("(plt) is only valid on branch targets"));
3429 reloc
= BFD_RELOC_UNUSED
;
3434 as_bad (_("%s relocations do not fit in %d bytes"),
3435 howto
->name
, nbytes
);
3438 /* We've parsed an expression stopping at O_symbol.
3439 But there may be more expression left now that we
3440 have parsed the relocation marker. Parse it again.
3441 XXX Surely there is a cleaner way to do this. */
3442 char *p
= input_line_pointer
;
3444 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3445 memcpy (save_buf
, base
, input_line_pointer
- base
);
3446 memmove (base
+ (input_line_pointer
- before_reloc
),
3447 base
, before_reloc
- base
);
3449 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3451 memcpy (base
, save_buf
, p
- base
);
3453 offset
= nbytes
- size
;
3454 p
= frag_more ((int) nbytes
);
3455 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3456 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3461 while (*input_line_pointer
++ == ',');
3463 /* Put terminator back into stream. */
3464 input_line_pointer
--;
3465 demand_empty_rest_of_line ();
3468 /* Emit an expression containing a 32-bit thumb instruction.
3469 Implementation based on put_thumb32_insn. */
3472 emit_thumb32_expr (expressionS
* exp
)
3474 expressionS exp_high
= *exp
;
3476 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3477 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3478 exp
->X_add_number
&= 0xffff;
3479 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3482 /* Guess the instruction size based on the opcode. */
3485 thumb_insn_size (int opcode
)
3487 if ((unsigned int) opcode
< 0xe800u
)
3489 else if ((unsigned int) opcode
>= 0xe8000000u
)
3496 emit_insn (expressionS
*exp
, int nbytes
)
3500 if (exp
->X_op
== O_constant
)
3505 size
= thumb_insn_size (exp
->X_add_number
);
3509 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3511 as_bad (_(".inst.n operand too big. "\
3512 "Use .inst.w instead"));
3517 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3518 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3520 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3522 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3523 emit_thumb32_expr (exp
);
3525 emit_expr (exp
, (unsigned int) size
);
3527 it_fsm_post_encode ();
3531 as_bad (_("cannot determine Thumb instruction size. " \
3532 "Use .inst.n/.inst.w instead"));
3535 as_bad (_("constant expression required"));
3540 /* Like s_arm_elf_cons but do not use md_cons_align and
3541 set the mapping state to MAP_ARM/MAP_THUMB. */
3544 s_arm_elf_inst (int nbytes
)
3546 if (is_it_end_of_statement ())
3548 demand_empty_rest_of_line ();
3552 /* Calling mapping_state () here will not change ARM/THUMB,
3553 but will ensure not to be in DATA state. */
3556 mapping_state (MAP_THUMB
);
3561 as_bad (_("width suffixes are invalid in ARM mode"));
3562 ignore_rest_of_line ();
3568 mapping_state (MAP_ARM
);
3577 if (! emit_insn (& exp
, nbytes
))
3579 ignore_rest_of_line ();
3583 while (*input_line_pointer
++ == ',');
3585 /* Put terminator back into stream. */
3586 input_line_pointer
--;
3587 demand_empty_rest_of_line ();
3590 /* Parse a .rel31 directive. */
3593 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3600 if (*input_line_pointer
== '1')
3601 highbit
= 0x80000000;
3602 else if (*input_line_pointer
!= '0')
3603 as_bad (_("expected 0 or 1"));
3605 input_line_pointer
++;
3606 if (*input_line_pointer
!= ',')
3607 as_bad (_("missing comma"));
3608 input_line_pointer
++;
3610 #ifdef md_flush_pending_output
3611 md_flush_pending_output ();
3614 #ifdef md_cons_align
3618 mapping_state (MAP_DATA
);
3623 md_number_to_chars (p
, highbit
, 4);
3624 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3625 BFD_RELOC_ARM_PREL31
);
3627 demand_empty_rest_of_line ();
3630 /* Directives: AEABI stack-unwind tables. */
3632 /* Parse an unwind_fnstart directive. Simply records the current location. */
3635 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3637 demand_empty_rest_of_line ();
3638 if (unwind
.proc_start
)
3640 as_bad (_("duplicate .fnstart directive"));
3644 /* Mark the start of the function. */
3645 unwind
.proc_start
= expr_build_dot ();
3647 /* Reset the rest of the unwind info. */
3648 unwind
.opcode_count
= 0;
3649 unwind
.table_entry
= NULL
;
3650 unwind
.personality_routine
= NULL
;
3651 unwind
.personality_index
= -1;
3652 unwind
.frame_size
= 0;
3653 unwind
.fp_offset
= 0;
3654 unwind
.fp_reg
= REG_SP
;
3656 unwind
.sp_restored
= 0;
3660 /* Parse a handlerdata directive. Creates the exception handling table entry
3661 for the function. */
3664 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3666 demand_empty_rest_of_line ();
3667 if (!unwind
.proc_start
)
3668 as_bad (MISSING_FNSTART
);
3670 if (unwind
.table_entry
)
3671 as_bad (_("duplicate .handlerdata directive"));
3673 create_unwind_entry (1);
3676 /* Parse an unwind_fnend directive. Generates the index table entry. */
3679 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3684 unsigned int marked_pr_dependency
;
3686 demand_empty_rest_of_line ();
3688 if (!unwind
.proc_start
)
3690 as_bad (_(".fnend directive without .fnstart"));
3694 /* Add eh table entry. */
3695 if (unwind
.table_entry
== NULL
)
3696 val
= create_unwind_entry (0);
3700 /* Add index table entry. This is two words. */
3701 start_unwind_section (unwind
.saved_seg
, 1);
3702 frag_align (2, 0, 0);
3703 record_alignment (now_seg
, 2);
3705 ptr
= frag_more (8);
3707 where
= frag_now_fix () - 8;
3709 /* Self relative offset of the function start. */
3710 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3711 BFD_RELOC_ARM_PREL31
);
3713 /* Indicate dependency on EHABI-defined personality routines to the
3714 linker, if it hasn't been done already. */
3715 marked_pr_dependency
3716 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3717 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3718 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3720 static const char *const name
[] =
3722 "__aeabi_unwind_cpp_pr0",
3723 "__aeabi_unwind_cpp_pr1",
3724 "__aeabi_unwind_cpp_pr2"
3726 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3727 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3728 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3729 |= 1 << unwind
.personality_index
;
3733 /* Inline exception table entry. */
3734 md_number_to_chars (ptr
+ 4, val
, 4);
3736 /* Self relative offset of the table entry. */
3737 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3738 BFD_RELOC_ARM_PREL31
);
3740 /* Restore the original section. */
3741 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3743 unwind
.proc_start
= NULL
;
3747 /* Parse an unwind_cantunwind directive. */
3750 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3752 demand_empty_rest_of_line ();
3753 if (!unwind
.proc_start
)
3754 as_bad (MISSING_FNSTART
);
3756 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3757 as_bad (_("personality routine specified for cantunwind frame"));
3759 unwind
.personality_index
= -2;
3763 /* Parse a personalityindex directive. */
3766 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3770 if (!unwind
.proc_start
)
3771 as_bad (MISSING_FNSTART
);
3773 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3774 as_bad (_("duplicate .personalityindex directive"));
3778 if (exp
.X_op
!= O_constant
3779 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3781 as_bad (_("bad personality routine number"));
3782 ignore_rest_of_line ();
3786 unwind
.personality_index
= exp
.X_add_number
;
3788 demand_empty_rest_of_line ();
3792 /* Parse a personality directive. */
3795 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3799 if (!unwind
.proc_start
)
3800 as_bad (MISSING_FNSTART
);
3802 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3803 as_bad (_("duplicate .personality directive"));
3805 name
= input_line_pointer
;
3806 c
= get_symbol_end ();
3807 p
= input_line_pointer
;
3808 unwind
.personality_routine
= symbol_find_or_make (name
);
3810 demand_empty_rest_of_line ();
3814 /* Parse a directive saving core registers. */
3817 s_arm_unwind_save_core (void)
3823 range
= parse_reg_list (&input_line_pointer
);
3826 as_bad (_("expected register list"));
3827 ignore_rest_of_line ();
3831 demand_empty_rest_of_line ();
3833 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3834 into .unwind_save {..., sp...}. We aren't bothered about the value of
3835 ip because it is clobbered by calls. */
3836 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3837 && (range
& 0x3000) == 0x1000)
3839 unwind
.opcode_count
--;
3840 unwind
.sp_restored
= 0;
3841 range
= (range
| 0x2000) & ~0x1000;
3842 unwind
.pending_offset
= 0;
3848 /* See if we can use the short opcodes. These pop a block of up to 8
3849 registers starting with r4, plus maybe r14. */
3850 for (n
= 0; n
< 8; n
++)
3852 /* Break at the first non-saved register. */
3853 if ((range
& (1 << (n
+ 4))) == 0)
3856 /* See if there are any other bits set. */
3857 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3859 /* Use the long form. */
3860 op
= 0x8000 | ((range
>> 4) & 0xfff);
3861 add_unwind_opcode (op
, 2);
3865 /* Use the short form. */
3867 op
= 0xa8; /* Pop r14. */
3869 op
= 0xa0; /* Do not pop r14. */
3871 add_unwind_opcode (op
, 1);
3878 op
= 0xb100 | (range
& 0xf);
3879 add_unwind_opcode (op
, 2);
3882 /* Record the number of bytes pushed. */
3883 for (n
= 0; n
< 16; n
++)
3885 if (range
& (1 << n
))
3886 unwind
.frame_size
+= 4;
3891 /* Parse a directive saving FPA registers. */
3894 s_arm_unwind_save_fpa (int reg
)
3900 /* Get Number of registers to transfer. */
3901 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3904 exp
.X_op
= O_illegal
;
3906 if (exp
.X_op
!= O_constant
)
3908 as_bad (_("expected , <constant>"));
3909 ignore_rest_of_line ();
3913 num_regs
= exp
.X_add_number
;
3915 if (num_regs
< 1 || num_regs
> 4)
3917 as_bad (_("number of registers must be in the range [1:4]"));
3918 ignore_rest_of_line ();
3922 demand_empty_rest_of_line ();
3927 op
= 0xb4 | (num_regs
- 1);
3928 add_unwind_opcode (op
, 1);
3933 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3934 add_unwind_opcode (op
, 2);
3936 unwind
.frame_size
+= num_regs
* 12;
3940 /* Parse a directive saving VFP registers for ARMv6 and above. */
3943 s_arm_unwind_save_vfp_armv6 (void)
3948 int num_vfpv3_regs
= 0;
3949 int num_regs_below_16
;
3951 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3954 as_bad (_("expected register list"));
3955 ignore_rest_of_line ();
3959 demand_empty_rest_of_line ();
3961 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3962 than FSTMX/FLDMX-style ones). */
3964 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3966 num_vfpv3_regs
= count
;
3967 else if (start
+ count
> 16)
3968 num_vfpv3_regs
= start
+ count
- 16;
3970 if (num_vfpv3_regs
> 0)
3972 int start_offset
= start
> 16 ? start
- 16 : 0;
3973 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3974 add_unwind_opcode (op
, 2);
3977 /* Generate opcode for registers numbered in the range 0 .. 15. */
3978 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3979 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3980 if (num_regs_below_16
> 0)
3982 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3983 add_unwind_opcode (op
, 2);
3986 unwind
.frame_size
+= count
* 8;
3990 /* Parse a directive saving VFP registers for pre-ARMv6. */
3993 s_arm_unwind_save_vfp (void)
3999 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4002 as_bad (_("expected register list"));
4003 ignore_rest_of_line ();
4007 demand_empty_rest_of_line ();
4012 op
= 0xb8 | (count
- 1);
4013 add_unwind_opcode (op
, 1);
4018 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4019 add_unwind_opcode (op
, 2);
4021 unwind
.frame_size
+= count
* 8 + 4;
4025 /* Parse a directive saving iWMMXt data registers. */
4028 s_arm_unwind_save_mmxwr (void)
4036 if (*input_line_pointer
== '{')
4037 input_line_pointer
++;
4041 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4045 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4050 as_tsktsk (_("register list not in ascending order"));
4053 if (*input_line_pointer
== '-')
4055 input_line_pointer
++;
4056 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4059 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4062 else if (reg
>= hi_reg
)
4064 as_bad (_("bad register range"));
4067 for (; reg
< hi_reg
; reg
++)
4071 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4073 skip_past_char (&input_line_pointer
, '}');
4075 demand_empty_rest_of_line ();
4077 /* Generate any deferred opcodes because we're going to be looking at
4079 flush_pending_unwind ();
4081 for (i
= 0; i
< 16; i
++)
4083 if (mask
& (1 << i
))
4084 unwind
.frame_size
+= 8;
4087 /* Attempt to combine with a previous opcode. We do this because gcc
4088 likes to output separate unwind directives for a single block of
4090 if (unwind
.opcode_count
> 0)
4092 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4093 if ((i
& 0xf8) == 0xc0)
4096 /* Only merge if the blocks are contiguous. */
4099 if ((mask
& 0xfe00) == (1 << 9))
4101 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4102 unwind
.opcode_count
--;
4105 else if (i
== 6 && unwind
.opcode_count
>= 2)
4107 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4111 op
= 0xffff << (reg
- 1);
4113 && ((mask
& op
) == (1u << (reg
- 1))))
4115 op
= (1 << (reg
+ i
+ 1)) - 1;
4116 op
&= ~((1 << reg
) - 1);
4118 unwind
.opcode_count
-= 2;
4125 /* We want to generate opcodes in the order the registers have been
4126 saved, ie. descending order. */
4127 for (reg
= 15; reg
>= -1; reg
--)
4129 /* Save registers in blocks. */
4131 || !(mask
& (1 << reg
)))
4133 /* We found an unsaved reg. Generate opcodes to save the
4140 op
= 0xc0 | (hi_reg
- 10);
4141 add_unwind_opcode (op
, 1);
4146 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4147 add_unwind_opcode (op
, 2);
4156 ignore_rest_of_line ();
4160 s_arm_unwind_save_mmxwcg (void)
4167 if (*input_line_pointer
== '{')
4168 input_line_pointer
++;
4170 skip_whitespace (input_line_pointer
);
4174 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4178 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4184 as_tsktsk (_("register list not in ascending order"));
4187 if (*input_line_pointer
== '-')
4189 input_line_pointer
++;
4190 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4193 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4196 else if (reg
>= hi_reg
)
4198 as_bad (_("bad register range"));
4201 for (; reg
< hi_reg
; reg
++)
4205 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4207 skip_past_char (&input_line_pointer
, '}');
4209 demand_empty_rest_of_line ();
4211 /* Generate any deferred opcodes because we're going to be looking at
4213 flush_pending_unwind ();
4215 for (reg
= 0; reg
< 16; reg
++)
4217 if (mask
& (1 << reg
))
4218 unwind
.frame_size
+= 4;
4221 add_unwind_opcode (op
, 2);
4224 ignore_rest_of_line ();
4228 /* Parse an unwind_save directive.
4229 If the argument is non-zero, this is a .vsave directive. */
4232 s_arm_unwind_save (int arch_v6
)
4235 struct reg_entry
*reg
;
4236 bfd_boolean had_brace
= FALSE
;
4238 if (!unwind
.proc_start
)
4239 as_bad (MISSING_FNSTART
);
4241 /* Figure out what sort of save we have. */
4242 peek
= input_line_pointer
;
4250 reg
= arm_reg_parse_multi (&peek
);
4254 as_bad (_("register expected"));
4255 ignore_rest_of_line ();
4264 as_bad (_("FPA .unwind_save does not take a register list"));
4265 ignore_rest_of_line ();
4268 input_line_pointer
= peek
;
4269 s_arm_unwind_save_fpa (reg
->number
);
4273 s_arm_unwind_save_core ();
4278 s_arm_unwind_save_vfp_armv6 ();
4280 s_arm_unwind_save_vfp ();
4283 case REG_TYPE_MMXWR
:
4284 s_arm_unwind_save_mmxwr ();
4287 case REG_TYPE_MMXWCG
:
4288 s_arm_unwind_save_mmxwcg ();
4292 as_bad (_(".unwind_save does not support this kind of register"));
4293 ignore_rest_of_line ();
4298 /* Parse an unwind_movsp directive. */
4301 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4307 if (!unwind
.proc_start
)
4308 as_bad (MISSING_FNSTART
);
4310 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4313 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4314 ignore_rest_of_line ();
4318 /* Optional constant. */
4319 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4321 if (immediate_for_directive (&offset
) == FAIL
)
4327 demand_empty_rest_of_line ();
4329 if (reg
== REG_SP
|| reg
== REG_PC
)
4331 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4335 if (unwind
.fp_reg
!= REG_SP
)
4336 as_bad (_("unexpected .unwind_movsp directive"));
4338 /* Generate opcode to restore the value. */
4340 add_unwind_opcode (op
, 1);
4342 /* Record the information for later. */
4343 unwind
.fp_reg
= reg
;
4344 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4345 unwind
.sp_restored
= 1;
4348 /* Parse an unwind_pad directive. */
4351 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4355 if (!unwind
.proc_start
)
4356 as_bad (MISSING_FNSTART
);
4358 if (immediate_for_directive (&offset
) == FAIL
)
4363 as_bad (_("stack increment must be multiple of 4"));
4364 ignore_rest_of_line ();
4368 /* Don't generate any opcodes, just record the details for later. */
4369 unwind
.frame_size
+= offset
;
4370 unwind
.pending_offset
+= offset
;
4372 demand_empty_rest_of_line ();
4375 /* Parse an unwind_setfp directive. */
4378 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4384 if (!unwind
.proc_start
)
4385 as_bad (MISSING_FNSTART
);
4387 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4388 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4391 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4393 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4395 as_bad (_("expected <reg>, <reg>"));
4396 ignore_rest_of_line ();
4400 /* Optional constant. */
4401 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4403 if (immediate_for_directive (&offset
) == FAIL
)
4409 demand_empty_rest_of_line ();
4411 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4413 as_bad (_("register must be either sp or set by a previous"
4414 "unwind_movsp directive"));
4418 /* Don't generate any opcodes, just record the information for later. */
4419 unwind
.fp_reg
= fp_reg
;
4421 if (sp_reg
== REG_SP
)
4422 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4424 unwind
.fp_offset
-= offset
;
4427 /* Parse an unwind_raw directive. */
4430 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4433 /* This is an arbitrary limit. */
4434 unsigned char op
[16];
4437 if (!unwind
.proc_start
)
4438 as_bad (MISSING_FNSTART
);
4441 if (exp
.X_op
== O_constant
4442 && skip_past_comma (&input_line_pointer
) != FAIL
)
4444 unwind
.frame_size
+= exp
.X_add_number
;
4448 exp
.X_op
= O_illegal
;
4450 if (exp
.X_op
!= O_constant
)
4452 as_bad (_("expected <offset>, <opcode>"));
4453 ignore_rest_of_line ();
4459 /* Parse the opcode. */
4464 as_bad (_("unwind opcode too long"));
4465 ignore_rest_of_line ();
4467 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4469 as_bad (_("invalid unwind opcode"));
4470 ignore_rest_of_line ();
4473 op
[count
++] = exp
.X_add_number
;
4475 /* Parse the next byte. */
4476 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4482 /* Add the opcode bytes in reverse order. */
4484 add_unwind_opcode (op
[count
], 1);
4486 demand_empty_rest_of_line ();
4490 /* Parse a .eabi_attribute directive. */
4493 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4495 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4497 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4498 attributes_set_explicitly
[tag
] = 1;
4501 /* Emit a tls fix for the symbol. */
4504 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4508 #ifdef md_flush_pending_output
4509 md_flush_pending_output ();
4512 #ifdef md_cons_align
4516 /* Since we're just labelling the code, there's no need to define a
4519 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4520 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4521 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4522 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4524 #endif /* OBJ_ELF */
4526 static void s_arm_arch (int);
4527 static void s_arm_object_arch (int);
4528 static void s_arm_cpu (int);
4529 static void s_arm_fpu (int);
4530 static void s_arm_arch_extension (int);
4535 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4542 if (exp
.X_op
== O_symbol
)
4543 exp
.X_op
= O_secrel
;
4545 emit_expr (&exp
, 4);
4547 while (*input_line_pointer
++ == ',');
4549 input_line_pointer
--;
4550 demand_empty_rest_of_line ();
4554 /* This table describes all the machine specific pseudo-ops the assembler
4555 has to support. The fields are:
4556 pseudo-op name without dot
4557 function to call to execute this pseudo-op
4558 Integer arg to pass to the function. */
4560 const pseudo_typeS md_pseudo_table
[] =
4562 /* Never called because '.req' does not start a line. */
4563 { "req", s_req
, 0 },
4564 /* Following two are likewise never called. */
4567 { "unreq", s_unreq
, 0 },
4568 { "bss", s_bss
, 0 },
4569 { "align", s_align
, 0 },
4570 { "arm", s_arm
, 0 },
4571 { "thumb", s_thumb
, 0 },
4572 { "code", s_code
, 0 },
4573 { "force_thumb", s_force_thumb
, 0 },
4574 { "thumb_func", s_thumb_func
, 0 },
4575 { "thumb_set", s_thumb_set
, 0 },
4576 { "even", s_even
, 0 },
4577 { "ltorg", s_ltorg
, 0 },
4578 { "pool", s_ltorg
, 0 },
4579 { "syntax", s_syntax
, 0 },
4580 { "cpu", s_arm_cpu
, 0 },
4581 { "arch", s_arm_arch
, 0 },
4582 { "object_arch", s_arm_object_arch
, 0 },
4583 { "fpu", s_arm_fpu
, 0 },
4584 { "arch_extension", s_arm_arch_extension
, 0 },
4586 { "word", s_arm_elf_cons
, 4 },
4587 { "long", s_arm_elf_cons
, 4 },
4588 { "inst.n", s_arm_elf_inst
, 2 },
4589 { "inst.w", s_arm_elf_inst
, 4 },
4590 { "inst", s_arm_elf_inst
, 0 },
4591 { "rel31", s_arm_rel31
, 0 },
4592 { "fnstart", s_arm_unwind_fnstart
, 0 },
4593 { "fnend", s_arm_unwind_fnend
, 0 },
4594 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4595 { "personality", s_arm_unwind_personality
, 0 },
4596 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4597 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4598 { "save", s_arm_unwind_save
, 0 },
4599 { "vsave", s_arm_unwind_save
, 1 },
4600 { "movsp", s_arm_unwind_movsp
, 0 },
4601 { "pad", s_arm_unwind_pad
, 0 },
4602 { "setfp", s_arm_unwind_setfp
, 0 },
4603 { "unwind_raw", s_arm_unwind_raw
, 0 },
4604 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4605 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4609 /* These are used for dwarf. */
4613 /* These are used for dwarf2. */
4614 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4615 { "loc", dwarf2_directive_loc
, 0 },
4616 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4618 { "extend", float_cons
, 'x' },
4619 { "ldouble", float_cons
, 'x' },
4620 { "packed", float_cons
, 'p' },
4622 {"secrel32", pe_directive_secrel
, 0},
4625 /* These are for compatibility with CodeComposer Studio. */
4626 {"ref", s_ccs_ref
, 0},
4627 {"def", s_ccs_def
, 0},
4628 {"asmfunc", s_ccs_asmfunc
, 0},
4629 {"endasmfunc", s_ccs_endasmfunc
, 0},
4634 /* Parser functions used exclusively in instruction operands. */
4636 /* Generic immediate-value read function for use in insn parsing.
4637 STR points to the beginning of the immediate (the leading #);
4638 VAL receives the value; if the value is outside [MIN, MAX]
4639 issue an error. PREFIX_OPT is true if the immediate prefix is
4643 parse_immediate (char **str
, int *val
, int min
, int max
,
4644 bfd_boolean prefix_opt
)
4647 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4648 if (exp
.X_op
!= O_constant
)
4650 inst
.error
= _("constant expression required");
4654 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4656 inst
.error
= _("immediate value out of range");
4660 *val
= exp
.X_add_number
;
4664 /* Less-generic immediate-value read function with the possibility of loading a
4665 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4666 instructions. Puts the result directly in inst.operands[i]. */
4669 parse_big_immediate (char **str
, int i
)
4674 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4676 if (exp
.X_op
== O_constant
)
4678 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4679 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4680 O_constant. We have to be careful not to break compilation for
4681 32-bit X_add_number, though. */
4682 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4684 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4685 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4686 inst
.operands
[i
].regisimm
= 1;
4689 else if (exp
.X_op
== O_big
4690 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4692 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4694 /* Bignums have their least significant bits in
4695 generic_bignum[0]. Make sure we put 32 bits in imm and
4696 32 bits in reg, in a (hopefully) portable way. */
4697 gas_assert (parts
!= 0);
4699 /* Make sure that the number is not too big.
4700 PR 11972: Bignums can now be sign-extended to the
4701 size of a .octa so check that the out of range bits
4702 are all zero or all one. */
4703 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4705 LITTLENUM_TYPE m
= -1;
4707 if (generic_bignum
[parts
* 2] != 0
4708 && generic_bignum
[parts
* 2] != m
)
4711 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4712 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4716 inst
.operands
[i
].imm
= 0;
4717 for (j
= 0; j
< parts
; j
++, idx
++)
4718 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4719 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4720 inst
.operands
[i
].reg
= 0;
4721 for (j
= 0; j
< parts
; j
++, idx
++)
4722 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4723 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4724 inst
.operands
[i
].regisimm
= 1;
4734 /* Returns the pseudo-register number of an FPA immediate constant,
4735 or FAIL if there isn't a valid constant here. */
4738 parse_fpa_immediate (char ** str
)
4740 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4746 /* First try and match exact strings, this is to guarantee
4747 that some formats will work even for cross assembly. */
4749 for (i
= 0; fp_const
[i
]; i
++)
4751 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4755 *str
+= strlen (fp_const
[i
]);
4756 if (is_end_of_line
[(unsigned char) **str
])
4762 /* Just because we didn't get a match doesn't mean that the constant
4763 isn't valid, just that it is in a format that we don't
4764 automatically recognize. Try parsing it with the standard
4765 expression routines. */
4767 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4769 /* Look for a raw floating point number. */
4770 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4771 && is_end_of_line
[(unsigned char) *save_in
])
4773 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4775 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4777 if (words
[j
] != fp_values
[i
][j
])
4781 if (j
== MAX_LITTLENUMS
)
4789 /* Try and parse a more complex expression, this will probably fail
4790 unless the code uses a floating point prefix (eg "0f"). */
4791 save_in
= input_line_pointer
;
4792 input_line_pointer
= *str
;
4793 if (expression (&exp
) == absolute_section
4794 && exp
.X_op
== O_big
4795 && exp
.X_add_number
< 0)
4797 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4799 if (gen_to_words (words
, 5, (long) 15) == 0)
4801 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4803 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4805 if (words
[j
] != fp_values
[i
][j
])
4809 if (j
== MAX_LITTLENUMS
)
4811 *str
= input_line_pointer
;
4812 input_line_pointer
= save_in
;
4819 *str
= input_line_pointer
;
4820 input_line_pointer
= save_in
;
4821 inst
.error
= _("invalid FPA immediate expression");
4825 /* Returns 1 if a number has "quarter-precision" float format
4826 0baBbbbbbc defgh000 00000000 00000000. */
4829 is_quarter_float (unsigned imm
)
4831 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4832 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4835 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4836 0baBbbbbbc defgh000 00000000 00000000.
4837 The zero and minus-zero cases need special handling, since they can't be
4838 encoded in the "quarter-precision" float format, but can nonetheless be
4839 loaded as integer constants. */
4842 parse_qfloat_immediate (char **ccp
, int *immed
)
4846 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4847 int found_fpchar
= 0;
4849 skip_past_char (&str
, '#');
4851 /* We must not accidentally parse an integer as a floating-point number. Make
4852 sure that the value we parse is not an integer by checking for special
4853 characters '.' or 'e'.
4854 FIXME: This is a horrible hack, but doing better is tricky because type
4855 information isn't in a very usable state at parse time. */
4857 skip_whitespace (fpnum
);
4859 if (strncmp (fpnum
, "0x", 2) == 0)
4863 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4864 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4874 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4876 unsigned fpword
= 0;
4879 /* Our FP word must be 32 bits (single-precision FP). */
4880 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4882 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4886 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4899 /* Shift operands. */
4902 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4905 struct asm_shift_name
4908 enum shift_kind kind
;
4911 /* Third argument to parse_shift. */
4912 enum parse_shift_mode
4914 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4915 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4916 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4917 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4918 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4921 /* Parse a <shift> specifier on an ARM data processing instruction.
4922 This has three forms:
4924 (LSL|LSR|ASL|ASR|ROR) Rs
4925 (LSL|LSR|ASL|ASR|ROR) #imm
4928 Note that ASL is assimilated to LSL in the instruction encoding, and
4929 RRX to ROR #0 (which cannot be written as such). */
4932 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4934 const struct asm_shift_name
*shift_name
;
4935 enum shift_kind shift
;
4940 for (p
= *str
; ISALPHA (*p
); p
++)
4945 inst
.error
= _("shift expression expected");
4949 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4952 if (shift_name
== NULL
)
4954 inst
.error
= _("shift expression expected");
4958 shift
= shift_name
->kind
;
4962 case NO_SHIFT_RESTRICT
:
4963 case SHIFT_IMMEDIATE
: break;
4965 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4966 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4968 inst
.error
= _("'LSL' or 'ASR' required");
4973 case SHIFT_LSL_IMMEDIATE
:
4974 if (shift
!= SHIFT_LSL
)
4976 inst
.error
= _("'LSL' required");
4981 case SHIFT_ASR_IMMEDIATE
:
4982 if (shift
!= SHIFT_ASR
)
4984 inst
.error
= _("'ASR' required");
4992 if (shift
!= SHIFT_RRX
)
4994 /* Whitespace can appear here if the next thing is a bare digit. */
4995 skip_whitespace (p
);
4997 if (mode
== NO_SHIFT_RESTRICT
4998 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5000 inst
.operands
[i
].imm
= reg
;
5001 inst
.operands
[i
].immisreg
= 1;
5003 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5006 inst
.operands
[i
].shift_kind
= shift
;
5007 inst
.operands
[i
].shifted
= 1;
5012 /* Parse a <shifter_operand> for an ARM data processing instruction:
5015 #<immediate>, <rotate>
5019 where <shift> is defined by parse_shift above, and <rotate> is a
5020 multiple of 2 between 0 and 30. Validation of immediate operands
5021 is deferred to md_apply_fix. */
5024 parse_shifter_operand (char **str
, int i
)
5029 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5031 inst
.operands
[i
].reg
= value
;
5032 inst
.operands
[i
].isreg
= 1;
5034 /* parse_shift will override this if appropriate */
5035 inst
.reloc
.exp
.X_op
= O_constant
;
5036 inst
.reloc
.exp
.X_add_number
= 0;
5038 if (skip_past_comma (str
) == FAIL
)
5041 /* Shift operation on register. */
5042 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5045 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5048 if (skip_past_comma (str
) == SUCCESS
)
5050 /* #x, y -- ie explicit rotation by Y. */
5051 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5054 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5056 inst
.error
= _("constant expression expected");
5060 value
= exp
.X_add_number
;
5061 if (value
< 0 || value
> 30 || value
% 2 != 0)
5063 inst
.error
= _("invalid rotation");
5066 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5068 inst
.error
= _("invalid constant");
5072 /* Encode as specified. */
5073 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5077 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5078 inst
.reloc
.pc_rel
= 0;
5082 /* Group relocation information. Each entry in the table contains the
5083 textual name of the relocation as may appear in assembler source
5084 and must end with a colon.
5085 Along with this textual name are the relocation codes to be used if
5086 the corresponding instruction is an ALU instruction (ADD or SUB only),
5087 an LDR, an LDRS, or an LDC. */
5089 struct group_reloc_table_entry
5100 /* Varieties of non-ALU group relocation. */
5107 static struct group_reloc_table_entry group_reloc_table
[] =
5108 { /* Program counter relative: */
5110 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5115 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5116 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5117 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5118 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5120 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5125 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5126 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5127 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5128 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5130 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5131 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5132 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5133 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5134 /* Section base relative */
5136 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5141 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5142 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5143 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5144 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5146 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5151 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5152 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5153 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5154 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5156 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5157 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5158 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5159 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5161 /* Given the address of a pointer pointing to the textual name of a group
5162 relocation as may appear in assembler source, attempt to find its details
5163 in group_reloc_table. The pointer will be updated to the character after
5164 the trailing colon. On failure, FAIL will be returned; SUCCESS
5165 otherwise. On success, *entry will be updated to point at the relevant
5166 group_reloc_table entry. */
5169 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5172 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5174 int length
= strlen (group_reloc_table
[i
].name
);
5176 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5177 && (*str
)[length
] == ':')
5179 *out
= &group_reloc_table
[i
];
5180 *str
+= (length
+ 1);
5188 /* Parse a <shifter_operand> for an ARM data processing instruction
5189 (as for parse_shifter_operand) where group relocations are allowed:
5192 #<immediate>, <rotate>
5193 #:<group_reloc>:<expression>
5197 where <group_reloc> is one of the strings defined in group_reloc_table.
5198 The hashes are optional.
5200 Everything else is as for parse_shifter_operand. */
5202 static parse_operand_result
5203 parse_shifter_operand_group_reloc (char **str
, int i
)
5205 /* Determine if we have the sequence of characters #: or just :
5206 coming next. If we do, then we check for a group relocation.
5207 If we don't, punt the whole lot to parse_shifter_operand. */
5209 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5210 || (*str
)[0] == ':')
5212 struct group_reloc_table_entry
*entry
;
5214 if ((*str
)[0] == '#')
5219 /* Try to parse a group relocation. Anything else is an error. */
5220 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5222 inst
.error
= _("unknown group relocation");
5223 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5226 /* We now have the group relocation table entry corresponding to
5227 the name in the assembler source. Next, we parse the expression. */
5228 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5229 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5231 /* Record the relocation type (always the ALU variant here). */
5232 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5233 gas_assert (inst
.reloc
.type
!= 0);
5235 return PARSE_OPERAND_SUCCESS
;
5238 return parse_shifter_operand (str
, i
) == SUCCESS
5239 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5241 /* Never reached. */
5244 /* Parse a Neon alignment expression. Information is written to
5245 inst.operands[i]. We assume the initial ':' has been skipped.
5247 align .imm = align << 8, .immisalign=1, .preind=0 */
5248 static parse_operand_result
5249 parse_neon_alignment (char **str
, int i
)
5254 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5256 if (exp
.X_op
!= O_constant
)
5258 inst
.error
= _("alignment must be constant");
5259 return PARSE_OPERAND_FAIL
;
5262 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5263 inst
.operands
[i
].immisalign
= 1;
5264 /* Alignments are not pre-indexes. */
5265 inst
.operands
[i
].preind
= 0;
5268 return PARSE_OPERAND_SUCCESS
;
5271 /* Parse all forms of an ARM address expression. Information is written
5272 to inst.operands[i] and/or inst.reloc.
5274 Preindexed addressing (.preind=1):
5276 [Rn, #offset] .reg=Rn .reloc.exp=offset
5277 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5278 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5279 .shift_kind=shift .reloc.exp=shift_imm
5281 These three may have a trailing ! which causes .writeback to be set also.
5283 Postindexed addressing (.postind=1, .writeback=1):
5285 [Rn], #offset .reg=Rn .reloc.exp=offset
5286 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5287 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5288 .shift_kind=shift .reloc.exp=shift_imm
5290 Unindexed addressing (.preind=0, .postind=0):
5292 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5296 [Rn]{!} shorthand for [Rn,#0]{!}
5297 =immediate .isreg=0 .reloc.exp=immediate
5298 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5300 It is the caller's responsibility to check for addressing modes not
5301 supported by the instruction, and to set inst.reloc.type. */
5303 static parse_operand_result
5304 parse_address_main (char **str
, int i
, int group_relocations
,
5305 group_reloc_type group_type
)
5310 if (skip_past_char (&p
, '[') == FAIL
)
5312 if (skip_past_char (&p
, '=') == FAIL
)
5314 /* Bare address - translate to PC-relative offset. */
5315 inst
.reloc
.pc_rel
= 1;
5316 inst
.operands
[i
].reg
= REG_PC
;
5317 inst
.operands
[i
].isreg
= 1;
5318 inst
.operands
[i
].preind
= 1;
5320 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5322 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5323 return PARSE_OPERAND_FAIL
;
5326 return PARSE_OPERAND_SUCCESS
;
5329 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5330 skip_whitespace (p
);
5332 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5334 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5335 return PARSE_OPERAND_FAIL
;
5337 inst
.operands
[i
].reg
= reg
;
5338 inst
.operands
[i
].isreg
= 1;
5340 if (skip_past_comma (&p
) == SUCCESS
)
5342 inst
.operands
[i
].preind
= 1;
5345 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5347 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5349 inst
.operands
[i
].imm
= reg
;
5350 inst
.operands
[i
].immisreg
= 1;
5352 if (skip_past_comma (&p
) == SUCCESS
)
5353 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5354 return PARSE_OPERAND_FAIL
;
5356 else if (skip_past_char (&p
, ':') == SUCCESS
)
5358 /* FIXME: '@' should be used here, but it's filtered out by generic
5359 code before we get to see it here. This may be subject to
5361 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5363 if (result
!= PARSE_OPERAND_SUCCESS
)
5368 if (inst
.operands
[i
].negative
)
5370 inst
.operands
[i
].negative
= 0;
5374 if (group_relocations
5375 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5377 struct group_reloc_table_entry
*entry
;
5379 /* Skip over the #: or : sequence. */
5385 /* Try to parse a group relocation. Anything else is an
5387 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5389 inst
.error
= _("unknown group relocation");
5390 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5393 /* We now have the group relocation table entry corresponding to
5394 the name in the assembler source. Next, we parse the
5396 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5397 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5399 /* Record the relocation type. */
5403 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5407 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5411 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5418 if (inst
.reloc
.type
== 0)
5420 inst
.error
= _("this group relocation is not allowed on this instruction");
5421 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5427 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5428 return PARSE_OPERAND_FAIL
;
5429 /* If the offset is 0, find out if it's a +0 or -0. */
5430 if (inst
.reloc
.exp
.X_op
== O_constant
5431 && inst
.reloc
.exp
.X_add_number
== 0)
5433 skip_whitespace (q
);
5437 skip_whitespace (q
);
5440 inst
.operands
[i
].negative
= 1;
5445 else if (skip_past_char (&p
, ':') == SUCCESS
)
5447 /* FIXME: '@' should be used here, but it's filtered out by generic code
5448 before we get to see it here. This may be subject to change. */
5449 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5451 if (result
!= PARSE_OPERAND_SUCCESS
)
5455 if (skip_past_char (&p
, ']') == FAIL
)
5457 inst
.error
= _("']' expected");
5458 return PARSE_OPERAND_FAIL
;
5461 if (skip_past_char (&p
, '!') == SUCCESS
)
5462 inst
.operands
[i
].writeback
= 1;
5464 else if (skip_past_comma (&p
) == SUCCESS
)
5466 if (skip_past_char (&p
, '{') == SUCCESS
)
5468 /* [Rn], {expr} - unindexed, with option */
5469 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5470 0, 255, TRUE
) == FAIL
)
5471 return PARSE_OPERAND_FAIL
;
5473 if (skip_past_char (&p
, '}') == FAIL
)
5475 inst
.error
= _("'}' expected at end of 'option' field");
5476 return PARSE_OPERAND_FAIL
;
5478 if (inst
.operands
[i
].preind
)
5480 inst
.error
= _("cannot combine index with option");
5481 return PARSE_OPERAND_FAIL
;
5484 return PARSE_OPERAND_SUCCESS
;
5488 inst
.operands
[i
].postind
= 1;
5489 inst
.operands
[i
].writeback
= 1;
5491 if (inst
.operands
[i
].preind
)
5493 inst
.error
= _("cannot combine pre- and post-indexing");
5494 return PARSE_OPERAND_FAIL
;
5498 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5500 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5502 /* We might be using the immediate for alignment already. If we
5503 are, OR the register number into the low-order bits. */
5504 if (inst
.operands
[i
].immisalign
)
5505 inst
.operands
[i
].imm
|= reg
;
5507 inst
.operands
[i
].imm
= reg
;
5508 inst
.operands
[i
].immisreg
= 1;
5510 if (skip_past_comma (&p
) == SUCCESS
)
5511 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5512 return PARSE_OPERAND_FAIL
;
5517 if (inst
.operands
[i
].negative
)
5519 inst
.operands
[i
].negative
= 0;
5522 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5523 return PARSE_OPERAND_FAIL
;
5524 /* If the offset is 0, find out if it's a +0 or -0. */
5525 if (inst
.reloc
.exp
.X_op
== O_constant
5526 && inst
.reloc
.exp
.X_add_number
== 0)
5528 skip_whitespace (q
);
5532 skip_whitespace (q
);
5535 inst
.operands
[i
].negative
= 1;
5541 /* If at this point neither .preind nor .postind is set, we have a
5542 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5543 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5545 inst
.operands
[i
].preind
= 1;
5546 inst
.reloc
.exp
.X_op
= O_constant
;
5547 inst
.reloc
.exp
.X_add_number
= 0;
5550 return PARSE_OPERAND_SUCCESS
;
5554 parse_address (char **str
, int i
)
5556 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5560 static parse_operand_result
5561 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5563 return parse_address_main (str
, i
, 1, type
);
5566 /* Parse an operand for a MOVW or MOVT instruction. */
5568 parse_half (char **str
)
5573 skip_past_char (&p
, '#');
5574 if (strncasecmp (p
, ":lower16:", 9) == 0)
5575 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5576 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5577 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5579 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5582 skip_whitespace (p
);
5585 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5588 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5590 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5592 inst
.error
= _("constant expression expected");
5595 if (inst
.reloc
.exp
.X_add_number
< 0
5596 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5598 inst
.error
= _("immediate value out of range");
5606 /* Miscellaneous. */
5608 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5609 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5611 parse_psr (char **str
, bfd_boolean lhs
)
5614 unsigned long psr_field
;
5615 const struct asm_psr
*psr
;
5617 bfd_boolean is_apsr
= FALSE
;
5618 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5620 /* PR gas/12698: If the user has specified -march=all then m_profile will
5621 be TRUE, but we want to ignore it in this case as we are building for any
5622 CPU type, including non-m variants. */
5623 if (selected_cpu
.core
== arm_arch_any
.core
)
5626 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5627 feature for ease of use and backwards compatibility. */
5629 if (strncasecmp (p
, "SPSR", 4) == 0)
5632 goto unsupported_psr
;
5634 psr_field
= SPSR_BIT
;
5636 else if (strncasecmp (p
, "CPSR", 4) == 0)
5639 goto unsupported_psr
;
5643 else if (strncasecmp (p
, "APSR", 4) == 0)
5645 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5646 and ARMv7-R architecture CPUs. */
5655 while (ISALNUM (*p
) || *p
== '_');
5657 if (strncasecmp (start
, "iapsr", 5) == 0
5658 || strncasecmp (start
, "eapsr", 5) == 0
5659 || strncasecmp (start
, "xpsr", 4) == 0
5660 || strncasecmp (start
, "psr", 3) == 0)
5661 p
= start
+ strcspn (start
, "rR") + 1;
5663 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5669 /* If APSR is being written, a bitfield may be specified. Note that
5670 APSR itself is handled above. */
5671 if (psr
->field
<= 3)
5673 psr_field
= psr
->field
;
5679 /* M-profile MSR instructions have the mask field set to "10", except
5680 *PSR variants which modify APSR, which may use a different mask (and
5681 have been handled already). Do that by setting the PSR_f field
5683 return psr
->field
| (lhs
? PSR_f
: 0);
5686 goto unsupported_psr
;
5692 /* A suffix follows. */
5698 while (ISALNUM (*p
) || *p
== '_');
5702 /* APSR uses a notation for bits, rather than fields. */
5703 unsigned int nzcvq_bits
= 0;
5704 unsigned int g_bit
= 0;
5707 for (bit
= start
; bit
!= p
; bit
++)
5709 switch (TOLOWER (*bit
))
5712 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5716 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5720 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5724 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5728 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5732 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5736 inst
.error
= _("unexpected bit specified after APSR");
5741 if (nzcvq_bits
== 0x1f)
5746 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5748 inst
.error
= _("selected processor does not "
5749 "support DSP extension");
5756 if ((nzcvq_bits
& 0x20) != 0
5757 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5758 || (g_bit
& 0x2) != 0)
5760 inst
.error
= _("bad bitmask specified after APSR");
5766 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5771 psr_field
|= psr
->field
;
5777 goto error
; /* Garbage after "[CS]PSR". */
5779 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5780 is deprecated, but allow it anyway. */
5784 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5787 else if (!m_profile
)
5788 /* These bits are never right for M-profile devices: don't set them
5789 (only code paths which read/write APSR reach here). */
5790 psr_field
|= (PSR_c
| PSR_f
);
5796 inst
.error
= _("selected processor does not support requested special "
5797 "purpose register");
5801 inst
.error
= _("flag for {c}psr instruction expected");
5805 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5806 value suitable for splatting into the AIF field of the instruction. */
5809 parse_cps_flags (char **str
)
5818 case '\0': case ',':
5821 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5822 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5823 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5826 inst
.error
= _("unrecognized CPS flag");
5831 if (saw_a_flag
== 0)
5833 inst
.error
= _("missing CPS flags");
5841 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5842 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5845 parse_endian_specifier (char **str
)
5850 if (strncasecmp (s
, "BE", 2))
5852 else if (strncasecmp (s
, "LE", 2))
5856 inst
.error
= _("valid endian specifiers are be or le");
5860 if (ISALNUM (s
[2]) || s
[2] == '_')
5862 inst
.error
= _("valid endian specifiers are be or le");
5867 return little_endian
;
5870 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5871 value suitable for poking into the rotate field of an sxt or sxta
5872 instruction, or FAIL on error. */
5875 parse_ror (char **str
)
5880 if (strncasecmp (s
, "ROR", 3) == 0)
5884 inst
.error
= _("missing rotation field after comma");
5888 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5893 case 0: *str
= s
; return 0x0;
5894 case 8: *str
= s
; return 0x1;
5895 case 16: *str
= s
; return 0x2;
5896 case 24: *str
= s
; return 0x3;
5899 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5904 /* Parse a conditional code (from conds[] below). The value returned is in the
5905 range 0 .. 14, or FAIL. */
5907 parse_cond (char **str
)
5910 const struct asm_cond
*c
;
5912 /* Condition codes are always 2 characters, so matching up to
5913 3 characters is sufficient. */
5918 while (ISALPHA (*q
) && n
< 3)
5920 cond
[n
] = TOLOWER (*q
);
5925 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5928 inst
.error
= _("condition required");
5936 /* If the given feature available in the selected CPU, mark it as used.
5937 Returns TRUE iff feature is available. */
5939 mark_feature_used (const arm_feature_set
*feature
)
5941 /* Ensure the option is valid on the current architecture. */
5942 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
5945 /* Add the appropriate architecture feature for the barrier option used.
5948 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
5950 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
5955 /* Parse an option for a barrier instruction. Returns the encoding for the
5958 parse_barrier (char **str
)
5961 const struct asm_barrier_opt
*o
;
5964 while (ISALPHA (*q
))
5967 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5972 if (!mark_feature_used (&o
->arch
))
5979 /* Parse the operands of a table branch instruction. Similar to a memory
5982 parse_tb (char **str
)
5987 if (skip_past_char (&p
, '[') == FAIL
)
5989 inst
.error
= _("'[' expected");
5993 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5995 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5998 inst
.operands
[0].reg
= reg
;
6000 if (skip_past_comma (&p
) == FAIL
)
6002 inst
.error
= _("',' expected");
6006 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6008 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6011 inst
.operands
[0].imm
= reg
;
6013 if (skip_past_comma (&p
) == SUCCESS
)
6015 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6017 if (inst
.reloc
.exp
.X_add_number
!= 1)
6019 inst
.error
= _("invalid shift");
6022 inst
.operands
[0].shifted
= 1;
6025 if (skip_past_char (&p
, ']') == FAIL
)
6027 inst
.error
= _("']' expected");
6034 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6035 information on the types the operands can take and how they are encoded.
6036 Up to four operands may be read; this function handles setting the
6037 ".present" field for each read operand itself.
6038 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6039 else returns FAIL. */
6042 parse_neon_mov (char **str
, int *which_operand
)
6044 int i
= *which_operand
, val
;
6045 enum arm_reg_type rtype
;
6047 struct neon_type_el optype
;
6049 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6051 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6052 inst
.operands
[i
].reg
= val
;
6053 inst
.operands
[i
].isscalar
= 1;
6054 inst
.operands
[i
].vectype
= optype
;
6055 inst
.operands
[i
++].present
= 1;
6057 if (skip_past_comma (&ptr
) == FAIL
)
6060 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6063 inst
.operands
[i
].reg
= val
;
6064 inst
.operands
[i
].isreg
= 1;
6065 inst
.operands
[i
].present
= 1;
6067 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6070 /* Cases 0, 1, 2, 3, 5 (D only). */
6071 if (skip_past_comma (&ptr
) == FAIL
)
6074 inst
.operands
[i
].reg
= val
;
6075 inst
.operands
[i
].isreg
= 1;
6076 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6077 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6078 inst
.operands
[i
].isvec
= 1;
6079 inst
.operands
[i
].vectype
= optype
;
6080 inst
.operands
[i
++].present
= 1;
6082 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6084 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6085 Case 13: VMOV <Sd>, <Rm> */
6086 inst
.operands
[i
].reg
= val
;
6087 inst
.operands
[i
].isreg
= 1;
6088 inst
.operands
[i
].present
= 1;
6090 if (rtype
== REG_TYPE_NQ
)
6092 first_error (_("can't use Neon quad register here"));
6095 else if (rtype
!= REG_TYPE_VFS
)
6098 if (skip_past_comma (&ptr
) == FAIL
)
6100 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6102 inst
.operands
[i
].reg
= val
;
6103 inst
.operands
[i
].isreg
= 1;
6104 inst
.operands
[i
].present
= 1;
6107 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6110 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6111 Case 1: VMOV<c><q> <Dd>, <Dm>
6112 Case 8: VMOV.F32 <Sd>, <Sm>
6113 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6115 inst
.operands
[i
].reg
= val
;
6116 inst
.operands
[i
].isreg
= 1;
6117 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6118 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6119 inst
.operands
[i
].isvec
= 1;
6120 inst
.operands
[i
].vectype
= optype
;
6121 inst
.operands
[i
].present
= 1;
6123 if (skip_past_comma (&ptr
) == SUCCESS
)
6128 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6131 inst
.operands
[i
].reg
= val
;
6132 inst
.operands
[i
].isreg
= 1;
6133 inst
.operands
[i
++].present
= 1;
6135 if (skip_past_comma (&ptr
) == FAIL
)
6138 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6141 inst
.operands
[i
].reg
= val
;
6142 inst
.operands
[i
].isreg
= 1;
6143 inst
.operands
[i
].present
= 1;
6146 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6147 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6148 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6149 Case 10: VMOV.F32 <Sd>, #<imm>
6150 Case 11: VMOV.F64 <Dd>, #<imm> */
6151 inst
.operands
[i
].immisfloat
= 1;
6152 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
6153 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6154 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6158 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6162 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6165 inst
.operands
[i
].reg
= val
;
6166 inst
.operands
[i
].isreg
= 1;
6167 inst
.operands
[i
++].present
= 1;
6169 if (skip_past_comma (&ptr
) == FAIL
)
6172 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6174 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6175 inst
.operands
[i
].reg
= val
;
6176 inst
.operands
[i
].isscalar
= 1;
6177 inst
.operands
[i
].present
= 1;
6178 inst
.operands
[i
].vectype
= optype
;
6180 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6182 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6183 inst
.operands
[i
].reg
= val
;
6184 inst
.operands
[i
].isreg
= 1;
6185 inst
.operands
[i
++].present
= 1;
6187 if (skip_past_comma (&ptr
) == FAIL
)
6190 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6193 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6197 inst
.operands
[i
].reg
= val
;
6198 inst
.operands
[i
].isreg
= 1;
6199 inst
.operands
[i
].isvec
= 1;
6200 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6201 inst
.operands
[i
].vectype
= optype
;
6202 inst
.operands
[i
].present
= 1;
6204 if (rtype
== REG_TYPE_VFS
)
6208 if (skip_past_comma (&ptr
) == FAIL
)
6210 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6213 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6216 inst
.operands
[i
].reg
= val
;
6217 inst
.operands
[i
].isreg
= 1;
6218 inst
.operands
[i
].isvec
= 1;
6219 inst
.operands
[i
].issingle
= 1;
6220 inst
.operands
[i
].vectype
= optype
;
6221 inst
.operands
[i
].present
= 1;
6224 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6228 inst
.operands
[i
].reg
= val
;
6229 inst
.operands
[i
].isreg
= 1;
6230 inst
.operands
[i
].isvec
= 1;
6231 inst
.operands
[i
].issingle
= 1;
6232 inst
.operands
[i
].vectype
= optype
;
6233 inst
.operands
[i
].present
= 1;
6238 first_error (_("parse error"));
6242 /* Successfully parsed the operands. Update args. */
6248 first_error (_("expected comma"));
6252 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6256 /* Use this macro when the operand constraints are different
6257 for ARM and THUMB (e.g. ldrd). */
6258 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6259 ((arm_operand) | ((thumb_operand) << 16))
6261 /* Matcher codes for parse_operands. */
6262 enum operand_parse_code
6264 OP_stop
, /* end of line */
6266 OP_RR
, /* ARM register */
6267 OP_RRnpc
, /* ARM register, not r15 */
6268 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6269 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6270 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6271 optional trailing ! */
6272 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6273 OP_RCP
, /* Coprocessor number */
6274 OP_RCN
, /* Coprocessor register */
6275 OP_RF
, /* FPA register */
6276 OP_RVS
, /* VFP single precision register */
6277 OP_RVD
, /* VFP double precision register (0..15) */
6278 OP_RND
, /* Neon double precision register (0..31) */
6279 OP_RNQ
, /* Neon quad precision register */
6280 OP_RVSD
, /* VFP single or double precision register */
6281 OP_RNDQ
, /* Neon double or quad precision register */
6282 OP_RNSDQ
, /* Neon single, double or quad precision register */
6283 OP_RNSC
, /* Neon scalar D[X] */
6284 OP_RVC
, /* VFP control register */
6285 OP_RMF
, /* Maverick F register */
6286 OP_RMD
, /* Maverick D register */
6287 OP_RMFX
, /* Maverick FX register */
6288 OP_RMDX
, /* Maverick DX register */
6289 OP_RMAX
, /* Maverick AX register */
6290 OP_RMDS
, /* Maverick DSPSC register */
6291 OP_RIWR
, /* iWMMXt wR register */
6292 OP_RIWC
, /* iWMMXt wC register */
6293 OP_RIWG
, /* iWMMXt wCG register */
6294 OP_RXA
, /* XScale accumulator register */
6296 OP_REGLST
, /* ARM register list */
6297 OP_VRSLST
, /* VFP single-precision register list */
6298 OP_VRDLST
, /* VFP double-precision register list */
6299 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6300 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6301 OP_NSTRLST
, /* Neon element/structure list */
6303 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6304 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6305 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6306 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6307 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6308 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6309 OP_VMOV
, /* Neon VMOV operands. */
6310 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6311 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6312 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6314 OP_I0
, /* immediate zero */
6315 OP_I7
, /* immediate value 0 .. 7 */
6316 OP_I15
, /* 0 .. 15 */
6317 OP_I16
, /* 1 .. 16 */
6318 OP_I16z
, /* 0 .. 16 */
6319 OP_I31
, /* 0 .. 31 */
6320 OP_I31w
, /* 0 .. 31, optional trailing ! */
6321 OP_I32
, /* 1 .. 32 */
6322 OP_I32z
, /* 0 .. 32 */
6323 OP_I63
, /* 0 .. 63 */
6324 OP_I63s
, /* -64 .. 63 */
6325 OP_I64
, /* 1 .. 64 */
6326 OP_I64z
, /* 0 .. 64 */
6327 OP_I255
, /* 0 .. 255 */
6329 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6330 OP_I7b
, /* 0 .. 7 */
6331 OP_I15b
, /* 0 .. 15 */
6332 OP_I31b
, /* 0 .. 31 */
6334 OP_SH
, /* shifter operand */
6335 OP_SHG
, /* shifter operand with possible group relocation */
6336 OP_ADDR
, /* Memory address expression (any mode) */
6337 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6338 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6339 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6340 OP_EXP
, /* arbitrary expression */
6341 OP_EXPi
, /* same, with optional immediate prefix */
6342 OP_EXPr
, /* same, with optional relocation suffix */
6343 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6345 OP_CPSF
, /* CPS flags */
6346 OP_ENDI
, /* Endianness specifier */
6347 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6348 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6349 OP_COND
, /* conditional code */
6350 OP_TB
, /* Table branch. */
6352 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6354 OP_RRnpc_I0
, /* ARM register or literal 0 */
6355 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6356 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6357 OP_RF_IF
, /* FPA register or immediate */
6358 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6359 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6361 /* Optional operands. */
6362 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6363 OP_oI31b
, /* 0 .. 31 */
6364 OP_oI32b
, /* 1 .. 32 */
6365 OP_oI32z
, /* 0 .. 32 */
6366 OP_oIffffb
, /* 0 .. 65535 */
6367 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6369 OP_oRR
, /* ARM register */
6370 OP_oRRnpc
, /* ARM register, not the PC */
6371 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6372 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6373 OP_oRND
, /* Optional Neon double precision register */
6374 OP_oRNQ
, /* Optional Neon quad precision register */
6375 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6376 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6377 OP_oSHll
, /* LSL immediate */
6378 OP_oSHar
, /* ASR immediate */
6379 OP_oSHllar
, /* LSL or ASR immediate */
6380 OP_oROR
, /* ROR 0/8/16/24 */
6381 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6383 /* Some pre-defined mixed (ARM/THUMB) operands. */
6384 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6385 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6386 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6388 OP_FIRST_OPTIONAL
= OP_oI7b
6391 /* Generic instruction operand parser. This does no encoding and no
6392 semantic validation; it merely squirrels values away in the inst
6393 structure. Returns SUCCESS or FAIL depending on whether the
6394 specified grammar matched. */
6396 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6398 unsigned const int *upat
= pattern
;
6399 char *backtrack_pos
= 0;
6400 const char *backtrack_error
= 0;
6401 int i
, val
= 0, backtrack_index
= 0;
6402 enum arm_reg_type rtype
;
6403 parse_operand_result result
;
6404 unsigned int op_parse_code
;
6406 #define po_char_or_fail(chr) \
6409 if (skip_past_char (&str, chr) == FAIL) \
6414 #define po_reg_or_fail(regtype) \
6417 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6418 & inst.operands[i].vectype); \
6421 first_error (_(reg_expected_msgs[regtype])); \
6424 inst.operands[i].reg = val; \
6425 inst.operands[i].isreg = 1; \
6426 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6427 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6428 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6429 || rtype == REG_TYPE_VFD \
6430 || rtype == REG_TYPE_NQ); \
6434 #define po_reg_or_goto(regtype, label) \
6437 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6438 & inst.operands[i].vectype); \
6442 inst.operands[i].reg = val; \
6443 inst.operands[i].isreg = 1; \
6444 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6445 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6446 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6447 || rtype == REG_TYPE_VFD \
6448 || rtype == REG_TYPE_NQ); \
6452 #define po_imm_or_fail(min, max, popt) \
6455 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6457 inst.operands[i].imm = val; \
6461 #define po_scalar_or_goto(elsz, label) \
6464 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6467 inst.operands[i].reg = val; \
6468 inst.operands[i].isscalar = 1; \
6472 #define po_misc_or_fail(expr) \
6480 #define po_misc_or_fail_no_backtrack(expr) \
6484 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6485 backtrack_pos = 0; \
6486 if (result != PARSE_OPERAND_SUCCESS) \
6491 #define po_barrier_or_imm(str) \
6494 val = parse_barrier (&str); \
6495 if (val == FAIL && ! ISALPHA (*str)) \
6498 /* ISB can only take SY as an option. */ \
6499 || ((inst.instruction & 0xf0) == 0x60 \
6502 inst.error = _("invalid barrier type"); \
6503 backtrack_pos = 0; \
6509 skip_whitespace (str
);
6511 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6513 op_parse_code
= upat
[i
];
6514 if (op_parse_code
>= 1<<16)
6515 op_parse_code
= thumb
? (op_parse_code
>> 16)
6516 : (op_parse_code
& ((1<<16)-1));
6518 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6520 /* Remember where we are in case we need to backtrack. */
6521 gas_assert (!backtrack_pos
);
6522 backtrack_pos
= str
;
6523 backtrack_error
= inst
.error
;
6524 backtrack_index
= i
;
6527 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6528 po_char_or_fail (',');
6530 switch (op_parse_code
)
6538 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6539 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6540 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6541 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6542 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6543 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6545 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6547 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6549 /* Also accept generic coprocessor regs for unknown registers. */
6551 po_reg_or_fail (REG_TYPE_CN
);
6553 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6554 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6555 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6556 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6557 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6558 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6559 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6560 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6561 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6562 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6564 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6566 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6567 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6569 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6571 /* Neon scalar. Using an element size of 8 means that some invalid
6572 scalars are accepted here, so deal with those in later code. */
6573 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6577 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6580 po_imm_or_fail (0, 0, TRUE
);
6585 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6590 po_scalar_or_goto (8, try_rr
);
6593 po_reg_or_fail (REG_TYPE_RN
);
6599 po_scalar_or_goto (8, try_nsdq
);
6602 po_reg_or_fail (REG_TYPE_NSDQ
);
6608 po_scalar_or_goto (8, try_ndq
);
6611 po_reg_or_fail (REG_TYPE_NDQ
);
6617 po_scalar_or_goto (8, try_vfd
);
6620 po_reg_or_fail (REG_TYPE_VFD
);
6625 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6626 not careful then bad things might happen. */
6627 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6632 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6635 /* There's a possibility of getting a 64-bit immediate here, so
6636 we need special handling. */
6637 if (parse_big_immediate (&str
, i
) == FAIL
)
6639 inst
.error
= _("immediate value is out of range");
6647 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6650 po_imm_or_fail (0, 63, TRUE
);
6655 po_char_or_fail ('[');
6656 po_reg_or_fail (REG_TYPE_RN
);
6657 po_char_or_fail (']');
6663 po_reg_or_fail (REG_TYPE_RN
);
6664 if (skip_past_char (&str
, '!') == SUCCESS
)
6665 inst
.operands
[i
].writeback
= 1;
6669 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6670 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6671 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6672 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6673 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6674 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6675 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6676 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6677 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6678 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6679 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6680 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6682 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6684 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6685 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6687 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6688 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6689 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6690 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6692 /* Immediate variants */
6694 po_char_or_fail ('{');
6695 po_imm_or_fail (0, 255, TRUE
);
6696 po_char_or_fail ('}');
6700 /* The expression parser chokes on a trailing !, so we have
6701 to find it first and zap it. */
6704 while (*s
&& *s
!= ',')
6709 inst
.operands
[i
].writeback
= 1;
6711 po_imm_or_fail (0, 31, TRUE
);
6719 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6724 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6729 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6731 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6733 val
= parse_reloc (&str
);
6736 inst
.error
= _("unrecognized relocation suffix");
6739 else if (val
!= BFD_RELOC_UNUSED
)
6741 inst
.operands
[i
].imm
= val
;
6742 inst
.operands
[i
].hasreloc
= 1;
6747 /* Operand for MOVW or MOVT. */
6749 po_misc_or_fail (parse_half (&str
));
6752 /* Register or expression. */
6753 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6754 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6756 /* Register or immediate. */
6757 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6758 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6760 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6762 if (!is_immediate_prefix (*str
))
6765 val
= parse_fpa_immediate (&str
);
6768 /* FPA immediates are encoded as registers 8-15.
6769 parse_fpa_immediate has already applied the offset. */
6770 inst
.operands
[i
].reg
= val
;
6771 inst
.operands
[i
].isreg
= 1;
6774 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6775 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6777 /* Two kinds of register. */
6780 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6782 || (rege
->type
!= REG_TYPE_MMXWR
6783 && rege
->type
!= REG_TYPE_MMXWC
6784 && rege
->type
!= REG_TYPE_MMXWCG
))
6786 inst
.error
= _("iWMMXt data or control register expected");
6789 inst
.operands
[i
].reg
= rege
->number
;
6790 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6796 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6798 || (rege
->type
!= REG_TYPE_MMXWC
6799 && rege
->type
!= REG_TYPE_MMXWCG
))
6801 inst
.error
= _("iWMMXt control register expected");
6804 inst
.operands
[i
].reg
= rege
->number
;
6805 inst
.operands
[i
].isreg
= 1;
6810 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6811 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6812 case OP_oROR
: val
= parse_ror (&str
); break;
6813 case OP_COND
: val
= parse_cond (&str
); break;
6814 case OP_oBARRIER_I15
:
6815 po_barrier_or_imm (str
); break;
6817 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6823 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6824 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6826 inst
.error
= _("Banked registers are not available with this "
6832 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6836 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6839 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6841 if (strncasecmp (str
, "APSR_", 5) == 0)
6848 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6849 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6850 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6851 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6852 default: found
= 16;
6856 inst
.operands
[i
].isvec
= 1;
6857 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6858 inst
.operands
[i
].reg
= REG_PC
;
6865 po_misc_or_fail (parse_tb (&str
));
6868 /* Register lists. */
6870 val
= parse_reg_list (&str
);
6873 inst
.operands
[1].writeback
= 1;
6879 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6883 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6887 /* Allow Q registers too. */
6888 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6893 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6895 inst
.operands
[i
].issingle
= 1;
6900 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6905 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6906 &inst
.operands
[i
].vectype
);
6909 /* Addressing modes */
6911 po_misc_or_fail (parse_address (&str
, i
));
6915 po_misc_or_fail_no_backtrack (
6916 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6920 po_misc_or_fail_no_backtrack (
6921 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6925 po_misc_or_fail_no_backtrack (
6926 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6930 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6934 po_misc_or_fail_no_backtrack (
6935 parse_shifter_operand_group_reloc (&str
, i
));
6939 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6943 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6947 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6951 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6954 /* Various value-based sanity checks and shared operations. We
6955 do not signal immediate failures for the register constraints;
6956 this allows a syntax error to take precedence. */
6957 switch (op_parse_code
)
6965 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6966 inst
.error
= BAD_PC
;
6971 if (inst
.operands
[i
].isreg
)
6973 if (inst
.operands
[i
].reg
== REG_PC
)
6974 inst
.error
= BAD_PC
;
6975 else if (inst
.operands
[i
].reg
== REG_SP
)
6976 inst
.error
= BAD_SP
;
6981 if (inst
.operands
[i
].isreg
6982 && inst
.operands
[i
].reg
== REG_PC
6983 && (inst
.operands
[i
].writeback
|| thumb
))
6984 inst
.error
= BAD_PC
;
6993 case OP_oBARRIER_I15
:
7002 inst
.operands
[i
].imm
= val
;
7009 /* If we get here, this operand was successfully parsed. */
7010 inst
.operands
[i
].present
= 1;
7014 inst
.error
= BAD_ARGS
;
7019 /* The parse routine should already have set inst.error, but set a
7020 default here just in case. */
7022 inst
.error
= _("syntax error");
7026 /* Do not backtrack over a trailing optional argument that
7027 absorbed some text. We will only fail again, with the
7028 'garbage following instruction' error message, which is
7029 probably less helpful than the current one. */
7030 if (backtrack_index
== i
&& backtrack_pos
!= str
7031 && upat
[i
+1] == OP_stop
)
7034 inst
.error
= _("syntax error");
7038 /* Try again, skipping the optional argument at backtrack_pos. */
7039 str
= backtrack_pos
;
7040 inst
.error
= backtrack_error
;
7041 inst
.operands
[backtrack_index
].present
= 0;
7042 i
= backtrack_index
;
7046 /* Check that we have parsed all the arguments. */
7047 if (*str
!= '\0' && !inst
.error
)
7048 inst
.error
= _("garbage following instruction");
7050 return inst
.error
? FAIL
: SUCCESS
;
7053 #undef po_char_or_fail
7054 #undef po_reg_or_fail
7055 #undef po_reg_or_goto
7056 #undef po_imm_or_fail
7057 #undef po_scalar_or_fail
7058 #undef po_barrier_or_imm
7060 /* Shorthand macro for instruction encoding functions issuing errors. */
7061 #define constraint(expr, err) \
7072 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7073 instructions are unpredictable if these registers are used. This
7074 is the BadReg predicate in ARM's Thumb-2 documentation. */
7075 #define reject_bad_reg(reg) \
7077 if (reg == REG_SP || reg == REG_PC) \
7079 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7084 /* If REG is R13 (the stack pointer), warn that its use is
7086 #define warn_deprecated_sp(reg) \
7088 if (warn_on_deprecated && reg == REG_SP) \
7089 as_warn (_("use of r13 is deprecated")); \
7092 /* Functions for operand encoding. ARM, then Thumb. */
7094 #define rotate_left(v, n) (v << n | v >> (32 - n))
7096 /* If VAL can be encoded in the immediate field of an ARM instruction,
7097 return the encoded form. Otherwise, return FAIL. */
7100 encode_arm_immediate (unsigned int val
)
7104 for (i
= 0; i
< 32; i
+= 2)
7105 if ((a
= rotate_left (val
, i
)) <= 0xff)
7106 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7111 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7112 return the encoded form. Otherwise, return FAIL. */
7114 encode_thumb32_immediate (unsigned int val
)
7121 for (i
= 1; i
<= 24; i
++)
7124 if ((val
& ~(0xff << i
)) == 0)
7125 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7129 if (val
== ((a
<< 16) | a
))
7131 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7135 if (val
== ((a
<< 16) | a
))
7136 return 0x200 | (a
>> 8);
7140 /* Encode a VFP SP or DP register number into inst.instruction. */
7143 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7145 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7148 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7151 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7154 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7159 first_error (_("D register out of range for selected VFP version"));
7167 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7171 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7175 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7179 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7183 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7187 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7195 /* Encode a <shift> in an ARM-format instruction. The immediate,
7196 if any, is handled by md_apply_fix. */
7198 encode_arm_shift (int i
)
7200 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7201 inst
.instruction
|= SHIFT_ROR
<< 5;
7204 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7205 if (inst
.operands
[i
].immisreg
)
7207 inst
.instruction
|= SHIFT_BY_REG
;
7208 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7211 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7216 encode_arm_shifter_operand (int i
)
7218 if (inst
.operands
[i
].isreg
)
7220 inst
.instruction
|= inst
.operands
[i
].reg
;
7221 encode_arm_shift (i
);
7225 inst
.instruction
|= INST_IMMEDIATE
;
7226 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7227 inst
.instruction
|= inst
.operands
[i
].imm
;
7231 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7233 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7236 Generate an error if the operand is not a register. */
7237 constraint (!inst
.operands
[i
].isreg
,
7238 _("Instruction does not support =N addresses"));
7240 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7242 if (inst
.operands
[i
].preind
)
7246 inst
.error
= _("instruction does not accept preindexed addressing");
7249 inst
.instruction
|= PRE_INDEX
;
7250 if (inst
.operands
[i
].writeback
)
7251 inst
.instruction
|= WRITE_BACK
;
7254 else if (inst
.operands
[i
].postind
)
7256 gas_assert (inst
.operands
[i
].writeback
);
7258 inst
.instruction
|= WRITE_BACK
;
7260 else /* unindexed - only for coprocessor */
7262 inst
.error
= _("instruction does not accept unindexed addressing");
7266 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7267 && (((inst
.instruction
& 0x000f0000) >> 16)
7268 == ((inst
.instruction
& 0x0000f000) >> 12)))
7269 as_warn ((inst
.instruction
& LOAD_BIT
)
7270 ? _("destination register same as write-back base")
7271 : _("source register same as write-back base"));
7274 /* inst.operands[i] was set up by parse_address. Encode it into an
7275 ARM-format mode 2 load or store instruction. If is_t is true,
7276 reject forms that cannot be used with a T instruction (i.e. not
7279 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7281 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7283 encode_arm_addr_mode_common (i
, is_t
);
7285 if (inst
.operands
[i
].immisreg
)
7287 constraint ((inst
.operands
[i
].imm
== REG_PC
7288 || (is_pc
&& inst
.operands
[i
].writeback
)),
7290 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7291 inst
.instruction
|= inst
.operands
[i
].imm
;
7292 if (!inst
.operands
[i
].negative
)
7293 inst
.instruction
|= INDEX_UP
;
7294 if (inst
.operands
[i
].shifted
)
7296 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7297 inst
.instruction
|= SHIFT_ROR
<< 5;
7300 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7301 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7305 else /* immediate offset in inst.reloc */
7307 if (is_pc
&& !inst
.reloc
.pc_rel
)
7309 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7311 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7312 cannot use PC in addressing.
7313 PC cannot be used in writeback addressing, either. */
7314 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7317 /* Use of PC in str is deprecated for ARMv7. */
7318 if (warn_on_deprecated
7320 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7321 as_warn (_("use of PC in this instruction is deprecated"));
7324 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7326 /* Prefer + for zero encoded value. */
7327 if (!inst
.operands
[i
].negative
)
7328 inst
.instruction
|= INDEX_UP
;
7329 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7334 /* inst.operands[i] was set up by parse_address. Encode it into an
7335 ARM-format mode 3 load or store instruction. Reject forms that
7336 cannot be used with such instructions. If is_t is true, reject
7337 forms that cannot be used with a T instruction (i.e. not
7340 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7342 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7344 inst
.error
= _("instruction does not accept scaled register index");
7348 encode_arm_addr_mode_common (i
, is_t
);
7350 if (inst
.operands
[i
].immisreg
)
7352 constraint ((inst
.operands
[i
].imm
== REG_PC
7353 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7355 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7357 inst
.instruction
|= inst
.operands
[i
].imm
;
7358 if (!inst
.operands
[i
].negative
)
7359 inst
.instruction
|= INDEX_UP
;
7361 else /* immediate offset in inst.reloc */
7363 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7364 && inst
.operands
[i
].writeback
),
7366 inst
.instruction
|= HWOFFSET_IMM
;
7367 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7369 /* Prefer + for zero encoded value. */
7370 if (!inst
.operands
[i
].negative
)
7371 inst
.instruction
|= INDEX_UP
;
7373 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7378 /* inst.operands[i] was set up by parse_address. Encode it into an
7379 ARM-format instruction. Reject all forms which cannot be encoded
7380 into a coprocessor load/store instruction. If wb_ok is false,
7381 reject use of writeback; if unind_ok is false, reject use of
7382 unindexed addressing. If reloc_override is not 0, use it instead
7383 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7384 (in which case it is preserved). */
7387 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7389 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7391 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7393 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7395 gas_assert (!inst
.operands
[i
].writeback
);
7398 inst
.error
= _("instruction does not support unindexed addressing");
7401 inst
.instruction
|= inst
.operands
[i
].imm
;
7402 inst
.instruction
|= INDEX_UP
;
7406 if (inst
.operands
[i
].preind
)
7407 inst
.instruction
|= PRE_INDEX
;
7409 if (inst
.operands
[i
].writeback
)
7411 if (inst
.operands
[i
].reg
== REG_PC
)
7413 inst
.error
= _("pc may not be used with write-back");
7418 inst
.error
= _("instruction does not support writeback");
7421 inst
.instruction
|= WRITE_BACK
;
7425 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7426 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7427 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7428 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7431 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7433 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7436 /* Prefer + for zero encoded value. */
7437 if (!inst
.operands
[i
].negative
)
7438 inst
.instruction
|= INDEX_UP
;
7443 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7444 Determine whether it can be performed with a move instruction; if
7445 it can, convert inst.instruction to that move instruction and
7446 return TRUE; if it can't, convert inst.instruction to a literal-pool
7447 load and return FALSE. If this is not a valid thing to do in the
7448 current context, set inst.error and return TRUE.
7450 inst.operands[i] describes the destination register. */
7453 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7458 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7462 if ((inst
.instruction
& tbit
) == 0)
7464 inst
.error
= _("invalid pseudo operation");
7467 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7469 inst
.error
= _("constant expression expected");
7472 if (inst
.reloc
.exp
.X_op
== O_constant
)
7476 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7478 /* This can be done with a mov(1) instruction. */
7479 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7480 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7486 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7489 /* This can be done with a mov instruction. */
7490 inst
.instruction
&= LITERAL_MASK
;
7491 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7492 inst
.instruction
|= value
& 0xfff;
7496 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7499 /* This can be done with a mvn instruction. */
7500 inst
.instruction
&= LITERAL_MASK
;
7501 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7502 inst
.instruction
|= value
& 0xfff;
7508 if (add_to_lit_pool () == FAIL
)
7510 inst
.error
= _("literal pool insertion failed");
7513 inst
.operands
[1].reg
= REG_PC
;
7514 inst
.operands
[1].isreg
= 1;
7515 inst
.operands
[1].preind
= 1;
7516 inst
.reloc
.pc_rel
= 1;
7517 inst
.reloc
.type
= (thumb_p
7518 ? BFD_RELOC_ARM_THUMB_OFFSET
7520 ? BFD_RELOC_ARM_HWLITERAL
7521 : BFD_RELOC_ARM_LITERAL
));
7525 /* Functions for instruction encoding, sorted by sub-architecture.
7526 First some generics; their names are taken from the conventional
7527 bit positions for register arguments in ARM format instructions. */
7537 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7544 inst
.instruction
|= inst
.operands
[1].reg
;
7550 inst
.instruction
|= inst
.operands
[0].reg
;
7551 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7557 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7558 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7564 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7565 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7569 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
7571 if (ARM_CPU_IS_ANY (cpu_variant
))
7573 as_warn ("%s", msg
);
7576 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
7588 unsigned Rn
= inst
.operands
[2].reg
;
7589 /* Enforce restrictions on SWP instruction. */
7590 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7592 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7593 _("Rn must not overlap other operands"));
7595 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7597 if (!check_obsolete (&arm_ext_v8
,
7598 _("swp{b} use is obsoleted for ARMv8 and later"))
7599 && warn_on_deprecated
7600 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
7601 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7604 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7605 inst
.instruction
|= inst
.operands
[1].reg
;
7606 inst
.instruction
|= Rn
<< 16;
7612 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7613 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7614 inst
.instruction
|= inst
.operands
[2].reg
;
7620 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7621 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7622 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7623 || inst
.reloc
.exp
.X_add_number
!= 0),
7625 inst
.instruction
|= inst
.operands
[0].reg
;
7626 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7627 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7633 inst
.instruction
|= inst
.operands
[0].imm
;
7639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7640 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7643 /* ARM instructions, in alphabetical order by function name (except
7644 that wrapper functions appear immediately after the function they
7647 /* This is a pseudo-op of the form "adr rd, label" to be converted
7648 into a relative address of the form "add rd, pc, #label-.-8". */
7653 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7655 /* Frag hacking will turn this into a sub instruction if the offset turns
7656 out to be negative. */
7657 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7658 inst
.reloc
.pc_rel
= 1;
7659 inst
.reloc
.exp
.X_add_number
-= 8;
7662 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7663 into a relative address of the form:
7664 add rd, pc, #low(label-.-8)"
7665 add rd, rd, #high(label-.-8)" */
7670 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7672 /* Frag hacking will turn this into a sub instruction if the offset turns
7673 out to be negative. */
7674 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7675 inst
.reloc
.pc_rel
= 1;
7676 inst
.size
= INSN_SIZE
* 2;
7677 inst
.reloc
.exp
.X_add_number
-= 8;
7683 if (!inst
.operands
[1].present
)
7684 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7686 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7687 encode_arm_shifter_operand (2);
7693 if (inst
.operands
[0].present
)
7694 inst
.instruction
|= inst
.operands
[0].imm
;
7696 inst
.instruction
|= 0xf;
7702 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7703 constraint (msb
> 32, _("bit-field extends past end of register"));
7704 /* The instruction encoding stores the LSB and MSB,
7705 not the LSB and width. */
7706 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7707 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7708 inst
.instruction
|= (msb
- 1) << 16;
7716 /* #0 in second position is alternative syntax for bfc, which is
7717 the same instruction but with REG_PC in the Rm field. */
7718 if (!inst
.operands
[1].isreg
)
7719 inst
.operands
[1].reg
= REG_PC
;
7721 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7722 constraint (msb
> 32, _("bit-field extends past end of register"));
7723 /* The instruction encoding stores the LSB and MSB,
7724 not the LSB and width. */
7725 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7726 inst
.instruction
|= inst
.operands
[1].reg
;
7727 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7728 inst
.instruction
|= (msb
- 1) << 16;
7734 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7735 _("bit-field extends past end of register"));
7736 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7737 inst
.instruction
|= inst
.operands
[1].reg
;
7738 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7739 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7742 /* ARM V5 breakpoint instruction (argument parse)
7743 BKPT <16 bit unsigned immediate>
7744 Instruction is not conditional.
7745 The bit pattern given in insns[] has the COND_ALWAYS condition,
7746 and it is an error if the caller tried to override that. */
7751 /* Top 12 of 16 bits to bits 19:8. */
7752 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7754 /* Bottom 4 of 16 bits to bits 3:0. */
7755 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7759 encode_branch (int default_reloc
)
7761 if (inst
.operands
[0].hasreloc
)
7763 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7764 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7765 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7766 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7767 ? BFD_RELOC_ARM_PLT32
7768 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7771 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7772 inst
.reloc
.pc_rel
= 1;
7779 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7780 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7783 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7790 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7792 if (inst
.cond
== COND_ALWAYS
)
7793 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7795 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7799 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7802 /* ARM V5 branch-link-exchange instruction (argument parse)
7803 BLX <target_addr> ie BLX(1)
7804 BLX{<condition>} <Rm> ie BLX(2)
7805 Unfortunately, there are two different opcodes for this mnemonic.
7806 So, the insns[].value is not used, and the code here zaps values
7807 into inst.instruction.
7808 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7813 if (inst
.operands
[0].isreg
)
7815 /* Arg is a register; the opcode provided by insns[] is correct.
7816 It is not illegal to do "blx pc", just useless. */
7817 if (inst
.operands
[0].reg
== REG_PC
)
7818 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7820 inst
.instruction
|= inst
.operands
[0].reg
;
7824 /* Arg is an address; this instruction cannot be executed
7825 conditionally, and the opcode must be adjusted.
7826 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7827 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7828 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7829 inst
.instruction
= 0xfa000000;
7830 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7837 bfd_boolean want_reloc
;
7839 if (inst
.operands
[0].reg
== REG_PC
)
7840 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7842 inst
.instruction
|= inst
.operands
[0].reg
;
7843 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7844 it is for ARMv4t or earlier. */
7845 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7846 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7850 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7855 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7859 /* ARM v5TEJ. Jump to Jazelle code. */
7864 if (inst
.operands
[0].reg
== REG_PC
)
7865 as_tsktsk (_("use of r15 in bxj is not really useful"));
7867 inst
.instruction
|= inst
.operands
[0].reg
;
7870 /* Co-processor data operation:
7871 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7872 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7876 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7877 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7878 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7879 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7880 inst
.instruction
|= inst
.operands
[4].reg
;
7881 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7887 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7888 encode_arm_shifter_operand (1);
7891 /* Transfer between coprocessor and ARM registers.
7892 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7897 No special properties. */
7899 struct deprecated_coproc_regs_s
7906 arm_feature_set deprecated
;
7907 arm_feature_set obsoleted
;
7908 const char *dep_msg
;
7909 const char *obs_msg
;
7912 #define DEPR_ACCESS_V8 \
7913 N_("This coprocessor register access is deprecated in ARMv8")
7915 /* Table of all deprecated coprocessor registers. */
7916 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
7918 {15, 0, 7, 10, 5, /* CP15DMB. */
7919 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7920 DEPR_ACCESS_V8
, NULL
},
7921 {15, 0, 7, 10, 4, /* CP15DSB. */
7922 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7923 DEPR_ACCESS_V8
, NULL
},
7924 {15, 0, 7, 5, 4, /* CP15ISB. */
7925 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7926 DEPR_ACCESS_V8
, NULL
},
7927 {14, 6, 1, 0, 0, /* TEEHBR. */
7928 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7929 DEPR_ACCESS_V8
, NULL
},
7930 {14, 6, 0, 0, 0, /* TEECR. */
7931 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7932 DEPR_ACCESS_V8
, NULL
},
7935 #undef DEPR_ACCESS_V8
7937 static const size_t deprecated_coproc_reg_count
=
7938 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
7946 Rd
= inst
.operands
[2].reg
;
7949 if (inst
.instruction
== 0xee000010
7950 || inst
.instruction
== 0xfe000010)
7952 reject_bad_reg (Rd
);
7955 constraint (Rd
== REG_SP
, BAD_SP
);
7960 if (inst
.instruction
== 0xe000010)
7961 constraint (Rd
== REG_PC
, BAD_PC
);
7964 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
7966 const struct deprecated_coproc_regs_s
*r
=
7967 deprecated_coproc_regs
+ i
;
7969 if (inst
.operands
[0].reg
== r
->cp
7970 && inst
.operands
[1].imm
== r
->opc1
7971 && inst
.operands
[3].reg
== r
->crn
7972 && inst
.operands
[4].reg
== r
->crm
7973 && inst
.operands
[5].imm
== r
->opc2
)
7975 if (! ARM_CPU_IS_ANY (cpu_variant
)
7976 && warn_on_deprecated
7977 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
7978 as_warn ("%s", r
->dep_msg
);
7982 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7983 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7984 inst
.instruction
|= Rd
<< 12;
7985 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7986 inst
.instruction
|= inst
.operands
[4].reg
;
7987 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7990 /* Transfer between coprocessor register and pair of ARM registers.
7991 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7996 Two XScale instructions are special cases of these:
7998 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7999 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8001 Result unpredictable if Rd or Rn is R15. */
8008 Rd
= inst
.operands
[2].reg
;
8009 Rn
= inst
.operands
[3].reg
;
8013 reject_bad_reg (Rd
);
8014 reject_bad_reg (Rn
);
8018 constraint (Rd
== REG_PC
, BAD_PC
);
8019 constraint (Rn
== REG_PC
, BAD_PC
);
8022 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8023 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8024 inst
.instruction
|= Rd
<< 12;
8025 inst
.instruction
|= Rn
<< 16;
8026 inst
.instruction
|= inst
.operands
[4].reg
;
8032 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8033 if (inst
.operands
[1].present
)
8035 inst
.instruction
|= CPSI_MMOD
;
8036 inst
.instruction
|= inst
.operands
[1].imm
;
8043 inst
.instruction
|= inst
.operands
[0].imm
;
8049 unsigned Rd
, Rn
, Rm
;
8051 Rd
= inst
.operands
[0].reg
;
8052 Rn
= (inst
.operands
[1].present
8053 ? inst
.operands
[1].reg
: Rd
);
8054 Rm
= inst
.operands
[2].reg
;
8056 constraint ((Rd
== REG_PC
), BAD_PC
);
8057 constraint ((Rn
== REG_PC
), BAD_PC
);
8058 constraint ((Rm
== REG_PC
), BAD_PC
);
8060 inst
.instruction
|= Rd
<< 16;
8061 inst
.instruction
|= Rn
<< 0;
8062 inst
.instruction
|= Rm
<< 8;
8068 /* There is no IT instruction in ARM mode. We
8069 process it to do the validation as if in
8070 thumb mode, just in case the code gets
8071 assembled for thumb using the unified syntax. */
8076 set_it_insn_type (IT_INSN
);
8077 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8078 now_it
.cc
= inst
.operands
[0].imm
;
8082 /* If there is only one register in the register list,
8083 then return its register number. Otherwise return -1. */
8085 only_one_reg_in_list (int range
)
8087 int i
= ffs (range
) - 1;
8088 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8092 encode_ldmstm(int from_push_pop_mnem
)
8094 int base_reg
= inst
.operands
[0].reg
;
8095 int range
= inst
.operands
[1].imm
;
8098 inst
.instruction
|= base_reg
<< 16;
8099 inst
.instruction
|= range
;
8101 if (inst
.operands
[1].writeback
)
8102 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8104 if (inst
.operands
[0].writeback
)
8106 inst
.instruction
|= WRITE_BACK
;
8107 /* Check for unpredictable uses of writeback. */
8108 if (inst
.instruction
& LOAD_BIT
)
8110 /* Not allowed in LDM type 2. */
8111 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8112 && ((range
& (1 << REG_PC
)) == 0))
8113 as_warn (_("writeback of base register is UNPREDICTABLE"));
8114 /* Only allowed if base reg not in list for other types. */
8115 else if (range
& (1 << base_reg
))
8116 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8120 /* Not allowed for type 2. */
8121 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8122 as_warn (_("writeback of base register is UNPREDICTABLE"));
8123 /* Only allowed if base reg not in list, or first in list. */
8124 else if ((range
& (1 << base_reg
))
8125 && (range
& ((1 << base_reg
) - 1)))
8126 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8130 /* If PUSH/POP has only one register, then use the A2 encoding. */
8131 one_reg
= only_one_reg_in_list (range
);
8132 if (from_push_pop_mnem
&& one_reg
>= 0)
8134 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8136 inst
.instruction
&= A_COND_MASK
;
8137 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8138 inst
.instruction
|= one_reg
<< 12;
8145 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8148 /* ARMv5TE load-consecutive (argument parse)
8157 constraint (inst
.operands
[0].reg
% 2 != 0,
8158 _("first transfer register must be even"));
8159 constraint (inst
.operands
[1].present
8160 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8161 _("can only transfer two consecutive registers"));
8162 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8163 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8165 if (!inst
.operands
[1].present
)
8166 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8168 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8169 register and the first register written; we have to diagnose
8170 overlap between the base and the second register written here. */
8172 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8173 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8174 as_warn (_("base register written back, and overlaps "
8175 "second transfer register"));
8177 if (!(inst
.instruction
& V4_STR_BIT
))
8179 /* For an index-register load, the index register must not overlap the
8180 destination (even if not write-back). */
8181 if (inst
.operands
[2].immisreg
8182 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8183 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8184 as_warn (_("index register overlaps transfer register"));
8186 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8187 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8193 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8194 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8195 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8196 || inst
.operands
[1].negative
8197 /* This can arise if the programmer has written
8199 or if they have mistakenly used a register name as the last
8202 It is very difficult to distinguish between these two cases
8203 because "rX" might actually be a label. ie the register
8204 name has been occluded by a symbol of the same name. So we
8205 just generate a general 'bad addressing mode' type error
8206 message and leave it up to the programmer to discover the
8207 true cause and fix their mistake. */
8208 || (inst
.operands
[1].reg
== REG_PC
),
8211 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8212 || inst
.reloc
.exp
.X_add_number
!= 0,
8213 _("offset must be zero in ARM encoding"));
8215 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8217 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8218 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8219 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8225 constraint (inst
.operands
[0].reg
% 2 != 0,
8226 _("even register required"));
8227 constraint (inst
.operands
[1].present
8228 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8229 _("can only load two consecutive registers"));
8230 /* If op 1 were present and equal to PC, this function wouldn't
8231 have been called in the first place. */
8232 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8235 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8238 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8239 which is not a multiple of four is UNPREDICTABLE. */
8241 check_ldr_r15_aligned (void)
8243 constraint (!(inst
.operands
[1].immisreg
)
8244 && (inst
.operands
[0].reg
== REG_PC
8245 && inst
.operands
[1].reg
== REG_PC
8246 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8247 _("ldr to register 15 must be 4-byte alligned"));
8253 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8254 if (!inst
.operands
[1].isreg
)
8255 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
8257 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8258 check_ldr_r15_aligned ();
8264 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8266 if (inst
.operands
[1].preind
)
8268 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8269 || inst
.reloc
.exp
.X_add_number
!= 0,
8270 _("this instruction requires a post-indexed address"));
8272 inst
.operands
[1].preind
= 0;
8273 inst
.operands
[1].postind
= 1;
8274 inst
.operands
[1].writeback
= 1;
8276 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8277 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8280 /* Halfword and signed-byte load/store operations. */
8285 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8287 if (!inst
.operands
[1].isreg
)
8288 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
8290 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8296 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8298 if (inst
.operands
[1].preind
)
8300 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8301 || inst
.reloc
.exp
.X_add_number
!= 0,
8302 _("this instruction requires a post-indexed address"));
8304 inst
.operands
[1].preind
= 0;
8305 inst
.operands
[1].postind
= 1;
8306 inst
.operands
[1].writeback
= 1;
8308 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8309 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8312 /* Co-processor register load/store.
8313 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8317 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8318 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8319 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8325 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8326 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8327 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8328 && !(inst
.instruction
& 0x00400000))
8329 as_tsktsk (_("Rd and Rm should be different in mla"));
8331 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8332 inst
.instruction
|= inst
.operands
[1].reg
;
8333 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8334 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8340 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8341 encode_arm_shifter_operand (1);
8344 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8351 top
= (inst
.instruction
& 0x00400000) != 0;
8352 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8353 _(":lower16: not allowed this instruction"));
8354 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8355 _(":upper16: not allowed instruction"));
8356 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8357 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8359 imm
= inst
.reloc
.exp
.X_add_number
;
8360 /* The value is in two pieces: 0:11, 16:19. */
8361 inst
.instruction
|= (imm
& 0x00000fff);
8362 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8366 static void do_vfp_nsyn_opcode (const char *);
8369 do_vfp_nsyn_mrs (void)
8371 if (inst
.operands
[0].isvec
)
8373 if (inst
.operands
[1].reg
!= 1)
8374 first_error (_("operand 1 must be FPSCR"));
8375 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8376 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8377 do_vfp_nsyn_opcode ("fmstat");
8379 else if (inst
.operands
[1].isvec
)
8380 do_vfp_nsyn_opcode ("fmrx");
8388 do_vfp_nsyn_msr (void)
8390 if (inst
.operands
[0].isvec
)
8391 do_vfp_nsyn_opcode ("fmxr");
8401 unsigned Rt
= inst
.operands
[0].reg
;
8403 if (thumb_mode
&& Rt
== REG_SP
)
8405 inst
.error
= BAD_SP
;
8409 /* APSR_ sets isvec. All other refs to PC are illegal. */
8410 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8412 inst
.error
= BAD_PC
;
8416 /* If we get through parsing the register name, we just insert the number
8417 generated into the instruction without further validation. */
8418 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8419 inst
.instruction
|= (Rt
<< 12);
8425 unsigned Rt
= inst
.operands
[1].reg
;
8428 reject_bad_reg (Rt
);
8429 else if (Rt
== REG_PC
)
8431 inst
.error
= BAD_PC
;
8435 /* If we get through parsing the register name, we just insert the number
8436 generated into the instruction without further validation. */
8437 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8438 inst
.instruction
|= (Rt
<< 12);
8446 if (do_vfp_nsyn_mrs () == SUCCESS
)
8449 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8450 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8452 if (inst
.operands
[1].isreg
)
8454 br
= inst
.operands
[1].reg
;
8455 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8456 as_bad (_("bad register for mrs"));
8460 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8461 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8463 _("'APSR', 'CPSR' or 'SPSR' expected"));
8464 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8467 inst
.instruction
|= br
;
8470 /* Two possible forms:
8471 "{C|S}PSR_<field>, Rm",
8472 "{C|S}PSR_f, #expression". */
8477 if (do_vfp_nsyn_msr () == SUCCESS
)
8480 inst
.instruction
|= inst
.operands
[0].imm
;
8481 if (inst
.operands
[1].isreg
)
8482 inst
.instruction
|= inst
.operands
[1].reg
;
8485 inst
.instruction
|= INST_IMMEDIATE
;
8486 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8487 inst
.reloc
.pc_rel
= 0;
8494 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8496 if (!inst
.operands
[2].present
)
8497 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8498 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8499 inst
.instruction
|= inst
.operands
[1].reg
;
8500 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8502 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8503 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8504 as_tsktsk (_("Rd and Rm should be different in mul"));
8507 /* Long Multiply Parser
8508 UMULL RdLo, RdHi, Rm, Rs
8509 SMULL RdLo, RdHi, Rm, Rs
8510 UMLAL RdLo, RdHi, Rm, Rs
8511 SMLAL RdLo, RdHi, Rm, Rs. */
8516 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8517 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8518 inst
.instruction
|= inst
.operands
[2].reg
;
8519 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8521 /* rdhi and rdlo must be different. */
8522 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8523 as_tsktsk (_("rdhi and rdlo must be different"));
8525 /* rdhi, rdlo and rm must all be different before armv6. */
8526 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8527 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8528 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8529 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8535 if (inst
.operands
[0].present
8536 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8538 /* Architectural NOP hints are CPSR sets with no bits selected. */
8539 inst
.instruction
&= 0xf0000000;
8540 inst
.instruction
|= 0x0320f000;
8541 if (inst
.operands
[0].present
)
8542 inst
.instruction
|= inst
.operands
[0].imm
;
8546 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8547 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8548 Condition defaults to COND_ALWAYS.
8549 Error if Rd, Rn or Rm are R15. */
8554 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8555 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8556 inst
.instruction
|= inst
.operands
[2].reg
;
8557 if (inst
.operands
[3].present
)
8558 encode_arm_shift (3);
8561 /* ARM V6 PKHTB (Argument Parse). */
8566 if (!inst
.operands
[3].present
)
8568 /* If the shift specifier is omitted, turn the instruction
8569 into pkhbt rd, rm, rn. */
8570 inst
.instruction
&= 0xfff00010;
8571 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8572 inst
.instruction
|= inst
.operands
[1].reg
;
8573 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8577 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8578 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8579 inst
.instruction
|= inst
.operands
[2].reg
;
8580 encode_arm_shift (3);
8584 /* ARMv5TE: Preload-Cache
8585 MP Extensions: Preload for write
8589 Syntactically, like LDR with B=1, W=0, L=1. */
8594 constraint (!inst
.operands
[0].isreg
,
8595 _("'[' expected after PLD mnemonic"));
8596 constraint (inst
.operands
[0].postind
,
8597 _("post-indexed expression used in preload instruction"));
8598 constraint (inst
.operands
[0].writeback
,
8599 _("writeback used in preload instruction"));
8600 constraint (!inst
.operands
[0].preind
,
8601 _("unindexed addressing used in preload instruction"));
8602 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8605 /* ARMv7: PLI <addr_mode> */
8609 constraint (!inst
.operands
[0].isreg
,
8610 _("'[' expected after PLI mnemonic"));
8611 constraint (inst
.operands
[0].postind
,
8612 _("post-indexed expression used in preload instruction"));
8613 constraint (inst
.operands
[0].writeback
,
8614 _("writeback used in preload instruction"));
8615 constraint (!inst
.operands
[0].preind
,
8616 _("unindexed addressing used in preload instruction"));
8617 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8618 inst
.instruction
&= ~PRE_INDEX
;
8624 inst
.operands
[1] = inst
.operands
[0];
8625 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8626 inst
.operands
[0].isreg
= 1;
8627 inst
.operands
[0].writeback
= 1;
8628 inst
.operands
[0].reg
= REG_SP
;
8629 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
8632 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8633 word at the specified address and the following word
8635 Unconditionally executed.
8636 Error if Rn is R15. */
8641 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8642 if (inst
.operands
[0].writeback
)
8643 inst
.instruction
|= WRITE_BACK
;
8646 /* ARM V6 ssat (argument parse). */
8651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8652 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8653 inst
.instruction
|= inst
.operands
[2].reg
;
8655 if (inst
.operands
[3].present
)
8656 encode_arm_shift (3);
8659 /* ARM V6 usat (argument parse). */
8664 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8665 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8666 inst
.instruction
|= inst
.operands
[2].reg
;
8668 if (inst
.operands
[3].present
)
8669 encode_arm_shift (3);
8672 /* ARM V6 ssat16 (argument parse). */
8677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8678 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8679 inst
.instruction
|= inst
.operands
[2].reg
;
8685 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8686 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8687 inst
.instruction
|= inst
.operands
[2].reg
;
8690 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8691 preserving the other bits.
8693 setend <endian_specifier>, where <endian_specifier> is either
8699 if (warn_on_deprecated
8700 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8701 as_warn (_("setend use is deprecated for ARMv8"));
8703 if (inst
.operands
[0].imm
)
8704 inst
.instruction
|= 0x200;
8710 unsigned int Rm
= (inst
.operands
[1].present
8711 ? inst
.operands
[1].reg
8712 : inst
.operands
[0].reg
);
8714 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8715 inst
.instruction
|= Rm
;
8716 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8718 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8719 inst
.instruction
|= SHIFT_BY_REG
;
8720 /* PR 12854: Error on extraneous shifts. */
8721 constraint (inst
.operands
[2].shifted
,
8722 _("extraneous shift as part of operand to shift insn"));
8725 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8731 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8732 inst
.reloc
.pc_rel
= 0;
8738 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8739 inst
.reloc
.pc_rel
= 0;
8745 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8746 inst
.reloc
.pc_rel
= 0;
8749 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8750 SMLAxy{cond} Rd,Rm,Rs,Rn
8751 SMLAWy{cond} Rd,Rm,Rs,Rn
8752 Error if any register is R15. */
8757 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8758 inst
.instruction
|= inst
.operands
[1].reg
;
8759 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8760 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8763 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8764 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8765 Error if any register is R15.
8766 Warning if Rdlo == Rdhi. */
8771 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8772 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8773 inst
.instruction
|= inst
.operands
[2].reg
;
8774 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8776 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8777 as_tsktsk (_("rdhi and rdlo must be different"));
8780 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8781 SMULxy{cond} Rd,Rm,Rs
8782 Error if any register is R15. */
8787 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8788 inst
.instruction
|= inst
.operands
[1].reg
;
8789 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8792 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8793 the same for both ARM and Thumb-2. */
8800 if (inst
.operands
[0].present
)
8802 reg
= inst
.operands
[0].reg
;
8803 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8808 inst
.instruction
|= reg
<< 16;
8809 inst
.instruction
|= inst
.operands
[1].imm
;
8810 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8811 inst
.instruction
|= WRITE_BACK
;
8814 /* ARM V6 strex (argument parse). */
8819 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8820 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8821 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8822 || inst
.operands
[2].negative
8823 /* See comment in do_ldrex(). */
8824 || (inst
.operands
[2].reg
== REG_PC
),
8827 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8828 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8830 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8831 || inst
.reloc
.exp
.X_add_number
!= 0,
8832 _("offset must be zero in ARM encoding"));
8834 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8835 inst
.instruction
|= inst
.operands
[1].reg
;
8836 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8837 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8843 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8844 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8845 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8846 || inst
.operands
[2].negative
,
8849 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8850 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8858 constraint (inst
.operands
[1].reg
% 2 != 0,
8859 _("even register required"));
8860 constraint (inst
.operands
[2].present
8861 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8862 _("can only store two consecutive registers"));
8863 /* If op 2 were present and equal to PC, this function wouldn't
8864 have been called in the first place. */
8865 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8867 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8868 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8869 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8872 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8873 inst
.instruction
|= inst
.operands
[1].reg
;
8874 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8881 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8882 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8890 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8891 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8896 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8897 extends it to 32-bits, and adds the result to a value in another
8898 register. You can specify a rotation by 0, 8, 16, or 24 bits
8899 before extracting the 16-bit value.
8900 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8901 Condition defaults to COND_ALWAYS.
8902 Error if any register uses R15. */
8907 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8908 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8909 inst
.instruction
|= inst
.operands
[2].reg
;
8910 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8915 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8916 Condition defaults to COND_ALWAYS.
8917 Error if any register uses R15. */
8922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8923 inst
.instruction
|= inst
.operands
[1].reg
;
8924 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8927 /* VFP instructions. In a logical order: SP variant first, monad
8928 before dyad, arithmetic then move then load/store. */
8931 do_vfp_sp_monadic (void)
8933 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8934 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8938 do_vfp_sp_dyadic (void)
8940 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8941 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8942 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8946 do_vfp_sp_compare_z (void)
8948 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8952 do_vfp_dp_sp_cvt (void)
8954 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8955 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8959 do_vfp_sp_dp_cvt (void)
8961 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8962 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8966 do_vfp_reg_from_sp (void)
8968 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8969 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8973 do_vfp_reg2_from_sp2 (void)
8975 constraint (inst
.operands
[2].imm
!= 2,
8976 _("only two consecutive VFP SP registers allowed here"));
8977 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8978 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8979 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8983 do_vfp_sp_from_reg (void)
8985 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8986 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8990 do_vfp_sp2_from_reg2 (void)
8992 constraint (inst
.operands
[0].imm
!= 2,
8993 _("only two consecutive VFP SP registers allowed here"));
8994 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8995 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8996 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9000 do_vfp_sp_ldst (void)
9002 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9003 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9007 do_vfp_dp_ldst (void)
9009 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9010 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9015 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9017 if (inst
.operands
[0].writeback
)
9018 inst
.instruction
|= WRITE_BACK
;
9020 constraint (ldstm_type
!= VFP_LDSTMIA
,
9021 _("this addressing mode requires base-register writeback"));
9022 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9023 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9024 inst
.instruction
|= inst
.operands
[1].imm
;
9028 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9032 if (inst
.operands
[0].writeback
)
9033 inst
.instruction
|= WRITE_BACK
;
9035 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9036 _("this addressing mode requires base-register writeback"));
9038 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9039 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9041 count
= inst
.operands
[1].imm
<< 1;
9042 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9045 inst
.instruction
|= count
;
9049 do_vfp_sp_ldstmia (void)
9051 vfp_sp_ldstm (VFP_LDSTMIA
);
9055 do_vfp_sp_ldstmdb (void)
9057 vfp_sp_ldstm (VFP_LDSTMDB
);
9061 do_vfp_dp_ldstmia (void)
9063 vfp_dp_ldstm (VFP_LDSTMIA
);
9067 do_vfp_dp_ldstmdb (void)
9069 vfp_dp_ldstm (VFP_LDSTMDB
);
9073 do_vfp_xp_ldstmia (void)
9075 vfp_dp_ldstm (VFP_LDSTMIAX
);
9079 do_vfp_xp_ldstmdb (void)
9081 vfp_dp_ldstm (VFP_LDSTMDBX
);
9085 do_vfp_dp_rd_rm (void)
9087 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9088 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9092 do_vfp_dp_rn_rd (void)
9094 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9095 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9099 do_vfp_dp_rd_rn (void)
9101 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9102 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9106 do_vfp_dp_rd_rn_rm (void)
9108 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9109 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9110 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9116 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9120 do_vfp_dp_rm_rd_rn (void)
9122 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9123 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9124 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9127 /* VFPv3 instructions. */
9129 do_vfp_sp_const (void)
9131 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9132 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9133 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9137 do_vfp_dp_const (void)
9139 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9140 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9141 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9145 vfp_conv (int srcsize
)
9147 int immbits
= srcsize
- inst
.operands
[1].imm
;
9149 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9151 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9152 i.e. immbits must be in range 0 - 16. */
9153 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9156 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9158 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9159 i.e. immbits must be in range 0 - 31. */
9160 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9164 inst
.instruction
|= (immbits
& 1) << 5;
9165 inst
.instruction
|= (immbits
>> 1);
9169 do_vfp_sp_conv_16 (void)
9171 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9176 do_vfp_dp_conv_16 (void)
9178 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9183 do_vfp_sp_conv_32 (void)
9185 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9190 do_vfp_dp_conv_32 (void)
9192 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9196 /* FPA instructions. Also in a logical order. */
9201 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9202 inst
.instruction
|= inst
.operands
[1].reg
;
9206 do_fpa_ldmstm (void)
9208 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9209 switch (inst
.operands
[1].imm
)
9211 case 1: inst
.instruction
|= CP_T_X
; break;
9212 case 2: inst
.instruction
|= CP_T_Y
; break;
9213 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9218 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9220 /* The instruction specified "ea" or "fd", so we can only accept
9221 [Rn]{!}. The instruction does not really support stacking or
9222 unstacking, so we have to emulate these by setting appropriate
9223 bits and offsets. */
9224 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9225 || inst
.reloc
.exp
.X_add_number
!= 0,
9226 _("this instruction does not support indexing"));
9228 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9229 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9231 if (!(inst
.instruction
& INDEX_UP
))
9232 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9234 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9236 inst
.operands
[2].preind
= 0;
9237 inst
.operands
[2].postind
= 1;
9241 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9244 /* iWMMXt instructions: strictly in alphabetical order. */
9247 do_iwmmxt_tandorc (void)
9249 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9253 do_iwmmxt_textrc (void)
9255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9256 inst
.instruction
|= inst
.operands
[1].imm
;
9260 do_iwmmxt_textrm (void)
9262 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9263 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9264 inst
.instruction
|= inst
.operands
[2].imm
;
9268 do_iwmmxt_tinsr (void)
9270 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9271 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9272 inst
.instruction
|= inst
.operands
[2].imm
;
9276 do_iwmmxt_tmia (void)
9278 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9279 inst
.instruction
|= inst
.operands
[1].reg
;
9280 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9284 do_iwmmxt_waligni (void)
9286 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9287 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9288 inst
.instruction
|= inst
.operands
[2].reg
;
9289 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9293 do_iwmmxt_wmerge (void)
9295 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9296 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9297 inst
.instruction
|= inst
.operands
[2].reg
;
9298 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9302 do_iwmmxt_wmov (void)
9304 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9305 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9306 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9307 inst
.instruction
|= inst
.operands
[1].reg
;
9311 do_iwmmxt_wldstbh (void)
9314 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9316 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9318 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9319 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9323 do_iwmmxt_wldstw (void)
9325 /* RIWR_RIWC clears .isreg for a control register. */
9326 if (!inst
.operands
[0].isreg
)
9328 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9329 inst
.instruction
|= 0xf0000000;
9332 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9333 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9337 do_iwmmxt_wldstd (void)
9339 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9340 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9341 && inst
.operands
[1].immisreg
)
9343 inst
.instruction
&= ~0x1a000ff;
9344 inst
.instruction
|= (0xf << 28);
9345 if (inst
.operands
[1].preind
)
9346 inst
.instruction
|= PRE_INDEX
;
9347 if (!inst
.operands
[1].negative
)
9348 inst
.instruction
|= INDEX_UP
;
9349 if (inst
.operands
[1].writeback
)
9350 inst
.instruction
|= WRITE_BACK
;
9351 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9352 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9353 inst
.instruction
|= inst
.operands
[1].imm
;
9356 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9360 do_iwmmxt_wshufh (void)
9362 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9363 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9364 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9365 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9369 do_iwmmxt_wzero (void)
9371 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9372 inst
.instruction
|= inst
.operands
[0].reg
;
9373 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9374 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9378 do_iwmmxt_wrwrwr_or_imm5 (void)
9380 if (inst
.operands
[2].isreg
)
9383 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9384 _("immediate operand requires iWMMXt2"));
9386 if (inst
.operands
[2].imm
== 0)
9388 switch ((inst
.instruction
>> 20) & 0xf)
9394 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9395 inst
.operands
[2].imm
= 16;
9396 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9402 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9403 inst
.operands
[2].imm
= 32;
9404 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9411 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9413 wrn
= (inst
.instruction
>> 16) & 0xf;
9414 inst
.instruction
&= 0xff0fff0f;
9415 inst
.instruction
|= wrn
;
9416 /* Bail out here; the instruction is now assembled. */
9421 /* Map 32 -> 0, etc. */
9422 inst
.operands
[2].imm
&= 0x1f;
9423 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9427 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9428 operations first, then control, shift, and load/store. */
9430 /* Insns like "foo X,Y,Z". */
9433 do_mav_triple (void)
9435 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9436 inst
.instruction
|= inst
.operands
[1].reg
;
9437 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9440 /* Insns like "foo W,X,Y,Z".
9441 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9446 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9447 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9448 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9449 inst
.instruction
|= inst
.operands
[3].reg
;
9452 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9456 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9459 /* Maverick shift immediate instructions.
9460 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9461 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9466 int imm
= inst
.operands
[2].imm
;
9468 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9469 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9471 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9472 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9473 Bit 4 should be 0. */
9474 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9476 inst
.instruction
|= imm
;
9479 /* XScale instructions. Also sorted arithmetic before move. */
9481 /* Xscale multiply-accumulate (argument parse)
9484 MIAxycc acc0,Rm,Rs. */
9489 inst
.instruction
|= inst
.operands
[1].reg
;
9490 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9493 /* Xscale move-accumulator-register (argument parse)
9495 MARcc acc0,RdLo,RdHi. */
9500 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9501 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9504 /* Xscale move-register-accumulator (argument parse)
9506 MRAcc RdLo,RdHi,acc0. */
9511 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9512 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9513 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9516 /* Encoding functions relevant only to Thumb. */
9518 /* inst.operands[i] is a shifted-register operand; encode
9519 it into inst.instruction in the format used by Thumb32. */
9522 encode_thumb32_shifted_operand (int i
)
9524 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9525 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9527 constraint (inst
.operands
[i
].immisreg
,
9528 _("shift by register not allowed in thumb mode"));
9529 inst
.instruction
|= inst
.operands
[i
].reg
;
9530 if (shift
== SHIFT_RRX
)
9531 inst
.instruction
|= SHIFT_ROR
<< 4;
9534 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9535 _("expression too complex"));
9537 constraint (value
> 32
9538 || (value
== 32 && (shift
== SHIFT_LSL
9539 || shift
== SHIFT_ROR
)),
9540 _("shift expression is too large"));
9544 else if (value
== 32)
9547 inst
.instruction
|= shift
<< 4;
9548 inst
.instruction
|= (value
& 0x1c) << 10;
9549 inst
.instruction
|= (value
& 0x03) << 6;
9554 /* inst.operands[i] was set up by parse_address. Encode it into a
9555 Thumb32 format load or store instruction. Reject forms that cannot
9556 be used with such instructions. If is_t is true, reject forms that
9557 cannot be used with a T instruction; if is_d is true, reject forms
9558 that cannot be used with a D instruction. If it is a store insn,
9562 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9564 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9566 constraint (!inst
.operands
[i
].isreg
,
9567 _("Instruction does not support =N addresses"));
9569 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9570 if (inst
.operands
[i
].immisreg
)
9572 constraint (is_pc
, BAD_PC_ADDRESSING
);
9573 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9574 constraint (inst
.operands
[i
].negative
,
9575 _("Thumb does not support negative register indexing"));
9576 constraint (inst
.operands
[i
].postind
,
9577 _("Thumb does not support register post-indexing"));
9578 constraint (inst
.operands
[i
].writeback
,
9579 _("Thumb does not support register indexing with writeback"));
9580 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9581 _("Thumb supports only LSL in shifted register indexing"));
9583 inst
.instruction
|= inst
.operands
[i
].imm
;
9584 if (inst
.operands
[i
].shifted
)
9586 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9587 _("expression too complex"));
9588 constraint (inst
.reloc
.exp
.X_add_number
< 0
9589 || inst
.reloc
.exp
.X_add_number
> 3,
9590 _("shift out of range"));
9591 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9593 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9595 else if (inst
.operands
[i
].preind
)
9597 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9598 constraint (is_t
&& inst
.operands
[i
].writeback
,
9599 _("cannot use writeback with this instruction"));
9600 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
9605 inst
.instruction
|= 0x01000000;
9606 if (inst
.operands
[i
].writeback
)
9607 inst
.instruction
|= 0x00200000;
9611 inst
.instruction
|= 0x00000c00;
9612 if (inst
.operands
[i
].writeback
)
9613 inst
.instruction
|= 0x00000100;
9615 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9617 else if (inst
.operands
[i
].postind
)
9619 gas_assert (inst
.operands
[i
].writeback
);
9620 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9621 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9624 inst
.instruction
|= 0x00200000;
9626 inst
.instruction
|= 0x00000900;
9627 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9629 else /* unindexed - only for coprocessor */
9630 inst
.error
= _("instruction does not accept unindexed addressing");
9633 /* Table of Thumb instructions which exist in both 16- and 32-bit
9634 encodings (the latter only in post-V6T2 cores). The index is the
9635 value used in the insns table below. When there is more than one
9636 possible 16-bit encoding for the instruction, this table always
9638 Also contains several pseudo-instructions used during relaxation. */
9639 #define T16_32_TAB \
9640 X(_adc, 4140, eb400000), \
9641 X(_adcs, 4140, eb500000), \
9642 X(_add, 1c00, eb000000), \
9643 X(_adds, 1c00, eb100000), \
9644 X(_addi, 0000, f1000000), \
9645 X(_addis, 0000, f1100000), \
9646 X(_add_pc,000f, f20f0000), \
9647 X(_add_sp,000d, f10d0000), \
9648 X(_adr, 000f, f20f0000), \
9649 X(_and, 4000, ea000000), \
9650 X(_ands, 4000, ea100000), \
9651 X(_asr, 1000, fa40f000), \
9652 X(_asrs, 1000, fa50f000), \
9653 X(_b, e000, f000b000), \
9654 X(_bcond, d000, f0008000), \
9655 X(_bic, 4380, ea200000), \
9656 X(_bics, 4380, ea300000), \
9657 X(_cmn, 42c0, eb100f00), \
9658 X(_cmp, 2800, ebb00f00), \
9659 X(_cpsie, b660, f3af8400), \
9660 X(_cpsid, b670, f3af8600), \
9661 X(_cpy, 4600, ea4f0000), \
9662 X(_dec_sp,80dd, f1ad0d00), \
9663 X(_eor, 4040, ea800000), \
9664 X(_eors, 4040, ea900000), \
9665 X(_inc_sp,00dd, f10d0d00), \
9666 X(_ldmia, c800, e8900000), \
9667 X(_ldr, 6800, f8500000), \
9668 X(_ldrb, 7800, f8100000), \
9669 X(_ldrh, 8800, f8300000), \
9670 X(_ldrsb, 5600, f9100000), \
9671 X(_ldrsh, 5e00, f9300000), \
9672 X(_ldr_pc,4800, f85f0000), \
9673 X(_ldr_pc2,4800, f85f0000), \
9674 X(_ldr_sp,9800, f85d0000), \
9675 X(_lsl, 0000, fa00f000), \
9676 X(_lsls, 0000, fa10f000), \
9677 X(_lsr, 0800, fa20f000), \
9678 X(_lsrs, 0800, fa30f000), \
9679 X(_mov, 2000, ea4f0000), \
9680 X(_movs, 2000, ea5f0000), \
9681 X(_mul, 4340, fb00f000), \
9682 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9683 X(_mvn, 43c0, ea6f0000), \
9684 X(_mvns, 43c0, ea7f0000), \
9685 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9686 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9687 X(_orr, 4300, ea400000), \
9688 X(_orrs, 4300, ea500000), \
9689 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9690 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9691 X(_rev, ba00, fa90f080), \
9692 X(_rev16, ba40, fa90f090), \
9693 X(_revsh, bac0, fa90f0b0), \
9694 X(_ror, 41c0, fa60f000), \
9695 X(_rors, 41c0, fa70f000), \
9696 X(_sbc, 4180, eb600000), \
9697 X(_sbcs, 4180, eb700000), \
9698 X(_stmia, c000, e8800000), \
9699 X(_str, 6000, f8400000), \
9700 X(_strb, 7000, f8000000), \
9701 X(_strh, 8000, f8200000), \
9702 X(_str_sp,9000, f84d0000), \
9703 X(_sub, 1e00, eba00000), \
9704 X(_subs, 1e00, ebb00000), \
9705 X(_subi, 8000, f1a00000), \
9706 X(_subis, 8000, f1b00000), \
9707 X(_sxtb, b240, fa4ff080), \
9708 X(_sxth, b200, fa0ff080), \
9709 X(_tst, 4200, ea100f00), \
9710 X(_uxtb, b2c0, fa5ff080), \
9711 X(_uxth, b280, fa1ff080), \
9712 X(_nop, bf00, f3af8000), \
9713 X(_yield, bf10, f3af8001), \
9714 X(_wfe, bf20, f3af8002), \
9715 X(_wfi, bf30, f3af8003), \
9716 X(_sev, bf40, f3af8004), \
9717 X(_sevl, bf50, f3af8005), \
9718 X(_udf, de00, f7f0a000)
9720 /* To catch errors in encoding functions, the codes are all offset by
9721 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9722 as 16-bit instructions. */
9723 #define X(a,b,c) T_MNEM##a
9724 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9727 #define X(a,b,c) 0x##b
9728 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9729 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9732 #define X(a,b,c) 0x##c
9733 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9734 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9735 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9739 /* Thumb instruction encoders, in alphabetical order. */
9744 do_t_add_sub_w (void)
9748 Rd
= inst
.operands
[0].reg
;
9749 Rn
= inst
.operands
[1].reg
;
9751 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9752 is the SP-{plus,minus}-immediate form of the instruction. */
9754 constraint (Rd
== REG_PC
, BAD_PC
);
9756 reject_bad_reg (Rd
);
9758 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9759 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9762 /* Parse an add or subtract instruction. We get here with inst.instruction
9763 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9770 Rd
= inst
.operands
[0].reg
;
9771 Rs
= (inst
.operands
[1].present
9772 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9773 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9776 set_it_insn_type_last ();
9784 flags
= (inst
.instruction
== T_MNEM_adds
9785 || inst
.instruction
== T_MNEM_subs
);
9787 narrow
= !in_it_block ();
9789 narrow
= in_it_block ();
9790 if (!inst
.operands
[2].isreg
)
9794 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9796 add
= (inst
.instruction
== T_MNEM_add
9797 || inst
.instruction
== T_MNEM_adds
);
9799 if (inst
.size_req
!= 4)
9801 /* Attempt to use a narrow opcode, with relaxation if
9803 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9804 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9805 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9806 opcode
= T_MNEM_add_sp
;
9807 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9808 opcode
= T_MNEM_add_pc
;
9809 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9812 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9814 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9818 inst
.instruction
= THUMB_OP16(opcode
);
9819 inst
.instruction
|= (Rd
<< 4) | Rs
;
9820 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9821 if (inst
.size_req
!= 2)
9822 inst
.relax
= opcode
;
9825 constraint (inst
.size_req
== 2, BAD_HIREG
);
9827 if (inst
.size_req
== 4
9828 || (inst
.size_req
!= 2 && !opcode
))
9832 constraint (add
, BAD_PC
);
9833 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9834 _("only SUBS PC, LR, #const allowed"));
9835 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9836 _("expression too complex"));
9837 constraint (inst
.reloc
.exp
.X_add_number
< 0
9838 || inst
.reloc
.exp
.X_add_number
> 0xff,
9839 _("immediate value out of range"));
9840 inst
.instruction
= T2_SUBS_PC_LR
9841 | inst
.reloc
.exp
.X_add_number
;
9842 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9845 else if (Rs
== REG_PC
)
9847 /* Always use addw/subw. */
9848 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9849 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9853 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9854 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9857 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9859 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9861 inst
.instruction
|= Rd
<< 8;
9862 inst
.instruction
|= Rs
<< 16;
9867 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9868 unsigned int shift
= inst
.operands
[2].shift_kind
;
9870 Rn
= inst
.operands
[2].reg
;
9871 /* See if we can do this with a 16-bit instruction. */
9872 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9874 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9879 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9880 || inst
.instruction
== T_MNEM_add
)
9883 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9887 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9889 /* Thumb-1 cores (except v6-M) require at least one high
9890 register in a narrow non flag setting add. */
9891 if (Rd
> 7 || Rn
> 7
9892 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9893 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9900 inst
.instruction
= T_OPCODE_ADD_HI
;
9901 inst
.instruction
|= (Rd
& 8) << 4;
9902 inst
.instruction
|= (Rd
& 7);
9903 inst
.instruction
|= Rn
<< 3;
9909 constraint (Rd
== REG_PC
, BAD_PC
);
9910 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9911 constraint (Rs
== REG_PC
, BAD_PC
);
9912 reject_bad_reg (Rn
);
9914 /* If we get here, it can't be done in 16 bits. */
9915 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9916 _("shift must be constant"));
9917 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9918 inst
.instruction
|= Rd
<< 8;
9919 inst
.instruction
|= Rs
<< 16;
9920 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
9921 _("shift value over 3 not allowed in thumb mode"));
9922 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
9923 _("only LSL shift allowed in thumb mode"));
9924 encode_thumb32_shifted_operand (2);
9929 constraint (inst
.instruction
== T_MNEM_adds
9930 || inst
.instruction
== T_MNEM_subs
,
9933 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9935 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9936 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9939 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9941 inst
.instruction
|= (Rd
<< 4) | Rs
;
9942 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9946 Rn
= inst
.operands
[2].reg
;
9947 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9949 /* We now have Rd, Rs, and Rn set to registers. */
9950 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9952 /* Can't do this for SUB. */
9953 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9954 inst
.instruction
= T_OPCODE_ADD_HI
;
9955 inst
.instruction
|= (Rd
& 8) << 4;
9956 inst
.instruction
|= (Rd
& 7);
9958 inst
.instruction
|= Rn
<< 3;
9960 inst
.instruction
|= Rs
<< 3;
9962 constraint (1, _("dest must overlap one source register"));
9966 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9967 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9968 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9978 Rd
= inst
.operands
[0].reg
;
9979 reject_bad_reg (Rd
);
9981 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9983 /* Defer to section relaxation. */
9984 inst
.relax
= inst
.instruction
;
9985 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9986 inst
.instruction
|= Rd
<< 4;
9988 else if (unified_syntax
&& inst
.size_req
!= 2)
9990 /* Generate a 32-bit opcode. */
9991 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9992 inst
.instruction
|= Rd
<< 8;
9993 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9994 inst
.reloc
.pc_rel
= 1;
9998 /* Generate a 16-bit opcode. */
9999 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10000 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10001 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10002 inst
.reloc
.pc_rel
= 1;
10004 inst
.instruction
|= Rd
<< 4;
10008 /* Arithmetic instructions for which there is just one 16-bit
10009 instruction encoding, and it allows only two low registers.
10010 For maximal compatibility with ARM syntax, we allow three register
10011 operands even when Thumb-32 instructions are not available, as long
10012 as the first two are identical. For instance, both "sbc r0,r1" and
10013 "sbc r0,r0,r1" are allowed. */
10019 Rd
= inst
.operands
[0].reg
;
10020 Rs
= (inst
.operands
[1].present
10021 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10022 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10023 Rn
= inst
.operands
[2].reg
;
10025 reject_bad_reg (Rd
);
10026 reject_bad_reg (Rs
);
10027 if (inst
.operands
[2].isreg
)
10028 reject_bad_reg (Rn
);
10030 if (unified_syntax
)
10032 if (!inst
.operands
[2].isreg
)
10034 /* For an immediate, we always generate a 32-bit opcode;
10035 section relaxation will shrink it later if possible. */
10036 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10037 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10038 inst
.instruction
|= Rd
<< 8;
10039 inst
.instruction
|= Rs
<< 16;
10040 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10044 bfd_boolean narrow
;
10046 /* See if we can do this with a 16-bit instruction. */
10047 if (THUMB_SETS_FLAGS (inst
.instruction
))
10048 narrow
= !in_it_block ();
10050 narrow
= in_it_block ();
10052 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10054 if (inst
.operands
[2].shifted
)
10056 if (inst
.size_req
== 4)
10062 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10063 inst
.instruction
|= Rd
;
10064 inst
.instruction
|= Rn
<< 3;
10068 /* If we get here, it can't be done in 16 bits. */
10069 constraint (inst
.operands
[2].shifted
10070 && inst
.operands
[2].immisreg
,
10071 _("shift must be constant"));
10072 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10073 inst
.instruction
|= Rd
<< 8;
10074 inst
.instruction
|= Rs
<< 16;
10075 encode_thumb32_shifted_operand (2);
10080 /* On its face this is a lie - the instruction does set the
10081 flags. However, the only supported mnemonic in this mode
10082 says it doesn't. */
10083 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10085 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10086 _("unshifted register required"));
10087 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10088 constraint (Rd
!= Rs
,
10089 _("dest and source1 must be the same register"));
10091 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10092 inst
.instruction
|= Rd
;
10093 inst
.instruction
|= Rn
<< 3;
10097 /* Similarly, but for instructions where the arithmetic operation is
10098 commutative, so we can allow either of them to be different from
10099 the destination operand in a 16-bit instruction. For instance, all
10100 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10107 Rd
= inst
.operands
[0].reg
;
10108 Rs
= (inst
.operands
[1].present
10109 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10110 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10111 Rn
= inst
.operands
[2].reg
;
10113 reject_bad_reg (Rd
);
10114 reject_bad_reg (Rs
);
10115 if (inst
.operands
[2].isreg
)
10116 reject_bad_reg (Rn
);
10118 if (unified_syntax
)
10120 if (!inst
.operands
[2].isreg
)
10122 /* For an immediate, we always generate a 32-bit opcode;
10123 section relaxation will shrink it later if possible. */
10124 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10125 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10126 inst
.instruction
|= Rd
<< 8;
10127 inst
.instruction
|= Rs
<< 16;
10128 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10132 bfd_boolean narrow
;
10134 /* See if we can do this with a 16-bit instruction. */
10135 if (THUMB_SETS_FLAGS (inst
.instruction
))
10136 narrow
= !in_it_block ();
10138 narrow
= in_it_block ();
10140 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10142 if (inst
.operands
[2].shifted
)
10144 if (inst
.size_req
== 4)
10151 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10152 inst
.instruction
|= Rd
;
10153 inst
.instruction
|= Rn
<< 3;
10158 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10159 inst
.instruction
|= Rd
;
10160 inst
.instruction
|= Rs
<< 3;
10165 /* If we get here, it can't be done in 16 bits. */
10166 constraint (inst
.operands
[2].shifted
10167 && inst
.operands
[2].immisreg
,
10168 _("shift must be constant"));
10169 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10170 inst
.instruction
|= Rd
<< 8;
10171 inst
.instruction
|= Rs
<< 16;
10172 encode_thumb32_shifted_operand (2);
10177 /* On its face this is a lie - the instruction does set the
10178 flags. However, the only supported mnemonic in this mode
10179 says it doesn't. */
10180 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10182 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10183 _("unshifted register required"));
10184 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10186 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10187 inst
.instruction
|= Rd
;
10190 inst
.instruction
|= Rn
<< 3;
10192 inst
.instruction
|= Rs
<< 3;
10194 constraint (1, _("dest must overlap one source register"));
10202 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10203 constraint (msb
> 32, _("bit-field extends past end of register"));
10204 /* The instruction encoding stores the LSB and MSB,
10205 not the LSB and width. */
10206 Rd
= inst
.operands
[0].reg
;
10207 reject_bad_reg (Rd
);
10208 inst
.instruction
|= Rd
<< 8;
10209 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10210 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10211 inst
.instruction
|= msb
- 1;
10220 Rd
= inst
.operands
[0].reg
;
10221 reject_bad_reg (Rd
);
10223 /* #0 in second position is alternative syntax for bfc, which is
10224 the same instruction but with REG_PC in the Rm field. */
10225 if (!inst
.operands
[1].isreg
)
10229 Rn
= inst
.operands
[1].reg
;
10230 reject_bad_reg (Rn
);
10233 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10234 constraint (msb
> 32, _("bit-field extends past end of register"));
10235 /* The instruction encoding stores the LSB and MSB,
10236 not the LSB and width. */
10237 inst
.instruction
|= Rd
<< 8;
10238 inst
.instruction
|= Rn
<< 16;
10239 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10240 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10241 inst
.instruction
|= msb
- 1;
10249 Rd
= inst
.operands
[0].reg
;
10250 Rn
= inst
.operands
[1].reg
;
10252 reject_bad_reg (Rd
);
10253 reject_bad_reg (Rn
);
10255 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10256 _("bit-field extends past end of register"));
10257 inst
.instruction
|= Rd
<< 8;
10258 inst
.instruction
|= Rn
<< 16;
10259 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10260 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10261 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10264 /* ARM V5 Thumb BLX (argument parse)
10265 BLX <target_addr> which is BLX(1)
10266 BLX <Rm> which is BLX(2)
10267 Unfortunately, there are two different opcodes for this mnemonic.
10268 So, the insns[].value is not used, and the code here zaps values
10269 into inst.instruction.
10271 ??? How to take advantage of the additional two bits of displacement
10272 available in Thumb32 mode? Need new relocation? */
10277 set_it_insn_type_last ();
10279 if (inst
.operands
[0].isreg
)
10281 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10282 /* We have a register, so this is BLX(2). */
10283 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10287 /* No register. This must be BLX(1). */
10288 inst
.instruction
= 0xf000e800;
10289 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10301 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10303 if (in_it_block ())
10305 /* Conditional branches inside IT blocks are encoded as unconditional
10307 cond
= COND_ALWAYS
;
10312 if (cond
!= COND_ALWAYS
)
10313 opcode
= T_MNEM_bcond
;
10315 opcode
= inst
.instruction
;
10318 && (inst
.size_req
== 4
10319 || (inst
.size_req
!= 2
10320 && (inst
.operands
[0].hasreloc
10321 || inst
.reloc
.exp
.X_op
== O_constant
))))
10323 inst
.instruction
= THUMB_OP32(opcode
);
10324 if (cond
== COND_ALWAYS
)
10325 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10328 gas_assert (cond
!= 0xF);
10329 inst
.instruction
|= cond
<< 22;
10330 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10335 inst
.instruction
= THUMB_OP16(opcode
);
10336 if (cond
== COND_ALWAYS
)
10337 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10340 inst
.instruction
|= cond
<< 8;
10341 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10343 /* Allow section relaxation. */
10344 if (unified_syntax
&& inst
.size_req
!= 2)
10345 inst
.relax
= opcode
;
10347 inst
.reloc
.type
= reloc
;
10348 inst
.reloc
.pc_rel
= 1;
10351 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10352 between the two is the maximum immediate allowed - which is passed in
10355 do_t_bkpt_hlt1 (int range
)
10357 constraint (inst
.cond
!= COND_ALWAYS
,
10358 _("instruction is always unconditional"));
10359 if (inst
.operands
[0].present
)
10361 constraint (inst
.operands
[0].imm
> range
,
10362 _("immediate value out of range"));
10363 inst
.instruction
|= inst
.operands
[0].imm
;
10366 set_it_insn_type (NEUTRAL_IT_INSN
);
10372 do_t_bkpt_hlt1 (63);
10378 do_t_bkpt_hlt1 (255);
10382 do_t_branch23 (void)
10384 set_it_insn_type_last ();
10385 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10387 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10388 this file. We used to simply ignore the PLT reloc type here --
10389 the branch encoding is now needed to deal with TLSCALL relocs.
10390 So if we see a PLT reloc now, put it back to how it used to be to
10391 keep the preexisting behaviour. */
10392 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10393 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10395 #if defined(OBJ_COFF)
10396 /* If the destination of the branch is a defined symbol which does not have
10397 the THUMB_FUNC attribute, then we must be calling a function which has
10398 the (interfacearm) attribute. We look for the Thumb entry point to that
10399 function and change the branch to refer to that function instead. */
10400 if ( inst
.reloc
.exp
.X_op
== O_symbol
10401 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10402 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10403 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10404 inst
.reloc
.exp
.X_add_symbol
=
10405 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10412 set_it_insn_type_last ();
10413 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10414 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10415 should cause the alignment to be checked once it is known. This is
10416 because BX PC only works if the instruction is word aligned. */
10424 set_it_insn_type_last ();
10425 Rm
= inst
.operands
[0].reg
;
10426 reject_bad_reg (Rm
);
10427 inst
.instruction
|= Rm
<< 16;
10436 Rd
= inst
.operands
[0].reg
;
10437 Rm
= inst
.operands
[1].reg
;
10439 reject_bad_reg (Rd
);
10440 reject_bad_reg (Rm
);
10442 inst
.instruction
|= Rd
<< 8;
10443 inst
.instruction
|= Rm
<< 16;
10444 inst
.instruction
|= Rm
;
10450 set_it_insn_type (OUTSIDE_IT_INSN
);
10451 inst
.instruction
|= inst
.operands
[0].imm
;
10457 set_it_insn_type (OUTSIDE_IT_INSN
);
10459 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10460 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10462 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10463 inst
.instruction
= 0xf3af8000;
10464 inst
.instruction
|= imod
<< 9;
10465 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10466 if (inst
.operands
[1].present
)
10467 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10471 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10472 && (inst
.operands
[0].imm
& 4),
10473 _("selected processor does not support 'A' form "
10474 "of this instruction"));
10475 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10476 _("Thumb does not support the 2-argument "
10477 "form of this instruction"));
10478 inst
.instruction
|= inst
.operands
[0].imm
;
10482 /* THUMB CPY instruction (argument parse). */
10487 if (inst
.size_req
== 4)
10489 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10490 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10491 inst
.instruction
|= inst
.operands
[1].reg
;
10495 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10496 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10497 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10504 set_it_insn_type (OUTSIDE_IT_INSN
);
10505 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10506 inst
.instruction
|= inst
.operands
[0].reg
;
10507 inst
.reloc
.pc_rel
= 1;
10508 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10514 inst
.instruction
|= inst
.operands
[0].imm
;
10520 unsigned Rd
, Rn
, Rm
;
10522 Rd
= inst
.operands
[0].reg
;
10523 Rn
= (inst
.operands
[1].present
10524 ? inst
.operands
[1].reg
: Rd
);
10525 Rm
= inst
.operands
[2].reg
;
10527 reject_bad_reg (Rd
);
10528 reject_bad_reg (Rn
);
10529 reject_bad_reg (Rm
);
10531 inst
.instruction
|= Rd
<< 8;
10532 inst
.instruction
|= Rn
<< 16;
10533 inst
.instruction
|= Rm
;
10539 if (unified_syntax
&& inst
.size_req
== 4)
10540 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10542 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10548 unsigned int cond
= inst
.operands
[0].imm
;
10550 set_it_insn_type (IT_INSN
);
10551 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10553 now_it
.warn_deprecated
= FALSE
;
10555 /* If the condition is a negative condition, invert the mask. */
10556 if ((cond
& 0x1) == 0x0)
10558 unsigned int mask
= inst
.instruction
& 0x000f;
10560 if ((mask
& 0x7) == 0)
10562 /* No conversion needed. */
10563 now_it
.block_length
= 1;
10565 else if ((mask
& 0x3) == 0)
10568 now_it
.block_length
= 2;
10570 else if ((mask
& 0x1) == 0)
10573 now_it
.block_length
= 3;
10578 now_it
.block_length
= 4;
10581 inst
.instruction
&= 0xfff0;
10582 inst
.instruction
|= mask
;
10585 inst
.instruction
|= cond
<< 4;
10588 /* Helper function used for both push/pop and ldm/stm. */
10590 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10594 load
= (inst
.instruction
& (1 << 20)) != 0;
10596 if (mask
& (1 << 13))
10597 inst
.error
= _("SP not allowed in register list");
10599 if ((mask
& (1 << base
)) != 0
10601 inst
.error
= _("having the base register in the register list when "
10602 "using write back is UNPREDICTABLE");
10606 if (mask
& (1 << 15))
10608 if (mask
& (1 << 14))
10609 inst
.error
= _("LR and PC should not both be in register list");
10611 set_it_insn_type_last ();
10616 if (mask
& (1 << 15))
10617 inst
.error
= _("PC not allowed in register list");
10620 if ((mask
& (mask
- 1)) == 0)
10622 /* Single register transfers implemented as str/ldr. */
10625 if (inst
.instruction
& (1 << 23))
10626 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10628 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10632 if (inst
.instruction
& (1 << 23))
10633 inst
.instruction
= 0x00800000; /* ia -> [base] */
10635 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10638 inst
.instruction
|= 0xf8400000;
10640 inst
.instruction
|= 0x00100000;
10642 mask
= ffs (mask
) - 1;
10645 else if (writeback
)
10646 inst
.instruction
|= WRITE_BACK
;
10648 inst
.instruction
|= mask
;
10649 inst
.instruction
|= base
<< 16;
10655 /* This really doesn't seem worth it. */
10656 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10657 _("expression too complex"));
10658 constraint (inst
.operands
[1].writeback
,
10659 _("Thumb load/store multiple does not support {reglist}^"));
10661 if (unified_syntax
)
10663 bfd_boolean narrow
;
10667 /* See if we can use a 16-bit instruction. */
10668 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10669 && inst
.size_req
!= 4
10670 && !(inst
.operands
[1].imm
& ~0xff))
10672 mask
= 1 << inst
.operands
[0].reg
;
10674 if (inst
.operands
[0].reg
<= 7)
10676 if (inst
.instruction
== T_MNEM_stmia
10677 ? inst
.operands
[0].writeback
10678 : (inst
.operands
[0].writeback
10679 == !(inst
.operands
[1].imm
& mask
)))
10681 if (inst
.instruction
== T_MNEM_stmia
10682 && (inst
.operands
[1].imm
& mask
)
10683 && (inst
.operands
[1].imm
& (mask
- 1)))
10684 as_warn (_("value stored for r%d is UNKNOWN"),
10685 inst
.operands
[0].reg
);
10687 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10688 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10689 inst
.instruction
|= inst
.operands
[1].imm
;
10692 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10694 /* This means 1 register in reg list one of 3 situations:
10695 1. Instruction is stmia, but without writeback.
10696 2. lmdia without writeback, but with Rn not in
10698 3. ldmia with writeback, but with Rn in reglist.
10699 Case 3 is UNPREDICTABLE behaviour, so we handle
10700 case 1 and 2 which can be converted into a 16-bit
10701 str or ldr. The SP cases are handled below. */
10702 unsigned long opcode
;
10703 /* First, record an error for Case 3. */
10704 if (inst
.operands
[1].imm
& mask
10705 && inst
.operands
[0].writeback
)
10707 _("having the base register in the register list when "
10708 "using write back is UNPREDICTABLE");
10710 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10712 inst
.instruction
= THUMB_OP16 (opcode
);
10713 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10714 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10718 else if (inst
.operands
[0] .reg
== REG_SP
)
10720 if (inst
.operands
[0].writeback
)
10723 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10724 ? T_MNEM_push
: T_MNEM_pop
);
10725 inst
.instruction
|= inst
.operands
[1].imm
;
10728 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10731 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10732 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10733 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10741 if (inst
.instruction
< 0xffff)
10742 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10744 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10745 inst
.operands
[0].writeback
);
10750 constraint (inst
.operands
[0].reg
> 7
10751 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10752 constraint (inst
.instruction
!= T_MNEM_ldmia
10753 && inst
.instruction
!= T_MNEM_stmia
,
10754 _("Thumb-2 instruction only valid in unified syntax"));
10755 if (inst
.instruction
== T_MNEM_stmia
)
10757 if (!inst
.operands
[0].writeback
)
10758 as_warn (_("this instruction will write back the base register"));
10759 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10760 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10761 as_warn (_("value stored for r%d is UNKNOWN"),
10762 inst
.operands
[0].reg
);
10766 if (!inst
.operands
[0].writeback
10767 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10768 as_warn (_("this instruction will write back the base register"));
10769 else if (inst
.operands
[0].writeback
10770 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10771 as_warn (_("this instruction will not write back the base register"));
10774 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10775 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10776 inst
.instruction
|= inst
.operands
[1].imm
;
10783 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10784 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10785 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10786 || inst
.operands
[1].negative
,
10789 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10791 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10792 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10793 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10799 if (!inst
.operands
[1].present
)
10801 constraint (inst
.operands
[0].reg
== REG_LR
,
10802 _("r14 not allowed as first register "
10803 "when second register is omitted"));
10804 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10806 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10809 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10810 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10811 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10817 unsigned long opcode
;
10820 if (inst
.operands
[0].isreg
10821 && !inst
.operands
[0].preind
10822 && inst
.operands
[0].reg
== REG_PC
)
10823 set_it_insn_type_last ();
10825 opcode
= inst
.instruction
;
10826 if (unified_syntax
)
10828 if (!inst
.operands
[1].isreg
)
10830 if (opcode
<= 0xffff)
10831 inst
.instruction
= THUMB_OP32 (opcode
);
10832 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10835 if (inst
.operands
[1].isreg
10836 && !inst
.operands
[1].writeback
10837 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10838 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10839 && opcode
<= 0xffff
10840 && inst
.size_req
!= 4)
10842 /* Insn may have a 16-bit form. */
10843 Rn
= inst
.operands
[1].reg
;
10844 if (inst
.operands
[1].immisreg
)
10846 inst
.instruction
= THUMB_OP16 (opcode
);
10848 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10850 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10851 reject_bad_reg (inst
.operands
[1].imm
);
10853 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10854 && opcode
!= T_MNEM_ldrsb
)
10855 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10856 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10863 if (inst
.reloc
.pc_rel
)
10864 opcode
= T_MNEM_ldr_pc2
;
10866 opcode
= T_MNEM_ldr_pc
;
10870 if (opcode
== T_MNEM_ldr
)
10871 opcode
= T_MNEM_ldr_sp
;
10873 opcode
= T_MNEM_str_sp
;
10875 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10879 inst
.instruction
= inst
.operands
[0].reg
;
10880 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10882 inst
.instruction
|= THUMB_OP16 (opcode
);
10883 if (inst
.size_req
== 2)
10884 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10886 inst
.relax
= opcode
;
10890 /* Definitely a 32-bit variant. */
10892 /* Warning for Erratum 752419. */
10893 if (opcode
== T_MNEM_ldr
10894 && inst
.operands
[0].reg
== REG_SP
10895 && inst
.operands
[1].writeback
== 1
10896 && !inst
.operands
[1].immisreg
)
10898 if (no_cpu_selected ()
10899 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10900 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10901 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10902 as_warn (_("This instruction may be unpredictable "
10903 "if executed on M-profile cores "
10904 "with interrupts enabled."));
10907 /* Do some validations regarding addressing modes. */
10908 if (inst
.operands
[1].immisreg
)
10909 reject_bad_reg (inst
.operands
[1].imm
);
10911 constraint (inst
.operands
[1].writeback
== 1
10912 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10915 inst
.instruction
= THUMB_OP32 (opcode
);
10916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10917 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10918 check_ldr_r15_aligned ();
10922 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10924 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10926 /* Only [Rn,Rm] is acceptable. */
10927 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10928 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10929 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10930 || inst
.operands
[1].negative
,
10931 _("Thumb does not support this addressing mode"));
10932 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10936 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10937 if (!inst
.operands
[1].isreg
)
10938 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10941 constraint (!inst
.operands
[1].preind
10942 || inst
.operands
[1].shifted
10943 || inst
.operands
[1].writeback
,
10944 _("Thumb does not support this addressing mode"));
10945 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10947 constraint (inst
.instruction
& 0x0600,
10948 _("byte or halfword not valid for base register"));
10949 constraint (inst
.operands
[1].reg
== REG_PC
10950 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10951 _("r15 based store not allowed"));
10952 constraint (inst
.operands
[1].immisreg
,
10953 _("invalid base register for register offset"));
10955 if (inst
.operands
[1].reg
== REG_PC
)
10956 inst
.instruction
= T_OPCODE_LDR_PC
;
10957 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10958 inst
.instruction
= T_OPCODE_LDR_SP
;
10960 inst
.instruction
= T_OPCODE_STR_SP
;
10962 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10963 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10967 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10968 if (!inst
.operands
[1].immisreg
)
10970 /* Immediate offset. */
10971 inst
.instruction
|= inst
.operands
[0].reg
;
10972 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10973 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10977 /* Register offset. */
10978 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10979 constraint (inst
.operands
[1].negative
,
10980 _("Thumb does not support this addressing mode"));
10983 switch (inst
.instruction
)
10985 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10986 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10987 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10988 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10989 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10990 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10991 case 0x5600 /* ldrsb */:
10992 case 0x5e00 /* ldrsh */: break;
10996 inst
.instruction
|= inst
.operands
[0].reg
;
10997 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10998 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11004 if (!inst
.operands
[1].present
)
11006 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11007 constraint (inst
.operands
[0].reg
== REG_LR
,
11008 _("r14 not allowed here"));
11009 constraint (inst
.operands
[0].reg
== REG_R12
,
11010 _("r12 not allowed here"));
11013 if (inst
.operands
[2].writeback
11014 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11015 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11016 as_warn (_("base register written back, and overlaps "
11017 "one of transfer registers"));
11019 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11020 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11021 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11027 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11028 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11034 unsigned Rd
, Rn
, Rm
, Ra
;
11036 Rd
= inst
.operands
[0].reg
;
11037 Rn
= inst
.operands
[1].reg
;
11038 Rm
= inst
.operands
[2].reg
;
11039 Ra
= inst
.operands
[3].reg
;
11041 reject_bad_reg (Rd
);
11042 reject_bad_reg (Rn
);
11043 reject_bad_reg (Rm
);
11044 reject_bad_reg (Ra
);
11046 inst
.instruction
|= Rd
<< 8;
11047 inst
.instruction
|= Rn
<< 16;
11048 inst
.instruction
|= Rm
;
11049 inst
.instruction
|= Ra
<< 12;
11055 unsigned RdLo
, RdHi
, Rn
, Rm
;
11057 RdLo
= inst
.operands
[0].reg
;
11058 RdHi
= inst
.operands
[1].reg
;
11059 Rn
= inst
.operands
[2].reg
;
11060 Rm
= inst
.operands
[3].reg
;
11062 reject_bad_reg (RdLo
);
11063 reject_bad_reg (RdHi
);
11064 reject_bad_reg (Rn
);
11065 reject_bad_reg (Rm
);
11067 inst
.instruction
|= RdLo
<< 12;
11068 inst
.instruction
|= RdHi
<< 8;
11069 inst
.instruction
|= Rn
<< 16;
11070 inst
.instruction
|= Rm
;
11074 do_t_mov_cmp (void)
11078 Rn
= inst
.operands
[0].reg
;
11079 Rm
= inst
.operands
[1].reg
;
11082 set_it_insn_type_last ();
11084 if (unified_syntax
)
11086 int r0off
= (inst
.instruction
== T_MNEM_mov
11087 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11088 unsigned long opcode
;
11089 bfd_boolean narrow
;
11090 bfd_boolean low_regs
;
11092 low_regs
= (Rn
<= 7 && Rm
<= 7);
11093 opcode
= inst
.instruction
;
11094 if (in_it_block ())
11095 narrow
= opcode
!= T_MNEM_movs
;
11097 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11098 if (inst
.size_req
== 4
11099 || inst
.operands
[1].shifted
)
11102 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11103 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11104 && !inst
.operands
[1].shifted
11108 inst
.instruction
= T2_SUBS_PC_LR
;
11112 if (opcode
== T_MNEM_cmp
)
11114 constraint (Rn
== REG_PC
, BAD_PC
);
11117 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11119 warn_deprecated_sp (Rm
);
11120 /* R15 was documented as a valid choice for Rm in ARMv6,
11121 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11122 tools reject R15, so we do too. */
11123 constraint (Rm
== REG_PC
, BAD_PC
);
11126 reject_bad_reg (Rm
);
11128 else if (opcode
== T_MNEM_mov
11129 || opcode
== T_MNEM_movs
)
11131 if (inst
.operands
[1].isreg
)
11133 if (opcode
== T_MNEM_movs
)
11135 reject_bad_reg (Rn
);
11136 reject_bad_reg (Rm
);
11140 /* This is mov.n. */
11141 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11142 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11144 as_warn (_("Use of r%u as a source register is "
11145 "deprecated when r%u is the destination "
11146 "register."), Rm
, Rn
);
11151 /* This is mov.w. */
11152 constraint (Rn
== REG_PC
, BAD_PC
);
11153 constraint (Rm
== REG_PC
, BAD_PC
);
11154 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11158 reject_bad_reg (Rn
);
11161 if (!inst
.operands
[1].isreg
)
11163 /* Immediate operand. */
11164 if (!in_it_block () && opcode
== T_MNEM_mov
)
11166 if (low_regs
&& narrow
)
11168 inst
.instruction
= THUMB_OP16 (opcode
);
11169 inst
.instruction
|= Rn
<< 8;
11170 if (inst
.size_req
== 2)
11171 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11173 inst
.relax
= opcode
;
11177 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11178 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11179 inst
.instruction
|= Rn
<< r0off
;
11180 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11183 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11184 && (inst
.instruction
== T_MNEM_mov
11185 || inst
.instruction
== T_MNEM_movs
))
11187 /* Register shifts are encoded as separate shift instructions. */
11188 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11190 if (in_it_block ())
11195 if (inst
.size_req
== 4)
11198 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11204 switch (inst
.operands
[1].shift_kind
)
11207 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11210 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11213 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11216 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11222 inst
.instruction
= opcode
;
11225 inst
.instruction
|= Rn
;
11226 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11231 inst
.instruction
|= CONDS_BIT
;
11233 inst
.instruction
|= Rn
<< 8;
11234 inst
.instruction
|= Rm
<< 16;
11235 inst
.instruction
|= inst
.operands
[1].imm
;
11240 /* Some mov with immediate shift have narrow variants.
11241 Register shifts are handled above. */
11242 if (low_regs
&& inst
.operands
[1].shifted
11243 && (inst
.instruction
== T_MNEM_mov
11244 || inst
.instruction
== T_MNEM_movs
))
11246 if (in_it_block ())
11247 narrow
= (inst
.instruction
== T_MNEM_mov
);
11249 narrow
= (inst
.instruction
== T_MNEM_movs
);
11254 switch (inst
.operands
[1].shift_kind
)
11256 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11257 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11258 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11259 default: narrow
= FALSE
; break;
11265 inst
.instruction
|= Rn
;
11266 inst
.instruction
|= Rm
<< 3;
11267 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11271 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11272 inst
.instruction
|= Rn
<< r0off
;
11273 encode_thumb32_shifted_operand (1);
11277 switch (inst
.instruction
)
11280 /* In v4t or v5t a move of two lowregs produces unpredictable
11281 results. Don't allow this. */
11284 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11285 "MOV Rd, Rs with two low registers is not "
11286 "permitted on this architecture");
11287 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11291 inst
.instruction
= T_OPCODE_MOV_HR
;
11292 inst
.instruction
|= (Rn
& 0x8) << 4;
11293 inst
.instruction
|= (Rn
& 0x7);
11294 inst
.instruction
|= Rm
<< 3;
11298 /* We know we have low registers at this point.
11299 Generate LSLS Rd, Rs, #0. */
11300 inst
.instruction
= T_OPCODE_LSL_I
;
11301 inst
.instruction
|= Rn
;
11302 inst
.instruction
|= Rm
<< 3;
11308 inst
.instruction
= T_OPCODE_CMP_LR
;
11309 inst
.instruction
|= Rn
;
11310 inst
.instruction
|= Rm
<< 3;
11314 inst
.instruction
= T_OPCODE_CMP_HR
;
11315 inst
.instruction
|= (Rn
& 0x8) << 4;
11316 inst
.instruction
|= (Rn
& 0x7);
11317 inst
.instruction
|= Rm
<< 3;
11324 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11326 /* PR 10443: Do not silently ignore shifted operands. */
11327 constraint (inst
.operands
[1].shifted
,
11328 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11330 if (inst
.operands
[1].isreg
)
11332 if (Rn
< 8 && Rm
< 8)
11334 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11335 since a MOV instruction produces unpredictable results. */
11336 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11337 inst
.instruction
= T_OPCODE_ADD_I3
;
11339 inst
.instruction
= T_OPCODE_CMP_LR
;
11341 inst
.instruction
|= Rn
;
11342 inst
.instruction
|= Rm
<< 3;
11346 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11347 inst
.instruction
= T_OPCODE_MOV_HR
;
11349 inst
.instruction
= T_OPCODE_CMP_HR
;
11355 constraint (Rn
> 7,
11356 _("only lo regs allowed with immediate"));
11357 inst
.instruction
|= Rn
<< 8;
11358 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11369 top
= (inst
.instruction
& 0x00800000) != 0;
11370 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11372 constraint (top
, _(":lower16: not allowed this instruction"));
11373 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11375 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11377 constraint (!top
, _(":upper16: not allowed this instruction"));
11378 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11381 Rd
= inst
.operands
[0].reg
;
11382 reject_bad_reg (Rd
);
11384 inst
.instruction
|= Rd
<< 8;
11385 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11387 imm
= inst
.reloc
.exp
.X_add_number
;
11388 inst
.instruction
|= (imm
& 0xf000) << 4;
11389 inst
.instruction
|= (imm
& 0x0800) << 15;
11390 inst
.instruction
|= (imm
& 0x0700) << 4;
11391 inst
.instruction
|= (imm
& 0x00ff);
11396 do_t_mvn_tst (void)
11400 Rn
= inst
.operands
[0].reg
;
11401 Rm
= inst
.operands
[1].reg
;
11403 if (inst
.instruction
== T_MNEM_cmp
11404 || inst
.instruction
== T_MNEM_cmn
)
11405 constraint (Rn
== REG_PC
, BAD_PC
);
11407 reject_bad_reg (Rn
);
11408 reject_bad_reg (Rm
);
11410 if (unified_syntax
)
11412 int r0off
= (inst
.instruction
== T_MNEM_mvn
11413 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11414 bfd_boolean narrow
;
11416 if (inst
.size_req
== 4
11417 || inst
.instruction
> 0xffff
11418 || inst
.operands
[1].shifted
11419 || Rn
> 7 || Rm
> 7)
11421 else if (inst
.instruction
== T_MNEM_cmn
11422 || inst
.instruction
== T_MNEM_tst
)
11424 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11425 narrow
= !in_it_block ();
11427 narrow
= in_it_block ();
11429 if (!inst
.operands
[1].isreg
)
11431 /* For an immediate, we always generate a 32-bit opcode;
11432 section relaxation will shrink it later if possible. */
11433 if (inst
.instruction
< 0xffff)
11434 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11435 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11436 inst
.instruction
|= Rn
<< r0off
;
11437 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11441 /* See if we can do this with a 16-bit instruction. */
11444 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11445 inst
.instruction
|= Rn
;
11446 inst
.instruction
|= Rm
<< 3;
11450 constraint (inst
.operands
[1].shifted
11451 && inst
.operands
[1].immisreg
,
11452 _("shift must be constant"));
11453 if (inst
.instruction
< 0xffff)
11454 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11455 inst
.instruction
|= Rn
<< r0off
;
11456 encode_thumb32_shifted_operand (1);
11462 constraint (inst
.instruction
> 0xffff
11463 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11464 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11465 _("unshifted register required"));
11466 constraint (Rn
> 7 || Rm
> 7,
11469 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11470 inst
.instruction
|= Rn
;
11471 inst
.instruction
|= Rm
<< 3;
11480 if (do_vfp_nsyn_mrs () == SUCCESS
)
11483 Rd
= inst
.operands
[0].reg
;
11484 reject_bad_reg (Rd
);
11485 inst
.instruction
|= Rd
<< 8;
11487 if (inst
.operands
[1].isreg
)
11489 unsigned br
= inst
.operands
[1].reg
;
11490 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11491 as_bad (_("bad register for mrs"));
11493 inst
.instruction
|= br
& (0xf << 16);
11494 inst
.instruction
|= (br
& 0x300) >> 4;
11495 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11499 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11501 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11503 /* PR gas/12698: The constraint is only applied for m_profile.
11504 If the user has specified -march=all, we want to ignore it as
11505 we are building for any CPU type, including non-m variants. */
11506 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11507 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
11508 "not support requested special purpose register"));
11511 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11513 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11514 _("'APSR', 'CPSR' or 'SPSR' expected"));
11516 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11517 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11518 inst
.instruction
|= 0xf0000;
11528 if (do_vfp_nsyn_msr () == SUCCESS
)
11531 constraint (!inst
.operands
[1].isreg
,
11532 _("Thumb encoding does not support an immediate here"));
11534 if (inst
.operands
[0].isreg
)
11535 flags
= (int)(inst
.operands
[0].reg
);
11537 flags
= inst
.operands
[0].imm
;
11539 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11541 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11543 /* PR gas/12698: The constraint is only applied for m_profile.
11544 If the user has specified -march=all, we want to ignore it as
11545 we are building for any CPU type, including non-m variants. */
11546 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11547 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11548 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11549 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11550 && bits
!= PSR_f
)) && m_profile
,
11551 _("selected processor does not support requested special "
11552 "purpose register"));
11555 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11556 "requested special purpose register"));
11558 Rn
= inst
.operands
[1].reg
;
11559 reject_bad_reg (Rn
);
11561 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11562 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11563 inst
.instruction
|= (flags
& 0x300) >> 4;
11564 inst
.instruction
|= (flags
& 0xff);
11565 inst
.instruction
|= Rn
<< 16;
11571 bfd_boolean narrow
;
11572 unsigned Rd
, Rn
, Rm
;
11574 if (!inst
.operands
[2].present
)
11575 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11577 Rd
= inst
.operands
[0].reg
;
11578 Rn
= inst
.operands
[1].reg
;
11579 Rm
= inst
.operands
[2].reg
;
11581 if (unified_syntax
)
11583 if (inst
.size_req
== 4
11589 else if (inst
.instruction
== T_MNEM_muls
)
11590 narrow
= !in_it_block ();
11592 narrow
= in_it_block ();
11596 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11597 constraint (Rn
> 7 || Rm
> 7,
11604 /* 16-bit MULS/Conditional MUL. */
11605 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11606 inst
.instruction
|= Rd
;
11609 inst
.instruction
|= Rm
<< 3;
11611 inst
.instruction
|= Rn
<< 3;
11613 constraint (1, _("dest must overlap one source register"));
11617 constraint (inst
.instruction
!= T_MNEM_mul
,
11618 _("Thumb-2 MUL must not set flags"));
11620 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11621 inst
.instruction
|= Rd
<< 8;
11622 inst
.instruction
|= Rn
<< 16;
11623 inst
.instruction
|= Rm
<< 0;
11625 reject_bad_reg (Rd
);
11626 reject_bad_reg (Rn
);
11627 reject_bad_reg (Rm
);
11634 unsigned RdLo
, RdHi
, Rn
, Rm
;
11636 RdLo
= inst
.operands
[0].reg
;
11637 RdHi
= inst
.operands
[1].reg
;
11638 Rn
= inst
.operands
[2].reg
;
11639 Rm
= inst
.operands
[3].reg
;
11641 reject_bad_reg (RdLo
);
11642 reject_bad_reg (RdHi
);
11643 reject_bad_reg (Rn
);
11644 reject_bad_reg (Rm
);
11646 inst
.instruction
|= RdLo
<< 12;
11647 inst
.instruction
|= RdHi
<< 8;
11648 inst
.instruction
|= Rn
<< 16;
11649 inst
.instruction
|= Rm
;
11652 as_tsktsk (_("rdhi and rdlo must be different"));
11658 set_it_insn_type (NEUTRAL_IT_INSN
);
11660 if (unified_syntax
)
11662 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11664 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11665 inst
.instruction
|= inst
.operands
[0].imm
;
11669 /* PR9722: Check for Thumb2 availability before
11670 generating a thumb2 nop instruction. */
11671 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11673 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11674 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11677 inst
.instruction
= 0x46c0;
11682 constraint (inst
.operands
[0].present
,
11683 _("Thumb does not support NOP with hints"));
11684 inst
.instruction
= 0x46c0;
11691 if (unified_syntax
)
11693 bfd_boolean narrow
;
11695 if (THUMB_SETS_FLAGS (inst
.instruction
))
11696 narrow
= !in_it_block ();
11698 narrow
= in_it_block ();
11699 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11701 if (inst
.size_req
== 4)
11706 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11707 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11708 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11712 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11713 inst
.instruction
|= inst
.operands
[0].reg
;
11714 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11719 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11721 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11723 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11724 inst
.instruction
|= inst
.operands
[0].reg
;
11725 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11734 Rd
= inst
.operands
[0].reg
;
11735 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11737 reject_bad_reg (Rd
);
11738 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11739 reject_bad_reg (Rn
);
11741 inst
.instruction
|= Rd
<< 8;
11742 inst
.instruction
|= Rn
<< 16;
11744 if (!inst
.operands
[2].isreg
)
11746 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11747 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11753 Rm
= inst
.operands
[2].reg
;
11754 reject_bad_reg (Rm
);
11756 constraint (inst
.operands
[2].shifted
11757 && inst
.operands
[2].immisreg
,
11758 _("shift must be constant"));
11759 encode_thumb32_shifted_operand (2);
11766 unsigned Rd
, Rn
, Rm
;
11768 Rd
= inst
.operands
[0].reg
;
11769 Rn
= inst
.operands
[1].reg
;
11770 Rm
= inst
.operands
[2].reg
;
11772 reject_bad_reg (Rd
);
11773 reject_bad_reg (Rn
);
11774 reject_bad_reg (Rm
);
11776 inst
.instruction
|= Rd
<< 8;
11777 inst
.instruction
|= Rn
<< 16;
11778 inst
.instruction
|= Rm
;
11779 if (inst
.operands
[3].present
)
11781 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11782 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11783 _("expression too complex"));
11784 inst
.instruction
|= (val
& 0x1c) << 10;
11785 inst
.instruction
|= (val
& 0x03) << 6;
11792 if (!inst
.operands
[3].present
)
11796 inst
.instruction
&= ~0x00000020;
11798 /* PR 10168. Swap the Rm and Rn registers. */
11799 Rtmp
= inst
.operands
[1].reg
;
11800 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11801 inst
.operands
[2].reg
= Rtmp
;
11809 if (inst
.operands
[0].immisreg
)
11810 reject_bad_reg (inst
.operands
[0].imm
);
11812 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11816 do_t_push_pop (void)
11820 constraint (inst
.operands
[0].writeback
,
11821 _("push/pop do not support {reglist}^"));
11822 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11823 _("expression too complex"));
11825 mask
= inst
.operands
[0].imm
;
11826 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
11827 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11828 else if (inst
.size_req
!= 4
11829 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
11830 ? REG_LR
: REG_PC
)))
11832 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11833 inst
.instruction
|= THUMB_PP_PC_LR
;
11834 inst
.instruction
|= mask
& 0xff;
11836 else if (unified_syntax
)
11838 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11839 encode_thumb2_ldmstm (13, mask
, TRUE
);
11843 inst
.error
= _("invalid register list to push/pop instruction");
11853 Rd
= inst
.operands
[0].reg
;
11854 Rm
= inst
.operands
[1].reg
;
11856 reject_bad_reg (Rd
);
11857 reject_bad_reg (Rm
);
11859 inst
.instruction
|= Rd
<< 8;
11860 inst
.instruction
|= Rm
<< 16;
11861 inst
.instruction
|= Rm
;
11869 Rd
= inst
.operands
[0].reg
;
11870 Rm
= inst
.operands
[1].reg
;
11872 reject_bad_reg (Rd
);
11873 reject_bad_reg (Rm
);
11875 if (Rd
<= 7 && Rm
<= 7
11876 && inst
.size_req
!= 4)
11878 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11879 inst
.instruction
|= Rd
;
11880 inst
.instruction
|= Rm
<< 3;
11882 else if (unified_syntax
)
11884 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11885 inst
.instruction
|= Rd
<< 8;
11886 inst
.instruction
|= Rm
<< 16;
11887 inst
.instruction
|= Rm
;
11890 inst
.error
= BAD_HIREG
;
11898 Rd
= inst
.operands
[0].reg
;
11899 Rm
= inst
.operands
[1].reg
;
11901 reject_bad_reg (Rd
);
11902 reject_bad_reg (Rm
);
11904 inst
.instruction
|= Rd
<< 8;
11905 inst
.instruction
|= Rm
;
11913 Rd
= inst
.operands
[0].reg
;
11914 Rs
= (inst
.operands
[1].present
11915 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11916 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11918 reject_bad_reg (Rd
);
11919 reject_bad_reg (Rs
);
11920 if (inst
.operands
[2].isreg
)
11921 reject_bad_reg (inst
.operands
[2].reg
);
11923 inst
.instruction
|= Rd
<< 8;
11924 inst
.instruction
|= Rs
<< 16;
11925 if (!inst
.operands
[2].isreg
)
11927 bfd_boolean narrow
;
11929 if ((inst
.instruction
& 0x00100000) != 0)
11930 narrow
= !in_it_block ();
11932 narrow
= in_it_block ();
11934 if (Rd
> 7 || Rs
> 7)
11937 if (inst
.size_req
== 4 || !unified_syntax
)
11940 if (inst
.reloc
.exp
.X_op
!= O_constant
11941 || inst
.reloc
.exp
.X_add_number
!= 0)
11944 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11945 relaxation, but it doesn't seem worth the hassle. */
11948 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11949 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11950 inst
.instruction
|= Rs
<< 3;
11951 inst
.instruction
|= Rd
;
11955 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11956 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11960 encode_thumb32_shifted_operand (2);
11966 if (warn_on_deprecated
11967 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11968 as_warn (_("setend use is deprecated for ARMv8"));
11970 set_it_insn_type (OUTSIDE_IT_INSN
);
11971 if (inst
.operands
[0].imm
)
11972 inst
.instruction
|= 0x8;
11978 if (!inst
.operands
[1].present
)
11979 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11981 if (unified_syntax
)
11983 bfd_boolean narrow
;
11986 switch (inst
.instruction
)
11989 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11991 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11993 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11995 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11999 if (THUMB_SETS_FLAGS (inst
.instruction
))
12000 narrow
= !in_it_block ();
12002 narrow
= in_it_block ();
12003 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12005 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12007 if (inst
.operands
[2].isreg
12008 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12009 || inst
.operands
[2].reg
> 7))
12011 if (inst
.size_req
== 4)
12014 reject_bad_reg (inst
.operands
[0].reg
);
12015 reject_bad_reg (inst
.operands
[1].reg
);
12019 if (inst
.operands
[2].isreg
)
12021 reject_bad_reg (inst
.operands
[2].reg
);
12022 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12023 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12024 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12025 inst
.instruction
|= inst
.operands
[2].reg
;
12027 /* PR 12854: Error on extraneous shifts. */
12028 constraint (inst
.operands
[2].shifted
,
12029 _("extraneous shift as part of operand to shift insn"));
12033 inst
.operands
[1].shifted
= 1;
12034 inst
.operands
[1].shift_kind
= shift_kind
;
12035 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12036 ? T_MNEM_movs
: T_MNEM_mov
);
12037 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12038 encode_thumb32_shifted_operand (1);
12039 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12040 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12045 if (inst
.operands
[2].isreg
)
12047 switch (shift_kind
)
12049 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12050 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12051 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12052 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12056 inst
.instruction
|= inst
.operands
[0].reg
;
12057 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12059 /* PR 12854: Error on extraneous shifts. */
12060 constraint (inst
.operands
[2].shifted
,
12061 _("extraneous shift as part of operand to shift insn"));
12065 switch (shift_kind
)
12067 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12068 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12069 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12072 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12073 inst
.instruction
|= inst
.operands
[0].reg
;
12074 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12080 constraint (inst
.operands
[0].reg
> 7
12081 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12082 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12084 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12086 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12087 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12088 _("source1 and dest must be same register"));
12090 switch (inst
.instruction
)
12092 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12093 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12094 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12095 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12099 inst
.instruction
|= inst
.operands
[0].reg
;
12100 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12102 /* PR 12854: Error on extraneous shifts. */
12103 constraint (inst
.operands
[2].shifted
,
12104 _("extraneous shift as part of operand to shift insn"));
12108 switch (inst
.instruction
)
12110 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12111 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12112 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12113 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12116 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12117 inst
.instruction
|= inst
.operands
[0].reg
;
12118 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12126 unsigned Rd
, Rn
, Rm
;
12128 Rd
= inst
.operands
[0].reg
;
12129 Rn
= inst
.operands
[1].reg
;
12130 Rm
= inst
.operands
[2].reg
;
12132 reject_bad_reg (Rd
);
12133 reject_bad_reg (Rn
);
12134 reject_bad_reg (Rm
);
12136 inst
.instruction
|= Rd
<< 8;
12137 inst
.instruction
|= Rn
<< 16;
12138 inst
.instruction
|= Rm
;
12144 unsigned Rd
, Rn
, Rm
;
12146 Rd
= inst
.operands
[0].reg
;
12147 Rm
= inst
.operands
[1].reg
;
12148 Rn
= inst
.operands
[2].reg
;
12150 reject_bad_reg (Rd
);
12151 reject_bad_reg (Rn
);
12152 reject_bad_reg (Rm
);
12154 inst
.instruction
|= Rd
<< 8;
12155 inst
.instruction
|= Rn
<< 16;
12156 inst
.instruction
|= Rm
;
12162 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12163 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12164 _("SMC is not permitted on this architecture"));
12165 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12166 _("expression too complex"));
12167 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12168 inst
.instruction
|= (value
& 0xf000) >> 12;
12169 inst
.instruction
|= (value
& 0x0ff0);
12170 inst
.instruction
|= (value
& 0x000f) << 16;
12171 /* PR gas/15623: SMC instructions must be last in an IT block. */
12172 set_it_insn_type_last ();
12178 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12180 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12181 inst
.instruction
|= (value
& 0x0fff);
12182 inst
.instruction
|= (value
& 0xf000) << 4;
12186 do_t_ssat_usat (int bias
)
12190 Rd
= inst
.operands
[0].reg
;
12191 Rn
= inst
.operands
[2].reg
;
12193 reject_bad_reg (Rd
);
12194 reject_bad_reg (Rn
);
12196 inst
.instruction
|= Rd
<< 8;
12197 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12198 inst
.instruction
|= Rn
<< 16;
12200 if (inst
.operands
[3].present
)
12202 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12204 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12206 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12207 _("expression too complex"));
12209 if (shift_amount
!= 0)
12211 constraint (shift_amount
> 31,
12212 _("shift expression is too large"));
12214 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12215 inst
.instruction
|= 0x00200000; /* sh bit. */
12217 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12218 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12226 do_t_ssat_usat (1);
12234 Rd
= inst
.operands
[0].reg
;
12235 Rn
= inst
.operands
[2].reg
;
12237 reject_bad_reg (Rd
);
12238 reject_bad_reg (Rn
);
12240 inst
.instruction
|= Rd
<< 8;
12241 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12242 inst
.instruction
|= Rn
<< 16;
12248 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12249 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12250 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12251 || inst
.operands
[2].negative
,
12254 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12256 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12257 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12258 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12259 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12265 if (!inst
.operands
[2].present
)
12266 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12268 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12269 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12270 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12273 inst
.instruction
|= inst
.operands
[0].reg
;
12274 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12275 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12276 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12282 unsigned Rd
, Rn
, Rm
;
12284 Rd
= inst
.operands
[0].reg
;
12285 Rn
= inst
.operands
[1].reg
;
12286 Rm
= inst
.operands
[2].reg
;
12288 reject_bad_reg (Rd
);
12289 reject_bad_reg (Rn
);
12290 reject_bad_reg (Rm
);
12292 inst
.instruction
|= Rd
<< 8;
12293 inst
.instruction
|= Rn
<< 16;
12294 inst
.instruction
|= Rm
;
12295 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12303 Rd
= inst
.operands
[0].reg
;
12304 Rm
= inst
.operands
[1].reg
;
12306 reject_bad_reg (Rd
);
12307 reject_bad_reg (Rm
);
12309 if (inst
.instruction
<= 0xffff
12310 && inst
.size_req
!= 4
12311 && Rd
<= 7 && Rm
<= 7
12312 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12314 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12315 inst
.instruction
|= Rd
;
12316 inst
.instruction
|= Rm
<< 3;
12318 else if (unified_syntax
)
12320 if (inst
.instruction
<= 0xffff)
12321 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12322 inst
.instruction
|= Rd
<< 8;
12323 inst
.instruction
|= Rm
;
12324 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12328 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12329 _("Thumb encoding does not support rotation"));
12330 constraint (1, BAD_HIREG
);
12337 /* We have to do the following check manually as ARM_EXT_OS only applies
12339 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12341 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12342 /* This only applies to the v6m howver, not later architectures. */
12343 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12344 as_bad (_("SVC is not permitted on this architecture"));
12345 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12348 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12357 half
= (inst
.instruction
& 0x10) != 0;
12358 set_it_insn_type_last ();
12359 constraint (inst
.operands
[0].immisreg
,
12360 _("instruction requires register index"));
12362 Rn
= inst
.operands
[0].reg
;
12363 Rm
= inst
.operands
[0].imm
;
12365 constraint (Rn
== REG_SP
, BAD_SP
);
12366 reject_bad_reg (Rm
);
12368 constraint (!half
&& inst
.operands
[0].shifted
,
12369 _("instruction does not allow shifted index"));
12370 inst
.instruction
|= (Rn
<< 16) | Rm
;
12376 if (!inst
.operands
[0].present
)
12377 inst
.operands
[0].imm
= 0;
12379 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12381 constraint (inst
.size_req
== 2,
12382 _("immediate value out of range"));
12383 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12384 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12385 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12389 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12390 inst
.instruction
|= inst
.operands
[0].imm
;
12393 set_it_insn_type (NEUTRAL_IT_INSN
);
12400 do_t_ssat_usat (0);
12408 Rd
= inst
.operands
[0].reg
;
12409 Rn
= inst
.operands
[2].reg
;
12411 reject_bad_reg (Rd
);
12412 reject_bad_reg (Rn
);
12414 inst
.instruction
|= Rd
<< 8;
12415 inst
.instruction
|= inst
.operands
[1].imm
;
12416 inst
.instruction
|= Rn
<< 16;
12419 /* Neon instruction encoder helpers. */
12421 /* Encodings for the different types for various Neon opcodes. */
12423 /* An "invalid" code for the following tables. */
12426 struct neon_tab_entry
12429 unsigned float_or_poly
;
12430 unsigned scalar_or_imm
;
12433 /* Map overloaded Neon opcodes to their respective encodings. */
12434 #define NEON_ENC_TAB \
12435 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12436 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12437 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12438 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12439 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12440 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12441 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12442 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12443 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12444 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12445 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12446 /* Register variants of the following two instructions are encoded as
12447 vcge / vcgt with the operands reversed. */ \
12448 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12449 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12450 X(vfma, N_INV, 0x0000c10, N_INV), \
12451 X(vfms, N_INV, 0x0200c10, N_INV), \
12452 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12453 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12454 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12455 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12456 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12457 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12458 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12459 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12460 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12461 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12462 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12463 X(vshl, 0x0000400, N_INV, 0x0800510), \
12464 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12465 X(vand, 0x0000110, N_INV, 0x0800030), \
12466 X(vbic, 0x0100110, N_INV, 0x0800030), \
12467 X(veor, 0x1000110, N_INV, N_INV), \
12468 X(vorn, 0x0300110, N_INV, 0x0800010), \
12469 X(vorr, 0x0200110, N_INV, 0x0800010), \
12470 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12471 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12472 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12473 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12474 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12475 X(vst1, 0x0000000, 0x0800000, N_INV), \
12476 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12477 X(vst2, 0x0000100, 0x0800100, N_INV), \
12478 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12479 X(vst3, 0x0000200, 0x0800200, N_INV), \
12480 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12481 X(vst4, 0x0000300, 0x0800300, N_INV), \
12482 X(vmovn, 0x1b20200, N_INV, N_INV), \
12483 X(vtrn, 0x1b20080, N_INV, N_INV), \
12484 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12485 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12486 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12487 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12488 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12489 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12490 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12491 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12492 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12493 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12494 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12495 X(vseleq, 0xe000a00, N_INV, N_INV), \
12496 X(vselvs, 0xe100a00, N_INV, N_INV), \
12497 X(vselge, 0xe200a00, N_INV, N_INV), \
12498 X(vselgt, 0xe300a00, N_INV, N_INV), \
12499 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12500 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12501 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12502 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12503 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12504 X(aes, 0x3b00300, N_INV, N_INV), \
12505 X(sha3op, 0x2000c00, N_INV, N_INV), \
12506 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12507 X(sha2op, 0x3ba0380, N_INV, N_INV)
12511 #define X(OPC,I,F,S) N_MNEM_##OPC
12516 static const struct neon_tab_entry neon_enc_tab
[] =
12518 #define X(OPC,I,F,S) { (I), (F), (S) }
12523 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12524 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12525 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12526 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12527 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12528 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12529 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12530 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12531 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12532 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12533 #define NEON_ENC_SINGLE_(X) \
12534 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12535 #define NEON_ENC_DOUBLE_(X) \
12536 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12537 #define NEON_ENC_FPV8_(X) \
12538 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12540 #define NEON_ENCODE(type, inst) \
12543 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12544 inst.is_neon = 1; \
12548 #define check_neon_suffixes \
12551 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12553 as_bad (_("invalid neon suffix for non neon instruction")); \
12559 /* Define shapes for instruction operands. The following mnemonic characters
12560 are used in this table:
12562 F - VFP S<n> register
12563 D - Neon D<n> register
12564 Q - Neon Q<n> register
12568 L - D<n> register list
12570 This table is used to generate various data:
12571 - enumerations of the form NS_DDR to be used as arguments to
12573 - a table classifying shapes into single, double, quad, mixed.
12574 - a table used to drive neon_select_shape. */
12576 #define NEON_SHAPE_DEF \
12577 X(3, (D, D, D), DOUBLE), \
12578 X(3, (Q, Q, Q), QUAD), \
12579 X(3, (D, D, I), DOUBLE), \
12580 X(3, (Q, Q, I), QUAD), \
12581 X(3, (D, D, S), DOUBLE), \
12582 X(3, (Q, Q, S), QUAD), \
12583 X(2, (D, D), DOUBLE), \
12584 X(2, (Q, Q), QUAD), \
12585 X(2, (D, S), DOUBLE), \
12586 X(2, (Q, S), QUAD), \
12587 X(2, (D, R), DOUBLE), \
12588 X(2, (Q, R), QUAD), \
12589 X(2, (D, I), DOUBLE), \
12590 X(2, (Q, I), QUAD), \
12591 X(3, (D, L, D), DOUBLE), \
12592 X(2, (D, Q), MIXED), \
12593 X(2, (Q, D), MIXED), \
12594 X(3, (D, Q, I), MIXED), \
12595 X(3, (Q, D, I), MIXED), \
12596 X(3, (Q, D, D), MIXED), \
12597 X(3, (D, Q, Q), MIXED), \
12598 X(3, (Q, Q, D), MIXED), \
12599 X(3, (Q, D, S), MIXED), \
12600 X(3, (D, Q, S), MIXED), \
12601 X(4, (D, D, D, I), DOUBLE), \
12602 X(4, (Q, Q, Q, I), QUAD), \
12603 X(2, (F, F), SINGLE), \
12604 X(3, (F, F, F), SINGLE), \
12605 X(2, (F, I), SINGLE), \
12606 X(2, (F, D), MIXED), \
12607 X(2, (D, F), MIXED), \
12608 X(3, (F, F, I), MIXED), \
12609 X(4, (R, R, F, F), SINGLE), \
12610 X(4, (F, F, R, R), SINGLE), \
12611 X(3, (D, R, R), DOUBLE), \
12612 X(3, (R, R, D), DOUBLE), \
12613 X(2, (S, R), SINGLE), \
12614 X(2, (R, S), SINGLE), \
12615 X(2, (F, R), SINGLE), \
12616 X(2, (R, F), SINGLE)
12618 #define S2(A,B) NS_##A##B
12619 #define S3(A,B,C) NS_##A##B##C
12620 #define S4(A,B,C,D) NS_##A##B##C##D
12622 #define X(N, L, C) S##N L
12635 enum neon_shape_class
12643 #define X(N, L, C) SC_##C
12645 static enum neon_shape_class neon_shape_class
[] =
12663 /* Register widths of above. */
12664 static unsigned neon_shape_el_size
[] =
12675 struct neon_shape_info
12678 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12681 #define S2(A,B) { SE_##A, SE_##B }
12682 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12683 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12685 #define X(N, L, C) { N, S##N L }
12687 static struct neon_shape_info neon_shape_tab
[] =
12697 /* Bit masks used in type checking given instructions.
12698 'N_EQK' means the type must be the same as (or based on in some way) the key
12699 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12700 set, various other bits can be set as well in order to modify the meaning of
12701 the type constraint. */
12703 enum neon_type_mask
12727 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12728 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12729 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12730 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
12731 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12732 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12733 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12734 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12735 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12736 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12737 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12739 N_MAX_NONSPECIAL
= N_P64
12742 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12744 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12745 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12746 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12747 #define N_SUF_32 (N_SU_32 | N_F32)
12748 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12749 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12751 /* Pass this as the first type argument to neon_check_type to ignore types
12753 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12755 /* Select a "shape" for the current instruction (describing register types or
12756 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12757 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12758 function of operand parsing, so this function doesn't need to be called.
12759 Shapes should be listed in order of decreasing length. */
12761 static enum neon_shape
12762 neon_select_shape (enum neon_shape shape
, ...)
12765 enum neon_shape first_shape
= shape
;
12767 /* Fix missing optional operands. FIXME: we don't know at this point how
12768 many arguments we should have, so this makes the assumption that we have
12769 > 1. This is true of all current Neon opcodes, I think, but may not be
12770 true in the future. */
12771 if (!inst
.operands
[1].present
)
12772 inst
.operands
[1] = inst
.operands
[0];
12774 va_start (ap
, shape
);
12776 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12781 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12783 if (!inst
.operands
[j
].present
)
12789 switch (neon_shape_tab
[shape
].el
[j
])
12792 if (!(inst
.operands
[j
].isreg
12793 && inst
.operands
[j
].isvec
12794 && inst
.operands
[j
].issingle
12795 && !inst
.operands
[j
].isquad
))
12800 if (!(inst
.operands
[j
].isreg
12801 && inst
.operands
[j
].isvec
12802 && !inst
.operands
[j
].isquad
12803 && !inst
.operands
[j
].issingle
))
12808 if (!(inst
.operands
[j
].isreg
12809 && !inst
.operands
[j
].isvec
))
12814 if (!(inst
.operands
[j
].isreg
12815 && inst
.operands
[j
].isvec
12816 && inst
.operands
[j
].isquad
12817 && !inst
.operands
[j
].issingle
))
12822 if (!(!inst
.operands
[j
].isreg
12823 && !inst
.operands
[j
].isscalar
))
12828 if (!(!inst
.operands
[j
].isreg
12829 && inst
.operands
[j
].isscalar
))
12839 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
12840 /* We've matched all the entries in the shape table, and we don't
12841 have any left over operands which have not been matched. */
12847 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12848 first_error (_("invalid instruction shape"));
12853 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12854 means the Q bit should be set). */
12857 neon_quad (enum neon_shape shape
)
12859 return neon_shape_class
[shape
] == SC_QUAD
;
12863 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12866 /* Allow modification to be made to types which are constrained to be
12867 based on the key element, based on bits set alongside N_EQK. */
12868 if ((typebits
& N_EQK
) != 0)
12870 if ((typebits
& N_HLF
) != 0)
12872 else if ((typebits
& N_DBL
) != 0)
12874 if ((typebits
& N_SGN
) != 0)
12875 *g_type
= NT_signed
;
12876 else if ((typebits
& N_UNS
) != 0)
12877 *g_type
= NT_unsigned
;
12878 else if ((typebits
& N_INT
) != 0)
12879 *g_type
= NT_integer
;
12880 else if ((typebits
& N_FLT
) != 0)
12881 *g_type
= NT_float
;
12882 else if ((typebits
& N_SIZ
) != 0)
12883 *g_type
= NT_untyped
;
12887 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12888 operand type, i.e. the single type specified in a Neon instruction when it
12889 is the only one given. */
12891 static struct neon_type_el
12892 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12894 struct neon_type_el dest
= *key
;
12896 gas_assert ((thisarg
& N_EQK
) != 0);
12898 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12903 /* Convert Neon type and size into compact bitmask representation. */
12905 static enum neon_type_mask
12906 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12913 case 8: return N_8
;
12914 case 16: return N_16
;
12915 case 32: return N_32
;
12916 case 64: return N_64
;
12924 case 8: return N_I8
;
12925 case 16: return N_I16
;
12926 case 32: return N_I32
;
12927 case 64: return N_I64
;
12935 case 16: return N_F16
;
12936 case 32: return N_F32
;
12937 case 64: return N_F64
;
12945 case 8: return N_P8
;
12946 case 16: return N_P16
;
12947 case 64: return N_P64
;
12955 case 8: return N_S8
;
12956 case 16: return N_S16
;
12957 case 32: return N_S32
;
12958 case 64: return N_S64
;
12966 case 8: return N_U8
;
12967 case 16: return N_U16
;
12968 case 32: return N_U32
;
12969 case 64: return N_U64
;
12980 /* Convert compact Neon bitmask type representation to a type and size. Only
12981 handles the case where a single bit is set in the mask. */
12984 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12985 enum neon_type_mask mask
)
12987 if ((mask
& N_EQK
) != 0)
12990 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12992 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
12994 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12996 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13001 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13003 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13004 *type
= NT_unsigned
;
13005 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13006 *type
= NT_integer
;
13007 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13008 *type
= NT_untyped
;
13009 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13011 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13019 /* Modify a bitmask of allowed types. This is only needed for type
13023 modify_types_allowed (unsigned allowed
, unsigned mods
)
13026 enum neon_el_type type
;
13032 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13034 if (el_type_of_type_chk (&type
, &size
,
13035 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13037 neon_modify_type_size (mods
, &type
, &size
);
13038 destmask
|= type_chk_of_el_type (type
, size
);
13045 /* Check type and return type classification.
13046 The manual states (paraphrase): If one datatype is given, it indicates the
13048 - the second operand, if there is one
13049 - the operand, if there is no second operand
13050 - the result, if there are no operands.
13051 This isn't quite good enough though, so we use a concept of a "key" datatype
13052 which is set on a per-instruction basis, which is the one which matters when
13053 only one data type is written.
13054 Note: this function has side-effects (e.g. filling in missing operands). All
13055 Neon instructions should call it before performing bit encoding. */
13057 static struct neon_type_el
13058 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13061 unsigned i
, pass
, key_el
= 0;
13062 unsigned types
[NEON_MAX_TYPE_ELS
];
13063 enum neon_el_type k_type
= NT_invtype
;
13064 unsigned k_size
= -1u;
13065 struct neon_type_el badtype
= {NT_invtype
, -1};
13066 unsigned key_allowed
= 0;
13068 /* Optional registers in Neon instructions are always (not) in operand 1.
13069 Fill in the missing operand here, if it was omitted. */
13070 if (els
> 1 && !inst
.operands
[1].present
)
13071 inst
.operands
[1] = inst
.operands
[0];
13073 /* Suck up all the varargs. */
13075 for (i
= 0; i
< els
; i
++)
13077 unsigned thisarg
= va_arg (ap
, unsigned);
13078 if (thisarg
== N_IGNORE_TYPE
)
13083 types
[i
] = thisarg
;
13084 if ((thisarg
& N_KEY
) != 0)
13089 if (inst
.vectype
.elems
> 0)
13090 for (i
= 0; i
< els
; i
++)
13091 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13093 first_error (_("types specified in both the mnemonic and operands"));
13097 /* Duplicate inst.vectype elements here as necessary.
13098 FIXME: No idea if this is exactly the same as the ARM assembler,
13099 particularly when an insn takes one register and one non-register
13101 if (inst
.vectype
.elems
== 1 && els
> 1)
13104 inst
.vectype
.elems
= els
;
13105 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13106 for (j
= 0; j
< els
; j
++)
13108 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13111 else if (inst
.vectype
.elems
== 0 && els
> 0)
13114 /* No types were given after the mnemonic, so look for types specified
13115 after each operand. We allow some flexibility here; as long as the
13116 "key" operand has a type, we can infer the others. */
13117 for (j
= 0; j
< els
; j
++)
13118 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13119 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13121 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13123 for (j
= 0; j
< els
; j
++)
13124 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13125 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13130 first_error (_("operand types can't be inferred"));
13134 else if (inst
.vectype
.elems
!= els
)
13136 first_error (_("type specifier has the wrong number of parts"));
13140 for (pass
= 0; pass
< 2; pass
++)
13142 for (i
= 0; i
< els
; i
++)
13144 unsigned thisarg
= types
[i
];
13145 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13146 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13147 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13148 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13150 /* Decay more-specific signed & unsigned types to sign-insensitive
13151 integer types if sign-specific variants are unavailable. */
13152 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13153 && (types_allowed
& N_SU_ALL
) == 0)
13154 g_type
= NT_integer
;
13156 /* If only untyped args are allowed, decay any more specific types to
13157 them. Some instructions only care about signs for some element
13158 sizes, so handle that properly. */
13159 if (((types_allowed
& N_UNT
) == 0)
13160 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13161 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13162 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13163 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13164 g_type
= NT_untyped
;
13168 if ((thisarg
& N_KEY
) != 0)
13172 key_allowed
= thisarg
& ~N_KEY
;
13177 if ((thisarg
& N_VFP
) != 0)
13179 enum neon_shape_el regshape
;
13180 unsigned regwidth
, match
;
13182 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13185 first_error (_("invalid instruction shape"));
13188 regshape
= neon_shape_tab
[ns
].el
[i
];
13189 regwidth
= neon_shape_el_size
[regshape
];
13191 /* In VFP mode, operands must match register widths. If we
13192 have a key operand, use its width, else use the width of
13193 the current operand. */
13199 if (regwidth
!= match
)
13201 first_error (_("operand size must match register width"));
13206 if ((thisarg
& N_EQK
) == 0)
13208 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13210 if ((given_type
& types_allowed
) == 0)
13212 first_error (_("bad type in Neon instruction"));
13218 enum neon_el_type mod_k_type
= k_type
;
13219 unsigned mod_k_size
= k_size
;
13220 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13221 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13223 first_error (_("inconsistent types in Neon instruction"));
13231 return inst
.vectype
.el
[key_el
];
13234 /* Neon-style VFP instruction forwarding. */
13236 /* Thumb VFP instructions have 0xE in the condition field. */
13239 do_vfp_cond_or_thumb (void)
13244 inst
.instruction
|= 0xe0000000;
13246 inst
.instruction
|= inst
.cond
<< 28;
13249 /* Look up and encode a simple mnemonic, for use as a helper function for the
13250 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13251 etc. It is assumed that operand parsing has already been done, and that the
13252 operands are in the form expected by the given opcode (this isn't necessarily
13253 the same as the form in which they were parsed, hence some massaging must
13254 take place before this function is called).
13255 Checks current arch version against that in the looked-up opcode. */
13258 do_vfp_nsyn_opcode (const char *opname
)
13260 const struct asm_opcode
*opcode
;
13262 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13267 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13268 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13275 inst
.instruction
= opcode
->tvalue
;
13276 opcode
->tencode ();
13280 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13281 opcode
->aencode ();
13286 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13288 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13293 do_vfp_nsyn_opcode ("fadds");
13295 do_vfp_nsyn_opcode ("fsubs");
13300 do_vfp_nsyn_opcode ("faddd");
13302 do_vfp_nsyn_opcode ("fsubd");
13306 /* Check operand types to see if this is a VFP instruction, and if so call
13310 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13312 enum neon_shape rs
;
13313 struct neon_type_el et
;
13318 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13319 et
= neon_check_type (2, rs
,
13320 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13324 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13325 et
= neon_check_type (3, rs
,
13326 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13333 if (et
.type
!= NT_invtype
)
13344 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13346 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13351 do_vfp_nsyn_opcode ("fmacs");
13353 do_vfp_nsyn_opcode ("fnmacs");
13358 do_vfp_nsyn_opcode ("fmacd");
13360 do_vfp_nsyn_opcode ("fnmacd");
13365 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13367 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13372 do_vfp_nsyn_opcode ("ffmas");
13374 do_vfp_nsyn_opcode ("ffnmas");
13379 do_vfp_nsyn_opcode ("ffmad");
13381 do_vfp_nsyn_opcode ("ffnmad");
13386 do_vfp_nsyn_mul (enum neon_shape rs
)
13389 do_vfp_nsyn_opcode ("fmuls");
13391 do_vfp_nsyn_opcode ("fmuld");
13395 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13397 int is_neg
= (inst
.instruction
& 0x80) != 0;
13398 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13403 do_vfp_nsyn_opcode ("fnegs");
13405 do_vfp_nsyn_opcode ("fabss");
13410 do_vfp_nsyn_opcode ("fnegd");
13412 do_vfp_nsyn_opcode ("fabsd");
13416 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13417 insns belong to Neon, and are handled elsewhere. */
13420 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13422 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13426 do_vfp_nsyn_opcode ("fldmdbs");
13428 do_vfp_nsyn_opcode ("fldmias");
13433 do_vfp_nsyn_opcode ("fstmdbs");
13435 do_vfp_nsyn_opcode ("fstmias");
13440 do_vfp_nsyn_sqrt (void)
13442 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13443 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13446 do_vfp_nsyn_opcode ("fsqrts");
13448 do_vfp_nsyn_opcode ("fsqrtd");
13452 do_vfp_nsyn_div (void)
13454 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13455 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13456 N_F32
| N_F64
| N_KEY
| N_VFP
);
13459 do_vfp_nsyn_opcode ("fdivs");
13461 do_vfp_nsyn_opcode ("fdivd");
13465 do_vfp_nsyn_nmul (void)
13467 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13468 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13469 N_F32
| N_F64
| N_KEY
| N_VFP
);
13473 NEON_ENCODE (SINGLE
, inst
);
13474 do_vfp_sp_dyadic ();
13478 NEON_ENCODE (DOUBLE
, inst
);
13479 do_vfp_dp_rd_rn_rm ();
13481 do_vfp_cond_or_thumb ();
13485 do_vfp_nsyn_cmp (void)
13487 if (inst
.operands
[1].isreg
)
13489 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13490 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13494 NEON_ENCODE (SINGLE
, inst
);
13495 do_vfp_sp_monadic ();
13499 NEON_ENCODE (DOUBLE
, inst
);
13500 do_vfp_dp_rd_rm ();
13505 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13506 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13508 switch (inst
.instruction
& 0x0fffffff)
13511 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13514 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13522 NEON_ENCODE (SINGLE
, inst
);
13523 do_vfp_sp_compare_z ();
13527 NEON_ENCODE (DOUBLE
, inst
);
13531 do_vfp_cond_or_thumb ();
13535 nsyn_insert_sp (void)
13537 inst
.operands
[1] = inst
.operands
[0];
13538 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13539 inst
.operands
[0].reg
= REG_SP
;
13540 inst
.operands
[0].isreg
= 1;
13541 inst
.operands
[0].writeback
= 1;
13542 inst
.operands
[0].present
= 1;
13546 do_vfp_nsyn_push (void)
13549 if (inst
.operands
[1].issingle
)
13550 do_vfp_nsyn_opcode ("fstmdbs");
13552 do_vfp_nsyn_opcode ("fstmdbd");
13556 do_vfp_nsyn_pop (void)
13559 if (inst
.operands
[1].issingle
)
13560 do_vfp_nsyn_opcode ("fldmias");
13562 do_vfp_nsyn_opcode ("fldmiad");
13565 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13566 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13569 neon_dp_fixup (struct arm_it
* insn
)
13571 unsigned int i
= insn
->instruction
;
13576 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13587 insn
->instruction
= i
;
13590 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13594 neon_logbits (unsigned x
)
13596 return ffs (x
) - 4;
13599 #define LOW4(R) ((R) & 0xf)
13600 #define HI1(R) (((R) >> 4) & 1)
13602 /* Encode insns with bit pattern:
13604 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13605 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13607 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13608 different meaning for some instruction. */
13611 neon_three_same (int isquad
, int ubit
, int size
)
13613 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13614 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13615 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13616 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13617 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13618 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13619 inst
.instruction
|= (isquad
!= 0) << 6;
13620 inst
.instruction
|= (ubit
!= 0) << 24;
13622 inst
.instruction
|= neon_logbits (size
) << 20;
13624 neon_dp_fixup (&inst
);
13627 /* Encode instructions of the form:
13629 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13630 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13632 Don't write size if SIZE == -1. */
13635 neon_two_same (int qbit
, int ubit
, int size
)
13637 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13638 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13639 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13640 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13641 inst
.instruction
|= (qbit
!= 0) << 6;
13642 inst
.instruction
|= (ubit
!= 0) << 24;
13645 inst
.instruction
|= neon_logbits (size
) << 18;
13647 neon_dp_fixup (&inst
);
13650 /* Neon instruction encoders, in approximate order of appearance. */
13653 do_neon_dyadic_i_su (void)
13655 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13656 struct neon_type_el et
= neon_check_type (3, rs
,
13657 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13658 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13662 do_neon_dyadic_i64_su (void)
13664 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13665 struct neon_type_el et
= neon_check_type (3, rs
,
13666 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13667 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13671 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13674 unsigned size
= et
.size
>> 3;
13675 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13676 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13677 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13678 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13679 inst
.instruction
|= (isquad
!= 0) << 6;
13680 inst
.instruction
|= immbits
<< 16;
13681 inst
.instruction
|= (size
>> 3) << 7;
13682 inst
.instruction
|= (size
& 0x7) << 19;
13684 inst
.instruction
|= (uval
!= 0) << 24;
13686 neon_dp_fixup (&inst
);
13690 do_neon_shl_imm (void)
13692 if (!inst
.operands
[2].isreg
)
13694 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13695 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13696 NEON_ENCODE (IMMED
, inst
);
13697 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13701 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13702 struct neon_type_el et
= neon_check_type (3, rs
,
13703 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13706 /* VSHL/VQSHL 3-register variants have syntax such as:
13708 whereas other 3-register operations encoded by neon_three_same have
13711 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13713 tmp
= inst
.operands
[2].reg
;
13714 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13715 inst
.operands
[1].reg
= tmp
;
13716 NEON_ENCODE (INTEGER
, inst
);
13717 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13722 do_neon_qshl_imm (void)
13724 if (!inst
.operands
[2].isreg
)
13726 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13727 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13729 NEON_ENCODE (IMMED
, inst
);
13730 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13731 inst
.operands
[2].imm
);
13735 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13736 struct neon_type_el et
= neon_check_type (3, rs
,
13737 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13740 /* See note in do_neon_shl_imm. */
13741 tmp
= inst
.operands
[2].reg
;
13742 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13743 inst
.operands
[1].reg
= tmp
;
13744 NEON_ENCODE (INTEGER
, inst
);
13745 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13750 do_neon_rshl (void)
13752 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13753 struct neon_type_el et
= neon_check_type (3, rs
,
13754 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13757 tmp
= inst
.operands
[2].reg
;
13758 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13759 inst
.operands
[1].reg
= tmp
;
13760 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13764 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13766 /* Handle .I8 pseudo-instructions. */
13769 /* Unfortunately, this will make everything apart from zero out-of-range.
13770 FIXME is this the intended semantics? There doesn't seem much point in
13771 accepting .I8 if so. */
13772 immediate
|= immediate
<< 8;
13778 if (immediate
== (immediate
& 0x000000ff))
13780 *immbits
= immediate
;
13783 else if (immediate
== (immediate
& 0x0000ff00))
13785 *immbits
= immediate
>> 8;
13788 else if (immediate
== (immediate
& 0x00ff0000))
13790 *immbits
= immediate
>> 16;
13793 else if (immediate
== (immediate
& 0xff000000))
13795 *immbits
= immediate
>> 24;
13798 if ((immediate
& 0xffff) != (immediate
>> 16))
13799 goto bad_immediate
;
13800 immediate
&= 0xffff;
13803 if (immediate
== (immediate
& 0x000000ff))
13805 *immbits
= immediate
;
13808 else if (immediate
== (immediate
& 0x0000ff00))
13810 *immbits
= immediate
>> 8;
13815 first_error (_("immediate value out of range"));
13819 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13823 neon_bits_same_in_bytes (unsigned imm
)
13825 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13826 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13827 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13828 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13831 /* For immediate of above form, return 0bABCD. */
13834 neon_squash_bits (unsigned imm
)
13836 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13837 | ((imm
& 0x01000000) >> 21);
13840 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13843 neon_qfloat_bits (unsigned imm
)
13845 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13848 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13849 the instruction. *OP is passed as the initial value of the op field, and
13850 may be set to a different value depending on the constant (i.e.
13851 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13852 MVN). If the immediate looks like a repeated pattern then also
13853 try smaller element sizes. */
13856 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13857 unsigned *immbits
, int *op
, int size
,
13858 enum neon_el_type type
)
13860 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13862 if (type
== NT_float
&& !float_p
)
13865 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13867 if (size
!= 32 || *op
== 1)
13869 *immbits
= neon_qfloat_bits (immlo
);
13875 if (neon_bits_same_in_bytes (immhi
)
13876 && neon_bits_same_in_bytes (immlo
))
13880 *immbits
= (neon_squash_bits (immhi
) << 4)
13881 | neon_squash_bits (immlo
);
13886 if (immhi
!= immlo
)
13892 if (immlo
== (immlo
& 0x000000ff))
13897 else if (immlo
== (immlo
& 0x0000ff00))
13899 *immbits
= immlo
>> 8;
13902 else if (immlo
== (immlo
& 0x00ff0000))
13904 *immbits
= immlo
>> 16;
13907 else if (immlo
== (immlo
& 0xff000000))
13909 *immbits
= immlo
>> 24;
13912 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13914 *immbits
= (immlo
>> 8) & 0xff;
13917 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13919 *immbits
= (immlo
>> 16) & 0xff;
13923 if ((immlo
& 0xffff) != (immlo
>> 16))
13930 if (immlo
== (immlo
& 0x000000ff))
13935 else if (immlo
== (immlo
& 0x0000ff00))
13937 *immbits
= immlo
>> 8;
13941 if ((immlo
& 0xff) != (immlo
>> 8))
13946 if (immlo
== (immlo
& 0x000000ff))
13948 /* Don't allow MVN with 8-bit immediate. */
13958 /* Write immediate bits [7:0] to the following locations:
13960 |28/24|23 19|18 16|15 4|3 0|
13961 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13963 This function is used by VMOV/VMVN/VORR/VBIC. */
13966 neon_write_immbits (unsigned immbits
)
13968 inst
.instruction
|= immbits
& 0xf;
13969 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13970 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13973 /* Invert low-order SIZE bits of XHI:XLO. */
13976 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13978 unsigned immlo
= xlo
? *xlo
: 0;
13979 unsigned immhi
= xhi
? *xhi
: 0;
13984 immlo
= (~immlo
) & 0xff;
13988 immlo
= (~immlo
) & 0xffff;
13992 immhi
= (~immhi
) & 0xffffffff;
13993 /* fall through. */
13996 immlo
= (~immlo
) & 0xffffffff;
14011 do_neon_logic (void)
14013 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14015 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14016 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14017 /* U bit and size field were set as part of the bitmask. */
14018 NEON_ENCODE (INTEGER
, inst
);
14019 neon_three_same (neon_quad (rs
), 0, -1);
14023 const int three_ops_form
= (inst
.operands
[2].present
14024 && !inst
.operands
[2].isreg
);
14025 const int immoperand
= (three_ops_form
? 2 : 1);
14026 enum neon_shape rs
= (three_ops_form
14027 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14028 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14029 struct neon_type_el et
= neon_check_type (2, rs
,
14030 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14031 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14035 if (et
.type
== NT_invtype
)
14038 if (three_ops_form
)
14039 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14040 _("first and second operands shall be the same register"));
14042 NEON_ENCODE (IMMED
, inst
);
14044 immbits
= inst
.operands
[immoperand
].imm
;
14047 /* .i64 is a pseudo-op, so the immediate must be a repeating
14049 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14050 inst
.operands
[immoperand
].reg
: 0))
14052 /* Set immbits to an invalid constant. */
14053 immbits
= 0xdeadbeef;
14060 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14064 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14068 /* Pseudo-instruction for VBIC. */
14069 neon_invert_size (&immbits
, 0, et
.size
);
14070 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14074 /* Pseudo-instruction for VORR. */
14075 neon_invert_size (&immbits
, 0, et
.size
);
14076 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14086 inst
.instruction
|= neon_quad (rs
) << 6;
14087 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14088 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14089 inst
.instruction
|= cmode
<< 8;
14090 neon_write_immbits (immbits
);
14092 neon_dp_fixup (&inst
);
14097 do_neon_bitfield (void)
14099 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14100 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14101 neon_three_same (neon_quad (rs
), 0, -1);
14105 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14108 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14109 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14111 if (et
.type
== NT_float
)
14113 NEON_ENCODE (FLOAT
, inst
);
14114 neon_three_same (neon_quad (rs
), 0, -1);
14118 NEON_ENCODE (INTEGER
, inst
);
14119 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14124 do_neon_dyadic_if_su (void)
14126 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14130 do_neon_dyadic_if_su_d (void)
14132 /* This version only allow D registers, but that constraint is enforced during
14133 operand parsing so we don't need to do anything extra here. */
14134 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14138 do_neon_dyadic_if_i_d (void)
14140 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14141 affected if we specify unsigned args. */
14142 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14145 enum vfp_or_neon_is_neon_bits
14148 NEON_CHECK_ARCH
= 2,
14149 NEON_CHECK_ARCH8
= 4
14152 /* Call this function if an instruction which may have belonged to the VFP or
14153 Neon instruction sets, but turned out to be a Neon instruction (due to the
14154 operand types involved, etc.). We have to check and/or fix-up a couple of
14157 - Make sure the user hasn't attempted to make a Neon instruction
14159 - Alter the value in the condition code field if necessary.
14160 - Make sure that the arch supports Neon instructions.
14162 Which of these operations take place depends on bits from enum
14163 vfp_or_neon_is_neon_bits.
14165 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14166 current instruction's condition is COND_ALWAYS, the condition field is
14167 changed to inst.uncond_value. This is necessary because instructions shared
14168 between VFP and Neon may be conditional for the VFP variants only, and the
14169 unconditional Neon version must have, e.g., 0xF in the condition field. */
14172 vfp_or_neon_is_neon (unsigned check
)
14174 /* Conditions are always legal in Thumb mode (IT blocks). */
14175 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14177 if (inst
.cond
!= COND_ALWAYS
)
14179 first_error (_(BAD_COND
));
14182 if (inst
.uncond_value
!= -1)
14183 inst
.instruction
|= inst
.uncond_value
<< 28;
14186 if ((check
& NEON_CHECK_ARCH
)
14187 && !mark_feature_used (&fpu_neon_ext_v1
))
14189 first_error (_(BAD_FPU
));
14193 if ((check
& NEON_CHECK_ARCH8
)
14194 && !mark_feature_used (&fpu_neon_ext_armv8
))
14196 first_error (_(BAD_FPU
));
14204 do_neon_addsub_if_i (void)
14206 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14209 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14212 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14213 affected if we specify unsigned args. */
14214 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14217 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14219 V<op> A,B (A is operand 0, B is operand 2)
14224 so handle that case specially. */
14227 neon_exchange_operands (void)
14229 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14230 if (inst
.operands
[1].present
)
14232 /* Swap operands[1] and operands[2]. */
14233 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14234 inst
.operands
[1] = inst
.operands
[2];
14235 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14239 inst
.operands
[1] = inst
.operands
[2];
14240 inst
.operands
[2] = inst
.operands
[0];
14245 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14247 if (inst
.operands
[2].isreg
)
14250 neon_exchange_operands ();
14251 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14255 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14256 struct neon_type_el et
= neon_check_type (2, rs
,
14257 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14259 NEON_ENCODE (IMMED
, inst
);
14260 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14261 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14262 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14263 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14264 inst
.instruction
|= neon_quad (rs
) << 6;
14265 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14266 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14268 neon_dp_fixup (&inst
);
14275 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14279 do_neon_cmp_inv (void)
14281 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14287 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14290 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14291 scalars, which are encoded in 5 bits, M : Rm.
14292 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14293 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14297 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14299 unsigned regno
= NEON_SCALAR_REG (scalar
);
14300 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14305 if (regno
> 7 || elno
> 3)
14307 return regno
| (elno
<< 3);
14310 if (regno
> 15 || elno
> 1)
14312 return regno
| (elno
<< 4);
14316 first_error (_("scalar out of range for multiply instruction"));
14322 /* Encode multiply / multiply-accumulate scalar instructions. */
14325 neon_mul_mac (struct neon_type_el et
, int ubit
)
14329 /* Give a more helpful error message if we have an invalid type. */
14330 if (et
.type
== NT_invtype
)
14333 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14334 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14335 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14336 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14337 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14338 inst
.instruction
|= LOW4 (scalar
);
14339 inst
.instruction
|= HI1 (scalar
) << 5;
14340 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14341 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14342 inst
.instruction
|= (ubit
!= 0) << 24;
14344 neon_dp_fixup (&inst
);
14348 do_neon_mac_maybe_scalar (void)
14350 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14353 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14356 if (inst
.operands
[2].isscalar
)
14358 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14359 struct neon_type_el et
= neon_check_type (3, rs
,
14360 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14361 NEON_ENCODE (SCALAR
, inst
);
14362 neon_mul_mac (et
, neon_quad (rs
));
14366 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14367 affected if we specify unsigned args. */
14368 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14373 do_neon_fmac (void)
14375 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14378 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14381 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14387 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14388 struct neon_type_el et
= neon_check_type (3, rs
,
14389 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14390 neon_three_same (neon_quad (rs
), 0, et
.size
);
14393 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14394 same types as the MAC equivalents. The polynomial type for this instruction
14395 is encoded the same as the integer type. */
14400 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14403 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14406 if (inst
.operands
[2].isscalar
)
14407 do_neon_mac_maybe_scalar ();
14409 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14413 do_neon_qdmulh (void)
14415 if (inst
.operands
[2].isscalar
)
14417 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14418 struct neon_type_el et
= neon_check_type (3, rs
,
14419 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14420 NEON_ENCODE (SCALAR
, inst
);
14421 neon_mul_mac (et
, neon_quad (rs
));
14425 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14426 struct neon_type_el et
= neon_check_type (3, rs
,
14427 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14428 NEON_ENCODE (INTEGER
, inst
);
14429 /* The U bit (rounding) comes from bit mask. */
14430 neon_three_same (neon_quad (rs
), 0, et
.size
);
14435 do_neon_fcmp_absolute (void)
14437 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14438 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14439 /* Size field comes from bit mask. */
14440 neon_three_same (neon_quad (rs
), 1, -1);
14444 do_neon_fcmp_absolute_inv (void)
14446 neon_exchange_operands ();
14447 do_neon_fcmp_absolute ();
14451 do_neon_step (void)
14453 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14454 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14455 neon_three_same (neon_quad (rs
), 0, -1);
14459 do_neon_abs_neg (void)
14461 enum neon_shape rs
;
14462 struct neon_type_el et
;
14464 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14467 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14470 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14471 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14473 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14474 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14475 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14476 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14477 inst
.instruction
|= neon_quad (rs
) << 6;
14478 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14479 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14481 neon_dp_fixup (&inst
);
14487 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14488 struct neon_type_el et
= neon_check_type (2, rs
,
14489 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14490 int imm
= inst
.operands
[2].imm
;
14491 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14492 _("immediate out of range for insert"));
14493 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14499 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14500 struct neon_type_el et
= neon_check_type (2, rs
,
14501 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14502 int imm
= inst
.operands
[2].imm
;
14503 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14504 _("immediate out of range for insert"));
14505 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14509 do_neon_qshlu_imm (void)
14511 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14512 struct neon_type_el et
= neon_check_type (2, rs
,
14513 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14514 int imm
= inst
.operands
[2].imm
;
14515 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14516 _("immediate out of range for shift"));
14517 /* Only encodes the 'U present' variant of the instruction.
14518 In this case, signed types have OP (bit 8) set to 0.
14519 Unsigned types have OP set to 1. */
14520 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14521 /* The rest of the bits are the same as other immediate shifts. */
14522 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14526 do_neon_qmovn (void)
14528 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14529 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14530 /* Saturating move where operands can be signed or unsigned, and the
14531 destination has the same signedness. */
14532 NEON_ENCODE (INTEGER
, inst
);
14533 if (et
.type
== NT_unsigned
)
14534 inst
.instruction
|= 0xc0;
14536 inst
.instruction
|= 0x80;
14537 neon_two_same (0, 1, et
.size
/ 2);
14541 do_neon_qmovun (void)
14543 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14544 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14545 /* Saturating move with unsigned results. Operands must be signed. */
14546 NEON_ENCODE (INTEGER
, inst
);
14547 neon_two_same (0, 1, et
.size
/ 2);
14551 do_neon_rshift_sat_narrow (void)
14553 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14554 or unsigned. If operands are unsigned, results must also be unsigned. */
14555 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14556 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14557 int imm
= inst
.operands
[2].imm
;
14558 /* This gets the bounds check, size encoding and immediate bits calculation
14562 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14563 VQMOVN.I<size> <Dd>, <Qm>. */
14566 inst
.operands
[2].present
= 0;
14567 inst
.instruction
= N_MNEM_vqmovn
;
14572 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14573 _("immediate out of range"));
14574 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14578 do_neon_rshift_sat_narrow_u (void)
14580 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14581 or unsigned. If operands are unsigned, results must also be unsigned. */
14582 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14583 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14584 int imm
= inst
.operands
[2].imm
;
14585 /* This gets the bounds check, size encoding and immediate bits calculation
14589 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14590 VQMOVUN.I<size> <Dd>, <Qm>. */
14593 inst
.operands
[2].present
= 0;
14594 inst
.instruction
= N_MNEM_vqmovun
;
14599 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14600 _("immediate out of range"));
14601 /* FIXME: The manual is kind of unclear about what value U should have in
14602 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14604 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14608 do_neon_movn (void)
14610 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14611 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14612 NEON_ENCODE (INTEGER
, inst
);
14613 neon_two_same (0, 1, et
.size
/ 2);
14617 do_neon_rshift_narrow (void)
14619 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14620 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14621 int imm
= inst
.operands
[2].imm
;
14622 /* This gets the bounds check, size encoding and immediate bits calculation
14626 /* If immediate is zero then we are a pseudo-instruction for
14627 VMOVN.I<size> <Dd>, <Qm> */
14630 inst
.operands
[2].present
= 0;
14631 inst
.instruction
= N_MNEM_vmovn
;
14636 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14637 _("immediate out of range for narrowing operation"));
14638 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14642 do_neon_shll (void)
14644 /* FIXME: Type checking when lengthening. */
14645 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14646 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14647 unsigned imm
= inst
.operands
[2].imm
;
14649 if (imm
== et
.size
)
14651 /* Maximum shift variant. */
14652 NEON_ENCODE (INTEGER
, inst
);
14653 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14654 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14655 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14656 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14657 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14659 neon_dp_fixup (&inst
);
14663 /* A more-specific type check for non-max versions. */
14664 et
= neon_check_type (2, NS_QDI
,
14665 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14666 NEON_ENCODE (IMMED
, inst
);
14667 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14671 /* Check the various types for the VCVT instruction, and return which version
14672 the current instruction is. */
14674 #define CVT_FLAVOUR_VAR \
14675 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14676 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14677 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14678 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14679 /* Half-precision conversions. */ \
14680 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14681 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14682 /* VFP instructions. */ \
14683 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14684 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14685 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14686 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14687 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14688 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14689 /* VFP instructions with bitshift. */ \
14690 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14691 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14692 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14693 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14694 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14695 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14696 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14697 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14699 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14700 neon_cvt_flavour_##C,
14702 /* The different types of conversions we can do. */
14703 enum neon_cvt_flavour
14706 neon_cvt_flavour_invalid
,
14707 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
14712 static enum neon_cvt_flavour
14713 get_neon_cvt_flavour (enum neon_shape rs
)
14715 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14716 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14717 if (et.type != NT_invtype) \
14719 inst.error = NULL; \
14720 return (neon_cvt_flavour_##C); \
14723 struct neon_type_el et
;
14724 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14725 || rs
== NS_FF
) ? N_VFP
: 0;
14726 /* The instruction versions which take an immediate take one register
14727 argument, which is extended to the width of the full register. Thus the
14728 "source" and "destination" registers must have the same width. Hack that
14729 here by making the size equal to the key (wider, in this case) operand. */
14730 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14734 return neon_cvt_flavour_invalid
;
14749 /* Neon-syntax VFP conversions. */
14752 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
14754 const char *opname
= 0;
14756 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14758 /* Conversions with immediate bitshift. */
14759 const char *enc
[] =
14761 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14767 if (flavour
< (int) ARRAY_SIZE (enc
))
14769 opname
= enc
[flavour
];
14770 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14771 _("operands 0 and 1 must be the same register"));
14772 inst
.operands
[1] = inst
.operands
[2];
14773 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14778 /* Conversions without bitshift. */
14779 const char *enc
[] =
14781 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14787 if (flavour
< (int) ARRAY_SIZE (enc
))
14788 opname
= enc
[flavour
];
14792 do_vfp_nsyn_opcode (opname
);
14796 do_vfp_nsyn_cvtz (void)
14798 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14799 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
14800 const char *enc
[] =
14802 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14808 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14809 do_vfp_nsyn_opcode (enc
[flavour
]);
14813 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
14814 enum neon_cvt_mode mode
)
14819 set_it_insn_type (OUTSIDE_IT_INSN
);
14823 case neon_cvt_flavour_s32_f64
:
14827 case neon_cvt_flavour_s32_f32
:
14831 case neon_cvt_flavour_u32_f64
:
14835 case neon_cvt_flavour_u32_f32
:
14840 first_error (_("invalid instruction shape"));
14846 case neon_cvt_mode_a
: rm
= 0; break;
14847 case neon_cvt_mode_n
: rm
= 1; break;
14848 case neon_cvt_mode_p
: rm
= 2; break;
14849 case neon_cvt_mode_m
: rm
= 3; break;
14850 default: first_error (_("invalid rounding mode")); return;
14853 NEON_ENCODE (FPV8
, inst
);
14854 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14855 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
14856 inst
.instruction
|= sz
<< 8;
14857 inst
.instruction
|= op
<< 7;
14858 inst
.instruction
|= rm
<< 16;
14859 inst
.instruction
|= 0xf0000000;
14860 inst
.is_neon
= TRUE
;
14864 do_neon_cvt_1 (enum neon_cvt_mode mode
)
14866 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14867 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14868 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
14870 /* PR11109: Handle round-to-zero for VCVT conversions. */
14871 if (mode
== neon_cvt_mode_z
14872 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14873 && (flavour
== neon_cvt_flavour_s32_f32
14874 || flavour
== neon_cvt_flavour_u32_f32
14875 || flavour
== neon_cvt_flavour_s32_f64
14876 || flavour
== neon_cvt_flavour_u32_f64
)
14877 && (rs
== NS_FD
|| rs
== NS_FF
))
14879 do_vfp_nsyn_cvtz ();
14883 /* VFP rather than Neon conversions. */
14884 if (flavour
>= neon_cvt_flavour_first_fp
)
14886 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
14887 do_vfp_nsyn_cvt (rs
, flavour
);
14889 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
14900 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14902 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14905 /* Fixed-point conversion with #0 immediate is encoded as an
14906 integer conversion. */
14907 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14909 immbits
= 32 - inst
.operands
[2].imm
;
14910 NEON_ENCODE (IMMED
, inst
);
14911 if (flavour
!= neon_cvt_flavour_invalid
)
14912 inst
.instruction
|= enctab
[flavour
];
14913 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14914 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14915 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14916 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14917 inst
.instruction
|= neon_quad (rs
) << 6;
14918 inst
.instruction
|= 1 << 21;
14919 inst
.instruction
|= immbits
<< 16;
14921 neon_dp_fixup (&inst
);
14927 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
14929 NEON_ENCODE (FLOAT
, inst
);
14930 set_it_insn_type (OUTSIDE_IT_INSN
);
14932 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
14935 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14936 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14937 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14938 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14939 inst
.instruction
|= neon_quad (rs
) << 6;
14940 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
14941 inst
.instruction
|= mode
<< 8;
14943 inst
.instruction
|= 0xfc000000;
14945 inst
.instruction
|= 0xf0000000;
14951 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14953 NEON_ENCODE (INTEGER
, inst
);
14955 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14958 if (flavour
!= neon_cvt_flavour_invalid
)
14959 inst
.instruction
|= enctab
[flavour
];
14961 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14962 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14963 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14964 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14965 inst
.instruction
|= neon_quad (rs
) << 6;
14966 inst
.instruction
|= 2 << 18;
14968 neon_dp_fixup (&inst
);
14973 /* Half-precision conversions for Advanced SIMD -- neon. */
14978 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14980 as_bad (_("operand size must match register width"));
14985 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14987 as_bad (_("operand size must match register width"));
14992 inst
.instruction
= 0x3b60600;
14994 inst
.instruction
= 0x3b60700;
14996 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14997 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14998 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14999 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15000 neon_dp_fixup (&inst
);
15004 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15005 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15006 do_vfp_nsyn_cvt (rs
, flavour
);
15008 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15013 do_neon_cvtr (void)
15015 do_neon_cvt_1 (neon_cvt_mode_x
);
15021 do_neon_cvt_1 (neon_cvt_mode_z
);
15025 do_neon_cvta (void)
15027 do_neon_cvt_1 (neon_cvt_mode_a
);
15031 do_neon_cvtn (void)
15033 do_neon_cvt_1 (neon_cvt_mode_n
);
15037 do_neon_cvtp (void)
15039 do_neon_cvt_1 (neon_cvt_mode_p
);
15043 do_neon_cvtm (void)
15045 do_neon_cvt_1 (neon_cvt_mode_m
);
15049 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15052 mark_feature_used (&fpu_vfp_ext_armv8
);
15054 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15055 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15056 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15057 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15058 inst
.instruction
|= to
? 0x10000 : 0;
15059 inst
.instruction
|= t
? 0x80 : 0;
15060 inst
.instruction
|= is_double
? 0x100 : 0;
15061 do_vfp_cond_or_thumb ();
15065 do_neon_cvttb_1 (bfd_boolean t
)
15067 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15071 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15074 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15076 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15079 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15081 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15084 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15086 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15089 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15096 do_neon_cvtb (void)
15098 do_neon_cvttb_1 (FALSE
);
15103 do_neon_cvtt (void)
15105 do_neon_cvttb_1 (TRUE
);
15109 neon_move_immediate (void)
15111 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15112 struct neon_type_el et
= neon_check_type (2, rs
,
15113 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15114 unsigned immlo
, immhi
= 0, immbits
;
15115 int op
, cmode
, float_p
;
15117 constraint (et
.type
== NT_invtype
,
15118 _("operand size must be specified for immediate VMOV"));
15120 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15121 op
= (inst
.instruction
& (1 << 5)) != 0;
15123 immlo
= inst
.operands
[1].imm
;
15124 if (inst
.operands
[1].regisimm
)
15125 immhi
= inst
.operands
[1].reg
;
15127 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15128 _("immediate has bits set outside the operand size"));
15130 float_p
= inst
.operands
[1].immisfloat
;
15132 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15133 et
.size
, et
.type
)) == FAIL
)
15135 /* Invert relevant bits only. */
15136 neon_invert_size (&immlo
, &immhi
, et
.size
);
15137 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15138 with one or the other; those cases are caught by
15139 neon_cmode_for_move_imm. */
15141 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15142 &op
, et
.size
, et
.type
)) == FAIL
)
15144 first_error (_("immediate out of range"));
15149 inst
.instruction
&= ~(1 << 5);
15150 inst
.instruction
|= op
<< 5;
15152 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15153 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15154 inst
.instruction
|= neon_quad (rs
) << 6;
15155 inst
.instruction
|= cmode
<< 8;
15157 neon_write_immbits (immbits
);
15163 if (inst
.operands
[1].isreg
)
15165 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15167 NEON_ENCODE (INTEGER
, inst
);
15168 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15169 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15170 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15171 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15172 inst
.instruction
|= neon_quad (rs
) << 6;
15176 NEON_ENCODE (IMMED
, inst
);
15177 neon_move_immediate ();
15180 neon_dp_fixup (&inst
);
15183 /* Encode instructions of form:
15185 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15186 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15189 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15191 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15192 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15193 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15194 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15195 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15196 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15197 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15198 inst
.instruction
|= neon_logbits (size
) << 20;
15200 neon_dp_fixup (&inst
);
15204 do_neon_dyadic_long (void)
15206 /* FIXME: Type checking for lengthening op. */
15207 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15208 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15209 neon_mixed_length (et
, et
.size
);
15213 do_neon_abal (void)
15215 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15216 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15217 neon_mixed_length (et
, et
.size
);
15221 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15223 if (inst
.operands
[2].isscalar
)
15225 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15226 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15227 NEON_ENCODE (SCALAR
, inst
);
15228 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15232 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15233 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15234 NEON_ENCODE (INTEGER
, inst
);
15235 neon_mixed_length (et
, et
.size
);
15240 do_neon_mac_maybe_scalar_long (void)
15242 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15246 do_neon_dyadic_wide (void)
15248 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15249 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15250 neon_mixed_length (et
, et
.size
);
15254 do_neon_dyadic_narrow (void)
15256 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15257 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15258 /* Operand sign is unimportant, and the U bit is part of the opcode,
15259 so force the operand type to integer. */
15260 et
.type
= NT_integer
;
15261 neon_mixed_length (et
, et
.size
/ 2);
15265 do_neon_mul_sat_scalar_long (void)
15267 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15271 do_neon_vmull (void)
15273 if (inst
.operands
[2].isscalar
)
15274 do_neon_mac_maybe_scalar_long ();
15277 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15278 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15280 if (et
.type
== NT_poly
)
15281 NEON_ENCODE (POLY
, inst
);
15283 NEON_ENCODE (INTEGER
, inst
);
15285 /* For polynomial encoding the U bit must be zero, and the size must
15286 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15287 obviously, as 0b10). */
15290 /* Check we're on the correct architecture. */
15291 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15293 _("Instruction form not available on this architecture.");
15298 neon_mixed_length (et
, et
.size
);
15305 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15306 struct neon_type_el et
= neon_check_type (3, rs
,
15307 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15308 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15310 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15311 _("shift out of range"));
15312 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15313 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15314 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15315 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15316 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15317 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15318 inst
.instruction
|= neon_quad (rs
) << 6;
15319 inst
.instruction
|= imm
<< 8;
15321 neon_dp_fixup (&inst
);
15327 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15328 struct neon_type_el et
= neon_check_type (2, rs
,
15329 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15330 unsigned op
= (inst
.instruction
>> 7) & 3;
15331 /* N (width of reversed regions) is encoded as part of the bitmask. We
15332 extract it here to check the elements to be reversed are smaller.
15333 Otherwise we'd get a reserved instruction. */
15334 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15335 gas_assert (elsize
!= 0);
15336 constraint (et
.size
>= elsize
,
15337 _("elements must be smaller than reversal region"));
15338 neon_two_same (neon_quad (rs
), 1, et
.size
);
15344 if (inst
.operands
[1].isscalar
)
15346 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15347 struct neon_type_el et
= neon_check_type (2, rs
,
15348 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15349 unsigned sizebits
= et
.size
>> 3;
15350 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15351 int logsize
= neon_logbits (et
.size
);
15352 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15354 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15357 NEON_ENCODE (SCALAR
, inst
);
15358 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15359 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15360 inst
.instruction
|= LOW4 (dm
);
15361 inst
.instruction
|= HI1 (dm
) << 5;
15362 inst
.instruction
|= neon_quad (rs
) << 6;
15363 inst
.instruction
|= x
<< 17;
15364 inst
.instruction
|= sizebits
<< 16;
15366 neon_dp_fixup (&inst
);
15370 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15371 struct neon_type_el et
= neon_check_type (2, rs
,
15372 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15373 /* Duplicate ARM register to lanes of vector. */
15374 NEON_ENCODE (ARMREG
, inst
);
15377 case 8: inst
.instruction
|= 0x400000; break;
15378 case 16: inst
.instruction
|= 0x000020; break;
15379 case 32: inst
.instruction
|= 0x000000; break;
15382 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15383 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15384 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15385 inst
.instruction
|= neon_quad (rs
) << 21;
15386 /* The encoding for this instruction is identical for the ARM and Thumb
15387 variants, except for the condition field. */
15388 do_vfp_cond_or_thumb ();
15392 /* VMOV has particularly many variations. It can be one of:
15393 0. VMOV<c><q> <Qd>, <Qm>
15394 1. VMOV<c><q> <Dd>, <Dm>
15395 (Register operations, which are VORR with Rm = Rn.)
15396 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15397 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15399 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15400 (ARM register to scalar.)
15401 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15402 (Two ARM registers to vector.)
15403 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15404 (Scalar to ARM register.)
15405 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15406 (Vector to two ARM registers.)
15407 8. VMOV.F32 <Sd>, <Sm>
15408 9. VMOV.F64 <Dd>, <Dm>
15409 (VFP register moves.)
15410 10. VMOV.F32 <Sd>, #imm
15411 11. VMOV.F64 <Dd>, #imm
15412 (VFP float immediate load.)
15413 12. VMOV <Rd>, <Sm>
15414 (VFP single to ARM reg.)
15415 13. VMOV <Sd>, <Rm>
15416 (ARM reg to VFP single.)
15417 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15418 (Two ARM regs to two VFP singles.)
15419 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15420 (Two VFP singles to two ARM regs.)
15422 These cases can be disambiguated using neon_select_shape, except cases 1/9
15423 and 3/11 which depend on the operand type too.
15425 All the encoded bits are hardcoded by this function.
15427 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15428 Cases 5, 7 may be used with VFPv2 and above.
15430 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15431 can specify a type where it doesn't make sense to, and is ignored). */
15436 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15437 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15439 struct neon_type_el et
;
15440 const char *ldconst
= 0;
15444 case NS_DD
: /* case 1/9. */
15445 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15446 /* It is not an error here if no type is given. */
15448 if (et
.type
== NT_float
&& et
.size
== 64)
15450 do_vfp_nsyn_opcode ("fcpyd");
15453 /* fall through. */
15455 case NS_QQ
: /* case 0/1. */
15457 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15459 /* The architecture manual I have doesn't explicitly state which
15460 value the U bit should have for register->register moves, but
15461 the equivalent VORR instruction has U = 0, so do that. */
15462 inst
.instruction
= 0x0200110;
15463 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15464 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15465 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15466 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15467 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15468 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15469 inst
.instruction
|= neon_quad (rs
) << 6;
15471 neon_dp_fixup (&inst
);
15475 case NS_DI
: /* case 3/11. */
15476 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15478 if (et
.type
== NT_float
&& et
.size
== 64)
15480 /* case 11 (fconstd). */
15481 ldconst
= "fconstd";
15482 goto encode_fconstd
;
15484 /* fall through. */
15486 case NS_QI
: /* case 2/3. */
15487 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15489 inst
.instruction
= 0x0800010;
15490 neon_move_immediate ();
15491 neon_dp_fixup (&inst
);
15494 case NS_SR
: /* case 4. */
15496 unsigned bcdebits
= 0;
15498 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15499 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15501 /* .<size> is optional here, defaulting to .32. */
15502 if (inst
.vectype
.elems
== 0
15503 && inst
.operands
[0].vectype
.type
== NT_invtype
15504 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15506 inst
.vectype
.el
[0].type
= NT_untyped
;
15507 inst
.vectype
.el
[0].size
= 32;
15508 inst
.vectype
.elems
= 1;
15511 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15512 logsize
= neon_logbits (et
.size
);
15514 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15516 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15517 && et
.size
!= 32, _(BAD_FPU
));
15518 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15519 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15523 case 8: bcdebits
= 0x8; break;
15524 case 16: bcdebits
= 0x1; break;
15525 case 32: bcdebits
= 0x0; break;
15529 bcdebits
|= x
<< logsize
;
15531 inst
.instruction
= 0xe000b10;
15532 do_vfp_cond_or_thumb ();
15533 inst
.instruction
|= LOW4 (dn
) << 16;
15534 inst
.instruction
|= HI1 (dn
) << 7;
15535 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15536 inst
.instruction
|= (bcdebits
& 3) << 5;
15537 inst
.instruction
|= (bcdebits
>> 2) << 21;
15541 case NS_DRR
: /* case 5 (fmdrr). */
15542 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15545 inst
.instruction
= 0xc400b10;
15546 do_vfp_cond_or_thumb ();
15547 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15548 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15549 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15550 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15553 case NS_RS
: /* case 6. */
15556 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15557 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15558 unsigned abcdebits
= 0;
15560 /* .<dt> is optional here, defaulting to .32. */
15561 if (inst
.vectype
.elems
== 0
15562 && inst
.operands
[0].vectype
.type
== NT_invtype
15563 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15565 inst
.vectype
.el
[0].type
= NT_untyped
;
15566 inst
.vectype
.el
[0].size
= 32;
15567 inst
.vectype
.elems
= 1;
15570 et
= neon_check_type (2, NS_NULL
,
15571 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15572 logsize
= neon_logbits (et
.size
);
15574 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15576 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15577 && et
.size
!= 32, _(BAD_FPU
));
15578 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15579 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15583 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15584 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15585 case 32: abcdebits
= 0x00; break;
15589 abcdebits
|= x
<< logsize
;
15590 inst
.instruction
= 0xe100b10;
15591 do_vfp_cond_or_thumb ();
15592 inst
.instruction
|= LOW4 (dn
) << 16;
15593 inst
.instruction
|= HI1 (dn
) << 7;
15594 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15595 inst
.instruction
|= (abcdebits
& 3) << 5;
15596 inst
.instruction
|= (abcdebits
>> 2) << 21;
15600 case NS_RRD
: /* case 7 (fmrrd). */
15601 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15604 inst
.instruction
= 0xc500b10;
15605 do_vfp_cond_or_thumb ();
15606 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15607 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15608 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15609 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15612 case NS_FF
: /* case 8 (fcpys). */
15613 do_vfp_nsyn_opcode ("fcpys");
15616 case NS_FI
: /* case 10 (fconsts). */
15617 ldconst
= "fconsts";
15619 if (is_quarter_float (inst
.operands
[1].imm
))
15621 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15622 do_vfp_nsyn_opcode (ldconst
);
15625 first_error (_("immediate out of range"));
15628 case NS_RF
: /* case 12 (fmrs). */
15629 do_vfp_nsyn_opcode ("fmrs");
15632 case NS_FR
: /* case 13 (fmsr). */
15633 do_vfp_nsyn_opcode ("fmsr");
15636 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15637 (one of which is a list), but we have parsed four. Do some fiddling to
15638 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15640 case NS_RRFF
: /* case 14 (fmrrs). */
15641 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15642 _("VFP registers must be adjacent"));
15643 inst
.operands
[2].imm
= 2;
15644 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15645 do_vfp_nsyn_opcode ("fmrrs");
15648 case NS_FFRR
: /* case 15 (fmsrr). */
15649 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15650 _("VFP registers must be adjacent"));
15651 inst
.operands
[1] = inst
.operands
[2];
15652 inst
.operands
[2] = inst
.operands
[3];
15653 inst
.operands
[0].imm
= 2;
15654 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15655 do_vfp_nsyn_opcode ("fmsrr");
15659 /* neon_select_shape has determined that the instruction
15660 shape is wrong and has already set the error message. */
15669 do_neon_rshift_round_imm (void)
15671 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15672 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15673 int imm
= inst
.operands
[2].imm
;
15675 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15678 inst
.operands
[2].present
= 0;
15683 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15684 _("immediate out of range for shift"));
15685 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15690 do_neon_movl (void)
15692 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15693 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15694 unsigned sizebits
= et
.size
>> 3;
15695 inst
.instruction
|= sizebits
<< 19;
15696 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15702 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15703 struct neon_type_el et
= neon_check_type (2, rs
,
15704 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15705 NEON_ENCODE (INTEGER
, inst
);
15706 neon_two_same (neon_quad (rs
), 1, et
.size
);
15710 do_neon_zip_uzp (void)
15712 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15713 struct neon_type_el et
= neon_check_type (2, rs
,
15714 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15715 if (rs
== NS_DD
&& et
.size
== 32)
15717 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15718 inst
.instruction
= N_MNEM_vtrn
;
15722 neon_two_same (neon_quad (rs
), 1, et
.size
);
15726 do_neon_sat_abs_neg (void)
15728 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15729 struct neon_type_el et
= neon_check_type (2, rs
,
15730 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15731 neon_two_same (neon_quad (rs
), 1, et
.size
);
15735 do_neon_pair_long (void)
15737 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15738 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15739 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15740 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15741 neon_two_same (neon_quad (rs
), 1, et
.size
);
15745 do_neon_recip_est (void)
15747 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15748 struct neon_type_el et
= neon_check_type (2, rs
,
15749 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15750 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15751 neon_two_same (neon_quad (rs
), 1, et
.size
);
15757 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15758 struct neon_type_el et
= neon_check_type (2, rs
,
15759 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15760 neon_two_same (neon_quad (rs
), 1, et
.size
);
15766 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15767 struct neon_type_el et
= neon_check_type (2, rs
,
15768 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15769 neon_two_same (neon_quad (rs
), 1, et
.size
);
15775 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15776 struct neon_type_el et
= neon_check_type (2, rs
,
15777 N_EQK
| N_INT
, N_8
| N_KEY
);
15778 neon_two_same (neon_quad (rs
), 1, et
.size
);
15784 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15785 neon_two_same (neon_quad (rs
), 1, -1);
15789 do_neon_tbl_tbx (void)
15791 unsigned listlenbits
;
15792 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15794 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15796 first_error (_("bad list length for table lookup"));
15800 listlenbits
= inst
.operands
[1].imm
- 1;
15801 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15802 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15803 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15804 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15805 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15806 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15807 inst
.instruction
|= listlenbits
<< 8;
15809 neon_dp_fixup (&inst
);
15813 do_neon_ldm_stm (void)
15815 /* P, U and L bits are part of bitmask. */
15816 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15817 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15819 if (inst
.operands
[1].issingle
)
15821 do_vfp_nsyn_ldm_stm (is_dbmode
);
15825 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15826 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15828 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15829 _("register list must contain at least 1 and at most 16 "
15832 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15833 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15834 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15835 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15837 inst
.instruction
|= offsetbits
;
15839 do_vfp_cond_or_thumb ();
15843 do_neon_ldr_str (void)
15845 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15847 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15848 And is UNPREDICTABLE in thumb mode. */
15850 && inst
.operands
[1].reg
== REG_PC
15851 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
15854 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15855 else if (warn_on_deprecated
)
15856 as_warn (_("Use of PC here is deprecated"));
15859 if (inst
.operands
[0].issingle
)
15862 do_vfp_nsyn_opcode ("flds");
15864 do_vfp_nsyn_opcode ("fsts");
15869 do_vfp_nsyn_opcode ("fldd");
15871 do_vfp_nsyn_opcode ("fstd");
15875 /* "interleave" version also handles non-interleaving register VLD1/VST1
15879 do_neon_ld_st_interleave (void)
15881 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15882 N_8
| N_16
| N_32
| N_64
);
15883 unsigned alignbits
= 0;
15885 /* The bits in this table go:
15886 0: register stride of one (0) or two (1)
15887 1,2: register list length, minus one (1, 2, 3, 4).
15888 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15889 We use -1 for invalid entries. */
15890 const int typetable
[] =
15892 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15893 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15894 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15895 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15899 if (et
.type
== NT_invtype
)
15902 if (inst
.operands
[1].immisalign
)
15903 switch (inst
.operands
[1].imm
>> 8)
15905 case 64: alignbits
= 1; break;
15907 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15908 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15909 goto bad_alignment
;
15913 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15914 goto bad_alignment
;
15919 first_error (_("bad alignment"));
15923 inst
.instruction
|= alignbits
<< 4;
15924 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15926 /* Bits [4:6] of the immediate in a list specifier encode register stride
15927 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15928 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15929 up the right value for "type" in a table based on this value and the given
15930 list style, then stick it back. */
15931 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15932 | (((inst
.instruction
>> 8) & 3) << 3);
15934 typebits
= typetable
[idx
];
15936 constraint (typebits
== -1, _("bad list type for instruction"));
15937 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
15938 _("bad element type for instruction"));
15940 inst
.instruction
&= ~0xf00;
15941 inst
.instruction
|= typebits
<< 8;
15944 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15945 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15946 otherwise. The variable arguments are a list of pairs of legal (size, align)
15947 values, terminated with -1. */
15950 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15953 int result
= FAIL
, thissize
, thisalign
;
15955 if (!inst
.operands
[1].immisalign
)
15961 va_start (ap
, do_align
);
15965 thissize
= va_arg (ap
, int);
15966 if (thissize
== -1)
15968 thisalign
= va_arg (ap
, int);
15970 if (size
== thissize
&& align
== thisalign
)
15973 while (result
!= SUCCESS
);
15977 if (result
== SUCCESS
)
15980 first_error (_("unsupported alignment for instruction"));
15986 do_neon_ld_st_lane (void)
15988 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15989 int align_good
, do_align
= 0;
15990 int logsize
= neon_logbits (et
.size
);
15991 int align
= inst
.operands
[1].imm
>> 8;
15992 int n
= (inst
.instruction
>> 8) & 3;
15993 int max_el
= 64 / et
.size
;
15995 if (et
.type
== NT_invtype
)
15998 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15999 _("bad list length"));
16000 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16001 _("scalar index out of range"));
16002 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16004 _("stride of 2 unavailable when element size is 8"));
16008 case 0: /* VLD1 / VST1. */
16009 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16011 if (align_good
== FAIL
)
16015 unsigned alignbits
= 0;
16018 case 16: alignbits
= 0x1; break;
16019 case 32: alignbits
= 0x3; break;
16022 inst
.instruction
|= alignbits
<< 4;
16026 case 1: /* VLD2 / VST2. */
16027 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16029 if (align_good
== FAIL
)
16032 inst
.instruction
|= 1 << 4;
16035 case 2: /* VLD3 / VST3. */
16036 constraint (inst
.operands
[1].immisalign
,
16037 _("can't use alignment with this instruction"));
16040 case 3: /* VLD4 / VST4. */
16041 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16042 16, 64, 32, 64, 32, 128, -1);
16043 if (align_good
== FAIL
)
16047 unsigned alignbits
= 0;
16050 case 8: alignbits
= 0x1; break;
16051 case 16: alignbits
= 0x1; break;
16052 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16055 inst
.instruction
|= alignbits
<< 4;
16062 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16063 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16064 inst
.instruction
|= 1 << (4 + logsize
);
16066 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16067 inst
.instruction
|= logsize
<< 10;
16070 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16073 do_neon_ld_dup (void)
16075 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16076 int align_good
, do_align
= 0;
16078 if (et
.type
== NT_invtype
)
16081 switch ((inst
.instruction
>> 8) & 3)
16083 case 0: /* VLD1. */
16084 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16085 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16086 &do_align
, 16, 16, 32, 32, -1);
16087 if (align_good
== FAIL
)
16089 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16092 case 2: inst
.instruction
|= 1 << 5; break;
16093 default: first_error (_("bad list length")); return;
16095 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16098 case 1: /* VLD2. */
16099 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16100 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16101 if (align_good
== FAIL
)
16103 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16104 _("bad list length"));
16105 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16106 inst
.instruction
|= 1 << 5;
16107 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16110 case 2: /* VLD3. */
16111 constraint (inst
.operands
[1].immisalign
,
16112 _("can't use alignment with this instruction"));
16113 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16114 _("bad list length"));
16115 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16116 inst
.instruction
|= 1 << 5;
16117 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16120 case 3: /* VLD4. */
16122 int align
= inst
.operands
[1].imm
>> 8;
16123 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16124 16, 64, 32, 64, 32, 128, -1);
16125 if (align_good
== FAIL
)
16127 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16128 _("bad list length"));
16129 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16130 inst
.instruction
|= 1 << 5;
16131 if (et
.size
== 32 && align
== 128)
16132 inst
.instruction
|= 0x3 << 6;
16134 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16141 inst
.instruction
|= do_align
<< 4;
16144 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16145 apart from bits [11:4]. */
16148 do_neon_ldx_stx (void)
16150 if (inst
.operands
[1].isreg
)
16151 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16153 switch (NEON_LANE (inst
.operands
[0].imm
))
16155 case NEON_INTERLEAVE_LANES
:
16156 NEON_ENCODE (INTERLV
, inst
);
16157 do_neon_ld_st_interleave ();
16160 case NEON_ALL_LANES
:
16161 NEON_ENCODE (DUP
, inst
);
16162 if (inst
.instruction
== N_INV
)
16164 first_error ("only loads support such operands");
16171 NEON_ENCODE (LANE
, inst
);
16172 do_neon_ld_st_lane ();
16175 /* L bit comes from bit mask. */
16176 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16177 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16178 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16180 if (inst
.operands
[1].postind
)
16182 int postreg
= inst
.operands
[1].imm
& 0xf;
16183 constraint (!inst
.operands
[1].immisreg
,
16184 _("post-index must be a register"));
16185 constraint (postreg
== 0xd || postreg
== 0xf,
16186 _("bad register for post-index"));
16187 inst
.instruction
|= postreg
;
16191 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16192 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16193 || inst
.reloc
.exp
.X_add_number
!= 0,
16196 if (inst
.operands
[1].writeback
)
16198 inst
.instruction
|= 0xd;
16201 inst
.instruction
|= 0xf;
16205 inst
.instruction
|= 0xf9000000;
16207 inst
.instruction
|= 0xf4000000;
16212 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16214 NEON_ENCODE (FPV8
, inst
);
16217 do_vfp_sp_dyadic ();
16219 do_vfp_dp_rd_rn_rm ();
16222 inst
.instruction
|= 0x100;
16224 inst
.instruction
|= 0xf0000000;
16230 set_it_insn_type (OUTSIDE_IT_INSN
);
16232 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16233 first_error (_("invalid instruction shape"));
16239 set_it_insn_type (OUTSIDE_IT_INSN
);
16241 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16244 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16247 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16251 do_vrint_1 (enum neon_cvt_mode mode
)
16253 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16254 struct neon_type_el et
;
16259 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16260 if (et
.type
!= NT_invtype
)
16262 /* VFP encodings. */
16263 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16264 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16265 set_it_insn_type (OUTSIDE_IT_INSN
);
16267 NEON_ENCODE (FPV8
, inst
);
16269 do_vfp_sp_monadic ();
16271 do_vfp_dp_rd_rm ();
16275 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16276 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16277 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16278 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16279 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16280 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16281 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16285 inst
.instruction
|= (rs
== NS_DD
) << 8;
16286 do_vfp_cond_or_thumb ();
16290 /* Neon encodings (or something broken...). */
16292 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16294 if (et
.type
== NT_invtype
)
16297 set_it_insn_type (OUTSIDE_IT_INSN
);
16298 NEON_ENCODE (FLOAT
, inst
);
16300 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16303 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16304 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16305 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16306 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16307 inst
.instruction
|= neon_quad (rs
) << 6;
16310 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16311 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16312 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16313 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16314 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16315 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16316 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16321 inst
.instruction
|= 0xfc000000;
16323 inst
.instruction
|= 0xf0000000;
16330 do_vrint_1 (neon_cvt_mode_x
);
16336 do_vrint_1 (neon_cvt_mode_z
);
16342 do_vrint_1 (neon_cvt_mode_r
);
16348 do_vrint_1 (neon_cvt_mode_a
);
16354 do_vrint_1 (neon_cvt_mode_n
);
16360 do_vrint_1 (neon_cvt_mode_p
);
16366 do_vrint_1 (neon_cvt_mode_m
);
16369 /* Crypto v1 instructions. */
16371 do_crypto_2op_1 (unsigned elttype
, int op
)
16373 set_it_insn_type (OUTSIDE_IT_INSN
);
16375 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16381 NEON_ENCODE (INTEGER
, inst
);
16382 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16383 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16384 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16385 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16387 inst
.instruction
|= op
<< 6;
16390 inst
.instruction
|= 0xfc000000;
16392 inst
.instruction
|= 0xf0000000;
16396 do_crypto_3op_1 (int u
, int op
)
16398 set_it_insn_type (OUTSIDE_IT_INSN
);
16400 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16401 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16406 NEON_ENCODE (INTEGER
, inst
);
16407 neon_three_same (1, u
, 8 << op
);
16413 do_crypto_2op_1 (N_8
, 0);
16419 do_crypto_2op_1 (N_8
, 1);
16425 do_crypto_2op_1 (N_8
, 2);
16431 do_crypto_2op_1 (N_8
, 3);
16437 do_crypto_3op_1 (0, 0);
16443 do_crypto_3op_1 (0, 1);
16449 do_crypto_3op_1 (0, 2);
16455 do_crypto_3op_1 (0, 3);
16461 do_crypto_3op_1 (1, 0);
16467 do_crypto_3op_1 (1, 1);
16471 do_sha256su1 (void)
16473 do_crypto_3op_1 (1, 2);
16479 do_crypto_2op_1 (N_32
, -1);
16485 do_crypto_2op_1 (N_32
, 0);
16489 do_sha256su0 (void)
16491 do_crypto_2op_1 (N_32
, 1);
16495 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16497 unsigned int Rd
= inst
.operands
[0].reg
;
16498 unsigned int Rn
= inst
.operands
[1].reg
;
16499 unsigned int Rm
= inst
.operands
[2].reg
;
16501 set_it_insn_type (OUTSIDE_IT_INSN
);
16502 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16503 inst
.instruction
|= LOW4 (Rn
) << 16;
16504 inst
.instruction
|= LOW4 (Rm
);
16505 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16506 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16508 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16509 as_warn (UNPRED_REG ("r15"));
16510 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16511 as_warn (UNPRED_REG ("r13"));
16551 /* Overall per-instruction processing. */
16553 /* We need to be able to fix up arbitrary expressions in some statements.
16554 This is so that we can handle symbols that are an arbitrary distance from
16555 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16556 which returns part of an address in a form which will be valid for
16557 a data instruction. We do this by pushing the expression into a symbol
16558 in the expr_section, and creating a fix for that. */
16561 fix_new_arm (fragS
* frag
,
16575 /* Create an absolute valued symbol, so we have something to
16576 refer to in the object file. Unfortunately for us, gas's
16577 generic expression parsing will already have folded out
16578 any use of .set foo/.type foo %function that may have
16579 been used to set type information of the target location,
16580 that's being specified symbolically. We have to presume
16581 the user knows what they are doing. */
16585 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
16587 symbol
= symbol_find_or_make (name
);
16588 S_SET_SEGMENT (symbol
, absolute_section
);
16589 symbol_set_frag (symbol
, &zero_address_frag
);
16590 S_SET_VALUE (symbol
, exp
->X_add_number
);
16591 exp
->X_op
= O_symbol
;
16592 exp
->X_add_symbol
= symbol
;
16593 exp
->X_add_number
= 0;
16599 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
16600 (enum bfd_reloc_code_real
) reloc
);
16604 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
16605 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
16609 /* Mark whether the fix is to a THUMB instruction, or an ARM
16611 new_fix
->tc_fix_data
= thumb_mode
;
16614 /* Create a frg for an instruction requiring relaxation. */
16616 output_relax_insn (void)
16622 /* The size of the instruction is unknown, so tie the debug info to the
16623 start of the instruction. */
16624 dwarf2_emit_insn (0);
16626 switch (inst
.reloc
.exp
.X_op
)
16629 sym
= inst
.reloc
.exp
.X_add_symbol
;
16630 offset
= inst
.reloc
.exp
.X_add_number
;
16634 offset
= inst
.reloc
.exp
.X_add_number
;
16637 sym
= make_expr_symbol (&inst
.reloc
.exp
);
16641 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
16642 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
16643 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
16646 /* Write a 32-bit thumb instruction to buf. */
16648 put_thumb32_insn (char * buf
, unsigned long insn
)
16650 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
16651 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
16655 output_inst (const char * str
)
16661 as_bad ("%s -- `%s'", inst
.error
, str
);
16666 output_relax_insn ();
16669 if (inst
.size
== 0)
16672 to
= frag_more (inst
.size
);
16673 /* PR 9814: Record the thumb mode into the current frag so that we know
16674 what type of NOP padding to use, if necessary. We override any previous
16675 setting so that if the mode has changed then the NOPS that we use will
16676 match the encoding of the last instruction in the frag. */
16677 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
16679 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
16681 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
16682 put_thumb32_insn (to
, inst
.instruction
);
16684 else if (inst
.size
> INSN_SIZE
)
16686 gas_assert (inst
.size
== (2 * INSN_SIZE
));
16687 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
16688 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
16691 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
16693 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
16694 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
16695 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
16698 dwarf2_emit_insn (inst
.size
);
16702 output_it_inst (int cond
, int mask
, char * to
)
16704 unsigned long instruction
= 0xbf00;
16707 instruction
|= mask
;
16708 instruction
|= cond
<< 4;
16712 to
= frag_more (2);
16714 dwarf2_emit_insn (2);
16718 md_number_to_chars (to
, instruction
, 2);
16723 /* Tag values used in struct asm_opcode's tag field. */
16726 OT_unconditional
, /* Instruction cannot be conditionalized.
16727 The ARM condition field is still 0xE. */
16728 OT_unconditionalF
, /* Instruction cannot be conditionalized
16729 and carries 0xF in its ARM condition field. */
16730 OT_csuffix
, /* Instruction takes a conditional suffix. */
16731 OT_csuffixF
, /* Some forms of the instruction take a conditional
16732 suffix, others place 0xF where the condition field
16734 OT_cinfix3
, /* Instruction takes a conditional infix,
16735 beginning at character index 3. (In
16736 unified mode, it becomes a suffix.) */
16737 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
16738 tsts, cmps, cmns, and teqs. */
16739 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
16740 character index 3, even in unified mode. Used for
16741 legacy instructions where suffix and infix forms
16742 may be ambiguous. */
16743 OT_csuf_or_in3
, /* Instruction takes either a conditional
16744 suffix or an infix at character index 3. */
16745 OT_odd_infix_unc
, /* This is the unconditional variant of an
16746 instruction that takes a conditional infix
16747 at an unusual position. In unified mode,
16748 this variant will accept a suffix. */
16749 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
16750 are the conditional variants of instructions that
16751 take conditional infixes in unusual positions.
16752 The infix appears at character index
16753 (tag - OT_odd_infix_0). These are not accepted
16754 in unified mode. */
16757 /* Subroutine of md_assemble, responsible for looking up the primary
16758 opcode from the mnemonic the user wrote. STR points to the
16759 beginning of the mnemonic.
16761 This is not simply a hash table lookup, because of conditional
16762 variants. Most instructions have conditional variants, which are
16763 expressed with a _conditional affix_ to the mnemonic. If we were
16764 to encode each conditional variant as a literal string in the opcode
16765 table, it would have approximately 20,000 entries.
16767 Most mnemonics take this affix as a suffix, and in unified syntax,
16768 'most' is upgraded to 'all'. However, in the divided syntax, some
16769 instructions take the affix as an infix, notably the s-variants of
16770 the arithmetic instructions. Of those instructions, all but six
16771 have the infix appear after the third character of the mnemonic.
16773 Accordingly, the algorithm for looking up primary opcodes given
16776 1. Look up the identifier in the opcode table.
16777 If we find a match, go to step U.
16779 2. Look up the last two characters of the identifier in the
16780 conditions table. If we find a match, look up the first N-2
16781 characters of the identifier in the opcode table. If we
16782 find a match, go to step CE.
16784 3. Look up the fourth and fifth characters of the identifier in
16785 the conditions table. If we find a match, extract those
16786 characters from the identifier, and look up the remaining
16787 characters in the opcode table. If we find a match, go
16792 U. Examine the tag field of the opcode structure, in case this is
16793 one of the six instructions with its conditional infix in an
16794 unusual place. If it is, the tag tells us where to find the
16795 infix; look it up in the conditions table and set inst.cond
16796 accordingly. Otherwise, this is an unconditional instruction.
16797 Again set inst.cond accordingly. Return the opcode structure.
16799 CE. Examine the tag field to make sure this is an instruction that
16800 should receive a conditional suffix. If it is not, fail.
16801 Otherwise, set inst.cond from the suffix we already looked up,
16802 and return the opcode structure.
16804 CM. Examine the tag field to make sure this is an instruction that
16805 should receive a conditional infix after the third character.
16806 If it is not, fail. Otherwise, undo the edits to the current
16807 line of input and proceed as for case CE. */
16809 static const struct asm_opcode
*
16810 opcode_lookup (char **str
)
16814 const struct asm_opcode
*opcode
;
16815 const struct asm_cond
*cond
;
16818 /* Scan up to the end of the mnemonic, which must end in white space,
16819 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16820 for (base
= end
= *str
; *end
!= '\0'; end
++)
16821 if (*end
== ' ' || *end
== '.')
16827 /* Handle a possible width suffix and/or Neon type suffix. */
16832 /* The .w and .n suffixes are only valid if the unified syntax is in
16834 if (unified_syntax
&& end
[1] == 'w')
16836 else if (unified_syntax
&& end
[1] == 'n')
16841 inst
.vectype
.elems
= 0;
16843 *str
= end
+ offset
;
16845 if (end
[offset
] == '.')
16847 /* See if we have a Neon type suffix (possible in either unified or
16848 non-unified ARM syntax mode). */
16849 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
16852 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
16858 /* Look for unaffixed or special-case affixed mnemonic. */
16859 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16864 if (opcode
->tag
< OT_odd_infix_0
)
16866 inst
.cond
= COND_ALWAYS
;
16870 if (warn_on_deprecated
&& unified_syntax
)
16871 as_warn (_("conditional infixes are deprecated in unified syntax"));
16872 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
16873 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16876 inst
.cond
= cond
->value
;
16880 /* Cannot have a conditional suffix on a mnemonic of less than two
16882 if (end
- base
< 3)
16885 /* Look for suffixed mnemonic. */
16887 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16888 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16890 if (opcode
&& cond
)
16893 switch (opcode
->tag
)
16895 case OT_cinfix3_legacy
:
16896 /* Ignore conditional suffixes matched on infix only mnemonics. */
16900 case OT_cinfix3_deprecated
:
16901 case OT_odd_infix_unc
:
16902 if (!unified_syntax
)
16904 /* else fall through */
16908 case OT_csuf_or_in3
:
16909 inst
.cond
= cond
->value
;
16912 case OT_unconditional
:
16913 case OT_unconditionalF
:
16915 inst
.cond
= cond
->value
;
16918 /* Delayed diagnostic. */
16919 inst
.error
= BAD_COND
;
16920 inst
.cond
= COND_ALWAYS
;
16929 /* Cannot have a usual-position infix on a mnemonic of less than
16930 six characters (five would be a suffix). */
16931 if (end
- base
< 6)
16934 /* Look for infixed mnemonic in the usual position. */
16936 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16940 memcpy (save
, affix
, 2);
16941 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
16942 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16944 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
16945 memcpy (affix
, save
, 2);
16948 && (opcode
->tag
== OT_cinfix3
16949 || opcode
->tag
== OT_cinfix3_deprecated
16950 || opcode
->tag
== OT_csuf_or_in3
16951 || opcode
->tag
== OT_cinfix3_legacy
))
16954 if (warn_on_deprecated
&& unified_syntax
16955 && (opcode
->tag
== OT_cinfix3
16956 || opcode
->tag
== OT_cinfix3_deprecated
))
16957 as_warn (_("conditional infixes are deprecated in unified syntax"));
16959 inst
.cond
= cond
->value
;
16966 /* This function generates an initial IT instruction, leaving its block
16967 virtually open for the new instructions. Eventually,
16968 the mask will be updated by now_it_add_mask () each time
16969 a new instruction needs to be included in the IT block.
16970 Finally, the block is closed with close_automatic_it_block ().
16971 The block closure can be requested either from md_assemble (),
16972 a tencode (), or due to a label hook. */
16975 new_automatic_it_block (int cond
)
16977 now_it
.state
= AUTOMATIC_IT_BLOCK
;
16978 now_it
.mask
= 0x18;
16980 now_it
.block_length
= 1;
16981 mapping_state (MAP_THUMB
);
16982 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
16983 now_it
.warn_deprecated
= FALSE
;
16984 now_it
.insn_cond
= TRUE
;
16987 /* Close an automatic IT block.
16988 See comments in new_automatic_it_block (). */
16991 close_automatic_it_block (void)
16993 now_it
.mask
= 0x10;
16994 now_it
.block_length
= 0;
16997 /* Update the mask of the current automatically-generated IT
16998 instruction. See comments in new_automatic_it_block (). */
17001 now_it_add_mask (int cond
)
17003 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17004 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17005 | ((bitvalue) << (nbit)))
17006 const int resulting_bit
= (cond
& 1);
17008 now_it
.mask
&= 0xf;
17009 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17011 (5 - now_it
.block_length
));
17012 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17014 ((5 - now_it
.block_length
) - 1) );
17015 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17018 #undef SET_BIT_VALUE
17021 /* The IT blocks handling machinery is accessed through the these functions:
17022 it_fsm_pre_encode () from md_assemble ()
17023 set_it_insn_type () optional, from the tencode functions
17024 set_it_insn_type_last () ditto
17025 in_it_block () ditto
17026 it_fsm_post_encode () from md_assemble ()
17027 force_automatic_it_block_close () from label habdling functions
17030 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17031 initializing the IT insn type with a generic initial value depending
17032 on the inst.condition.
17033 2) During the tencode function, two things may happen:
17034 a) The tencode function overrides the IT insn type by
17035 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17036 b) The tencode function queries the IT block state by
17037 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17039 Both set_it_insn_type and in_it_block run the internal FSM state
17040 handling function (handle_it_state), because: a) setting the IT insn
17041 type may incur in an invalid state (exiting the function),
17042 and b) querying the state requires the FSM to be updated.
17043 Specifically we want to avoid creating an IT block for conditional
17044 branches, so it_fsm_pre_encode is actually a guess and we can't
17045 determine whether an IT block is required until the tencode () routine
17046 has decided what type of instruction this actually it.
17047 Because of this, if set_it_insn_type and in_it_block have to be used,
17048 set_it_insn_type has to be called first.
17050 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17051 determines the insn IT type depending on the inst.cond code.
17052 When a tencode () routine encodes an instruction that can be
17053 either outside an IT block, or, in the case of being inside, has to be
17054 the last one, set_it_insn_type_last () will determine the proper
17055 IT instruction type based on the inst.cond code. Otherwise,
17056 set_it_insn_type can be called for overriding that logic or
17057 for covering other cases.
17059 Calling handle_it_state () may not transition the IT block state to
17060 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17061 still queried. Instead, if the FSM determines that the state should
17062 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17063 after the tencode () function: that's what it_fsm_post_encode () does.
17065 Since in_it_block () calls the state handling function to get an
17066 updated state, an error may occur (due to invalid insns combination).
17067 In that case, inst.error is set.
17068 Therefore, inst.error has to be checked after the execution of
17069 the tencode () routine.
17071 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17072 any pending state change (if any) that didn't take place in
17073 handle_it_state () as explained above. */
17076 it_fsm_pre_encode (void)
17078 if (inst
.cond
!= COND_ALWAYS
)
17079 inst
.it_insn_type
= INSIDE_IT_INSN
;
17081 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17083 now_it
.state_handled
= 0;
17086 /* IT state FSM handling function. */
17089 handle_it_state (void)
17091 now_it
.state_handled
= 1;
17092 now_it
.insn_cond
= FALSE
;
17094 switch (now_it
.state
)
17096 case OUTSIDE_IT_BLOCK
:
17097 switch (inst
.it_insn_type
)
17099 case OUTSIDE_IT_INSN
:
17102 case INSIDE_IT_INSN
:
17103 case INSIDE_IT_LAST_INSN
:
17104 if (thumb_mode
== 0)
17107 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17108 as_tsktsk (_("Warning: conditional outside an IT block"\
17113 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17114 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17116 /* Automatically generate the IT instruction. */
17117 new_automatic_it_block (inst
.cond
);
17118 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17119 close_automatic_it_block ();
17123 inst
.error
= BAD_OUT_IT
;
17129 case IF_INSIDE_IT_LAST_INSN
:
17130 case NEUTRAL_IT_INSN
:
17134 now_it
.state
= MANUAL_IT_BLOCK
;
17135 now_it
.block_length
= 0;
17140 case AUTOMATIC_IT_BLOCK
:
17141 /* Three things may happen now:
17142 a) We should increment current it block size;
17143 b) We should close current it block (closing insn or 4 insns);
17144 c) We should close current it block and start a new one (due
17145 to incompatible conditions or
17146 4 insns-length block reached). */
17148 switch (inst
.it_insn_type
)
17150 case OUTSIDE_IT_INSN
:
17151 /* The closure of the block shall happen immediatelly,
17152 so any in_it_block () call reports the block as closed. */
17153 force_automatic_it_block_close ();
17156 case INSIDE_IT_INSN
:
17157 case INSIDE_IT_LAST_INSN
:
17158 case IF_INSIDE_IT_LAST_INSN
:
17159 now_it
.block_length
++;
17161 if (now_it
.block_length
> 4
17162 || !now_it_compatible (inst
.cond
))
17164 force_automatic_it_block_close ();
17165 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17166 new_automatic_it_block (inst
.cond
);
17170 now_it
.insn_cond
= TRUE
;
17171 now_it_add_mask (inst
.cond
);
17174 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17175 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17176 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17177 close_automatic_it_block ();
17180 case NEUTRAL_IT_INSN
:
17181 now_it
.block_length
++;
17182 now_it
.insn_cond
= TRUE
;
17184 if (now_it
.block_length
> 4)
17185 force_automatic_it_block_close ();
17187 now_it_add_mask (now_it
.cc
& 1);
17191 close_automatic_it_block ();
17192 now_it
.state
= MANUAL_IT_BLOCK
;
17197 case MANUAL_IT_BLOCK
:
17199 /* Check conditional suffixes. */
17200 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17203 now_it
.mask
&= 0x1f;
17204 is_last
= (now_it
.mask
== 0x10);
17205 now_it
.insn_cond
= TRUE
;
17207 switch (inst
.it_insn_type
)
17209 case OUTSIDE_IT_INSN
:
17210 inst
.error
= BAD_NOT_IT
;
17213 case INSIDE_IT_INSN
:
17214 if (cond
!= inst
.cond
)
17216 inst
.error
= BAD_IT_COND
;
17221 case INSIDE_IT_LAST_INSN
:
17222 case IF_INSIDE_IT_LAST_INSN
:
17223 if (cond
!= inst
.cond
)
17225 inst
.error
= BAD_IT_COND
;
17230 inst
.error
= BAD_BRANCH
;
17235 case NEUTRAL_IT_INSN
:
17236 /* The BKPT instruction is unconditional even in an IT block. */
17240 inst
.error
= BAD_IT_IT
;
17250 struct depr_insn_mask
17252 unsigned long pattern
;
17253 unsigned long mask
;
17254 const char* description
;
17257 /* List of 16-bit instruction patterns deprecated in an IT block in
17259 static const struct depr_insn_mask depr_it_insns
[] = {
17260 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17261 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17262 { 0xa000, 0xb800, N_("ADR") },
17263 { 0x4800, 0xf800, N_("Literal loads") },
17264 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17265 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17270 it_fsm_post_encode (void)
17274 if (!now_it
.state_handled
)
17275 handle_it_state ();
17277 if (now_it
.insn_cond
17278 && !now_it
.warn_deprecated
17279 && warn_on_deprecated
17280 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17282 if (inst
.instruction
>= 0x10000)
17284 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
17285 "deprecated in ARMv8"));
17286 now_it
.warn_deprecated
= TRUE
;
17290 const struct depr_insn_mask
*p
= depr_it_insns
;
17292 while (p
->mask
!= 0)
17294 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17296 as_warn (_("IT blocks containing 16-bit Thumb instructions "
17297 "of the following class are deprecated in ARMv8: "
17298 "%s"), p
->description
);
17299 now_it
.warn_deprecated
= TRUE
;
17307 if (now_it
.block_length
> 1)
17309 as_warn (_("IT blocks containing more than one conditional "
17310 "instruction are deprecated in ARMv8"));
17311 now_it
.warn_deprecated
= TRUE
;
17315 is_last
= (now_it
.mask
== 0x10);
17318 now_it
.state
= OUTSIDE_IT_BLOCK
;
17324 force_automatic_it_block_close (void)
17326 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17328 close_automatic_it_block ();
17329 now_it
.state
= OUTSIDE_IT_BLOCK
;
17337 if (!now_it
.state_handled
)
17338 handle_it_state ();
17340 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17344 md_assemble (char *str
)
17347 const struct asm_opcode
* opcode
;
17349 /* Align the previous label if needed. */
17350 if (last_label_seen
!= NULL
)
17352 symbol_set_frag (last_label_seen
, frag_now
);
17353 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17354 S_SET_SEGMENT (last_label_seen
, now_seg
);
17357 memset (&inst
, '\0', sizeof (inst
));
17358 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17360 opcode
= opcode_lookup (&p
);
17363 /* It wasn't an instruction, but it might be a register alias of
17364 the form alias .req reg, or a Neon .dn/.qn directive. */
17365 if (! create_register_alias (str
, p
)
17366 && ! create_neon_reg_alias (str
, p
))
17367 as_bad (_("bad instruction `%s'"), str
);
17372 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17373 as_warn (_("s suffix on comparison instruction is deprecated"));
17375 /* The value which unconditional instructions should have in place of the
17376 condition field. */
17377 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17381 arm_feature_set variant
;
17383 variant
= cpu_variant
;
17384 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17385 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17386 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17387 /* Check that this instruction is supported for this CPU. */
17388 if (!opcode
->tvariant
17389 || (thumb_mode
== 1
17390 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17392 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17395 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17396 && opcode
->tencode
!= do_t_branch
)
17398 as_bad (_("Thumb does not support conditional execution"));
17402 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17404 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17405 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17406 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17408 /* Two things are addressed here.
17409 1) Implicit require narrow instructions on Thumb-1.
17410 This avoids relaxation accidentally introducing Thumb-2
17412 2) Reject wide instructions in non Thumb-2 cores. */
17413 if (inst
.size_req
== 0)
17415 else if (inst
.size_req
== 4)
17417 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17423 inst
.instruction
= opcode
->tvalue
;
17425 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17427 /* Prepare the it_insn_type for those encodings that don't set
17429 it_fsm_pre_encode ();
17431 opcode
->tencode ();
17433 it_fsm_post_encode ();
17436 if (!(inst
.error
|| inst
.relax
))
17438 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17439 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17440 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17442 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17447 /* Something has gone badly wrong if we try to relax a fixed size
17449 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17451 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17452 *opcode
->tvariant
);
17453 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17454 set those bits when Thumb-2 32-bit instructions are seen. ie.
17455 anything other than bl/blx and v6-M instructions.
17456 This is overly pessimistic for relaxable instructions. */
17457 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17459 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17460 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17461 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17464 check_neon_suffixes
;
17468 mapping_state (MAP_THUMB
);
17471 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17475 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17476 is_bx
= (opcode
->aencode
== do_bx
);
17478 /* Check that this instruction is supported for this CPU. */
17479 if (!(is_bx
&& fix_v4bx
)
17480 && !(opcode
->avariant
&&
17481 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17483 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17488 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17492 inst
.instruction
= opcode
->avalue
;
17493 if (opcode
->tag
== OT_unconditionalF
)
17494 inst
.instruction
|= 0xF << 28;
17496 inst
.instruction
|= inst
.cond
<< 28;
17497 inst
.size
= INSN_SIZE
;
17498 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17500 it_fsm_pre_encode ();
17501 opcode
->aencode ();
17502 it_fsm_post_encode ();
17504 /* Arm mode bx is marked as both v4T and v5 because it's still required
17505 on a hypothetical non-thumb v5 core. */
17507 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17509 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17510 *opcode
->avariant
);
17512 check_neon_suffixes
;
17516 mapping_state (MAP_ARM
);
17521 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17529 check_it_blocks_finished (void)
17534 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17535 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17536 == MANUAL_IT_BLOCK
)
17538 as_warn (_("section '%s' finished with an open IT block."),
17542 if (now_it
.state
== MANUAL_IT_BLOCK
)
17543 as_warn (_("file finished with an open IT block."));
17547 /* Various frobbings of labels and their addresses. */
17550 arm_start_line_hook (void)
17552 last_label_seen
= NULL
;
17556 arm_frob_label (symbolS
* sym
)
17558 last_label_seen
= sym
;
17560 ARM_SET_THUMB (sym
, thumb_mode
);
17562 #if defined OBJ_COFF || defined OBJ_ELF
17563 ARM_SET_INTERWORK (sym
, support_interwork
);
17566 force_automatic_it_block_close ();
17568 /* Note - do not allow local symbols (.Lxxx) to be labelled
17569 as Thumb functions. This is because these labels, whilst
17570 they exist inside Thumb code, are not the entry points for
17571 possible ARM->Thumb calls. Also, these labels can be used
17572 as part of a computed goto or switch statement. eg gcc
17573 can generate code that looks like this:
17575 ldr r2, [pc, .Laaa]
17585 The first instruction loads the address of the jump table.
17586 The second instruction converts a table index into a byte offset.
17587 The third instruction gets the jump address out of the table.
17588 The fourth instruction performs the jump.
17590 If the address stored at .Laaa is that of a symbol which has the
17591 Thumb_Func bit set, then the linker will arrange for this address
17592 to have the bottom bit set, which in turn would mean that the
17593 address computation performed by the third instruction would end
17594 up with the bottom bit set. Since the ARM is capable of unaligned
17595 word loads, the instruction would then load the incorrect address
17596 out of the jump table, and chaos would ensue. */
17597 if (label_is_thumb_function_name
17598 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
17599 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
17601 /* When the address of a Thumb function is taken the bottom
17602 bit of that address should be set. This will allow
17603 interworking between Arm and Thumb functions to work
17606 THUMB_SET_FUNC (sym
, 1);
17608 label_is_thumb_function_name
= FALSE
;
17611 dwarf2_emit_label (sym
);
17615 arm_data_in_code (void)
17617 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
17619 *input_line_pointer
= '/';
17620 input_line_pointer
+= 5;
17621 *input_line_pointer
= 0;
17629 arm_canonicalize_symbol_name (char * name
)
17633 if (thumb_mode
&& (len
= strlen (name
)) > 5
17634 && streq (name
+ len
- 5, "/data"))
17635 *(name
+ len
- 5) = 0;
17640 /* Table of all register names defined by default. The user can
17641 define additional names with .req. Note that all register names
17642 should appear in both upper and lowercase variants. Some registers
17643 also have mixed-case names. */
17645 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17646 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17647 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17648 #define REGSET(p,t) \
17649 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17650 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17651 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17652 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17653 #define REGSETH(p,t) \
17654 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17655 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17656 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17657 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17658 #define REGSET2(p,t) \
17659 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17660 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17661 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17662 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17663 #define SPLRBANK(base,bank,t) \
17664 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17665 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17666 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17667 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17668 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17669 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17671 static const struct reg_entry reg_names
[] =
17673 /* ARM integer registers. */
17674 REGSET(r
, RN
), REGSET(R
, RN
),
17676 /* ATPCS synonyms. */
17677 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
17678 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
17679 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
17681 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
17682 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
17683 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
17685 /* Well-known aliases. */
17686 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
17687 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
17689 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
17690 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
17692 /* Coprocessor numbers. */
17693 REGSET(p
, CP
), REGSET(P
, CP
),
17695 /* Coprocessor register numbers. The "cr" variants are for backward
17697 REGSET(c
, CN
), REGSET(C
, CN
),
17698 REGSET(cr
, CN
), REGSET(CR
, CN
),
17700 /* ARM banked registers. */
17701 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
17702 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
17703 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
17704 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
17705 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
17706 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
17707 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
17709 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
17710 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
17711 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
17712 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
17713 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
17714 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
17715 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
17716 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
17718 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
17719 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
17720 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
17721 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
17722 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
17723 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
17724 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
17725 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17726 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17728 /* FPA registers. */
17729 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
17730 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
17732 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
17733 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
17735 /* VFP SP registers. */
17736 REGSET(s
,VFS
), REGSET(S
,VFS
),
17737 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
17739 /* VFP DP Registers. */
17740 REGSET(d
,VFD
), REGSET(D
,VFD
),
17741 /* Extra Neon DP registers. */
17742 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
17744 /* Neon QP registers. */
17745 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
17747 /* VFP control registers. */
17748 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
17749 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
17750 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
17751 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
17752 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
17753 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
17755 /* Maverick DSP coprocessor registers. */
17756 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
17757 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
17759 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
17760 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
17761 REGDEF(dspsc
,0,DSPSC
),
17763 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
17764 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
17765 REGDEF(DSPSC
,0,DSPSC
),
17767 /* iWMMXt data registers - p0, c0-15. */
17768 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
17770 /* iWMMXt control registers - p1, c0-3. */
17771 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
17772 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
17773 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
17774 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
17776 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17777 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
17778 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
17779 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
17780 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
17782 /* XScale accumulator registers. */
17783 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
17789 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17790 within psr_required_here. */
17791 static const struct asm_psr psrs
[] =
17793 /* Backward compatibility notation. Note that "all" is no longer
17794 truly all possible PSR bits. */
17795 {"all", PSR_c
| PSR_f
},
17799 /* Individual flags. */
17805 /* Combinations of flags. */
17806 {"fs", PSR_f
| PSR_s
},
17807 {"fx", PSR_f
| PSR_x
},
17808 {"fc", PSR_f
| PSR_c
},
17809 {"sf", PSR_s
| PSR_f
},
17810 {"sx", PSR_s
| PSR_x
},
17811 {"sc", PSR_s
| PSR_c
},
17812 {"xf", PSR_x
| PSR_f
},
17813 {"xs", PSR_x
| PSR_s
},
17814 {"xc", PSR_x
| PSR_c
},
17815 {"cf", PSR_c
| PSR_f
},
17816 {"cs", PSR_c
| PSR_s
},
17817 {"cx", PSR_c
| PSR_x
},
17818 {"fsx", PSR_f
| PSR_s
| PSR_x
},
17819 {"fsc", PSR_f
| PSR_s
| PSR_c
},
17820 {"fxs", PSR_f
| PSR_x
| PSR_s
},
17821 {"fxc", PSR_f
| PSR_x
| PSR_c
},
17822 {"fcs", PSR_f
| PSR_c
| PSR_s
},
17823 {"fcx", PSR_f
| PSR_c
| PSR_x
},
17824 {"sfx", PSR_s
| PSR_f
| PSR_x
},
17825 {"sfc", PSR_s
| PSR_f
| PSR_c
},
17826 {"sxf", PSR_s
| PSR_x
| PSR_f
},
17827 {"sxc", PSR_s
| PSR_x
| PSR_c
},
17828 {"scf", PSR_s
| PSR_c
| PSR_f
},
17829 {"scx", PSR_s
| PSR_c
| PSR_x
},
17830 {"xfs", PSR_x
| PSR_f
| PSR_s
},
17831 {"xfc", PSR_x
| PSR_f
| PSR_c
},
17832 {"xsf", PSR_x
| PSR_s
| PSR_f
},
17833 {"xsc", PSR_x
| PSR_s
| PSR_c
},
17834 {"xcf", PSR_x
| PSR_c
| PSR_f
},
17835 {"xcs", PSR_x
| PSR_c
| PSR_s
},
17836 {"cfs", PSR_c
| PSR_f
| PSR_s
},
17837 {"cfx", PSR_c
| PSR_f
| PSR_x
},
17838 {"csf", PSR_c
| PSR_s
| PSR_f
},
17839 {"csx", PSR_c
| PSR_s
| PSR_x
},
17840 {"cxf", PSR_c
| PSR_x
| PSR_f
},
17841 {"cxs", PSR_c
| PSR_x
| PSR_s
},
17842 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
17843 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
17844 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
17845 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
17846 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
17847 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
17848 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
17849 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
17850 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
17851 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
17852 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
17853 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
17854 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
17855 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
17856 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
17857 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
17858 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
17859 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
17860 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
17861 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
17862 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
17863 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
17864 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
17865 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
17868 /* Table of V7M psr names. */
17869 static const struct asm_psr v7m_psrs
[] =
17871 {"apsr", 0 }, {"APSR", 0 },
17872 {"iapsr", 1 }, {"IAPSR", 1 },
17873 {"eapsr", 2 }, {"EAPSR", 2 },
17874 {"psr", 3 }, {"PSR", 3 },
17875 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17876 {"ipsr", 5 }, {"IPSR", 5 },
17877 {"epsr", 6 }, {"EPSR", 6 },
17878 {"iepsr", 7 }, {"IEPSR", 7 },
17879 {"msp", 8 }, {"MSP", 8 },
17880 {"psp", 9 }, {"PSP", 9 },
17881 {"primask", 16}, {"PRIMASK", 16},
17882 {"basepri", 17}, {"BASEPRI", 17},
17883 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17884 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17885 {"faultmask", 19}, {"FAULTMASK", 19},
17886 {"control", 20}, {"CONTROL", 20}
17889 /* Table of all shift-in-operand names. */
17890 static const struct asm_shift_name shift_names
[] =
17892 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
17893 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
17894 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
17895 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
17896 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
17897 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
17900 /* Table of all explicit relocation names. */
17902 static struct reloc_entry reloc_names
[] =
17904 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
17905 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
17906 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
17907 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
17908 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
17909 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
17910 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
17911 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
17912 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
17913 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
17914 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
17915 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
17916 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
17917 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
17918 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
17919 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
17920 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
17921 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
17925 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17926 static const struct asm_cond conds
[] =
17930 {"cs", 0x2}, {"hs", 0x2},
17931 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17945 #define UL_BARRIER(L,U,CODE,FEAT) \
17946 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17947 { U, CODE, ARM_FEATURE (FEAT, 0) }
17949 static struct asm_barrier_opt barrier_opt_names
[] =
17951 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
17952 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
17953 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
17954 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
17955 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
17956 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
17957 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
17958 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
17959 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
17960 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
17961 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
17962 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
17963 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
17964 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
17965 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
17966 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
17971 /* Table of ARM-format instructions. */
17973 /* Macros for gluing together operand strings. N.B. In all cases
17974 other than OPS0, the trailing OP_stop comes from default
17975 zero-initialization of the unspecified elements of the array. */
17976 #define OPS0() { OP_stop, }
17977 #define OPS1(a) { OP_##a, }
17978 #define OPS2(a,b) { OP_##a,OP_##b, }
17979 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17980 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17981 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17982 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17984 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17985 This is useful when mixing operands for ARM and THUMB, i.e. using the
17986 MIX_ARM_THUMB_OPERANDS macro.
17987 In order to use these macros, prefix the number of operands with _
17989 #define OPS_1(a) { a, }
17990 #define OPS_2(a,b) { a,b, }
17991 #define OPS_3(a,b,c) { a,b,c, }
17992 #define OPS_4(a,b,c,d) { a,b,c,d, }
17993 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17994 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17996 /* These macros abstract out the exact format of the mnemonic table and
17997 save some repeated characters. */
17999 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18000 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18001 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18002 THUMB_VARIANT, do_##ae, do_##te }
18004 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18005 a T_MNEM_xyz enumerator. */
18006 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18007 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18008 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18009 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18011 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18012 infix after the third character. */
18013 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18014 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18015 THUMB_VARIANT, do_##ae, do_##te }
18016 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18017 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18018 THUMB_VARIANT, do_##ae, do_##te }
18019 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18020 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18021 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18022 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18023 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18024 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18025 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18026 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18028 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18029 field is still 0xE. Many of the Thumb variants can be executed
18030 conditionally, so this is checked separately. */
18031 #define TUE(mnem, op, top, nops, ops, ae, te) \
18032 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18033 THUMB_VARIANT, do_##ae, do_##te }
18035 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18036 Used by mnemonics that have very minimal differences in the encoding for
18037 ARM and Thumb variants and can be handled in a common function. */
18038 #define TUEc(mnem, op, top, nops, ops, en) \
18039 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18040 THUMB_VARIANT, do_##en, do_##en }
18042 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18043 condition code field. */
18044 #define TUF(mnem, op, top, nops, ops, ae, te) \
18045 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18046 THUMB_VARIANT, do_##ae, do_##te }
18048 /* ARM-only variants of all the above. */
18049 #define CE(mnem, op, nops, ops, ae) \
18050 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18052 #define C3(mnem, op, nops, ops, ae) \
18053 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18055 /* Legacy mnemonics that always have conditional infix after the third
18057 #define CL(mnem, op, nops, ops, ae) \
18058 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18059 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18061 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18062 #define cCE(mnem, op, nops, ops, ae) \
18063 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18065 /* Legacy coprocessor instructions where conditional infix and conditional
18066 suffix are ambiguous. For consistency this includes all FPA instructions,
18067 not just the potentially ambiguous ones. */
18068 #define cCL(mnem, op, nops, ops, ae) \
18069 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18070 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18072 /* Coprocessor, takes either a suffix or a position-3 infix
18073 (for an FPA corner case). */
18074 #define C3E(mnem, op, nops, ops, ae) \
18075 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18076 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18078 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18079 { m1 #m2 m3, OPS##nops ops, \
18080 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18081 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18083 #define CM(m1, m2, op, nops, ops, ae) \
18084 xCM_ (m1, , m2, op, nops, ops, ae), \
18085 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18086 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18087 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18088 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18089 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18090 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18091 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18092 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18093 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18094 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18095 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18096 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18097 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18098 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18099 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18100 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18101 xCM_ (m1, le, m2, op, nops, ops, ae), \
18102 xCM_ (m1, al, m2, op, nops, ops, ae)
18104 #define UE(mnem, op, nops, ops, ae) \
18105 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18107 #define UF(mnem, op, nops, ops, ae) \
18108 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18110 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18111 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18112 use the same encoding function for each. */
18113 #define NUF(mnem, op, nops, ops, enc) \
18114 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18115 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18117 /* Neon data processing, version which indirects through neon_enc_tab for
18118 the various overloaded versions of opcodes. */
18119 #define nUF(mnem, op, nops, ops, enc) \
18120 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18121 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18123 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18125 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18126 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18127 THUMB_VARIANT, do_##enc, do_##enc }
18129 #define NCE(mnem, op, nops, ops, enc) \
18130 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18132 #define NCEF(mnem, op, nops, ops, enc) \
18133 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18135 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18136 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18137 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18138 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18140 #define nCE(mnem, op, nops, ops, enc) \
18141 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18143 #define nCEF(mnem, op, nops, ops, enc) \
18144 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18148 static const struct asm_opcode insns
[] =
18150 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18151 #define THUMB_VARIANT & arm_ext_v4t
18152 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18153 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18154 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18155 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18156 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18157 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18158 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18159 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18160 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18161 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18162 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18163 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18164 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18165 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18166 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18167 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18169 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18170 for setting PSR flag bits. They are obsolete in V6 and do not
18171 have Thumb equivalents. */
18172 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18173 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18174 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18175 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18176 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18177 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18178 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18179 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18180 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18182 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18183 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18184 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18185 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18187 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18188 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18189 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18191 OP_ADDRGLDR
),ldst
, t_ldst
),
18192 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18194 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18195 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18196 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18197 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18198 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18199 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18201 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18202 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18203 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18204 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18207 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18208 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18209 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18210 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18212 /* Thumb-compatibility pseudo ops. */
18213 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18214 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18215 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18216 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18217 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18218 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18219 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18220 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18221 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18222 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18223 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18224 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18226 /* These may simplify to neg. */
18227 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18228 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18230 #undef THUMB_VARIANT
18231 #define THUMB_VARIANT & arm_ext_v6
18233 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18235 /* V1 instructions with no Thumb analogue prior to V6T2. */
18236 #undef THUMB_VARIANT
18237 #define THUMB_VARIANT & arm_ext_v6t2
18239 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18240 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18241 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18243 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18244 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18245 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18246 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18248 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18249 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18251 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18252 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18254 /* V1 instructions with no Thumb analogue at all. */
18255 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18256 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18258 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18259 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18260 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18261 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18262 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18263 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18264 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18265 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18268 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18269 #undef THUMB_VARIANT
18270 #define THUMB_VARIANT & arm_ext_v4t
18272 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18273 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18275 #undef THUMB_VARIANT
18276 #define THUMB_VARIANT & arm_ext_v6t2
18278 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18279 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18281 /* Generic coprocessor instructions. */
18282 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18283 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18284 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18285 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18286 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18287 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18288 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18291 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18293 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18294 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18297 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18298 #undef THUMB_VARIANT
18299 #define THUMB_VARIANT & arm_ext_msr
18301 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18302 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18305 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18306 #undef THUMB_VARIANT
18307 #define THUMB_VARIANT & arm_ext_v6t2
18309 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18310 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18311 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18312 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18313 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18314 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18315 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18316 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18319 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18320 #undef THUMB_VARIANT
18321 #define THUMB_VARIANT & arm_ext_v4t
18323 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18324 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18325 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18326 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18327 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18328 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18331 #define ARM_VARIANT & arm_ext_v4t_5
18333 /* ARM Architecture 4T. */
18334 /* Note: bx (and blx) are required on V5, even if the processor does
18335 not support Thumb. */
18336 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18339 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18340 #undef THUMB_VARIANT
18341 #define THUMB_VARIANT & arm_ext_v5t
18343 /* Note: blx has 2 variants; the .value coded here is for
18344 BLX(2). Only this variant has conditional execution. */
18345 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18346 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18348 #undef THUMB_VARIANT
18349 #define THUMB_VARIANT & arm_ext_v6t2
18351 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18352 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18353 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18354 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18355 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18356 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18357 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18358 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18361 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18362 #undef THUMB_VARIANT
18363 #define THUMB_VARIANT & arm_ext_v5exp
18365 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18366 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18367 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18368 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18370 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18371 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18373 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18374 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18375 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18376 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18378 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18379 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18380 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18381 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18383 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18384 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18386 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18387 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18388 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18389 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18392 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18393 #undef THUMB_VARIANT
18394 #define THUMB_VARIANT & arm_ext_v6t2
18396 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18397 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18399 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18400 ADDRGLDRS
), ldrd
, t_ldstd
),
18402 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18403 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18406 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18408 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18411 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18412 #undef THUMB_VARIANT
18413 #define THUMB_VARIANT & arm_ext_v6
18415 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18416 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18417 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18418 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18419 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18420 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18421 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18422 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18423 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18424 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18426 #undef THUMB_VARIANT
18427 #define THUMB_VARIANT & arm_ext_v6t2
18429 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18430 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18432 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18433 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18435 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18436 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18438 /* ARM V6 not included in V7M. */
18439 #undef THUMB_VARIANT
18440 #define THUMB_VARIANT & arm_ext_v6_notm
18441 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18442 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18443 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18444 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18445 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18446 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18447 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18448 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18449 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18450 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18451 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18452 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18453 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18454 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18455 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18456 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18457 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18458 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18460 /* ARM V6 not included in V7M (eg. integer SIMD). */
18461 #undef THUMB_VARIANT
18462 #define THUMB_VARIANT & arm_ext_v6_dsp
18463 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18464 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18465 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18466 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18467 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18468 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18469 /* Old name for QASX. */
18470 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18471 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18472 /* Old name for QSAX. */
18473 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18474 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18475 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18476 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18477 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18478 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18479 /* Old name for SASX. */
18480 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18481 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18482 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18483 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18484 /* Old name for SHASX. */
18485 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18486 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18487 /* Old name for SHSAX. */
18488 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18489 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18490 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18491 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18492 /* Old name for SSAX. */
18493 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18494 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18495 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18496 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18497 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18498 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18499 /* Old name for UASX. */
18500 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18501 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18502 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18503 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18504 /* Old name for UHASX. */
18505 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18506 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18507 /* Old name for UHSAX. */
18508 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18509 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18510 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18511 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18512 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18513 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18514 /* Old name for UQASX. */
18515 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18516 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18517 /* Old name for UQSAX. */
18518 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18519 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18520 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18521 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18522 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18523 /* Old name for USAX. */
18524 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18525 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18526 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18527 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18528 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18529 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18530 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18531 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18532 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18533 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18534 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18535 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18536 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18537 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18538 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18539 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18540 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18541 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18542 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18543 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18544 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18545 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18546 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18547 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18548 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18549 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18550 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18551 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18552 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18553 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18554 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18555 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18556 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18557 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18560 #define ARM_VARIANT & arm_ext_v6k
18561 #undef THUMB_VARIANT
18562 #define THUMB_VARIANT & arm_ext_v6k
18564 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18565 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18566 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18567 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18569 #undef THUMB_VARIANT
18570 #define THUMB_VARIANT & arm_ext_v6_notm
18571 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
18573 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
18574 RRnpcb
), strexd
, t_strexd
),
18576 #undef THUMB_VARIANT
18577 #define THUMB_VARIANT & arm_ext_v6t2
18578 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
18580 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
18582 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18584 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18586 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
18589 #define ARM_VARIANT & arm_ext_sec
18590 #undef THUMB_VARIANT
18591 #define THUMB_VARIANT & arm_ext_sec
18593 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
18596 #define ARM_VARIANT & arm_ext_virt
18597 #undef THUMB_VARIANT
18598 #define THUMB_VARIANT & arm_ext_virt
18600 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
18601 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
18604 #define ARM_VARIANT & arm_ext_v6t2
18605 #undef THUMB_VARIANT
18606 #define THUMB_VARIANT & arm_ext_v6t2
18608 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
18609 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
18610 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18611 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18613 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18614 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18615 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18616 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
18618 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18619 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18620 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18621 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18623 /* Thumb-only instructions. */
18625 #define ARM_VARIANT NULL
18626 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
18627 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
18629 /* ARM does not really have an IT instruction, so always allow it.
18630 The opcode is copied from Thumb in order to allow warnings in
18631 -mimplicit-it=[never | arm] modes. */
18633 #define ARM_VARIANT & arm_ext_v1
18635 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
18636 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
18637 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
18638 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
18639 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
18640 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
18641 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
18642 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
18643 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
18644 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
18645 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
18646 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
18647 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
18648 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
18649 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
18650 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18651 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18652 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18654 /* Thumb2 only instructions. */
18656 #define ARM_VARIANT NULL
18658 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18659 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18660 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18661 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18662 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
18663 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
18665 /* Hardware division instructions. */
18667 #define ARM_VARIANT & arm_ext_adiv
18668 #undef THUMB_VARIANT
18669 #define THUMB_VARIANT & arm_ext_div
18671 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18672 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18674 /* ARM V6M/V7 instructions. */
18676 #define ARM_VARIANT & arm_ext_barrier
18677 #undef THUMB_VARIANT
18678 #define THUMB_VARIANT & arm_ext_barrier
18680 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
18681 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
18682 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
18684 /* ARM V7 instructions. */
18686 #define ARM_VARIANT & arm_ext_v7
18687 #undef THUMB_VARIANT
18688 #define THUMB_VARIANT & arm_ext_v7
18690 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
18691 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
18694 #define ARM_VARIANT & arm_ext_mp
18695 #undef THUMB_VARIANT
18696 #define THUMB_VARIANT & arm_ext_mp
18698 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
18700 /* AArchv8 instructions. */
18702 #define ARM_VARIANT & arm_ext_v8
18703 #undef THUMB_VARIANT
18704 #define THUMB_VARIANT & arm_ext_v8
18706 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
18707 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
18708 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18709 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
18711 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
18712 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18713 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18715 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
18717 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18719 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18721 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18722 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18723 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18724 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18725 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18726 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18728 /* ARMv8 T32 only. */
18730 #define ARM_VARIANT NULL
18731 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
18732 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
18733 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
18735 /* FP for ARMv8. */
18737 #define ARM_VARIANT & fpu_vfp_ext_armv8
18738 #undef THUMB_VARIANT
18739 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18741 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18742 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18743 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18744 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18745 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
18746 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
18747 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
18748 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
18749 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
18750 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
18751 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
18752 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
18753 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
18754 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
18755 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
18756 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
18757 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
18759 /* Crypto v1 extensions. */
18761 #define ARM_VARIANT & fpu_crypto_ext_armv8
18762 #undef THUMB_VARIANT
18763 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18765 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
18766 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
18767 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
18768 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
18769 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
18770 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
18771 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
18772 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
18773 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
18774 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
18775 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
18776 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
18777 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
18778 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
18781 #define ARM_VARIANT & crc_ext_armv8
18782 #undef THUMB_VARIANT
18783 #define THUMB_VARIANT & crc_ext_armv8
18784 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
18785 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
18786 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
18787 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
18788 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
18789 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
18792 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18793 #undef THUMB_VARIANT
18794 #define THUMB_VARIANT NULL
18796 cCE("wfs", e200110
, 1, (RR
), rd
),
18797 cCE("rfs", e300110
, 1, (RR
), rd
),
18798 cCE("wfc", e400110
, 1, (RR
), rd
),
18799 cCE("rfc", e500110
, 1, (RR
), rd
),
18801 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18802 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18803 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18804 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18806 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18807 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18808 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18809 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18811 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
18812 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
18813 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
18814 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
18815 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
18816 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
18817 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
18818 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
18819 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
18820 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
18821 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
18822 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
18824 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
18825 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
18826 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
18827 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
18828 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
18829 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
18830 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
18831 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
18832 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
18833 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
18834 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
18835 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
18837 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
18838 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
18839 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
18840 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
18841 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
18842 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
18843 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
18844 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
18845 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
18846 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
18847 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
18848 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
18850 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
18851 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
18852 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
18853 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
18854 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
18855 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
18856 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
18857 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
18858 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
18859 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
18860 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
18861 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
18863 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
18864 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
18865 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
18866 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
18867 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
18868 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
18869 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
18870 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
18871 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
18872 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
18873 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
18874 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
18876 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
18877 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
18878 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
18879 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
18880 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
18881 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
18882 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
18883 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
18884 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
18885 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
18886 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
18887 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
18889 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
18890 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
18891 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
18892 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
18893 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
18894 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
18895 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
18896 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
18897 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
18898 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
18899 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
18900 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
18902 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
18903 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
18904 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
18905 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
18906 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
18907 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
18908 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
18909 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
18910 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
18911 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
18912 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
18913 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
18915 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
18916 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
18917 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
18918 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
18919 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
18920 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
18921 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
18922 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
18923 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
18924 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
18925 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
18926 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
18928 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
18929 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
18930 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
18931 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
18932 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
18933 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
18934 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
18935 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
18936 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
18937 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
18938 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
18939 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
18941 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
18942 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
18943 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
18944 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
18945 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
18946 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
18947 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
18948 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
18949 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
18950 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
18951 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
18952 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
18954 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
18955 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
18956 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
18957 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
18958 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
18959 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
18960 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
18961 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
18962 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
18963 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
18964 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
18965 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
18967 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
18968 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
18969 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
18970 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
18971 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
18972 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
18973 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
18974 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
18975 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
18976 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
18977 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
18978 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
18980 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
18981 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
18982 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
18983 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
18984 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
18985 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
18986 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
18987 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
18988 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
18989 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
18990 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
18991 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
18993 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
18994 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
18995 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
18996 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
18997 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
18998 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
18999 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19000 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19001 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19002 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19003 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19004 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19006 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19007 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19008 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19009 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19010 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19011 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19012 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19013 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19014 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19015 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19016 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19017 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19019 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19020 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19021 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19022 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19023 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19024 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19025 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19026 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19027 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19028 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19029 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19030 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19032 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19033 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19034 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19035 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19036 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19037 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19038 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19039 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19040 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19041 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19042 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19043 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19045 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19046 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19047 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19048 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19049 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19050 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19051 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19052 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19053 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19054 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19055 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19056 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19058 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19059 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19060 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19061 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19062 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19063 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19064 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19065 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19066 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19067 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19068 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19069 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19071 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19072 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19073 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19074 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19075 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19076 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19077 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19078 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19079 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19080 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19081 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19082 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19084 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19085 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19086 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19087 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19088 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19089 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19090 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19091 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19092 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19093 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19094 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19095 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19097 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19098 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19099 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19100 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19101 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19102 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19103 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19104 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19105 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19106 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19107 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19108 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19110 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19111 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19112 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19113 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19114 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19115 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19116 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19117 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19118 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19119 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19120 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19121 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19123 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19124 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19125 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19126 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19127 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19128 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19129 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19130 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19131 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19132 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19133 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19134 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19136 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19137 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19138 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19139 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19140 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19141 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19142 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19143 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19144 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19145 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19146 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19147 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19149 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19150 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19151 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19152 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19153 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19154 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19155 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19156 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19157 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19158 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19159 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19160 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19162 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19163 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19164 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19165 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19166 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19167 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19168 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19169 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19170 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19171 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19172 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19173 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19175 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19176 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19177 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19178 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19179 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19180 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19181 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19182 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19183 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19184 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19185 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19186 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19188 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19189 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19190 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19191 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19193 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19194 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19195 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19196 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19197 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19198 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19199 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19200 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19201 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19202 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19203 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19204 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19206 /* The implementation of the FIX instruction is broken on some
19207 assemblers, in that it accepts a precision specifier as well as a
19208 rounding specifier, despite the fact that this is meaningless.
19209 To be more compatible, we accept it as well, though of course it
19210 does not set any bits. */
19211 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19212 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19213 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19214 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19215 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19216 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19217 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19218 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19219 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19220 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19221 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19222 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19223 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19225 /* Instructions that were new with the real FPA, call them V2. */
19227 #define ARM_VARIANT & fpu_fpa_ext_v2
19229 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19230 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19231 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19232 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19233 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19234 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19237 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19239 /* Moves and type conversions. */
19240 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19241 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19242 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19243 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19244 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19245 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19246 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19247 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19248 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19249 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19250 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19251 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19252 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19253 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19255 /* Memory operations. */
19256 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19257 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19258 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19259 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19260 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19261 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19262 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19263 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19264 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19265 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19266 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19267 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19268 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19269 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19270 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19271 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19272 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19273 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19275 /* Monadic operations. */
19276 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19277 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19278 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19280 /* Dyadic operations. */
19281 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19282 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19283 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19284 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19285 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19286 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19287 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19288 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19289 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19292 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19293 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19294 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19295 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19297 /* Double precision load/store are still present on single precision
19298 implementations. */
19299 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19300 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19301 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19302 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19303 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19304 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19305 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19306 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19307 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19308 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19311 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19313 /* Moves and type conversions. */
19314 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19315 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19316 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19317 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19318 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19319 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19320 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19321 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19322 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19323 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19324 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19325 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19326 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19328 /* Monadic operations. */
19329 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19330 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19331 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19333 /* Dyadic operations. */
19334 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19335 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19336 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19337 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19338 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19339 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19340 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19341 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19342 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19345 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19346 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19347 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19348 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19351 #define ARM_VARIANT & fpu_vfp_ext_v2
19353 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19354 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19355 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19356 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19358 /* Instructions which may belong to either the Neon or VFP instruction sets.
19359 Individual encoder functions perform additional architecture checks. */
19361 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19362 #undef THUMB_VARIANT
19363 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19365 /* These mnemonics are unique to VFP. */
19366 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19367 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19368 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19369 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19370 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19371 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
19372 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
19373 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19374 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19375 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19377 /* Mnemonics shared by Neon and VFP. */
19378 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19379 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19380 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19382 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19383 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19385 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19386 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19388 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19389 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19390 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19391 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19392 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19393 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19394 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19395 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19397 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19398 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19399 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19400 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19403 /* NOTE: All VMOV encoding is special-cased! */
19404 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19405 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19407 #undef THUMB_VARIANT
19408 #define THUMB_VARIANT & fpu_neon_ext_v1
19410 #define ARM_VARIANT & fpu_neon_ext_v1
19412 /* Data processing with three registers of the same length. */
19413 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19414 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19415 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19416 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19417 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19418 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19419 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19420 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19421 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19422 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19423 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19424 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19425 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19426 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19427 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19428 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19429 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19430 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19431 /* If not immediate, fall back to neon_dyadic_i64_su.
19432 shl_imm should accept I8 I16 I32 I64,
19433 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19434 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19435 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19436 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19437 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19438 /* Logic ops, types optional & ignored. */
19439 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19440 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19441 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19442 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19443 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19444 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19445 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19446 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19447 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19448 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19449 /* Bitfield ops, untyped. */
19450 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19451 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19452 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19453 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19454 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19455 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19456 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19457 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19458 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19459 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19460 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19461 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19462 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19463 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19464 back to neon_dyadic_if_su. */
19465 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19466 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19467 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19468 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19469 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19470 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19471 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19472 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19473 /* Comparison. Type I8 I16 I32 F32. */
19474 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19475 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19476 /* As above, D registers only. */
19477 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19478 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19479 /* Int and float variants, signedness unimportant. */
19480 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19481 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19482 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19483 /* Add/sub take types I8 I16 I32 I64 F32. */
19484 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19485 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19486 /* vtst takes sizes 8, 16, 32. */
19487 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19488 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19489 /* VMUL takes I8 I16 I32 F32 P8. */
19490 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19491 /* VQD{R}MULH takes S16 S32. */
19492 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19493 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19494 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19495 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19496 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19497 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19498 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19499 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19500 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19501 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19502 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19503 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19504 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19505 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19506 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19507 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19509 /* Two address, int/float. Types S8 S16 S32 F32. */
19510 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19511 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19513 /* Data processing with two registers and a shift amount. */
19514 /* Right shifts, and variants with rounding.
19515 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19516 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19517 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19518 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19519 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19520 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19521 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19522 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19523 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19524 /* Shift and insert. Sizes accepted 8 16 32 64. */
19525 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19526 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19527 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19528 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19529 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19530 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19531 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19532 /* Right shift immediate, saturating & narrowing, with rounding variants.
19533 Types accepted S16 S32 S64 U16 U32 U64. */
19534 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19535 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19536 /* As above, unsigned. Types accepted S16 S32 S64. */
19537 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19538 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19539 /* Right shift narrowing. Types accepted I16 I32 I64. */
19540 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19541 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19542 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19543 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19544 /* CVT with optional immediate for fixed-point variant. */
19545 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19547 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19548 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19550 /* Data processing, three registers of different lengths. */
19551 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19552 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19553 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19554 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19555 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19556 /* If not scalar, fall back to neon_dyadic_long.
19557 Vector types as above, scalar types S16 S32 U16 U32. */
19558 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19559 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19560 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19561 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19562 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19563 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19564 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19565 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19566 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19567 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19568 /* Saturating doubling multiplies. Types S16 S32. */
19569 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19570 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19571 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19572 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19573 S16 S32 U16 U32. */
19574 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
19576 /* Extract. Size 8. */
19577 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
19578 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
19580 /* Two registers, miscellaneous. */
19581 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19582 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
19583 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
19584 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
19585 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
19586 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
19587 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
19588 /* Vector replicate. Sizes 8 16 32. */
19589 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
19590 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
19591 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19592 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
19593 /* VMOVN. Types I16 I32 I64. */
19594 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
19595 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19596 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
19597 /* VQMOVUN. Types S16 S32 S64. */
19598 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
19599 /* VZIP / VUZP. Sizes 8 16 32. */
19600 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19601 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19602 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19603 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19604 /* VQABS / VQNEG. Types S8 S16 S32. */
19605 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19606 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19607 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19608 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19609 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19610 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19611 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
19612 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19613 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
19614 /* Reciprocal estimates. Types U32 F32. */
19615 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19616 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
19617 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19618 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
19619 /* VCLS. Types S8 S16 S32. */
19620 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
19621 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
19622 /* VCLZ. Types I8 I16 I32. */
19623 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
19624 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
19625 /* VCNT. Size 8. */
19626 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
19627 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
19628 /* Two address, untyped. */
19629 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
19630 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
19631 /* VTRN. Sizes 8 16 32. */
19632 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
19633 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
19635 /* Table lookup. Size 8. */
19636 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19637 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19639 #undef THUMB_VARIANT
19640 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19642 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19644 /* Neon element/structure load/store. */
19645 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19646 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19647 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19648 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19649 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19650 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19651 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19652 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19654 #undef THUMB_VARIANT
19655 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
19657 #define ARM_VARIANT & fpu_vfp_ext_v3xd
19658 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
19659 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19660 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19661 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19662 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19663 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19664 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19665 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19666 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19668 #undef THUMB_VARIANT
19669 #define THUMB_VARIANT & fpu_vfp_ext_v3
19671 #define ARM_VARIANT & fpu_vfp_ext_v3
19673 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
19674 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19675 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19676 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19677 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19678 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19679 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19680 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19681 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19684 #define ARM_VARIANT & fpu_vfp_ext_fma
19685 #undef THUMB_VARIANT
19686 #define THUMB_VARIANT & fpu_vfp_ext_fma
19687 /* Mnemonics shared by Neon and VFP. These are included in the
19688 VFP FMA variant; NEON and VFP FMA always includes the NEON
19689 FMA instructions. */
19690 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19691 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19692 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19693 the v form should always be used. */
19694 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19695 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19696 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19697 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19698 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19699 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19701 #undef THUMB_VARIANT
19703 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19705 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19706 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19707 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19708 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19709 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19710 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19711 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
19712 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
19715 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19717 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
19718 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
19719 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
19720 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
19721 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
19722 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
19723 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
19724 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
19725 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
19726 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19727 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19728 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19729 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19730 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19731 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19732 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19733 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19734 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19735 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
19736 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
19737 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19738 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19739 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19740 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19741 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19742 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19743 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
19744 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
19745 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
19746 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
19747 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
19748 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
19749 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
19750 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
19751 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19752 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19753 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19754 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19755 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19756 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19757 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19758 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19759 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19760 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19761 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19762 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19763 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
19764 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19765 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19766 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19767 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19768 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19769 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19770 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19771 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19772 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19773 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19774 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19775 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19776 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19777 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19778 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19779 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19780 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19781 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19782 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19783 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19784 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19785 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19786 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19787 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19788 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19789 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19790 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19791 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19792 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19793 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19794 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19795 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19796 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19797 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19798 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19799 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19800 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19801 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19802 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19803 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19804 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19805 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
19806 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19807 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19808 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19809 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19810 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19811 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19812 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19813 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19814 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19815 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19816 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19817 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19818 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19819 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19820 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19821 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19822 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19823 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19824 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19825 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19826 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19827 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
19828 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19829 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19830 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19831 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19832 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19833 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19834 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19835 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19836 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19837 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19838 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19839 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19840 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19841 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19842 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19843 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19844 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19845 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19846 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19847 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19848 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19849 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19850 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19851 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19852 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19853 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19854 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19855 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19856 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19857 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19858 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19859 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19860 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19861 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19862 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19863 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19864 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19865 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19866 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19867 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19868 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19869 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19870 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19871 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19872 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19873 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19874 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19875 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19876 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19877 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19878 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
19881 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19883 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
19884 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
19885 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
19886 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19887 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19888 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19889 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19890 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19891 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19892 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19893 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19894 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19895 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19896 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19897 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19898 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19899 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19900 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19901 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19902 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19903 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
19904 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19905 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19906 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19907 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19908 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19909 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19910 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19911 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19912 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19913 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19914 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19915 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19916 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19917 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19918 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19919 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19920 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19921 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19922 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19923 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19924 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19925 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19926 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19927 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19928 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19929 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19930 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19931 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19932 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19933 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19934 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19935 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19936 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19937 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19938 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19939 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19942 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19944 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19945 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19946 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19947 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19948 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19949 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19950 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19951 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19952 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
19953 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
19954 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
19955 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
19956 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
19957 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
19958 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
19959 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
19960 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
19961 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
19962 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
19963 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
19964 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
19965 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
19966 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
19967 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
19968 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
19969 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
19970 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
19971 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
19972 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
19973 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
19974 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
19975 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
19976 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
19977 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
19978 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
19979 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
19980 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
19981 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
19982 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
19983 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
19984 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
19985 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
19986 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
19987 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
19988 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
19989 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
19990 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
19991 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
19992 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
19993 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
19994 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
19995 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
19996 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
19997 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
19998 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
19999 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20000 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20001 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20002 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20003 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20004 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20005 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20006 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20007 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20008 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20009 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20010 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20011 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20012 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20013 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20014 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20015 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20016 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20017 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20018 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20019 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20022 #undef THUMB_VARIANT
20048 /* MD interface: bits in the object file. */
20050 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20051 for use in the a.out file, and stores them in the array pointed to by buf.
20052 This knows about the endian-ness of the target machine and does
20053 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20054 2 (short) and 4 (long) Floating numbers are put out as a series of
20055 LITTLENUMS (shorts, here at least). */
20058 md_number_to_chars (char * buf
, valueT val
, int n
)
20060 if (target_big_endian
)
20061 number_to_chars_bigendian (buf
, val
, n
);
20063 number_to_chars_littleendian (buf
, val
, n
);
20067 md_chars_to_number (char * buf
, int n
)
20070 unsigned char * where
= (unsigned char *) buf
;
20072 if (target_big_endian
)
20077 result
|= (*where
++ & 255);
20085 result
|= (where
[n
] & 255);
20092 /* MD interface: Sections. */
20094 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20095 that an rs_machine_dependent frag may reach. */
20098 arm_frag_max_var (fragS
*fragp
)
20100 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20101 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20103 Note that we generate relaxable instructions even for cases that don't
20104 really need it, like an immediate that's a trivial constant. So we're
20105 overestimating the instruction size for some of those cases. Rather
20106 than putting more intelligence here, it would probably be better to
20107 avoid generating a relaxation frag in the first place when it can be
20108 determined up front that a short instruction will suffice. */
20110 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20114 /* Estimate the size of a frag before relaxing. Assume everything fits in
20118 md_estimate_size_before_relax (fragS
* fragp
,
20119 segT segtype ATTRIBUTE_UNUSED
)
20125 /* Convert a machine dependent frag. */
20128 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20130 unsigned long insn
;
20131 unsigned long old_op
;
20139 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20141 old_op
= bfd_get_16(abfd
, buf
);
20142 if (fragp
->fr_symbol
)
20144 exp
.X_op
= O_symbol
;
20145 exp
.X_add_symbol
= fragp
->fr_symbol
;
20149 exp
.X_op
= O_constant
;
20151 exp
.X_add_number
= fragp
->fr_offset
;
20152 opcode
= fragp
->fr_subtype
;
20155 case T_MNEM_ldr_pc
:
20156 case T_MNEM_ldr_pc2
:
20157 case T_MNEM_ldr_sp
:
20158 case T_MNEM_str_sp
:
20165 if (fragp
->fr_var
== 4)
20167 insn
= THUMB_OP32 (opcode
);
20168 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20170 insn
|= (old_op
& 0x700) << 4;
20174 insn
|= (old_op
& 7) << 12;
20175 insn
|= (old_op
& 0x38) << 13;
20177 insn
|= 0x00000c00;
20178 put_thumb32_insn (buf
, insn
);
20179 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20183 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20185 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20188 if (fragp
->fr_var
== 4)
20190 insn
= THUMB_OP32 (opcode
);
20191 insn
|= (old_op
& 0xf0) << 4;
20192 put_thumb32_insn (buf
, insn
);
20193 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20197 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20198 exp
.X_add_number
-= 4;
20206 if (fragp
->fr_var
== 4)
20208 int r0off
= (opcode
== T_MNEM_mov
20209 || opcode
== T_MNEM_movs
) ? 0 : 8;
20210 insn
= THUMB_OP32 (opcode
);
20211 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20212 insn
|= (old_op
& 0x700) << r0off
;
20213 put_thumb32_insn (buf
, insn
);
20214 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20218 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20223 if (fragp
->fr_var
== 4)
20225 insn
= THUMB_OP32(opcode
);
20226 put_thumb32_insn (buf
, insn
);
20227 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20230 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20234 if (fragp
->fr_var
== 4)
20236 insn
= THUMB_OP32(opcode
);
20237 insn
|= (old_op
& 0xf00) << 14;
20238 put_thumb32_insn (buf
, insn
);
20239 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20242 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20245 case T_MNEM_add_sp
:
20246 case T_MNEM_add_pc
:
20247 case T_MNEM_inc_sp
:
20248 case T_MNEM_dec_sp
:
20249 if (fragp
->fr_var
== 4)
20251 /* ??? Choose between add and addw. */
20252 insn
= THUMB_OP32 (opcode
);
20253 insn
|= (old_op
& 0xf0) << 4;
20254 put_thumb32_insn (buf
, insn
);
20255 if (opcode
== T_MNEM_add_pc
)
20256 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20258 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20261 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20269 if (fragp
->fr_var
== 4)
20271 insn
= THUMB_OP32 (opcode
);
20272 insn
|= (old_op
& 0xf0) << 4;
20273 insn
|= (old_op
& 0xf) << 16;
20274 put_thumb32_insn (buf
, insn
);
20275 if (insn
& (1 << 20))
20276 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20278 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20281 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20287 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20288 (enum bfd_reloc_code_real
) reloc_type
);
20289 fixp
->fx_file
= fragp
->fr_file
;
20290 fixp
->fx_line
= fragp
->fr_line
;
20291 fragp
->fr_fix
+= fragp
->fr_var
;
20294 /* Return the size of a relaxable immediate operand instruction.
20295 SHIFT and SIZE specify the form of the allowable immediate. */
20297 relax_immediate (fragS
*fragp
, int size
, int shift
)
20303 /* ??? Should be able to do better than this. */
20304 if (fragp
->fr_symbol
)
20307 low
= (1 << shift
) - 1;
20308 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20309 offset
= fragp
->fr_offset
;
20310 /* Force misaligned offsets to 32-bit variant. */
20313 if (offset
& ~mask
)
20318 /* Get the address of a symbol during relaxation. */
20320 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20326 sym
= fragp
->fr_symbol
;
20327 sym_frag
= symbol_get_frag (sym
);
20328 know (S_GET_SEGMENT (sym
) != absolute_section
20329 || sym_frag
== &zero_address_frag
);
20330 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20332 /* If frag has yet to be reached on this pass, assume it will
20333 move by STRETCH just as we did. If this is not so, it will
20334 be because some frag between grows, and that will force
20338 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20342 /* Adjust stretch for any alignment frag. Note that if have
20343 been expanding the earlier code, the symbol may be
20344 defined in what appears to be an earlier frag. FIXME:
20345 This doesn't handle the fr_subtype field, which specifies
20346 a maximum number of bytes to skip when doing an
20348 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20350 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20353 stretch
= - ((- stretch
)
20354 & ~ ((1 << (int) f
->fr_offset
) - 1));
20356 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20368 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20371 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20376 /* Assume worst case for symbols not known to be in the same section. */
20377 if (fragp
->fr_symbol
== NULL
20378 || !S_IS_DEFINED (fragp
->fr_symbol
)
20379 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20380 || S_IS_WEAK (fragp
->fr_symbol
))
20383 val
= relaxed_symbol_addr (fragp
, stretch
);
20384 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20385 addr
= (addr
+ 4) & ~3;
20386 /* Force misaligned targets to 32-bit variant. */
20390 if (val
< 0 || val
> 1020)
20395 /* Return the size of a relaxable add/sub immediate instruction. */
20397 relax_addsub (fragS
*fragp
, asection
*sec
)
20402 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20403 op
= bfd_get_16(sec
->owner
, buf
);
20404 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20405 return relax_immediate (fragp
, 8, 0);
20407 return relax_immediate (fragp
, 3, 0);
20410 /* Return TRUE iff the definition of symbol S could be pre-empted
20411 (overridden) at link or load time. */
20413 symbol_preemptible (symbolS
*s
)
20415 /* Weak symbols can always be pre-empted. */
20419 /* Non-global symbols cannot be pre-empted. */
20420 if (! S_IS_EXTERNAL (s
))
20424 /* In ELF, a global symbol can be marked protected, or private. In that
20425 case it can't be pre-empted (other definitions in the same link unit
20426 would violate the ODR). */
20427 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20431 /* Other global symbols might be pre-empted. */
20435 /* Return the size of a relaxable branch instruction. BITS is the
20436 size of the offset field in the narrow instruction. */
20439 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20445 /* Assume worst case for symbols not known to be in the same section. */
20446 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20447 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20448 || S_IS_WEAK (fragp
->fr_symbol
))
20452 /* A branch to a function in ARM state will require interworking. */
20453 if (S_IS_DEFINED (fragp
->fr_symbol
)
20454 && ARM_IS_FUNC (fragp
->fr_symbol
))
20458 if (symbol_preemptible (fragp
->fr_symbol
))
20461 val
= relaxed_symbol_addr (fragp
, stretch
);
20462 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20465 /* Offset is a signed value *2 */
20467 if (val
>= limit
|| val
< -limit
)
20473 /* Relax a machine dependent frag. This returns the amount by which
20474 the current size of the frag should change. */
20477 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20482 oldsize
= fragp
->fr_var
;
20483 switch (fragp
->fr_subtype
)
20485 case T_MNEM_ldr_pc2
:
20486 newsize
= relax_adr (fragp
, sec
, stretch
);
20488 case T_MNEM_ldr_pc
:
20489 case T_MNEM_ldr_sp
:
20490 case T_MNEM_str_sp
:
20491 newsize
= relax_immediate (fragp
, 8, 2);
20495 newsize
= relax_immediate (fragp
, 5, 2);
20499 newsize
= relax_immediate (fragp
, 5, 1);
20503 newsize
= relax_immediate (fragp
, 5, 0);
20506 newsize
= relax_adr (fragp
, sec
, stretch
);
20512 newsize
= relax_immediate (fragp
, 8, 0);
20515 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20518 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20520 case T_MNEM_add_sp
:
20521 case T_MNEM_add_pc
:
20522 newsize
= relax_immediate (fragp
, 8, 2);
20524 case T_MNEM_inc_sp
:
20525 case T_MNEM_dec_sp
:
20526 newsize
= relax_immediate (fragp
, 7, 2);
20532 newsize
= relax_addsub (fragp
, sec
);
20538 fragp
->fr_var
= newsize
;
20539 /* Freeze wide instructions that are at or before the same location as
20540 in the previous pass. This avoids infinite loops.
20541 Don't freeze them unconditionally because targets may be artificially
20542 misaligned by the expansion of preceding frags. */
20543 if (stretch
<= 0 && newsize
> 2)
20545 md_convert_frag (sec
->owner
, sec
, fragp
);
20549 return newsize
- oldsize
;
20552 /* Round up a section size to the appropriate boundary. */
20555 md_section_align (segT segment ATTRIBUTE_UNUSED
,
20558 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20559 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
20561 /* For a.out, force the section size to be aligned. If we don't do
20562 this, BFD will align it for us, but it will not write out the
20563 final bytes of the section. This may be a bug in BFD, but it is
20564 easier to fix it here since that is how the other a.out targets
20568 align
= bfd_get_section_alignment (stdoutput
, segment
);
20569 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
20576 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20577 of an rs_align_code fragment. */
20580 arm_handle_align (fragS
* fragP
)
20582 static char const arm_noop
[2][2][4] =
20585 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20586 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20589 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20590 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20593 static char const thumb_noop
[2][2][2] =
20596 {0xc0, 0x46}, /* LE */
20597 {0x46, 0xc0}, /* BE */
20600 {0x00, 0xbf}, /* LE */
20601 {0xbf, 0x00} /* BE */
20604 static char const wide_thumb_noop
[2][4] =
20605 { /* Wide Thumb-2 */
20606 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20607 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20610 unsigned bytes
, fix
, noop_size
;
20613 const char *narrow_noop
= NULL
;
20618 if (fragP
->fr_type
!= rs_align_code
)
20621 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
20622 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
20625 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20626 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
20628 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
20630 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
20632 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
20634 narrow_noop
= thumb_noop
[1][target_big_endian
];
20635 noop
= wide_thumb_noop
[target_big_endian
];
20638 noop
= thumb_noop
[0][target_big_endian
];
20646 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
20647 [target_big_endian
];
20654 fragP
->fr_var
= noop_size
;
20656 if (bytes
& (noop_size
- 1))
20658 fix
= bytes
& (noop_size
- 1);
20660 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
20662 memset (p
, 0, fix
);
20669 if (bytes
& noop_size
)
20671 /* Insert a narrow noop. */
20672 memcpy (p
, narrow_noop
, noop_size
);
20674 bytes
-= noop_size
;
20678 /* Use wide noops for the remainder */
20682 while (bytes
>= noop_size
)
20684 memcpy (p
, noop
, noop_size
);
20686 bytes
-= noop_size
;
20690 fragP
->fr_fix
+= fix
;
20693 /* Called from md_do_align. Used to create an alignment
20694 frag in a code section. */
20697 arm_frag_align_code (int n
, int max
)
20701 /* We assume that there will never be a requirement
20702 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20703 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20708 _("alignments greater than %d bytes not supported in .text sections."),
20709 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
20710 as_fatal ("%s", err_msg
);
20713 p
= frag_var (rs_align_code
,
20714 MAX_MEM_FOR_RS_ALIGN_CODE
,
20716 (relax_substateT
) max
,
20723 /* Perform target specific initialisation of a frag.
20724 Note - despite the name this initialisation is not done when the frag
20725 is created, but only when its type is assigned. A frag can be created
20726 and used a long time before its type is set, so beware of assuming that
20727 this initialisationis performed first. */
20731 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
20733 /* Record whether this frag is in an ARM or a THUMB area. */
20734 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20737 #else /* OBJ_ELF is defined. */
20739 arm_init_frag (fragS
* fragP
, int max_chars
)
20741 /* If the current ARM vs THUMB mode has not already
20742 been recorded into this frag then do so now. */
20743 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
20745 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20747 /* Record a mapping symbol for alignment frags. We will delete this
20748 later if the alignment ends up empty. */
20749 switch (fragP
->fr_type
)
20752 case rs_align_test
:
20754 mapping_state_2 (MAP_DATA
, max_chars
);
20756 case rs_align_code
:
20757 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
20765 /* When we change sections we need to issue a new mapping symbol. */
20768 arm_elf_change_section (void)
20770 /* Link an unlinked unwind index table section to the .text section. */
20771 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
20772 && elf_linked_to_section (now_seg
) == NULL
)
20773 elf_linked_to_section (now_seg
) = text_section
;
20777 arm_elf_section_type (const char * str
, size_t len
)
20779 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
20780 return SHT_ARM_EXIDX
;
20785 /* Code to deal with unwinding tables. */
20787 static void add_unwind_adjustsp (offsetT
);
20789 /* Generate any deferred unwind frame offset. */
20792 flush_pending_unwind (void)
20796 offset
= unwind
.pending_offset
;
20797 unwind
.pending_offset
= 0;
20799 add_unwind_adjustsp (offset
);
20802 /* Add an opcode to this list for this function. Two-byte opcodes should
20803 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20807 add_unwind_opcode (valueT op
, int length
)
20809 /* Add any deferred stack adjustment. */
20810 if (unwind
.pending_offset
)
20811 flush_pending_unwind ();
20813 unwind
.sp_restored
= 0;
20815 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
20817 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
20818 if (unwind
.opcodes
)
20819 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
20820 unwind
.opcode_alloc
);
20822 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
20827 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
20829 unwind
.opcode_count
++;
20833 /* Add unwind opcodes to adjust the stack pointer. */
20836 add_unwind_adjustsp (offsetT offset
)
20840 if (offset
> 0x200)
20842 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20847 /* Long form: 0xb2, uleb128. */
20848 /* This might not fit in a word so add the individual bytes,
20849 remembering the list is built in reverse order. */
20850 o
= (valueT
) ((offset
- 0x204) >> 2);
20852 add_unwind_opcode (0, 1);
20854 /* Calculate the uleb128 encoding of the offset. */
20858 bytes
[n
] = o
& 0x7f;
20864 /* Add the insn. */
20866 add_unwind_opcode (bytes
[n
- 1], 1);
20867 add_unwind_opcode (0xb2, 1);
20869 else if (offset
> 0x100)
20871 /* Two short opcodes. */
20872 add_unwind_opcode (0x3f, 1);
20873 op
= (offset
- 0x104) >> 2;
20874 add_unwind_opcode (op
, 1);
20876 else if (offset
> 0)
20878 /* Short opcode. */
20879 op
= (offset
- 4) >> 2;
20880 add_unwind_opcode (op
, 1);
20882 else if (offset
< 0)
20885 while (offset
> 0x100)
20887 add_unwind_opcode (0x7f, 1);
20890 op
= ((offset
- 4) >> 2) | 0x40;
20891 add_unwind_opcode (op
, 1);
20895 /* Finish the list of unwind opcodes for this function. */
20897 finish_unwind_opcodes (void)
20901 if (unwind
.fp_used
)
20903 /* Adjust sp as necessary. */
20904 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
20905 flush_pending_unwind ();
20907 /* After restoring sp from the frame pointer. */
20908 op
= 0x90 | unwind
.fp_reg
;
20909 add_unwind_opcode (op
, 1);
20912 flush_pending_unwind ();
20916 /* Start an exception table entry. If idx is nonzero this is an index table
20920 start_unwind_section (const segT text_seg
, int idx
)
20922 const char * text_name
;
20923 const char * prefix
;
20924 const char * prefix_once
;
20925 const char * group_name
;
20929 size_t sec_name_len
;
20936 prefix
= ELF_STRING_ARM_unwind
;
20937 prefix_once
= ELF_STRING_ARM_unwind_once
;
20938 type
= SHT_ARM_EXIDX
;
20942 prefix
= ELF_STRING_ARM_unwind_info
;
20943 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
20944 type
= SHT_PROGBITS
;
20947 text_name
= segment_name (text_seg
);
20948 if (streq (text_name
, ".text"))
20951 if (strncmp (text_name
, ".gnu.linkonce.t.",
20952 strlen (".gnu.linkonce.t.")) == 0)
20954 prefix
= prefix_once
;
20955 text_name
+= strlen (".gnu.linkonce.t.");
20958 prefix_len
= strlen (prefix
);
20959 text_len
= strlen (text_name
);
20960 sec_name_len
= prefix_len
+ text_len
;
20961 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
20962 memcpy (sec_name
, prefix
, prefix_len
);
20963 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
20964 sec_name
[prefix_len
+ text_len
] = '\0';
20970 /* Handle COMDAT group. */
20971 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
20973 group_name
= elf_group_name (text_seg
);
20974 if (group_name
== NULL
)
20976 as_bad (_("Group section `%s' has no group signature"),
20977 segment_name (text_seg
));
20978 ignore_rest_of_line ();
20981 flags
|= SHF_GROUP
;
20985 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
20987 /* Set the section link for index tables. */
20989 elf_linked_to_section (now_seg
) = text_seg
;
20993 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20994 personality routine data. Returns zero, or the index table value for
20995 and inline entry. */
20998 create_unwind_entry (int have_data
)
21003 /* The current word of data. */
21005 /* The number of bytes left in this word. */
21008 finish_unwind_opcodes ();
21010 /* Remember the current text section. */
21011 unwind
.saved_seg
= now_seg
;
21012 unwind
.saved_subseg
= now_subseg
;
21014 start_unwind_section (now_seg
, 0);
21016 if (unwind
.personality_routine
== NULL
)
21018 if (unwind
.personality_index
== -2)
21021 as_bad (_("handlerdata in cantunwind frame"));
21022 return 1; /* EXIDX_CANTUNWIND. */
21025 /* Use a default personality routine if none is specified. */
21026 if (unwind
.personality_index
== -1)
21028 if (unwind
.opcode_count
> 3)
21029 unwind
.personality_index
= 1;
21031 unwind
.personality_index
= 0;
21034 /* Space for the personality routine entry. */
21035 if (unwind
.personality_index
== 0)
21037 if (unwind
.opcode_count
> 3)
21038 as_bad (_("too many unwind opcodes for personality routine 0"));
21042 /* All the data is inline in the index table. */
21045 while (unwind
.opcode_count
> 0)
21047 unwind
.opcode_count
--;
21048 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21052 /* Pad with "finish" opcodes. */
21054 data
= (data
<< 8) | 0xb0;
21061 /* We get two opcodes "free" in the first word. */
21062 size
= unwind
.opcode_count
- 2;
21066 gas_assert (unwind
.personality_index
== -1);
21068 /* An extra byte is required for the opcode count. */
21069 size
= unwind
.opcode_count
+ 1;
21072 size
= (size
+ 3) >> 2;
21074 as_bad (_("too many unwind opcodes"));
21076 frag_align (2, 0, 0);
21077 record_alignment (now_seg
, 2);
21078 unwind
.table_entry
= expr_build_dot ();
21080 /* Allocate the table entry. */
21081 ptr
= frag_more ((size
<< 2) + 4);
21082 /* PR 13449: Zero the table entries in case some of them are not used. */
21083 memset (ptr
, 0, (size
<< 2) + 4);
21084 where
= frag_now_fix () - ((size
<< 2) + 4);
21086 switch (unwind
.personality_index
)
21089 /* ??? Should this be a PLT generating relocation? */
21090 /* Custom personality routine. */
21091 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21092 BFD_RELOC_ARM_PREL31
);
21097 /* Set the first byte to the number of additional words. */
21098 data
= size
> 0 ? size
- 1 : 0;
21102 /* ABI defined personality routines. */
21104 /* Three opcodes bytes are packed into the first word. */
21111 /* The size and first two opcode bytes go in the first word. */
21112 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21117 /* Should never happen. */
21121 /* Pack the opcodes into words (MSB first), reversing the list at the same
21123 while (unwind
.opcode_count
> 0)
21127 md_number_to_chars (ptr
, data
, 4);
21132 unwind
.opcode_count
--;
21134 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21137 /* Finish off the last word. */
21140 /* Pad with "finish" opcodes. */
21142 data
= (data
<< 8) | 0xb0;
21144 md_number_to_chars (ptr
, data
, 4);
21149 /* Add an empty descriptor if there is no user-specified data. */
21150 ptr
= frag_more (4);
21151 md_number_to_chars (ptr
, 0, 4);
21158 /* Initialize the DWARF-2 unwind information for this procedure. */
21161 tc_arm_frame_initial_instructions (void)
21163 cfi_add_CFA_def_cfa (REG_SP
, 0);
21165 #endif /* OBJ_ELF */
21167 /* Convert REGNAME to a DWARF-2 register number. */
21170 tc_arm_regname_to_dw2regnum (char *regname
)
21172 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21176 /* PR 16694: Allow VFP registers as well. */
21177 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21181 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21190 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21194 exp
.X_op
= O_secrel
;
21195 exp
.X_add_symbol
= symbol
;
21196 exp
.X_add_number
= 0;
21197 emit_expr (&exp
, size
);
21201 /* MD interface: Symbol and relocation handling. */
21203 /* Return the address within the segment that a PC-relative fixup is
21204 relative to. For ARM, PC-relative fixups applied to instructions
21205 are generally relative to the location of the fixup plus 8 bytes.
21206 Thumb branches are offset by 4, and Thumb loads relative to PC
21207 require special handling. */
21210 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21212 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21214 /* If this is pc-relative and we are going to emit a relocation
21215 then we just want to put out any pipeline compensation that the linker
21216 will need. Otherwise we want to use the calculated base.
21217 For WinCE we skip the bias for externals as well, since this
21218 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21220 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21221 || (arm_force_relocation (fixP
)
21223 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21229 switch (fixP
->fx_r_type
)
21231 /* PC relative addressing on the Thumb is slightly odd as the
21232 bottom two bits of the PC are forced to zero for the
21233 calculation. This happens *after* application of the
21234 pipeline offset. However, Thumb adrl already adjusts for
21235 this, so we need not do it again. */
21236 case BFD_RELOC_ARM_THUMB_ADD
:
21239 case BFD_RELOC_ARM_THUMB_OFFSET
:
21240 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21241 case BFD_RELOC_ARM_T32_ADD_PC12
:
21242 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21243 return (base
+ 4) & ~3;
21245 /* Thumb branches are simply offset by +4. */
21246 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21247 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21248 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21249 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21250 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21253 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21255 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21256 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21257 && ARM_IS_FUNC (fixP
->fx_addsy
)
21258 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21259 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21262 /* BLX is like branches above, but forces the low two bits of PC to
21264 case BFD_RELOC_THUMB_PCREL_BLX
:
21266 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21267 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21268 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21269 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21270 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21271 return (base
+ 4) & ~3;
21273 /* ARM mode branches are offset by +8. However, the Windows CE
21274 loader expects the relocation not to take this into account. */
21275 case BFD_RELOC_ARM_PCREL_BLX
:
21277 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21278 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21279 && ARM_IS_FUNC (fixP
->fx_addsy
)
21280 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21281 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21284 case BFD_RELOC_ARM_PCREL_CALL
:
21286 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21287 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21288 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21289 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21290 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21293 case BFD_RELOC_ARM_PCREL_BRANCH
:
21294 case BFD_RELOC_ARM_PCREL_JUMP
:
21295 case BFD_RELOC_ARM_PLT32
:
21297 /* When handling fixups immediately, because we have already
21298 discovered the value of a symbol, or the address of the frag involved
21299 we must account for the offset by +8, as the OS loader will never see the reloc.
21300 see fixup_segment() in write.c
21301 The S_IS_EXTERNAL test handles the case of global symbols.
21302 Those need the calculated base, not just the pipe compensation the linker will need. */
21304 && fixP
->fx_addsy
!= NULL
21305 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21306 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21314 /* ARM mode loads relative to PC are also offset by +8. Unlike
21315 branches, the Windows CE loader *does* expect the relocation
21316 to take this into account. */
21317 case BFD_RELOC_ARM_OFFSET_IMM
:
21318 case BFD_RELOC_ARM_OFFSET_IMM8
:
21319 case BFD_RELOC_ARM_HWLITERAL
:
21320 case BFD_RELOC_ARM_LITERAL
:
21321 case BFD_RELOC_ARM_CP_OFF_IMM
:
21325 /* Other PC-relative relocations are un-offset. */
21331 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21332 Otherwise we have no need to default values of symbols. */
21335 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21338 if (name
[0] == '_' && name
[1] == 'G'
21339 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21343 if (symbol_find (name
))
21344 as_bad (_("GOT already in the symbol table"));
21346 GOT_symbol
= symbol_new (name
, undefined_section
,
21347 (valueT
) 0, & zero_address_frag
);
21357 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21358 computed as two separate immediate values, added together. We
21359 already know that this value cannot be computed by just one ARM
21362 static unsigned int
21363 validate_immediate_twopart (unsigned int val
,
21364 unsigned int * highpart
)
21369 for (i
= 0; i
< 32; i
+= 2)
21370 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21376 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21378 else if (a
& 0xff0000)
21380 if (a
& 0xff000000)
21382 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21386 gas_assert (a
& 0xff000000);
21387 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21390 return (a
& 0xff) | (i
<< 7);
21397 validate_offset_imm (unsigned int val
, int hwse
)
21399 if ((hwse
&& val
> 255) || val
> 4095)
21404 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21405 negative immediate constant by altering the instruction. A bit of
21410 by inverting the second operand, and
21413 by negating the second operand. */
21416 negate_data_op (unsigned long * instruction
,
21417 unsigned long value
)
21420 unsigned long negated
, inverted
;
21422 negated
= encode_arm_immediate (-value
);
21423 inverted
= encode_arm_immediate (~value
);
21425 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21428 /* First negates. */
21429 case OPCODE_SUB
: /* ADD <-> SUB */
21430 new_inst
= OPCODE_ADD
;
21435 new_inst
= OPCODE_SUB
;
21439 case OPCODE_CMP
: /* CMP <-> CMN */
21440 new_inst
= OPCODE_CMN
;
21445 new_inst
= OPCODE_CMP
;
21449 /* Now Inverted ops. */
21450 case OPCODE_MOV
: /* MOV <-> MVN */
21451 new_inst
= OPCODE_MVN
;
21456 new_inst
= OPCODE_MOV
;
21460 case OPCODE_AND
: /* AND <-> BIC */
21461 new_inst
= OPCODE_BIC
;
21466 new_inst
= OPCODE_AND
;
21470 case OPCODE_ADC
: /* ADC <-> SBC */
21471 new_inst
= OPCODE_SBC
;
21476 new_inst
= OPCODE_ADC
;
21480 /* We cannot do anything. */
21485 if (value
== (unsigned) FAIL
)
21488 *instruction
&= OPCODE_MASK
;
21489 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21493 /* Like negate_data_op, but for Thumb-2. */
21495 static unsigned int
21496 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
21500 unsigned int negated
, inverted
;
21502 negated
= encode_thumb32_immediate (-value
);
21503 inverted
= encode_thumb32_immediate (~value
);
21505 rd
= (*instruction
>> 8) & 0xf;
21506 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
21509 /* ADD <-> SUB. Includes CMP <-> CMN. */
21510 case T2_OPCODE_SUB
:
21511 new_inst
= T2_OPCODE_ADD
;
21515 case T2_OPCODE_ADD
:
21516 new_inst
= T2_OPCODE_SUB
;
21520 /* ORR <-> ORN. Includes MOV <-> MVN. */
21521 case T2_OPCODE_ORR
:
21522 new_inst
= T2_OPCODE_ORN
;
21526 case T2_OPCODE_ORN
:
21527 new_inst
= T2_OPCODE_ORR
;
21531 /* AND <-> BIC. TST has no inverted equivalent. */
21532 case T2_OPCODE_AND
:
21533 new_inst
= T2_OPCODE_BIC
;
21540 case T2_OPCODE_BIC
:
21541 new_inst
= T2_OPCODE_AND
;
21546 case T2_OPCODE_ADC
:
21547 new_inst
= T2_OPCODE_SBC
;
21551 case T2_OPCODE_SBC
:
21552 new_inst
= T2_OPCODE_ADC
;
21556 /* We cannot do anything. */
21561 if (value
== (unsigned int)FAIL
)
21564 *instruction
&= T2_OPCODE_MASK
;
21565 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
21569 /* Read a 32-bit thumb instruction from buf. */
21570 static unsigned long
21571 get_thumb32_insn (char * buf
)
21573 unsigned long insn
;
21574 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
21575 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21581 /* We usually want to set the low bit on the address of thumb function
21582 symbols. In particular .word foo - . should have the low bit set.
21583 Generic code tries to fold the difference of two symbols to
21584 a constant. Prevent this and force a relocation when the first symbols
21585 is a thumb function. */
21588 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
21590 if (op
== O_subtract
21591 && l
->X_op
== O_symbol
21592 && r
->X_op
== O_symbol
21593 && THUMB_IS_FUNC (l
->X_add_symbol
))
21595 l
->X_op
= O_subtract
;
21596 l
->X_op_symbol
= r
->X_add_symbol
;
21597 l
->X_add_number
-= r
->X_add_number
;
21601 /* Process as normal. */
21605 /* Encode Thumb2 unconditional branches and calls. The encoding
21606 for the 2 are identical for the immediate values. */
21609 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
21611 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21614 addressT S
, I1
, I2
, lo
, hi
;
21616 S
= (value
>> 24) & 0x01;
21617 I1
= (value
>> 23) & 0x01;
21618 I2
= (value
>> 22) & 0x01;
21619 hi
= (value
>> 12) & 0x3ff;
21620 lo
= (value
>> 1) & 0x7ff;
21621 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21622 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21623 newval
|= (S
<< 10) | hi
;
21624 newval2
&= ~T2I1I2MASK
;
21625 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
21626 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21627 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21631 md_apply_fix (fixS
* fixP
,
21635 offsetT value
= * valP
;
21637 unsigned int newimm
;
21638 unsigned long temp
;
21640 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
21642 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
21644 /* Note whether this will delete the relocation. */
21646 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
21649 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21650 consistency with the behaviour on 32-bit hosts. Remember value
21652 value
&= 0xffffffff;
21653 value
^= 0x80000000;
21654 value
-= 0x80000000;
21657 fixP
->fx_addnumber
= value
;
21659 /* Same treatment for fixP->fx_offset. */
21660 fixP
->fx_offset
&= 0xffffffff;
21661 fixP
->fx_offset
^= 0x80000000;
21662 fixP
->fx_offset
-= 0x80000000;
21664 switch (fixP
->fx_r_type
)
21666 case BFD_RELOC_NONE
:
21667 /* This will need to go in the object file. */
21671 case BFD_RELOC_ARM_IMMEDIATE
:
21672 /* We claim that this fixup has been processed here,
21673 even if in fact we generate an error because we do
21674 not have a reloc for it, so tc_gen_reloc will reject it. */
21677 if (fixP
->fx_addsy
)
21679 const char *msg
= 0;
21681 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21682 msg
= _("undefined symbol %s used as an immediate value");
21683 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21684 msg
= _("symbol %s is in a different section");
21685 else if (S_IS_WEAK (fixP
->fx_addsy
))
21686 msg
= _("symbol %s is weak and may be overridden later");
21690 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21691 msg
, S_GET_NAME (fixP
->fx_addsy
));
21696 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21698 /* If the offset is negative, we should use encoding A2 for ADR. */
21699 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
21700 newimm
= negate_data_op (&temp
, value
);
21703 newimm
= encode_arm_immediate (value
);
21705 /* If the instruction will fail, see if we can fix things up by
21706 changing the opcode. */
21707 if (newimm
== (unsigned int) FAIL
)
21708 newimm
= negate_data_op (&temp
, value
);
21711 if (newimm
== (unsigned int) FAIL
)
21713 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21714 _("invalid constant (%lx) after fixup"),
21715 (unsigned long) value
);
21719 newimm
|= (temp
& 0xfffff000);
21720 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21723 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21725 unsigned int highpart
= 0;
21726 unsigned int newinsn
= 0xe1a00000; /* nop. */
21728 if (fixP
->fx_addsy
)
21730 const char *msg
= 0;
21732 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21733 msg
= _("undefined symbol %s used as an immediate value");
21734 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21735 msg
= _("symbol %s is in a different section");
21736 else if (S_IS_WEAK (fixP
->fx_addsy
))
21737 msg
= _("symbol %s is weak and may be overridden later");
21741 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21742 msg
, S_GET_NAME (fixP
->fx_addsy
));
21747 newimm
= encode_arm_immediate (value
);
21748 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21750 /* If the instruction will fail, see if we can fix things up by
21751 changing the opcode. */
21752 if (newimm
== (unsigned int) FAIL
21753 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
21755 /* No ? OK - try using two ADD instructions to generate
21757 newimm
= validate_immediate_twopart (value
, & highpart
);
21759 /* Yes - then make sure that the second instruction is
21761 if (newimm
!= (unsigned int) FAIL
)
21763 /* Still No ? Try using a negated value. */
21764 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
21765 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
21766 /* Otherwise - give up. */
21769 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21770 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21775 /* Replace the first operand in the 2nd instruction (which
21776 is the PC) with the destination register. We have
21777 already added in the PC in the first instruction and we
21778 do not want to do it again. */
21779 newinsn
&= ~ 0xf0000;
21780 newinsn
|= ((newinsn
& 0x0f000) << 4);
21783 newimm
|= (temp
& 0xfffff000);
21784 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21786 highpart
|= (newinsn
& 0xfffff000);
21787 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
21791 case BFD_RELOC_ARM_OFFSET_IMM
:
21792 if (!fixP
->fx_done
&& seg
->use_rela_p
)
21795 case BFD_RELOC_ARM_LITERAL
:
21801 if (validate_offset_imm (value
, 0) == FAIL
)
21803 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
21804 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21805 _("invalid literal constant: pool needs to be closer"));
21807 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21808 _("bad immediate value for offset (%ld)"),
21813 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21815 newval
&= 0xfffff000;
21818 newval
&= 0xff7ff000;
21819 newval
|= value
| (sign
? INDEX_UP
: 0);
21821 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21824 case BFD_RELOC_ARM_OFFSET_IMM8
:
21825 case BFD_RELOC_ARM_HWLITERAL
:
21831 if (validate_offset_imm (value
, 1) == FAIL
)
21833 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
21834 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21835 _("invalid literal constant: pool needs to be closer"));
21837 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21838 _("bad immediate value for 8-bit offset (%ld)"),
21843 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21845 newval
&= 0xfffff0f0;
21848 newval
&= 0xff7ff0f0;
21849 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
21851 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21854 case BFD_RELOC_ARM_T32_OFFSET_U8
:
21855 if (value
< 0 || value
> 1020 || value
% 4 != 0)
21856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21857 _("bad immediate value for offset (%ld)"), (long) value
);
21860 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
21862 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
21865 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21866 /* This is a complicated relocation used for all varieties of Thumb32
21867 load/store instruction with immediate offset:
21869 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21870 *4, optional writeback(W)
21871 (doubleword load/store)
21873 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21874 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21875 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21876 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21877 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21879 Uppercase letters indicate bits that are already encoded at
21880 this point. Lowercase letters are our problem. For the
21881 second block of instructions, the secondary opcode nybble
21882 (bits 8..11) is present, and bit 23 is zero, even if this is
21883 a PC-relative operation. */
21884 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21886 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
21888 if ((newval
& 0xf0000000) == 0xe0000000)
21890 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21892 newval
|= (1 << 23);
21895 if (value
% 4 != 0)
21897 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21898 _("offset not a multiple of 4"));
21904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21905 _("offset out of range"));
21910 else if ((newval
& 0x000f0000) == 0x000f0000)
21912 /* PC-relative, 12-bit offset. */
21914 newval
|= (1 << 23);
21919 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21920 _("offset out of range"));
21925 else if ((newval
& 0x00000100) == 0x00000100)
21927 /* Writeback: 8-bit, +/- offset. */
21929 newval
|= (1 << 9);
21934 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21935 _("offset out of range"));
21940 else if ((newval
& 0x00000f00) == 0x00000e00)
21942 /* T-instruction: positive 8-bit offset. */
21943 if (value
< 0 || value
> 0xff)
21945 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21946 _("offset out of range"));
21954 /* Positive 12-bit or negative 8-bit offset. */
21958 newval
|= (1 << 23);
21968 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21969 _("offset out of range"));
21976 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
21977 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
21980 case BFD_RELOC_ARM_SHIFT_IMM
:
21981 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21982 if (((unsigned long) value
) > 32
21984 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
21986 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21987 _("shift expression is too large"));
21992 /* Shifts of zero must be done as lsl. */
21994 else if (value
== 32)
21996 newval
&= 0xfffff07f;
21997 newval
|= (value
& 0x1f) << 7;
21998 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22001 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22002 case BFD_RELOC_ARM_T32_ADD_IMM
:
22003 case BFD_RELOC_ARM_T32_IMM12
:
22004 case BFD_RELOC_ARM_T32_ADD_PC12
:
22005 /* We claim that this fixup has been processed here,
22006 even if in fact we generate an error because we do
22007 not have a reloc for it, so tc_gen_reloc will reject it. */
22011 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22013 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22014 _("undefined symbol %s used as an immediate value"),
22015 S_GET_NAME (fixP
->fx_addsy
));
22019 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22021 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22024 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22025 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22027 newimm
= encode_thumb32_immediate (value
);
22028 if (newimm
== (unsigned int) FAIL
)
22029 newimm
= thumb32_negate_data_op (&newval
, value
);
22031 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22032 && newimm
== (unsigned int) FAIL
)
22034 /* Turn add/sum into addw/subw. */
22035 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22036 newval
= (newval
& 0xfeffffff) | 0x02000000;
22037 /* No flat 12-bit imm encoding for addsw/subsw. */
22038 if ((newval
& 0x00100000) == 0)
22040 /* 12 bit immediate for addw/subw. */
22044 newval
^= 0x00a00000;
22047 newimm
= (unsigned int) FAIL
;
22053 if (newimm
== (unsigned int)FAIL
)
22055 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22056 _("invalid constant (%lx) after fixup"),
22057 (unsigned long) value
);
22061 newval
|= (newimm
& 0x800) << 15;
22062 newval
|= (newimm
& 0x700) << 4;
22063 newval
|= (newimm
& 0x0ff);
22065 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22066 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22069 case BFD_RELOC_ARM_SMC
:
22070 if (((unsigned long) value
) > 0xffff)
22071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22072 _("invalid smc expression"));
22073 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22074 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22075 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22078 case BFD_RELOC_ARM_HVC
:
22079 if (((unsigned long) value
) > 0xffff)
22080 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22081 _("invalid hvc expression"));
22082 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22083 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22084 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22087 case BFD_RELOC_ARM_SWI
:
22088 if (fixP
->tc_fix_data
!= 0)
22090 if (((unsigned long) value
) > 0xff)
22091 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22092 _("invalid swi expression"));
22093 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22095 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22099 if (((unsigned long) value
) > 0x00ffffff)
22100 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22101 _("invalid swi expression"));
22102 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22104 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22108 case BFD_RELOC_ARM_MULTI
:
22109 if (((unsigned long) value
) > 0xffff)
22110 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22111 _("invalid expression in load/store multiple"));
22112 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22113 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22117 case BFD_RELOC_ARM_PCREL_CALL
:
22119 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22121 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22122 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22123 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22124 /* Flip the bl to blx. This is a simple flip
22125 bit here because we generate PCREL_CALL for
22126 unconditional bls. */
22128 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22129 newval
= newval
| 0x10000000;
22130 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22136 goto arm_branch_common
;
22138 case BFD_RELOC_ARM_PCREL_JUMP
:
22139 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22141 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22142 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22143 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22145 /* This would map to a bl<cond>, b<cond>,
22146 b<always> to a Thumb function. We
22147 need to force a relocation for this particular
22149 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22153 case BFD_RELOC_ARM_PLT32
:
22155 case BFD_RELOC_ARM_PCREL_BRANCH
:
22157 goto arm_branch_common
;
22159 case BFD_RELOC_ARM_PCREL_BLX
:
22162 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22164 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22165 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22166 && ARM_IS_FUNC (fixP
->fx_addsy
))
22168 /* Flip the blx to a bl and warn. */
22169 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22170 newval
= 0xeb000000;
22171 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22172 _("blx to '%s' an ARM ISA state function changed to bl"),
22174 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22180 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22181 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22185 /* We are going to store value (shifted right by two) in the
22186 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22187 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22188 also be be clear. */
22190 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22191 _("misaligned branch destination"));
22192 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22193 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22194 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22196 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22198 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22199 newval
|= (value
>> 2) & 0x00ffffff;
22200 /* Set the H bit on BLX instructions. */
22204 newval
|= 0x01000000;
22206 newval
&= ~0x01000000;
22208 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22212 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22213 /* CBZ can only branch forward. */
22215 /* Attempts to use CBZ to branch to the next instruction
22216 (which, strictly speaking, are prohibited) will be turned into
22219 FIXME: It may be better to remove the instruction completely and
22220 perform relaxation. */
22223 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22224 newval
= 0xbf00; /* NOP encoding T1 */
22225 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22230 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22232 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22234 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22235 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22236 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22241 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22242 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22243 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22245 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22247 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22248 newval
|= (value
& 0x1ff) >> 1;
22249 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22253 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22254 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22257 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22259 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22260 newval
|= (value
& 0xfff) >> 1;
22261 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22265 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22267 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22268 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22269 && ARM_IS_FUNC (fixP
->fx_addsy
)
22270 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22272 /* Force a relocation for a branch 20 bits wide. */
22275 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22276 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22277 _("conditional branch out of range"));
22279 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22282 addressT S
, J1
, J2
, lo
, hi
;
22284 S
= (value
& 0x00100000) >> 20;
22285 J2
= (value
& 0x00080000) >> 19;
22286 J1
= (value
& 0x00040000) >> 18;
22287 hi
= (value
& 0x0003f000) >> 12;
22288 lo
= (value
& 0x00000ffe) >> 1;
22290 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22291 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22292 newval
|= (S
<< 10) | hi
;
22293 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22294 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22295 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22299 case BFD_RELOC_THUMB_PCREL_BLX
:
22300 /* If there is a blx from a thumb state function to
22301 another thumb function flip this to a bl and warn
22305 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22306 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22307 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22309 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22310 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22311 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22313 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22314 newval
= newval
| 0x1000;
22315 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22316 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22321 goto thumb_bl_common
;
22323 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22324 /* A bl from Thumb state ISA to an internal ARM state function
22325 is converted to a blx. */
22327 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22328 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22329 && ARM_IS_FUNC (fixP
->fx_addsy
)
22330 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22332 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22333 newval
= newval
& ~0x1000;
22334 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22335 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22341 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22342 /* For a BLX instruction, make sure that the relocation is rounded up
22343 to a word boundary. This follows the semantics of the instruction
22344 which specifies that bit 1 of the target address will come from bit
22345 1 of the base address. */
22346 value
= (value
+ 3) & ~ 3;
22349 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22350 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22351 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22354 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22356 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22357 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22358 else if ((value
& ~0x1ffffff)
22359 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22360 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22361 _("Thumb2 branch out of range"));
22364 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22365 encode_thumb2_b_bl_offset (buf
, value
);
22369 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22370 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22371 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22373 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22374 encode_thumb2_b_bl_offset (buf
, value
);
22379 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22380 md_number_to_chars (buf
, value
, 1);
22384 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22385 md_number_to_chars (buf
, value
, 2);
22389 case BFD_RELOC_ARM_TLS_CALL
:
22390 case BFD_RELOC_ARM_THM_TLS_CALL
:
22391 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22392 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22393 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22396 case BFD_RELOC_ARM_TLS_GOTDESC
:
22397 case BFD_RELOC_ARM_TLS_GD32
:
22398 case BFD_RELOC_ARM_TLS_LE32
:
22399 case BFD_RELOC_ARM_TLS_IE32
:
22400 case BFD_RELOC_ARM_TLS_LDM32
:
22401 case BFD_RELOC_ARM_TLS_LDO32
:
22402 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22405 case BFD_RELOC_ARM_GOT32
:
22406 case BFD_RELOC_ARM_GOTOFF
:
22407 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22408 md_number_to_chars (buf
, 0, 4);
22411 case BFD_RELOC_ARM_GOT_PREL
:
22412 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22413 md_number_to_chars (buf
, value
, 4);
22416 case BFD_RELOC_ARM_TARGET2
:
22417 /* TARGET2 is not partial-inplace, so we need to write the
22418 addend here for REL targets, because it won't be written out
22419 during reloc processing later. */
22420 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22421 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22425 case BFD_RELOC_RVA
:
22427 case BFD_RELOC_ARM_TARGET1
:
22428 case BFD_RELOC_ARM_ROSEGREL32
:
22429 case BFD_RELOC_ARM_SBREL32
:
22430 case BFD_RELOC_32_PCREL
:
22432 case BFD_RELOC_32_SECREL
:
22434 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22436 /* For WinCE we only do this for pcrel fixups. */
22437 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22439 md_number_to_chars (buf
, value
, 4);
22443 case BFD_RELOC_ARM_PREL31
:
22444 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22446 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22447 if ((value
^ (value
>> 1)) & 0x40000000)
22449 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22450 _("rel31 relocation overflow"));
22452 newval
|= value
& 0x7fffffff;
22453 md_number_to_chars (buf
, newval
, 4);
22458 case BFD_RELOC_ARM_CP_OFF_IMM
:
22459 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22460 if (value
< -1023 || value
> 1023 || (value
& 3))
22461 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22462 _("co-processor offset out of range"));
22467 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22468 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22469 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22471 newval
= get_thumb32_insn (buf
);
22473 newval
&= 0xffffff00;
22476 newval
&= 0xff7fff00;
22477 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22479 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22480 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22481 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22483 put_thumb32_insn (buf
, newval
);
22486 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22487 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22488 if (value
< -255 || value
> 255)
22489 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22490 _("co-processor offset out of range"));
22492 goto cp_off_common
;
22494 case BFD_RELOC_ARM_THUMB_OFFSET
:
22495 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22496 /* Exactly what ranges, and where the offset is inserted depends
22497 on the type of instruction, we can establish this from the
22499 switch (newval
>> 12)
22501 case 4: /* PC load. */
22502 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22503 forced to zero for these loads; md_pcrel_from has already
22504 compensated for this. */
22506 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22507 _("invalid offset, target not word aligned (0x%08lX)"),
22508 (((unsigned long) fixP
->fx_frag
->fr_address
22509 + (unsigned long) fixP
->fx_where
) & ~3)
22510 + (unsigned long) value
);
22512 if (value
& ~0x3fc)
22513 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22514 _("invalid offset, value too big (0x%08lX)"),
22517 newval
|= value
>> 2;
22520 case 9: /* SP load/store. */
22521 if (value
& ~0x3fc)
22522 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22523 _("invalid offset, value too big (0x%08lX)"),
22525 newval
|= value
>> 2;
22528 case 6: /* Word load/store. */
22530 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22531 _("invalid offset, value too big (0x%08lX)"),
22533 newval
|= value
<< 4; /* 6 - 2. */
22536 case 7: /* Byte load/store. */
22538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22539 _("invalid offset, value too big (0x%08lX)"),
22541 newval
|= value
<< 6;
22544 case 8: /* Halfword load/store. */
22546 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22547 _("invalid offset, value too big (0x%08lX)"),
22549 newval
|= value
<< 5; /* 6 - 1. */
22553 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22554 "Unable to process relocation for thumb opcode: %lx",
22555 (unsigned long) newval
);
22558 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22561 case BFD_RELOC_ARM_THUMB_ADD
:
22562 /* This is a complicated relocation, since we use it for all of
22563 the following immediate relocations:
22567 9bit ADD/SUB SP word-aligned
22568 10bit ADD PC/SP word-aligned
22570 The type of instruction being processed is encoded in the
22577 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22579 int rd
= (newval
>> 4) & 0xf;
22580 int rs
= newval
& 0xf;
22581 int subtract
= !!(newval
& 0x8000);
22583 /* Check for HI regs, only very restricted cases allowed:
22584 Adjusting SP, and using PC or SP to get an address. */
22585 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
22586 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
22587 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22588 _("invalid Hi register with immediate"));
22590 /* If value is negative, choose the opposite instruction. */
22594 subtract
= !subtract
;
22596 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22597 _("immediate value out of range"));
22602 if (value
& ~0x1fc)
22603 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22604 _("invalid immediate for stack address calculation"));
22605 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
22606 newval
|= value
>> 2;
22608 else if (rs
== REG_PC
|| rs
== REG_SP
)
22610 if (subtract
|| value
& ~0x3fc)
22611 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22612 _("invalid immediate for address calculation (value = 0x%08lX)"),
22613 (unsigned long) value
);
22614 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
22616 newval
|= value
>> 2;
22621 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22622 _("immediate value out of range"));
22623 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
22624 newval
|= (rd
<< 8) | value
;
22629 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22630 _("immediate value out of range"));
22631 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
22632 newval
|= rd
| (rs
<< 3) | (value
<< 6);
22635 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22638 case BFD_RELOC_ARM_THUMB_IMM
:
22639 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22640 if (value
< 0 || value
> 255)
22641 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22642 _("invalid immediate: %ld is out of range"),
22645 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22648 case BFD_RELOC_ARM_THUMB_SHIFT
:
22649 /* 5bit shift value (0..32). LSL cannot take 32. */
22650 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
22651 temp
= newval
& 0xf800;
22652 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
22653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22654 _("invalid shift value: %ld"), (long) value
);
22655 /* Shifts of zero must be encoded as LSL. */
22657 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
22658 /* Shifts of 32 are encoded as zero. */
22659 else if (value
== 32)
22661 newval
|= value
<< 6;
22662 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22665 case BFD_RELOC_VTABLE_INHERIT
:
22666 case BFD_RELOC_VTABLE_ENTRY
:
22670 case BFD_RELOC_ARM_MOVW
:
22671 case BFD_RELOC_ARM_MOVT
:
22672 case BFD_RELOC_ARM_THUMB_MOVW
:
22673 case BFD_RELOC_ARM_THUMB_MOVT
:
22674 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22676 /* REL format relocations are limited to a 16-bit addend. */
22677 if (!fixP
->fx_done
)
22679 if (value
< -0x8000 || value
> 0x7fff)
22680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22681 _("offset out of range"));
22683 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22684 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22689 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22690 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22692 newval
= get_thumb32_insn (buf
);
22693 newval
&= 0xfbf08f00;
22694 newval
|= (value
& 0xf000) << 4;
22695 newval
|= (value
& 0x0800) << 15;
22696 newval
|= (value
& 0x0700) << 4;
22697 newval
|= (value
& 0x00ff);
22698 put_thumb32_insn (buf
, newval
);
22702 newval
= md_chars_to_number (buf
, 4);
22703 newval
&= 0xfff0f000;
22704 newval
|= value
& 0x0fff;
22705 newval
|= (value
& 0xf000) << 4;
22706 md_number_to_chars (buf
, newval
, 4);
22711 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
22712 case BFD_RELOC_ARM_ALU_PC_G0
:
22713 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
22714 case BFD_RELOC_ARM_ALU_PC_G1
:
22715 case BFD_RELOC_ARM_ALU_PC_G2
:
22716 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
22717 case BFD_RELOC_ARM_ALU_SB_G0
:
22718 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
22719 case BFD_RELOC_ARM_ALU_SB_G1
:
22720 case BFD_RELOC_ARM_ALU_SB_G2
:
22721 gas_assert (!fixP
->fx_done
);
22722 if (!seg
->use_rela_p
)
22725 bfd_vma encoded_addend
;
22726 bfd_vma addend_abs
= abs (value
);
22728 /* Check that the absolute value of the addend can be
22729 expressed as an 8-bit constant plus a rotation. */
22730 encoded_addend
= encode_arm_immediate (addend_abs
);
22731 if (encoded_addend
== (unsigned int) FAIL
)
22732 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22733 _("the offset 0x%08lX is not representable"),
22734 (unsigned long) addend_abs
);
22736 /* Extract the instruction. */
22737 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22739 /* If the addend is positive, use an ADD instruction.
22740 Otherwise use a SUB. Take care not to destroy the S bit. */
22741 insn
&= 0xff1fffff;
22747 /* Place the encoded addend into the first 12 bits of the
22749 insn
&= 0xfffff000;
22750 insn
|= encoded_addend
;
22752 /* Update the instruction. */
22753 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22757 case BFD_RELOC_ARM_LDR_PC_G0
:
22758 case BFD_RELOC_ARM_LDR_PC_G1
:
22759 case BFD_RELOC_ARM_LDR_PC_G2
:
22760 case BFD_RELOC_ARM_LDR_SB_G0
:
22761 case BFD_RELOC_ARM_LDR_SB_G1
:
22762 case BFD_RELOC_ARM_LDR_SB_G2
:
22763 gas_assert (!fixP
->fx_done
);
22764 if (!seg
->use_rela_p
)
22767 bfd_vma addend_abs
= abs (value
);
22769 /* Check that the absolute value of the addend can be
22770 encoded in 12 bits. */
22771 if (addend_abs
>= 0x1000)
22772 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22773 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22774 (unsigned long) addend_abs
);
22776 /* Extract the instruction. */
22777 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22779 /* If the addend is negative, clear bit 23 of the instruction.
22780 Otherwise set it. */
22782 insn
&= ~(1 << 23);
22786 /* Place the absolute value of the addend into the first 12 bits
22787 of the instruction. */
22788 insn
&= 0xfffff000;
22789 insn
|= addend_abs
;
22791 /* Update the instruction. */
22792 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22796 case BFD_RELOC_ARM_LDRS_PC_G0
:
22797 case BFD_RELOC_ARM_LDRS_PC_G1
:
22798 case BFD_RELOC_ARM_LDRS_PC_G2
:
22799 case BFD_RELOC_ARM_LDRS_SB_G0
:
22800 case BFD_RELOC_ARM_LDRS_SB_G1
:
22801 case BFD_RELOC_ARM_LDRS_SB_G2
:
22802 gas_assert (!fixP
->fx_done
);
22803 if (!seg
->use_rela_p
)
22806 bfd_vma addend_abs
= abs (value
);
22808 /* Check that the absolute value of the addend can be
22809 encoded in 8 bits. */
22810 if (addend_abs
>= 0x100)
22811 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22812 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22813 (unsigned long) addend_abs
);
22815 /* Extract the instruction. */
22816 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22818 /* If the addend is negative, clear bit 23 of the instruction.
22819 Otherwise set it. */
22821 insn
&= ~(1 << 23);
22825 /* Place the first four bits of the absolute value of the addend
22826 into the first 4 bits of the instruction, and the remaining
22827 four into bits 8 .. 11. */
22828 insn
&= 0xfffff0f0;
22829 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
22831 /* Update the instruction. */
22832 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22836 case BFD_RELOC_ARM_LDC_PC_G0
:
22837 case BFD_RELOC_ARM_LDC_PC_G1
:
22838 case BFD_RELOC_ARM_LDC_PC_G2
:
22839 case BFD_RELOC_ARM_LDC_SB_G0
:
22840 case BFD_RELOC_ARM_LDC_SB_G1
:
22841 case BFD_RELOC_ARM_LDC_SB_G2
:
22842 gas_assert (!fixP
->fx_done
);
22843 if (!seg
->use_rela_p
)
22846 bfd_vma addend_abs
= abs (value
);
22848 /* Check that the absolute value of the addend is a multiple of
22849 four and, when divided by four, fits in 8 bits. */
22850 if (addend_abs
& 0x3)
22851 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22852 _("bad offset 0x%08lX (must be word-aligned)"),
22853 (unsigned long) addend_abs
);
22855 if ((addend_abs
>> 2) > 0xff)
22856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22857 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22858 (unsigned long) addend_abs
);
22860 /* Extract the instruction. */
22861 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22863 /* If the addend is negative, clear bit 23 of the instruction.
22864 Otherwise set it. */
22866 insn
&= ~(1 << 23);
22870 /* Place the addend (divided by four) into the first eight
22871 bits of the instruction. */
22872 insn
&= 0xfffffff0;
22873 insn
|= addend_abs
>> 2;
22875 /* Update the instruction. */
22876 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22880 case BFD_RELOC_ARM_V4BX
:
22881 /* This will need to go in the object file. */
22885 case BFD_RELOC_UNUSED
:
22887 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22888 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
22892 /* Translate internal representation of relocation info to BFD target
22896 tc_gen_reloc (asection
*section
, fixS
*fixp
)
22899 bfd_reloc_code_real_type code
;
22901 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
22903 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
22904 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
22905 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
22907 if (fixp
->fx_pcrel
)
22909 if (section
->use_rela_p
)
22910 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
22912 fixp
->fx_offset
= reloc
->address
;
22914 reloc
->addend
= fixp
->fx_offset
;
22916 switch (fixp
->fx_r_type
)
22919 if (fixp
->fx_pcrel
)
22921 code
= BFD_RELOC_8_PCREL
;
22926 if (fixp
->fx_pcrel
)
22928 code
= BFD_RELOC_16_PCREL
;
22933 if (fixp
->fx_pcrel
)
22935 code
= BFD_RELOC_32_PCREL
;
22939 case BFD_RELOC_ARM_MOVW
:
22940 if (fixp
->fx_pcrel
)
22942 code
= BFD_RELOC_ARM_MOVW_PCREL
;
22946 case BFD_RELOC_ARM_MOVT
:
22947 if (fixp
->fx_pcrel
)
22949 code
= BFD_RELOC_ARM_MOVT_PCREL
;
22953 case BFD_RELOC_ARM_THUMB_MOVW
:
22954 if (fixp
->fx_pcrel
)
22956 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
22960 case BFD_RELOC_ARM_THUMB_MOVT
:
22961 if (fixp
->fx_pcrel
)
22963 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
22967 case BFD_RELOC_NONE
:
22968 case BFD_RELOC_ARM_PCREL_BRANCH
:
22969 case BFD_RELOC_ARM_PCREL_BLX
:
22970 case BFD_RELOC_RVA
:
22971 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22972 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22973 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22974 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22975 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22976 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22977 case BFD_RELOC_VTABLE_ENTRY
:
22978 case BFD_RELOC_VTABLE_INHERIT
:
22980 case BFD_RELOC_32_SECREL
:
22982 code
= fixp
->fx_r_type
;
22985 case BFD_RELOC_THUMB_PCREL_BLX
:
22987 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22988 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22991 code
= BFD_RELOC_THUMB_PCREL_BLX
;
22994 case BFD_RELOC_ARM_LITERAL
:
22995 case BFD_RELOC_ARM_HWLITERAL
:
22996 /* If this is called then the a literal has
22997 been referenced across a section boundary. */
22998 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
22999 _("literal referenced across section boundary"));
23003 case BFD_RELOC_ARM_TLS_CALL
:
23004 case BFD_RELOC_ARM_THM_TLS_CALL
:
23005 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23006 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23007 case BFD_RELOC_ARM_GOT32
:
23008 case BFD_RELOC_ARM_GOTOFF
:
23009 case BFD_RELOC_ARM_GOT_PREL
:
23010 case BFD_RELOC_ARM_PLT32
:
23011 case BFD_RELOC_ARM_TARGET1
:
23012 case BFD_RELOC_ARM_ROSEGREL32
:
23013 case BFD_RELOC_ARM_SBREL32
:
23014 case BFD_RELOC_ARM_PREL31
:
23015 case BFD_RELOC_ARM_TARGET2
:
23016 case BFD_RELOC_ARM_TLS_LE32
:
23017 case BFD_RELOC_ARM_TLS_LDO32
:
23018 case BFD_RELOC_ARM_PCREL_CALL
:
23019 case BFD_RELOC_ARM_PCREL_JUMP
:
23020 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23021 case BFD_RELOC_ARM_ALU_PC_G0
:
23022 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23023 case BFD_RELOC_ARM_ALU_PC_G1
:
23024 case BFD_RELOC_ARM_ALU_PC_G2
:
23025 case BFD_RELOC_ARM_LDR_PC_G0
:
23026 case BFD_RELOC_ARM_LDR_PC_G1
:
23027 case BFD_RELOC_ARM_LDR_PC_G2
:
23028 case BFD_RELOC_ARM_LDRS_PC_G0
:
23029 case BFD_RELOC_ARM_LDRS_PC_G1
:
23030 case BFD_RELOC_ARM_LDRS_PC_G2
:
23031 case BFD_RELOC_ARM_LDC_PC_G0
:
23032 case BFD_RELOC_ARM_LDC_PC_G1
:
23033 case BFD_RELOC_ARM_LDC_PC_G2
:
23034 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23035 case BFD_RELOC_ARM_ALU_SB_G0
:
23036 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23037 case BFD_RELOC_ARM_ALU_SB_G1
:
23038 case BFD_RELOC_ARM_ALU_SB_G2
:
23039 case BFD_RELOC_ARM_LDR_SB_G0
:
23040 case BFD_RELOC_ARM_LDR_SB_G1
:
23041 case BFD_RELOC_ARM_LDR_SB_G2
:
23042 case BFD_RELOC_ARM_LDRS_SB_G0
:
23043 case BFD_RELOC_ARM_LDRS_SB_G1
:
23044 case BFD_RELOC_ARM_LDRS_SB_G2
:
23045 case BFD_RELOC_ARM_LDC_SB_G0
:
23046 case BFD_RELOC_ARM_LDC_SB_G1
:
23047 case BFD_RELOC_ARM_LDC_SB_G2
:
23048 case BFD_RELOC_ARM_V4BX
:
23049 code
= fixp
->fx_r_type
;
23052 case BFD_RELOC_ARM_TLS_GOTDESC
:
23053 case BFD_RELOC_ARM_TLS_GD32
:
23054 case BFD_RELOC_ARM_TLS_IE32
:
23055 case BFD_RELOC_ARM_TLS_LDM32
:
23056 /* BFD will include the symbol's address in the addend.
23057 But we don't want that, so subtract it out again here. */
23058 if (!S_IS_COMMON (fixp
->fx_addsy
))
23059 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23060 code
= fixp
->fx_r_type
;
23064 case BFD_RELOC_ARM_IMMEDIATE
:
23065 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23066 _("internal relocation (type: IMMEDIATE) not fixed up"));
23069 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23070 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23071 _("ADRL used for a symbol not defined in the same file"));
23074 case BFD_RELOC_ARM_OFFSET_IMM
:
23075 if (section
->use_rela_p
)
23077 code
= fixp
->fx_r_type
;
23081 if (fixp
->fx_addsy
!= NULL
23082 && !S_IS_DEFINED (fixp
->fx_addsy
)
23083 && S_IS_LOCAL (fixp
->fx_addsy
))
23085 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23086 _("undefined local label `%s'"),
23087 S_GET_NAME (fixp
->fx_addsy
));
23091 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23092 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23099 switch (fixp
->fx_r_type
)
23101 case BFD_RELOC_NONE
: type
= "NONE"; break;
23102 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23103 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23104 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23105 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23106 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23107 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23108 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23109 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23110 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23111 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23112 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23113 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23114 default: type
= _("<unknown>"); break;
23116 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23117 _("cannot represent %s relocation in this object file format"),
23124 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23126 && fixp
->fx_addsy
== GOT_symbol
)
23128 code
= BFD_RELOC_ARM_GOTPC
;
23129 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23133 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23135 if (reloc
->howto
== NULL
)
23137 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23138 _("cannot represent %s relocation in this object file format"),
23139 bfd_get_reloc_code_name (code
));
23143 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23144 vtable entry to be used in the relocation's section offset. */
23145 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23146 reloc
->address
= fixp
->fx_offset
;
23151 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23154 cons_fix_new_arm (fragS
* frag
,
23159 bfd_reloc_code_real_type type
;
23163 FIXME: @@ Should look at CPU word size. */
23167 type
= BFD_RELOC_8
;
23170 type
= BFD_RELOC_16
;
23174 type
= BFD_RELOC_32
;
23177 type
= BFD_RELOC_64
;
23182 if (exp
->X_op
== O_secrel
)
23184 exp
->X_op
= O_symbol
;
23185 type
= BFD_RELOC_32_SECREL
;
23189 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
23192 #if defined (OBJ_COFF)
23194 arm_validate_fix (fixS
* fixP
)
23196 /* If the destination of the branch is a defined symbol which does not have
23197 the THUMB_FUNC attribute, then we must be calling a function which has
23198 the (interfacearm) attribute. We look for the Thumb entry point to that
23199 function and change the branch to refer to that function instead. */
23200 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23201 && fixP
->fx_addsy
!= NULL
23202 && S_IS_DEFINED (fixP
->fx_addsy
)
23203 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23205 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23212 arm_force_relocation (struct fix
* fixp
)
23214 #if defined (OBJ_COFF) && defined (TE_PE)
23215 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23219 /* In case we have a call or a branch to a function in ARM ISA mode from
23220 a thumb function or vice-versa force the relocation. These relocations
23221 are cleared off for some cores that might have blx and simple transformations
23225 switch (fixp
->fx_r_type
)
23227 case BFD_RELOC_ARM_PCREL_JUMP
:
23228 case BFD_RELOC_ARM_PCREL_CALL
:
23229 case BFD_RELOC_THUMB_PCREL_BLX
:
23230 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23234 case BFD_RELOC_ARM_PCREL_BLX
:
23235 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23236 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23237 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23238 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23247 /* Resolve these relocations even if the symbol is extern or weak.
23248 Technically this is probably wrong due to symbol preemption.
23249 In practice these relocations do not have enough range to be useful
23250 at dynamic link time, and some code (e.g. in the Linux kernel)
23251 expects these references to be resolved. */
23252 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23253 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23254 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23255 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23256 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23257 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23258 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23259 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23260 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23261 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23262 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23263 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23264 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23265 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23268 /* Always leave these relocations for the linker. */
23269 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23270 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23271 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23274 /* Always generate relocations against function symbols. */
23275 if (fixp
->fx_r_type
== BFD_RELOC_32
23277 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23280 return generic_force_reloc (fixp
);
23283 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23284 /* Relocations against function names must be left unadjusted,
23285 so that the linker can use this information to generate interworking
23286 stubs. The MIPS version of this function
23287 also prevents relocations that are mips-16 specific, but I do not
23288 know why it does this.
23291 There is one other problem that ought to be addressed here, but
23292 which currently is not: Taking the address of a label (rather
23293 than a function) and then later jumping to that address. Such
23294 addresses also ought to have their bottom bit set (assuming that
23295 they reside in Thumb code), but at the moment they will not. */
23298 arm_fix_adjustable (fixS
* fixP
)
23300 if (fixP
->fx_addsy
== NULL
)
23303 /* Preserve relocations against symbols with function type. */
23304 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23307 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23308 && fixP
->fx_subsy
== NULL
)
23311 /* We need the symbol name for the VTABLE entries. */
23312 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23313 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23316 /* Don't allow symbols to be discarded on GOT related relocs. */
23317 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23318 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23319 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23320 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23321 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23322 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23323 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23324 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23325 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23326 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23327 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23328 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23329 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23330 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23333 /* Similarly for group relocations. */
23334 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23335 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23336 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23339 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23340 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23341 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23342 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23343 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23344 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23345 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23346 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23347 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23352 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23357 elf32_arm_target_format (void)
23360 return (target_big_endian
23361 ? "elf32-bigarm-symbian"
23362 : "elf32-littlearm-symbian");
23363 #elif defined (TE_VXWORKS)
23364 return (target_big_endian
23365 ? "elf32-bigarm-vxworks"
23366 : "elf32-littlearm-vxworks");
23367 #elif defined (TE_NACL)
23368 return (target_big_endian
23369 ? "elf32-bigarm-nacl"
23370 : "elf32-littlearm-nacl");
23372 if (target_big_endian
)
23373 return "elf32-bigarm";
23375 return "elf32-littlearm";
23380 armelf_frob_symbol (symbolS
* symp
,
23383 elf_frob_symbol (symp
, puntp
);
23387 /* MD interface: Finalization. */
23392 literal_pool
* pool
;
23394 /* Ensure that all the IT blocks are properly closed. */
23395 check_it_blocks_finished ();
23397 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23399 /* Put it at the end of the relevant section. */
23400 subseg_set (pool
->section
, pool
->sub_section
);
23402 arm_elf_change_section ();
23409 /* Remove any excess mapping symbols generated for alignment frags in
23410 SEC. We may have created a mapping symbol before a zero byte
23411 alignment; remove it if there's a mapping symbol after the
23414 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23415 void *dummy ATTRIBUTE_UNUSED
)
23417 segment_info_type
*seginfo
= seg_info (sec
);
23420 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23423 for (fragp
= seginfo
->frchainP
->frch_root
;
23425 fragp
= fragp
->fr_next
)
23427 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23428 fragS
*next
= fragp
->fr_next
;
23430 /* Variable-sized frags have been converted to fixed size by
23431 this point. But if this was variable-sized to start with,
23432 there will be a fixed-size frag after it. So don't handle
23434 if (sym
== NULL
|| next
== NULL
)
23437 if (S_GET_VALUE (sym
) < next
->fr_address
)
23438 /* Not at the end of this frag. */
23440 know (S_GET_VALUE (sym
) == next
->fr_address
);
23444 if (next
->tc_frag_data
.first_map
!= NULL
)
23446 /* Next frag starts with a mapping symbol. Discard this
23448 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23452 if (next
->fr_next
== NULL
)
23454 /* This mapping symbol is at the end of the section. Discard
23456 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23457 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23461 /* As long as we have empty frags without any mapping symbols,
23463 /* If the next frag is non-empty and does not start with a
23464 mapping symbol, then this mapping symbol is required. */
23465 if (next
->fr_address
!= next
->fr_next
->fr_address
)
23468 next
= next
->fr_next
;
23470 while (next
!= NULL
);
23475 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23479 arm_adjust_symtab (void)
23484 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23486 if (ARM_IS_THUMB (sym
))
23488 if (THUMB_IS_FUNC (sym
))
23490 /* Mark the symbol as a Thumb function. */
23491 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
23492 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
23493 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
23495 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
23496 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
23498 as_bad (_("%s: unexpected function type: %d"),
23499 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
23501 else switch (S_GET_STORAGE_CLASS (sym
))
23504 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
23507 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
23510 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
23518 if (ARM_IS_INTERWORK (sym
))
23519 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
23526 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23528 if (ARM_IS_THUMB (sym
))
23530 elf_symbol_type
* elf_sym
;
23532 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
23533 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
23535 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
23536 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
23538 /* If it's a .thumb_func, declare it as so,
23539 otherwise tag label as .code 16. */
23540 if (THUMB_IS_FUNC (sym
))
23541 elf_sym
->internal_elf_sym
.st_target_internal
23542 = ST_BRANCH_TO_THUMB
;
23543 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23544 elf_sym
->internal_elf_sym
.st_info
=
23545 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
23550 /* Remove any overlapping mapping symbols generated by alignment frags. */
23551 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
23552 /* Now do generic ELF adjustments. */
23553 elf_adjust_symtab ();
23557 /* MD interface: Initialization. */
23560 set_constant_flonums (void)
23564 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
23565 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
23569 /* Auto-select Thumb mode if it's the only available instruction set for the
23570 given architecture. */
23573 autoselect_thumb_from_cpu_variant (void)
23575 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23576 opcode_select (16);
23585 if ( (arm_ops_hsh
= hash_new ()) == NULL
23586 || (arm_cond_hsh
= hash_new ()) == NULL
23587 || (arm_shift_hsh
= hash_new ()) == NULL
23588 || (arm_psr_hsh
= hash_new ()) == NULL
23589 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
23590 || (arm_reg_hsh
= hash_new ()) == NULL
23591 || (arm_reloc_hsh
= hash_new ()) == NULL
23592 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
23593 as_fatal (_("virtual memory exhausted"));
23595 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
23596 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
23597 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
23598 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
23599 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
23600 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
23601 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
23602 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
23603 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
23604 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
23605 (void *) (v7m_psrs
+ i
));
23606 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
23607 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
23609 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
23611 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
23612 (void *) (barrier_opt_names
+ i
));
23614 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
23616 struct reloc_entry
* entry
= reloc_names
+ i
;
23618 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
23619 /* This makes encode_branch() use the EABI versions of this relocation. */
23620 entry
->reloc
= BFD_RELOC_UNUSED
;
23622 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
23626 set_constant_flonums ();
23628 /* Set the cpu variant based on the command-line options. We prefer
23629 -mcpu= over -march= if both are set (as for GCC); and we prefer
23630 -mfpu= over any other way of setting the floating point unit.
23631 Use of legacy options with new options are faulted. */
23634 if (mcpu_cpu_opt
|| march_cpu_opt
)
23635 as_bad (_("use of old and new-style options to set CPU type"));
23637 mcpu_cpu_opt
= legacy_cpu
;
23639 else if (!mcpu_cpu_opt
)
23640 mcpu_cpu_opt
= march_cpu_opt
;
23645 as_bad (_("use of old and new-style options to set FPU type"));
23647 mfpu_opt
= legacy_fpu
;
23649 else if (!mfpu_opt
)
23651 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23652 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23653 /* Some environments specify a default FPU. If they don't, infer it
23654 from the processor. */
23656 mfpu_opt
= mcpu_fpu_opt
;
23658 mfpu_opt
= march_fpu_opt
;
23660 mfpu_opt
= &fpu_default
;
23666 if (mcpu_cpu_opt
!= NULL
)
23667 mfpu_opt
= &fpu_default
;
23668 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
23669 mfpu_opt
= &fpu_arch_vfp_v2
;
23671 mfpu_opt
= &fpu_arch_fpa
;
23677 mcpu_cpu_opt
= &cpu_default
;
23678 selected_cpu
= cpu_default
;
23682 selected_cpu
= *mcpu_cpu_opt
;
23684 mcpu_cpu_opt
= &arm_arch_any
;
23687 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23689 autoselect_thumb_from_cpu_variant ();
23691 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
23693 #if defined OBJ_COFF || defined OBJ_ELF
23695 unsigned int flags
= 0;
23697 #if defined OBJ_ELF
23698 flags
= meabi_flags
;
23700 switch (meabi_flags
)
23702 case EF_ARM_EABI_UNKNOWN
:
23704 /* Set the flags in the private structure. */
23705 if (uses_apcs_26
) flags
|= F_APCS26
;
23706 if (support_interwork
) flags
|= F_INTERWORK
;
23707 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
23708 if (pic_code
) flags
|= F_PIC
;
23709 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
23710 flags
|= F_SOFT_FLOAT
;
23712 switch (mfloat_abi_opt
)
23714 case ARM_FLOAT_ABI_SOFT
:
23715 case ARM_FLOAT_ABI_SOFTFP
:
23716 flags
|= F_SOFT_FLOAT
;
23719 case ARM_FLOAT_ABI_HARD
:
23720 if (flags
& F_SOFT_FLOAT
)
23721 as_bad (_("hard-float conflicts with specified fpu"));
23725 /* Using pure-endian doubles (even if soft-float). */
23726 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
23727 flags
|= F_VFP_FLOAT
;
23729 #if defined OBJ_ELF
23730 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
23731 flags
|= EF_ARM_MAVERICK_FLOAT
;
23734 case EF_ARM_EABI_VER4
:
23735 case EF_ARM_EABI_VER5
:
23736 /* No additional flags to set. */
23743 bfd_set_private_flags (stdoutput
, flags
);
23745 /* We have run out flags in the COFF header to encode the
23746 status of ATPCS support, so instead we create a dummy,
23747 empty, debug section called .arm.atpcs. */
23752 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
23756 bfd_set_section_flags
23757 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
23758 bfd_set_section_size (stdoutput
, sec
, 0);
23759 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
23765 /* Record the CPU type as well. */
23766 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
23767 mach
= bfd_mach_arm_iWMMXt2
;
23768 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
23769 mach
= bfd_mach_arm_iWMMXt
;
23770 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
23771 mach
= bfd_mach_arm_XScale
;
23772 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
23773 mach
= bfd_mach_arm_ep9312
;
23774 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
23775 mach
= bfd_mach_arm_5TE
;
23776 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
23778 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
23779 mach
= bfd_mach_arm_5T
;
23781 mach
= bfd_mach_arm_5
;
23783 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
23785 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
23786 mach
= bfd_mach_arm_4T
;
23788 mach
= bfd_mach_arm_4
;
23790 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
23791 mach
= bfd_mach_arm_3M
;
23792 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
23793 mach
= bfd_mach_arm_3
;
23794 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
23795 mach
= bfd_mach_arm_2a
;
23796 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
23797 mach
= bfd_mach_arm_2
;
23799 mach
= bfd_mach_arm_unknown
;
23801 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
23804 /* Command line processing. */
23807 Invocation line includes a switch not recognized by the base assembler.
23808 See if it's a processor-specific option.
23810 This routine is somewhat complicated by the need for backwards
23811 compatibility (since older releases of gcc can't be changed).
23812 The new options try to make the interface as compatible as
23815 New options (supported) are:
23817 -mcpu=<cpu name> Assemble for selected processor
23818 -march=<architecture name> Assemble for selected architecture
23819 -mfpu=<fpu architecture> Assemble for selected FPU.
23820 -EB/-mbig-endian Big-endian
23821 -EL/-mlittle-endian Little-endian
23822 -k Generate PIC code
23823 -mthumb Start in Thumb mode
23824 -mthumb-interwork Code supports ARM/Thumb interworking
23826 -m[no-]warn-deprecated Warn about deprecated features
23828 For now we will also provide support for:
23830 -mapcs-32 32-bit Program counter
23831 -mapcs-26 26-bit Program counter
23832 -macps-float Floats passed in FP registers
23833 -mapcs-reentrant Reentrant code
23835 (sometime these will probably be replaced with -mapcs=<list of options>
23836 and -matpcs=<list of options>)
23838 The remaining options are only supported for back-wards compatibility.
23839 Cpu variants, the arm part is optional:
23840 -m[arm]1 Currently not supported.
23841 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23842 -m[arm]3 Arm 3 processor
23843 -m[arm]6[xx], Arm 6 processors
23844 -m[arm]7[xx][t][[d]m] Arm 7 processors
23845 -m[arm]8[10] Arm 8 processors
23846 -m[arm]9[20][tdmi] Arm 9 processors
23847 -mstrongarm[110[0]] StrongARM processors
23848 -mxscale XScale processors
23849 -m[arm]v[2345[t[e]]] Arm architectures
23850 -mall All (except the ARM1)
23852 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23853 -mfpe-old (No float load/store multiples)
23854 -mvfpxd VFP Single precision
23856 -mno-fpu Disable all floating point instructions
23858 The following CPU names are recognized:
23859 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23860 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23861 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23862 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23863 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23864 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23865 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23869 const char * md_shortopts
= "m:k";
23871 #ifdef ARM_BI_ENDIAN
23872 #define OPTION_EB (OPTION_MD_BASE + 0)
23873 #define OPTION_EL (OPTION_MD_BASE + 1)
23875 #if TARGET_BYTES_BIG_ENDIAN
23876 #define OPTION_EB (OPTION_MD_BASE + 0)
23878 #define OPTION_EL (OPTION_MD_BASE + 1)
23881 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23883 struct option md_longopts
[] =
23886 {"EB", no_argument
, NULL
, OPTION_EB
},
23889 {"EL", no_argument
, NULL
, OPTION_EL
},
23891 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
23892 {NULL
, no_argument
, NULL
, 0}
23895 size_t md_longopts_size
= sizeof (md_longopts
);
23897 struct arm_option_table
23899 char *option
; /* Option name to match. */
23900 char *help
; /* Help information. */
23901 int *var
; /* Variable to change. */
23902 int value
; /* What to change it to. */
23903 char *deprecated
; /* If non-null, print this message. */
23906 struct arm_option_table arm_opts
[] =
23908 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
23909 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
23910 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23911 &support_interwork
, 1, NULL
},
23912 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
23913 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
23914 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
23916 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
23917 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
23918 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
23919 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
23922 /* These are recognized by the assembler, but have no affect on code. */
23923 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
23924 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
23926 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
23927 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23928 &warn_on_deprecated
, 0, NULL
},
23929 {NULL
, NULL
, NULL
, 0, NULL
}
23932 struct arm_legacy_option_table
23934 char *option
; /* Option name to match. */
23935 const arm_feature_set
**var
; /* Variable to change. */
23936 const arm_feature_set value
; /* What to change it to. */
23937 char *deprecated
; /* If non-null, print this message. */
23940 const struct arm_legacy_option_table arm_legacy_opts
[] =
23942 /* DON'T add any new processors to this list -- we want the whole list
23943 to go away... Add them to the processors table instead. */
23944 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23945 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23946 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23947 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23948 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23949 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23950 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23951 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23952 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23953 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23954 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23955 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23956 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23957 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23958 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23959 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23960 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23961 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23962 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23963 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23964 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23965 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23966 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23967 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23968 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23969 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23970 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23971 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23972 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23973 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23974 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23975 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23976 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23977 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23978 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23979 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23980 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23981 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23982 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23983 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23984 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23985 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23986 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23987 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23988 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23989 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23990 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23991 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23992 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23993 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23994 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
23995 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
23996 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
23997 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
23998 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
23999 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24000 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24001 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24002 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24003 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24004 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24005 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24006 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24007 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24008 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24009 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24010 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24011 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24012 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24013 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24014 N_("use -mcpu=strongarm110")},
24015 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24016 N_("use -mcpu=strongarm1100")},
24017 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24018 N_("use -mcpu=strongarm1110")},
24019 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24020 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24021 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24023 /* Architecture variants -- don't add any more to this list either. */
24024 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24025 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24026 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24027 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24028 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24029 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24030 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24031 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24032 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24033 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24034 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24035 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24036 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24037 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24038 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24039 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24040 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24041 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24043 /* Floating point variants -- don't add any more to this list either. */
24044 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24045 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24046 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24047 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24048 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24050 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24053 struct arm_cpu_option_table
24057 const arm_feature_set value
;
24058 /* For some CPUs we assume an FPU unless the user explicitly sets
24060 const arm_feature_set default_fpu
;
24061 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24063 const char *canonical_name
;
24066 /* This list should, at a minimum, contain all the cpu names
24067 recognized by GCC. */
24068 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24069 static const struct arm_cpu_option_table arm_cpus
[] =
24071 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24072 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24073 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24074 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24075 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24076 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24077 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24078 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24079 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24080 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24081 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24082 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24083 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24084 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24085 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24086 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24087 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24088 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24089 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24090 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24091 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24092 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24093 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24094 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24095 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24096 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24097 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24098 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24099 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24100 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24101 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24102 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24103 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24104 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24105 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24106 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24107 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24108 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24109 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24110 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24111 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24112 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24113 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24114 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24115 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24116 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24117 /* For V5 or later processors we default to using VFP; but the user
24118 should really set the FPU type explicitly. */
24119 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24120 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24121 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24122 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24123 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24124 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24125 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24126 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24127 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24128 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24129 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24130 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24131 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24132 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24133 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24134 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24135 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24136 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24137 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24138 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24140 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24141 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24142 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24143 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24144 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24145 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24146 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24147 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24148 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24150 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24151 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24152 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24153 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24154 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24155 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
24156 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
24157 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24158 FPU_NONE
, "Cortex-A5"),
24159 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24161 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24162 ARM_FEATURE (0, FPU_VFP_V3
24163 | FPU_NEON_EXT_V1
),
24165 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24166 ARM_FEATURE (0, FPU_VFP_V3
24167 | FPU_NEON_EXT_V1
),
24169 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24171 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24173 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24175 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24177 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24178 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24180 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24181 FPU_NONE
, "Cortex-R5"),
24182 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24183 FPU_ARCH_VFP_V3D16
,
24185 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24186 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24187 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24188 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24189 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24190 /* ??? XSCALE is really an architecture. */
24191 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24192 /* ??? iwmmxt is not a processor. */
24193 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24194 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24195 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24197 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24198 FPU_ARCH_MAVERICK
, "ARM920T"),
24199 /* Marvell processors. */
24200 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A
| ARM_EXT_MP
| ARM_EXT_SEC
, 0),
24201 FPU_ARCH_VFP_V3D16
, NULL
),
24203 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24207 struct arm_arch_option_table
24211 const arm_feature_set value
;
24212 const arm_feature_set default_fpu
;
24215 /* This list should, at a minimum, contain all the architecture names
24216 recognized by GCC. */
24217 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24218 static const struct arm_arch_option_table arm_archs
[] =
24220 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24221 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24222 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24223 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24224 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24225 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24226 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24227 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24228 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24229 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24230 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24231 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24232 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24233 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24234 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24235 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24236 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24237 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24238 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24239 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24240 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24241 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
24242 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24243 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24244 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24245 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
24246 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24247 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24248 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24249 /* The official spelling of the ARMv7 profile variants is the dashed form.
24250 Accept the non-dashed form for compatibility with old toolchains. */
24251 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24252 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24253 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24254 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24255 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24256 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24257 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24258 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24259 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24260 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24261 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24262 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24263 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24265 #undef ARM_ARCH_OPT
24267 /* ISA extensions in the co-processor and main instruction set space. */
24268 struct arm_option_extension_value_table
24272 const arm_feature_set value
;
24273 const arm_feature_set allowed_archs
;
24276 /* The following table must be in alphabetical order with a NULL last entry.
24278 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24279 static const struct arm_option_extension_value_table arm_extensions
[] =
24281 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE (ARM_EXT_V8
, 0)),
24282 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24283 ARM_FEATURE (ARM_EXT_V8
, 0)),
24284 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
,
24285 ARM_FEATURE (ARM_EXT_V8
, 0)),
24286 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
24287 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24288 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
),
24289 ARM_EXT_OPT ("iwmmxt2",
24290 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
),
24291 ARM_EXT_OPT ("maverick",
24292 ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
),
24293 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP
, 0),
24294 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24295 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24296 ARM_FEATURE (ARM_EXT_V8
, 0)),
24297 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS
, 0),
24298 ARM_FEATURE (ARM_EXT_V6M
, 0)),
24299 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
24300 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)),
24301 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
24303 ARM_FEATURE (ARM_EXT_V7A
, 0)),
24304 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
),
24305 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24309 /* ISA floating-point and Advanced SIMD extensions. */
24310 struct arm_option_fpu_value_table
24313 const arm_feature_set value
;
24316 /* This list should, at a minimum, contain all the fpu names
24317 recognized by GCC. */
24318 static const struct arm_option_fpu_value_table arm_fpus
[] =
24320 {"softfpa", FPU_NONE
},
24321 {"fpe", FPU_ARCH_FPE
},
24322 {"fpe2", FPU_ARCH_FPE
},
24323 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24324 {"fpa", FPU_ARCH_FPA
},
24325 {"fpa10", FPU_ARCH_FPA
},
24326 {"fpa11", FPU_ARCH_FPA
},
24327 {"arm7500fe", FPU_ARCH_FPA
},
24328 {"softvfp", FPU_ARCH_VFP
},
24329 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24330 {"vfp", FPU_ARCH_VFP_V2
},
24331 {"vfp9", FPU_ARCH_VFP_V2
},
24332 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24333 {"vfp10", FPU_ARCH_VFP_V2
},
24334 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24335 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24336 {"vfpv2", FPU_ARCH_VFP_V2
},
24337 {"vfpv3", FPU_ARCH_VFP_V3
},
24338 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24339 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24340 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24341 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24342 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24343 {"arm1020t", FPU_ARCH_VFP_V1
},
24344 {"arm1020e", FPU_ARCH_VFP_V2
},
24345 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24346 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24347 {"maverick", FPU_ARCH_MAVERICK
},
24348 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24349 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24350 {"vfpv4", FPU_ARCH_VFP_V4
},
24351 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24352 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24353 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24354 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24355 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24356 {"crypto-neon-fp-armv8",
24357 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24358 {NULL
, ARM_ARCH_NONE
}
24361 struct arm_option_value_table
24367 static const struct arm_option_value_table arm_float_abis
[] =
24369 {"hard", ARM_FLOAT_ABI_HARD
},
24370 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24371 {"soft", ARM_FLOAT_ABI_SOFT
},
24376 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24377 static const struct arm_option_value_table arm_eabis
[] =
24379 {"gnu", EF_ARM_EABI_UNKNOWN
},
24380 {"4", EF_ARM_EABI_VER4
},
24381 {"5", EF_ARM_EABI_VER5
},
24386 struct arm_long_option_table
24388 char * option
; /* Substring to match. */
24389 char * help
; /* Help information. */
24390 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24391 char * deprecated
; /* If non-null, print this message. */
24395 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24397 arm_feature_set
*ext_set
= (arm_feature_set
*)
24398 xmalloc (sizeof (arm_feature_set
));
24400 /* We insist on extensions being specified in alphabetical order, and with
24401 extensions being added before being removed. We achieve this by having
24402 the global ARM_EXTENSIONS table in alphabetical order, and using the
24403 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24404 or removing it (0) and only allowing it to change in the order
24406 const struct arm_option_extension_value_table
* opt
= NULL
;
24407 int adding_value
= -1;
24409 /* Copy the feature set, so that we can modify it. */
24410 *ext_set
= **opt_p
;
24413 while (str
!= NULL
&& *str
!= 0)
24420 as_bad (_("invalid architectural extension"));
24425 ext
= strchr (str
, '+');
24430 len
= strlen (str
);
24432 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
24434 if (adding_value
!= 0)
24437 opt
= arm_extensions
;
24445 if (adding_value
== -1)
24448 opt
= arm_extensions
;
24450 else if (adding_value
!= 1)
24452 as_bad (_("must specify extensions to add before specifying "
24453 "those to remove"));
24460 as_bad (_("missing architectural extension"));
24464 gas_assert (adding_value
!= -1);
24465 gas_assert (opt
!= NULL
);
24467 /* Scan over the options table trying to find an exact match. */
24468 for (; opt
->name
!= NULL
; opt
++)
24469 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24471 /* Check we can apply the extension to this architecture. */
24472 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
24474 as_bad (_("extension does not apply to the base architecture"));
24478 /* Add or remove the extension. */
24480 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
24482 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
24487 if (opt
->name
== NULL
)
24489 /* Did we fail to find an extension because it wasn't specified in
24490 alphabetical order, or because it does not exist? */
24492 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24493 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24496 if (opt
->name
== NULL
)
24497 as_bad (_("unknown architectural extension `%s'"), str
);
24499 as_bad (_("architectural extensions must be specified in "
24500 "alphabetical order"));
24506 /* We should skip the extension we've just matched the next time
24518 arm_parse_cpu (char *str
)
24520 const struct arm_cpu_option_table
*opt
;
24521 char *ext
= strchr (str
, '+');
24527 len
= strlen (str
);
24531 as_bad (_("missing cpu name `%s'"), str
);
24535 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
24536 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24538 mcpu_cpu_opt
= &opt
->value
;
24539 mcpu_fpu_opt
= &opt
->default_fpu
;
24540 if (opt
->canonical_name
)
24541 strcpy (selected_cpu_name
, opt
->canonical_name
);
24546 for (i
= 0; i
< len
; i
++)
24547 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24548 selected_cpu_name
[i
] = 0;
24552 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
24557 as_bad (_("unknown cpu `%s'"), str
);
24562 arm_parse_arch (char *str
)
24564 const struct arm_arch_option_table
*opt
;
24565 char *ext
= strchr (str
, '+');
24571 len
= strlen (str
);
24575 as_bad (_("missing architecture name `%s'"), str
);
24579 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
24580 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24582 march_cpu_opt
= &opt
->value
;
24583 march_fpu_opt
= &opt
->default_fpu
;
24584 strcpy (selected_cpu_name
, opt
->name
);
24587 return arm_parse_extension (ext
, &march_cpu_opt
);
24592 as_bad (_("unknown architecture `%s'\n"), str
);
24597 arm_parse_fpu (char * str
)
24599 const struct arm_option_fpu_value_table
* opt
;
24601 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24602 if (streq (opt
->name
, str
))
24604 mfpu_opt
= &opt
->value
;
24608 as_bad (_("unknown floating point format `%s'\n"), str
);
24613 arm_parse_float_abi (char * str
)
24615 const struct arm_option_value_table
* opt
;
24617 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
24618 if (streq (opt
->name
, str
))
24620 mfloat_abi_opt
= opt
->value
;
24624 as_bad (_("unknown floating point abi `%s'\n"), str
);
24630 arm_parse_eabi (char * str
)
24632 const struct arm_option_value_table
*opt
;
24634 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
24635 if (streq (opt
->name
, str
))
24637 meabi_flags
= opt
->value
;
24640 as_bad (_("unknown EABI `%s'\n"), str
);
24646 arm_parse_it_mode (char * str
)
24648 bfd_boolean ret
= TRUE
;
24650 if (streq ("arm", str
))
24651 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
24652 else if (streq ("thumb", str
))
24653 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
24654 else if (streq ("always", str
))
24655 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
24656 else if (streq ("never", str
))
24657 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
24660 as_bad (_("unknown implicit IT mode `%s', should be "\
24661 "arm, thumb, always, or never."), str
);
24669 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
24671 codecomposer_syntax
= TRUE
;
24672 arm_comment_chars
[0] = ';';
24673 arm_line_separator_chars
[0] = 0;
24677 struct arm_long_option_table arm_long_opts
[] =
24679 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24680 arm_parse_cpu
, NULL
},
24681 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24682 arm_parse_arch
, NULL
},
24683 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24684 arm_parse_fpu
, NULL
},
24685 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24686 arm_parse_float_abi
, NULL
},
24688 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24689 arm_parse_eabi
, NULL
},
24691 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24692 arm_parse_it_mode
, NULL
},
24693 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
24694 arm_ccs_mode
, NULL
},
24695 {NULL
, NULL
, 0, NULL
}
24699 md_parse_option (int c
, char * arg
)
24701 struct arm_option_table
*opt
;
24702 const struct arm_legacy_option_table
*fopt
;
24703 struct arm_long_option_table
*lopt
;
24709 target_big_endian
= 1;
24715 target_big_endian
= 0;
24719 case OPTION_FIX_V4BX
:
24724 /* Listing option. Just ignore these, we don't support additional
24729 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
24731 if (c
== opt
->option
[0]
24732 && ((arg
== NULL
&& opt
->option
[1] == 0)
24733 || streq (arg
, opt
->option
+ 1)))
24735 /* If the option is deprecated, tell the user. */
24736 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
24737 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
24738 arg
? arg
: "", _(opt
->deprecated
));
24740 if (opt
->var
!= NULL
)
24741 *opt
->var
= opt
->value
;
24747 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
24749 if (c
== fopt
->option
[0]
24750 && ((arg
== NULL
&& fopt
->option
[1] == 0)
24751 || streq (arg
, fopt
->option
+ 1)))
24753 /* If the option is deprecated, tell the user. */
24754 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
24755 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
24756 arg
? arg
: "", _(fopt
->deprecated
));
24758 if (fopt
->var
!= NULL
)
24759 *fopt
->var
= &fopt
->value
;
24765 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
24767 /* These options are expected to have an argument. */
24768 if (c
== lopt
->option
[0]
24770 && strncmp (arg
, lopt
->option
+ 1,
24771 strlen (lopt
->option
+ 1)) == 0)
24773 /* If the option is deprecated, tell the user. */
24774 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
24775 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
24776 _(lopt
->deprecated
));
24778 /* Call the sup-option parser. */
24779 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
24790 md_show_usage (FILE * fp
)
24792 struct arm_option_table
*opt
;
24793 struct arm_long_option_table
*lopt
;
24795 fprintf (fp
, _(" ARM-specific assembler options:\n"));
24797 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
24798 if (opt
->help
!= NULL
)
24799 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
24801 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
24802 if (lopt
->help
!= NULL
)
24803 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
24807 -EB assemble code for a big-endian cpu\n"));
24812 -EL assemble code for a little-endian cpu\n"));
24816 --fix-v4bx Allow BX in ARMv4 code\n"));
24824 arm_feature_set flags
;
24825 } cpu_arch_ver_table
;
24827 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24828 least features first. */
24829 static const cpu_arch_ver_table cpu_arch_ver
[] =
24835 {4, ARM_ARCH_V5TE
},
24836 {5, ARM_ARCH_V5TEJ
},
24840 {11, ARM_ARCH_V6M
},
24841 {12, ARM_ARCH_V6SM
},
24842 {8, ARM_ARCH_V6T2
},
24843 {10, ARM_ARCH_V7VE
},
24844 {10, ARM_ARCH_V7R
},
24845 {10, ARM_ARCH_V7M
},
24846 {14, ARM_ARCH_V8A
},
24850 /* Set an attribute if it has not already been set by the user. */
24852 aeabi_set_attribute_int (int tag
, int value
)
24855 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24856 || !attributes_set_explicitly
[tag
])
24857 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
24861 aeabi_set_attribute_string (int tag
, const char *value
)
24864 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24865 || !attributes_set_explicitly
[tag
])
24866 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
24869 /* Set the public EABI object attributes. */
24871 aeabi_set_public_attributes (void)
24876 int fp16_optional
= 0;
24877 arm_feature_set flags
;
24878 arm_feature_set tmp
;
24879 const cpu_arch_ver_table
*p
;
24881 /* Choose the architecture based on the capabilities of the requested cpu
24882 (if any) and/or the instructions actually used. */
24883 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
24884 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
24885 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
24887 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
24888 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
24890 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
24891 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
24893 /* Allow the user to override the reported architecture. */
24896 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
24897 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
24900 /* We need to make sure that the attributes do not identify us as v6S-M
24901 when the only v6S-M feature in use is the Operating System Extensions. */
24902 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
24903 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
24904 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
24908 for (p
= cpu_arch_ver
; p
->val
; p
++)
24910 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
24913 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
24917 /* The table lookup above finds the last architecture to contribute
24918 a new feature. Unfortunately, Tag13 is a subset of the union of
24919 v6T2 and v7-M, so it is never seen as contributing a new feature.
24920 We can not search for the last entry which is entirely used,
24921 because if no CPU is specified we build up only those flags
24922 actually used. Perhaps we should separate out the specified
24923 and implicit cases. Avoid taking this path for -march=all by
24924 checking for contradictory v7-A / v7-M features. */
24926 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
24927 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
24928 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
24931 /* Tag_CPU_name. */
24932 if (selected_cpu_name
[0])
24936 q
= selected_cpu_name
;
24937 if (strncmp (q
, "armv", 4) == 0)
24942 for (i
= 0; q
[i
]; i
++)
24943 q
[i
] = TOUPPER (q
[i
]);
24945 aeabi_set_attribute_string (Tag_CPU_name
, q
);
24948 /* Tag_CPU_arch. */
24949 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
24951 /* Tag_CPU_arch_profile. */
24952 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
24954 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
24956 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
24961 if (profile
!= '\0')
24962 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
24964 /* Tag_ARM_ISA_use. */
24965 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
24967 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
24969 /* Tag_THUMB_ISA_use. */
24970 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
24972 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
24973 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
24975 /* Tag_VFP_arch. */
24976 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8
))
24977 aeabi_set_attribute_int (Tag_VFP_arch
, 7);
24978 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
24979 aeabi_set_attribute_int (Tag_VFP_arch
,
24980 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
24982 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
24985 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
24987 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
24989 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
24992 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
24993 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
24994 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
24995 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
24996 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
24998 /* Tag_ABI_HardFP_use. */
24999 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25000 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25001 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25003 /* Tag_WMMX_arch. */
25004 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25005 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25006 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25007 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25009 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25010 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25011 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25012 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25014 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25016 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25020 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25025 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25026 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25027 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25031 We set Tag_DIV_use to two when integer divide instructions have been used
25032 in ARM state, or when Thumb integer divide instructions have been used,
25033 but we have no architecture profile set, nor have we any ARM instructions.
25035 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25038 For new architectures we will have to check these tests. */
25039 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25040 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25041 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25042 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25043 || (profile
== '\0'
25044 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25045 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25046 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25048 /* Tag_MP_extension_use. */
25049 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25050 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25052 /* Tag Virtualization_use. */
25053 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25055 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25058 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25061 /* Add the default contents for the .ARM.attributes section. */
25065 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25068 aeabi_set_public_attributes ();
25070 #endif /* OBJ_ELF */
25073 /* Parse a .cpu directive. */
25076 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25078 const struct arm_cpu_option_table
*opt
;
25082 name
= input_line_pointer
;
25083 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25084 input_line_pointer
++;
25085 saved_char
= *input_line_pointer
;
25086 *input_line_pointer
= 0;
25088 /* Skip the first "all" entry. */
25089 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25090 if (streq (opt
->name
, name
))
25092 mcpu_cpu_opt
= &opt
->value
;
25093 selected_cpu
= opt
->value
;
25094 if (opt
->canonical_name
)
25095 strcpy (selected_cpu_name
, opt
->canonical_name
);
25099 for (i
= 0; opt
->name
[i
]; i
++)
25100 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25102 selected_cpu_name
[i
] = 0;
25104 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25105 *input_line_pointer
= saved_char
;
25106 demand_empty_rest_of_line ();
25109 as_bad (_("unknown cpu `%s'"), name
);
25110 *input_line_pointer
= saved_char
;
25111 ignore_rest_of_line ();
25115 /* Parse a .arch directive. */
25118 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25120 const struct arm_arch_option_table
*opt
;
25124 name
= input_line_pointer
;
25125 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25126 input_line_pointer
++;
25127 saved_char
= *input_line_pointer
;
25128 *input_line_pointer
= 0;
25130 /* Skip the first "all" entry. */
25131 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25132 if (streq (opt
->name
, name
))
25134 mcpu_cpu_opt
= &opt
->value
;
25135 selected_cpu
= opt
->value
;
25136 strcpy (selected_cpu_name
, opt
->name
);
25137 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25138 *input_line_pointer
= saved_char
;
25139 demand_empty_rest_of_line ();
25143 as_bad (_("unknown architecture `%s'\n"), name
);
25144 *input_line_pointer
= saved_char
;
25145 ignore_rest_of_line ();
25149 /* Parse a .object_arch directive. */
25152 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25154 const struct arm_arch_option_table
*opt
;
25158 name
= input_line_pointer
;
25159 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25160 input_line_pointer
++;
25161 saved_char
= *input_line_pointer
;
25162 *input_line_pointer
= 0;
25164 /* Skip the first "all" entry. */
25165 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25166 if (streq (opt
->name
, name
))
25168 object_arch
= &opt
->value
;
25169 *input_line_pointer
= saved_char
;
25170 demand_empty_rest_of_line ();
25174 as_bad (_("unknown architecture `%s'\n"), name
);
25175 *input_line_pointer
= saved_char
;
25176 ignore_rest_of_line ();
25179 /* Parse a .arch_extension directive. */
25182 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25184 const struct arm_option_extension_value_table
*opt
;
25187 int adding_value
= 1;
25189 name
= input_line_pointer
;
25190 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25191 input_line_pointer
++;
25192 saved_char
= *input_line_pointer
;
25193 *input_line_pointer
= 0;
25195 if (strlen (name
) >= 2
25196 && strncmp (name
, "no", 2) == 0)
25202 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25203 if (streq (opt
->name
, name
))
25205 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25207 as_bad (_("architectural extension `%s' is not allowed for the "
25208 "current base architecture"), name
);
25213 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
25215 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
25217 mcpu_cpu_opt
= &selected_cpu
;
25218 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25219 *input_line_pointer
= saved_char
;
25220 demand_empty_rest_of_line ();
25224 if (opt
->name
== NULL
)
25225 as_bad (_("unknown architecture extension `%s'\n"), name
);
25227 *input_line_pointer
= saved_char
;
25228 ignore_rest_of_line ();
25231 /* Parse a .fpu directive. */
25234 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25236 const struct arm_option_fpu_value_table
*opt
;
25240 name
= input_line_pointer
;
25241 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25242 input_line_pointer
++;
25243 saved_char
= *input_line_pointer
;
25244 *input_line_pointer
= 0;
25246 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25247 if (streq (opt
->name
, name
))
25249 mfpu_opt
= &opt
->value
;
25250 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25251 *input_line_pointer
= saved_char
;
25252 demand_empty_rest_of_line ();
25256 as_bad (_("unknown floating point format `%s'\n"), name
);
25257 *input_line_pointer
= saved_char
;
25258 ignore_rest_of_line ();
25261 /* Copy symbol information. */
25264 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25266 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25270 /* Given a symbolic attribute NAME, return the proper integer value.
25271 Returns -1 if the attribute is not known. */
25274 arm_convert_symbolic_attribute (const char *name
)
25276 static const struct
25281 attribute_table
[] =
25283 /* When you modify this table you should
25284 also modify the list in doc/c-arm.texi. */
25285 #define T(tag) {#tag, tag}
25286 T (Tag_CPU_raw_name
),
25289 T (Tag_CPU_arch_profile
),
25290 T (Tag_ARM_ISA_use
),
25291 T (Tag_THUMB_ISA_use
),
25295 T (Tag_Advanced_SIMD_arch
),
25296 T (Tag_PCS_config
),
25297 T (Tag_ABI_PCS_R9_use
),
25298 T (Tag_ABI_PCS_RW_data
),
25299 T (Tag_ABI_PCS_RO_data
),
25300 T (Tag_ABI_PCS_GOT_use
),
25301 T (Tag_ABI_PCS_wchar_t
),
25302 T (Tag_ABI_FP_rounding
),
25303 T (Tag_ABI_FP_denormal
),
25304 T (Tag_ABI_FP_exceptions
),
25305 T (Tag_ABI_FP_user_exceptions
),
25306 T (Tag_ABI_FP_number_model
),
25307 T (Tag_ABI_align_needed
),
25308 T (Tag_ABI_align8_needed
),
25309 T (Tag_ABI_align_preserved
),
25310 T (Tag_ABI_align8_preserved
),
25311 T (Tag_ABI_enum_size
),
25312 T (Tag_ABI_HardFP_use
),
25313 T (Tag_ABI_VFP_args
),
25314 T (Tag_ABI_WMMX_args
),
25315 T (Tag_ABI_optimization_goals
),
25316 T (Tag_ABI_FP_optimization_goals
),
25317 T (Tag_compatibility
),
25318 T (Tag_CPU_unaligned_access
),
25319 T (Tag_FP_HP_extension
),
25320 T (Tag_VFP_HP_extension
),
25321 T (Tag_ABI_FP_16bit_format
),
25322 T (Tag_MPextension_use
),
25324 T (Tag_nodefaults
),
25325 T (Tag_also_compatible_with
),
25326 T (Tag_conformance
),
25328 T (Tag_Virtualization_use
),
25329 /* We deliberately do not include Tag_MPextension_use_legacy. */
25337 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25338 if (streq (name
, attribute_table
[i
].name
))
25339 return attribute_table
[i
].tag
;
25345 /* Apply sym value for relocations only in the case that
25346 they are for local symbols and you have the respective
25347 architectural feature for blx and simple switches. */
25349 arm_apply_sym_value (struct fix
* fixP
)
25352 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25353 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25355 switch (fixP
->fx_r_type
)
25357 case BFD_RELOC_ARM_PCREL_BLX
:
25358 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25359 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25363 case BFD_RELOC_ARM_PCREL_CALL
:
25364 case BFD_RELOC_THUMB_PCREL_BLX
:
25365 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25376 #endif /* OBJ_ELF */