1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2016 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
);
189 static const arm_feature_set arm_ext_v6_notm
=
190 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
191 static const arm_feature_set arm_ext_v6_dsp
=
192 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
193 static const arm_feature_set arm_ext_barrier
=
194 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
195 static const arm_feature_set arm_ext_msr
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
197 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
198 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
199 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
200 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
201 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
202 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
203 static const arm_feature_set arm_ext_m
=
204 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, ARM_EXT2_V8M
);
205 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
206 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
207 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
208 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
209 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
210 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
211 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
212 static const arm_feature_set arm_ext_v6t2_v8m
=
213 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
214 /* Instructions shared between ARMv8-A and ARMv8-M. */
215 static const arm_feature_set arm_ext_atomics
=
216 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
217 static const arm_feature_set arm_ext_v8_2
=
218 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
219 /* FP16 instructions. */
220 static const arm_feature_set arm_ext_fp16
=
221 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
223 static const arm_feature_set arm_arch_any
= ARM_ANY
;
224 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1, -1);
225 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
226 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
227 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
229 static const arm_feature_set arm_cext_iwmmxt2
=
230 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
231 static const arm_feature_set arm_cext_iwmmxt
=
232 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
233 static const arm_feature_set arm_cext_xscale
=
234 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
235 static const arm_feature_set arm_cext_maverick
=
236 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
237 static const arm_feature_set fpu_fpa_ext_v1
=
238 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
239 static const arm_feature_set fpu_fpa_ext_v2
=
240 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
241 static const arm_feature_set fpu_vfp_ext_v1xd
=
242 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
243 static const arm_feature_set fpu_vfp_ext_v1
=
244 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
245 static const arm_feature_set fpu_vfp_ext_v2
=
246 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
247 static const arm_feature_set fpu_vfp_ext_v3xd
=
248 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
249 static const arm_feature_set fpu_vfp_ext_v3
=
250 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
251 static const arm_feature_set fpu_vfp_ext_d32
=
252 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
253 static const arm_feature_set fpu_neon_ext_v1
=
254 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
255 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
256 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
257 static const arm_feature_set fpu_vfp_fp16
=
258 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
259 static const arm_feature_set fpu_neon_ext_fma
=
260 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
261 static const arm_feature_set fpu_vfp_ext_fma
=
262 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
263 static const arm_feature_set fpu_vfp_ext_armv8
=
264 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
265 static const arm_feature_set fpu_vfp_ext_armv8xd
=
266 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
267 static const arm_feature_set fpu_neon_ext_armv8
=
268 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
269 static const arm_feature_set fpu_crypto_ext_armv8
=
270 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
271 static const arm_feature_set crc_ext_armv8
=
272 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
273 static const arm_feature_set fpu_neon_ext_v8_1
=
274 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
276 static int mfloat_abi_opt
= -1;
277 /* Record user cpu selection for object attributes. */
278 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
279 /* Must be long enough to hold any of the names in arm_cpus. */
280 static char selected_cpu_name
[20];
282 extern FLONUM_TYPE generic_floating_point_number
;
284 /* Return if no cpu was selected on command-line. */
286 no_cpu_selected (void)
288 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
293 static int meabi_flags
= EABI_DEFAULT
;
295 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
298 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
303 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
308 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
309 symbolS
* GOT_symbol
;
312 /* 0: assemble for ARM,
313 1: assemble for Thumb,
314 2: assemble for Thumb even though target CPU does not support thumb
316 static int thumb_mode
= 0;
317 /* A value distinct from the possible values for thumb_mode that we
318 can use to record whether thumb_mode has been copied into the
319 tc_frag_data field of a frag. */
320 #define MODE_RECORDED (1 << 4)
322 /* Specifies the intrinsic IT insn behavior mode. */
323 enum implicit_it_mode
325 IMPLICIT_IT_MODE_NEVER
= 0x00,
326 IMPLICIT_IT_MODE_ARM
= 0x01,
327 IMPLICIT_IT_MODE_THUMB
= 0x02,
328 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
330 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
332 /* If unified_syntax is true, we are processing the new unified
333 ARM/Thumb syntax. Important differences from the old ARM mode:
335 - Immediate operands do not require a # prefix.
336 - Conditional affixes always appear at the end of the
337 instruction. (For backward compatibility, those instructions
338 that formerly had them in the middle, continue to accept them
340 - The IT instruction may appear, and if it does is validated
341 against subsequent conditional affixes. It does not generate
344 Important differences from the old Thumb mode:
346 - Immediate operands do not require a # prefix.
347 - Most of the V6T2 instructions are only available in unified mode.
348 - The .N and .W suffixes are recognized and honored (it is an error
349 if they cannot be honored).
350 - All instructions set the flags if and only if they have an 's' affix.
351 - Conditional affixes may be used. They are validated against
352 preceding IT instructions. Unlike ARM mode, you cannot use a
353 conditional affix except in the scope of an IT instruction. */
355 static bfd_boolean unified_syntax
= FALSE
;
357 /* An immediate operand can start with #, and ld*, st*, pld operands
358 can contain [ and ]. We need to tell APP not to elide whitespace
359 before a [, which can appear as the first operand for pld.
360 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
361 const char arm_symbol_chars
[] = "#[]{}";
376 enum neon_el_type type
;
380 #define NEON_MAX_TYPE_ELS 4
384 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
388 enum it_instruction_type
393 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
394 if inside, should be the last one. */
395 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
396 i.e. BKPT and NOP. */
397 IT_INSN
/* The IT insn has been parsed. */
400 /* The maximum number of operands we need. */
401 #define ARM_IT_MAX_OPERANDS 6
406 unsigned long instruction
;
410 /* "uncond_value" is set to the value in place of the conditional field in
411 unconditional versions of the instruction, or -1 if nothing is
414 struct neon_type vectype
;
415 /* This does not indicate an actual NEON instruction, only that
416 the mnemonic accepts neon-style type suffixes. */
418 /* Set to the opcode if the instruction needs relaxation.
419 Zero if the instruction is not relaxed. */
423 bfd_reloc_code_real_type type
;
428 enum it_instruction_type it_insn_type
;
434 struct neon_type_el vectype
;
435 unsigned present
: 1; /* Operand present. */
436 unsigned isreg
: 1; /* Operand was a register. */
437 unsigned immisreg
: 1; /* .imm field is a second register. */
438 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
439 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
440 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
441 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
442 instructions. This allows us to disambiguate ARM <-> vector insns. */
443 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
444 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
445 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
446 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
447 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
448 unsigned writeback
: 1; /* Operand has trailing ! */
449 unsigned preind
: 1; /* Preindexed address. */
450 unsigned postind
: 1; /* Postindexed address. */
451 unsigned negative
: 1; /* Index register was negated. */
452 unsigned shifted
: 1; /* Shift applied to operation. */
453 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
454 } operands
[ARM_IT_MAX_OPERANDS
];
457 static struct arm_it inst
;
459 #define NUM_FLOAT_VALS 8
461 const char * fp_const
[] =
463 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
466 /* Number of littlenums required to hold an extended precision number. */
467 #define MAX_LITTLENUMS 6
469 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
479 #define CP_T_X 0x00008000
480 #define CP_T_Y 0x00400000
482 #define CONDS_BIT 0x00100000
483 #define LOAD_BIT 0x00100000
485 #define DOUBLE_LOAD_FLAG 0x00000001
489 const char * template_name
;
493 #define COND_ALWAYS 0xE
497 const char * template_name
;
501 struct asm_barrier_opt
503 const char * template_name
;
505 const arm_feature_set arch
;
508 /* The bit that distinguishes CPSR and SPSR. */
509 #define SPSR_BIT (1 << 22)
511 /* The individual PSR flag bits. */
512 #define PSR_c (1 << 16)
513 #define PSR_x (1 << 17)
514 #define PSR_s (1 << 18)
515 #define PSR_f (1 << 19)
520 bfd_reloc_code_real_type reloc
;
525 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
526 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
531 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
534 /* Bits for DEFINED field in neon_typed_alias. */
535 #define NTA_HASTYPE 1
536 #define NTA_HASINDEX 2
538 struct neon_typed_alias
540 unsigned char defined
;
542 struct neon_type_el eltype
;
545 /* ARM register categories. This includes coprocessor numbers and various
546 architecture extensions' registers. */
573 /* Structure for a hash table entry for a register.
574 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
575 information which states whether a vector type or index is specified (for a
576 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
582 unsigned char builtin
;
583 struct neon_typed_alias
* neon
;
586 /* Diagnostics used when we don't get a register of the expected type. */
587 const char * const reg_expected_msgs
[] =
589 N_("ARM register expected"),
590 N_("bad or missing co-processor number"),
591 N_("co-processor register expected"),
592 N_("FPA register expected"),
593 N_("VFP single precision register expected"),
594 N_("VFP/Neon double precision register expected"),
595 N_("Neon quad precision register expected"),
596 N_("VFP single or double precision register expected"),
597 N_("Neon double or quad precision register expected"),
598 N_("VFP single, double or Neon quad precision register expected"),
599 N_("VFP system register expected"),
600 N_("Maverick MVF register expected"),
601 N_("Maverick MVD register expected"),
602 N_("Maverick MVFX register expected"),
603 N_("Maverick MVDX register expected"),
604 N_("Maverick MVAX register expected"),
605 N_("Maverick DSPSC register expected"),
606 N_("iWMMXt data register expected"),
607 N_("iWMMXt control register expected"),
608 N_("iWMMXt scalar register expected"),
609 N_("XScale accumulator register expected"),
612 /* Some well known registers that we refer to directly elsewhere. */
618 /* ARM instructions take 4bytes in the object file, Thumb instructions
624 /* Basic string to match. */
625 const char * template_name
;
627 /* Parameters to instruction. */
628 unsigned int operands
[8];
630 /* Conditional tag - see opcode_lookup. */
631 unsigned int tag
: 4;
633 /* Basic instruction code. */
634 unsigned int avalue
: 28;
636 /* Thumb-format instruction code. */
639 /* Which architecture variant provides this instruction. */
640 const arm_feature_set
* avariant
;
641 const arm_feature_set
* tvariant
;
643 /* Function to call to encode instruction in ARM format. */
644 void (* aencode
) (void);
646 /* Function to call to encode instruction in Thumb format. */
647 void (* tencode
) (void);
650 /* Defines for various bits that we will want to toggle. */
651 #define INST_IMMEDIATE 0x02000000
652 #define OFFSET_REG 0x02000000
653 #define HWOFFSET_IMM 0x00400000
654 #define SHIFT_BY_REG 0x00000010
655 #define PRE_INDEX 0x01000000
656 #define INDEX_UP 0x00800000
657 #define WRITE_BACK 0x00200000
658 #define LDM_TYPE_2_OR_3 0x00400000
659 #define CPSI_MMOD 0x00020000
661 #define LITERAL_MASK 0xf000f000
662 #define OPCODE_MASK 0xfe1fffff
663 #define V4_STR_BIT 0x00000020
664 #define VLDR_VMOV_SAME 0x0040f000
666 #define T2_SUBS_PC_LR 0xf3de8f00
668 #define DATA_OP_SHIFT 21
670 #define T2_OPCODE_MASK 0xfe1fffff
671 #define T2_DATA_OP_SHIFT 21
673 #define A_COND_MASK 0xf0000000
674 #define A_PUSH_POP_OP_MASK 0x0fff0000
676 /* Opcodes for pushing/poping registers to/from the stack. */
677 #define A1_OPCODE_PUSH 0x092d0000
678 #define A2_OPCODE_PUSH 0x052d0004
679 #define A2_OPCODE_POP 0x049d0004
681 /* Codes to distinguish the arithmetic instructions. */
692 #define OPCODE_CMP 10
693 #define OPCODE_CMN 11
694 #define OPCODE_ORR 12
695 #define OPCODE_MOV 13
696 #define OPCODE_BIC 14
697 #define OPCODE_MVN 15
699 #define T2_OPCODE_AND 0
700 #define T2_OPCODE_BIC 1
701 #define T2_OPCODE_ORR 2
702 #define T2_OPCODE_ORN 3
703 #define T2_OPCODE_EOR 4
704 #define T2_OPCODE_ADD 8
705 #define T2_OPCODE_ADC 10
706 #define T2_OPCODE_SBC 11
707 #define T2_OPCODE_SUB 13
708 #define T2_OPCODE_RSB 14
710 #define T_OPCODE_MUL 0x4340
711 #define T_OPCODE_TST 0x4200
712 #define T_OPCODE_CMN 0x42c0
713 #define T_OPCODE_NEG 0x4240
714 #define T_OPCODE_MVN 0x43c0
716 #define T_OPCODE_ADD_R3 0x1800
717 #define T_OPCODE_SUB_R3 0x1a00
718 #define T_OPCODE_ADD_HI 0x4400
719 #define T_OPCODE_ADD_ST 0xb000
720 #define T_OPCODE_SUB_ST 0xb080
721 #define T_OPCODE_ADD_SP 0xa800
722 #define T_OPCODE_ADD_PC 0xa000
723 #define T_OPCODE_ADD_I8 0x3000
724 #define T_OPCODE_SUB_I8 0x3800
725 #define T_OPCODE_ADD_I3 0x1c00
726 #define T_OPCODE_SUB_I3 0x1e00
728 #define T_OPCODE_ASR_R 0x4100
729 #define T_OPCODE_LSL_R 0x4080
730 #define T_OPCODE_LSR_R 0x40c0
731 #define T_OPCODE_ROR_R 0x41c0
732 #define T_OPCODE_ASR_I 0x1000
733 #define T_OPCODE_LSL_I 0x0000
734 #define T_OPCODE_LSR_I 0x0800
736 #define T_OPCODE_MOV_I8 0x2000
737 #define T_OPCODE_CMP_I8 0x2800
738 #define T_OPCODE_CMP_LR 0x4280
739 #define T_OPCODE_MOV_HR 0x4600
740 #define T_OPCODE_CMP_HR 0x4500
742 #define T_OPCODE_LDR_PC 0x4800
743 #define T_OPCODE_LDR_SP 0x9800
744 #define T_OPCODE_STR_SP 0x9000
745 #define T_OPCODE_LDR_IW 0x6800
746 #define T_OPCODE_STR_IW 0x6000
747 #define T_OPCODE_LDR_IH 0x8800
748 #define T_OPCODE_STR_IH 0x8000
749 #define T_OPCODE_LDR_IB 0x7800
750 #define T_OPCODE_STR_IB 0x7000
751 #define T_OPCODE_LDR_RW 0x5800
752 #define T_OPCODE_STR_RW 0x5000
753 #define T_OPCODE_LDR_RH 0x5a00
754 #define T_OPCODE_STR_RH 0x5200
755 #define T_OPCODE_LDR_RB 0x5c00
756 #define T_OPCODE_STR_RB 0x5400
758 #define T_OPCODE_PUSH 0xb400
759 #define T_OPCODE_POP 0xbc00
761 #define T_OPCODE_BRANCH 0xe000
763 #define THUMB_SIZE 2 /* Size of thumb instruction. */
764 #define THUMB_PP_PC_LR 0x0100
765 #define THUMB_LOAD_BIT 0x0800
766 #define THUMB2_LOAD_BIT 0x00100000
768 #define BAD_ARGS _("bad arguments to instruction")
769 #define BAD_SP _("r13 not allowed here")
770 #define BAD_PC _("r15 not allowed here")
771 #define BAD_COND _("instruction cannot be conditional")
772 #define BAD_OVERLAP _("registers may not be the same")
773 #define BAD_HIREG _("lo register required")
774 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
775 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
776 #define BAD_BRANCH _("branch must be last instruction in IT block")
777 #define BAD_NOT_IT _("instruction not allowed in IT block")
778 #define BAD_FPU _("selected FPU does not support instruction")
779 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
780 #define BAD_IT_COND _("incorrect condition in IT block")
781 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
782 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
783 #define BAD_PC_ADDRESSING \
784 _("cannot use register index with PC-relative addressing")
785 #define BAD_PC_WRITEBACK \
786 _("cannot use writeback with PC-relative addressing")
787 #define BAD_RANGE _("branch out of range")
788 #define BAD_FP16 _("selected processor does not support fp16 instruction")
789 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
790 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
792 static struct hash_control
* arm_ops_hsh
;
793 static struct hash_control
* arm_cond_hsh
;
794 static struct hash_control
* arm_shift_hsh
;
795 static struct hash_control
* arm_psr_hsh
;
796 static struct hash_control
* arm_v7m_psr_hsh
;
797 static struct hash_control
* arm_reg_hsh
;
798 static struct hash_control
* arm_reloc_hsh
;
799 static struct hash_control
* arm_barrier_opt_hsh
;
801 /* Stuff needed to resolve the label ambiguity
810 symbolS
* last_label_seen
;
811 static int label_is_thumb_function_name
= FALSE
;
813 /* Literal pool structure. Held on a per-section
814 and per-sub-section basis. */
816 #define MAX_LITERAL_POOL_SIZE 1024
817 typedef struct literal_pool
819 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
820 unsigned int next_free_entry
;
826 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
828 struct literal_pool
* next
;
829 unsigned int alignment
;
832 /* Pointer to a linked list of literal pools. */
833 literal_pool
* list_of_pools
= NULL
;
835 typedef enum asmfunc_states
838 WAITING_ASMFUNC_NAME
,
842 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
845 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
847 static struct current_it now_it
;
851 now_it_compatible (int cond
)
853 return (cond
& ~1) == (now_it
.cc
& ~1);
857 conditional_insn (void)
859 return inst
.cond
!= COND_ALWAYS
;
862 static int in_it_block (void);
864 static int handle_it_state (void);
866 static void force_automatic_it_block_close (void);
868 static void it_fsm_post_encode (void);
870 #define set_it_insn_type(type) \
873 inst.it_insn_type = type; \
874 if (handle_it_state () == FAIL) \
879 #define set_it_insn_type_nonvoid(type, failret) \
882 inst.it_insn_type = type; \
883 if (handle_it_state () == FAIL) \
888 #define set_it_insn_type_last() \
891 if (inst.cond == COND_ALWAYS) \
892 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
894 set_it_insn_type (INSIDE_IT_LAST_INSN); \
900 /* This array holds the chars that always start a comment. If the
901 pre-processor is disabled, these aren't very useful. */
902 char arm_comment_chars
[] = "@";
904 /* This array holds the chars that only start a comment at the beginning of
905 a line. If the line seems to have the form '# 123 filename'
906 .line and .file directives will appear in the pre-processed output. */
907 /* Note that input_file.c hand checks for '#' at the beginning of the
908 first line of the input file. This is because the compiler outputs
909 #NO_APP at the beginning of its output. */
910 /* Also note that comments like this one will always work. */
911 const char line_comment_chars
[] = "#";
913 char arm_line_separator_chars
[] = ";";
915 /* Chars that can be used to separate mant
916 from exp in floating point numbers. */
917 const char EXP_CHARS
[] = "eE";
919 /* Chars that mean this number is a floating point constant. */
923 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
925 /* Prefix characters that indicate the start of an immediate
927 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
929 /* Separator character handling. */
931 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
934 skip_past_char (char ** str
, char c
)
936 /* PR gas/14987: Allow for whitespace before the expected character. */
937 skip_whitespace (*str
);
948 #define skip_past_comma(str) skip_past_char (str, ',')
950 /* Arithmetic expressions (possibly involving symbols). */
952 /* Return TRUE if anything in the expression is a bignum. */
955 walk_no_bignums (symbolS
* sp
)
957 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
960 if (symbol_get_value_expression (sp
)->X_add_symbol
)
962 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
963 || (symbol_get_value_expression (sp
)->X_op_symbol
964 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
970 static int in_my_get_expression
= 0;
972 /* Third argument to my_get_expression. */
973 #define GE_NO_PREFIX 0
974 #define GE_IMM_PREFIX 1
975 #define GE_OPT_PREFIX 2
976 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
977 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
978 #define GE_OPT_PREFIX_BIG 3
981 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
986 /* In unified syntax, all prefixes are optional. */
988 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
993 case GE_NO_PREFIX
: break;
995 if (!is_immediate_prefix (**str
))
997 inst
.error
= _("immediate expression requires a # prefix");
1003 case GE_OPT_PREFIX_BIG
:
1004 if (is_immediate_prefix (**str
))
1010 memset (ep
, 0, sizeof (expressionS
));
1012 save_in
= input_line_pointer
;
1013 input_line_pointer
= *str
;
1014 in_my_get_expression
= 1;
1015 seg
= expression (ep
);
1016 in_my_get_expression
= 0;
1018 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1020 /* We found a bad or missing expression in md_operand(). */
1021 *str
= input_line_pointer
;
1022 input_line_pointer
= save_in
;
1023 if (inst
.error
== NULL
)
1024 inst
.error
= (ep
->X_op
== O_absent
1025 ? _("missing expression") :_("bad expression"));
1030 if (seg
!= absolute_section
1031 && seg
!= text_section
1032 && seg
!= data_section
1033 && seg
!= bss_section
1034 && seg
!= undefined_section
)
1036 inst
.error
= _("bad segment");
1037 *str
= input_line_pointer
;
1038 input_line_pointer
= save_in
;
1045 /* Get rid of any bignums now, so that we don't generate an error for which
1046 we can't establish a line number later on. Big numbers are never valid
1047 in instructions, which is where this routine is always called. */
1048 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1049 && (ep
->X_op
== O_big
1050 || (ep
->X_add_symbol
1051 && (walk_no_bignums (ep
->X_add_symbol
)
1053 && walk_no_bignums (ep
->X_op_symbol
))))))
1055 inst
.error
= _("invalid constant");
1056 *str
= input_line_pointer
;
1057 input_line_pointer
= save_in
;
1061 *str
= input_line_pointer
;
1062 input_line_pointer
= save_in
;
1066 /* Turn a string in input_line_pointer into a floating point constant
1067 of type TYPE, and store the appropriate bytes in *LITP. The number
1068 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1069 returned, or NULL on OK.
1071 Note that fp constants aren't represent in the normal way on the ARM.
1072 In big endian mode, things are as expected. However, in little endian
1073 mode fp constants are big-endian word-wise, and little-endian byte-wise
1074 within the words. For example, (double) 1.1 in big endian mode is
1075 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1076 the byte sequence 99 99 f1 3f 9a 99 99 99.
1078 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1081 md_atof (int type
, char * litP
, int * sizeP
)
1084 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1116 return _("Unrecognized or unsupported floating point constant");
1119 t
= atof_ieee (input_line_pointer
, type
, words
);
1121 input_line_pointer
= t
;
1122 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1124 if (target_big_endian
)
1126 for (i
= 0; i
< prec
; i
++)
1128 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1129 litP
+= sizeof (LITTLENUM_TYPE
);
1134 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1135 for (i
= prec
- 1; i
>= 0; i
--)
1137 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1138 litP
+= sizeof (LITTLENUM_TYPE
);
1141 /* For a 4 byte float the order of elements in `words' is 1 0.
1142 For an 8 byte float the order is 1 0 3 2. */
1143 for (i
= 0; i
< prec
; i
+= 2)
1145 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1146 sizeof (LITTLENUM_TYPE
));
1147 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1148 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1149 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1156 /* We handle all bad expressions here, so that we can report the faulty
1157 instruction in the error message. */
1159 md_operand (expressionS
* exp
)
1161 if (in_my_get_expression
)
1162 exp
->X_op
= O_illegal
;
1165 /* Immediate values. */
1167 /* Generic immediate-value read function for use in directives.
1168 Accepts anything that 'expression' can fold to a constant.
1169 *val receives the number. */
1172 immediate_for_directive (int *val
)
1175 exp
.X_op
= O_illegal
;
1177 if (is_immediate_prefix (*input_line_pointer
))
1179 input_line_pointer
++;
1183 if (exp
.X_op
!= O_constant
)
1185 as_bad (_("expected #constant"));
1186 ignore_rest_of_line ();
1189 *val
= exp
.X_add_number
;
1194 /* Register parsing. */
1196 /* Generic register parser. CCP points to what should be the
1197 beginning of a register name. If it is indeed a valid register
1198 name, advance CCP over it and return the reg_entry structure;
1199 otherwise return NULL. Does not issue diagnostics. */
1201 static struct reg_entry
*
1202 arm_reg_parse_multi (char **ccp
)
1206 struct reg_entry
*reg
;
1208 skip_whitespace (start
);
1210 #ifdef REGISTER_PREFIX
1211 if (*start
!= REGISTER_PREFIX
)
1215 #ifdef OPTIONAL_REGISTER_PREFIX
1216 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1221 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1226 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1228 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1238 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1239 enum arm_reg_type type
)
1241 /* Alternative syntaxes are accepted for a few register classes. */
1248 /* Generic coprocessor register names are allowed for these. */
1249 if (reg
&& reg
->type
== REG_TYPE_CN
)
1254 /* For backward compatibility, a bare number is valid here. */
1256 unsigned long processor
= strtoul (start
, ccp
, 10);
1257 if (*ccp
!= start
&& processor
<= 15)
1261 case REG_TYPE_MMXWC
:
1262 /* WC includes WCG. ??? I'm not sure this is true for all
1263 instructions that take WC registers. */
1264 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1275 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1276 return value is the register number or FAIL. */
1279 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1282 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1285 /* Do not allow a scalar (reg+index) to parse as a register. */
1286 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1289 if (reg
&& reg
->type
== type
)
1292 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1299 /* Parse a Neon type specifier. *STR should point at the leading '.'
1300 character. Does no verification at this stage that the type fits the opcode
1307 Can all be legally parsed by this function.
1309 Fills in neon_type struct pointer with parsed information, and updates STR
1310 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1311 type, FAIL if not. */
1314 parse_neon_type (struct neon_type
*type
, char **str
)
1321 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1323 enum neon_el_type thistype
= NT_untyped
;
1324 unsigned thissize
= -1u;
1331 /* Just a size without an explicit type. */
1335 switch (TOLOWER (*ptr
))
1337 case 'i': thistype
= NT_integer
; break;
1338 case 'f': thistype
= NT_float
; break;
1339 case 'p': thistype
= NT_poly
; break;
1340 case 's': thistype
= NT_signed
; break;
1341 case 'u': thistype
= NT_unsigned
; break;
1343 thistype
= NT_float
;
1348 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1354 /* .f is an abbreviation for .f32. */
1355 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1360 thissize
= strtoul (ptr
, &ptr
, 10);
1362 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1365 as_bad (_("bad size %d in type specifier"), thissize
);
1373 type
->el
[type
->elems
].type
= thistype
;
1374 type
->el
[type
->elems
].size
= thissize
;
1379 /* Empty/missing type is not a successful parse. */
1380 if (type
->elems
== 0)
1388 /* Errors may be set multiple times during parsing or bit encoding
1389 (particularly in the Neon bits), but usually the earliest error which is set
1390 will be the most meaningful. Avoid overwriting it with later (cascading)
1391 errors by calling this function. */
1394 first_error (const char *err
)
1400 /* Parse a single type, e.g. ".s32", leading period included. */
1402 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1405 struct neon_type optype
;
1409 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1411 if (optype
.elems
== 1)
1412 *vectype
= optype
.el
[0];
1415 first_error (_("only one type should be specified for operand"));
1421 first_error (_("vector type expected"));
1433 /* Special meanings for indices (which have a range of 0-7), which will fit into
1436 #define NEON_ALL_LANES 15
1437 #define NEON_INTERLEAVE_LANES 14
1439 /* Parse either a register or a scalar, with an optional type. Return the
1440 register number, and optionally fill in the actual type of the register
1441 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1442 type/index information in *TYPEINFO. */
1445 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1446 enum arm_reg_type
*rtype
,
1447 struct neon_typed_alias
*typeinfo
)
1450 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1451 struct neon_typed_alias atype
;
1452 struct neon_type_el parsetype
;
1456 atype
.eltype
.type
= NT_invtype
;
1457 atype
.eltype
.size
= -1;
1459 /* Try alternate syntax for some types of register. Note these are mutually
1460 exclusive with the Neon syntax extensions. */
1463 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1471 /* Undo polymorphism when a set of register types may be accepted. */
1472 if ((type
== REG_TYPE_NDQ
1473 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1474 || (type
== REG_TYPE_VFSD
1475 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1476 || (type
== REG_TYPE_NSDQ
1477 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1478 || reg
->type
== REG_TYPE_NQ
))
1479 || (type
== REG_TYPE_MMXWC
1480 && (reg
->type
== REG_TYPE_MMXWCG
)))
1481 type
= (enum arm_reg_type
) reg
->type
;
1483 if (type
!= reg
->type
)
1489 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1491 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1493 first_error (_("can't redefine type for operand"));
1496 atype
.defined
|= NTA_HASTYPE
;
1497 atype
.eltype
= parsetype
;
1500 if (skip_past_char (&str
, '[') == SUCCESS
)
1502 if (type
!= REG_TYPE_VFD
)
1504 first_error (_("only D registers may be indexed"));
1508 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1510 first_error (_("can't change index for operand"));
1514 atype
.defined
|= NTA_HASINDEX
;
1516 if (skip_past_char (&str
, ']') == SUCCESS
)
1517 atype
.index
= NEON_ALL_LANES
;
1522 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1524 if (exp
.X_op
!= O_constant
)
1526 first_error (_("constant expression required"));
1530 if (skip_past_char (&str
, ']') == FAIL
)
1533 atype
.index
= exp
.X_add_number
;
1548 /* Like arm_reg_parse, but allow allow the following extra features:
1549 - If RTYPE is non-zero, return the (possibly restricted) type of the
1550 register (e.g. Neon double or quad reg when either has been requested).
1551 - If this is a Neon vector type with additional type information, fill
1552 in the struct pointed to by VECTYPE (if non-NULL).
1553 This function will fault on encountering a scalar. */
1556 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1557 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1559 struct neon_typed_alias atype
;
1561 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1566 /* Do not allow regname(... to parse as a register. */
1570 /* Do not allow a scalar (reg+index) to parse as a register. */
1571 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1573 first_error (_("register operand expected, but got scalar"));
1578 *vectype
= atype
.eltype
;
1585 #define NEON_SCALAR_REG(X) ((X) >> 4)
1586 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1588 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1589 have enough information to be able to do a good job bounds-checking. So, we
1590 just do easy checks here, and do further checks later. */
1593 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1597 struct neon_typed_alias atype
;
1599 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1601 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1604 if (atype
.index
== NEON_ALL_LANES
)
1606 first_error (_("scalar must have an index"));
1609 else if (atype
.index
>= 64 / elsize
)
1611 first_error (_("scalar index out of range"));
1616 *type
= atype
.eltype
;
1620 return reg
* 16 + atype
.index
;
1623 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1626 parse_reg_list (char ** strp
)
1628 char * str
= * strp
;
1632 /* We come back here if we get ranges concatenated by '+' or '|'. */
1635 skip_whitespace (str
);
1649 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1651 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1661 first_error (_("bad range in register list"));
1665 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1667 if (range
& (1 << i
))
1669 (_("Warning: duplicated register (r%d) in register list"),
1677 if (range
& (1 << reg
))
1678 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1680 else if (reg
<= cur_reg
)
1681 as_tsktsk (_("Warning: register range not in ascending order"));
1686 while (skip_past_comma (&str
) != FAIL
1687 || (in_range
= 1, *str
++ == '-'));
1690 if (skip_past_char (&str
, '}') == FAIL
)
1692 first_error (_("missing `}'"));
1700 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1703 if (exp
.X_op
== O_constant
)
1705 if (exp
.X_add_number
1706 != (exp
.X_add_number
& 0x0000ffff))
1708 inst
.error
= _("invalid register mask");
1712 if ((range
& exp
.X_add_number
) != 0)
1714 int regno
= range
& exp
.X_add_number
;
1717 regno
= (1 << regno
) - 1;
1719 (_("Warning: duplicated register (r%d) in register list"),
1723 range
|= exp
.X_add_number
;
1727 if (inst
.reloc
.type
!= 0)
1729 inst
.error
= _("expression too complex");
1733 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1734 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1735 inst
.reloc
.pc_rel
= 0;
1739 if (*str
== '|' || *str
== '+')
1745 while (another_range
);
1751 /* Types of registers in a list. */
1760 /* Parse a VFP register list. If the string is invalid return FAIL.
1761 Otherwise return the number of registers, and set PBASE to the first
1762 register. Parses registers of type ETYPE.
1763 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1764 - Q registers can be used to specify pairs of D registers
1765 - { } can be omitted from around a singleton register list
1766 FIXME: This is not implemented, as it would require backtracking in
1769 This could be done (the meaning isn't really ambiguous), but doesn't
1770 fit in well with the current parsing framework.
1771 - 32 D registers may be used (also true for VFPv3).
1772 FIXME: Types are ignored in these register lists, which is probably a
1776 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1781 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1785 unsigned long mask
= 0;
1788 if (skip_past_char (&str
, '{') == FAIL
)
1790 inst
.error
= _("expecting {");
1797 regtype
= REG_TYPE_VFS
;
1802 regtype
= REG_TYPE_VFD
;
1805 case REGLIST_NEON_D
:
1806 regtype
= REG_TYPE_NDQ
;
1810 if (etype
!= REGLIST_VFP_S
)
1812 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1813 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1817 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1820 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1827 base_reg
= max_regs
;
1831 int setmask
= 1, addregs
= 1;
1833 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1835 if (new_base
== FAIL
)
1837 first_error (_(reg_expected_msgs
[regtype
]));
1841 if (new_base
>= max_regs
)
1843 first_error (_("register out of range in list"));
1847 /* Note: a value of 2 * n is returned for the register Q<n>. */
1848 if (regtype
== REG_TYPE_NQ
)
1854 if (new_base
< base_reg
)
1855 base_reg
= new_base
;
1857 if (mask
& (setmask
<< new_base
))
1859 first_error (_("invalid register list"));
1863 if ((mask
>> new_base
) != 0 && ! warned
)
1865 as_tsktsk (_("register list not in ascending order"));
1869 mask
|= setmask
<< new_base
;
1872 if (*str
== '-') /* We have the start of a range expression */
1878 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1881 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1885 if (high_range
>= max_regs
)
1887 first_error (_("register out of range in list"));
1891 if (regtype
== REG_TYPE_NQ
)
1892 high_range
= high_range
+ 1;
1894 if (high_range
<= new_base
)
1896 inst
.error
= _("register range not in ascending order");
1900 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1902 if (mask
& (setmask
<< new_base
))
1904 inst
.error
= _("invalid register list");
1908 mask
|= setmask
<< new_base
;
1913 while (skip_past_comma (&str
) != FAIL
);
1917 /* Sanity check -- should have raised a parse error above. */
1918 if (count
== 0 || count
> max_regs
)
1923 /* Final test -- the registers must be consecutive. */
1925 for (i
= 0; i
< count
; i
++)
1927 if ((mask
& (1u << i
)) == 0)
1929 inst
.error
= _("non-contiguous register range");
1939 /* True if two alias types are the same. */
1942 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1950 if (a
->defined
!= b
->defined
)
1953 if ((a
->defined
& NTA_HASTYPE
) != 0
1954 && (a
->eltype
.type
!= b
->eltype
.type
1955 || a
->eltype
.size
!= b
->eltype
.size
))
1958 if ((a
->defined
& NTA_HASINDEX
) != 0
1959 && (a
->index
!= b
->index
))
1965 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1966 The base register is put in *PBASE.
1967 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1969 The register stride (minus one) is put in bit 4 of the return value.
1970 Bits [6:5] encode the list length (minus one).
1971 The type of the list elements is put in *ELTYPE, if non-NULL. */
1973 #define NEON_LANE(X) ((X) & 0xf)
1974 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1975 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1978 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1979 struct neon_type_el
*eltype
)
1986 int leading_brace
= 0;
1987 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1988 const char *const incr_error
= _("register stride must be 1 or 2");
1989 const char *const type_error
= _("mismatched element/structure types in list");
1990 struct neon_typed_alias firsttype
;
1992 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1997 struct neon_typed_alias atype
;
1998 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2002 first_error (_(reg_expected_msgs
[rtype
]));
2009 if (rtype
== REG_TYPE_NQ
)
2015 else if (reg_incr
== -1)
2017 reg_incr
= getreg
- base_reg
;
2018 if (reg_incr
< 1 || reg_incr
> 2)
2020 first_error (_(incr_error
));
2024 else if (getreg
!= base_reg
+ reg_incr
* count
)
2026 first_error (_(incr_error
));
2030 if (! neon_alias_types_same (&atype
, &firsttype
))
2032 first_error (_(type_error
));
2036 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2040 struct neon_typed_alias htype
;
2041 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2043 lane
= NEON_INTERLEAVE_LANES
;
2044 else if (lane
!= NEON_INTERLEAVE_LANES
)
2046 first_error (_(type_error
));
2051 else if (reg_incr
!= 1)
2053 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2057 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2060 first_error (_(reg_expected_msgs
[rtype
]));
2063 if (! neon_alias_types_same (&htype
, &firsttype
))
2065 first_error (_(type_error
));
2068 count
+= hireg
+ dregs
- getreg
;
2072 /* If we're using Q registers, we can't use [] or [n] syntax. */
2073 if (rtype
== REG_TYPE_NQ
)
2079 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2083 else if (lane
!= atype
.index
)
2085 first_error (_(type_error
));
2089 else if (lane
== -1)
2090 lane
= NEON_INTERLEAVE_LANES
;
2091 else if (lane
!= NEON_INTERLEAVE_LANES
)
2093 first_error (_(type_error
));
2098 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2100 /* No lane set by [x]. We must be interleaving structures. */
2102 lane
= NEON_INTERLEAVE_LANES
;
2105 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2106 || (count
> 1 && reg_incr
== -1))
2108 first_error (_("error parsing element/structure list"));
2112 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2114 first_error (_("expected }"));
2122 *eltype
= firsttype
.eltype
;
2127 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2130 /* Parse an explicit relocation suffix on an expression. This is
2131 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2132 arm_reloc_hsh contains no entries, so this function can only
2133 succeed if there is no () after the word. Returns -1 on error,
2134 BFD_RELOC_UNUSED if there wasn't any suffix. */
2137 parse_reloc (char **str
)
2139 struct reloc_entry
*r
;
2143 return BFD_RELOC_UNUSED
;
2148 while (*q
&& *q
!= ')' && *q
!= ',')
2153 if ((r
= (struct reloc_entry
*)
2154 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2161 /* Directives: register aliases. */
2163 static struct reg_entry
*
2164 insert_reg_alias (char *str
, unsigned number
, int type
)
2166 struct reg_entry
*new_reg
;
2169 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2171 if (new_reg
->builtin
)
2172 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2174 /* Only warn about a redefinition if it's not defined as the
2176 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2177 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2182 name
= xstrdup (str
);
2183 new_reg
= XNEW (struct reg_entry
);
2185 new_reg
->name
= name
;
2186 new_reg
->number
= number
;
2187 new_reg
->type
= type
;
2188 new_reg
->builtin
= FALSE
;
2189 new_reg
->neon
= NULL
;
2191 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2198 insert_neon_reg_alias (char *str
, int number
, int type
,
2199 struct neon_typed_alias
*atype
)
2201 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2205 first_error (_("attempt to redefine typed alias"));
2211 reg
->neon
= XNEW (struct neon_typed_alias
);
2212 *reg
->neon
= *atype
;
2216 /* Look for the .req directive. This is of the form:
2218 new_register_name .req existing_register_name
2220 If we find one, or if it looks sufficiently like one that we want to
2221 handle any error here, return TRUE. Otherwise return FALSE. */
2224 create_register_alias (char * newname
, char *p
)
2226 struct reg_entry
*old
;
2227 char *oldname
, *nbuf
;
2230 /* The input scrubber ensures that whitespace after the mnemonic is
2231 collapsed to single spaces. */
2233 if (strncmp (oldname
, " .req ", 6) != 0)
2237 if (*oldname
== '\0')
2240 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2243 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2247 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2248 the desired alias name, and p points to its end. If not, then
2249 the desired alias name is in the global original_case_string. */
2250 #ifdef TC_CASE_SENSITIVE
2253 newname
= original_case_string
;
2254 nlen
= strlen (newname
);
2257 nbuf
= xmalloc (nlen
+ 1);
2258 memcpy (nbuf
, newname
, nlen
);
2261 /* Create aliases under the new name as stated; an all-lowercase
2262 version of the new name; and an all-uppercase version of the new
2264 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2266 for (p
= nbuf
; *p
; p
++)
2269 if (strncmp (nbuf
, newname
, nlen
))
2271 /* If this attempt to create an additional alias fails, do not bother
2272 trying to create the all-lower case alias. We will fail and issue
2273 a second, duplicate error message. This situation arises when the
2274 programmer does something like:
2277 The second .req creates the "Foo" alias but then fails to create
2278 the artificial FOO alias because it has already been created by the
2280 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2287 for (p
= nbuf
; *p
; p
++)
2290 if (strncmp (nbuf
, newname
, nlen
))
2291 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2298 /* Create a Neon typed/indexed register alias using directives, e.g.:
2303 These typed registers can be used instead of the types specified after the
2304 Neon mnemonic, so long as all operands given have types. Types can also be
2305 specified directly, e.g.:
2306 vadd d0.s32, d1.s32, d2.s32 */
2309 create_neon_reg_alias (char *newname
, char *p
)
2311 enum arm_reg_type basetype
;
2312 struct reg_entry
*basereg
;
2313 struct reg_entry mybasereg
;
2314 struct neon_type ntype
;
2315 struct neon_typed_alias typeinfo
;
2316 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2319 typeinfo
.defined
= 0;
2320 typeinfo
.eltype
.type
= NT_invtype
;
2321 typeinfo
.eltype
.size
= -1;
2322 typeinfo
.index
= -1;
2326 if (strncmp (p
, " .dn ", 5) == 0)
2327 basetype
= REG_TYPE_VFD
;
2328 else if (strncmp (p
, " .qn ", 5) == 0)
2329 basetype
= REG_TYPE_NQ
;
2338 basereg
= arm_reg_parse_multi (&p
);
2340 if (basereg
&& basereg
->type
!= basetype
)
2342 as_bad (_("bad type for register"));
2346 if (basereg
== NULL
)
2349 /* Try parsing as an integer. */
2350 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2351 if (exp
.X_op
!= O_constant
)
2353 as_bad (_("expression must be constant"));
2356 basereg
= &mybasereg
;
2357 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2363 typeinfo
= *basereg
->neon
;
2365 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2367 /* We got a type. */
2368 if (typeinfo
.defined
& NTA_HASTYPE
)
2370 as_bad (_("can't redefine the type of a register alias"));
2374 typeinfo
.defined
|= NTA_HASTYPE
;
2375 if (ntype
.elems
!= 1)
2377 as_bad (_("you must specify a single type only"));
2380 typeinfo
.eltype
= ntype
.el
[0];
2383 if (skip_past_char (&p
, '[') == SUCCESS
)
2386 /* We got a scalar index. */
2388 if (typeinfo
.defined
& NTA_HASINDEX
)
2390 as_bad (_("can't redefine the index of a scalar alias"));
2394 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2396 if (exp
.X_op
!= O_constant
)
2398 as_bad (_("scalar index must be constant"));
2402 typeinfo
.defined
|= NTA_HASINDEX
;
2403 typeinfo
.index
= exp
.X_add_number
;
2405 if (skip_past_char (&p
, ']') == FAIL
)
2407 as_bad (_("expecting ]"));
2412 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2413 the desired alias name, and p points to its end. If not, then
2414 the desired alias name is in the global original_case_string. */
2415 #ifdef TC_CASE_SENSITIVE
2416 namelen
= nameend
- newname
;
2418 newname
= original_case_string
;
2419 namelen
= strlen (newname
);
2422 namebuf
= xmalloc (namelen
+ 1);
2423 strncpy (namebuf
, newname
, namelen
);
2424 namebuf
[namelen
] = '\0';
2426 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2427 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2429 /* Insert name in all uppercase. */
2430 for (p
= namebuf
; *p
; p
++)
2433 if (strncmp (namebuf
, newname
, namelen
))
2434 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2435 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2437 /* Insert name in all lowercase. */
2438 for (p
= namebuf
; *p
; p
++)
2441 if (strncmp (namebuf
, newname
, namelen
))
2442 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2443 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2449 /* Should never be called, as .req goes between the alias and the
2450 register name, not at the beginning of the line. */
2453 s_req (int a ATTRIBUTE_UNUSED
)
2455 as_bad (_("invalid syntax for .req directive"));
2459 s_dn (int a ATTRIBUTE_UNUSED
)
2461 as_bad (_("invalid syntax for .dn directive"));
2465 s_qn (int a ATTRIBUTE_UNUSED
)
2467 as_bad (_("invalid syntax for .qn directive"));
2470 /* The .unreq directive deletes an alias which was previously defined
2471 by .req. For example:
2477 s_unreq (int a ATTRIBUTE_UNUSED
)
2482 name
= input_line_pointer
;
2484 while (*input_line_pointer
!= 0
2485 && *input_line_pointer
!= ' '
2486 && *input_line_pointer
!= '\n')
2487 ++input_line_pointer
;
2489 saved_char
= *input_line_pointer
;
2490 *input_line_pointer
= 0;
2493 as_bad (_("invalid syntax for .unreq directive"));
2496 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2500 as_bad (_("unknown register alias '%s'"), name
);
2501 else if (reg
->builtin
)
2502 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2509 hash_delete (arm_reg_hsh
, name
, FALSE
);
2510 free ((char *) reg
->name
);
2515 /* Also locate the all upper case and all lower case versions.
2516 Do not complain if we cannot find one or the other as it
2517 was probably deleted above. */
2519 nbuf
= strdup (name
);
2520 for (p
= nbuf
; *p
; p
++)
2522 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2525 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2526 free ((char *) reg
->name
);
2532 for (p
= nbuf
; *p
; p
++)
2534 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2537 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2538 free ((char *) reg
->name
);
2548 *input_line_pointer
= saved_char
;
2549 demand_empty_rest_of_line ();
2552 /* Directives: Instruction set selection. */
2555 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2556 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2557 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2558 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2560 /* Create a new mapping symbol for the transition to STATE. */
2563 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2566 const char * symname
;
2573 type
= BSF_NO_FLAGS
;
2577 type
= BSF_NO_FLAGS
;
2581 type
= BSF_NO_FLAGS
;
2587 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2588 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2593 THUMB_SET_FUNC (symbolP
, 0);
2594 ARM_SET_THUMB (symbolP
, 0);
2595 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2599 THUMB_SET_FUNC (symbolP
, 1);
2600 ARM_SET_THUMB (symbolP
, 1);
2601 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2609 /* Save the mapping symbols for future reference. Also check that
2610 we do not place two mapping symbols at the same offset within a
2611 frag. We'll handle overlap between frags in
2612 check_mapping_symbols.
2614 If .fill or other data filling directive generates zero sized data,
2615 the mapping symbol for the following code will have the same value
2616 as the one generated for the data filling directive. In this case,
2617 we replace the old symbol with the new one at the same address. */
2620 if (frag
->tc_frag_data
.first_map
!= NULL
)
2622 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2623 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2625 frag
->tc_frag_data
.first_map
= symbolP
;
2627 if (frag
->tc_frag_data
.last_map
!= NULL
)
2629 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2630 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2631 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2633 frag
->tc_frag_data
.last_map
= symbolP
;
2636 /* We must sometimes convert a region marked as code to data during
2637 code alignment, if an odd number of bytes have to be padded. The
2638 code mapping symbol is pushed to an aligned address. */
2641 insert_data_mapping_symbol (enum mstate state
,
2642 valueT value
, fragS
*frag
, offsetT bytes
)
2644 /* If there was already a mapping symbol, remove it. */
2645 if (frag
->tc_frag_data
.last_map
!= NULL
2646 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2648 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2652 know (frag
->tc_frag_data
.first_map
== symp
);
2653 frag
->tc_frag_data
.first_map
= NULL
;
2655 frag
->tc_frag_data
.last_map
= NULL
;
2656 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2659 make_mapping_symbol (MAP_DATA
, value
, frag
);
2660 make_mapping_symbol (state
, value
+ bytes
, frag
);
2663 static void mapping_state_2 (enum mstate state
, int max_chars
);
2665 /* Set the mapping state to STATE. Only call this when about to
2666 emit some STATE bytes to the file. */
2668 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2670 mapping_state (enum mstate state
)
2672 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2674 if (mapstate
== state
)
2675 /* The mapping symbol has already been emitted.
2676 There is nothing else to do. */
2679 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2681 All ARM instructions require 4-byte alignment.
2682 (Almost) all Thumb instructions require 2-byte alignment.
2684 When emitting instructions into any section, mark the section
2687 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2688 but themselves require 2-byte alignment; this applies to some
2689 PC- relative forms. However, these cases will invovle implicit
2690 literal pool generation or an explicit .align >=2, both of
2691 which will cause the section to me marked with sufficient
2692 alignment. Thus, we don't handle those cases here. */
2693 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2695 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2696 /* This case will be evaluated later. */
2699 mapping_state_2 (state
, 0);
2702 /* Same as mapping_state, but MAX_CHARS bytes have already been
2703 allocated. Put the mapping symbol that far back. */
2706 mapping_state_2 (enum mstate state
, int max_chars
)
2708 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2710 if (!SEG_NORMAL (now_seg
))
2713 if (mapstate
== state
)
2714 /* The mapping symbol has already been emitted.
2715 There is nothing else to do. */
2718 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2719 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2721 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2722 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2725 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2728 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2729 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2733 #define mapping_state(x) ((void)0)
2734 #define mapping_state_2(x, y) ((void)0)
2737 /* Find the real, Thumb encoded start of a Thumb function. */
2741 find_real_start (symbolS
* symbolP
)
2744 const char * name
= S_GET_NAME (symbolP
);
2745 symbolS
* new_target
;
2747 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2748 #define STUB_NAME ".real_start_of"
2753 /* The compiler may generate BL instructions to local labels because
2754 it needs to perform a branch to a far away location. These labels
2755 do not have a corresponding ".real_start_of" label. We check
2756 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2757 the ".real_start_of" convention for nonlocal branches. */
2758 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2761 real_start
= concat (STUB_NAME
, name
, NULL
);
2762 new_target
= symbol_find (real_start
);
2765 if (new_target
== NULL
)
2767 as_warn (_("Failed to find real start of function: %s\n"), name
);
2768 new_target
= symbolP
;
2776 opcode_select (int width
)
2783 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2784 as_bad (_("selected processor does not support THUMB opcodes"));
2787 /* No need to force the alignment, since we will have been
2788 coming from ARM mode, which is word-aligned. */
2789 record_alignment (now_seg
, 1);
2796 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2797 as_bad (_("selected processor does not support ARM opcodes"));
2802 frag_align (2, 0, 0);
2804 record_alignment (now_seg
, 1);
2809 as_bad (_("invalid instruction size selected (%d)"), width
);
2814 s_arm (int ignore ATTRIBUTE_UNUSED
)
2817 demand_empty_rest_of_line ();
2821 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2824 demand_empty_rest_of_line ();
2828 s_code (int unused ATTRIBUTE_UNUSED
)
2832 temp
= get_absolute_expression ();
2837 opcode_select (temp
);
2841 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2846 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2848 /* If we are not already in thumb mode go into it, EVEN if
2849 the target processor does not support thumb instructions.
2850 This is used by gcc/config/arm/lib1funcs.asm for example
2851 to compile interworking support functions even if the
2852 target processor should not support interworking. */
2856 record_alignment (now_seg
, 1);
2859 demand_empty_rest_of_line ();
2863 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2867 /* The following label is the name/address of the start of a Thumb function.
2868 We need to know this for the interworking support. */
2869 label_is_thumb_function_name
= TRUE
;
2872 /* Perform a .set directive, but also mark the alias as
2873 being a thumb function. */
2876 s_thumb_set (int equiv
)
2878 /* XXX the following is a duplicate of the code for s_set() in read.c
2879 We cannot just call that code as we need to get at the symbol that
2886 /* Especial apologies for the random logic:
2887 This just grew, and could be parsed much more simply!
2889 delim
= get_symbol_name (& name
);
2890 end_name
= input_line_pointer
;
2891 (void) restore_line_pointer (delim
);
2893 if (*input_line_pointer
!= ',')
2896 as_bad (_("expected comma after name \"%s\""), name
);
2898 ignore_rest_of_line ();
2902 input_line_pointer
++;
2905 if (name
[0] == '.' && name
[1] == '\0')
2907 /* XXX - this should not happen to .thumb_set. */
2911 if ((symbolP
= symbol_find (name
)) == NULL
2912 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2915 /* When doing symbol listings, play games with dummy fragments living
2916 outside the normal fragment chain to record the file and line info
2918 if (listing
& LISTING_SYMBOLS
)
2920 extern struct list_info_struct
* listing_tail
;
2921 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2923 memset (dummy_frag
, 0, sizeof (fragS
));
2924 dummy_frag
->fr_type
= rs_fill
;
2925 dummy_frag
->line
= listing_tail
;
2926 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2927 dummy_frag
->fr_symbol
= symbolP
;
2931 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2934 /* "set" symbols are local unless otherwise specified. */
2935 SF_SET_LOCAL (symbolP
);
2936 #endif /* OBJ_COFF */
2937 } /* Make a new symbol. */
2939 symbol_table_insert (symbolP
);
2944 && S_IS_DEFINED (symbolP
)
2945 && S_GET_SEGMENT (symbolP
) != reg_section
)
2946 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2948 pseudo_set (symbolP
);
2950 demand_empty_rest_of_line ();
2952 /* XXX Now we come to the Thumb specific bit of code. */
2954 THUMB_SET_FUNC (symbolP
, 1);
2955 ARM_SET_THUMB (symbolP
, 1);
2956 #if defined OBJ_ELF || defined OBJ_COFF
2957 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2961 /* Directives: Mode selection. */
2963 /* .syntax [unified|divided] - choose the new unified syntax
2964 (same for Arm and Thumb encoding, modulo slight differences in what
2965 can be represented) or the old divergent syntax for each mode. */
2967 s_syntax (int unused ATTRIBUTE_UNUSED
)
2971 delim
= get_symbol_name (& name
);
2973 if (!strcasecmp (name
, "unified"))
2974 unified_syntax
= TRUE
;
2975 else if (!strcasecmp (name
, "divided"))
2976 unified_syntax
= FALSE
;
2979 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2982 (void) restore_line_pointer (delim
);
2983 demand_empty_rest_of_line ();
2986 /* Directives: sectioning and alignment. */
2989 s_bss (int ignore ATTRIBUTE_UNUSED
)
2991 /* We don't support putting frags in the BSS segment, we fake it by
2992 marking in_bss, then looking at s_skip for clues. */
2993 subseg_set (bss_section
, 0);
2994 demand_empty_rest_of_line ();
2996 #ifdef md_elf_section_change_hook
2997 md_elf_section_change_hook ();
3002 s_even (int ignore ATTRIBUTE_UNUSED
)
3004 /* Never make frag if expect extra pass. */
3006 frag_align (1, 0, 0);
3008 record_alignment (now_seg
, 1);
3010 demand_empty_rest_of_line ();
3013 /* Directives: CodeComposer Studio. */
3015 /* .ref (for CodeComposer Studio syntax only). */
3017 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3019 if (codecomposer_syntax
)
3020 ignore_rest_of_line ();
3022 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3025 /* If name is not NULL, then it is used for marking the beginning of a
3026 function, wherease if it is NULL then it means the function end. */
3028 asmfunc_debug (const char * name
)
3030 static const char * last_name
= NULL
;
3034 gas_assert (last_name
== NULL
);
3037 if (debug_type
== DEBUG_STABS
)
3038 stabs_generate_asm_func (name
, name
);
3042 gas_assert (last_name
!= NULL
);
3044 if (debug_type
== DEBUG_STABS
)
3045 stabs_generate_asm_endfunc (last_name
, last_name
);
3052 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3054 if (codecomposer_syntax
)
3056 switch (asmfunc_state
)
3058 case OUTSIDE_ASMFUNC
:
3059 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3062 case WAITING_ASMFUNC_NAME
:
3063 as_bad (_(".asmfunc repeated."));
3066 case WAITING_ENDASMFUNC
:
3067 as_bad (_(".asmfunc without function."));
3070 demand_empty_rest_of_line ();
3073 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3077 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3079 if (codecomposer_syntax
)
3081 switch (asmfunc_state
)
3083 case OUTSIDE_ASMFUNC
:
3084 as_bad (_(".endasmfunc without a .asmfunc."));
3087 case WAITING_ASMFUNC_NAME
:
3088 as_bad (_(".endasmfunc without function."));
3091 case WAITING_ENDASMFUNC
:
3092 asmfunc_state
= OUTSIDE_ASMFUNC
;
3093 asmfunc_debug (NULL
);
3096 demand_empty_rest_of_line ();
3099 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3103 s_ccs_def (int name
)
3105 if (codecomposer_syntax
)
3108 as_bad (_(".def pseudo-op only available with -mccs flag."));
3111 /* Directives: Literal pools. */
3113 static literal_pool
*
3114 find_literal_pool (void)
3116 literal_pool
* pool
;
3118 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3120 if (pool
->section
== now_seg
3121 && pool
->sub_section
== now_subseg
)
3128 static literal_pool
*
3129 find_or_make_literal_pool (void)
3131 /* Next literal pool ID number. */
3132 static unsigned int latest_pool_num
= 1;
3133 literal_pool
* pool
;
3135 pool
= find_literal_pool ();
3139 /* Create a new pool. */
3140 pool
= XNEW (literal_pool
);
3144 pool
->next_free_entry
= 0;
3145 pool
->section
= now_seg
;
3146 pool
->sub_section
= now_subseg
;
3147 pool
->next
= list_of_pools
;
3148 pool
->symbol
= NULL
;
3149 pool
->alignment
= 2;
3151 /* Add it to the list. */
3152 list_of_pools
= pool
;
3155 /* New pools, and emptied pools, will have a NULL symbol. */
3156 if (pool
->symbol
== NULL
)
3158 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3159 (valueT
) 0, &zero_address_frag
);
3160 pool
->id
= latest_pool_num
++;
3167 /* Add the literal in the global 'inst'
3168 structure to the relevant literal pool. */
3171 add_to_lit_pool (unsigned int nbytes
)
3173 #define PADDING_SLOT 0x1
3174 #define LIT_ENTRY_SIZE_MASK 0xFF
3175 literal_pool
* pool
;
3176 unsigned int entry
, pool_size
= 0;
3177 bfd_boolean padding_slot_p
= FALSE
;
3183 imm1
= inst
.operands
[1].imm
;
3184 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3185 : inst
.reloc
.exp
.X_unsigned
? 0
3186 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3187 if (target_big_endian
)
3190 imm2
= inst
.operands
[1].imm
;
3194 pool
= find_or_make_literal_pool ();
3196 /* Check if this literal value is already in the pool. */
3197 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3201 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3202 && (inst
.reloc
.exp
.X_op
== O_constant
)
3203 && (pool
->literals
[entry
].X_add_number
3204 == inst
.reloc
.exp
.X_add_number
)
3205 && (pool
->literals
[entry
].X_md
== nbytes
)
3206 && (pool
->literals
[entry
].X_unsigned
3207 == inst
.reloc
.exp
.X_unsigned
))
3210 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3211 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3212 && (pool
->literals
[entry
].X_add_number
3213 == inst
.reloc
.exp
.X_add_number
)
3214 && (pool
->literals
[entry
].X_add_symbol
3215 == inst
.reloc
.exp
.X_add_symbol
)
3216 && (pool
->literals
[entry
].X_op_symbol
3217 == inst
.reloc
.exp
.X_op_symbol
)
3218 && (pool
->literals
[entry
].X_md
== nbytes
))
3221 else if ((nbytes
== 8)
3222 && !(pool_size
& 0x7)
3223 && ((entry
+ 1) != pool
->next_free_entry
)
3224 && (pool
->literals
[entry
].X_op
== O_constant
)
3225 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3226 && (pool
->literals
[entry
].X_unsigned
3227 == inst
.reloc
.exp
.X_unsigned
)
3228 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3229 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3230 && (pool
->literals
[entry
+ 1].X_unsigned
3231 == inst
.reloc
.exp
.X_unsigned
))
3234 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3235 if (padding_slot_p
&& (nbytes
== 4))
3241 /* Do we need to create a new entry? */
3242 if (entry
== pool
->next_free_entry
)
3244 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3246 inst
.error
= _("literal pool overflow");
3252 /* For 8-byte entries, we align to an 8-byte boundary,
3253 and split it into two 4-byte entries, because on 32-bit
3254 host, 8-byte constants are treated as big num, thus
3255 saved in "generic_bignum" which will be overwritten
3256 by later assignments.
3258 We also need to make sure there is enough space for
3261 We also check to make sure the literal operand is a
3263 if (!(inst
.reloc
.exp
.X_op
== O_constant
3264 || inst
.reloc
.exp
.X_op
== O_big
))
3266 inst
.error
= _("invalid type for literal pool");
3269 else if (pool_size
& 0x7)
3271 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3273 inst
.error
= _("literal pool overflow");
3277 pool
->literals
[entry
] = inst
.reloc
.exp
;
3278 pool
->literals
[entry
].X_add_number
= 0;
3279 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3280 pool
->next_free_entry
+= 1;
3283 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3285 inst
.error
= _("literal pool overflow");
3289 pool
->literals
[entry
] = inst
.reloc
.exp
;
3290 pool
->literals
[entry
].X_op
= O_constant
;
3291 pool
->literals
[entry
].X_add_number
= imm1
;
3292 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3293 pool
->literals
[entry
++].X_md
= 4;
3294 pool
->literals
[entry
] = inst
.reloc
.exp
;
3295 pool
->literals
[entry
].X_op
= O_constant
;
3296 pool
->literals
[entry
].X_add_number
= imm2
;
3297 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3298 pool
->literals
[entry
].X_md
= 4;
3299 pool
->alignment
= 3;
3300 pool
->next_free_entry
+= 1;
3304 pool
->literals
[entry
] = inst
.reloc
.exp
;
3305 pool
->literals
[entry
].X_md
= 4;
3309 /* PR ld/12974: Record the location of the first source line to reference
3310 this entry in the literal pool. If it turns out during linking that the
3311 symbol does not exist we will be able to give an accurate line number for
3312 the (first use of the) missing reference. */
3313 if (debug_type
== DEBUG_DWARF2
)
3314 dwarf2_where (pool
->locs
+ entry
);
3316 pool
->next_free_entry
+= 1;
3318 else if (padding_slot_p
)
3320 pool
->literals
[entry
] = inst
.reloc
.exp
;
3321 pool
->literals
[entry
].X_md
= nbytes
;
3324 inst
.reloc
.exp
.X_op
= O_symbol
;
3325 inst
.reloc
.exp
.X_add_number
= pool_size
;
3326 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3332 tc_start_label_without_colon (void)
3334 bfd_boolean ret
= TRUE
;
3336 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3338 const char *label
= input_line_pointer
;
3340 while (!is_end_of_line
[(int) label
[-1]])
3345 as_bad (_("Invalid label '%s'"), label
);
3349 asmfunc_debug (label
);
3351 asmfunc_state
= WAITING_ENDASMFUNC
;
3357 /* Can't use symbol_new here, so have to create a symbol and then at
3358 a later date assign it a value. Thats what these functions do. */
3361 symbol_locate (symbolS
* symbolP
,
3362 const char * name
, /* It is copied, the caller can modify. */
3363 segT segment
, /* Segment identifier (SEG_<something>). */
3364 valueT valu
, /* Symbol value. */
3365 fragS
* frag
) /* Associated fragment. */
3368 char * preserved_copy_of_name
;
3370 name_length
= strlen (name
) + 1; /* +1 for \0. */
3371 obstack_grow (¬es
, name
, name_length
);
3372 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3374 #ifdef tc_canonicalize_symbol_name
3375 preserved_copy_of_name
=
3376 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3379 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3381 S_SET_SEGMENT (symbolP
, segment
);
3382 S_SET_VALUE (symbolP
, valu
);
3383 symbol_clear_list_pointers (symbolP
);
3385 symbol_set_frag (symbolP
, frag
);
3387 /* Link to end of symbol chain. */
3389 extern int symbol_table_frozen
;
3391 if (symbol_table_frozen
)
3395 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3397 obj_symbol_new_hook (symbolP
);
3399 #ifdef tc_symbol_new_hook
3400 tc_symbol_new_hook (symbolP
);
3404 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3405 #endif /* DEBUG_SYMS */
3409 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3412 literal_pool
* pool
;
3415 pool
= find_literal_pool ();
3417 || pool
->symbol
== NULL
3418 || pool
->next_free_entry
== 0)
3421 /* Align pool as you have word accesses.
3422 Only make a frag if we have to. */
3424 frag_align (pool
->alignment
, 0, 0);
3426 record_alignment (now_seg
, 2);
3429 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3430 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3432 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3434 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3435 (valueT
) frag_now_fix (), frag_now
);
3436 symbol_table_insert (pool
->symbol
);
3438 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3440 #if defined OBJ_COFF || defined OBJ_ELF
3441 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3444 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3447 if (debug_type
== DEBUG_DWARF2
)
3448 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3450 /* First output the expression in the instruction to the pool. */
3451 emit_expr (&(pool
->literals
[entry
]),
3452 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3455 /* Mark the pool as empty. */
3456 pool
->next_free_entry
= 0;
3457 pool
->symbol
= NULL
;
3461 /* Forward declarations for functions below, in the MD interface
3463 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3464 static valueT
create_unwind_entry (int);
3465 static void start_unwind_section (const segT
, int);
3466 static void add_unwind_opcode (valueT
, int);
3467 static void flush_pending_unwind (void);
3469 /* Directives: Data. */
3472 s_arm_elf_cons (int nbytes
)
3476 #ifdef md_flush_pending_output
3477 md_flush_pending_output ();
3480 if (is_it_end_of_statement ())
3482 demand_empty_rest_of_line ();
3486 #ifdef md_cons_align
3487 md_cons_align (nbytes
);
3490 mapping_state (MAP_DATA
);
3494 char *base
= input_line_pointer
;
3498 if (exp
.X_op
!= O_symbol
)
3499 emit_expr (&exp
, (unsigned int) nbytes
);
3502 char *before_reloc
= input_line_pointer
;
3503 reloc
= parse_reloc (&input_line_pointer
);
3506 as_bad (_("unrecognized relocation suffix"));
3507 ignore_rest_of_line ();
3510 else if (reloc
== BFD_RELOC_UNUSED
)
3511 emit_expr (&exp
, (unsigned int) nbytes
);
3514 reloc_howto_type
*howto
= (reloc_howto_type
*)
3515 bfd_reloc_type_lookup (stdoutput
,
3516 (bfd_reloc_code_real_type
) reloc
);
3517 int size
= bfd_get_reloc_size (howto
);
3519 if (reloc
== BFD_RELOC_ARM_PLT32
)
3521 as_bad (_("(plt) is only valid on branch targets"));
3522 reloc
= BFD_RELOC_UNUSED
;
3527 as_bad (_("%s relocations do not fit in %d bytes"),
3528 howto
->name
, nbytes
);
3531 /* We've parsed an expression stopping at O_symbol.
3532 But there may be more expression left now that we
3533 have parsed the relocation marker. Parse it again.
3534 XXX Surely there is a cleaner way to do this. */
3535 char *p
= input_line_pointer
;
3537 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3539 memcpy (save_buf
, base
, input_line_pointer
- base
);
3540 memmove (base
+ (input_line_pointer
- before_reloc
),
3541 base
, before_reloc
- base
);
3543 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3545 memcpy (base
, save_buf
, p
- base
);
3547 offset
= nbytes
- size
;
3548 p
= frag_more (nbytes
);
3549 memset (p
, 0, nbytes
);
3550 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3551 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3557 while (*input_line_pointer
++ == ',');
3559 /* Put terminator back into stream. */
3560 input_line_pointer
--;
3561 demand_empty_rest_of_line ();
3564 /* Emit an expression containing a 32-bit thumb instruction.
3565 Implementation based on put_thumb32_insn. */
3568 emit_thumb32_expr (expressionS
* exp
)
3570 expressionS exp_high
= *exp
;
3572 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3573 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3574 exp
->X_add_number
&= 0xffff;
3575 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3578 /* Guess the instruction size based on the opcode. */
3581 thumb_insn_size (int opcode
)
3583 if ((unsigned int) opcode
< 0xe800u
)
3585 else if ((unsigned int) opcode
>= 0xe8000000u
)
3592 emit_insn (expressionS
*exp
, int nbytes
)
3596 if (exp
->X_op
== O_constant
)
3601 size
= thumb_insn_size (exp
->X_add_number
);
3605 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3607 as_bad (_(".inst.n operand too big. "\
3608 "Use .inst.w instead"));
3613 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3614 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3616 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3618 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3619 emit_thumb32_expr (exp
);
3621 emit_expr (exp
, (unsigned int) size
);
3623 it_fsm_post_encode ();
3627 as_bad (_("cannot determine Thumb instruction size. " \
3628 "Use .inst.n/.inst.w instead"));
3631 as_bad (_("constant expression required"));
3636 /* Like s_arm_elf_cons but do not use md_cons_align and
3637 set the mapping state to MAP_ARM/MAP_THUMB. */
3640 s_arm_elf_inst (int nbytes
)
3642 if (is_it_end_of_statement ())
3644 demand_empty_rest_of_line ();
3648 /* Calling mapping_state () here will not change ARM/THUMB,
3649 but will ensure not to be in DATA state. */
3652 mapping_state (MAP_THUMB
);
3657 as_bad (_("width suffixes are invalid in ARM mode"));
3658 ignore_rest_of_line ();
3664 mapping_state (MAP_ARM
);
3673 if (! emit_insn (& exp
, nbytes
))
3675 ignore_rest_of_line ();
3679 while (*input_line_pointer
++ == ',');
3681 /* Put terminator back into stream. */
3682 input_line_pointer
--;
3683 demand_empty_rest_of_line ();
3686 /* Parse a .rel31 directive. */
3689 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3696 if (*input_line_pointer
== '1')
3697 highbit
= 0x80000000;
3698 else if (*input_line_pointer
!= '0')
3699 as_bad (_("expected 0 or 1"));
3701 input_line_pointer
++;
3702 if (*input_line_pointer
!= ',')
3703 as_bad (_("missing comma"));
3704 input_line_pointer
++;
3706 #ifdef md_flush_pending_output
3707 md_flush_pending_output ();
3710 #ifdef md_cons_align
3714 mapping_state (MAP_DATA
);
3719 md_number_to_chars (p
, highbit
, 4);
3720 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3721 BFD_RELOC_ARM_PREL31
);
3723 demand_empty_rest_of_line ();
3726 /* Directives: AEABI stack-unwind tables. */
3728 /* Parse an unwind_fnstart directive. Simply records the current location. */
3731 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3733 demand_empty_rest_of_line ();
3734 if (unwind
.proc_start
)
3736 as_bad (_("duplicate .fnstart directive"));
3740 /* Mark the start of the function. */
3741 unwind
.proc_start
= expr_build_dot ();
3743 /* Reset the rest of the unwind info. */
3744 unwind
.opcode_count
= 0;
3745 unwind
.table_entry
= NULL
;
3746 unwind
.personality_routine
= NULL
;
3747 unwind
.personality_index
= -1;
3748 unwind
.frame_size
= 0;
3749 unwind
.fp_offset
= 0;
3750 unwind
.fp_reg
= REG_SP
;
3752 unwind
.sp_restored
= 0;
3756 /* Parse a handlerdata directive. Creates the exception handling table entry
3757 for the function. */
3760 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3762 demand_empty_rest_of_line ();
3763 if (!unwind
.proc_start
)
3764 as_bad (MISSING_FNSTART
);
3766 if (unwind
.table_entry
)
3767 as_bad (_("duplicate .handlerdata directive"));
3769 create_unwind_entry (1);
3772 /* Parse an unwind_fnend directive. Generates the index table entry. */
3775 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3780 unsigned int marked_pr_dependency
;
3782 demand_empty_rest_of_line ();
3784 if (!unwind
.proc_start
)
3786 as_bad (_(".fnend directive without .fnstart"));
3790 /* Add eh table entry. */
3791 if (unwind
.table_entry
== NULL
)
3792 val
= create_unwind_entry (0);
3796 /* Add index table entry. This is two words. */
3797 start_unwind_section (unwind
.saved_seg
, 1);
3798 frag_align (2, 0, 0);
3799 record_alignment (now_seg
, 2);
3801 ptr
= frag_more (8);
3803 where
= frag_now_fix () - 8;
3805 /* Self relative offset of the function start. */
3806 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3807 BFD_RELOC_ARM_PREL31
);
3809 /* Indicate dependency on EHABI-defined personality routines to the
3810 linker, if it hasn't been done already. */
3811 marked_pr_dependency
3812 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3813 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3814 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3816 static const char *const name
[] =
3818 "__aeabi_unwind_cpp_pr0",
3819 "__aeabi_unwind_cpp_pr1",
3820 "__aeabi_unwind_cpp_pr2"
3822 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3823 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3824 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3825 |= 1 << unwind
.personality_index
;
3829 /* Inline exception table entry. */
3830 md_number_to_chars (ptr
+ 4, val
, 4);
3832 /* Self relative offset of the table entry. */
3833 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3834 BFD_RELOC_ARM_PREL31
);
3836 /* Restore the original section. */
3837 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3839 unwind
.proc_start
= NULL
;
3843 /* Parse an unwind_cantunwind directive. */
3846 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3848 demand_empty_rest_of_line ();
3849 if (!unwind
.proc_start
)
3850 as_bad (MISSING_FNSTART
);
3852 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3853 as_bad (_("personality routine specified for cantunwind frame"));
3855 unwind
.personality_index
= -2;
3859 /* Parse a personalityindex directive. */
3862 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3866 if (!unwind
.proc_start
)
3867 as_bad (MISSING_FNSTART
);
3869 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3870 as_bad (_("duplicate .personalityindex directive"));
3874 if (exp
.X_op
!= O_constant
3875 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3877 as_bad (_("bad personality routine number"));
3878 ignore_rest_of_line ();
3882 unwind
.personality_index
= exp
.X_add_number
;
3884 demand_empty_rest_of_line ();
3888 /* Parse a personality directive. */
3891 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3895 if (!unwind
.proc_start
)
3896 as_bad (MISSING_FNSTART
);
3898 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3899 as_bad (_("duplicate .personality directive"));
3901 c
= get_symbol_name (& name
);
3902 p
= input_line_pointer
;
3904 ++ input_line_pointer
;
3905 unwind
.personality_routine
= symbol_find_or_make (name
);
3907 demand_empty_rest_of_line ();
3911 /* Parse a directive saving core registers. */
3914 s_arm_unwind_save_core (void)
3920 range
= parse_reg_list (&input_line_pointer
);
3923 as_bad (_("expected register list"));
3924 ignore_rest_of_line ();
3928 demand_empty_rest_of_line ();
3930 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3931 into .unwind_save {..., sp...}. We aren't bothered about the value of
3932 ip because it is clobbered by calls. */
3933 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3934 && (range
& 0x3000) == 0x1000)
3936 unwind
.opcode_count
--;
3937 unwind
.sp_restored
= 0;
3938 range
= (range
| 0x2000) & ~0x1000;
3939 unwind
.pending_offset
= 0;
3945 /* See if we can use the short opcodes. These pop a block of up to 8
3946 registers starting with r4, plus maybe r14. */
3947 for (n
= 0; n
< 8; n
++)
3949 /* Break at the first non-saved register. */
3950 if ((range
& (1 << (n
+ 4))) == 0)
3953 /* See if there are any other bits set. */
3954 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3956 /* Use the long form. */
3957 op
= 0x8000 | ((range
>> 4) & 0xfff);
3958 add_unwind_opcode (op
, 2);
3962 /* Use the short form. */
3964 op
= 0xa8; /* Pop r14. */
3966 op
= 0xa0; /* Do not pop r14. */
3968 add_unwind_opcode (op
, 1);
3975 op
= 0xb100 | (range
& 0xf);
3976 add_unwind_opcode (op
, 2);
3979 /* Record the number of bytes pushed. */
3980 for (n
= 0; n
< 16; n
++)
3982 if (range
& (1 << n
))
3983 unwind
.frame_size
+= 4;
3988 /* Parse a directive saving FPA registers. */
3991 s_arm_unwind_save_fpa (int reg
)
3997 /* Get Number of registers to transfer. */
3998 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4001 exp
.X_op
= O_illegal
;
4003 if (exp
.X_op
!= O_constant
)
4005 as_bad (_("expected , <constant>"));
4006 ignore_rest_of_line ();
4010 num_regs
= exp
.X_add_number
;
4012 if (num_regs
< 1 || num_regs
> 4)
4014 as_bad (_("number of registers must be in the range [1:4]"));
4015 ignore_rest_of_line ();
4019 demand_empty_rest_of_line ();
4024 op
= 0xb4 | (num_regs
- 1);
4025 add_unwind_opcode (op
, 1);
4030 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4031 add_unwind_opcode (op
, 2);
4033 unwind
.frame_size
+= num_regs
* 12;
4037 /* Parse a directive saving VFP registers for ARMv6 and above. */
4040 s_arm_unwind_save_vfp_armv6 (void)
4045 int num_vfpv3_regs
= 0;
4046 int num_regs_below_16
;
4048 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4051 as_bad (_("expected register list"));
4052 ignore_rest_of_line ();
4056 demand_empty_rest_of_line ();
4058 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4059 than FSTMX/FLDMX-style ones). */
4061 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4063 num_vfpv3_regs
= count
;
4064 else if (start
+ count
> 16)
4065 num_vfpv3_regs
= start
+ count
- 16;
4067 if (num_vfpv3_regs
> 0)
4069 int start_offset
= start
> 16 ? start
- 16 : 0;
4070 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4071 add_unwind_opcode (op
, 2);
4074 /* Generate opcode for registers numbered in the range 0 .. 15. */
4075 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4076 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4077 if (num_regs_below_16
> 0)
4079 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4080 add_unwind_opcode (op
, 2);
4083 unwind
.frame_size
+= count
* 8;
4087 /* Parse a directive saving VFP registers for pre-ARMv6. */
4090 s_arm_unwind_save_vfp (void)
4096 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4099 as_bad (_("expected register list"));
4100 ignore_rest_of_line ();
4104 demand_empty_rest_of_line ();
4109 op
= 0xb8 | (count
- 1);
4110 add_unwind_opcode (op
, 1);
4115 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4116 add_unwind_opcode (op
, 2);
4118 unwind
.frame_size
+= count
* 8 + 4;
4122 /* Parse a directive saving iWMMXt data registers. */
4125 s_arm_unwind_save_mmxwr (void)
4133 if (*input_line_pointer
== '{')
4134 input_line_pointer
++;
4138 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4142 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4147 as_tsktsk (_("register list not in ascending order"));
4150 if (*input_line_pointer
== '-')
4152 input_line_pointer
++;
4153 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4156 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4159 else if (reg
>= hi_reg
)
4161 as_bad (_("bad register range"));
4164 for (; reg
< hi_reg
; reg
++)
4168 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4170 skip_past_char (&input_line_pointer
, '}');
4172 demand_empty_rest_of_line ();
4174 /* Generate any deferred opcodes because we're going to be looking at
4176 flush_pending_unwind ();
4178 for (i
= 0; i
< 16; i
++)
4180 if (mask
& (1 << i
))
4181 unwind
.frame_size
+= 8;
4184 /* Attempt to combine with a previous opcode. We do this because gcc
4185 likes to output separate unwind directives for a single block of
4187 if (unwind
.opcode_count
> 0)
4189 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4190 if ((i
& 0xf8) == 0xc0)
4193 /* Only merge if the blocks are contiguous. */
4196 if ((mask
& 0xfe00) == (1 << 9))
4198 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4199 unwind
.opcode_count
--;
4202 else if (i
== 6 && unwind
.opcode_count
>= 2)
4204 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4208 op
= 0xffff << (reg
- 1);
4210 && ((mask
& op
) == (1u << (reg
- 1))))
4212 op
= (1 << (reg
+ i
+ 1)) - 1;
4213 op
&= ~((1 << reg
) - 1);
4215 unwind
.opcode_count
-= 2;
4222 /* We want to generate opcodes in the order the registers have been
4223 saved, ie. descending order. */
4224 for (reg
= 15; reg
>= -1; reg
--)
4226 /* Save registers in blocks. */
4228 || !(mask
& (1 << reg
)))
4230 /* We found an unsaved reg. Generate opcodes to save the
4237 op
= 0xc0 | (hi_reg
- 10);
4238 add_unwind_opcode (op
, 1);
4243 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4244 add_unwind_opcode (op
, 2);
4253 ignore_rest_of_line ();
4257 s_arm_unwind_save_mmxwcg (void)
4264 if (*input_line_pointer
== '{')
4265 input_line_pointer
++;
4267 skip_whitespace (input_line_pointer
);
4271 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4275 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4281 as_tsktsk (_("register list not in ascending order"));
4284 if (*input_line_pointer
== '-')
4286 input_line_pointer
++;
4287 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4290 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4293 else if (reg
>= hi_reg
)
4295 as_bad (_("bad register range"));
4298 for (; reg
< hi_reg
; reg
++)
4302 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4304 skip_past_char (&input_line_pointer
, '}');
4306 demand_empty_rest_of_line ();
4308 /* Generate any deferred opcodes because we're going to be looking at
4310 flush_pending_unwind ();
4312 for (reg
= 0; reg
< 16; reg
++)
4314 if (mask
& (1 << reg
))
4315 unwind
.frame_size
+= 4;
4318 add_unwind_opcode (op
, 2);
4321 ignore_rest_of_line ();
4325 /* Parse an unwind_save directive.
4326 If the argument is non-zero, this is a .vsave directive. */
4329 s_arm_unwind_save (int arch_v6
)
4332 struct reg_entry
*reg
;
4333 bfd_boolean had_brace
= FALSE
;
4335 if (!unwind
.proc_start
)
4336 as_bad (MISSING_FNSTART
);
4338 /* Figure out what sort of save we have. */
4339 peek
= input_line_pointer
;
4347 reg
= arm_reg_parse_multi (&peek
);
4351 as_bad (_("register expected"));
4352 ignore_rest_of_line ();
4361 as_bad (_("FPA .unwind_save does not take a register list"));
4362 ignore_rest_of_line ();
4365 input_line_pointer
= peek
;
4366 s_arm_unwind_save_fpa (reg
->number
);
4370 s_arm_unwind_save_core ();
4375 s_arm_unwind_save_vfp_armv6 ();
4377 s_arm_unwind_save_vfp ();
4380 case REG_TYPE_MMXWR
:
4381 s_arm_unwind_save_mmxwr ();
4384 case REG_TYPE_MMXWCG
:
4385 s_arm_unwind_save_mmxwcg ();
4389 as_bad (_(".unwind_save does not support this kind of register"));
4390 ignore_rest_of_line ();
4395 /* Parse an unwind_movsp directive. */
4398 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4404 if (!unwind
.proc_start
)
4405 as_bad (MISSING_FNSTART
);
4407 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4410 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4411 ignore_rest_of_line ();
4415 /* Optional constant. */
4416 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4418 if (immediate_for_directive (&offset
) == FAIL
)
4424 demand_empty_rest_of_line ();
4426 if (reg
== REG_SP
|| reg
== REG_PC
)
4428 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4432 if (unwind
.fp_reg
!= REG_SP
)
4433 as_bad (_("unexpected .unwind_movsp directive"));
4435 /* Generate opcode to restore the value. */
4437 add_unwind_opcode (op
, 1);
4439 /* Record the information for later. */
4440 unwind
.fp_reg
= reg
;
4441 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4442 unwind
.sp_restored
= 1;
4445 /* Parse an unwind_pad directive. */
4448 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4452 if (!unwind
.proc_start
)
4453 as_bad (MISSING_FNSTART
);
4455 if (immediate_for_directive (&offset
) == FAIL
)
4460 as_bad (_("stack increment must be multiple of 4"));
4461 ignore_rest_of_line ();
4465 /* Don't generate any opcodes, just record the details for later. */
4466 unwind
.frame_size
+= offset
;
4467 unwind
.pending_offset
+= offset
;
4469 demand_empty_rest_of_line ();
4472 /* Parse an unwind_setfp directive. */
4475 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4481 if (!unwind
.proc_start
)
4482 as_bad (MISSING_FNSTART
);
4484 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4485 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4488 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4490 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4492 as_bad (_("expected <reg>, <reg>"));
4493 ignore_rest_of_line ();
4497 /* Optional constant. */
4498 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4500 if (immediate_for_directive (&offset
) == FAIL
)
4506 demand_empty_rest_of_line ();
4508 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4510 as_bad (_("register must be either sp or set by a previous"
4511 "unwind_movsp directive"));
4515 /* Don't generate any opcodes, just record the information for later. */
4516 unwind
.fp_reg
= fp_reg
;
4518 if (sp_reg
== REG_SP
)
4519 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4521 unwind
.fp_offset
-= offset
;
4524 /* Parse an unwind_raw directive. */
4527 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4530 /* This is an arbitrary limit. */
4531 unsigned char op
[16];
4534 if (!unwind
.proc_start
)
4535 as_bad (MISSING_FNSTART
);
4538 if (exp
.X_op
== O_constant
4539 && skip_past_comma (&input_line_pointer
) != FAIL
)
4541 unwind
.frame_size
+= exp
.X_add_number
;
4545 exp
.X_op
= O_illegal
;
4547 if (exp
.X_op
!= O_constant
)
4549 as_bad (_("expected <offset>, <opcode>"));
4550 ignore_rest_of_line ();
4556 /* Parse the opcode. */
4561 as_bad (_("unwind opcode too long"));
4562 ignore_rest_of_line ();
4564 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4566 as_bad (_("invalid unwind opcode"));
4567 ignore_rest_of_line ();
4570 op
[count
++] = exp
.X_add_number
;
4572 /* Parse the next byte. */
4573 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4579 /* Add the opcode bytes in reverse order. */
4581 add_unwind_opcode (op
[count
], 1);
4583 demand_empty_rest_of_line ();
4587 /* Parse a .eabi_attribute directive. */
4590 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4592 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4594 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4595 attributes_set_explicitly
[tag
] = 1;
4598 /* Emit a tls fix for the symbol. */
4601 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4605 #ifdef md_flush_pending_output
4606 md_flush_pending_output ();
4609 #ifdef md_cons_align
4613 /* Since we're just labelling the code, there's no need to define a
4616 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4617 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4618 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4619 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4621 #endif /* OBJ_ELF */
4623 static void s_arm_arch (int);
4624 static void s_arm_object_arch (int);
4625 static void s_arm_cpu (int);
4626 static void s_arm_fpu (int);
4627 static void s_arm_arch_extension (int);
4632 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4639 if (exp
.X_op
== O_symbol
)
4640 exp
.X_op
= O_secrel
;
4642 emit_expr (&exp
, 4);
4644 while (*input_line_pointer
++ == ',');
4646 input_line_pointer
--;
4647 demand_empty_rest_of_line ();
4651 /* This table describes all the machine specific pseudo-ops the assembler
4652 has to support. The fields are:
4653 pseudo-op name without dot
4654 function to call to execute this pseudo-op
4655 Integer arg to pass to the function. */
4657 const pseudo_typeS md_pseudo_table
[] =
4659 /* Never called because '.req' does not start a line. */
4660 { "req", s_req
, 0 },
4661 /* Following two are likewise never called. */
4664 { "unreq", s_unreq
, 0 },
4665 { "bss", s_bss
, 0 },
4666 { "align", s_align_ptwo
, 2 },
4667 { "arm", s_arm
, 0 },
4668 { "thumb", s_thumb
, 0 },
4669 { "code", s_code
, 0 },
4670 { "force_thumb", s_force_thumb
, 0 },
4671 { "thumb_func", s_thumb_func
, 0 },
4672 { "thumb_set", s_thumb_set
, 0 },
4673 { "even", s_even
, 0 },
4674 { "ltorg", s_ltorg
, 0 },
4675 { "pool", s_ltorg
, 0 },
4676 { "syntax", s_syntax
, 0 },
4677 { "cpu", s_arm_cpu
, 0 },
4678 { "arch", s_arm_arch
, 0 },
4679 { "object_arch", s_arm_object_arch
, 0 },
4680 { "fpu", s_arm_fpu
, 0 },
4681 { "arch_extension", s_arm_arch_extension
, 0 },
4683 { "word", s_arm_elf_cons
, 4 },
4684 { "long", s_arm_elf_cons
, 4 },
4685 { "inst.n", s_arm_elf_inst
, 2 },
4686 { "inst.w", s_arm_elf_inst
, 4 },
4687 { "inst", s_arm_elf_inst
, 0 },
4688 { "rel31", s_arm_rel31
, 0 },
4689 { "fnstart", s_arm_unwind_fnstart
, 0 },
4690 { "fnend", s_arm_unwind_fnend
, 0 },
4691 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4692 { "personality", s_arm_unwind_personality
, 0 },
4693 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4694 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4695 { "save", s_arm_unwind_save
, 0 },
4696 { "vsave", s_arm_unwind_save
, 1 },
4697 { "movsp", s_arm_unwind_movsp
, 0 },
4698 { "pad", s_arm_unwind_pad
, 0 },
4699 { "setfp", s_arm_unwind_setfp
, 0 },
4700 { "unwind_raw", s_arm_unwind_raw
, 0 },
4701 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4702 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4706 /* These are used for dwarf. */
4710 /* These are used for dwarf2. */
4711 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4712 { "loc", dwarf2_directive_loc
, 0 },
4713 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4715 { "extend", float_cons
, 'x' },
4716 { "ldouble", float_cons
, 'x' },
4717 { "packed", float_cons
, 'p' },
4719 {"secrel32", pe_directive_secrel
, 0},
4722 /* These are for compatibility with CodeComposer Studio. */
4723 {"ref", s_ccs_ref
, 0},
4724 {"def", s_ccs_def
, 0},
4725 {"asmfunc", s_ccs_asmfunc
, 0},
4726 {"endasmfunc", s_ccs_endasmfunc
, 0},
4731 /* Parser functions used exclusively in instruction operands. */
4733 /* Generic immediate-value read function for use in insn parsing.
4734 STR points to the beginning of the immediate (the leading #);
4735 VAL receives the value; if the value is outside [MIN, MAX]
4736 issue an error. PREFIX_OPT is true if the immediate prefix is
4740 parse_immediate (char **str
, int *val
, int min
, int max
,
4741 bfd_boolean prefix_opt
)
4744 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4745 if (exp
.X_op
!= O_constant
)
4747 inst
.error
= _("constant expression required");
4751 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4753 inst
.error
= _("immediate value out of range");
4757 *val
= exp
.X_add_number
;
4761 /* Less-generic immediate-value read function with the possibility of loading a
4762 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4763 instructions. Puts the result directly in inst.operands[i]. */
4766 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4767 bfd_boolean allow_symbol_p
)
4770 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4773 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4775 if (exp_p
->X_op
== O_constant
)
4777 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4778 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4779 O_constant. We have to be careful not to break compilation for
4780 32-bit X_add_number, though. */
4781 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4783 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4784 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4786 inst
.operands
[i
].regisimm
= 1;
4789 else if (exp_p
->X_op
== O_big
4790 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4792 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4794 /* Bignums have their least significant bits in
4795 generic_bignum[0]. Make sure we put 32 bits in imm and
4796 32 bits in reg, in a (hopefully) portable way. */
4797 gas_assert (parts
!= 0);
4799 /* Make sure that the number is not too big.
4800 PR 11972: Bignums can now be sign-extended to the
4801 size of a .octa so check that the out of range bits
4802 are all zero or all one. */
4803 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4805 LITTLENUM_TYPE m
= -1;
4807 if (generic_bignum
[parts
* 2] != 0
4808 && generic_bignum
[parts
* 2] != m
)
4811 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4812 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4816 inst
.operands
[i
].imm
= 0;
4817 for (j
= 0; j
< parts
; j
++, idx
++)
4818 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4819 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4820 inst
.operands
[i
].reg
= 0;
4821 for (j
= 0; j
< parts
; j
++, idx
++)
4822 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4823 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4824 inst
.operands
[i
].regisimm
= 1;
4826 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4834 /* Returns the pseudo-register number of an FPA immediate constant,
4835 or FAIL if there isn't a valid constant here. */
4838 parse_fpa_immediate (char ** str
)
4840 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4846 /* First try and match exact strings, this is to guarantee
4847 that some formats will work even for cross assembly. */
4849 for (i
= 0; fp_const
[i
]; i
++)
4851 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4855 *str
+= strlen (fp_const
[i
]);
4856 if (is_end_of_line
[(unsigned char) **str
])
4862 /* Just because we didn't get a match doesn't mean that the constant
4863 isn't valid, just that it is in a format that we don't
4864 automatically recognize. Try parsing it with the standard
4865 expression routines. */
4867 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4869 /* Look for a raw floating point number. */
4870 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4871 && is_end_of_line
[(unsigned char) *save_in
])
4873 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4875 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4877 if (words
[j
] != fp_values
[i
][j
])
4881 if (j
== MAX_LITTLENUMS
)
4889 /* Try and parse a more complex expression, this will probably fail
4890 unless the code uses a floating point prefix (eg "0f"). */
4891 save_in
= input_line_pointer
;
4892 input_line_pointer
= *str
;
4893 if (expression (&exp
) == absolute_section
4894 && exp
.X_op
== O_big
4895 && exp
.X_add_number
< 0)
4897 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4899 #define X_PRECISION 5
4900 #define E_PRECISION 15L
4901 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4903 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4905 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4907 if (words
[j
] != fp_values
[i
][j
])
4911 if (j
== MAX_LITTLENUMS
)
4913 *str
= input_line_pointer
;
4914 input_line_pointer
= save_in
;
4921 *str
= input_line_pointer
;
4922 input_line_pointer
= save_in
;
4923 inst
.error
= _("invalid FPA immediate expression");
4927 /* Returns 1 if a number has "quarter-precision" float format
4928 0baBbbbbbc defgh000 00000000 00000000. */
4931 is_quarter_float (unsigned imm
)
4933 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4934 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4938 /* Detect the presence of a floating point or integer zero constant,
4942 parse_ifimm_zero (char **in
)
4946 if (!is_immediate_prefix (**in
))
4951 /* Accept #0x0 as a synonym for #0. */
4952 if (strncmp (*in
, "0x", 2) == 0)
4955 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
4960 error_code
= atof_generic (in
, ".", EXP_CHARS
,
4961 &generic_floating_point_number
);
4964 && generic_floating_point_number
.sign
== '+'
4965 && (generic_floating_point_number
.low
4966 > generic_floating_point_number
.leader
))
4972 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4973 0baBbbbbbc defgh000 00000000 00000000.
4974 The zero and minus-zero cases need special handling, since they can't be
4975 encoded in the "quarter-precision" float format, but can nonetheless be
4976 loaded as integer constants. */
4979 parse_qfloat_immediate (char **ccp
, int *immed
)
4983 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4984 int found_fpchar
= 0;
4986 skip_past_char (&str
, '#');
4988 /* We must not accidentally parse an integer as a floating-point number. Make
4989 sure that the value we parse is not an integer by checking for special
4990 characters '.' or 'e'.
4991 FIXME: This is a horrible hack, but doing better is tricky because type
4992 information isn't in a very usable state at parse time. */
4994 skip_whitespace (fpnum
);
4996 if (strncmp (fpnum
, "0x", 2) == 0)
5000 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5001 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5011 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5013 unsigned fpword
= 0;
5016 /* Our FP word must be 32 bits (single-precision FP). */
5017 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5019 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5023 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5036 /* Shift operands. */
5039 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5042 struct asm_shift_name
5045 enum shift_kind kind
;
5048 /* Third argument to parse_shift. */
5049 enum parse_shift_mode
5051 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5052 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5053 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5054 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5055 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5058 /* Parse a <shift> specifier on an ARM data processing instruction.
5059 This has three forms:
5061 (LSL|LSR|ASL|ASR|ROR) Rs
5062 (LSL|LSR|ASL|ASR|ROR) #imm
5065 Note that ASL is assimilated to LSL in the instruction encoding, and
5066 RRX to ROR #0 (which cannot be written as such). */
5069 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5071 const struct asm_shift_name
*shift_name
;
5072 enum shift_kind shift
;
5077 for (p
= *str
; ISALPHA (*p
); p
++)
5082 inst
.error
= _("shift expression expected");
5086 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5089 if (shift_name
== NULL
)
5091 inst
.error
= _("shift expression expected");
5095 shift
= shift_name
->kind
;
5099 case NO_SHIFT_RESTRICT
:
5100 case SHIFT_IMMEDIATE
: break;
5102 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5103 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5105 inst
.error
= _("'LSL' or 'ASR' required");
5110 case SHIFT_LSL_IMMEDIATE
:
5111 if (shift
!= SHIFT_LSL
)
5113 inst
.error
= _("'LSL' required");
5118 case SHIFT_ASR_IMMEDIATE
:
5119 if (shift
!= SHIFT_ASR
)
5121 inst
.error
= _("'ASR' required");
5129 if (shift
!= SHIFT_RRX
)
5131 /* Whitespace can appear here if the next thing is a bare digit. */
5132 skip_whitespace (p
);
5134 if (mode
== NO_SHIFT_RESTRICT
5135 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5137 inst
.operands
[i
].imm
= reg
;
5138 inst
.operands
[i
].immisreg
= 1;
5140 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5143 inst
.operands
[i
].shift_kind
= shift
;
5144 inst
.operands
[i
].shifted
= 1;
5149 /* Parse a <shifter_operand> for an ARM data processing instruction:
5152 #<immediate>, <rotate>
5156 where <shift> is defined by parse_shift above, and <rotate> is a
5157 multiple of 2 between 0 and 30. Validation of immediate operands
5158 is deferred to md_apply_fix. */
5161 parse_shifter_operand (char **str
, int i
)
5166 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5168 inst
.operands
[i
].reg
= value
;
5169 inst
.operands
[i
].isreg
= 1;
5171 /* parse_shift will override this if appropriate */
5172 inst
.reloc
.exp
.X_op
= O_constant
;
5173 inst
.reloc
.exp
.X_add_number
= 0;
5175 if (skip_past_comma (str
) == FAIL
)
5178 /* Shift operation on register. */
5179 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5182 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5185 if (skip_past_comma (str
) == SUCCESS
)
5187 /* #x, y -- ie explicit rotation by Y. */
5188 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5191 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5193 inst
.error
= _("constant expression expected");
5197 value
= exp
.X_add_number
;
5198 if (value
< 0 || value
> 30 || value
% 2 != 0)
5200 inst
.error
= _("invalid rotation");
5203 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5205 inst
.error
= _("invalid constant");
5209 /* Encode as specified. */
5210 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5214 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5215 inst
.reloc
.pc_rel
= 0;
5219 /* Group relocation information. Each entry in the table contains the
5220 textual name of the relocation as may appear in assembler source
5221 and must end with a colon.
5222 Along with this textual name are the relocation codes to be used if
5223 the corresponding instruction is an ALU instruction (ADD or SUB only),
5224 an LDR, an LDRS, or an LDC. */
5226 struct group_reloc_table_entry
5237 /* Varieties of non-ALU group relocation. */
5244 static struct group_reloc_table_entry group_reloc_table
[] =
5245 { /* Program counter relative: */
5247 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5252 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5253 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5254 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5255 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5257 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5262 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5263 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5264 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5265 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5267 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5268 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5269 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5270 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5271 /* Section base relative */
5273 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5278 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5279 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5280 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5281 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5283 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5288 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5289 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5290 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5291 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5293 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5294 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5295 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5296 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5297 /* Absolute thumb alu relocations. */
5299 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5304 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5309 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5314 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5319 /* Given the address of a pointer pointing to the textual name of a group
5320 relocation as may appear in assembler source, attempt to find its details
5321 in group_reloc_table. The pointer will be updated to the character after
5322 the trailing colon. On failure, FAIL will be returned; SUCCESS
5323 otherwise. On success, *entry will be updated to point at the relevant
5324 group_reloc_table entry. */
5327 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5330 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5332 int length
= strlen (group_reloc_table
[i
].name
);
5334 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5335 && (*str
)[length
] == ':')
5337 *out
= &group_reloc_table
[i
];
5338 *str
+= (length
+ 1);
5346 /* Parse a <shifter_operand> for an ARM data processing instruction
5347 (as for parse_shifter_operand) where group relocations are allowed:
5350 #<immediate>, <rotate>
5351 #:<group_reloc>:<expression>
5355 where <group_reloc> is one of the strings defined in group_reloc_table.
5356 The hashes are optional.
5358 Everything else is as for parse_shifter_operand. */
5360 static parse_operand_result
5361 parse_shifter_operand_group_reloc (char **str
, int i
)
5363 /* Determine if we have the sequence of characters #: or just :
5364 coming next. If we do, then we check for a group relocation.
5365 If we don't, punt the whole lot to parse_shifter_operand. */
5367 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5368 || (*str
)[0] == ':')
5370 struct group_reloc_table_entry
*entry
;
5372 if ((*str
)[0] == '#')
5377 /* Try to parse a group relocation. Anything else is an error. */
5378 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5380 inst
.error
= _("unknown group relocation");
5381 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5384 /* We now have the group relocation table entry corresponding to
5385 the name in the assembler source. Next, we parse the expression. */
5386 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5387 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5389 /* Record the relocation type (always the ALU variant here). */
5390 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5391 gas_assert (inst
.reloc
.type
!= 0);
5393 return PARSE_OPERAND_SUCCESS
;
5396 return parse_shifter_operand (str
, i
) == SUCCESS
5397 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5399 /* Never reached. */
5402 /* Parse a Neon alignment expression. Information is written to
5403 inst.operands[i]. We assume the initial ':' has been skipped.
5405 align .imm = align << 8, .immisalign=1, .preind=0 */
5406 static parse_operand_result
5407 parse_neon_alignment (char **str
, int i
)
5412 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5414 if (exp
.X_op
!= O_constant
)
5416 inst
.error
= _("alignment must be constant");
5417 return PARSE_OPERAND_FAIL
;
5420 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5421 inst
.operands
[i
].immisalign
= 1;
5422 /* Alignments are not pre-indexes. */
5423 inst
.operands
[i
].preind
= 0;
5426 return PARSE_OPERAND_SUCCESS
;
5429 /* Parse all forms of an ARM address expression. Information is written
5430 to inst.operands[i] and/or inst.reloc.
5432 Preindexed addressing (.preind=1):
5434 [Rn, #offset] .reg=Rn .reloc.exp=offset
5435 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5436 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5437 .shift_kind=shift .reloc.exp=shift_imm
5439 These three may have a trailing ! which causes .writeback to be set also.
5441 Postindexed addressing (.postind=1, .writeback=1):
5443 [Rn], #offset .reg=Rn .reloc.exp=offset
5444 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5445 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5446 .shift_kind=shift .reloc.exp=shift_imm
5448 Unindexed addressing (.preind=0, .postind=0):
5450 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5454 [Rn]{!} shorthand for [Rn,#0]{!}
5455 =immediate .isreg=0 .reloc.exp=immediate
5456 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5458 It is the caller's responsibility to check for addressing modes not
5459 supported by the instruction, and to set inst.reloc.type. */
5461 static parse_operand_result
5462 parse_address_main (char **str
, int i
, int group_relocations
,
5463 group_reloc_type group_type
)
5468 if (skip_past_char (&p
, '[') == FAIL
)
5470 if (skip_past_char (&p
, '=') == FAIL
)
5472 /* Bare address - translate to PC-relative offset. */
5473 inst
.reloc
.pc_rel
= 1;
5474 inst
.operands
[i
].reg
= REG_PC
;
5475 inst
.operands
[i
].isreg
= 1;
5476 inst
.operands
[i
].preind
= 1;
5478 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5479 return PARSE_OPERAND_FAIL
;
5481 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5482 /*allow_symbol_p=*/TRUE
))
5483 return PARSE_OPERAND_FAIL
;
5486 return PARSE_OPERAND_SUCCESS
;
5489 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5490 skip_whitespace (p
);
5492 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5494 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5495 return PARSE_OPERAND_FAIL
;
5497 inst
.operands
[i
].reg
= reg
;
5498 inst
.operands
[i
].isreg
= 1;
5500 if (skip_past_comma (&p
) == SUCCESS
)
5502 inst
.operands
[i
].preind
= 1;
5505 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5507 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5509 inst
.operands
[i
].imm
= reg
;
5510 inst
.operands
[i
].immisreg
= 1;
5512 if (skip_past_comma (&p
) == SUCCESS
)
5513 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5514 return PARSE_OPERAND_FAIL
;
5516 else if (skip_past_char (&p
, ':') == SUCCESS
)
5518 /* FIXME: '@' should be used here, but it's filtered out by generic
5519 code before we get to see it here. This may be subject to
5521 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5523 if (result
!= PARSE_OPERAND_SUCCESS
)
5528 if (inst
.operands
[i
].negative
)
5530 inst
.operands
[i
].negative
= 0;
5534 if (group_relocations
5535 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5537 struct group_reloc_table_entry
*entry
;
5539 /* Skip over the #: or : sequence. */
5545 /* Try to parse a group relocation. Anything else is an
5547 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5549 inst
.error
= _("unknown group relocation");
5550 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5553 /* We now have the group relocation table entry corresponding to
5554 the name in the assembler source. Next, we parse the
5556 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5557 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5559 /* Record the relocation type. */
5563 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5567 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5571 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5578 if (inst
.reloc
.type
== 0)
5580 inst
.error
= _("this group relocation is not allowed on this instruction");
5581 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5587 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5588 return PARSE_OPERAND_FAIL
;
5589 /* If the offset is 0, find out if it's a +0 or -0. */
5590 if (inst
.reloc
.exp
.X_op
== O_constant
5591 && inst
.reloc
.exp
.X_add_number
== 0)
5593 skip_whitespace (q
);
5597 skip_whitespace (q
);
5600 inst
.operands
[i
].negative
= 1;
5605 else if (skip_past_char (&p
, ':') == SUCCESS
)
5607 /* FIXME: '@' should be used here, but it's filtered out by generic code
5608 before we get to see it here. This may be subject to change. */
5609 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5611 if (result
!= PARSE_OPERAND_SUCCESS
)
5615 if (skip_past_char (&p
, ']') == FAIL
)
5617 inst
.error
= _("']' expected");
5618 return PARSE_OPERAND_FAIL
;
5621 if (skip_past_char (&p
, '!') == SUCCESS
)
5622 inst
.operands
[i
].writeback
= 1;
5624 else if (skip_past_comma (&p
) == SUCCESS
)
5626 if (skip_past_char (&p
, '{') == SUCCESS
)
5628 /* [Rn], {expr} - unindexed, with option */
5629 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5630 0, 255, TRUE
) == FAIL
)
5631 return PARSE_OPERAND_FAIL
;
5633 if (skip_past_char (&p
, '}') == FAIL
)
5635 inst
.error
= _("'}' expected at end of 'option' field");
5636 return PARSE_OPERAND_FAIL
;
5638 if (inst
.operands
[i
].preind
)
5640 inst
.error
= _("cannot combine index with option");
5641 return PARSE_OPERAND_FAIL
;
5644 return PARSE_OPERAND_SUCCESS
;
5648 inst
.operands
[i
].postind
= 1;
5649 inst
.operands
[i
].writeback
= 1;
5651 if (inst
.operands
[i
].preind
)
5653 inst
.error
= _("cannot combine pre- and post-indexing");
5654 return PARSE_OPERAND_FAIL
;
5658 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5660 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5662 /* We might be using the immediate for alignment already. If we
5663 are, OR the register number into the low-order bits. */
5664 if (inst
.operands
[i
].immisalign
)
5665 inst
.operands
[i
].imm
|= reg
;
5667 inst
.operands
[i
].imm
= reg
;
5668 inst
.operands
[i
].immisreg
= 1;
5670 if (skip_past_comma (&p
) == SUCCESS
)
5671 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5672 return PARSE_OPERAND_FAIL
;
5677 if (inst
.operands
[i
].negative
)
5679 inst
.operands
[i
].negative
= 0;
5682 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5683 return PARSE_OPERAND_FAIL
;
5684 /* If the offset is 0, find out if it's a +0 or -0. */
5685 if (inst
.reloc
.exp
.X_op
== O_constant
5686 && inst
.reloc
.exp
.X_add_number
== 0)
5688 skip_whitespace (q
);
5692 skip_whitespace (q
);
5695 inst
.operands
[i
].negative
= 1;
5701 /* If at this point neither .preind nor .postind is set, we have a
5702 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5703 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5705 inst
.operands
[i
].preind
= 1;
5706 inst
.reloc
.exp
.X_op
= O_constant
;
5707 inst
.reloc
.exp
.X_add_number
= 0;
5710 return PARSE_OPERAND_SUCCESS
;
5714 parse_address (char **str
, int i
)
5716 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5720 static parse_operand_result
5721 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5723 return parse_address_main (str
, i
, 1, type
);
5726 /* Parse an operand for a MOVW or MOVT instruction. */
5728 parse_half (char **str
)
5733 skip_past_char (&p
, '#');
5734 if (strncasecmp (p
, ":lower16:", 9) == 0)
5735 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5736 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5737 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5739 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5742 skip_whitespace (p
);
5745 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5748 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5750 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5752 inst
.error
= _("constant expression expected");
5755 if (inst
.reloc
.exp
.X_add_number
< 0
5756 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5758 inst
.error
= _("immediate value out of range");
5766 /* Miscellaneous. */
5768 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5769 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5771 parse_psr (char **str
, bfd_boolean lhs
)
5774 unsigned long psr_field
;
5775 const struct asm_psr
*psr
;
5777 bfd_boolean is_apsr
= FALSE
;
5778 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5780 /* PR gas/12698: If the user has specified -march=all then m_profile will
5781 be TRUE, but we want to ignore it in this case as we are building for any
5782 CPU type, including non-m variants. */
5783 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5786 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5787 feature for ease of use and backwards compatibility. */
5789 if (strncasecmp (p
, "SPSR", 4) == 0)
5792 goto unsupported_psr
;
5794 psr_field
= SPSR_BIT
;
5796 else if (strncasecmp (p
, "CPSR", 4) == 0)
5799 goto unsupported_psr
;
5803 else if (strncasecmp (p
, "APSR", 4) == 0)
5805 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5806 and ARMv7-R architecture CPUs. */
5815 while (ISALNUM (*p
) || *p
== '_');
5817 if (strncasecmp (start
, "iapsr", 5) == 0
5818 || strncasecmp (start
, "eapsr", 5) == 0
5819 || strncasecmp (start
, "xpsr", 4) == 0
5820 || strncasecmp (start
, "psr", 3) == 0)
5821 p
= start
+ strcspn (start
, "rR") + 1;
5823 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5829 /* If APSR is being written, a bitfield may be specified. Note that
5830 APSR itself is handled above. */
5831 if (psr
->field
<= 3)
5833 psr_field
= psr
->field
;
5839 /* M-profile MSR instructions have the mask field set to "10", except
5840 *PSR variants which modify APSR, which may use a different mask (and
5841 have been handled already). Do that by setting the PSR_f field
5843 return psr
->field
| (lhs
? PSR_f
: 0);
5846 goto unsupported_psr
;
5852 /* A suffix follows. */
5858 while (ISALNUM (*p
) || *p
== '_');
5862 /* APSR uses a notation for bits, rather than fields. */
5863 unsigned int nzcvq_bits
= 0;
5864 unsigned int g_bit
= 0;
5867 for (bit
= start
; bit
!= p
; bit
++)
5869 switch (TOLOWER (*bit
))
5872 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5876 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5880 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5884 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5888 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5892 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5896 inst
.error
= _("unexpected bit specified after APSR");
5901 if (nzcvq_bits
== 0x1f)
5906 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5908 inst
.error
= _("selected processor does not "
5909 "support DSP extension");
5916 if ((nzcvq_bits
& 0x20) != 0
5917 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5918 || (g_bit
& 0x2) != 0)
5920 inst
.error
= _("bad bitmask specified after APSR");
5926 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5931 psr_field
|= psr
->field
;
5937 goto error
; /* Garbage after "[CS]PSR". */
5939 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5940 is deprecated, but allow it anyway. */
5944 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5947 else if (!m_profile
)
5948 /* These bits are never right for M-profile devices: don't set them
5949 (only code paths which read/write APSR reach here). */
5950 psr_field
|= (PSR_c
| PSR_f
);
5956 inst
.error
= _("selected processor does not support requested special "
5957 "purpose register");
5961 inst
.error
= _("flag for {c}psr instruction expected");
5965 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5966 value suitable for splatting into the AIF field of the instruction. */
5969 parse_cps_flags (char **str
)
5978 case '\0': case ',':
5981 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5982 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5983 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5986 inst
.error
= _("unrecognized CPS flag");
5991 if (saw_a_flag
== 0)
5993 inst
.error
= _("missing CPS flags");
6001 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6002 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6005 parse_endian_specifier (char **str
)
6010 if (strncasecmp (s
, "BE", 2))
6012 else if (strncasecmp (s
, "LE", 2))
6016 inst
.error
= _("valid endian specifiers are be or le");
6020 if (ISALNUM (s
[2]) || s
[2] == '_')
6022 inst
.error
= _("valid endian specifiers are be or le");
6027 return little_endian
;
6030 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6031 value suitable for poking into the rotate field of an sxt or sxta
6032 instruction, or FAIL on error. */
6035 parse_ror (char **str
)
6040 if (strncasecmp (s
, "ROR", 3) == 0)
6044 inst
.error
= _("missing rotation field after comma");
6048 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6053 case 0: *str
= s
; return 0x0;
6054 case 8: *str
= s
; return 0x1;
6055 case 16: *str
= s
; return 0x2;
6056 case 24: *str
= s
; return 0x3;
6059 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6064 /* Parse a conditional code (from conds[] below). The value returned is in the
6065 range 0 .. 14, or FAIL. */
6067 parse_cond (char **str
)
6070 const struct asm_cond
*c
;
6072 /* Condition codes are always 2 characters, so matching up to
6073 3 characters is sufficient. */
6078 while (ISALPHA (*q
) && n
< 3)
6080 cond
[n
] = TOLOWER (*q
);
6085 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6088 inst
.error
= _("condition required");
6096 /* Record a use of the given feature. */
6098 record_feature_use (const arm_feature_set
*feature
)
6101 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6103 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6106 /* If the given feature available in the selected CPU, mark it as used.
6107 Returns TRUE iff feature is available. */
6109 mark_feature_used (const arm_feature_set
*feature
)
6111 /* Ensure the option is valid on the current architecture. */
6112 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6115 /* Add the appropriate architecture feature for the barrier option used.
6117 record_feature_use (feature
);
6122 /* Parse an option for a barrier instruction. Returns the encoding for the
6125 parse_barrier (char **str
)
6128 const struct asm_barrier_opt
*o
;
6131 while (ISALPHA (*q
))
6134 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6139 if (!mark_feature_used (&o
->arch
))
6146 /* Parse the operands of a table branch instruction. Similar to a memory
6149 parse_tb (char **str
)
6154 if (skip_past_char (&p
, '[') == FAIL
)
6156 inst
.error
= _("'[' expected");
6160 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6162 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6165 inst
.operands
[0].reg
= reg
;
6167 if (skip_past_comma (&p
) == FAIL
)
6169 inst
.error
= _("',' expected");
6173 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6175 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6178 inst
.operands
[0].imm
= reg
;
6180 if (skip_past_comma (&p
) == SUCCESS
)
6182 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6184 if (inst
.reloc
.exp
.X_add_number
!= 1)
6186 inst
.error
= _("invalid shift");
6189 inst
.operands
[0].shifted
= 1;
6192 if (skip_past_char (&p
, ']') == FAIL
)
6194 inst
.error
= _("']' expected");
6201 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6202 information on the types the operands can take and how they are encoded.
6203 Up to four operands may be read; this function handles setting the
6204 ".present" field for each read operand itself.
6205 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6206 else returns FAIL. */
6209 parse_neon_mov (char **str
, int *which_operand
)
6211 int i
= *which_operand
, val
;
6212 enum arm_reg_type rtype
;
6214 struct neon_type_el optype
;
6216 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6218 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6219 inst
.operands
[i
].reg
= val
;
6220 inst
.operands
[i
].isscalar
= 1;
6221 inst
.operands
[i
].vectype
= optype
;
6222 inst
.operands
[i
++].present
= 1;
6224 if (skip_past_comma (&ptr
) == FAIL
)
6227 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6230 inst
.operands
[i
].reg
= val
;
6231 inst
.operands
[i
].isreg
= 1;
6232 inst
.operands
[i
].present
= 1;
6234 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6237 /* Cases 0, 1, 2, 3, 5 (D only). */
6238 if (skip_past_comma (&ptr
) == FAIL
)
6241 inst
.operands
[i
].reg
= val
;
6242 inst
.operands
[i
].isreg
= 1;
6243 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6244 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6245 inst
.operands
[i
].isvec
= 1;
6246 inst
.operands
[i
].vectype
= optype
;
6247 inst
.operands
[i
++].present
= 1;
6249 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6251 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6252 Case 13: VMOV <Sd>, <Rm> */
6253 inst
.operands
[i
].reg
= val
;
6254 inst
.operands
[i
].isreg
= 1;
6255 inst
.operands
[i
].present
= 1;
6257 if (rtype
== REG_TYPE_NQ
)
6259 first_error (_("can't use Neon quad register here"));
6262 else if (rtype
!= REG_TYPE_VFS
)
6265 if (skip_past_comma (&ptr
) == FAIL
)
6267 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6269 inst
.operands
[i
].reg
= val
;
6270 inst
.operands
[i
].isreg
= 1;
6271 inst
.operands
[i
].present
= 1;
6274 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6277 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6278 Case 1: VMOV<c><q> <Dd>, <Dm>
6279 Case 8: VMOV.F32 <Sd>, <Sm>
6280 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6282 inst
.operands
[i
].reg
= val
;
6283 inst
.operands
[i
].isreg
= 1;
6284 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6285 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6286 inst
.operands
[i
].isvec
= 1;
6287 inst
.operands
[i
].vectype
= optype
;
6288 inst
.operands
[i
].present
= 1;
6290 if (skip_past_comma (&ptr
) == SUCCESS
)
6295 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6298 inst
.operands
[i
].reg
= val
;
6299 inst
.operands
[i
].isreg
= 1;
6300 inst
.operands
[i
++].present
= 1;
6302 if (skip_past_comma (&ptr
) == FAIL
)
6305 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6308 inst
.operands
[i
].reg
= val
;
6309 inst
.operands
[i
].isreg
= 1;
6310 inst
.operands
[i
].present
= 1;
6313 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6314 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6315 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6316 Case 10: VMOV.F32 <Sd>, #<imm>
6317 Case 11: VMOV.F64 <Dd>, #<imm> */
6318 inst
.operands
[i
].immisfloat
= 1;
6319 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6321 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6322 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6326 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6330 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6333 inst
.operands
[i
].reg
= val
;
6334 inst
.operands
[i
].isreg
= 1;
6335 inst
.operands
[i
++].present
= 1;
6337 if (skip_past_comma (&ptr
) == FAIL
)
6340 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6342 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6343 inst
.operands
[i
].reg
= val
;
6344 inst
.operands
[i
].isscalar
= 1;
6345 inst
.operands
[i
].present
= 1;
6346 inst
.operands
[i
].vectype
= optype
;
6348 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6350 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6351 inst
.operands
[i
].reg
= val
;
6352 inst
.operands
[i
].isreg
= 1;
6353 inst
.operands
[i
++].present
= 1;
6355 if (skip_past_comma (&ptr
) == FAIL
)
6358 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6361 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6365 inst
.operands
[i
].reg
= val
;
6366 inst
.operands
[i
].isreg
= 1;
6367 inst
.operands
[i
].isvec
= 1;
6368 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6369 inst
.operands
[i
].vectype
= optype
;
6370 inst
.operands
[i
].present
= 1;
6372 if (rtype
== REG_TYPE_VFS
)
6376 if (skip_past_comma (&ptr
) == FAIL
)
6378 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6381 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6384 inst
.operands
[i
].reg
= val
;
6385 inst
.operands
[i
].isreg
= 1;
6386 inst
.operands
[i
].isvec
= 1;
6387 inst
.operands
[i
].issingle
= 1;
6388 inst
.operands
[i
].vectype
= optype
;
6389 inst
.operands
[i
].present
= 1;
6392 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6396 inst
.operands
[i
].reg
= val
;
6397 inst
.operands
[i
].isreg
= 1;
6398 inst
.operands
[i
].isvec
= 1;
6399 inst
.operands
[i
].issingle
= 1;
6400 inst
.operands
[i
].vectype
= optype
;
6401 inst
.operands
[i
].present
= 1;
6406 first_error (_("parse error"));
6410 /* Successfully parsed the operands. Update args. */
6416 first_error (_("expected comma"));
6420 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6424 /* Use this macro when the operand constraints are different
6425 for ARM and THUMB (e.g. ldrd). */
6426 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6427 ((arm_operand) | ((thumb_operand) << 16))
6429 /* Matcher codes for parse_operands. */
6430 enum operand_parse_code
6432 OP_stop
, /* end of line */
6434 OP_RR
, /* ARM register */
6435 OP_RRnpc
, /* ARM register, not r15 */
6436 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6437 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6438 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6439 optional trailing ! */
6440 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6441 OP_RCP
, /* Coprocessor number */
6442 OP_RCN
, /* Coprocessor register */
6443 OP_RF
, /* FPA register */
6444 OP_RVS
, /* VFP single precision register */
6445 OP_RVD
, /* VFP double precision register (0..15) */
6446 OP_RND
, /* Neon double precision register (0..31) */
6447 OP_RNQ
, /* Neon quad precision register */
6448 OP_RVSD
, /* VFP single or double precision register */
6449 OP_RNDQ
, /* Neon double or quad precision register */
6450 OP_RNSDQ
, /* Neon single, double or quad precision register */
6451 OP_RNSC
, /* Neon scalar D[X] */
6452 OP_RVC
, /* VFP control register */
6453 OP_RMF
, /* Maverick F register */
6454 OP_RMD
, /* Maverick D register */
6455 OP_RMFX
, /* Maverick FX register */
6456 OP_RMDX
, /* Maverick DX register */
6457 OP_RMAX
, /* Maverick AX register */
6458 OP_RMDS
, /* Maverick DSPSC register */
6459 OP_RIWR
, /* iWMMXt wR register */
6460 OP_RIWC
, /* iWMMXt wC register */
6461 OP_RIWG
, /* iWMMXt wCG register */
6462 OP_RXA
, /* XScale accumulator register */
6464 OP_REGLST
, /* ARM register list */
6465 OP_VRSLST
, /* VFP single-precision register list */
6466 OP_VRDLST
, /* VFP double-precision register list */
6467 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6468 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6469 OP_NSTRLST
, /* Neon element/structure list */
6471 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6472 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6473 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6474 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6475 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6476 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6477 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6478 OP_VMOV
, /* Neon VMOV operands. */
6479 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6480 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6481 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6483 OP_I0
, /* immediate zero */
6484 OP_I7
, /* immediate value 0 .. 7 */
6485 OP_I15
, /* 0 .. 15 */
6486 OP_I16
, /* 1 .. 16 */
6487 OP_I16z
, /* 0 .. 16 */
6488 OP_I31
, /* 0 .. 31 */
6489 OP_I31w
, /* 0 .. 31, optional trailing ! */
6490 OP_I32
, /* 1 .. 32 */
6491 OP_I32z
, /* 0 .. 32 */
6492 OP_I63
, /* 0 .. 63 */
6493 OP_I63s
, /* -64 .. 63 */
6494 OP_I64
, /* 1 .. 64 */
6495 OP_I64z
, /* 0 .. 64 */
6496 OP_I255
, /* 0 .. 255 */
6498 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6499 OP_I7b
, /* 0 .. 7 */
6500 OP_I15b
, /* 0 .. 15 */
6501 OP_I31b
, /* 0 .. 31 */
6503 OP_SH
, /* shifter operand */
6504 OP_SHG
, /* shifter operand with possible group relocation */
6505 OP_ADDR
, /* Memory address expression (any mode) */
6506 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6507 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6508 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6509 OP_EXP
, /* arbitrary expression */
6510 OP_EXPi
, /* same, with optional immediate prefix */
6511 OP_EXPr
, /* same, with optional relocation suffix */
6512 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6514 OP_CPSF
, /* CPS flags */
6515 OP_ENDI
, /* Endianness specifier */
6516 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6517 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6518 OP_COND
, /* conditional code */
6519 OP_TB
, /* Table branch. */
6521 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6523 OP_RRnpc_I0
, /* ARM register or literal 0 */
6524 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6525 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6526 OP_RF_IF
, /* FPA register or immediate */
6527 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6528 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6530 /* Optional operands. */
6531 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6532 OP_oI31b
, /* 0 .. 31 */
6533 OP_oI32b
, /* 1 .. 32 */
6534 OP_oI32z
, /* 0 .. 32 */
6535 OP_oIffffb
, /* 0 .. 65535 */
6536 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6538 OP_oRR
, /* ARM register */
6539 OP_oRRnpc
, /* ARM register, not the PC */
6540 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6541 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6542 OP_oRND
, /* Optional Neon double precision register */
6543 OP_oRNQ
, /* Optional Neon quad precision register */
6544 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6545 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6546 OP_oSHll
, /* LSL immediate */
6547 OP_oSHar
, /* ASR immediate */
6548 OP_oSHllar
, /* LSL or ASR immediate */
6549 OP_oROR
, /* ROR 0/8/16/24 */
6550 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6552 /* Some pre-defined mixed (ARM/THUMB) operands. */
6553 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6554 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6555 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6557 OP_FIRST_OPTIONAL
= OP_oI7b
6560 /* Generic instruction operand parser. This does no encoding and no
6561 semantic validation; it merely squirrels values away in the inst
6562 structure. Returns SUCCESS or FAIL depending on whether the
6563 specified grammar matched. */
6565 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6567 unsigned const int *upat
= pattern
;
6568 char *backtrack_pos
= 0;
6569 const char *backtrack_error
= 0;
6570 int i
, val
= 0, backtrack_index
= 0;
6571 enum arm_reg_type rtype
;
6572 parse_operand_result result
;
6573 unsigned int op_parse_code
;
6575 #define po_char_or_fail(chr) \
6578 if (skip_past_char (&str, chr) == FAIL) \
6583 #define po_reg_or_fail(regtype) \
6586 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6587 & inst.operands[i].vectype); \
6590 first_error (_(reg_expected_msgs[regtype])); \
6593 inst.operands[i].reg = val; \
6594 inst.operands[i].isreg = 1; \
6595 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6596 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6597 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6598 || rtype == REG_TYPE_VFD \
6599 || rtype == REG_TYPE_NQ); \
6603 #define po_reg_or_goto(regtype, label) \
6606 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6607 & inst.operands[i].vectype); \
6611 inst.operands[i].reg = val; \
6612 inst.operands[i].isreg = 1; \
6613 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6614 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6615 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6616 || rtype == REG_TYPE_VFD \
6617 || rtype == REG_TYPE_NQ); \
6621 #define po_imm_or_fail(min, max, popt) \
6624 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6626 inst.operands[i].imm = val; \
6630 #define po_scalar_or_goto(elsz, label) \
6633 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6636 inst.operands[i].reg = val; \
6637 inst.operands[i].isscalar = 1; \
6641 #define po_misc_or_fail(expr) \
6649 #define po_misc_or_fail_no_backtrack(expr) \
6653 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6654 backtrack_pos = 0; \
6655 if (result != PARSE_OPERAND_SUCCESS) \
6660 #define po_barrier_or_imm(str) \
6663 val = parse_barrier (&str); \
6664 if (val == FAIL && ! ISALPHA (*str)) \
6667 /* ISB can only take SY as an option. */ \
6668 || ((inst.instruction & 0xf0) == 0x60 \
6671 inst.error = _("invalid barrier type"); \
6672 backtrack_pos = 0; \
6678 skip_whitespace (str
);
6680 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6682 op_parse_code
= upat
[i
];
6683 if (op_parse_code
>= 1<<16)
6684 op_parse_code
= thumb
? (op_parse_code
>> 16)
6685 : (op_parse_code
& ((1<<16)-1));
6687 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6689 /* Remember where we are in case we need to backtrack. */
6690 gas_assert (!backtrack_pos
);
6691 backtrack_pos
= str
;
6692 backtrack_error
= inst
.error
;
6693 backtrack_index
= i
;
6696 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6697 po_char_or_fail (',');
6699 switch (op_parse_code
)
6707 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6708 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6709 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6710 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6711 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6712 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6714 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6716 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6718 /* Also accept generic coprocessor regs for unknown registers. */
6720 po_reg_or_fail (REG_TYPE_CN
);
6722 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6723 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6724 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6725 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6726 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6727 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6728 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6729 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6730 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6731 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6733 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6735 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6736 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6738 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6740 /* Neon scalar. Using an element size of 8 means that some invalid
6741 scalars are accepted here, so deal with those in later code. */
6742 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6746 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6749 po_imm_or_fail (0, 0, TRUE
);
6754 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6759 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6762 if (parse_ifimm_zero (&str
))
6763 inst
.operands
[i
].imm
= 0;
6767 = _("only floating point zero is allowed as immediate value");
6775 po_scalar_or_goto (8, try_rr
);
6778 po_reg_or_fail (REG_TYPE_RN
);
6784 po_scalar_or_goto (8, try_nsdq
);
6787 po_reg_or_fail (REG_TYPE_NSDQ
);
6793 po_scalar_or_goto (8, try_ndq
);
6796 po_reg_or_fail (REG_TYPE_NDQ
);
6802 po_scalar_or_goto (8, try_vfd
);
6805 po_reg_or_fail (REG_TYPE_VFD
);
6810 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6811 not careful then bad things might happen. */
6812 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6817 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6820 /* There's a possibility of getting a 64-bit immediate here, so
6821 we need special handling. */
6822 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6825 inst
.error
= _("immediate value is out of range");
6833 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6836 po_imm_or_fail (0, 63, TRUE
);
6841 po_char_or_fail ('[');
6842 po_reg_or_fail (REG_TYPE_RN
);
6843 po_char_or_fail (']');
6849 po_reg_or_fail (REG_TYPE_RN
);
6850 if (skip_past_char (&str
, '!') == SUCCESS
)
6851 inst
.operands
[i
].writeback
= 1;
6855 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6856 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6857 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6858 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6859 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6860 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6861 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6862 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6863 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6864 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6865 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6866 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6868 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6870 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6871 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6873 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6874 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6875 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6876 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6878 /* Immediate variants */
6880 po_char_or_fail ('{');
6881 po_imm_or_fail (0, 255, TRUE
);
6882 po_char_or_fail ('}');
6886 /* The expression parser chokes on a trailing !, so we have
6887 to find it first and zap it. */
6890 while (*s
&& *s
!= ',')
6895 inst
.operands
[i
].writeback
= 1;
6897 po_imm_or_fail (0, 31, TRUE
);
6905 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6910 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6915 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6917 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6919 val
= parse_reloc (&str
);
6922 inst
.error
= _("unrecognized relocation suffix");
6925 else if (val
!= BFD_RELOC_UNUSED
)
6927 inst
.operands
[i
].imm
= val
;
6928 inst
.operands
[i
].hasreloc
= 1;
6933 /* Operand for MOVW or MOVT. */
6935 po_misc_or_fail (parse_half (&str
));
6938 /* Register or expression. */
6939 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6940 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6942 /* Register or immediate. */
6943 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6944 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6946 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6948 if (!is_immediate_prefix (*str
))
6951 val
= parse_fpa_immediate (&str
);
6954 /* FPA immediates are encoded as registers 8-15.
6955 parse_fpa_immediate has already applied the offset. */
6956 inst
.operands
[i
].reg
= val
;
6957 inst
.operands
[i
].isreg
= 1;
6960 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6961 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6963 /* Two kinds of register. */
6966 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6968 || (rege
->type
!= REG_TYPE_MMXWR
6969 && rege
->type
!= REG_TYPE_MMXWC
6970 && rege
->type
!= REG_TYPE_MMXWCG
))
6972 inst
.error
= _("iWMMXt data or control register expected");
6975 inst
.operands
[i
].reg
= rege
->number
;
6976 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6982 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6984 || (rege
->type
!= REG_TYPE_MMXWC
6985 && rege
->type
!= REG_TYPE_MMXWCG
))
6987 inst
.error
= _("iWMMXt control register expected");
6990 inst
.operands
[i
].reg
= rege
->number
;
6991 inst
.operands
[i
].isreg
= 1;
6996 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6997 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6998 case OP_oROR
: val
= parse_ror (&str
); break;
6999 case OP_COND
: val
= parse_cond (&str
); break;
7000 case OP_oBARRIER_I15
:
7001 po_barrier_or_imm (str
); break;
7003 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7009 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7010 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7012 inst
.error
= _("Banked registers are not available with this "
7018 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7022 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7025 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7027 if (strncasecmp (str
, "APSR_", 5) == 0)
7034 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7035 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7036 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7037 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7038 default: found
= 16;
7042 inst
.operands
[i
].isvec
= 1;
7043 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7044 inst
.operands
[i
].reg
= REG_PC
;
7051 po_misc_or_fail (parse_tb (&str
));
7054 /* Register lists. */
7056 val
= parse_reg_list (&str
);
7059 inst
.operands
[i
].writeback
= 1;
7065 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7069 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7073 /* Allow Q registers too. */
7074 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7079 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7081 inst
.operands
[i
].issingle
= 1;
7086 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7091 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7092 &inst
.operands
[i
].vectype
);
7095 /* Addressing modes */
7097 po_misc_or_fail (parse_address (&str
, i
));
7101 po_misc_or_fail_no_backtrack (
7102 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7106 po_misc_or_fail_no_backtrack (
7107 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7111 po_misc_or_fail_no_backtrack (
7112 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7116 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7120 po_misc_or_fail_no_backtrack (
7121 parse_shifter_operand_group_reloc (&str
, i
));
7125 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7129 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7133 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7137 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7140 /* Various value-based sanity checks and shared operations. We
7141 do not signal immediate failures for the register constraints;
7142 this allows a syntax error to take precedence. */
7143 switch (op_parse_code
)
7151 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7152 inst
.error
= BAD_PC
;
7157 if (inst
.operands
[i
].isreg
)
7159 if (inst
.operands
[i
].reg
== REG_PC
)
7160 inst
.error
= BAD_PC
;
7161 else if (inst
.operands
[i
].reg
== REG_SP
)
7162 inst
.error
= BAD_SP
;
7167 if (inst
.operands
[i
].isreg
7168 && inst
.operands
[i
].reg
== REG_PC
7169 && (inst
.operands
[i
].writeback
|| thumb
))
7170 inst
.error
= BAD_PC
;
7179 case OP_oBARRIER_I15
:
7188 inst
.operands
[i
].imm
= val
;
7195 /* If we get here, this operand was successfully parsed. */
7196 inst
.operands
[i
].present
= 1;
7200 inst
.error
= BAD_ARGS
;
7205 /* The parse routine should already have set inst.error, but set a
7206 default here just in case. */
7208 inst
.error
= _("syntax error");
7212 /* Do not backtrack over a trailing optional argument that
7213 absorbed some text. We will only fail again, with the
7214 'garbage following instruction' error message, which is
7215 probably less helpful than the current one. */
7216 if (backtrack_index
== i
&& backtrack_pos
!= str
7217 && upat
[i
+1] == OP_stop
)
7220 inst
.error
= _("syntax error");
7224 /* Try again, skipping the optional argument at backtrack_pos. */
7225 str
= backtrack_pos
;
7226 inst
.error
= backtrack_error
;
7227 inst
.operands
[backtrack_index
].present
= 0;
7228 i
= backtrack_index
;
7232 /* Check that we have parsed all the arguments. */
7233 if (*str
!= '\0' && !inst
.error
)
7234 inst
.error
= _("garbage following instruction");
7236 return inst
.error
? FAIL
: SUCCESS
;
7239 #undef po_char_or_fail
7240 #undef po_reg_or_fail
7241 #undef po_reg_or_goto
7242 #undef po_imm_or_fail
7243 #undef po_scalar_or_fail
7244 #undef po_barrier_or_imm
7246 /* Shorthand macro for instruction encoding functions issuing errors. */
7247 #define constraint(expr, err) \
7258 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7259 instructions are unpredictable if these registers are used. This
7260 is the BadReg predicate in ARM's Thumb-2 documentation. */
7261 #define reject_bad_reg(reg) \
7263 if (reg == REG_SP || reg == REG_PC) \
7265 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7270 /* If REG is R13 (the stack pointer), warn that its use is
7272 #define warn_deprecated_sp(reg) \
7274 if (warn_on_deprecated && reg == REG_SP) \
7275 as_tsktsk (_("use of r13 is deprecated")); \
7278 /* Functions for operand encoding. ARM, then Thumb. */
7280 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7282 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7284 The only binary encoding difference is the Coprocessor number. Coprocessor
7285 9 is used for half-precision calculations or conversions. The format of the
7286 instruction is the same as the equivalent Coprocessor 10 instuction that
7287 exists for Single-Precision operation. */
7290 do_scalar_fp16_v82_encode (void)
7292 if (inst
.cond
!= COND_ALWAYS
)
7293 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7294 " the behaviour is UNPREDICTABLE"));
7295 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7298 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7299 mark_feature_used (&arm_ext_fp16
);
7302 /* If VAL can be encoded in the immediate field of an ARM instruction,
7303 return the encoded form. Otherwise, return FAIL. */
7306 encode_arm_immediate (unsigned int val
)
7313 for (i
= 2; i
< 32; i
+= 2)
7314 if ((a
= rotate_left (val
, i
)) <= 0xff)
7315 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7320 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7321 return the encoded form. Otherwise, return FAIL. */
7323 encode_thumb32_immediate (unsigned int val
)
7330 for (i
= 1; i
<= 24; i
++)
7333 if ((val
& ~(0xff << i
)) == 0)
7334 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7338 if (val
== ((a
<< 16) | a
))
7340 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7344 if (val
== ((a
<< 16) | a
))
7345 return 0x200 | (a
>> 8);
7349 /* Encode a VFP SP or DP register number into inst.instruction. */
7352 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7354 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7357 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7360 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7363 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7368 first_error (_("D register out of range for selected VFP version"));
7376 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7380 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7384 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7388 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7392 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7396 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7404 /* Encode a <shift> in an ARM-format instruction. The immediate,
7405 if any, is handled by md_apply_fix. */
7407 encode_arm_shift (int i
)
7409 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7410 inst
.instruction
|= SHIFT_ROR
<< 5;
7413 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7414 if (inst
.operands
[i
].immisreg
)
7416 inst
.instruction
|= SHIFT_BY_REG
;
7417 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7420 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7425 encode_arm_shifter_operand (int i
)
7427 if (inst
.operands
[i
].isreg
)
7429 inst
.instruction
|= inst
.operands
[i
].reg
;
7430 encode_arm_shift (i
);
7434 inst
.instruction
|= INST_IMMEDIATE
;
7435 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7436 inst
.instruction
|= inst
.operands
[i
].imm
;
7440 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7442 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7445 Generate an error if the operand is not a register. */
7446 constraint (!inst
.operands
[i
].isreg
,
7447 _("Instruction does not support =N addresses"));
7449 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7451 if (inst
.operands
[i
].preind
)
7455 inst
.error
= _("instruction does not accept preindexed addressing");
7458 inst
.instruction
|= PRE_INDEX
;
7459 if (inst
.operands
[i
].writeback
)
7460 inst
.instruction
|= WRITE_BACK
;
7463 else if (inst
.operands
[i
].postind
)
7465 gas_assert (inst
.operands
[i
].writeback
);
7467 inst
.instruction
|= WRITE_BACK
;
7469 else /* unindexed - only for coprocessor */
7471 inst
.error
= _("instruction does not accept unindexed addressing");
7475 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7476 && (((inst
.instruction
& 0x000f0000) >> 16)
7477 == ((inst
.instruction
& 0x0000f000) >> 12)))
7478 as_warn ((inst
.instruction
& LOAD_BIT
)
7479 ? _("destination register same as write-back base")
7480 : _("source register same as write-back base"));
7483 /* inst.operands[i] was set up by parse_address. Encode it into an
7484 ARM-format mode 2 load or store instruction. If is_t is true,
7485 reject forms that cannot be used with a T instruction (i.e. not
7488 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7490 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7492 encode_arm_addr_mode_common (i
, is_t
);
7494 if (inst
.operands
[i
].immisreg
)
7496 constraint ((inst
.operands
[i
].imm
== REG_PC
7497 || (is_pc
&& inst
.operands
[i
].writeback
)),
7499 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7500 inst
.instruction
|= inst
.operands
[i
].imm
;
7501 if (!inst
.operands
[i
].negative
)
7502 inst
.instruction
|= INDEX_UP
;
7503 if (inst
.operands
[i
].shifted
)
7505 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7506 inst
.instruction
|= SHIFT_ROR
<< 5;
7509 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7510 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7514 else /* immediate offset in inst.reloc */
7516 if (is_pc
&& !inst
.reloc
.pc_rel
)
7518 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7520 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7521 cannot use PC in addressing.
7522 PC cannot be used in writeback addressing, either. */
7523 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7526 /* Use of PC in str is deprecated for ARMv7. */
7527 if (warn_on_deprecated
7529 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7530 as_tsktsk (_("use of PC in this instruction is deprecated"));
7533 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7535 /* Prefer + for zero encoded value. */
7536 if (!inst
.operands
[i
].negative
)
7537 inst
.instruction
|= INDEX_UP
;
7538 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7543 /* inst.operands[i] was set up by parse_address. Encode it into an
7544 ARM-format mode 3 load or store instruction. Reject forms that
7545 cannot be used with such instructions. If is_t is true, reject
7546 forms that cannot be used with a T instruction (i.e. not
7549 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7551 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7553 inst
.error
= _("instruction does not accept scaled register index");
7557 encode_arm_addr_mode_common (i
, is_t
);
7559 if (inst
.operands
[i
].immisreg
)
7561 constraint ((inst
.operands
[i
].imm
== REG_PC
7562 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7564 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7566 inst
.instruction
|= inst
.operands
[i
].imm
;
7567 if (!inst
.operands
[i
].negative
)
7568 inst
.instruction
|= INDEX_UP
;
7570 else /* immediate offset in inst.reloc */
7572 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7573 && inst
.operands
[i
].writeback
),
7575 inst
.instruction
|= HWOFFSET_IMM
;
7576 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7578 /* Prefer + for zero encoded value. */
7579 if (!inst
.operands
[i
].negative
)
7580 inst
.instruction
|= INDEX_UP
;
7582 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7587 /* Write immediate bits [7:0] to the following locations:
7589 |28/24|23 19|18 16|15 4|3 0|
7590 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7592 This function is used by VMOV/VMVN/VORR/VBIC. */
7595 neon_write_immbits (unsigned immbits
)
7597 inst
.instruction
|= immbits
& 0xf;
7598 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7599 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7602 /* Invert low-order SIZE bits of XHI:XLO. */
7605 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7607 unsigned immlo
= xlo
? *xlo
: 0;
7608 unsigned immhi
= xhi
? *xhi
: 0;
7613 immlo
= (~immlo
) & 0xff;
7617 immlo
= (~immlo
) & 0xffff;
7621 immhi
= (~immhi
) & 0xffffffff;
7625 immlo
= (~immlo
) & 0xffffffff;
7639 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7643 neon_bits_same_in_bytes (unsigned imm
)
7645 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7646 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7647 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7648 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7651 /* For immediate of above form, return 0bABCD. */
7654 neon_squash_bits (unsigned imm
)
7656 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7657 | ((imm
& 0x01000000) >> 21);
7660 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7663 neon_qfloat_bits (unsigned imm
)
7665 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7668 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7669 the instruction. *OP is passed as the initial value of the op field, and
7670 may be set to a different value depending on the constant (i.e.
7671 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7672 MVN). If the immediate looks like a repeated pattern then also
7673 try smaller element sizes. */
7676 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7677 unsigned *immbits
, int *op
, int size
,
7678 enum neon_el_type type
)
7680 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7682 if (type
== NT_float
&& !float_p
)
7685 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7687 if (size
!= 32 || *op
== 1)
7689 *immbits
= neon_qfloat_bits (immlo
);
7695 if (neon_bits_same_in_bytes (immhi
)
7696 && neon_bits_same_in_bytes (immlo
))
7700 *immbits
= (neon_squash_bits (immhi
) << 4)
7701 | neon_squash_bits (immlo
);
7712 if (immlo
== (immlo
& 0x000000ff))
7717 else if (immlo
== (immlo
& 0x0000ff00))
7719 *immbits
= immlo
>> 8;
7722 else if (immlo
== (immlo
& 0x00ff0000))
7724 *immbits
= immlo
>> 16;
7727 else if (immlo
== (immlo
& 0xff000000))
7729 *immbits
= immlo
>> 24;
7732 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7734 *immbits
= (immlo
>> 8) & 0xff;
7737 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7739 *immbits
= (immlo
>> 16) & 0xff;
7743 if ((immlo
& 0xffff) != (immlo
>> 16))
7750 if (immlo
== (immlo
& 0x000000ff))
7755 else if (immlo
== (immlo
& 0x0000ff00))
7757 *immbits
= immlo
>> 8;
7761 if ((immlo
& 0xff) != (immlo
>> 8))
7766 if (immlo
== (immlo
& 0x000000ff))
7768 /* Don't allow MVN with 8-bit immediate. */
7778 #if defined BFD_HOST_64_BIT
7779 /* Returns TRUE if double precision value V may be cast
7780 to single precision without loss of accuracy. */
7783 is_double_a_single (bfd_int64_t v
)
7785 int exp
= (int)((v
>> 52) & 0x7FF);
7786 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7788 return (exp
== 0 || exp
== 0x7FF
7789 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7790 && (mantissa
& 0x1FFFFFFFl
) == 0;
7793 /* Returns a double precision value casted to single precision
7794 (ignoring the least significant bits in exponent and mantissa). */
7797 double_to_single (bfd_int64_t v
)
7799 int sign
= (int) ((v
>> 63) & 1l);
7800 int exp
= (int) ((v
>> 52) & 0x7FF);
7801 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7807 exp
= exp
- 1023 + 127;
7816 /* No denormalized numbers. */
7822 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7824 #endif /* BFD_HOST_64_BIT */
7833 static void do_vfp_nsyn_opcode (const char *);
7835 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7836 Determine whether it can be performed with a move instruction; if
7837 it can, convert inst.instruction to that move instruction and
7838 return TRUE; if it can't, convert inst.instruction to a literal-pool
7839 load and return FALSE. If this is not a valid thing to do in the
7840 current context, set inst.error and return TRUE.
7842 inst.operands[i] describes the destination register. */
7845 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7848 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7849 bfd_boolean arm_p
= (t
== CONST_ARM
);
7852 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7856 if ((inst
.instruction
& tbit
) == 0)
7858 inst
.error
= _("invalid pseudo operation");
7862 if (inst
.reloc
.exp
.X_op
!= O_constant
7863 && inst
.reloc
.exp
.X_op
!= O_symbol
7864 && inst
.reloc
.exp
.X_op
!= O_big
)
7866 inst
.error
= _("constant expression expected");
7870 if (inst
.reloc
.exp
.X_op
== O_constant
7871 || inst
.reloc
.exp
.X_op
== O_big
)
7873 #if defined BFD_HOST_64_BIT
7878 if (inst
.reloc
.exp
.X_op
== O_big
)
7880 LITTLENUM_TYPE w
[X_PRECISION
];
7883 if (inst
.reloc
.exp
.X_add_number
== -1)
7885 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
7887 /* FIXME: Should we check words w[2..5] ? */
7892 #if defined BFD_HOST_64_BIT
7894 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
7895 << LITTLENUM_NUMBER_OF_BITS
)
7896 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
7897 << LITTLENUM_NUMBER_OF_BITS
)
7898 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
7899 << LITTLENUM_NUMBER_OF_BITS
)
7900 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
7902 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
7903 | (l
[0] & LITTLENUM_MASK
);
7907 v
= inst
.reloc
.exp
.X_add_number
;
7909 if (!inst
.operands
[i
].issingle
)
7913 /* This can be encoded only for a low register. */
7914 if ((v
& ~0xFF) == 0 && (inst
.operands
[i
].reg
< 8))
7916 /* This can be done with a mov(1) instruction. */
7917 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7918 inst
.instruction
|= v
;
7922 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
7923 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7925 /* Check if on thumb2 it can be done with a mov.w, mvn or
7926 movw instruction. */
7927 unsigned int newimm
;
7928 bfd_boolean isNegated
;
7930 newimm
= encode_thumb32_immediate (v
);
7931 if (newimm
!= (unsigned int) FAIL
)
7935 newimm
= encode_thumb32_immediate (~v
);
7936 if (newimm
!= (unsigned int) FAIL
)
7940 /* The number can be loaded with a mov.w or mvn
7942 if (newimm
!= (unsigned int) FAIL
7943 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
7945 inst
.instruction
= (0xf04f0000 /* MOV.W. */
7946 | (inst
.operands
[i
].reg
<< 8));
7947 /* Change to MOVN. */
7948 inst
.instruction
|= (isNegated
? 0x200000 : 0);
7949 inst
.instruction
|= (newimm
& 0x800) << 15;
7950 inst
.instruction
|= (newimm
& 0x700) << 4;
7951 inst
.instruction
|= (newimm
& 0x0ff);
7954 /* The number can be loaded with a movw instruction. */
7955 else if ((v
& ~0xFFFF) == 0
7956 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
7958 int imm
= v
& 0xFFFF;
7960 inst
.instruction
= 0xf2400000; /* MOVW. */
7961 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
7962 inst
.instruction
|= (imm
& 0xf000) << 4;
7963 inst
.instruction
|= (imm
& 0x0800) << 15;
7964 inst
.instruction
|= (imm
& 0x0700) << 4;
7965 inst
.instruction
|= (imm
& 0x00ff);
7972 int value
= encode_arm_immediate (v
);
7976 /* This can be done with a mov instruction. */
7977 inst
.instruction
&= LITERAL_MASK
;
7978 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7979 inst
.instruction
|= value
& 0xfff;
7983 value
= encode_arm_immediate (~ v
);
7986 /* This can be done with a mvn instruction. */
7987 inst
.instruction
&= LITERAL_MASK
;
7988 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7989 inst
.instruction
|= value
& 0xfff;
7993 else if (t
== CONST_VEC
)
7996 unsigned immbits
= 0;
7997 unsigned immlo
= inst
.operands
[1].imm
;
7998 unsigned immhi
= inst
.operands
[1].regisimm
7999 ? inst
.operands
[1].reg
8000 : inst
.reloc
.exp
.X_unsigned
8002 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8003 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8004 &op
, 64, NT_invtype
);
8008 neon_invert_size (&immlo
, &immhi
, 64);
8010 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8011 &op
, 64, NT_invtype
);
8016 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8022 /* Fill other bits in vmov encoding for both thumb and arm. */
8024 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8026 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8027 neon_write_immbits (immbits
);
8035 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8036 if (inst
.operands
[i
].issingle
8037 && is_quarter_float (inst
.operands
[1].imm
)
8038 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8040 inst
.operands
[1].imm
=
8041 neon_qfloat_bits (v
);
8042 do_vfp_nsyn_opcode ("fconsts");
8046 /* If our host does not support a 64-bit type then we cannot perform
8047 the following optimization. This mean that there will be a
8048 discrepancy between the output produced by an assembler built for
8049 a 32-bit-only host and the output produced from a 64-bit host, but
8050 this cannot be helped. */
8051 #if defined BFD_HOST_64_BIT
8052 else if (!inst
.operands
[1].issingle
8053 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8055 if (is_double_a_single (v
)
8056 && is_quarter_float (double_to_single (v
)))
8058 inst
.operands
[1].imm
=
8059 neon_qfloat_bits (double_to_single (v
));
8060 do_vfp_nsyn_opcode ("fconstd");
8068 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8069 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8072 inst
.operands
[1].reg
= REG_PC
;
8073 inst
.operands
[1].isreg
= 1;
8074 inst
.operands
[1].preind
= 1;
8075 inst
.reloc
.pc_rel
= 1;
8076 inst
.reloc
.type
= (thumb_p
8077 ? BFD_RELOC_ARM_THUMB_OFFSET
8079 ? BFD_RELOC_ARM_HWLITERAL
8080 : BFD_RELOC_ARM_LITERAL
));
8084 /* inst.operands[i] was set up by parse_address. Encode it into an
8085 ARM-format instruction. Reject all forms which cannot be encoded
8086 into a coprocessor load/store instruction. If wb_ok is false,
8087 reject use of writeback; if unind_ok is false, reject use of
8088 unindexed addressing. If reloc_override is not 0, use it instead
8089 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8090 (in which case it is preserved). */
8093 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8095 if (!inst
.operands
[i
].isreg
)
8098 if (! inst
.operands
[0].isvec
)
8100 inst
.error
= _("invalid co-processor operand");
8103 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8107 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8109 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8111 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8113 gas_assert (!inst
.operands
[i
].writeback
);
8116 inst
.error
= _("instruction does not support unindexed addressing");
8119 inst
.instruction
|= inst
.operands
[i
].imm
;
8120 inst
.instruction
|= INDEX_UP
;
8124 if (inst
.operands
[i
].preind
)
8125 inst
.instruction
|= PRE_INDEX
;
8127 if (inst
.operands
[i
].writeback
)
8129 if (inst
.operands
[i
].reg
== REG_PC
)
8131 inst
.error
= _("pc may not be used with write-back");
8136 inst
.error
= _("instruction does not support writeback");
8139 inst
.instruction
|= WRITE_BACK
;
8143 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8144 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8145 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8146 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8149 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8151 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8154 /* Prefer + for zero encoded value. */
8155 if (!inst
.operands
[i
].negative
)
8156 inst
.instruction
|= INDEX_UP
;
8161 /* Functions for instruction encoding, sorted by sub-architecture.
8162 First some generics; their names are taken from the conventional
8163 bit positions for register arguments in ARM format instructions. */
8173 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8180 inst
.instruction
|= inst
.operands
[1].reg
;
8186 inst
.instruction
|= inst
.operands
[0].reg
;
8187 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8193 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8194 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8200 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8201 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8207 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8208 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8212 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8214 if (ARM_CPU_IS_ANY (cpu_variant
))
8216 as_tsktsk ("%s", msg
);
8219 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8231 unsigned Rn
= inst
.operands
[2].reg
;
8232 /* Enforce restrictions on SWP instruction. */
8233 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8235 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8236 _("Rn must not overlap other operands"));
8238 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8240 if (!check_obsolete (&arm_ext_v8
,
8241 _("swp{b} use is obsoleted for ARMv8 and later"))
8242 && warn_on_deprecated
8243 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8244 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8247 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8248 inst
.instruction
|= inst
.operands
[1].reg
;
8249 inst
.instruction
|= Rn
<< 16;
8255 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8256 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8257 inst
.instruction
|= inst
.operands
[2].reg
;
8263 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8264 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8265 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8266 || inst
.reloc
.exp
.X_add_number
!= 0),
8268 inst
.instruction
|= inst
.operands
[0].reg
;
8269 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8270 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8276 inst
.instruction
|= inst
.operands
[0].imm
;
8282 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8283 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8286 /* ARM instructions, in alphabetical order by function name (except
8287 that wrapper functions appear immediately after the function they
8290 /* This is a pseudo-op of the form "adr rd, label" to be converted
8291 into a relative address of the form "add rd, pc, #label-.-8". */
8296 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8298 /* Frag hacking will turn this into a sub instruction if the offset turns
8299 out to be negative. */
8300 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8301 inst
.reloc
.pc_rel
= 1;
8302 inst
.reloc
.exp
.X_add_number
-= 8;
8305 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8306 into a relative address of the form:
8307 add rd, pc, #low(label-.-8)"
8308 add rd, rd, #high(label-.-8)" */
8313 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8315 /* Frag hacking will turn this into a sub instruction if the offset turns
8316 out to be negative. */
8317 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8318 inst
.reloc
.pc_rel
= 1;
8319 inst
.size
= INSN_SIZE
* 2;
8320 inst
.reloc
.exp
.X_add_number
-= 8;
8326 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8327 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8329 if (!inst
.operands
[1].present
)
8330 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8332 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8333 encode_arm_shifter_operand (2);
8339 if (inst
.operands
[0].present
)
8340 inst
.instruction
|= inst
.operands
[0].imm
;
8342 inst
.instruction
|= 0xf;
8348 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8349 constraint (msb
> 32, _("bit-field extends past end of register"));
8350 /* The instruction encoding stores the LSB and MSB,
8351 not the LSB and width. */
8352 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8353 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8354 inst
.instruction
|= (msb
- 1) << 16;
8362 /* #0 in second position is alternative syntax for bfc, which is
8363 the same instruction but with REG_PC in the Rm field. */
8364 if (!inst
.operands
[1].isreg
)
8365 inst
.operands
[1].reg
= REG_PC
;
8367 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8368 constraint (msb
> 32, _("bit-field extends past end of register"));
8369 /* The instruction encoding stores the LSB and MSB,
8370 not the LSB and width. */
8371 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8372 inst
.instruction
|= inst
.operands
[1].reg
;
8373 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8374 inst
.instruction
|= (msb
- 1) << 16;
8380 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8381 _("bit-field extends past end of register"));
8382 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8383 inst
.instruction
|= inst
.operands
[1].reg
;
8384 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8385 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8388 /* ARM V5 breakpoint instruction (argument parse)
8389 BKPT <16 bit unsigned immediate>
8390 Instruction is not conditional.
8391 The bit pattern given in insns[] has the COND_ALWAYS condition,
8392 and it is an error if the caller tried to override that. */
8397 /* Top 12 of 16 bits to bits 19:8. */
8398 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8400 /* Bottom 4 of 16 bits to bits 3:0. */
8401 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8405 encode_branch (int default_reloc
)
8407 if (inst
.operands
[0].hasreloc
)
8409 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8410 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8411 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8412 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8413 ? BFD_RELOC_ARM_PLT32
8414 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8417 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8418 inst
.reloc
.pc_rel
= 1;
8425 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8426 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8429 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8436 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8438 if (inst
.cond
== COND_ALWAYS
)
8439 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8441 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8445 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8448 /* ARM V5 branch-link-exchange instruction (argument parse)
8449 BLX <target_addr> ie BLX(1)
8450 BLX{<condition>} <Rm> ie BLX(2)
8451 Unfortunately, there are two different opcodes for this mnemonic.
8452 So, the insns[].value is not used, and the code here zaps values
8453 into inst.instruction.
8454 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8459 if (inst
.operands
[0].isreg
)
8461 /* Arg is a register; the opcode provided by insns[] is correct.
8462 It is not illegal to do "blx pc", just useless. */
8463 if (inst
.operands
[0].reg
== REG_PC
)
8464 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8466 inst
.instruction
|= inst
.operands
[0].reg
;
8470 /* Arg is an address; this instruction cannot be executed
8471 conditionally, and the opcode must be adjusted.
8472 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8473 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8474 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8475 inst
.instruction
= 0xfa000000;
8476 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8483 bfd_boolean want_reloc
;
8485 if (inst
.operands
[0].reg
== REG_PC
)
8486 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8488 inst
.instruction
|= inst
.operands
[0].reg
;
8489 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8490 it is for ARMv4t or earlier. */
8491 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8492 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
8496 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8501 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8505 /* ARM v5TEJ. Jump to Jazelle code. */
8510 if (inst
.operands
[0].reg
== REG_PC
)
8511 as_tsktsk (_("use of r15 in bxj is not really useful"));
8513 inst
.instruction
|= inst
.operands
[0].reg
;
8516 /* Co-processor data operation:
8517 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8518 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8522 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8523 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8524 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8525 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8526 inst
.instruction
|= inst
.operands
[4].reg
;
8527 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8533 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8534 encode_arm_shifter_operand (1);
8537 /* Transfer between coprocessor and ARM registers.
8538 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8543 No special properties. */
8545 struct deprecated_coproc_regs_s
8552 arm_feature_set deprecated
;
8553 arm_feature_set obsoleted
;
8554 const char *dep_msg
;
8555 const char *obs_msg
;
8558 #define DEPR_ACCESS_V8 \
8559 N_("This coprocessor register access is deprecated in ARMv8")
8561 /* Table of all deprecated coprocessor registers. */
8562 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8564 {15, 0, 7, 10, 5, /* CP15DMB. */
8565 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8566 DEPR_ACCESS_V8
, NULL
},
8567 {15, 0, 7, 10, 4, /* CP15DSB. */
8568 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8569 DEPR_ACCESS_V8
, NULL
},
8570 {15, 0, 7, 5, 4, /* CP15ISB. */
8571 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8572 DEPR_ACCESS_V8
, NULL
},
8573 {14, 6, 1, 0, 0, /* TEEHBR. */
8574 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8575 DEPR_ACCESS_V8
, NULL
},
8576 {14, 6, 0, 0, 0, /* TEECR. */
8577 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8578 DEPR_ACCESS_V8
, NULL
},
8581 #undef DEPR_ACCESS_V8
8583 static const size_t deprecated_coproc_reg_count
=
8584 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8592 Rd
= inst
.operands
[2].reg
;
8595 if (inst
.instruction
== 0xee000010
8596 || inst
.instruction
== 0xfe000010)
8598 reject_bad_reg (Rd
);
8601 constraint (Rd
== REG_SP
, BAD_SP
);
8606 if (inst
.instruction
== 0xe000010)
8607 constraint (Rd
== REG_PC
, BAD_PC
);
8610 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8612 const struct deprecated_coproc_regs_s
*r
=
8613 deprecated_coproc_regs
+ i
;
8615 if (inst
.operands
[0].reg
== r
->cp
8616 && inst
.operands
[1].imm
== r
->opc1
8617 && inst
.operands
[3].reg
== r
->crn
8618 && inst
.operands
[4].reg
== r
->crm
8619 && inst
.operands
[5].imm
== r
->opc2
)
8621 if (! ARM_CPU_IS_ANY (cpu_variant
)
8622 && warn_on_deprecated
8623 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8624 as_tsktsk ("%s", r
->dep_msg
);
8628 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8629 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8630 inst
.instruction
|= Rd
<< 12;
8631 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8632 inst
.instruction
|= inst
.operands
[4].reg
;
8633 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8636 /* Transfer between coprocessor register and pair of ARM registers.
8637 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8642 Two XScale instructions are special cases of these:
8644 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8645 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8647 Result unpredictable if Rd or Rn is R15. */
8654 Rd
= inst
.operands
[2].reg
;
8655 Rn
= inst
.operands
[3].reg
;
8659 reject_bad_reg (Rd
);
8660 reject_bad_reg (Rn
);
8664 constraint (Rd
== REG_PC
, BAD_PC
);
8665 constraint (Rn
== REG_PC
, BAD_PC
);
8668 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8669 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8670 inst
.instruction
|= Rd
<< 12;
8671 inst
.instruction
|= Rn
<< 16;
8672 inst
.instruction
|= inst
.operands
[4].reg
;
8678 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8679 if (inst
.operands
[1].present
)
8681 inst
.instruction
|= CPSI_MMOD
;
8682 inst
.instruction
|= inst
.operands
[1].imm
;
8689 inst
.instruction
|= inst
.operands
[0].imm
;
8695 unsigned Rd
, Rn
, Rm
;
8697 Rd
= inst
.operands
[0].reg
;
8698 Rn
= (inst
.operands
[1].present
8699 ? inst
.operands
[1].reg
: Rd
);
8700 Rm
= inst
.operands
[2].reg
;
8702 constraint ((Rd
== REG_PC
), BAD_PC
);
8703 constraint ((Rn
== REG_PC
), BAD_PC
);
8704 constraint ((Rm
== REG_PC
), BAD_PC
);
8706 inst
.instruction
|= Rd
<< 16;
8707 inst
.instruction
|= Rn
<< 0;
8708 inst
.instruction
|= Rm
<< 8;
8714 /* There is no IT instruction in ARM mode. We
8715 process it to do the validation as if in
8716 thumb mode, just in case the code gets
8717 assembled for thumb using the unified syntax. */
8722 set_it_insn_type (IT_INSN
);
8723 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8724 now_it
.cc
= inst
.operands
[0].imm
;
8728 /* If there is only one register in the register list,
8729 then return its register number. Otherwise return -1. */
8731 only_one_reg_in_list (int range
)
8733 int i
= ffs (range
) - 1;
8734 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8738 encode_ldmstm(int from_push_pop_mnem
)
8740 int base_reg
= inst
.operands
[0].reg
;
8741 int range
= inst
.operands
[1].imm
;
8744 inst
.instruction
|= base_reg
<< 16;
8745 inst
.instruction
|= range
;
8747 if (inst
.operands
[1].writeback
)
8748 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8750 if (inst
.operands
[0].writeback
)
8752 inst
.instruction
|= WRITE_BACK
;
8753 /* Check for unpredictable uses of writeback. */
8754 if (inst
.instruction
& LOAD_BIT
)
8756 /* Not allowed in LDM type 2. */
8757 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8758 && ((range
& (1 << REG_PC
)) == 0))
8759 as_warn (_("writeback of base register is UNPREDICTABLE"));
8760 /* Only allowed if base reg not in list for other types. */
8761 else if (range
& (1 << base_reg
))
8762 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8766 /* Not allowed for type 2. */
8767 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8768 as_warn (_("writeback of base register is UNPREDICTABLE"));
8769 /* Only allowed if base reg not in list, or first in list. */
8770 else if ((range
& (1 << base_reg
))
8771 && (range
& ((1 << base_reg
) - 1)))
8772 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8776 /* If PUSH/POP has only one register, then use the A2 encoding. */
8777 one_reg
= only_one_reg_in_list (range
);
8778 if (from_push_pop_mnem
&& one_reg
>= 0)
8780 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8782 inst
.instruction
&= A_COND_MASK
;
8783 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8784 inst
.instruction
|= one_reg
<< 12;
8791 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8794 /* ARMv5TE load-consecutive (argument parse)
8803 constraint (inst
.operands
[0].reg
% 2 != 0,
8804 _("first transfer register must be even"));
8805 constraint (inst
.operands
[1].present
8806 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8807 _("can only transfer two consecutive registers"));
8808 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8809 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8811 if (!inst
.operands
[1].present
)
8812 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8814 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8815 register and the first register written; we have to diagnose
8816 overlap between the base and the second register written here. */
8818 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8819 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8820 as_warn (_("base register written back, and overlaps "
8821 "second transfer register"));
8823 if (!(inst
.instruction
& V4_STR_BIT
))
8825 /* For an index-register load, the index register must not overlap the
8826 destination (even if not write-back). */
8827 if (inst
.operands
[2].immisreg
8828 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8829 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8830 as_warn (_("index register overlaps transfer register"));
8832 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8833 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8839 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8840 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8841 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8842 || inst
.operands
[1].negative
8843 /* This can arise if the programmer has written
8845 or if they have mistakenly used a register name as the last
8848 It is very difficult to distinguish between these two cases
8849 because "rX" might actually be a label. ie the register
8850 name has been occluded by a symbol of the same name. So we
8851 just generate a general 'bad addressing mode' type error
8852 message and leave it up to the programmer to discover the
8853 true cause and fix their mistake. */
8854 || (inst
.operands
[1].reg
== REG_PC
),
8857 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8858 || inst
.reloc
.exp
.X_add_number
!= 0,
8859 _("offset must be zero in ARM encoding"));
8861 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8863 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8864 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8865 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8871 constraint (inst
.operands
[0].reg
% 2 != 0,
8872 _("even register required"));
8873 constraint (inst
.operands
[1].present
8874 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8875 _("can only load two consecutive registers"));
8876 /* If op 1 were present and equal to PC, this function wouldn't
8877 have been called in the first place. */
8878 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8880 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8881 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8884 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8885 which is not a multiple of four is UNPREDICTABLE. */
8887 check_ldr_r15_aligned (void)
8889 constraint (!(inst
.operands
[1].immisreg
)
8890 && (inst
.operands
[0].reg
== REG_PC
8891 && inst
.operands
[1].reg
== REG_PC
8892 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8893 _("ldr to register 15 must be 4-byte alligned"));
8899 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8900 if (!inst
.operands
[1].isreg
)
8901 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
8903 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8904 check_ldr_r15_aligned ();
8910 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8912 if (inst
.operands
[1].preind
)
8914 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8915 || inst
.reloc
.exp
.X_add_number
!= 0,
8916 _("this instruction requires a post-indexed address"));
8918 inst
.operands
[1].preind
= 0;
8919 inst
.operands
[1].postind
= 1;
8920 inst
.operands
[1].writeback
= 1;
8922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8923 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8926 /* Halfword and signed-byte load/store operations. */
8931 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8932 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8933 if (!inst
.operands
[1].isreg
)
8934 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
8936 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8942 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8944 if (inst
.operands
[1].preind
)
8946 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8947 || inst
.reloc
.exp
.X_add_number
!= 0,
8948 _("this instruction requires a post-indexed address"));
8950 inst
.operands
[1].preind
= 0;
8951 inst
.operands
[1].postind
= 1;
8952 inst
.operands
[1].writeback
= 1;
8954 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8955 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8958 /* Co-processor register load/store.
8959 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8963 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8964 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8965 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8971 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8972 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8973 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8974 && !(inst
.instruction
& 0x00400000))
8975 as_tsktsk (_("Rd and Rm should be different in mla"));
8977 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8978 inst
.instruction
|= inst
.operands
[1].reg
;
8979 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8980 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8986 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8987 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8989 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8990 encode_arm_shifter_operand (1);
8993 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9000 top
= (inst
.instruction
& 0x00400000) != 0;
9001 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9002 _(":lower16: not allowed this instruction"));
9003 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9004 _(":upper16: not allowed instruction"));
9005 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9006 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9008 imm
= inst
.reloc
.exp
.X_add_number
;
9009 /* The value is in two pieces: 0:11, 16:19. */
9010 inst
.instruction
|= (imm
& 0x00000fff);
9011 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9016 do_vfp_nsyn_mrs (void)
9018 if (inst
.operands
[0].isvec
)
9020 if (inst
.operands
[1].reg
!= 1)
9021 first_error (_("operand 1 must be FPSCR"));
9022 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9023 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9024 do_vfp_nsyn_opcode ("fmstat");
9026 else if (inst
.operands
[1].isvec
)
9027 do_vfp_nsyn_opcode ("fmrx");
9035 do_vfp_nsyn_msr (void)
9037 if (inst
.operands
[0].isvec
)
9038 do_vfp_nsyn_opcode ("fmxr");
9048 unsigned Rt
= inst
.operands
[0].reg
;
9050 if (thumb_mode
&& Rt
== REG_SP
)
9052 inst
.error
= BAD_SP
;
9056 /* APSR_ sets isvec. All other refs to PC are illegal. */
9057 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9059 inst
.error
= BAD_PC
;
9063 /* If we get through parsing the register name, we just insert the number
9064 generated into the instruction without further validation. */
9065 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9066 inst
.instruction
|= (Rt
<< 12);
9072 unsigned Rt
= inst
.operands
[1].reg
;
9075 reject_bad_reg (Rt
);
9076 else if (Rt
== REG_PC
)
9078 inst
.error
= BAD_PC
;
9082 /* If we get through parsing the register name, we just insert the number
9083 generated into the instruction without further validation. */
9084 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9085 inst
.instruction
|= (Rt
<< 12);
9093 if (do_vfp_nsyn_mrs () == SUCCESS
)
9096 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9099 if (inst
.operands
[1].isreg
)
9101 br
= inst
.operands
[1].reg
;
9102 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
9103 as_bad (_("bad register for mrs"));
9107 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9108 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9110 _("'APSR', 'CPSR' or 'SPSR' expected"));
9111 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9114 inst
.instruction
|= br
;
9117 /* Two possible forms:
9118 "{C|S}PSR_<field>, Rm",
9119 "{C|S}PSR_f, #expression". */
9124 if (do_vfp_nsyn_msr () == SUCCESS
)
9127 inst
.instruction
|= inst
.operands
[0].imm
;
9128 if (inst
.operands
[1].isreg
)
9129 inst
.instruction
|= inst
.operands
[1].reg
;
9132 inst
.instruction
|= INST_IMMEDIATE
;
9133 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9134 inst
.reloc
.pc_rel
= 0;
9141 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9143 if (!inst
.operands
[2].present
)
9144 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9145 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9146 inst
.instruction
|= inst
.operands
[1].reg
;
9147 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9149 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9150 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9151 as_tsktsk (_("Rd and Rm should be different in mul"));
9154 /* Long Multiply Parser
9155 UMULL RdLo, RdHi, Rm, Rs
9156 SMULL RdLo, RdHi, Rm, Rs
9157 UMLAL RdLo, RdHi, Rm, Rs
9158 SMLAL RdLo, RdHi, Rm, Rs. */
9163 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9164 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9165 inst
.instruction
|= inst
.operands
[2].reg
;
9166 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9168 /* rdhi and rdlo must be different. */
9169 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9170 as_tsktsk (_("rdhi and rdlo must be different"));
9172 /* rdhi, rdlo and rm must all be different before armv6. */
9173 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9174 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9175 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9176 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9182 if (inst
.operands
[0].present
9183 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9185 /* Architectural NOP hints are CPSR sets with no bits selected. */
9186 inst
.instruction
&= 0xf0000000;
9187 inst
.instruction
|= 0x0320f000;
9188 if (inst
.operands
[0].present
)
9189 inst
.instruction
|= inst
.operands
[0].imm
;
9193 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9194 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9195 Condition defaults to COND_ALWAYS.
9196 Error if Rd, Rn or Rm are R15. */
9201 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9202 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9203 inst
.instruction
|= inst
.operands
[2].reg
;
9204 if (inst
.operands
[3].present
)
9205 encode_arm_shift (3);
9208 /* ARM V6 PKHTB (Argument Parse). */
9213 if (!inst
.operands
[3].present
)
9215 /* If the shift specifier is omitted, turn the instruction
9216 into pkhbt rd, rm, rn. */
9217 inst
.instruction
&= 0xfff00010;
9218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9219 inst
.instruction
|= inst
.operands
[1].reg
;
9220 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9224 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9225 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9226 inst
.instruction
|= inst
.operands
[2].reg
;
9227 encode_arm_shift (3);
9231 /* ARMv5TE: Preload-Cache
9232 MP Extensions: Preload for write
9236 Syntactically, like LDR with B=1, W=0, L=1. */
9241 constraint (!inst
.operands
[0].isreg
,
9242 _("'[' expected after PLD mnemonic"));
9243 constraint (inst
.operands
[0].postind
,
9244 _("post-indexed expression used in preload instruction"));
9245 constraint (inst
.operands
[0].writeback
,
9246 _("writeback used in preload instruction"));
9247 constraint (!inst
.operands
[0].preind
,
9248 _("unindexed addressing used in preload instruction"));
9249 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9252 /* ARMv7: PLI <addr_mode> */
9256 constraint (!inst
.operands
[0].isreg
,
9257 _("'[' expected after PLI mnemonic"));
9258 constraint (inst
.operands
[0].postind
,
9259 _("post-indexed expression used in preload instruction"));
9260 constraint (inst
.operands
[0].writeback
,
9261 _("writeback used in preload instruction"));
9262 constraint (!inst
.operands
[0].preind
,
9263 _("unindexed addressing used in preload instruction"));
9264 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9265 inst
.instruction
&= ~PRE_INDEX
;
9271 constraint (inst
.operands
[0].writeback
,
9272 _("push/pop do not support {reglist}^"));
9273 inst
.operands
[1] = inst
.operands
[0];
9274 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9275 inst
.operands
[0].isreg
= 1;
9276 inst
.operands
[0].writeback
= 1;
9277 inst
.operands
[0].reg
= REG_SP
;
9278 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9281 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9282 word at the specified address and the following word
9284 Unconditionally executed.
9285 Error if Rn is R15. */
9290 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9291 if (inst
.operands
[0].writeback
)
9292 inst
.instruction
|= WRITE_BACK
;
9295 /* ARM V6 ssat (argument parse). */
9300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9301 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9302 inst
.instruction
|= inst
.operands
[2].reg
;
9304 if (inst
.operands
[3].present
)
9305 encode_arm_shift (3);
9308 /* ARM V6 usat (argument parse). */
9313 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9314 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9315 inst
.instruction
|= inst
.operands
[2].reg
;
9317 if (inst
.operands
[3].present
)
9318 encode_arm_shift (3);
9321 /* ARM V6 ssat16 (argument parse). */
9326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9327 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9328 inst
.instruction
|= inst
.operands
[2].reg
;
9334 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9335 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9336 inst
.instruction
|= inst
.operands
[2].reg
;
9339 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9340 preserving the other bits.
9342 setend <endian_specifier>, where <endian_specifier> is either
9348 if (warn_on_deprecated
9349 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9350 as_tsktsk (_("setend use is deprecated for ARMv8"));
9352 if (inst
.operands
[0].imm
)
9353 inst
.instruction
|= 0x200;
9359 unsigned int Rm
= (inst
.operands
[1].present
9360 ? inst
.operands
[1].reg
9361 : inst
.operands
[0].reg
);
9363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9364 inst
.instruction
|= Rm
;
9365 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9367 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9368 inst
.instruction
|= SHIFT_BY_REG
;
9369 /* PR 12854: Error on extraneous shifts. */
9370 constraint (inst
.operands
[2].shifted
,
9371 _("extraneous shift as part of operand to shift insn"));
9374 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9380 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9381 inst
.reloc
.pc_rel
= 0;
9387 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9388 inst
.reloc
.pc_rel
= 0;
9394 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9395 inst
.reloc
.pc_rel
= 0;
9401 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9402 _("selected processor does not support SETPAN instruction"));
9404 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9410 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9411 _("selected processor does not support SETPAN instruction"));
9413 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9416 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9417 SMLAxy{cond} Rd,Rm,Rs,Rn
9418 SMLAWy{cond} Rd,Rm,Rs,Rn
9419 Error if any register is R15. */
9424 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9425 inst
.instruction
|= inst
.operands
[1].reg
;
9426 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9427 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9430 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9431 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9432 Error if any register is R15.
9433 Warning if Rdlo == Rdhi. */
9438 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9439 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9440 inst
.instruction
|= inst
.operands
[2].reg
;
9441 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9443 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9444 as_tsktsk (_("rdhi and rdlo must be different"));
9447 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9448 SMULxy{cond} Rd,Rm,Rs
9449 Error if any register is R15. */
9454 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9455 inst
.instruction
|= inst
.operands
[1].reg
;
9456 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9459 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9460 the same for both ARM and Thumb-2. */
9467 if (inst
.operands
[0].present
)
9469 reg
= inst
.operands
[0].reg
;
9470 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9475 inst
.instruction
|= reg
<< 16;
9476 inst
.instruction
|= inst
.operands
[1].imm
;
9477 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9478 inst
.instruction
|= WRITE_BACK
;
9481 /* ARM V6 strex (argument parse). */
9486 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9487 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9488 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9489 || inst
.operands
[2].negative
9490 /* See comment in do_ldrex(). */
9491 || (inst
.operands
[2].reg
== REG_PC
),
9494 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9495 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9497 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9498 || inst
.reloc
.exp
.X_add_number
!= 0,
9499 _("offset must be zero in ARM encoding"));
9501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9502 inst
.instruction
|= inst
.operands
[1].reg
;
9503 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9504 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9510 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9511 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9512 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9513 || inst
.operands
[2].negative
,
9516 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9517 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9525 constraint (inst
.operands
[1].reg
% 2 != 0,
9526 _("even register required"));
9527 constraint (inst
.operands
[2].present
9528 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9529 _("can only store two consecutive registers"));
9530 /* If op 2 were present and equal to PC, this function wouldn't
9531 have been called in the first place. */
9532 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9534 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9535 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9536 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9539 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9540 inst
.instruction
|= inst
.operands
[1].reg
;
9541 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9548 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9549 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9557 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9558 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9563 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9564 extends it to 32-bits, and adds the result to a value in another
9565 register. You can specify a rotation by 0, 8, 16, or 24 bits
9566 before extracting the 16-bit value.
9567 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9568 Condition defaults to COND_ALWAYS.
9569 Error if any register uses R15. */
9574 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9575 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9576 inst
.instruction
|= inst
.operands
[2].reg
;
9577 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9582 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9583 Condition defaults to COND_ALWAYS.
9584 Error if any register uses R15. */
9589 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9590 inst
.instruction
|= inst
.operands
[1].reg
;
9591 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9594 /* VFP instructions. In a logical order: SP variant first, monad
9595 before dyad, arithmetic then move then load/store. */
9598 do_vfp_sp_monadic (void)
9600 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9601 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9605 do_vfp_sp_dyadic (void)
9607 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9608 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9609 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9613 do_vfp_sp_compare_z (void)
9615 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9619 do_vfp_dp_sp_cvt (void)
9621 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9622 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9626 do_vfp_sp_dp_cvt (void)
9628 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9629 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9633 do_vfp_reg_from_sp (void)
9635 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9636 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9640 do_vfp_reg2_from_sp2 (void)
9642 constraint (inst
.operands
[2].imm
!= 2,
9643 _("only two consecutive VFP SP registers allowed here"));
9644 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9645 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9646 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9650 do_vfp_sp_from_reg (void)
9652 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9653 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9657 do_vfp_sp2_from_reg2 (void)
9659 constraint (inst
.operands
[0].imm
!= 2,
9660 _("only two consecutive VFP SP registers allowed here"));
9661 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9662 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9663 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9667 do_vfp_sp_ldst (void)
9669 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9670 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9674 do_vfp_dp_ldst (void)
9676 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9677 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9682 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9684 if (inst
.operands
[0].writeback
)
9685 inst
.instruction
|= WRITE_BACK
;
9687 constraint (ldstm_type
!= VFP_LDSTMIA
,
9688 _("this addressing mode requires base-register writeback"));
9689 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9690 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9691 inst
.instruction
|= inst
.operands
[1].imm
;
9695 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9699 if (inst
.operands
[0].writeback
)
9700 inst
.instruction
|= WRITE_BACK
;
9702 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9703 _("this addressing mode requires base-register writeback"));
9705 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9706 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9708 count
= inst
.operands
[1].imm
<< 1;
9709 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9712 inst
.instruction
|= count
;
9716 do_vfp_sp_ldstmia (void)
9718 vfp_sp_ldstm (VFP_LDSTMIA
);
9722 do_vfp_sp_ldstmdb (void)
9724 vfp_sp_ldstm (VFP_LDSTMDB
);
9728 do_vfp_dp_ldstmia (void)
9730 vfp_dp_ldstm (VFP_LDSTMIA
);
9734 do_vfp_dp_ldstmdb (void)
9736 vfp_dp_ldstm (VFP_LDSTMDB
);
9740 do_vfp_xp_ldstmia (void)
9742 vfp_dp_ldstm (VFP_LDSTMIAX
);
9746 do_vfp_xp_ldstmdb (void)
9748 vfp_dp_ldstm (VFP_LDSTMDBX
);
9752 do_vfp_dp_rd_rm (void)
9754 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9755 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9759 do_vfp_dp_rn_rd (void)
9761 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9762 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9766 do_vfp_dp_rd_rn (void)
9768 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9769 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9773 do_vfp_dp_rd_rn_rm (void)
9775 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9776 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9777 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9783 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9787 do_vfp_dp_rm_rd_rn (void)
9789 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9790 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9791 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9794 /* VFPv3 instructions. */
9796 do_vfp_sp_const (void)
9798 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9799 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9800 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9804 do_vfp_dp_const (void)
9806 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9807 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9808 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9812 vfp_conv (int srcsize
)
9814 int immbits
= srcsize
- inst
.operands
[1].imm
;
9816 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9818 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9819 i.e. immbits must be in range 0 - 16. */
9820 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9823 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9825 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9826 i.e. immbits must be in range 0 - 31. */
9827 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9831 inst
.instruction
|= (immbits
& 1) << 5;
9832 inst
.instruction
|= (immbits
>> 1);
9836 do_vfp_sp_conv_16 (void)
9838 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9843 do_vfp_dp_conv_16 (void)
9845 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9850 do_vfp_sp_conv_32 (void)
9852 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9857 do_vfp_dp_conv_32 (void)
9859 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9863 /* FPA instructions. Also in a logical order. */
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9869 inst
.instruction
|= inst
.operands
[1].reg
;
9873 do_fpa_ldmstm (void)
9875 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9876 switch (inst
.operands
[1].imm
)
9878 case 1: inst
.instruction
|= CP_T_X
; break;
9879 case 2: inst
.instruction
|= CP_T_Y
; break;
9880 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9885 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9887 /* The instruction specified "ea" or "fd", so we can only accept
9888 [Rn]{!}. The instruction does not really support stacking or
9889 unstacking, so we have to emulate these by setting appropriate
9890 bits and offsets. */
9891 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9892 || inst
.reloc
.exp
.X_add_number
!= 0,
9893 _("this instruction does not support indexing"));
9895 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9896 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9898 if (!(inst
.instruction
& INDEX_UP
))
9899 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9901 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9903 inst
.operands
[2].preind
= 0;
9904 inst
.operands
[2].postind
= 1;
9908 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9911 /* iWMMXt instructions: strictly in alphabetical order. */
9914 do_iwmmxt_tandorc (void)
9916 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9920 do_iwmmxt_textrc (void)
9922 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9923 inst
.instruction
|= inst
.operands
[1].imm
;
9927 do_iwmmxt_textrm (void)
9929 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9930 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9931 inst
.instruction
|= inst
.operands
[2].imm
;
9935 do_iwmmxt_tinsr (void)
9937 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9938 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9939 inst
.instruction
|= inst
.operands
[2].imm
;
9943 do_iwmmxt_tmia (void)
9945 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9946 inst
.instruction
|= inst
.operands
[1].reg
;
9947 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9951 do_iwmmxt_waligni (void)
9953 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9954 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9955 inst
.instruction
|= inst
.operands
[2].reg
;
9956 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9960 do_iwmmxt_wmerge (void)
9962 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9963 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9964 inst
.instruction
|= inst
.operands
[2].reg
;
9965 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9969 do_iwmmxt_wmov (void)
9971 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9972 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9973 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9974 inst
.instruction
|= inst
.operands
[1].reg
;
9978 do_iwmmxt_wldstbh (void)
9981 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9983 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9985 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9986 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9990 do_iwmmxt_wldstw (void)
9992 /* RIWR_RIWC clears .isreg for a control register. */
9993 if (!inst
.operands
[0].isreg
)
9995 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9996 inst
.instruction
|= 0xf0000000;
9999 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10000 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10004 do_iwmmxt_wldstd (void)
10006 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10007 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10008 && inst
.operands
[1].immisreg
)
10010 inst
.instruction
&= ~0x1a000ff;
10011 inst
.instruction
|= (0xfU
<< 28);
10012 if (inst
.operands
[1].preind
)
10013 inst
.instruction
|= PRE_INDEX
;
10014 if (!inst
.operands
[1].negative
)
10015 inst
.instruction
|= INDEX_UP
;
10016 if (inst
.operands
[1].writeback
)
10017 inst
.instruction
|= WRITE_BACK
;
10018 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10019 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10020 inst
.instruction
|= inst
.operands
[1].imm
;
10023 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10027 do_iwmmxt_wshufh (void)
10029 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10030 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10031 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10032 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10036 do_iwmmxt_wzero (void)
10038 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10039 inst
.instruction
|= inst
.operands
[0].reg
;
10040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10041 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10045 do_iwmmxt_wrwrwr_or_imm5 (void)
10047 if (inst
.operands
[2].isreg
)
10050 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10051 _("immediate operand requires iWMMXt2"));
10053 if (inst
.operands
[2].imm
== 0)
10055 switch ((inst
.instruction
>> 20) & 0xf)
10061 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10062 inst
.operands
[2].imm
= 16;
10063 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10069 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10070 inst
.operands
[2].imm
= 32;
10071 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10078 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10080 wrn
= (inst
.instruction
>> 16) & 0xf;
10081 inst
.instruction
&= 0xff0fff0f;
10082 inst
.instruction
|= wrn
;
10083 /* Bail out here; the instruction is now assembled. */
10088 /* Map 32 -> 0, etc. */
10089 inst
.operands
[2].imm
&= 0x1f;
10090 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10094 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10095 operations first, then control, shift, and load/store. */
10097 /* Insns like "foo X,Y,Z". */
10100 do_mav_triple (void)
10102 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10103 inst
.instruction
|= inst
.operands
[1].reg
;
10104 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10107 /* Insns like "foo W,X,Y,Z".
10108 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10113 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10114 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10115 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10116 inst
.instruction
|= inst
.operands
[3].reg
;
10119 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10121 do_mav_dspsc (void)
10123 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10126 /* Maverick shift immediate instructions.
10127 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10128 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10131 do_mav_shift (void)
10133 int imm
= inst
.operands
[2].imm
;
10135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10136 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10138 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10139 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10140 Bit 4 should be 0. */
10141 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10143 inst
.instruction
|= imm
;
10146 /* XScale instructions. Also sorted arithmetic before move. */
10148 /* Xscale multiply-accumulate (argument parse)
10151 MIAxycc acc0,Rm,Rs. */
10156 inst
.instruction
|= inst
.operands
[1].reg
;
10157 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10160 /* Xscale move-accumulator-register (argument parse)
10162 MARcc acc0,RdLo,RdHi. */
10167 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10168 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10171 /* Xscale move-register-accumulator (argument parse)
10173 MRAcc RdLo,RdHi,acc0. */
10178 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10179 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10180 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10183 /* Encoding functions relevant only to Thumb. */
10185 /* inst.operands[i] is a shifted-register operand; encode
10186 it into inst.instruction in the format used by Thumb32. */
10189 encode_thumb32_shifted_operand (int i
)
10191 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10192 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10194 constraint (inst
.operands
[i
].immisreg
,
10195 _("shift by register not allowed in thumb mode"));
10196 inst
.instruction
|= inst
.operands
[i
].reg
;
10197 if (shift
== SHIFT_RRX
)
10198 inst
.instruction
|= SHIFT_ROR
<< 4;
10201 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10202 _("expression too complex"));
10204 constraint (value
> 32
10205 || (value
== 32 && (shift
== SHIFT_LSL
10206 || shift
== SHIFT_ROR
)),
10207 _("shift expression is too large"));
10211 else if (value
== 32)
10214 inst
.instruction
|= shift
<< 4;
10215 inst
.instruction
|= (value
& 0x1c) << 10;
10216 inst
.instruction
|= (value
& 0x03) << 6;
10221 /* inst.operands[i] was set up by parse_address. Encode it into a
10222 Thumb32 format load or store instruction. Reject forms that cannot
10223 be used with such instructions. If is_t is true, reject forms that
10224 cannot be used with a T instruction; if is_d is true, reject forms
10225 that cannot be used with a D instruction. If it is a store insn,
10226 reject PC in Rn. */
10229 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10231 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10233 constraint (!inst
.operands
[i
].isreg
,
10234 _("Instruction does not support =N addresses"));
10236 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10237 if (inst
.operands
[i
].immisreg
)
10239 constraint (is_pc
, BAD_PC_ADDRESSING
);
10240 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10241 constraint (inst
.operands
[i
].negative
,
10242 _("Thumb does not support negative register indexing"));
10243 constraint (inst
.operands
[i
].postind
,
10244 _("Thumb does not support register post-indexing"));
10245 constraint (inst
.operands
[i
].writeback
,
10246 _("Thumb does not support register indexing with writeback"));
10247 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10248 _("Thumb supports only LSL in shifted register indexing"));
10250 inst
.instruction
|= inst
.operands
[i
].imm
;
10251 if (inst
.operands
[i
].shifted
)
10253 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10254 _("expression too complex"));
10255 constraint (inst
.reloc
.exp
.X_add_number
< 0
10256 || inst
.reloc
.exp
.X_add_number
> 3,
10257 _("shift out of range"));
10258 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10260 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10262 else if (inst
.operands
[i
].preind
)
10264 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10265 constraint (is_t
&& inst
.operands
[i
].writeback
,
10266 _("cannot use writeback with this instruction"));
10267 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10268 BAD_PC_ADDRESSING
);
10272 inst
.instruction
|= 0x01000000;
10273 if (inst
.operands
[i
].writeback
)
10274 inst
.instruction
|= 0x00200000;
10278 inst
.instruction
|= 0x00000c00;
10279 if (inst
.operands
[i
].writeback
)
10280 inst
.instruction
|= 0x00000100;
10282 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10284 else if (inst
.operands
[i
].postind
)
10286 gas_assert (inst
.operands
[i
].writeback
);
10287 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10288 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10291 inst
.instruction
|= 0x00200000;
10293 inst
.instruction
|= 0x00000900;
10294 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10296 else /* unindexed - only for coprocessor */
10297 inst
.error
= _("instruction does not accept unindexed addressing");
10300 /* Table of Thumb instructions which exist in both 16- and 32-bit
10301 encodings (the latter only in post-V6T2 cores). The index is the
10302 value used in the insns table below. When there is more than one
10303 possible 16-bit encoding for the instruction, this table always
10305 Also contains several pseudo-instructions used during relaxation. */
10306 #define T16_32_TAB \
10307 X(_adc, 4140, eb400000), \
10308 X(_adcs, 4140, eb500000), \
10309 X(_add, 1c00, eb000000), \
10310 X(_adds, 1c00, eb100000), \
10311 X(_addi, 0000, f1000000), \
10312 X(_addis, 0000, f1100000), \
10313 X(_add_pc,000f, f20f0000), \
10314 X(_add_sp,000d, f10d0000), \
10315 X(_adr, 000f, f20f0000), \
10316 X(_and, 4000, ea000000), \
10317 X(_ands, 4000, ea100000), \
10318 X(_asr, 1000, fa40f000), \
10319 X(_asrs, 1000, fa50f000), \
10320 X(_b, e000, f000b000), \
10321 X(_bcond, d000, f0008000), \
10322 X(_bic, 4380, ea200000), \
10323 X(_bics, 4380, ea300000), \
10324 X(_cmn, 42c0, eb100f00), \
10325 X(_cmp, 2800, ebb00f00), \
10326 X(_cpsie, b660, f3af8400), \
10327 X(_cpsid, b670, f3af8600), \
10328 X(_cpy, 4600, ea4f0000), \
10329 X(_dec_sp,80dd, f1ad0d00), \
10330 X(_eor, 4040, ea800000), \
10331 X(_eors, 4040, ea900000), \
10332 X(_inc_sp,00dd, f10d0d00), \
10333 X(_ldmia, c800, e8900000), \
10334 X(_ldr, 6800, f8500000), \
10335 X(_ldrb, 7800, f8100000), \
10336 X(_ldrh, 8800, f8300000), \
10337 X(_ldrsb, 5600, f9100000), \
10338 X(_ldrsh, 5e00, f9300000), \
10339 X(_ldr_pc,4800, f85f0000), \
10340 X(_ldr_pc2,4800, f85f0000), \
10341 X(_ldr_sp,9800, f85d0000), \
10342 X(_lsl, 0000, fa00f000), \
10343 X(_lsls, 0000, fa10f000), \
10344 X(_lsr, 0800, fa20f000), \
10345 X(_lsrs, 0800, fa30f000), \
10346 X(_mov, 2000, ea4f0000), \
10347 X(_movs, 2000, ea5f0000), \
10348 X(_mul, 4340, fb00f000), \
10349 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10350 X(_mvn, 43c0, ea6f0000), \
10351 X(_mvns, 43c0, ea7f0000), \
10352 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10353 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10354 X(_orr, 4300, ea400000), \
10355 X(_orrs, 4300, ea500000), \
10356 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10357 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10358 X(_rev, ba00, fa90f080), \
10359 X(_rev16, ba40, fa90f090), \
10360 X(_revsh, bac0, fa90f0b0), \
10361 X(_ror, 41c0, fa60f000), \
10362 X(_rors, 41c0, fa70f000), \
10363 X(_sbc, 4180, eb600000), \
10364 X(_sbcs, 4180, eb700000), \
10365 X(_stmia, c000, e8800000), \
10366 X(_str, 6000, f8400000), \
10367 X(_strb, 7000, f8000000), \
10368 X(_strh, 8000, f8200000), \
10369 X(_str_sp,9000, f84d0000), \
10370 X(_sub, 1e00, eba00000), \
10371 X(_subs, 1e00, ebb00000), \
10372 X(_subi, 8000, f1a00000), \
10373 X(_subis, 8000, f1b00000), \
10374 X(_sxtb, b240, fa4ff080), \
10375 X(_sxth, b200, fa0ff080), \
10376 X(_tst, 4200, ea100f00), \
10377 X(_uxtb, b2c0, fa5ff080), \
10378 X(_uxth, b280, fa1ff080), \
10379 X(_nop, bf00, f3af8000), \
10380 X(_yield, bf10, f3af8001), \
10381 X(_wfe, bf20, f3af8002), \
10382 X(_wfi, bf30, f3af8003), \
10383 X(_sev, bf40, f3af8004), \
10384 X(_sevl, bf50, f3af8005), \
10385 X(_udf, de00, f7f0a000)
10387 /* To catch errors in encoding functions, the codes are all offset by
10388 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10389 as 16-bit instructions. */
10390 #define X(a,b,c) T_MNEM##a
10391 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10394 #define X(a,b,c) 0x##b
10395 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10396 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10399 #define X(a,b,c) 0x##c
10400 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10401 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10402 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10406 /* Thumb instruction encoders, in alphabetical order. */
10408 /* ADDW or SUBW. */
10411 do_t_add_sub_w (void)
10415 Rd
= inst
.operands
[0].reg
;
10416 Rn
= inst
.operands
[1].reg
;
10418 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10419 is the SP-{plus,minus}-immediate form of the instruction. */
10421 constraint (Rd
== REG_PC
, BAD_PC
);
10423 reject_bad_reg (Rd
);
10425 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10426 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10429 /* Parse an add or subtract instruction. We get here with inst.instruction
10430 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
10433 do_t_add_sub (void)
10437 Rd
= inst
.operands
[0].reg
;
10438 Rs
= (inst
.operands
[1].present
10439 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10440 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10443 set_it_insn_type_last ();
10445 if (unified_syntax
)
10448 bfd_boolean narrow
;
10451 flags
= (inst
.instruction
== T_MNEM_adds
10452 || inst
.instruction
== T_MNEM_subs
);
10454 narrow
= !in_it_block ();
10456 narrow
= in_it_block ();
10457 if (!inst
.operands
[2].isreg
)
10461 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10463 add
= (inst
.instruction
== T_MNEM_add
10464 || inst
.instruction
== T_MNEM_adds
);
10466 if (inst
.size_req
!= 4)
10468 /* Attempt to use a narrow opcode, with relaxation if
10470 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10471 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10472 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10473 opcode
= T_MNEM_add_sp
;
10474 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10475 opcode
= T_MNEM_add_pc
;
10476 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10479 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10481 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10485 inst
.instruction
= THUMB_OP16(opcode
);
10486 inst
.instruction
|= (Rd
<< 4) | Rs
;
10487 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10488 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10490 if (inst
.size_req
== 2)
10491 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10493 inst
.relax
= opcode
;
10497 constraint (inst
.size_req
== 2, BAD_HIREG
);
10499 if (inst
.size_req
== 4
10500 || (inst
.size_req
!= 2 && !opcode
))
10502 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10503 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10504 THUMB1_RELOC_ONLY
);
10507 constraint (add
, BAD_PC
);
10508 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10509 _("only SUBS PC, LR, #const allowed"));
10510 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10511 _("expression too complex"));
10512 constraint (inst
.reloc
.exp
.X_add_number
< 0
10513 || inst
.reloc
.exp
.X_add_number
> 0xff,
10514 _("immediate value out of range"));
10515 inst
.instruction
= T2_SUBS_PC_LR
10516 | inst
.reloc
.exp
.X_add_number
;
10517 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10520 else if (Rs
== REG_PC
)
10522 /* Always use addw/subw. */
10523 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10524 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10528 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10529 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10532 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10534 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10536 inst
.instruction
|= Rd
<< 8;
10537 inst
.instruction
|= Rs
<< 16;
10542 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10543 unsigned int shift
= inst
.operands
[2].shift_kind
;
10545 Rn
= inst
.operands
[2].reg
;
10546 /* See if we can do this with a 16-bit instruction. */
10547 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10549 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10554 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10555 || inst
.instruction
== T_MNEM_add
)
10557 : T_OPCODE_SUB_R3
);
10558 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10562 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10564 /* Thumb-1 cores (except v6-M) require at least one high
10565 register in a narrow non flag setting add. */
10566 if (Rd
> 7 || Rn
> 7
10567 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10568 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10575 inst
.instruction
= T_OPCODE_ADD_HI
;
10576 inst
.instruction
|= (Rd
& 8) << 4;
10577 inst
.instruction
|= (Rd
& 7);
10578 inst
.instruction
|= Rn
<< 3;
10584 constraint (Rd
== REG_PC
, BAD_PC
);
10585 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10586 constraint (Rs
== REG_PC
, BAD_PC
);
10587 reject_bad_reg (Rn
);
10589 /* If we get here, it can't be done in 16 bits. */
10590 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10591 _("shift must be constant"));
10592 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10593 inst
.instruction
|= Rd
<< 8;
10594 inst
.instruction
|= Rs
<< 16;
10595 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10596 _("shift value over 3 not allowed in thumb mode"));
10597 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10598 _("only LSL shift allowed in thumb mode"));
10599 encode_thumb32_shifted_operand (2);
10604 constraint (inst
.instruction
== T_MNEM_adds
10605 || inst
.instruction
== T_MNEM_subs
,
10608 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10610 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10611 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10614 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10615 ? 0x0000 : 0x8000);
10616 inst
.instruction
|= (Rd
<< 4) | Rs
;
10617 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10621 Rn
= inst
.operands
[2].reg
;
10622 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10624 /* We now have Rd, Rs, and Rn set to registers. */
10625 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10627 /* Can't do this for SUB. */
10628 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10629 inst
.instruction
= T_OPCODE_ADD_HI
;
10630 inst
.instruction
|= (Rd
& 8) << 4;
10631 inst
.instruction
|= (Rd
& 7);
10633 inst
.instruction
|= Rn
<< 3;
10635 inst
.instruction
|= Rs
<< 3;
10637 constraint (1, _("dest must overlap one source register"));
10641 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10642 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10643 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10653 Rd
= inst
.operands
[0].reg
;
10654 reject_bad_reg (Rd
);
10656 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10658 /* Defer to section relaxation. */
10659 inst
.relax
= inst
.instruction
;
10660 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10661 inst
.instruction
|= Rd
<< 4;
10663 else if (unified_syntax
&& inst
.size_req
!= 2)
10665 /* Generate a 32-bit opcode. */
10666 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10667 inst
.instruction
|= Rd
<< 8;
10668 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10669 inst
.reloc
.pc_rel
= 1;
10673 /* Generate a 16-bit opcode. */
10674 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10675 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10676 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10677 inst
.reloc
.pc_rel
= 1;
10679 inst
.instruction
|= Rd
<< 4;
10683 /* Arithmetic instructions for which there is just one 16-bit
10684 instruction encoding, and it allows only two low registers.
10685 For maximal compatibility with ARM syntax, we allow three register
10686 operands even when Thumb-32 instructions are not available, as long
10687 as the first two are identical. For instance, both "sbc r0,r1" and
10688 "sbc r0,r0,r1" are allowed. */
10694 Rd
= inst
.operands
[0].reg
;
10695 Rs
= (inst
.operands
[1].present
10696 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10697 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10698 Rn
= inst
.operands
[2].reg
;
10700 reject_bad_reg (Rd
);
10701 reject_bad_reg (Rs
);
10702 if (inst
.operands
[2].isreg
)
10703 reject_bad_reg (Rn
);
10705 if (unified_syntax
)
10707 if (!inst
.operands
[2].isreg
)
10709 /* For an immediate, we always generate a 32-bit opcode;
10710 section relaxation will shrink it later if possible. */
10711 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10712 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10713 inst
.instruction
|= Rd
<< 8;
10714 inst
.instruction
|= Rs
<< 16;
10715 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10719 bfd_boolean narrow
;
10721 /* See if we can do this with a 16-bit instruction. */
10722 if (THUMB_SETS_FLAGS (inst
.instruction
))
10723 narrow
= !in_it_block ();
10725 narrow
= in_it_block ();
10727 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10729 if (inst
.operands
[2].shifted
)
10731 if (inst
.size_req
== 4)
10737 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10738 inst
.instruction
|= Rd
;
10739 inst
.instruction
|= Rn
<< 3;
10743 /* If we get here, it can't be done in 16 bits. */
10744 constraint (inst
.operands
[2].shifted
10745 && inst
.operands
[2].immisreg
,
10746 _("shift must be constant"));
10747 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10748 inst
.instruction
|= Rd
<< 8;
10749 inst
.instruction
|= Rs
<< 16;
10750 encode_thumb32_shifted_operand (2);
10755 /* On its face this is a lie - the instruction does set the
10756 flags. However, the only supported mnemonic in this mode
10757 says it doesn't. */
10758 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10760 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10761 _("unshifted register required"));
10762 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10763 constraint (Rd
!= Rs
,
10764 _("dest and source1 must be the same register"));
10766 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10767 inst
.instruction
|= Rd
;
10768 inst
.instruction
|= Rn
<< 3;
10772 /* Similarly, but for instructions where the arithmetic operation is
10773 commutative, so we can allow either of them to be different from
10774 the destination operand in a 16-bit instruction. For instance, all
10775 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10782 Rd
= inst
.operands
[0].reg
;
10783 Rs
= (inst
.operands
[1].present
10784 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10785 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10786 Rn
= inst
.operands
[2].reg
;
10788 reject_bad_reg (Rd
);
10789 reject_bad_reg (Rs
);
10790 if (inst
.operands
[2].isreg
)
10791 reject_bad_reg (Rn
);
10793 if (unified_syntax
)
10795 if (!inst
.operands
[2].isreg
)
10797 /* For an immediate, we always generate a 32-bit opcode;
10798 section relaxation will shrink it later if possible. */
10799 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10800 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10801 inst
.instruction
|= Rd
<< 8;
10802 inst
.instruction
|= Rs
<< 16;
10803 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10807 bfd_boolean narrow
;
10809 /* See if we can do this with a 16-bit instruction. */
10810 if (THUMB_SETS_FLAGS (inst
.instruction
))
10811 narrow
= !in_it_block ();
10813 narrow
= in_it_block ();
10815 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10817 if (inst
.operands
[2].shifted
)
10819 if (inst
.size_req
== 4)
10826 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10827 inst
.instruction
|= Rd
;
10828 inst
.instruction
|= Rn
<< 3;
10833 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10834 inst
.instruction
|= Rd
;
10835 inst
.instruction
|= Rs
<< 3;
10840 /* If we get here, it can't be done in 16 bits. */
10841 constraint (inst
.operands
[2].shifted
10842 && inst
.operands
[2].immisreg
,
10843 _("shift must be constant"));
10844 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10845 inst
.instruction
|= Rd
<< 8;
10846 inst
.instruction
|= Rs
<< 16;
10847 encode_thumb32_shifted_operand (2);
10852 /* On its face this is a lie - the instruction does set the
10853 flags. However, the only supported mnemonic in this mode
10854 says it doesn't. */
10855 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10857 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10858 _("unshifted register required"));
10859 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10861 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10862 inst
.instruction
|= Rd
;
10865 inst
.instruction
|= Rn
<< 3;
10867 inst
.instruction
|= Rs
<< 3;
10869 constraint (1, _("dest must overlap one source register"));
10877 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10878 constraint (msb
> 32, _("bit-field extends past end of register"));
10879 /* The instruction encoding stores the LSB and MSB,
10880 not the LSB and width. */
10881 Rd
= inst
.operands
[0].reg
;
10882 reject_bad_reg (Rd
);
10883 inst
.instruction
|= Rd
<< 8;
10884 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10885 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10886 inst
.instruction
|= msb
- 1;
10895 Rd
= inst
.operands
[0].reg
;
10896 reject_bad_reg (Rd
);
10898 /* #0 in second position is alternative syntax for bfc, which is
10899 the same instruction but with REG_PC in the Rm field. */
10900 if (!inst
.operands
[1].isreg
)
10904 Rn
= inst
.operands
[1].reg
;
10905 reject_bad_reg (Rn
);
10908 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10909 constraint (msb
> 32, _("bit-field extends past end of register"));
10910 /* The instruction encoding stores the LSB and MSB,
10911 not the LSB and width. */
10912 inst
.instruction
|= Rd
<< 8;
10913 inst
.instruction
|= Rn
<< 16;
10914 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10915 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10916 inst
.instruction
|= msb
- 1;
10924 Rd
= inst
.operands
[0].reg
;
10925 Rn
= inst
.operands
[1].reg
;
10927 reject_bad_reg (Rd
);
10928 reject_bad_reg (Rn
);
10930 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10931 _("bit-field extends past end of register"));
10932 inst
.instruction
|= Rd
<< 8;
10933 inst
.instruction
|= Rn
<< 16;
10934 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10935 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10936 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10939 /* ARM V5 Thumb BLX (argument parse)
10940 BLX <target_addr> which is BLX(1)
10941 BLX <Rm> which is BLX(2)
10942 Unfortunately, there are two different opcodes for this mnemonic.
10943 So, the insns[].value is not used, and the code here zaps values
10944 into inst.instruction.
10946 ??? How to take advantage of the additional two bits of displacement
10947 available in Thumb32 mode? Need new relocation? */
10952 set_it_insn_type_last ();
10954 if (inst
.operands
[0].isreg
)
10956 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10957 /* We have a register, so this is BLX(2). */
10958 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10962 /* No register. This must be BLX(1). */
10963 inst
.instruction
= 0xf000e800;
10964 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10973 bfd_reloc_code_real_type reloc
;
10976 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10978 if (in_it_block ())
10980 /* Conditional branches inside IT blocks are encoded as unconditional
10982 cond
= COND_ALWAYS
;
10987 if (cond
!= COND_ALWAYS
)
10988 opcode
= T_MNEM_bcond
;
10990 opcode
= inst
.instruction
;
10993 && (inst
.size_req
== 4
10994 || (inst
.size_req
!= 2
10995 && (inst
.operands
[0].hasreloc
10996 || inst
.reloc
.exp
.X_op
== O_constant
))))
10998 inst
.instruction
= THUMB_OP32(opcode
);
10999 if (cond
== COND_ALWAYS
)
11000 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11003 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11004 _("selected architecture does not support "
11005 "wide conditional branch instruction"));
11007 gas_assert (cond
!= 0xF);
11008 inst
.instruction
|= cond
<< 22;
11009 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11014 inst
.instruction
= THUMB_OP16(opcode
);
11015 if (cond
== COND_ALWAYS
)
11016 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11019 inst
.instruction
|= cond
<< 8;
11020 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11022 /* Allow section relaxation. */
11023 if (unified_syntax
&& inst
.size_req
!= 2)
11024 inst
.relax
= opcode
;
11026 inst
.reloc
.type
= reloc
;
11027 inst
.reloc
.pc_rel
= 1;
11030 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11031 between the two is the maximum immediate allowed - which is passed in
11034 do_t_bkpt_hlt1 (int range
)
11036 constraint (inst
.cond
!= COND_ALWAYS
,
11037 _("instruction is always unconditional"));
11038 if (inst
.operands
[0].present
)
11040 constraint (inst
.operands
[0].imm
> range
,
11041 _("immediate value out of range"));
11042 inst
.instruction
|= inst
.operands
[0].imm
;
11045 set_it_insn_type (NEUTRAL_IT_INSN
);
11051 do_t_bkpt_hlt1 (63);
11057 do_t_bkpt_hlt1 (255);
11061 do_t_branch23 (void)
11063 set_it_insn_type_last ();
11064 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11066 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11067 this file. We used to simply ignore the PLT reloc type here --
11068 the branch encoding is now needed to deal with TLSCALL relocs.
11069 So if we see a PLT reloc now, put it back to how it used to be to
11070 keep the preexisting behaviour. */
11071 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11072 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11074 #if defined(OBJ_COFF)
11075 /* If the destination of the branch is a defined symbol which does not have
11076 the THUMB_FUNC attribute, then we must be calling a function which has
11077 the (interfacearm) attribute. We look for the Thumb entry point to that
11078 function and change the branch to refer to that function instead. */
11079 if ( inst
.reloc
.exp
.X_op
== O_symbol
11080 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11081 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11082 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11083 inst
.reloc
.exp
.X_add_symbol
=
11084 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11091 set_it_insn_type_last ();
11092 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11093 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11094 should cause the alignment to be checked once it is known. This is
11095 because BX PC only works if the instruction is word aligned. */
11103 set_it_insn_type_last ();
11104 Rm
= inst
.operands
[0].reg
;
11105 reject_bad_reg (Rm
);
11106 inst
.instruction
|= Rm
<< 16;
11115 Rd
= inst
.operands
[0].reg
;
11116 Rm
= inst
.operands
[1].reg
;
11118 reject_bad_reg (Rd
);
11119 reject_bad_reg (Rm
);
11121 inst
.instruction
|= Rd
<< 8;
11122 inst
.instruction
|= Rm
<< 16;
11123 inst
.instruction
|= Rm
;
11129 set_it_insn_type (OUTSIDE_IT_INSN
);
11130 inst
.instruction
|= inst
.operands
[0].imm
;
11136 set_it_insn_type (OUTSIDE_IT_INSN
);
11138 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11139 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11141 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11142 inst
.instruction
= 0xf3af8000;
11143 inst
.instruction
|= imod
<< 9;
11144 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11145 if (inst
.operands
[1].present
)
11146 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11150 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11151 && (inst
.operands
[0].imm
& 4),
11152 _("selected processor does not support 'A' form "
11153 "of this instruction"));
11154 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11155 _("Thumb does not support the 2-argument "
11156 "form of this instruction"));
11157 inst
.instruction
|= inst
.operands
[0].imm
;
11161 /* THUMB CPY instruction (argument parse). */
11166 if (inst
.size_req
== 4)
11168 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11169 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11170 inst
.instruction
|= inst
.operands
[1].reg
;
11174 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11175 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11176 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11183 set_it_insn_type (OUTSIDE_IT_INSN
);
11184 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11185 inst
.instruction
|= inst
.operands
[0].reg
;
11186 inst
.reloc
.pc_rel
= 1;
11187 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11193 inst
.instruction
|= inst
.operands
[0].imm
;
11199 unsigned Rd
, Rn
, Rm
;
11201 Rd
= inst
.operands
[0].reg
;
11202 Rn
= (inst
.operands
[1].present
11203 ? inst
.operands
[1].reg
: Rd
);
11204 Rm
= inst
.operands
[2].reg
;
11206 reject_bad_reg (Rd
);
11207 reject_bad_reg (Rn
);
11208 reject_bad_reg (Rm
);
11210 inst
.instruction
|= Rd
<< 8;
11211 inst
.instruction
|= Rn
<< 16;
11212 inst
.instruction
|= Rm
;
11218 if (unified_syntax
&& inst
.size_req
== 4)
11219 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11221 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11227 unsigned int cond
= inst
.operands
[0].imm
;
11229 set_it_insn_type (IT_INSN
);
11230 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11232 now_it
.warn_deprecated
= FALSE
;
11234 /* If the condition is a negative condition, invert the mask. */
11235 if ((cond
& 0x1) == 0x0)
11237 unsigned int mask
= inst
.instruction
& 0x000f;
11239 if ((mask
& 0x7) == 0)
11241 /* No conversion needed. */
11242 now_it
.block_length
= 1;
11244 else if ((mask
& 0x3) == 0)
11247 now_it
.block_length
= 2;
11249 else if ((mask
& 0x1) == 0)
11252 now_it
.block_length
= 3;
11257 now_it
.block_length
= 4;
11260 inst
.instruction
&= 0xfff0;
11261 inst
.instruction
|= mask
;
11264 inst
.instruction
|= cond
<< 4;
11267 /* Helper function used for both push/pop and ldm/stm. */
11269 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11273 load
= (inst
.instruction
& (1 << 20)) != 0;
11275 if (mask
& (1 << 13))
11276 inst
.error
= _("SP not allowed in register list");
11278 if ((mask
& (1 << base
)) != 0
11280 inst
.error
= _("having the base register in the register list when "
11281 "using write back is UNPREDICTABLE");
11285 if (mask
& (1 << 15))
11287 if (mask
& (1 << 14))
11288 inst
.error
= _("LR and PC should not both be in register list");
11290 set_it_insn_type_last ();
11295 if (mask
& (1 << 15))
11296 inst
.error
= _("PC not allowed in register list");
11299 if ((mask
& (mask
- 1)) == 0)
11301 /* Single register transfers implemented as str/ldr. */
11304 if (inst
.instruction
& (1 << 23))
11305 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11307 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11311 if (inst
.instruction
& (1 << 23))
11312 inst
.instruction
= 0x00800000; /* ia -> [base] */
11314 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11317 inst
.instruction
|= 0xf8400000;
11319 inst
.instruction
|= 0x00100000;
11321 mask
= ffs (mask
) - 1;
11324 else if (writeback
)
11325 inst
.instruction
|= WRITE_BACK
;
11327 inst
.instruction
|= mask
;
11328 inst
.instruction
|= base
<< 16;
11334 /* This really doesn't seem worth it. */
11335 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11336 _("expression too complex"));
11337 constraint (inst
.operands
[1].writeback
,
11338 _("Thumb load/store multiple does not support {reglist}^"));
11340 if (unified_syntax
)
11342 bfd_boolean narrow
;
11346 /* See if we can use a 16-bit instruction. */
11347 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11348 && inst
.size_req
!= 4
11349 && !(inst
.operands
[1].imm
& ~0xff))
11351 mask
= 1 << inst
.operands
[0].reg
;
11353 if (inst
.operands
[0].reg
<= 7)
11355 if (inst
.instruction
== T_MNEM_stmia
11356 ? inst
.operands
[0].writeback
11357 : (inst
.operands
[0].writeback
11358 == !(inst
.operands
[1].imm
& mask
)))
11360 if (inst
.instruction
== T_MNEM_stmia
11361 && (inst
.operands
[1].imm
& mask
)
11362 && (inst
.operands
[1].imm
& (mask
- 1)))
11363 as_warn (_("value stored for r%d is UNKNOWN"),
11364 inst
.operands
[0].reg
);
11366 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11367 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11368 inst
.instruction
|= inst
.operands
[1].imm
;
11371 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11373 /* This means 1 register in reg list one of 3 situations:
11374 1. Instruction is stmia, but without writeback.
11375 2. lmdia without writeback, but with Rn not in
11377 3. ldmia with writeback, but with Rn in reglist.
11378 Case 3 is UNPREDICTABLE behaviour, so we handle
11379 case 1 and 2 which can be converted into a 16-bit
11380 str or ldr. The SP cases are handled below. */
11381 unsigned long opcode
;
11382 /* First, record an error for Case 3. */
11383 if (inst
.operands
[1].imm
& mask
11384 && inst
.operands
[0].writeback
)
11386 _("having the base register in the register list when "
11387 "using write back is UNPREDICTABLE");
11389 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11391 inst
.instruction
= THUMB_OP16 (opcode
);
11392 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11393 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11397 else if (inst
.operands
[0] .reg
== REG_SP
)
11399 if (inst
.operands
[0].writeback
)
11402 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11403 ? T_MNEM_push
: T_MNEM_pop
);
11404 inst
.instruction
|= inst
.operands
[1].imm
;
11407 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11410 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11411 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11412 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11420 if (inst
.instruction
< 0xffff)
11421 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11423 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11424 inst
.operands
[0].writeback
);
11429 constraint (inst
.operands
[0].reg
> 7
11430 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11431 constraint (inst
.instruction
!= T_MNEM_ldmia
11432 && inst
.instruction
!= T_MNEM_stmia
,
11433 _("Thumb-2 instruction only valid in unified syntax"));
11434 if (inst
.instruction
== T_MNEM_stmia
)
11436 if (!inst
.operands
[0].writeback
)
11437 as_warn (_("this instruction will write back the base register"));
11438 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11439 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11440 as_warn (_("value stored for r%d is UNKNOWN"),
11441 inst
.operands
[0].reg
);
11445 if (!inst
.operands
[0].writeback
11446 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11447 as_warn (_("this instruction will write back the base register"));
11448 else if (inst
.operands
[0].writeback
11449 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11450 as_warn (_("this instruction will not write back the base register"));
11453 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11454 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11455 inst
.instruction
|= inst
.operands
[1].imm
;
11462 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11463 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11464 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11465 || inst
.operands
[1].negative
,
11468 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11470 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11471 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11472 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11478 if (!inst
.operands
[1].present
)
11480 constraint (inst
.operands
[0].reg
== REG_LR
,
11481 _("r14 not allowed as first register "
11482 "when second register is omitted"));
11483 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11485 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11488 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11489 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11490 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11496 unsigned long opcode
;
11499 if (inst
.operands
[0].isreg
11500 && !inst
.operands
[0].preind
11501 && inst
.operands
[0].reg
== REG_PC
)
11502 set_it_insn_type_last ();
11504 opcode
= inst
.instruction
;
11505 if (unified_syntax
)
11507 if (!inst
.operands
[1].isreg
)
11509 if (opcode
<= 0xffff)
11510 inst
.instruction
= THUMB_OP32 (opcode
);
11511 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11514 if (inst
.operands
[1].isreg
11515 && !inst
.operands
[1].writeback
11516 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11517 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11518 && opcode
<= 0xffff
11519 && inst
.size_req
!= 4)
11521 /* Insn may have a 16-bit form. */
11522 Rn
= inst
.operands
[1].reg
;
11523 if (inst
.operands
[1].immisreg
)
11525 inst
.instruction
= THUMB_OP16 (opcode
);
11527 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11529 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11530 reject_bad_reg (inst
.operands
[1].imm
);
11532 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11533 && opcode
!= T_MNEM_ldrsb
)
11534 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11535 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11542 if (inst
.reloc
.pc_rel
)
11543 opcode
= T_MNEM_ldr_pc2
;
11545 opcode
= T_MNEM_ldr_pc
;
11549 if (opcode
== T_MNEM_ldr
)
11550 opcode
= T_MNEM_ldr_sp
;
11552 opcode
= T_MNEM_str_sp
;
11554 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11558 inst
.instruction
= inst
.operands
[0].reg
;
11559 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11561 inst
.instruction
|= THUMB_OP16 (opcode
);
11562 if (inst
.size_req
== 2)
11563 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11565 inst
.relax
= opcode
;
11569 /* Definitely a 32-bit variant. */
11571 /* Warning for Erratum 752419. */
11572 if (opcode
== T_MNEM_ldr
11573 && inst
.operands
[0].reg
== REG_SP
11574 && inst
.operands
[1].writeback
== 1
11575 && !inst
.operands
[1].immisreg
)
11577 if (no_cpu_selected ()
11578 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11579 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11580 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11581 as_warn (_("This instruction may be unpredictable "
11582 "if executed on M-profile cores "
11583 "with interrupts enabled."));
11586 /* Do some validations regarding addressing modes. */
11587 if (inst
.operands
[1].immisreg
)
11588 reject_bad_reg (inst
.operands
[1].imm
);
11590 constraint (inst
.operands
[1].writeback
== 1
11591 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11594 inst
.instruction
= THUMB_OP32 (opcode
);
11595 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11596 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11597 check_ldr_r15_aligned ();
11601 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11603 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11605 /* Only [Rn,Rm] is acceptable. */
11606 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11607 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11608 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11609 || inst
.operands
[1].negative
,
11610 _("Thumb does not support this addressing mode"));
11611 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11615 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11616 if (!inst
.operands
[1].isreg
)
11617 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11620 constraint (!inst
.operands
[1].preind
11621 || inst
.operands
[1].shifted
11622 || inst
.operands
[1].writeback
,
11623 _("Thumb does not support this addressing mode"));
11624 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11626 constraint (inst
.instruction
& 0x0600,
11627 _("byte or halfword not valid for base register"));
11628 constraint (inst
.operands
[1].reg
== REG_PC
11629 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11630 _("r15 based store not allowed"));
11631 constraint (inst
.operands
[1].immisreg
,
11632 _("invalid base register for register offset"));
11634 if (inst
.operands
[1].reg
== REG_PC
)
11635 inst
.instruction
= T_OPCODE_LDR_PC
;
11636 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11637 inst
.instruction
= T_OPCODE_LDR_SP
;
11639 inst
.instruction
= T_OPCODE_STR_SP
;
11641 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11642 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11646 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11647 if (!inst
.operands
[1].immisreg
)
11649 /* Immediate offset. */
11650 inst
.instruction
|= inst
.operands
[0].reg
;
11651 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11652 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11656 /* Register offset. */
11657 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11658 constraint (inst
.operands
[1].negative
,
11659 _("Thumb does not support this addressing mode"));
11662 switch (inst
.instruction
)
11664 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11665 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11666 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11667 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11668 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11669 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11670 case 0x5600 /* ldrsb */:
11671 case 0x5e00 /* ldrsh */: break;
11675 inst
.instruction
|= inst
.operands
[0].reg
;
11676 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11677 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11683 if (!inst
.operands
[1].present
)
11685 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11686 constraint (inst
.operands
[0].reg
== REG_LR
,
11687 _("r14 not allowed here"));
11688 constraint (inst
.operands
[0].reg
== REG_R12
,
11689 _("r12 not allowed here"));
11692 if (inst
.operands
[2].writeback
11693 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11694 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11695 as_warn (_("base register written back, and overlaps "
11696 "one of transfer registers"));
11698 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11699 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11700 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11706 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11707 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11713 unsigned Rd
, Rn
, Rm
, Ra
;
11715 Rd
= inst
.operands
[0].reg
;
11716 Rn
= inst
.operands
[1].reg
;
11717 Rm
= inst
.operands
[2].reg
;
11718 Ra
= inst
.operands
[3].reg
;
11720 reject_bad_reg (Rd
);
11721 reject_bad_reg (Rn
);
11722 reject_bad_reg (Rm
);
11723 reject_bad_reg (Ra
);
11725 inst
.instruction
|= Rd
<< 8;
11726 inst
.instruction
|= Rn
<< 16;
11727 inst
.instruction
|= Rm
;
11728 inst
.instruction
|= Ra
<< 12;
11734 unsigned RdLo
, RdHi
, Rn
, Rm
;
11736 RdLo
= inst
.operands
[0].reg
;
11737 RdHi
= inst
.operands
[1].reg
;
11738 Rn
= inst
.operands
[2].reg
;
11739 Rm
= inst
.operands
[3].reg
;
11741 reject_bad_reg (RdLo
);
11742 reject_bad_reg (RdHi
);
11743 reject_bad_reg (Rn
);
11744 reject_bad_reg (Rm
);
11746 inst
.instruction
|= RdLo
<< 12;
11747 inst
.instruction
|= RdHi
<< 8;
11748 inst
.instruction
|= Rn
<< 16;
11749 inst
.instruction
|= Rm
;
11753 do_t_mov_cmp (void)
11757 Rn
= inst
.operands
[0].reg
;
11758 Rm
= inst
.operands
[1].reg
;
11761 set_it_insn_type_last ();
11763 if (unified_syntax
)
11765 int r0off
= (inst
.instruction
== T_MNEM_mov
11766 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11767 unsigned long opcode
;
11768 bfd_boolean narrow
;
11769 bfd_boolean low_regs
;
11771 low_regs
= (Rn
<= 7 && Rm
<= 7);
11772 opcode
= inst
.instruction
;
11773 if (in_it_block ())
11774 narrow
= opcode
!= T_MNEM_movs
;
11776 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11777 if (inst
.size_req
== 4
11778 || inst
.operands
[1].shifted
)
11781 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11782 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11783 && !inst
.operands
[1].shifted
11787 inst
.instruction
= T2_SUBS_PC_LR
;
11791 if (opcode
== T_MNEM_cmp
)
11793 constraint (Rn
== REG_PC
, BAD_PC
);
11796 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11798 warn_deprecated_sp (Rm
);
11799 /* R15 was documented as a valid choice for Rm in ARMv6,
11800 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11801 tools reject R15, so we do too. */
11802 constraint (Rm
== REG_PC
, BAD_PC
);
11805 reject_bad_reg (Rm
);
11807 else if (opcode
== T_MNEM_mov
11808 || opcode
== T_MNEM_movs
)
11810 if (inst
.operands
[1].isreg
)
11812 if (opcode
== T_MNEM_movs
)
11814 reject_bad_reg (Rn
);
11815 reject_bad_reg (Rm
);
11819 /* This is mov.n. */
11820 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11821 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11823 as_tsktsk (_("Use of r%u as a source register is "
11824 "deprecated when r%u is the destination "
11825 "register."), Rm
, Rn
);
11830 /* This is mov.w. */
11831 constraint (Rn
== REG_PC
, BAD_PC
);
11832 constraint (Rm
== REG_PC
, BAD_PC
);
11833 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11837 reject_bad_reg (Rn
);
11840 if (!inst
.operands
[1].isreg
)
11842 /* Immediate operand. */
11843 if (!in_it_block () && opcode
== T_MNEM_mov
)
11845 if (low_regs
&& narrow
)
11847 inst
.instruction
= THUMB_OP16 (opcode
);
11848 inst
.instruction
|= Rn
<< 8;
11849 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11850 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
11852 if (inst
.size_req
== 2)
11853 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11855 inst
.relax
= opcode
;
11860 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11861 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
11862 THUMB1_RELOC_ONLY
);
11864 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11865 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11866 inst
.instruction
|= Rn
<< r0off
;
11867 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11870 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11871 && (inst
.instruction
== T_MNEM_mov
11872 || inst
.instruction
== T_MNEM_movs
))
11874 /* Register shifts are encoded as separate shift instructions. */
11875 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11877 if (in_it_block ())
11882 if (inst
.size_req
== 4)
11885 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11891 switch (inst
.operands
[1].shift_kind
)
11894 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11897 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11900 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11903 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11909 inst
.instruction
= opcode
;
11912 inst
.instruction
|= Rn
;
11913 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11918 inst
.instruction
|= CONDS_BIT
;
11920 inst
.instruction
|= Rn
<< 8;
11921 inst
.instruction
|= Rm
<< 16;
11922 inst
.instruction
|= inst
.operands
[1].imm
;
11927 /* Some mov with immediate shift have narrow variants.
11928 Register shifts are handled above. */
11929 if (low_regs
&& inst
.operands
[1].shifted
11930 && (inst
.instruction
== T_MNEM_mov
11931 || inst
.instruction
== T_MNEM_movs
))
11933 if (in_it_block ())
11934 narrow
= (inst
.instruction
== T_MNEM_mov
);
11936 narrow
= (inst
.instruction
== T_MNEM_movs
);
11941 switch (inst
.operands
[1].shift_kind
)
11943 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11944 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11945 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11946 default: narrow
= FALSE
; break;
11952 inst
.instruction
|= Rn
;
11953 inst
.instruction
|= Rm
<< 3;
11954 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11958 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11959 inst
.instruction
|= Rn
<< r0off
;
11960 encode_thumb32_shifted_operand (1);
11964 switch (inst
.instruction
)
11967 /* In v4t or v5t a move of two lowregs produces unpredictable
11968 results. Don't allow this. */
11971 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11972 "MOV Rd, Rs with two low registers is not "
11973 "permitted on this architecture");
11974 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11978 inst
.instruction
= T_OPCODE_MOV_HR
;
11979 inst
.instruction
|= (Rn
& 0x8) << 4;
11980 inst
.instruction
|= (Rn
& 0x7);
11981 inst
.instruction
|= Rm
<< 3;
11985 /* We know we have low registers at this point.
11986 Generate LSLS Rd, Rs, #0. */
11987 inst
.instruction
= T_OPCODE_LSL_I
;
11988 inst
.instruction
|= Rn
;
11989 inst
.instruction
|= Rm
<< 3;
11995 inst
.instruction
= T_OPCODE_CMP_LR
;
11996 inst
.instruction
|= Rn
;
11997 inst
.instruction
|= Rm
<< 3;
12001 inst
.instruction
= T_OPCODE_CMP_HR
;
12002 inst
.instruction
|= (Rn
& 0x8) << 4;
12003 inst
.instruction
|= (Rn
& 0x7);
12004 inst
.instruction
|= Rm
<< 3;
12011 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12013 /* PR 10443: Do not silently ignore shifted operands. */
12014 constraint (inst
.operands
[1].shifted
,
12015 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12017 if (inst
.operands
[1].isreg
)
12019 if (Rn
< 8 && Rm
< 8)
12021 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12022 since a MOV instruction produces unpredictable results. */
12023 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12024 inst
.instruction
= T_OPCODE_ADD_I3
;
12026 inst
.instruction
= T_OPCODE_CMP_LR
;
12028 inst
.instruction
|= Rn
;
12029 inst
.instruction
|= Rm
<< 3;
12033 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12034 inst
.instruction
= T_OPCODE_MOV_HR
;
12036 inst
.instruction
= T_OPCODE_CMP_HR
;
12042 constraint (Rn
> 7,
12043 _("only lo regs allowed with immediate"));
12044 inst
.instruction
|= Rn
<< 8;
12045 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12056 top
= (inst
.instruction
& 0x00800000) != 0;
12057 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12059 constraint (top
, _(":lower16: not allowed this instruction"));
12060 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12062 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12064 constraint (!top
, _(":upper16: not allowed this instruction"));
12065 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12068 Rd
= inst
.operands
[0].reg
;
12069 reject_bad_reg (Rd
);
12071 inst
.instruction
|= Rd
<< 8;
12072 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12074 imm
= inst
.reloc
.exp
.X_add_number
;
12075 inst
.instruction
|= (imm
& 0xf000) << 4;
12076 inst
.instruction
|= (imm
& 0x0800) << 15;
12077 inst
.instruction
|= (imm
& 0x0700) << 4;
12078 inst
.instruction
|= (imm
& 0x00ff);
12083 do_t_mvn_tst (void)
12087 Rn
= inst
.operands
[0].reg
;
12088 Rm
= inst
.operands
[1].reg
;
12090 if (inst
.instruction
== T_MNEM_cmp
12091 || inst
.instruction
== T_MNEM_cmn
)
12092 constraint (Rn
== REG_PC
, BAD_PC
);
12094 reject_bad_reg (Rn
);
12095 reject_bad_reg (Rm
);
12097 if (unified_syntax
)
12099 int r0off
= (inst
.instruction
== T_MNEM_mvn
12100 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12101 bfd_boolean narrow
;
12103 if (inst
.size_req
== 4
12104 || inst
.instruction
> 0xffff
12105 || inst
.operands
[1].shifted
12106 || Rn
> 7 || Rm
> 7)
12108 else if (inst
.instruction
== T_MNEM_cmn
12109 || inst
.instruction
== T_MNEM_tst
)
12111 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12112 narrow
= !in_it_block ();
12114 narrow
= in_it_block ();
12116 if (!inst
.operands
[1].isreg
)
12118 /* For an immediate, we always generate a 32-bit opcode;
12119 section relaxation will shrink it later if possible. */
12120 if (inst
.instruction
< 0xffff)
12121 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12122 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12123 inst
.instruction
|= Rn
<< r0off
;
12124 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12128 /* See if we can do this with a 16-bit instruction. */
12131 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12132 inst
.instruction
|= Rn
;
12133 inst
.instruction
|= Rm
<< 3;
12137 constraint (inst
.operands
[1].shifted
12138 && inst
.operands
[1].immisreg
,
12139 _("shift must be constant"));
12140 if (inst
.instruction
< 0xffff)
12141 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12142 inst
.instruction
|= Rn
<< r0off
;
12143 encode_thumb32_shifted_operand (1);
12149 constraint (inst
.instruction
> 0xffff
12150 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12151 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12152 _("unshifted register required"));
12153 constraint (Rn
> 7 || Rm
> 7,
12156 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12157 inst
.instruction
|= Rn
;
12158 inst
.instruction
|= Rm
<< 3;
12167 if (do_vfp_nsyn_mrs () == SUCCESS
)
12170 Rd
= inst
.operands
[0].reg
;
12171 reject_bad_reg (Rd
);
12172 inst
.instruction
|= Rd
<< 8;
12174 if (inst
.operands
[1].isreg
)
12176 unsigned br
= inst
.operands
[1].reg
;
12177 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12178 as_bad (_("bad register for mrs"));
12180 inst
.instruction
|= br
& (0xf << 16);
12181 inst
.instruction
|= (br
& 0x300) >> 4;
12182 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12186 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12188 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12190 /* PR gas/12698: The constraint is only applied for m_profile.
12191 If the user has specified -march=all, we want to ignore it as
12192 we are building for any CPU type, including non-m variants. */
12193 bfd_boolean m_profile
=
12194 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12195 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12196 "not support requested special purpose register"));
12199 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12201 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12202 _("'APSR', 'CPSR' or 'SPSR' expected"));
12204 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12205 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12206 inst
.instruction
|= 0xf0000;
12216 if (do_vfp_nsyn_msr () == SUCCESS
)
12219 constraint (!inst
.operands
[1].isreg
,
12220 _("Thumb encoding does not support an immediate here"));
12222 if (inst
.operands
[0].isreg
)
12223 flags
= (int)(inst
.operands
[0].reg
);
12225 flags
= inst
.operands
[0].imm
;
12227 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12229 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12231 /* PR gas/12698: The constraint is only applied for m_profile.
12232 If the user has specified -march=all, we want to ignore it as
12233 we are building for any CPU type, including non-m variants. */
12234 bfd_boolean m_profile
=
12235 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12236 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12237 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12238 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12239 && bits
!= PSR_f
)) && m_profile
,
12240 _("selected processor does not support requested special "
12241 "purpose register"));
12244 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12245 "requested special purpose register"));
12247 Rn
= inst
.operands
[1].reg
;
12248 reject_bad_reg (Rn
);
12250 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12251 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12252 inst
.instruction
|= (flags
& 0x300) >> 4;
12253 inst
.instruction
|= (flags
& 0xff);
12254 inst
.instruction
|= Rn
<< 16;
12260 bfd_boolean narrow
;
12261 unsigned Rd
, Rn
, Rm
;
12263 if (!inst
.operands
[2].present
)
12264 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12266 Rd
= inst
.operands
[0].reg
;
12267 Rn
= inst
.operands
[1].reg
;
12268 Rm
= inst
.operands
[2].reg
;
12270 if (unified_syntax
)
12272 if (inst
.size_req
== 4
12278 else if (inst
.instruction
== T_MNEM_muls
)
12279 narrow
= !in_it_block ();
12281 narrow
= in_it_block ();
12285 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12286 constraint (Rn
> 7 || Rm
> 7,
12293 /* 16-bit MULS/Conditional MUL. */
12294 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12295 inst
.instruction
|= Rd
;
12298 inst
.instruction
|= Rm
<< 3;
12300 inst
.instruction
|= Rn
<< 3;
12302 constraint (1, _("dest must overlap one source register"));
12306 constraint (inst
.instruction
!= T_MNEM_mul
,
12307 _("Thumb-2 MUL must not set flags"));
12309 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12310 inst
.instruction
|= Rd
<< 8;
12311 inst
.instruction
|= Rn
<< 16;
12312 inst
.instruction
|= Rm
<< 0;
12314 reject_bad_reg (Rd
);
12315 reject_bad_reg (Rn
);
12316 reject_bad_reg (Rm
);
12323 unsigned RdLo
, RdHi
, Rn
, Rm
;
12325 RdLo
= inst
.operands
[0].reg
;
12326 RdHi
= inst
.operands
[1].reg
;
12327 Rn
= inst
.operands
[2].reg
;
12328 Rm
= inst
.operands
[3].reg
;
12330 reject_bad_reg (RdLo
);
12331 reject_bad_reg (RdHi
);
12332 reject_bad_reg (Rn
);
12333 reject_bad_reg (Rm
);
12335 inst
.instruction
|= RdLo
<< 12;
12336 inst
.instruction
|= RdHi
<< 8;
12337 inst
.instruction
|= Rn
<< 16;
12338 inst
.instruction
|= Rm
;
12341 as_tsktsk (_("rdhi and rdlo must be different"));
12347 set_it_insn_type (NEUTRAL_IT_INSN
);
12349 if (unified_syntax
)
12351 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12353 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12354 inst
.instruction
|= inst
.operands
[0].imm
;
12358 /* PR9722: Check for Thumb2 availability before
12359 generating a thumb2 nop instruction. */
12360 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12362 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12363 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12366 inst
.instruction
= 0x46c0;
12371 constraint (inst
.operands
[0].present
,
12372 _("Thumb does not support NOP with hints"));
12373 inst
.instruction
= 0x46c0;
12380 if (unified_syntax
)
12382 bfd_boolean narrow
;
12384 if (THUMB_SETS_FLAGS (inst
.instruction
))
12385 narrow
= !in_it_block ();
12387 narrow
= in_it_block ();
12388 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12390 if (inst
.size_req
== 4)
12395 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12396 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12397 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12401 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12402 inst
.instruction
|= inst
.operands
[0].reg
;
12403 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12408 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12410 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12412 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12413 inst
.instruction
|= inst
.operands
[0].reg
;
12414 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12423 Rd
= inst
.operands
[0].reg
;
12424 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12426 reject_bad_reg (Rd
);
12427 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12428 reject_bad_reg (Rn
);
12430 inst
.instruction
|= Rd
<< 8;
12431 inst
.instruction
|= Rn
<< 16;
12433 if (!inst
.operands
[2].isreg
)
12435 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12436 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12442 Rm
= inst
.operands
[2].reg
;
12443 reject_bad_reg (Rm
);
12445 constraint (inst
.operands
[2].shifted
12446 && inst
.operands
[2].immisreg
,
12447 _("shift must be constant"));
12448 encode_thumb32_shifted_operand (2);
12455 unsigned Rd
, Rn
, Rm
;
12457 Rd
= inst
.operands
[0].reg
;
12458 Rn
= inst
.operands
[1].reg
;
12459 Rm
= inst
.operands
[2].reg
;
12461 reject_bad_reg (Rd
);
12462 reject_bad_reg (Rn
);
12463 reject_bad_reg (Rm
);
12465 inst
.instruction
|= Rd
<< 8;
12466 inst
.instruction
|= Rn
<< 16;
12467 inst
.instruction
|= Rm
;
12468 if (inst
.operands
[3].present
)
12470 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12471 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12472 _("expression too complex"));
12473 inst
.instruction
|= (val
& 0x1c) << 10;
12474 inst
.instruction
|= (val
& 0x03) << 6;
12481 if (!inst
.operands
[3].present
)
12485 inst
.instruction
&= ~0x00000020;
12487 /* PR 10168. Swap the Rm and Rn registers. */
12488 Rtmp
= inst
.operands
[1].reg
;
12489 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12490 inst
.operands
[2].reg
= Rtmp
;
12498 if (inst
.operands
[0].immisreg
)
12499 reject_bad_reg (inst
.operands
[0].imm
);
12501 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12505 do_t_push_pop (void)
12509 constraint (inst
.operands
[0].writeback
,
12510 _("push/pop do not support {reglist}^"));
12511 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12512 _("expression too complex"));
12514 mask
= inst
.operands
[0].imm
;
12515 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12516 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12517 else if (inst
.size_req
!= 4
12518 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12519 ? REG_LR
: REG_PC
)))
12521 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12522 inst
.instruction
|= THUMB_PP_PC_LR
;
12523 inst
.instruction
|= mask
& 0xff;
12525 else if (unified_syntax
)
12527 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12528 encode_thumb2_ldmstm (13, mask
, TRUE
);
12532 inst
.error
= _("invalid register list to push/pop instruction");
12542 Rd
= inst
.operands
[0].reg
;
12543 Rm
= inst
.operands
[1].reg
;
12545 reject_bad_reg (Rd
);
12546 reject_bad_reg (Rm
);
12548 inst
.instruction
|= Rd
<< 8;
12549 inst
.instruction
|= Rm
<< 16;
12550 inst
.instruction
|= Rm
;
12558 Rd
= inst
.operands
[0].reg
;
12559 Rm
= inst
.operands
[1].reg
;
12561 reject_bad_reg (Rd
);
12562 reject_bad_reg (Rm
);
12564 if (Rd
<= 7 && Rm
<= 7
12565 && inst
.size_req
!= 4)
12567 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12568 inst
.instruction
|= Rd
;
12569 inst
.instruction
|= Rm
<< 3;
12571 else if (unified_syntax
)
12573 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12574 inst
.instruction
|= Rd
<< 8;
12575 inst
.instruction
|= Rm
<< 16;
12576 inst
.instruction
|= Rm
;
12579 inst
.error
= BAD_HIREG
;
12587 Rd
= inst
.operands
[0].reg
;
12588 Rm
= inst
.operands
[1].reg
;
12590 reject_bad_reg (Rd
);
12591 reject_bad_reg (Rm
);
12593 inst
.instruction
|= Rd
<< 8;
12594 inst
.instruction
|= Rm
;
12602 Rd
= inst
.operands
[0].reg
;
12603 Rs
= (inst
.operands
[1].present
12604 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12605 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12607 reject_bad_reg (Rd
);
12608 reject_bad_reg (Rs
);
12609 if (inst
.operands
[2].isreg
)
12610 reject_bad_reg (inst
.operands
[2].reg
);
12612 inst
.instruction
|= Rd
<< 8;
12613 inst
.instruction
|= Rs
<< 16;
12614 if (!inst
.operands
[2].isreg
)
12616 bfd_boolean narrow
;
12618 if ((inst
.instruction
& 0x00100000) != 0)
12619 narrow
= !in_it_block ();
12621 narrow
= in_it_block ();
12623 if (Rd
> 7 || Rs
> 7)
12626 if (inst
.size_req
== 4 || !unified_syntax
)
12629 if (inst
.reloc
.exp
.X_op
!= O_constant
12630 || inst
.reloc
.exp
.X_add_number
!= 0)
12633 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12634 relaxation, but it doesn't seem worth the hassle. */
12637 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12638 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12639 inst
.instruction
|= Rs
<< 3;
12640 inst
.instruction
|= Rd
;
12644 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12645 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12649 encode_thumb32_shifted_operand (2);
12655 if (warn_on_deprecated
12656 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12657 as_tsktsk (_("setend use is deprecated for ARMv8"));
12659 set_it_insn_type (OUTSIDE_IT_INSN
);
12660 if (inst
.operands
[0].imm
)
12661 inst
.instruction
|= 0x8;
12667 if (!inst
.operands
[1].present
)
12668 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12670 if (unified_syntax
)
12672 bfd_boolean narrow
;
12675 switch (inst
.instruction
)
12678 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12680 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12682 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12684 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12688 if (THUMB_SETS_FLAGS (inst
.instruction
))
12689 narrow
= !in_it_block ();
12691 narrow
= in_it_block ();
12692 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12694 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12696 if (inst
.operands
[2].isreg
12697 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12698 || inst
.operands
[2].reg
> 7))
12700 if (inst
.size_req
== 4)
12703 reject_bad_reg (inst
.operands
[0].reg
);
12704 reject_bad_reg (inst
.operands
[1].reg
);
12708 if (inst
.operands
[2].isreg
)
12710 reject_bad_reg (inst
.operands
[2].reg
);
12711 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12712 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12713 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12714 inst
.instruction
|= inst
.operands
[2].reg
;
12716 /* PR 12854: Error on extraneous shifts. */
12717 constraint (inst
.operands
[2].shifted
,
12718 _("extraneous shift as part of operand to shift insn"));
12722 inst
.operands
[1].shifted
= 1;
12723 inst
.operands
[1].shift_kind
= shift_kind
;
12724 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12725 ? T_MNEM_movs
: T_MNEM_mov
);
12726 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12727 encode_thumb32_shifted_operand (1);
12728 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12729 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12734 if (inst
.operands
[2].isreg
)
12736 switch (shift_kind
)
12738 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12739 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12740 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12741 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12745 inst
.instruction
|= inst
.operands
[0].reg
;
12746 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12748 /* PR 12854: Error on extraneous shifts. */
12749 constraint (inst
.operands
[2].shifted
,
12750 _("extraneous shift as part of operand to shift insn"));
12754 switch (shift_kind
)
12756 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12757 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12758 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12761 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12762 inst
.instruction
|= inst
.operands
[0].reg
;
12763 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12769 constraint (inst
.operands
[0].reg
> 7
12770 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12771 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12773 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12775 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12776 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12777 _("source1 and dest must be same register"));
12779 switch (inst
.instruction
)
12781 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12782 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12783 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12784 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12788 inst
.instruction
|= inst
.operands
[0].reg
;
12789 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12791 /* PR 12854: Error on extraneous shifts. */
12792 constraint (inst
.operands
[2].shifted
,
12793 _("extraneous shift as part of operand to shift insn"));
12797 switch (inst
.instruction
)
12799 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12800 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12801 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12802 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12805 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12806 inst
.instruction
|= inst
.operands
[0].reg
;
12807 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12815 unsigned Rd
, Rn
, Rm
;
12817 Rd
= inst
.operands
[0].reg
;
12818 Rn
= inst
.operands
[1].reg
;
12819 Rm
= inst
.operands
[2].reg
;
12821 reject_bad_reg (Rd
);
12822 reject_bad_reg (Rn
);
12823 reject_bad_reg (Rm
);
12825 inst
.instruction
|= Rd
<< 8;
12826 inst
.instruction
|= Rn
<< 16;
12827 inst
.instruction
|= Rm
;
12833 unsigned Rd
, Rn
, Rm
;
12835 Rd
= inst
.operands
[0].reg
;
12836 Rm
= inst
.operands
[1].reg
;
12837 Rn
= inst
.operands
[2].reg
;
12839 reject_bad_reg (Rd
);
12840 reject_bad_reg (Rn
);
12841 reject_bad_reg (Rm
);
12843 inst
.instruction
|= Rd
<< 8;
12844 inst
.instruction
|= Rn
<< 16;
12845 inst
.instruction
|= Rm
;
12851 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12853 _("SMC is not permitted on this architecture"));
12854 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12855 _("expression too complex"));
12856 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12857 inst
.instruction
|= (value
& 0xf000) >> 12;
12858 inst
.instruction
|= (value
& 0x0ff0);
12859 inst
.instruction
|= (value
& 0x000f) << 16;
12860 /* PR gas/15623: SMC instructions must be last in an IT block. */
12861 set_it_insn_type_last ();
12867 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12869 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12870 inst
.instruction
|= (value
& 0x0fff);
12871 inst
.instruction
|= (value
& 0xf000) << 4;
12875 do_t_ssat_usat (int bias
)
12879 Rd
= inst
.operands
[0].reg
;
12880 Rn
= inst
.operands
[2].reg
;
12882 reject_bad_reg (Rd
);
12883 reject_bad_reg (Rn
);
12885 inst
.instruction
|= Rd
<< 8;
12886 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12887 inst
.instruction
|= Rn
<< 16;
12889 if (inst
.operands
[3].present
)
12891 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12893 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12895 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12896 _("expression too complex"));
12898 if (shift_amount
!= 0)
12900 constraint (shift_amount
> 31,
12901 _("shift expression is too large"));
12903 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12904 inst
.instruction
|= 0x00200000; /* sh bit. */
12906 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12907 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12915 do_t_ssat_usat (1);
12923 Rd
= inst
.operands
[0].reg
;
12924 Rn
= inst
.operands
[2].reg
;
12926 reject_bad_reg (Rd
);
12927 reject_bad_reg (Rn
);
12929 inst
.instruction
|= Rd
<< 8;
12930 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12931 inst
.instruction
|= Rn
<< 16;
12937 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12938 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12939 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12940 || inst
.operands
[2].negative
,
12943 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12945 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12946 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12947 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12948 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12954 if (!inst
.operands
[2].present
)
12955 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12957 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12958 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12959 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12962 inst
.instruction
|= inst
.operands
[0].reg
;
12963 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12964 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12965 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12971 unsigned Rd
, Rn
, Rm
;
12973 Rd
= inst
.operands
[0].reg
;
12974 Rn
= inst
.operands
[1].reg
;
12975 Rm
= inst
.operands
[2].reg
;
12977 reject_bad_reg (Rd
);
12978 reject_bad_reg (Rn
);
12979 reject_bad_reg (Rm
);
12981 inst
.instruction
|= Rd
<< 8;
12982 inst
.instruction
|= Rn
<< 16;
12983 inst
.instruction
|= Rm
;
12984 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12992 Rd
= inst
.operands
[0].reg
;
12993 Rm
= inst
.operands
[1].reg
;
12995 reject_bad_reg (Rd
);
12996 reject_bad_reg (Rm
);
12998 if (inst
.instruction
<= 0xffff
12999 && inst
.size_req
!= 4
13000 && Rd
<= 7 && Rm
<= 7
13001 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13003 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13004 inst
.instruction
|= Rd
;
13005 inst
.instruction
|= Rm
<< 3;
13007 else if (unified_syntax
)
13009 if (inst
.instruction
<= 0xffff)
13010 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13011 inst
.instruction
|= Rd
<< 8;
13012 inst
.instruction
|= Rm
;
13013 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13017 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13018 _("Thumb encoding does not support rotation"));
13019 constraint (1, BAD_HIREG
);
13026 /* We have to do the following check manually as ARM_EXT_OS only applies
13028 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
13030 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
13031 /* This only applies to the v6m howver, not later architectures. */
13032 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
13033 as_bad (_("SVC is not permitted on this architecture"));
13034 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
13037 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13046 half
= (inst
.instruction
& 0x10) != 0;
13047 set_it_insn_type_last ();
13048 constraint (inst
.operands
[0].immisreg
,
13049 _("instruction requires register index"));
13051 Rn
= inst
.operands
[0].reg
;
13052 Rm
= inst
.operands
[0].imm
;
13054 constraint (Rn
== REG_SP
, BAD_SP
);
13055 reject_bad_reg (Rm
);
13057 constraint (!half
&& inst
.operands
[0].shifted
,
13058 _("instruction does not allow shifted index"));
13059 inst
.instruction
|= (Rn
<< 16) | Rm
;
13065 if (!inst
.operands
[0].present
)
13066 inst
.operands
[0].imm
= 0;
13068 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13070 constraint (inst
.size_req
== 2,
13071 _("immediate value out of range"));
13072 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13073 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13074 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13078 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13079 inst
.instruction
|= inst
.operands
[0].imm
;
13082 set_it_insn_type (NEUTRAL_IT_INSN
);
13089 do_t_ssat_usat (0);
13097 Rd
= inst
.operands
[0].reg
;
13098 Rn
= inst
.operands
[2].reg
;
13100 reject_bad_reg (Rd
);
13101 reject_bad_reg (Rn
);
13103 inst
.instruction
|= Rd
<< 8;
13104 inst
.instruction
|= inst
.operands
[1].imm
;
13105 inst
.instruction
|= Rn
<< 16;
13108 /* Neon instruction encoder helpers. */
13110 /* Encodings for the different types for various Neon opcodes. */
13112 /* An "invalid" code for the following tables. */
13115 struct neon_tab_entry
13118 unsigned float_or_poly
;
13119 unsigned scalar_or_imm
;
13122 /* Map overloaded Neon opcodes to their respective encodings. */
13123 #define NEON_ENC_TAB \
13124 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13125 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13126 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13127 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13128 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13129 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13130 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13131 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13132 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13133 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13134 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13135 /* Register variants of the following two instructions are encoded as
13136 vcge / vcgt with the operands reversed. */ \
13137 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13138 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13139 X(vfma, N_INV, 0x0000c10, N_INV), \
13140 X(vfms, N_INV, 0x0200c10, N_INV), \
13141 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13142 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13143 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13144 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13145 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13146 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13147 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13148 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13149 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13150 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13151 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13152 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13153 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13154 X(vshl, 0x0000400, N_INV, 0x0800510), \
13155 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13156 X(vand, 0x0000110, N_INV, 0x0800030), \
13157 X(vbic, 0x0100110, N_INV, 0x0800030), \
13158 X(veor, 0x1000110, N_INV, N_INV), \
13159 X(vorn, 0x0300110, N_INV, 0x0800010), \
13160 X(vorr, 0x0200110, N_INV, 0x0800010), \
13161 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13162 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13163 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13164 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13165 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13166 X(vst1, 0x0000000, 0x0800000, N_INV), \
13167 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13168 X(vst2, 0x0000100, 0x0800100, N_INV), \
13169 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13170 X(vst3, 0x0000200, 0x0800200, N_INV), \
13171 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13172 X(vst4, 0x0000300, 0x0800300, N_INV), \
13173 X(vmovn, 0x1b20200, N_INV, N_INV), \
13174 X(vtrn, 0x1b20080, N_INV, N_INV), \
13175 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13176 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13177 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13178 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13179 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13180 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13181 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13182 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13183 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13184 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13185 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13186 X(vseleq, 0xe000a00, N_INV, N_INV), \
13187 X(vselvs, 0xe100a00, N_INV, N_INV), \
13188 X(vselge, 0xe200a00, N_INV, N_INV), \
13189 X(vselgt, 0xe300a00, N_INV, N_INV), \
13190 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13191 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13192 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13193 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13194 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13195 X(aes, 0x3b00300, N_INV, N_INV), \
13196 X(sha3op, 0x2000c00, N_INV, N_INV), \
13197 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13198 X(sha2op, 0x3ba0380, N_INV, N_INV)
13202 #define X(OPC,I,F,S) N_MNEM_##OPC
13207 static const struct neon_tab_entry neon_enc_tab
[] =
13209 #define X(OPC,I,F,S) { (I), (F), (S) }
13214 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13215 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13216 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13217 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13218 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13219 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13220 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13221 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13222 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13223 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13224 #define NEON_ENC_SINGLE_(X) \
13225 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13226 #define NEON_ENC_DOUBLE_(X) \
13227 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13228 #define NEON_ENC_FPV8_(X) \
13229 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13231 #define NEON_ENCODE(type, inst) \
13234 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13235 inst.is_neon = 1; \
13239 #define check_neon_suffixes \
13242 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13244 as_bad (_("invalid neon suffix for non neon instruction")); \
13250 /* Define shapes for instruction operands. The following mnemonic characters
13251 are used in this table:
13253 F - VFP S<n> register
13254 D - Neon D<n> register
13255 Q - Neon Q<n> register
13259 L - D<n> register list
13261 This table is used to generate various data:
13262 - enumerations of the form NS_DDR to be used as arguments to
13264 - a table classifying shapes into single, double, quad, mixed.
13265 - a table used to drive neon_select_shape. */
13267 #define NEON_SHAPE_DEF \
13268 X(3, (D, D, D), DOUBLE), \
13269 X(3, (Q, Q, Q), QUAD), \
13270 X(3, (D, D, I), DOUBLE), \
13271 X(3, (Q, Q, I), QUAD), \
13272 X(3, (D, D, S), DOUBLE), \
13273 X(3, (Q, Q, S), QUAD), \
13274 X(2, (D, D), DOUBLE), \
13275 X(2, (Q, Q), QUAD), \
13276 X(2, (D, S), DOUBLE), \
13277 X(2, (Q, S), QUAD), \
13278 X(2, (D, R), DOUBLE), \
13279 X(2, (Q, R), QUAD), \
13280 X(2, (D, I), DOUBLE), \
13281 X(2, (Q, I), QUAD), \
13282 X(3, (D, L, D), DOUBLE), \
13283 X(2, (D, Q), MIXED), \
13284 X(2, (Q, D), MIXED), \
13285 X(3, (D, Q, I), MIXED), \
13286 X(3, (Q, D, I), MIXED), \
13287 X(3, (Q, D, D), MIXED), \
13288 X(3, (D, Q, Q), MIXED), \
13289 X(3, (Q, Q, D), MIXED), \
13290 X(3, (Q, D, S), MIXED), \
13291 X(3, (D, Q, S), MIXED), \
13292 X(4, (D, D, D, I), DOUBLE), \
13293 X(4, (Q, Q, Q, I), QUAD), \
13294 X(2, (F, F), SINGLE), \
13295 X(3, (F, F, F), SINGLE), \
13296 X(2, (F, I), SINGLE), \
13297 X(2, (F, D), MIXED), \
13298 X(2, (D, F), MIXED), \
13299 X(3, (F, F, I), MIXED), \
13300 X(4, (R, R, F, F), SINGLE), \
13301 X(4, (F, F, R, R), SINGLE), \
13302 X(3, (D, R, R), DOUBLE), \
13303 X(3, (R, R, D), DOUBLE), \
13304 X(2, (S, R), SINGLE), \
13305 X(2, (R, S), SINGLE), \
13306 X(2, (F, R), SINGLE), \
13307 X(2, (R, F), SINGLE), \
13308 /* Half float shape supported so far. */\
13309 X (2, (H, D), MIXED), \
13310 X (2, (D, H), MIXED), \
13311 X (2, (H, F), MIXED), \
13312 X (2, (F, H), MIXED), \
13313 X (2, (H, H), HALF), \
13314 X (2, (H, R), HALF), \
13315 X (2, (R, H), HALF), \
13316 X (2, (H, I), HALF), \
13317 X (3, (H, H, H), HALF), \
13318 X (3, (H, F, I), MIXED), \
13319 X (3, (F, H, I), MIXED)
13321 #define S2(A,B) NS_##A##B
13322 #define S3(A,B,C) NS_##A##B##C
13323 #define S4(A,B,C,D) NS_##A##B##C##D
13325 #define X(N, L, C) S##N L
13338 enum neon_shape_class
13347 #define X(N, L, C) SC_##C
13349 static enum neon_shape_class neon_shape_class
[] =
13368 /* Register widths of above. */
13369 static unsigned neon_shape_el_size
[] =
13381 struct neon_shape_info
13384 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13387 #define S2(A,B) { SE_##A, SE_##B }
13388 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13389 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13391 #define X(N, L, C) { N, S##N L }
13393 static struct neon_shape_info neon_shape_tab
[] =
13403 /* Bit masks used in type checking given instructions.
13404 'N_EQK' means the type must be the same as (or based on in some way) the key
13405 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13406 set, various other bits can be set as well in order to modify the meaning of
13407 the type constraint. */
13409 enum neon_type_mask
13433 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13434 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13435 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13436 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13437 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13438 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13439 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13440 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13441 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13442 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13443 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13445 N_MAX_NONSPECIAL
= N_P64
13448 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13450 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13451 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13452 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13453 #define N_S_32 (N_S8 | N_S16 | N_S32)
13454 #define N_F_16_32 (N_F16 | N_F32)
13455 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13456 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13457 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13458 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13460 /* Pass this as the first type argument to neon_check_type to ignore types
13462 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13464 /* Select a "shape" for the current instruction (describing register types or
13465 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13466 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13467 function of operand parsing, so this function doesn't need to be called.
13468 Shapes should be listed in order of decreasing length. */
13470 static enum neon_shape
13471 neon_select_shape (enum neon_shape shape
, ...)
13474 enum neon_shape first_shape
= shape
;
13476 /* Fix missing optional operands. FIXME: we don't know at this point how
13477 many arguments we should have, so this makes the assumption that we have
13478 > 1. This is true of all current Neon opcodes, I think, but may not be
13479 true in the future. */
13480 if (!inst
.operands
[1].present
)
13481 inst
.operands
[1] = inst
.operands
[0];
13483 va_start (ap
, shape
);
13485 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13490 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13492 if (!inst
.operands
[j
].present
)
13498 switch (neon_shape_tab
[shape
].el
[j
])
13500 /* If a .f16, .16, .u16, .s16 type specifier is given over
13501 a VFP single precision register operand, it's essentially
13502 means only half of the register is used.
13504 If the type specifier is given after the mnemonics, the
13505 information is stored in inst.vectype. If the type specifier
13506 is given after register operand, the information is stored
13507 in inst.operands[].vectype.
13509 When there is only one type specifier, and all the register
13510 operands are the same type of hardware register, the type
13511 specifier applies to all register operands.
13513 If no type specifier is given, the shape is inferred from
13514 operand information.
13517 vadd.f16 s0, s1, s2: NS_HHH
13518 vabs.f16 s0, s1: NS_HH
13519 vmov.f16 s0, r1: NS_HR
13520 vmov.f16 r0, s1: NS_RH
13521 vcvt.f16 r0, s1: NS_RH
13522 vcvt.f16.s32 s2, s2, #29: NS_HFI
13523 vcvt.f16.s32 s2, s2: NS_HF
13526 if (!(inst
.operands
[j
].isreg
13527 && inst
.operands
[j
].isvec
13528 && inst
.operands
[j
].issingle
13529 && !inst
.operands
[j
].isquad
13530 && ((inst
.vectype
.elems
== 1
13531 && inst
.vectype
.el
[0].size
== 16)
13532 || (inst
.vectype
.elems
> 1
13533 && inst
.vectype
.el
[j
].size
== 16)
13534 || (inst
.vectype
.elems
== 0
13535 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13536 && inst
.operands
[j
].vectype
.size
== 16))))
13541 if (!(inst
.operands
[j
].isreg
13542 && inst
.operands
[j
].isvec
13543 && inst
.operands
[j
].issingle
13544 && !inst
.operands
[j
].isquad
13545 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13546 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13547 || (inst
.vectype
.elems
== 0
13548 && (inst
.operands
[j
].vectype
.size
== 32
13549 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13554 if (!(inst
.operands
[j
].isreg
13555 && inst
.operands
[j
].isvec
13556 && !inst
.operands
[j
].isquad
13557 && !inst
.operands
[j
].issingle
))
13562 if (!(inst
.operands
[j
].isreg
13563 && !inst
.operands
[j
].isvec
))
13568 if (!(inst
.operands
[j
].isreg
13569 && inst
.operands
[j
].isvec
13570 && inst
.operands
[j
].isquad
13571 && !inst
.operands
[j
].issingle
))
13576 if (!(!inst
.operands
[j
].isreg
13577 && !inst
.operands
[j
].isscalar
))
13582 if (!(!inst
.operands
[j
].isreg
13583 && inst
.operands
[j
].isscalar
))
13593 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13594 /* We've matched all the entries in the shape table, and we don't
13595 have any left over operands which have not been matched. */
13601 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13602 first_error (_("invalid instruction shape"));
13607 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13608 means the Q bit should be set). */
13611 neon_quad (enum neon_shape shape
)
13613 return neon_shape_class
[shape
] == SC_QUAD
;
13617 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13620 /* Allow modification to be made to types which are constrained to be
13621 based on the key element, based on bits set alongside N_EQK. */
13622 if ((typebits
& N_EQK
) != 0)
13624 if ((typebits
& N_HLF
) != 0)
13626 else if ((typebits
& N_DBL
) != 0)
13628 if ((typebits
& N_SGN
) != 0)
13629 *g_type
= NT_signed
;
13630 else if ((typebits
& N_UNS
) != 0)
13631 *g_type
= NT_unsigned
;
13632 else if ((typebits
& N_INT
) != 0)
13633 *g_type
= NT_integer
;
13634 else if ((typebits
& N_FLT
) != 0)
13635 *g_type
= NT_float
;
13636 else if ((typebits
& N_SIZ
) != 0)
13637 *g_type
= NT_untyped
;
13641 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13642 operand type, i.e. the single type specified in a Neon instruction when it
13643 is the only one given. */
13645 static struct neon_type_el
13646 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13648 struct neon_type_el dest
= *key
;
13650 gas_assert ((thisarg
& N_EQK
) != 0);
13652 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13657 /* Convert Neon type and size into compact bitmask representation. */
13659 static enum neon_type_mask
13660 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13667 case 8: return N_8
;
13668 case 16: return N_16
;
13669 case 32: return N_32
;
13670 case 64: return N_64
;
13678 case 8: return N_I8
;
13679 case 16: return N_I16
;
13680 case 32: return N_I32
;
13681 case 64: return N_I64
;
13689 case 16: return N_F16
;
13690 case 32: return N_F32
;
13691 case 64: return N_F64
;
13699 case 8: return N_P8
;
13700 case 16: return N_P16
;
13701 case 64: return N_P64
;
13709 case 8: return N_S8
;
13710 case 16: return N_S16
;
13711 case 32: return N_S32
;
13712 case 64: return N_S64
;
13720 case 8: return N_U8
;
13721 case 16: return N_U16
;
13722 case 32: return N_U32
;
13723 case 64: return N_U64
;
13734 /* Convert compact Neon bitmask type representation to a type and size. Only
13735 handles the case where a single bit is set in the mask. */
13738 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13739 enum neon_type_mask mask
)
13741 if ((mask
& N_EQK
) != 0)
13744 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13746 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13748 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13750 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13755 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13757 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13758 *type
= NT_unsigned
;
13759 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13760 *type
= NT_integer
;
13761 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13762 *type
= NT_untyped
;
13763 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13765 else if ((mask
& (N_F_ALL
)) != 0)
13773 /* Modify a bitmask of allowed types. This is only needed for type
13777 modify_types_allowed (unsigned allowed
, unsigned mods
)
13780 enum neon_el_type type
;
13786 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13788 if (el_type_of_type_chk (&type
, &size
,
13789 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13791 neon_modify_type_size (mods
, &type
, &size
);
13792 destmask
|= type_chk_of_el_type (type
, size
);
13799 /* Check type and return type classification.
13800 The manual states (paraphrase): If one datatype is given, it indicates the
13802 - the second operand, if there is one
13803 - the operand, if there is no second operand
13804 - the result, if there are no operands.
13805 This isn't quite good enough though, so we use a concept of a "key" datatype
13806 which is set on a per-instruction basis, which is the one which matters when
13807 only one data type is written.
13808 Note: this function has side-effects (e.g. filling in missing operands). All
13809 Neon instructions should call it before performing bit encoding. */
13811 static struct neon_type_el
13812 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13815 unsigned i
, pass
, key_el
= 0;
13816 unsigned types
[NEON_MAX_TYPE_ELS
];
13817 enum neon_el_type k_type
= NT_invtype
;
13818 unsigned k_size
= -1u;
13819 struct neon_type_el badtype
= {NT_invtype
, -1};
13820 unsigned key_allowed
= 0;
13822 /* Optional registers in Neon instructions are always (not) in operand 1.
13823 Fill in the missing operand here, if it was omitted. */
13824 if (els
> 1 && !inst
.operands
[1].present
)
13825 inst
.operands
[1] = inst
.operands
[0];
13827 /* Suck up all the varargs. */
13829 for (i
= 0; i
< els
; i
++)
13831 unsigned thisarg
= va_arg (ap
, unsigned);
13832 if (thisarg
== N_IGNORE_TYPE
)
13837 types
[i
] = thisarg
;
13838 if ((thisarg
& N_KEY
) != 0)
13843 if (inst
.vectype
.elems
> 0)
13844 for (i
= 0; i
< els
; i
++)
13845 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13847 first_error (_("types specified in both the mnemonic and operands"));
13851 /* Duplicate inst.vectype elements here as necessary.
13852 FIXME: No idea if this is exactly the same as the ARM assembler,
13853 particularly when an insn takes one register and one non-register
13855 if (inst
.vectype
.elems
== 1 && els
> 1)
13858 inst
.vectype
.elems
= els
;
13859 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13860 for (j
= 0; j
< els
; j
++)
13862 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13865 else if (inst
.vectype
.elems
== 0 && els
> 0)
13868 /* No types were given after the mnemonic, so look for types specified
13869 after each operand. We allow some flexibility here; as long as the
13870 "key" operand has a type, we can infer the others. */
13871 for (j
= 0; j
< els
; j
++)
13872 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13873 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13875 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13877 for (j
= 0; j
< els
; j
++)
13878 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13879 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13884 first_error (_("operand types can't be inferred"));
13888 else if (inst
.vectype
.elems
!= els
)
13890 first_error (_("type specifier has the wrong number of parts"));
13894 for (pass
= 0; pass
< 2; pass
++)
13896 for (i
= 0; i
< els
; i
++)
13898 unsigned thisarg
= types
[i
];
13899 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13900 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13901 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13902 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13904 /* Decay more-specific signed & unsigned types to sign-insensitive
13905 integer types if sign-specific variants are unavailable. */
13906 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13907 && (types_allowed
& N_SU_ALL
) == 0)
13908 g_type
= NT_integer
;
13910 /* If only untyped args are allowed, decay any more specific types to
13911 them. Some instructions only care about signs for some element
13912 sizes, so handle that properly. */
13913 if (((types_allowed
& N_UNT
) == 0)
13914 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13915 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13916 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13917 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13918 g_type
= NT_untyped
;
13922 if ((thisarg
& N_KEY
) != 0)
13926 key_allowed
= thisarg
& ~N_KEY
;
13928 /* Check architecture constraint on FP16 extension. */
13930 && k_type
== NT_float
13931 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13933 inst
.error
= _(BAD_FP16
);
13940 if ((thisarg
& N_VFP
) != 0)
13942 enum neon_shape_el regshape
;
13943 unsigned regwidth
, match
;
13945 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13948 first_error (_("invalid instruction shape"));
13951 regshape
= neon_shape_tab
[ns
].el
[i
];
13952 regwidth
= neon_shape_el_size
[regshape
];
13954 /* In VFP mode, operands must match register widths. If we
13955 have a key operand, use its width, else use the width of
13956 the current operand. */
13962 /* FP16 will use a single precision register. */
13963 if (regwidth
== 32 && match
== 16)
13965 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
13969 inst
.error
= _(BAD_FP16
);
13974 if (regwidth
!= match
)
13976 first_error (_("operand size must match register width"));
13981 if ((thisarg
& N_EQK
) == 0)
13983 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13985 if ((given_type
& types_allowed
) == 0)
13987 first_error (_("bad type in Neon instruction"));
13993 enum neon_el_type mod_k_type
= k_type
;
13994 unsigned mod_k_size
= k_size
;
13995 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13996 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13998 first_error (_("inconsistent types in Neon instruction"));
14006 return inst
.vectype
.el
[key_el
];
14009 /* Neon-style VFP instruction forwarding. */
14011 /* Thumb VFP instructions have 0xE in the condition field. */
14014 do_vfp_cond_or_thumb (void)
14019 inst
.instruction
|= 0xe0000000;
14021 inst
.instruction
|= inst
.cond
<< 28;
14024 /* Look up and encode a simple mnemonic, for use as a helper function for the
14025 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14026 etc. It is assumed that operand parsing has already been done, and that the
14027 operands are in the form expected by the given opcode (this isn't necessarily
14028 the same as the form in which they were parsed, hence some massaging must
14029 take place before this function is called).
14030 Checks current arch version against that in the looked-up opcode. */
14033 do_vfp_nsyn_opcode (const char *opname
)
14035 const struct asm_opcode
*opcode
;
14037 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14042 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14043 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14050 inst
.instruction
= opcode
->tvalue
;
14051 opcode
->tencode ();
14055 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14056 opcode
->aencode ();
14061 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14063 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14065 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14068 do_vfp_nsyn_opcode ("fadds");
14070 do_vfp_nsyn_opcode ("fsubs");
14072 /* ARMv8.2 fp16 instruction. */
14074 do_scalar_fp16_v82_encode ();
14079 do_vfp_nsyn_opcode ("faddd");
14081 do_vfp_nsyn_opcode ("fsubd");
14085 /* Check operand types to see if this is a VFP instruction, and if so call
14089 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14091 enum neon_shape rs
;
14092 struct neon_type_el et
;
14097 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14098 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14102 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14103 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14104 N_F_ALL
| N_KEY
| N_VFP
);
14111 if (et
.type
!= NT_invtype
)
14122 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14124 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14126 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14129 do_vfp_nsyn_opcode ("fmacs");
14131 do_vfp_nsyn_opcode ("fnmacs");
14133 /* ARMv8.2 fp16 instruction. */
14135 do_scalar_fp16_v82_encode ();
14140 do_vfp_nsyn_opcode ("fmacd");
14142 do_vfp_nsyn_opcode ("fnmacd");
14147 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14149 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14151 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14154 do_vfp_nsyn_opcode ("ffmas");
14156 do_vfp_nsyn_opcode ("ffnmas");
14158 /* ARMv8.2 fp16 instruction. */
14160 do_scalar_fp16_v82_encode ();
14165 do_vfp_nsyn_opcode ("ffmad");
14167 do_vfp_nsyn_opcode ("ffnmad");
14172 do_vfp_nsyn_mul (enum neon_shape rs
)
14174 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14176 do_vfp_nsyn_opcode ("fmuls");
14178 /* ARMv8.2 fp16 instruction. */
14180 do_scalar_fp16_v82_encode ();
14183 do_vfp_nsyn_opcode ("fmuld");
14187 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14189 int is_neg
= (inst
.instruction
& 0x80) != 0;
14190 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14192 if (rs
== NS_FF
|| rs
== NS_HH
)
14195 do_vfp_nsyn_opcode ("fnegs");
14197 do_vfp_nsyn_opcode ("fabss");
14199 /* ARMv8.2 fp16 instruction. */
14201 do_scalar_fp16_v82_encode ();
14206 do_vfp_nsyn_opcode ("fnegd");
14208 do_vfp_nsyn_opcode ("fabsd");
14212 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14213 insns belong to Neon, and are handled elsewhere. */
14216 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14218 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14222 do_vfp_nsyn_opcode ("fldmdbs");
14224 do_vfp_nsyn_opcode ("fldmias");
14229 do_vfp_nsyn_opcode ("fstmdbs");
14231 do_vfp_nsyn_opcode ("fstmias");
14236 do_vfp_nsyn_sqrt (void)
14238 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14239 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14241 if (rs
== NS_FF
|| rs
== NS_HH
)
14243 do_vfp_nsyn_opcode ("fsqrts");
14245 /* ARMv8.2 fp16 instruction. */
14247 do_scalar_fp16_v82_encode ();
14250 do_vfp_nsyn_opcode ("fsqrtd");
14254 do_vfp_nsyn_div (void)
14256 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14257 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14258 N_F_ALL
| N_KEY
| N_VFP
);
14260 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14262 do_vfp_nsyn_opcode ("fdivs");
14264 /* ARMv8.2 fp16 instruction. */
14266 do_scalar_fp16_v82_encode ();
14269 do_vfp_nsyn_opcode ("fdivd");
14273 do_vfp_nsyn_nmul (void)
14275 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14276 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14277 N_F_ALL
| N_KEY
| N_VFP
);
14279 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14281 NEON_ENCODE (SINGLE
, inst
);
14282 do_vfp_sp_dyadic ();
14284 /* ARMv8.2 fp16 instruction. */
14286 do_scalar_fp16_v82_encode ();
14290 NEON_ENCODE (DOUBLE
, inst
);
14291 do_vfp_dp_rd_rn_rm ();
14293 do_vfp_cond_or_thumb ();
14298 do_vfp_nsyn_cmp (void)
14300 enum neon_shape rs
;
14301 if (inst
.operands
[1].isreg
)
14303 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14304 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14306 if (rs
== NS_FF
|| rs
== NS_HH
)
14308 NEON_ENCODE (SINGLE
, inst
);
14309 do_vfp_sp_monadic ();
14313 NEON_ENCODE (DOUBLE
, inst
);
14314 do_vfp_dp_rd_rm ();
14319 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14320 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14322 switch (inst
.instruction
& 0x0fffffff)
14325 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14328 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14334 if (rs
== NS_FI
|| rs
== NS_HI
)
14336 NEON_ENCODE (SINGLE
, inst
);
14337 do_vfp_sp_compare_z ();
14341 NEON_ENCODE (DOUBLE
, inst
);
14345 do_vfp_cond_or_thumb ();
14347 /* ARMv8.2 fp16 instruction. */
14348 if (rs
== NS_HI
|| rs
== NS_HH
)
14349 do_scalar_fp16_v82_encode ();
14353 nsyn_insert_sp (void)
14355 inst
.operands
[1] = inst
.operands
[0];
14356 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14357 inst
.operands
[0].reg
= REG_SP
;
14358 inst
.operands
[0].isreg
= 1;
14359 inst
.operands
[0].writeback
= 1;
14360 inst
.operands
[0].present
= 1;
14364 do_vfp_nsyn_push (void)
14367 if (inst
.operands
[1].issingle
)
14368 do_vfp_nsyn_opcode ("fstmdbs");
14370 do_vfp_nsyn_opcode ("fstmdbd");
14374 do_vfp_nsyn_pop (void)
14377 if (inst
.operands
[1].issingle
)
14378 do_vfp_nsyn_opcode ("fldmias");
14380 do_vfp_nsyn_opcode ("fldmiad");
14383 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14384 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14387 neon_dp_fixup (struct arm_it
* insn
)
14389 unsigned int i
= insn
->instruction
;
14394 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14405 insn
->instruction
= i
;
14408 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14412 neon_logbits (unsigned x
)
14414 return ffs (x
) - 4;
14417 #define LOW4(R) ((R) & 0xf)
14418 #define HI1(R) (((R) >> 4) & 1)
14420 /* Encode insns with bit pattern:
14422 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14423 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14425 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14426 different meaning for some instruction. */
14429 neon_three_same (int isquad
, int ubit
, int size
)
14431 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14432 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14433 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14434 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14435 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14436 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14437 inst
.instruction
|= (isquad
!= 0) << 6;
14438 inst
.instruction
|= (ubit
!= 0) << 24;
14440 inst
.instruction
|= neon_logbits (size
) << 20;
14442 neon_dp_fixup (&inst
);
14445 /* Encode instructions of the form:
14447 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14448 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14450 Don't write size if SIZE == -1. */
14453 neon_two_same (int qbit
, int ubit
, int size
)
14455 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14456 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14457 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14458 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14459 inst
.instruction
|= (qbit
!= 0) << 6;
14460 inst
.instruction
|= (ubit
!= 0) << 24;
14463 inst
.instruction
|= neon_logbits (size
) << 18;
14465 neon_dp_fixup (&inst
);
14468 /* Neon instruction encoders, in approximate order of appearance. */
14471 do_neon_dyadic_i_su (void)
14473 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14474 struct neon_type_el et
= neon_check_type (3, rs
,
14475 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14476 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14480 do_neon_dyadic_i64_su (void)
14482 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14483 struct neon_type_el et
= neon_check_type (3, rs
,
14484 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14485 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14489 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14492 unsigned size
= et
.size
>> 3;
14493 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14494 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14495 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14496 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14497 inst
.instruction
|= (isquad
!= 0) << 6;
14498 inst
.instruction
|= immbits
<< 16;
14499 inst
.instruction
|= (size
>> 3) << 7;
14500 inst
.instruction
|= (size
& 0x7) << 19;
14502 inst
.instruction
|= (uval
!= 0) << 24;
14504 neon_dp_fixup (&inst
);
14508 do_neon_shl_imm (void)
14510 if (!inst
.operands
[2].isreg
)
14512 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14513 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14514 int imm
= inst
.operands
[2].imm
;
14516 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14517 _("immediate out of range for shift"));
14518 NEON_ENCODE (IMMED
, inst
);
14519 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14523 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14524 struct neon_type_el et
= neon_check_type (3, rs
,
14525 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14528 /* VSHL/VQSHL 3-register variants have syntax such as:
14530 whereas other 3-register operations encoded by neon_three_same have
14533 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14535 tmp
= inst
.operands
[2].reg
;
14536 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14537 inst
.operands
[1].reg
= tmp
;
14538 NEON_ENCODE (INTEGER
, inst
);
14539 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14544 do_neon_qshl_imm (void)
14546 if (!inst
.operands
[2].isreg
)
14548 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14549 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14550 int imm
= inst
.operands
[2].imm
;
14552 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14553 _("immediate out of range for shift"));
14554 NEON_ENCODE (IMMED
, inst
);
14555 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14559 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14560 struct neon_type_el et
= neon_check_type (3, rs
,
14561 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14564 /* See note in do_neon_shl_imm. */
14565 tmp
= inst
.operands
[2].reg
;
14566 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14567 inst
.operands
[1].reg
= tmp
;
14568 NEON_ENCODE (INTEGER
, inst
);
14569 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14574 do_neon_rshl (void)
14576 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14577 struct neon_type_el et
= neon_check_type (3, rs
,
14578 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14581 tmp
= inst
.operands
[2].reg
;
14582 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14583 inst
.operands
[1].reg
= tmp
;
14584 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14588 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14590 /* Handle .I8 pseudo-instructions. */
14593 /* Unfortunately, this will make everything apart from zero out-of-range.
14594 FIXME is this the intended semantics? There doesn't seem much point in
14595 accepting .I8 if so. */
14596 immediate
|= immediate
<< 8;
14602 if (immediate
== (immediate
& 0x000000ff))
14604 *immbits
= immediate
;
14607 else if (immediate
== (immediate
& 0x0000ff00))
14609 *immbits
= immediate
>> 8;
14612 else if (immediate
== (immediate
& 0x00ff0000))
14614 *immbits
= immediate
>> 16;
14617 else if (immediate
== (immediate
& 0xff000000))
14619 *immbits
= immediate
>> 24;
14622 if ((immediate
& 0xffff) != (immediate
>> 16))
14623 goto bad_immediate
;
14624 immediate
&= 0xffff;
14627 if (immediate
== (immediate
& 0x000000ff))
14629 *immbits
= immediate
;
14632 else if (immediate
== (immediate
& 0x0000ff00))
14634 *immbits
= immediate
>> 8;
14639 first_error (_("immediate value out of range"));
14644 do_neon_logic (void)
14646 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14648 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14649 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14650 /* U bit and size field were set as part of the bitmask. */
14651 NEON_ENCODE (INTEGER
, inst
);
14652 neon_three_same (neon_quad (rs
), 0, -1);
14656 const int three_ops_form
= (inst
.operands
[2].present
14657 && !inst
.operands
[2].isreg
);
14658 const int immoperand
= (three_ops_form
? 2 : 1);
14659 enum neon_shape rs
= (three_ops_form
14660 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14661 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14662 struct neon_type_el et
= neon_check_type (2, rs
,
14663 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14664 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14668 if (et
.type
== NT_invtype
)
14671 if (three_ops_form
)
14672 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14673 _("first and second operands shall be the same register"));
14675 NEON_ENCODE (IMMED
, inst
);
14677 immbits
= inst
.operands
[immoperand
].imm
;
14680 /* .i64 is a pseudo-op, so the immediate must be a repeating
14682 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14683 inst
.operands
[immoperand
].reg
: 0))
14685 /* Set immbits to an invalid constant. */
14686 immbits
= 0xdeadbeef;
14693 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14697 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14701 /* Pseudo-instruction for VBIC. */
14702 neon_invert_size (&immbits
, 0, et
.size
);
14703 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14707 /* Pseudo-instruction for VORR. */
14708 neon_invert_size (&immbits
, 0, et
.size
);
14709 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14719 inst
.instruction
|= neon_quad (rs
) << 6;
14720 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14721 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14722 inst
.instruction
|= cmode
<< 8;
14723 neon_write_immbits (immbits
);
14725 neon_dp_fixup (&inst
);
14730 do_neon_bitfield (void)
14732 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14733 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14734 neon_three_same (neon_quad (rs
), 0, -1);
14738 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14741 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14742 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14744 if (et
.type
== NT_float
)
14746 NEON_ENCODE (FLOAT
, inst
);
14747 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14751 NEON_ENCODE (INTEGER
, inst
);
14752 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14757 do_neon_dyadic_if_su (void)
14759 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14763 do_neon_dyadic_if_su_d (void)
14765 /* This version only allow D registers, but that constraint is enforced during
14766 operand parsing so we don't need to do anything extra here. */
14767 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14771 do_neon_dyadic_if_i_d (void)
14773 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14774 affected if we specify unsigned args. */
14775 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14778 enum vfp_or_neon_is_neon_bits
14781 NEON_CHECK_ARCH
= 2,
14782 NEON_CHECK_ARCH8
= 4
14785 /* Call this function if an instruction which may have belonged to the VFP or
14786 Neon instruction sets, but turned out to be a Neon instruction (due to the
14787 operand types involved, etc.). We have to check and/or fix-up a couple of
14790 - Make sure the user hasn't attempted to make a Neon instruction
14792 - Alter the value in the condition code field if necessary.
14793 - Make sure that the arch supports Neon instructions.
14795 Which of these operations take place depends on bits from enum
14796 vfp_or_neon_is_neon_bits.
14798 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14799 current instruction's condition is COND_ALWAYS, the condition field is
14800 changed to inst.uncond_value. This is necessary because instructions shared
14801 between VFP and Neon may be conditional for the VFP variants only, and the
14802 unconditional Neon version must have, e.g., 0xF in the condition field. */
14805 vfp_or_neon_is_neon (unsigned check
)
14807 /* Conditions are always legal in Thumb mode (IT blocks). */
14808 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14810 if (inst
.cond
!= COND_ALWAYS
)
14812 first_error (_(BAD_COND
));
14815 if (inst
.uncond_value
!= -1)
14816 inst
.instruction
|= inst
.uncond_value
<< 28;
14819 if ((check
& NEON_CHECK_ARCH
)
14820 && !mark_feature_used (&fpu_neon_ext_v1
))
14822 first_error (_(BAD_FPU
));
14826 if ((check
& NEON_CHECK_ARCH8
)
14827 && !mark_feature_used (&fpu_neon_ext_armv8
))
14829 first_error (_(BAD_FPU
));
14837 do_neon_addsub_if_i (void)
14839 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14842 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14845 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14846 affected if we specify unsigned args. */
14847 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14850 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14852 V<op> A,B (A is operand 0, B is operand 2)
14857 so handle that case specially. */
14860 neon_exchange_operands (void)
14862 if (inst
.operands
[1].present
)
14864 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
14866 /* Swap operands[1] and operands[2]. */
14867 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14868 inst
.operands
[1] = inst
.operands
[2];
14869 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14874 inst
.operands
[1] = inst
.operands
[2];
14875 inst
.operands
[2] = inst
.operands
[0];
14880 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14882 if (inst
.operands
[2].isreg
)
14885 neon_exchange_operands ();
14886 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14890 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14891 struct neon_type_el et
= neon_check_type (2, rs
,
14892 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14894 NEON_ENCODE (IMMED
, inst
);
14895 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14896 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14897 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14898 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14899 inst
.instruction
|= neon_quad (rs
) << 6;
14900 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14901 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14903 neon_dp_fixup (&inst
);
14910 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
14914 do_neon_cmp_inv (void)
14916 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
14922 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14925 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14926 scalars, which are encoded in 5 bits, M : Rm.
14927 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14928 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14932 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14934 unsigned regno
= NEON_SCALAR_REG (scalar
);
14935 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14940 if (regno
> 7 || elno
> 3)
14942 return regno
| (elno
<< 3);
14945 if (regno
> 15 || elno
> 1)
14947 return regno
| (elno
<< 4);
14951 first_error (_("scalar out of range for multiply instruction"));
14957 /* Encode multiply / multiply-accumulate scalar instructions. */
14960 neon_mul_mac (struct neon_type_el et
, int ubit
)
14964 /* Give a more helpful error message if we have an invalid type. */
14965 if (et
.type
== NT_invtype
)
14968 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14969 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14970 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14971 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14972 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14973 inst
.instruction
|= LOW4 (scalar
);
14974 inst
.instruction
|= HI1 (scalar
) << 5;
14975 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14976 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14977 inst
.instruction
|= (ubit
!= 0) << 24;
14979 neon_dp_fixup (&inst
);
14983 do_neon_mac_maybe_scalar (void)
14985 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14988 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14991 if (inst
.operands
[2].isscalar
)
14993 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14994 struct neon_type_el et
= neon_check_type (3, rs
,
14995 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14996 NEON_ENCODE (SCALAR
, inst
);
14997 neon_mul_mac (et
, neon_quad (rs
));
15001 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15002 affected if we specify unsigned args. */
15003 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15008 do_neon_fmac (void)
15010 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15013 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15016 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15022 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15023 struct neon_type_el et
= neon_check_type (3, rs
,
15024 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15025 neon_three_same (neon_quad (rs
), 0, et
.size
);
15028 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15029 same types as the MAC equivalents. The polynomial type for this instruction
15030 is encoded the same as the integer type. */
15035 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15038 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15041 if (inst
.operands
[2].isscalar
)
15042 do_neon_mac_maybe_scalar ();
15044 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15048 do_neon_qdmulh (void)
15050 if (inst
.operands
[2].isscalar
)
15052 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15053 struct neon_type_el et
= neon_check_type (3, rs
,
15054 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15055 NEON_ENCODE (SCALAR
, inst
);
15056 neon_mul_mac (et
, neon_quad (rs
));
15060 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15061 struct neon_type_el et
= neon_check_type (3, rs
,
15062 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15063 NEON_ENCODE (INTEGER
, inst
);
15064 /* The U bit (rounding) comes from bit mask. */
15065 neon_three_same (neon_quad (rs
), 0, et
.size
);
15070 do_neon_qrdmlah (void)
15072 /* Check we're on the correct architecture. */
15073 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15075 _("instruction form not available on this architecture.");
15076 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15078 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15079 record_feature_use (&fpu_neon_ext_v8_1
);
15082 if (inst
.operands
[2].isscalar
)
15084 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15085 struct neon_type_el et
= neon_check_type (3, rs
,
15086 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15087 NEON_ENCODE (SCALAR
, inst
);
15088 neon_mul_mac (et
, neon_quad (rs
));
15092 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15093 struct neon_type_el et
= neon_check_type (3, rs
,
15094 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15095 NEON_ENCODE (INTEGER
, inst
);
15096 /* The U bit (rounding) comes from bit mask. */
15097 neon_three_same (neon_quad (rs
), 0, et
.size
);
15102 do_neon_fcmp_absolute (void)
15104 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15105 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15106 N_F_16_32
| N_KEY
);
15107 /* Size field comes from bit mask. */
15108 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15112 do_neon_fcmp_absolute_inv (void)
15114 neon_exchange_operands ();
15115 do_neon_fcmp_absolute ();
15119 do_neon_step (void)
15121 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15122 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15123 N_F_16_32
| N_KEY
);
15124 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15128 do_neon_abs_neg (void)
15130 enum neon_shape rs
;
15131 struct neon_type_el et
;
15133 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15136 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15139 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15140 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15142 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15143 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15144 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15145 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15146 inst
.instruction
|= neon_quad (rs
) << 6;
15147 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15148 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15150 neon_dp_fixup (&inst
);
15156 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15157 struct neon_type_el et
= neon_check_type (2, rs
,
15158 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15159 int imm
= inst
.operands
[2].imm
;
15160 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15161 _("immediate out of range for insert"));
15162 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15168 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15169 struct neon_type_el et
= neon_check_type (2, rs
,
15170 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15171 int imm
= inst
.operands
[2].imm
;
15172 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15173 _("immediate out of range for insert"));
15174 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15178 do_neon_qshlu_imm (void)
15180 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15181 struct neon_type_el et
= neon_check_type (2, rs
,
15182 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15183 int imm
= inst
.operands
[2].imm
;
15184 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15185 _("immediate out of range for shift"));
15186 /* Only encodes the 'U present' variant of the instruction.
15187 In this case, signed types have OP (bit 8) set to 0.
15188 Unsigned types have OP set to 1. */
15189 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15190 /* The rest of the bits are the same as other immediate shifts. */
15191 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15195 do_neon_qmovn (void)
15197 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15198 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15199 /* Saturating move where operands can be signed or unsigned, and the
15200 destination has the same signedness. */
15201 NEON_ENCODE (INTEGER
, inst
);
15202 if (et
.type
== NT_unsigned
)
15203 inst
.instruction
|= 0xc0;
15205 inst
.instruction
|= 0x80;
15206 neon_two_same (0, 1, et
.size
/ 2);
15210 do_neon_qmovun (void)
15212 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15213 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15214 /* Saturating move with unsigned results. Operands must be signed. */
15215 NEON_ENCODE (INTEGER
, inst
);
15216 neon_two_same (0, 1, et
.size
/ 2);
15220 do_neon_rshift_sat_narrow (void)
15222 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15223 or unsigned. If operands are unsigned, results must also be unsigned. */
15224 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15225 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15226 int imm
= inst
.operands
[2].imm
;
15227 /* This gets the bounds check, size encoding and immediate bits calculation
15231 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15232 VQMOVN.I<size> <Dd>, <Qm>. */
15235 inst
.operands
[2].present
= 0;
15236 inst
.instruction
= N_MNEM_vqmovn
;
15241 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15242 _("immediate out of range"));
15243 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15247 do_neon_rshift_sat_narrow_u (void)
15249 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15250 or unsigned. If operands are unsigned, results must also be unsigned. */
15251 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15252 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15253 int imm
= inst
.operands
[2].imm
;
15254 /* This gets the bounds check, size encoding and immediate bits calculation
15258 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15259 VQMOVUN.I<size> <Dd>, <Qm>. */
15262 inst
.operands
[2].present
= 0;
15263 inst
.instruction
= N_MNEM_vqmovun
;
15268 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15269 _("immediate out of range"));
15270 /* FIXME: The manual is kind of unclear about what value U should have in
15271 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15273 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15277 do_neon_movn (void)
15279 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15280 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15281 NEON_ENCODE (INTEGER
, inst
);
15282 neon_two_same (0, 1, et
.size
/ 2);
15286 do_neon_rshift_narrow (void)
15288 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15289 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15290 int imm
= inst
.operands
[2].imm
;
15291 /* This gets the bounds check, size encoding and immediate bits calculation
15295 /* If immediate is zero then we are a pseudo-instruction for
15296 VMOVN.I<size> <Dd>, <Qm> */
15299 inst
.operands
[2].present
= 0;
15300 inst
.instruction
= N_MNEM_vmovn
;
15305 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15306 _("immediate out of range for narrowing operation"));
15307 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15311 do_neon_shll (void)
15313 /* FIXME: Type checking when lengthening. */
15314 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15315 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15316 unsigned imm
= inst
.operands
[2].imm
;
15318 if (imm
== et
.size
)
15320 /* Maximum shift variant. */
15321 NEON_ENCODE (INTEGER
, inst
);
15322 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15323 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15324 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15325 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15326 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15328 neon_dp_fixup (&inst
);
15332 /* A more-specific type check for non-max versions. */
15333 et
= neon_check_type (2, NS_QDI
,
15334 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15335 NEON_ENCODE (IMMED
, inst
);
15336 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15340 /* Check the various types for the VCVT instruction, and return which version
15341 the current instruction is. */
15343 #define CVT_FLAVOUR_VAR \
15344 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15345 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15346 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15347 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15348 /* Half-precision conversions. */ \
15349 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15350 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15351 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15352 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15353 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15354 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15355 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15356 Compared with single/double precision variants, only the co-processor \
15357 field is different, so the encoding flow is reused here. */ \
15358 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15359 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15360 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15361 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15362 /* VFP instructions. */ \
15363 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15364 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15365 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15366 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15367 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15368 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15369 /* VFP instructions with bitshift. */ \
15370 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15371 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15372 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15373 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15374 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15375 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15376 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15377 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15379 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15380 neon_cvt_flavour_##C,
15382 /* The different types of conversions we can do. */
15383 enum neon_cvt_flavour
15386 neon_cvt_flavour_invalid
,
15387 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15392 static enum neon_cvt_flavour
15393 get_neon_cvt_flavour (enum neon_shape rs
)
15395 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15396 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15397 if (et.type != NT_invtype) \
15399 inst.error = NULL; \
15400 return (neon_cvt_flavour_##C); \
15403 struct neon_type_el et
;
15404 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15405 || rs
== NS_FF
) ? N_VFP
: 0;
15406 /* The instruction versions which take an immediate take one register
15407 argument, which is extended to the width of the full register. Thus the
15408 "source" and "destination" registers must have the same width. Hack that
15409 here by making the size equal to the key (wider, in this case) operand. */
15410 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15414 return neon_cvt_flavour_invalid
;
15429 /* Neon-syntax VFP conversions. */
15432 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15434 const char *opname
= 0;
15436 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15437 || rs
== NS_FHI
|| rs
== NS_HFI
)
15439 /* Conversions with immediate bitshift. */
15440 const char *enc
[] =
15442 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15448 if (flavour
< (int) ARRAY_SIZE (enc
))
15450 opname
= enc
[flavour
];
15451 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15452 _("operands 0 and 1 must be the same register"));
15453 inst
.operands
[1] = inst
.operands
[2];
15454 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15459 /* Conversions without bitshift. */
15460 const char *enc
[] =
15462 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15468 if (flavour
< (int) ARRAY_SIZE (enc
))
15469 opname
= enc
[flavour
];
15473 do_vfp_nsyn_opcode (opname
);
15475 /* ARMv8.2 fp16 VCVT instruction. */
15476 if (flavour
== neon_cvt_flavour_s32_f16
15477 || flavour
== neon_cvt_flavour_u32_f16
15478 || flavour
== neon_cvt_flavour_f16_u32
15479 || flavour
== neon_cvt_flavour_f16_s32
)
15480 do_scalar_fp16_v82_encode ();
15484 do_vfp_nsyn_cvtz (void)
15486 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15487 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15488 const char *enc
[] =
15490 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15496 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15497 do_vfp_nsyn_opcode (enc
[flavour
]);
15501 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15502 enum neon_cvt_mode mode
)
15507 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15508 D register operands. */
15509 if (flavour
== neon_cvt_flavour_s32_f64
15510 || flavour
== neon_cvt_flavour_u32_f64
)
15511 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15514 if (flavour
== neon_cvt_flavour_s32_f16
15515 || flavour
== neon_cvt_flavour_u32_f16
)
15516 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15519 set_it_insn_type (OUTSIDE_IT_INSN
);
15523 case neon_cvt_flavour_s32_f64
:
15527 case neon_cvt_flavour_s32_f32
:
15531 case neon_cvt_flavour_s32_f16
:
15535 case neon_cvt_flavour_u32_f64
:
15539 case neon_cvt_flavour_u32_f32
:
15543 case neon_cvt_flavour_u32_f16
:
15548 first_error (_("invalid instruction shape"));
15554 case neon_cvt_mode_a
: rm
= 0; break;
15555 case neon_cvt_mode_n
: rm
= 1; break;
15556 case neon_cvt_mode_p
: rm
= 2; break;
15557 case neon_cvt_mode_m
: rm
= 3; break;
15558 default: first_error (_("invalid rounding mode")); return;
15561 NEON_ENCODE (FPV8
, inst
);
15562 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15563 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15564 inst
.instruction
|= sz
<< 8;
15566 /* ARMv8.2 fp16 VCVT instruction. */
15567 if (flavour
== neon_cvt_flavour_s32_f16
15568 ||flavour
== neon_cvt_flavour_u32_f16
)
15569 do_scalar_fp16_v82_encode ();
15570 inst
.instruction
|= op
<< 7;
15571 inst
.instruction
|= rm
<< 16;
15572 inst
.instruction
|= 0xf0000000;
15573 inst
.is_neon
= TRUE
;
15577 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15579 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15580 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15581 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15583 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15585 if (flavour
== neon_cvt_flavour_invalid
)
15588 /* PR11109: Handle round-to-zero for VCVT conversions. */
15589 if (mode
== neon_cvt_mode_z
15590 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15591 && (flavour
== neon_cvt_flavour_s16_f16
15592 || flavour
== neon_cvt_flavour_u16_f16
15593 || flavour
== neon_cvt_flavour_s32_f32
15594 || flavour
== neon_cvt_flavour_u32_f32
15595 || flavour
== neon_cvt_flavour_s32_f64
15596 || flavour
== neon_cvt_flavour_u32_f64
)
15597 && (rs
== NS_FD
|| rs
== NS_FF
))
15599 do_vfp_nsyn_cvtz ();
15603 /* ARMv8.2 fp16 VCVT conversions. */
15604 if (mode
== neon_cvt_mode_z
15605 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15606 && (flavour
== neon_cvt_flavour_s32_f16
15607 || flavour
== neon_cvt_flavour_u32_f16
)
15610 do_vfp_nsyn_cvtz ();
15611 do_scalar_fp16_v82_encode ();
15615 /* VFP rather than Neon conversions. */
15616 if (flavour
>= neon_cvt_flavour_first_fp
)
15618 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15619 do_vfp_nsyn_cvt (rs
, flavour
);
15621 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15632 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15633 0x0000100, 0x1000100, 0x0, 0x1000000};
15635 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15638 /* Fixed-point conversion with #0 immediate is encoded as an
15639 integer conversion. */
15640 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15642 NEON_ENCODE (IMMED
, inst
);
15643 if (flavour
!= neon_cvt_flavour_invalid
)
15644 inst
.instruction
|= enctab
[flavour
];
15645 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15646 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15647 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15648 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15649 inst
.instruction
|= neon_quad (rs
) << 6;
15650 inst
.instruction
|= 1 << 21;
15651 if (flavour
< neon_cvt_flavour_s16_f16
)
15653 inst
.instruction
|= 1 << 21;
15654 immbits
= 32 - inst
.operands
[2].imm
;
15655 inst
.instruction
|= immbits
<< 16;
15659 inst
.instruction
|= 3 << 20;
15660 immbits
= 16 - inst
.operands
[2].imm
;
15661 inst
.instruction
|= immbits
<< 16;
15662 inst
.instruction
&= ~(1 << 9);
15665 neon_dp_fixup (&inst
);
15671 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15673 NEON_ENCODE (FLOAT
, inst
);
15674 set_it_insn_type (OUTSIDE_IT_INSN
);
15676 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15679 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15680 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15681 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15682 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15683 inst
.instruction
|= neon_quad (rs
) << 6;
15684 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15685 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15686 inst
.instruction
|= mode
<< 8;
15687 if (flavour
== neon_cvt_flavour_u16_f16
15688 || flavour
== neon_cvt_flavour_s16_f16
)
15689 /* Mask off the original size bits and reencode them. */
15690 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15693 inst
.instruction
|= 0xfc000000;
15695 inst
.instruction
|= 0xf0000000;
15701 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15702 0x100, 0x180, 0x0, 0x080};
15704 NEON_ENCODE (INTEGER
, inst
);
15706 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15709 if (flavour
!= neon_cvt_flavour_invalid
)
15710 inst
.instruction
|= enctab
[flavour
];
15712 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15713 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15714 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15715 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15716 inst
.instruction
|= neon_quad (rs
) << 6;
15717 if (flavour
>= neon_cvt_flavour_s16_f16
15718 && flavour
<= neon_cvt_flavour_f16_u16
)
15719 /* Half precision. */
15720 inst
.instruction
|= 1 << 18;
15722 inst
.instruction
|= 2 << 18;
15724 neon_dp_fixup (&inst
);
15729 /* Half-precision conversions for Advanced SIMD -- neon. */
15734 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15736 as_bad (_("operand size must match register width"));
15741 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15743 as_bad (_("operand size must match register width"));
15748 inst
.instruction
= 0x3b60600;
15750 inst
.instruction
= 0x3b60700;
15752 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15753 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15754 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15755 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15756 neon_dp_fixup (&inst
);
15760 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15761 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15762 do_vfp_nsyn_cvt (rs
, flavour
);
15764 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15769 do_neon_cvtr (void)
15771 do_neon_cvt_1 (neon_cvt_mode_x
);
15777 do_neon_cvt_1 (neon_cvt_mode_z
);
15781 do_neon_cvta (void)
15783 do_neon_cvt_1 (neon_cvt_mode_a
);
15787 do_neon_cvtn (void)
15789 do_neon_cvt_1 (neon_cvt_mode_n
);
15793 do_neon_cvtp (void)
15795 do_neon_cvt_1 (neon_cvt_mode_p
);
15799 do_neon_cvtm (void)
15801 do_neon_cvt_1 (neon_cvt_mode_m
);
15805 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15808 mark_feature_used (&fpu_vfp_ext_armv8
);
15810 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15811 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15812 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15813 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15814 inst
.instruction
|= to
? 0x10000 : 0;
15815 inst
.instruction
|= t
? 0x80 : 0;
15816 inst
.instruction
|= is_double
? 0x100 : 0;
15817 do_vfp_cond_or_thumb ();
15821 do_neon_cvttb_1 (bfd_boolean t
)
15823 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
15824 NS_DF
, NS_DH
, NS_NULL
);
15828 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15831 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15833 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15836 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15838 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15840 /* The VCVTB and VCVTT instructions with D-register operands
15841 don't work for SP only targets. */
15842 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15846 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15848 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15850 /* The VCVTB and VCVTT instructions with D-register operands
15851 don't work for SP only targets. */
15852 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15856 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15863 do_neon_cvtb (void)
15865 do_neon_cvttb_1 (FALSE
);
15870 do_neon_cvtt (void)
15872 do_neon_cvttb_1 (TRUE
);
15876 neon_move_immediate (void)
15878 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15879 struct neon_type_el et
= neon_check_type (2, rs
,
15880 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15881 unsigned immlo
, immhi
= 0, immbits
;
15882 int op
, cmode
, float_p
;
15884 constraint (et
.type
== NT_invtype
,
15885 _("operand size must be specified for immediate VMOV"));
15887 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15888 op
= (inst
.instruction
& (1 << 5)) != 0;
15890 immlo
= inst
.operands
[1].imm
;
15891 if (inst
.operands
[1].regisimm
)
15892 immhi
= inst
.operands
[1].reg
;
15894 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15895 _("immediate has bits set outside the operand size"));
15897 float_p
= inst
.operands
[1].immisfloat
;
15899 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15900 et
.size
, et
.type
)) == FAIL
)
15902 /* Invert relevant bits only. */
15903 neon_invert_size (&immlo
, &immhi
, et
.size
);
15904 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15905 with one or the other; those cases are caught by
15906 neon_cmode_for_move_imm. */
15908 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15909 &op
, et
.size
, et
.type
)) == FAIL
)
15911 first_error (_("immediate out of range"));
15916 inst
.instruction
&= ~(1 << 5);
15917 inst
.instruction
|= op
<< 5;
15919 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15920 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15921 inst
.instruction
|= neon_quad (rs
) << 6;
15922 inst
.instruction
|= cmode
<< 8;
15924 neon_write_immbits (immbits
);
15930 if (inst
.operands
[1].isreg
)
15932 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15934 NEON_ENCODE (INTEGER
, inst
);
15935 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15936 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15937 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15938 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15939 inst
.instruction
|= neon_quad (rs
) << 6;
15943 NEON_ENCODE (IMMED
, inst
);
15944 neon_move_immediate ();
15947 neon_dp_fixup (&inst
);
15950 /* Encode instructions of form:
15952 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15953 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15956 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15958 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15959 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15960 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15961 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15962 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15963 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15964 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15965 inst
.instruction
|= neon_logbits (size
) << 20;
15967 neon_dp_fixup (&inst
);
15971 do_neon_dyadic_long (void)
15973 /* FIXME: Type checking for lengthening op. */
15974 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15975 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15976 neon_mixed_length (et
, et
.size
);
15980 do_neon_abal (void)
15982 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15983 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15984 neon_mixed_length (et
, et
.size
);
15988 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15990 if (inst
.operands
[2].isscalar
)
15992 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15993 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15994 NEON_ENCODE (SCALAR
, inst
);
15995 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15999 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16000 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16001 NEON_ENCODE (INTEGER
, inst
);
16002 neon_mixed_length (et
, et
.size
);
16007 do_neon_mac_maybe_scalar_long (void)
16009 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16013 do_neon_dyadic_wide (void)
16015 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16016 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16017 neon_mixed_length (et
, et
.size
);
16021 do_neon_dyadic_narrow (void)
16023 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16024 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16025 /* Operand sign is unimportant, and the U bit is part of the opcode,
16026 so force the operand type to integer. */
16027 et
.type
= NT_integer
;
16028 neon_mixed_length (et
, et
.size
/ 2);
16032 do_neon_mul_sat_scalar_long (void)
16034 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16038 do_neon_vmull (void)
16040 if (inst
.operands
[2].isscalar
)
16041 do_neon_mac_maybe_scalar_long ();
16044 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16045 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16047 if (et
.type
== NT_poly
)
16048 NEON_ENCODE (POLY
, inst
);
16050 NEON_ENCODE (INTEGER
, inst
);
16052 /* For polynomial encoding the U bit must be zero, and the size must
16053 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16054 obviously, as 0b10). */
16057 /* Check we're on the correct architecture. */
16058 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16060 _("Instruction form not available on this architecture.");
16065 neon_mixed_length (et
, et
.size
);
16072 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16073 struct neon_type_el et
= neon_check_type (3, rs
,
16074 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16075 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16077 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16078 _("shift out of range"));
16079 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16080 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16081 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16082 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16083 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16084 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16085 inst
.instruction
|= neon_quad (rs
) << 6;
16086 inst
.instruction
|= imm
<< 8;
16088 neon_dp_fixup (&inst
);
16094 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16095 struct neon_type_el et
= neon_check_type (2, rs
,
16096 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16097 unsigned op
= (inst
.instruction
>> 7) & 3;
16098 /* N (width of reversed regions) is encoded as part of the bitmask. We
16099 extract it here to check the elements to be reversed are smaller.
16100 Otherwise we'd get a reserved instruction. */
16101 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16102 gas_assert (elsize
!= 0);
16103 constraint (et
.size
>= elsize
,
16104 _("elements must be smaller than reversal region"));
16105 neon_two_same (neon_quad (rs
), 1, et
.size
);
16111 if (inst
.operands
[1].isscalar
)
16113 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16114 struct neon_type_el et
= neon_check_type (2, rs
,
16115 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16116 unsigned sizebits
= et
.size
>> 3;
16117 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16118 int logsize
= neon_logbits (et
.size
);
16119 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16121 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16124 NEON_ENCODE (SCALAR
, inst
);
16125 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16126 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16127 inst
.instruction
|= LOW4 (dm
);
16128 inst
.instruction
|= HI1 (dm
) << 5;
16129 inst
.instruction
|= neon_quad (rs
) << 6;
16130 inst
.instruction
|= x
<< 17;
16131 inst
.instruction
|= sizebits
<< 16;
16133 neon_dp_fixup (&inst
);
16137 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16138 struct neon_type_el et
= neon_check_type (2, rs
,
16139 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16140 /* Duplicate ARM register to lanes of vector. */
16141 NEON_ENCODE (ARMREG
, inst
);
16144 case 8: inst
.instruction
|= 0x400000; break;
16145 case 16: inst
.instruction
|= 0x000020; break;
16146 case 32: inst
.instruction
|= 0x000000; break;
16149 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16150 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16152 inst
.instruction
|= neon_quad (rs
) << 21;
16153 /* The encoding for this instruction is identical for the ARM and Thumb
16154 variants, except for the condition field. */
16155 do_vfp_cond_or_thumb ();
16159 /* VMOV has particularly many variations. It can be one of:
16160 0. VMOV<c><q> <Qd>, <Qm>
16161 1. VMOV<c><q> <Dd>, <Dm>
16162 (Register operations, which are VORR with Rm = Rn.)
16163 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16164 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16166 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16167 (ARM register to scalar.)
16168 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16169 (Two ARM registers to vector.)
16170 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16171 (Scalar to ARM register.)
16172 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16173 (Vector to two ARM registers.)
16174 8. VMOV.F32 <Sd>, <Sm>
16175 9. VMOV.F64 <Dd>, <Dm>
16176 (VFP register moves.)
16177 10. VMOV.F32 <Sd>, #imm
16178 11. VMOV.F64 <Dd>, #imm
16179 (VFP float immediate load.)
16180 12. VMOV <Rd>, <Sm>
16181 (VFP single to ARM reg.)
16182 13. VMOV <Sd>, <Rm>
16183 (ARM reg to VFP single.)
16184 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16185 (Two ARM regs to two VFP singles.)
16186 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16187 (Two VFP singles to two ARM regs.)
16189 These cases can be disambiguated using neon_select_shape, except cases 1/9
16190 and 3/11 which depend on the operand type too.
16192 All the encoded bits are hardcoded by this function.
16194 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16195 Cases 5, 7 may be used with VFPv2 and above.
16197 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16198 can specify a type where it doesn't make sense to, and is ignored). */
16203 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16204 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16205 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16206 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16207 struct neon_type_el et
;
16208 const char *ldconst
= 0;
16212 case NS_DD
: /* case 1/9. */
16213 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16214 /* It is not an error here if no type is given. */
16216 if (et
.type
== NT_float
&& et
.size
== 64)
16218 do_vfp_nsyn_opcode ("fcpyd");
16221 /* fall through. */
16223 case NS_QQ
: /* case 0/1. */
16225 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16227 /* The architecture manual I have doesn't explicitly state which
16228 value the U bit should have for register->register moves, but
16229 the equivalent VORR instruction has U = 0, so do that. */
16230 inst
.instruction
= 0x0200110;
16231 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16232 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16233 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16234 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16235 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16236 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16237 inst
.instruction
|= neon_quad (rs
) << 6;
16239 neon_dp_fixup (&inst
);
16243 case NS_DI
: /* case 3/11. */
16244 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16246 if (et
.type
== NT_float
&& et
.size
== 64)
16248 /* case 11 (fconstd). */
16249 ldconst
= "fconstd";
16250 goto encode_fconstd
;
16252 /* fall through. */
16254 case NS_QI
: /* case 2/3. */
16255 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16257 inst
.instruction
= 0x0800010;
16258 neon_move_immediate ();
16259 neon_dp_fixup (&inst
);
16262 case NS_SR
: /* case 4. */
16264 unsigned bcdebits
= 0;
16266 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16267 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16269 /* .<size> is optional here, defaulting to .32. */
16270 if (inst
.vectype
.elems
== 0
16271 && inst
.operands
[0].vectype
.type
== NT_invtype
16272 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16274 inst
.vectype
.el
[0].type
= NT_untyped
;
16275 inst
.vectype
.el
[0].size
= 32;
16276 inst
.vectype
.elems
= 1;
16279 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16280 logsize
= neon_logbits (et
.size
);
16282 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16284 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16285 && et
.size
!= 32, _(BAD_FPU
));
16286 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16287 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16291 case 8: bcdebits
= 0x8; break;
16292 case 16: bcdebits
= 0x1; break;
16293 case 32: bcdebits
= 0x0; break;
16297 bcdebits
|= x
<< logsize
;
16299 inst
.instruction
= 0xe000b10;
16300 do_vfp_cond_or_thumb ();
16301 inst
.instruction
|= LOW4 (dn
) << 16;
16302 inst
.instruction
|= HI1 (dn
) << 7;
16303 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16304 inst
.instruction
|= (bcdebits
& 3) << 5;
16305 inst
.instruction
|= (bcdebits
>> 2) << 21;
16309 case NS_DRR
: /* case 5 (fmdrr). */
16310 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16313 inst
.instruction
= 0xc400b10;
16314 do_vfp_cond_or_thumb ();
16315 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16316 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16317 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16318 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16321 case NS_RS
: /* case 6. */
16324 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16325 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16326 unsigned abcdebits
= 0;
16328 /* .<dt> is optional here, defaulting to .32. */
16329 if (inst
.vectype
.elems
== 0
16330 && inst
.operands
[0].vectype
.type
== NT_invtype
16331 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16333 inst
.vectype
.el
[0].type
= NT_untyped
;
16334 inst
.vectype
.el
[0].size
= 32;
16335 inst
.vectype
.elems
= 1;
16338 et
= neon_check_type (2, NS_NULL
,
16339 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16340 logsize
= neon_logbits (et
.size
);
16342 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16344 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16345 && et
.size
!= 32, _(BAD_FPU
));
16346 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16347 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16351 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16352 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16353 case 32: abcdebits
= 0x00; break;
16357 abcdebits
|= x
<< logsize
;
16358 inst
.instruction
= 0xe100b10;
16359 do_vfp_cond_or_thumb ();
16360 inst
.instruction
|= LOW4 (dn
) << 16;
16361 inst
.instruction
|= HI1 (dn
) << 7;
16362 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16363 inst
.instruction
|= (abcdebits
& 3) << 5;
16364 inst
.instruction
|= (abcdebits
>> 2) << 21;
16368 case NS_RRD
: /* case 7 (fmrrd). */
16369 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16372 inst
.instruction
= 0xc500b10;
16373 do_vfp_cond_or_thumb ();
16374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16375 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16376 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16377 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16380 case NS_FF
: /* case 8 (fcpys). */
16381 do_vfp_nsyn_opcode ("fcpys");
16385 case NS_FI
: /* case 10 (fconsts). */
16386 ldconst
= "fconsts";
16388 if (is_quarter_float (inst
.operands
[1].imm
))
16390 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16391 do_vfp_nsyn_opcode (ldconst
);
16393 /* ARMv8.2 fp16 vmov.f16 instruction. */
16395 do_scalar_fp16_v82_encode ();
16398 first_error (_("immediate out of range"));
16402 case NS_RF
: /* case 12 (fmrs). */
16403 do_vfp_nsyn_opcode ("fmrs");
16404 /* ARMv8.2 fp16 vmov.f16 instruction. */
16406 do_scalar_fp16_v82_encode ();
16410 case NS_FR
: /* case 13 (fmsr). */
16411 do_vfp_nsyn_opcode ("fmsr");
16412 /* ARMv8.2 fp16 vmov.f16 instruction. */
16414 do_scalar_fp16_v82_encode ();
16417 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16418 (one of which is a list), but we have parsed four. Do some fiddling to
16419 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16421 case NS_RRFF
: /* case 14 (fmrrs). */
16422 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16423 _("VFP registers must be adjacent"));
16424 inst
.operands
[2].imm
= 2;
16425 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16426 do_vfp_nsyn_opcode ("fmrrs");
16429 case NS_FFRR
: /* case 15 (fmsrr). */
16430 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16431 _("VFP registers must be adjacent"));
16432 inst
.operands
[1] = inst
.operands
[2];
16433 inst
.operands
[2] = inst
.operands
[3];
16434 inst
.operands
[0].imm
= 2;
16435 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16436 do_vfp_nsyn_opcode ("fmsrr");
16440 /* neon_select_shape has determined that the instruction
16441 shape is wrong and has already set the error message. */
16450 do_neon_rshift_round_imm (void)
16452 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16453 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16454 int imm
= inst
.operands
[2].imm
;
16456 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16459 inst
.operands
[2].present
= 0;
16464 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16465 _("immediate out of range for shift"));
16466 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16471 do_neon_movhf (void)
16473 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16474 constraint (rs
!= NS_HH
, _("invalid suffix"));
16476 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16479 do_vfp_sp_monadic ();
16482 inst
.instruction
|= 0xf0000000;
16486 do_neon_movl (void)
16488 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16489 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16490 unsigned sizebits
= et
.size
>> 3;
16491 inst
.instruction
|= sizebits
<< 19;
16492 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16498 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16499 struct neon_type_el et
= neon_check_type (2, rs
,
16500 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16501 NEON_ENCODE (INTEGER
, inst
);
16502 neon_two_same (neon_quad (rs
), 1, et
.size
);
16506 do_neon_zip_uzp (void)
16508 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16509 struct neon_type_el et
= neon_check_type (2, rs
,
16510 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16511 if (rs
== NS_DD
&& et
.size
== 32)
16513 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16514 inst
.instruction
= N_MNEM_vtrn
;
16518 neon_two_same (neon_quad (rs
), 1, et
.size
);
16522 do_neon_sat_abs_neg (void)
16524 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16525 struct neon_type_el et
= neon_check_type (2, rs
,
16526 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16527 neon_two_same (neon_quad (rs
), 1, et
.size
);
16531 do_neon_pair_long (void)
16533 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16534 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16535 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16536 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16537 neon_two_same (neon_quad (rs
), 1, et
.size
);
16541 do_neon_recip_est (void)
16543 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16544 struct neon_type_el et
= neon_check_type (2, rs
,
16545 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16546 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16547 neon_two_same (neon_quad (rs
), 1, et
.size
);
16553 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16554 struct neon_type_el et
= neon_check_type (2, rs
,
16555 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16556 neon_two_same (neon_quad (rs
), 1, et
.size
);
16562 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16563 struct neon_type_el et
= neon_check_type (2, rs
,
16564 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16565 neon_two_same (neon_quad (rs
), 1, et
.size
);
16571 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16572 struct neon_type_el et
= neon_check_type (2, rs
,
16573 N_EQK
| N_INT
, N_8
| N_KEY
);
16574 neon_two_same (neon_quad (rs
), 1, et
.size
);
16580 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16581 neon_two_same (neon_quad (rs
), 1, -1);
16585 do_neon_tbl_tbx (void)
16587 unsigned listlenbits
;
16588 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16590 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16592 first_error (_("bad list length for table lookup"));
16596 listlenbits
= inst
.operands
[1].imm
- 1;
16597 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16598 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16599 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16600 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16601 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16602 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16603 inst
.instruction
|= listlenbits
<< 8;
16605 neon_dp_fixup (&inst
);
16609 do_neon_ldm_stm (void)
16611 /* P, U and L bits are part of bitmask. */
16612 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16613 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16615 if (inst
.operands
[1].issingle
)
16617 do_vfp_nsyn_ldm_stm (is_dbmode
);
16621 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16622 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16624 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16625 _("register list must contain at least 1 and at most 16 "
16628 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16629 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16630 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16631 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16633 inst
.instruction
|= offsetbits
;
16635 do_vfp_cond_or_thumb ();
16639 do_neon_ldr_str (void)
16641 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16643 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16644 And is UNPREDICTABLE in thumb mode. */
16646 && inst
.operands
[1].reg
== REG_PC
16647 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16650 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16651 else if (warn_on_deprecated
)
16652 as_tsktsk (_("Use of PC here is deprecated"));
16655 if (inst
.operands
[0].issingle
)
16658 do_vfp_nsyn_opcode ("flds");
16660 do_vfp_nsyn_opcode ("fsts");
16662 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16663 if (inst
.vectype
.el
[0].size
== 16)
16664 do_scalar_fp16_v82_encode ();
16669 do_vfp_nsyn_opcode ("fldd");
16671 do_vfp_nsyn_opcode ("fstd");
16675 /* "interleave" version also handles non-interleaving register VLD1/VST1
16679 do_neon_ld_st_interleave (void)
16681 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
16682 N_8
| N_16
| N_32
| N_64
);
16683 unsigned alignbits
= 0;
16685 /* The bits in this table go:
16686 0: register stride of one (0) or two (1)
16687 1,2: register list length, minus one (1, 2, 3, 4).
16688 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
16689 We use -1 for invalid entries. */
16690 const int typetable
[] =
16692 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
16693 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
16694 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
16695 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
16699 if (et
.type
== NT_invtype
)
16702 if (inst
.operands
[1].immisalign
)
16703 switch (inst
.operands
[1].imm
>> 8)
16705 case 64: alignbits
= 1; break;
16707 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
16708 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16709 goto bad_alignment
;
16713 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
16714 goto bad_alignment
;
16719 first_error (_("bad alignment"));
16723 inst
.instruction
|= alignbits
<< 4;
16724 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16726 /* Bits [4:6] of the immediate in a list specifier encode register stride
16727 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
16728 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
16729 up the right value for "type" in a table based on this value and the given
16730 list style, then stick it back. */
16731 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
16732 | (((inst
.instruction
>> 8) & 3) << 3);
16734 typebits
= typetable
[idx
];
16736 constraint (typebits
== -1, _("bad list type for instruction"));
16737 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
16738 _("bad element type for instruction"));
16740 inst
.instruction
&= ~0xf00;
16741 inst
.instruction
|= typebits
<< 8;
16744 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
16745 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
16746 otherwise. The variable arguments are a list of pairs of legal (size, align)
16747 values, terminated with -1. */
16750 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
16753 int result
= FAIL
, thissize
, thisalign
;
16755 if (!inst
.operands
[1].immisalign
)
16761 va_start (ap
, do_alignment
);
16765 thissize
= va_arg (ap
, int);
16766 if (thissize
== -1)
16768 thisalign
= va_arg (ap
, int);
16770 if (size
== thissize
&& align
== thisalign
)
16773 while (result
!= SUCCESS
);
16777 if (result
== SUCCESS
)
16780 first_error (_("unsupported alignment for instruction"));
16786 do_neon_ld_st_lane (void)
16788 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16789 int align_good
, do_alignment
= 0;
16790 int logsize
= neon_logbits (et
.size
);
16791 int align
= inst
.operands
[1].imm
>> 8;
16792 int n
= (inst
.instruction
>> 8) & 3;
16793 int max_el
= 64 / et
.size
;
16795 if (et
.type
== NT_invtype
)
16798 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16799 _("bad list length"));
16800 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16801 _("scalar index out of range"));
16802 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16804 _("stride of 2 unavailable when element size is 8"));
16808 case 0: /* VLD1 / VST1. */
16809 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
16811 if (align_good
== FAIL
)
16815 unsigned alignbits
= 0;
16818 case 16: alignbits
= 0x1; break;
16819 case 32: alignbits
= 0x3; break;
16822 inst
.instruction
|= alignbits
<< 4;
16826 case 1: /* VLD2 / VST2. */
16827 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
16828 16, 32, 32, 64, -1);
16829 if (align_good
== FAIL
)
16832 inst
.instruction
|= 1 << 4;
16835 case 2: /* VLD3 / VST3. */
16836 constraint (inst
.operands
[1].immisalign
,
16837 _("can't use alignment with this instruction"));
16840 case 3: /* VLD4 / VST4. */
16841 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16842 16, 64, 32, 64, 32, 128, -1);
16843 if (align_good
== FAIL
)
16847 unsigned alignbits
= 0;
16850 case 8: alignbits
= 0x1; break;
16851 case 16: alignbits
= 0x1; break;
16852 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16855 inst
.instruction
|= alignbits
<< 4;
16862 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16863 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16864 inst
.instruction
|= 1 << (4 + logsize
);
16866 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16867 inst
.instruction
|= logsize
<< 10;
16870 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16873 do_neon_ld_dup (void)
16875 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16876 int align_good
, do_alignment
= 0;
16878 if (et
.type
== NT_invtype
)
16881 switch ((inst
.instruction
>> 8) & 3)
16883 case 0: /* VLD1. */
16884 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16885 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16886 &do_alignment
, 16, 16, 32, 32, -1);
16887 if (align_good
== FAIL
)
16889 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16892 case 2: inst
.instruction
|= 1 << 5; break;
16893 default: first_error (_("bad list length")); return;
16895 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16898 case 1: /* VLD2. */
16899 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16900 &do_alignment
, 8, 16, 16, 32, 32, 64,
16902 if (align_good
== FAIL
)
16904 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16905 _("bad list length"));
16906 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16907 inst
.instruction
|= 1 << 5;
16908 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16911 case 2: /* VLD3. */
16912 constraint (inst
.operands
[1].immisalign
,
16913 _("can't use alignment with this instruction"));
16914 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16915 _("bad list length"));
16916 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16917 inst
.instruction
|= 1 << 5;
16918 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16921 case 3: /* VLD4. */
16923 int align
= inst
.operands
[1].imm
>> 8;
16924 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
16925 16, 64, 32, 64, 32, 128, -1);
16926 if (align_good
== FAIL
)
16928 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16929 _("bad list length"));
16930 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16931 inst
.instruction
|= 1 << 5;
16932 if (et
.size
== 32 && align
== 128)
16933 inst
.instruction
|= 0x3 << 6;
16935 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16942 inst
.instruction
|= do_alignment
<< 4;
16945 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16946 apart from bits [11:4]. */
16949 do_neon_ldx_stx (void)
16951 if (inst
.operands
[1].isreg
)
16952 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16954 switch (NEON_LANE (inst
.operands
[0].imm
))
16956 case NEON_INTERLEAVE_LANES
:
16957 NEON_ENCODE (INTERLV
, inst
);
16958 do_neon_ld_st_interleave ();
16961 case NEON_ALL_LANES
:
16962 NEON_ENCODE (DUP
, inst
);
16963 if (inst
.instruction
== N_INV
)
16965 first_error ("only loads support such operands");
16972 NEON_ENCODE (LANE
, inst
);
16973 do_neon_ld_st_lane ();
16976 /* L bit comes from bit mask. */
16977 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16978 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16979 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16981 if (inst
.operands
[1].postind
)
16983 int postreg
= inst
.operands
[1].imm
& 0xf;
16984 constraint (!inst
.operands
[1].immisreg
,
16985 _("post-index must be a register"));
16986 constraint (postreg
== 0xd || postreg
== 0xf,
16987 _("bad register for post-index"));
16988 inst
.instruction
|= postreg
;
16992 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16993 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16994 || inst
.reloc
.exp
.X_add_number
!= 0,
16997 if (inst
.operands
[1].writeback
)
16999 inst
.instruction
|= 0xd;
17002 inst
.instruction
|= 0xf;
17006 inst
.instruction
|= 0xf9000000;
17008 inst
.instruction
|= 0xf4000000;
17013 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17015 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17016 D register operands. */
17017 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17018 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17021 NEON_ENCODE (FPV8
, inst
);
17023 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17025 do_vfp_sp_dyadic ();
17027 /* ARMv8.2 fp16 instruction. */
17029 do_scalar_fp16_v82_encode ();
17032 do_vfp_dp_rd_rn_rm ();
17035 inst
.instruction
|= 0x100;
17037 inst
.instruction
|= 0xf0000000;
17043 set_it_insn_type (OUTSIDE_IT_INSN
);
17045 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17046 first_error (_("invalid instruction shape"));
17052 set_it_insn_type (OUTSIDE_IT_INSN
);
17054 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17057 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17060 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17064 do_vrint_1 (enum neon_cvt_mode mode
)
17066 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17067 struct neon_type_el et
;
17072 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17073 D register operands. */
17074 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17075 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17078 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17080 if (et
.type
!= NT_invtype
)
17082 /* VFP encodings. */
17083 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17084 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17085 set_it_insn_type (OUTSIDE_IT_INSN
);
17087 NEON_ENCODE (FPV8
, inst
);
17088 if (rs
== NS_FF
|| rs
== NS_HH
)
17089 do_vfp_sp_monadic ();
17091 do_vfp_dp_rd_rm ();
17095 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17096 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17097 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17098 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17099 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17100 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17101 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17105 inst
.instruction
|= (rs
== NS_DD
) << 8;
17106 do_vfp_cond_or_thumb ();
17108 /* ARMv8.2 fp16 vrint instruction. */
17110 do_scalar_fp16_v82_encode ();
17114 /* Neon encodings (or something broken...). */
17116 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17118 if (et
.type
== NT_invtype
)
17121 set_it_insn_type (OUTSIDE_IT_INSN
);
17122 NEON_ENCODE (FLOAT
, inst
);
17124 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17127 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17128 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17129 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17130 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17131 inst
.instruction
|= neon_quad (rs
) << 6;
17132 /* Mask off the original size bits and reencode them. */
17133 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17134 | neon_logbits (et
.size
) << 18);
17138 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17139 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17140 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17141 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17142 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17143 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17144 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17149 inst
.instruction
|= 0xfc000000;
17151 inst
.instruction
|= 0xf0000000;
17158 do_vrint_1 (neon_cvt_mode_x
);
17164 do_vrint_1 (neon_cvt_mode_z
);
17170 do_vrint_1 (neon_cvt_mode_r
);
17176 do_vrint_1 (neon_cvt_mode_a
);
17182 do_vrint_1 (neon_cvt_mode_n
);
17188 do_vrint_1 (neon_cvt_mode_p
);
17194 do_vrint_1 (neon_cvt_mode_m
);
17197 /* Crypto v1 instructions. */
17199 do_crypto_2op_1 (unsigned elttype
, int op
)
17201 set_it_insn_type (OUTSIDE_IT_INSN
);
17203 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17209 NEON_ENCODE (INTEGER
, inst
);
17210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17212 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17213 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17215 inst
.instruction
|= op
<< 6;
17218 inst
.instruction
|= 0xfc000000;
17220 inst
.instruction
|= 0xf0000000;
17224 do_crypto_3op_1 (int u
, int op
)
17226 set_it_insn_type (OUTSIDE_IT_INSN
);
17228 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17229 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17234 NEON_ENCODE (INTEGER
, inst
);
17235 neon_three_same (1, u
, 8 << op
);
17241 do_crypto_2op_1 (N_8
, 0);
17247 do_crypto_2op_1 (N_8
, 1);
17253 do_crypto_2op_1 (N_8
, 2);
17259 do_crypto_2op_1 (N_8
, 3);
17265 do_crypto_3op_1 (0, 0);
17271 do_crypto_3op_1 (0, 1);
17277 do_crypto_3op_1 (0, 2);
17283 do_crypto_3op_1 (0, 3);
17289 do_crypto_3op_1 (1, 0);
17295 do_crypto_3op_1 (1, 1);
17299 do_sha256su1 (void)
17301 do_crypto_3op_1 (1, 2);
17307 do_crypto_2op_1 (N_32
, -1);
17313 do_crypto_2op_1 (N_32
, 0);
17317 do_sha256su0 (void)
17319 do_crypto_2op_1 (N_32
, 1);
17323 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17325 unsigned int Rd
= inst
.operands
[0].reg
;
17326 unsigned int Rn
= inst
.operands
[1].reg
;
17327 unsigned int Rm
= inst
.operands
[2].reg
;
17329 set_it_insn_type (OUTSIDE_IT_INSN
);
17330 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17331 inst
.instruction
|= LOW4 (Rn
) << 16;
17332 inst
.instruction
|= LOW4 (Rm
);
17333 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17334 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17336 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17337 as_warn (UNPRED_REG ("r15"));
17338 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
17339 as_warn (UNPRED_REG ("r13"));
17379 /* Overall per-instruction processing. */
17381 /* We need to be able to fix up arbitrary expressions in some statements.
17382 This is so that we can handle symbols that are an arbitrary distance from
17383 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17384 which returns part of an address in a form which will be valid for
17385 a data instruction. We do this by pushing the expression into a symbol
17386 in the expr_section, and creating a fix for that. */
17389 fix_new_arm (fragS
* frag
,
17403 /* Create an absolute valued symbol, so we have something to
17404 refer to in the object file. Unfortunately for us, gas's
17405 generic expression parsing will already have folded out
17406 any use of .set foo/.type foo %function that may have
17407 been used to set type information of the target location,
17408 that's being specified symbolically. We have to presume
17409 the user knows what they are doing. */
17413 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17415 symbol
= symbol_find_or_make (name
);
17416 S_SET_SEGMENT (symbol
, absolute_section
);
17417 symbol_set_frag (symbol
, &zero_address_frag
);
17418 S_SET_VALUE (symbol
, exp
->X_add_number
);
17419 exp
->X_op
= O_symbol
;
17420 exp
->X_add_symbol
= symbol
;
17421 exp
->X_add_number
= 0;
17427 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17428 (enum bfd_reloc_code_real
) reloc
);
17432 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17433 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17437 /* Mark whether the fix is to a THUMB instruction, or an ARM
17439 new_fix
->tc_fix_data
= thumb_mode
;
17442 /* Create a frg for an instruction requiring relaxation. */
17444 output_relax_insn (void)
17450 /* The size of the instruction is unknown, so tie the debug info to the
17451 start of the instruction. */
17452 dwarf2_emit_insn (0);
17454 switch (inst
.reloc
.exp
.X_op
)
17457 sym
= inst
.reloc
.exp
.X_add_symbol
;
17458 offset
= inst
.reloc
.exp
.X_add_number
;
17462 offset
= inst
.reloc
.exp
.X_add_number
;
17465 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17469 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17470 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17471 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17474 /* Write a 32-bit thumb instruction to buf. */
17476 put_thumb32_insn (char * buf
, unsigned long insn
)
17478 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17479 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17483 output_inst (const char * str
)
17489 as_bad ("%s -- `%s'", inst
.error
, str
);
17494 output_relax_insn ();
17497 if (inst
.size
== 0)
17500 to
= frag_more (inst
.size
);
17501 /* PR 9814: Record the thumb mode into the current frag so that we know
17502 what type of NOP padding to use, if necessary. We override any previous
17503 setting so that if the mode has changed then the NOPS that we use will
17504 match the encoding of the last instruction in the frag. */
17505 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17507 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17509 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17510 put_thumb32_insn (to
, inst
.instruction
);
17512 else if (inst
.size
> INSN_SIZE
)
17514 gas_assert (inst
.size
== (2 * INSN_SIZE
));
17515 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
17516 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
17519 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
17521 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
17522 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
17523 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
17526 dwarf2_emit_insn (inst
.size
);
17530 output_it_inst (int cond
, int mask
, char * to
)
17532 unsigned long instruction
= 0xbf00;
17535 instruction
|= mask
;
17536 instruction
|= cond
<< 4;
17540 to
= frag_more (2);
17542 dwarf2_emit_insn (2);
17546 md_number_to_chars (to
, instruction
, 2);
17551 /* Tag values used in struct asm_opcode's tag field. */
17554 OT_unconditional
, /* Instruction cannot be conditionalized.
17555 The ARM condition field is still 0xE. */
17556 OT_unconditionalF
, /* Instruction cannot be conditionalized
17557 and carries 0xF in its ARM condition field. */
17558 OT_csuffix
, /* Instruction takes a conditional suffix. */
17559 OT_csuffixF
, /* Some forms of the instruction take a conditional
17560 suffix, others place 0xF where the condition field
17562 OT_cinfix3
, /* Instruction takes a conditional infix,
17563 beginning at character index 3. (In
17564 unified mode, it becomes a suffix.) */
17565 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
17566 tsts, cmps, cmns, and teqs. */
17567 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
17568 character index 3, even in unified mode. Used for
17569 legacy instructions where suffix and infix forms
17570 may be ambiguous. */
17571 OT_csuf_or_in3
, /* Instruction takes either a conditional
17572 suffix or an infix at character index 3. */
17573 OT_odd_infix_unc
, /* This is the unconditional variant of an
17574 instruction that takes a conditional infix
17575 at an unusual position. In unified mode,
17576 this variant will accept a suffix. */
17577 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
17578 are the conditional variants of instructions that
17579 take conditional infixes in unusual positions.
17580 The infix appears at character index
17581 (tag - OT_odd_infix_0). These are not accepted
17582 in unified mode. */
17585 /* Subroutine of md_assemble, responsible for looking up the primary
17586 opcode from the mnemonic the user wrote. STR points to the
17587 beginning of the mnemonic.
17589 This is not simply a hash table lookup, because of conditional
17590 variants. Most instructions have conditional variants, which are
17591 expressed with a _conditional affix_ to the mnemonic. If we were
17592 to encode each conditional variant as a literal string in the opcode
17593 table, it would have approximately 20,000 entries.
17595 Most mnemonics take this affix as a suffix, and in unified syntax,
17596 'most' is upgraded to 'all'. However, in the divided syntax, some
17597 instructions take the affix as an infix, notably the s-variants of
17598 the arithmetic instructions. Of those instructions, all but six
17599 have the infix appear after the third character of the mnemonic.
17601 Accordingly, the algorithm for looking up primary opcodes given
17604 1. Look up the identifier in the opcode table.
17605 If we find a match, go to step U.
17607 2. Look up the last two characters of the identifier in the
17608 conditions table. If we find a match, look up the first N-2
17609 characters of the identifier in the opcode table. If we
17610 find a match, go to step CE.
17612 3. Look up the fourth and fifth characters of the identifier in
17613 the conditions table. If we find a match, extract those
17614 characters from the identifier, and look up the remaining
17615 characters in the opcode table. If we find a match, go
17620 U. Examine the tag field of the opcode structure, in case this is
17621 one of the six instructions with its conditional infix in an
17622 unusual place. If it is, the tag tells us where to find the
17623 infix; look it up in the conditions table and set inst.cond
17624 accordingly. Otherwise, this is an unconditional instruction.
17625 Again set inst.cond accordingly. Return the opcode structure.
17627 CE. Examine the tag field to make sure this is an instruction that
17628 should receive a conditional suffix. If it is not, fail.
17629 Otherwise, set inst.cond from the suffix we already looked up,
17630 and return the opcode structure.
17632 CM. Examine the tag field to make sure this is an instruction that
17633 should receive a conditional infix after the third character.
17634 If it is not, fail. Otherwise, undo the edits to the current
17635 line of input and proceed as for case CE. */
17637 static const struct asm_opcode
*
17638 opcode_lookup (char **str
)
17642 const struct asm_opcode
*opcode
;
17643 const struct asm_cond
*cond
;
17646 /* Scan up to the end of the mnemonic, which must end in white space,
17647 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
17648 for (base
= end
= *str
; *end
!= '\0'; end
++)
17649 if (*end
== ' ' || *end
== '.')
17655 /* Handle a possible width suffix and/or Neon type suffix. */
17660 /* The .w and .n suffixes are only valid if the unified syntax is in
17662 if (unified_syntax
&& end
[1] == 'w')
17664 else if (unified_syntax
&& end
[1] == 'n')
17669 inst
.vectype
.elems
= 0;
17671 *str
= end
+ offset
;
17673 if (end
[offset
] == '.')
17675 /* See if we have a Neon type suffix (possible in either unified or
17676 non-unified ARM syntax mode). */
17677 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
17680 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
17686 /* Look for unaffixed or special-case affixed mnemonic. */
17687 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17692 if (opcode
->tag
< OT_odd_infix_0
)
17694 inst
.cond
= COND_ALWAYS
;
17698 if (warn_on_deprecated
&& unified_syntax
)
17699 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17700 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
17701 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17704 inst
.cond
= cond
->value
;
17708 /* Cannot have a conditional suffix on a mnemonic of less than two
17710 if (end
- base
< 3)
17713 /* Look for suffixed mnemonic. */
17715 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17716 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17718 if (opcode
&& cond
)
17721 switch (opcode
->tag
)
17723 case OT_cinfix3_legacy
:
17724 /* Ignore conditional suffixes matched on infix only mnemonics. */
17728 case OT_cinfix3_deprecated
:
17729 case OT_odd_infix_unc
:
17730 if (!unified_syntax
)
17732 /* else fall through */
17736 case OT_csuf_or_in3
:
17737 inst
.cond
= cond
->value
;
17740 case OT_unconditional
:
17741 case OT_unconditionalF
:
17743 inst
.cond
= cond
->value
;
17746 /* Delayed diagnostic. */
17747 inst
.error
= BAD_COND
;
17748 inst
.cond
= COND_ALWAYS
;
17757 /* Cannot have a usual-position infix on a mnemonic of less than
17758 six characters (five would be a suffix). */
17759 if (end
- base
< 6)
17762 /* Look for infixed mnemonic in the usual position. */
17764 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
17768 memcpy (save
, affix
, 2);
17769 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
17770 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
17772 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
17773 memcpy (affix
, save
, 2);
17776 && (opcode
->tag
== OT_cinfix3
17777 || opcode
->tag
== OT_cinfix3_deprecated
17778 || opcode
->tag
== OT_csuf_or_in3
17779 || opcode
->tag
== OT_cinfix3_legacy
))
17782 if (warn_on_deprecated
&& unified_syntax
17783 && (opcode
->tag
== OT_cinfix3
17784 || opcode
->tag
== OT_cinfix3_deprecated
))
17785 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
17787 inst
.cond
= cond
->value
;
17794 /* This function generates an initial IT instruction, leaving its block
17795 virtually open for the new instructions. Eventually,
17796 the mask will be updated by now_it_add_mask () each time
17797 a new instruction needs to be included in the IT block.
17798 Finally, the block is closed with close_automatic_it_block ().
17799 The block closure can be requested either from md_assemble (),
17800 a tencode (), or due to a label hook. */
17803 new_automatic_it_block (int cond
)
17805 now_it
.state
= AUTOMATIC_IT_BLOCK
;
17806 now_it
.mask
= 0x18;
17808 now_it
.block_length
= 1;
17809 mapping_state (MAP_THUMB
);
17810 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
17811 now_it
.warn_deprecated
= FALSE
;
17812 now_it
.insn_cond
= TRUE
;
17815 /* Close an automatic IT block.
17816 See comments in new_automatic_it_block (). */
17819 close_automatic_it_block (void)
17821 now_it
.mask
= 0x10;
17822 now_it
.block_length
= 0;
17825 /* Update the mask of the current automatically-generated IT
17826 instruction. See comments in new_automatic_it_block (). */
17829 now_it_add_mask (int cond
)
17831 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17832 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17833 | ((bitvalue) << (nbit)))
17834 const int resulting_bit
= (cond
& 1);
17836 now_it
.mask
&= 0xf;
17837 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17839 (5 - now_it
.block_length
));
17840 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17842 ((5 - now_it
.block_length
) - 1) );
17843 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17846 #undef SET_BIT_VALUE
17849 /* The IT blocks handling machinery is accessed through the these functions:
17850 it_fsm_pre_encode () from md_assemble ()
17851 set_it_insn_type () optional, from the tencode functions
17852 set_it_insn_type_last () ditto
17853 in_it_block () ditto
17854 it_fsm_post_encode () from md_assemble ()
17855 force_automatic_it_block_close () from label habdling functions
17858 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17859 initializing the IT insn type with a generic initial value depending
17860 on the inst.condition.
17861 2) During the tencode function, two things may happen:
17862 a) The tencode function overrides the IT insn type by
17863 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17864 b) The tencode function queries the IT block state by
17865 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17867 Both set_it_insn_type and in_it_block run the internal FSM state
17868 handling function (handle_it_state), because: a) setting the IT insn
17869 type may incur in an invalid state (exiting the function),
17870 and b) querying the state requires the FSM to be updated.
17871 Specifically we want to avoid creating an IT block for conditional
17872 branches, so it_fsm_pre_encode is actually a guess and we can't
17873 determine whether an IT block is required until the tencode () routine
17874 has decided what type of instruction this actually it.
17875 Because of this, if set_it_insn_type and in_it_block have to be used,
17876 set_it_insn_type has to be called first.
17878 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17879 determines the insn IT type depending on the inst.cond code.
17880 When a tencode () routine encodes an instruction that can be
17881 either outside an IT block, or, in the case of being inside, has to be
17882 the last one, set_it_insn_type_last () will determine the proper
17883 IT instruction type based on the inst.cond code. Otherwise,
17884 set_it_insn_type can be called for overriding that logic or
17885 for covering other cases.
17887 Calling handle_it_state () may not transition the IT block state to
17888 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17889 still queried. Instead, if the FSM determines that the state should
17890 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17891 after the tencode () function: that's what it_fsm_post_encode () does.
17893 Since in_it_block () calls the state handling function to get an
17894 updated state, an error may occur (due to invalid insns combination).
17895 In that case, inst.error is set.
17896 Therefore, inst.error has to be checked after the execution of
17897 the tencode () routine.
17899 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17900 any pending state change (if any) that didn't take place in
17901 handle_it_state () as explained above. */
17904 it_fsm_pre_encode (void)
17906 if (inst
.cond
!= COND_ALWAYS
)
17907 inst
.it_insn_type
= INSIDE_IT_INSN
;
17909 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17911 now_it
.state_handled
= 0;
17914 /* IT state FSM handling function. */
17917 handle_it_state (void)
17919 now_it
.state_handled
= 1;
17920 now_it
.insn_cond
= FALSE
;
17922 switch (now_it
.state
)
17924 case OUTSIDE_IT_BLOCK
:
17925 switch (inst
.it_insn_type
)
17927 case OUTSIDE_IT_INSN
:
17930 case INSIDE_IT_INSN
:
17931 case INSIDE_IT_LAST_INSN
:
17932 if (thumb_mode
== 0)
17935 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17936 as_tsktsk (_("Warning: conditional outside an IT block"\
17941 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17942 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
17944 /* Automatically generate the IT instruction. */
17945 new_automatic_it_block (inst
.cond
);
17946 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17947 close_automatic_it_block ();
17951 inst
.error
= BAD_OUT_IT
;
17957 case IF_INSIDE_IT_LAST_INSN
:
17958 case NEUTRAL_IT_INSN
:
17962 now_it
.state
= MANUAL_IT_BLOCK
;
17963 now_it
.block_length
= 0;
17968 case AUTOMATIC_IT_BLOCK
:
17969 /* Three things may happen now:
17970 a) We should increment current it block size;
17971 b) We should close current it block (closing insn or 4 insns);
17972 c) We should close current it block and start a new one (due
17973 to incompatible conditions or
17974 4 insns-length block reached). */
17976 switch (inst
.it_insn_type
)
17978 case OUTSIDE_IT_INSN
:
17979 /* The closure of the block shall happen immediatelly,
17980 so any in_it_block () call reports the block as closed. */
17981 force_automatic_it_block_close ();
17984 case INSIDE_IT_INSN
:
17985 case INSIDE_IT_LAST_INSN
:
17986 case IF_INSIDE_IT_LAST_INSN
:
17987 now_it
.block_length
++;
17989 if (now_it
.block_length
> 4
17990 || !now_it_compatible (inst
.cond
))
17992 force_automatic_it_block_close ();
17993 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17994 new_automatic_it_block (inst
.cond
);
17998 now_it
.insn_cond
= TRUE
;
17999 now_it_add_mask (inst
.cond
);
18002 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18003 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18004 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18005 close_automatic_it_block ();
18008 case NEUTRAL_IT_INSN
:
18009 now_it
.block_length
++;
18010 now_it
.insn_cond
= TRUE
;
18012 if (now_it
.block_length
> 4)
18013 force_automatic_it_block_close ();
18015 now_it_add_mask (now_it
.cc
& 1);
18019 close_automatic_it_block ();
18020 now_it
.state
= MANUAL_IT_BLOCK
;
18025 case MANUAL_IT_BLOCK
:
18027 /* Check conditional suffixes. */
18028 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18031 now_it
.mask
&= 0x1f;
18032 is_last
= (now_it
.mask
== 0x10);
18033 now_it
.insn_cond
= TRUE
;
18035 switch (inst
.it_insn_type
)
18037 case OUTSIDE_IT_INSN
:
18038 inst
.error
= BAD_NOT_IT
;
18041 case INSIDE_IT_INSN
:
18042 if (cond
!= inst
.cond
)
18044 inst
.error
= BAD_IT_COND
;
18049 case INSIDE_IT_LAST_INSN
:
18050 case IF_INSIDE_IT_LAST_INSN
:
18051 if (cond
!= inst
.cond
)
18053 inst
.error
= BAD_IT_COND
;
18058 inst
.error
= BAD_BRANCH
;
18063 case NEUTRAL_IT_INSN
:
18064 /* The BKPT instruction is unconditional even in an IT block. */
18068 inst
.error
= BAD_IT_IT
;
18078 struct depr_insn_mask
18080 unsigned long pattern
;
18081 unsigned long mask
;
18082 const char* description
;
18085 /* List of 16-bit instruction patterns deprecated in an IT block in
18087 static const struct depr_insn_mask depr_it_insns
[] = {
18088 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18089 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18090 { 0xa000, 0xb800, N_("ADR") },
18091 { 0x4800, 0xf800, N_("Literal loads") },
18092 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18093 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18094 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18095 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18096 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18101 it_fsm_post_encode (void)
18105 if (!now_it
.state_handled
)
18106 handle_it_state ();
18108 if (now_it
.insn_cond
18109 && !now_it
.warn_deprecated
18110 && warn_on_deprecated
18111 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
18113 if (inst
.instruction
>= 0x10000)
18115 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18116 "deprecated in ARMv8"));
18117 now_it
.warn_deprecated
= TRUE
;
18121 const struct depr_insn_mask
*p
= depr_it_insns
;
18123 while (p
->mask
!= 0)
18125 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18127 as_tsktsk (_("IT blocks containing 16-bit Thumb instructions "
18128 "of the following class are deprecated in ARMv8: "
18129 "%s"), p
->description
);
18130 now_it
.warn_deprecated
= TRUE
;
18138 if (now_it
.block_length
> 1)
18140 as_tsktsk (_("IT blocks containing more than one conditional "
18141 "instruction are deprecated in ARMv8"));
18142 now_it
.warn_deprecated
= TRUE
;
18146 is_last
= (now_it
.mask
== 0x10);
18149 now_it
.state
= OUTSIDE_IT_BLOCK
;
18155 force_automatic_it_block_close (void)
18157 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18159 close_automatic_it_block ();
18160 now_it
.state
= OUTSIDE_IT_BLOCK
;
18168 if (!now_it
.state_handled
)
18169 handle_it_state ();
18171 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18174 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18175 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18176 here, hence the "known" in the function name. */
18179 known_t32_only_insn (const struct asm_opcode
*opcode
)
18181 /* Original Thumb-1 wide instruction. */
18182 if (opcode
->tencode
== do_t_blx
18183 || opcode
->tencode
== do_t_branch23
18184 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18185 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18188 /* Wide-only instruction added to ARMv8-M. */
18189 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m
)
18190 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18191 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18192 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18198 /* Whether wide instruction variant can be used if available for a valid OPCODE
18202 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18204 if (known_t32_only_insn (opcode
))
18207 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18208 of variant T3 of B.W is checked in do_t_branch. */
18209 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18210 && opcode
->tencode
== do_t_branch
)
18213 /* Wide instruction variants of all instructions with narrow *and* wide
18214 variants become available with ARMv6t2. Other opcodes are either
18215 narrow-only or wide-only and are thus available if OPCODE is valid. */
18216 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18219 /* OPCODE with narrow only instruction variant or wide variant not
18225 md_assemble (char *str
)
18228 const struct asm_opcode
* opcode
;
18230 /* Align the previous label if needed. */
18231 if (last_label_seen
!= NULL
)
18233 symbol_set_frag (last_label_seen
, frag_now
);
18234 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18235 S_SET_SEGMENT (last_label_seen
, now_seg
);
18238 memset (&inst
, '\0', sizeof (inst
));
18239 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18241 opcode
= opcode_lookup (&p
);
18244 /* It wasn't an instruction, but it might be a register alias of
18245 the form alias .req reg, or a Neon .dn/.qn directive. */
18246 if (! create_register_alias (str
, p
)
18247 && ! create_neon_reg_alias (str
, p
))
18248 as_bad (_("bad instruction `%s'"), str
);
18253 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18254 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18256 /* The value which unconditional instructions should have in place of the
18257 condition field. */
18258 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18262 arm_feature_set variant
;
18264 variant
= cpu_variant
;
18265 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18266 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18267 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18268 /* Check that this instruction is supported for this CPU. */
18269 if (!opcode
->tvariant
18270 || (thumb_mode
== 1
18271 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18273 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18276 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18277 && opcode
->tencode
!= do_t_branch
)
18279 as_bad (_("Thumb does not support conditional execution"));
18283 /* Two things are addressed here:
18284 1) Implicit require narrow instructions on Thumb-1.
18285 This avoids relaxation accidentally introducing Thumb-2
18287 2) Reject wide instructions in non Thumb-2 cores.
18289 Only instructions with narrow and wide variants need to be handled
18290 but selecting all non wide-only instructions is easier. */
18291 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18292 && !t32_insn_ok (variant
, opcode
))
18294 if (inst
.size_req
== 0)
18296 else if (inst
.size_req
== 4)
18298 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18299 as_bad (_("selected processor does not support 32bit wide "
18300 "variant of instruction `%s'"), str
);
18302 as_bad (_("selected processor does not support `%s' in "
18303 "Thumb-2 mode"), str
);
18308 inst
.instruction
= opcode
->tvalue
;
18310 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18312 /* Prepare the it_insn_type for those encodings that don't set
18314 it_fsm_pre_encode ();
18316 opcode
->tencode ();
18318 it_fsm_post_encode ();
18321 if (!(inst
.error
|| inst
.relax
))
18323 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18324 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18325 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18327 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18332 /* Something has gone badly wrong if we try to relax a fixed size
18334 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18336 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18337 *opcode
->tvariant
);
18338 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18339 set those bits when Thumb-2 32-bit instructions are seen. The impact
18340 of relaxable instructions will be considered later after we finish all
18342 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18343 variant
= arm_arch_none
;
18345 variant
= cpu_variant
;
18346 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18347 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18350 check_neon_suffixes
;
18354 mapping_state (MAP_THUMB
);
18357 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18361 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18362 is_bx
= (opcode
->aencode
== do_bx
);
18364 /* Check that this instruction is supported for this CPU. */
18365 if (!(is_bx
&& fix_v4bx
)
18366 && !(opcode
->avariant
&&
18367 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18369 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18374 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18378 inst
.instruction
= opcode
->avalue
;
18379 if (opcode
->tag
== OT_unconditionalF
)
18380 inst
.instruction
|= 0xFU
<< 28;
18382 inst
.instruction
|= inst
.cond
<< 28;
18383 inst
.size
= INSN_SIZE
;
18384 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18386 it_fsm_pre_encode ();
18387 opcode
->aencode ();
18388 it_fsm_post_encode ();
18390 /* Arm mode bx is marked as both v4T and v5 because it's still required
18391 on a hypothetical non-thumb v5 core. */
18393 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18395 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18396 *opcode
->avariant
);
18398 check_neon_suffixes
;
18402 mapping_state (MAP_ARM
);
18407 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18415 check_it_blocks_finished (void)
18420 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18421 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18422 == MANUAL_IT_BLOCK
)
18424 as_warn (_("section '%s' finished with an open IT block."),
18428 if (now_it
.state
== MANUAL_IT_BLOCK
)
18429 as_warn (_("file finished with an open IT block."));
18433 /* Various frobbings of labels and their addresses. */
18436 arm_start_line_hook (void)
18438 last_label_seen
= NULL
;
18442 arm_frob_label (symbolS
* sym
)
18444 last_label_seen
= sym
;
18446 ARM_SET_THUMB (sym
, thumb_mode
);
18448 #if defined OBJ_COFF || defined OBJ_ELF
18449 ARM_SET_INTERWORK (sym
, support_interwork
);
18452 force_automatic_it_block_close ();
18454 /* Note - do not allow local symbols (.Lxxx) to be labelled
18455 as Thumb functions. This is because these labels, whilst
18456 they exist inside Thumb code, are not the entry points for
18457 possible ARM->Thumb calls. Also, these labels can be used
18458 as part of a computed goto or switch statement. eg gcc
18459 can generate code that looks like this:
18461 ldr r2, [pc, .Laaa]
18471 The first instruction loads the address of the jump table.
18472 The second instruction converts a table index into a byte offset.
18473 The third instruction gets the jump address out of the table.
18474 The fourth instruction performs the jump.
18476 If the address stored at .Laaa is that of a symbol which has the
18477 Thumb_Func bit set, then the linker will arrange for this address
18478 to have the bottom bit set, which in turn would mean that the
18479 address computation performed by the third instruction would end
18480 up with the bottom bit set. Since the ARM is capable of unaligned
18481 word loads, the instruction would then load the incorrect address
18482 out of the jump table, and chaos would ensue. */
18483 if (label_is_thumb_function_name
18484 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18485 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18487 /* When the address of a Thumb function is taken the bottom
18488 bit of that address should be set. This will allow
18489 interworking between Arm and Thumb functions to work
18492 THUMB_SET_FUNC (sym
, 1);
18494 label_is_thumb_function_name
= FALSE
;
18497 dwarf2_emit_label (sym
);
18501 arm_data_in_code (void)
18503 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
18505 *input_line_pointer
= '/';
18506 input_line_pointer
+= 5;
18507 *input_line_pointer
= 0;
18515 arm_canonicalize_symbol_name (char * name
)
18519 if (thumb_mode
&& (len
= strlen (name
)) > 5
18520 && streq (name
+ len
- 5, "/data"))
18521 *(name
+ len
- 5) = 0;
18526 /* Table of all register names defined by default. The user can
18527 define additional names with .req. Note that all register names
18528 should appear in both upper and lowercase variants. Some registers
18529 also have mixed-case names. */
18531 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
18532 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
18533 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
18534 #define REGSET(p,t) \
18535 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
18536 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
18537 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
18538 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
18539 #define REGSETH(p,t) \
18540 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
18541 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
18542 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
18543 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
18544 #define REGSET2(p,t) \
18545 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
18546 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
18547 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
18548 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
18549 #define SPLRBANK(base,bank,t) \
18550 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
18551 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
18552 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
18553 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
18554 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
18555 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
18557 static const struct reg_entry reg_names
[] =
18559 /* ARM integer registers. */
18560 REGSET(r
, RN
), REGSET(R
, RN
),
18562 /* ATPCS synonyms. */
18563 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
18564 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
18565 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
18567 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
18568 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
18569 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
18571 /* Well-known aliases. */
18572 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
18573 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
18575 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
18576 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
18578 /* Coprocessor numbers. */
18579 REGSET(p
, CP
), REGSET(P
, CP
),
18581 /* Coprocessor register numbers. The "cr" variants are for backward
18583 REGSET(c
, CN
), REGSET(C
, CN
),
18584 REGSET(cr
, CN
), REGSET(CR
, CN
),
18586 /* ARM banked registers. */
18587 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
18588 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
18589 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
18590 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
18591 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
18592 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
18593 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
18595 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
18596 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
18597 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
18598 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
18599 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
18600 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
18601 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
18602 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
18604 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
18605 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
18606 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
18607 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
18608 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
18609 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
18610 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
18611 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18612 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
18614 /* FPA registers. */
18615 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
18616 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
18618 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
18619 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
18621 /* VFP SP registers. */
18622 REGSET(s
,VFS
), REGSET(S
,VFS
),
18623 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
18625 /* VFP DP Registers. */
18626 REGSET(d
,VFD
), REGSET(D
,VFD
),
18627 /* Extra Neon DP registers. */
18628 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
18630 /* Neon QP registers. */
18631 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
18633 /* VFP control registers. */
18634 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
18635 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
18636 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
18637 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
18638 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
18639 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
18641 /* Maverick DSP coprocessor registers. */
18642 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
18643 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
18645 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
18646 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
18647 REGDEF(dspsc
,0,DSPSC
),
18649 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
18650 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
18651 REGDEF(DSPSC
,0,DSPSC
),
18653 /* iWMMXt data registers - p0, c0-15. */
18654 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
18656 /* iWMMXt control registers - p1, c0-3. */
18657 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
18658 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
18659 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
18660 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
18662 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
18663 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
18664 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
18665 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
18666 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
18668 /* XScale accumulator registers. */
18669 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
18675 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
18676 within psr_required_here. */
18677 static const struct asm_psr psrs
[] =
18679 /* Backward compatibility notation. Note that "all" is no longer
18680 truly all possible PSR bits. */
18681 {"all", PSR_c
| PSR_f
},
18685 /* Individual flags. */
18691 /* Combinations of flags. */
18692 {"fs", PSR_f
| PSR_s
},
18693 {"fx", PSR_f
| PSR_x
},
18694 {"fc", PSR_f
| PSR_c
},
18695 {"sf", PSR_s
| PSR_f
},
18696 {"sx", PSR_s
| PSR_x
},
18697 {"sc", PSR_s
| PSR_c
},
18698 {"xf", PSR_x
| PSR_f
},
18699 {"xs", PSR_x
| PSR_s
},
18700 {"xc", PSR_x
| PSR_c
},
18701 {"cf", PSR_c
| PSR_f
},
18702 {"cs", PSR_c
| PSR_s
},
18703 {"cx", PSR_c
| PSR_x
},
18704 {"fsx", PSR_f
| PSR_s
| PSR_x
},
18705 {"fsc", PSR_f
| PSR_s
| PSR_c
},
18706 {"fxs", PSR_f
| PSR_x
| PSR_s
},
18707 {"fxc", PSR_f
| PSR_x
| PSR_c
},
18708 {"fcs", PSR_f
| PSR_c
| PSR_s
},
18709 {"fcx", PSR_f
| PSR_c
| PSR_x
},
18710 {"sfx", PSR_s
| PSR_f
| PSR_x
},
18711 {"sfc", PSR_s
| PSR_f
| PSR_c
},
18712 {"sxf", PSR_s
| PSR_x
| PSR_f
},
18713 {"sxc", PSR_s
| PSR_x
| PSR_c
},
18714 {"scf", PSR_s
| PSR_c
| PSR_f
},
18715 {"scx", PSR_s
| PSR_c
| PSR_x
},
18716 {"xfs", PSR_x
| PSR_f
| PSR_s
},
18717 {"xfc", PSR_x
| PSR_f
| PSR_c
},
18718 {"xsf", PSR_x
| PSR_s
| PSR_f
},
18719 {"xsc", PSR_x
| PSR_s
| PSR_c
},
18720 {"xcf", PSR_x
| PSR_c
| PSR_f
},
18721 {"xcs", PSR_x
| PSR_c
| PSR_s
},
18722 {"cfs", PSR_c
| PSR_f
| PSR_s
},
18723 {"cfx", PSR_c
| PSR_f
| PSR_x
},
18724 {"csf", PSR_c
| PSR_s
| PSR_f
},
18725 {"csx", PSR_c
| PSR_s
| PSR_x
},
18726 {"cxf", PSR_c
| PSR_x
| PSR_f
},
18727 {"cxs", PSR_c
| PSR_x
| PSR_s
},
18728 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
18729 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
18730 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
18731 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
18732 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
18733 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
18734 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
18735 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
18736 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
18737 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
18738 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
18739 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
18740 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
18741 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
18742 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
18743 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
18744 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
18745 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
18746 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
18747 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
18748 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
18749 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
18750 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
18751 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
18754 /* Table of V7M psr names. */
18755 static const struct asm_psr v7m_psrs
[] =
18757 {"apsr", 0 }, {"APSR", 0 },
18758 {"iapsr", 1 }, {"IAPSR", 1 },
18759 {"eapsr", 2 }, {"EAPSR", 2 },
18760 {"psr", 3 }, {"PSR", 3 },
18761 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
18762 {"ipsr", 5 }, {"IPSR", 5 },
18763 {"epsr", 6 }, {"EPSR", 6 },
18764 {"iepsr", 7 }, {"IEPSR", 7 },
18765 {"msp", 8 }, {"MSP", 8 },
18766 {"psp", 9 }, {"PSP", 9 },
18767 {"primask", 16}, {"PRIMASK", 16},
18768 {"basepri", 17}, {"BASEPRI", 17},
18769 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
18770 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
18771 {"faultmask", 19}, {"FAULTMASK", 19},
18772 {"control", 20}, {"CONTROL", 20}
18775 /* Table of all shift-in-operand names. */
18776 static const struct asm_shift_name shift_names
[] =
18778 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
18779 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
18780 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
18781 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
18782 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
18783 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
18786 /* Table of all explicit relocation names. */
18788 static struct reloc_entry reloc_names
[] =
18790 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
18791 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
18792 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
18793 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
18794 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
18795 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
18796 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
18797 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
18798 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
18799 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
18800 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
18801 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
18802 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
18803 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
18804 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
18805 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
18806 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
18807 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
18811 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
18812 static const struct asm_cond conds
[] =
18816 {"cs", 0x2}, {"hs", 0x2},
18817 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
18831 #define UL_BARRIER(L,U,CODE,FEAT) \
18832 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
18833 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
18835 static struct asm_barrier_opt barrier_opt_names
[] =
18837 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
18838 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
18839 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
18840 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
18841 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
18842 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
18843 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
18844 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
18845 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
18846 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
18847 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
18848 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
18849 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
18850 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
18851 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
18852 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
18857 /* Table of ARM-format instructions. */
18859 /* Macros for gluing together operand strings. N.B. In all cases
18860 other than OPS0, the trailing OP_stop comes from default
18861 zero-initialization of the unspecified elements of the array. */
18862 #define OPS0() { OP_stop, }
18863 #define OPS1(a) { OP_##a, }
18864 #define OPS2(a,b) { OP_##a,OP_##b, }
18865 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
18866 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
18867 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
18868 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
18870 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
18871 This is useful when mixing operands for ARM and THUMB, i.e. using the
18872 MIX_ARM_THUMB_OPERANDS macro.
18873 In order to use these macros, prefix the number of operands with _
18875 #define OPS_1(a) { a, }
18876 #define OPS_2(a,b) { a,b, }
18877 #define OPS_3(a,b,c) { a,b,c, }
18878 #define OPS_4(a,b,c,d) { a,b,c,d, }
18879 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
18880 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
18882 /* These macros abstract out the exact format of the mnemonic table and
18883 save some repeated characters. */
18885 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18886 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18887 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18888 THUMB_VARIANT, do_##ae, do_##te }
18890 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18891 a T_MNEM_xyz enumerator. */
18892 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18893 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18894 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18895 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18897 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18898 infix after the third character. */
18899 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18900 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18901 THUMB_VARIANT, do_##ae, do_##te }
18902 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18903 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18904 THUMB_VARIANT, do_##ae, do_##te }
18905 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18906 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18907 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18908 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18909 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18910 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18911 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18912 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18914 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18915 field is still 0xE. Many of the Thumb variants can be executed
18916 conditionally, so this is checked separately. */
18917 #define TUE(mnem, op, top, nops, ops, ae, te) \
18918 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18919 THUMB_VARIANT, do_##ae, do_##te }
18921 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18922 Used by mnemonics that have very minimal differences in the encoding for
18923 ARM and Thumb variants and can be handled in a common function. */
18924 #define TUEc(mnem, op, top, nops, ops, en) \
18925 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18926 THUMB_VARIANT, do_##en, do_##en }
18928 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18929 condition code field. */
18930 #define TUF(mnem, op, top, nops, ops, ae, te) \
18931 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18932 THUMB_VARIANT, do_##ae, do_##te }
18934 /* ARM-only variants of all the above. */
18935 #define CE(mnem, op, nops, ops, ae) \
18936 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18938 #define C3(mnem, op, nops, ops, ae) \
18939 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18941 /* Legacy mnemonics that always have conditional infix after the third
18943 #define CL(mnem, op, nops, ops, ae) \
18944 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18945 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18947 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18948 #define cCE(mnem, op, nops, ops, ae) \
18949 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18951 /* Legacy coprocessor instructions where conditional infix and conditional
18952 suffix are ambiguous. For consistency this includes all FPA instructions,
18953 not just the potentially ambiguous ones. */
18954 #define cCL(mnem, op, nops, ops, ae) \
18955 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18956 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18958 /* Coprocessor, takes either a suffix or a position-3 infix
18959 (for an FPA corner case). */
18960 #define C3E(mnem, op, nops, ops, ae) \
18961 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18962 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18964 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18965 { m1 #m2 m3, OPS##nops ops, \
18966 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18967 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18969 #define CM(m1, m2, op, nops, ops, ae) \
18970 xCM_ (m1, , m2, op, nops, ops, ae), \
18971 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18972 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18973 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18974 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18975 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18976 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18977 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18978 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18979 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18980 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18981 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18982 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18983 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18984 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18985 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18986 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18987 xCM_ (m1, le, m2, op, nops, ops, ae), \
18988 xCM_ (m1, al, m2, op, nops, ops, ae)
18990 #define UE(mnem, op, nops, ops, ae) \
18991 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18993 #define UF(mnem, op, nops, ops, ae) \
18994 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18996 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18997 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18998 use the same encoding function for each. */
18999 #define NUF(mnem, op, nops, ops, enc) \
19000 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19001 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19003 /* Neon data processing, version which indirects through neon_enc_tab for
19004 the various overloaded versions of opcodes. */
19005 #define nUF(mnem, op, nops, ops, enc) \
19006 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19007 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19009 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19011 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19012 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19013 THUMB_VARIANT, do_##enc, do_##enc }
19015 #define NCE(mnem, op, nops, ops, enc) \
19016 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19018 #define NCEF(mnem, op, nops, ops, enc) \
19019 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19021 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19022 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19023 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19024 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19026 #define nCE(mnem, op, nops, ops, enc) \
19027 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19029 #define nCEF(mnem, op, nops, ops, enc) \
19030 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19034 static const struct asm_opcode insns
[] =
19036 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19037 #define THUMB_VARIANT & arm_ext_v4t
19038 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19039 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19040 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19041 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19042 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19043 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19044 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19045 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19046 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19047 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19048 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19049 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19050 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19051 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19052 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19053 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19055 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19056 for setting PSR flag bits. They are obsolete in V6 and do not
19057 have Thumb equivalents. */
19058 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19059 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19060 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19061 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19062 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19063 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19064 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19065 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19066 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19068 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19069 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19070 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19071 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19073 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19074 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19075 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19077 OP_ADDRGLDR
),ldst
, t_ldst
),
19078 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19080 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19081 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19082 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19083 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19084 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19085 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19087 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19088 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19089 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19090 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19093 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19094 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19095 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19096 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19098 /* Thumb-compatibility pseudo ops. */
19099 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19100 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19101 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19102 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19103 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19104 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19105 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19106 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19107 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19108 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19109 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19110 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19112 /* These may simplify to neg. */
19113 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19114 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19116 #undef THUMB_VARIANT
19117 #define THUMB_VARIANT & arm_ext_v6
19119 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19121 /* V1 instructions with no Thumb analogue prior to V6T2. */
19122 #undef THUMB_VARIANT
19123 #define THUMB_VARIANT & arm_ext_v6t2
19125 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19126 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19127 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19129 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19130 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19131 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19132 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19134 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19135 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19137 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19138 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19140 /* V1 instructions with no Thumb analogue at all. */
19141 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19142 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19144 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19145 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19146 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19147 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19148 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19149 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19150 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19151 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19154 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19155 #undef THUMB_VARIANT
19156 #define THUMB_VARIANT & arm_ext_v4t
19158 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19159 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19161 #undef THUMB_VARIANT
19162 #define THUMB_VARIANT & arm_ext_v6t2
19164 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19165 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19167 /* Generic coprocessor instructions. */
19168 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19169 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19170 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19171 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19172 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19173 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19174 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19177 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19179 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19180 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19183 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19184 #undef THUMB_VARIANT
19185 #define THUMB_VARIANT & arm_ext_msr
19187 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19188 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19191 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19192 #undef THUMB_VARIANT
19193 #define THUMB_VARIANT & arm_ext_v6t2
19195 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19196 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19197 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19198 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19199 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19200 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19201 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19202 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19205 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19206 #undef THUMB_VARIANT
19207 #define THUMB_VARIANT & arm_ext_v4t
19209 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19210 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19211 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19212 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19213 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19214 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19217 #define ARM_VARIANT & arm_ext_v4t_5
19219 /* ARM Architecture 4T. */
19220 /* Note: bx (and blx) are required on V5, even if the processor does
19221 not support Thumb. */
19222 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19225 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19226 #undef THUMB_VARIANT
19227 #define THUMB_VARIANT & arm_ext_v5t
19229 /* Note: blx has 2 variants; the .value coded here is for
19230 BLX(2). Only this variant has conditional execution. */
19231 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19232 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19234 #undef THUMB_VARIANT
19235 #define THUMB_VARIANT & arm_ext_v6t2
19237 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19238 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19239 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19240 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19241 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19242 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19243 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19244 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19247 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19248 #undef THUMB_VARIANT
19249 #define THUMB_VARIANT & arm_ext_v5exp
19251 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19252 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19253 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19254 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19256 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19257 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19259 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19260 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19261 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19262 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19264 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19265 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19266 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19267 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19269 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19270 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19272 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19273 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19274 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19275 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19278 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19279 #undef THUMB_VARIANT
19280 #define THUMB_VARIANT & arm_ext_v6t2
19282 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19283 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19285 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19286 ADDRGLDRS
), ldrd
, t_ldstd
),
19288 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19289 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19292 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19294 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19297 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19298 #undef THUMB_VARIANT
19299 #define THUMB_VARIANT & arm_ext_v6
19301 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19302 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19303 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19304 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19305 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19306 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19307 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19308 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19309 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19310 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19312 #undef THUMB_VARIANT
19313 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19315 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19316 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19318 #undef THUMB_VARIANT
19319 #define THUMB_VARIANT & arm_ext_v6t2
19321 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19322 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19324 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19325 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19327 /* ARM V6 not included in V7M. */
19328 #undef THUMB_VARIANT
19329 #define THUMB_VARIANT & arm_ext_v6_notm
19330 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19331 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19332 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19333 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19334 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19335 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19336 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19337 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19338 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19339 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19340 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19341 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19342 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19343 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19344 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19345 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19346 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19347 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19348 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19350 /* ARM V6 not included in V7M (eg. integer SIMD). */
19351 #undef THUMB_VARIANT
19352 #define THUMB_VARIANT & arm_ext_v6_dsp
19353 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19354 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19355 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19356 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19357 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19358 /* Old name for QASX. */
19359 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19360 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19361 /* Old name for QSAX. */
19362 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19363 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19364 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19365 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19366 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19367 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19368 /* Old name for SASX. */
19369 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19370 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19371 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19372 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19373 /* Old name for SHASX. */
19374 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19375 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19376 /* Old name for SHSAX. */
19377 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19378 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19379 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19380 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19381 /* Old name for SSAX. */
19382 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19383 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19384 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19385 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19386 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19387 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19388 /* Old name for UASX. */
19389 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19390 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19391 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19392 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19393 /* Old name for UHASX. */
19394 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19395 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19396 /* Old name for UHSAX. */
19397 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19398 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19399 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19400 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19401 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19402 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19403 /* Old name for UQASX. */
19404 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19405 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19406 /* Old name for UQSAX. */
19407 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19408 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19409 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19410 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19411 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19412 /* Old name for USAX. */
19413 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19414 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19415 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19416 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19417 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19418 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19419 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19420 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19421 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19422 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19423 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19424 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19425 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19426 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19427 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19428 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19429 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19430 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19431 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19432 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19433 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19434 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19435 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19436 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19437 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19438 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19439 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19440 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19441 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19442 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19443 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19444 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19445 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19446 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19449 #define ARM_VARIANT & arm_ext_v6k
19450 #undef THUMB_VARIANT
19451 #define THUMB_VARIANT & arm_ext_v6k
19453 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19454 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19455 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19456 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19458 #undef THUMB_VARIANT
19459 #define THUMB_VARIANT & arm_ext_v6_notm
19460 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19462 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19463 RRnpcb
), strexd
, t_strexd
),
19465 #undef THUMB_VARIANT
19466 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19467 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19469 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19471 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19473 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19475 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
19478 #define ARM_VARIANT & arm_ext_sec
19479 #undef THUMB_VARIANT
19480 #define THUMB_VARIANT & arm_ext_sec
19482 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
19485 #define ARM_VARIANT & arm_ext_virt
19486 #undef THUMB_VARIANT
19487 #define THUMB_VARIANT & arm_ext_virt
19489 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
19490 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
19493 #define ARM_VARIANT & arm_ext_pan
19494 #undef THUMB_VARIANT
19495 #define THUMB_VARIANT & arm_ext_pan
19497 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
19500 #define ARM_VARIANT & arm_ext_v6t2
19501 #undef THUMB_VARIANT
19502 #define THUMB_VARIANT & arm_ext_v6t2
19504 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
19505 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
19506 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19507 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
19509 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19510 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
19512 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19513 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19514 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19515 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
19517 #undef THUMB_VARIANT
19518 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19519 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19520 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
19522 /* Thumb-only instructions. */
19524 #define ARM_VARIANT NULL
19525 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
19526 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
19528 /* ARM does not really have an IT instruction, so always allow it.
19529 The opcode is copied from Thumb in order to allow warnings in
19530 -mimplicit-it=[never | arm] modes. */
19532 #define ARM_VARIANT & arm_ext_v1
19533 #undef THUMB_VARIANT
19534 #define THUMB_VARIANT & arm_ext_v6t2
19536 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
19537 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
19538 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
19539 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
19540 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
19541 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
19542 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
19543 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
19544 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
19545 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
19546 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
19547 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
19548 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
19549 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
19550 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
19551 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
19552 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19553 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
19555 /* Thumb2 only instructions. */
19557 #define ARM_VARIANT NULL
19559 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19560 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
19561 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19562 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
19563 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
19564 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
19566 /* Hardware division instructions. */
19568 #define ARM_VARIANT & arm_ext_adiv
19569 #undef THUMB_VARIANT
19570 #define THUMB_VARIANT & arm_ext_div
19572 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19573 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
19575 /* ARM V6M/V7 instructions. */
19577 #define ARM_VARIANT & arm_ext_barrier
19578 #undef THUMB_VARIANT
19579 #define THUMB_VARIANT & arm_ext_barrier
19581 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
19582 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
19583 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
19585 /* ARM V7 instructions. */
19587 #define ARM_VARIANT & arm_ext_v7
19588 #undef THUMB_VARIANT
19589 #define THUMB_VARIANT & arm_ext_v7
19591 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
19592 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
19595 #define ARM_VARIANT & arm_ext_mp
19596 #undef THUMB_VARIANT
19597 #define THUMB_VARIANT & arm_ext_mp
19599 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
19601 /* AArchv8 instructions. */
19603 #define ARM_VARIANT & arm_ext_v8
19605 /* Instructions shared between armv8-a and armv8-m. */
19606 #undef THUMB_VARIANT
19607 #define THUMB_VARIANT & arm_ext_atomics
19609 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19610 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19611 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19612 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19613 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19614 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
19615 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19616 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
19617 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
19618 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19620 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19622 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
19624 #undef THUMB_VARIANT
19625 #define THUMB_VARIANT & arm_ext_v8
19627 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
19628 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
19629 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
19631 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
19633 /* ARMv8 T32 only. */
19635 #define ARM_VARIANT NULL
19636 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
19637 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
19638 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
19640 /* FP for ARMv8. */
19642 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
19643 #undef THUMB_VARIANT
19644 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
19646 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19647 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19648 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19649 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
19650 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19651 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
19652 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
19653 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
19654 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
19655 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
19656 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
19657 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
19658 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
19659 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
19660 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
19661 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
19662 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
19664 /* Crypto v1 extensions. */
19666 #define ARM_VARIANT & fpu_crypto_ext_armv8
19667 #undef THUMB_VARIANT
19668 #define THUMB_VARIANT & fpu_crypto_ext_armv8
19670 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
19671 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
19672 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
19673 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
19674 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
19675 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
19676 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
19677 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
19678 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
19679 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
19680 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
19681 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
19682 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
19683 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
19686 #define ARM_VARIANT & crc_ext_armv8
19687 #undef THUMB_VARIANT
19688 #define THUMB_VARIANT & crc_ext_armv8
19689 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
19690 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
19691 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
19692 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
19693 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
19694 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
19696 /* ARMv8.2 RAS extension. */
19698 #define ARM_VARIANT & arm_ext_v8_2
19699 #undef THUMB_VARIANT
19700 #define THUMB_VARIANT & arm_ext_v8_2
19701 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
19704 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
19705 #undef THUMB_VARIANT
19706 #define THUMB_VARIANT NULL
19708 cCE("wfs", e200110
, 1, (RR
), rd
),
19709 cCE("rfs", e300110
, 1, (RR
), rd
),
19710 cCE("wfc", e400110
, 1, (RR
), rd
),
19711 cCE("rfc", e500110
, 1, (RR
), rd
),
19713 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19714 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19715 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19716 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19718 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19719 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19720 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19721 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
19723 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
19724 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
19725 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
19726 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
19727 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
19728 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
19729 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
19730 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
19731 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
19732 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
19733 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
19734 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
19736 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
19737 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
19738 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
19739 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
19740 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
19741 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
19742 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
19743 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
19744 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
19745 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
19746 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
19747 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
19749 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
19750 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
19751 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
19752 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
19753 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
19754 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
19755 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
19756 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
19757 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
19758 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
19759 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
19760 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
19762 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
19763 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
19764 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
19765 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
19766 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
19767 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
19768 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
19769 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
19770 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
19771 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
19772 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
19773 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
19775 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
19776 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
19777 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
19778 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
19779 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
19780 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
19781 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
19782 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
19783 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
19784 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
19785 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
19786 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
19788 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
19789 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
19790 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
19791 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
19792 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
19793 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
19794 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
19795 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
19796 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
19797 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
19798 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
19799 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
19801 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
19802 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
19803 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
19804 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
19805 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
19806 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
19807 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
19808 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
19809 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
19810 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
19811 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
19812 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
19814 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
19815 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
19816 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
19817 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
19818 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
19819 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
19820 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
19821 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
19822 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
19823 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
19824 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
19825 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
19827 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
19828 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
19829 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
19830 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
19831 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
19832 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
19833 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
19834 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
19835 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
19836 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
19837 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
19838 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
19840 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
19841 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
19842 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
19843 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
19844 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
19845 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
19846 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
19847 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
19848 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
19849 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
19850 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
19851 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
19853 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
19854 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
19855 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
19856 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
19857 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
19858 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
19859 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
19860 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
19861 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
19862 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
19863 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
19864 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
19866 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
19867 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
19868 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
19869 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
19870 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
19871 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
19872 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
19873 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
19874 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
19875 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
19876 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
19877 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
19879 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
19880 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
19881 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
19882 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
19883 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
19884 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
19885 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
19886 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
19887 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
19888 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
19889 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
19890 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
19892 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
19893 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
19894 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
19895 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
19896 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
19897 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
19898 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
19899 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
19900 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
19901 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
19902 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
19903 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
19905 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
19906 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
19907 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
19908 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
19909 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
19910 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19911 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19912 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19913 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19914 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19915 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19916 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19918 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19919 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19920 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19921 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19922 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19923 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19924 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19925 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19926 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19927 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19928 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19929 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19931 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19932 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19933 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19934 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19935 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19936 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19937 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19938 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19939 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19940 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19941 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19942 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19944 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19945 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19946 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19947 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19948 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19949 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19950 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19951 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19952 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19953 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19954 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19955 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19957 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19958 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19959 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19960 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19961 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19962 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19963 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19964 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19965 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19966 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19967 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19968 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19970 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19971 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19972 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19973 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19974 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19975 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19976 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19977 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19978 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19979 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19980 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19981 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19983 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19984 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19985 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19986 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19987 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19988 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19989 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19990 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19991 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19992 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19993 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19994 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19996 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19997 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19998 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19999 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20000 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20001 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20002 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20003 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20004 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20005 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20006 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20007 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20009 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20010 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20011 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20012 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20013 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20014 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20015 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20016 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20017 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20018 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20019 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20020 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20022 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20023 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20024 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20025 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20026 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20027 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20028 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20029 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20030 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20031 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20032 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20033 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20035 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20036 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20037 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20038 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20039 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20040 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20041 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20042 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20043 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20044 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20045 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20046 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20048 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20049 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20050 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20051 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20052 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20053 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20054 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20055 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20056 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20057 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20058 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20059 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20061 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20062 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20063 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20064 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20065 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20066 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20067 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20068 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20069 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20070 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20071 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20072 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20074 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20075 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20076 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20077 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20078 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20079 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20080 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20081 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20082 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20083 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20084 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20085 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20087 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20088 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20089 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20090 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20091 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20092 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20093 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20094 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20095 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20096 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20097 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20098 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20100 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20101 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20102 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20103 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20105 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20106 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20107 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20108 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20109 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20110 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20111 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20112 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20113 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20114 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20115 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20116 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20118 /* The implementation of the FIX instruction is broken on some
20119 assemblers, in that it accepts a precision specifier as well as a
20120 rounding specifier, despite the fact that this is meaningless.
20121 To be more compatible, we accept it as well, though of course it
20122 does not set any bits. */
20123 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20124 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20125 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20126 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20127 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20128 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20129 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20130 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20131 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20132 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20133 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20134 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20135 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20137 /* Instructions that were new with the real FPA, call them V2. */
20139 #define ARM_VARIANT & fpu_fpa_ext_v2
20141 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20142 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20143 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20144 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20145 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20146 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20149 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20151 /* Moves and type conversions. */
20152 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20153 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20154 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20155 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20156 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20157 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20158 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20159 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20160 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20161 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20162 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20163 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20164 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20165 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20167 /* Memory operations. */
20168 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20169 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20170 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20171 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20172 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20173 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20174 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20175 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20176 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20177 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20178 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20179 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20180 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20181 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20182 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20183 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20184 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20185 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20187 /* Monadic operations. */
20188 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20189 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20190 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20192 /* Dyadic operations. */
20193 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20194 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20195 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20196 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20197 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20198 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20199 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20200 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20201 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20204 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20205 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20206 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20207 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20209 /* Double precision load/store are still present on single precision
20210 implementations. */
20211 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20212 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20213 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20214 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20215 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20216 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20217 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20218 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20219 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20220 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20223 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20225 /* Moves and type conversions. */
20226 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20227 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20228 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20229 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20230 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20231 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20232 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20233 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20234 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20235 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20236 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20237 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20238 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20240 /* Monadic operations. */
20241 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20242 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20243 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20245 /* Dyadic operations. */
20246 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20247 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20248 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20249 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20250 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20251 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20252 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20253 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20254 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20257 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20258 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20259 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20260 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20263 #define ARM_VARIANT & fpu_vfp_ext_v2
20265 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20266 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20267 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20268 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20270 /* Instructions which may belong to either the Neon or VFP instruction sets.
20271 Individual encoder functions perform additional architecture checks. */
20273 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20274 #undef THUMB_VARIANT
20275 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20277 /* These mnemonics are unique to VFP. */
20278 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20279 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20280 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20281 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20282 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20283 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20284 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20285 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20286 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20287 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20289 /* Mnemonics shared by Neon and VFP. */
20290 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20291 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20292 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20294 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20295 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20297 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20298 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20300 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20301 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20302 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20303 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20304 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20305 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20306 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20307 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20309 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20310 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20311 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20312 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20315 /* NOTE: All VMOV encoding is special-cased! */
20316 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20317 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20320 #define ARM_VARIANT & arm_ext_fp16
20321 #undef THUMB_VARIANT
20322 #define THUMB_VARIANT & arm_ext_fp16
20323 /* New instructions added from v8.2, allowing the extraction and insertion of
20324 the upper 16 bits of a 32-bit vector register. */
20325 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20326 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20328 #undef THUMB_VARIANT
20329 #define THUMB_VARIANT & fpu_neon_ext_v1
20331 #define ARM_VARIANT & fpu_neon_ext_v1
20333 /* Data processing with three registers of the same length. */
20334 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20335 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20336 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20337 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20338 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20339 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20340 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20341 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20342 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20343 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20344 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20345 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20346 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20347 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20348 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20349 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20350 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20351 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20352 /* If not immediate, fall back to neon_dyadic_i64_su.
20353 shl_imm should accept I8 I16 I32 I64,
20354 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20355 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20356 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20357 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20358 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20359 /* Logic ops, types optional & ignored. */
20360 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20361 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20362 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20363 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20364 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20365 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20366 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20367 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20368 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20369 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20370 /* Bitfield ops, untyped. */
20371 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20372 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20373 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20374 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20375 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20376 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20377 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20378 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20379 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20380 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20381 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20382 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20383 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20384 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20385 back to neon_dyadic_if_su. */
20386 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20387 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20388 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20389 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20390 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20391 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20392 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20393 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20394 /* Comparison. Type I8 I16 I32 F32. */
20395 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20396 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20397 /* As above, D registers only. */
20398 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20399 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20400 /* Int and float variants, signedness unimportant. */
20401 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20402 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20403 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20404 /* Add/sub take types I8 I16 I32 I64 F32. */
20405 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20406 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20407 /* vtst takes sizes 8, 16, 32. */
20408 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20409 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20410 /* VMUL takes I8 I16 I32 F32 P8. */
20411 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20412 /* VQD{R}MULH takes S16 S32. */
20413 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20414 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20415 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20416 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20417 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20418 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20419 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20420 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20421 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20422 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20423 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20424 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20425 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20426 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20427 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20428 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20429 /* ARM v8.1 extension. */
20430 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20431 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20432 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20433 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20435 /* Two address, int/float. Types S8 S16 S32 F32. */
20436 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20437 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20439 /* Data processing with two registers and a shift amount. */
20440 /* Right shifts, and variants with rounding.
20441 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20442 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20443 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20444 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20445 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20446 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20447 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20448 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
20449 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
20450 /* Shift and insert. Sizes accepted 8 16 32 64. */
20451 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
20452 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
20453 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
20454 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
20455 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
20456 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
20457 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
20458 /* Right shift immediate, saturating & narrowing, with rounding variants.
20459 Types accepted S16 S32 S64 U16 U32 U64. */
20460 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20461 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
20462 /* As above, unsigned. Types accepted S16 S32 S64. */
20463 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20464 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
20465 /* Right shift narrowing. Types accepted I16 I32 I64. */
20466 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20467 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
20468 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
20469 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
20470 /* CVT with optional immediate for fixed-point variant. */
20471 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
20473 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
20474 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
20476 /* Data processing, three registers of different lengths. */
20477 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
20478 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
20479 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20480 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20481 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
20482 /* If not scalar, fall back to neon_dyadic_long.
20483 Vector types as above, scalar types S16 S32 U16 U32. */
20484 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20485 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
20486 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
20487 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20488 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
20489 /* Dyadic, narrowing insns. Types I16 I32 I64. */
20490 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20491 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20492 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20493 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
20494 /* Saturating doubling multiplies. Types S16 S32. */
20495 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20496 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20497 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
20498 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
20499 S16 S32 U16 U32. */
20500 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
20502 /* Extract. Size 8. */
20503 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
20504 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
20506 /* Two registers, miscellaneous. */
20507 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
20508 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
20509 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
20510 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
20511 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
20512 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
20513 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
20514 /* Vector replicate. Sizes 8 16 32. */
20515 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
20516 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
20517 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
20518 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
20519 /* VMOVN. Types I16 I32 I64. */
20520 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
20521 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
20522 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
20523 /* VQMOVUN. Types S16 S32 S64. */
20524 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
20525 /* VZIP / VUZP. Sizes 8 16 32. */
20526 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20527 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20528 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
20529 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
20530 /* VQABS / VQNEG. Types S8 S16 S32. */
20531 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20532 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20533 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
20534 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
20535 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
20536 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20537 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
20538 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
20539 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
20540 /* Reciprocal estimates. Types U32 F16 F32. */
20541 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20542 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
20543 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
20544 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
20545 /* VCLS. Types S8 S16 S32. */
20546 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
20547 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
20548 /* VCLZ. Types I8 I16 I32. */
20549 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
20550 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
20551 /* VCNT. Size 8. */
20552 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
20553 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
20554 /* Two address, untyped. */
20555 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
20556 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
20557 /* VTRN. Sizes 8 16 32. */
20558 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
20559 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
20561 /* Table lookup. Size 8. */
20562 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20563 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
20565 #undef THUMB_VARIANT
20566 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
20568 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
20570 /* Neon element/structure load/store. */
20571 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20572 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20573 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20574 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20575 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20576 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20577 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20578 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
20580 #undef THUMB_VARIANT
20581 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
20583 #define ARM_VARIANT & fpu_vfp_ext_v3xd
20584 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
20585 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20586 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20587 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20588 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20589 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20590 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20591 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
20592 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
20594 #undef THUMB_VARIANT
20595 #define THUMB_VARIANT & fpu_vfp_ext_v3
20597 #define ARM_VARIANT & fpu_vfp_ext_v3
20599 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
20600 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20601 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20602 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20603 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20604 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20605 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20606 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
20607 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
20610 #define ARM_VARIANT & fpu_vfp_ext_fma
20611 #undef THUMB_VARIANT
20612 #define THUMB_VARIANT & fpu_vfp_ext_fma
20613 /* Mnemonics shared by Neon and VFP. These are included in the
20614 VFP FMA variant; NEON and VFP FMA always includes the NEON
20615 FMA instructions. */
20616 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20617 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
20618 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
20619 the v form should always be used. */
20620 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20621 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20622 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20623 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20624 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20625 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20627 #undef THUMB_VARIANT
20629 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
20631 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20632 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20633 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20634 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20635 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20636 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
20637 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
20638 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
20641 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
20643 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
20644 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
20645 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
20646 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
20647 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
20648 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
20649 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
20650 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
20651 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
20652 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20653 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20654 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20655 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20656 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20657 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
20658 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20659 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20660 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
20661 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
20662 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
20663 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20664 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20665 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20666 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20667 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20668 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
20669 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
20670 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
20671 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
20672 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
20673 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
20674 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
20675 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
20676 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
20677 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20678 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20679 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20680 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20681 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20682 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20683 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20684 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20685 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20686 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20687 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20688 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20689 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
20690 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20691 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20692 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20693 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20694 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20695 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20696 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20697 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20698 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20699 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20700 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20701 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20702 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20703 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20704 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20705 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20706 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20707 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20708 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20709 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20710 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20711 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20712 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20713 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20714 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20715 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20716 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20717 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20718 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20719 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20720 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20721 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20722 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20723 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20724 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20725 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20726 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20727 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20728 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20729 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20730 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20731 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
20732 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20733 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20734 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20735 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20736 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20737 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20738 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20739 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20740 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20741 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20742 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20743 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20744 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20745 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20746 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20747 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20748 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20749 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20750 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20751 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20752 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20753 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
20754 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20755 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20756 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20757 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20758 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20759 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20760 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20761 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20762 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20763 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20764 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20765 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20766 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20767 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20768 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20769 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20770 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
20771 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
20772 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20773 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
20774 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
20775 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
20776 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20777 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20778 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20779 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20780 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20781 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20782 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20783 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20784 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20785 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20786 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20787 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20788 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20789 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20790 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
20791 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20792 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20793 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20794 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20795 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20796 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20797 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20798 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20799 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
20800 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20801 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20802 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20803 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20804 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
20807 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
20809 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
20810 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
20811 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
20812 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20813 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20814 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
20815 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20816 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20817 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20818 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20819 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20820 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20821 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20822 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20823 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20824 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20825 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20826 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20827 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20828 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20829 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
20830 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20831 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20832 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20833 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20834 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20835 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20836 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20837 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20838 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20839 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20840 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20841 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20842 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20843 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20844 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20845 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20846 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20847 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20848 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20849 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20850 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20851 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20852 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20853 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20854 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20855 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20856 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20857 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20858 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20859 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20860 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20861 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20862 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20863 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20864 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20865 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
20868 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
20870 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20871 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20872 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20873 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20874 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
20875 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
20876 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
20877 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
20878 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
20879 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
20880 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
20881 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
20882 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
20883 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
20884 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
20885 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
20886 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
20887 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
20888 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
20889 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
20890 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
20891 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
20892 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
20893 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
20894 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
20895 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
20896 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
20897 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
20898 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
20899 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
20900 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
20901 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
20902 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
20903 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
20904 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
20905 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
20906 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
20907 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
20908 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
20909 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
20910 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
20911 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
20912 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
20913 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
20914 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
20915 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
20916 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
20917 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
20918 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
20919 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
20920 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
20921 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
20922 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
20923 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
20924 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20925 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20926 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20927 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20928 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20929 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20930 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20931 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20932 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20933 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20934 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20935 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20936 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20937 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20938 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20939 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20940 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20941 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20942 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20943 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20944 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20945 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20948 #define ARM_VARIANT NULL
20949 #undef THUMB_VARIANT
20950 #define THUMB_VARIANT & arm_ext_v8m
20951 TUE("tt", 0, e840f000
, 2, (RRnpc
, RRnpc
), 0, tt
),
20952 TUE("ttt", 0, e840f040
, 2, (RRnpc
, RRnpc
), 0, tt
),
20955 #undef THUMB_VARIANT
20981 /* MD interface: bits in the object file. */
20983 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20984 for use in the a.out file, and stores them in the array pointed to by buf.
20985 This knows about the endian-ness of the target machine and does
20986 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20987 2 (short) and 4 (long) Floating numbers are put out as a series of
20988 LITTLENUMS (shorts, here at least). */
20991 md_number_to_chars (char * buf
, valueT val
, int n
)
20993 if (target_big_endian
)
20994 number_to_chars_bigendian (buf
, val
, n
);
20996 number_to_chars_littleendian (buf
, val
, n
);
21000 md_chars_to_number (char * buf
, int n
)
21003 unsigned char * where
= (unsigned char *) buf
;
21005 if (target_big_endian
)
21010 result
|= (*where
++ & 255);
21018 result
|= (where
[n
] & 255);
21025 /* MD interface: Sections. */
21027 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21028 that an rs_machine_dependent frag may reach. */
21031 arm_frag_max_var (fragS
*fragp
)
21033 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21034 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21036 Note that we generate relaxable instructions even for cases that don't
21037 really need it, like an immediate that's a trivial constant. So we're
21038 overestimating the instruction size for some of those cases. Rather
21039 than putting more intelligence here, it would probably be better to
21040 avoid generating a relaxation frag in the first place when it can be
21041 determined up front that a short instruction will suffice. */
21043 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21047 /* Estimate the size of a frag before relaxing. Assume everything fits in
21051 md_estimate_size_before_relax (fragS
* fragp
,
21052 segT segtype ATTRIBUTE_UNUSED
)
21058 /* Convert a machine dependent frag. */
21061 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21063 unsigned long insn
;
21064 unsigned long old_op
;
21072 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21074 old_op
= bfd_get_16(abfd
, buf
);
21075 if (fragp
->fr_symbol
)
21077 exp
.X_op
= O_symbol
;
21078 exp
.X_add_symbol
= fragp
->fr_symbol
;
21082 exp
.X_op
= O_constant
;
21084 exp
.X_add_number
= fragp
->fr_offset
;
21085 opcode
= fragp
->fr_subtype
;
21088 case T_MNEM_ldr_pc
:
21089 case T_MNEM_ldr_pc2
:
21090 case T_MNEM_ldr_sp
:
21091 case T_MNEM_str_sp
:
21098 if (fragp
->fr_var
== 4)
21100 insn
= THUMB_OP32 (opcode
);
21101 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21103 insn
|= (old_op
& 0x700) << 4;
21107 insn
|= (old_op
& 7) << 12;
21108 insn
|= (old_op
& 0x38) << 13;
21110 insn
|= 0x00000c00;
21111 put_thumb32_insn (buf
, insn
);
21112 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21116 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21118 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21121 if (fragp
->fr_var
== 4)
21123 insn
= THUMB_OP32 (opcode
);
21124 insn
|= (old_op
& 0xf0) << 4;
21125 put_thumb32_insn (buf
, insn
);
21126 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21130 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21131 exp
.X_add_number
-= 4;
21139 if (fragp
->fr_var
== 4)
21141 int r0off
= (opcode
== T_MNEM_mov
21142 || opcode
== T_MNEM_movs
) ? 0 : 8;
21143 insn
= THUMB_OP32 (opcode
);
21144 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21145 insn
|= (old_op
& 0x700) << r0off
;
21146 put_thumb32_insn (buf
, insn
);
21147 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21151 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21156 if (fragp
->fr_var
== 4)
21158 insn
= THUMB_OP32(opcode
);
21159 put_thumb32_insn (buf
, insn
);
21160 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21163 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21167 if (fragp
->fr_var
== 4)
21169 insn
= THUMB_OP32(opcode
);
21170 insn
|= (old_op
& 0xf00) << 14;
21171 put_thumb32_insn (buf
, insn
);
21172 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21175 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21178 case T_MNEM_add_sp
:
21179 case T_MNEM_add_pc
:
21180 case T_MNEM_inc_sp
:
21181 case T_MNEM_dec_sp
:
21182 if (fragp
->fr_var
== 4)
21184 /* ??? Choose between add and addw. */
21185 insn
= THUMB_OP32 (opcode
);
21186 insn
|= (old_op
& 0xf0) << 4;
21187 put_thumb32_insn (buf
, insn
);
21188 if (opcode
== T_MNEM_add_pc
)
21189 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21191 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21194 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21202 if (fragp
->fr_var
== 4)
21204 insn
= THUMB_OP32 (opcode
);
21205 insn
|= (old_op
& 0xf0) << 4;
21206 insn
|= (old_op
& 0xf) << 16;
21207 put_thumb32_insn (buf
, insn
);
21208 if (insn
& (1 << 20))
21209 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21211 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21214 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21220 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21221 (enum bfd_reloc_code_real
) reloc_type
);
21222 fixp
->fx_file
= fragp
->fr_file
;
21223 fixp
->fx_line
= fragp
->fr_line
;
21224 fragp
->fr_fix
+= fragp
->fr_var
;
21226 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21227 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21228 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21229 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21232 /* Return the size of a relaxable immediate operand instruction.
21233 SHIFT and SIZE specify the form of the allowable immediate. */
21235 relax_immediate (fragS
*fragp
, int size
, int shift
)
21241 /* ??? Should be able to do better than this. */
21242 if (fragp
->fr_symbol
)
21245 low
= (1 << shift
) - 1;
21246 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21247 offset
= fragp
->fr_offset
;
21248 /* Force misaligned offsets to 32-bit variant. */
21251 if (offset
& ~mask
)
21256 /* Get the address of a symbol during relaxation. */
21258 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21264 sym
= fragp
->fr_symbol
;
21265 sym_frag
= symbol_get_frag (sym
);
21266 know (S_GET_SEGMENT (sym
) != absolute_section
21267 || sym_frag
== &zero_address_frag
);
21268 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21270 /* If frag has yet to be reached on this pass, assume it will
21271 move by STRETCH just as we did. If this is not so, it will
21272 be because some frag between grows, and that will force
21276 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21280 /* Adjust stretch for any alignment frag. Note that if have
21281 been expanding the earlier code, the symbol may be
21282 defined in what appears to be an earlier frag. FIXME:
21283 This doesn't handle the fr_subtype field, which specifies
21284 a maximum number of bytes to skip when doing an
21286 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21288 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21291 stretch
= - ((- stretch
)
21292 & ~ ((1 << (int) f
->fr_offset
) - 1));
21294 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21306 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21309 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21314 /* Assume worst case for symbols not known to be in the same section. */
21315 if (fragp
->fr_symbol
== NULL
21316 || !S_IS_DEFINED (fragp
->fr_symbol
)
21317 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21318 || S_IS_WEAK (fragp
->fr_symbol
))
21321 val
= relaxed_symbol_addr (fragp
, stretch
);
21322 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21323 addr
= (addr
+ 4) & ~3;
21324 /* Force misaligned targets to 32-bit variant. */
21328 if (val
< 0 || val
> 1020)
21333 /* Return the size of a relaxable add/sub immediate instruction. */
21335 relax_addsub (fragS
*fragp
, asection
*sec
)
21340 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21341 op
= bfd_get_16(sec
->owner
, buf
);
21342 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21343 return relax_immediate (fragp
, 8, 0);
21345 return relax_immediate (fragp
, 3, 0);
21348 /* Return TRUE iff the definition of symbol S could be pre-empted
21349 (overridden) at link or load time. */
21351 symbol_preemptible (symbolS
*s
)
21353 /* Weak symbols can always be pre-empted. */
21357 /* Non-global symbols cannot be pre-empted. */
21358 if (! S_IS_EXTERNAL (s
))
21362 /* In ELF, a global symbol can be marked protected, or private. In that
21363 case it can't be pre-empted (other definitions in the same link unit
21364 would violate the ODR). */
21365 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21369 /* Other global symbols might be pre-empted. */
21373 /* Return the size of a relaxable branch instruction. BITS is the
21374 size of the offset field in the narrow instruction. */
21377 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21383 /* Assume worst case for symbols not known to be in the same section. */
21384 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21385 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21386 || S_IS_WEAK (fragp
->fr_symbol
))
21390 /* A branch to a function in ARM state will require interworking. */
21391 if (S_IS_DEFINED (fragp
->fr_symbol
)
21392 && ARM_IS_FUNC (fragp
->fr_symbol
))
21396 if (symbol_preemptible (fragp
->fr_symbol
))
21399 val
= relaxed_symbol_addr (fragp
, stretch
);
21400 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21403 /* Offset is a signed value *2 */
21405 if (val
>= limit
|| val
< -limit
)
21411 /* Relax a machine dependent frag. This returns the amount by which
21412 the current size of the frag should change. */
21415 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21420 oldsize
= fragp
->fr_var
;
21421 switch (fragp
->fr_subtype
)
21423 case T_MNEM_ldr_pc2
:
21424 newsize
= relax_adr (fragp
, sec
, stretch
);
21426 case T_MNEM_ldr_pc
:
21427 case T_MNEM_ldr_sp
:
21428 case T_MNEM_str_sp
:
21429 newsize
= relax_immediate (fragp
, 8, 2);
21433 newsize
= relax_immediate (fragp
, 5, 2);
21437 newsize
= relax_immediate (fragp
, 5, 1);
21441 newsize
= relax_immediate (fragp
, 5, 0);
21444 newsize
= relax_adr (fragp
, sec
, stretch
);
21450 newsize
= relax_immediate (fragp
, 8, 0);
21453 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
21456 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
21458 case T_MNEM_add_sp
:
21459 case T_MNEM_add_pc
:
21460 newsize
= relax_immediate (fragp
, 8, 2);
21462 case T_MNEM_inc_sp
:
21463 case T_MNEM_dec_sp
:
21464 newsize
= relax_immediate (fragp
, 7, 2);
21470 newsize
= relax_addsub (fragp
, sec
);
21476 fragp
->fr_var
= newsize
;
21477 /* Freeze wide instructions that are at or before the same location as
21478 in the previous pass. This avoids infinite loops.
21479 Don't freeze them unconditionally because targets may be artificially
21480 misaligned by the expansion of preceding frags. */
21481 if (stretch
<= 0 && newsize
> 2)
21483 md_convert_frag (sec
->owner
, sec
, fragp
);
21487 return newsize
- oldsize
;
21490 /* Round up a section size to the appropriate boundary. */
21493 md_section_align (segT segment ATTRIBUTE_UNUSED
,
21496 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
21497 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
21499 /* For a.out, force the section size to be aligned. If we don't do
21500 this, BFD will align it for us, but it will not write out the
21501 final bytes of the section. This may be a bug in BFD, but it is
21502 easier to fix it here since that is how the other a.out targets
21506 align
= bfd_get_section_alignment (stdoutput
, segment
);
21507 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
21514 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
21515 of an rs_align_code fragment. */
21518 arm_handle_align (fragS
* fragP
)
21520 static unsigned char const arm_noop
[2][2][4] =
21523 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
21524 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
21527 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
21528 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
21531 static unsigned char const thumb_noop
[2][2][2] =
21534 {0xc0, 0x46}, /* LE */
21535 {0x46, 0xc0}, /* BE */
21538 {0x00, 0xbf}, /* LE */
21539 {0xbf, 0x00} /* BE */
21542 static unsigned char const wide_thumb_noop
[2][4] =
21543 { /* Wide Thumb-2 */
21544 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
21545 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
21548 unsigned bytes
, fix
, noop_size
;
21550 const unsigned char * noop
;
21551 const unsigned char *narrow_noop
= NULL
;
21556 if (fragP
->fr_type
!= rs_align_code
)
21559 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
21560 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
21563 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21564 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
21566 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
21568 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
21570 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21571 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
21573 narrow_noop
= thumb_noop
[1][target_big_endian
];
21574 noop
= wide_thumb_noop
[target_big_endian
];
21577 noop
= thumb_noop
[0][target_big_endian
];
21585 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
21586 ? selected_cpu
: arm_arch_none
,
21588 [target_big_endian
];
21595 fragP
->fr_var
= noop_size
;
21597 if (bytes
& (noop_size
- 1))
21599 fix
= bytes
& (noop_size
- 1);
21601 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
21603 memset (p
, 0, fix
);
21610 if (bytes
& noop_size
)
21612 /* Insert a narrow noop. */
21613 memcpy (p
, narrow_noop
, noop_size
);
21615 bytes
-= noop_size
;
21619 /* Use wide noops for the remainder */
21623 while (bytes
>= noop_size
)
21625 memcpy (p
, noop
, noop_size
);
21627 bytes
-= noop_size
;
21631 fragP
->fr_fix
+= fix
;
21634 /* Called from md_do_align. Used to create an alignment
21635 frag in a code section. */
21638 arm_frag_align_code (int n
, int max
)
21642 /* We assume that there will never be a requirement
21643 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
21644 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
21649 _("alignments greater than %d bytes not supported in .text sections."),
21650 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
21651 as_fatal ("%s", err_msg
);
21654 p
= frag_var (rs_align_code
,
21655 MAX_MEM_FOR_RS_ALIGN_CODE
,
21657 (relax_substateT
) max
,
21664 /* Perform target specific initialisation of a frag.
21665 Note - despite the name this initialisation is not done when the frag
21666 is created, but only when its type is assigned. A frag can be created
21667 and used a long time before its type is set, so beware of assuming that
21668 this initialisationis performed first. */
21672 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
21674 /* Record whether this frag is in an ARM or a THUMB area. */
21675 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21678 #else /* OBJ_ELF is defined. */
21680 arm_init_frag (fragS
* fragP
, int max_chars
)
21682 int frag_thumb_mode
;
21684 /* If the current ARM vs THUMB mode has not already
21685 been recorded into this frag then do so now. */
21686 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
21687 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21689 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
21691 /* Record a mapping symbol for alignment frags. We will delete this
21692 later if the alignment ends up empty. */
21693 switch (fragP
->fr_type
)
21696 case rs_align_test
:
21698 mapping_state_2 (MAP_DATA
, max_chars
);
21700 case rs_align_code
:
21701 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
21708 /* When we change sections we need to issue a new mapping symbol. */
21711 arm_elf_change_section (void)
21713 /* Link an unlinked unwind index table section to the .text section. */
21714 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
21715 && elf_linked_to_section (now_seg
) == NULL
)
21716 elf_linked_to_section (now_seg
) = text_section
;
21720 arm_elf_section_type (const char * str
, size_t len
)
21722 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
21723 return SHT_ARM_EXIDX
;
21728 /* Code to deal with unwinding tables. */
21730 static void add_unwind_adjustsp (offsetT
);
21732 /* Generate any deferred unwind frame offset. */
21735 flush_pending_unwind (void)
21739 offset
= unwind
.pending_offset
;
21740 unwind
.pending_offset
= 0;
21742 add_unwind_adjustsp (offset
);
21745 /* Add an opcode to this list for this function. Two-byte opcodes should
21746 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
21750 add_unwind_opcode (valueT op
, int length
)
21752 /* Add any deferred stack adjustment. */
21753 if (unwind
.pending_offset
)
21754 flush_pending_unwind ();
21756 unwind
.sp_restored
= 0;
21758 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
21760 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
21761 if (unwind
.opcodes
)
21762 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
21763 unwind
.opcode_alloc
);
21765 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
21770 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
21772 unwind
.opcode_count
++;
21776 /* Add unwind opcodes to adjust the stack pointer. */
21779 add_unwind_adjustsp (offsetT offset
)
21783 if (offset
> 0x200)
21785 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
21790 /* Long form: 0xb2, uleb128. */
21791 /* This might not fit in a word so add the individual bytes,
21792 remembering the list is built in reverse order. */
21793 o
= (valueT
) ((offset
- 0x204) >> 2);
21795 add_unwind_opcode (0, 1);
21797 /* Calculate the uleb128 encoding of the offset. */
21801 bytes
[n
] = o
& 0x7f;
21807 /* Add the insn. */
21809 add_unwind_opcode (bytes
[n
- 1], 1);
21810 add_unwind_opcode (0xb2, 1);
21812 else if (offset
> 0x100)
21814 /* Two short opcodes. */
21815 add_unwind_opcode (0x3f, 1);
21816 op
= (offset
- 0x104) >> 2;
21817 add_unwind_opcode (op
, 1);
21819 else if (offset
> 0)
21821 /* Short opcode. */
21822 op
= (offset
- 4) >> 2;
21823 add_unwind_opcode (op
, 1);
21825 else if (offset
< 0)
21828 while (offset
> 0x100)
21830 add_unwind_opcode (0x7f, 1);
21833 op
= ((offset
- 4) >> 2) | 0x40;
21834 add_unwind_opcode (op
, 1);
21838 /* Finish the list of unwind opcodes for this function. */
21840 finish_unwind_opcodes (void)
21844 if (unwind
.fp_used
)
21846 /* Adjust sp as necessary. */
21847 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
21848 flush_pending_unwind ();
21850 /* After restoring sp from the frame pointer. */
21851 op
= 0x90 | unwind
.fp_reg
;
21852 add_unwind_opcode (op
, 1);
21855 flush_pending_unwind ();
21859 /* Start an exception table entry. If idx is nonzero this is an index table
21863 start_unwind_section (const segT text_seg
, int idx
)
21865 const char * text_name
;
21866 const char * prefix
;
21867 const char * prefix_once
;
21868 const char * group_name
;
21872 size_t sec_name_len
;
21879 prefix
= ELF_STRING_ARM_unwind
;
21880 prefix_once
= ELF_STRING_ARM_unwind_once
;
21881 type
= SHT_ARM_EXIDX
;
21885 prefix
= ELF_STRING_ARM_unwind_info
;
21886 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
21887 type
= SHT_PROGBITS
;
21890 text_name
= segment_name (text_seg
);
21891 if (streq (text_name
, ".text"))
21894 if (strncmp (text_name
, ".gnu.linkonce.t.",
21895 strlen (".gnu.linkonce.t.")) == 0)
21897 prefix
= prefix_once
;
21898 text_name
+= strlen (".gnu.linkonce.t.");
21901 prefix_len
= strlen (prefix
);
21902 text_len
= strlen (text_name
);
21903 sec_name_len
= prefix_len
+ text_len
;
21904 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
21905 memcpy (sec_name
, prefix
, prefix_len
);
21906 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
21907 sec_name
[prefix_len
+ text_len
] = '\0';
21913 /* Handle COMDAT group. */
21914 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
21916 group_name
= elf_group_name (text_seg
);
21917 if (group_name
== NULL
)
21919 as_bad (_("Group section `%s' has no group signature"),
21920 segment_name (text_seg
));
21921 ignore_rest_of_line ();
21924 flags
|= SHF_GROUP
;
21928 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
21930 /* Set the section link for index tables. */
21932 elf_linked_to_section (now_seg
) = text_seg
;
21936 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
21937 personality routine data. Returns zero, or the index table value for
21938 an inline entry. */
21941 create_unwind_entry (int have_data
)
21946 /* The current word of data. */
21948 /* The number of bytes left in this word. */
21951 finish_unwind_opcodes ();
21953 /* Remember the current text section. */
21954 unwind
.saved_seg
= now_seg
;
21955 unwind
.saved_subseg
= now_subseg
;
21957 start_unwind_section (now_seg
, 0);
21959 if (unwind
.personality_routine
== NULL
)
21961 if (unwind
.personality_index
== -2)
21964 as_bad (_("handlerdata in cantunwind frame"));
21965 return 1; /* EXIDX_CANTUNWIND. */
21968 /* Use a default personality routine if none is specified. */
21969 if (unwind
.personality_index
== -1)
21971 if (unwind
.opcode_count
> 3)
21972 unwind
.personality_index
= 1;
21974 unwind
.personality_index
= 0;
21977 /* Space for the personality routine entry. */
21978 if (unwind
.personality_index
== 0)
21980 if (unwind
.opcode_count
> 3)
21981 as_bad (_("too many unwind opcodes for personality routine 0"));
21985 /* All the data is inline in the index table. */
21988 while (unwind
.opcode_count
> 0)
21990 unwind
.opcode_count
--;
21991 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21995 /* Pad with "finish" opcodes. */
21997 data
= (data
<< 8) | 0xb0;
22004 /* We get two opcodes "free" in the first word. */
22005 size
= unwind
.opcode_count
- 2;
22009 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22010 if (unwind
.personality_index
!= -1)
22012 as_bad (_("attempt to recreate an unwind entry"));
22016 /* An extra byte is required for the opcode count. */
22017 size
= unwind
.opcode_count
+ 1;
22020 size
= (size
+ 3) >> 2;
22022 as_bad (_("too many unwind opcodes"));
22024 frag_align (2, 0, 0);
22025 record_alignment (now_seg
, 2);
22026 unwind
.table_entry
= expr_build_dot ();
22028 /* Allocate the table entry. */
22029 ptr
= frag_more ((size
<< 2) + 4);
22030 /* PR 13449: Zero the table entries in case some of them are not used. */
22031 memset (ptr
, 0, (size
<< 2) + 4);
22032 where
= frag_now_fix () - ((size
<< 2) + 4);
22034 switch (unwind
.personality_index
)
22037 /* ??? Should this be a PLT generating relocation? */
22038 /* Custom personality routine. */
22039 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22040 BFD_RELOC_ARM_PREL31
);
22045 /* Set the first byte to the number of additional words. */
22046 data
= size
> 0 ? size
- 1 : 0;
22050 /* ABI defined personality routines. */
22052 /* Three opcodes bytes are packed into the first word. */
22059 /* The size and first two opcode bytes go in the first word. */
22060 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22065 /* Should never happen. */
22069 /* Pack the opcodes into words (MSB first), reversing the list at the same
22071 while (unwind
.opcode_count
> 0)
22075 md_number_to_chars (ptr
, data
, 4);
22080 unwind
.opcode_count
--;
22082 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22085 /* Finish off the last word. */
22088 /* Pad with "finish" opcodes. */
22090 data
= (data
<< 8) | 0xb0;
22092 md_number_to_chars (ptr
, data
, 4);
22097 /* Add an empty descriptor if there is no user-specified data. */
22098 ptr
= frag_more (4);
22099 md_number_to_chars (ptr
, 0, 4);
22106 /* Initialize the DWARF-2 unwind information for this procedure. */
22109 tc_arm_frame_initial_instructions (void)
22111 cfi_add_CFA_def_cfa (REG_SP
, 0);
22113 #endif /* OBJ_ELF */
22115 /* Convert REGNAME to a DWARF-2 register number. */
22118 tc_arm_regname_to_dw2regnum (char *regname
)
22120 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22124 /* PR 16694: Allow VFP registers as well. */
22125 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22129 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22138 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22142 exp
.X_op
= O_secrel
;
22143 exp
.X_add_symbol
= symbol
;
22144 exp
.X_add_number
= 0;
22145 emit_expr (&exp
, size
);
22149 /* MD interface: Symbol and relocation handling. */
22151 /* Return the address within the segment that a PC-relative fixup is
22152 relative to. For ARM, PC-relative fixups applied to instructions
22153 are generally relative to the location of the fixup plus 8 bytes.
22154 Thumb branches are offset by 4, and Thumb loads relative to PC
22155 require special handling. */
22158 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22160 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22162 /* If this is pc-relative and we are going to emit a relocation
22163 then we just want to put out any pipeline compensation that the linker
22164 will need. Otherwise we want to use the calculated base.
22165 For WinCE we skip the bias for externals as well, since this
22166 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22168 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22169 || (arm_force_relocation (fixP
)
22171 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22177 switch (fixP
->fx_r_type
)
22179 /* PC relative addressing on the Thumb is slightly odd as the
22180 bottom two bits of the PC are forced to zero for the
22181 calculation. This happens *after* application of the
22182 pipeline offset. However, Thumb adrl already adjusts for
22183 this, so we need not do it again. */
22184 case BFD_RELOC_ARM_THUMB_ADD
:
22187 case BFD_RELOC_ARM_THUMB_OFFSET
:
22188 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22189 case BFD_RELOC_ARM_T32_ADD_PC12
:
22190 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22191 return (base
+ 4) & ~3;
22193 /* Thumb branches are simply offset by +4. */
22194 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22195 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22196 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22197 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22198 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22201 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22203 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22204 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22205 && ARM_IS_FUNC (fixP
->fx_addsy
)
22206 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22207 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22210 /* BLX is like branches above, but forces the low two bits of PC to
22212 case BFD_RELOC_THUMB_PCREL_BLX
:
22214 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22215 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22216 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22217 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22218 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22219 return (base
+ 4) & ~3;
22221 /* ARM mode branches are offset by +8. However, the Windows CE
22222 loader expects the relocation not to take this into account. */
22223 case BFD_RELOC_ARM_PCREL_BLX
:
22225 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22226 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22227 && ARM_IS_FUNC (fixP
->fx_addsy
)
22228 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22229 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22232 case BFD_RELOC_ARM_PCREL_CALL
:
22234 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22235 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22236 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22237 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22238 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22241 case BFD_RELOC_ARM_PCREL_BRANCH
:
22242 case BFD_RELOC_ARM_PCREL_JUMP
:
22243 case BFD_RELOC_ARM_PLT32
:
22245 /* When handling fixups immediately, because we have already
22246 discovered the value of a symbol, or the address of the frag involved
22247 we must account for the offset by +8, as the OS loader will never see the reloc.
22248 see fixup_segment() in write.c
22249 The S_IS_EXTERNAL test handles the case of global symbols.
22250 Those need the calculated base, not just the pipe compensation the linker will need. */
22252 && fixP
->fx_addsy
!= NULL
22253 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22254 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22262 /* ARM mode loads relative to PC are also offset by +8. Unlike
22263 branches, the Windows CE loader *does* expect the relocation
22264 to take this into account. */
22265 case BFD_RELOC_ARM_OFFSET_IMM
:
22266 case BFD_RELOC_ARM_OFFSET_IMM8
:
22267 case BFD_RELOC_ARM_HWLITERAL
:
22268 case BFD_RELOC_ARM_LITERAL
:
22269 case BFD_RELOC_ARM_CP_OFF_IMM
:
22273 /* Other PC-relative relocations are un-offset. */
22279 static bfd_boolean flag_warn_syms
= TRUE
;
22282 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22284 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22285 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22286 does mean that the resulting code might be very confusing to the reader.
22287 Also this warning can be triggered if the user omits an operand before
22288 an immediate address, eg:
22292 GAS treats this as an assignment of the value of the symbol foo to a
22293 symbol LDR, and so (without this code) it will not issue any kind of
22294 warning or error message.
22296 Note - ARM instructions are case-insensitive but the strings in the hash
22297 table are all stored in lower case, so we must first ensure that name is
22299 if (flag_warn_syms
&& arm_ops_hsh
)
22301 char * nbuf
= strdup (name
);
22304 for (p
= nbuf
; *p
; p
++)
22306 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22308 static struct hash_control
* already_warned
= NULL
;
22310 if (already_warned
== NULL
)
22311 already_warned
= hash_new ();
22312 /* Only warn about the symbol once. To keep the code
22313 simple we let hash_insert do the lookup for us. */
22314 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22315 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22324 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22325 Otherwise we have no need to default values of symbols. */
22328 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22331 if (name
[0] == '_' && name
[1] == 'G'
22332 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22336 if (symbol_find (name
))
22337 as_bad (_("GOT already in the symbol table"));
22339 GOT_symbol
= symbol_new (name
, undefined_section
,
22340 (valueT
) 0, & zero_address_frag
);
22350 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22351 computed as two separate immediate values, added together. We
22352 already know that this value cannot be computed by just one ARM
22355 static unsigned int
22356 validate_immediate_twopart (unsigned int val
,
22357 unsigned int * highpart
)
22362 for (i
= 0; i
< 32; i
+= 2)
22363 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22369 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22371 else if (a
& 0xff0000)
22373 if (a
& 0xff000000)
22375 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22379 gas_assert (a
& 0xff000000);
22380 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22383 return (a
& 0xff) | (i
<< 7);
22390 validate_offset_imm (unsigned int val
, int hwse
)
22392 if ((hwse
&& val
> 255) || val
> 4095)
22397 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22398 negative immediate constant by altering the instruction. A bit of
22403 by inverting the second operand, and
22406 by negating the second operand. */
22409 negate_data_op (unsigned long * instruction
,
22410 unsigned long value
)
22413 unsigned long negated
, inverted
;
22415 negated
= encode_arm_immediate (-value
);
22416 inverted
= encode_arm_immediate (~value
);
22418 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22421 /* First negates. */
22422 case OPCODE_SUB
: /* ADD <-> SUB */
22423 new_inst
= OPCODE_ADD
;
22428 new_inst
= OPCODE_SUB
;
22432 case OPCODE_CMP
: /* CMP <-> CMN */
22433 new_inst
= OPCODE_CMN
;
22438 new_inst
= OPCODE_CMP
;
22442 /* Now Inverted ops. */
22443 case OPCODE_MOV
: /* MOV <-> MVN */
22444 new_inst
= OPCODE_MVN
;
22449 new_inst
= OPCODE_MOV
;
22453 case OPCODE_AND
: /* AND <-> BIC */
22454 new_inst
= OPCODE_BIC
;
22459 new_inst
= OPCODE_AND
;
22463 case OPCODE_ADC
: /* ADC <-> SBC */
22464 new_inst
= OPCODE_SBC
;
22469 new_inst
= OPCODE_ADC
;
22473 /* We cannot do anything. */
22478 if (value
== (unsigned) FAIL
)
22481 *instruction
&= OPCODE_MASK
;
22482 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
22486 /* Like negate_data_op, but for Thumb-2. */
22488 static unsigned int
22489 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
22493 unsigned int negated
, inverted
;
22495 negated
= encode_thumb32_immediate (-value
);
22496 inverted
= encode_thumb32_immediate (~value
);
22498 rd
= (*instruction
>> 8) & 0xf;
22499 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
22502 /* ADD <-> SUB. Includes CMP <-> CMN. */
22503 case T2_OPCODE_SUB
:
22504 new_inst
= T2_OPCODE_ADD
;
22508 case T2_OPCODE_ADD
:
22509 new_inst
= T2_OPCODE_SUB
;
22513 /* ORR <-> ORN. Includes MOV <-> MVN. */
22514 case T2_OPCODE_ORR
:
22515 new_inst
= T2_OPCODE_ORN
;
22519 case T2_OPCODE_ORN
:
22520 new_inst
= T2_OPCODE_ORR
;
22524 /* AND <-> BIC. TST has no inverted equivalent. */
22525 case T2_OPCODE_AND
:
22526 new_inst
= T2_OPCODE_BIC
;
22533 case T2_OPCODE_BIC
:
22534 new_inst
= T2_OPCODE_AND
;
22539 case T2_OPCODE_ADC
:
22540 new_inst
= T2_OPCODE_SBC
;
22544 case T2_OPCODE_SBC
:
22545 new_inst
= T2_OPCODE_ADC
;
22549 /* We cannot do anything. */
22554 if (value
== (unsigned int)FAIL
)
22557 *instruction
&= T2_OPCODE_MASK
;
22558 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
22562 /* Read a 32-bit thumb instruction from buf. */
22563 static unsigned long
22564 get_thumb32_insn (char * buf
)
22566 unsigned long insn
;
22567 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
22568 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22574 /* We usually want to set the low bit on the address of thumb function
22575 symbols. In particular .word foo - . should have the low bit set.
22576 Generic code tries to fold the difference of two symbols to
22577 a constant. Prevent this and force a relocation when the first symbols
22578 is a thumb function. */
22581 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
22583 if (op
== O_subtract
22584 && l
->X_op
== O_symbol
22585 && r
->X_op
== O_symbol
22586 && THUMB_IS_FUNC (l
->X_add_symbol
))
22588 l
->X_op
= O_subtract
;
22589 l
->X_op_symbol
= r
->X_add_symbol
;
22590 l
->X_add_number
-= r
->X_add_number
;
22594 /* Process as normal. */
22598 /* Encode Thumb2 unconditional branches and calls. The encoding
22599 for the 2 are identical for the immediate values. */
22602 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
22604 #define T2I1I2MASK ((1 << 13) | (1 << 11))
22607 addressT S
, I1
, I2
, lo
, hi
;
22609 S
= (value
>> 24) & 0x01;
22610 I1
= (value
>> 23) & 0x01;
22611 I2
= (value
>> 22) & 0x01;
22612 hi
= (value
>> 12) & 0x3ff;
22613 lo
= (value
>> 1) & 0x7ff;
22614 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22615 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22616 newval
|= (S
<< 10) | hi
;
22617 newval2
&= ~T2I1I2MASK
;
22618 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
22619 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22620 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22624 md_apply_fix (fixS
* fixP
,
22628 offsetT value
= * valP
;
22630 unsigned int newimm
;
22631 unsigned long temp
;
22633 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
22635 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
22637 /* Note whether this will delete the relocation. */
22639 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
22642 /* On a 64-bit host, silently truncate 'value' to 32 bits for
22643 consistency with the behaviour on 32-bit hosts. Remember value
22645 value
&= 0xffffffff;
22646 value
^= 0x80000000;
22647 value
-= 0x80000000;
22650 fixP
->fx_addnumber
= value
;
22652 /* Same treatment for fixP->fx_offset. */
22653 fixP
->fx_offset
&= 0xffffffff;
22654 fixP
->fx_offset
^= 0x80000000;
22655 fixP
->fx_offset
-= 0x80000000;
22657 switch (fixP
->fx_r_type
)
22659 case BFD_RELOC_NONE
:
22660 /* This will need to go in the object file. */
22664 case BFD_RELOC_ARM_IMMEDIATE
:
22665 /* We claim that this fixup has been processed here,
22666 even if in fact we generate an error because we do
22667 not have a reloc for it, so tc_gen_reloc will reject it. */
22670 if (fixP
->fx_addsy
)
22672 const char *msg
= 0;
22674 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22675 msg
= _("undefined symbol %s used as an immediate value");
22676 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22677 msg
= _("symbol %s is in a different section");
22678 else if (S_IS_WEAK (fixP
->fx_addsy
))
22679 msg
= _("symbol %s is weak and may be overridden later");
22683 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22684 msg
, S_GET_NAME (fixP
->fx_addsy
));
22689 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22691 /* If the offset is negative, we should use encoding A2 for ADR. */
22692 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
22693 newimm
= negate_data_op (&temp
, value
);
22696 newimm
= encode_arm_immediate (value
);
22698 /* If the instruction will fail, see if we can fix things up by
22699 changing the opcode. */
22700 if (newimm
== (unsigned int) FAIL
)
22701 newimm
= negate_data_op (&temp
, value
);
22704 if (newimm
== (unsigned int) FAIL
)
22706 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22707 _("invalid constant (%lx) after fixup"),
22708 (unsigned long) value
);
22712 newimm
|= (temp
& 0xfffff000);
22713 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22716 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
22718 unsigned int highpart
= 0;
22719 unsigned int newinsn
= 0xe1a00000; /* nop. */
22721 if (fixP
->fx_addsy
)
22723 const char *msg
= 0;
22725 if (! S_IS_DEFINED (fixP
->fx_addsy
))
22726 msg
= _("undefined symbol %s used as an immediate value");
22727 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22728 msg
= _("symbol %s is in a different section");
22729 else if (S_IS_WEAK (fixP
->fx_addsy
))
22730 msg
= _("symbol %s is weak and may be overridden later");
22734 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22735 msg
, S_GET_NAME (fixP
->fx_addsy
));
22740 newimm
= encode_arm_immediate (value
);
22741 temp
= md_chars_to_number (buf
, INSN_SIZE
);
22743 /* If the instruction will fail, see if we can fix things up by
22744 changing the opcode. */
22745 if (newimm
== (unsigned int) FAIL
22746 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
22748 /* No ? OK - try using two ADD instructions to generate
22750 newimm
= validate_immediate_twopart (value
, & highpart
);
22752 /* Yes - then make sure that the second instruction is
22754 if (newimm
!= (unsigned int) FAIL
)
22756 /* Still No ? Try using a negated value. */
22757 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
22758 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
22759 /* Otherwise - give up. */
22762 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22763 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
22768 /* Replace the first operand in the 2nd instruction (which
22769 is the PC) with the destination register. We have
22770 already added in the PC in the first instruction and we
22771 do not want to do it again. */
22772 newinsn
&= ~ 0xf0000;
22773 newinsn
|= ((newinsn
& 0x0f000) << 4);
22776 newimm
|= (temp
& 0xfffff000);
22777 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
22779 highpart
|= (newinsn
& 0xfffff000);
22780 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
22784 case BFD_RELOC_ARM_OFFSET_IMM
:
22785 if (!fixP
->fx_done
&& seg
->use_rela_p
)
22788 case BFD_RELOC_ARM_LITERAL
:
22794 if (validate_offset_imm (value
, 0) == FAIL
)
22796 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
22797 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22798 _("invalid literal constant: pool needs to be closer"));
22800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22801 _("bad immediate value for offset (%ld)"),
22806 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22808 newval
&= 0xfffff000;
22811 newval
&= 0xff7ff000;
22812 newval
|= value
| (sign
? INDEX_UP
: 0);
22814 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22817 case BFD_RELOC_ARM_OFFSET_IMM8
:
22818 case BFD_RELOC_ARM_HWLITERAL
:
22824 if (validate_offset_imm (value
, 1) == FAIL
)
22826 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
22827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22828 _("invalid literal constant: pool needs to be closer"));
22830 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22831 _("bad immediate value for 8-bit offset (%ld)"),
22836 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22838 newval
&= 0xfffff0f0;
22841 newval
&= 0xff7ff0f0;
22842 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
22844 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22847 case BFD_RELOC_ARM_T32_OFFSET_U8
:
22848 if (value
< 0 || value
> 1020 || value
% 4 != 0)
22849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22850 _("bad immediate value for offset (%ld)"), (long) value
);
22853 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
22855 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
22858 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22859 /* This is a complicated relocation used for all varieties of Thumb32
22860 load/store instruction with immediate offset:
22862 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
22863 *4, optional writeback(W)
22864 (doubleword load/store)
22866 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
22867 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
22868 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
22869 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
22870 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
22872 Uppercase letters indicate bits that are already encoded at
22873 this point. Lowercase letters are our problem. For the
22874 second block of instructions, the secondary opcode nybble
22875 (bits 8..11) is present, and bit 23 is zero, even if this is
22876 a PC-relative operation. */
22877 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22879 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
22881 if ((newval
& 0xf0000000) == 0xe0000000)
22883 /* Doubleword load/store: 8-bit offset, scaled by 4. */
22885 newval
|= (1 << 23);
22888 if (value
% 4 != 0)
22890 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22891 _("offset not a multiple of 4"));
22897 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22898 _("offset out of range"));
22903 else if ((newval
& 0x000f0000) == 0x000f0000)
22905 /* PC-relative, 12-bit offset. */
22907 newval
|= (1 << 23);
22912 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22913 _("offset out of range"));
22918 else if ((newval
& 0x00000100) == 0x00000100)
22920 /* Writeback: 8-bit, +/- offset. */
22922 newval
|= (1 << 9);
22927 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22928 _("offset out of range"));
22933 else if ((newval
& 0x00000f00) == 0x00000e00)
22935 /* T-instruction: positive 8-bit offset. */
22936 if (value
< 0 || value
> 0xff)
22938 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22939 _("offset out of range"));
22947 /* Positive 12-bit or negative 8-bit offset. */
22951 newval
|= (1 << 23);
22961 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22962 _("offset out of range"));
22969 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
22970 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
22973 case BFD_RELOC_ARM_SHIFT_IMM
:
22974 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22975 if (((unsigned long) value
) > 32
22977 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
22979 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22980 _("shift expression is too large"));
22985 /* Shifts of zero must be done as lsl. */
22987 else if (value
== 32)
22989 newval
&= 0xfffff07f;
22990 newval
|= (value
& 0x1f) << 7;
22991 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22994 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22995 case BFD_RELOC_ARM_T32_ADD_IMM
:
22996 case BFD_RELOC_ARM_T32_IMM12
:
22997 case BFD_RELOC_ARM_T32_ADD_PC12
:
22998 /* We claim that this fixup has been processed here,
22999 even if in fact we generate an error because we do
23000 not have a reloc for it, so tc_gen_reloc will reject it. */
23004 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23006 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23007 _("undefined symbol %s used as an immediate value"),
23008 S_GET_NAME (fixP
->fx_addsy
));
23012 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23014 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23017 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23018 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23020 newimm
= encode_thumb32_immediate (value
);
23021 if (newimm
== (unsigned int) FAIL
)
23022 newimm
= thumb32_negate_data_op (&newval
, value
);
23024 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
23025 && newimm
== (unsigned int) FAIL
)
23027 /* Turn add/sum into addw/subw. */
23028 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23029 newval
= (newval
& 0xfeffffff) | 0x02000000;
23030 /* No flat 12-bit imm encoding for addsw/subsw. */
23031 if ((newval
& 0x00100000) == 0)
23033 /* 12 bit immediate for addw/subw. */
23037 newval
^= 0x00a00000;
23040 newimm
= (unsigned int) FAIL
;
23046 if (newimm
== (unsigned int)FAIL
)
23048 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23049 _("invalid constant (%lx) after fixup"),
23050 (unsigned long) value
);
23054 newval
|= (newimm
& 0x800) << 15;
23055 newval
|= (newimm
& 0x700) << 4;
23056 newval
|= (newimm
& 0x0ff);
23058 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23059 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23062 case BFD_RELOC_ARM_SMC
:
23063 if (((unsigned long) value
) > 0xffff)
23064 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23065 _("invalid smc expression"));
23066 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23067 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23068 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23071 case BFD_RELOC_ARM_HVC
:
23072 if (((unsigned long) value
) > 0xffff)
23073 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23074 _("invalid hvc expression"));
23075 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23076 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23077 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23080 case BFD_RELOC_ARM_SWI
:
23081 if (fixP
->tc_fix_data
!= 0)
23083 if (((unsigned long) value
) > 0xff)
23084 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23085 _("invalid swi expression"));
23086 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23088 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23092 if (((unsigned long) value
) > 0x00ffffff)
23093 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23094 _("invalid swi expression"));
23095 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23097 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23101 case BFD_RELOC_ARM_MULTI
:
23102 if (((unsigned long) value
) > 0xffff)
23103 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23104 _("invalid expression in load/store multiple"));
23105 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23106 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23110 case BFD_RELOC_ARM_PCREL_CALL
:
23112 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23114 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23115 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23116 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23117 /* Flip the bl to blx. This is a simple flip
23118 bit here because we generate PCREL_CALL for
23119 unconditional bls. */
23121 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23122 newval
= newval
| 0x10000000;
23123 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23129 goto arm_branch_common
;
23131 case BFD_RELOC_ARM_PCREL_JUMP
:
23132 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23134 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23135 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23136 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23138 /* This would map to a bl<cond>, b<cond>,
23139 b<always> to a Thumb function. We
23140 need to force a relocation for this particular
23142 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23146 case BFD_RELOC_ARM_PLT32
:
23148 case BFD_RELOC_ARM_PCREL_BRANCH
:
23150 goto arm_branch_common
;
23152 case BFD_RELOC_ARM_PCREL_BLX
:
23155 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23157 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23158 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23159 && ARM_IS_FUNC (fixP
->fx_addsy
))
23161 /* Flip the blx to a bl and warn. */
23162 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23163 newval
= 0xeb000000;
23164 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23165 _("blx to '%s' an ARM ISA state function changed to bl"),
23167 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23173 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23174 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23178 /* We are going to store value (shifted right by two) in the
23179 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23180 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23181 also be be clear. */
23183 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23184 _("misaligned branch destination"));
23185 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23186 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23187 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23189 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23191 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23192 newval
|= (value
>> 2) & 0x00ffffff;
23193 /* Set the H bit on BLX instructions. */
23197 newval
|= 0x01000000;
23199 newval
&= ~0x01000000;
23201 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23205 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23206 /* CBZ can only branch forward. */
23208 /* Attempts to use CBZ to branch to the next instruction
23209 (which, strictly speaking, are prohibited) will be turned into
23212 FIXME: It may be better to remove the instruction completely and
23213 perform relaxation. */
23216 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23217 newval
= 0xbf00; /* NOP encoding T1 */
23218 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23223 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23225 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23227 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23228 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23229 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23234 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23235 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23236 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23238 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23240 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23241 newval
|= (value
& 0x1ff) >> 1;
23242 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23246 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23247 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23250 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23252 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23253 newval
|= (value
& 0xfff) >> 1;
23254 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23258 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23260 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23261 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23262 && ARM_IS_FUNC (fixP
->fx_addsy
)
23263 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23265 /* Force a relocation for a branch 20 bits wide. */
23268 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23270 _("conditional branch out of range"));
23272 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23275 addressT S
, J1
, J2
, lo
, hi
;
23277 S
= (value
& 0x00100000) >> 20;
23278 J2
= (value
& 0x00080000) >> 19;
23279 J1
= (value
& 0x00040000) >> 18;
23280 hi
= (value
& 0x0003f000) >> 12;
23281 lo
= (value
& 0x00000ffe) >> 1;
23283 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23284 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23285 newval
|= (S
<< 10) | hi
;
23286 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23287 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23288 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23292 case BFD_RELOC_THUMB_PCREL_BLX
:
23293 /* If there is a blx from a thumb state function to
23294 another thumb function flip this to a bl and warn
23298 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23299 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23300 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23302 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23303 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23304 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23306 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23307 newval
= newval
| 0x1000;
23308 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23309 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23314 goto thumb_bl_common
;
23316 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23317 /* A bl from Thumb state ISA to an internal ARM state function
23318 is converted to a blx. */
23320 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23321 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23322 && ARM_IS_FUNC (fixP
->fx_addsy
)
23323 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23325 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23326 newval
= newval
& ~0x1000;
23327 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23328 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23334 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23335 /* For a BLX instruction, make sure that the relocation is rounded up
23336 to a word boundary. This follows the semantics of the instruction
23337 which specifies that bit 1 of the target address will come from bit
23338 1 of the base address. */
23339 value
= (value
+ 3) & ~ 3;
23342 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23343 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23344 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23347 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23349 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23350 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23351 else if ((value
& ~0x1ffffff)
23352 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23354 _("Thumb2 branch out of range"));
23357 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23358 encode_thumb2_b_bl_offset (buf
, value
);
23362 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23363 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23364 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23366 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23367 encode_thumb2_b_bl_offset (buf
, value
);
23372 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23377 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23378 md_number_to_chars (buf
, value
, 2);
23382 case BFD_RELOC_ARM_TLS_CALL
:
23383 case BFD_RELOC_ARM_THM_TLS_CALL
:
23384 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23385 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23386 case BFD_RELOC_ARM_TLS_GOTDESC
:
23387 case BFD_RELOC_ARM_TLS_GD32
:
23388 case BFD_RELOC_ARM_TLS_LE32
:
23389 case BFD_RELOC_ARM_TLS_IE32
:
23390 case BFD_RELOC_ARM_TLS_LDM32
:
23391 case BFD_RELOC_ARM_TLS_LDO32
:
23392 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
23395 case BFD_RELOC_ARM_GOT32
:
23396 case BFD_RELOC_ARM_GOTOFF
:
23399 case BFD_RELOC_ARM_GOT_PREL
:
23400 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23401 md_number_to_chars (buf
, value
, 4);
23404 case BFD_RELOC_ARM_TARGET2
:
23405 /* TARGET2 is not partial-inplace, so we need to write the
23406 addend here for REL targets, because it won't be written out
23407 during reloc processing later. */
23408 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23409 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
23413 case BFD_RELOC_RVA
:
23415 case BFD_RELOC_ARM_TARGET1
:
23416 case BFD_RELOC_ARM_ROSEGREL32
:
23417 case BFD_RELOC_ARM_SBREL32
:
23418 case BFD_RELOC_32_PCREL
:
23420 case BFD_RELOC_32_SECREL
:
23422 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23424 /* For WinCE we only do this for pcrel fixups. */
23425 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
23427 md_number_to_chars (buf
, value
, 4);
23431 case BFD_RELOC_ARM_PREL31
:
23432 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23434 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
23435 if ((value
^ (value
>> 1)) & 0x40000000)
23437 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23438 _("rel31 relocation overflow"));
23440 newval
|= value
& 0x7fffffff;
23441 md_number_to_chars (buf
, newval
, 4);
23446 case BFD_RELOC_ARM_CP_OFF_IMM
:
23447 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
23448 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
23449 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23451 newval
= get_thumb32_insn (buf
);
23452 if ((newval
& 0x0f200f00) == 0x0d000900)
23454 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
23455 has permitted values that are multiples of 2, in the range 0
23457 if (value
< -510 || value
> 510 || (value
& 1))
23458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23459 _("co-processor offset out of range"));
23461 else if (value
< -1023 || value
> 1023 || (value
& 3))
23462 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23463 _("co-processor offset out of range"));
23468 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23469 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23470 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23472 newval
= get_thumb32_insn (buf
);
23474 newval
&= 0xffffff00;
23477 newval
&= 0xff7fff00;
23478 if ((newval
& 0x0f200f00) == 0x0d000900)
23480 /* This is a fp16 vstr/vldr.
23482 It requires the immediate offset in the instruction is shifted
23483 left by 1 to be a half-word offset.
23485 Here, left shift by 1 first, and later right shift by 2
23486 should get the right offset. */
23489 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
23491 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23492 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
23493 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23495 put_thumb32_insn (buf
, newval
);
23498 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
23499 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
23500 if (value
< -255 || value
> 255)
23501 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23502 _("co-processor offset out of range"));
23504 goto cp_off_common
;
23506 case BFD_RELOC_ARM_THUMB_OFFSET
:
23507 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23508 /* Exactly what ranges, and where the offset is inserted depends
23509 on the type of instruction, we can establish this from the
23511 switch (newval
>> 12)
23513 case 4: /* PC load. */
23514 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
23515 forced to zero for these loads; md_pcrel_from has already
23516 compensated for this. */
23518 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23519 _("invalid offset, target not word aligned (0x%08lX)"),
23520 (((unsigned long) fixP
->fx_frag
->fr_address
23521 + (unsigned long) fixP
->fx_where
) & ~3)
23522 + (unsigned long) value
);
23524 if (value
& ~0x3fc)
23525 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23526 _("invalid offset, value too big (0x%08lX)"),
23529 newval
|= value
>> 2;
23532 case 9: /* SP load/store. */
23533 if (value
& ~0x3fc)
23534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23535 _("invalid offset, value too big (0x%08lX)"),
23537 newval
|= value
>> 2;
23540 case 6: /* Word load/store. */
23542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23543 _("invalid offset, value too big (0x%08lX)"),
23545 newval
|= value
<< 4; /* 6 - 2. */
23548 case 7: /* Byte load/store. */
23550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23551 _("invalid offset, value too big (0x%08lX)"),
23553 newval
|= value
<< 6;
23556 case 8: /* Halfword load/store. */
23558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23559 _("invalid offset, value too big (0x%08lX)"),
23561 newval
|= value
<< 5; /* 6 - 1. */
23565 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23566 "Unable to process relocation for thumb opcode: %lx",
23567 (unsigned long) newval
);
23570 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23573 case BFD_RELOC_ARM_THUMB_ADD
:
23574 /* This is a complicated relocation, since we use it for all of
23575 the following immediate relocations:
23579 9bit ADD/SUB SP word-aligned
23580 10bit ADD PC/SP word-aligned
23582 The type of instruction being processed is encoded in the
23589 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23591 int rd
= (newval
>> 4) & 0xf;
23592 int rs
= newval
& 0xf;
23593 int subtract
= !!(newval
& 0x8000);
23595 /* Check for HI regs, only very restricted cases allowed:
23596 Adjusting SP, and using PC or SP to get an address. */
23597 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
23598 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
23599 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23600 _("invalid Hi register with immediate"));
23602 /* If value is negative, choose the opposite instruction. */
23606 subtract
= !subtract
;
23608 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23609 _("immediate value out of range"));
23614 if (value
& ~0x1fc)
23615 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23616 _("invalid immediate for stack address calculation"));
23617 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
23618 newval
|= value
>> 2;
23620 else if (rs
== REG_PC
|| rs
== REG_SP
)
23622 /* PR gas/18541. If the addition is for a defined symbol
23623 within range of an ADR instruction then accept it. */
23626 && fixP
->fx_addsy
!= NULL
)
23630 if (! S_IS_DEFINED (fixP
->fx_addsy
)
23631 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
23632 || S_IS_WEAK (fixP
->fx_addsy
))
23634 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23635 _("address calculation needs a strongly defined nearby symbol"));
23639 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
23641 /* Round up to the next 4-byte boundary. */
23646 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
23650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23651 _("symbol too far away"));
23661 if (subtract
|| value
& ~0x3fc)
23662 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23663 _("invalid immediate for address calculation (value = 0x%08lX)"),
23664 (unsigned long) (subtract
? - value
: value
));
23665 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
23667 newval
|= value
>> 2;
23672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23673 _("immediate value out of range"));
23674 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
23675 newval
|= (rd
<< 8) | value
;
23680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23681 _("immediate value out of range"));
23682 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
23683 newval
|= rd
| (rs
<< 3) | (value
<< 6);
23686 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23689 case BFD_RELOC_ARM_THUMB_IMM
:
23690 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23691 if (value
< 0 || value
> 255)
23692 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23693 _("invalid immediate: %ld is out of range"),
23696 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23699 case BFD_RELOC_ARM_THUMB_SHIFT
:
23700 /* 5bit shift value (0..32). LSL cannot take 32. */
23701 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
23702 temp
= newval
& 0xf800;
23703 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
23704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23705 _("invalid shift value: %ld"), (long) value
);
23706 /* Shifts of zero must be encoded as LSL. */
23708 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
23709 /* Shifts of 32 are encoded as zero. */
23710 else if (value
== 32)
23712 newval
|= value
<< 6;
23713 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23716 case BFD_RELOC_VTABLE_INHERIT
:
23717 case BFD_RELOC_VTABLE_ENTRY
:
23721 case BFD_RELOC_ARM_MOVW
:
23722 case BFD_RELOC_ARM_MOVT
:
23723 case BFD_RELOC_ARM_THUMB_MOVW
:
23724 case BFD_RELOC_ARM_THUMB_MOVT
:
23725 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23727 /* REL format relocations are limited to a 16-bit addend. */
23728 if (!fixP
->fx_done
)
23730 if (value
< -0x8000 || value
> 0x7fff)
23731 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23732 _("offset out of range"));
23734 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23735 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23740 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23741 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
23743 newval
= get_thumb32_insn (buf
);
23744 newval
&= 0xfbf08f00;
23745 newval
|= (value
& 0xf000) << 4;
23746 newval
|= (value
& 0x0800) << 15;
23747 newval
|= (value
& 0x0700) << 4;
23748 newval
|= (value
& 0x00ff);
23749 put_thumb32_insn (buf
, newval
);
23753 newval
= md_chars_to_number (buf
, 4);
23754 newval
&= 0xfff0f000;
23755 newval
|= value
& 0x0fff;
23756 newval
|= (value
& 0xf000) << 4;
23757 md_number_to_chars (buf
, newval
, 4);
23762 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
23763 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
23764 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
23765 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
23766 gas_assert (!fixP
->fx_done
);
23769 bfd_boolean is_mov
;
23770 bfd_vma encoded_addend
= value
;
23772 /* Check that addend can be encoded in instruction. */
23773 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
23774 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23775 _("the offset 0x%08lX is not representable"),
23776 (unsigned long) encoded_addend
);
23778 /* Extract the instruction. */
23779 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
23780 is_mov
= (insn
& 0xf800) == 0x2000;
23785 if (!seg
->use_rela_p
)
23786 insn
|= encoded_addend
;
23792 /* Extract the instruction. */
23793 /* Encoding is the following
23798 /* The following conditions must be true :
23803 rd
= (insn
>> 4) & 0xf;
23805 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
23806 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23807 _("Unable to process relocation for thumb opcode: %lx"),
23808 (unsigned long) insn
);
23810 /* Encode as ADD immediate8 thumb 1 code. */
23811 insn
= 0x3000 | (rd
<< 8);
23813 /* Place the encoded addend into the first 8 bits of the
23815 if (!seg
->use_rela_p
)
23816 insn
|= encoded_addend
;
23819 /* Update the instruction. */
23820 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
23824 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23825 case BFD_RELOC_ARM_ALU_PC_G0
:
23826 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23827 case BFD_RELOC_ARM_ALU_PC_G1
:
23828 case BFD_RELOC_ARM_ALU_PC_G2
:
23829 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23830 case BFD_RELOC_ARM_ALU_SB_G0
:
23831 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23832 case BFD_RELOC_ARM_ALU_SB_G1
:
23833 case BFD_RELOC_ARM_ALU_SB_G2
:
23834 gas_assert (!fixP
->fx_done
);
23835 if (!seg
->use_rela_p
)
23838 bfd_vma encoded_addend
;
23839 bfd_vma addend_abs
= abs (value
);
23841 /* Check that the absolute value of the addend can be
23842 expressed as an 8-bit constant plus a rotation. */
23843 encoded_addend
= encode_arm_immediate (addend_abs
);
23844 if (encoded_addend
== (unsigned int) FAIL
)
23845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23846 _("the offset 0x%08lX is not representable"),
23847 (unsigned long) addend_abs
);
23849 /* Extract the instruction. */
23850 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23852 /* If the addend is positive, use an ADD instruction.
23853 Otherwise use a SUB. Take care not to destroy the S bit. */
23854 insn
&= 0xff1fffff;
23860 /* Place the encoded addend into the first 12 bits of the
23862 insn
&= 0xfffff000;
23863 insn
|= encoded_addend
;
23865 /* Update the instruction. */
23866 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23870 case BFD_RELOC_ARM_LDR_PC_G0
:
23871 case BFD_RELOC_ARM_LDR_PC_G1
:
23872 case BFD_RELOC_ARM_LDR_PC_G2
:
23873 case BFD_RELOC_ARM_LDR_SB_G0
:
23874 case BFD_RELOC_ARM_LDR_SB_G1
:
23875 case BFD_RELOC_ARM_LDR_SB_G2
:
23876 gas_assert (!fixP
->fx_done
);
23877 if (!seg
->use_rela_p
)
23880 bfd_vma addend_abs
= abs (value
);
23882 /* Check that the absolute value of the addend can be
23883 encoded in 12 bits. */
23884 if (addend_abs
>= 0x1000)
23885 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23886 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
23887 (unsigned long) addend_abs
);
23889 /* Extract the instruction. */
23890 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23892 /* If the addend is negative, clear bit 23 of the instruction.
23893 Otherwise set it. */
23895 insn
&= ~(1 << 23);
23899 /* Place the absolute value of the addend into the first 12 bits
23900 of the instruction. */
23901 insn
&= 0xfffff000;
23902 insn
|= addend_abs
;
23904 /* Update the instruction. */
23905 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23909 case BFD_RELOC_ARM_LDRS_PC_G0
:
23910 case BFD_RELOC_ARM_LDRS_PC_G1
:
23911 case BFD_RELOC_ARM_LDRS_PC_G2
:
23912 case BFD_RELOC_ARM_LDRS_SB_G0
:
23913 case BFD_RELOC_ARM_LDRS_SB_G1
:
23914 case BFD_RELOC_ARM_LDRS_SB_G2
:
23915 gas_assert (!fixP
->fx_done
);
23916 if (!seg
->use_rela_p
)
23919 bfd_vma addend_abs
= abs (value
);
23921 /* Check that the absolute value of the addend can be
23922 encoded in 8 bits. */
23923 if (addend_abs
>= 0x100)
23924 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23925 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
23926 (unsigned long) addend_abs
);
23928 /* Extract the instruction. */
23929 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23931 /* If the addend is negative, clear bit 23 of the instruction.
23932 Otherwise set it. */
23934 insn
&= ~(1 << 23);
23938 /* Place the first four bits of the absolute value of the addend
23939 into the first 4 bits of the instruction, and the remaining
23940 four into bits 8 .. 11. */
23941 insn
&= 0xfffff0f0;
23942 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
23944 /* Update the instruction. */
23945 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23949 case BFD_RELOC_ARM_LDC_PC_G0
:
23950 case BFD_RELOC_ARM_LDC_PC_G1
:
23951 case BFD_RELOC_ARM_LDC_PC_G2
:
23952 case BFD_RELOC_ARM_LDC_SB_G0
:
23953 case BFD_RELOC_ARM_LDC_SB_G1
:
23954 case BFD_RELOC_ARM_LDC_SB_G2
:
23955 gas_assert (!fixP
->fx_done
);
23956 if (!seg
->use_rela_p
)
23959 bfd_vma addend_abs
= abs (value
);
23961 /* Check that the absolute value of the addend is a multiple of
23962 four and, when divided by four, fits in 8 bits. */
23963 if (addend_abs
& 0x3)
23964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23965 _("bad offset 0x%08lX (must be word-aligned)"),
23966 (unsigned long) addend_abs
);
23968 if ((addend_abs
>> 2) > 0xff)
23969 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23970 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
23971 (unsigned long) addend_abs
);
23973 /* Extract the instruction. */
23974 insn
= md_chars_to_number (buf
, INSN_SIZE
);
23976 /* If the addend is negative, clear bit 23 of the instruction.
23977 Otherwise set it. */
23979 insn
&= ~(1 << 23);
23983 /* Place the addend (divided by four) into the first eight
23984 bits of the instruction. */
23985 insn
&= 0xfffffff0;
23986 insn
|= addend_abs
>> 2;
23988 /* Update the instruction. */
23989 md_number_to_chars (buf
, insn
, INSN_SIZE
);
23993 case BFD_RELOC_ARM_V4BX
:
23994 /* This will need to go in the object file. */
23998 case BFD_RELOC_UNUSED
:
24000 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24001 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24005 /* Translate internal representation of relocation info to BFD target
24009 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24012 bfd_reloc_code_real_type code
;
24014 reloc
= XNEW (arelent
);
24016 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24017 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24018 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24020 if (fixp
->fx_pcrel
)
24022 if (section
->use_rela_p
)
24023 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24025 fixp
->fx_offset
= reloc
->address
;
24027 reloc
->addend
= fixp
->fx_offset
;
24029 switch (fixp
->fx_r_type
)
24032 if (fixp
->fx_pcrel
)
24034 code
= BFD_RELOC_8_PCREL
;
24039 if (fixp
->fx_pcrel
)
24041 code
= BFD_RELOC_16_PCREL
;
24046 if (fixp
->fx_pcrel
)
24048 code
= BFD_RELOC_32_PCREL
;
24052 case BFD_RELOC_ARM_MOVW
:
24053 if (fixp
->fx_pcrel
)
24055 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24059 case BFD_RELOC_ARM_MOVT
:
24060 if (fixp
->fx_pcrel
)
24062 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24066 case BFD_RELOC_ARM_THUMB_MOVW
:
24067 if (fixp
->fx_pcrel
)
24069 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24073 case BFD_RELOC_ARM_THUMB_MOVT
:
24074 if (fixp
->fx_pcrel
)
24076 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24080 case BFD_RELOC_NONE
:
24081 case BFD_RELOC_ARM_PCREL_BRANCH
:
24082 case BFD_RELOC_ARM_PCREL_BLX
:
24083 case BFD_RELOC_RVA
:
24084 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24085 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24086 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24087 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24088 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24089 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24090 case BFD_RELOC_VTABLE_ENTRY
:
24091 case BFD_RELOC_VTABLE_INHERIT
:
24093 case BFD_RELOC_32_SECREL
:
24095 code
= fixp
->fx_r_type
;
24098 case BFD_RELOC_THUMB_PCREL_BLX
:
24100 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24101 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24104 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24107 case BFD_RELOC_ARM_LITERAL
:
24108 case BFD_RELOC_ARM_HWLITERAL
:
24109 /* If this is called then the a literal has
24110 been referenced across a section boundary. */
24111 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24112 _("literal referenced across section boundary"));
24116 case BFD_RELOC_ARM_TLS_CALL
:
24117 case BFD_RELOC_ARM_THM_TLS_CALL
:
24118 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24119 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24120 case BFD_RELOC_ARM_GOT32
:
24121 case BFD_RELOC_ARM_GOTOFF
:
24122 case BFD_RELOC_ARM_GOT_PREL
:
24123 case BFD_RELOC_ARM_PLT32
:
24124 case BFD_RELOC_ARM_TARGET1
:
24125 case BFD_RELOC_ARM_ROSEGREL32
:
24126 case BFD_RELOC_ARM_SBREL32
:
24127 case BFD_RELOC_ARM_PREL31
:
24128 case BFD_RELOC_ARM_TARGET2
:
24129 case BFD_RELOC_ARM_TLS_LDO32
:
24130 case BFD_RELOC_ARM_PCREL_CALL
:
24131 case BFD_RELOC_ARM_PCREL_JUMP
:
24132 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24133 case BFD_RELOC_ARM_ALU_PC_G0
:
24134 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24135 case BFD_RELOC_ARM_ALU_PC_G1
:
24136 case BFD_RELOC_ARM_ALU_PC_G2
:
24137 case BFD_RELOC_ARM_LDR_PC_G0
:
24138 case BFD_RELOC_ARM_LDR_PC_G1
:
24139 case BFD_RELOC_ARM_LDR_PC_G2
:
24140 case BFD_RELOC_ARM_LDRS_PC_G0
:
24141 case BFD_RELOC_ARM_LDRS_PC_G1
:
24142 case BFD_RELOC_ARM_LDRS_PC_G2
:
24143 case BFD_RELOC_ARM_LDC_PC_G0
:
24144 case BFD_RELOC_ARM_LDC_PC_G1
:
24145 case BFD_RELOC_ARM_LDC_PC_G2
:
24146 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24147 case BFD_RELOC_ARM_ALU_SB_G0
:
24148 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24149 case BFD_RELOC_ARM_ALU_SB_G1
:
24150 case BFD_RELOC_ARM_ALU_SB_G2
:
24151 case BFD_RELOC_ARM_LDR_SB_G0
:
24152 case BFD_RELOC_ARM_LDR_SB_G1
:
24153 case BFD_RELOC_ARM_LDR_SB_G2
:
24154 case BFD_RELOC_ARM_LDRS_SB_G0
:
24155 case BFD_RELOC_ARM_LDRS_SB_G1
:
24156 case BFD_RELOC_ARM_LDRS_SB_G2
:
24157 case BFD_RELOC_ARM_LDC_SB_G0
:
24158 case BFD_RELOC_ARM_LDC_SB_G1
:
24159 case BFD_RELOC_ARM_LDC_SB_G2
:
24160 case BFD_RELOC_ARM_V4BX
:
24161 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24162 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24163 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24164 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24165 code
= fixp
->fx_r_type
;
24168 case BFD_RELOC_ARM_TLS_GOTDESC
:
24169 case BFD_RELOC_ARM_TLS_GD32
:
24170 case BFD_RELOC_ARM_TLS_LE32
:
24171 case BFD_RELOC_ARM_TLS_IE32
:
24172 case BFD_RELOC_ARM_TLS_LDM32
:
24173 /* BFD will include the symbol's address in the addend.
24174 But we don't want that, so subtract it out again here. */
24175 if (!S_IS_COMMON (fixp
->fx_addsy
))
24176 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24177 code
= fixp
->fx_r_type
;
24181 case BFD_RELOC_ARM_IMMEDIATE
:
24182 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24183 _("internal relocation (type: IMMEDIATE) not fixed up"));
24186 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24187 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24188 _("ADRL used for a symbol not defined in the same file"));
24191 case BFD_RELOC_ARM_OFFSET_IMM
:
24192 if (section
->use_rela_p
)
24194 code
= fixp
->fx_r_type
;
24198 if (fixp
->fx_addsy
!= NULL
24199 && !S_IS_DEFINED (fixp
->fx_addsy
)
24200 && S_IS_LOCAL (fixp
->fx_addsy
))
24202 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24203 _("undefined local label `%s'"),
24204 S_GET_NAME (fixp
->fx_addsy
));
24208 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24209 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24216 switch (fixp
->fx_r_type
)
24218 case BFD_RELOC_NONE
: type
= "NONE"; break;
24219 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24220 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24221 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24222 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24223 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24224 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24225 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24226 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24227 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24228 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24229 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24230 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24231 default: type
= _("<unknown>"); break;
24233 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24234 _("cannot represent %s relocation in this object file format"),
24241 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24243 && fixp
->fx_addsy
== GOT_symbol
)
24245 code
= BFD_RELOC_ARM_GOTPC
;
24246 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24250 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24252 if (reloc
->howto
== NULL
)
24254 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24255 _("cannot represent %s relocation in this object file format"),
24256 bfd_get_reloc_code_name (code
));
24260 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24261 vtable entry to be used in the relocation's section offset. */
24262 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24263 reloc
->address
= fixp
->fx_offset
;
24268 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24271 cons_fix_new_arm (fragS
* frag
,
24275 bfd_reloc_code_real_type reloc
)
24280 FIXME: @@ Should look at CPU word size. */
24284 reloc
= BFD_RELOC_8
;
24287 reloc
= BFD_RELOC_16
;
24291 reloc
= BFD_RELOC_32
;
24294 reloc
= BFD_RELOC_64
;
24299 if (exp
->X_op
== O_secrel
)
24301 exp
->X_op
= O_symbol
;
24302 reloc
= BFD_RELOC_32_SECREL
;
24306 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24309 #if defined (OBJ_COFF)
24311 arm_validate_fix (fixS
* fixP
)
24313 /* If the destination of the branch is a defined symbol which does not have
24314 the THUMB_FUNC attribute, then we must be calling a function which has
24315 the (interfacearm) attribute. We look for the Thumb entry point to that
24316 function and change the branch to refer to that function instead. */
24317 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24318 && fixP
->fx_addsy
!= NULL
24319 && S_IS_DEFINED (fixP
->fx_addsy
)
24320 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24322 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24329 arm_force_relocation (struct fix
* fixp
)
24331 #if defined (OBJ_COFF) && defined (TE_PE)
24332 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24336 /* In case we have a call or a branch to a function in ARM ISA mode from
24337 a thumb function or vice-versa force the relocation. These relocations
24338 are cleared off for some cores that might have blx and simple transformations
24342 switch (fixp
->fx_r_type
)
24344 case BFD_RELOC_ARM_PCREL_JUMP
:
24345 case BFD_RELOC_ARM_PCREL_CALL
:
24346 case BFD_RELOC_THUMB_PCREL_BLX
:
24347 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24351 case BFD_RELOC_ARM_PCREL_BLX
:
24352 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24353 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24354 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24355 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24364 /* Resolve these relocations even if the symbol is extern or weak.
24365 Technically this is probably wrong due to symbol preemption.
24366 In practice these relocations do not have enough range to be useful
24367 at dynamic link time, and some code (e.g. in the Linux kernel)
24368 expects these references to be resolved. */
24369 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24370 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24371 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24372 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24373 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24374 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24375 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24376 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24377 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24378 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24379 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
24380 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
24381 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
24382 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
24385 /* Always leave these relocations for the linker. */
24386 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24387 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24388 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24391 /* Always generate relocations against function symbols. */
24392 if (fixp
->fx_r_type
== BFD_RELOC_32
24394 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
24397 return generic_force_reloc (fixp
);
24400 #if defined (OBJ_ELF) || defined (OBJ_COFF)
24401 /* Relocations against function names must be left unadjusted,
24402 so that the linker can use this information to generate interworking
24403 stubs. The MIPS version of this function
24404 also prevents relocations that are mips-16 specific, but I do not
24405 know why it does this.
24408 There is one other problem that ought to be addressed here, but
24409 which currently is not: Taking the address of a label (rather
24410 than a function) and then later jumping to that address. Such
24411 addresses also ought to have their bottom bit set (assuming that
24412 they reside in Thumb code), but at the moment they will not. */
24415 arm_fix_adjustable (fixS
* fixP
)
24417 if (fixP
->fx_addsy
== NULL
)
24420 /* Preserve relocations against symbols with function type. */
24421 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
24424 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
24425 && fixP
->fx_subsy
== NULL
)
24428 /* We need the symbol name for the VTABLE entries. */
24429 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
24430 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24433 /* Don't allow symbols to be discarded on GOT related relocs. */
24434 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
24435 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
24436 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
24437 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
24438 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
24439 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
24440 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
24441 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
24442 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
24443 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
24444 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
24445 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
24446 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
24447 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
24450 /* Similarly for group relocations. */
24451 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
24452 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
24453 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
24456 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
24457 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
24458 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24459 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
24460 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
24461 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24462 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
24463 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
24464 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
24467 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
24468 offsets, so keep these symbols. */
24469 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
24470 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
24475 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
24479 elf32_arm_target_format (void)
24482 return (target_big_endian
24483 ? "elf32-bigarm-symbian"
24484 : "elf32-littlearm-symbian");
24485 #elif defined (TE_VXWORKS)
24486 return (target_big_endian
24487 ? "elf32-bigarm-vxworks"
24488 : "elf32-littlearm-vxworks");
24489 #elif defined (TE_NACL)
24490 return (target_big_endian
24491 ? "elf32-bigarm-nacl"
24492 : "elf32-littlearm-nacl");
24494 if (target_big_endian
)
24495 return "elf32-bigarm";
24497 return "elf32-littlearm";
24502 armelf_frob_symbol (symbolS
* symp
,
24505 elf_frob_symbol (symp
, puntp
);
24509 /* MD interface: Finalization. */
24514 literal_pool
* pool
;
24516 /* Ensure that all the IT blocks are properly closed. */
24517 check_it_blocks_finished ();
24519 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
24521 /* Put it at the end of the relevant section. */
24522 subseg_set (pool
->section
, pool
->sub_section
);
24524 arm_elf_change_section ();
24531 /* Remove any excess mapping symbols generated for alignment frags in
24532 SEC. We may have created a mapping symbol before a zero byte
24533 alignment; remove it if there's a mapping symbol after the
24536 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
24537 void *dummy ATTRIBUTE_UNUSED
)
24539 segment_info_type
*seginfo
= seg_info (sec
);
24542 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
24545 for (fragp
= seginfo
->frchainP
->frch_root
;
24547 fragp
= fragp
->fr_next
)
24549 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
24550 fragS
*next
= fragp
->fr_next
;
24552 /* Variable-sized frags have been converted to fixed size by
24553 this point. But if this was variable-sized to start with,
24554 there will be a fixed-size frag after it. So don't handle
24556 if (sym
== NULL
|| next
== NULL
)
24559 if (S_GET_VALUE (sym
) < next
->fr_address
)
24560 /* Not at the end of this frag. */
24562 know (S_GET_VALUE (sym
) == next
->fr_address
);
24566 if (next
->tc_frag_data
.first_map
!= NULL
)
24568 /* Next frag starts with a mapping symbol. Discard this
24570 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24574 if (next
->fr_next
== NULL
)
24576 /* This mapping symbol is at the end of the section. Discard
24578 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
24579 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
24583 /* As long as we have empty frags without any mapping symbols,
24585 /* If the next frag is non-empty and does not start with a
24586 mapping symbol, then this mapping symbol is required. */
24587 if (next
->fr_address
!= next
->fr_next
->fr_address
)
24590 next
= next
->fr_next
;
24592 while (next
!= NULL
);
24597 /* Adjust the symbol table. This marks Thumb symbols as distinct from
24601 arm_adjust_symtab (void)
24606 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24608 if (ARM_IS_THUMB (sym
))
24610 if (THUMB_IS_FUNC (sym
))
24612 /* Mark the symbol as a Thumb function. */
24613 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
24614 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
24615 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
24617 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
24618 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
24620 as_bad (_("%s: unexpected function type: %d"),
24621 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
24623 else switch (S_GET_STORAGE_CLASS (sym
))
24626 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
24629 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
24632 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
24640 if (ARM_IS_INTERWORK (sym
))
24641 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
24648 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
24650 if (ARM_IS_THUMB (sym
))
24652 elf_symbol_type
* elf_sym
;
24654 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
24655 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
24657 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
24658 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
24660 /* If it's a .thumb_func, declare it as so,
24661 otherwise tag label as .code 16. */
24662 if (THUMB_IS_FUNC (sym
))
24663 elf_sym
->internal_elf_sym
.st_target_internal
24664 = ST_BRANCH_TO_THUMB
;
24665 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
24666 elf_sym
->internal_elf_sym
.st_info
=
24667 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
24672 /* Remove any overlapping mapping symbols generated by alignment frags. */
24673 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
24674 /* Now do generic ELF adjustments. */
24675 elf_adjust_symtab ();
24679 /* MD interface: Initialization. */
24682 set_constant_flonums (void)
24686 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
24687 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
24691 /* Auto-select Thumb mode if it's the only available instruction set for the
24692 given architecture. */
24695 autoselect_thumb_from_cpu_variant (void)
24697 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
24698 opcode_select (16);
24707 if ( (arm_ops_hsh
= hash_new ()) == NULL
24708 || (arm_cond_hsh
= hash_new ()) == NULL
24709 || (arm_shift_hsh
= hash_new ()) == NULL
24710 || (arm_psr_hsh
= hash_new ()) == NULL
24711 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
24712 || (arm_reg_hsh
= hash_new ()) == NULL
24713 || (arm_reloc_hsh
= hash_new ()) == NULL
24714 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
24715 as_fatal (_("virtual memory exhausted"));
24717 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
24718 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
24719 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
24720 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
24721 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
24722 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
24723 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
24724 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
24725 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
24726 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
24727 (void *) (v7m_psrs
+ i
));
24728 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
24729 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
24731 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
24733 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
24734 (void *) (barrier_opt_names
+ i
));
24736 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
24738 struct reloc_entry
* entry
= reloc_names
+ i
;
24740 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
24741 /* This makes encode_branch() use the EABI versions of this relocation. */
24742 entry
->reloc
= BFD_RELOC_UNUSED
;
24744 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
24748 set_constant_flonums ();
24750 /* Set the cpu variant based on the command-line options. We prefer
24751 -mcpu= over -march= if both are set (as for GCC); and we prefer
24752 -mfpu= over any other way of setting the floating point unit.
24753 Use of legacy options with new options are faulted. */
24756 if (mcpu_cpu_opt
|| march_cpu_opt
)
24757 as_bad (_("use of old and new-style options to set CPU type"));
24759 mcpu_cpu_opt
= legacy_cpu
;
24761 else if (!mcpu_cpu_opt
)
24762 mcpu_cpu_opt
= march_cpu_opt
;
24767 as_bad (_("use of old and new-style options to set FPU type"));
24769 mfpu_opt
= legacy_fpu
;
24771 else if (!mfpu_opt
)
24773 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
24774 || defined (TE_NetBSD) || defined (TE_VXWORKS))
24775 /* Some environments specify a default FPU. If they don't, infer it
24776 from the processor. */
24778 mfpu_opt
= mcpu_fpu_opt
;
24780 mfpu_opt
= march_fpu_opt
;
24782 mfpu_opt
= &fpu_default
;
24788 if (mcpu_cpu_opt
!= NULL
)
24789 mfpu_opt
= &fpu_default
;
24790 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
24791 mfpu_opt
= &fpu_arch_vfp_v2
;
24793 mfpu_opt
= &fpu_arch_fpa
;
24799 mcpu_cpu_opt
= &cpu_default
;
24800 selected_cpu
= cpu_default
;
24802 else if (no_cpu_selected ())
24803 selected_cpu
= cpu_default
;
24806 selected_cpu
= *mcpu_cpu_opt
;
24808 mcpu_cpu_opt
= &arm_arch_any
;
24811 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
24813 autoselect_thumb_from_cpu_variant ();
24815 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
24817 #if defined OBJ_COFF || defined OBJ_ELF
24819 unsigned int flags
= 0;
24821 #if defined OBJ_ELF
24822 flags
= meabi_flags
;
24824 switch (meabi_flags
)
24826 case EF_ARM_EABI_UNKNOWN
:
24828 /* Set the flags in the private structure. */
24829 if (uses_apcs_26
) flags
|= F_APCS26
;
24830 if (support_interwork
) flags
|= F_INTERWORK
;
24831 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
24832 if (pic_code
) flags
|= F_PIC
;
24833 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
24834 flags
|= F_SOFT_FLOAT
;
24836 switch (mfloat_abi_opt
)
24838 case ARM_FLOAT_ABI_SOFT
:
24839 case ARM_FLOAT_ABI_SOFTFP
:
24840 flags
|= F_SOFT_FLOAT
;
24843 case ARM_FLOAT_ABI_HARD
:
24844 if (flags
& F_SOFT_FLOAT
)
24845 as_bad (_("hard-float conflicts with specified fpu"));
24849 /* Using pure-endian doubles (even if soft-float). */
24850 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
24851 flags
|= F_VFP_FLOAT
;
24853 #if defined OBJ_ELF
24854 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
24855 flags
|= EF_ARM_MAVERICK_FLOAT
;
24858 case EF_ARM_EABI_VER4
:
24859 case EF_ARM_EABI_VER5
:
24860 /* No additional flags to set. */
24867 bfd_set_private_flags (stdoutput
, flags
);
24869 /* We have run out flags in the COFF header to encode the
24870 status of ATPCS support, so instead we create a dummy,
24871 empty, debug section called .arm.atpcs. */
24876 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
24880 bfd_set_section_flags
24881 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
24882 bfd_set_section_size (stdoutput
, sec
, 0);
24883 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
24889 /* Record the CPU type as well. */
24890 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
24891 mach
= bfd_mach_arm_iWMMXt2
;
24892 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
24893 mach
= bfd_mach_arm_iWMMXt
;
24894 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
24895 mach
= bfd_mach_arm_XScale
;
24896 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
24897 mach
= bfd_mach_arm_ep9312
;
24898 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
24899 mach
= bfd_mach_arm_5TE
;
24900 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
24902 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24903 mach
= bfd_mach_arm_5T
;
24905 mach
= bfd_mach_arm_5
;
24907 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
24909 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
24910 mach
= bfd_mach_arm_4T
;
24912 mach
= bfd_mach_arm_4
;
24914 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
24915 mach
= bfd_mach_arm_3M
;
24916 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
24917 mach
= bfd_mach_arm_3
;
24918 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
24919 mach
= bfd_mach_arm_2a
;
24920 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
24921 mach
= bfd_mach_arm_2
;
24923 mach
= bfd_mach_arm_unknown
;
24925 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
24928 /* Command line processing. */
24931 Invocation line includes a switch not recognized by the base assembler.
24932 See if it's a processor-specific option.
24934 This routine is somewhat complicated by the need for backwards
24935 compatibility (since older releases of gcc can't be changed).
24936 The new options try to make the interface as compatible as
24939 New options (supported) are:
24941 -mcpu=<cpu name> Assemble for selected processor
24942 -march=<architecture name> Assemble for selected architecture
24943 -mfpu=<fpu architecture> Assemble for selected FPU.
24944 -EB/-mbig-endian Big-endian
24945 -EL/-mlittle-endian Little-endian
24946 -k Generate PIC code
24947 -mthumb Start in Thumb mode
24948 -mthumb-interwork Code supports ARM/Thumb interworking
24950 -m[no-]warn-deprecated Warn about deprecated features
24951 -m[no-]warn-syms Warn when symbols match instructions
24953 For now we will also provide support for:
24955 -mapcs-32 32-bit Program counter
24956 -mapcs-26 26-bit Program counter
24957 -macps-float Floats passed in FP registers
24958 -mapcs-reentrant Reentrant code
24960 (sometime these will probably be replaced with -mapcs=<list of options>
24961 and -matpcs=<list of options>)
24963 The remaining options are only supported for back-wards compatibility.
24964 Cpu variants, the arm part is optional:
24965 -m[arm]1 Currently not supported.
24966 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
24967 -m[arm]3 Arm 3 processor
24968 -m[arm]6[xx], Arm 6 processors
24969 -m[arm]7[xx][t][[d]m] Arm 7 processors
24970 -m[arm]8[10] Arm 8 processors
24971 -m[arm]9[20][tdmi] Arm 9 processors
24972 -mstrongarm[110[0]] StrongARM processors
24973 -mxscale XScale processors
24974 -m[arm]v[2345[t[e]]] Arm architectures
24975 -mall All (except the ARM1)
24977 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
24978 -mfpe-old (No float load/store multiples)
24979 -mvfpxd VFP Single precision
24981 -mno-fpu Disable all floating point instructions
24983 The following CPU names are recognized:
24984 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
24985 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
24986 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
24987 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
24988 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
24989 arm10t arm10e, arm1020t, arm1020e, arm10200e,
24990 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
24994 const char * md_shortopts
= "m:k";
24996 #ifdef ARM_BI_ENDIAN
24997 #define OPTION_EB (OPTION_MD_BASE + 0)
24998 #define OPTION_EL (OPTION_MD_BASE + 1)
25000 #if TARGET_BYTES_BIG_ENDIAN
25001 #define OPTION_EB (OPTION_MD_BASE + 0)
25003 #define OPTION_EL (OPTION_MD_BASE + 1)
25006 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25008 struct option md_longopts
[] =
25011 {"EB", no_argument
, NULL
, OPTION_EB
},
25014 {"EL", no_argument
, NULL
, OPTION_EL
},
25016 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25017 {NULL
, no_argument
, NULL
, 0}
25021 size_t md_longopts_size
= sizeof (md_longopts
);
25023 struct arm_option_table
25025 const char *option
; /* Option name to match. */
25026 const char *help
; /* Help information. */
25027 int *var
; /* Variable to change. */
25028 int value
; /* What to change it to. */
25029 const char *deprecated
; /* If non-null, print this message. */
25032 struct arm_option_table arm_opts
[] =
25034 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25035 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25036 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25037 &support_interwork
, 1, NULL
},
25038 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25039 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25040 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25042 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25043 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25044 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25045 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25048 /* These are recognized by the assembler, but have no affect on code. */
25049 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25050 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25052 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25053 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25054 &warn_on_deprecated
, 0, NULL
},
25055 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25056 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25057 {NULL
, NULL
, NULL
, 0, NULL
}
25060 struct arm_legacy_option_table
25062 const char *option
; /* Option name to match. */
25063 const arm_feature_set
**var
; /* Variable to change. */
25064 const arm_feature_set value
; /* What to change it to. */
25065 const char *deprecated
; /* If non-null, print this message. */
25068 const struct arm_legacy_option_table arm_legacy_opts
[] =
25070 /* DON'T add any new processors to this list -- we want the whole list
25071 to go away... Add them to the processors table instead. */
25072 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25073 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25074 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25075 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25076 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25077 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25078 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25079 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25080 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25081 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25082 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25083 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25084 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25085 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25086 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25087 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25088 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25089 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25090 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25091 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25092 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25093 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25094 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25095 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25096 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25097 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25098 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25099 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25100 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25101 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25102 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25103 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25104 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25105 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25106 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25107 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25108 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25109 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25110 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25111 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25112 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25113 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25114 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25115 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25116 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25117 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25118 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25119 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25120 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25121 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25122 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25123 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25124 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25125 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25126 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25127 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25128 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25129 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25130 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25131 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25132 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25133 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25134 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25135 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25136 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25137 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25138 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25139 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25140 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25141 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25142 N_("use -mcpu=strongarm110")},
25143 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25144 N_("use -mcpu=strongarm1100")},
25145 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25146 N_("use -mcpu=strongarm1110")},
25147 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25148 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25149 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25151 /* Architecture variants -- don't add any more to this list either. */
25152 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25153 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25154 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25155 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25156 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25157 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25158 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25159 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25160 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25161 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25162 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25163 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25164 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25165 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25166 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25167 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25168 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25169 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25171 /* Floating point variants -- don't add any more to this list either. */
25172 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25173 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25174 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25175 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25176 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25178 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25181 struct arm_cpu_option_table
25185 const arm_feature_set value
;
25186 /* For some CPUs we assume an FPU unless the user explicitly sets
25188 const arm_feature_set default_fpu
;
25189 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25191 const char *canonical_name
;
25194 /* This list should, at a minimum, contain all the cpu names
25195 recognized by GCC. */
25196 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
25197 static const struct arm_cpu_option_table arm_cpus
[] =
25199 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
25200 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
25201 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
25202 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25203 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
25204 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25205 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25206 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25207 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25208 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25209 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25210 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25211 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25212 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25213 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25214 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
25215 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25216 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25217 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25218 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25219 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25220 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25221 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25222 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25223 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25224 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25225 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25226 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
25227 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25228 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25229 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25230 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25231 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25232 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25233 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25234 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25235 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25236 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25237 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25238 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
25239 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25240 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25241 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25242 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
25243 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25244 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
25245 /* For V5 or later processors we default to using VFP; but the user
25246 should really set the FPU type explicitly. */
25247 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25248 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25249 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25250 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
25251 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25252 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25253 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
25254 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25255 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
25256 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
25257 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25258 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25259 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25260 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25261 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25262 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
25263 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
25264 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25265 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25266 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
25268 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
25269 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25270 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25271 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25272 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25273 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
25274 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
25275 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
25276 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
25278 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
25279 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
25280 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
25281 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
25282 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
25283 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ
, FPU_NONE
, NULL
),
25284 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ
, FPU_ARCH_VFP_V2
, NULL
),
25285 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
25286 FPU_NONE
, "Cortex-A5"),
25287 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25289 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
25290 ARM_FEATURE_COPROC (FPU_VFP_V3
25291 | FPU_NEON_EXT_V1
),
25293 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
25294 ARM_FEATURE_COPROC (FPU_VFP_V3
25295 | FPU_NEON_EXT_V1
),
25297 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25299 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25301 ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
25303 ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25305 ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25307 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25309 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25311 ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25313 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
25314 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
25316 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
25317 FPU_NONE
, "Cortex-R5"),
25318 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
25319 FPU_ARCH_VFP_V3D16
,
25321 ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV
,
25322 FPU_ARCH_VFP_V3D16
,
25324 ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M7"),
25325 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
25326 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
25327 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
25328 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
25329 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
25330 ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25333 ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25337 /* ??? XSCALE is really an architecture. */
25338 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25339 /* ??? iwmmxt is not a processor. */
25340 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
25341 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
25342 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
25344 ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
25345 FPU_ARCH_MAVERICK
, "ARM920T"),
25346 /* Marvell processors. */
25347 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25349 ARM_EXT2_V6T2_V8M
),
25350 FPU_ARCH_VFP_V3D16
, NULL
),
25351 ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A
| ARM_EXT_MP
25353 ARM_EXT2_V6T2_V8M
),
25354 FPU_ARCH_NEON_VFP_V4
, NULL
),
25355 /* APM X-Gene family. */
25356 ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25358 ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25361 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
25365 struct arm_arch_option_table
25369 const arm_feature_set value
;
25370 const arm_feature_set default_fpu
;
25373 /* This list should, at a minimum, contain all the architecture names
25374 recognized by GCC. */
25375 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
25376 static const struct arm_arch_option_table arm_archs
[] =
25378 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
25379 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
25380 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
25381 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25382 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
25383 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
25384 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
25385 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
25386 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
25387 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
25388 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
25389 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
25390 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
25391 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
25392 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
25393 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
25394 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
25395 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25396 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
25397 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
25398 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
25399 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
25400 kept to preserve existing behaviour. */
25401 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25402 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
25403 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
25404 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
25405 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
25406 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
25407 kept to preserve existing behaviour. */
25408 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25409 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
25410 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
25411 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
25412 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
25413 /* The official spelling of the ARMv7 profile variants is the dashed form.
25414 Accept the non-dashed form for compatibility with old toolchains. */
25415 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25416 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
25417 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25418 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25419 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
25420 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
25421 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
25422 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
25423 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
25424 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
25425 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
25426 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
25427 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
25428 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
25429 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
25430 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
25431 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25433 #undef ARM_ARCH_OPT
25435 /* ISA extensions in the co-processor and main instruction set space. */
25436 struct arm_option_extension_value_table
25440 const arm_feature_set merge_value
;
25441 const arm_feature_set clear_value
;
25442 const arm_feature_set allowed_archs
;
25445 /* The following table must be in alphabetical order with a NULL last entry.
25447 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, AA }
25448 static const struct arm_option_extension_value_table arm_extensions
[] =
25450 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
25451 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25452 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
25453 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
25454 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25455 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
25456 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25457 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25458 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
25460 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25461 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
25462 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25463 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
25464 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ANY
),
25465 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
25466 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ANY
),
25467 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
25468 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ANY
),
25469 ARM_EXT_OPT ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25470 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
25471 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
| ARM_EXT_V7R
)),
25472 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25473 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
25474 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
25475 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
25476 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
25477 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25478 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
25479 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
25480 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25481 ARM_EXT_OPT ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25482 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
25483 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V7A
)),
25484 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
25485 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
25486 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
25487 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
25489 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
25490 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
25491 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
25492 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ANY
),
25493 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
25497 /* ISA floating-point and Advanced SIMD extensions. */
25498 struct arm_option_fpu_value_table
25501 const arm_feature_set value
;
25504 /* This list should, at a minimum, contain all the fpu names
25505 recognized by GCC. */
25506 static const struct arm_option_fpu_value_table arm_fpus
[] =
25508 {"softfpa", FPU_NONE
},
25509 {"fpe", FPU_ARCH_FPE
},
25510 {"fpe2", FPU_ARCH_FPE
},
25511 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
25512 {"fpa", FPU_ARCH_FPA
},
25513 {"fpa10", FPU_ARCH_FPA
},
25514 {"fpa11", FPU_ARCH_FPA
},
25515 {"arm7500fe", FPU_ARCH_FPA
},
25516 {"softvfp", FPU_ARCH_VFP
},
25517 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
25518 {"vfp", FPU_ARCH_VFP_V2
},
25519 {"vfp9", FPU_ARCH_VFP_V2
},
25520 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
25521 {"vfp10", FPU_ARCH_VFP_V2
},
25522 {"vfp10-r0", FPU_ARCH_VFP_V1
},
25523 {"vfpxd", FPU_ARCH_VFP_V1xD
},
25524 {"vfpv2", FPU_ARCH_VFP_V2
},
25525 {"vfpv3", FPU_ARCH_VFP_V3
},
25526 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
25527 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
25528 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
25529 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
25530 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
25531 {"arm1020t", FPU_ARCH_VFP_V1
},
25532 {"arm1020e", FPU_ARCH_VFP_V2
},
25533 {"arm1136jfs", FPU_ARCH_VFP_V2
},
25534 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
25535 {"maverick", FPU_ARCH_MAVERICK
},
25536 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
25537 {"neon-fp16", FPU_ARCH_NEON_FP16
},
25538 {"vfpv4", FPU_ARCH_VFP_V4
},
25539 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
25540 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
25541 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
25542 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
25543 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
25544 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
25545 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
25546 {"crypto-neon-fp-armv8",
25547 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
25548 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
25549 {"crypto-neon-fp-armv8.1",
25550 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
25551 {NULL
, ARM_ARCH_NONE
}
25554 struct arm_option_value_table
25560 static const struct arm_option_value_table arm_float_abis
[] =
25562 {"hard", ARM_FLOAT_ABI_HARD
},
25563 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
25564 {"soft", ARM_FLOAT_ABI_SOFT
},
25569 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
25570 static const struct arm_option_value_table arm_eabis
[] =
25572 {"gnu", EF_ARM_EABI_UNKNOWN
},
25573 {"4", EF_ARM_EABI_VER4
},
25574 {"5", EF_ARM_EABI_VER5
},
25579 struct arm_long_option_table
25581 const char * option
; /* Substring to match. */
25582 const char * help
; /* Help information. */
25583 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
25584 const char * deprecated
; /* If non-null, print this message. */
25588 arm_parse_extension (const char *str
, const arm_feature_set
**opt_p
)
25590 arm_feature_set
*ext_set
= XNEW (arm_feature_set
);
25592 /* We insist on extensions being specified in alphabetical order, and with
25593 extensions being added before being removed. We achieve this by having
25594 the global ARM_EXTENSIONS table in alphabetical order, and using the
25595 ADDING_VALUE variable to indicate whether we are adding an extension (1)
25596 or removing it (0) and only allowing it to change in the order
25598 const struct arm_option_extension_value_table
* opt
= NULL
;
25599 int adding_value
= -1;
25601 /* Copy the feature set, so that we can modify it. */
25602 *ext_set
= **opt_p
;
25605 while (str
!= NULL
&& *str
!= 0)
25612 as_bad (_("invalid architectural extension"));
25617 ext
= strchr (str
, '+');
25622 len
= strlen (str
);
25624 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
25626 if (adding_value
!= 0)
25629 opt
= arm_extensions
;
25637 if (adding_value
== -1)
25640 opt
= arm_extensions
;
25642 else if (adding_value
!= 1)
25644 as_bad (_("must specify extensions to add before specifying "
25645 "those to remove"));
25652 as_bad (_("missing architectural extension"));
25656 gas_assert (adding_value
!= -1);
25657 gas_assert (opt
!= NULL
);
25659 /* Scan over the options table trying to find an exact match. */
25660 for (; opt
->name
!= NULL
; opt
++)
25661 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25663 /* Check we can apply the extension to this architecture. */
25664 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
25666 as_bad (_("extension does not apply to the base architecture"));
25670 /* Add or remove the extension. */
25672 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
25674 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
25679 if (opt
->name
== NULL
)
25681 /* Did we fail to find an extension because it wasn't specified in
25682 alphabetical order, or because it does not exist? */
25684 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25685 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25688 if (opt
->name
== NULL
)
25689 as_bad (_("unknown architectural extension `%s'"), str
);
25691 as_bad (_("architectural extensions must be specified in "
25692 "alphabetical order"));
25698 /* We should skip the extension we've just matched the next time
25710 arm_parse_cpu (const char *str
)
25712 const struct arm_cpu_option_table
*opt
;
25713 const char *ext
= strchr (str
, '+');
25719 len
= strlen (str
);
25723 as_bad (_("missing cpu name `%s'"), str
);
25727 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
25728 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25730 mcpu_cpu_opt
= &opt
->value
;
25731 mcpu_fpu_opt
= &opt
->default_fpu
;
25732 if (opt
->canonical_name
)
25734 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
25735 strcpy (selected_cpu_name
, opt
->canonical_name
);
25741 if (len
>= sizeof selected_cpu_name
)
25742 len
= (sizeof selected_cpu_name
) - 1;
25744 for (i
= 0; i
< len
; i
++)
25745 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25746 selected_cpu_name
[i
] = 0;
25750 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
25755 as_bad (_("unknown cpu `%s'"), str
);
25760 arm_parse_arch (const char *str
)
25762 const struct arm_arch_option_table
*opt
;
25763 const char *ext
= strchr (str
, '+');
25769 len
= strlen (str
);
25773 as_bad (_("missing architecture name `%s'"), str
);
25777 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
25778 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
25780 march_cpu_opt
= &opt
->value
;
25781 march_fpu_opt
= &opt
->default_fpu
;
25782 strcpy (selected_cpu_name
, opt
->name
);
25785 return arm_parse_extension (ext
, &march_cpu_opt
);
25790 as_bad (_("unknown architecture `%s'\n"), str
);
25795 arm_parse_fpu (const char * str
)
25797 const struct arm_option_fpu_value_table
* opt
;
25799 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25800 if (streq (opt
->name
, str
))
25802 mfpu_opt
= &opt
->value
;
25806 as_bad (_("unknown floating point format `%s'\n"), str
);
25811 arm_parse_float_abi (const char * str
)
25813 const struct arm_option_value_table
* opt
;
25815 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
25816 if (streq (opt
->name
, str
))
25818 mfloat_abi_opt
= opt
->value
;
25822 as_bad (_("unknown floating point abi `%s'\n"), str
);
25828 arm_parse_eabi (const char * str
)
25830 const struct arm_option_value_table
*opt
;
25832 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
25833 if (streq (opt
->name
, str
))
25835 meabi_flags
= opt
->value
;
25838 as_bad (_("unknown EABI `%s'\n"), str
);
25844 arm_parse_it_mode (const char * str
)
25846 bfd_boolean ret
= TRUE
;
25848 if (streq ("arm", str
))
25849 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
25850 else if (streq ("thumb", str
))
25851 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
25852 else if (streq ("always", str
))
25853 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
25854 else if (streq ("never", str
))
25855 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
25858 as_bad (_("unknown implicit IT mode `%s', should be "\
25859 "arm, thumb, always, or never."), str
);
25867 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
25869 codecomposer_syntax
= TRUE
;
25870 arm_comment_chars
[0] = ';';
25871 arm_line_separator_chars
[0] = 0;
25875 struct arm_long_option_table arm_long_opts
[] =
25877 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
25878 arm_parse_cpu
, NULL
},
25879 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
25880 arm_parse_arch
, NULL
},
25881 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
25882 arm_parse_fpu
, NULL
},
25883 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
25884 arm_parse_float_abi
, NULL
},
25886 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
25887 arm_parse_eabi
, NULL
},
25889 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
25890 arm_parse_it_mode
, NULL
},
25891 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
25892 arm_ccs_mode
, NULL
},
25893 {NULL
, NULL
, 0, NULL
}
25897 md_parse_option (int c
, const char * arg
)
25899 struct arm_option_table
*opt
;
25900 const struct arm_legacy_option_table
*fopt
;
25901 struct arm_long_option_table
*lopt
;
25907 target_big_endian
= 1;
25913 target_big_endian
= 0;
25917 case OPTION_FIX_V4BX
:
25922 /* Listing option. Just ignore these, we don't support additional
25927 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25929 if (c
== opt
->option
[0]
25930 && ((arg
== NULL
&& opt
->option
[1] == 0)
25931 || streq (arg
, opt
->option
+ 1)))
25933 /* If the option is deprecated, tell the user. */
25934 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
25935 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25936 arg
? arg
: "", _(opt
->deprecated
));
25938 if (opt
->var
!= NULL
)
25939 *opt
->var
= opt
->value
;
25945 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
25947 if (c
== fopt
->option
[0]
25948 && ((arg
== NULL
&& fopt
->option
[1] == 0)
25949 || streq (arg
, fopt
->option
+ 1)))
25951 /* If the option is deprecated, tell the user. */
25952 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
25953 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
25954 arg
? arg
: "", _(fopt
->deprecated
));
25956 if (fopt
->var
!= NULL
)
25957 *fopt
->var
= &fopt
->value
;
25963 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
25965 /* These options are expected to have an argument. */
25966 if (c
== lopt
->option
[0]
25968 && strncmp (arg
, lopt
->option
+ 1,
25969 strlen (lopt
->option
+ 1)) == 0)
25971 /* If the option is deprecated, tell the user. */
25972 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
25973 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
25974 _(lopt
->deprecated
));
25976 /* Call the sup-option parser. */
25977 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
25988 md_show_usage (FILE * fp
)
25990 struct arm_option_table
*opt
;
25991 struct arm_long_option_table
*lopt
;
25993 fprintf (fp
, _(" ARM-specific assembler options:\n"));
25995 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
25996 if (opt
->help
!= NULL
)
25997 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
25999 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26000 if (lopt
->help
!= NULL
)
26001 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26005 -EB assemble code for a big-endian cpu\n"));
26010 -EL assemble code for a little-endian cpu\n"));
26014 --fix-v4bx Allow BX in ARMv4 code\n"));
26022 arm_feature_set flags
;
26023 } cpu_arch_ver_table
;
26025 /* Mapping from CPU features to EABI CPU arch values. As a general rule, table
26026 must be sorted least features first but some reordering is needed, eg. for
26027 Thumb-2 instructions to be detected as coming from ARMv6T2. */
26028 static const cpu_arch_ver_table cpu_arch_ver
[] =
26034 {4, ARM_ARCH_V5TE
},
26035 {5, ARM_ARCH_V5TEJ
},
26039 {11, ARM_ARCH_V6M
},
26040 {12, ARM_ARCH_V6SM
},
26041 {8, ARM_ARCH_V6T2
},
26042 {10, ARM_ARCH_V7VE
},
26043 {10, ARM_ARCH_V7R
},
26044 {10, ARM_ARCH_V7M
},
26045 {14, ARM_ARCH_V8A
},
26046 {16, ARM_ARCH_V8M_BASE
},
26047 {17, ARM_ARCH_V8M_MAIN
},
26051 /* Set an attribute if it has not already been set by the user. */
26053 aeabi_set_attribute_int (int tag
, int value
)
26056 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26057 || !attributes_set_explicitly
[tag
])
26058 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26062 aeabi_set_attribute_string (int tag
, const char *value
)
26065 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26066 || !attributes_set_explicitly
[tag
])
26067 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
26070 /* Set the public EABI object attributes. */
26072 aeabi_set_public_attributes (void)
26077 int fp16_optional
= 0;
26078 arm_feature_set flags
;
26079 arm_feature_set tmp
;
26080 arm_feature_set arm_arch_v8m_base
= ARM_ARCH_V8M_BASE
;
26081 const cpu_arch_ver_table
*p
;
26083 /* Choose the architecture based on the capabilities of the requested cpu
26084 (if any) and/or the instructions actually used. */
26085 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
26086 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
26087 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
26089 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
26090 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
26092 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
26093 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
26095 selected_cpu
= flags
;
26097 /* Allow the user to override the reported architecture. */
26100 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
26101 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
26104 /* We need to make sure that the attributes do not identify us as v6S-M
26105 when the only v6S-M feature in use is the Operating System Extensions. */
26106 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
26107 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
26108 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
26112 for (p
= cpu_arch_ver
; p
->val
; p
++)
26114 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
26117 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
26121 /* The table lookup above finds the last architecture to contribute
26122 a new feature. Unfortunately, Tag13 is a subset of the union of
26123 v6T2 and v7-M, so it is never seen as contributing a new feature.
26124 We can not search for the last entry which is entirely used,
26125 because if no CPU is specified we build up only those flags
26126 actually used. Perhaps we should separate out the specified
26127 and implicit cases. Avoid taking this path for -march=all by
26128 checking for contradictory v7-A / v7-M features. */
26129 if (arch
== TAG_CPU_ARCH_V7
26130 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26131 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
26132 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
26133 arch
= TAG_CPU_ARCH_V7E_M
;
26135 ARM_CLEAR_FEATURE (tmp
, flags
, arm_arch_v8m_base
);
26136 if (arch
== TAG_CPU_ARCH_V8M_BASE
&& ARM_CPU_HAS_FEATURE (tmp
, arm_arch_any
))
26137 arch
= TAG_CPU_ARCH_V8M_MAIN
;
26139 /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
26140 coming from ARMv8-A. However, since ARMv8-A has more instructions than
26141 ARMv8-M, -march=all must be detected as ARMv8-A. */
26142 if (arch
== TAG_CPU_ARCH_V8M_MAIN
26143 && ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
26144 arch
= TAG_CPU_ARCH_V8
;
26146 /* Tag_CPU_name. */
26147 if (selected_cpu_name
[0])
26151 q
= selected_cpu_name
;
26152 if (strncmp (q
, "armv", 4) == 0)
26157 for (i
= 0; q
[i
]; i
++)
26158 q
[i
] = TOUPPER (q
[i
]);
26160 aeabi_set_attribute_string (Tag_CPU_name
, q
);
26163 /* Tag_CPU_arch. */
26164 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
26166 /* Tag_CPU_arch_profile. */
26167 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
26168 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26169 || (ARM_CPU_HAS_FEATURE (flags
, arm_ext_atomics
)
26170 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
)))
26172 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
26174 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
26179 if (profile
!= '\0')
26180 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
26182 /* Tag_ARM_ISA_use. */
26183 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
26185 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
26187 /* Tag_THUMB_ISA_use. */
26188 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
26193 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26194 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26196 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
26200 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
26203 /* Tag_VFP_arch. */
26204 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
26205 aeabi_set_attribute_int (Tag_VFP_arch
,
26206 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26208 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
26209 aeabi_set_attribute_int (Tag_VFP_arch
,
26210 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
26212 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
26215 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
26217 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
26219 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
26222 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
26223 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
26224 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
26225 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
26226 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
26228 /* Tag_ABI_HardFP_use. */
26229 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
26230 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
26231 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
26233 /* Tag_WMMX_arch. */
26234 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
26235 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
26236 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
26237 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
26239 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
26240 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
26241 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
26242 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
26243 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
26244 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
26246 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
26248 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
26252 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
26257 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
26258 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
26259 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
26263 We set Tag_DIV_use to two when integer divide instructions have been used
26264 in ARM state, or when Thumb integer divide instructions have been used,
26265 but we have no architecture profile set, nor have we any ARM instructions.
26267 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
26268 by the base architecture.
26270 For new architectures we will have to check these tests. */
26271 gas_assert (arch
<= TAG_CPU_ARCH_V8
26272 || (arch
>= TAG_CPU_ARCH_V8M_BASE
26273 && arch
<= TAG_CPU_ARCH_V8M_MAIN
));
26274 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
26275 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
26276 aeabi_set_attribute_int (Tag_DIV_use
, 0);
26277 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
26278 || (profile
== '\0'
26279 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
26280 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
26281 aeabi_set_attribute_int (Tag_DIV_use
, 2);
26283 /* Tag_MP_extension_use. */
26284 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
26285 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
26287 /* Tag Virtualization_use. */
26288 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
26290 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
26293 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
26296 /* Add the default contents for the .ARM.attributes section. */
26300 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
26303 aeabi_set_public_attributes ();
26305 #endif /* OBJ_ELF */
26308 /* Parse a .cpu directive. */
26311 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
26313 const struct arm_cpu_option_table
*opt
;
26317 name
= input_line_pointer
;
26318 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26319 input_line_pointer
++;
26320 saved_char
= *input_line_pointer
;
26321 *input_line_pointer
= 0;
26323 /* Skip the first "all" entry. */
26324 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
26325 if (streq (opt
->name
, name
))
26327 mcpu_cpu_opt
= &opt
->value
;
26328 selected_cpu
= opt
->value
;
26329 if (opt
->canonical_name
)
26330 strcpy (selected_cpu_name
, opt
->canonical_name
);
26334 for (i
= 0; opt
->name
[i
]; i
++)
26335 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26337 selected_cpu_name
[i
] = 0;
26339 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26340 *input_line_pointer
= saved_char
;
26341 demand_empty_rest_of_line ();
26344 as_bad (_("unknown cpu `%s'"), name
);
26345 *input_line_pointer
= saved_char
;
26346 ignore_rest_of_line ();
26350 /* Parse a .arch directive. */
26353 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
26355 const struct arm_arch_option_table
*opt
;
26359 name
= input_line_pointer
;
26360 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26361 input_line_pointer
++;
26362 saved_char
= *input_line_pointer
;
26363 *input_line_pointer
= 0;
26365 /* Skip the first "all" entry. */
26366 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26367 if (streq (opt
->name
, name
))
26369 mcpu_cpu_opt
= &opt
->value
;
26370 selected_cpu
= opt
->value
;
26371 strcpy (selected_cpu_name
, opt
->name
);
26372 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26373 *input_line_pointer
= saved_char
;
26374 demand_empty_rest_of_line ();
26378 as_bad (_("unknown architecture `%s'\n"), name
);
26379 *input_line_pointer
= saved_char
;
26380 ignore_rest_of_line ();
26384 /* Parse a .object_arch directive. */
26387 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
26389 const struct arm_arch_option_table
*opt
;
26393 name
= input_line_pointer
;
26394 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26395 input_line_pointer
++;
26396 saved_char
= *input_line_pointer
;
26397 *input_line_pointer
= 0;
26399 /* Skip the first "all" entry. */
26400 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
26401 if (streq (opt
->name
, name
))
26403 object_arch
= &opt
->value
;
26404 *input_line_pointer
= saved_char
;
26405 demand_empty_rest_of_line ();
26409 as_bad (_("unknown architecture `%s'\n"), name
);
26410 *input_line_pointer
= saved_char
;
26411 ignore_rest_of_line ();
26414 /* Parse a .arch_extension directive. */
26417 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
26419 const struct arm_option_extension_value_table
*opt
;
26422 int adding_value
= 1;
26424 name
= input_line_pointer
;
26425 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26426 input_line_pointer
++;
26427 saved_char
= *input_line_pointer
;
26428 *input_line_pointer
= 0;
26430 if (strlen (name
) >= 2
26431 && strncmp (name
, "no", 2) == 0)
26437 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26438 if (streq (opt
->name
, name
))
26440 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
26442 as_bad (_("architectural extension `%s' is not allowed for the "
26443 "current base architecture"), name
);
26448 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
,
26451 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->clear_value
);
26453 mcpu_cpu_opt
= &selected_cpu
;
26454 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26455 *input_line_pointer
= saved_char
;
26456 demand_empty_rest_of_line ();
26460 if (opt
->name
== NULL
)
26461 as_bad (_("unknown architecture extension `%s'\n"), name
);
26463 *input_line_pointer
= saved_char
;
26464 ignore_rest_of_line ();
26467 /* Parse a .fpu directive. */
26470 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
26472 const struct arm_option_fpu_value_table
*opt
;
26476 name
= input_line_pointer
;
26477 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
26478 input_line_pointer
++;
26479 saved_char
= *input_line_pointer
;
26480 *input_line_pointer
= 0;
26482 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26483 if (streq (opt
->name
, name
))
26485 mfpu_opt
= &opt
->value
;
26486 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
26487 *input_line_pointer
= saved_char
;
26488 demand_empty_rest_of_line ();
26492 as_bad (_("unknown floating point format `%s'\n"), name
);
26493 *input_line_pointer
= saved_char
;
26494 ignore_rest_of_line ();
26497 /* Copy symbol information. */
26500 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
26502 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
26506 /* Given a symbolic attribute NAME, return the proper integer value.
26507 Returns -1 if the attribute is not known. */
26510 arm_convert_symbolic_attribute (const char *name
)
26512 static const struct
26517 attribute_table
[] =
26519 /* When you modify this table you should
26520 also modify the list in doc/c-arm.texi. */
26521 #define T(tag) {#tag, tag}
26522 T (Tag_CPU_raw_name
),
26525 T (Tag_CPU_arch_profile
),
26526 T (Tag_ARM_ISA_use
),
26527 T (Tag_THUMB_ISA_use
),
26531 T (Tag_Advanced_SIMD_arch
),
26532 T (Tag_PCS_config
),
26533 T (Tag_ABI_PCS_R9_use
),
26534 T (Tag_ABI_PCS_RW_data
),
26535 T (Tag_ABI_PCS_RO_data
),
26536 T (Tag_ABI_PCS_GOT_use
),
26537 T (Tag_ABI_PCS_wchar_t
),
26538 T (Tag_ABI_FP_rounding
),
26539 T (Tag_ABI_FP_denormal
),
26540 T (Tag_ABI_FP_exceptions
),
26541 T (Tag_ABI_FP_user_exceptions
),
26542 T (Tag_ABI_FP_number_model
),
26543 T (Tag_ABI_align_needed
),
26544 T (Tag_ABI_align8_needed
),
26545 T (Tag_ABI_align_preserved
),
26546 T (Tag_ABI_align8_preserved
),
26547 T (Tag_ABI_enum_size
),
26548 T (Tag_ABI_HardFP_use
),
26549 T (Tag_ABI_VFP_args
),
26550 T (Tag_ABI_WMMX_args
),
26551 T (Tag_ABI_optimization_goals
),
26552 T (Tag_ABI_FP_optimization_goals
),
26553 T (Tag_compatibility
),
26554 T (Tag_CPU_unaligned_access
),
26555 T (Tag_FP_HP_extension
),
26556 T (Tag_VFP_HP_extension
),
26557 T (Tag_ABI_FP_16bit_format
),
26558 T (Tag_MPextension_use
),
26560 T (Tag_nodefaults
),
26561 T (Tag_also_compatible_with
),
26562 T (Tag_conformance
),
26564 T (Tag_Virtualization_use
),
26565 /* We deliberately do not include Tag_MPextension_use_legacy. */
26573 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
26574 if (streq (name
, attribute_table
[i
].name
))
26575 return attribute_table
[i
].tag
;
26581 /* Apply sym value for relocations only in the case that they are for
26582 local symbols in the same segment as the fixup and you have the
26583 respective architectural feature for blx and simple switches. */
26585 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
26588 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
26589 /* PR 17444: If the local symbol is in a different section then a reloc
26590 will always be generated for it, so applying the symbol value now
26591 will result in a double offset being stored in the relocation. */
26592 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
26593 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
26595 switch (fixP
->fx_r_type
)
26597 case BFD_RELOC_ARM_PCREL_BLX
:
26598 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26599 if (ARM_IS_FUNC (fixP
->fx_addsy
))
26603 case BFD_RELOC_ARM_PCREL_CALL
:
26604 case BFD_RELOC_THUMB_PCREL_BLX
:
26605 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
26616 #endif /* OBJ_ELF */