1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
45 #define WARN_DEPRECATED 1
48 /* Must be at least the size of the largest unwind opcode (currently two). */
49 #define ARM_OPCODE_CHUNK_SIZE 8
51 /* This structure holds the unwinding state. */
56 symbolS
* table_entry
;
57 symbolS
* personality_routine
;
58 int personality_index
;
59 /* The segment containing the function. */
62 /* Opcodes generated from this function. */
63 unsigned char * opcodes
;
66 /* The number of bytes pushed to the stack. */
68 /* We don't add stack adjustment opcodes immediately so that we can merge
69 multiple adjustments. We can also omit the final adjustment
70 when using a frame pointer. */
71 offsetT pending_offset
;
72 /* These two fields are set by both unwind_movsp and unwind_setfp. They
73 hold the reg+offset to use when restoring sp from a frame pointer. */
76 /* Nonzero if an unwind_setfp directive has been seen. */
78 /* Nonzero if the last opcode restores sp from fp_reg. */
79 unsigned sp_restored
:1;
82 /* Bit N indicates that an R_ARM_NONE relocation has been output for
83 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
84 emitted only once per section, to save unnecessary bloat. */
85 static unsigned int marked_pr_dependency
= 0;
89 /* Results from operand parsing worker functions. */
93 PARSE_OPERAND_SUCCESS
,
95 PARSE_OPERAND_FAIL_NO_BACKTRACK
96 } parse_operand_result
;
101 ARM_FLOAT_ABI_SOFTFP
,
105 /* Types of processor to assemble for. */
107 #if defined __XSCALE__
108 #define CPU_DEFAULT ARM_ARCH_XSCALE
110 #if defined __thumb__
111 #define CPU_DEFAULT ARM_ARCH_V5T
118 # define FPU_DEFAULT FPU_ARCH_FPA
119 # elif defined (TE_NetBSD)
121 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
123 /* Legacy a.out format. */
124 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
126 # elif defined (TE_VXWORKS)
127 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
129 /* For backwards compatibility, default to FPA. */
130 # define FPU_DEFAULT FPU_ARCH_FPA
132 #endif /* ifndef FPU_DEFAULT */
134 #define streq(a, b) (strcmp (a, b) == 0)
136 static arm_feature_set cpu_variant
;
137 static arm_feature_set arm_arch_used
;
138 static arm_feature_set thumb_arch_used
;
140 /* Flags stored in private area of BFD structure. */
141 static int uses_apcs_26
= FALSE
;
142 static int atpcs
= FALSE
;
143 static int support_interwork
= FALSE
;
144 static int uses_apcs_float
= FALSE
;
145 static int pic_code
= FALSE
;
147 /* Variables that we set while parsing command-line options. Once all
148 options have been read we re-process these values to set the real
150 static const arm_feature_set
*legacy_cpu
= NULL
;
151 static const arm_feature_set
*legacy_fpu
= NULL
;
153 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
154 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
155 static const arm_feature_set
*march_cpu_opt
= NULL
;
156 static const arm_feature_set
*march_fpu_opt
= NULL
;
157 static const arm_feature_set
*mfpu_opt
= NULL
;
159 /* Constants for known architecture features. */
160 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
161 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
162 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
163 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
164 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
165 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
166 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
167 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
168 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
171 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
174 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
175 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
176 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
177 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
178 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
179 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
180 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
181 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
182 static const arm_feature_set arm_ext_v4t_5
=
183 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
184 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
185 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
186 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
187 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
188 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
189 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
190 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
191 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
192 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
199 static const arm_feature_set arm_arch_any
= ARM_ANY
;
200 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
201 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
202 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
204 static const arm_feature_set arm_cext_iwmmxt
=
205 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
206 static const arm_feature_set arm_cext_xscale
=
207 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
208 static const arm_feature_set arm_cext_maverick
=
209 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
210 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
211 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
212 static const arm_feature_set fpu_vfp_ext_v1xd
=
213 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
214 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
215 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
216 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
217 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
218 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
219 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
221 static int mfloat_abi_opt
= -1;
222 /* Record user cpu selection for object attributes. */
223 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
224 /* Must be long enough to hold any of the names in arm_cpus. */
225 static char selected_cpu_name
[16];
228 static int meabi_flags
= EABI_DEFAULT
;
230 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
235 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
236 symbolS
* GOT_symbol
;
239 /* 0: assemble for ARM,
240 1: assemble for Thumb,
241 2: assemble for Thumb even though target CPU does not support thumb
243 static int thumb_mode
= 0;
245 /* If unified_syntax is true, we are processing the new unified
246 ARM/Thumb syntax. Important differences from the old ARM mode:
248 - Immediate operands do not require a # prefix.
249 - Conditional affixes always appear at the end of the
250 instruction. (For backward compatibility, those instructions
251 that formerly had them in the middle, continue to accept them
253 - The IT instruction may appear, and if it does is validated
254 against subsequent conditional affixes. It does not generate
257 Important differences from the old Thumb mode:
259 - Immediate operands do not require a # prefix.
260 - Most of the V6T2 instructions are only available in unified mode.
261 - The .N and .W suffixes are recognized and honored (it is an error
262 if they cannot be honored).
263 - All instructions set the flags if and only if they have an 's' affix.
264 - Conditional affixes may be used. They are validated against
265 preceding IT instructions. Unlike ARM mode, you cannot use a
266 conditional affix except in the scope of an IT instruction. */
268 static bfd_boolean unified_syntax
= FALSE
;
283 enum neon_el_type type
;
287 #define NEON_MAX_TYPE_ELS 4
291 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
298 unsigned long instruction
;
302 /* "uncond_value" is set to the value in place of the conditional field in
303 unconditional versions of the instruction, or -1 if nothing is
306 struct neon_type vectype
;
307 /* Set to the opcode if the instruction needs relaxation.
308 Zero if the instruction is not relaxed. */
312 bfd_reloc_code_real_type type
;
321 struct neon_type_el vectype
;
322 unsigned present
: 1; /* Operand present. */
323 unsigned isreg
: 1; /* Operand was a register. */
324 unsigned immisreg
: 1; /* .imm field is a second register. */
325 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
326 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
327 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
328 instructions. This allows us to disambiguate ARM <-> vector insns. */
329 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
330 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
331 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
332 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
333 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
334 unsigned writeback
: 1; /* Operand has trailing ! */
335 unsigned preind
: 1; /* Preindexed address. */
336 unsigned postind
: 1; /* Postindexed address. */
337 unsigned negative
: 1; /* Index register was negated. */
338 unsigned shifted
: 1; /* Shift applied to operation. */
339 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
343 static struct arm_it inst
;
345 #define NUM_FLOAT_VALS 8
347 const char * fp_const
[] =
349 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
352 /* Number of littlenums required to hold an extended precision number. */
353 #define MAX_LITTLENUMS 6
355 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
365 #define CP_T_X 0x00008000
366 #define CP_T_Y 0x00400000
368 #define CONDS_BIT 0x00100000
369 #define LOAD_BIT 0x00100000
371 #define DOUBLE_LOAD_FLAG 0x00000001
375 const char * template;
379 #define COND_ALWAYS 0xE
383 const char *template;
387 struct asm_barrier_opt
389 const char *template;
393 /* The bit that distinguishes CPSR and SPSR. */
394 #define SPSR_BIT (1 << 22)
396 /* The individual PSR flag bits. */
397 #define PSR_c (1 << 16)
398 #define PSR_x (1 << 17)
399 #define PSR_s (1 << 18)
400 #define PSR_f (1 << 19)
405 bfd_reloc_code_real_type reloc
;
410 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
411 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
416 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
419 /* Bits for DEFINED field in neon_typed_alias. */
420 #define NTA_HASTYPE 1
421 #define NTA_HASINDEX 2
423 struct neon_typed_alias
425 unsigned char defined
;
427 struct neon_type_el eltype
;
430 /* ARM register categories. This includes coprocessor numbers and various
431 architecture extensions' registers. */
457 /* Structure for a hash table entry for a register.
458 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
459 information which states whether a vector type or index is specified (for a
460 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
464 unsigned char number
;
466 unsigned char builtin
;
467 struct neon_typed_alias
*neon
;
470 /* Diagnostics used when we don't get a register of the expected type. */
471 const char *const reg_expected_msgs
[] =
473 N_("ARM register expected"),
474 N_("bad or missing co-processor number"),
475 N_("co-processor register expected"),
476 N_("FPA register expected"),
477 N_("VFP single precision register expected"),
478 N_("VFP/Neon double precision register expected"),
479 N_("Neon quad precision register expected"),
480 N_("VFP single or double precision register expected"),
481 N_("Neon double or quad precision register expected"),
482 N_("VFP single, double or Neon quad precision register expected"),
483 N_("VFP system register expected"),
484 N_("Maverick MVF register expected"),
485 N_("Maverick MVD register expected"),
486 N_("Maverick MVFX register expected"),
487 N_("Maverick MVDX register expected"),
488 N_("Maverick MVAX register expected"),
489 N_("Maverick DSPSC register expected"),
490 N_("iWMMXt data register expected"),
491 N_("iWMMXt control register expected"),
492 N_("iWMMXt scalar register expected"),
493 N_("XScale accumulator register expected"),
496 /* Some well known registers that we refer to directly elsewhere. */
501 /* ARM instructions take 4bytes in the object file, Thumb instructions
507 /* Basic string to match. */
508 const char *template;
510 /* Parameters to instruction. */
511 unsigned char operands
[8];
513 /* Conditional tag - see opcode_lookup. */
514 unsigned int tag
: 4;
516 /* Basic instruction code. */
517 unsigned int avalue
: 28;
519 /* Thumb-format instruction code. */
522 /* Which architecture variant provides this instruction. */
523 const arm_feature_set
*avariant
;
524 const arm_feature_set
*tvariant
;
526 /* Function to call to encode instruction in ARM format. */
527 void (* aencode
) (void);
529 /* Function to call to encode instruction in Thumb format. */
530 void (* tencode
) (void);
533 /* Defines for various bits that we will want to toggle. */
534 #define INST_IMMEDIATE 0x02000000
535 #define OFFSET_REG 0x02000000
536 #define HWOFFSET_IMM 0x00400000
537 #define SHIFT_BY_REG 0x00000010
538 #define PRE_INDEX 0x01000000
539 #define INDEX_UP 0x00800000
540 #define WRITE_BACK 0x00200000
541 #define LDM_TYPE_2_OR_3 0x00400000
543 #define LITERAL_MASK 0xf000f000
544 #define OPCODE_MASK 0xfe1fffff
545 #define V4_STR_BIT 0x00000020
547 #define DATA_OP_SHIFT 21
549 #define T2_OPCODE_MASK 0xfe1fffff
550 #define T2_DATA_OP_SHIFT 21
552 /* Codes to distinguish the arithmetic instructions. */
563 #define OPCODE_CMP 10
564 #define OPCODE_CMN 11
565 #define OPCODE_ORR 12
566 #define OPCODE_MOV 13
567 #define OPCODE_BIC 14
568 #define OPCODE_MVN 15
570 #define T2_OPCODE_AND 0
571 #define T2_OPCODE_BIC 1
572 #define T2_OPCODE_ORR 2
573 #define T2_OPCODE_ORN 3
574 #define T2_OPCODE_EOR 4
575 #define T2_OPCODE_ADD 8
576 #define T2_OPCODE_ADC 10
577 #define T2_OPCODE_SBC 11
578 #define T2_OPCODE_SUB 13
579 #define T2_OPCODE_RSB 14
581 #define T_OPCODE_MUL 0x4340
582 #define T_OPCODE_TST 0x4200
583 #define T_OPCODE_CMN 0x42c0
584 #define T_OPCODE_NEG 0x4240
585 #define T_OPCODE_MVN 0x43c0
587 #define T_OPCODE_ADD_R3 0x1800
588 #define T_OPCODE_SUB_R3 0x1a00
589 #define T_OPCODE_ADD_HI 0x4400
590 #define T_OPCODE_ADD_ST 0xb000
591 #define T_OPCODE_SUB_ST 0xb080
592 #define T_OPCODE_ADD_SP 0xa800
593 #define T_OPCODE_ADD_PC 0xa000
594 #define T_OPCODE_ADD_I8 0x3000
595 #define T_OPCODE_SUB_I8 0x3800
596 #define T_OPCODE_ADD_I3 0x1c00
597 #define T_OPCODE_SUB_I3 0x1e00
599 #define T_OPCODE_ASR_R 0x4100
600 #define T_OPCODE_LSL_R 0x4080
601 #define T_OPCODE_LSR_R 0x40c0
602 #define T_OPCODE_ROR_R 0x41c0
603 #define T_OPCODE_ASR_I 0x1000
604 #define T_OPCODE_LSL_I 0x0000
605 #define T_OPCODE_LSR_I 0x0800
607 #define T_OPCODE_MOV_I8 0x2000
608 #define T_OPCODE_CMP_I8 0x2800
609 #define T_OPCODE_CMP_LR 0x4280
610 #define T_OPCODE_MOV_HR 0x4600
611 #define T_OPCODE_CMP_HR 0x4500
613 #define T_OPCODE_LDR_PC 0x4800
614 #define T_OPCODE_LDR_SP 0x9800
615 #define T_OPCODE_STR_SP 0x9000
616 #define T_OPCODE_LDR_IW 0x6800
617 #define T_OPCODE_STR_IW 0x6000
618 #define T_OPCODE_LDR_IH 0x8800
619 #define T_OPCODE_STR_IH 0x8000
620 #define T_OPCODE_LDR_IB 0x7800
621 #define T_OPCODE_STR_IB 0x7000
622 #define T_OPCODE_LDR_RW 0x5800
623 #define T_OPCODE_STR_RW 0x5000
624 #define T_OPCODE_LDR_RH 0x5a00
625 #define T_OPCODE_STR_RH 0x5200
626 #define T_OPCODE_LDR_RB 0x5c00
627 #define T_OPCODE_STR_RB 0x5400
629 #define T_OPCODE_PUSH 0xb400
630 #define T_OPCODE_POP 0xbc00
632 #define T_OPCODE_BRANCH 0xe000
634 #define THUMB_SIZE 2 /* Size of thumb instruction. */
635 #define THUMB_PP_PC_LR 0x0100
636 #define THUMB_LOAD_BIT 0x0800
637 #define THUMB2_LOAD_BIT 0x00100000
639 #define BAD_ARGS _("bad arguments to instruction")
640 #define BAD_PC _("r15 not allowed here")
641 #define BAD_COND _("instruction cannot be conditional")
642 #define BAD_OVERLAP _("registers may not be the same")
643 #define BAD_HIREG _("lo register required")
644 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
645 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
646 #define BAD_BRANCH _("branch must be last instruction in IT block")
647 #define BAD_NOT_IT _("instruction not allowed in IT block")
648 #define BAD_FPU _("selected FPU does not support instruction")
650 static struct hash_control
*arm_ops_hsh
;
651 static struct hash_control
*arm_cond_hsh
;
652 static struct hash_control
*arm_shift_hsh
;
653 static struct hash_control
*arm_psr_hsh
;
654 static struct hash_control
*arm_v7m_psr_hsh
;
655 static struct hash_control
*arm_reg_hsh
;
656 static struct hash_control
*arm_reloc_hsh
;
657 static struct hash_control
*arm_barrier_opt_hsh
;
659 /* Stuff needed to resolve the label ambiguity
669 symbolS
* last_label_seen
;
670 static int label_is_thumb_function_name
= FALSE
;
672 /* Literal pool structure. Held on a per-section
673 and per-sub-section basis. */
675 #define MAX_LITERAL_POOL_SIZE 1024
676 typedef struct literal_pool
678 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
679 unsigned int next_free_entry
;
684 struct literal_pool
* next
;
687 /* Pointer to a linked list of literal pools. */
688 literal_pool
* list_of_pools
= NULL
;
690 /* State variables for IT block handling. */
691 static bfd_boolean current_it_mask
= 0;
692 static int current_cc
;
697 /* This array holds the chars that always start a comment. If the
698 pre-processor is disabled, these aren't very useful. */
699 const char comment_chars
[] = "@";
701 /* This array holds the chars that only start a comment at the beginning of
702 a line. If the line seems to have the form '# 123 filename'
703 .line and .file directives will appear in the pre-processed output. */
704 /* Note that input_file.c hand checks for '#' at the beginning of the
705 first line of the input file. This is because the compiler outputs
706 #NO_APP at the beginning of its output. */
707 /* Also note that comments like this one will always work. */
708 const char line_comment_chars
[] = "#";
710 const char line_separator_chars
[] = ";";
712 /* Chars that can be used to separate mant
713 from exp in floating point numbers. */
714 const char EXP_CHARS
[] = "eE";
716 /* Chars that mean this number is a floating point constant. */
720 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
722 /* Prefix characters that indicate the start of an immediate
724 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
726 /* Separator character handling. */
728 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
731 skip_past_char (char ** str
, char c
)
741 #define skip_past_comma(str) skip_past_char (str, ',')
743 /* Arithmetic expressions (possibly involving symbols). */
745 /* Return TRUE if anything in the expression is a bignum. */
748 walk_no_bignums (symbolS
* sp
)
750 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
753 if (symbol_get_value_expression (sp
)->X_add_symbol
)
755 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
756 || (symbol_get_value_expression (sp
)->X_op_symbol
757 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
763 static int in_my_get_expression
= 0;
765 /* Third argument to my_get_expression. */
766 #define GE_NO_PREFIX 0
767 #define GE_IMM_PREFIX 1
768 #define GE_OPT_PREFIX 2
769 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
770 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
771 #define GE_OPT_PREFIX_BIG 3
774 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
779 /* In unified syntax, all prefixes are optional. */
781 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
786 case GE_NO_PREFIX
: break;
788 if (!is_immediate_prefix (**str
))
790 inst
.error
= _("immediate expression requires a # prefix");
796 case GE_OPT_PREFIX_BIG
:
797 if (is_immediate_prefix (**str
))
803 memset (ep
, 0, sizeof (expressionS
));
805 save_in
= input_line_pointer
;
806 input_line_pointer
= *str
;
807 in_my_get_expression
= 1;
808 seg
= expression (ep
);
809 in_my_get_expression
= 0;
811 if (ep
->X_op
== O_illegal
)
813 /* We found a bad expression in md_operand(). */
814 *str
= input_line_pointer
;
815 input_line_pointer
= save_in
;
816 if (inst
.error
== NULL
)
817 inst
.error
= _("bad expression");
822 if (seg
!= absolute_section
823 && seg
!= text_section
824 && seg
!= data_section
825 && seg
!= bss_section
826 && seg
!= undefined_section
)
828 inst
.error
= _("bad segment");
829 *str
= input_line_pointer
;
830 input_line_pointer
= save_in
;
835 /* Get rid of any bignums now, so that we don't generate an error for which
836 we can't establish a line number later on. Big numbers are never valid
837 in instructions, which is where this routine is always called. */
838 if (prefix_mode
!= GE_OPT_PREFIX_BIG
839 && (ep
->X_op
== O_big
841 && (walk_no_bignums (ep
->X_add_symbol
)
843 && walk_no_bignums (ep
->X_op_symbol
))))))
845 inst
.error
= _("invalid constant");
846 *str
= input_line_pointer
;
847 input_line_pointer
= save_in
;
851 *str
= input_line_pointer
;
852 input_line_pointer
= save_in
;
856 /* Turn a string in input_line_pointer into a floating point constant
857 of type TYPE, and store the appropriate bytes in *LITP. The number
858 of LITTLENUMS emitted is stored in *SIZEP. An error message is
859 returned, or NULL on OK.
861 Note that fp constants aren't represent in the normal way on the ARM.
862 In big endian mode, things are as expected. However, in little endian
863 mode fp constants are big-endian word-wise, and little-endian byte-wise
864 within the words. For example, (double) 1.1 in big endian mode is
865 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
866 the byte sequence 99 99 f1 3f 9a 99 99 99.
868 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
871 md_atof (int type
, char * litP
, int * sizeP
)
874 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
906 return _("bad call to MD_ATOF()");
909 t
= atof_ieee (input_line_pointer
, type
, words
);
911 input_line_pointer
= t
;
914 if (target_big_endian
)
916 for (i
= 0; i
< prec
; i
++)
918 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
924 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
925 for (i
= prec
- 1; i
>= 0; i
--)
927 md_number_to_chars (litP
, (valueT
) words
[i
], 2);
931 /* For a 4 byte float the order of elements in `words' is 1 0.
932 For an 8 byte float the order is 1 0 3 2. */
933 for (i
= 0; i
< prec
; i
+= 2)
935 md_number_to_chars (litP
, (valueT
) words
[i
+ 1], 2);
936 md_number_to_chars (litP
+ 2, (valueT
) words
[i
], 2);
944 /* We handle all bad expressions here, so that we can report the faulty
945 instruction in the error message. */
947 md_operand (expressionS
* expr
)
949 if (in_my_get_expression
)
950 expr
->X_op
= O_illegal
;
953 /* Immediate values. */
955 /* Generic immediate-value read function for use in directives.
956 Accepts anything that 'expression' can fold to a constant.
957 *val receives the number. */
960 immediate_for_directive (int *val
)
963 exp
.X_op
= O_illegal
;
965 if (is_immediate_prefix (*input_line_pointer
))
967 input_line_pointer
++;
971 if (exp
.X_op
!= O_constant
)
973 as_bad (_("expected #constant"));
974 ignore_rest_of_line ();
977 *val
= exp
.X_add_number
;
982 /* Register parsing. */
984 /* Generic register parser. CCP points to what should be the
985 beginning of a register name. If it is indeed a valid register
986 name, advance CCP over it and return the reg_entry structure;
987 otherwise return NULL. Does not issue diagnostics. */
989 static struct reg_entry
*
990 arm_reg_parse_multi (char **ccp
)
994 struct reg_entry
*reg
;
996 #ifdef REGISTER_PREFIX
997 if (*start
!= REGISTER_PREFIX
)
1001 #ifdef OPTIONAL_REGISTER_PREFIX
1002 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1007 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1012 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1014 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1024 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1025 enum arm_reg_type type
)
1027 /* Alternative syntaxes are accepted for a few register classes. */
1034 /* Generic coprocessor register names are allowed for these. */
1035 if (reg
&& reg
->type
== REG_TYPE_CN
)
1040 /* For backward compatibility, a bare number is valid here. */
1042 unsigned long processor
= strtoul (start
, ccp
, 10);
1043 if (*ccp
!= start
&& processor
<= 15)
1047 case REG_TYPE_MMXWC
:
1048 /* WC includes WCG. ??? I'm not sure this is true for all
1049 instructions that take WC registers. */
1050 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1061 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1062 return value is the register number or FAIL. */
1065 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1068 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1071 /* Do not allow a scalar (reg+index) to parse as a register. */
1072 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1075 if (reg
&& reg
->type
== type
)
1078 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1085 /* Parse a Neon type specifier. *STR should point at the leading '.'
1086 character. Does no verification at this stage that the type fits the opcode
1093 Can all be legally parsed by this function.
1095 Fills in neon_type struct pointer with parsed information, and updates STR
1096 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1097 type, FAIL if not. */
1100 parse_neon_type (struct neon_type
*type
, char **str
)
1107 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1109 enum neon_el_type thistype
= NT_untyped
;
1110 unsigned thissize
= -1u;
1117 /* Just a size without an explicit type. */
1121 switch (TOLOWER (*ptr
))
1123 case 'i': thistype
= NT_integer
; break;
1124 case 'f': thistype
= NT_float
; break;
1125 case 'p': thistype
= NT_poly
; break;
1126 case 's': thistype
= NT_signed
; break;
1127 case 'u': thistype
= NT_unsigned
; break;
1129 thistype
= NT_float
;
1134 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1140 /* .f is an abbreviation for .f32. */
1141 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1146 thissize
= strtoul (ptr
, &ptr
, 10);
1148 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1151 as_bad (_("bad size %d in type specifier"), thissize
);
1159 type
->el
[type
->elems
].type
= thistype
;
1160 type
->el
[type
->elems
].size
= thissize
;
1165 /* Empty/missing type is not a successful parse. */
1166 if (type
->elems
== 0)
1174 /* Errors may be set multiple times during parsing or bit encoding
1175 (particularly in the Neon bits), but usually the earliest error which is set
1176 will be the most meaningful. Avoid overwriting it with later (cascading)
1177 errors by calling this function. */
1180 first_error (const char *err
)
1186 /* Parse a single type, e.g. ".s32", leading period included. */
1188 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1191 struct neon_type optype
;
1195 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1197 if (optype
.elems
== 1)
1198 *vectype
= optype
.el
[0];
1201 first_error (_("only one type should be specified for operand"));
1207 first_error (_("vector type expected"));
1219 /* Special meanings for indices (which have a range of 0-7), which will fit into
1222 #define NEON_ALL_LANES 15
1223 #define NEON_INTERLEAVE_LANES 14
1225 /* Parse either a register or a scalar, with an optional type. Return the
1226 register number, and optionally fill in the actual type of the register
1227 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1228 type/index information in *TYPEINFO. */
1231 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1232 enum arm_reg_type
*rtype
,
1233 struct neon_typed_alias
*typeinfo
)
1236 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1237 struct neon_typed_alias atype
;
1238 struct neon_type_el parsetype
;
1242 atype
.eltype
.type
= NT_invtype
;
1243 atype
.eltype
.size
= -1;
1245 /* Try alternate syntax for some types of register. Note these are mutually
1246 exclusive with the Neon syntax extensions. */
1249 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1257 /* Undo polymorphism when a set of register types may be accepted. */
1258 if ((type
== REG_TYPE_NDQ
1259 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1260 || (type
== REG_TYPE_VFSD
1261 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1262 || (type
== REG_TYPE_NSDQ
1263 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1264 || reg
->type
== REG_TYPE_NQ
)))
1267 if (type
!= reg
->type
)
1273 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1275 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1277 first_error (_("can't redefine type for operand"));
1280 atype
.defined
|= NTA_HASTYPE
;
1281 atype
.eltype
= parsetype
;
1284 if (skip_past_char (&str
, '[') == SUCCESS
)
1286 if (type
!= REG_TYPE_VFD
)
1288 first_error (_("only D registers may be indexed"));
1292 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1294 first_error (_("can't change index for operand"));
1298 atype
.defined
|= NTA_HASINDEX
;
1300 if (skip_past_char (&str
, ']') == SUCCESS
)
1301 atype
.index
= NEON_ALL_LANES
;
1306 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1308 if (exp
.X_op
!= O_constant
)
1310 first_error (_("constant expression required"));
1314 if (skip_past_char (&str
, ']') == FAIL
)
1317 atype
.index
= exp
.X_add_number
;
1332 /* Like arm_reg_parse, but allow allow the following extra features:
1333 - If RTYPE is non-zero, return the (possibly restricted) type of the
1334 register (e.g. Neon double or quad reg when either has been requested).
1335 - If this is a Neon vector type with additional type information, fill
1336 in the struct pointed to by VECTYPE (if non-NULL).
1337 This function will fault on encountering a scalar.
1341 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1342 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1344 struct neon_typed_alias atype
;
1346 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1351 /* Do not allow a scalar (reg+index) to parse as a register. */
1352 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1354 first_error (_("register operand expected, but got scalar"));
1359 *vectype
= atype
.eltype
;
1366 #define NEON_SCALAR_REG(X) ((X) >> 4)
1367 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1369 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1370 have enough information to be able to do a good job bounds-checking. So, we
1371 just do easy checks here, and do further checks later. */
1374 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1378 struct neon_typed_alias atype
;
1380 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1382 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1385 if (atype
.index
== NEON_ALL_LANES
)
1387 first_error (_("scalar must have an index"));
1390 else if (atype
.index
>= 64 / elsize
)
1392 first_error (_("scalar index out of range"));
1397 *type
= atype
.eltype
;
1401 return reg
* 16 + atype
.index
;
1404 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1406 parse_reg_list (char ** strp
)
1408 char * str
= * strp
;
1412 /* We come back here if we get ranges concatenated by '+' or '|'. */
1427 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1429 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1439 first_error (_("bad range in register list"));
1443 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1445 if (range
& (1 << i
))
1447 (_("Warning: duplicated register (r%d) in register list"),
1455 if (range
& (1 << reg
))
1456 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1458 else if (reg
<= cur_reg
)
1459 as_tsktsk (_("Warning: register range not in ascending order"));
1464 while (skip_past_comma (&str
) != FAIL
1465 || (in_range
= 1, *str
++ == '-'));
1470 first_error (_("missing `}'"));
1478 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1481 if (expr
.X_op
== O_constant
)
1483 if (expr
.X_add_number
1484 != (expr
.X_add_number
& 0x0000ffff))
1486 inst
.error
= _("invalid register mask");
1490 if ((range
& expr
.X_add_number
) != 0)
1492 int regno
= range
& expr
.X_add_number
;
1495 regno
= (1 << regno
) - 1;
1497 (_("Warning: duplicated register (r%d) in register list"),
1501 range
|= expr
.X_add_number
;
1505 if (inst
.reloc
.type
!= 0)
1507 inst
.error
= _("expression too complex");
1511 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1512 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1513 inst
.reloc
.pc_rel
= 0;
1517 if (*str
== '|' || *str
== '+')
1523 while (another_range
);
1529 /* Types of registers in a list. */
1538 /* Parse a VFP register list. If the string is invalid return FAIL.
1539 Otherwise return the number of registers, and set PBASE to the first
1540 register. Parses registers of type ETYPE.
1541 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1542 - Q registers can be used to specify pairs of D registers
1543 - { } can be omitted from around a singleton register list
1544 FIXME: This is not implemented, as it would require backtracking in
1547 This could be done (the meaning isn't really ambiguous), but doesn't
1548 fit in well with the current parsing framework.
1549 - 32 D registers may be used (also true for VFPv3).
1550 FIXME: Types are ignored in these register lists, which is probably a
1554 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1559 enum arm_reg_type regtype
= 0;
1563 unsigned long mask
= 0;
1568 inst
.error
= _("expecting {");
1577 regtype
= REG_TYPE_VFS
;
1582 regtype
= REG_TYPE_VFD
;
1585 case REGLIST_NEON_D
:
1586 regtype
= REG_TYPE_NDQ
;
1590 if (etype
!= REGLIST_VFP_S
)
1592 /* VFPv3 allows 32 D registers. */
1593 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
1597 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1600 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1607 base_reg
= max_regs
;
1611 int setmask
= 1, addregs
= 1;
1613 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1615 if (new_base
== FAIL
)
1617 first_error (_(reg_expected_msgs
[regtype
]));
1621 if (new_base
>= max_regs
)
1623 first_error (_("register out of range in list"));
1627 /* Note: a value of 2 * n is returned for the register Q<n>. */
1628 if (regtype
== REG_TYPE_NQ
)
1634 if (new_base
< base_reg
)
1635 base_reg
= new_base
;
1637 if (mask
& (setmask
<< new_base
))
1639 first_error (_("invalid register list"));
1643 if ((mask
>> new_base
) != 0 && ! warned
)
1645 as_tsktsk (_("register list not in ascending order"));
1649 mask
|= setmask
<< new_base
;
1652 if (*str
== '-') /* We have the start of a range expression */
1658 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1661 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1665 if (high_range
>= max_regs
)
1667 first_error (_("register out of range in list"));
1671 if (regtype
== REG_TYPE_NQ
)
1672 high_range
= high_range
+ 1;
1674 if (high_range
<= new_base
)
1676 inst
.error
= _("register range not in ascending order");
1680 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1682 if (mask
& (setmask
<< new_base
))
1684 inst
.error
= _("invalid register list");
1688 mask
|= setmask
<< new_base
;
1693 while (skip_past_comma (&str
) != FAIL
);
1697 /* Sanity check -- should have raised a parse error above. */
1698 if (count
== 0 || count
> max_regs
)
1703 /* Final test -- the registers must be consecutive. */
1705 for (i
= 0; i
< count
; i
++)
1707 if ((mask
& (1u << i
)) == 0)
1709 inst
.error
= _("non-contiguous register range");
1719 /* True if two alias types are the same. */
1722 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1730 if (a
->defined
!= b
->defined
)
1733 if ((a
->defined
& NTA_HASTYPE
) != 0
1734 && (a
->eltype
.type
!= b
->eltype
.type
1735 || a
->eltype
.size
!= b
->eltype
.size
))
1738 if ((a
->defined
& NTA_HASINDEX
) != 0
1739 && (a
->index
!= b
->index
))
1745 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1746 The base register is put in *PBASE.
1747 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1749 The register stride (minus one) is put in bit 4 of the return value.
1750 Bits [6:5] encode the list length (minus one).
1751 The type of the list elements is put in *ELTYPE, if non-NULL. */
1753 #define NEON_LANE(X) ((X) & 0xf)
1754 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1755 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1758 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1759 struct neon_type_el
*eltype
)
1766 int leading_brace
= 0;
1767 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1769 const char *const incr_error
= "register stride must be 1 or 2";
1770 const char *const type_error
= "mismatched element/structure types in list";
1771 struct neon_typed_alias firsttype
;
1773 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1778 struct neon_typed_alias atype
;
1779 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1783 first_error (_(reg_expected_msgs
[rtype
]));
1790 if (rtype
== REG_TYPE_NQ
)
1797 else if (reg_incr
== -1)
1799 reg_incr
= getreg
- base_reg
;
1800 if (reg_incr
< 1 || reg_incr
> 2)
1802 first_error (_(incr_error
));
1806 else if (getreg
!= base_reg
+ reg_incr
* count
)
1808 first_error (_(incr_error
));
1812 if (!neon_alias_types_same (&atype
, &firsttype
))
1814 first_error (_(type_error
));
1818 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1822 struct neon_typed_alias htype
;
1823 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1825 lane
= NEON_INTERLEAVE_LANES
;
1826 else if (lane
!= NEON_INTERLEAVE_LANES
)
1828 first_error (_(type_error
));
1833 else if (reg_incr
!= 1)
1835 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1839 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1842 first_error (_(reg_expected_msgs
[rtype
]));
1845 if (!neon_alias_types_same (&htype
, &firsttype
))
1847 first_error (_(type_error
));
1850 count
+= hireg
+ dregs
- getreg
;
1854 /* If we're using Q registers, we can't use [] or [n] syntax. */
1855 if (rtype
== REG_TYPE_NQ
)
1861 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1865 else if (lane
!= atype
.index
)
1867 first_error (_(type_error
));
1871 else if (lane
== -1)
1872 lane
= NEON_INTERLEAVE_LANES
;
1873 else if (lane
!= NEON_INTERLEAVE_LANES
)
1875 first_error (_(type_error
));
1880 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1882 /* No lane set by [x]. We must be interleaving structures. */
1884 lane
= NEON_INTERLEAVE_LANES
;
1887 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1888 || (count
> 1 && reg_incr
== -1))
1890 first_error (_("error parsing element/structure list"));
1894 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1896 first_error (_("expected }"));
1904 *eltype
= firsttype
.eltype
;
1909 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1912 /* Parse an explicit relocation suffix on an expression. This is
1913 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1914 arm_reloc_hsh contains no entries, so this function can only
1915 succeed if there is no () after the word. Returns -1 on error,
1916 BFD_RELOC_UNUSED if there wasn't any suffix. */
1918 parse_reloc (char **str
)
1920 struct reloc_entry
*r
;
1924 return BFD_RELOC_UNUSED
;
1929 while (*q
&& *q
!= ')' && *q
!= ',')
1934 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1941 /* Directives: register aliases. */
1943 static struct reg_entry
*
1944 insert_reg_alias (char *str
, int number
, int type
)
1946 struct reg_entry
*new;
1949 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1952 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1954 /* Only warn about a redefinition if it's not defined as the
1956 else if (new->number
!= number
|| new->type
!= type
)
1957 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1962 name
= xstrdup (str
);
1963 new = xmalloc (sizeof (struct reg_entry
));
1966 new->number
= number
;
1968 new->builtin
= FALSE
;
1971 if (hash_insert (arm_reg_hsh
, name
, (PTR
) new))
1978 insert_neon_reg_alias (char *str
, int number
, int type
,
1979 struct neon_typed_alias
*atype
)
1981 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
1985 first_error (_("attempt to redefine typed alias"));
1991 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
1992 *reg
->neon
= *atype
;
1996 /* Look for the .req directive. This is of the form:
1998 new_register_name .req existing_register_name
2000 If we find one, or if it looks sufficiently like one that we want to
2001 handle any error here, return non-zero. Otherwise return zero. */
2004 create_register_alias (char * newname
, char *p
)
2006 struct reg_entry
*old
;
2007 char *oldname
, *nbuf
;
2010 /* The input scrubber ensures that whitespace after the mnemonic is
2011 collapsed to single spaces. */
2013 if (strncmp (oldname
, " .req ", 6) != 0)
2017 if (*oldname
== '\0')
2020 old
= hash_find (arm_reg_hsh
, oldname
);
2023 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2027 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2028 the desired alias name, and p points to its end. If not, then
2029 the desired alias name is in the global original_case_string. */
2030 #ifdef TC_CASE_SENSITIVE
2033 newname
= original_case_string
;
2034 nlen
= strlen (newname
);
2037 nbuf
= alloca (nlen
+ 1);
2038 memcpy (nbuf
, newname
, nlen
);
2041 /* Create aliases under the new name as stated; an all-lowercase
2042 version of the new name; and an all-uppercase version of the new
2044 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2046 for (p
= nbuf
; *p
; p
++)
2049 if (strncmp (nbuf
, newname
, nlen
))
2050 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2052 for (p
= nbuf
; *p
; p
++)
2055 if (strncmp (nbuf
, newname
, nlen
))
2056 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2061 /* Create a Neon typed/indexed register alias using directives, e.g.:
2066 These typed registers can be used instead of the types specified after the
2067 Neon mnemonic, so long as all operands given have types. Types can also be
2068 specified directly, e.g.:
2069 vadd d0.s32, d1.s32, d2.s32
2073 create_neon_reg_alias (char *newname
, char *p
)
2075 enum arm_reg_type basetype
;
2076 struct reg_entry
*basereg
;
2077 struct reg_entry mybasereg
;
2078 struct neon_type ntype
;
2079 struct neon_typed_alias typeinfo
;
2080 char *namebuf
, *nameend
;
2083 typeinfo
.defined
= 0;
2084 typeinfo
.eltype
.type
= NT_invtype
;
2085 typeinfo
.eltype
.size
= -1;
2086 typeinfo
.index
= -1;
2090 if (strncmp (p
, " .dn ", 5) == 0)
2091 basetype
= REG_TYPE_VFD
;
2092 else if (strncmp (p
, " .qn ", 5) == 0)
2093 basetype
= REG_TYPE_NQ
;
2102 basereg
= arm_reg_parse_multi (&p
);
2104 if (basereg
&& basereg
->type
!= basetype
)
2106 as_bad (_("bad type for register"));
2110 if (basereg
== NULL
)
2113 /* Try parsing as an integer. */
2114 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2115 if (exp
.X_op
!= O_constant
)
2117 as_bad (_("expression must be constant"));
2120 basereg
= &mybasereg
;
2121 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2127 typeinfo
= *basereg
->neon
;
2129 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2131 /* We got a type. */
2132 if (typeinfo
.defined
& NTA_HASTYPE
)
2134 as_bad (_("can't redefine the type of a register alias"));
2138 typeinfo
.defined
|= NTA_HASTYPE
;
2139 if (ntype
.elems
!= 1)
2141 as_bad (_("you must specify a single type only"));
2144 typeinfo
.eltype
= ntype
.el
[0];
2147 if (skip_past_char (&p
, '[') == SUCCESS
)
2150 /* We got a scalar index. */
2152 if (typeinfo
.defined
& NTA_HASINDEX
)
2154 as_bad (_("can't redefine the index of a scalar alias"));
2158 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2160 if (exp
.X_op
!= O_constant
)
2162 as_bad (_("scalar index must be constant"));
2166 typeinfo
.defined
|= NTA_HASINDEX
;
2167 typeinfo
.index
= exp
.X_add_number
;
2169 if (skip_past_char (&p
, ']') == FAIL
)
2171 as_bad (_("expecting ]"));
2176 namelen
= nameend
- newname
;
2177 namebuf
= alloca (namelen
+ 1);
2178 strncpy (namebuf
, newname
, namelen
);
2179 namebuf
[namelen
] = '\0';
2181 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2182 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2184 /* Insert name in all uppercase. */
2185 for (p
= namebuf
; *p
; p
++)
2188 if (strncmp (namebuf
, newname
, namelen
))
2189 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2190 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2192 /* Insert name in all lowercase. */
2193 for (p
= namebuf
; *p
; p
++)
2196 if (strncmp (namebuf
, newname
, namelen
))
2197 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2198 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2203 /* Should never be called, as .req goes between the alias and the
2204 register name, not at the beginning of the line. */
2206 s_req (int a ATTRIBUTE_UNUSED
)
2208 as_bad (_("invalid syntax for .req directive"));
2212 s_dn (int a ATTRIBUTE_UNUSED
)
2214 as_bad (_("invalid syntax for .dn directive"));
2218 s_qn (int a ATTRIBUTE_UNUSED
)
2220 as_bad (_("invalid syntax for .qn directive"));
2223 /* The .unreq directive deletes an alias which was previously defined
2224 by .req. For example:
2230 s_unreq (int a ATTRIBUTE_UNUSED
)
2235 name
= input_line_pointer
;
2237 while (*input_line_pointer
!= 0
2238 && *input_line_pointer
!= ' '
2239 && *input_line_pointer
!= '\n')
2240 ++input_line_pointer
;
2242 saved_char
= *input_line_pointer
;
2243 *input_line_pointer
= 0;
2246 as_bad (_("invalid syntax for .unreq directive"));
2249 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2252 as_bad (_("unknown register alias '%s'"), name
);
2253 else if (reg
->builtin
)
2254 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2258 hash_delete (arm_reg_hsh
, name
);
2259 free ((char *) reg
->name
);
2266 *input_line_pointer
= saved_char
;
2267 demand_empty_rest_of_line ();
2270 /* Directives: Instruction set selection. */
2273 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2274 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2275 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2276 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2278 static enum mstate mapstate
= MAP_UNDEFINED
;
2281 mapping_state (enum mstate state
)
2284 const char * symname
;
2287 if (mapstate
== state
)
2288 /* The mapping symbol has already been emitted.
2289 There is nothing else to do. */
2298 type
= BSF_NO_FLAGS
;
2302 type
= BSF_NO_FLAGS
;
2306 type
= BSF_NO_FLAGS
;
2314 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2316 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2317 symbol_table_insert (symbolP
);
2318 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2323 THUMB_SET_FUNC (symbolP
, 0);
2324 ARM_SET_THUMB (symbolP
, 0);
2325 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2329 THUMB_SET_FUNC (symbolP
, 1);
2330 ARM_SET_THUMB (symbolP
, 1);
2331 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2340 #define mapping_state(x) /* nothing */
2343 /* Find the real, Thumb encoded start of a Thumb function. */
2346 find_real_start (symbolS
* symbolP
)
2349 const char * name
= S_GET_NAME (symbolP
);
2350 symbolS
* new_target
;
2352 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2353 #define STUB_NAME ".real_start_of"
2358 /* The compiler may generate BL instructions to local labels because
2359 it needs to perform a branch to a far away location. These labels
2360 do not have a corresponding ".real_start_of" label. We check
2361 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2362 the ".real_start_of" convention for nonlocal branches. */
2363 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2366 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2367 new_target
= symbol_find (real_start
);
2369 if (new_target
== NULL
)
2371 as_warn ("Failed to find real start of function: %s\n", name
);
2372 new_target
= symbolP
;
2379 opcode_select (int width
)
2386 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2387 as_bad (_("selected processor does not support THUMB opcodes"));
2390 /* No need to force the alignment, since we will have been
2391 coming from ARM mode, which is word-aligned. */
2392 record_alignment (now_seg
, 1);
2394 mapping_state (MAP_THUMB
);
2400 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2401 as_bad (_("selected processor does not support ARM opcodes"));
2406 frag_align (2, 0, 0);
2408 record_alignment (now_seg
, 1);
2410 mapping_state (MAP_ARM
);
2414 as_bad (_("invalid instruction size selected (%d)"), width
);
2419 s_arm (int ignore ATTRIBUTE_UNUSED
)
2422 demand_empty_rest_of_line ();
2426 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2429 demand_empty_rest_of_line ();
2433 s_code (int unused ATTRIBUTE_UNUSED
)
2437 temp
= get_absolute_expression ();
2442 opcode_select (temp
);
2446 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2451 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2453 /* If we are not already in thumb mode go into it, EVEN if
2454 the target processor does not support thumb instructions.
2455 This is used by gcc/config/arm/lib1funcs.asm for example
2456 to compile interworking support functions even if the
2457 target processor should not support interworking. */
2461 record_alignment (now_seg
, 1);
2464 demand_empty_rest_of_line ();
2468 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2472 /* The following label is the name/address of the start of a Thumb function.
2473 We need to know this for the interworking support. */
2474 label_is_thumb_function_name
= TRUE
;
2477 /* Perform a .set directive, but also mark the alias as
2478 being a thumb function. */
2481 s_thumb_set (int equiv
)
2483 /* XXX the following is a duplicate of the code for s_set() in read.c
2484 We cannot just call that code as we need to get at the symbol that
2491 /* Especial apologies for the random logic:
2492 This just grew, and could be parsed much more simply!
2494 name
= input_line_pointer
;
2495 delim
= get_symbol_end ();
2496 end_name
= input_line_pointer
;
2499 if (*input_line_pointer
!= ',')
2502 as_bad (_("expected comma after name \"%s\""), name
);
2504 ignore_rest_of_line ();
2508 input_line_pointer
++;
2511 if (name
[0] == '.' && name
[1] == '\0')
2513 /* XXX - this should not happen to .thumb_set. */
2517 if ((symbolP
= symbol_find (name
)) == NULL
2518 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2521 /* When doing symbol listings, play games with dummy fragments living
2522 outside the normal fragment chain to record the file and line info
2524 if (listing
& LISTING_SYMBOLS
)
2526 extern struct list_info_struct
* listing_tail
;
2527 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2529 memset (dummy_frag
, 0, sizeof (fragS
));
2530 dummy_frag
->fr_type
= rs_fill
;
2531 dummy_frag
->line
= listing_tail
;
2532 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2533 dummy_frag
->fr_symbol
= symbolP
;
2537 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2540 /* "set" symbols are local unless otherwise specified. */
2541 SF_SET_LOCAL (symbolP
);
2542 #endif /* OBJ_COFF */
2543 } /* Make a new symbol. */
2545 symbol_table_insert (symbolP
);
2550 && S_IS_DEFINED (symbolP
)
2551 && S_GET_SEGMENT (symbolP
) != reg_section
)
2552 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2554 pseudo_set (symbolP
);
2556 demand_empty_rest_of_line ();
2558 /* XXX Now we come to the Thumb specific bit of code. */
2560 THUMB_SET_FUNC (symbolP
, 1);
2561 ARM_SET_THUMB (symbolP
, 1);
2562 #if defined OBJ_ELF || defined OBJ_COFF
2563 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2567 /* Directives: Mode selection. */
2569 /* .syntax [unified|divided] - choose the new unified syntax
2570 (same for Arm and Thumb encoding, modulo slight differences in what
2571 can be represented) or the old divergent syntax for each mode. */
2573 s_syntax (int unused ATTRIBUTE_UNUSED
)
2577 name
= input_line_pointer
;
2578 delim
= get_symbol_end ();
2580 if (!strcasecmp (name
, "unified"))
2581 unified_syntax
= TRUE
;
2582 else if (!strcasecmp (name
, "divided"))
2583 unified_syntax
= FALSE
;
2586 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2589 *input_line_pointer
= delim
;
2590 demand_empty_rest_of_line ();
2593 /* Directives: sectioning and alignment. */
2595 /* Same as s_align_ptwo but align 0 => align 2. */
2598 s_align (int unused ATTRIBUTE_UNUSED
)
2602 long max_alignment
= 15;
2604 temp
= get_absolute_expression ();
2605 if (temp
> max_alignment
)
2606 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2609 as_bad (_("alignment negative. 0 assumed."));
2613 if (*input_line_pointer
== ',')
2615 input_line_pointer
++;
2616 temp_fill
= get_absolute_expression ();
2624 /* Only make a frag if we HAVE to. */
2625 if (temp
&& !need_pass_2
)
2626 frag_align (temp
, (int) temp_fill
, 0);
2627 demand_empty_rest_of_line ();
2629 record_alignment (now_seg
, temp
);
2633 s_bss (int ignore ATTRIBUTE_UNUSED
)
2635 /* We don't support putting frags in the BSS segment, we fake it by
2636 marking in_bss, then looking at s_skip for clues. */
2637 subseg_set (bss_section
, 0);
2638 demand_empty_rest_of_line ();
2639 mapping_state (MAP_DATA
);
2643 s_even (int ignore ATTRIBUTE_UNUSED
)
2645 /* Never make frag if expect extra pass. */
2647 frag_align (1, 0, 0);
2649 record_alignment (now_seg
, 1);
2651 demand_empty_rest_of_line ();
2654 /* Directives: Literal pools. */
2656 static literal_pool
*
2657 find_literal_pool (void)
2659 literal_pool
* pool
;
2661 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2663 if (pool
->section
== now_seg
2664 && pool
->sub_section
== now_subseg
)
2671 static literal_pool
*
2672 find_or_make_literal_pool (void)
2674 /* Next literal pool ID number. */
2675 static unsigned int latest_pool_num
= 1;
2676 literal_pool
* pool
;
2678 pool
= find_literal_pool ();
2682 /* Create a new pool. */
2683 pool
= xmalloc (sizeof (* pool
));
2687 pool
->next_free_entry
= 0;
2688 pool
->section
= now_seg
;
2689 pool
->sub_section
= now_subseg
;
2690 pool
->next
= list_of_pools
;
2691 pool
->symbol
= NULL
;
2693 /* Add it to the list. */
2694 list_of_pools
= pool
;
2697 /* New pools, and emptied pools, will have a NULL symbol. */
2698 if (pool
->symbol
== NULL
)
2700 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2701 (valueT
) 0, &zero_address_frag
);
2702 pool
->id
= latest_pool_num
++;
2709 /* Add the literal in the global 'inst'
2710 structure to the relevent literal pool. */
2713 add_to_lit_pool (void)
2715 literal_pool
* pool
;
2718 pool
= find_or_make_literal_pool ();
2720 /* Check if this literal value is already in the pool. */
2721 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2723 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2724 && (inst
.reloc
.exp
.X_op
== O_constant
)
2725 && (pool
->literals
[entry
].X_add_number
2726 == inst
.reloc
.exp
.X_add_number
)
2727 && (pool
->literals
[entry
].X_unsigned
2728 == inst
.reloc
.exp
.X_unsigned
))
2731 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2732 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2733 && (pool
->literals
[entry
].X_add_number
2734 == inst
.reloc
.exp
.X_add_number
)
2735 && (pool
->literals
[entry
].X_add_symbol
2736 == inst
.reloc
.exp
.X_add_symbol
)
2737 && (pool
->literals
[entry
].X_op_symbol
2738 == inst
.reloc
.exp
.X_op_symbol
))
2742 /* Do we need to create a new entry? */
2743 if (entry
== pool
->next_free_entry
)
2745 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2747 inst
.error
= _("literal pool overflow");
2751 pool
->literals
[entry
] = inst
.reloc
.exp
;
2752 pool
->next_free_entry
+= 1;
2755 inst
.reloc
.exp
.X_op
= O_symbol
;
2756 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2757 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2762 /* Can't use symbol_new here, so have to create a symbol and then at
2763 a later date assign it a value. Thats what these functions do. */
2766 symbol_locate (symbolS
* symbolP
,
2767 const char * name
, /* It is copied, the caller can modify. */
2768 segT segment
, /* Segment identifier (SEG_<something>). */
2769 valueT valu
, /* Symbol value. */
2770 fragS
* frag
) /* Associated fragment. */
2772 unsigned int name_length
;
2773 char * preserved_copy_of_name
;
2775 name_length
= strlen (name
) + 1; /* +1 for \0. */
2776 obstack_grow (¬es
, name
, name_length
);
2777 preserved_copy_of_name
= obstack_finish (¬es
);
2779 #ifdef tc_canonicalize_symbol_name
2780 preserved_copy_of_name
=
2781 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2784 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2786 S_SET_SEGMENT (symbolP
, segment
);
2787 S_SET_VALUE (symbolP
, valu
);
2788 symbol_clear_list_pointers (symbolP
);
2790 symbol_set_frag (symbolP
, frag
);
2792 /* Link to end of symbol chain. */
2794 extern int symbol_table_frozen
;
2796 if (symbol_table_frozen
)
2800 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2802 obj_symbol_new_hook (symbolP
);
2804 #ifdef tc_symbol_new_hook
2805 tc_symbol_new_hook (symbolP
);
2809 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2810 #endif /* DEBUG_SYMS */
2815 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2818 literal_pool
* pool
;
2821 pool
= find_literal_pool ();
2823 || pool
->symbol
== NULL
2824 || pool
->next_free_entry
== 0)
2827 mapping_state (MAP_DATA
);
2829 /* Align pool as you have word accesses.
2830 Only make a frag if we have to. */
2832 frag_align (2, 0, 0);
2834 record_alignment (now_seg
, 2);
2836 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2838 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2839 (valueT
) frag_now_fix (), frag_now
);
2840 symbol_table_insert (pool
->symbol
);
2842 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2844 #if defined OBJ_COFF || defined OBJ_ELF
2845 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2848 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2849 /* First output the expression in the instruction to the pool. */
2850 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2852 /* Mark the pool as empty. */
2853 pool
->next_free_entry
= 0;
2854 pool
->symbol
= NULL
;
2858 /* Forward declarations for functions below, in the MD interface
2860 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2861 static valueT
create_unwind_entry (int);
2862 static void start_unwind_section (const segT
, int);
2863 static void add_unwind_opcode (valueT
, int);
2864 static void flush_pending_unwind (void);
2866 /* Directives: Data. */
2869 s_arm_elf_cons (int nbytes
)
2873 #ifdef md_flush_pending_output
2874 md_flush_pending_output ();
2877 if (is_it_end_of_statement ())
2879 demand_empty_rest_of_line ();
2883 #ifdef md_cons_align
2884 md_cons_align (nbytes
);
2887 mapping_state (MAP_DATA
);
2891 char *base
= input_line_pointer
;
2895 if (exp
.X_op
!= O_symbol
)
2896 emit_expr (&exp
, (unsigned int) nbytes
);
2899 char *before_reloc
= input_line_pointer
;
2900 reloc
= parse_reloc (&input_line_pointer
);
2903 as_bad (_("unrecognized relocation suffix"));
2904 ignore_rest_of_line ();
2907 else if (reloc
== BFD_RELOC_UNUSED
)
2908 emit_expr (&exp
, (unsigned int) nbytes
);
2911 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2912 int size
= bfd_get_reloc_size (howto
);
2914 if (reloc
== BFD_RELOC_ARM_PLT32
)
2916 as_bad (_("(plt) is only valid on branch targets"));
2917 reloc
= BFD_RELOC_UNUSED
;
2922 as_bad (_("%s relocations do not fit in %d bytes"),
2923 howto
->name
, nbytes
);
2926 /* We've parsed an expression stopping at O_symbol.
2927 But there may be more expression left now that we
2928 have parsed the relocation marker. Parse it again.
2929 XXX Surely there is a cleaner way to do this. */
2930 char *p
= input_line_pointer
;
2932 char *save_buf
= alloca (input_line_pointer
- base
);
2933 memcpy (save_buf
, base
, input_line_pointer
- base
);
2934 memmove (base
+ (input_line_pointer
- before_reloc
),
2935 base
, before_reloc
- base
);
2937 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
2939 memcpy (base
, save_buf
, p
- base
);
2941 offset
= nbytes
- size
;
2942 p
= frag_more ((int) nbytes
);
2943 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
2944 size
, &exp
, 0, reloc
);
2949 while (*input_line_pointer
++ == ',');
2951 /* Put terminator back into stream. */
2952 input_line_pointer
--;
2953 demand_empty_rest_of_line ();
2957 /* Parse a .rel31 directive. */
2960 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
2967 if (*input_line_pointer
== '1')
2968 highbit
= 0x80000000;
2969 else if (*input_line_pointer
!= '0')
2970 as_bad (_("expected 0 or 1"));
2972 input_line_pointer
++;
2973 if (*input_line_pointer
!= ',')
2974 as_bad (_("missing comma"));
2975 input_line_pointer
++;
2977 #ifdef md_flush_pending_output
2978 md_flush_pending_output ();
2981 #ifdef md_cons_align
2985 mapping_state (MAP_DATA
);
2990 md_number_to_chars (p
, highbit
, 4);
2991 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
2992 BFD_RELOC_ARM_PREL31
);
2994 demand_empty_rest_of_line ();
2997 /* Directives: AEABI stack-unwind tables. */
2999 /* Parse an unwind_fnstart directive. Simply records the current location. */
3002 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3004 demand_empty_rest_of_line ();
3005 /* Mark the start of the function. */
3006 unwind
.proc_start
= expr_build_dot ();
3008 /* Reset the rest of the unwind info. */
3009 unwind
.opcode_count
= 0;
3010 unwind
.table_entry
= NULL
;
3011 unwind
.personality_routine
= NULL
;
3012 unwind
.personality_index
= -1;
3013 unwind
.frame_size
= 0;
3014 unwind
.fp_offset
= 0;
3017 unwind
.sp_restored
= 0;
3021 /* Parse a handlerdata directive. Creates the exception handling table entry
3022 for the function. */
3025 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3027 demand_empty_rest_of_line ();
3028 if (unwind
.table_entry
)
3029 as_bad (_("dupicate .handlerdata directive"));
3031 create_unwind_entry (1);
3034 /* Parse an unwind_fnend directive. Generates the index table entry. */
3037 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3043 demand_empty_rest_of_line ();
3045 /* Add eh table entry. */
3046 if (unwind
.table_entry
== NULL
)
3047 val
= create_unwind_entry (0);
3051 /* Add index table entry. This is two words. */
3052 start_unwind_section (unwind
.saved_seg
, 1);
3053 frag_align (2, 0, 0);
3054 record_alignment (now_seg
, 2);
3056 ptr
= frag_more (8);
3057 where
= frag_now_fix () - 8;
3059 /* Self relative offset of the function start. */
3060 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3061 BFD_RELOC_ARM_PREL31
);
3063 /* Indicate dependency on EHABI-defined personality routines to the
3064 linker, if it hasn't been done already. */
3065 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3066 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3068 static const char *const name
[] = {
3069 "__aeabi_unwind_cpp_pr0",
3070 "__aeabi_unwind_cpp_pr1",
3071 "__aeabi_unwind_cpp_pr2"
3073 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3074 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3075 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3076 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3077 = marked_pr_dependency
;
3081 /* Inline exception table entry. */
3082 md_number_to_chars (ptr
+ 4, val
, 4);
3084 /* Self relative offset of the table entry. */
3085 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3086 BFD_RELOC_ARM_PREL31
);
3088 /* Restore the original section. */
3089 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3093 /* Parse an unwind_cantunwind directive. */
3096 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3098 demand_empty_rest_of_line ();
3099 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3100 as_bad (_("personality routine specified for cantunwind frame"));
3102 unwind
.personality_index
= -2;
3106 /* Parse a personalityindex directive. */
3109 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3113 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3114 as_bad (_("duplicate .personalityindex directive"));
3118 if (exp
.X_op
!= O_constant
3119 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3121 as_bad (_("bad personality routine number"));
3122 ignore_rest_of_line ();
3126 unwind
.personality_index
= exp
.X_add_number
;
3128 demand_empty_rest_of_line ();
3132 /* Parse a personality directive. */
3135 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3139 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3140 as_bad (_("duplicate .personality directive"));
3142 name
= input_line_pointer
;
3143 c
= get_symbol_end ();
3144 p
= input_line_pointer
;
3145 unwind
.personality_routine
= symbol_find_or_make (name
);
3147 demand_empty_rest_of_line ();
3151 /* Parse a directive saving core registers. */
3154 s_arm_unwind_save_core (void)
3160 range
= parse_reg_list (&input_line_pointer
);
3163 as_bad (_("expected register list"));
3164 ignore_rest_of_line ();
3168 demand_empty_rest_of_line ();
3170 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3171 into .unwind_save {..., sp...}. We aren't bothered about the value of
3172 ip because it is clobbered by calls. */
3173 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3174 && (range
& 0x3000) == 0x1000)
3176 unwind
.opcode_count
--;
3177 unwind
.sp_restored
= 0;
3178 range
= (range
| 0x2000) & ~0x1000;
3179 unwind
.pending_offset
= 0;
3185 /* See if we can use the short opcodes. These pop a block of up to 8
3186 registers starting with r4, plus maybe r14. */
3187 for (n
= 0; n
< 8; n
++)
3189 /* Break at the first non-saved register. */
3190 if ((range
& (1 << (n
+ 4))) == 0)
3193 /* See if there are any other bits set. */
3194 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3196 /* Use the long form. */
3197 op
= 0x8000 | ((range
>> 4) & 0xfff);
3198 add_unwind_opcode (op
, 2);
3202 /* Use the short form. */
3204 op
= 0xa8; /* Pop r14. */
3206 op
= 0xa0; /* Do not pop r14. */
3208 add_unwind_opcode (op
, 1);
3215 op
= 0xb100 | (range
& 0xf);
3216 add_unwind_opcode (op
, 2);
3219 /* Record the number of bytes pushed. */
3220 for (n
= 0; n
< 16; n
++)
3222 if (range
& (1 << n
))
3223 unwind
.frame_size
+= 4;
3228 /* Parse a directive saving FPA registers. */
3231 s_arm_unwind_save_fpa (int reg
)
3237 /* Get Number of registers to transfer. */
3238 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3241 exp
.X_op
= O_illegal
;
3243 if (exp
.X_op
!= O_constant
)
3245 as_bad (_("expected , <constant>"));
3246 ignore_rest_of_line ();
3250 num_regs
= exp
.X_add_number
;
3252 if (num_regs
< 1 || num_regs
> 4)
3254 as_bad (_("number of registers must be in the range [1:4]"));
3255 ignore_rest_of_line ();
3259 demand_empty_rest_of_line ();
3264 op
= 0xb4 | (num_regs
- 1);
3265 add_unwind_opcode (op
, 1);
3270 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3271 add_unwind_opcode (op
, 2);
3273 unwind
.frame_size
+= num_regs
* 12;
3277 /* Parse a directive saving VFP registers for ARMv6 and above. */
3280 s_arm_unwind_save_vfp_armv6 (void)
3285 int num_vfpv3_regs
= 0;
3286 int num_regs_below_16
;
3288 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3291 as_bad (_("expected register list"));
3292 ignore_rest_of_line ();
3296 demand_empty_rest_of_line ();
3298 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3299 than FSTMX/FLDMX-style ones). */
3301 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3303 num_vfpv3_regs
= count
;
3304 else if (start
+ count
> 16)
3305 num_vfpv3_regs
= start
+ count
- 16;
3307 if (num_vfpv3_regs
> 0)
3309 int start_offset
= start
> 16 ? start
- 16 : 0;
3310 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3311 add_unwind_opcode (op
, 2);
3314 /* Generate opcode for registers numbered in the range 0 .. 15. */
3315 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3316 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3317 if (num_regs_below_16
> 0)
3319 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3320 add_unwind_opcode (op
, 2);
3323 unwind
.frame_size
+= count
* 8;
3327 /* Parse a directive saving VFP registers for pre-ARMv6. */
3330 s_arm_unwind_save_vfp (void)
3336 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3339 as_bad (_("expected register list"));
3340 ignore_rest_of_line ();
3344 demand_empty_rest_of_line ();
3349 op
= 0xb8 | (count
- 1);
3350 add_unwind_opcode (op
, 1);
3355 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3356 add_unwind_opcode (op
, 2);
3358 unwind
.frame_size
+= count
* 8 + 4;
3362 /* Parse a directive saving iWMMXt data registers. */
3365 s_arm_unwind_save_mmxwr (void)
3373 if (*input_line_pointer
== '{')
3374 input_line_pointer
++;
3378 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3382 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3387 as_tsktsk (_("register list not in ascending order"));
3390 if (*input_line_pointer
== '-')
3392 input_line_pointer
++;
3393 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3396 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3399 else if (reg
>= hi_reg
)
3401 as_bad (_("bad register range"));
3404 for (; reg
< hi_reg
; reg
++)
3408 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3410 if (*input_line_pointer
== '}')
3411 input_line_pointer
++;
3413 demand_empty_rest_of_line ();
3415 /* Generate any deferred opcodes because we're going to be looking at
3417 flush_pending_unwind ();
3419 for (i
= 0; i
< 16; i
++)
3421 if (mask
& (1 << i
))
3422 unwind
.frame_size
+= 8;
3425 /* Attempt to combine with a previous opcode. We do this because gcc
3426 likes to output separate unwind directives for a single block of
3428 if (unwind
.opcode_count
> 0)
3430 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3431 if ((i
& 0xf8) == 0xc0)
3434 /* Only merge if the blocks are contiguous. */
3437 if ((mask
& 0xfe00) == (1 << 9))
3439 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3440 unwind
.opcode_count
--;
3443 else if (i
== 6 && unwind
.opcode_count
>= 2)
3445 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3449 op
= 0xffff << (reg
- 1);
3451 || ((mask
& op
) == (1u << (reg
- 1))))
3453 op
= (1 << (reg
+ i
+ 1)) - 1;
3454 op
&= ~((1 << reg
) - 1);
3456 unwind
.opcode_count
-= 2;
3463 /* We want to generate opcodes in the order the registers have been
3464 saved, ie. descending order. */
3465 for (reg
= 15; reg
>= -1; reg
--)
3467 /* Save registers in blocks. */
3469 || !(mask
& (1 << reg
)))
3471 /* We found an unsaved reg. Generate opcodes to save the
3472 preceeding block. */
3478 op
= 0xc0 | (hi_reg
- 10);
3479 add_unwind_opcode (op
, 1);
3484 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3485 add_unwind_opcode (op
, 2);
3494 ignore_rest_of_line ();
3498 s_arm_unwind_save_mmxwcg (void)
3505 if (*input_line_pointer
== '{')
3506 input_line_pointer
++;
3510 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3514 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3520 as_tsktsk (_("register list not in ascending order"));
3523 if (*input_line_pointer
== '-')
3525 input_line_pointer
++;
3526 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3529 as_bad (_(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3532 else if (reg
>= hi_reg
)
3534 as_bad (_("bad register range"));
3537 for (; reg
< hi_reg
; reg
++)
3541 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3543 if (*input_line_pointer
== '}')
3544 input_line_pointer
++;
3546 demand_empty_rest_of_line ();
3548 /* Generate any deferred opcodes because we're going to be looking at
3550 flush_pending_unwind ();
3552 for (reg
= 0; reg
< 16; reg
++)
3554 if (mask
& (1 << reg
))
3555 unwind
.frame_size
+= 4;
3558 add_unwind_opcode (op
, 2);
3561 ignore_rest_of_line ();
3565 /* Parse an unwind_save directive.
3566 If the argument is non-zero, this is a .vsave directive. */
3569 s_arm_unwind_save (int arch_v6
)
3572 struct reg_entry
*reg
;
3573 bfd_boolean had_brace
= FALSE
;
3575 /* Figure out what sort of save we have. */
3576 peek
= input_line_pointer
;
3584 reg
= arm_reg_parse_multi (&peek
);
3588 as_bad (_("register expected"));
3589 ignore_rest_of_line ();
3598 as_bad (_("FPA .unwind_save does not take a register list"));
3599 ignore_rest_of_line ();
3602 s_arm_unwind_save_fpa (reg
->number
);
3605 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3608 s_arm_unwind_save_vfp_armv6 ();
3610 s_arm_unwind_save_vfp ();
3612 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3613 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3616 as_bad (_(".unwind_save does not support this kind of register"));
3617 ignore_rest_of_line ();
3622 /* Parse an unwind_movsp directive. */
3625 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3630 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3633 as_bad (_(reg_expected_msgs
[REG_TYPE_RN
]));
3634 ignore_rest_of_line ();
3637 demand_empty_rest_of_line ();
3639 if (reg
== REG_SP
|| reg
== REG_PC
)
3641 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3645 if (unwind
.fp_reg
!= REG_SP
)
3646 as_bad (_("unexpected .unwind_movsp directive"));
3648 /* Generate opcode to restore the value. */
3650 add_unwind_opcode (op
, 1);
3652 /* Record the information for later. */
3653 unwind
.fp_reg
= reg
;
3654 unwind
.fp_offset
= unwind
.frame_size
;
3655 unwind
.sp_restored
= 1;
3658 /* Parse an unwind_pad directive. */
3661 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3665 if (immediate_for_directive (&offset
) == FAIL
)
3670 as_bad (_("stack increment must be multiple of 4"));
3671 ignore_rest_of_line ();
3675 /* Don't generate any opcodes, just record the details for later. */
3676 unwind
.frame_size
+= offset
;
3677 unwind
.pending_offset
+= offset
;
3679 demand_empty_rest_of_line ();
3682 /* Parse an unwind_setfp directive. */
3685 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3691 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3692 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3695 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3697 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3699 as_bad (_("expected <reg>, <reg>"));
3700 ignore_rest_of_line ();
3704 /* Optional constant. */
3705 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3707 if (immediate_for_directive (&offset
) == FAIL
)
3713 demand_empty_rest_of_line ();
3715 if (sp_reg
!= 13 && sp_reg
!= unwind
.fp_reg
)
3717 as_bad (_("register must be either sp or set by a previous"
3718 "unwind_movsp directive"));
3722 /* Don't generate any opcodes, just record the information for later. */
3723 unwind
.fp_reg
= fp_reg
;
3726 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3728 unwind
.fp_offset
-= offset
;
3731 /* Parse an unwind_raw directive. */
3734 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3737 /* This is an arbitrary limit. */
3738 unsigned char op
[16];
3742 if (exp
.X_op
== O_constant
3743 && skip_past_comma (&input_line_pointer
) != FAIL
)
3745 unwind
.frame_size
+= exp
.X_add_number
;
3749 exp
.X_op
= O_illegal
;
3751 if (exp
.X_op
!= O_constant
)
3753 as_bad (_("expected <offset>, <opcode>"));
3754 ignore_rest_of_line ();
3760 /* Parse the opcode. */
3765 as_bad (_("unwind opcode too long"));
3766 ignore_rest_of_line ();
3768 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3770 as_bad (_("invalid unwind opcode"));
3771 ignore_rest_of_line ();
3774 op
[count
++] = exp
.X_add_number
;
3776 /* Parse the next byte. */
3777 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3783 /* Add the opcode bytes in reverse order. */
3785 add_unwind_opcode (op
[count
], 1);
3787 demand_empty_rest_of_line ();
3791 /* Parse a .eabi_attribute directive. */
3794 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3797 bfd_boolean is_string
;
3804 if (exp
.X_op
!= O_constant
)
3807 tag
= exp
.X_add_number
;
3808 if (tag
== 4 || tag
== 5 || tag
== 32 || (tag
> 32 && (tag
& 1) != 0))
3813 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3815 if (tag
== 32 || !is_string
)
3818 if (exp
.X_op
!= O_constant
)
3820 as_bad (_("expected numeric constant"));
3821 ignore_rest_of_line ();
3824 i
= exp
.X_add_number
;
3826 if (tag
== Tag_compatibility
3827 && skip_past_comma (&input_line_pointer
) == FAIL
)
3829 as_bad (_("expected comma"));
3830 ignore_rest_of_line ();
3835 skip_whitespace(input_line_pointer
);
3836 if (*input_line_pointer
!= '"')
3838 input_line_pointer
++;
3839 s
= input_line_pointer
;
3840 while (*input_line_pointer
&& *input_line_pointer
!= '"')
3841 input_line_pointer
++;
3842 if (*input_line_pointer
!= '"')
3844 saved_char
= *input_line_pointer
;
3845 *input_line_pointer
= 0;
3853 if (tag
== Tag_compatibility
)
3854 elf32_arm_add_eabi_attr_compat (stdoutput
, i
, s
);
3856 elf32_arm_add_eabi_attr_string (stdoutput
, tag
, s
);
3858 elf32_arm_add_eabi_attr_int (stdoutput
, tag
, i
);
3862 *input_line_pointer
= saved_char
;
3863 input_line_pointer
++;
3865 demand_empty_rest_of_line ();
3868 as_bad (_("bad string constant"));
3869 ignore_rest_of_line ();
3872 as_bad (_("expected <tag> , <value>"));
3873 ignore_rest_of_line ();
3875 #endif /* OBJ_ELF */
3877 static void s_arm_arch (int);
3878 static void s_arm_cpu (int);
3879 static void s_arm_fpu (int);
3884 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3891 if (exp
.X_op
== O_symbol
)
3892 exp
.X_op
= O_secrel
;
3894 emit_expr (&exp
, 4);
3896 while (*input_line_pointer
++ == ',');
3898 input_line_pointer
--;
3899 demand_empty_rest_of_line ();
3903 /* This table describes all the machine specific pseudo-ops the assembler
3904 has to support. The fields are:
3905 pseudo-op name without dot
3906 function to call to execute this pseudo-op
3907 Integer arg to pass to the function. */
3909 const pseudo_typeS md_pseudo_table
[] =
3911 /* Never called because '.req' does not start a line. */
3912 { "req", s_req
, 0 },
3913 /* Following two are likewise never called. */
3916 { "unreq", s_unreq
, 0 },
3917 { "bss", s_bss
, 0 },
3918 { "align", s_align
, 0 },
3919 { "arm", s_arm
, 0 },
3920 { "thumb", s_thumb
, 0 },
3921 { "code", s_code
, 0 },
3922 { "force_thumb", s_force_thumb
, 0 },
3923 { "thumb_func", s_thumb_func
, 0 },
3924 { "thumb_set", s_thumb_set
, 0 },
3925 { "even", s_even
, 0 },
3926 { "ltorg", s_ltorg
, 0 },
3927 { "pool", s_ltorg
, 0 },
3928 { "syntax", s_syntax
, 0 },
3929 { "cpu", s_arm_cpu
, 0 },
3930 { "arch", s_arm_arch
, 0 },
3931 { "fpu", s_arm_fpu
, 0 },
3933 { "word", s_arm_elf_cons
, 4 },
3934 { "long", s_arm_elf_cons
, 4 },
3935 { "rel31", s_arm_rel31
, 0 },
3936 { "fnstart", s_arm_unwind_fnstart
, 0 },
3937 { "fnend", s_arm_unwind_fnend
, 0 },
3938 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3939 { "personality", s_arm_unwind_personality
, 0 },
3940 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3941 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3942 { "save", s_arm_unwind_save
, 0 },
3943 { "vsave", s_arm_unwind_save
, 1 },
3944 { "movsp", s_arm_unwind_movsp
, 0 },
3945 { "pad", s_arm_unwind_pad
, 0 },
3946 { "setfp", s_arm_unwind_setfp
, 0 },
3947 { "unwind_raw", s_arm_unwind_raw
, 0 },
3948 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3952 /* These are used for dwarf. */
3956 /* These are used for dwarf2. */
3957 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3958 { "loc", dwarf2_directive_loc
, 0 },
3959 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3961 { "extend", float_cons
, 'x' },
3962 { "ldouble", float_cons
, 'x' },
3963 { "packed", float_cons
, 'p' },
3965 {"secrel32", pe_directive_secrel
, 0},
3970 /* Parser functions used exclusively in instruction operands. */
3972 /* Generic immediate-value read function for use in insn parsing.
3973 STR points to the beginning of the immediate (the leading #);
3974 VAL receives the value; if the value is outside [MIN, MAX]
3975 issue an error. PREFIX_OPT is true if the immediate prefix is
3979 parse_immediate (char **str
, int *val
, int min
, int max
,
3980 bfd_boolean prefix_opt
)
3983 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
3984 if (exp
.X_op
!= O_constant
)
3986 inst
.error
= _("constant expression required");
3990 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
3992 inst
.error
= _("immediate value out of range");
3996 *val
= exp
.X_add_number
;
4000 /* Less-generic immediate-value read function with the possibility of loading a
4001 big (64-bit) immediate, as required by Neon VMOV and VMVN immediate
4002 instructions. Puts the result directly in inst.operands[i]. */
4005 parse_big_immediate (char **str
, int i
)
4010 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4012 if (exp
.X_op
== O_constant
)
4013 inst
.operands
[i
].imm
= exp
.X_add_number
;
4014 else if (exp
.X_op
== O_big
4015 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4016 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4018 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4019 /* Bignums have their least significant bits in
4020 generic_bignum[0]. Make sure we put 32 bits in imm and
4021 32 bits in reg, in a (hopefully) portable way. */
4022 assert (parts
!= 0);
4023 inst
.operands
[i
].imm
= 0;
4024 for (j
= 0; j
< parts
; j
++, idx
++)
4025 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4026 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4027 inst
.operands
[i
].reg
= 0;
4028 for (j
= 0; j
< parts
; j
++, idx
++)
4029 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4030 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4031 inst
.operands
[i
].regisimm
= 1;
4041 /* Returns the pseudo-register number of an FPA immediate constant,
4042 or FAIL if there isn't a valid constant here. */
4045 parse_fpa_immediate (char ** str
)
4047 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4053 /* First try and match exact strings, this is to guarantee
4054 that some formats will work even for cross assembly. */
4056 for (i
= 0; fp_const
[i
]; i
++)
4058 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4062 *str
+= strlen (fp_const
[i
]);
4063 if (is_end_of_line
[(unsigned char) **str
])
4069 /* Just because we didn't get a match doesn't mean that the constant
4070 isn't valid, just that it is in a format that we don't
4071 automatically recognize. Try parsing it with the standard
4072 expression routines. */
4074 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4076 /* Look for a raw floating point number. */
4077 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4078 && is_end_of_line
[(unsigned char) *save_in
])
4080 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4082 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4084 if (words
[j
] != fp_values
[i
][j
])
4088 if (j
== MAX_LITTLENUMS
)
4096 /* Try and parse a more complex expression, this will probably fail
4097 unless the code uses a floating point prefix (eg "0f"). */
4098 save_in
= input_line_pointer
;
4099 input_line_pointer
= *str
;
4100 if (expression (&exp
) == absolute_section
4101 && exp
.X_op
== O_big
4102 && exp
.X_add_number
< 0)
4104 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4106 if (gen_to_words (words
, 5, (long) 15) == 0)
4108 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4110 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4112 if (words
[j
] != fp_values
[i
][j
])
4116 if (j
== MAX_LITTLENUMS
)
4118 *str
= input_line_pointer
;
4119 input_line_pointer
= save_in
;
4126 *str
= input_line_pointer
;
4127 input_line_pointer
= save_in
;
4128 inst
.error
= _("invalid FPA immediate expression");
4132 /* Returns 1 if a number has "quarter-precision" float format
4133 0baBbbbbbc defgh000 00000000 00000000. */
4136 is_quarter_float (unsigned imm
)
4138 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4139 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4142 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4143 0baBbbbbbc defgh000 00000000 00000000.
4144 The minus-zero case needs special handling, since it can't be encoded in the
4145 "quarter-precision" float format, but can nonetheless be loaded as an integer
4149 parse_qfloat_immediate (char **ccp
, int *immed
)
4152 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4154 skip_past_char (&str
, '#');
4156 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4158 unsigned fpword
= 0;
4161 /* Our FP word must be 32 bits (single-precision FP). */
4162 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4164 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4168 if (is_quarter_float (fpword
) || fpword
== 0x80000000)
4181 /* Shift operands. */
4184 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4187 struct asm_shift_name
4190 enum shift_kind kind
;
4193 /* Third argument to parse_shift. */
4194 enum parse_shift_mode
4196 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4197 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4198 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4199 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4200 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4203 /* Parse a <shift> specifier on an ARM data processing instruction.
4204 This has three forms:
4206 (LSL|LSR|ASL|ASR|ROR) Rs
4207 (LSL|LSR|ASL|ASR|ROR) #imm
4210 Note that ASL is assimilated to LSL in the instruction encoding, and
4211 RRX to ROR #0 (which cannot be written as such). */
4214 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4216 const struct asm_shift_name
*shift_name
;
4217 enum shift_kind shift
;
4222 for (p
= *str
; ISALPHA (*p
); p
++)
4227 inst
.error
= _("shift expression expected");
4231 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4233 if (shift_name
== NULL
)
4235 inst
.error
= _("shift expression expected");
4239 shift
= shift_name
->kind
;
4243 case NO_SHIFT_RESTRICT
:
4244 case SHIFT_IMMEDIATE
: break;
4246 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4247 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4249 inst
.error
= _("'LSL' or 'ASR' required");
4254 case SHIFT_LSL_IMMEDIATE
:
4255 if (shift
!= SHIFT_LSL
)
4257 inst
.error
= _("'LSL' required");
4262 case SHIFT_ASR_IMMEDIATE
:
4263 if (shift
!= SHIFT_ASR
)
4265 inst
.error
= _("'ASR' required");
4273 if (shift
!= SHIFT_RRX
)
4275 /* Whitespace can appear here if the next thing is a bare digit. */
4276 skip_whitespace (p
);
4278 if (mode
== NO_SHIFT_RESTRICT
4279 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4281 inst
.operands
[i
].imm
= reg
;
4282 inst
.operands
[i
].immisreg
= 1;
4284 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4287 inst
.operands
[i
].shift_kind
= shift
;
4288 inst
.operands
[i
].shifted
= 1;
4293 /* Parse a <shifter_operand> for an ARM data processing instruction:
4296 #<immediate>, <rotate>
4300 where <shift> is defined by parse_shift above, and <rotate> is a
4301 multiple of 2 between 0 and 30. Validation of immediate operands
4302 is deferred to md_apply_fix. */
4305 parse_shifter_operand (char **str
, int i
)
4310 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4312 inst
.operands
[i
].reg
= value
;
4313 inst
.operands
[i
].isreg
= 1;
4315 /* parse_shift will override this if appropriate */
4316 inst
.reloc
.exp
.X_op
= O_constant
;
4317 inst
.reloc
.exp
.X_add_number
= 0;
4319 if (skip_past_comma (str
) == FAIL
)
4322 /* Shift operation on register. */
4323 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4326 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4329 if (skip_past_comma (str
) == SUCCESS
)
4331 /* #x, y -- ie explicit rotation by Y. */
4332 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4335 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4337 inst
.error
= _("constant expression expected");
4341 value
= expr
.X_add_number
;
4342 if (value
< 0 || value
> 30 || value
% 2 != 0)
4344 inst
.error
= _("invalid rotation");
4347 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4349 inst
.error
= _("invalid constant");
4353 /* Convert to decoded value. md_apply_fix will put it back. */
4354 inst
.reloc
.exp
.X_add_number
4355 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4356 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4359 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4360 inst
.reloc
.pc_rel
= 0;
4364 /* Group relocation information. Each entry in the table contains the
4365 textual name of the relocation as may appear in assembler source
4366 and must end with a colon.
4367 Along with this textual name are the relocation codes to be used if
4368 the corresponding instruction is an ALU instruction (ADD or SUB only),
4369 an LDR, an LDRS, or an LDC. */
4371 struct group_reloc_table_entry
4382 /* Varieties of non-ALU group relocation. */
4389 static struct group_reloc_table_entry group_reloc_table
[] =
4390 { /* Program counter relative: */
4392 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4397 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4398 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4399 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4400 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4402 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4407 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4408 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4409 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4410 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4412 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4413 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4414 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4415 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4416 /* Section base relative */
4418 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4423 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4424 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4425 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4426 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4428 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4433 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4434 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4435 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4436 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4438 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4439 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4440 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4441 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4443 /* Given the address of a pointer pointing to the textual name of a group
4444 relocation as may appear in assembler source, attempt to find its details
4445 in group_reloc_table. The pointer will be updated to the character after
4446 the trailing colon. On failure, FAIL will be returned; SUCCESS
4447 otherwise. On success, *entry will be updated to point at the relevant
4448 group_reloc_table entry. */
4451 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4454 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4456 int length
= strlen (group_reloc_table
[i
].name
);
4458 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0 &&
4459 (*str
)[length
] == ':')
4461 *out
= &group_reloc_table
[i
];
4462 *str
+= (length
+ 1);
4470 /* Parse a <shifter_operand> for an ARM data processing instruction
4471 (as for parse_shifter_operand) where group relocations are allowed:
4474 #<immediate>, <rotate>
4475 #:<group_reloc>:<expression>
4479 where <group_reloc> is one of the strings defined in group_reloc_table.
4480 The hashes are optional.
4482 Everything else is as for parse_shifter_operand. */
4484 static parse_operand_result
4485 parse_shifter_operand_group_reloc (char **str
, int i
)
4487 /* Determine if we have the sequence of characters #: or just :
4488 coming next. If we do, then we check for a group relocation.
4489 If we don't, punt the whole lot to parse_shifter_operand. */
4491 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4492 || (*str
)[0] == ':')
4494 struct group_reloc_table_entry
*entry
;
4496 if ((*str
)[0] == '#')
4501 /* Try to parse a group relocation. Anything else is an error. */
4502 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4504 inst
.error
= _("unknown group relocation");
4505 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4508 /* We now have the group relocation table entry corresponding to
4509 the name in the assembler source. Next, we parse the expression. */
4510 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4511 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4513 /* Record the relocation type (always the ALU variant here). */
4514 inst
.reloc
.type
= entry
->alu_code
;
4515 assert (inst
.reloc
.type
!= 0);
4517 return PARSE_OPERAND_SUCCESS
;
4520 return parse_shifter_operand (str
, i
) == SUCCESS
4521 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4523 /* Never reached. */
4526 /* Parse all forms of an ARM address expression. Information is written
4527 to inst.operands[i] and/or inst.reloc.
4529 Preindexed addressing (.preind=1):
4531 [Rn, #offset] .reg=Rn .reloc.exp=offset
4532 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4533 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4534 .shift_kind=shift .reloc.exp=shift_imm
4536 These three may have a trailing ! which causes .writeback to be set also.
4538 Postindexed addressing (.postind=1, .writeback=1):
4540 [Rn], #offset .reg=Rn .reloc.exp=offset
4541 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4542 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4543 .shift_kind=shift .reloc.exp=shift_imm
4545 Unindexed addressing (.preind=0, .postind=0):
4547 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4551 [Rn]{!} shorthand for [Rn,#0]{!}
4552 =immediate .isreg=0 .reloc.exp=immediate
4553 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4555 It is the caller's responsibility to check for addressing modes not
4556 supported by the instruction, and to set inst.reloc.type. */
4558 static parse_operand_result
4559 parse_address_main (char **str
, int i
, int group_relocations
,
4560 group_reloc_type group_type
)
4565 if (skip_past_char (&p
, '[') == FAIL
)
4567 if (skip_past_char (&p
, '=') == FAIL
)
4569 /* bare address - translate to PC-relative offset */
4570 inst
.reloc
.pc_rel
= 1;
4571 inst
.operands
[i
].reg
= REG_PC
;
4572 inst
.operands
[i
].isreg
= 1;
4573 inst
.operands
[i
].preind
= 1;
4575 /* else a load-constant pseudo op, no special treatment needed here */
4577 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4578 return PARSE_OPERAND_FAIL
;
4581 return PARSE_OPERAND_SUCCESS
;
4584 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4586 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4587 return PARSE_OPERAND_FAIL
;
4589 inst
.operands
[i
].reg
= reg
;
4590 inst
.operands
[i
].isreg
= 1;
4592 if (skip_past_comma (&p
) == SUCCESS
)
4594 inst
.operands
[i
].preind
= 1;
4597 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4599 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4601 inst
.operands
[i
].imm
= reg
;
4602 inst
.operands
[i
].immisreg
= 1;
4604 if (skip_past_comma (&p
) == SUCCESS
)
4605 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4606 return PARSE_OPERAND_FAIL
;
4608 else if (skip_past_char (&p
, ':') == SUCCESS
)
4610 /* FIXME: '@' should be used here, but it's filtered out by generic
4611 code before we get to see it here. This may be subject to
4614 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4615 if (exp
.X_op
!= O_constant
)
4617 inst
.error
= _("alignment must be constant");
4618 return PARSE_OPERAND_FAIL
;
4620 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4621 inst
.operands
[i
].immisalign
= 1;
4622 /* Alignments are not pre-indexes. */
4623 inst
.operands
[i
].preind
= 0;
4627 if (inst
.operands
[i
].negative
)
4629 inst
.operands
[i
].negative
= 0;
4633 if (group_relocations
&&
4634 ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4637 struct group_reloc_table_entry
*entry
;
4639 /* Skip over the #: or : sequence. */
4645 /* Try to parse a group relocation. Anything else is an
4647 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4649 inst
.error
= _("unknown group relocation");
4650 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4653 /* We now have the group relocation table entry corresponding to
4654 the name in the assembler source. Next, we parse the
4656 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4657 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4659 /* Record the relocation type. */
4663 inst
.reloc
.type
= entry
->ldr_code
;
4667 inst
.reloc
.type
= entry
->ldrs_code
;
4671 inst
.reloc
.type
= entry
->ldc_code
;
4678 if (inst
.reloc
.type
== 0)
4680 inst
.error
= _("this group relocation is not allowed on this instruction");
4681 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4685 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4686 return PARSE_OPERAND_FAIL
;
4690 if (skip_past_char (&p
, ']') == FAIL
)
4692 inst
.error
= _("']' expected");
4693 return PARSE_OPERAND_FAIL
;
4696 if (skip_past_char (&p
, '!') == SUCCESS
)
4697 inst
.operands
[i
].writeback
= 1;
4699 else if (skip_past_comma (&p
) == SUCCESS
)
4701 if (skip_past_char (&p
, '{') == SUCCESS
)
4703 /* [Rn], {expr} - unindexed, with option */
4704 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4705 0, 255, TRUE
) == FAIL
)
4706 return PARSE_OPERAND_FAIL
;
4708 if (skip_past_char (&p
, '}') == FAIL
)
4710 inst
.error
= _("'}' expected at end of 'option' field");
4711 return PARSE_OPERAND_FAIL
;
4713 if (inst
.operands
[i
].preind
)
4715 inst
.error
= _("cannot combine index with option");
4716 return PARSE_OPERAND_FAIL
;
4719 return PARSE_OPERAND_SUCCESS
;
4723 inst
.operands
[i
].postind
= 1;
4724 inst
.operands
[i
].writeback
= 1;
4726 if (inst
.operands
[i
].preind
)
4728 inst
.error
= _("cannot combine pre- and post-indexing");
4729 return PARSE_OPERAND_FAIL
;
4733 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4735 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4737 /* We might be using the immediate for alignment already. If we
4738 are, OR the register number into the low-order bits. */
4739 if (inst
.operands
[i
].immisalign
)
4740 inst
.operands
[i
].imm
|= reg
;
4742 inst
.operands
[i
].imm
= reg
;
4743 inst
.operands
[i
].immisreg
= 1;
4745 if (skip_past_comma (&p
) == SUCCESS
)
4746 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4747 return PARSE_OPERAND_FAIL
;
4751 if (inst
.operands
[i
].negative
)
4753 inst
.operands
[i
].negative
= 0;
4756 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4757 return PARSE_OPERAND_FAIL
;
4762 /* If at this point neither .preind nor .postind is set, we have a
4763 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4764 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4766 inst
.operands
[i
].preind
= 1;
4767 inst
.reloc
.exp
.X_op
= O_constant
;
4768 inst
.reloc
.exp
.X_add_number
= 0;
4771 return PARSE_OPERAND_SUCCESS
;
4775 parse_address (char **str
, int i
)
4777 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4781 static parse_operand_result
4782 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4784 return parse_address_main (str
, i
, 1, type
);
4787 /* Parse an operand for a MOVW or MOVT instruction. */
4789 parse_half (char **str
)
4794 skip_past_char (&p
, '#');
4795 if (strncasecmp (p
, ":lower16:", 9) == 0)
4796 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4797 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4798 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4800 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4806 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4809 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4811 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4813 inst
.error
= _("constant expression expected");
4816 if (inst
.reloc
.exp
.X_add_number
< 0
4817 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4819 inst
.error
= _("immediate value out of range");
4827 /* Miscellaneous. */
4829 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4830 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4832 parse_psr (char **str
)
4835 unsigned long psr_field
;
4836 const struct asm_psr
*psr
;
4839 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4840 feature for ease of use and backwards compatibility. */
4842 if (strncasecmp (p
, "SPSR", 4) == 0)
4843 psr_field
= SPSR_BIT
;
4844 else if (strncasecmp (p
, "CPSR", 4) == 0)
4851 while (ISALNUM (*p
) || *p
== '_');
4853 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4864 /* A suffix follows. */
4870 while (ISALNUM (*p
) || *p
== '_');
4872 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4876 psr_field
|= psr
->field
;
4881 goto error
; /* Garbage after "[CS]PSR". */
4883 psr_field
|= (PSR_c
| PSR_f
);
4889 inst
.error
= _("flag for {c}psr instruction expected");
4893 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4894 value suitable for splatting into the AIF field of the instruction. */
4897 parse_cps_flags (char **str
)
4906 case '\0': case ',':
4909 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4910 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4911 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4914 inst
.error
= _("unrecognized CPS flag");
4919 if (saw_a_flag
== 0)
4921 inst
.error
= _("missing CPS flags");
4929 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4930 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4933 parse_endian_specifier (char **str
)
4938 if (strncasecmp (s
, "BE", 2))
4940 else if (strncasecmp (s
, "LE", 2))
4944 inst
.error
= _("valid endian specifiers are be or le");
4948 if (ISALNUM (s
[2]) || s
[2] == '_')
4950 inst
.error
= _("valid endian specifiers are be or le");
4955 return little_endian
;
4958 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
4959 value suitable for poking into the rotate field of an sxt or sxta
4960 instruction, or FAIL on error. */
4963 parse_ror (char **str
)
4968 if (strncasecmp (s
, "ROR", 3) == 0)
4972 inst
.error
= _("missing rotation field after comma");
4976 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
4981 case 0: *str
= s
; return 0x0;
4982 case 8: *str
= s
; return 0x1;
4983 case 16: *str
= s
; return 0x2;
4984 case 24: *str
= s
; return 0x3;
4987 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
4992 /* Parse a conditional code (from conds[] below). The value returned is in the
4993 range 0 .. 14, or FAIL. */
4995 parse_cond (char **str
)
4998 const struct asm_cond
*c
;
5001 while (ISALPHA (*q
))
5004 c
= hash_find_n (arm_cond_hsh
, p
, q
- p
);
5007 inst
.error
= _("condition required");
5015 /* Parse an option for a barrier instruction. Returns the encoding for the
5018 parse_barrier (char **str
)
5021 const struct asm_barrier_opt
*o
;
5024 while (ISALPHA (*q
))
5027 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5035 /* Parse the operands of a table branch instruction. Similar to a memory
5038 parse_tb (char **str
)
5043 if (skip_past_char (&p
, '[') == FAIL
)
5045 inst
.error
= _("'[' expected");
5049 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5051 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5054 inst
.operands
[0].reg
= reg
;
5056 if (skip_past_comma (&p
) == FAIL
)
5058 inst
.error
= _("',' expected");
5062 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5064 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5067 inst
.operands
[0].imm
= reg
;
5069 if (skip_past_comma (&p
) == SUCCESS
)
5071 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5073 if (inst
.reloc
.exp
.X_add_number
!= 1)
5075 inst
.error
= _("invalid shift");
5078 inst
.operands
[0].shifted
= 1;
5081 if (skip_past_char (&p
, ']') == FAIL
)
5083 inst
.error
= _("']' expected");
5090 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5091 information on the types the operands can take and how they are encoded.
5092 Up to four operands may be read; this function handles setting the
5093 ".present" field for each read operand itself.
5094 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5095 else returns FAIL. */
5098 parse_neon_mov (char **str
, int *which_operand
)
5100 int i
= *which_operand
, val
;
5101 enum arm_reg_type rtype
;
5103 struct neon_type_el optype
;
5105 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5107 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5108 inst
.operands
[i
].reg
= val
;
5109 inst
.operands
[i
].isscalar
= 1;
5110 inst
.operands
[i
].vectype
= optype
;
5111 inst
.operands
[i
++].present
= 1;
5113 if (skip_past_comma (&ptr
) == FAIL
)
5116 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5119 inst
.operands
[i
].reg
= val
;
5120 inst
.operands
[i
].isreg
= 1;
5121 inst
.operands
[i
].present
= 1;
5123 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5126 /* Cases 0, 1, 2, 3, 5 (D only). */
5127 if (skip_past_comma (&ptr
) == FAIL
)
5130 inst
.operands
[i
].reg
= val
;
5131 inst
.operands
[i
].isreg
= 1;
5132 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5133 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5134 inst
.operands
[i
].isvec
= 1;
5135 inst
.operands
[i
].vectype
= optype
;
5136 inst
.operands
[i
++].present
= 1;
5138 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5140 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5141 Case 13: VMOV <Sd>, <Rm> */
5142 inst
.operands
[i
].reg
= val
;
5143 inst
.operands
[i
].isreg
= 1;
5144 inst
.operands
[i
].present
= 1;
5146 if (rtype
== REG_TYPE_NQ
)
5148 first_error (_("can't use Neon quad register here"));
5151 else if (rtype
!= REG_TYPE_VFS
)
5154 if (skip_past_comma (&ptr
) == FAIL
)
5156 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5158 inst
.operands
[i
].reg
= val
;
5159 inst
.operands
[i
].isreg
= 1;
5160 inst
.operands
[i
].present
= 1;
5163 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5164 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5165 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5166 Case 10: VMOV.F32 <Sd>, #<imm>
5167 Case 11: VMOV.F64 <Dd>, #<imm> */
5169 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5170 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5171 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5173 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5176 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5177 Case 1: VMOV<c><q> <Dd>, <Dm>
5178 Case 8: VMOV.F32 <Sd>, <Sm>
5179 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5181 inst
.operands
[i
].reg
= val
;
5182 inst
.operands
[i
].isreg
= 1;
5183 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5184 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5185 inst
.operands
[i
].isvec
= 1;
5186 inst
.operands
[i
].vectype
= optype
;
5187 inst
.operands
[i
].present
= 1;
5189 if (skip_past_comma (&ptr
) == SUCCESS
)
5194 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5197 inst
.operands
[i
].reg
= val
;
5198 inst
.operands
[i
].isreg
= 1;
5199 inst
.operands
[i
++].present
= 1;
5201 if (skip_past_comma (&ptr
) == FAIL
)
5204 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5207 inst
.operands
[i
].reg
= val
;
5208 inst
.operands
[i
].isreg
= 1;
5209 inst
.operands
[i
++].present
= 1;
5214 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5218 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5221 inst
.operands
[i
].reg
= val
;
5222 inst
.operands
[i
].isreg
= 1;
5223 inst
.operands
[i
++].present
= 1;
5225 if (skip_past_comma (&ptr
) == FAIL
)
5228 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5230 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5231 inst
.operands
[i
].reg
= val
;
5232 inst
.operands
[i
].isscalar
= 1;
5233 inst
.operands
[i
].present
= 1;
5234 inst
.operands
[i
].vectype
= optype
;
5236 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5238 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5239 inst
.operands
[i
].reg
= val
;
5240 inst
.operands
[i
].isreg
= 1;
5241 inst
.operands
[i
++].present
= 1;
5243 if (skip_past_comma (&ptr
) == FAIL
)
5246 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5249 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5253 inst
.operands
[i
].reg
= val
;
5254 inst
.operands
[i
].isreg
= 1;
5255 inst
.operands
[i
].isvec
= 1;
5256 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5257 inst
.operands
[i
].vectype
= optype
;
5258 inst
.operands
[i
].present
= 1;
5260 if (rtype
== REG_TYPE_VFS
)
5264 if (skip_past_comma (&ptr
) == FAIL
)
5266 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5269 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5272 inst
.operands
[i
].reg
= val
;
5273 inst
.operands
[i
].isreg
= 1;
5274 inst
.operands
[i
].isvec
= 1;
5275 inst
.operands
[i
].issingle
= 1;
5276 inst
.operands
[i
].vectype
= optype
;
5277 inst
.operands
[i
].present
= 1;
5280 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5284 inst
.operands
[i
].reg
= val
;
5285 inst
.operands
[i
].isreg
= 1;
5286 inst
.operands
[i
].isvec
= 1;
5287 inst
.operands
[i
].issingle
= 1;
5288 inst
.operands
[i
].vectype
= optype
;
5289 inst
.operands
[i
++].present
= 1;
5294 first_error (_("parse error"));
5298 /* Successfully parsed the operands. Update args. */
5304 first_error (_("expected comma"));
5308 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5312 /* Matcher codes for parse_operands. */
5313 enum operand_parse_code
5315 OP_stop
, /* end of line */
5317 OP_RR
, /* ARM register */
5318 OP_RRnpc
, /* ARM register, not r15 */
5319 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5320 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5321 OP_RCP
, /* Coprocessor number */
5322 OP_RCN
, /* Coprocessor register */
5323 OP_RF
, /* FPA register */
5324 OP_RVS
, /* VFP single precision register */
5325 OP_RVD
, /* VFP double precision register (0..15) */
5326 OP_RND
, /* Neon double precision register (0..31) */
5327 OP_RNQ
, /* Neon quad precision register */
5328 OP_RVSD
, /* VFP single or double precision register */
5329 OP_RNDQ
, /* Neon double or quad precision register */
5330 OP_RNSDQ
, /* Neon single, double or quad precision register */
5331 OP_RNSC
, /* Neon scalar D[X] */
5332 OP_RVC
, /* VFP control register */
5333 OP_RMF
, /* Maverick F register */
5334 OP_RMD
, /* Maverick D register */
5335 OP_RMFX
, /* Maverick FX register */
5336 OP_RMDX
, /* Maverick DX register */
5337 OP_RMAX
, /* Maverick AX register */
5338 OP_RMDS
, /* Maverick DSPSC register */
5339 OP_RIWR
, /* iWMMXt wR register */
5340 OP_RIWC
, /* iWMMXt wC register */
5341 OP_RIWG
, /* iWMMXt wCG register */
5342 OP_RXA
, /* XScale accumulator register */
5344 OP_REGLST
, /* ARM register list */
5345 OP_VRSLST
, /* VFP single-precision register list */
5346 OP_VRDLST
, /* VFP double-precision register list */
5347 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5348 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5349 OP_NSTRLST
, /* Neon element/structure list */
5351 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5352 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5353 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5354 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5355 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5356 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5357 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5358 OP_VMOV
, /* Neon VMOV operands. */
5359 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5360 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5362 OP_I0
, /* immediate zero */
5363 OP_I7
, /* immediate value 0 .. 7 */
5364 OP_I15
, /* 0 .. 15 */
5365 OP_I16
, /* 1 .. 16 */
5366 OP_I16z
, /* 0 .. 16 */
5367 OP_I31
, /* 0 .. 31 */
5368 OP_I31w
, /* 0 .. 31, optional trailing ! */
5369 OP_I32
, /* 1 .. 32 */
5370 OP_I32z
, /* 0 .. 32 */
5371 OP_I63
, /* 0 .. 63 */
5372 OP_I63s
, /* -64 .. 63 */
5373 OP_I64
, /* 1 .. 64 */
5374 OP_I64z
, /* 0 .. 64 */
5375 OP_I255
, /* 0 .. 255 */
5377 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5378 OP_I7b
, /* 0 .. 7 */
5379 OP_I15b
, /* 0 .. 15 */
5380 OP_I31b
, /* 0 .. 31 */
5382 OP_SH
, /* shifter operand */
5383 OP_SHG
, /* shifter operand with possible group relocation */
5384 OP_ADDR
, /* Memory address expression (any mode) */
5385 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5386 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5387 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5388 OP_EXP
, /* arbitrary expression */
5389 OP_EXPi
, /* same, with optional immediate prefix */
5390 OP_EXPr
, /* same, with optional relocation suffix */
5391 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5393 OP_CPSF
, /* CPS flags */
5394 OP_ENDI
, /* Endianness specifier */
5395 OP_PSR
, /* CPSR/SPSR mask for msr */
5396 OP_COND
, /* conditional code */
5397 OP_TB
, /* Table branch. */
5399 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5400 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5402 OP_RRnpc_I0
, /* ARM register or literal 0 */
5403 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5404 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5405 OP_RF_IF
, /* FPA register or immediate */
5406 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5407 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5409 /* Optional operands. */
5410 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5411 OP_oI31b
, /* 0 .. 31 */
5412 OP_oI32b
, /* 1 .. 32 */
5413 OP_oIffffb
, /* 0 .. 65535 */
5414 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5416 OP_oRR
, /* ARM register */
5417 OP_oRRnpc
, /* ARM register, not the PC */
5418 OP_oRND
, /* Optional Neon double precision register */
5419 OP_oRNQ
, /* Optional Neon quad precision register */
5420 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5421 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5422 OP_oSHll
, /* LSL immediate */
5423 OP_oSHar
, /* ASR immediate */
5424 OP_oSHllar
, /* LSL or ASR immediate */
5425 OP_oROR
, /* ROR 0/8/16/24 */
5426 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5428 OP_FIRST_OPTIONAL
= OP_oI7b
5431 /* Generic instruction operand parser. This does no encoding and no
5432 semantic validation; it merely squirrels values away in the inst
5433 structure. Returns SUCCESS or FAIL depending on whether the
5434 specified grammar matched. */
5436 parse_operands (char *str
, const unsigned char *pattern
)
5438 unsigned const char *upat
= pattern
;
5439 char *backtrack_pos
= 0;
5440 const char *backtrack_error
= 0;
5441 int i
, val
, backtrack_index
= 0;
5442 enum arm_reg_type rtype
;
5443 parse_operand_result result
;
5445 #define po_char_or_fail(chr) do { \
5446 if (skip_past_char (&str, chr) == FAIL) \
5450 #define po_reg_or_fail(regtype) do { \
5451 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5452 &inst.operands[i].vectype); \
5455 first_error (_(reg_expected_msgs[regtype])); \
5458 inst.operands[i].reg = val; \
5459 inst.operands[i].isreg = 1; \
5460 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5461 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5462 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5463 || rtype == REG_TYPE_VFD \
5464 || rtype == REG_TYPE_NQ); \
5467 #define po_reg_or_goto(regtype, label) do { \
5468 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5469 &inst.operands[i].vectype); \
5473 inst.operands[i].reg = val; \
5474 inst.operands[i].isreg = 1; \
5475 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5476 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5477 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5478 || rtype == REG_TYPE_VFD \
5479 || rtype == REG_TYPE_NQ); \
5482 #define po_imm_or_fail(min, max, popt) do { \
5483 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5485 inst.operands[i].imm = val; \
5488 #define po_scalar_or_goto(elsz, label) do { \
5489 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5492 inst.operands[i].reg = val; \
5493 inst.operands[i].isscalar = 1; \
5496 #define po_misc_or_fail(expr) do { \
5501 #define po_misc_or_fail_no_backtrack(expr) do { \
5503 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5504 backtrack_pos = 0; \
5505 if (result != PARSE_OPERAND_SUCCESS) \
5509 skip_whitespace (str
);
5511 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5513 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5515 /* Remember where we are in case we need to backtrack. */
5516 assert (!backtrack_pos
);
5517 backtrack_pos
= str
;
5518 backtrack_error
= inst
.error
;
5519 backtrack_index
= i
;
5523 po_char_or_fail (',');
5531 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5532 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5533 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5534 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5535 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5536 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5538 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5539 case OP_RVC
: po_reg_or_fail (REG_TYPE_VFC
); break;
5540 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5541 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5542 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5543 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5544 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5545 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5546 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5547 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5548 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5549 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5551 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5553 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5554 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5556 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5558 /* Neon scalar. Using an element size of 8 means that some invalid
5559 scalars are accepted here, so deal with those in later code. */
5560 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5562 /* WARNING: We can expand to two operands here. This has the potential
5563 to totally confuse the backtracking mechanism! It will be OK at
5564 least as long as we don't try to use optional args as well,
5568 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5570 skip_past_comma (&str
);
5571 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5574 /* Optional register operand was omitted. Unfortunately, it's in
5575 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5576 here (this is a bit grotty). */
5577 inst
.operands
[i
] = inst
.operands
[i
-1];
5578 inst
.operands
[i
-1].present
= 0;
5581 /* Immediate gets verified properly later, so accept any now. */
5582 po_imm_or_fail (INT_MIN
, INT_MAX
, TRUE
);
5588 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5591 po_imm_or_fail (0, 0, TRUE
);
5596 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5601 po_scalar_or_goto (8, try_rr
);
5604 po_reg_or_fail (REG_TYPE_RN
);
5610 po_scalar_or_goto (8, try_nsdq
);
5613 po_reg_or_fail (REG_TYPE_NSDQ
);
5619 po_scalar_or_goto (8, try_ndq
);
5622 po_reg_or_fail (REG_TYPE_NDQ
);
5628 po_scalar_or_goto (8, try_vfd
);
5631 po_reg_or_fail (REG_TYPE_VFD
);
5636 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5637 not careful then bad things might happen. */
5638 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5643 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5646 /* There's a possibility of getting a 64-bit immediate here, so
5647 we need special handling. */
5648 if (parse_big_immediate (&str
, i
) == FAIL
)
5650 inst
.error
= _("immediate value is out of range");
5658 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5661 po_imm_or_fail (0, 63, TRUE
);
5666 po_char_or_fail ('[');
5667 po_reg_or_fail (REG_TYPE_RN
);
5668 po_char_or_fail (']');
5672 po_reg_or_fail (REG_TYPE_RN
);
5673 if (skip_past_char (&str
, '!') == SUCCESS
)
5674 inst
.operands
[i
].writeback
= 1;
5678 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5679 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5680 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5681 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5682 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5683 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5684 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5685 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5686 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5687 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5688 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5689 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5691 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5693 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5694 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5696 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5697 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5698 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5700 /* Immediate variants */
5702 po_char_or_fail ('{');
5703 po_imm_or_fail (0, 255, TRUE
);
5704 po_char_or_fail ('}');
5708 /* The expression parser chokes on a trailing !, so we have
5709 to find it first and zap it. */
5712 while (*s
&& *s
!= ',')
5717 inst
.operands
[i
].writeback
= 1;
5719 po_imm_or_fail (0, 31, TRUE
);
5727 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5732 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5737 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5739 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5741 val
= parse_reloc (&str
);
5744 inst
.error
= _("unrecognized relocation suffix");
5747 else if (val
!= BFD_RELOC_UNUSED
)
5749 inst
.operands
[i
].imm
= val
;
5750 inst
.operands
[i
].hasreloc
= 1;
5755 /* Operand for MOVW or MOVT. */
5757 po_misc_or_fail (parse_half (&str
));
5760 /* Register or expression */
5761 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5762 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5764 /* Register or immediate */
5765 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5766 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5768 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5770 if (!is_immediate_prefix (*str
))
5773 val
= parse_fpa_immediate (&str
);
5776 /* FPA immediates are encoded as registers 8-15.
5777 parse_fpa_immediate has already applied the offset. */
5778 inst
.operands
[i
].reg
= val
;
5779 inst
.operands
[i
].isreg
= 1;
5782 /* Two kinds of register */
5785 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5787 || (rege
->type
!= REG_TYPE_MMXWR
5788 && rege
->type
!= REG_TYPE_MMXWC
5789 && rege
->type
!= REG_TYPE_MMXWCG
))
5791 inst
.error
= _("iWMMXt data or control register expected");
5794 inst
.operands
[i
].reg
= rege
->number
;
5795 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5801 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5803 || (rege
->type
!= REG_TYPE_MMXWC
5804 && rege
->type
!= REG_TYPE_MMXWCG
))
5806 inst
.error
= _("iWMMXt control register expected");
5809 inst
.operands
[i
].reg
= rege
->number
;
5810 inst
.operands
[i
].isreg
= 1;
5815 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5816 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5817 case OP_oROR
: val
= parse_ror (&str
); break;
5818 case OP_PSR
: val
= parse_psr (&str
); break;
5819 case OP_COND
: val
= parse_cond (&str
); break;
5820 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5823 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5824 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5827 val
= parse_psr (&str
);
5831 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5834 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5836 if (strncasecmp (str
, "APSR_", 5) == 0)
5843 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5844 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5845 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5846 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5847 default: found
= 16;
5851 inst
.operands
[i
].isvec
= 1;
5858 po_misc_or_fail (parse_tb (&str
));
5861 /* Register lists */
5863 val
= parse_reg_list (&str
);
5866 inst
.operands
[1].writeback
= 1;
5872 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5876 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5880 /* Allow Q registers too. */
5881 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5886 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5888 inst
.operands
[i
].issingle
= 1;
5893 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5898 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5899 &inst
.operands
[i
].vectype
);
5902 /* Addressing modes */
5904 po_misc_or_fail (parse_address (&str
, i
));
5908 po_misc_or_fail_no_backtrack (
5909 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
5913 po_misc_or_fail_no_backtrack (
5914 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
5918 po_misc_or_fail_no_backtrack (
5919 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
5923 po_misc_or_fail (parse_shifter_operand (&str
, i
));
5927 po_misc_or_fail_no_backtrack (
5928 parse_shifter_operand_group_reloc (&str
, i
));
5932 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
5936 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
5940 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
5944 as_fatal ("unhandled operand code %d", upat
[i
]);
5947 /* Various value-based sanity checks and shared operations. We
5948 do not signal immediate failures for the register constraints;
5949 this allows a syntax error to take precedence. */
5957 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
5958 inst
.error
= BAD_PC
;
5976 inst
.operands
[i
].imm
= val
;
5983 /* If we get here, this operand was successfully parsed. */
5984 inst
.operands
[i
].present
= 1;
5988 inst
.error
= BAD_ARGS
;
5993 /* The parse routine should already have set inst.error, but set a
5994 defaut here just in case. */
5996 inst
.error
= _("syntax error");
6000 /* Do not backtrack over a trailing optional argument that
6001 absorbed some text. We will only fail again, with the
6002 'garbage following instruction' error message, which is
6003 probably less helpful than the current one. */
6004 if (backtrack_index
== i
&& backtrack_pos
!= str
6005 && upat
[i
+1] == OP_stop
)
6008 inst
.error
= _("syntax error");
6012 /* Try again, skipping the optional argument at backtrack_pos. */
6013 str
= backtrack_pos
;
6014 inst
.error
= backtrack_error
;
6015 inst
.operands
[backtrack_index
].present
= 0;
6016 i
= backtrack_index
;
6020 /* Check that we have parsed all the arguments. */
6021 if (*str
!= '\0' && !inst
.error
)
6022 inst
.error
= _("garbage following instruction");
6024 return inst
.error
? FAIL
: SUCCESS
;
6027 #undef po_char_or_fail
6028 #undef po_reg_or_fail
6029 #undef po_reg_or_goto
6030 #undef po_imm_or_fail
6031 #undef po_scalar_or_fail
6033 /* Shorthand macro for instruction encoding functions issuing errors. */
6034 #define constraint(expr, err) do { \
6042 /* Functions for operand encoding. ARM, then Thumb. */
6044 #define rotate_left(v, n) (v << n | v >> (32 - n))
6046 /* If VAL can be encoded in the immediate field of an ARM instruction,
6047 return the encoded form. Otherwise, return FAIL. */
6050 encode_arm_immediate (unsigned int val
)
6054 for (i
= 0; i
< 32; i
+= 2)
6055 if ((a
= rotate_left (val
, i
)) <= 0xff)
6056 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6061 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6062 return the encoded form. Otherwise, return FAIL. */
6064 encode_thumb32_immediate (unsigned int val
)
6071 for (i
= 1; i
<= 24; i
++)
6074 if ((val
& ~(0xff << i
)) == 0)
6075 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6079 if (val
== ((a
<< 16) | a
))
6081 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6085 if (val
== ((a
<< 16) | a
))
6086 return 0x200 | (a
>> 8);
6090 /* Encode a VFP SP or DP register number into inst.instruction. */
6093 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6095 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6098 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
6101 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6104 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6109 first_error (_("D register out of range for selected VFP version"));
6117 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6121 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6125 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6129 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6133 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6137 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6145 /* Encode a <shift> in an ARM-format instruction. The immediate,
6146 if any, is handled by md_apply_fix. */
6148 encode_arm_shift (int i
)
6150 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6151 inst
.instruction
|= SHIFT_ROR
<< 5;
6154 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6155 if (inst
.operands
[i
].immisreg
)
6157 inst
.instruction
|= SHIFT_BY_REG
;
6158 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6161 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6166 encode_arm_shifter_operand (int i
)
6168 if (inst
.operands
[i
].isreg
)
6170 inst
.instruction
|= inst
.operands
[i
].reg
;
6171 encode_arm_shift (i
);
6174 inst
.instruction
|= INST_IMMEDIATE
;
6177 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6179 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6181 assert (inst
.operands
[i
].isreg
);
6182 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6184 if (inst
.operands
[i
].preind
)
6188 inst
.error
= _("instruction does not accept preindexed addressing");
6191 inst
.instruction
|= PRE_INDEX
;
6192 if (inst
.operands
[i
].writeback
)
6193 inst
.instruction
|= WRITE_BACK
;
6196 else if (inst
.operands
[i
].postind
)
6198 assert (inst
.operands
[i
].writeback
);
6200 inst
.instruction
|= WRITE_BACK
;
6202 else /* unindexed - only for coprocessor */
6204 inst
.error
= _("instruction does not accept unindexed addressing");
6208 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6209 && (((inst
.instruction
& 0x000f0000) >> 16)
6210 == ((inst
.instruction
& 0x0000f000) >> 12)))
6211 as_warn ((inst
.instruction
& LOAD_BIT
)
6212 ? _("destination register same as write-back base")
6213 : _("source register same as write-back base"));
6216 /* inst.operands[i] was set up by parse_address. Encode it into an
6217 ARM-format mode 2 load or store instruction. If is_t is true,
6218 reject forms that cannot be used with a T instruction (i.e. not
6221 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6223 encode_arm_addr_mode_common (i
, is_t
);
6225 if (inst
.operands
[i
].immisreg
)
6227 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6228 inst
.instruction
|= inst
.operands
[i
].imm
;
6229 if (!inst
.operands
[i
].negative
)
6230 inst
.instruction
|= INDEX_UP
;
6231 if (inst
.operands
[i
].shifted
)
6233 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6234 inst
.instruction
|= SHIFT_ROR
<< 5;
6237 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6238 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6242 else /* immediate offset in inst.reloc */
6244 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6245 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6249 /* inst.operands[i] was set up by parse_address. Encode it into an
6250 ARM-format mode 3 load or store instruction. Reject forms that
6251 cannot be used with such instructions. If is_t is true, reject
6252 forms that cannot be used with a T instruction (i.e. not
6255 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6257 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6259 inst
.error
= _("instruction does not accept scaled register index");
6263 encode_arm_addr_mode_common (i
, is_t
);
6265 if (inst
.operands
[i
].immisreg
)
6267 inst
.instruction
|= inst
.operands
[i
].imm
;
6268 if (!inst
.operands
[i
].negative
)
6269 inst
.instruction
|= INDEX_UP
;
6271 else /* immediate offset in inst.reloc */
6273 inst
.instruction
|= HWOFFSET_IMM
;
6274 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6275 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6279 /* inst.operands[i] was set up by parse_address. Encode it into an
6280 ARM-format instruction. Reject all forms which cannot be encoded
6281 into a coprocessor load/store instruction. If wb_ok is false,
6282 reject use of writeback; if unind_ok is false, reject use of
6283 unindexed addressing. If reloc_override is not 0, use it instead
6284 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6285 (in which case it is preserved). */
6288 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6290 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6292 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6294 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6296 assert (!inst
.operands
[i
].writeback
);
6299 inst
.error
= _("instruction does not support unindexed addressing");
6302 inst
.instruction
|= inst
.operands
[i
].imm
;
6303 inst
.instruction
|= INDEX_UP
;
6307 if (inst
.operands
[i
].preind
)
6308 inst
.instruction
|= PRE_INDEX
;
6310 if (inst
.operands
[i
].writeback
)
6312 if (inst
.operands
[i
].reg
== REG_PC
)
6314 inst
.error
= _("pc may not be used with write-back");
6319 inst
.error
= _("instruction does not support writeback");
6322 inst
.instruction
|= WRITE_BACK
;
6326 inst
.reloc
.type
= reloc_override
;
6327 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6328 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6329 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6332 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6334 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6340 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6341 Determine whether it can be performed with a move instruction; if
6342 it can, convert inst.instruction to that move instruction and
6343 return 1; if it can't, convert inst.instruction to a literal-pool
6344 load and return 0. If this is not a valid thing to do in the
6345 current context, set inst.error and return 1.
6347 inst.operands[i] describes the destination register. */
6350 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6355 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6359 if ((inst
.instruction
& tbit
) == 0)
6361 inst
.error
= _("invalid pseudo operation");
6364 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6366 inst
.error
= _("constant expression expected");
6369 if (inst
.reloc
.exp
.X_op
== O_constant
)
6373 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6375 /* This can be done with a mov(1) instruction. */
6376 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6377 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6383 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6386 /* This can be done with a mov instruction. */
6387 inst
.instruction
&= LITERAL_MASK
;
6388 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6389 inst
.instruction
|= value
& 0xfff;
6393 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6396 /* This can be done with a mvn instruction. */
6397 inst
.instruction
&= LITERAL_MASK
;
6398 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6399 inst
.instruction
|= value
& 0xfff;
6405 if (add_to_lit_pool () == FAIL
)
6407 inst
.error
= _("literal pool insertion failed");
6410 inst
.operands
[1].reg
= REG_PC
;
6411 inst
.operands
[1].isreg
= 1;
6412 inst
.operands
[1].preind
= 1;
6413 inst
.reloc
.pc_rel
= 1;
6414 inst
.reloc
.type
= (thumb_p
6415 ? BFD_RELOC_ARM_THUMB_OFFSET
6417 ? BFD_RELOC_ARM_HWLITERAL
6418 : BFD_RELOC_ARM_LITERAL
));
6422 /* Functions for instruction encoding, sorted by subarchitecture.
6423 First some generics; their names are taken from the conventional
6424 bit positions for register arguments in ARM format instructions. */
6434 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6440 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6441 inst
.instruction
|= inst
.operands
[1].reg
;
6447 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6448 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6454 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6455 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6461 unsigned Rn
= inst
.operands
[2].reg
;
6462 /* Enforce restrictions on SWP instruction. */
6463 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6464 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6465 _("Rn must not overlap other operands"));
6466 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6467 inst
.instruction
|= inst
.operands
[1].reg
;
6468 inst
.instruction
|= Rn
<< 16;
6474 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6475 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6476 inst
.instruction
|= inst
.operands
[2].reg
;
6482 inst
.instruction
|= inst
.operands
[0].reg
;
6483 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6484 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6490 inst
.instruction
|= inst
.operands
[0].imm
;
6496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6497 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6500 /* ARM instructions, in alphabetical order by function name (except
6501 that wrapper functions appear immediately after the function they
6504 /* This is a pseudo-op of the form "adr rd, label" to be converted
6505 into a relative address of the form "add rd, pc, #label-.-8". */
6510 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6512 /* Frag hacking will turn this into a sub instruction if the offset turns
6513 out to be negative. */
6514 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6515 inst
.reloc
.pc_rel
= 1;
6516 inst
.reloc
.exp
.X_add_number
-= 8;
6519 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6520 into a relative address of the form:
6521 add rd, pc, #low(label-.-8)"
6522 add rd, rd, #high(label-.-8)" */
6527 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6529 /* Frag hacking will turn this into a sub instruction if the offset turns
6530 out to be negative. */
6531 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6532 inst
.reloc
.pc_rel
= 1;
6533 inst
.size
= INSN_SIZE
* 2;
6534 inst
.reloc
.exp
.X_add_number
-= 8;
6540 if (!inst
.operands
[1].present
)
6541 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6542 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6543 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6544 encode_arm_shifter_operand (2);
6550 if (inst
.operands
[0].present
)
6552 constraint ((inst
.instruction
& 0xf0) != 0x40
6553 && inst
.operands
[0].imm
!= 0xf,
6554 "bad barrier type");
6555 inst
.instruction
|= inst
.operands
[0].imm
;
6558 inst
.instruction
|= 0xf;
6564 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6565 constraint (msb
> 32, _("bit-field extends past end of register"));
6566 /* The instruction encoding stores the LSB and MSB,
6567 not the LSB and width. */
6568 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6569 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6570 inst
.instruction
|= (msb
- 1) << 16;
6578 /* #0 in second position is alternative syntax for bfc, which is
6579 the same instruction but with REG_PC in the Rm field. */
6580 if (!inst
.operands
[1].isreg
)
6581 inst
.operands
[1].reg
= REG_PC
;
6583 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6584 constraint (msb
> 32, _("bit-field extends past end of register"));
6585 /* The instruction encoding stores the LSB and MSB,
6586 not the LSB and width. */
6587 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6588 inst
.instruction
|= inst
.operands
[1].reg
;
6589 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6590 inst
.instruction
|= (msb
- 1) << 16;
6596 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6597 _("bit-field extends past end of register"));
6598 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6599 inst
.instruction
|= inst
.operands
[1].reg
;
6600 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6601 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6604 /* ARM V5 breakpoint instruction (argument parse)
6605 BKPT <16 bit unsigned immediate>
6606 Instruction is not conditional.
6607 The bit pattern given in insns[] has the COND_ALWAYS condition,
6608 and it is an error if the caller tried to override that. */
6613 /* Top 12 of 16 bits to bits 19:8. */
6614 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6616 /* Bottom 4 of 16 bits to bits 3:0. */
6617 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6621 encode_branch (int default_reloc
)
6623 if (inst
.operands
[0].hasreloc
)
6625 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6626 _("the only suffix valid here is '(plt)'"));
6627 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6631 inst
.reloc
.type
= default_reloc
;
6633 inst
.reloc
.pc_rel
= 1;
6640 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6641 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6644 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6651 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6653 if (inst
.cond
== COND_ALWAYS
)
6654 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6656 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6660 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6663 /* ARM V5 branch-link-exchange instruction (argument parse)
6664 BLX <target_addr> ie BLX(1)
6665 BLX{<condition>} <Rm> ie BLX(2)
6666 Unfortunately, there are two different opcodes for this mnemonic.
6667 So, the insns[].value is not used, and the code here zaps values
6668 into inst.instruction.
6669 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6674 if (inst
.operands
[0].isreg
)
6676 /* Arg is a register; the opcode provided by insns[] is correct.
6677 It is not illegal to do "blx pc", just useless. */
6678 if (inst
.operands
[0].reg
== REG_PC
)
6679 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6681 inst
.instruction
|= inst
.operands
[0].reg
;
6685 /* Arg is an address; this instruction cannot be executed
6686 conditionally, and the opcode must be adjusted. */
6687 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6688 inst
.instruction
= 0xfa000000;
6690 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6691 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6694 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6701 if (inst
.operands
[0].reg
== REG_PC
)
6702 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6704 inst
.instruction
|= inst
.operands
[0].reg
;
6708 /* ARM v5TEJ. Jump to Jazelle code. */
6713 if (inst
.operands
[0].reg
== REG_PC
)
6714 as_tsktsk (_("use of r15 in bxj is not really useful"));
6716 inst
.instruction
|= inst
.operands
[0].reg
;
6719 /* Co-processor data operation:
6720 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6721 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6725 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6726 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6727 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6728 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6729 inst
.instruction
|= inst
.operands
[4].reg
;
6730 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6736 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6737 encode_arm_shifter_operand (1);
6740 /* Transfer between coprocessor and ARM registers.
6741 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6746 No special properties. */
6751 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6752 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6753 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6754 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6755 inst
.instruction
|= inst
.operands
[4].reg
;
6756 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6759 /* Transfer between coprocessor register and pair of ARM registers.
6760 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6765 Two XScale instructions are special cases of these:
6767 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6768 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6770 Result unpredicatable if Rd or Rn is R15. */
6775 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6776 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6777 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6778 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6779 inst
.instruction
|= inst
.operands
[4].reg
;
6785 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6786 inst
.instruction
|= inst
.operands
[1].imm
;
6792 inst
.instruction
|= inst
.operands
[0].imm
;
6798 /* There is no IT instruction in ARM mode. We
6799 process it but do not generate code for it. */
6806 int base_reg
= inst
.operands
[0].reg
;
6807 int range
= inst
.operands
[1].imm
;
6809 inst
.instruction
|= base_reg
<< 16;
6810 inst
.instruction
|= range
;
6812 if (inst
.operands
[1].writeback
)
6813 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6815 if (inst
.operands
[0].writeback
)
6817 inst
.instruction
|= WRITE_BACK
;
6818 /* Check for unpredictable uses of writeback. */
6819 if (inst
.instruction
& LOAD_BIT
)
6821 /* Not allowed in LDM type 2. */
6822 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6823 && ((range
& (1 << REG_PC
)) == 0))
6824 as_warn (_("writeback of base register is UNPREDICTABLE"));
6825 /* Only allowed if base reg not in list for other types. */
6826 else if (range
& (1 << base_reg
))
6827 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6831 /* Not allowed for type 2. */
6832 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6833 as_warn (_("writeback of base register is UNPREDICTABLE"));
6834 /* Only allowed if base reg not in list, or first in list. */
6835 else if ((range
& (1 << base_reg
))
6836 && (range
& ((1 << base_reg
) - 1)))
6837 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
6842 /* ARMv5TE load-consecutive (argument parse)
6851 constraint (inst
.operands
[0].reg
% 2 != 0,
6852 _("first destination register must be even"));
6853 constraint (inst
.operands
[1].present
6854 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6855 _("can only load two consecutive registers"));
6856 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6857 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
6859 if (!inst
.operands
[1].present
)
6860 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
6862 if (inst
.instruction
& LOAD_BIT
)
6864 /* encode_arm_addr_mode_3 will diagnose overlap between the base
6865 register and the first register written; we have to diagnose
6866 overlap between the base and the second register written here. */
6868 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
6869 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
6870 as_warn (_("base register written back, and overlaps "
6871 "second destination register"));
6873 /* For an index-register load, the index register must not overlap the
6874 destination (even if not write-back). */
6875 else if (inst
.operands
[2].immisreg
6876 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
6877 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
6878 as_warn (_("index register overlaps destination register"));
6881 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6882 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
6888 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
6889 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
6890 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
6891 || inst
.operands
[1].negative
6892 /* This can arise if the programmer has written
6894 or if they have mistakenly used a register name as the last
6897 It is very difficult to distinguish between these two cases
6898 because "rX" might actually be a label. ie the register
6899 name has been occluded by a symbol of the same name. So we
6900 just generate a general 'bad addressing mode' type error
6901 message and leave it up to the programmer to discover the
6902 true cause and fix their mistake. */
6903 || (inst
.operands
[1].reg
== REG_PC
),
6906 constraint (inst
.reloc
.exp
.X_op
!= O_constant
6907 || inst
.reloc
.exp
.X_add_number
!= 0,
6908 _("offset must be zero in ARM encoding"));
6910 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6911 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6912 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
6918 constraint (inst
.operands
[0].reg
% 2 != 0,
6919 _("even register required"));
6920 constraint (inst
.operands
[1].present
6921 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
6922 _("can only load two consecutive registers"));
6923 /* If op 1 were present and equal to PC, this function wouldn't
6924 have been called in the first place. */
6925 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
6927 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6928 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6934 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6935 if (!inst
.operands
[1].isreg
)
6936 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
6938 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
6944 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6946 if (inst
.operands
[1].preind
)
6948 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6949 inst
.reloc
.exp
.X_add_number
!= 0,
6950 _("this instruction requires a post-indexed address"));
6952 inst
.operands
[1].preind
= 0;
6953 inst
.operands
[1].postind
= 1;
6954 inst
.operands
[1].writeback
= 1;
6956 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6957 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
6960 /* Halfword and signed-byte load/store operations. */
6965 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6966 if (!inst
.operands
[1].isreg
)
6967 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
6969 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
6975 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
6977 if (inst
.operands
[1].preind
)
6979 constraint (inst
.reloc
.exp
.X_op
!= O_constant
||
6980 inst
.reloc
.exp
.X_add_number
!= 0,
6981 _("this instruction requires a post-indexed address"));
6983 inst
.operands
[1].preind
= 0;
6984 inst
.operands
[1].postind
= 1;
6985 inst
.operands
[1].writeback
= 1;
6987 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6988 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
6991 /* Co-processor register load/store.
6992 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
6996 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6997 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6998 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7004 /* This restriction does not apply to mls (nor to mla in v6, but
7005 that's hard to detect at present). */
7006 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7007 && !(inst
.instruction
& 0x00400000))
7008 as_tsktsk (_("rd and rm should be different in mla"));
7010 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7011 inst
.instruction
|= inst
.operands
[1].reg
;
7012 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7013 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7020 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7021 encode_arm_shifter_operand (1);
7024 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7031 top
= (inst
.instruction
& 0x00400000) != 0;
7032 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7033 _(":lower16: not allowed this instruction"));
7034 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7035 _(":upper16: not allowed instruction"));
7036 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7037 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7039 imm
= inst
.reloc
.exp
.X_add_number
;
7040 /* The value is in two pieces: 0:11, 16:19. */
7041 inst
.instruction
|= (imm
& 0x00000fff);
7042 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7046 static void do_vfp_nsyn_opcode (const char *);
7049 do_vfp_nsyn_mrs (void)
7051 if (inst
.operands
[0].isvec
)
7053 if (inst
.operands
[1].reg
!= 1)
7054 first_error (_("operand 1 must be FPSCR"));
7055 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7056 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7057 do_vfp_nsyn_opcode ("fmstat");
7059 else if (inst
.operands
[1].isvec
)
7060 do_vfp_nsyn_opcode ("fmrx");
7068 do_vfp_nsyn_msr (void)
7070 if (inst
.operands
[0].isvec
)
7071 do_vfp_nsyn_opcode ("fmxr");
7081 if (do_vfp_nsyn_mrs () == SUCCESS
)
7084 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7085 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7087 _("'CPSR' or 'SPSR' expected"));
7088 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7089 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7092 /* Two possible forms:
7093 "{C|S}PSR_<field>, Rm",
7094 "{C|S}PSR_f, #expression". */
7099 if (do_vfp_nsyn_msr () == SUCCESS
)
7102 inst
.instruction
|= inst
.operands
[0].imm
;
7103 if (inst
.operands
[1].isreg
)
7104 inst
.instruction
|= inst
.operands
[1].reg
;
7107 inst
.instruction
|= INST_IMMEDIATE
;
7108 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7109 inst
.reloc
.pc_rel
= 0;
7116 if (!inst
.operands
[2].present
)
7117 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7118 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7119 inst
.instruction
|= inst
.operands
[1].reg
;
7120 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7122 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7123 as_tsktsk (_("rd and rm should be different in mul"));
7126 /* Long Multiply Parser
7127 UMULL RdLo, RdHi, Rm, Rs
7128 SMULL RdLo, RdHi, Rm, Rs
7129 UMLAL RdLo, RdHi, Rm, Rs
7130 SMLAL RdLo, RdHi, Rm, Rs. */
7135 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7136 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7137 inst
.instruction
|= inst
.operands
[2].reg
;
7138 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7140 /* rdhi, rdlo and rm must all be different. */
7141 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7142 || inst
.operands
[0].reg
== inst
.operands
[2].reg
7143 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7144 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7150 if (inst
.operands
[0].present
)
7152 /* Architectural NOP hints are CPSR sets with no bits selected. */
7153 inst
.instruction
&= 0xf0000000;
7154 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7158 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7159 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7160 Condition defaults to COND_ALWAYS.
7161 Error if Rd, Rn or Rm are R15. */
7166 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7167 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7168 inst
.instruction
|= inst
.operands
[2].reg
;
7169 if (inst
.operands
[3].present
)
7170 encode_arm_shift (3);
7173 /* ARM V6 PKHTB (Argument Parse). */
7178 if (!inst
.operands
[3].present
)
7180 /* If the shift specifier is omitted, turn the instruction
7181 into pkhbt rd, rm, rn. */
7182 inst
.instruction
&= 0xfff00010;
7183 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7184 inst
.instruction
|= inst
.operands
[1].reg
;
7185 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7189 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7190 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7191 inst
.instruction
|= inst
.operands
[2].reg
;
7192 encode_arm_shift (3);
7196 /* ARMv5TE: Preload-Cache
7200 Syntactically, like LDR with B=1, W=0, L=1. */
7205 constraint (!inst
.operands
[0].isreg
,
7206 _("'[' expected after PLD mnemonic"));
7207 constraint (inst
.operands
[0].postind
,
7208 _("post-indexed expression used in preload instruction"));
7209 constraint (inst
.operands
[0].writeback
,
7210 _("writeback used in preload instruction"));
7211 constraint (!inst
.operands
[0].preind
,
7212 _("unindexed addressing used in preload instruction"));
7213 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7216 /* ARMv7: PLI <addr_mode> */
7220 constraint (!inst
.operands
[0].isreg
,
7221 _("'[' expected after PLI mnemonic"));
7222 constraint (inst
.operands
[0].postind
,
7223 _("post-indexed expression used in preload instruction"));
7224 constraint (inst
.operands
[0].writeback
,
7225 _("writeback used in preload instruction"));
7226 constraint (!inst
.operands
[0].preind
,
7227 _("unindexed addressing used in preload instruction"));
7228 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7229 inst
.instruction
&= ~PRE_INDEX
;
7235 inst
.operands
[1] = inst
.operands
[0];
7236 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7237 inst
.operands
[0].isreg
= 1;
7238 inst
.operands
[0].writeback
= 1;
7239 inst
.operands
[0].reg
= REG_SP
;
7243 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7244 word at the specified address and the following word
7246 Unconditionally executed.
7247 Error if Rn is R15. */
7252 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7253 if (inst
.operands
[0].writeback
)
7254 inst
.instruction
|= WRITE_BACK
;
7257 /* ARM V6 ssat (argument parse). */
7262 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7263 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7264 inst
.instruction
|= inst
.operands
[2].reg
;
7266 if (inst
.operands
[3].present
)
7267 encode_arm_shift (3);
7270 /* ARM V6 usat (argument parse). */
7275 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7276 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7277 inst
.instruction
|= inst
.operands
[2].reg
;
7279 if (inst
.operands
[3].present
)
7280 encode_arm_shift (3);
7283 /* ARM V6 ssat16 (argument parse). */
7288 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7289 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7290 inst
.instruction
|= inst
.operands
[2].reg
;
7296 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7297 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7298 inst
.instruction
|= inst
.operands
[2].reg
;
7301 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7302 preserving the other bits.
7304 setend <endian_specifier>, where <endian_specifier> is either
7310 if (inst
.operands
[0].imm
)
7311 inst
.instruction
|= 0x200;
7317 unsigned int Rm
= (inst
.operands
[1].present
7318 ? inst
.operands
[1].reg
7319 : inst
.operands
[0].reg
);
7321 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7322 inst
.instruction
|= Rm
;
7323 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7325 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7326 inst
.instruction
|= SHIFT_BY_REG
;
7329 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7335 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7336 inst
.reloc
.pc_rel
= 0;
7342 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7343 inst
.reloc
.pc_rel
= 0;
7346 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7347 SMLAxy{cond} Rd,Rm,Rs,Rn
7348 SMLAWy{cond} Rd,Rm,Rs,Rn
7349 Error if any register is R15. */
7354 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7355 inst
.instruction
|= inst
.operands
[1].reg
;
7356 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7357 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7360 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7361 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7362 Error if any register is R15.
7363 Warning if Rdlo == Rdhi. */
7368 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7369 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7370 inst
.instruction
|= inst
.operands
[2].reg
;
7371 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7373 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7374 as_tsktsk (_("rdhi and rdlo must be different"));
7377 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7378 SMULxy{cond} Rd,Rm,Rs
7379 Error if any register is R15. */
7384 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7385 inst
.instruction
|= inst
.operands
[1].reg
;
7386 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7389 /* ARM V6 srs (argument parse). */
7394 inst
.instruction
|= inst
.operands
[0].imm
;
7395 if (inst
.operands
[0].writeback
)
7396 inst
.instruction
|= WRITE_BACK
;
7399 /* ARM V6 strex (argument parse). */
7404 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7405 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7406 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7407 || inst
.operands
[2].negative
7408 /* See comment in do_ldrex(). */
7409 || (inst
.operands
[2].reg
== REG_PC
),
7412 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7413 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7415 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7416 || inst
.reloc
.exp
.X_add_number
!= 0,
7417 _("offset must be zero in ARM encoding"));
7419 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7420 inst
.instruction
|= inst
.operands
[1].reg
;
7421 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7422 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7428 constraint (inst
.operands
[1].reg
% 2 != 0,
7429 _("even register required"));
7430 constraint (inst
.operands
[2].present
7431 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7432 _("can only store two consecutive registers"));
7433 /* If op 2 were present and equal to PC, this function wouldn't
7434 have been called in the first place. */
7435 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7437 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7438 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7439 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7442 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7443 inst
.instruction
|= inst
.operands
[1].reg
;
7444 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7447 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7448 extends it to 32-bits, and adds the result to a value in another
7449 register. You can specify a rotation by 0, 8, 16, or 24 bits
7450 before extracting the 16-bit value.
7451 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7452 Condition defaults to COND_ALWAYS.
7453 Error if any register uses R15. */
7458 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7459 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7460 inst
.instruction
|= inst
.operands
[2].reg
;
7461 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7466 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7467 Condition defaults to COND_ALWAYS.
7468 Error if any register uses R15. */
7473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7474 inst
.instruction
|= inst
.operands
[1].reg
;
7475 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7478 /* VFP instructions. In a logical order: SP variant first, monad
7479 before dyad, arithmetic then move then load/store. */
7482 do_vfp_sp_monadic (void)
7484 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7485 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7489 do_vfp_sp_dyadic (void)
7491 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7492 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7493 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7497 do_vfp_sp_compare_z (void)
7499 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7503 do_vfp_dp_sp_cvt (void)
7505 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7506 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7510 do_vfp_sp_dp_cvt (void)
7512 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7513 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7517 do_vfp_reg_from_sp (void)
7519 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7520 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7524 do_vfp_reg2_from_sp2 (void)
7526 constraint (inst
.operands
[2].imm
!= 2,
7527 _("only two consecutive VFP SP registers allowed here"));
7528 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7529 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7530 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7534 do_vfp_sp_from_reg (void)
7536 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7537 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7541 do_vfp_sp2_from_reg2 (void)
7543 constraint (inst
.operands
[0].imm
!= 2,
7544 _("only two consecutive VFP SP registers allowed here"));
7545 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7546 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7547 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7551 do_vfp_sp_ldst (void)
7553 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7554 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7558 do_vfp_dp_ldst (void)
7560 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7561 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7566 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7568 if (inst
.operands
[0].writeback
)
7569 inst
.instruction
|= WRITE_BACK
;
7571 constraint (ldstm_type
!= VFP_LDSTMIA
,
7572 _("this addressing mode requires base-register writeback"));
7573 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7574 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7575 inst
.instruction
|= inst
.operands
[1].imm
;
7579 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7583 if (inst
.operands
[0].writeback
)
7584 inst
.instruction
|= WRITE_BACK
;
7586 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7587 _("this addressing mode requires base-register writeback"));
7589 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7590 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7592 count
= inst
.operands
[1].imm
<< 1;
7593 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7596 inst
.instruction
|= count
;
7600 do_vfp_sp_ldstmia (void)
7602 vfp_sp_ldstm (VFP_LDSTMIA
);
7606 do_vfp_sp_ldstmdb (void)
7608 vfp_sp_ldstm (VFP_LDSTMDB
);
7612 do_vfp_dp_ldstmia (void)
7614 vfp_dp_ldstm (VFP_LDSTMIA
);
7618 do_vfp_dp_ldstmdb (void)
7620 vfp_dp_ldstm (VFP_LDSTMDB
);
7624 do_vfp_xp_ldstmia (void)
7626 vfp_dp_ldstm (VFP_LDSTMIAX
);
7630 do_vfp_xp_ldstmdb (void)
7632 vfp_dp_ldstm (VFP_LDSTMDBX
);
7636 do_vfp_dp_rd_rm (void)
7638 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7639 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7643 do_vfp_dp_rn_rd (void)
7645 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7646 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7650 do_vfp_dp_rd_rn (void)
7652 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7653 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7657 do_vfp_dp_rd_rn_rm (void)
7659 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7660 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7661 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7667 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7671 do_vfp_dp_rm_rd_rn (void)
7673 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7674 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7675 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7678 /* VFPv3 instructions. */
7680 do_vfp_sp_const (void)
7682 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7683 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7684 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7688 do_vfp_dp_const (void)
7690 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7691 inst
.instruction
|= (inst
.operands
[1].imm
& 15) << 16;
7692 inst
.instruction
|= (inst
.operands
[1].imm
>> 4);
7696 vfp_conv (int srcsize
)
7698 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7699 inst
.instruction
|= (immbits
& 1) << 5;
7700 inst
.instruction
|= (immbits
>> 1);
7704 do_vfp_sp_conv_16 (void)
7706 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7711 do_vfp_dp_conv_16 (void)
7713 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7718 do_vfp_sp_conv_32 (void)
7720 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7725 do_vfp_dp_conv_32 (void)
7727 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7732 /* FPA instructions. Also in a logical order. */
7737 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7738 inst
.instruction
|= inst
.operands
[1].reg
;
7742 do_fpa_ldmstm (void)
7744 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7745 switch (inst
.operands
[1].imm
)
7747 case 1: inst
.instruction
|= CP_T_X
; break;
7748 case 2: inst
.instruction
|= CP_T_Y
; break;
7749 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7754 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7756 /* The instruction specified "ea" or "fd", so we can only accept
7757 [Rn]{!}. The instruction does not really support stacking or
7758 unstacking, so we have to emulate these by setting appropriate
7759 bits and offsets. */
7760 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7761 || inst
.reloc
.exp
.X_add_number
!= 0,
7762 _("this instruction does not support indexing"));
7764 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7765 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7767 if (!(inst
.instruction
& INDEX_UP
))
7768 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7770 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7772 inst
.operands
[2].preind
= 0;
7773 inst
.operands
[2].postind
= 1;
7777 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7781 /* iWMMXt instructions: strictly in alphabetical order. */
7784 do_iwmmxt_tandorc (void)
7786 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7790 do_iwmmxt_textrc (void)
7792 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7793 inst
.instruction
|= inst
.operands
[1].imm
;
7797 do_iwmmxt_textrm (void)
7799 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7800 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7801 inst
.instruction
|= inst
.operands
[2].imm
;
7805 do_iwmmxt_tinsr (void)
7807 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7808 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7809 inst
.instruction
|= inst
.operands
[2].imm
;
7813 do_iwmmxt_tmia (void)
7815 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7816 inst
.instruction
|= inst
.operands
[1].reg
;
7817 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7821 do_iwmmxt_waligni (void)
7823 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7824 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7825 inst
.instruction
|= inst
.operands
[2].reg
;
7826 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
7830 do_iwmmxt_wmov (void)
7832 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
7833 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7834 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7835 inst
.instruction
|= inst
.operands
[1].reg
;
7839 do_iwmmxt_wldstbh (void)
7842 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7844 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
7846 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
7847 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
7851 do_iwmmxt_wldstw (void)
7853 /* RIWR_RIWC clears .isreg for a control register. */
7854 if (!inst
.operands
[0].isreg
)
7856 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7857 inst
.instruction
|= 0xf0000000;
7860 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7861 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7865 do_iwmmxt_wldstd (void)
7867 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7868 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
7872 do_iwmmxt_wshufh (void)
7874 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7875 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7876 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
7877 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
7881 do_iwmmxt_wzero (void)
7883 /* WZERO reg is an alias for WANDN reg, reg, reg. */
7884 inst
.instruction
|= inst
.operands
[0].reg
;
7885 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7886 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7889 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
7890 operations first, then control, shift, and load/store. */
7892 /* Insns like "foo X,Y,Z". */
7895 do_mav_triple (void)
7897 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7898 inst
.instruction
|= inst
.operands
[1].reg
;
7899 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7902 /* Insns like "foo W,X,Y,Z".
7903 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
7908 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7909 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7910 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7911 inst
.instruction
|= inst
.operands
[3].reg
;
7914 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
7918 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7921 /* Maverick shift immediate instructions.
7922 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
7923 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
7928 int imm
= inst
.operands
[2].imm
;
7930 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7931 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7933 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
7934 Bits 5-7 of the insn should have bits 4-6 of the immediate.
7935 Bit 4 should be 0. */
7936 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
7938 inst
.instruction
|= imm
;
7941 /* XScale instructions. Also sorted arithmetic before move. */
7943 /* Xscale multiply-accumulate (argument parse)
7946 MIAxycc acc0,Rm,Rs. */
7951 inst
.instruction
|= inst
.operands
[1].reg
;
7952 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7955 /* Xscale move-accumulator-register (argument parse)
7957 MARcc acc0,RdLo,RdHi. */
7962 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7963 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7966 /* Xscale move-register-accumulator (argument parse)
7968 MRAcc RdLo,RdHi,acc0. */
7973 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
7974 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7975 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7978 /* Encoding functions relevant only to Thumb. */
7980 /* inst.operands[i] is a shifted-register operand; encode
7981 it into inst.instruction in the format used by Thumb32. */
7984 encode_thumb32_shifted_operand (int i
)
7986 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
7987 unsigned int shift
= inst
.operands
[i
].shift_kind
;
7989 constraint (inst
.operands
[i
].immisreg
,
7990 _("shift by register not allowed in thumb mode"));
7991 inst
.instruction
|= inst
.operands
[i
].reg
;
7992 if (shift
== SHIFT_RRX
)
7993 inst
.instruction
|= SHIFT_ROR
<< 4;
7996 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
7997 _("expression too complex"));
7999 constraint (value
> 32
8000 || (value
== 32 && (shift
== SHIFT_LSL
8001 || shift
== SHIFT_ROR
)),
8002 _("shift expression is too large"));
8006 else if (value
== 32)
8009 inst
.instruction
|= shift
<< 4;
8010 inst
.instruction
|= (value
& 0x1c) << 10;
8011 inst
.instruction
|= (value
& 0x03) << 6;
8016 /* inst.operands[i] was set up by parse_address. Encode it into a
8017 Thumb32 format load or store instruction. Reject forms that cannot
8018 be used with such instructions. If is_t is true, reject forms that
8019 cannot be used with a T instruction; if is_d is true, reject forms
8020 that cannot be used with a D instruction. */
8023 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8025 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8027 constraint (!inst
.operands
[i
].isreg
,
8028 _("Instruction does not support =N addresses"));
8030 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8031 if (inst
.operands
[i
].immisreg
)
8033 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8034 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8035 constraint (inst
.operands
[i
].negative
,
8036 _("Thumb does not support negative register indexing"));
8037 constraint (inst
.operands
[i
].postind
,
8038 _("Thumb does not support register post-indexing"));
8039 constraint (inst
.operands
[i
].writeback
,
8040 _("Thumb does not support register indexing with writeback"));
8041 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8042 _("Thumb supports only LSL in shifted register indexing"));
8044 inst
.instruction
|= inst
.operands
[i
].imm
;
8045 if (inst
.operands
[i
].shifted
)
8047 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8048 _("expression too complex"));
8049 constraint (inst
.reloc
.exp
.X_add_number
< 0
8050 || inst
.reloc
.exp
.X_add_number
> 3,
8051 _("shift out of range"));
8052 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8054 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8056 else if (inst
.operands
[i
].preind
)
8058 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8059 _("cannot use writeback with PC-relative addressing"));
8060 constraint (is_t
&& inst
.operands
[i
].writeback
,
8061 _("cannot use writeback with this instruction"));
8065 inst
.instruction
|= 0x01000000;
8066 if (inst
.operands
[i
].writeback
)
8067 inst
.instruction
|= 0x00200000;
8071 inst
.instruction
|= 0x00000c00;
8072 if (inst
.operands
[i
].writeback
)
8073 inst
.instruction
|= 0x00000100;
8075 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8077 else if (inst
.operands
[i
].postind
)
8079 assert (inst
.operands
[i
].writeback
);
8080 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8081 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8084 inst
.instruction
|= 0x00200000;
8086 inst
.instruction
|= 0x00000900;
8087 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8089 else /* unindexed - only for coprocessor */
8090 inst
.error
= _("instruction does not accept unindexed addressing");
8093 /* Table of Thumb instructions which exist in both 16- and 32-bit
8094 encodings (the latter only in post-V6T2 cores). The index is the
8095 value used in the insns table below. When there is more than one
8096 possible 16-bit encoding for the instruction, this table always
8098 Also contains several pseudo-instructions used during relaxation. */
8099 #define T16_32_TAB \
8100 X(adc, 4140, eb400000), \
8101 X(adcs, 4140, eb500000), \
8102 X(add, 1c00, eb000000), \
8103 X(adds, 1c00, eb100000), \
8104 X(addi, 0000, f1000000), \
8105 X(addis, 0000, f1100000), \
8106 X(add_pc,000f, f20f0000), \
8107 X(add_sp,000d, f10d0000), \
8108 X(adr, 000f, f20f0000), \
8109 X(and, 4000, ea000000), \
8110 X(ands, 4000, ea100000), \
8111 X(asr, 1000, fa40f000), \
8112 X(asrs, 1000, fa50f000), \
8113 X(b, e000, f000b000), \
8114 X(bcond, d000, f0008000), \
8115 X(bic, 4380, ea200000), \
8116 X(bics, 4380, ea300000), \
8117 X(cmn, 42c0, eb100f00), \
8118 X(cmp, 2800, ebb00f00), \
8119 X(cpsie, b660, f3af8400), \
8120 X(cpsid, b670, f3af8600), \
8121 X(cpy, 4600, ea4f0000), \
8122 X(dec_sp,80dd, f1bd0d00), \
8123 X(eor, 4040, ea800000), \
8124 X(eors, 4040, ea900000), \
8125 X(inc_sp,00dd, f10d0d00), \
8126 X(ldmia, c800, e8900000), \
8127 X(ldr, 6800, f8500000), \
8128 X(ldrb, 7800, f8100000), \
8129 X(ldrh, 8800, f8300000), \
8130 X(ldrsb, 5600, f9100000), \
8131 X(ldrsh, 5e00, f9300000), \
8132 X(ldr_pc,4800, f85f0000), \
8133 X(ldr_pc2,4800, f85f0000), \
8134 X(ldr_sp,9800, f85d0000), \
8135 X(lsl, 0000, fa00f000), \
8136 X(lsls, 0000, fa10f000), \
8137 X(lsr, 0800, fa20f000), \
8138 X(lsrs, 0800, fa30f000), \
8139 X(mov, 2000, ea4f0000), \
8140 X(movs, 2000, ea5f0000), \
8141 X(mul, 4340, fb00f000), \
8142 X(muls, 4340, ffffffff), /* no 32b muls */ \
8143 X(mvn, 43c0, ea6f0000), \
8144 X(mvns, 43c0, ea7f0000), \
8145 X(neg, 4240, f1c00000), /* rsb #0 */ \
8146 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8147 X(orr, 4300, ea400000), \
8148 X(orrs, 4300, ea500000), \
8149 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8150 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8151 X(rev, ba00, fa90f080), \
8152 X(rev16, ba40, fa90f090), \
8153 X(revsh, bac0, fa90f0b0), \
8154 X(ror, 41c0, fa60f000), \
8155 X(rors, 41c0, fa70f000), \
8156 X(sbc, 4180, eb600000), \
8157 X(sbcs, 4180, eb700000), \
8158 X(stmia, c000, e8800000), \
8159 X(str, 6000, f8400000), \
8160 X(strb, 7000, f8000000), \
8161 X(strh, 8000, f8200000), \
8162 X(str_sp,9000, f84d0000), \
8163 X(sub, 1e00, eba00000), \
8164 X(subs, 1e00, ebb00000), \
8165 X(subi, 8000, f1a00000), \
8166 X(subis, 8000, f1b00000), \
8167 X(sxtb, b240, fa4ff080), \
8168 X(sxth, b200, fa0ff080), \
8169 X(tst, 4200, ea100f00), \
8170 X(uxtb, b2c0, fa5ff080), \
8171 X(uxth, b280, fa1ff080), \
8172 X(nop, bf00, f3af8000), \
8173 X(yield, bf10, f3af8001), \
8174 X(wfe, bf20, f3af8002), \
8175 X(wfi, bf30, f3af8003), \
8176 X(sev, bf40, f3af9004), /* typo, 8004? */
8178 /* To catch errors in encoding functions, the codes are all offset by
8179 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8180 as 16-bit instructions. */
8181 #define X(a,b,c) T_MNEM_##a
8182 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8185 #define X(a,b,c) 0x##b
8186 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8187 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8190 #define X(a,b,c) 0x##c
8191 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8192 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8193 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8197 /* Thumb instruction encoders, in alphabetical order. */
8201 do_t_add_sub_w (void)
8205 Rd
= inst
.operands
[0].reg
;
8206 Rn
= inst
.operands
[1].reg
;
8208 constraint (Rd
== 15, _("PC not allowed as destination"));
8209 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8210 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8213 /* Parse an add or subtract instruction. We get here with inst.instruction
8214 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8221 Rd
= inst
.operands
[0].reg
;
8222 Rs
= (inst
.operands
[1].present
8223 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8224 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8232 flags
= (inst
.instruction
== T_MNEM_adds
8233 || inst
.instruction
== T_MNEM_subs
);
8235 narrow
= (current_it_mask
== 0);
8237 narrow
= (current_it_mask
!= 0);
8238 if (!inst
.operands
[2].isreg
)
8242 add
= (inst
.instruction
== T_MNEM_add
8243 || inst
.instruction
== T_MNEM_adds
);
8245 if (inst
.size_req
!= 4)
8247 /* Attempt to use a narrow opcode, with relaxation if
8249 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8250 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8251 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8252 opcode
= T_MNEM_add_sp
;
8253 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8254 opcode
= T_MNEM_add_pc
;
8255 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8258 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8260 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8264 inst
.instruction
= THUMB_OP16(opcode
);
8265 inst
.instruction
|= (Rd
<< 4) | Rs
;
8266 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8267 if (inst
.size_req
!= 2)
8268 inst
.relax
= opcode
;
8271 constraint (inst
.size_req
== 2, BAD_HIREG
);
8273 if (inst
.size_req
== 4
8274 || (inst
.size_req
!= 2 && !opcode
))
8278 /* Always use addw/subw. */
8279 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8280 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8284 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8285 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8288 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8290 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8292 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8293 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8298 Rn
= inst
.operands
[2].reg
;
8299 /* See if we can do this with a 16-bit instruction. */
8300 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8302 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8307 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8308 || inst
.instruction
== T_MNEM_add
)
8311 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8315 if (inst
.instruction
== T_MNEM_add
)
8319 inst
.instruction
= T_OPCODE_ADD_HI
;
8320 inst
.instruction
|= (Rd
& 8) << 4;
8321 inst
.instruction
|= (Rd
& 7);
8322 inst
.instruction
|= Rn
<< 3;
8325 /* ... because addition is commutative! */
8328 inst
.instruction
= T_OPCODE_ADD_HI
;
8329 inst
.instruction
|= (Rd
& 8) << 4;
8330 inst
.instruction
|= (Rd
& 7);
8331 inst
.instruction
|= Rs
<< 3;
8336 /* If we get here, it can't be done in 16 bits. */
8337 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8338 _("shift must be constant"));
8339 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8340 inst
.instruction
|= Rd
<< 8;
8341 inst
.instruction
|= Rs
<< 16;
8342 encode_thumb32_shifted_operand (2);
8347 constraint (inst
.instruction
== T_MNEM_adds
8348 || inst
.instruction
== T_MNEM_subs
,
8351 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8353 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8354 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8357 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8359 inst
.instruction
|= (Rd
<< 4) | Rs
;
8360 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8364 Rn
= inst
.operands
[2].reg
;
8365 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8367 /* We now have Rd, Rs, and Rn set to registers. */
8368 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8370 /* Can't do this for SUB. */
8371 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8372 inst
.instruction
= T_OPCODE_ADD_HI
;
8373 inst
.instruction
|= (Rd
& 8) << 4;
8374 inst
.instruction
|= (Rd
& 7);
8376 inst
.instruction
|= Rn
<< 3;
8378 inst
.instruction
|= Rs
<< 3;
8380 constraint (1, _("dest must overlap one source register"));
8384 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8385 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8386 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8394 if (unified_syntax
&& inst
.size_req
== 0 && inst
.operands
[0].reg
<= 7)
8396 /* Defer to section relaxation. */
8397 inst
.relax
= inst
.instruction
;
8398 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8399 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8401 else if (unified_syntax
&& inst
.size_req
!= 2)
8403 /* Generate a 32-bit opcode. */
8404 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8405 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8406 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8407 inst
.reloc
.pc_rel
= 1;
8411 /* Generate a 16-bit opcode. */
8412 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8413 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8414 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8415 inst
.reloc
.pc_rel
= 1;
8417 inst
.instruction
|= inst
.operands
[0].reg
<< 4;
8421 /* Arithmetic instructions for which there is just one 16-bit
8422 instruction encoding, and it allows only two low registers.
8423 For maximal compatibility with ARM syntax, we allow three register
8424 operands even when Thumb-32 instructions are not available, as long
8425 as the first two are identical. For instance, both "sbc r0,r1" and
8426 "sbc r0,r0,r1" are allowed. */
8432 Rd
= inst
.operands
[0].reg
;
8433 Rs
= (inst
.operands
[1].present
8434 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8435 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8436 Rn
= inst
.operands
[2].reg
;
8440 if (!inst
.operands
[2].isreg
)
8442 /* For an immediate, we always generate a 32-bit opcode;
8443 section relaxation will shrink it later if possible. */
8444 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8445 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8446 inst
.instruction
|= Rd
<< 8;
8447 inst
.instruction
|= Rs
<< 16;
8448 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8454 /* See if we can do this with a 16-bit instruction. */
8455 if (THUMB_SETS_FLAGS (inst
.instruction
))
8456 narrow
= current_it_mask
== 0;
8458 narrow
= current_it_mask
!= 0;
8460 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8462 if (inst
.operands
[2].shifted
)
8464 if (inst
.size_req
== 4)
8470 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8471 inst
.instruction
|= Rd
;
8472 inst
.instruction
|= Rn
<< 3;
8476 /* If we get here, it can't be done in 16 bits. */
8477 constraint (inst
.operands
[2].shifted
8478 && inst
.operands
[2].immisreg
,
8479 _("shift must be constant"));
8480 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8481 inst
.instruction
|= Rd
<< 8;
8482 inst
.instruction
|= Rs
<< 16;
8483 encode_thumb32_shifted_operand (2);
8488 /* On its face this is a lie - the instruction does set the
8489 flags. However, the only supported mnemonic in this mode
8491 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8493 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8494 _("unshifted register required"));
8495 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8496 constraint (Rd
!= Rs
,
8497 _("dest and source1 must be the same register"));
8499 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8500 inst
.instruction
|= Rd
;
8501 inst
.instruction
|= Rn
<< 3;
8505 /* Similarly, but for instructions where the arithmetic operation is
8506 commutative, so we can allow either of them to be different from
8507 the destination operand in a 16-bit instruction. For instance, all
8508 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8515 Rd
= inst
.operands
[0].reg
;
8516 Rs
= (inst
.operands
[1].present
8517 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8518 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8519 Rn
= inst
.operands
[2].reg
;
8523 if (!inst
.operands
[2].isreg
)
8525 /* For an immediate, we always generate a 32-bit opcode;
8526 section relaxation will shrink it later if possible. */
8527 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8528 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8529 inst
.instruction
|= Rd
<< 8;
8530 inst
.instruction
|= Rs
<< 16;
8531 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8537 /* See if we can do this with a 16-bit instruction. */
8538 if (THUMB_SETS_FLAGS (inst
.instruction
))
8539 narrow
= current_it_mask
== 0;
8541 narrow
= current_it_mask
!= 0;
8543 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8545 if (inst
.operands
[2].shifted
)
8547 if (inst
.size_req
== 4)
8554 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8555 inst
.instruction
|= Rd
;
8556 inst
.instruction
|= Rn
<< 3;
8561 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8562 inst
.instruction
|= Rd
;
8563 inst
.instruction
|= Rs
<< 3;
8568 /* If we get here, it can't be done in 16 bits. */
8569 constraint (inst
.operands
[2].shifted
8570 && inst
.operands
[2].immisreg
,
8571 _("shift must be constant"));
8572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8573 inst
.instruction
|= Rd
<< 8;
8574 inst
.instruction
|= Rs
<< 16;
8575 encode_thumb32_shifted_operand (2);
8580 /* On its face this is a lie - the instruction does set the
8581 flags. However, the only supported mnemonic in this mode
8583 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8585 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8586 _("unshifted register required"));
8587 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8589 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8590 inst
.instruction
|= Rd
;
8593 inst
.instruction
|= Rn
<< 3;
8595 inst
.instruction
|= Rs
<< 3;
8597 constraint (1, _("dest must overlap one source register"));
8604 if (inst
.operands
[0].present
)
8606 constraint ((inst
.instruction
& 0xf0) != 0x40
8607 && inst
.operands
[0].imm
!= 0xf,
8608 "bad barrier type");
8609 inst
.instruction
|= inst
.operands
[0].imm
;
8612 inst
.instruction
|= 0xf;
8618 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8619 constraint (msb
> 32, _("bit-field extends past end of register"));
8620 /* The instruction encoding stores the LSB and MSB,
8621 not the LSB and width. */
8622 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8623 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8624 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8625 inst
.instruction
|= msb
- 1;
8633 /* #0 in second position is alternative syntax for bfc, which is
8634 the same instruction but with REG_PC in the Rm field. */
8635 if (!inst
.operands
[1].isreg
)
8636 inst
.operands
[1].reg
= REG_PC
;
8638 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8639 constraint (msb
> 32, _("bit-field extends past end of register"));
8640 /* The instruction encoding stores the LSB and MSB,
8641 not the LSB and width. */
8642 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8643 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8644 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8645 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8646 inst
.instruction
|= msb
- 1;
8652 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8653 _("bit-field extends past end of register"));
8654 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8655 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8656 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8657 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8658 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8661 /* ARM V5 Thumb BLX (argument parse)
8662 BLX <target_addr> which is BLX(1)
8663 BLX <Rm> which is BLX(2)
8664 Unfortunately, there are two different opcodes for this mnemonic.
8665 So, the insns[].value is not used, and the code here zaps values
8666 into inst.instruction.
8668 ??? How to take advantage of the additional two bits of displacement
8669 available in Thumb32 mode? Need new relocation? */
8674 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8675 if (inst
.operands
[0].isreg
)
8676 /* We have a register, so this is BLX(2). */
8677 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8680 /* No register. This must be BLX(1). */
8681 inst
.instruction
= 0xf000e800;
8683 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8684 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8687 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
8688 inst
.reloc
.pc_rel
= 1;
8698 if (current_it_mask
)
8700 /* Conditional branches inside IT blocks are encoded as unconditional
8703 /* A branch must be the last instruction in an IT block. */
8704 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
8709 if (cond
!= COND_ALWAYS
)
8710 opcode
= T_MNEM_bcond
;
8712 opcode
= inst
.instruction
;
8714 if (unified_syntax
&& inst
.size_req
== 4)
8716 inst
.instruction
= THUMB_OP32(opcode
);
8717 if (cond
== COND_ALWAYS
)
8718 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
8721 assert (cond
!= 0xF);
8722 inst
.instruction
|= cond
<< 22;
8723 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
8728 inst
.instruction
= THUMB_OP16(opcode
);
8729 if (cond
== COND_ALWAYS
)
8730 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
8733 inst
.instruction
|= cond
<< 8;
8734 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
8736 /* Allow section relaxation. */
8737 if (unified_syntax
&& inst
.size_req
!= 2)
8738 inst
.relax
= opcode
;
8741 inst
.reloc
.pc_rel
= 1;
8747 constraint (inst
.cond
!= COND_ALWAYS
,
8748 _("instruction is always unconditional"));
8749 if (inst
.operands
[0].present
)
8751 constraint (inst
.operands
[0].imm
> 255,
8752 _("immediate value out of range"));
8753 inst
.instruction
|= inst
.operands
[0].imm
;
8758 do_t_branch23 (void)
8760 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8761 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
8762 inst
.reloc
.pc_rel
= 1;
8764 /* If the destination of the branch is a defined symbol which does not have
8765 the THUMB_FUNC attribute, then we must be calling a function which has
8766 the (interfacearm) attribute. We look for the Thumb entry point to that
8767 function and change the branch to refer to that function instead. */
8768 if ( inst
.reloc
.exp
.X_op
== O_symbol
8769 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8770 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8771 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8772 inst
.reloc
.exp
.X_add_symbol
=
8773 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
8779 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8780 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8781 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
8782 should cause the alignment to be checked once it is known. This is
8783 because BX PC only works if the instruction is word aligned. */
8789 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8790 if (inst
.operands
[0].reg
== REG_PC
)
8791 as_tsktsk (_("use of r15 in bxj is not really useful"));
8793 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8799 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8800 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8801 inst
.instruction
|= inst
.operands
[1].reg
;
8807 constraint (current_it_mask
, BAD_NOT_IT
);
8808 inst
.instruction
|= inst
.operands
[0].imm
;
8814 constraint (current_it_mask
, BAD_NOT_IT
);
8816 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
8817 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
8819 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
8820 inst
.instruction
= 0xf3af8000;
8821 inst
.instruction
|= imod
<< 9;
8822 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
8823 if (inst
.operands
[1].present
)
8824 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
8828 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
8829 && (inst
.operands
[0].imm
& 4),
8830 _("selected processor does not support 'A' form "
8831 "of this instruction"));
8832 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
8833 _("Thumb does not support the 2-argument "
8834 "form of this instruction"));
8835 inst
.instruction
|= inst
.operands
[0].imm
;
8839 /* THUMB CPY instruction (argument parse). */
8844 if (inst
.size_req
== 4)
8846 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
8847 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8848 inst
.instruction
|= inst
.operands
[1].reg
;
8852 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
8853 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
8854 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
8861 constraint (current_it_mask
, BAD_NOT_IT
);
8862 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
8863 inst
.instruction
|= inst
.operands
[0].reg
;
8864 inst
.reloc
.pc_rel
= 1;
8865 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
8871 inst
.instruction
|= inst
.operands
[0].imm
;
8877 if (!inst
.operands
[1].present
)
8878 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8879 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8880 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8881 inst
.instruction
|= inst
.operands
[2].reg
;
8887 if (unified_syntax
&& inst
.size_req
== 4)
8888 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8890 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8896 unsigned int cond
= inst
.operands
[0].imm
;
8898 constraint (current_it_mask
, BAD_NOT_IT
);
8899 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
8902 /* If the condition is a negative condition, invert the mask. */
8903 if ((cond
& 0x1) == 0x0)
8905 unsigned int mask
= inst
.instruction
& 0x000f;
8907 if ((mask
& 0x7) == 0)
8908 /* no conversion needed */;
8909 else if ((mask
& 0x3) == 0)
8911 else if ((mask
& 0x1) == 0)
8916 inst
.instruction
&= 0xfff0;
8917 inst
.instruction
|= mask
;
8920 inst
.instruction
|= cond
<< 4;
8926 /* This really doesn't seem worth it. */
8927 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
8928 _("expression too complex"));
8929 constraint (inst
.operands
[1].writeback
,
8930 _("Thumb load/store multiple does not support {reglist}^"));
8934 /* See if we can use a 16-bit instruction. */
8935 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
8936 && inst
.size_req
!= 4
8937 && inst
.operands
[0].reg
<= 7
8938 && !(inst
.operands
[1].imm
& ~0xff)
8939 && (inst
.instruction
== T_MNEM_stmia
8940 ? inst
.operands
[0].writeback
8941 : (inst
.operands
[0].writeback
8942 == !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))))
8944 if (inst
.instruction
== T_MNEM_stmia
8945 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8946 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8947 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8948 inst
.operands
[0].reg
);
8950 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8951 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8952 inst
.instruction
|= inst
.operands
[1].imm
;
8956 if (inst
.operands
[1].imm
& (1 << 13))
8957 as_warn (_("SP should not be in register list"));
8958 if (inst
.instruction
== T_MNEM_stmia
)
8960 if (inst
.operands
[1].imm
& (1 << 15))
8961 as_warn (_("PC should not be in register list"));
8962 if (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8963 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8964 inst
.operands
[0].reg
);
8968 if (inst
.operands
[1].imm
& (1 << 14)
8969 && inst
.operands
[1].imm
& (1 << 15))
8970 as_warn (_("LR and PC should not both be in register list"));
8971 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8972 && inst
.operands
[0].writeback
)
8973 as_warn (_("base register should not be in register list "
8974 "when written back"));
8976 if (inst
.instruction
< 0xffff)
8977 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8978 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8979 inst
.instruction
|= inst
.operands
[1].imm
;
8980 if (inst
.operands
[0].writeback
)
8981 inst
.instruction
|= WRITE_BACK
;
8986 constraint (inst
.operands
[0].reg
> 7
8987 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
8988 if (inst
.instruction
== T_MNEM_stmia
)
8990 if (!inst
.operands
[0].writeback
)
8991 as_warn (_("this instruction will write back the base register"));
8992 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
8993 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
8994 as_warn (_("value stored for r%d is UNPREDICTABLE"),
8995 inst
.operands
[0].reg
);
8999 if (!inst
.operands
[0].writeback
9000 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9001 as_warn (_("this instruction will write back the base register"));
9002 else if (inst
.operands
[0].writeback
9003 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9004 as_warn (_("this instruction will not write back the base register"));
9007 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9008 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9009 inst
.instruction
|= inst
.operands
[1].imm
;
9016 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9017 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9018 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9019 || inst
.operands
[1].negative
,
9022 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9023 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9024 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9030 if (!inst
.operands
[1].present
)
9032 constraint (inst
.operands
[0].reg
== REG_LR
,
9033 _("r14 not allowed as first register "
9034 "when second register is omitted"));
9035 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9037 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9040 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9041 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9042 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9048 unsigned long opcode
;
9051 opcode
= inst
.instruction
;
9054 if (!inst
.operands
[1].isreg
)
9056 if (opcode
<= 0xffff)
9057 inst
.instruction
= THUMB_OP32 (opcode
);
9058 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9061 if (inst
.operands
[1].isreg
9062 && !inst
.operands
[1].writeback
9063 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9064 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9066 && inst
.size_req
!= 4)
9068 /* Insn may have a 16-bit form. */
9069 Rn
= inst
.operands
[1].reg
;
9070 if (inst
.operands
[1].immisreg
)
9072 inst
.instruction
= THUMB_OP16 (opcode
);
9074 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9077 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9078 && opcode
!= T_MNEM_ldrsb
)
9079 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9080 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9087 if (inst
.reloc
.pc_rel
)
9088 opcode
= T_MNEM_ldr_pc2
;
9090 opcode
= T_MNEM_ldr_pc
;
9094 if (opcode
== T_MNEM_ldr
)
9095 opcode
= T_MNEM_ldr_sp
;
9097 opcode
= T_MNEM_str_sp
;
9099 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9103 inst
.instruction
= inst
.operands
[0].reg
;
9104 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9106 inst
.instruction
|= THUMB_OP16 (opcode
);
9107 if (inst
.size_req
== 2)
9108 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9110 inst
.relax
= opcode
;
9114 /* Definitely a 32-bit variant. */
9115 inst
.instruction
= THUMB_OP32 (opcode
);
9116 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9117 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9121 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9123 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9125 /* Only [Rn,Rm] is acceptable. */
9126 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9127 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9128 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9129 || inst
.operands
[1].negative
,
9130 _("Thumb does not support this addressing mode"));
9131 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9135 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9136 if (!inst
.operands
[1].isreg
)
9137 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9140 constraint (!inst
.operands
[1].preind
9141 || inst
.operands
[1].shifted
9142 || inst
.operands
[1].writeback
,
9143 _("Thumb does not support this addressing mode"));
9144 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9146 constraint (inst
.instruction
& 0x0600,
9147 _("byte or halfword not valid for base register"));
9148 constraint (inst
.operands
[1].reg
== REG_PC
9149 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9150 _("r15 based store not allowed"));
9151 constraint (inst
.operands
[1].immisreg
,
9152 _("invalid base register for register offset"));
9154 if (inst
.operands
[1].reg
== REG_PC
)
9155 inst
.instruction
= T_OPCODE_LDR_PC
;
9156 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9157 inst
.instruction
= T_OPCODE_LDR_SP
;
9159 inst
.instruction
= T_OPCODE_STR_SP
;
9161 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9162 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9166 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9167 if (!inst
.operands
[1].immisreg
)
9169 /* Immediate offset. */
9170 inst
.instruction
|= inst
.operands
[0].reg
;
9171 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9172 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9176 /* Register offset. */
9177 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9178 constraint (inst
.operands
[1].negative
,
9179 _("Thumb does not support this addressing mode"));
9182 switch (inst
.instruction
)
9184 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9185 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9186 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9187 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9188 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9189 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9190 case 0x5600 /* ldrsb */:
9191 case 0x5e00 /* ldrsh */: break;
9195 inst
.instruction
|= inst
.operands
[0].reg
;
9196 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9197 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9203 if (!inst
.operands
[1].present
)
9205 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9206 constraint (inst
.operands
[0].reg
== REG_LR
,
9207 _("r14 not allowed here"));
9209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9210 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9211 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9219 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9225 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9226 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9227 inst
.instruction
|= inst
.operands
[2].reg
;
9228 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9234 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9235 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9236 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9237 inst
.instruction
|= inst
.operands
[3].reg
;
9245 int r0off
= (inst
.instruction
== T_MNEM_mov
9246 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9247 unsigned long opcode
;
9249 bfd_boolean low_regs
;
9251 low_regs
= (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7);
9252 opcode
= inst
.instruction
;
9253 if (current_it_mask
)
9254 narrow
= opcode
!= T_MNEM_movs
;
9256 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9257 if (inst
.size_req
== 4
9258 || inst
.operands
[1].shifted
)
9261 if (!inst
.operands
[1].isreg
)
9263 /* Immediate operand. */
9264 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9266 if (low_regs
&& narrow
)
9268 inst
.instruction
= THUMB_OP16 (opcode
);
9269 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9270 if (inst
.size_req
== 2)
9271 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9273 inst
.relax
= opcode
;
9277 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9278 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9279 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9280 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9285 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9286 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9287 encode_thumb32_shifted_operand (1);
9290 switch (inst
.instruction
)
9293 inst
.instruction
= T_OPCODE_MOV_HR
;
9294 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9295 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9296 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9300 /* We know we have low registers at this point.
9301 Generate ADD Rd, Rs, #0. */
9302 inst
.instruction
= T_OPCODE_ADD_I3
;
9303 inst
.instruction
|= inst
.operands
[0].reg
;
9304 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9310 inst
.instruction
= T_OPCODE_CMP_LR
;
9311 inst
.instruction
|= inst
.operands
[0].reg
;
9312 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9316 inst
.instruction
= T_OPCODE_CMP_HR
;
9317 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9318 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9319 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9326 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9327 if (inst
.operands
[1].isreg
)
9329 if (inst
.operands
[0].reg
< 8 && inst
.operands
[1].reg
< 8)
9331 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9332 since a MOV instruction produces unpredictable results. */
9333 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9334 inst
.instruction
= T_OPCODE_ADD_I3
;
9336 inst
.instruction
= T_OPCODE_CMP_LR
;
9338 inst
.instruction
|= inst
.operands
[0].reg
;
9339 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9343 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9344 inst
.instruction
= T_OPCODE_MOV_HR
;
9346 inst
.instruction
= T_OPCODE_CMP_HR
;
9352 constraint (inst
.operands
[0].reg
> 7,
9353 _("only lo regs allowed with immediate"));
9354 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9355 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9365 top
= (inst
.instruction
& 0x00800000) != 0;
9366 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9368 constraint (top
, _(":lower16: not allowed this instruction"));
9369 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9371 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9373 constraint (!top
, _(":upper16: not allowed this instruction"));
9374 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9377 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9378 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9380 imm
= inst
.reloc
.exp
.X_add_number
;
9381 inst
.instruction
|= (imm
& 0xf000) << 4;
9382 inst
.instruction
|= (imm
& 0x0800) << 15;
9383 inst
.instruction
|= (imm
& 0x0700) << 4;
9384 inst
.instruction
|= (imm
& 0x00ff);
9393 int r0off
= (inst
.instruction
== T_MNEM_mvn
9394 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9397 if (inst
.size_req
== 4
9398 || inst
.instruction
> 0xffff
9399 || inst
.operands
[1].shifted
9400 || inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9402 else if (inst
.instruction
== T_MNEM_cmn
)
9404 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9405 narrow
= (current_it_mask
== 0);
9407 narrow
= (current_it_mask
!= 0);
9409 if (!inst
.operands
[1].isreg
)
9411 /* For an immediate, we always generate a 32-bit opcode;
9412 section relaxation will shrink it later if possible. */
9413 if (inst
.instruction
< 0xffff)
9414 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9415 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9416 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9417 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9421 /* See if we can do this with a 16-bit instruction. */
9424 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9425 inst
.instruction
|= inst
.operands
[0].reg
;
9426 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9430 constraint (inst
.operands
[1].shifted
9431 && inst
.operands
[1].immisreg
,
9432 _("shift must be constant"));
9433 if (inst
.instruction
< 0xffff)
9434 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9435 inst
.instruction
|= inst
.operands
[0].reg
<< r0off
;
9436 encode_thumb32_shifted_operand (1);
9442 constraint (inst
.instruction
> 0xffff
9443 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
9444 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
9445 _("unshifted register required"));
9446 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9449 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9450 inst
.instruction
|= inst
.operands
[0].reg
;
9451 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9460 if (do_vfp_nsyn_mrs () == SUCCESS
)
9463 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
9466 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9467 _("selected processor does not support "
9468 "requested special purpose register"));
9472 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9473 _("selected processor does not support "
9474 "requested special purpose register %x"));
9475 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9476 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
9477 _("'CPSR' or 'SPSR' expected"));
9480 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9481 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9482 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
9490 if (do_vfp_nsyn_msr () == SUCCESS
)
9493 constraint (!inst
.operands
[1].isreg
,
9494 _("Thumb encoding does not support an immediate here"));
9495 flags
= inst
.operands
[0].imm
;
9498 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
9499 _("selected processor does not support "
9500 "requested special purpose register"));
9504 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7m
),
9505 _("selected processor does not support "
9506 "requested special purpose register"));
9509 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
9510 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
9511 inst
.instruction
|= (flags
& 0xff);
9512 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9518 if (!inst
.operands
[2].present
)
9519 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9521 /* There is no 32-bit MULS and no 16-bit MUL. */
9522 if (unified_syntax
&& inst
.instruction
== T_MNEM_mul
)
9524 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9525 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9526 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9527 inst
.instruction
|= inst
.operands
[2].reg
<< 0;
9531 constraint (!unified_syntax
9532 && inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
9533 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9536 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9537 inst
.instruction
|= inst
.operands
[0].reg
;
9539 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9540 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9541 else if (inst
.operands
[0].reg
== inst
.operands
[2].reg
)
9542 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9544 constraint (1, _("dest must overlap one source register"));
9551 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9552 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9553 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9554 inst
.instruction
|= inst
.operands
[3].reg
;
9556 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9557 as_tsktsk (_("rdhi and rdlo must be different"));
9565 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
9567 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9568 inst
.instruction
|= inst
.operands
[0].imm
;
9572 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9573 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
9578 constraint (inst
.operands
[0].present
,
9579 _("Thumb does not support NOP with hints"));
9580 inst
.instruction
= 0x46c0;
9591 if (THUMB_SETS_FLAGS (inst
.instruction
))
9592 narrow
= (current_it_mask
== 0);
9594 narrow
= (current_it_mask
!= 0);
9595 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9597 if (inst
.size_req
== 4)
9602 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9603 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9604 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9608 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9609 inst
.instruction
|= inst
.operands
[0].reg
;
9610 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9615 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
9617 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9619 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9620 inst
.instruction
|= inst
.operands
[0].reg
;
9621 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9628 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9629 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9630 inst
.instruction
|= inst
.operands
[2].reg
;
9631 if (inst
.operands
[3].present
)
9633 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
9634 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9635 _("expression too complex"));
9636 inst
.instruction
|= (val
& 0x1c) << 10;
9637 inst
.instruction
|= (val
& 0x03) << 6;
9644 if (!inst
.operands
[3].present
)
9645 inst
.instruction
&= ~0x00000020;
9652 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9656 do_t_push_pop (void)
9660 constraint (inst
.operands
[0].writeback
,
9661 _("push/pop do not support {reglist}^"));
9662 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9663 _("expression too complex"));
9665 mask
= inst
.operands
[0].imm
;
9666 if ((mask
& ~0xff) == 0)
9667 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9668 else if ((inst
.instruction
== T_MNEM_push
9669 && (mask
& ~0xff) == 1 << REG_LR
)
9670 || (inst
.instruction
== T_MNEM_pop
9671 && (mask
& ~0xff) == 1 << REG_PC
))
9673 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9674 inst
.instruction
|= THUMB_PP_PC_LR
;
9677 else if (unified_syntax
)
9679 if (mask
& (1 << 13))
9680 inst
.error
= _("SP not allowed in register list");
9681 if (inst
.instruction
== T_MNEM_push
)
9683 if (mask
& (1 << 15))
9684 inst
.error
= _("PC not allowed in register list");
9688 if (mask
& (1 << 14)
9689 && mask
& (1 << 15))
9690 inst
.error
= _("LR and PC should not both be in register list");
9692 if ((mask
& (mask
- 1)) == 0)
9694 /* Single register push/pop implemented as str/ldr. */
9695 if (inst
.instruction
== T_MNEM_push
)
9696 inst
.instruction
= 0xf84d0d04; /* str reg, [sp, #-4]! */
9698 inst
.instruction
= 0xf85d0b04; /* ldr reg, [sp], #4 */
9699 mask
= ffs(mask
) - 1;
9703 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9707 inst
.error
= _("invalid register list to push/pop instruction");
9711 inst
.instruction
|= mask
;
9717 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9718 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9724 if (inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
9725 && inst
.size_req
!= 4)
9727 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9728 inst
.instruction
|= inst
.operands
[0].reg
;
9729 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9731 else if (unified_syntax
)
9733 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9734 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9735 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9736 inst
.instruction
|= inst
.operands
[1].reg
;
9739 inst
.error
= BAD_HIREG
;
9747 Rd
= inst
.operands
[0].reg
;
9748 Rs
= (inst
.operands
[1].present
9749 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9750 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9752 inst
.instruction
|= Rd
<< 8;
9753 inst
.instruction
|= Rs
<< 16;
9754 if (!inst
.operands
[2].isreg
)
9756 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9757 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9760 encode_thumb32_shifted_operand (2);
9766 constraint (current_it_mask
, BAD_NOT_IT
);
9767 if (inst
.operands
[0].imm
)
9768 inst
.instruction
|= 0x8;
9774 if (!inst
.operands
[1].present
)
9775 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9782 switch (inst
.instruction
)
9785 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
9787 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
9789 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
9791 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
9795 if (THUMB_SETS_FLAGS (inst
.instruction
))
9796 narrow
= (current_it_mask
== 0);
9798 narrow
= (current_it_mask
!= 0);
9799 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
9801 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
9803 if (inst
.operands
[2].isreg
9804 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
9805 || inst
.operands
[2].reg
> 7))
9807 if (inst
.size_req
== 4)
9812 if (inst
.operands
[2].isreg
)
9814 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9815 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9816 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9817 inst
.instruction
|= inst
.operands
[2].reg
;
9821 inst
.operands
[1].shifted
= 1;
9822 inst
.operands
[1].shift_kind
= shift_kind
;
9823 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
9824 ? T_MNEM_movs
: T_MNEM_mov
);
9825 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9826 encode_thumb32_shifted_operand (1);
9827 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
9828 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9833 if (inst
.operands
[2].isreg
)
9837 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9838 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9839 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9840 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9844 inst
.instruction
|= inst
.operands
[0].reg
;
9845 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9851 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9852 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9853 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9856 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9857 inst
.instruction
|= inst
.operands
[0].reg
;
9858 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9864 constraint (inst
.operands
[0].reg
> 7
9865 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
9866 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9868 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
9870 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
9871 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
9872 _("source1 and dest must be same register"));
9874 switch (inst
.instruction
)
9876 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
9877 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
9878 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
9879 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
9883 inst
.instruction
|= inst
.operands
[0].reg
;
9884 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
9888 switch (inst
.instruction
)
9890 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9891 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9892 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9893 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
9896 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9897 inst
.instruction
|= inst
.operands
[0].reg
;
9898 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9906 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9907 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9908 inst
.instruction
|= inst
.operands
[2].reg
;
9914 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9915 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9916 _("expression too complex"));
9917 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9918 inst
.instruction
|= (value
& 0xf000) >> 12;
9919 inst
.instruction
|= (value
& 0x0ff0);
9920 inst
.instruction
|= (value
& 0x000f) << 16;
9926 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9927 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9928 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9930 if (inst
.operands
[3].present
)
9932 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9933 _("expression too complex"));
9935 if (inst
.reloc
.exp
.X_add_number
!= 0)
9937 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
9938 inst
.instruction
|= 0x00200000; /* sh bit */
9939 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
9940 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
9942 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9949 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9950 inst
.instruction
|= inst
.operands
[1].imm
- 1;
9951 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9957 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9958 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9959 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9960 || inst
.operands
[2].negative
,
9963 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9964 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9965 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9966 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9972 if (!inst
.operands
[2].present
)
9973 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
9975 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9976 || inst
.operands
[0].reg
== inst
.operands
[2].reg
9977 || inst
.operands
[0].reg
== inst
.operands
[3].reg
9978 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
9981 inst
.instruction
|= inst
.operands
[0].reg
;
9982 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9983 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9984 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9990 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9991 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9992 inst
.instruction
|= inst
.operands
[2].reg
;
9993 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
9999 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10000 && inst
.operands
[0].reg
<= 7 && inst
.operands
[1].reg
<= 7
10001 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10003 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10004 inst
.instruction
|= inst
.operands
[0].reg
;
10005 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10007 else if (unified_syntax
)
10009 if (inst
.instruction
<= 0xffff)
10010 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10011 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10012 inst
.instruction
|= inst
.operands
[1].reg
;
10013 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10017 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10018 _("Thumb encoding does not support rotation"));
10019 constraint (1, BAD_HIREG
);
10026 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10034 half
= (inst
.instruction
& 0x10) != 0;
10035 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10036 constraint (inst
.operands
[0].immisreg
,
10037 _("instruction requires register index"));
10038 constraint (inst
.operands
[0].imm
== 15,
10039 _("PC is not a valid index register"));
10040 constraint (!half
&& inst
.operands
[0].shifted
,
10041 _("instruction does not allow shifted index"));
10042 inst
.instruction
|= (inst
.operands
[0].reg
<< 16) | inst
.operands
[0].imm
;
10048 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10049 inst
.instruction
|= inst
.operands
[1].imm
;
10050 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10052 if (inst
.operands
[3].present
)
10054 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10055 _("expression too complex"));
10056 if (inst
.reloc
.exp
.X_add_number
!= 0)
10058 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10059 inst
.instruction
|= 0x00200000; /* sh bit */
10061 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10062 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10064 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10071 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10072 inst
.instruction
|= inst
.operands
[1].imm
;
10073 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10076 /* Neon instruction encoder helpers. */
10078 /* Encodings for the different types for various Neon opcodes. */
10080 /* An "invalid" code for the following tables. */
10083 struct neon_tab_entry
10086 unsigned float_or_poly
;
10087 unsigned scalar_or_imm
;
10090 /* Map overloaded Neon opcodes to their respective encodings. */
10091 #define NEON_ENC_TAB \
10092 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10093 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10094 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10095 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10096 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10097 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10098 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10099 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10100 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10101 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10102 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10103 /* Register variants of the following two instructions are encoded as
10104 vcge / vcgt with the operands reversed. */ \
10105 X(vclt, 0x0000310, 0x1000e00, 0x1b10200), \
10106 X(vcle, 0x0000300, 0x1200e00, 0x1b10180), \
10107 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10108 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10109 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10110 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10111 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10112 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10113 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10114 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10115 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10116 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10117 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10118 X(vshl, 0x0000400, N_INV, 0x0800510), \
10119 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10120 X(vand, 0x0000110, N_INV, 0x0800030), \
10121 X(vbic, 0x0100110, N_INV, 0x0800030), \
10122 X(veor, 0x1000110, N_INV, N_INV), \
10123 X(vorn, 0x0300110, N_INV, 0x0800010), \
10124 X(vorr, 0x0200110, N_INV, 0x0800010), \
10125 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10126 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10127 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10128 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10129 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10130 X(vst1, 0x0000000, 0x0800000, N_INV), \
10131 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10132 X(vst2, 0x0000100, 0x0800100, N_INV), \
10133 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10134 X(vst3, 0x0000200, 0x0800200, N_INV), \
10135 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10136 X(vst4, 0x0000300, 0x0800300, N_INV), \
10137 X(vmovn, 0x1b20200, N_INV, N_INV), \
10138 X(vtrn, 0x1b20080, N_INV, N_INV), \
10139 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10140 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10141 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10142 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10143 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10144 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10145 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10146 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10147 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10151 #define X(OPC,I,F,S) N_MNEM_##OPC
10156 static const struct neon_tab_entry neon_enc_tab
[] =
10158 #define X(OPC,I,F,S) { (I), (F), (S) }
10163 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10164 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10165 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10166 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10167 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10168 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10169 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10170 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10171 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10172 #define NEON_ENC_SINGLE(X) \
10173 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10174 #define NEON_ENC_DOUBLE(X) \
10175 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10177 /* Define shapes for instruction operands. The following mnemonic characters
10178 are used in this table:
10180 F - VFP S<n> register
10181 D - Neon D<n> register
10182 Q - Neon Q<n> register
10186 L - D<n> register list
10188 This table is used to generate various data:
10189 - enumerations of the form NS_DDR to be used as arguments to
10191 - a table classifying shapes into single, double, quad, mixed.
10192 - a table used to drive neon_select_shape.
10195 #define NEON_SHAPE_DEF \
10196 X(3, (D, D, D), DOUBLE), \
10197 X(3, (Q, Q, Q), QUAD), \
10198 X(3, (D, D, I), DOUBLE), \
10199 X(3, (Q, Q, I), QUAD), \
10200 X(3, (D, D, S), DOUBLE), \
10201 X(3, (Q, Q, S), QUAD), \
10202 X(2, (D, D), DOUBLE), \
10203 X(2, (Q, Q), QUAD), \
10204 X(2, (D, S), DOUBLE), \
10205 X(2, (Q, S), QUAD), \
10206 X(2, (D, R), DOUBLE), \
10207 X(2, (Q, R), QUAD), \
10208 X(2, (D, I), DOUBLE), \
10209 X(2, (Q, I), QUAD), \
10210 X(3, (D, L, D), DOUBLE), \
10211 X(2, (D, Q), MIXED), \
10212 X(2, (Q, D), MIXED), \
10213 X(3, (D, Q, I), MIXED), \
10214 X(3, (Q, D, I), MIXED), \
10215 X(3, (Q, D, D), MIXED), \
10216 X(3, (D, Q, Q), MIXED), \
10217 X(3, (Q, Q, D), MIXED), \
10218 X(3, (Q, D, S), MIXED), \
10219 X(3, (D, Q, S), MIXED), \
10220 X(4, (D, D, D, I), DOUBLE), \
10221 X(4, (Q, Q, Q, I), QUAD), \
10222 X(2, (F, F), SINGLE), \
10223 X(3, (F, F, F), SINGLE), \
10224 X(2, (F, I), SINGLE), \
10225 X(2, (F, D), MIXED), \
10226 X(2, (D, F), MIXED), \
10227 X(3, (F, F, I), MIXED), \
10228 X(4, (R, R, F, F), SINGLE), \
10229 X(4, (F, F, R, R), SINGLE), \
10230 X(3, (D, R, R), DOUBLE), \
10231 X(3, (R, R, D), DOUBLE), \
10232 X(2, (S, R), SINGLE), \
10233 X(2, (R, S), SINGLE), \
10234 X(2, (F, R), SINGLE), \
10235 X(2, (R, F), SINGLE)
10237 #define S2(A,B) NS_##A##B
10238 #define S3(A,B,C) NS_##A##B##C
10239 #define S4(A,B,C,D) NS_##A##B##C##D
10241 #define X(N, L, C) S##N L
10254 enum neon_shape_class
10262 #define X(N, L, C) SC_##C
10264 static enum neon_shape_class neon_shape_class
[] =
10282 /* Register widths of above. */
10283 static unsigned neon_shape_el_size
[] =
10294 struct neon_shape_info
10297 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
10300 #define S2(A,B) { SE_##A, SE_##B }
10301 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
10302 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
10304 #define X(N, L, C) { N, S##N L }
10306 static struct neon_shape_info neon_shape_tab
[] =
10316 /* Bit masks used in type checking given instructions.
10317 'N_EQK' means the type must be the same as (or based on in some way) the key
10318 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
10319 set, various other bits can be set as well in order to modify the meaning of
10320 the type constraint. */
10322 enum neon_type_mask
10344 N_KEY
= 0x100000, /* key element (main type specifier). */
10345 N_EQK
= 0x200000, /* given operand has the same type & size as the key. */
10346 N_VFP
= 0x400000, /* VFP mode: operand size must match register width. */
10347 N_DBL
= 0x000001, /* if N_EQK, this operand is twice the size. */
10348 N_HLF
= 0x000002, /* if N_EQK, this operand is half the size. */
10349 N_SGN
= 0x000004, /* if N_EQK, this operand is forced to be signed. */
10350 N_UNS
= 0x000008, /* if N_EQK, this operand is forced to be unsigned. */
10351 N_INT
= 0x000010, /* if N_EQK, this operand is forced to be integer. */
10352 N_FLT
= 0x000020, /* if N_EQK, this operand is forced to be float. */
10353 N_SIZ
= 0x000040, /* if N_EQK, this operand is forced to be size-only. */
10355 N_MAX_NONSPECIAL
= N_F64
10358 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
10360 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
10361 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
10362 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
10363 #define N_SUF_32 (N_SU_32 | N_F32)
10364 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
10365 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
10367 /* Pass this as the first type argument to neon_check_type to ignore types
10369 #define N_IGNORE_TYPE (N_KEY | N_EQK)
10371 /* Select a "shape" for the current instruction (describing register types or
10372 sizes) from a list of alternatives. Return NS_NULL if the current instruction
10373 doesn't fit. For non-polymorphic shapes, checking is usually done as a
10374 function of operand parsing, so this function doesn't need to be called.
10375 Shapes should be listed in order of decreasing length. */
10377 static enum neon_shape
10378 neon_select_shape (enum neon_shape shape
, ...)
10381 enum neon_shape first_shape
= shape
;
10383 /* Fix missing optional operands. FIXME: we don't know at this point how
10384 many arguments we should have, so this makes the assumption that we have
10385 > 1. This is true of all current Neon opcodes, I think, but may not be
10386 true in the future. */
10387 if (!inst
.operands
[1].present
)
10388 inst
.operands
[1] = inst
.operands
[0];
10390 va_start (ap
, shape
);
10392 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
10397 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
10399 if (!inst
.operands
[j
].present
)
10405 switch (neon_shape_tab
[shape
].el
[j
])
10408 if (!(inst
.operands
[j
].isreg
10409 && inst
.operands
[j
].isvec
10410 && inst
.operands
[j
].issingle
10411 && !inst
.operands
[j
].isquad
))
10416 if (!(inst
.operands
[j
].isreg
10417 && inst
.operands
[j
].isvec
10418 && !inst
.operands
[j
].isquad
10419 && !inst
.operands
[j
].issingle
))
10424 if (!(inst
.operands
[j
].isreg
10425 && !inst
.operands
[j
].isvec
))
10430 if (!(inst
.operands
[j
].isreg
10431 && inst
.operands
[j
].isvec
10432 && inst
.operands
[j
].isquad
10433 && !inst
.operands
[j
].issingle
))
10438 if (!(!inst
.operands
[j
].isreg
10439 && !inst
.operands
[j
].isscalar
))
10444 if (!(!inst
.operands
[j
].isreg
10445 && inst
.operands
[j
].isscalar
))
10459 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
10460 first_error (_("invalid instruction shape"));
10465 /* True if SHAPE is predominantly a quadword operation (most of the time, this
10466 means the Q bit should be set). */
10469 neon_quad (enum neon_shape shape
)
10471 return neon_shape_class
[shape
] == SC_QUAD
;
10475 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
10478 /* Allow modification to be made to types which are constrained to be
10479 based on the key element, based on bits set alongside N_EQK. */
10480 if ((typebits
& N_EQK
) != 0)
10482 if ((typebits
& N_HLF
) != 0)
10484 else if ((typebits
& N_DBL
) != 0)
10486 if ((typebits
& N_SGN
) != 0)
10487 *g_type
= NT_signed
;
10488 else if ((typebits
& N_UNS
) != 0)
10489 *g_type
= NT_unsigned
;
10490 else if ((typebits
& N_INT
) != 0)
10491 *g_type
= NT_integer
;
10492 else if ((typebits
& N_FLT
) != 0)
10493 *g_type
= NT_float
;
10494 else if ((typebits
& N_SIZ
) != 0)
10495 *g_type
= NT_untyped
;
10499 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
10500 operand type, i.e. the single type specified in a Neon instruction when it
10501 is the only one given. */
10503 static struct neon_type_el
10504 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
10506 struct neon_type_el dest
= *key
;
10508 assert ((thisarg
& N_EQK
) != 0);
10510 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
10515 /* Convert Neon type and size into compact bitmask representation. */
10517 static enum neon_type_mask
10518 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
10525 case 8: return N_8
;
10526 case 16: return N_16
;
10527 case 32: return N_32
;
10528 case 64: return N_64
;
10536 case 8: return N_I8
;
10537 case 16: return N_I16
;
10538 case 32: return N_I32
;
10539 case 64: return N_I64
;
10547 case 32: return N_F32
;
10548 case 64: return N_F64
;
10556 case 8: return N_P8
;
10557 case 16: return N_P16
;
10565 case 8: return N_S8
;
10566 case 16: return N_S16
;
10567 case 32: return N_S32
;
10568 case 64: return N_S64
;
10576 case 8: return N_U8
;
10577 case 16: return N_U16
;
10578 case 32: return N_U32
;
10579 case 64: return N_U64
;
10590 /* Convert compact Neon bitmask type representation to a type and size. Only
10591 handles the case where a single bit is set in the mask. */
10594 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
10595 enum neon_type_mask mask
)
10597 if ((mask
& N_EQK
) != 0)
10600 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
10602 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
10604 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
10606 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
10611 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
10613 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
10614 *type
= NT_unsigned
;
10615 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
10616 *type
= NT_integer
;
10617 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
10618 *type
= NT_untyped
;
10619 else if ((mask
& (N_P8
| N_P16
)) != 0)
10621 else if ((mask
& (N_F32
| N_F64
)) != 0)
10629 /* Modify a bitmask of allowed types. This is only needed for type
10633 modify_types_allowed (unsigned allowed
, unsigned mods
)
10636 enum neon_el_type type
;
10642 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
10644 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
10646 neon_modify_type_size (mods
, &type
, &size
);
10647 destmask
|= type_chk_of_el_type (type
, size
);
10654 /* Check type and return type classification.
10655 The manual states (paraphrase): If one datatype is given, it indicates the
10657 - the second operand, if there is one
10658 - the operand, if there is no second operand
10659 - the result, if there are no operands.
10660 This isn't quite good enough though, so we use a concept of a "key" datatype
10661 which is set on a per-instruction basis, which is the one which matters when
10662 only one data type is written.
10663 Note: this function has side-effects (e.g. filling in missing operands). All
10664 Neon instructions should call it before performing bit encoding. */
10666 static struct neon_type_el
10667 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
10670 unsigned i
, pass
, key_el
= 0;
10671 unsigned types
[NEON_MAX_TYPE_ELS
];
10672 enum neon_el_type k_type
= NT_invtype
;
10673 unsigned k_size
= -1u;
10674 struct neon_type_el badtype
= {NT_invtype
, -1};
10675 unsigned key_allowed
= 0;
10677 /* Optional registers in Neon instructions are always (not) in operand 1.
10678 Fill in the missing operand here, if it was omitted. */
10679 if (els
> 1 && !inst
.operands
[1].present
)
10680 inst
.operands
[1] = inst
.operands
[0];
10682 /* Suck up all the varargs. */
10684 for (i
= 0; i
< els
; i
++)
10686 unsigned thisarg
= va_arg (ap
, unsigned);
10687 if (thisarg
== N_IGNORE_TYPE
)
10692 types
[i
] = thisarg
;
10693 if ((thisarg
& N_KEY
) != 0)
10698 if (inst
.vectype
.elems
> 0)
10699 for (i
= 0; i
< els
; i
++)
10700 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
10702 first_error (_("types specified in both the mnemonic and operands"));
10706 /* Duplicate inst.vectype elements here as necessary.
10707 FIXME: No idea if this is exactly the same as the ARM assembler,
10708 particularly when an insn takes one register and one non-register
10710 if (inst
.vectype
.elems
== 1 && els
> 1)
10713 inst
.vectype
.elems
= els
;
10714 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
10715 for (j
= 0; j
< els
; j
++)
10717 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10720 else if (inst
.vectype
.elems
== 0 && els
> 0)
10723 /* No types were given after the mnemonic, so look for types specified
10724 after each operand. We allow some flexibility here; as long as the
10725 "key" operand has a type, we can infer the others. */
10726 for (j
= 0; j
< els
; j
++)
10727 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
10728 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
10730 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
10732 for (j
= 0; j
< els
; j
++)
10733 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
10734 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
10739 first_error (_("operand types can't be inferred"));
10743 else if (inst
.vectype
.elems
!= els
)
10745 first_error (_("type specifier has the wrong number of parts"));
10749 for (pass
= 0; pass
< 2; pass
++)
10751 for (i
= 0; i
< els
; i
++)
10753 unsigned thisarg
= types
[i
];
10754 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
10755 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
10756 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
10757 unsigned g_size
= inst
.vectype
.el
[i
].size
;
10759 /* Decay more-specific signed & unsigned types to sign-insensitive
10760 integer types if sign-specific variants are unavailable. */
10761 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
10762 && (types_allowed
& N_SU_ALL
) == 0)
10763 g_type
= NT_integer
;
10765 /* If only untyped args are allowed, decay any more specific types to
10766 them. Some instructions only care about signs for some element
10767 sizes, so handle that properly. */
10768 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
10769 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
10770 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
10771 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
10772 g_type
= NT_untyped
;
10776 if ((thisarg
& N_KEY
) != 0)
10780 key_allowed
= thisarg
& ~N_KEY
;
10785 if ((thisarg
& N_VFP
) != 0)
10787 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
10788 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
10790 /* In VFP mode, operands must match register widths. If we
10791 have a key operand, use its width, else use the width of
10792 the current operand. */
10798 if (regwidth
!= match
)
10800 first_error (_("operand size must match register width"));
10805 if ((thisarg
& N_EQK
) == 0)
10807 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
10809 if ((given_type
& types_allowed
) == 0)
10811 first_error (_("bad type in Neon instruction"));
10817 enum neon_el_type mod_k_type
= k_type
;
10818 unsigned mod_k_size
= k_size
;
10819 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
10820 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
10822 first_error (_("inconsistent types in Neon instruction"));
10830 return inst
.vectype
.el
[key_el
];
10833 /* Neon-style VFP instruction forwarding. */
10835 /* Thumb VFP instructions have 0xE in the condition field. */
10838 do_vfp_cond_or_thumb (void)
10841 inst
.instruction
|= 0xe0000000;
10843 inst
.instruction
|= inst
.cond
<< 28;
10846 /* Look up and encode a simple mnemonic, for use as a helper function for the
10847 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
10848 etc. It is assumed that operand parsing has already been done, and that the
10849 operands are in the form expected by the given opcode (this isn't necessarily
10850 the same as the form in which they were parsed, hence some massaging must
10851 take place before this function is called).
10852 Checks current arch version against that in the looked-up opcode. */
10855 do_vfp_nsyn_opcode (const char *opname
)
10857 const struct asm_opcode
*opcode
;
10859 opcode
= hash_find (arm_ops_hsh
, opname
);
10864 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
10865 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
10870 inst
.instruction
= opcode
->tvalue
;
10871 opcode
->tencode ();
10875 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
10876 opcode
->aencode ();
10881 do_vfp_nsyn_add_sub (enum neon_shape rs
)
10883 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
10888 do_vfp_nsyn_opcode ("fadds");
10890 do_vfp_nsyn_opcode ("fsubs");
10895 do_vfp_nsyn_opcode ("faddd");
10897 do_vfp_nsyn_opcode ("fsubd");
10901 /* Check operand types to see if this is a VFP instruction, and if so call
10905 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
10907 enum neon_shape rs
;
10908 struct neon_type_el et
;
10913 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
10914 et
= neon_check_type (2, rs
,
10915 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10919 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
10920 et
= neon_check_type (3, rs
,
10921 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
10928 if (et
.type
!= NT_invtype
)
10940 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
10942 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
10947 do_vfp_nsyn_opcode ("fmacs");
10949 do_vfp_nsyn_opcode ("fmscs");
10954 do_vfp_nsyn_opcode ("fmacd");
10956 do_vfp_nsyn_opcode ("fmscd");
10961 do_vfp_nsyn_mul (enum neon_shape rs
)
10964 do_vfp_nsyn_opcode ("fmuls");
10966 do_vfp_nsyn_opcode ("fmuld");
10970 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
10972 int is_neg
= (inst
.instruction
& 0x80) != 0;
10973 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
10978 do_vfp_nsyn_opcode ("fnegs");
10980 do_vfp_nsyn_opcode ("fabss");
10985 do_vfp_nsyn_opcode ("fnegd");
10987 do_vfp_nsyn_opcode ("fabsd");
10991 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
10992 insns belong to Neon, and are handled elsewhere. */
10995 do_vfp_nsyn_ldm_stm (int is_dbmode
)
10997 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11001 do_vfp_nsyn_opcode ("fldmdbs");
11003 do_vfp_nsyn_opcode ("fldmias");
11008 do_vfp_nsyn_opcode ("fstmdbs");
11010 do_vfp_nsyn_opcode ("fstmias");
11015 do_vfp_nsyn_sqrt (void)
11017 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11018 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11021 do_vfp_nsyn_opcode ("fsqrts");
11023 do_vfp_nsyn_opcode ("fsqrtd");
11027 do_vfp_nsyn_div (void)
11029 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11030 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11031 N_F32
| N_F64
| N_KEY
| N_VFP
);
11034 do_vfp_nsyn_opcode ("fdivs");
11036 do_vfp_nsyn_opcode ("fdivd");
11040 do_vfp_nsyn_nmul (void)
11042 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11043 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11044 N_F32
| N_F64
| N_KEY
| N_VFP
);
11048 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11049 do_vfp_sp_dyadic ();
11053 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11054 do_vfp_dp_rd_rn_rm ();
11056 do_vfp_cond_or_thumb ();
11060 do_vfp_nsyn_cmp (void)
11062 if (inst
.operands
[1].isreg
)
11064 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11065 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11069 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11070 do_vfp_sp_monadic ();
11074 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11075 do_vfp_dp_rd_rm ();
11080 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11081 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11083 switch (inst
.instruction
& 0x0fffffff)
11086 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11089 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11097 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11098 do_vfp_sp_compare_z ();
11102 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11106 do_vfp_cond_or_thumb ();
11110 nsyn_insert_sp (void)
11112 inst
.operands
[1] = inst
.operands
[0];
11113 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11114 inst
.operands
[0].reg
= 13;
11115 inst
.operands
[0].isreg
= 1;
11116 inst
.operands
[0].writeback
= 1;
11117 inst
.operands
[0].present
= 1;
11121 do_vfp_nsyn_push (void)
11124 if (inst
.operands
[1].issingle
)
11125 do_vfp_nsyn_opcode ("fstmdbs");
11127 do_vfp_nsyn_opcode ("fstmdbd");
11131 do_vfp_nsyn_pop (void)
11134 if (inst
.operands
[1].issingle
)
11135 do_vfp_nsyn_opcode ("fldmdbs");
11137 do_vfp_nsyn_opcode ("fldmdbd");
11140 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11141 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11144 neon_dp_fixup (unsigned i
)
11148 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11162 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11166 neon_logbits (unsigned x
)
11168 return ffs (x
) - 4;
11171 #define LOW4(R) ((R) & 0xf)
11172 #define HI1(R) (((R) >> 4) & 1)
11174 /* Encode insns with bit pattern:
11176 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11177 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11179 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11180 different meaning for some instruction. */
11183 neon_three_same (int isquad
, int ubit
, int size
)
11185 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11186 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11187 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11188 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11189 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11190 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11191 inst
.instruction
|= (isquad
!= 0) << 6;
11192 inst
.instruction
|= (ubit
!= 0) << 24;
11194 inst
.instruction
|= neon_logbits (size
) << 20;
11196 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11199 /* Encode instructions of the form:
11201 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11202 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11204 Don't write size if SIZE == -1. */
11207 neon_two_same (int qbit
, int ubit
, int size
)
11209 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11210 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11211 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11212 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11213 inst
.instruction
|= (qbit
!= 0) << 6;
11214 inst
.instruction
|= (ubit
!= 0) << 24;
11217 inst
.instruction
|= neon_logbits (size
) << 18;
11219 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11222 /* Neon instruction encoders, in approximate order of appearance. */
11225 do_neon_dyadic_i_su (void)
11227 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11228 struct neon_type_el et
= neon_check_type (3, rs
,
11229 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
11230 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11234 do_neon_dyadic_i64_su (void)
11236 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11237 struct neon_type_el et
= neon_check_type (3, rs
,
11238 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
11239 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11243 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
11246 unsigned size
= et
.size
>> 3;
11247 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11248 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11249 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11250 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11251 inst
.instruction
|= (isquad
!= 0) << 6;
11252 inst
.instruction
|= immbits
<< 16;
11253 inst
.instruction
|= (size
>> 3) << 7;
11254 inst
.instruction
|= (size
& 0x7) << 19;
11256 inst
.instruction
|= (uval
!= 0) << 24;
11258 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11262 do_neon_shl_imm (void)
11264 if (!inst
.operands
[2].isreg
)
11266 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11267 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
11268 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11269 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
11273 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11274 struct neon_type_el et
= neon_check_type (3, rs
,
11275 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11276 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11277 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11282 do_neon_qshl_imm (void)
11284 if (!inst
.operands
[2].isreg
)
11286 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11287 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
11288 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11289 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
11290 inst
.operands
[2].imm
);
11294 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11295 struct neon_type_el et
= neon_check_type (3, rs
,
11296 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
11297 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11298 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
11303 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
11305 /* Handle .I8 and .I64 as pseudo-instructions. */
11309 /* Unfortunately, this will make everything apart from zero out-of-range.
11310 FIXME is this the intended semantics? There doesn't seem much point in
11311 accepting .I8 if so. */
11312 immediate
|= immediate
<< 8;
11316 /* Similarly, anything other than zero will be replicated in bits [63:32],
11317 which probably isn't want we want if we specified .I64. */
11318 if (immediate
!= 0)
11319 goto bad_immediate
;
11325 if (immediate
== (immediate
& 0x000000ff))
11327 *immbits
= immediate
;
11328 return (size
== 16) ? 0x9 : 0x1;
11330 else if (immediate
== (immediate
& 0x0000ff00))
11332 *immbits
= immediate
>> 8;
11333 return (size
== 16) ? 0xb : 0x3;
11335 else if (immediate
== (immediate
& 0x00ff0000))
11337 *immbits
= immediate
>> 16;
11340 else if (immediate
== (immediate
& 0xff000000))
11342 *immbits
= immediate
>> 24;
11347 first_error (_("immediate value out of range"));
11351 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
11355 neon_bits_same_in_bytes (unsigned imm
)
11357 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
11358 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
11359 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
11360 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
11363 /* For immediate of above form, return 0bABCD. */
11366 neon_squash_bits (unsigned imm
)
11368 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
11369 | ((imm
& 0x01000000) >> 21);
11372 /* Compress quarter-float representation to 0b...000 abcdefgh. */
11375 neon_qfloat_bits (unsigned imm
)
11377 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
11380 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
11381 the instruction. *OP is passed as the initial value of the op field, and
11382 may be set to a different value depending on the constant (i.e.
11383 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
11387 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, unsigned *immbits
,
11388 int *op
, int size
, enum neon_el_type type
)
11390 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
11392 if (size
!= 32 || *op
== 1)
11394 *immbits
= neon_qfloat_bits (immlo
);
11397 else if (size
== 64 && neon_bits_same_in_bytes (immhi
)
11398 && neon_bits_same_in_bytes (immlo
))
11400 /* Check this one first so we don't have to bother with immhi in later
11404 *immbits
= (neon_squash_bits (immhi
) << 4) | neon_squash_bits (immlo
);
11408 else if (immhi
!= 0)
11410 else if (immlo
== (immlo
& 0x000000ff))
11412 /* 64-bit case was already handled. Don't allow MVN with 8-bit
11414 if ((size
!= 8 && size
!= 16 && size
!= 32)
11415 || (size
== 8 && *op
== 1))
11418 return (size
== 8) ? 0xe : (size
== 16) ? 0x8 : 0x0;
11420 else if (immlo
== (immlo
& 0x0000ff00))
11422 if (size
!= 16 && size
!= 32)
11424 *immbits
= immlo
>> 8;
11425 return (size
== 16) ? 0xa : 0x2;
11427 else if (immlo
== (immlo
& 0x00ff0000))
11431 *immbits
= immlo
>> 16;
11434 else if (immlo
== (immlo
& 0xff000000))
11438 *immbits
= immlo
>> 24;
11441 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
11445 *immbits
= (immlo
>> 8) & 0xff;
11448 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
11452 *immbits
= (immlo
>> 16) & 0xff;
11459 /* Write immediate bits [7:0] to the following locations:
11461 |28/24|23 19|18 16|15 4|3 0|
11462 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
11464 This function is used by VMOV/VMVN/VORR/VBIC. */
11467 neon_write_immbits (unsigned immbits
)
11469 inst
.instruction
|= immbits
& 0xf;
11470 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
11471 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
11474 /* Invert low-order SIZE bits of XHI:XLO. */
11477 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
11479 unsigned immlo
= xlo
? *xlo
: 0;
11480 unsigned immhi
= xhi
? *xhi
: 0;
11485 immlo
= (~immlo
) & 0xff;
11489 immlo
= (~immlo
) & 0xffff;
11493 immhi
= (~immhi
) & 0xffffffff;
11494 /* fall through. */
11497 immlo
= (~immlo
) & 0xffffffff;
11512 do_neon_logic (void)
11514 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
11516 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11517 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11518 /* U bit and size field were set as part of the bitmask. */
11519 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11520 neon_three_same (neon_quad (rs
), 0, -1);
11524 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
11525 struct neon_type_el et
= neon_check_type (2, rs
,
11526 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
11527 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
11531 if (et
.type
== NT_invtype
)
11534 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11539 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11544 cmode
= neon_cmode_for_logic_imm (inst
.operands
[1].imm
, &immbits
,
11549 /* Pseudo-instruction for VBIC. */
11550 immbits
= inst
.operands
[1].imm
;
11551 neon_invert_size (&immbits
, 0, et
.size
);
11552 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11556 /* Pseudo-instruction for VORR. */
11557 immbits
= inst
.operands
[1].imm
;
11558 neon_invert_size (&immbits
, 0, et
.size
);
11559 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
11569 inst
.instruction
|= neon_quad (rs
) << 6;
11570 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11571 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11572 inst
.instruction
|= cmode
<< 8;
11573 neon_write_immbits (immbits
);
11575 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11580 do_neon_bitfield (void)
11582 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11583 neon_check_type (3, rs
, N_IGNORE_TYPE
);
11584 neon_three_same (neon_quad (rs
), 0, -1);
11588 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
11591 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11592 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
11594 if (et
.type
== NT_float
)
11596 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
11597 neon_three_same (neon_quad (rs
), 0, -1);
11601 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11602 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
11607 do_neon_dyadic_if_su (void)
11609 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11613 do_neon_dyadic_if_su_d (void)
11615 /* This version only allow D registers, but that constraint is enforced during
11616 operand parsing so we don't need to do anything extra here. */
11617 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
11621 do_neon_dyadic_if_i (void)
11623 neon_dyadic_misc (NT_unsigned
, N_IF_32
, 0);
11627 do_neon_dyadic_if_i_d (void)
11629 neon_dyadic_misc (NT_unsigned
, N_IF_32
, 0);
11632 enum vfp_or_neon_is_neon_bits
11635 NEON_CHECK_ARCH
= 2
11638 /* Call this function if an instruction which may have belonged to the VFP or
11639 Neon instruction sets, but turned out to be a Neon instruction (due to the
11640 operand types involved, etc.). We have to check and/or fix-up a couple of
11643 - Make sure the user hasn't attempted to make a Neon instruction
11645 - Alter the value in the condition code field if necessary.
11646 - Make sure that the arch supports Neon instructions.
11648 Which of these operations take place depends on bits from enum
11649 vfp_or_neon_is_neon_bits.
11651 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
11652 current instruction's condition is COND_ALWAYS, the condition field is
11653 changed to inst.uncond_value. This is necessary because instructions shared
11654 between VFP and Neon may be conditional for the VFP variants only, and the
11655 unconditional Neon version must have, e.g., 0xF in the condition field. */
11658 vfp_or_neon_is_neon (unsigned check
)
11660 /* Conditions are always legal in Thumb mode (IT blocks). */
11661 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
11663 if (inst
.cond
!= COND_ALWAYS
)
11665 first_error (_(BAD_COND
));
11668 if (inst
.uncond_value
!= -1)
11669 inst
.instruction
|= inst
.uncond_value
<< 28;
11672 if ((check
& NEON_CHECK_ARCH
)
11673 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
11675 first_error (_(BAD_FPU
));
11683 do_neon_addsub_if_i (void)
11685 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
11688 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11691 /* The "untyped" case can't happen. Do this to stop the "U" bit being
11692 affected if we specify unsigned args. */
11693 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
11696 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
11698 V<op> A,B (A is operand 0, B is operand 2)
11703 so handle that case specially. */
11706 neon_exchange_operands (void)
11708 void *scratch
= alloca (sizeof (inst
.operands
[0]));
11709 if (inst
.operands
[1].present
)
11711 /* Swap operands[1] and operands[2]. */
11712 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
11713 inst
.operands
[1] = inst
.operands
[2];
11714 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
11718 inst
.operands
[1] = inst
.operands
[2];
11719 inst
.operands
[2] = inst
.operands
[0];
11724 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
11726 if (inst
.operands
[2].isreg
)
11729 neon_exchange_operands ();
11730 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
11734 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11735 struct neon_type_el et
= neon_check_type (2, rs
,
11736 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
11738 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
11739 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11740 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11741 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11742 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11743 inst
.instruction
|= neon_quad (rs
) << 6;
11744 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11745 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11747 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11754 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
11758 do_neon_cmp_inv (void)
11760 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
11766 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
11769 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
11770 scalars, which are encoded in 5 bits, M : Rm.
11771 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
11772 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
11776 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
11778 unsigned regno
= NEON_SCALAR_REG (scalar
);
11779 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
11784 if (regno
> 7 || elno
> 3)
11786 return regno
| (elno
<< 3);
11789 if (regno
> 15 || elno
> 1)
11791 return regno
| (elno
<< 4);
11795 first_error (_("scalar out of range for multiply instruction"));
11801 /* Encode multiply / multiply-accumulate scalar instructions. */
11804 neon_mul_mac (struct neon_type_el et
, int ubit
)
11808 /* Give a more helpful error message if we have an invalid type. */
11809 if (et
.type
== NT_invtype
)
11812 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
11813 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11814 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11815 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11816 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11817 inst
.instruction
|= LOW4 (scalar
);
11818 inst
.instruction
|= HI1 (scalar
) << 5;
11819 inst
.instruction
|= (et
.type
== NT_float
) << 8;
11820 inst
.instruction
|= neon_logbits (et
.size
) << 20;
11821 inst
.instruction
|= (ubit
!= 0) << 24;
11823 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11827 do_neon_mac_maybe_scalar (void)
11829 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
11832 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11835 if (inst
.operands
[2].isscalar
)
11837 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11838 struct neon_type_el et
= neon_check_type (3, rs
,
11839 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
11840 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11841 neon_mul_mac (et
, neon_quad (rs
));
11844 do_neon_dyadic_if_i ();
11850 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11851 struct neon_type_el et
= neon_check_type (3, rs
,
11852 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
11853 neon_three_same (neon_quad (rs
), 0, et
.size
);
11856 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
11857 same types as the MAC equivalents. The polynomial type for this instruction
11858 is encoded the same as the integer type. */
11863 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
11866 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11869 if (inst
.operands
[2].isscalar
)
11870 do_neon_mac_maybe_scalar ();
11872 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
11876 do_neon_qdmulh (void)
11878 if (inst
.operands
[2].isscalar
)
11880 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
11881 struct neon_type_el et
= neon_check_type (3, rs
,
11882 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11883 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
11884 neon_mul_mac (et
, neon_quad (rs
));
11888 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11889 struct neon_type_el et
= neon_check_type (3, rs
,
11890 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
11891 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11892 /* The U bit (rounding) comes from bit mask. */
11893 neon_three_same (neon_quad (rs
), 0, et
.size
);
11898 do_neon_fcmp_absolute (void)
11900 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11901 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11902 /* Size field comes from bit mask. */
11903 neon_three_same (neon_quad (rs
), 1, -1);
11907 do_neon_fcmp_absolute_inv (void)
11909 neon_exchange_operands ();
11910 do_neon_fcmp_absolute ();
11914 do_neon_step (void)
11916 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
11917 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
11918 neon_three_same (neon_quad (rs
), 0, -1);
11922 do_neon_abs_neg (void)
11924 enum neon_shape rs
;
11925 struct neon_type_el et
;
11927 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
11930 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
11933 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
11934 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
11936 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11937 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11938 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
11939 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
11940 inst
.instruction
|= neon_quad (rs
) << 6;
11941 inst
.instruction
|= (et
.type
== NT_float
) << 10;
11942 inst
.instruction
|= neon_logbits (et
.size
) << 18;
11944 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11950 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11951 struct neon_type_el et
= neon_check_type (2, rs
,
11952 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11953 int imm
= inst
.operands
[2].imm
;
11954 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11955 _("immediate out of range for insert"));
11956 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11962 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11963 struct neon_type_el et
= neon_check_type (2, rs
,
11964 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
11965 int imm
= inst
.operands
[2].imm
;
11966 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
11967 _("immediate out of range for insert"));
11968 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
11972 do_neon_qshlu_imm (void)
11974 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
11975 struct neon_type_el et
= neon_check_type (2, rs
,
11976 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
11977 int imm
= inst
.operands
[2].imm
;
11978 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
11979 _("immediate out of range for shift"));
11980 /* Only encodes the 'U present' variant of the instruction.
11981 In this case, signed types have OP (bit 8) set to 0.
11982 Unsigned types have OP set to 1. */
11983 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
11984 /* The rest of the bits are the same as other immediate shifts. */
11985 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
11989 do_neon_qmovn (void)
11991 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
11992 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
11993 /* Saturating move where operands can be signed or unsigned, and the
11994 destination has the same signedness. */
11995 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
11996 if (et
.type
== NT_unsigned
)
11997 inst
.instruction
|= 0xc0;
11999 inst
.instruction
|= 0x80;
12000 neon_two_same (0, 1, et
.size
/ 2);
12004 do_neon_qmovun (void)
12006 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12007 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12008 /* Saturating move with unsigned results. Operands must be signed. */
12009 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12010 neon_two_same (0, 1, et
.size
/ 2);
12014 do_neon_rshift_sat_narrow (void)
12016 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12017 or unsigned. If operands are unsigned, results must also be unsigned. */
12018 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12019 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12020 int imm
= inst
.operands
[2].imm
;
12021 /* This gets the bounds check, size encoding and immediate bits calculation
12025 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12026 VQMOVN.I<size> <Dd>, <Qm>. */
12029 inst
.operands
[2].present
= 0;
12030 inst
.instruction
= N_MNEM_vqmovn
;
12035 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12036 _("immediate out of range"));
12037 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12041 do_neon_rshift_sat_narrow_u (void)
12043 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12044 or unsigned. If operands are unsigned, results must also be unsigned. */
12045 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12046 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12047 int imm
= inst
.operands
[2].imm
;
12048 /* This gets the bounds check, size encoding and immediate bits calculation
12052 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12053 VQMOVUN.I<size> <Dd>, <Qm>. */
12056 inst
.operands
[2].present
= 0;
12057 inst
.instruction
= N_MNEM_vqmovun
;
12062 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12063 _("immediate out of range"));
12064 /* FIXME: The manual is kind of unclear about what value U should have in
12065 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12067 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12071 do_neon_movn (void)
12073 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12074 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12075 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12076 neon_two_same (0, 1, et
.size
/ 2);
12080 do_neon_rshift_narrow (void)
12082 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12083 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12084 int imm
= inst
.operands
[2].imm
;
12085 /* This gets the bounds check, size encoding and immediate bits calculation
12089 /* If immediate is zero then we are a pseudo-instruction for
12090 VMOVN.I<size> <Dd>, <Qm> */
12093 inst
.operands
[2].present
= 0;
12094 inst
.instruction
= N_MNEM_vmovn
;
12099 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12100 _("immediate out of range for narrowing operation"));
12101 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12105 do_neon_shll (void)
12107 /* FIXME: Type checking when lengthening. */
12108 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12109 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12110 unsigned imm
= inst
.operands
[2].imm
;
12112 if (imm
== et
.size
)
12114 /* Maximum shift variant. */
12115 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12116 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12117 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12118 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12119 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12120 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12122 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12126 /* A more-specific type check for non-max versions. */
12127 et
= neon_check_type (2, NS_QDI
,
12128 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12129 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12130 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
12134 /* Check the various types for the VCVT instruction, and return which version
12135 the current instruction is. */
12138 neon_cvt_flavour (enum neon_shape rs
)
12140 #define CVT_VAR(C,X,Y) \
12141 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
12142 if (et.type != NT_invtype) \
12144 inst.error = NULL; \
12147 struct neon_type_el et
;
12148 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
12149 || rs
== NS_FF
) ? N_VFP
: 0;
12150 /* The instruction versions which take an immediate take one register
12151 argument, which is extended to the width of the full register. Thus the
12152 "source" and "destination" registers must have the same width. Hack that
12153 here by making the size equal to the key (wider, in this case) operand. */
12154 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
12156 CVT_VAR (0, N_S32
, N_F32
);
12157 CVT_VAR (1, N_U32
, N_F32
);
12158 CVT_VAR (2, N_F32
, N_S32
);
12159 CVT_VAR (3, N_F32
, N_U32
);
12163 /* VFP instructions. */
12164 CVT_VAR (4, N_F32
, N_F64
);
12165 CVT_VAR (5, N_F64
, N_F32
);
12166 CVT_VAR (6, N_S32
, N_F64
| key
);
12167 CVT_VAR (7, N_U32
, N_F64
| key
);
12168 CVT_VAR (8, N_F64
| key
, N_S32
);
12169 CVT_VAR (9, N_F64
| key
, N_U32
);
12170 /* VFP instructions with bitshift. */
12171 CVT_VAR (10, N_F32
| key
, N_S16
);
12172 CVT_VAR (11, N_F32
| key
, N_U16
);
12173 CVT_VAR (12, N_F64
| key
, N_S16
);
12174 CVT_VAR (13, N_F64
| key
, N_U16
);
12175 CVT_VAR (14, N_S16
, N_F32
| key
);
12176 CVT_VAR (15, N_U16
, N_F32
| key
);
12177 CVT_VAR (16, N_S16
, N_F64
| key
);
12178 CVT_VAR (17, N_U16
, N_F64
| key
);
12184 /* Neon-syntax VFP conversions. */
12187 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
12189 const char *opname
= 0;
12191 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
12193 /* Conversions with immediate bitshift. */
12194 const char *enc
[] =
12216 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12218 opname
= enc
[flavour
];
12219 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12220 _("operands 0 and 1 must be the same register"));
12221 inst
.operands
[1] = inst
.operands
[2];
12222 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
12227 /* Conversions without bitshift. */
12228 const char *enc
[] =
12242 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
12243 opname
= enc
[flavour
];
12247 do_vfp_nsyn_opcode (opname
);
12251 do_vfp_nsyn_cvtz (void)
12253 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
12254 int flavour
= neon_cvt_flavour (rs
);
12255 const char *enc
[] =
12267 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
12268 do_vfp_nsyn_opcode (enc
[flavour
]);
12274 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
12275 NS_FD
, NS_DF
, NS_FF
, NS_NULL
);
12276 int flavour
= neon_cvt_flavour (rs
);
12278 /* VFP rather than Neon conversions. */
12281 do_vfp_nsyn_cvt (rs
, flavour
);
12290 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12293 /* Fixed-point conversion with #0 immediate is encoded as an
12294 integer conversion. */
12295 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
12297 unsigned immbits
= 32 - inst
.operands
[2].imm
;
12298 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
12299 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12301 inst
.instruction
|= enctab
[flavour
];
12302 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12303 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12304 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12305 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12306 inst
.instruction
|= neon_quad (rs
) << 6;
12307 inst
.instruction
|= 1 << 21;
12308 inst
.instruction
|= immbits
<< 16;
12310 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12318 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
12320 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12322 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12326 inst
.instruction
|= enctab
[flavour
];
12328 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12329 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12330 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12331 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12332 inst
.instruction
|= neon_quad (rs
) << 6;
12333 inst
.instruction
|= 2 << 18;
12335 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12340 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
12341 do_vfp_nsyn_cvt (rs
, flavour
);
12346 neon_move_immediate (void)
12348 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12349 struct neon_type_el et
= neon_check_type (2, rs
,
12350 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12351 unsigned immlo
, immhi
= 0, immbits
;
12354 constraint (et
.type
== NT_invtype
,
12355 _("operand size must be specified for immediate VMOV"));
12357 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
12358 op
= (inst
.instruction
& (1 << 5)) != 0;
12360 immlo
= inst
.operands
[1].imm
;
12361 if (inst
.operands
[1].regisimm
)
12362 immhi
= inst
.operands
[1].reg
;
12364 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
12365 _("immediate has bits set outside the operand size"));
12367 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12368 et
.size
, et
.type
)) == FAIL
)
12370 /* Invert relevant bits only. */
12371 neon_invert_size (&immlo
, &immhi
, et
.size
);
12372 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
12373 with one or the other; those cases are caught by
12374 neon_cmode_for_move_imm. */
12376 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, &immbits
, &op
,
12377 et
.size
, et
.type
)) == FAIL
)
12379 first_error (_("immediate out of range"));
12384 inst
.instruction
&= ~(1 << 5);
12385 inst
.instruction
|= op
<< 5;
12387 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12388 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12389 inst
.instruction
|= neon_quad (rs
) << 6;
12390 inst
.instruction
|= cmode
<< 8;
12392 neon_write_immbits (immbits
);
12398 if (inst
.operands
[1].isreg
)
12400 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12402 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12403 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12404 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12405 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12406 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12407 inst
.instruction
|= neon_quad (rs
) << 6;
12411 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12412 neon_move_immediate ();
12415 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12418 /* Encode instructions of form:
12420 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
12421 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm |
12426 neon_mixed_length (struct neon_type_el et
, unsigned size
)
12428 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12429 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12430 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12431 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12432 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12433 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12434 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
12435 inst
.instruction
|= neon_logbits (size
) << 20;
12437 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12441 do_neon_dyadic_long (void)
12443 /* FIXME: Type checking for lengthening op. */
12444 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12445 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12446 neon_mixed_length (et
, et
.size
);
12450 do_neon_abal (void)
12452 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12453 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
12454 neon_mixed_length (et
, et
.size
);
12458 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
12460 if (inst
.operands
[2].isscalar
)
12462 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
12463 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
12464 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12465 neon_mul_mac (et
, et
.type
== NT_unsigned
);
12469 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12470 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
12471 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12472 neon_mixed_length (et
, et
.size
);
12477 do_neon_mac_maybe_scalar_long (void)
12479 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
12483 do_neon_dyadic_wide (void)
12485 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
12486 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12487 neon_mixed_length (et
, et
.size
);
12491 do_neon_dyadic_narrow (void)
12493 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12494 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
12495 neon_mixed_length (et
, et
.size
/ 2);
12499 do_neon_mul_sat_scalar_long (void)
12501 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
12505 do_neon_vmull (void)
12507 if (inst
.operands
[2].isscalar
)
12508 do_neon_mac_maybe_scalar_long ();
12511 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
12512 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
12513 if (et
.type
== NT_poly
)
12514 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
12516 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12517 /* For polynomial encoding, size field must be 0b00 and the U bit must be
12518 zero. Should be OK as-is. */
12519 neon_mixed_length (et
, et
.size
);
12526 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
12527 struct neon_type_el et
= neon_check_type (3, rs
,
12528 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12529 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
12530 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12531 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12532 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12533 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12534 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12535 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12536 inst
.instruction
|= neon_quad (rs
) << 6;
12537 inst
.instruction
|= imm
<< 8;
12539 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12545 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12546 struct neon_type_el et
= neon_check_type (2, rs
,
12547 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12548 unsigned op
= (inst
.instruction
>> 7) & 3;
12549 /* N (width of reversed regions) is encoded as part of the bitmask. We
12550 extract it here to check the elements to be reversed are smaller.
12551 Otherwise we'd get a reserved instruction. */
12552 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
12553 assert (elsize
!= 0);
12554 constraint (et
.size
>= elsize
,
12555 _("elements must be smaller than reversal region"));
12556 neon_two_same (neon_quad (rs
), 1, et
.size
);
12562 if (inst
.operands
[1].isscalar
)
12564 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
12565 struct neon_type_el et
= neon_check_type (2, rs
,
12566 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12567 unsigned sizebits
= et
.size
>> 3;
12568 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12569 int logsize
= neon_logbits (et
.size
);
12570 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
12572 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
12575 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12576 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12577 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12578 inst
.instruction
|= LOW4 (dm
);
12579 inst
.instruction
|= HI1 (dm
) << 5;
12580 inst
.instruction
|= neon_quad (rs
) << 6;
12581 inst
.instruction
|= x
<< 17;
12582 inst
.instruction
|= sizebits
<< 16;
12584 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12588 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
12589 struct neon_type_el et
= neon_check_type (2, rs
,
12590 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12591 /* Duplicate ARM register to lanes of vector. */
12592 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
12595 case 8: inst
.instruction
|= 0x400000; break;
12596 case 16: inst
.instruction
|= 0x000020; break;
12597 case 32: inst
.instruction
|= 0x000000; break;
12600 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
12601 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
12602 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
12603 inst
.instruction
|= neon_quad (rs
) << 21;
12604 /* The encoding for this instruction is identical for the ARM and Thumb
12605 variants, except for the condition field. */
12606 do_vfp_cond_or_thumb ();
12610 /* VMOV has particularly many variations. It can be one of:
12611 0. VMOV<c><q> <Qd>, <Qm>
12612 1. VMOV<c><q> <Dd>, <Dm>
12613 (Register operations, which are VORR with Rm = Rn.)
12614 2. VMOV<c><q>.<dt> <Qd>, #<imm>
12615 3. VMOV<c><q>.<dt> <Dd>, #<imm>
12617 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
12618 (ARM register to scalar.)
12619 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
12620 (Two ARM registers to vector.)
12621 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
12622 (Scalar to ARM register.)
12623 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
12624 (Vector to two ARM registers.)
12625 8. VMOV.F32 <Sd>, <Sm>
12626 9. VMOV.F64 <Dd>, <Dm>
12627 (VFP register moves.)
12628 10. VMOV.F32 <Sd>, #imm
12629 11. VMOV.F64 <Dd>, #imm
12630 (VFP float immediate load.)
12631 12. VMOV <Rd>, <Sm>
12632 (VFP single to ARM reg.)
12633 13. VMOV <Sd>, <Rm>
12634 (ARM reg to VFP single.)
12635 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
12636 (Two ARM regs to two VFP singles.)
12637 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
12638 (Two VFP singles to two ARM regs.)
12640 These cases can be disambiguated using neon_select_shape, except cases 1/9
12641 and 3/11 which depend on the operand type too.
12643 All the encoded bits are hardcoded by this function.
12645 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
12646 Cases 5, 7 may be used with VFPv2 and above.
12648 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
12649 can specify a type where it doesn't make sense to, and is ignored).
12655 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
12656 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
12658 struct neon_type_el et
;
12659 const char *ldconst
= 0;
12663 case NS_DD
: /* case 1/9. */
12664 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12665 /* It is not an error here if no type is given. */
12667 if (et
.type
== NT_float
&& et
.size
== 64)
12669 do_vfp_nsyn_opcode ("fcpyd");
12672 /* fall through. */
12674 case NS_QQ
: /* case 0/1. */
12676 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12678 /* The architecture manual I have doesn't explicitly state which
12679 value the U bit should have for register->register moves, but
12680 the equivalent VORR instruction has U = 0, so do that. */
12681 inst
.instruction
= 0x0200110;
12682 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12683 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12684 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12685 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12686 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12687 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12688 inst
.instruction
|= neon_quad (rs
) << 6;
12690 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12694 case NS_DI
: /* case 3/11. */
12695 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
12697 if (et
.type
== NT_float
&& et
.size
== 64)
12699 /* case 11 (fconstd). */
12700 ldconst
= "fconstd";
12701 goto encode_fconstd
;
12703 /* fall through. */
12705 case NS_QI
: /* case 2/3. */
12706 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12708 inst
.instruction
= 0x0800010;
12709 neon_move_immediate ();
12710 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12713 case NS_SR
: /* case 4. */
12715 unsigned bcdebits
= 0;
12716 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12717 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
12718 int logsize
= neon_logbits (et
.size
);
12719 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
12720 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
12722 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12725 && et
.size
!= 32, _(BAD_FPU
));
12726 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12727 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12731 case 8: bcdebits
= 0x8; break;
12732 case 16: bcdebits
= 0x1; break;
12733 case 32: bcdebits
= 0x0; break;
12737 bcdebits
|= x
<< logsize
;
12739 inst
.instruction
= 0xe000b10;
12740 do_vfp_cond_or_thumb ();
12741 inst
.instruction
|= LOW4 (dn
) << 16;
12742 inst
.instruction
|= HI1 (dn
) << 7;
12743 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12744 inst
.instruction
|= (bcdebits
& 3) << 5;
12745 inst
.instruction
|= (bcdebits
>> 2) << 21;
12749 case NS_DRR
: /* case 5 (fmdrr). */
12750 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12753 inst
.instruction
= 0xc400b10;
12754 do_vfp_cond_or_thumb ();
12755 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
12756 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
12757 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12758 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12761 case NS_RS
: /* case 6. */
12763 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
12764 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
12765 unsigned logsize
= neon_logbits (et
.size
);
12766 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
12767 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
12768 unsigned abcdebits
= 0;
12770 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
12772 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
12773 && et
.size
!= 32, _(BAD_FPU
));
12774 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
12775 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
12779 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
12780 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
12781 case 32: abcdebits
= 0x00; break;
12785 abcdebits
|= x
<< logsize
;
12786 inst
.instruction
= 0xe100b10;
12787 do_vfp_cond_or_thumb ();
12788 inst
.instruction
|= LOW4 (dn
) << 16;
12789 inst
.instruction
|= HI1 (dn
) << 7;
12790 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12791 inst
.instruction
|= (abcdebits
& 3) << 5;
12792 inst
.instruction
|= (abcdebits
>> 2) << 21;
12796 case NS_RRD
: /* case 7 (fmrrd). */
12797 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
12800 inst
.instruction
= 0xc500b10;
12801 do_vfp_cond_or_thumb ();
12802 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12803 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12804 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12805 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12808 case NS_FF
: /* case 8 (fcpys). */
12809 do_vfp_nsyn_opcode ("fcpys");
12812 case NS_FI
: /* case 10 (fconsts). */
12813 ldconst
= "fconsts";
12815 if (is_quarter_float (inst
.operands
[1].imm
))
12817 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
12818 do_vfp_nsyn_opcode (ldconst
);
12821 first_error (_("immediate out of range"));
12824 case NS_RF
: /* case 12 (fmrs). */
12825 do_vfp_nsyn_opcode ("fmrs");
12828 case NS_FR
: /* case 13 (fmsr). */
12829 do_vfp_nsyn_opcode ("fmsr");
12832 /* The encoders for the fmrrs and fmsrr instructions expect three operands
12833 (one of which is a list), but we have parsed four. Do some fiddling to
12834 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
12836 case NS_RRFF
: /* case 14 (fmrrs). */
12837 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
12838 _("VFP registers must be adjacent"));
12839 inst
.operands
[2].imm
= 2;
12840 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12841 do_vfp_nsyn_opcode ("fmrrs");
12844 case NS_FFRR
: /* case 15 (fmsrr). */
12845 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
12846 _("VFP registers must be adjacent"));
12847 inst
.operands
[1] = inst
.operands
[2];
12848 inst
.operands
[2] = inst
.operands
[3];
12849 inst
.operands
[0].imm
= 2;
12850 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
12851 do_vfp_nsyn_opcode ("fmsrr");
12860 do_neon_rshift_round_imm (void)
12862 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12863 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12864 int imm
= inst
.operands
[2].imm
;
12866 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
12869 inst
.operands
[2].present
= 0;
12874 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12875 _("immediate out of range for shift"));
12876 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12881 do_neon_movl (void)
12883 struct neon_type_el et
= neon_check_type (2, NS_QD
,
12884 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
12885 unsigned sizebits
= et
.size
>> 3;
12886 inst
.instruction
|= sizebits
<< 19;
12887 neon_two_same (0, et
.type
== NT_unsigned
, -1);
12893 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12894 struct neon_type_el et
= neon_check_type (2, rs
,
12895 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12896 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12897 neon_two_same (neon_quad (rs
), 1, et
.size
);
12901 do_neon_zip_uzp (void)
12903 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12904 struct neon_type_el et
= neon_check_type (2, rs
,
12905 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12906 if (rs
== NS_DD
&& et
.size
== 32)
12908 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
12909 inst
.instruction
= N_MNEM_vtrn
;
12913 neon_two_same (neon_quad (rs
), 1, et
.size
);
12917 do_neon_sat_abs_neg (void)
12919 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12920 struct neon_type_el et
= neon_check_type (2, rs
,
12921 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12922 neon_two_same (neon_quad (rs
), 1, et
.size
);
12926 do_neon_pair_long (void)
12928 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12929 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
12930 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
12931 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
12932 neon_two_same (neon_quad (rs
), 1, et
.size
);
12936 do_neon_recip_est (void)
12938 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12939 struct neon_type_el et
= neon_check_type (2, rs
,
12940 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
12941 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12942 neon_two_same (neon_quad (rs
), 1, et
.size
);
12948 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12949 struct neon_type_el et
= neon_check_type (2, rs
,
12950 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
12951 neon_two_same (neon_quad (rs
), 1, et
.size
);
12957 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12958 struct neon_type_el et
= neon_check_type (2, rs
,
12959 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
12960 neon_two_same (neon_quad (rs
), 1, et
.size
);
12966 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12967 struct neon_type_el et
= neon_check_type (2, rs
,
12968 N_EQK
| N_INT
, N_8
| N_KEY
);
12969 neon_two_same (neon_quad (rs
), 1, et
.size
);
12975 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12976 neon_two_same (neon_quad (rs
), 1, -1);
12980 do_neon_tbl_tbx (void)
12982 unsigned listlenbits
;
12983 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
12985 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
12987 first_error (_("bad list length for table lookup"));
12991 listlenbits
= inst
.operands
[1].imm
- 1;
12992 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12993 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12994 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12995 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12996 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
12997 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
12998 inst
.instruction
|= listlenbits
<< 8;
13000 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13004 do_neon_ldm_stm (void)
13006 /* P, U and L bits are part of bitmask. */
13007 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13008 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13010 if (inst
.operands
[1].issingle
)
13012 do_vfp_nsyn_ldm_stm (is_dbmode
);
13016 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13017 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13019 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13020 _("register list must contain at least 1 and at most 16 "
13023 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13024 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13025 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13026 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13028 inst
.instruction
|= offsetbits
;
13030 do_vfp_cond_or_thumb ();
13034 do_neon_ldr_str (void)
13036 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13038 if (inst
.operands
[0].issingle
)
13041 do_vfp_nsyn_opcode ("flds");
13043 do_vfp_nsyn_opcode ("fsts");
13048 do_vfp_nsyn_opcode ("fldd");
13050 do_vfp_nsyn_opcode ("fstd");
13054 /* "interleave" version also handles non-interleaving register VLD1/VST1
13058 do_neon_ld_st_interleave (void)
13060 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
13061 N_8
| N_16
| N_32
| N_64
);
13062 unsigned alignbits
= 0;
13064 /* The bits in this table go:
13065 0: register stride of one (0) or two (1)
13066 1,2: register list length, minus one (1, 2, 3, 4).
13067 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
13068 We use -1 for invalid entries. */
13069 const int typetable
[] =
13071 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
13072 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
13073 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
13074 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
13078 if (et
.type
== NT_invtype
)
13081 if (inst
.operands
[1].immisalign
)
13082 switch (inst
.operands
[1].imm
>> 8)
13084 case 64: alignbits
= 1; break;
13086 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13087 goto bad_alignment
;
13091 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
13092 goto bad_alignment
;
13097 first_error (_("bad alignment"));
13101 inst
.instruction
|= alignbits
<< 4;
13102 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13104 /* Bits [4:6] of the immediate in a list specifier encode register stride
13105 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
13106 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
13107 up the right value for "type" in a table based on this value and the given
13108 list style, then stick it back. */
13109 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
13110 | (((inst
.instruction
>> 8) & 3) << 3);
13112 typebits
= typetable
[idx
];
13114 constraint (typebits
== -1, _("bad list type for instruction"));
13116 inst
.instruction
&= ~0xf00;
13117 inst
.instruction
|= typebits
<< 8;
13120 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
13121 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
13122 otherwise. The variable arguments are a list of pairs of legal (size, align)
13123 values, terminated with -1. */
13126 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
13129 int result
= FAIL
, thissize
, thisalign
;
13131 if (!inst
.operands
[1].immisalign
)
13137 va_start (ap
, do_align
);
13141 thissize
= va_arg (ap
, int);
13142 if (thissize
== -1)
13144 thisalign
= va_arg (ap
, int);
13146 if (size
== thissize
&& align
== thisalign
)
13149 while (result
!= SUCCESS
);
13153 if (result
== SUCCESS
)
13156 first_error (_("unsupported alignment for instruction"));
13162 do_neon_ld_st_lane (void)
13164 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13165 int align_good
, do_align
= 0;
13166 int logsize
= neon_logbits (et
.size
);
13167 int align
= inst
.operands
[1].imm
>> 8;
13168 int n
= (inst
.instruction
>> 8) & 3;
13169 int max_el
= 64 / et
.size
;
13171 if (et
.type
== NT_invtype
)
13174 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
13175 _("bad list length"));
13176 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
13177 _("scalar index out of range"));
13178 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
13180 _("stride of 2 unavailable when element size is 8"));
13184 case 0: /* VLD1 / VST1. */
13185 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
13187 if (align_good
== FAIL
)
13191 unsigned alignbits
= 0;
13194 case 16: alignbits
= 0x1; break;
13195 case 32: alignbits
= 0x3; break;
13198 inst
.instruction
|= alignbits
<< 4;
13202 case 1: /* VLD2 / VST2. */
13203 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
13205 if (align_good
== FAIL
)
13208 inst
.instruction
|= 1 << 4;
13211 case 2: /* VLD3 / VST3. */
13212 constraint (inst
.operands
[1].immisalign
,
13213 _("can't use alignment with this instruction"));
13216 case 3: /* VLD4 / VST4. */
13217 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13218 16, 64, 32, 64, 32, 128, -1);
13219 if (align_good
== FAIL
)
13223 unsigned alignbits
= 0;
13226 case 8: alignbits
= 0x1; break;
13227 case 16: alignbits
= 0x1; break;
13228 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
13231 inst
.instruction
|= alignbits
<< 4;
13238 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
13239 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13240 inst
.instruction
|= 1 << (4 + logsize
);
13242 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
13243 inst
.instruction
|= logsize
<< 10;
13246 /* Encode single n-element structure to all lanes VLD<n> instructions. */
13249 do_neon_ld_dup (void)
13251 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
13252 int align_good
, do_align
= 0;
13254 if (et
.type
== NT_invtype
)
13257 switch ((inst
.instruction
>> 8) & 3)
13259 case 0: /* VLD1. */
13260 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
13261 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13262 &do_align
, 16, 16, 32, 32, -1);
13263 if (align_good
== FAIL
)
13265 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
13268 case 2: inst
.instruction
|= 1 << 5; break;
13269 default: first_error (_("bad list length")); return;
13271 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13274 case 1: /* VLD2. */
13275 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
13276 &do_align
, 8, 16, 16, 32, 32, 64, -1);
13277 if (align_good
== FAIL
)
13279 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
13280 _("bad list length"));
13281 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13282 inst
.instruction
|= 1 << 5;
13283 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13286 case 2: /* VLD3. */
13287 constraint (inst
.operands
[1].immisalign
,
13288 _("can't use alignment with this instruction"));
13289 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
13290 _("bad list length"));
13291 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13292 inst
.instruction
|= 1 << 5;
13293 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13296 case 3: /* VLD4. */
13298 int align
= inst
.operands
[1].imm
>> 8;
13299 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
13300 16, 64, 32, 64, 32, 128, -1);
13301 if (align_good
== FAIL
)
13303 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
13304 _("bad list length"));
13305 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
13306 inst
.instruction
|= 1 << 5;
13307 if (et
.size
== 32 && align
== 128)
13308 inst
.instruction
|= 0x3 << 6;
13310 inst
.instruction
|= neon_logbits (et
.size
) << 6;
13317 inst
.instruction
|= do_align
<< 4;
13320 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
13321 apart from bits [11:4]. */
13324 do_neon_ldx_stx (void)
13326 switch (NEON_LANE (inst
.operands
[0].imm
))
13328 case NEON_INTERLEAVE_LANES
:
13329 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
13330 do_neon_ld_st_interleave ();
13333 case NEON_ALL_LANES
:
13334 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
13339 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
13340 do_neon_ld_st_lane ();
13343 /* L bit comes from bit mask. */
13344 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13345 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13346 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13348 if (inst
.operands
[1].postind
)
13350 int postreg
= inst
.operands
[1].imm
& 0xf;
13351 constraint (!inst
.operands
[1].immisreg
,
13352 _("post-index must be a register"));
13353 constraint (postreg
== 0xd || postreg
== 0xf,
13354 _("bad register for post-index"));
13355 inst
.instruction
|= postreg
;
13357 else if (inst
.operands
[1].writeback
)
13359 inst
.instruction
|= 0xd;
13362 inst
.instruction
|= 0xf;
13365 inst
.instruction
|= 0xf9000000;
13367 inst
.instruction
|= 0xf4000000;
13371 /* Overall per-instruction processing. */
13373 /* We need to be able to fix up arbitrary expressions in some statements.
13374 This is so that we can handle symbols that are an arbitrary distance from
13375 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
13376 which returns part of an address in a form which will be valid for
13377 a data instruction. We do this by pushing the expression into a symbol
13378 in the expr_section, and creating a fix for that. */
13381 fix_new_arm (fragS
* frag
,
13396 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
13400 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
13405 /* Mark whether the fix is to a THUMB instruction, or an ARM
13407 new_fix
->tc_fix_data
= thumb_mode
;
13410 /* Create a frg for an instruction requiring relaxation. */
13412 output_relax_insn (void)
13418 /* The size of the instruction is unknown, so tie the debug info to the
13419 start of the instruction. */
13420 dwarf2_emit_insn (0);
13422 switch (inst
.reloc
.exp
.X_op
)
13425 sym
= inst
.reloc
.exp
.X_add_symbol
;
13426 offset
= inst
.reloc
.exp
.X_add_number
;
13430 offset
= inst
.reloc
.exp
.X_add_number
;
13433 sym
= make_expr_symbol (&inst
.reloc
.exp
);
13437 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
13438 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
13439 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
13442 /* Write a 32-bit thumb instruction to buf. */
13444 put_thumb32_insn (char * buf
, unsigned long insn
)
13446 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
13447 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
13451 output_inst (const char * str
)
13457 as_bad ("%s -- `%s'", inst
.error
, str
);
13461 output_relax_insn();
13464 if (inst
.size
== 0)
13467 to
= frag_more (inst
.size
);
13469 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
13471 assert (inst
.size
== (2 * THUMB_SIZE
));
13472 put_thumb32_insn (to
, inst
.instruction
);
13474 else if (inst
.size
> INSN_SIZE
)
13476 assert (inst
.size
== (2 * INSN_SIZE
));
13477 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
13478 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
13481 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
13483 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
13484 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
13485 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
13488 dwarf2_emit_insn (inst
.size
);
13491 /* Tag values used in struct asm_opcode's tag field. */
13494 OT_unconditional
, /* Instruction cannot be conditionalized.
13495 The ARM condition field is still 0xE. */
13496 OT_unconditionalF
, /* Instruction cannot be conditionalized
13497 and carries 0xF in its ARM condition field. */
13498 OT_csuffix
, /* Instruction takes a conditional suffix. */
13499 OT_csuffixF
, /* Some forms of the instruction take a conditional
13500 suffix, others place 0xF where the condition field
13502 OT_cinfix3
, /* Instruction takes a conditional infix,
13503 beginning at character index 3. (In
13504 unified mode, it becomes a suffix.) */
13505 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
13506 tsts, cmps, cmns, and teqs. */
13507 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
13508 character index 3, even in unified mode. Used for
13509 legacy instructions where suffix and infix forms
13510 may be ambiguous. */
13511 OT_csuf_or_in3
, /* Instruction takes either a conditional
13512 suffix or an infix at character index 3. */
13513 OT_odd_infix_unc
, /* This is the unconditional variant of an
13514 instruction that takes a conditional infix
13515 at an unusual position. In unified mode,
13516 this variant will accept a suffix. */
13517 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
13518 are the conditional variants of instructions that
13519 take conditional infixes in unusual positions.
13520 The infix appears at character index
13521 (tag - OT_odd_infix_0). These are not accepted
13522 in unified mode. */
13525 /* Subroutine of md_assemble, responsible for looking up the primary
13526 opcode from the mnemonic the user wrote. STR points to the
13527 beginning of the mnemonic.
13529 This is not simply a hash table lookup, because of conditional
13530 variants. Most instructions have conditional variants, which are
13531 expressed with a _conditional affix_ to the mnemonic. If we were
13532 to encode each conditional variant as a literal string in the opcode
13533 table, it would have approximately 20,000 entries.
13535 Most mnemonics take this affix as a suffix, and in unified syntax,
13536 'most' is upgraded to 'all'. However, in the divided syntax, some
13537 instructions take the affix as an infix, notably the s-variants of
13538 the arithmetic instructions. Of those instructions, all but six
13539 have the infix appear after the third character of the mnemonic.
13541 Accordingly, the algorithm for looking up primary opcodes given
13544 1. Look up the identifier in the opcode table.
13545 If we find a match, go to step U.
13547 2. Look up the last two characters of the identifier in the
13548 conditions table. If we find a match, look up the first N-2
13549 characters of the identifier in the opcode table. If we
13550 find a match, go to step CE.
13552 3. Look up the fourth and fifth characters of the identifier in
13553 the conditions table. If we find a match, extract those
13554 characters from the identifier, and look up the remaining
13555 characters in the opcode table. If we find a match, go
13560 U. Examine the tag field of the opcode structure, in case this is
13561 one of the six instructions with its conditional infix in an
13562 unusual place. If it is, the tag tells us where to find the
13563 infix; look it up in the conditions table and set inst.cond
13564 accordingly. Otherwise, this is an unconditional instruction.
13565 Again set inst.cond accordingly. Return the opcode structure.
13567 CE. Examine the tag field to make sure this is an instruction that
13568 should receive a conditional suffix. If it is not, fail.
13569 Otherwise, set inst.cond from the suffix we already looked up,
13570 and return the opcode structure.
13572 CM. Examine the tag field to make sure this is an instruction that
13573 should receive a conditional infix after the third character.
13574 If it is not, fail. Otherwise, undo the edits to the current
13575 line of input and proceed as for case CE. */
13577 static const struct asm_opcode
*
13578 opcode_lookup (char **str
)
13582 const struct asm_opcode
*opcode
;
13583 const struct asm_cond
*cond
;
13585 bfd_boolean neon_supported
;
13587 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
13589 /* Scan up to the end of the mnemonic, which must end in white space,
13590 '.' (in unified mode, or for Neon instructions), or end of string. */
13591 for (base
= end
= *str
; *end
!= '\0'; end
++)
13592 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
13598 /* Handle a possible width suffix and/or Neon type suffix. */
13603 /* The .w and .n suffixes are only valid if the unified syntax is in
13605 if (unified_syntax
&& end
[1] == 'w')
13607 else if (unified_syntax
&& end
[1] == 'n')
13612 inst
.vectype
.elems
= 0;
13614 *str
= end
+ offset
;
13616 if (end
[offset
] == '.')
13618 /* See if we have a Neon type suffix (possible in either unified or
13619 non-unified ARM syntax mode). */
13620 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
13623 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
13629 /* Look for unaffixed or special-case affixed mnemonic. */
13630 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
13634 if (opcode
->tag
< OT_odd_infix_0
)
13636 inst
.cond
= COND_ALWAYS
;
13640 if (unified_syntax
)
13641 as_warn (_("conditional infixes are deprecated in unified syntax"));
13642 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
13643 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13646 inst
.cond
= cond
->value
;
13650 /* Cannot have a conditional suffix on a mnemonic of less than two
13652 if (end
- base
< 3)
13655 /* Look for suffixed mnemonic. */
13657 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13658 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
13659 if (opcode
&& cond
)
13662 switch (opcode
->tag
)
13664 case OT_cinfix3_legacy
:
13665 /* Ignore conditional suffixes matched on infix only mnemonics. */
13669 case OT_cinfix3_deprecated
:
13670 case OT_odd_infix_unc
:
13671 if (!unified_syntax
)
13673 /* else fall through */
13677 case OT_csuf_or_in3
:
13678 inst
.cond
= cond
->value
;
13681 case OT_unconditional
:
13682 case OT_unconditionalF
:
13685 inst
.cond
= cond
->value
;
13689 /* delayed diagnostic */
13690 inst
.error
= BAD_COND
;
13691 inst
.cond
= COND_ALWAYS
;
13700 /* Cannot have a usual-position infix on a mnemonic of less than
13701 six characters (five would be a suffix). */
13702 if (end
- base
< 6)
13705 /* Look for infixed mnemonic in the usual position. */
13707 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
13711 memcpy (save
, affix
, 2);
13712 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
13713 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
13714 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
13715 memcpy (affix
, save
, 2);
13718 && (opcode
->tag
== OT_cinfix3
13719 || opcode
->tag
== OT_cinfix3_deprecated
13720 || opcode
->tag
== OT_csuf_or_in3
13721 || opcode
->tag
== OT_cinfix3_legacy
))
13725 && (opcode
->tag
== OT_cinfix3
13726 || opcode
->tag
== OT_cinfix3_deprecated
))
13727 as_warn (_("conditional infixes are deprecated in unified syntax"));
13729 inst
.cond
= cond
->value
;
13737 md_assemble (char *str
)
13740 const struct asm_opcode
* opcode
;
13742 /* Align the previous label if needed. */
13743 if (last_label_seen
!= NULL
)
13745 symbol_set_frag (last_label_seen
, frag_now
);
13746 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
13747 S_SET_SEGMENT (last_label_seen
, now_seg
);
13750 memset (&inst
, '\0', sizeof (inst
));
13751 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13753 opcode
= opcode_lookup (&p
);
13756 /* It wasn't an instruction, but it might be a register alias of
13757 the form alias .req reg, or a Neon .dn/.qn directive. */
13758 if (!create_register_alias (str
, p
)
13759 && !create_neon_reg_alias (str
, p
))
13760 as_bad (_("bad instruction `%s'"), str
);
13765 if (opcode
->tag
== OT_cinfix3_deprecated
)
13766 as_warn (_("s suffix on comparison instruction is deprecated"));
13768 /* The value which unconditional instructions should have in place of the
13769 condition field. */
13770 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
13774 arm_feature_set variant
;
13776 variant
= cpu_variant
;
13777 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
13778 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
13779 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
13780 /* Check that this instruction is supported for this CPU. */
13781 if (!opcode
->tvariant
13782 || (thumb_mode
== 1
13783 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
13785 as_bad (_("selected processor does not support `%s'"), str
);
13788 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
13789 && opcode
->tencode
!= do_t_branch
)
13791 as_bad (_("Thumb does not support conditional execution"));
13795 /* Check conditional suffixes. */
13796 if (current_it_mask
)
13799 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
13800 current_it_mask
<<= 1;
13801 current_it_mask
&= 0x1f;
13802 /* The BKPT instruction is unconditional even in an IT block. */
13804 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
13806 as_bad (_("incorrect condition in IT block"));
13810 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
13812 as_bad (_("thumb conditional instrunction not in IT block"));
13816 mapping_state (MAP_THUMB
);
13817 inst
.instruction
= opcode
->tvalue
;
13819 if (!parse_operands (p
, opcode
->operands
))
13820 opcode
->tencode ();
13822 /* Clear current_it_mask at the end of an IT block. */
13823 if (current_it_mask
== 0x10)
13824 current_it_mask
= 0;
13826 if (!(inst
.error
|| inst
.relax
))
13828 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
13829 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
13830 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
13832 as_bad (_("cannot honor width suffix -- `%s'"), str
);
13836 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13837 *opcode
->tvariant
);
13838 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
13839 set those bits when Thumb-2 32-bit instructions are seen. ie.
13840 anything other than bl/blx.
13841 This is overly pessimistic for relaxable instructions. */
13842 if ((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
13844 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13847 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
13849 /* Check that this instruction is supported for this CPU. */
13850 if (!opcode
->avariant
||
13851 !ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
))
13853 as_bad (_("selected processor does not support `%s'"), str
);
13858 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
13862 mapping_state (MAP_ARM
);
13863 inst
.instruction
= opcode
->avalue
;
13864 if (opcode
->tag
== OT_unconditionalF
)
13865 inst
.instruction
|= 0xF << 28;
13867 inst
.instruction
|= inst
.cond
<< 28;
13868 inst
.size
= INSN_SIZE
;
13869 if (!parse_operands (p
, opcode
->operands
))
13870 opcode
->aencode ();
13871 /* Arm mode bx is marked as both v4T and v5 because it's still required
13872 on a hypothetical non-thumb v5 core. */
13873 if (ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v4t
)
13874 || ARM_CPU_HAS_FEATURE (*opcode
->avariant
, arm_ext_v5
))
13875 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
13877 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
13878 *opcode
->avariant
);
13882 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
13889 /* Various frobbings of labels and their addresses. */
13892 arm_start_line_hook (void)
13894 last_label_seen
= NULL
;
13898 arm_frob_label (symbolS
* sym
)
13900 last_label_seen
= sym
;
13902 ARM_SET_THUMB (sym
, thumb_mode
);
13904 #if defined OBJ_COFF || defined OBJ_ELF
13905 ARM_SET_INTERWORK (sym
, support_interwork
);
13908 /* Note - do not allow local symbols (.Lxxx) to be labeled
13909 as Thumb functions. This is because these labels, whilst
13910 they exist inside Thumb code, are not the entry points for
13911 possible ARM->Thumb calls. Also, these labels can be used
13912 as part of a computed goto or switch statement. eg gcc
13913 can generate code that looks like this:
13915 ldr r2, [pc, .Laaa]
13925 The first instruction loads the address of the jump table.
13926 The second instruction converts a table index into a byte offset.
13927 The third instruction gets the jump address out of the table.
13928 The fourth instruction performs the jump.
13930 If the address stored at .Laaa is that of a symbol which has the
13931 Thumb_Func bit set, then the linker will arrange for this address
13932 to have the bottom bit set, which in turn would mean that the
13933 address computation performed by the third instruction would end
13934 up with the bottom bit set. Since the ARM is capable of unaligned
13935 word loads, the instruction would then load the incorrect address
13936 out of the jump table, and chaos would ensue. */
13937 if (label_is_thumb_function_name
13938 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
13939 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
13941 /* When the address of a Thumb function is taken the bottom
13942 bit of that address should be set. This will allow
13943 interworking between Arm and Thumb functions to work
13946 THUMB_SET_FUNC (sym
, 1);
13948 label_is_thumb_function_name
= FALSE
;
13951 dwarf2_emit_label (sym
);
13955 arm_data_in_code (void)
13957 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
13959 *input_line_pointer
= '/';
13960 input_line_pointer
+= 5;
13961 *input_line_pointer
= 0;
13969 arm_canonicalize_symbol_name (char * name
)
13973 if (thumb_mode
&& (len
= strlen (name
)) > 5
13974 && streq (name
+ len
- 5, "/data"))
13975 *(name
+ len
- 5) = 0;
13980 /* Table of all register names defined by default. The user can
13981 define additional names with .req. Note that all register names
13982 should appear in both upper and lowercase variants. Some registers
13983 also have mixed-case names. */
13985 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
13986 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
13987 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
13988 #define REGSET(p,t) \
13989 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
13990 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
13991 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
13992 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
13993 #define REGSETH(p,t) \
13994 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
13995 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
13996 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
13997 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
13998 #define REGSET2(p,t) \
13999 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14000 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14001 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14002 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14004 static const struct reg_entry reg_names
[] =
14006 /* ARM integer registers. */
14007 REGSET(r
, RN
), REGSET(R
, RN
),
14009 /* ATPCS synonyms. */
14010 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14011 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14012 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14014 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14015 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14016 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14018 /* Well-known aliases. */
14019 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14020 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14022 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14023 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14025 /* Coprocessor numbers. */
14026 REGSET(p
, CP
), REGSET(P
, CP
),
14028 /* Coprocessor register numbers. The "cr" variants are for backward
14030 REGSET(c
, CN
), REGSET(C
, CN
),
14031 REGSET(cr
, CN
), REGSET(CR
, CN
),
14033 /* FPA registers. */
14034 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
14035 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
14037 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
14038 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
14040 /* VFP SP registers. */
14041 REGSET(s
,VFS
), REGSET(S
,VFS
),
14042 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
14044 /* VFP DP Registers. */
14045 REGSET(d
,VFD
), REGSET(D
,VFD
),
14046 /* Extra Neon DP registers. */
14047 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
14049 /* Neon QP registers. */
14050 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
14052 /* VFP control registers. */
14053 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
14054 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
14056 /* Maverick DSP coprocessor registers. */
14057 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
14058 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
14060 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
14061 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
14062 REGDEF(dspsc
,0,DSPSC
),
14064 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
14065 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
14066 REGDEF(DSPSC
,0,DSPSC
),
14068 /* iWMMXt data registers - p0, c0-15. */
14069 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
14071 /* iWMMXt control registers - p1, c0-3. */
14072 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
14073 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
14074 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
14075 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
14077 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
14078 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
14079 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
14080 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
14081 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
14083 /* XScale accumulator registers. */
14084 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
14090 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
14091 within psr_required_here. */
14092 static const struct asm_psr psrs
[] =
14094 /* Backward compatibility notation. Note that "all" is no longer
14095 truly all possible PSR bits. */
14096 {"all", PSR_c
| PSR_f
},
14100 /* Individual flags. */
14105 /* Combinations of flags. */
14106 {"fs", PSR_f
| PSR_s
},
14107 {"fx", PSR_f
| PSR_x
},
14108 {"fc", PSR_f
| PSR_c
},
14109 {"sf", PSR_s
| PSR_f
},
14110 {"sx", PSR_s
| PSR_x
},
14111 {"sc", PSR_s
| PSR_c
},
14112 {"xf", PSR_x
| PSR_f
},
14113 {"xs", PSR_x
| PSR_s
},
14114 {"xc", PSR_x
| PSR_c
},
14115 {"cf", PSR_c
| PSR_f
},
14116 {"cs", PSR_c
| PSR_s
},
14117 {"cx", PSR_c
| PSR_x
},
14118 {"fsx", PSR_f
| PSR_s
| PSR_x
},
14119 {"fsc", PSR_f
| PSR_s
| PSR_c
},
14120 {"fxs", PSR_f
| PSR_x
| PSR_s
},
14121 {"fxc", PSR_f
| PSR_x
| PSR_c
},
14122 {"fcs", PSR_f
| PSR_c
| PSR_s
},
14123 {"fcx", PSR_f
| PSR_c
| PSR_x
},
14124 {"sfx", PSR_s
| PSR_f
| PSR_x
},
14125 {"sfc", PSR_s
| PSR_f
| PSR_c
},
14126 {"sxf", PSR_s
| PSR_x
| PSR_f
},
14127 {"sxc", PSR_s
| PSR_x
| PSR_c
},
14128 {"scf", PSR_s
| PSR_c
| PSR_f
},
14129 {"scx", PSR_s
| PSR_c
| PSR_x
},
14130 {"xfs", PSR_x
| PSR_f
| PSR_s
},
14131 {"xfc", PSR_x
| PSR_f
| PSR_c
},
14132 {"xsf", PSR_x
| PSR_s
| PSR_f
},
14133 {"xsc", PSR_x
| PSR_s
| PSR_c
},
14134 {"xcf", PSR_x
| PSR_c
| PSR_f
},
14135 {"xcs", PSR_x
| PSR_c
| PSR_s
},
14136 {"cfs", PSR_c
| PSR_f
| PSR_s
},
14137 {"cfx", PSR_c
| PSR_f
| PSR_x
},
14138 {"csf", PSR_c
| PSR_s
| PSR_f
},
14139 {"csx", PSR_c
| PSR_s
| PSR_x
},
14140 {"cxf", PSR_c
| PSR_x
| PSR_f
},
14141 {"cxs", PSR_c
| PSR_x
| PSR_s
},
14142 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
14143 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
14144 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
14145 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
14146 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
14147 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
14148 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
14149 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
14150 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
14151 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
14152 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
14153 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
14154 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
14155 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
14156 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
14157 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
14158 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
14159 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
14160 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
14161 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
14162 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
14163 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
14164 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
14165 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
14168 /* Table of V7M psr names. */
14169 static const struct asm_psr v7m_psrs
[] =
14182 {"basepri_max", 18},
14187 /* Table of all shift-in-operand names. */
14188 static const struct asm_shift_name shift_names
[] =
14190 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
14191 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
14192 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
14193 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
14194 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
14195 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
14198 /* Table of all explicit relocation names. */
14200 static struct reloc_entry reloc_names
[] =
14202 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
14203 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
14204 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
14205 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
14206 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
14207 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
14208 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
14209 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
14210 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
14211 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
14212 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
14216 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
14217 static const struct asm_cond conds
[] =
14221 {"cs", 0x2}, {"hs", 0x2},
14222 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
14236 static struct asm_barrier_opt barrier_opt_names
[] =
14244 /* Table of ARM-format instructions. */
14246 /* Macros for gluing together operand strings. N.B. In all cases
14247 other than OPS0, the trailing OP_stop comes from default
14248 zero-initialization of the unspecified elements of the array. */
14249 #define OPS0() { OP_stop, }
14250 #define OPS1(a) { OP_##a, }
14251 #define OPS2(a,b) { OP_##a,OP_##b, }
14252 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
14253 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
14254 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
14255 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
14257 /* These macros abstract out the exact format of the mnemonic table and
14258 save some repeated characters. */
14260 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
14261 #define TxCE(mnem, op, top, nops, ops, ae, te) \
14262 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
14263 THUMB_VARIANT, do_##ae, do_##te }
14265 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
14266 a T_MNEM_xyz enumerator. */
14267 #define TCE(mnem, aop, top, nops, ops, ae, te) \
14268 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
14269 #define tCE(mnem, aop, top, nops, ops, ae, te) \
14270 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14272 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
14273 infix after the third character. */
14274 #define TxC3(mnem, op, top, nops, ops, ae, te) \
14275 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
14276 THUMB_VARIANT, do_##ae, do_##te }
14277 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
14278 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
14279 THUMB_VARIANT, do_##ae, do_##te }
14280 #define TC3(mnem, aop, top, nops, ops, ae, te) \
14281 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
14282 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
14283 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
14284 #define tC3(mnem, aop, top, nops, ops, ae, te) \
14285 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14286 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
14287 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
14289 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
14290 appear in the condition table. */
14291 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
14292 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14293 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
14295 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
14296 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
14297 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
14298 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
14299 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
14300 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
14301 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
14302 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
14303 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
14304 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
14305 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
14306 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
14307 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
14308 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
14309 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
14310 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
14311 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
14312 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
14313 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
14314 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
14316 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
14317 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
14318 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
14319 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
14321 /* Mnemonic that cannot be conditionalized. The ARM condition-code
14322 field is still 0xE. Many of the Thumb variants can be executed
14323 conditionally, so this is checked separately. */
14324 #define TUE(mnem, op, top, nops, ops, ae, te) \
14325 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
14326 THUMB_VARIANT, do_##ae, do_##te }
14328 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
14329 condition code field. */
14330 #define TUF(mnem, op, top, nops, ops, ae, te) \
14331 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
14332 THUMB_VARIANT, do_##ae, do_##te }
14334 /* ARM-only variants of all the above. */
14335 #define CE(mnem, op, nops, ops, ae) \
14336 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14338 #define C3(mnem, op, nops, ops, ae) \
14339 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14341 /* Legacy mnemonics that always have conditional infix after the third
14343 #define CL(mnem, op, nops, ops, ae) \
14344 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14345 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14347 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
14348 #define cCE(mnem, op, nops, ops, ae) \
14349 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14351 /* Legacy coprocessor instructions where conditional infix and conditional
14352 suffix are ambiguous. For consistency this includes all FPA instructions,
14353 not just the potentially ambiguous ones. */
14354 #define cCL(mnem, op, nops, ops, ae) \
14355 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
14356 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14358 /* Coprocessor, takes either a suffix or a position-3 infix
14359 (for an FPA corner case). */
14360 #define C3E(mnem, op, nops, ops, ae) \
14361 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
14362 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
14364 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
14365 { #m1 #m2 #m3, OPS##nops ops, \
14366 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
14367 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
14369 #define CM(m1, m2, op, nops, ops, ae) \
14370 xCM_(m1, , m2, op, nops, ops, ae), \
14371 xCM_(m1, eq, m2, op, nops, ops, ae), \
14372 xCM_(m1, ne, m2, op, nops, ops, ae), \
14373 xCM_(m1, cs, m2, op, nops, ops, ae), \
14374 xCM_(m1, hs, m2, op, nops, ops, ae), \
14375 xCM_(m1, cc, m2, op, nops, ops, ae), \
14376 xCM_(m1, ul, m2, op, nops, ops, ae), \
14377 xCM_(m1, lo, m2, op, nops, ops, ae), \
14378 xCM_(m1, mi, m2, op, nops, ops, ae), \
14379 xCM_(m1, pl, m2, op, nops, ops, ae), \
14380 xCM_(m1, vs, m2, op, nops, ops, ae), \
14381 xCM_(m1, vc, m2, op, nops, ops, ae), \
14382 xCM_(m1, hi, m2, op, nops, ops, ae), \
14383 xCM_(m1, ls, m2, op, nops, ops, ae), \
14384 xCM_(m1, ge, m2, op, nops, ops, ae), \
14385 xCM_(m1, lt, m2, op, nops, ops, ae), \
14386 xCM_(m1, gt, m2, op, nops, ops, ae), \
14387 xCM_(m1, le, m2, op, nops, ops, ae), \
14388 xCM_(m1, al, m2, op, nops, ops, ae)
14390 #define UE(mnem, op, nops, ops, ae) \
14391 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14393 #define UF(mnem, op, nops, ops, ae) \
14394 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
14396 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
14397 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
14398 use the same encoding function for each. */
14399 #define NUF(mnem, op, nops, ops, enc) \
14400 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
14401 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14403 /* Neon data processing, version which indirects through neon_enc_tab for
14404 the various overloaded versions of opcodes. */
14405 #define nUF(mnem, op, nops, ops, enc) \
14406 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
14407 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14409 /* Neon insn with conditional suffix for the ARM version, non-overloaded
14411 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
14412 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
14413 THUMB_VARIANT, do_##enc, do_##enc }
14415 #define NCE(mnem, op, nops, ops, enc) \
14416 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14418 #define NCEF(mnem, op, nops, ops, enc) \
14419 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14421 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
14422 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
14423 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
14424 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
14426 #define nCE(mnem, op, nops, ops, enc) \
14427 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
14429 #define nCEF(mnem, op, nops, ops, enc) \
14430 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
14434 /* Thumb-only, unconditional. */
14435 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
14437 static const struct asm_opcode insns
[] =
14439 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
14440 #define THUMB_VARIANT &arm_ext_v4t
14441 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14442 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14443 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14444 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14445 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14446 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
14447 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14448 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
14449 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14450 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14451 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14452 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14453 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14454 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
14455 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14456 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
14458 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
14459 for setting PSR flag bits. They are obsolete in V6 and do not
14460 have Thumb equivalents. */
14461 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14462 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14463 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
14464 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14465 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
14466 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
14467 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14468 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14469 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
14471 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14472 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
14473 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14474 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
14476 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14477 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14478 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14479 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
14481 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14482 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14483 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14484 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14485 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14486 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14488 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14489 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
14490 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
14491 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
14494 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
14495 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
14496 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
14498 /* Thumb-compatibility pseudo ops. */
14499 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14500 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14501 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14502 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14503 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14504 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14505 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14506 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
14507 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
14508 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
14509 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
14510 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
14512 #undef THUMB_VARIANT
14513 #define THUMB_VARIANT &arm_ext_v6
14514 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
14516 /* V1 instructions with no Thumb analogue prior to V6T2. */
14517 #undef THUMB_VARIANT
14518 #define THUMB_VARIANT &arm_ext_v6t2
14519 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14520 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
14521 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14522 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
14523 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
14525 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14526 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14527 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14528 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
14530 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14531 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14533 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14534 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
14536 /* V1 instructions with no Thumb analogue at all. */
14537 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
14538 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
14540 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14541 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
14542 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14543 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
14544 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14545 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
14546 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14547 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
14550 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
14551 #undef THUMB_VARIANT
14552 #define THUMB_VARIANT &arm_ext_v4t
14553 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14554 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
14556 #undef THUMB_VARIANT
14557 #define THUMB_VARIANT &arm_ext_v6t2
14558 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14559 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
14561 /* Generic coprocessor instructions. */
14562 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14563 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14564 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14565 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14566 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14567 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14568 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14571 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
14572 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14573 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
14576 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
14577 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
14578 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
14581 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
14582 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14583 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14584 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14585 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14586 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14587 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14588 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
14589 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
14592 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
14593 #undef THUMB_VARIANT
14594 #define THUMB_VARIANT &arm_ext_v4t
14595 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14596 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14597 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14598 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14599 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14600 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
14603 #define ARM_VARIANT &arm_ext_v4t_5
14604 /* ARM Architecture 4T. */
14605 /* Note: bx (and blx) are required on V5, even if the processor does
14606 not support Thumb. */
14607 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
14610 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
14611 #undef THUMB_VARIANT
14612 #define THUMB_VARIANT &arm_ext_v5t
14613 /* Note: blx has 2 variants; the .value coded here is for
14614 BLX(2). Only this variant has conditional execution. */
14615 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
14616 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
14618 #undef THUMB_VARIANT
14619 #define THUMB_VARIANT &arm_ext_v6t2
14620 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
14621 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14622 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14623 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14624 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
14625 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
14626 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14627 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
14630 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
14631 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14632 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14633 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14634 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14636 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14637 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
14639 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14640 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14641 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14642 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
14644 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14645 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14646 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14647 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14649 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14650 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14652 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14653 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14654 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14655 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, rd_rm_rn
),
14658 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
14659 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
14660 TC3(ldrd
, 00000d0
, e9500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14661 TC3(strd
, 00000f0
, e9400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
14663 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14664 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14667 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
14668 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
14671 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
14672 #undef THUMB_VARIANT
14673 #define THUMB_VARIANT &arm_ext_v6
14674 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14675 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
14676 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14677 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14678 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
14679 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14680 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14681 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14682 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14683 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
14685 #undef THUMB_VARIANT
14686 #define THUMB_VARIANT &arm_ext_v6t2
14687 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
14688 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14689 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
14691 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
14692 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
14694 /* ARM V6 not included in V7M (eg. integer SIMD). */
14695 #undef THUMB_VARIANT
14696 #define THUMB_VARIANT &arm_ext_v6_notm
14697 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
14698 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
14699 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
14700 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14701 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14702 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14703 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14704 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14705 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14706 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14707 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14708 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14709 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14710 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14711 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14712 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14713 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14714 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14715 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14716 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14717 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14718 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14719 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14720 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14721 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14722 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14723 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14724 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14725 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14726 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14727 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14728 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14729 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14730 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14731 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14732 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14733 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14734 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14735 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14736 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14737 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
14738 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
14739 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14740 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
14741 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
14742 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
14743 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
14744 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14745 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14746 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14747 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14748 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14749 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14750 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
14751 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
14752 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
14753 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14754 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14755 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14756 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14757 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14758 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14759 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14760 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
14761 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14762 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14763 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14764 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14765 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14766 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14767 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14768 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14769 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14770 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14771 TUF(srsia
, 8cd0500
, e980c000
, 1, (I31w
), srs
, srs
),
14772 UF(srsib
, 9cd0500
, 1, (I31w
), srs
),
14773 UF(srsda
, 84d0500
, 1, (I31w
), srs
),
14774 TUF(srsdb
, 94d0500
, e800c000
, 1, (I31w
), srs
, srs
),
14775 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
14776 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
14777 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
14778 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
14779 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
14780 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
14783 #define ARM_VARIANT &arm_ext_v6k
14784 #undef THUMB_VARIANT
14785 #define THUMB_VARIANT &arm_ext_v6k
14786 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
14787 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
14788 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
14789 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
14791 #undef THUMB_VARIANT
14792 #define THUMB_VARIANT &arm_ext_v6_notm
14793 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
14794 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
14796 #undef THUMB_VARIANT
14797 #define THUMB_VARIANT &arm_ext_v6t2
14798 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14799 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
14800 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14801 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
14802 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
14805 #define ARM_VARIANT &arm_ext_v6z
14806 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
14809 #define ARM_VARIANT &arm_ext_v6t2
14810 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
14811 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
14812 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14813 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
14815 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
14816 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14817 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
14818 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
14820 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14821 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14822 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14823 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
14825 UT(cbnz
, b900
, 2, (RR
, EXP
), t_czb
),
14826 UT(cbz
, b100
, 2, (RR
, EXP
), t_czb
),
14827 /* ARM does not really have an IT instruction. */
14828 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
14829 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
14830 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
14831 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
14832 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
14833 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
14834 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
14835 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
14836 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
14837 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
14838 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
14839 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
14840 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
14841 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
14842 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
14844 /* Thumb2 only instructions. */
14846 #define ARM_VARIANT NULL
14848 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14849 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
14850 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
14851 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
14853 /* Thumb-2 hardware division instructions (R and M profiles only). */
14854 #undef THUMB_VARIANT
14855 #define THUMB_VARIANT &arm_ext_div
14856 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14857 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
14859 /* ARM V7 instructions. */
14861 #define ARM_VARIANT &arm_ext_v7
14862 #undef THUMB_VARIANT
14863 #define THUMB_VARIANT &arm_ext_v7
14864 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
14865 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
14866 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
14867 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
14868 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
14871 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
14872 cCE(wfs
, e200110
, 1, (RR
), rd
),
14873 cCE(rfs
, e300110
, 1, (RR
), rd
),
14874 cCE(wfc
, e400110
, 1, (RR
), rd
),
14875 cCE(rfc
, e500110
, 1, (RR
), rd
),
14877 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14878 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14879 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14880 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14882 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14883 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14884 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14885 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
14887 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
14888 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
14889 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
14890 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
14891 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
14892 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
14893 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
14894 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
14895 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
14896 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
14897 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
14898 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
14900 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
14901 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
14902 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
14903 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
14904 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
14905 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
14906 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
14907 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
14908 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
14909 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
14910 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
14911 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
14913 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
14914 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
14915 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
14916 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
14917 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
14918 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
14919 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
14920 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
14921 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
14922 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
14923 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
14924 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
14926 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
14927 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
14928 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
14929 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
14930 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
14931 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
14932 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
14933 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
14934 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
14935 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
14936 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
14937 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
14939 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
14940 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
14941 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
14942 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
14943 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
14944 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
14945 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
14946 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
14947 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
14948 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
14949 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
14950 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
14952 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
14953 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
14954 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
14955 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
14956 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
14957 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
14958 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
14959 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
14960 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
14961 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
14962 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
14963 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
14965 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
14966 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
14967 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
14968 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
14969 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
14970 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
14971 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
14972 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
14973 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
14974 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
14975 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
14976 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
14978 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
14979 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
14980 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
14981 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
14982 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
14983 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
14984 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
14985 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
14986 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
14987 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
14988 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
14989 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
14991 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
14992 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
14993 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
14994 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
14995 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
14996 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
14997 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
14998 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
14999 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
15000 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
15001 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
15002 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
15004 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
15005 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
15006 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
15007 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
15008 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
15009 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
15010 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
15011 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
15012 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
15013 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
15014 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
15015 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
15017 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
15018 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
15019 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
15020 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
15021 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
15022 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
15023 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
15024 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
15025 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
15026 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
15027 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
15028 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
15030 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
15031 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
15032 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
15033 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
15034 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
15035 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
15036 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
15037 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
15038 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
15039 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
15040 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
15041 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
15043 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
15044 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
15045 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
15046 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
15047 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
15048 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
15049 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
15050 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
15051 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
15052 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
15053 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
15054 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
15056 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
15057 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
15058 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
15059 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
15060 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
15061 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
15062 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
15063 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
15064 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
15065 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
15066 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
15067 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
15069 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
15070 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
15071 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
15072 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
15073 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
15074 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
15075 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
15076 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
15077 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
15078 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
15079 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
15080 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
15082 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
15083 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
15084 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
15085 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
15086 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
15087 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
15088 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
15089 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
15090 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
15091 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
15092 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
15093 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
15095 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15096 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15097 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15098 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15099 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15100 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15101 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15102 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15103 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15104 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15105 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15106 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15108 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15109 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15110 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15111 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15112 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15113 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15114 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15115 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15116 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15117 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15118 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15119 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15121 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15122 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15123 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15124 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15125 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15126 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15127 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15128 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15129 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15130 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15131 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15132 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15134 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15135 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15136 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15137 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15138 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15139 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15140 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15141 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15142 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15143 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15144 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15145 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15147 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15148 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15149 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15150 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15151 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15152 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15153 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15154 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15155 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15156 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15157 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15158 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15160 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15161 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15162 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15163 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15164 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15165 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15166 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15167 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15168 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15169 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15170 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15171 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15173 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15174 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15175 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15176 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15177 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15178 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15179 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15180 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15181 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15182 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15183 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15184 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15186 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15187 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15188 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15189 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15190 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15191 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15192 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15193 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15194 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15195 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15196 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15197 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15199 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15200 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15201 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15202 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15203 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15204 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15205 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15206 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15207 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15208 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15209 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15210 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15212 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15213 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15214 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15215 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15216 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15217 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15218 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15219 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15220 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15221 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15222 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15223 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15225 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15226 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15227 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15228 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15229 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15230 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15231 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15232 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15233 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15234 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15235 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15236 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15238 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15239 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15240 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15241 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15242 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15243 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15244 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15245 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15246 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15247 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15248 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15249 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15251 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15252 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15253 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15254 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15255 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15256 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15257 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15258 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15259 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15260 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15261 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15262 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
15264 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15265 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15266 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15267 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
15269 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
15270 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
15271 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
15272 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
15273 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
15274 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
15275 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
15276 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
15277 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
15278 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
15279 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
15280 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
15282 /* The implementation of the FIX instruction is broken on some
15283 assemblers, in that it accepts a precision specifier as well as a
15284 rounding specifier, despite the fact that this is meaningless.
15285 To be more compatible, we accept it as well, though of course it
15286 does not set any bits. */
15287 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
15288 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
15289 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
15290 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
15291 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
15292 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
15293 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
15294 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
15295 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
15296 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
15297 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
15298 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
15299 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
15301 /* Instructions that were new with the real FPA, call them V2. */
15303 #define ARM_VARIANT &fpu_fpa_ext_v2
15304 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15305 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15306 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15307 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15308 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15309 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
15312 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
15313 /* Moves and type conversions. */
15314 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15315 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
15316 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
15317 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
15318 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15319 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15320 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15321 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15322 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15323 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15324 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
15325 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
15327 /* Memory operations. */
15328 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15329 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
15330 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15331 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15332 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15333 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15334 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15335 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15336 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15337 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15338 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15339 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
15340 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15341 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
15342 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15343 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
15344 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15345 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
15347 /* Monadic operations. */
15348 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15349 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15350 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15352 /* Dyadic operations. */
15353 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15354 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15355 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15356 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15357 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15358 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15359 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15360 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15361 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
15364 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15365 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
15366 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
15367 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
15370 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
15371 /* Moves and type conversions. */
15372 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15373 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15374 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15375 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15376 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
15377 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15378 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
15379 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15380 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
15381 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15382 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15383 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15384 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
15386 /* Memory operations. */
15387 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15388 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
15389 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15390 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15391 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15392 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15393 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15394 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
15395 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15396 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
15398 /* Monadic operations. */
15399 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15400 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15401 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15403 /* Dyadic operations. */
15404 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15405 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15406 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15407 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15408 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15409 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15410 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15411 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15412 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
15415 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15416 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
15417 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
15418 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
15421 #define ARM_VARIANT &fpu_vfp_ext_v2
15422 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
15423 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
15424 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
15425 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
15427 /* Instructions which may belong to either the Neon or VFP instruction sets.
15428 Individual encoder functions perform additional architecture checks. */
15430 #define ARM_VARIANT &fpu_vfp_ext_v1xd
15431 #undef THUMB_VARIANT
15432 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
15433 /* These mnemonics are unique to VFP. */
15434 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
15435 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
15436 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15437 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15438 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
15439 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15440 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
15441 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
15442 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
15443 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
15445 /* Mnemonics shared by Neon and VFP. */
15446 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
15447 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15448 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
15450 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15451 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
15453 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15454 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
15456 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15457 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15458 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15459 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15460 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15461 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
15462 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15463 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
15465 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
15467 /* NOTE: All VMOV encoding is special-cased! */
15468 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
15469 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
15471 #undef THUMB_VARIANT
15472 #define THUMB_VARIANT &fpu_neon_ext_v1
15474 #define ARM_VARIANT &fpu_neon_ext_v1
15475 /* Data processing with three registers of the same length. */
15476 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
15477 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
15478 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
15479 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15480 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15481 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15482 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15483 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
15484 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
15485 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
15486 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15487 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15488 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15489 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15490 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15491 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15492 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
15493 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
15494 /* If not immediate, fall back to neon_dyadic_i64_su.
15495 shl_imm should accept I8 I16 I32 I64,
15496 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
15497 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
15498 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
15499 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
15500 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
15501 /* Logic ops, types optional & ignored. */
15502 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
15503 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
15504 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
15505 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
15506 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
15507 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
15508 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
15509 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
15510 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
15511 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
15512 /* Bitfield ops, untyped. */
15513 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15514 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15515 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15516 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15517 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
15518 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
15519 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
15520 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15521 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15522 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15523 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15524 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
15525 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
15526 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
15527 back to neon_dyadic_if_su. */
15528 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15529 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15530 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
15531 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
15532 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15533 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15534 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
15535 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
15536 /* Comparison. Type I8 I16 I32 F32. Non-immediate -> neon_dyadic_if_i. */
15537 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
15538 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
15539 /* As above, D registers only. */
15540 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15541 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
15542 /* Int and float variants, signedness unimportant. */
15543 /* If not scalar, fall back to neon_dyadic_if_i. */
15544 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15545 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
15546 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
15547 /* Add/sub take types I8 I16 I32 I64 F32. */
15548 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15549 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
15550 /* vtst takes sizes 8, 16, 32. */
15551 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
15552 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
15553 /* VMUL takes I8 I16 I32 F32 P8. */
15554 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
15555 /* VQD{R}MULH takes S16 S32. */
15556 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15557 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15558 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
15559 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
15560 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15561 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15562 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
15563 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
15564 NUF(vaclt
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15565 NUF(vacltq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15566 NUF(vacle
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
15567 NUF(vacleq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
15568 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15569 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15570 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
15571 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
15573 /* Two address, int/float. Types S8 S16 S32 F32. */
15574 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15575 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
15577 /* Data processing with two registers and a shift amount. */
15578 /* Right shifts, and variants with rounding.
15579 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
15580 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15581 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15582 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
15583 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
15584 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15585 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15586 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
15587 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
15588 /* Shift and insert. Sizes accepted 8 16 32 64. */
15589 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
15590 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
15591 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
15592 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
15593 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
15594 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
15595 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
15596 /* Right shift immediate, saturating & narrowing, with rounding variants.
15597 Types accepted S16 S32 S64 U16 U32 U64. */
15598 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15599 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
15600 /* As above, unsigned. Types accepted S16 S32 S64. */
15601 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15602 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
15603 /* Right shift narrowing. Types accepted I16 I32 I64. */
15604 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15605 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
15606 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
15607 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
15608 /* CVT with optional immediate for fixed-point variant. */
15609 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
15611 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
15612 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
15614 /* Data processing, three registers of different lengths. */
15615 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
15616 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
15617 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15618 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15619 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
15620 /* If not scalar, fall back to neon_dyadic_long.
15621 Vector types as above, scalar types S16 S32 U16 U32. */
15622 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15623 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
15624 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
15625 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15626 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
15627 /* Dyadic, narrowing insns. Types I16 I32 I64. */
15628 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15629 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15630 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15631 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
15632 /* Saturating doubling multiplies. Types S16 S32. */
15633 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15634 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15635 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
15636 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
15637 S16 S32 U16 U32. */
15638 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
15640 /* Extract. Size 8. */
15641 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I7
), neon_ext
),
15642 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I7
), neon_ext
),
15644 /* Two registers, miscellaneous. */
15645 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
15646 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
15647 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
15648 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
15649 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
15650 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
15651 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
15652 /* Vector replicate. Sizes 8 16 32. */
15653 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
15654 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
15655 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
15656 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
15657 /* VMOVN. Types I16 I32 I64. */
15658 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
15659 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
15660 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
15661 /* VQMOVUN. Types S16 S32 S64. */
15662 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
15663 /* VZIP / VUZP. Sizes 8 16 32. */
15664 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15665 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15666 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
15667 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
15668 /* VQABS / VQNEG. Types S8 S16 S32. */
15669 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15670 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15671 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
15672 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
15673 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
15674 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15675 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
15676 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
15677 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
15678 /* Reciprocal estimates. Types U32 F32. */
15679 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15680 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
15681 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
15682 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
15683 /* VCLS. Types S8 S16 S32. */
15684 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
15685 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
15686 /* VCLZ. Types I8 I16 I32. */
15687 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
15688 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
15689 /* VCNT. Size 8. */
15690 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
15691 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
15692 /* Two address, untyped. */
15693 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
15694 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
15695 /* VTRN. Sizes 8 16 32. */
15696 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
15697 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
15699 /* Table lookup. Size 8. */
15700 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15701 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
15703 #undef THUMB_VARIANT
15704 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
15706 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
15707 /* Neon element/structure load/store. */
15708 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15709 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15710 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15711 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15712 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15713 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15714 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15715 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
15717 #undef THUMB_VARIANT
15718 #define THUMB_VARIANT &fpu_vfp_ext_v3
15720 #define ARM_VARIANT &fpu_vfp_ext_v3
15721 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
15722 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
15723 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15724 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15725 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15726 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15727 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15728 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15729 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15730 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15731 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15732 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15733 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15734 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15735 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
15736 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
15737 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
15738 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
15740 #undef THUMB_VARIANT
15742 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
15743 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15744 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15745 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15746 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15747 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15748 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
15749 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
15750 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
15753 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
15754 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
15755 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
15756 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
15757 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
15758 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
15759 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
15760 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
15761 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
15762 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
15763 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15764 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15765 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15766 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15767 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15768 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
15769 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15770 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15771 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
15772 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
15773 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
15774 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15775 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15776 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15777 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15778 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15779 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
15780 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
15781 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
15782 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
15783 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
15784 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
15785 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
15786 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
15787 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
15788 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15789 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15790 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
15791 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15792 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15793 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15794 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15795 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15796 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15797 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15798 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15799 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15800 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
15801 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15802 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15803 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15804 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15805 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15806 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15807 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15808 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15809 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15810 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15811 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15812 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15813 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15814 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15815 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15816 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15817 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15818 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15819 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15820 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15821 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15822 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15823 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15824 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15825 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15826 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15827 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15828 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15829 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15830 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15831 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15832 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15833 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15834 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15835 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15836 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15837 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15838 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15839 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15840 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15841 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15842 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
15843 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15844 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15845 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15846 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15847 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15848 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15849 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15850 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15851 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15852 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15853 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15854 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15855 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15856 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15857 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15858 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15859 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15860 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15861 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15862 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15863 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15864 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
15865 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15866 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15867 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15868 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15869 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15870 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15871 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15872 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15873 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15874 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15875 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15876 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15877 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15878 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15879 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15880 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15881 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15882 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
15883 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15884 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
15885 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
15886 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
15887 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15888 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15889 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15890 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15891 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15892 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15893 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15894 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15895 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15896 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15897 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15898 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15899 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15900 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15901 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
15902 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15903 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15904 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15905 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15906 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15907 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15908 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15909 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15910 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
15911 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15912 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15913 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15914 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
15915 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
15918 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
15919 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15920 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15921 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15922 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15923 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
15924 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
15925 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
15926 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
15927 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
15928 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
15929 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
15930 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
15931 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
15932 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
15933 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
15934 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
15935 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
15936 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
15937 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
15938 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
15939 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
15940 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
15941 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
15942 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
15943 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
15944 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
15945 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
15946 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
15947 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
15948 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
15949 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
15950 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
15951 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
15952 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
15953 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
15954 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
15955 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
15956 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
15957 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
15958 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
15959 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
15960 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
15961 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
15962 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
15963 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
15964 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
15965 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
15966 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
15967 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
15968 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
15969 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
15970 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
15971 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
15972 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
15973 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15974 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15975 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15976 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15977 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
15978 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
15979 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
15980 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
15981 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
15982 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
15983 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15984 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15985 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15986 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15987 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15988 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
15989 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15990 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
15991 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15992 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
15993 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15994 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
15997 #undef THUMB_VARIANT
16024 /* MD interface: bits in the object file. */
16026 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
16027 for use in the a.out file, and stores them in the array pointed to by buf.
16028 This knows about the endian-ness of the target machine and does
16029 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
16030 2 (short) and 4 (long) Floating numbers are put out as a series of
16031 LITTLENUMS (shorts, here at least). */
16034 md_number_to_chars (char * buf
, valueT val
, int n
)
16036 if (target_big_endian
)
16037 number_to_chars_bigendian (buf
, val
, n
);
16039 number_to_chars_littleendian (buf
, val
, n
);
16043 md_chars_to_number (char * buf
, int n
)
16046 unsigned char * where
= (unsigned char *) buf
;
16048 if (target_big_endian
)
16053 result
|= (*where
++ & 255);
16061 result
|= (where
[n
] & 255);
16068 /* MD interface: Sections. */
16070 /* Estimate the size of a frag before relaxing. Assume everything fits in
16074 md_estimate_size_before_relax (fragS
* fragp
,
16075 segT segtype ATTRIBUTE_UNUSED
)
16081 /* Convert a machine dependent frag. */
16084 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
16086 unsigned long insn
;
16087 unsigned long old_op
;
16095 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16097 old_op
= bfd_get_16(abfd
, buf
);
16098 if (fragp
->fr_symbol
) {
16099 exp
.X_op
= O_symbol
;
16100 exp
.X_add_symbol
= fragp
->fr_symbol
;
16102 exp
.X_op
= O_constant
;
16104 exp
.X_add_number
= fragp
->fr_offset
;
16105 opcode
= fragp
->fr_subtype
;
16108 case T_MNEM_ldr_pc
:
16109 case T_MNEM_ldr_pc2
:
16110 case T_MNEM_ldr_sp
:
16111 case T_MNEM_str_sp
:
16118 if (fragp
->fr_var
== 4)
16120 insn
= THUMB_OP32(opcode
);
16121 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
16123 insn
|= (old_op
& 0x700) << 4;
16127 insn
|= (old_op
& 7) << 12;
16128 insn
|= (old_op
& 0x38) << 13;
16130 insn
|= 0x00000c00;
16131 put_thumb32_insn (buf
, insn
);
16132 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
16136 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
16138 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
16141 if (fragp
->fr_var
== 4)
16143 insn
= THUMB_OP32 (opcode
);
16144 insn
|= (old_op
& 0xf0) << 4;
16145 put_thumb32_insn (buf
, insn
);
16146 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
16150 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16151 exp
.X_add_number
-= 4;
16159 if (fragp
->fr_var
== 4)
16161 int r0off
= (opcode
== T_MNEM_mov
16162 || opcode
== T_MNEM_movs
) ? 0 : 8;
16163 insn
= THUMB_OP32 (opcode
);
16164 insn
= (insn
& 0xe1ffffff) | 0x10000000;
16165 insn
|= (old_op
& 0x700) << r0off
;
16166 put_thumb32_insn (buf
, insn
);
16167 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16171 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
16176 if (fragp
->fr_var
== 4)
16178 insn
= THUMB_OP32(opcode
);
16179 put_thumb32_insn (buf
, insn
);
16180 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
16183 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
16187 if (fragp
->fr_var
== 4)
16189 insn
= THUMB_OP32(opcode
);
16190 insn
|= (old_op
& 0xf00) << 14;
16191 put_thumb32_insn (buf
, insn
);
16192 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
16195 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
16198 case T_MNEM_add_sp
:
16199 case T_MNEM_add_pc
:
16200 case T_MNEM_inc_sp
:
16201 case T_MNEM_dec_sp
:
16202 if (fragp
->fr_var
== 4)
16204 /* ??? Choose between add and addw. */
16205 insn
= THUMB_OP32 (opcode
);
16206 insn
|= (old_op
& 0xf0) << 4;
16207 put_thumb32_insn (buf
, insn
);
16208 if (opcode
== T_MNEM_add_pc
)
16209 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
16211 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16214 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16222 if (fragp
->fr_var
== 4)
16224 insn
= THUMB_OP32 (opcode
);
16225 insn
|= (old_op
& 0xf0) << 4;
16226 insn
|= (old_op
& 0xf) << 16;
16227 put_thumb32_insn (buf
, insn
);
16228 if (insn
& (1 << 20))
16229 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
16231 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
16234 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
16240 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
16242 fixp
->fx_file
= fragp
->fr_file
;
16243 fixp
->fx_line
= fragp
->fr_line
;
16244 fragp
->fr_fix
+= fragp
->fr_var
;
16247 /* Return the size of a relaxable immediate operand instruction.
16248 SHIFT and SIZE specify the form of the allowable immediate. */
16250 relax_immediate (fragS
*fragp
, int size
, int shift
)
16256 /* ??? Should be able to do better than this. */
16257 if (fragp
->fr_symbol
)
16260 low
= (1 << shift
) - 1;
16261 mask
= (1 << (shift
+ size
)) - (1 << shift
);
16262 offset
= fragp
->fr_offset
;
16263 /* Force misaligned offsets to 32-bit variant. */
16266 if (offset
& ~mask
)
16271 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
16274 relax_adr (fragS
*fragp
, asection
*sec
)
16279 /* Assume worst case for symbols not known to be in the same section. */
16280 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16281 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16284 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16285 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
16286 addr
= (addr
+ 4) & ~3;
16287 /* Fix the insn as the 4-byte version if the target address is not
16288 sufficiently aligned. This is prevents an infinite loop when two
16289 instructions have contradictory range/alignment requirements. */
16293 if (val
< 0 || val
> 1020)
16298 /* Return the size of a relaxable add/sub immediate instruction. */
16300 relax_addsub (fragS
*fragp
, asection
*sec
)
16305 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
16306 op
= bfd_get_16(sec
->owner
, buf
);
16307 if ((op
& 0xf) == ((op
>> 4) & 0xf))
16308 return relax_immediate (fragp
, 8, 0);
16310 return relax_immediate (fragp
, 3, 0);
16314 /* Return the size of a relaxable branch instruction. BITS is the
16315 size of the offset field in the narrow instruction. */
16318 relax_branch (fragS
*fragp
, asection
*sec
, int bits
)
16324 /* Assume worst case for symbols not known to be in the same section. */
16325 if (!S_IS_DEFINED(fragp
->fr_symbol
)
16326 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
16329 val
= S_GET_VALUE(fragp
->fr_symbol
) + fragp
->fr_offset
;
16330 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
16333 /* Offset is a signed value *2 */
16335 if (val
>= limit
|| val
< -limit
)
16341 /* Relax a machine dependent frag. This returns the amount by which
16342 the current size of the frag should change. */
16345 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch ATTRIBUTE_UNUSED
)
16350 oldsize
= fragp
->fr_var
;
16351 switch (fragp
->fr_subtype
)
16353 case T_MNEM_ldr_pc2
:
16354 newsize
= relax_adr(fragp
, sec
);
16356 case T_MNEM_ldr_pc
:
16357 case T_MNEM_ldr_sp
:
16358 case T_MNEM_str_sp
:
16359 newsize
= relax_immediate(fragp
, 8, 2);
16363 newsize
= relax_immediate(fragp
, 5, 2);
16367 newsize
= relax_immediate(fragp
, 5, 1);
16371 newsize
= relax_immediate(fragp
, 5, 0);
16374 newsize
= relax_adr(fragp
, sec
);
16380 newsize
= relax_immediate(fragp
, 8, 0);
16383 newsize
= relax_branch(fragp
, sec
, 11);
16386 newsize
= relax_branch(fragp
, sec
, 8);
16388 case T_MNEM_add_sp
:
16389 case T_MNEM_add_pc
:
16390 newsize
= relax_immediate (fragp
, 8, 2);
16392 case T_MNEM_inc_sp
:
16393 case T_MNEM_dec_sp
:
16394 newsize
= relax_immediate (fragp
, 7, 2);
16400 newsize
= relax_addsub (fragp
, sec
);
16407 fragp
->fr_var
= -newsize
;
16408 md_convert_frag (sec
->owner
, sec
, fragp
);
16410 return -(newsize
+ oldsize
);
16412 fragp
->fr_var
= newsize
;
16413 return newsize
- oldsize
;
16416 /* Round up a section size to the appropriate boundary. */
16419 md_section_align (segT segment ATTRIBUTE_UNUSED
,
16422 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
16423 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
16425 /* For a.out, force the section size to be aligned. If we don't do
16426 this, BFD will align it for us, but it will not write out the
16427 final bytes of the section. This may be a bug in BFD, but it is
16428 easier to fix it here since that is how the other a.out targets
16432 align
= bfd_get_section_alignment (stdoutput
, segment
);
16433 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
16440 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
16441 of an rs_align_code fragment. */
16444 arm_handle_align (fragS
* fragP
)
16446 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
16447 static char const thumb_noop
[2] = { 0xc0, 0x46 };
16448 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
16449 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
16451 int bytes
, fix
, noop_size
;
16455 if (fragP
->fr_type
!= rs_align_code
)
16458 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
16459 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
16462 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16463 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
16465 if (fragP
->tc_frag_data
)
16467 if (target_big_endian
)
16468 noop
= thumb_bigend_noop
;
16471 noop_size
= sizeof (thumb_noop
);
16475 if (target_big_endian
)
16476 noop
= arm_bigend_noop
;
16479 noop_size
= sizeof (arm_noop
);
16482 if (bytes
& (noop_size
- 1))
16484 fix
= bytes
& (noop_size
- 1);
16485 memset (p
, 0, fix
);
16490 while (bytes
>= noop_size
)
16492 memcpy (p
, noop
, noop_size
);
16494 bytes
-= noop_size
;
16498 fragP
->fr_fix
+= fix
;
16499 fragP
->fr_var
= noop_size
;
16502 /* Called from md_do_align. Used to create an alignment
16503 frag in a code section. */
16506 arm_frag_align_code (int n
, int max
)
16510 /* We assume that there will never be a requirement
16511 to support alignments greater than 32 bytes. */
16512 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
16513 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
16515 p
= frag_var (rs_align_code
,
16516 MAX_MEM_FOR_RS_ALIGN_CODE
,
16518 (relax_substateT
) max
,
16525 /* Perform target specific initialisation of a frag. */
16528 arm_init_frag (fragS
* fragP
)
16530 /* Record whether this frag is in an ARM or a THUMB area. */
16531 fragP
->tc_frag_data
= thumb_mode
;
16535 /* When we change sections we need to issue a new mapping symbol. */
16538 arm_elf_change_section (void)
16541 segment_info_type
*seginfo
;
16543 /* Link an unlinked unwind index table section to the .text section. */
16544 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
16545 && elf_linked_to_section (now_seg
) == NULL
)
16546 elf_linked_to_section (now_seg
) = text_section
;
16548 if (!SEG_NORMAL (now_seg
))
16551 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
16553 /* We can ignore sections that only contain debug info. */
16554 if ((flags
& SEC_ALLOC
) == 0)
16557 seginfo
= seg_info (now_seg
);
16558 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
16559 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
16563 arm_elf_section_type (const char * str
, size_t len
)
16565 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
16566 return SHT_ARM_EXIDX
;
16571 /* Code to deal with unwinding tables. */
16573 static void add_unwind_adjustsp (offsetT
);
16575 /* Cenerate and deferred unwind frame offset. */
16578 flush_pending_unwind (void)
16582 offset
= unwind
.pending_offset
;
16583 unwind
.pending_offset
= 0;
16585 add_unwind_adjustsp (offset
);
16588 /* Add an opcode to this list for this function. Two-byte opcodes should
16589 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
16593 add_unwind_opcode (valueT op
, int length
)
16595 /* Add any deferred stack adjustment. */
16596 if (unwind
.pending_offset
)
16597 flush_pending_unwind ();
16599 unwind
.sp_restored
= 0;
16601 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
16603 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
16604 if (unwind
.opcodes
)
16605 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
16606 unwind
.opcode_alloc
);
16608 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
16613 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
16615 unwind
.opcode_count
++;
16619 /* Add unwind opcodes to adjust the stack pointer. */
16622 add_unwind_adjustsp (offsetT offset
)
16626 if (offset
> 0x200)
16628 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
16633 /* Long form: 0xb2, uleb128. */
16634 /* This might not fit in a word so add the individual bytes,
16635 remembering the list is built in reverse order. */
16636 o
= (valueT
) ((offset
- 0x204) >> 2);
16638 add_unwind_opcode (0, 1);
16640 /* Calculate the uleb128 encoding of the offset. */
16644 bytes
[n
] = o
& 0x7f;
16650 /* Add the insn. */
16652 add_unwind_opcode (bytes
[n
- 1], 1);
16653 add_unwind_opcode (0xb2, 1);
16655 else if (offset
> 0x100)
16657 /* Two short opcodes. */
16658 add_unwind_opcode (0x3f, 1);
16659 op
= (offset
- 0x104) >> 2;
16660 add_unwind_opcode (op
, 1);
16662 else if (offset
> 0)
16664 /* Short opcode. */
16665 op
= (offset
- 4) >> 2;
16666 add_unwind_opcode (op
, 1);
16668 else if (offset
< 0)
16671 while (offset
> 0x100)
16673 add_unwind_opcode (0x7f, 1);
16676 op
= ((offset
- 4) >> 2) | 0x40;
16677 add_unwind_opcode (op
, 1);
16681 /* Finish the list of unwind opcodes for this function. */
16683 finish_unwind_opcodes (void)
16687 if (unwind
.fp_used
)
16689 /* Adjust sp as necessary. */
16690 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
16691 flush_pending_unwind ();
16693 /* After restoring sp from the frame pointer. */
16694 op
= 0x90 | unwind
.fp_reg
;
16695 add_unwind_opcode (op
, 1);
16698 flush_pending_unwind ();
16702 /* Start an exception table entry. If idx is nonzero this is an index table
16706 start_unwind_section (const segT text_seg
, int idx
)
16708 const char * text_name
;
16709 const char * prefix
;
16710 const char * prefix_once
;
16711 const char * group_name
;
16715 size_t sec_name_len
;
16722 prefix
= ELF_STRING_ARM_unwind
;
16723 prefix_once
= ELF_STRING_ARM_unwind_once
;
16724 type
= SHT_ARM_EXIDX
;
16728 prefix
= ELF_STRING_ARM_unwind_info
;
16729 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
16730 type
= SHT_PROGBITS
;
16733 text_name
= segment_name (text_seg
);
16734 if (streq (text_name
, ".text"))
16737 if (strncmp (text_name
, ".gnu.linkonce.t.",
16738 strlen (".gnu.linkonce.t.")) == 0)
16740 prefix
= prefix_once
;
16741 text_name
+= strlen (".gnu.linkonce.t.");
16744 prefix_len
= strlen (prefix
);
16745 text_len
= strlen (text_name
);
16746 sec_name_len
= prefix_len
+ text_len
;
16747 sec_name
= xmalloc (sec_name_len
+ 1);
16748 memcpy (sec_name
, prefix
, prefix_len
);
16749 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
16750 sec_name
[prefix_len
+ text_len
] = '\0';
16756 /* Handle COMDAT group. */
16757 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
16759 group_name
= elf_group_name (text_seg
);
16760 if (group_name
== NULL
)
16762 as_bad ("Group section `%s' has no group signature",
16763 segment_name (text_seg
));
16764 ignore_rest_of_line ();
16767 flags
|= SHF_GROUP
;
16771 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
16773 /* Set the setion link for index tables. */
16775 elf_linked_to_section (now_seg
) = text_seg
;
16779 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
16780 personality routine data. Returns zero, or the index table value for
16781 and inline entry. */
16784 create_unwind_entry (int have_data
)
16789 /* The current word of data. */
16791 /* The number of bytes left in this word. */
16794 finish_unwind_opcodes ();
16796 /* Remember the current text section. */
16797 unwind
.saved_seg
= now_seg
;
16798 unwind
.saved_subseg
= now_subseg
;
16800 start_unwind_section (now_seg
, 0);
16802 if (unwind
.personality_routine
== NULL
)
16804 if (unwind
.personality_index
== -2)
16807 as_bad (_("handerdata in cantunwind frame"));
16808 return 1; /* EXIDX_CANTUNWIND. */
16811 /* Use a default personality routine if none is specified. */
16812 if (unwind
.personality_index
== -1)
16814 if (unwind
.opcode_count
> 3)
16815 unwind
.personality_index
= 1;
16817 unwind
.personality_index
= 0;
16820 /* Space for the personality routine entry. */
16821 if (unwind
.personality_index
== 0)
16823 if (unwind
.opcode_count
> 3)
16824 as_bad (_("too many unwind opcodes for personality routine 0"));
16828 /* All the data is inline in the index table. */
16831 while (unwind
.opcode_count
> 0)
16833 unwind
.opcode_count
--;
16834 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16838 /* Pad with "finish" opcodes. */
16840 data
= (data
<< 8) | 0xb0;
16847 /* We get two opcodes "free" in the first word. */
16848 size
= unwind
.opcode_count
- 2;
16851 /* An extra byte is required for the opcode count. */
16852 size
= unwind
.opcode_count
+ 1;
16854 size
= (size
+ 3) >> 2;
16856 as_bad (_("too many unwind opcodes"));
16858 frag_align (2, 0, 0);
16859 record_alignment (now_seg
, 2);
16860 unwind
.table_entry
= expr_build_dot ();
16862 /* Allocate the table entry. */
16863 ptr
= frag_more ((size
<< 2) + 4);
16864 where
= frag_now_fix () - ((size
<< 2) + 4);
16866 switch (unwind
.personality_index
)
16869 /* ??? Should this be a PLT generating relocation? */
16870 /* Custom personality routine. */
16871 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
16872 BFD_RELOC_ARM_PREL31
);
16877 /* Set the first byte to the number of additional words. */
16882 /* ABI defined personality routines. */
16884 /* Three opcodes bytes are packed into the first word. */
16891 /* The size and first two opcode bytes go in the first word. */
16892 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
16897 /* Should never happen. */
16901 /* Pack the opcodes into words (MSB first), reversing the list at the same
16903 while (unwind
.opcode_count
> 0)
16907 md_number_to_chars (ptr
, data
, 4);
16912 unwind
.opcode_count
--;
16914 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
16917 /* Finish off the last word. */
16920 /* Pad with "finish" opcodes. */
16922 data
= (data
<< 8) | 0xb0;
16924 md_number_to_chars (ptr
, data
, 4);
16929 /* Add an empty descriptor if there is no user-specified data. */
16930 ptr
= frag_more (4);
16931 md_number_to_chars (ptr
, 0, 4);
16938 /* Initialize the DWARF-2 unwind information for this procedure. */
16941 tc_arm_frame_initial_instructions (void)
16943 cfi_add_CFA_def_cfa (REG_SP
, 0);
16945 #endif /* OBJ_ELF */
16947 /* Convert REGNAME to a DWARF-2 register number. */
16950 tc_arm_regname_to_dw2regnum (char *regname
)
16952 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
16962 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
16966 expr
.X_op
= O_secrel
;
16967 expr
.X_add_symbol
= symbol
;
16968 expr
.X_add_number
= 0;
16969 emit_expr (&expr
, size
);
16973 /* MD interface: Symbol and relocation handling. */
16975 /* Return the address within the segment that a PC-relative fixup is
16976 relative to. For ARM, PC-relative fixups applied to instructions
16977 are generally relative to the location of the fixup plus 8 bytes.
16978 Thumb branches are offset by 4, and Thumb loads relative to PC
16979 require special handling. */
16982 md_pcrel_from_section (fixS
* fixP
, segT seg
)
16984 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
16986 /* If this is pc-relative and we are going to emit a relocation
16987 then we just want to put out any pipeline compensation that the linker
16988 will need. Otherwise we want to use the calculated base.
16989 For WinCE we skip the bias for externals as well, since this
16990 is how the MS ARM-CE assembler behaves and we want to be compatible. */
16992 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
16993 || (arm_force_relocation (fixP
)
16995 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
17000 switch (fixP
->fx_r_type
)
17002 /* PC relative addressing on the Thumb is slightly odd as the
17003 bottom two bits of the PC are forced to zero for the
17004 calculation. This happens *after* application of the
17005 pipeline offset. However, Thumb adrl already adjusts for
17006 this, so we need not do it again. */
17007 case BFD_RELOC_ARM_THUMB_ADD
:
17010 case BFD_RELOC_ARM_THUMB_OFFSET
:
17011 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17012 case BFD_RELOC_ARM_T32_ADD_PC12
:
17013 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17014 return (base
+ 4) & ~3;
17016 /* Thumb branches are simply offset by +4. */
17017 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
17018 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
17019 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
17020 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17021 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17022 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17023 case BFD_RELOC_THUMB_PCREL_BLX
:
17026 /* ARM mode branches are offset by +8. However, the Windows CE
17027 loader expects the relocation not to take this into account. */
17028 case BFD_RELOC_ARM_PCREL_BRANCH
:
17029 case BFD_RELOC_ARM_PCREL_CALL
:
17030 case BFD_RELOC_ARM_PCREL_JUMP
:
17031 case BFD_RELOC_ARM_PCREL_BLX
:
17032 case BFD_RELOC_ARM_PLT32
:
17034 /* When handling fixups immediately, because we have already
17035 discovered the value of a symbol, or the address of the frag involved
17036 we must account for the offset by +8, as the OS loader will never see the reloc.
17037 see fixup_segment() in write.c
17038 The S_IS_EXTERNAL test handles the case of global symbols.
17039 Those need the calculated base, not just the pipe compensation the linker will need. */
17041 && fixP
->fx_addsy
!= NULL
17042 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
17043 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
17050 /* ARM mode loads relative to PC are also offset by +8. Unlike
17051 branches, the Windows CE loader *does* expect the relocation
17052 to take this into account. */
17053 case BFD_RELOC_ARM_OFFSET_IMM
:
17054 case BFD_RELOC_ARM_OFFSET_IMM8
:
17055 case BFD_RELOC_ARM_HWLITERAL
:
17056 case BFD_RELOC_ARM_LITERAL
:
17057 case BFD_RELOC_ARM_CP_OFF_IMM
:
17061 /* Other PC-relative relocations are un-offset. */
17067 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
17068 Otherwise we have no need to default values of symbols. */
17071 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
17074 if (name
[0] == '_' && name
[1] == 'G'
17075 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
17079 if (symbol_find (name
))
17080 as_bad ("GOT already in the symbol table");
17082 GOT_symbol
= symbol_new (name
, undefined_section
,
17083 (valueT
) 0, & zero_address_frag
);
17093 /* Subroutine of md_apply_fix. Check to see if an immediate can be
17094 computed as two separate immediate values, added together. We
17095 already know that this value cannot be computed by just one ARM
17098 static unsigned int
17099 validate_immediate_twopart (unsigned int val
,
17100 unsigned int * highpart
)
17105 for (i
= 0; i
< 32; i
+= 2)
17106 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
17112 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
17114 else if (a
& 0xff0000)
17116 if (a
& 0xff000000)
17118 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
17122 assert (a
& 0xff000000);
17123 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
17126 return (a
& 0xff) | (i
<< 7);
17133 validate_offset_imm (unsigned int val
, int hwse
)
17135 if ((hwse
&& val
> 255) || val
> 4095)
17140 /* Subroutine of md_apply_fix. Do those data_ops which can take a
17141 negative immediate constant by altering the instruction. A bit of
17146 by inverting the second operand, and
17149 by negating the second operand. */
17152 negate_data_op (unsigned long * instruction
,
17153 unsigned long value
)
17156 unsigned long negated
, inverted
;
17158 negated
= encode_arm_immediate (-value
);
17159 inverted
= encode_arm_immediate (~value
);
17161 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
17164 /* First negates. */
17165 case OPCODE_SUB
: /* ADD <-> SUB */
17166 new_inst
= OPCODE_ADD
;
17171 new_inst
= OPCODE_SUB
;
17175 case OPCODE_CMP
: /* CMP <-> CMN */
17176 new_inst
= OPCODE_CMN
;
17181 new_inst
= OPCODE_CMP
;
17185 /* Now Inverted ops. */
17186 case OPCODE_MOV
: /* MOV <-> MVN */
17187 new_inst
= OPCODE_MVN
;
17192 new_inst
= OPCODE_MOV
;
17196 case OPCODE_AND
: /* AND <-> BIC */
17197 new_inst
= OPCODE_BIC
;
17202 new_inst
= OPCODE_AND
;
17206 case OPCODE_ADC
: /* ADC <-> SBC */
17207 new_inst
= OPCODE_SBC
;
17212 new_inst
= OPCODE_ADC
;
17216 /* We cannot do anything. */
17221 if (value
== (unsigned) FAIL
)
17224 *instruction
&= OPCODE_MASK
;
17225 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
17229 /* Like negate_data_op, but for Thumb-2. */
17231 static unsigned int
17232 thumb32_negate_data_op (offsetT
*instruction
, offsetT value
)
17236 offsetT negated
, inverted
;
17238 negated
= encode_thumb32_immediate (-value
);
17239 inverted
= encode_thumb32_immediate (~value
);
17241 rd
= (*instruction
>> 8) & 0xf;
17242 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
17245 /* ADD <-> SUB. Includes CMP <-> CMN. */
17246 case T2_OPCODE_SUB
:
17247 new_inst
= T2_OPCODE_ADD
;
17251 case T2_OPCODE_ADD
:
17252 new_inst
= T2_OPCODE_SUB
;
17256 /* ORR <-> ORN. Includes MOV <-> MVN. */
17257 case T2_OPCODE_ORR
:
17258 new_inst
= T2_OPCODE_ORN
;
17262 case T2_OPCODE_ORN
:
17263 new_inst
= T2_OPCODE_ORR
;
17267 /* AND <-> BIC. TST has no inverted equivalent. */
17268 case T2_OPCODE_AND
:
17269 new_inst
= T2_OPCODE_BIC
;
17276 case T2_OPCODE_BIC
:
17277 new_inst
= T2_OPCODE_AND
;
17282 case T2_OPCODE_ADC
:
17283 new_inst
= T2_OPCODE_SBC
;
17287 case T2_OPCODE_SBC
:
17288 new_inst
= T2_OPCODE_ADC
;
17292 /* We cannot do anything. */
17300 *instruction
&= T2_OPCODE_MASK
;
17301 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
17305 /* Read a 32-bit thumb instruction from buf. */
17306 static unsigned long
17307 get_thumb32_insn (char * buf
)
17309 unsigned long insn
;
17310 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
17311 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17317 /* We usually want to set the low bit on the address of thumb function
17318 symbols. In particular .word foo - . should have the low bit set.
17319 Generic code tries to fold the difference of two symbols to
17320 a constant. Prevent this and force a relocation when the first symbols
17321 is a thumb function. */
17323 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
17325 if (op
== O_subtract
17326 && l
->X_op
== O_symbol
17327 && r
->X_op
== O_symbol
17328 && THUMB_IS_FUNC (l
->X_add_symbol
))
17330 l
->X_op
= O_subtract
;
17331 l
->X_op_symbol
= r
->X_add_symbol
;
17332 l
->X_add_number
-= r
->X_add_number
;
17335 /* Process as normal. */
17340 md_apply_fix (fixS
* fixP
,
17344 offsetT value
= * valP
;
17346 unsigned int newimm
;
17347 unsigned long temp
;
17349 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
17351 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
17353 /* Note whether this will delete the relocation. */
17355 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
17358 /* On a 64-bit host, silently truncate 'value' to 32 bits for
17359 consistency with the behavior on 32-bit hosts. Remember value
17361 value
&= 0xffffffff;
17362 value
^= 0x80000000;
17363 value
-= 0x80000000;
17366 fixP
->fx_addnumber
= value
;
17368 /* Same treatment for fixP->fx_offset. */
17369 fixP
->fx_offset
&= 0xffffffff;
17370 fixP
->fx_offset
^= 0x80000000;
17371 fixP
->fx_offset
-= 0x80000000;
17373 switch (fixP
->fx_r_type
)
17375 case BFD_RELOC_NONE
:
17376 /* This will need to go in the object file. */
17380 case BFD_RELOC_ARM_IMMEDIATE
:
17381 /* We claim that this fixup has been processed here,
17382 even if in fact we generate an error because we do
17383 not have a reloc for it, so tc_gen_reloc will reject it. */
17387 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17389 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17390 _("undefined symbol %s used as an immediate value"),
17391 S_GET_NAME (fixP
->fx_addsy
));
17395 newimm
= encode_arm_immediate (value
);
17396 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17398 /* If the instruction will fail, see if we can fix things up by
17399 changing the opcode. */
17400 if (newimm
== (unsigned int) FAIL
17401 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
17403 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17404 _("invalid constant (%lx) after fixup"),
17405 (unsigned long) value
);
17409 newimm
|= (temp
& 0xfffff000);
17410 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17413 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
17415 unsigned int highpart
= 0;
17416 unsigned int newinsn
= 0xe1a00000; /* nop. */
17418 newimm
= encode_arm_immediate (value
);
17419 temp
= md_chars_to_number (buf
, INSN_SIZE
);
17421 /* If the instruction will fail, see if we can fix things up by
17422 changing the opcode. */
17423 if (newimm
== (unsigned int) FAIL
17424 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
17426 /* No ? OK - try using two ADD instructions to generate
17428 newimm
= validate_immediate_twopart (value
, & highpart
);
17430 /* Yes - then make sure that the second instruction is
17432 if (newimm
!= (unsigned int) FAIL
)
17434 /* Still No ? Try using a negated value. */
17435 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
17436 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
17437 /* Otherwise - give up. */
17440 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17441 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
17446 /* Replace the first operand in the 2nd instruction (which
17447 is the PC) with the destination register. We have
17448 already added in the PC in the first instruction and we
17449 do not want to do it again. */
17450 newinsn
&= ~ 0xf0000;
17451 newinsn
|= ((newinsn
& 0x0f000) << 4);
17454 newimm
|= (temp
& 0xfffff000);
17455 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
17457 highpart
|= (newinsn
& 0xfffff000);
17458 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
17462 case BFD_RELOC_ARM_OFFSET_IMM
:
17463 if (!fixP
->fx_done
&& seg
->use_rela_p
)
17466 case BFD_RELOC_ARM_LITERAL
:
17472 if (validate_offset_imm (value
, 0) == FAIL
)
17474 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
17475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17476 _("invalid literal constant: pool needs to be closer"));
17478 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17479 _("bad immediate value for offset (%ld)"),
17484 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17485 newval
&= 0xff7ff000;
17486 newval
|= value
| (sign
? INDEX_UP
: 0);
17487 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17490 case BFD_RELOC_ARM_OFFSET_IMM8
:
17491 case BFD_RELOC_ARM_HWLITERAL
:
17497 if (validate_offset_imm (value
, 1) == FAIL
)
17499 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
17500 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17501 _("invalid literal constant: pool needs to be closer"));
17503 as_bad (_("bad immediate value for half-word offset (%ld)"),
17508 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17509 newval
&= 0xff7ff0f0;
17510 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
17511 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17514 case BFD_RELOC_ARM_T32_OFFSET_U8
:
17515 if (value
< 0 || value
> 1020 || value
% 4 != 0)
17516 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17517 _("bad immediate value for offset (%ld)"), (long) value
);
17520 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
17522 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
17525 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
17526 /* This is a complicated relocation used for all varieties of Thumb32
17527 load/store instruction with immediate offset:
17529 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
17530 *4, optional writeback(W)
17531 (doubleword load/store)
17533 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
17534 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
17535 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
17536 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
17537 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
17539 Uppercase letters indicate bits that are already encoded at
17540 this point. Lowercase letters are our problem. For the
17541 second block of instructions, the secondary opcode nybble
17542 (bits 8..11) is present, and bit 23 is zero, even if this is
17543 a PC-relative operation. */
17544 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17546 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
17548 if ((newval
& 0xf0000000) == 0xe0000000)
17550 /* Doubleword load/store: 8-bit offset, scaled by 4. */
17552 newval
|= (1 << 23);
17555 if (value
% 4 != 0)
17557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17558 _("offset not a multiple of 4"));
17564 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17565 _("offset out of range"));
17570 else if ((newval
& 0x000f0000) == 0x000f0000)
17572 /* PC-relative, 12-bit offset. */
17574 newval
|= (1 << 23);
17579 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17580 _("offset out of range"));
17585 else if ((newval
& 0x00000100) == 0x00000100)
17587 /* Writeback: 8-bit, +/- offset. */
17589 newval
|= (1 << 9);
17594 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17595 _("offset out of range"));
17600 else if ((newval
& 0x00000f00) == 0x00000e00)
17602 /* T-instruction: positive 8-bit offset. */
17603 if (value
< 0 || value
> 0xff)
17605 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17606 _("offset out of range"));
17614 /* Positive 12-bit or negative 8-bit offset. */
17618 newval
|= (1 << 23);
17628 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17629 _("offset out of range"));
17636 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
17637 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
17640 case BFD_RELOC_ARM_SHIFT_IMM
:
17641 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17642 if (((unsigned long) value
) > 32
17644 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
17646 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17647 _("shift expression is too large"));
17652 /* Shifts of zero must be done as lsl. */
17654 else if (value
== 32)
17656 newval
&= 0xfffff07f;
17657 newval
|= (value
& 0x1f) << 7;
17658 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17661 case BFD_RELOC_ARM_T32_IMMEDIATE
:
17662 case BFD_RELOC_ARM_T32_ADD_IMM
:
17663 case BFD_RELOC_ARM_T32_IMM12
:
17664 case BFD_RELOC_ARM_T32_ADD_PC12
:
17665 /* We claim that this fixup has been processed here,
17666 even if in fact we generate an error because we do
17667 not have a reloc for it, so tc_gen_reloc will reject it. */
17671 && ! S_IS_DEFINED (fixP
->fx_addsy
))
17673 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17674 _("undefined symbol %s used as an immediate value"),
17675 S_GET_NAME (fixP
->fx_addsy
));
17679 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17681 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
17684 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
17685 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17687 newimm
= encode_thumb32_immediate (value
);
17688 if (newimm
== (unsigned int) FAIL
)
17689 newimm
= thumb32_negate_data_op (&newval
, value
);
17691 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
17692 && newimm
== (unsigned int) FAIL
)
17694 /* Turn add/sum into addw/subw. */
17695 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
17696 newval
= (newval
& 0xfeffffff) | 0x02000000;
17698 /* 12 bit immediate for addw/subw. */
17702 newval
^= 0x00a00000;
17705 newimm
= (unsigned int) FAIL
;
17710 if (newimm
== (unsigned int)FAIL
)
17712 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17713 _("invalid constant (%lx) after fixup"),
17714 (unsigned long) value
);
17718 newval
|= (newimm
& 0x800) << 15;
17719 newval
|= (newimm
& 0x700) << 4;
17720 newval
|= (newimm
& 0x0ff);
17722 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
17723 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
17726 case BFD_RELOC_ARM_SMC
:
17727 if (((unsigned long) value
) > 0xffff)
17728 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17729 _("invalid smc expression"));
17730 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17731 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
17732 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17735 case BFD_RELOC_ARM_SWI
:
17736 if (fixP
->tc_fix_data
!= 0)
17738 if (((unsigned long) value
) > 0xff)
17739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17740 _("invalid swi expression"));
17741 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17743 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17747 if (((unsigned long) value
) > 0x00ffffff)
17748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17749 _("invalid swi expression"));
17750 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17752 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17756 case BFD_RELOC_ARM_MULTI
:
17757 if (((unsigned long) value
) > 0xffff)
17758 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17759 _("invalid expression in load/store multiple"));
17760 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
17761 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17765 case BFD_RELOC_ARM_PCREL_CALL
:
17766 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17767 if ((newval
& 0xf0000000) == 0xf0000000)
17771 goto arm_branch_common
;
17773 case BFD_RELOC_ARM_PCREL_JUMP
:
17774 case BFD_RELOC_ARM_PLT32
:
17776 case BFD_RELOC_ARM_PCREL_BRANCH
:
17778 goto arm_branch_common
;
17780 case BFD_RELOC_ARM_PCREL_BLX
:
17783 /* We are going to store value (shifted right by two) in the
17784 instruction, in a 24 bit, signed field. Bits 26 through 32 either
17785 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
17786 also be be clear. */
17788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17789 _("misaligned branch destination"));
17790 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
17791 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
17792 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17793 _("branch out of range"));
17795 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17797 newval
= md_chars_to_number (buf
, INSN_SIZE
);
17798 newval
|= (value
>> 2) & 0x00ffffff;
17799 /* Set the H bit on BLX instructions. */
17803 newval
|= 0x01000000;
17805 newval
&= ~0x01000000;
17807 md_number_to_chars (buf
, newval
, INSN_SIZE
);
17811 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CZB */
17812 /* CZB can only branch forward. */
17814 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17815 _("branch out of range"));
17817 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17819 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17820 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
17821 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17825 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
17826 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
17827 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17828 _("branch out of range"));
17830 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17832 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17833 newval
|= (value
& 0x1ff) >> 1;
17834 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17838 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
17839 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
17840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17841 _("branch out of range"));
17843 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17845 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17846 newval
|= (value
& 0xfff) >> 1;
17847 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17851 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
17852 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
17853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17854 _("conditional branch out of range"));
17856 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17859 addressT S
, J1
, J2
, lo
, hi
;
17861 S
= (value
& 0x00100000) >> 20;
17862 J2
= (value
& 0x00080000) >> 19;
17863 J1
= (value
& 0x00040000) >> 18;
17864 hi
= (value
& 0x0003f000) >> 12;
17865 lo
= (value
& 0x00000ffe) >> 1;
17867 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17868 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17869 newval
|= (S
<< 10) | hi
;
17870 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
17871 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17872 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17876 case BFD_RELOC_THUMB_PCREL_BLX
:
17877 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
17878 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
17879 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17880 _("branch out of range"));
17882 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
17883 /* For a BLX instruction, make sure that the relocation is rounded up
17884 to a word boundary. This follows the semantics of the instruction
17885 which specifies that bit 1 of the target address will come from bit
17886 1 of the base address. */
17887 value
= (value
+ 1) & ~ 1;
17889 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17893 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17894 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17895 newval
|= (value
& 0x7fffff) >> 12;
17896 newval2
|= (value
& 0xfff) >> 1;
17897 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17898 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17902 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
17903 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
17904 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17905 _("branch out of range"));
17907 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17910 addressT S
, I1
, I2
, lo
, hi
;
17912 S
= (value
& 0x01000000) >> 24;
17913 I1
= (value
& 0x00800000) >> 23;
17914 I2
= (value
& 0x00400000) >> 22;
17915 hi
= (value
& 0x003ff000) >> 12;
17916 lo
= (value
& 0x00000ffe) >> 1;
17921 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
17922 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
17923 newval
|= (S
<< 10) | hi
;
17924 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
17925 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
17926 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
17931 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17932 md_number_to_chars (buf
, value
, 1);
17936 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17937 md_number_to_chars (buf
, value
, 2);
17941 case BFD_RELOC_ARM_TLS_GD32
:
17942 case BFD_RELOC_ARM_TLS_LE32
:
17943 case BFD_RELOC_ARM_TLS_IE32
:
17944 case BFD_RELOC_ARM_TLS_LDM32
:
17945 case BFD_RELOC_ARM_TLS_LDO32
:
17946 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
17949 case BFD_RELOC_ARM_GOT32
:
17950 case BFD_RELOC_ARM_GOTOFF
:
17951 case BFD_RELOC_ARM_TARGET2
:
17952 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17953 md_number_to_chars (buf
, 0, 4);
17957 case BFD_RELOC_RVA
:
17959 case BFD_RELOC_ARM_TARGET1
:
17960 case BFD_RELOC_ARM_ROSEGREL32
:
17961 case BFD_RELOC_ARM_SBREL32
:
17962 case BFD_RELOC_32_PCREL
:
17964 case BFD_RELOC_32_SECREL
:
17966 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17968 /* For WinCE we only do this for pcrel fixups. */
17969 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
17971 md_number_to_chars (buf
, value
, 4);
17975 case BFD_RELOC_ARM_PREL31
:
17976 if (fixP
->fx_done
|| !seg
->use_rela_p
)
17978 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
17979 if ((value
^ (value
>> 1)) & 0x40000000)
17981 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17982 _("rel31 relocation overflow"));
17984 newval
|= value
& 0x7fffffff;
17985 md_number_to_chars (buf
, newval
, 4);
17990 case BFD_RELOC_ARM_CP_OFF_IMM
:
17991 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
17992 if (value
< -1023 || value
> 1023 || (value
& 3))
17993 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
17994 _("co-processor offset out of range"));
17999 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18000 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18001 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18003 newval
= get_thumb32_insn (buf
);
18004 newval
&= 0xff7fff00;
18005 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
18007 newval
&= ~WRITE_BACK
;
18008 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
18009 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
18010 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18012 put_thumb32_insn (buf
, newval
);
18015 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
18016 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
18017 if (value
< -255 || value
> 255)
18018 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18019 _("co-processor offset out of range"));
18021 goto cp_off_common
;
18023 case BFD_RELOC_ARM_THUMB_OFFSET
:
18024 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18025 /* Exactly what ranges, and where the offset is inserted depends
18026 on the type of instruction, we can establish this from the
18028 switch (newval
>> 12)
18030 case 4: /* PC load. */
18031 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
18032 forced to zero for these loads; md_pcrel_from has already
18033 compensated for this. */
18035 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18036 _("invalid offset, target not word aligned (0x%08lX)"),
18037 (((unsigned long) fixP
->fx_frag
->fr_address
18038 + (unsigned long) fixP
->fx_where
) & ~3)
18039 + (unsigned long) value
);
18041 if (value
& ~0x3fc)
18042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18043 _("invalid offset, value too big (0x%08lX)"),
18046 newval
|= value
>> 2;
18049 case 9: /* SP load/store. */
18050 if (value
& ~0x3fc)
18051 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18052 _("invalid offset, value too big (0x%08lX)"),
18054 newval
|= value
>> 2;
18057 case 6: /* Word load/store. */
18059 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18060 _("invalid offset, value too big (0x%08lX)"),
18062 newval
|= value
<< 4; /* 6 - 2. */
18065 case 7: /* Byte load/store. */
18067 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18068 _("invalid offset, value too big (0x%08lX)"),
18070 newval
|= value
<< 6;
18073 case 8: /* Halfword load/store. */
18075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18076 _("invalid offset, value too big (0x%08lX)"),
18078 newval
|= value
<< 5; /* 6 - 1. */
18082 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18083 "Unable to process relocation for thumb opcode: %lx",
18084 (unsigned long) newval
);
18087 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18090 case BFD_RELOC_ARM_THUMB_ADD
:
18091 /* This is a complicated relocation, since we use it for all of
18092 the following immediate relocations:
18096 9bit ADD/SUB SP word-aligned
18097 10bit ADD PC/SP word-aligned
18099 The type of instruction being processed is encoded in the
18106 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18108 int rd
= (newval
>> 4) & 0xf;
18109 int rs
= newval
& 0xf;
18110 int subtract
= !!(newval
& 0x8000);
18112 /* Check for HI regs, only very restricted cases allowed:
18113 Adjusting SP, and using PC or SP to get an address. */
18114 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
18115 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
18116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18117 _("invalid Hi register with immediate"));
18119 /* If value is negative, choose the opposite instruction. */
18123 subtract
= !subtract
;
18125 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18126 _("immediate value out of range"));
18131 if (value
& ~0x1fc)
18132 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18133 _("invalid immediate for stack address calculation"));
18134 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
18135 newval
|= value
>> 2;
18137 else if (rs
== REG_PC
|| rs
== REG_SP
)
18139 if (subtract
|| value
& ~0x3fc)
18140 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18141 _("invalid immediate for address calculation (value = 0x%08lX)"),
18142 (unsigned long) value
);
18143 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
18145 newval
|= value
>> 2;
18150 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18151 _("immediate value out of range"));
18152 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
18153 newval
|= (rd
<< 8) | value
;
18158 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18159 _("immediate value out of range"));
18160 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
18161 newval
|= rd
| (rs
<< 3) | (value
<< 6);
18164 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18167 case BFD_RELOC_ARM_THUMB_IMM
:
18168 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18169 if (value
< 0 || value
> 255)
18170 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18171 _("invalid immediate: %ld is too large"),
18174 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18177 case BFD_RELOC_ARM_THUMB_SHIFT
:
18178 /* 5bit shift value (0..32). LSL cannot take 32. */
18179 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
18180 temp
= newval
& 0xf800;
18181 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
18182 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18183 _("invalid shift value: %ld"), (long) value
);
18184 /* Shifts of zero must be encoded as LSL. */
18186 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
18187 /* Shifts of 32 are encoded as zero. */
18188 else if (value
== 32)
18190 newval
|= value
<< 6;
18191 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18194 case BFD_RELOC_VTABLE_INHERIT
:
18195 case BFD_RELOC_VTABLE_ENTRY
:
18199 case BFD_RELOC_ARM_MOVW
:
18200 case BFD_RELOC_ARM_MOVT
:
18201 case BFD_RELOC_ARM_THUMB_MOVW
:
18202 case BFD_RELOC_ARM_THUMB_MOVT
:
18203 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18205 /* REL format relocations are limited to a 16-bit addend. */
18206 if (!fixP
->fx_done
)
18208 if (value
< -0x1000 || value
> 0xffff)
18209 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18210 _("offset too big"));
18212 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
18213 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18218 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
18219 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
18221 newval
= get_thumb32_insn (buf
);
18222 newval
&= 0xfbf08f00;
18223 newval
|= (value
& 0xf000) << 4;
18224 newval
|= (value
& 0x0800) << 15;
18225 newval
|= (value
& 0x0700) << 4;
18226 newval
|= (value
& 0x00ff);
18227 put_thumb32_insn (buf
, newval
);
18231 newval
= md_chars_to_number (buf
, 4);
18232 newval
&= 0xfff0f000;
18233 newval
|= value
& 0x0fff;
18234 newval
|= (value
& 0xf000) << 4;
18235 md_number_to_chars (buf
, newval
, 4);
18240 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18241 case BFD_RELOC_ARM_ALU_PC_G0
:
18242 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18243 case BFD_RELOC_ARM_ALU_PC_G1
:
18244 case BFD_RELOC_ARM_ALU_PC_G2
:
18245 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18246 case BFD_RELOC_ARM_ALU_SB_G0
:
18247 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18248 case BFD_RELOC_ARM_ALU_SB_G1
:
18249 case BFD_RELOC_ARM_ALU_SB_G2
:
18250 assert (!fixP
->fx_done
);
18251 if (!seg
->use_rela_p
)
18254 bfd_vma encoded_addend
;
18255 bfd_vma addend_abs
= abs (value
);
18257 /* Check that the absolute value of the addend can be
18258 expressed as an 8-bit constant plus a rotation. */
18259 encoded_addend
= encode_arm_immediate (addend_abs
);
18260 if (encoded_addend
== (unsigned int) FAIL
)
18261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18262 _("the offset 0x%08lX is not representable"),
18265 /* Extract the instruction. */
18266 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18268 /* If the addend is positive, use an ADD instruction.
18269 Otherwise use a SUB. Take care not to destroy the S bit. */
18270 insn
&= 0xff1fffff;
18276 /* Place the encoded addend into the first 12 bits of the
18278 insn
&= 0xfffff000;
18279 insn
|= encoded_addend
;
18281 /* Update the instruction. */
18282 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18286 case BFD_RELOC_ARM_LDR_PC_G0
:
18287 case BFD_RELOC_ARM_LDR_PC_G1
:
18288 case BFD_RELOC_ARM_LDR_PC_G2
:
18289 case BFD_RELOC_ARM_LDR_SB_G0
:
18290 case BFD_RELOC_ARM_LDR_SB_G1
:
18291 case BFD_RELOC_ARM_LDR_SB_G2
:
18292 assert (!fixP
->fx_done
);
18293 if (!seg
->use_rela_p
)
18296 bfd_vma addend_abs
= abs (value
);
18298 /* Check that the absolute value of the addend can be
18299 encoded in 12 bits. */
18300 if (addend_abs
>= 0x1000)
18301 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18302 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
18305 /* Extract the instruction. */
18306 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18308 /* If the addend is negative, clear bit 23 of the instruction.
18309 Otherwise set it. */
18311 insn
&= ~(1 << 23);
18315 /* Place the absolute value of the addend into the first 12 bits
18316 of the instruction. */
18317 insn
&= 0xfffff000;
18318 insn
|= addend_abs
;
18320 /* Update the instruction. */
18321 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18325 case BFD_RELOC_ARM_LDRS_PC_G0
:
18326 case BFD_RELOC_ARM_LDRS_PC_G1
:
18327 case BFD_RELOC_ARM_LDRS_PC_G2
:
18328 case BFD_RELOC_ARM_LDRS_SB_G0
:
18329 case BFD_RELOC_ARM_LDRS_SB_G1
:
18330 case BFD_RELOC_ARM_LDRS_SB_G2
:
18331 assert (!fixP
->fx_done
);
18332 if (!seg
->use_rela_p
)
18335 bfd_vma addend_abs
= abs (value
);
18337 /* Check that the absolute value of the addend can be
18338 encoded in 8 bits. */
18339 if (addend_abs
>= 0x100)
18340 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18341 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
18344 /* Extract the instruction. */
18345 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18347 /* If the addend is negative, clear bit 23 of the instruction.
18348 Otherwise set it. */
18350 insn
&= ~(1 << 23);
18354 /* Place the first four bits of the absolute value of the addend
18355 into the first 4 bits of the instruction, and the remaining
18356 four into bits 8 .. 11. */
18357 insn
&= 0xfffff0f0;
18358 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
18360 /* Update the instruction. */
18361 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18365 case BFD_RELOC_ARM_LDC_PC_G0
:
18366 case BFD_RELOC_ARM_LDC_PC_G1
:
18367 case BFD_RELOC_ARM_LDC_PC_G2
:
18368 case BFD_RELOC_ARM_LDC_SB_G0
:
18369 case BFD_RELOC_ARM_LDC_SB_G1
:
18370 case BFD_RELOC_ARM_LDC_SB_G2
:
18371 assert (!fixP
->fx_done
);
18372 if (!seg
->use_rela_p
)
18375 bfd_vma addend_abs
= abs (value
);
18377 /* Check that the absolute value of the addend is a multiple of
18378 four and, when divided by four, fits in 8 bits. */
18379 if (addend_abs
& 0x3)
18380 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18381 _("bad offset 0x%08lX (must be word-aligned)"),
18384 if ((addend_abs
>> 2) > 0xff)
18385 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18386 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
18389 /* Extract the instruction. */
18390 insn
= md_chars_to_number (buf
, INSN_SIZE
);
18392 /* If the addend is negative, clear bit 23 of the instruction.
18393 Otherwise set it. */
18395 insn
&= ~(1 << 23);
18399 /* Place the addend (divided by four) into the first eight
18400 bits of the instruction. */
18401 insn
&= 0xfffffff0;
18402 insn
|= addend_abs
>> 2;
18404 /* Update the instruction. */
18405 md_number_to_chars (buf
, insn
, INSN_SIZE
);
18409 case BFD_RELOC_UNUSED
:
18411 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18412 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
18416 /* Translate internal representation of relocation info to BFD target
18420 tc_gen_reloc (asection
*section
, fixS
*fixp
)
18423 bfd_reloc_code_real_type code
;
18425 reloc
= xmalloc (sizeof (arelent
));
18427 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
18428 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
18429 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
18431 if (fixp
->fx_pcrel
)
18433 if (section
->use_rela_p
)
18434 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
18436 fixp
->fx_offset
= reloc
->address
;
18438 reloc
->addend
= fixp
->fx_offset
;
18440 switch (fixp
->fx_r_type
)
18443 if (fixp
->fx_pcrel
)
18445 code
= BFD_RELOC_8_PCREL
;
18450 if (fixp
->fx_pcrel
)
18452 code
= BFD_RELOC_16_PCREL
;
18457 if (fixp
->fx_pcrel
)
18459 code
= BFD_RELOC_32_PCREL
;
18463 case BFD_RELOC_ARM_MOVW
:
18464 if (fixp
->fx_pcrel
)
18466 code
= BFD_RELOC_ARM_MOVW_PCREL
;
18470 case BFD_RELOC_ARM_MOVT
:
18471 if (fixp
->fx_pcrel
)
18473 code
= BFD_RELOC_ARM_MOVT_PCREL
;
18477 case BFD_RELOC_ARM_THUMB_MOVW
:
18478 if (fixp
->fx_pcrel
)
18480 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
18484 case BFD_RELOC_ARM_THUMB_MOVT
:
18485 if (fixp
->fx_pcrel
)
18487 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
18491 case BFD_RELOC_NONE
:
18492 case BFD_RELOC_ARM_PCREL_BRANCH
:
18493 case BFD_RELOC_ARM_PCREL_BLX
:
18494 case BFD_RELOC_RVA
:
18495 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18496 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18497 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18498 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18499 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18500 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18501 case BFD_RELOC_THUMB_PCREL_BLX
:
18502 case BFD_RELOC_VTABLE_ENTRY
:
18503 case BFD_RELOC_VTABLE_INHERIT
:
18505 case BFD_RELOC_32_SECREL
:
18507 code
= fixp
->fx_r_type
;
18510 case BFD_RELOC_ARM_LITERAL
:
18511 case BFD_RELOC_ARM_HWLITERAL
:
18512 /* If this is called then the a literal has
18513 been referenced across a section boundary. */
18514 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18515 _("literal referenced across section boundary"));
18519 case BFD_RELOC_ARM_GOT32
:
18520 case BFD_RELOC_ARM_GOTOFF
:
18521 case BFD_RELOC_ARM_PLT32
:
18522 case BFD_RELOC_ARM_TARGET1
:
18523 case BFD_RELOC_ARM_ROSEGREL32
:
18524 case BFD_RELOC_ARM_SBREL32
:
18525 case BFD_RELOC_ARM_PREL31
:
18526 case BFD_RELOC_ARM_TARGET2
:
18527 case BFD_RELOC_ARM_TLS_LE32
:
18528 case BFD_RELOC_ARM_TLS_LDO32
:
18529 case BFD_RELOC_ARM_PCREL_CALL
:
18530 case BFD_RELOC_ARM_PCREL_JUMP
:
18531 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
18532 case BFD_RELOC_ARM_ALU_PC_G0
:
18533 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
18534 case BFD_RELOC_ARM_ALU_PC_G1
:
18535 case BFD_RELOC_ARM_ALU_PC_G2
:
18536 case BFD_RELOC_ARM_LDR_PC_G0
:
18537 case BFD_RELOC_ARM_LDR_PC_G1
:
18538 case BFD_RELOC_ARM_LDR_PC_G2
:
18539 case BFD_RELOC_ARM_LDRS_PC_G0
:
18540 case BFD_RELOC_ARM_LDRS_PC_G1
:
18541 case BFD_RELOC_ARM_LDRS_PC_G2
:
18542 case BFD_RELOC_ARM_LDC_PC_G0
:
18543 case BFD_RELOC_ARM_LDC_PC_G1
:
18544 case BFD_RELOC_ARM_LDC_PC_G2
:
18545 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
18546 case BFD_RELOC_ARM_ALU_SB_G0
:
18547 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
18548 case BFD_RELOC_ARM_ALU_SB_G1
:
18549 case BFD_RELOC_ARM_ALU_SB_G2
:
18550 case BFD_RELOC_ARM_LDR_SB_G0
:
18551 case BFD_RELOC_ARM_LDR_SB_G1
:
18552 case BFD_RELOC_ARM_LDR_SB_G2
:
18553 case BFD_RELOC_ARM_LDRS_SB_G0
:
18554 case BFD_RELOC_ARM_LDRS_SB_G1
:
18555 case BFD_RELOC_ARM_LDRS_SB_G2
:
18556 case BFD_RELOC_ARM_LDC_SB_G0
:
18557 case BFD_RELOC_ARM_LDC_SB_G1
:
18558 case BFD_RELOC_ARM_LDC_SB_G2
:
18559 code
= fixp
->fx_r_type
;
18562 case BFD_RELOC_ARM_TLS_GD32
:
18563 case BFD_RELOC_ARM_TLS_IE32
:
18564 case BFD_RELOC_ARM_TLS_LDM32
:
18565 /* BFD will include the symbol's address in the addend.
18566 But we don't want that, so subtract it out again here. */
18567 if (!S_IS_COMMON (fixp
->fx_addsy
))
18568 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
18569 code
= fixp
->fx_r_type
;
18573 case BFD_RELOC_ARM_IMMEDIATE
:
18574 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18575 _("internal relocation (type: IMMEDIATE) not fixed up"));
18578 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18579 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18580 _("ADRL used for a symbol not defined in the same file"));
18583 case BFD_RELOC_ARM_OFFSET_IMM
:
18584 if (section
->use_rela_p
)
18586 code
= fixp
->fx_r_type
;
18590 if (fixp
->fx_addsy
!= NULL
18591 && !S_IS_DEFINED (fixp
->fx_addsy
)
18592 && S_IS_LOCAL (fixp
->fx_addsy
))
18594 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18595 _("undefined local label `%s'"),
18596 S_GET_NAME (fixp
->fx_addsy
));
18600 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18601 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
18608 switch (fixp
->fx_r_type
)
18610 case BFD_RELOC_NONE
: type
= "NONE"; break;
18611 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
18612 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
18613 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
18614 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
18615 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
18616 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
18617 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
18618 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
18619 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
18620 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
18621 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
18622 default: type
= _("<unknown>"); break;
18624 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18625 _("cannot represent %s relocation in this object file format"),
18632 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
18634 && fixp
->fx_addsy
== GOT_symbol
)
18636 code
= BFD_RELOC_ARM_GOTPC
;
18637 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
18641 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
18643 if (reloc
->howto
== NULL
)
18645 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
18646 _("cannot represent %s relocation in this object file format"),
18647 bfd_get_reloc_code_name (code
));
18651 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
18652 vtable entry to be used in the relocation's section offset. */
18653 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18654 reloc
->address
= fixp
->fx_offset
;
18659 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
18662 cons_fix_new_arm (fragS
* frag
,
18667 bfd_reloc_code_real_type type
;
18671 FIXME: @@ Should look at CPU word size. */
18675 type
= BFD_RELOC_8
;
18678 type
= BFD_RELOC_16
;
18682 type
= BFD_RELOC_32
;
18685 type
= BFD_RELOC_64
;
18690 if (exp
->X_op
== O_secrel
)
18692 exp
->X_op
= O_symbol
;
18693 type
= BFD_RELOC_32_SECREL
;
18697 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
18700 #if defined OBJ_COFF || defined OBJ_ELF
18702 arm_validate_fix (fixS
* fixP
)
18704 /* If the destination of the branch is a defined symbol which does not have
18705 the THUMB_FUNC attribute, then we must be calling a function which has
18706 the (interfacearm) attribute. We look for the Thumb entry point to that
18707 function and change the branch to refer to that function instead. */
18708 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
18709 && fixP
->fx_addsy
!= NULL
18710 && S_IS_DEFINED (fixP
->fx_addsy
)
18711 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
18713 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
18719 arm_force_relocation (struct fix
* fixp
)
18721 #if defined (OBJ_COFF) && defined (TE_PE)
18722 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
18726 /* Resolve these relocations even if the symbol is extern or weak. */
18727 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
18728 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
18729 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
18730 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
18731 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18732 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
18733 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
18736 /* Always leave these relocations for the linker. */
18737 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18738 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18739 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18742 return generic_force_reloc (fixp
);
18747 arm_fix_adjustable (fixS
* fixP
)
18749 /* This is a little hack to help the gas/arm/adrl.s test. It prevents
18750 local labels from being added to the output symbol table when they
18751 are used with the ADRL pseudo op. The ADRL relocation should always
18752 be resolved before the binbary is emitted, so it is safe to say that
18753 it is adjustable. */
18754 if (fixP
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
)
18757 /* This is a hack for the gas/all/redef2.s test. This test causes symbols
18758 to be cloned, and without this test relocs would still be generated
18759 against the original, pre-cloned symbol. Such symbols would not appear
18760 in the symbol table however, and so a valid reloc could not be
18761 generated. So check to see if the fixup is against a symbol which has
18762 been removed from the symbol chain, and if it is, then allow it to be
18763 adjusted into a reloc against a section symbol. */
18764 if (fixP
->fx_addsy
!= NULL
18765 && ! S_IS_LOCAL (fixP
->fx_addsy
)
18766 && symbol_next (fixP
->fx_addsy
) == NULL
18767 && symbol_next (fixP
->fx_addsy
) == symbol_previous (fixP
->fx_addsy
))
18775 /* Relocations against function names must be left unadjusted,
18776 so that the linker can use this information to generate interworking
18777 stubs. The MIPS version of this function
18778 also prevents relocations that are mips-16 specific, but I do not
18779 know why it does this.
18782 There is one other problem that ought to be addressed here, but
18783 which currently is not: Taking the address of a label (rather
18784 than a function) and then later jumping to that address. Such
18785 addresses also ought to have their bottom bit set (assuming that
18786 they reside in Thumb code), but at the moment they will not. */
18789 arm_fix_adjustable (fixS
* fixP
)
18791 if (fixP
->fx_addsy
== NULL
)
18794 /* Preserve relocations against symbols with function type. */
18795 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
18798 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
18799 && fixP
->fx_subsy
== NULL
)
18802 /* We need the symbol name for the VTABLE entries. */
18803 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
18804 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
18807 /* Don't allow symbols to be discarded on GOT related relocs. */
18808 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
18809 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
18810 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
18811 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
18812 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
18813 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
18814 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
18815 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
18816 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
18819 /* Similarly for group relocations. */
18820 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
18821 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
18822 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
18829 elf32_arm_target_format (void)
18832 return (target_big_endian
18833 ? "elf32-bigarm-symbian"
18834 : "elf32-littlearm-symbian");
18835 #elif defined (TE_VXWORKS)
18836 return (target_big_endian
18837 ? "elf32-bigarm-vxworks"
18838 : "elf32-littlearm-vxworks");
18840 if (target_big_endian
)
18841 return "elf32-bigarm";
18843 return "elf32-littlearm";
18848 armelf_frob_symbol (symbolS
* symp
,
18851 elf_frob_symbol (symp
, puntp
);
18855 /* MD interface: Finalization. */
18857 /* A good place to do this, although this was probably not intended
18858 for this kind of use. We need to dump the literal pool before
18859 references are made to a null symbol pointer. */
18864 literal_pool
* pool
;
18866 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
18868 /* Put it at the end of the relevent section. */
18869 subseg_set (pool
->section
, pool
->sub_section
);
18871 arm_elf_change_section ();
18877 /* Adjust the symbol table. This marks Thumb symbols as distinct from
18881 arm_adjust_symtab (void)
18886 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18888 if (ARM_IS_THUMB (sym
))
18890 if (THUMB_IS_FUNC (sym
))
18892 /* Mark the symbol as a Thumb function. */
18893 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
18894 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
18895 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
18897 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
18898 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
18900 as_bad (_("%s: unexpected function type: %d"),
18901 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
18903 else switch (S_GET_STORAGE_CLASS (sym
))
18906 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
18909 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
18912 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
18920 if (ARM_IS_INTERWORK (sym
))
18921 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
18928 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
18930 if (ARM_IS_THUMB (sym
))
18932 elf_symbol_type
* elf_sym
;
18934 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
18935 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
18937 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
18938 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
18940 /* If it's a .thumb_func, declare it as so,
18941 otherwise tag label as .code 16. */
18942 if (THUMB_IS_FUNC (sym
))
18943 elf_sym
->internal_elf_sym
.st_info
=
18944 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
18946 elf_sym
->internal_elf_sym
.st_info
=
18947 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
18954 /* MD interface: Initialization. */
18957 set_constant_flonums (void)
18961 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
18962 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
18966 /* Auto-select Thumb mode if it's the only available instruction set for the
18967 given architecture. */
18970 autoselect_thumb_from_cpu_variant (void)
18972 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18973 opcode_select (16);
18982 if ( (arm_ops_hsh
= hash_new ()) == NULL
18983 || (arm_cond_hsh
= hash_new ()) == NULL
18984 || (arm_shift_hsh
= hash_new ()) == NULL
18985 || (arm_psr_hsh
= hash_new ()) == NULL
18986 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
18987 || (arm_reg_hsh
= hash_new ()) == NULL
18988 || (arm_reloc_hsh
= hash_new ()) == NULL
18989 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
18990 as_fatal (_("virtual memory exhausted"));
18992 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
18993 hash_insert (arm_ops_hsh
, insns
[i
].template, (PTR
) (insns
+ i
));
18994 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
18995 hash_insert (arm_cond_hsh
, conds
[i
].template, (PTR
) (conds
+ i
));
18996 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
18997 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (PTR
) (shift_names
+ i
));
18998 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
18999 hash_insert (arm_psr_hsh
, psrs
[i
].template, (PTR
) (psrs
+ i
));
19000 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
19001 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (PTR
) (v7m_psrs
+ i
));
19002 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
19003 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (PTR
) (reg_names
+ i
));
19005 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
19007 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
19008 (PTR
) (barrier_opt_names
+ i
));
19010 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
19011 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (PTR
) (reloc_names
+ i
));
19014 set_constant_flonums ();
19016 /* Set the cpu variant based on the command-line options. We prefer
19017 -mcpu= over -march= if both are set (as for GCC); and we prefer
19018 -mfpu= over any other way of setting the floating point unit.
19019 Use of legacy options with new options are faulted. */
19022 if (mcpu_cpu_opt
|| march_cpu_opt
)
19023 as_bad (_("use of old and new-style options to set CPU type"));
19025 mcpu_cpu_opt
= legacy_cpu
;
19027 else if (!mcpu_cpu_opt
)
19028 mcpu_cpu_opt
= march_cpu_opt
;
19033 as_bad (_("use of old and new-style options to set FPU type"));
19035 mfpu_opt
= legacy_fpu
;
19037 else if (!mfpu_opt
)
19039 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
19040 /* Some environments specify a default FPU. If they don't, infer it
19041 from the processor. */
19043 mfpu_opt
= mcpu_fpu_opt
;
19045 mfpu_opt
= march_fpu_opt
;
19047 mfpu_opt
= &fpu_default
;
19054 mfpu_opt
= &fpu_default
;
19055 else if (ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
19056 mfpu_opt
= &fpu_arch_vfp_v2
;
19058 mfpu_opt
= &fpu_arch_fpa
;
19064 mcpu_cpu_opt
= &cpu_default
;
19065 selected_cpu
= cpu_default
;
19069 selected_cpu
= *mcpu_cpu_opt
;
19071 mcpu_cpu_opt
= &arm_arch_any
;
19074 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
19076 autoselect_thumb_from_cpu_variant ();
19078 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
19080 #if defined OBJ_COFF || defined OBJ_ELF
19082 unsigned int flags
= 0;
19084 #if defined OBJ_ELF
19085 flags
= meabi_flags
;
19087 switch (meabi_flags
)
19089 case EF_ARM_EABI_UNKNOWN
:
19091 /* Set the flags in the private structure. */
19092 if (uses_apcs_26
) flags
|= F_APCS26
;
19093 if (support_interwork
) flags
|= F_INTERWORK
;
19094 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
19095 if (pic_code
) flags
|= F_PIC
;
19096 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
19097 flags
|= F_SOFT_FLOAT
;
19099 switch (mfloat_abi_opt
)
19101 case ARM_FLOAT_ABI_SOFT
:
19102 case ARM_FLOAT_ABI_SOFTFP
:
19103 flags
|= F_SOFT_FLOAT
;
19106 case ARM_FLOAT_ABI_HARD
:
19107 if (flags
& F_SOFT_FLOAT
)
19108 as_bad (_("hard-float conflicts with specified fpu"));
19112 /* Using pure-endian doubles (even if soft-float). */
19113 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
19114 flags
|= F_VFP_FLOAT
;
19116 #if defined OBJ_ELF
19117 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
19118 flags
|= EF_ARM_MAVERICK_FLOAT
;
19121 case EF_ARM_EABI_VER4
:
19122 case EF_ARM_EABI_VER5
:
19123 /* No additional flags to set. */
19130 bfd_set_private_flags (stdoutput
, flags
);
19132 /* We have run out flags in the COFF header to encode the
19133 status of ATPCS support, so instead we create a dummy,
19134 empty, debug section called .arm.atpcs. */
19139 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
19143 bfd_set_section_flags
19144 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
19145 bfd_set_section_size (stdoutput
, sec
, 0);
19146 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
19152 /* Record the CPU type as well. */
19153 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
19154 mach
= bfd_mach_arm_iWMMXt
;
19155 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
19156 mach
= bfd_mach_arm_XScale
;
19157 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
19158 mach
= bfd_mach_arm_ep9312
;
19159 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
19160 mach
= bfd_mach_arm_5TE
;
19161 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
19163 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19164 mach
= bfd_mach_arm_5T
;
19166 mach
= bfd_mach_arm_5
;
19168 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
19170 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
19171 mach
= bfd_mach_arm_4T
;
19173 mach
= bfd_mach_arm_4
;
19175 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
19176 mach
= bfd_mach_arm_3M
;
19177 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
19178 mach
= bfd_mach_arm_3
;
19179 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
19180 mach
= bfd_mach_arm_2a
;
19181 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
19182 mach
= bfd_mach_arm_2
;
19184 mach
= bfd_mach_arm_unknown
;
19186 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
19189 /* Command line processing. */
19192 Invocation line includes a switch not recognized by the base assembler.
19193 See if it's a processor-specific option.
19195 This routine is somewhat complicated by the need for backwards
19196 compatibility (since older releases of gcc can't be changed).
19197 The new options try to make the interface as compatible as
19200 New options (supported) are:
19202 -mcpu=<cpu name> Assemble for selected processor
19203 -march=<architecture name> Assemble for selected architecture
19204 -mfpu=<fpu architecture> Assemble for selected FPU.
19205 -EB/-mbig-endian Big-endian
19206 -EL/-mlittle-endian Little-endian
19207 -k Generate PIC code
19208 -mthumb Start in Thumb mode
19209 -mthumb-interwork Code supports ARM/Thumb interworking
19211 For now we will also provide support for:
19213 -mapcs-32 32-bit Program counter
19214 -mapcs-26 26-bit Program counter
19215 -macps-float Floats passed in FP registers
19216 -mapcs-reentrant Reentrant code
19218 (sometime these will probably be replaced with -mapcs=<list of options>
19219 and -matpcs=<list of options>)
19221 The remaining options are only supported for back-wards compatibility.
19222 Cpu variants, the arm part is optional:
19223 -m[arm]1 Currently not supported.
19224 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
19225 -m[arm]3 Arm 3 processor
19226 -m[arm]6[xx], Arm 6 processors
19227 -m[arm]7[xx][t][[d]m] Arm 7 processors
19228 -m[arm]8[10] Arm 8 processors
19229 -m[arm]9[20][tdmi] Arm 9 processors
19230 -mstrongarm[110[0]] StrongARM processors
19231 -mxscale XScale processors
19232 -m[arm]v[2345[t[e]]] Arm architectures
19233 -mall All (except the ARM1)
19235 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
19236 -mfpe-old (No float load/store multiples)
19237 -mvfpxd VFP Single precision
19239 -mno-fpu Disable all floating point instructions
19241 The following CPU names are recognized:
19242 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
19243 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
19244 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
19245 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
19246 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
19247 arm10t arm10e, arm1020t, arm1020e, arm10200e,
19248 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
19252 const char * md_shortopts
= "m:k";
19254 #ifdef ARM_BI_ENDIAN
19255 #define OPTION_EB (OPTION_MD_BASE + 0)
19256 #define OPTION_EL (OPTION_MD_BASE + 1)
19258 #if TARGET_BYTES_BIG_ENDIAN
19259 #define OPTION_EB (OPTION_MD_BASE + 0)
19261 #define OPTION_EL (OPTION_MD_BASE + 1)
19265 struct option md_longopts
[] =
19268 {"EB", no_argument
, NULL
, OPTION_EB
},
19271 {"EL", no_argument
, NULL
, OPTION_EL
},
19273 {NULL
, no_argument
, NULL
, 0}
19276 size_t md_longopts_size
= sizeof (md_longopts
);
19278 struct arm_option_table
19280 char *option
; /* Option name to match. */
19281 char *help
; /* Help information. */
19282 int *var
; /* Variable to change. */
19283 int value
; /* What to change it to. */
19284 char *deprecated
; /* If non-null, print this message. */
19287 struct arm_option_table arm_opts
[] =
19289 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
19290 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
19291 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
19292 &support_interwork
, 1, NULL
},
19293 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
19294 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
19295 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
19297 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
19298 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
19299 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
19300 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
19303 /* These are recognized by the assembler, but have no affect on code. */
19304 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
19305 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
19306 {NULL
, NULL
, NULL
, 0, NULL
}
19309 struct arm_legacy_option_table
19311 char *option
; /* Option name to match. */
19312 const arm_feature_set
**var
; /* Variable to change. */
19313 const arm_feature_set value
; /* What to change it to. */
19314 char *deprecated
; /* If non-null, print this message. */
19317 const struct arm_legacy_option_table arm_legacy_opts
[] =
19319 /* DON'T add any new processors to this list -- we want the whole list
19320 to go away... Add them to the processors table instead. */
19321 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19322 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
19323 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19324 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
19325 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19326 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
19327 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19328 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
19329 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19330 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
19331 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19332 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
19333 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19334 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
19335 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19336 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
19337 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19338 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
19339 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19340 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
19341 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19342 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
19343 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19344 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
19345 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19346 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
19347 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19348 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
19349 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19350 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
19351 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19352 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
19353 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19354 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
19355 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19356 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
19357 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19358 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
19359 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19360 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
19361 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19362 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
19363 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19364 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
19365 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19366 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
19367 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19368 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19369 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19370 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
19371 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19372 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
19373 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19374 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
19375 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19376 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
19377 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19378 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
19379 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19380 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
19381 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19382 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
19383 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19384 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
19385 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19386 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
19387 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19388 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
19389 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
19390 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
19391 N_("use -mcpu=strongarm110")},
19392 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
19393 N_("use -mcpu=strongarm1100")},
19394 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
19395 N_("use -mcpu=strongarm1110")},
19396 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
19397 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
19398 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
19400 /* Architecture variants -- don't add any more to this list either. */
19401 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19402 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
19403 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19404 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
19405 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19406 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
19407 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19408 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
19409 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19410 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
19411 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19412 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
19413 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19414 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
19415 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19416 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
19417 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19418 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
19420 /* Floating point variants -- don't add any more to this list either. */
19421 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
19422 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
19423 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
19424 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
19425 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
19427 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
19430 struct arm_cpu_option_table
19433 const arm_feature_set value
;
19434 /* For some CPUs we assume an FPU unless the user explicitly sets
19436 const arm_feature_set default_fpu
;
19437 /* The canonical name of the CPU, or NULL to use NAME converted to upper
19439 const char *canonical_name
;
19442 /* This list should, at a minimum, contain all the cpu names
19443 recognized by GCC. */
19444 static const struct arm_cpu_option_table arm_cpus
[] =
19446 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
19447 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
19448 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
19449 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19450 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
19451 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19452 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19453 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19454 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19455 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19456 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19457 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19458 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19459 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19460 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19461 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
19462 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19463 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19464 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19465 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19466 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19467 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19468 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19469 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19470 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19471 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19472 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19473 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
19474 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19475 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19476 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19477 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19478 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19479 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19480 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19481 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19482 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19483 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
19484 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19485 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
19486 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19487 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19488 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19489 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
19490 /* For V5 or later processors we default to using VFP; but the user
19491 should really set the FPU type explicitly. */
19492 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19493 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19494 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19495 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
19496 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19497 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19498 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
19499 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19500 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
19501 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
19502 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19503 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19504 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19505 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19506 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19507 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
19508 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
19509 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19510 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
19511 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
19512 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
19513 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
19514 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
19515 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
19516 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
19517 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
19518 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
19519 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
19520 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
19521 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
19522 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
19523 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
19524 | FPU_NEON_EXT_V1
),
19526 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
19527 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
19528 /* ??? XSCALE is really an architecture. */
19529 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19530 /* ??? iwmmxt is not a processor. */
19531 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
19532 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
19534 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
19535 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
19538 struct arm_arch_option_table
19541 const arm_feature_set value
;
19542 const arm_feature_set default_fpu
;
19545 /* This list should, at a minimum, contain all the architecture names
19546 recognized by GCC. */
19547 static const struct arm_arch_option_table arm_archs
[] =
19549 {"all", ARM_ANY
, FPU_ARCH_FPA
},
19550 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
19551 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
19552 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19553 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
19554 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
19555 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
19556 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
19557 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
19558 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
19559 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
19560 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
19561 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
19562 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
19563 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
19564 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
19565 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
19566 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19567 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
19568 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
19569 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
19570 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
19571 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
19572 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
19573 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
19574 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
19575 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
19576 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
19577 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
19578 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
19579 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
19580 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
19581 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
19584 /* ISA extensions in the co-processor space. */
19585 struct arm_option_cpu_value_table
19588 const arm_feature_set value
;
19591 static const struct arm_option_cpu_value_table arm_extensions
[] =
19593 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
19594 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
19595 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
19596 {NULL
, ARM_ARCH_NONE
}
19599 /* This list should, at a minimum, contain all the fpu names
19600 recognized by GCC. */
19601 static const struct arm_option_cpu_value_table arm_fpus
[] =
19603 {"softfpa", FPU_NONE
},
19604 {"fpe", FPU_ARCH_FPE
},
19605 {"fpe2", FPU_ARCH_FPE
},
19606 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
19607 {"fpa", FPU_ARCH_FPA
},
19608 {"fpa10", FPU_ARCH_FPA
},
19609 {"fpa11", FPU_ARCH_FPA
},
19610 {"arm7500fe", FPU_ARCH_FPA
},
19611 {"softvfp", FPU_ARCH_VFP
},
19612 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
19613 {"vfp", FPU_ARCH_VFP_V2
},
19614 {"vfp9", FPU_ARCH_VFP_V2
},
19615 {"vfp3", FPU_ARCH_VFP_V3
},
19616 {"vfp10", FPU_ARCH_VFP_V2
},
19617 {"vfp10-r0", FPU_ARCH_VFP_V1
},
19618 {"vfpxd", FPU_ARCH_VFP_V1xD
},
19619 {"arm1020t", FPU_ARCH_VFP_V1
},
19620 {"arm1020e", FPU_ARCH_VFP_V2
},
19621 {"arm1136jfs", FPU_ARCH_VFP_V2
},
19622 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
19623 {"maverick", FPU_ARCH_MAVERICK
},
19624 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
19625 {NULL
, ARM_ARCH_NONE
}
19628 struct arm_option_value_table
19634 static const struct arm_option_value_table arm_float_abis
[] =
19636 {"hard", ARM_FLOAT_ABI_HARD
},
19637 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
19638 {"soft", ARM_FLOAT_ABI_SOFT
},
19643 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
19644 static const struct arm_option_value_table arm_eabis
[] =
19646 {"gnu", EF_ARM_EABI_UNKNOWN
},
19647 {"4", EF_ARM_EABI_VER4
},
19648 {"5", EF_ARM_EABI_VER5
},
19653 struct arm_long_option_table
19655 char * option
; /* Substring to match. */
19656 char * help
; /* Help information. */
19657 int (* func
) (char * subopt
); /* Function to decode sub-option. */
19658 char * deprecated
; /* If non-null, print this message. */
19662 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
19664 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
19666 /* Copy the feature set, so that we can modify it. */
19667 *ext_set
= **opt_p
;
19670 while (str
!= NULL
&& *str
!= 0)
19672 const struct arm_option_cpu_value_table
* opt
;
19678 as_bad (_("invalid architectural extension"));
19683 ext
= strchr (str
, '+');
19686 optlen
= ext
- str
;
19688 optlen
= strlen (str
);
19692 as_bad (_("missing architectural extension"));
19696 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
19697 if (strncmp (opt
->name
, str
, optlen
) == 0)
19699 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
19703 if (opt
->name
== NULL
)
19705 as_bad (_("unknown architectural extnsion `%s'"), str
);
19716 arm_parse_cpu (char * str
)
19718 const struct arm_cpu_option_table
* opt
;
19719 char * ext
= strchr (str
, '+');
19723 optlen
= ext
- str
;
19725 optlen
= strlen (str
);
19729 as_bad (_("missing cpu name `%s'"), str
);
19733 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
19734 if (strncmp (opt
->name
, str
, optlen
) == 0)
19736 mcpu_cpu_opt
= &opt
->value
;
19737 mcpu_fpu_opt
= &opt
->default_fpu
;
19738 if (opt
->canonical_name
)
19739 strcpy(selected_cpu_name
, opt
->canonical_name
);
19743 for (i
= 0; i
< optlen
; i
++)
19744 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
19745 selected_cpu_name
[i
] = 0;
19749 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
19754 as_bad (_("unknown cpu `%s'"), str
);
19759 arm_parse_arch (char * str
)
19761 const struct arm_arch_option_table
*opt
;
19762 char *ext
= strchr (str
, '+');
19766 optlen
= ext
- str
;
19768 optlen
= strlen (str
);
19772 as_bad (_("missing architecture name `%s'"), str
);
19776 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
19777 if (streq (opt
->name
, str
))
19779 march_cpu_opt
= &opt
->value
;
19780 march_fpu_opt
= &opt
->default_fpu
;
19781 strcpy(selected_cpu_name
, opt
->name
);
19784 return arm_parse_extension (ext
, &march_cpu_opt
);
19789 as_bad (_("unknown architecture `%s'\n"), str
);
19794 arm_parse_fpu (char * str
)
19796 const struct arm_option_cpu_value_table
* opt
;
19798 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
19799 if (streq (opt
->name
, str
))
19801 mfpu_opt
= &opt
->value
;
19805 as_bad (_("unknown floating point format `%s'\n"), str
);
19810 arm_parse_float_abi (char * str
)
19812 const struct arm_option_value_table
* opt
;
19814 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
19815 if (streq (opt
->name
, str
))
19817 mfloat_abi_opt
= opt
->value
;
19821 as_bad (_("unknown floating point abi `%s'\n"), str
);
19827 arm_parse_eabi (char * str
)
19829 const struct arm_option_value_table
*opt
;
19831 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
19832 if (streq (opt
->name
, str
))
19834 meabi_flags
= opt
->value
;
19837 as_bad (_("unknown EABI `%s'\n"), str
);
19842 struct arm_long_option_table arm_long_opts
[] =
19844 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
19845 arm_parse_cpu
, NULL
},
19846 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
19847 arm_parse_arch
, NULL
},
19848 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
19849 arm_parse_fpu
, NULL
},
19850 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
19851 arm_parse_float_abi
, NULL
},
19853 {"meabi=", N_("<ver>\t assemble for eabi version <ver>"),
19854 arm_parse_eabi
, NULL
},
19856 {NULL
, NULL
, 0, NULL
}
19860 md_parse_option (int c
, char * arg
)
19862 struct arm_option_table
*opt
;
19863 const struct arm_legacy_option_table
*fopt
;
19864 struct arm_long_option_table
*lopt
;
19870 target_big_endian
= 1;
19876 target_big_endian
= 0;
19881 /* Listing option. Just ignore these, we don't support additional
19886 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19888 if (c
== opt
->option
[0]
19889 && ((arg
== NULL
&& opt
->option
[1] == 0)
19890 || streq (arg
, opt
->option
+ 1)))
19892 #if WARN_DEPRECATED
19893 /* If the option is deprecated, tell the user. */
19894 if (opt
->deprecated
!= NULL
)
19895 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19896 arg
? arg
: "", _(opt
->deprecated
));
19899 if (opt
->var
!= NULL
)
19900 *opt
->var
= opt
->value
;
19906 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
19908 if (c
== fopt
->option
[0]
19909 && ((arg
== NULL
&& fopt
->option
[1] == 0)
19910 || streq (arg
, fopt
->option
+ 1)))
19912 #if WARN_DEPRECATED
19913 /* If the option is deprecated, tell the user. */
19914 if (fopt
->deprecated
!= NULL
)
19915 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
19916 arg
? arg
: "", _(fopt
->deprecated
));
19919 if (fopt
->var
!= NULL
)
19920 *fopt
->var
= &fopt
->value
;
19926 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19928 /* These options are expected to have an argument. */
19929 if (c
== lopt
->option
[0]
19931 && strncmp (arg
, lopt
->option
+ 1,
19932 strlen (lopt
->option
+ 1)) == 0)
19934 #if WARN_DEPRECATED
19935 /* If the option is deprecated, tell the user. */
19936 if (lopt
->deprecated
!= NULL
)
19937 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
19938 _(lopt
->deprecated
));
19941 /* Call the sup-option parser. */
19942 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
19953 md_show_usage (FILE * fp
)
19955 struct arm_option_table
*opt
;
19956 struct arm_long_option_table
*lopt
;
19958 fprintf (fp
, _(" ARM-specific assembler options:\n"));
19960 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
19961 if (opt
->help
!= NULL
)
19962 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
19964 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
19965 if (lopt
->help
!= NULL
)
19966 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
19970 -EB assemble code for a big-endian cpu\n"));
19975 -EL assemble code for a little-endian cpu\n"));
19984 arm_feature_set flags
;
19985 } cpu_arch_ver_table
;
19987 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
19988 least features first. */
19989 static const cpu_arch_ver_table cpu_arch_ver
[] =
19994 {4, ARM_ARCH_V5TE
},
19995 {5, ARM_ARCH_V5TEJ
},
19999 {9, ARM_ARCH_V6T2
},
20000 {10, ARM_ARCH_V7A
},
20001 {10, ARM_ARCH_V7R
},
20002 {10, ARM_ARCH_V7M
},
20006 /* Set the public EABI object attributes. */
20008 aeabi_set_public_attributes (void)
20011 arm_feature_set flags
;
20012 arm_feature_set tmp
;
20013 const cpu_arch_ver_table
*p
;
20015 /* Choose the architecture based on the capabilities of the requested cpu
20016 (if any) and/or the instructions actually used. */
20017 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
20018 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
20019 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
20023 for (p
= cpu_arch_ver
; p
->val
; p
++)
20025 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
20028 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
20032 /* Tag_CPU_name. */
20033 if (selected_cpu_name
[0])
20037 p
= selected_cpu_name
;
20038 if (strncmp(p
, "armv", 4) == 0)
20043 for (i
= 0; p
[i
]; i
++)
20044 p
[i
] = TOUPPER (p
[i
]);
20046 elf32_arm_add_eabi_attr_string (stdoutput
, 5, p
);
20048 /* Tag_CPU_arch. */
20049 elf32_arm_add_eabi_attr_int (stdoutput
, 6, arch
);
20050 /* Tag_CPU_arch_profile. */
20051 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
20052 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'A');
20053 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
20054 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'R');
20055 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
))
20056 elf32_arm_add_eabi_attr_int (stdoutput
, 7, 'M');
20057 /* Tag_ARM_ISA_use. */
20058 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_full
))
20059 elf32_arm_add_eabi_attr_int (stdoutput
, 8, 1);
20060 /* Tag_THUMB_ISA_use. */
20061 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_full
))
20062 elf32_arm_add_eabi_attr_int (stdoutput
, 9,
20063 ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
) ? 2 : 1);
20064 /* Tag_VFP_arch. */
20065 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v3
)
20066 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v3
))
20067 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 3);
20068 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v2
)
20069 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v2
))
20070 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 2);
20071 else if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1
)
20072 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1
)
20073 || ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_vfp_ext_v1xd
)
20074 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_vfp_ext_v1xd
))
20075 elf32_arm_add_eabi_attr_int (stdoutput
, 10, 1);
20076 /* Tag_WMMX_arch. */
20077 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_cext_iwmmxt
)
20078 || ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_cext_iwmmxt
))
20079 elf32_arm_add_eabi_attr_int (stdoutput
, 11, 1);
20080 /* Tag_NEON_arch. */
20081 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, fpu_neon_ext_v1
)
20082 || ARM_CPU_HAS_FEATURE (arm_arch_used
, fpu_neon_ext_v1
))
20083 elf32_arm_add_eabi_attr_int (stdoutput
, 12, 1);
20086 /* Add the .ARM.attributes section. */
20095 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20098 aeabi_set_public_attributes ();
20099 size
= elf32_arm_eabi_attr_size (stdoutput
);
20100 s
= subseg_new (".ARM.attributes", 0);
20101 bfd_set_section_flags (stdoutput
, s
, SEC_READONLY
| SEC_DATA
);
20102 addr
= frag_now_fix ();
20103 p
= frag_more (size
);
20104 elf32_arm_set_eabi_attr_contents (stdoutput
, (bfd_byte
*)p
, size
);
20106 #endif /* OBJ_ELF */
20109 /* Parse a .cpu directive. */
20112 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
20114 const struct arm_cpu_option_table
*opt
;
20118 name
= input_line_pointer
;
20119 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20120 input_line_pointer
++;
20121 saved_char
= *input_line_pointer
;
20122 *input_line_pointer
= 0;
20124 /* Skip the first "all" entry. */
20125 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
20126 if (streq (opt
->name
, name
))
20128 mcpu_cpu_opt
= &opt
->value
;
20129 selected_cpu
= opt
->value
;
20130 if (opt
->canonical_name
)
20131 strcpy(selected_cpu_name
, opt
->canonical_name
);
20135 for (i
= 0; opt
->name
[i
]; i
++)
20136 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20137 selected_cpu_name
[i
] = 0;
20139 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20140 *input_line_pointer
= saved_char
;
20141 demand_empty_rest_of_line ();
20144 as_bad (_("unknown cpu `%s'"), name
);
20145 *input_line_pointer
= saved_char
;
20146 ignore_rest_of_line ();
20150 /* Parse a .arch directive. */
20153 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
20155 const struct arm_arch_option_table
*opt
;
20159 name
= input_line_pointer
;
20160 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20161 input_line_pointer
++;
20162 saved_char
= *input_line_pointer
;
20163 *input_line_pointer
= 0;
20165 /* Skip the first "all" entry. */
20166 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
20167 if (streq (opt
->name
, name
))
20169 mcpu_cpu_opt
= &opt
->value
;
20170 selected_cpu
= opt
->value
;
20171 strcpy(selected_cpu_name
, opt
->name
);
20172 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20173 *input_line_pointer
= saved_char
;
20174 demand_empty_rest_of_line ();
20178 as_bad (_("unknown architecture `%s'\n"), name
);
20179 *input_line_pointer
= saved_char
;
20180 ignore_rest_of_line ();
20184 /* Parse a .fpu directive. */
20187 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
20189 const struct arm_option_cpu_value_table
*opt
;
20193 name
= input_line_pointer
;
20194 while (*input_line_pointer
&& !ISSPACE(*input_line_pointer
))
20195 input_line_pointer
++;
20196 saved_char
= *input_line_pointer
;
20197 *input_line_pointer
= 0;
20199 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
20200 if (streq (opt
->name
, name
))
20202 mfpu_opt
= &opt
->value
;
20203 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20204 *input_line_pointer
= saved_char
;
20205 demand_empty_rest_of_line ();
20209 as_bad (_("unknown floating point format `%s'\n"), name
);
20210 *input_line_pointer
= saved_char
;
20211 ignore_rest_of_line ();