1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
80 /* Bit N indicates that an R_ARM_NONE relocation has been output for
81 __aeabi_unwind_cpp_prN already if set. This enables dependencies to be
82 emitted only once per section, to save unnecessary bloat. */
83 static unsigned int marked_pr_dependency
= 0;
87 /* Results from operand parsing worker functions. */
91 PARSE_OPERAND_SUCCESS
,
93 PARSE_OPERAND_FAIL_NO_BACKTRACK
94 } parse_operand_result
;
103 /* Types of processor to assemble for. */
105 #if defined __XSCALE__
106 #define CPU_DEFAULT ARM_ARCH_XSCALE
108 #if defined __thumb__
109 #define CPU_DEFAULT ARM_ARCH_V5T
116 # define FPU_DEFAULT FPU_ARCH_FPA
117 # elif defined (TE_NetBSD)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
121 /* Legacy a.out format. */
122 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
124 # elif defined (TE_VXWORKS)
125 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
127 /* For backwards compatibility, default to FPA. */
128 # define FPU_DEFAULT FPU_ARCH_FPA
130 #endif /* ifndef FPU_DEFAULT */
132 #define streq(a, b) (strcmp (a, b) == 0)
134 static arm_feature_set cpu_variant
;
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
149 /* Variables that we set while parsing command-line options. Once all
150 options have been read we re-process these values to set the real
152 static const arm_feature_set
*legacy_cpu
= NULL
;
153 static const arm_feature_set
*legacy_fpu
= NULL
;
155 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
156 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
157 static const arm_feature_set
*march_cpu_opt
= NULL
;
158 static const arm_feature_set
*march_fpu_opt
= NULL
;
159 static const arm_feature_set
*mfpu_opt
= NULL
;
160 static const arm_feature_set
*object_arch
= NULL
;
162 /* Constants for known architecture features. */
163 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
164 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
165 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
166 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
167 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
168 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
169 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
170 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
171 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
174 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
177 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
178 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
179 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
180 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
181 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
182 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
183 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
184 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
185 static const arm_feature_set arm_ext_v4t_5
=
186 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
187 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
188 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
189 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
190 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
191 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
192 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
193 static const arm_feature_set arm_ext_v6z
= ARM_FEATURE (ARM_EXT_V6Z
, 0);
194 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
195 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
196 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
197 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
198 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
199 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
200 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
201 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
202 static const arm_feature_set arm_ext_m
=
203 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_V7M
, 0);
205 static const arm_feature_set arm_arch_any
= ARM_ANY
;
206 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
207 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
208 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_cext_iwmmxt2
=
211 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
212 static const arm_feature_set arm_cext_iwmmxt
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
214 static const arm_feature_set arm_cext_xscale
=
215 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
216 static const arm_feature_set arm_cext_maverick
=
217 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
218 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
219 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
220 static const arm_feature_set fpu_vfp_ext_v1xd
=
221 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
222 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
223 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
224 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
225 static const arm_feature_set fpu_vfp_ext_d32
=
226 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
227 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
228 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
229 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
230 static const arm_feature_set fpu_neon_fp16
= ARM_FEATURE (0, FPU_NEON_FP16
);
232 static int mfloat_abi_opt
= -1;
233 /* Record user cpu selection for object attributes. */
234 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
235 /* Must be long enough to hold any of the names in arm_cpus. */
236 static char selected_cpu_name
[16];
239 static int meabi_flags
= EABI_DEFAULT
;
241 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
244 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
249 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
254 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
255 symbolS
* GOT_symbol
;
258 /* 0: assemble for ARM,
259 1: assemble for Thumb,
260 2: assemble for Thumb even though target CPU does not support thumb
262 static int thumb_mode
= 0;
263 /* A value distinct from the possible values for thumb_mode that we
264 can use to record whether thumb_mode has been copied into the
265 tc_frag_data field of a frag. */
266 #define MODE_RECORDED (1 << 4)
268 /* If unified_syntax is true, we are processing the new unified
269 ARM/Thumb syntax. Important differences from the old ARM mode:
271 - Immediate operands do not require a # prefix.
272 - Conditional affixes always appear at the end of the
273 instruction. (For backward compatibility, those instructions
274 that formerly had them in the middle, continue to accept them
276 - The IT instruction may appear, and if it does is validated
277 against subsequent conditional affixes. It does not generate
280 Important differences from the old Thumb mode:
282 - Immediate operands do not require a # prefix.
283 - Most of the V6T2 instructions are only available in unified mode.
284 - The .N and .W suffixes are recognized and honored (it is an error
285 if they cannot be honored).
286 - All instructions set the flags if and only if they have an 's' affix.
287 - Conditional affixes may be used. They are validated against
288 preceding IT instructions. Unlike ARM mode, you cannot use a
289 conditional affix except in the scope of an IT instruction. */
291 static bfd_boolean unified_syntax
= FALSE
;
306 enum neon_el_type type
;
310 #define NEON_MAX_TYPE_ELS 4
314 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
321 unsigned long instruction
;
325 /* "uncond_value" is set to the value in place of the conditional field in
326 unconditional versions of the instruction, or -1 if nothing is
329 struct neon_type vectype
;
330 /* Set to the opcode if the instruction needs relaxation.
331 Zero if the instruction is not relaxed. */
335 bfd_reloc_code_real_type type
;
344 struct neon_type_el vectype
;
345 unsigned present
: 1; /* Operand present. */
346 unsigned isreg
: 1; /* Operand was a register. */
347 unsigned immisreg
: 1; /* .imm field is a second register. */
348 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
349 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
350 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
351 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
352 instructions. This allows us to disambiguate ARM <-> vector insns. */
353 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
354 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
355 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
356 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
357 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
358 unsigned writeback
: 1; /* Operand has trailing ! */
359 unsigned preind
: 1; /* Preindexed address. */
360 unsigned postind
: 1; /* Postindexed address. */
361 unsigned negative
: 1; /* Index register was negated. */
362 unsigned shifted
: 1; /* Shift applied to operation. */
363 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
367 static struct arm_it inst
;
369 #define NUM_FLOAT_VALS 8
371 const char * fp_const
[] =
373 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
376 /* Number of littlenums required to hold an extended precision number. */
377 #define MAX_LITTLENUMS 6
379 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
389 #define CP_T_X 0x00008000
390 #define CP_T_Y 0x00400000
392 #define CONDS_BIT 0x00100000
393 #define LOAD_BIT 0x00100000
395 #define DOUBLE_LOAD_FLAG 0x00000001
399 const char * template;
403 #define COND_ALWAYS 0xE
407 const char *template;
411 struct asm_barrier_opt
413 const char *template;
417 /* The bit that distinguishes CPSR and SPSR. */
418 #define SPSR_BIT (1 << 22)
420 /* The individual PSR flag bits. */
421 #define PSR_c (1 << 16)
422 #define PSR_x (1 << 17)
423 #define PSR_s (1 << 18)
424 #define PSR_f (1 << 19)
429 bfd_reloc_code_real_type reloc
;
434 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
435 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
440 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
443 /* Bits for DEFINED field in neon_typed_alias. */
444 #define NTA_HASTYPE 1
445 #define NTA_HASINDEX 2
447 struct neon_typed_alias
449 unsigned char defined
;
451 struct neon_type_el eltype
;
454 /* ARM register categories. This includes coprocessor numbers and various
455 architecture extensions' registers. */
481 /* Structure for a hash table entry for a register.
482 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
483 information which states whether a vector type or index is specified (for a
484 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
488 unsigned char number
;
490 unsigned char builtin
;
491 struct neon_typed_alias
*neon
;
494 /* Diagnostics used when we don't get a register of the expected type. */
495 const char *const reg_expected_msgs
[] =
497 N_("ARM register expected"),
498 N_("bad or missing co-processor number"),
499 N_("co-processor register expected"),
500 N_("FPA register expected"),
501 N_("VFP single precision register expected"),
502 N_("VFP/Neon double precision register expected"),
503 N_("Neon quad precision register expected"),
504 N_("VFP single or double precision register expected"),
505 N_("Neon double or quad precision register expected"),
506 N_("VFP single, double or Neon quad precision register expected"),
507 N_("VFP system register expected"),
508 N_("Maverick MVF register expected"),
509 N_("Maverick MVD register expected"),
510 N_("Maverick MVFX register expected"),
511 N_("Maverick MVDX register expected"),
512 N_("Maverick MVAX register expected"),
513 N_("Maverick DSPSC register expected"),
514 N_("iWMMXt data register expected"),
515 N_("iWMMXt control register expected"),
516 N_("iWMMXt scalar register expected"),
517 N_("XScale accumulator register expected"),
520 /* Some well known registers that we refer to directly elsewhere. */
525 /* ARM instructions take 4bytes in the object file, Thumb instructions
531 /* Basic string to match. */
532 const char *template;
534 /* Parameters to instruction. */
535 unsigned char operands
[8];
537 /* Conditional tag - see opcode_lookup. */
538 unsigned int tag
: 4;
540 /* Basic instruction code. */
541 unsigned int avalue
: 28;
543 /* Thumb-format instruction code. */
546 /* Which architecture variant provides this instruction. */
547 const arm_feature_set
*avariant
;
548 const arm_feature_set
*tvariant
;
550 /* Function to call to encode instruction in ARM format. */
551 void (* aencode
) (void);
553 /* Function to call to encode instruction in Thumb format. */
554 void (* tencode
) (void);
557 /* Defines for various bits that we will want to toggle. */
558 #define INST_IMMEDIATE 0x02000000
559 #define OFFSET_REG 0x02000000
560 #define HWOFFSET_IMM 0x00400000
561 #define SHIFT_BY_REG 0x00000010
562 #define PRE_INDEX 0x01000000
563 #define INDEX_UP 0x00800000
564 #define WRITE_BACK 0x00200000
565 #define LDM_TYPE_2_OR_3 0x00400000
566 #define CPSI_MMOD 0x00020000
568 #define LITERAL_MASK 0xf000f000
569 #define OPCODE_MASK 0xfe1fffff
570 #define V4_STR_BIT 0x00000020
572 #define T2_SUBS_PC_LR 0xf3de8f00
574 #define DATA_OP_SHIFT 21
576 #define T2_OPCODE_MASK 0xfe1fffff
577 #define T2_DATA_OP_SHIFT 21
579 /* Codes to distinguish the arithmetic instructions. */
590 #define OPCODE_CMP 10
591 #define OPCODE_CMN 11
592 #define OPCODE_ORR 12
593 #define OPCODE_MOV 13
594 #define OPCODE_BIC 14
595 #define OPCODE_MVN 15
597 #define T2_OPCODE_AND 0
598 #define T2_OPCODE_BIC 1
599 #define T2_OPCODE_ORR 2
600 #define T2_OPCODE_ORN 3
601 #define T2_OPCODE_EOR 4
602 #define T2_OPCODE_ADD 8
603 #define T2_OPCODE_ADC 10
604 #define T2_OPCODE_SBC 11
605 #define T2_OPCODE_SUB 13
606 #define T2_OPCODE_RSB 14
608 #define T_OPCODE_MUL 0x4340
609 #define T_OPCODE_TST 0x4200
610 #define T_OPCODE_CMN 0x42c0
611 #define T_OPCODE_NEG 0x4240
612 #define T_OPCODE_MVN 0x43c0
614 #define T_OPCODE_ADD_R3 0x1800
615 #define T_OPCODE_SUB_R3 0x1a00
616 #define T_OPCODE_ADD_HI 0x4400
617 #define T_OPCODE_ADD_ST 0xb000
618 #define T_OPCODE_SUB_ST 0xb080
619 #define T_OPCODE_ADD_SP 0xa800
620 #define T_OPCODE_ADD_PC 0xa000
621 #define T_OPCODE_ADD_I8 0x3000
622 #define T_OPCODE_SUB_I8 0x3800
623 #define T_OPCODE_ADD_I3 0x1c00
624 #define T_OPCODE_SUB_I3 0x1e00
626 #define T_OPCODE_ASR_R 0x4100
627 #define T_OPCODE_LSL_R 0x4080
628 #define T_OPCODE_LSR_R 0x40c0
629 #define T_OPCODE_ROR_R 0x41c0
630 #define T_OPCODE_ASR_I 0x1000
631 #define T_OPCODE_LSL_I 0x0000
632 #define T_OPCODE_LSR_I 0x0800
634 #define T_OPCODE_MOV_I8 0x2000
635 #define T_OPCODE_CMP_I8 0x2800
636 #define T_OPCODE_CMP_LR 0x4280
637 #define T_OPCODE_MOV_HR 0x4600
638 #define T_OPCODE_CMP_HR 0x4500
640 #define T_OPCODE_LDR_PC 0x4800
641 #define T_OPCODE_LDR_SP 0x9800
642 #define T_OPCODE_STR_SP 0x9000
643 #define T_OPCODE_LDR_IW 0x6800
644 #define T_OPCODE_STR_IW 0x6000
645 #define T_OPCODE_LDR_IH 0x8800
646 #define T_OPCODE_STR_IH 0x8000
647 #define T_OPCODE_LDR_IB 0x7800
648 #define T_OPCODE_STR_IB 0x7000
649 #define T_OPCODE_LDR_RW 0x5800
650 #define T_OPCODE_STR_RW 0x5000
651 #define T_OPCODE_LDR_RH 0x5a00
652 #define T_OPCODE_STR_RH 0x5200
653 #define T_OPCODE_LDR_RB 0x5c00
654 #define T_OPCODE_STR_RB 0x5400
656 #define T_OPCODE_PUSH 0xb400
657 #define T_OPCODE_POP 0xbc00
659 #define T_OPCODE_BRANCH 0xe000
661 #define THUMB_SIZE 2 /* Size of thumb instruction. */
662 #define THUMB_PP_PC_LR 0x0100
663 #define THUMB_LOAD_BIT 0x0800
664 #define THUMB2_LOAD_BIT 0x00100000
666 #define BAD_ARGS _("bad arguments to instruction")
667 #define BAD_SP _("r13 not allowed here")
668 #define BAD_PC _("r15 not allowed here")
669 #define BAD_COND _("instruction cannot be conditional")
670 #define BAD_OVERLAP _("registers may not be the same")
671 #define BAD_HIREG _("lo register required")
672 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
673 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
674 #define BAD_BRANCH _("branch must be last instruction in IT block")
675 #define BAD_NOT_IT _("instruction not allowed in IT block")
676 #define BAD_FPU _("selected FPU does not support instruction")
678 static struct hash_control
*arm_ops_hsh
;
679 static struct hash_control
*arm_cond_hsh
;
680 static struct hash_control
*arm_shift_hsh
;
681 static struct hash_control
*arm_psr_hsh
;
682 static struct hash_control
*arm_v7m_psr_hsh
;
683 static struct hash_control
*arm_reg_hsh
;
684 static struct hash_control
*arm_reloc_hsh
;
685 static struct hash_control
*arm_barrier_opt_hsh
;
687 /* Stuff needed to resolve the label ambiguity
696 symbolS
* last_label_seen
;
697 static int label_is_thumb_function_name
= FALSE
;
699 /* Literal pool structure. Held on a per-section
700 and per-sub-section basis. */
702 #define MAX_LITERAL_POOL_SIZE 1024
703 typedef struct literal_pool
705 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
706 unsigned int next_free_entry
;
711 struct literal_pool
* next
;
714 /* Pointer to a linked list of literal pools. */
715 literal_pool
* list_of_pools
= NULL
;
717 /* State variables for IT block handling. */
718 static bfd_boolean current_it_mask
= 0;
719 static int current_cc
;
723 /* This array holds the chars that always start a comment. If the
724 pre-processor is disabled, these aren't very useful. */
725 const char comment_chars
[] = "@";
727 /* This array holds the chars that only start a comment at the beginning of
728 a line. If the line seems to have the form '# 123 filename'
729 .line and .file directives will appear in the pre-processed output. */
730 /* Note that input_file.c hand checks for '#' at the beginning of the
731 first line of the input file. This is because the compiler outputs
732 #NO_APP at the beginning of its output. */
733 /* Also note that comments like this one will always work. */
734 const char line_comment_chars
[] = "#";
736 const char line_separator_chars
[] = ";";
738 /* Chars that can be used to separate mant
739 from exp in floating point numbers. */
740 const char EXP_CHARS
[] = "eE";
742 /* Chars that mean this number is a floating point constant. */
746 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
748 /* Prefix characters that indicate the start of an immediate
750 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
752 /* Separator character handling. */
754 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
757 skip_past_char (char ** str
, char c
)
767 #define skip_past_comma(str) skip_past_char (str, ',')
769 /* Arithmetic expressions (possibly involving symbols). */
771 /* Return TRUE if anything in the expression is a bignum. */
774 walk_no_bignums (symbolS
* sp
)
776 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
779 if (symbol_get_value_expression (sp
)->X_add_symbol
)
781 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
782 || (symbol_get_value_expression (sp
)->X_op_symbol
783 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
789 static int in_my_get_expression
= 0;
791 /* Third argument to my_get_expression. */
792 #define GE_NO_PREFIX 0
793 #define GE_IMM_PREFIX 1
794 #define GE_OPT_PREFIX 2
795 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
796 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
797 #define GE_OPT_PREFIX_BIG 3
800 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
805 /* In unified syntax, all prefixes are optional. */
807 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
812 case GE_NO_PREFIX
: break;
814 if (!is_immediate_prefix (**str
))
816 inst
.error
= _("immediate expression requires a # prefix");
822 case GE_OPT_PREFIX_BIG
:
823 if (is_immediate_prefix (**str
))
829 memset (ep
, 0, sizeof (expressionS
));
831 save_in
= input_line_pointer
;
832 input_line_pointer
= *str
;
833 in_my_get_expression
= 1;
834 seg
= expression (ep
);
835 in_my_get_expression
= 0;
837 if (ep
->X_op
== O_illegal
)
839 /* We found a bad expression in md_operand(). */
840 *str
= input_line_pointer
;
841 input_line_pointer
= save_in
;
842 if (inst
.error
== NULL
)
843 inst
.error
= _("bad expression");
848 if (seg
!= absolute_section
849 && seg
!= text_section
850 && seg
!= data_section
851 && seg
!= bss_section
852 && seg
!= undefined_section
)
854 inst
.error
= _("bad segment");
855 *str
= input_line_pointer
;
856 input_line_pointer
= save_in
;
861 /* Get rid of any bignums now, so that we don't generate an error for which
862 we can't establish a line number later on. Big numbers are never valid
863 in instructions, which is where this routine is always called. */
864 if (prefix_mode
!= GE_OPT_PREFIX_BIG
865 && (ep
->X_op
== O_big
867 && (walk_no_bignums (ep
->X_add_symbol
)
869 && walk_no_bignums (ep
->X_op_symbol
))))))
871 inst
.error
= _("invalid constant");
872 *str
= input_line_pointer
;
873 input_line_pointer
= save_in
;
877 *str
= input_line_pointer
;
878 input_line_pointer
= save_in
;
882 /* Turn a string in input_line_pointer into a floating point constant
883 of type TYPE, and store the appropriate bytes in *LITP. The number
884 of LITTLENUMS emitted is stored in *SIZEP. An error message is
885 returned, or NULL on OK.
887 Note that fp constants aren't represent in the normal way on the ARM.
888 In big endian mode, things are as expected. However, in little endian
889 mode fp constants are big-endian word-wise, and little-endian byte-wise
890 within the words. For example, (double) 1.1 in big endian mode is
891 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
892 the byte sequence 99 99 f1 3f 9a 99 99 99.
894 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
897 md_atof (int type
, char * litP
, int * sizeP
)
900 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
932 return _("Unrecognized or unsupported floating point constant");
935 t
= atof_ieee (input_line_pointer
, type
, words
);
937 input_line_pointer
= t
;
938 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
940 if (target_big_endian
)
942 for (i
= 0; i
< prec
; i
++)
944 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
945 litP
+= sizeof (LITTLENUM_TYPE
);
950 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
951 for (i
= prec
- 1; i
>= 0; i
--)
953 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
954 litP
+= sizeof (LITTLENUM_TYPE
);
957 /* For a 4 byte float the order of elements in `words' is 1 0.
958 For an 8 byte float the order is 1 0 3 2. */
959 for (i
= 0; i
< prec
; i
+= 2)
961 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
962 sizeof (LITTLENUM_TYPE
));
963 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
964 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
965 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
972 /* We handle all bad expressions here, so that we can report the faulty
973 instruction in the error message. */
975 md_operand (expressionS
* expr
)
977 if (in_my_get_expression
)
978 expr
->X_op
= O_illegal
;
981 /* Immediate values. */
983 /* Generic immediate-value read function for use in directives.
984 Accepts anything that 'expression' can fold to a constant.
985 *val receives the number. */
988 immediate_for_directive (int *val
)
991 exp
.X_op
= O_illegal
;
993 if (is_immediate_prefix (*input_line_pointer
))
995 input_line_pointer
++;
999 if (exp
.X_op
!= O_constant
)
1001 as_bad (_("expected #constant"));
1002 ignore_rest_of_line ();
1005 *val
= exp
.X_add_number
;
1010 /* Register parsing. */
1012 /* Generic register parser. CCP points to what should be the
1013 beginning of a register name. If it is indeed a valid register
1014 name, advance CCP over it and return the reg_entry structure;
1015 otherwise return NULL. Does not issue diagnostics. */
1017 static struct reg_entry
*
1018 arm_reg_parse_multi (char **ccp
)
1022 struct reg_entry
*reg
;
1024 #ifdef REGISTER_PREFIX
1025 if (*start
!= REGISTER_PREFIX
)
1029 #ifdef OPTIONAL_REGISTER_PREFIX
1030 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1035 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1040 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1042 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1052 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1053 enum arm_reg_type type
)
1055 /* Alternative syntaxes are accepted for a few register classes. */
1062 /* Generic coprocessor register names are allowed for these. */
1063 if (reg
&& reg
->type
== REG_TYPE_CN
)
1068 /* For backward compatibility, a bare number is valid here. */
1070 unsigned long processor
= strtoul (start
, ccp
, 10);
1071 if (*ccp
!= start
&& processor
<= 15)
1075 case REG_TYPE_MMXWC
:
1076 /* WC includes WCG. ??? I'm not sure this is true for all
1077 instructions that take WC registers. */
1078 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1089 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1090 return value is the register number or FAIL. */
1093 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1096 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1099 /* Do not allow a scalar (reg+index) to parse as a register. */
1100 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1103 if (reg
&& reg
->type
== type
)
1106 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1113 /* Parse a Neon type specifier. *STR should point at the leading '.'
1114 character. Does no verification at this stage that the type fits the opcode
1121 Can all be legally parsed by this function.
1123 Fills in neon_type struct pointer with parsed information, and updates STR
1124 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1125 type, FAIL if not. */
1128 parse_neon_type (struct neon_type
*type
, char **str
)
1135 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1137 enum neon_el_type thistype
= NT_untyped
;
1138 unsigned thissize
= -1u;
1145 /* Just a size without an explicit type. */
1149 switch (TOLOWER (*ptr
))
1151 case 'i': thistype
= NT_integer
; break;
1152 case 'f': thistype
= NT_float
; break;
1153 case 'p': thistype
= NT_poly
; break;
1154 case 's': thistype
= NT_signed
; break;
1155 case 'u': thistype
= NT_unsigned
; break;
1157 thistype
= NT_float
;
1162 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1168 /* .f is an abbreviation for .f32. */
1169 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1174 thissize
= strtoul (ptr
, &ptr
, 10);
1176 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1179 as_bad (_("bad size %d in type specifier"), thissize
);
1187 type
->el
[type
->elems
].type
= thistype
;
1188 type
->el
[type
->elems
].size
= thissize
;
1193 /* Empty/missing type is not a successful parse. */
1194 if (type
->elems
== 0)
1202 /* Errors may be set multiple times during parsing or bit encoding
1203 (particularly in the Neon bits), but usually the earliest error which is set
1204 will be the most meaningful. Avoid overwriting it with later (cascading)
1205 errors by calling this function. */
1208 first_error (const char *err
)
1214 /* Parse a single type, e.g. ".s32", leading period included. */
1216 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1219 struct neon_type optype
;
1223 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1225 if (optype
.elems
== 1)
1226 *vectype
= optype
.el
[0];
1229 first_error (_("only one type should be specified for operand"));
1235 first_error (_("vector type expected"));
1247 /* Special meanings for indices (which have a range of 0-7), which will fit into
1250 #define NEON_ALL_LANES 15
1251 #define NEON_INTERLEAVE_LANES 14
1253 /* Parse either a register or a scalar, with an optional type. Return the
1254 register number, and optionally fill in the actual type of the register
1255 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1256 type/index information in *TYPEINFO. */
1259 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1260 enum arm_reg_type
*rtype
,
1261 struct neon_typed_alias
*typeinfo
)
1264 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1265 struct neon_typed_alias atype
;
1266 struct neon_type_el parsetype
;
1270 atype
.eltype
.type
= NT_invtype
;
1271 atype
.eltype
.size
= -1;
1273 /* Try alternate syntax for some types of register. Note these are mutually
1274 exclusive with the Neon syntax extensions. */
1277 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1285 /* Undo polymorphism when a set of register types may be accepted. */
1286 if ((type
== REG_TYPE_NDQ
1287 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1288 || (type
== REG_TYPE_VFSD
1289 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1290 || (type
== REG_TYPE_NSDQ
1291 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1292 || reg
->type
== REG_TYPE_NQ
))
1293 || (type
== REG_TYPE_MMXWC
1294 && (reg
->type
== REG_TYPE_MMXWCG
)))
1297 if (type
!= reg
->type
)
1303 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1305 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1307 first_error (_("can't redefine type for operand"));
1310 atype
.defined
|= NTA_HASTYPE
;
1311 atype
.eltype
= parsetype
;
1314 if (skip_past_char (&str
, '[') == SUCCESS
)
1316 if (type
!= REG_TYPE_VFD
)
1318 first_error (_("only D registers may be indexed"));
1322 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1324 first_error (_("can't change index for operand"));
1328 atype
.defined
|= NTA_HASINDEX
;
1330 if (skip_past_char (&str
, ']') == SUCCESS
)
1331 atype
.index
= NEON_ALL_LANES
;
1336 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1338 if (exp
.X_op
!= O_constant
)
1340 first_error (_("constant expression required"));
1344 if (skip_past_char (&str
, ']') == FAIL
)
1347 atype
.index
= exp
.X_add_number
;
1362 /* Like arm_reg_parse, but allow allow the following extra features:
1363 - If RTYPE is non-zero, return the (possibly restricted) type of the
1364 register (e.g. Neon double or quad reg when either has been requested).
1365 - If this is a Neon vector type with additional type information, fill
1366 in the struct pointed to by VECTYPE (if non-NULL).
1367 This function will fault on encountering a scalar. */
1370 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1371 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1373 struct neon_typed_alias atype
;
1375 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1380 /* Do not allow a scalar (reg+index) to parse as a register. */
1381 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1383 first_error (_("register operand expected, but got scalar"));
1388 *vectype
= atype
.eltype
;
1395 #define NEON_SCALAR_REG(X) ((X) >> 4)
1396 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1398 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1399 have enough information to be able to do a good job bounds-checking. So, we
1400 just do easy checks here, and do further checks later. */
1403 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1407 struct neon_typed_alias atype
;
1409 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1411 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1414 if (atype
.index
== NEON_ALL_LANES
)
1416 first_error (_("scalar must have an index"));
1419 else if (atype
.index
>= 64 / elsize
)
1421 first_error (_("scalar index out of range"));
1426 *type
= atype
.eltype
;
1430 return reg
* 16 + atype
.index
;
1433 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1435 parse_reg_list (char ** strp
)
1437 char * str
= * strp
;
1441 /* We come back here if we get ranges concatenated by '+' or '|'. */
1456 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1458 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1468 first_error (_("bad range in register list"));
1472 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1474 if (range
& (1 << i
))
1476 (_("Warning: duplicated register (r%d) in register list"),
1484 if (range
& (1 << reg
))
1485 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1487 else if (reg
<= cur_reg
)
1488 as_tsktsk (_("Warning: register range not in ascending order"));
1493 while (skip_past_comma (&str
) != FAIL
1494 || (in_range
= 1, *str
++ == '-'));
1499 first_error (_("missing `}'"));
1507 if (my_get_expression (&expr
, &str
, GE_NO_PREFIX
))
1510 if (expr
.X_op
== O_constant
)
1512 if (expr
.X_add_number
1513 != (expr
.X_add_number
& 0x0000ffff))
1515 inst
.error
= _("invalid register mask");
1519 if ((range
& expr
.X_add_number
) != 0)
1521 int regno
= range
& expr
.X_add_number
;
1524 regno
= (1 << regno
) - 1;
1526 (_("Warning: duplicated register (r%d) in register list"),
1530 range
|= expr
.X_add_number
;
1534 if (inst
.reloc
.type
!= 0)
1536 inst
.error
= _("expression too complex");
1540 memcpy (&inst
.reloc
.exp
, &expr
, sizeof (expressionS
));
1541 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1542 inst
.reloc
.pc_rel
= 0;
1546 if (*str
== '|' || *str
== '+')
1552 while (another_range
);
1558 /* Types of registers in a list. */
1567 /* Parse a VFP register list. If the string is invalid return FAIL.
1568 Otherwise return the number of registers, and set PBASE to the first
1569 register. Parses registers of type ETYPE.
1570 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1571 - Q registers can be used to specify pairs of D registers
1572 - { } can be omitted from around a singleton register list
1573 FIXME: This is not implemented, as it would require backtracking in
1576 This could be done (the meaning isn't really ambiguous), but doesn't
1577 fit in well with the current parsing framework.
1578 - 32 D registers may be used (also true for VFPv3).
1579 FIXME: Types are ignored in these register lists, which is probably a
1583 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1588 enum arm_reg_type regtype
= 0;
1592 unsigned long mask
= 0;
1597 inst
.error
= _("expecting {");
1606 regtype
= REG_TYPE_VFS
;
1611 regtype
= REG_TYPE_VFD
;
1614 case REGLIST_NEON_D
:
1615 regtype
= REG_TYPE_NDQ
;
1619 if (etype
!= REGLIST_VFP_S
)
1621 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1622 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1626 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1629 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1636 base_reg
= max_regs
;
1640 int setmask
= 1, addregs
= 1;
1642 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1644 if (new_base
== FAIL
)
1646 first_error (_(reg_expected_msgs
[regtype
]));
1650 if (new_base
>= max_regs
)
1652 first_error (_("register out of range in list"));
1656 /* Note: a value of 2 * n is returned for the register Q<n>. */
1657 if (regtype
== REG_TYPE_NQ
)
1663 if (new_base
< base_reg
)
1664 base_reg
= new_base
;
1666 if (mask
& (setmask
<< new_base
))
1668 first_error (_("invalid register list"));
1672 if ((mask
>> new_base
) != 0 && ! warned
)
1674 as_tsktsk (_("register list not in ascending order"));
1678 mask
|= setmask
<< new_base
;
1681 if (*str
== '-') /* We have the start of a range expression */
1687 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1690 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1694 if (high_range
>= max_regs
)
1696 first_error (_("register out of range in list"));
1700 if (regtype
== REG_TYPE_NQ
)
1701 high_range
= high_range
+ 1;
1703 if (high_range
<= new_base
)
1705 inst
.error
= _("register range not in ascending order");
1709 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1711 if (mask
& (setmask
<< new_base
))
1713 inst
.error
= _("invalid register list");
1717 mask
|= setmask
<< new_base
;
1722 while (skip_past_comma (&str
) != FAIL
);
1726 /* Sanity check -- should have raised a parse error above. */
1727 if (count
== 0 || count
> max_regs
)
1732 /* Final test -- the registers must be consecutive. */
1734 for (i
= 0; i
< count
; i
++)
1736 if ((mask
& (1u << i
)) == 0)
1738 inst
.error
= _("non-contiguous register range");
1748 /* True if two alias types are the same. */
1751 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1759 if (a
->defined
!= b
->defined
)
1762 if ((a
->defined
& NTA_HASTYPE
) != 0
1763 && (a
->eltype
.type
!= b
->eltype
.type
1764 || a
->eltype
.size
!= b
->eltype
.size
))
1767 if ((a
->defined
& NTA_HASINDEX
) != 0
1768 && (a
->index
!= b
->index
))
1774 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1775 The base register is put in *PBASE.
1776 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1778 The register stride (minus one) is put in bit 4 of the return value.
1779 Bits [6:5] encode the list length (minus one).
1780 The type of the list elements is put in *ELTYPE, if non-NULL. */
1782 #define NEON_LANE(X) ((X) & 0xf)
1783 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1784 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1787 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1788 struct neon_type_el
*eltype
)
1795 int leading_brace
= 0;
1796 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1798 const char *const incr_error
= "register stride must be 1 or 2";
1799 const char *const type_error
= "mismatched element/structure types in list";
1800 struct neon_typed_alias firsttype
;
1802 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1807 struct neon_typed_alias atype
;
1808 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1812 first_error (_(reg_expected_msgs
[rtype
]));
1819 if (rtype
== REG_TYPE_NQ
)
1826 else if (reg_incr
== -1)
1828 reg_incr
= getreg
- base_reg
;
1829 if (reg_incr
< 1 || reg_incr
> 2)
1831 first_error (_(incr_error
));
1835 else if (getreg
!= base_reg
+ reg_incr
* count
)
1837 first_error (_(incr_error
));
1841 if (!neon_alias_types_same (&atype
, &firsttype
))
1843 first_error (_(type_error
));
1847 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1851 struct neon_typed_alias htype
;
1852 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1854 lane
= NEON_INTERLEAVE_LANES
;
1855 else if (lane
!= NEON_INTERLEAVE_LANES
)
1857 first_error (_(type_error
));
1862 else if (reg_incr
!= 1)
1864 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1868 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1871 first_error (_(reg_expected_msgs
[rtype
]));
1874 if (!neon_alias_types_same (&htype
, &firsttype
))
1876 first_error (_(type_error
));
1879 count
+= hireg
+ dregs
- getreg
;
1883 /* If we're using Q registers, we can't use [] or [n] syntax. */
1884 if (rtype
== REG_TYPE_NQ
)
1890 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1894 else if (lane
!= atype
.index
)
1896 first_error (_(type_error
));
1900 else if (lane
== -1)
1901 lane
= NEON_INTERLEAVE_LANES
;
1902 else if (lane
!= NEON_INTERLEAVE_LANES
)
1904 first_error (_(type_error
));
1909 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
1911 /* No lane set by [x]. We must be interleaving structures. */
1913 lane
= NEON_INTERLEAVE_LANES
;
1916 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
1917 || (count
> 1 && reg_incr
== -1))
1919 first_error (_("error parsing element/structure list"));
1923 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
1925 first_error (_("expected }"));
1933 *eltype
= firsttype
.eltype
;
1938 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
1941 /* Parse an explicit relocation suffix on an expression. This is
1942 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
1943 arm_reloc_hsh contains no entries, so this function can only
1944 succeed if there is no () after the word. Returns -1 on error,
1945 BFD_RELOC_UNUSED if there wasn't any suffix. */
1947 parse_reloc (char **str
)
1949 struct reloc_entry
*r
;
1953 return BFD_RELOC_UNUSED
;
1958 while (*q
&& *q
!= ')' && *q
!= ',')
1963 if ((r
= hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
1970 /* Directives: register aliases. */
1972 static struct reg_entry
*
1973 insert_reg_alias (char *str
, int number
, int type
)
1975 struct reg_entry
*new;
1978 if ((new = hash_find (arm_reg_hsh
, str
)) != 0)
1981 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
1983 /* Only warn about a redefinition if it's not defined as the
1985 else if (new->number
!= number
|| new->type
!= type
)
1986 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
1991 name
= xstrdup (str
);
1992 new = xmalloc (sizeof (struct reg_entry
));
1995 new->number
= number
;
1997 new->builtin
= FALSE
;
2000 if (hash_insert (arm_reg_hsh
, name
, (void *) new))
2007 insert_neon_reg_alias (char *str
, int number
, int type
,
2008 struct neon_typed_alias
*atype
)
2010 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2014 first_error (_("attempt to redefine typed alias"));
2020 reg
->neon
= xmalloc (sizeof (struct neon_typed_alias
));
2021 *reg
->neon
= *atype
;
2025 /* Look for the .req directive. This is of the form:
2027 new_register_name .req existing_register_name
2029 If we find one, or if it looks sufficiently like one that we want to
2030 handle any error here, return TRUE. Otherwise return FALSE. */
2033 create_register_alias (char * newname
, char *p
)
2035 struct reg_entry
*old
;
2036 char *oldname
, *nbuf
;
2039 /* The input scrubber ensures that whitespace after the mnemonic is
2040 collapsed to single spaces. */
2042 if (strncmp (oldname
, " .req ", 6) != 0)
2046 if (*oldname
== '\0')
2049 old
= hash_find (arm_reg_hsh
, oldname
);
2052 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2056 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2057 the desired alias name, and p points to its end. If not, then
2058 the desired alias name is in the global original_case_string. */
2059 #ifdef TC_CASE_SENSITIVE
2062 newname
= original_case_string
;
2063 nlen
= strlen (newname
);
2066 nbuf
= alloca (nlen
+ 1);
2067 memcpy (nbuf
, newname
, nlen
);
2070 /* Create aliases under the new name as stated; an all-lowercase
2071 version of the new name; and an all-uppercase version of the new
2073 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2075 for (p
= nbuf
; *p
; p
++)
2078 if (strncmp (nbuf
, newname
, nlen
))
2080 /* If this attempt to create an additional alias fails, do not bother
2081 trying to create the all-lower case alias. We will fail and issue
2082 a second, duplicate error message. This situation arises when the
2083 programmer does something like:
2086 The second .req creates the "Foo" alias but then fails to create
2087 the artificial FOO alias because it has already been created by the
2089 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2093 for (p
= nbuf
; *p
; p
++)
2096 if (strncmp (nbuf
, newname
, nlen
))
2097 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2103 /* Create a Neon typed/indexed register alias using directives, e.g.:
2108 These typed registers can be used instead of the types specified after the
2109 Neon mnemonic, so long as all operands given have types. Types can also be
2110 specified directly, e.g.:
2111 vadd d0.s32, d1.s32, d2.s32 */
2114 create_neon_reg_alias (char *newname
, char *p
)
2116 enum arm_reg_type basetype
;
2117 struct reg_entry
*basereg
;
2118 struct reg_entry mybasereg
;
2119 struct neon_type ntype
;
2120 struct neon_typed_alias typeinfo
;
2121 char *namebuf
, *nameend
;
2124 typeinfo
.defined
= 0;
2125 typeinfo
.eltype
.type
= NT_invtype
;
2126 typeinfo
.eltype
.size
= -1;
2127 typeinfo
.index
= -1;
2131 if (strncmp (p
, " .dn ", 5) == 0)
2132 basetype
= REG_TYPE_VFD
;
2133 else if (strncmp (p
, " .qn ", 5) == 0)
2134 basetype
= REG_TYPE_NQ
;
2143 basereg
= arm_reg_parse_multi (&p
);
2145 if (basereg
&& basereg
->type
!= basetype
)
2147 as_bad (_("bad type for register"));
2151 if (basereg
== NULL
)
2154 /* Try parsing as an integer. */
2155 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2156 if (exp
.X_op
!= O_constant
)
2158 as_bad (_("expression must be constant"));
2161 basereg
= &mybasereg
;
2162 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2168 typeinfo
= *basereg
->neon
;
2170 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2172 /* We got a type. */
2173 if (typeinfo
.defined
& NTA_HASTYPE
)
2175 as_bad (_("can't redefine the type of a register alias"));
2179 typeinfo
.defined
|= NTA_HASTYPE
;
2180 if (ntype
.elems
!= 1)
2182 as_bad (_("you must specify a single type only"));
2185 typeinfo
.eltype
= ntype
.el
[0];
2188 if (skip_past_char (&p
, '[') == SUCCESS
)
2191 /* We got a scalar index. */
2193 if (typeinfo
.defined
& NTA_HASINDEX
)
2195 as_bad (_("can't redefine the index of a scalar alias"));
2199 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2201 if (exp
.X_op
!= O_constant
)
2203 as_bad (_("scalar index must be constant"));
2207 typeinfo
.defined
|= NTA_HASINDEX
;
2208 typeinfo
.index
= exp
.X_add_number
;
2210 if (skip_past_char (&p
, ']') == FAIL
)
2212 as_bad (_("expecting ]"));
2217 namelen
= nameend
- newname
;
2218 namebuf
= alloca (namelen
+ 1);
2219 strncpy (namebuf
, newname
, namelen
);
2220 namebuf
[namelen
] = '\0';
2222 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2223 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2225 /* Insert name in all uppercase. */
2226 for (p
= namebuf
; *p
; p
++)
2229 if (strncmp (namebuf
, newname
, namelen
))
2230 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2231 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2233 /* Insert name in all lowercase. */
2234 for (p
= namebuf
; *p
; p
++)
2237 if (strncmp (namebuf
, newname
, namelen
))
2238 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2239 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2244 /* Should never be called, as .req goes between the alias and the
2245 register name, not at the beginning of the line. */
2247 s_req (int a ATTRIBUTE_UNUSED
)
2249 as_bad (_("invalid syntax for .req directive"));
2253 s_dn (int a ATTRIBUTE_UNUSED
)
2255 as_bad (_("invalid syntax for .dn directive"));
2259 s_qn (int a ATTRIBUTE_UNUSED
)
2261 as_bad (_("invalid syntax for .qn directive"));
2264 /* The .unreq directive deletes an alias which was previously defined
2265 by .req. For example:
2271 s_unreq (int a ATTRIBUTE_UNUSED
)
2276 name
= input_line_pointer
;
2278 while (*input_line_pointer
!= 0
2279 && *input_line_pointer
!= ' '
2280 && *input_line_pointer
!= '\n')
2281 ++input_line_pointer
;
2283 saved_char
= *input_line_pointer
;
2284 *input_line_pointer
= 0;
2287 as_bad (_("invalid syntax for .unreq directive"));
2290 struct reg_entry
*reg
= hash_find (arm_reg_hsh
, name
);
2293 as_bad (_("unknown register alias '%s'"), name
);
2294 else if (reg
->builtin
)
2295 as_warn (_("ignoring attempt to undefine built-in register '%s'"),
2302 hash_delete (arm_reg_hsh
, name
, FALSE
);
2303 free ((char *) reg
->name
);
2308 /* Also locate the all upper case and all lower case versions.
2309 Do not complain if we cannot find one or the other as it
2310 was probably deleted above. */
2312 nbuf
= strdup (name
);
2313 for (p
= nbuf
; *p
; p
++)
2315 reg
= hash_find (arm_reg_hsh
, nbuf
);
2318 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2319 free ((char *) reg
->name
);
2325 for (p
= nbuf
; *p
; p
++)
2327 reg
= hash_find (arm_reg_hsh
, nbuf
);
2330 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2331 free ((char *) reg
->name
);
2341 *input_line_pointer
= saved_char
;
2342 demand_empty_rest_of_line ();
2345 /* Directives: Instruction set selection. */
2348 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2349 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2350 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2351 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2353 static enum mstate mapstate
= MAP_UNDEFINED
;
2356 mapping_state (enum mstate state
)
2359 const char * symname
;
2362 if (mapstate
== state
)
2363 /* The mapping symbol has already been emitted.
2364 There is nothing else to do. */
2373 type
= BSF_NO_FLAGS
;
2377 type
= BSF_NO_FLAGS
;
2381 type
= BSF_NO_FLAGS
;
2389 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2391 symbolP
= symbol_new (symname
, now_seg
, (valueT
) frag_now_fix (), frag_now
);
2392 symbol_table_insert (symbolP
);
2393 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2398 THUMB_SET_FUNC (symbolP
, 0);
2399 ARM_SET_THUMB (symbolP
, 0);
2400 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2404 THUMB_SET_FUNC (symbolP
, 1);
2405 ARM_SET_THUMB (symbolP
, 1);
2406 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2415 #define mapping_state(x) /* nothing */
2418 /* Find the real, Thumb encoded start of a Thumb function. */
2421 find_real_start (symbolS
* symbolP
)
2424 const char * name
= S_GET_NAME (symbolP
);
2425 symbolS
* new_target
;
2427 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2428 #define STUB_NAME ".real_start_of"
2433 /* The compiler may generate BL instructions to local labels because
2434 it needs to perform a branch to a far away location. These labels
2435 do not have a corresponding ".real_start_of" label. We check
2436 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2437 the ".real_start_of" convention for nonlocal branches. */
2438 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2441 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2442 new_target
= symbol_find (real_start
);
2444 if (new_target
== NULL
)
2446 as_warn (_("Failed to find real start of function: %s\n"), name
);
2447 new_target
= symbolP
;
2454 opcode_select (int width
)
2461 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2462 as_bad (_("selected processor does not support THUMB opcodes"));
2465 /* No need to force the alignment, since we will have been
2466 coming from ARM mode, which is word-aligned. */
2467 record_alignment (now_seg
, 1);
2469 mapping_state (MAP_THUMB
);
2475 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2476 as_bad (_("selected processor does not support ARM opcodes"));
2481 frag_align (2, 0, 0);
2483 record_alignment (now_seg
, 1);
2485 mapping_state (MAP_ARM
);
2489 as_bad (_("invalid instruction size selected (%d)"), width
);
2494 s_arm (int ignore ATTRIBUTE_UNUSED
)
2497 demand_empty_rest_of_line ();
2501 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2504 demand_empty_rest_of_line ();
2508 s_code (int unused ATTRIBUTE_UNUSED
)
2512 temp
= get_absolute_expression ();
2517 opcode_select (temp
);
2521 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2526 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2528 /* If we are not already in thumb mode go into it, EVEN if
2529 the target processor does not support thumb instructions.
2530 This is used by gcc/config/arm/lib1funcs.asm for example
2531 to compile interworking support functions even if the
2532 target processor should not support interworking. */
2536 record_alignment (now_seg
, 1);
2539 demand_empty_rest_of_line ();
2543 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2547 /* The following label is the name/address of the start of a Thumb function.
2548 We need to know this for the interworking support. */
2549 label_is_thumb_function_name
= TRUE
;
2552 /* Perform a .set directive, but also mark the alias as
2553 being a thumb function. */
2556 s_thumb_set (int equiv
)
2558 /* XXX the following is a duplicate of the code for s_set() in read.c
2559 We cannot just call that code as we need to get at the symbol that
2566 /* Especial apologies for the random logic:
2567 This just grew, and could be parsed much more simply!
2569 name
= input_line_pointer
;
2570 delim
= get_symbol_end ();
2571 end_name
= input_line_pointer
;
2574 if (*input_line_pointer
!= ',')
2577 as_bad (_("expected comma after name \"%s\""), name
);
2579 ignore_rest_of_line ();
2583 input_line_pointer
++;
2586 if (name
[0] == '.' && name
[1] == '\0')
2588 /* XXX - this should not happen to .thumb_set. */
2592 if ((symbolP
= symbol_find (name
)) == NULL
2593 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2596 /* When doing symbol listings, play games with dummy fragments living
2597 outside the normal fragment chain to record the file and line info
2599 if (listing
& LISTING_SYMBOLS
)
2601 extern struct list_info_struct
* listing_tail
;
2602 fragS
* dummy_frag
= xmalloc (sizeof (fragS
));
2604 memset (dummy_frag
, 0, sizeof (fragS
));
2605 dummy_frag
->fr_type
= rs_fill
;
2606 dummy_frag
->line
= listing_tail
;
2607 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2608 dummy_frag
->fr_symbol
= symbolP
;
2612 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2615 /* "set" symbols are local unless otherwise specified. */
2616 SF_SET_LOCAL (symbolP
);
2617 #endif /* OBJ_COFF */
2618 } /* Make a new symbol. */
2620 symbol_table_insert (symbolP
);
2625 && S_IS_DEFINED (symbolP
)
2626 && S_GET_SEGMENT (symbolP
) != reg_section
)
2627 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2629 pseudo_set (symbolP
);
2631 demand_empty_rest_of_line ();
2633 /* XXX Now we come to the Thumb specific bit of code. */
2635 THUMB_SET_FUNC (symbolP
, 1);
2636 ARM_SET_THUMB (symbolP
, 1);
2637 #if defined OBJ_ELF || defined OBJ_COFF
2638 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2642 /* Directives: Mode selection. */
2644 /* .syntax [unified|divided] - choose the new unified syntax
2645 (same for Arm and Thumb encoding, modulo slight differences in what
2646 can be represented) or the old divergent syntax for each mode. */
2648 s_syntax (int unused ATTRIBUTE_UNUSED
)
2652 name
= input_line_pointer
;
2653 delim
= get_symbol_end ();
2655 if (!strcasecmp (name
, "unified"))
2656 unified_syntax
= TRUE
;
2657 else if (!strcasecmp (name
, "divided"))
2658 unified_syntax
= FALSE
;
2661 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2664 *input_line_pointer
= delim
;
2665 demand_empty_rest_of_line ();
2668 /* Directives: sectioning and alignment. */
2670 /* Same as s_align_ptwo but align 0 => align 2. */
2673 s_align (int unused ATTRIBUTE_UNUSED
)
2678 long max_alignment
= 15;
2680 temp
= get_absolute_expression ();
2681 if (temp
> max_alignment
)
2682 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2685 as_bad (_("alignment negative. 0 assumed."));
2689 if (*input_line_pointer
== ',')
2691 input_line_pointer
++;
2692 temp_fill
= get_absolute_expression ();
2704 /* Only make a frag if we HAVE to. */
2705 if (temp
&& !need_pass_2
)
2707 if (!fill_p
&& subseg_text_p (now_seg
))
2708 frag_align_code (temp
, 0);
2710 frag_align (temp
, (int) temp_fill
, 0);
2712 demand_empty_rest_of_line ();
2714 record_alignment (now_seg
, temp
);
2718 s_bss (int ignore ATTRIBUTE_UNUSED
)
2720 /* We don't support putting frags in the BSS segment, we fake it by
2721 marking in_bss, then looking at s_skip for clues. */
2722 subseg_set (bss_section
, 0);
2723 demand_empty_rest_of_line ();
2724 mapping_state (MAP_DATA
);
2728 s_even (int ignore ATTRIBUTE_UNUSED
)
2730 /* Never make frag if expect extra pass. */
2732 frag_align (1, 0, 0);
2734 record_alignment (now_seg
, 1);
2736 demand_empty_rest_of_line ();
2739 /* Directives: Literal pools. */
2741 static literal_pool
*
2742 find_literal_pool (void)
2744 literal_pool
* pool
;
2746 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2748 if (pool
->section
== now_seg
2749 && pool
->sub_section
== now_subseg
)
2756 static literal_pool
*
2757 find_or_make_literal_pool (void)
2759 /* Next literal pool ID number. */
2760 static unsigned int latest_pool_num
= 1;
2761 literal_pool
* pool
;
2763 pool
= find_literal_pool ();
2767 /* Create a new pool. */
2768 pool
= xmalloc (sizeof (* pool
));
2772 pool
->next_free_entry
= 0;
2773 pool
->section
= now_seg
;
2774 pool
->sub_section
= now_subseg
;
2775 pool
->next
= list_of_pools
;
2776 pool
->symbol
= NULL
;
2778 /* Add it to the list. */
2779 list_of_pools
= pool
;
2782 /* New pools, and emptied pools, will have a NULL symbol. */
2783 if (pool
->symbol
== NULL
)
2785 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
2786 (valueT
) 0, &zero_address_frag
);
2787 pool
->id
= latest_pool_num
++;
2794 /* Add the literal in the global 'inst'
2795 structure to the relevant literal pool. */
2798 add_to_lit_pool (void)
2800 literal_pool
* pool
;
2803 pool
= find_or_make_literal_pool ();
2805 /* Check if this literal value is already in the pool. */
2806 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2808 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2809 && (inst
.reloc
.exp
.X_op
== O_constant
)
2810 && (pool
->literals
[entry
].X_add_number
2811 == inst
.reloc
.exp
.X_add_number
)
2812 && (pool
->literals
[entry
].X_unsigned
2813 == inst
.reloc
.exp
.X_unsigned
))
2816 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
2817 && (inst
.reloc
.exp
.X_op
== O_symbol
)
2818 && (pool
->literals
[entry
].X_add_number
2819 == inst
.reloc
.exp
.X_add_number
)
2820 && (pool
->literals
[entry
].X_add_symbol
2821 == inst
.reloc
.exp
.X_add_symbol
)
2822 && (pool
->literals
[entry
].X_op_symbol
2823 == inst
.reloc
.exp
.X_op_symbol
))
2827 /* Do we need to create a new entry? */
2828 if (entry
== pool
->next_free_entry
)
2830 if (entry
>= MAX_LITERAL_POOL_SIZE
)
2832 inst
.error
= _("literal pool overflow");
2836 pool
->literals
[entry
] = inst
.reloc
.exp
;
2837 pool
->next_free_entry
+= 1;
2840 inst
.reloc
.exp
.X_op
= O_symbol
;
2841 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
2842 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
2847 /* Can't use symbol_new here, so have to create a symbol and then at
2848 a later date assign it a value. Thats what these functions do. */
2851 symbol_locate (symbolS
* symbolP
,
2852 const char * name
, /* It is copied, the caller can modify. */
2853 segT segment
, /* Segment identifier (SEG_<something>). */
2854 valueT valu
, /* Symbol value. */
2855 fragS
* frag
) /* Associated fragment. */
2857 unsigned int name_length
;
2858 char * preserved_copy_of_name
;
2860 name_length
= strlen (name
) + 1; /* +1 for \0. */
2861 obstack_grow (¬es
, name
, name_length
);
2862 preserved_copy_of_name
= obstack_finish (¬es
);
2864 #ifdef tc_canonicalize_symbol_name
2865 preserved_copy_of_name
=
2866 tc_canonicalize_symbol_name (preserved_copy_of_name
);
2869 S_SET_NAME (symbolP
, preserved_copy_of_name
);
2871 S_SET_SEGMENT (symbolP
, segment
);
2872 S_SET_VALUE (symbolP
, valu
);
2873 symbol_clear_list_pointers (symbolP
);
2875 symbol_set_frag (symbolP
, frag
);
2877 /* Link to end of symbol chain. */
2879 extern int symbol_table_frozen
;
2881 if (symbol_table_frozen
)
2885 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
2887 obj_symbol_new_hook (symbolP
);
2889 #ifdef tc_symbol_new_hook
2890 tc_symbol_new_hook (symbolP
);
2894 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
2895 #endif /* DEBUG_SYMS */
2900 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
2903 literal_pool
* pool
;
2906 pool
= find_literal_pool ();
2908 || pool
->symbol
== NULL
2909 || pool
->next_free_entry
== 0)
2912 mapping_state (MAP_DATA
);
2914 /* Align pool as you have word accesses.
2915 Only make a frag if we have to. */
2917 frag_align (2, 0, 0);
2919 record_alignment (now_seg
, 2);
2921 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
2923 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
2924 (valueT
) frag_now_fix (), frag_now
);
2925 symbol_table_insert (pool
->symbol
);
2927 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
2929 #if defined OBJ_COFF || defined OBJ_ELF
2930 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
2933 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
2934 /* First output the expression in the instruction to the pool. */
2935 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
2937 /* Mark the pool as empty. */
2938 pool
->next_free_entry
= 0;
2939 pool
->symbol
= NULL
;
2943 /* Forward declarations for functions below, in the MD interface
2945 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
2946 static valueT
create_unwind_entry (int);
2947 static void start_unwind_section (const segT
, int);
2948 static void add_unwind_opcode (valueT
, int);
2949 static void flush_pending_unwind (void);
2951 /* Directives: Data. */
2954 s_arm_elf_cons (int nbytes
)
2958 #ifdef md_flush_pending_output
2959 md_flush_pending_output ();
2962 if (is_it_end_of_statement ())
2964 demand_empty_rest_of_line ();
2968 #ifdef md_cons_align
2969 md_cons_align (nbytes
);
2972 mapping_state (MAP_DATA
);
2976 char *base
= input_line_pointer
;
2980 if (exp
.X_op
!= O_symbol
)
2981 emit_expr (&exp
, (unsigned int) nbytes
);
2984 char *before_reloc
= input_line_pointer
;
2985 reloc
= parse_reloc (&input_line_pointer
);
2988 as_bad (_("unrecognized relocation suffix"));
2989 ignore_rest_of_line ();
2992 else if (reloc
== BFD_RELOC_UNUSED
)
2993 emit_expr (&exp
, (unsigned int) nbytes
);
2996 reloc_howto_type
*howto
= bfd_reloc_type_lookup (stdoutput
, reloc
);
2997 int size
= bfd_get_reloc_size (howto
);
2999 if (reloc
== BFD_RELOC_ARM_PLT32
)
3001 as_bad (_("(plt) is only valid on branch targets"));
3002 reloc
= BFD_RELOC_UNUSED
;
3007 as_bad (_("%s relocations do not fit in %d bytes"),
3008 howto
->name
, nbytes
);
3011 /* We've parsed an expression stopping at O_symbol.
3012 But there may be more expression left now that we
3013 have parsed the relocation marker. Parse it again.
3014 XXX Surely there is a cleaner way to do this. */
3015 char *p
= input_line_pointer
;
3017 char *save_buf
= alloca (input_line_pointer
- base
);
3018 memcpy (save_buf
, base
, input_line_pointer
- base
);
3019 memmove (base
+ (input_line_pointer
- before_reloc
),
3020 base
, before_reloc
- base
);
3022 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3024 memcpy (base
, save_buf
, p
- base
);
3026 offset
= nbytes
- size
;
3027 p
= frag_more ((int) nbytes
);
3028 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3029 size
, &exp
, 0, reloc
);
3034 while (*input_line_pointer
++ == ',');
3036 /* Put terminator back into stream. */
3037 input_line_pointer
--;
3038 demand_empty_rest_of_line ();
3042 /* Parse a .rel31 directive. */
3045 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3052 if (*input_line_pointer
== '1')
3053 highbit
= 0x80000000;
3054 else if (*input_line_pointer
!= '0')
3055 as_bad (_("expected 0 or 1"));
3057 input_line_pointer
++;
3058 if (*input_line_pointer
!= ',')
3059 as_bad (_("missing comma"));
3060 input_line_pointer
++;
3062 #ifdef md_flush_pending_output
3063 md_flush_pending_output ();
3066 #ifdef md_cons_align
3070 mapping_state (MAP_DATA
);
3075 md_number_to_chars (p
, highbit
, 4);
3076 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3077 BFD_RELOC_ARM_PREL31
);
3079 demand_empty_rest_of_line ();
3082 /* Directives: AEABI stack-unwind tables. */
3084 /* Parse an unwind_fnstart directive. Simply records the current location. */
3087 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3089 demand_empty_rest_of_line ();
3090 /* Mark the start of the function. */
3091 unwind
.proc_start
= expr_build_dot ();
3093 /* Reset the rest of the unwind info. */
3094 unwind
.opcode_count
= 0;
3095 unwind
.table_entry
= NULL
;
3096 unwind
.personality_routine
= NULL
;
3097 unwind
.personality_index
= -1;
3098 unwind
.frame_size
= 0;
3099 unwind
.fp_offset
= 0;
3100 unwind
.fp_reg
= REG_SP
;
3102 unwind
.sp_restored
= 0;
3106 /* Parse a handlerdata directive. Creates the exception handling table entry
3107 for the function. */
3110 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3112 demand_empty_rest_of_line ();
3113 if (unwind
.table_entry
)
3114 as_bad (_("duplicate .handlerdata directive"));
3116 create_unwind_entry (1);
3119 /* Parse an unwind_fnend directive. Generates the index table entry. */
3122 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3128 demand_empty_rest_of_line ();
3130 /* Add eh table entry. */
3131 if (unwind
.table_entry
== NULL
)
3132 val
= create_unwind_entry (0);
3136 /* Add index table entry. This is two words. */
3137 start_unwind_section (unwind
.saved_seg
, 1);
3138 frag_align (2, 0, 0);
3139 record_alignment (now_seg
, 2);
3141 ptr
= frag_more (8);
3142 where
= frag_now_fix () - 8;
3144 /* Self relative offset of the function start. */
3145 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3146 BFD_RELOC_ARM_PREL31
);
3148 /* Indicate dependency on EHABI-defined personality routines to the
3149 linker, if it hasn't been done already. */
3150 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3151 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3153 static const char *const name
[] =
3155 "__aeabi_unwind_cpp_pr0",
3156 "__aeabi_unwind_cpp_pr1",
3157 "__aeabi_unwind_cpp_pr2"
3159 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3160 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3161 marked_pr_dependency
|= 1 << unwind
.personality_index
;
3162 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3163 = marked_pr_dependency
;
3167 /* Inline exception table entry. */
3168 md_number_to_chars (ptr
+ 4, val
, 4);
3170 /* Self relative offset of the table entry. */
3171 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3172 BFD_RELOC_ARM_PREL31
);
3174 /* Restore the original section. */
3175 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3179 /* Parse an unwind_cantunwind directive. */
3182 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3184 demand_empty_rest_of_line ();
3185 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3186 as_bad (_("personality routine specified for cantunwind frame"));
3188 unwind
.personality_index
= -2;
3192 /* Parse a personalityindex directive. */
3195 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3199 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3200 as_bad (_("duplicate .personalityindex directive"));
3204 if (exp
.X_op
!= O_constant
3205 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3207 as_bad (_("bad personality routine number"));
3208 ignore_rest_of_line ();
3212 unwind
.personality_index
= exp
.X_add_number
;
3214 demand_empty_rest_of_line ();
3218 /* Parse a personality directive. */
3221 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3225 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3226 as_bad (_("duplicate .personality directive"));
3228 name
= input_line_pointer
;
3229 c
= get_symbol_end ();
3230 p
= input_line_pointer
;
3231 unwind
.personality_routine
= symbol_find_or_make (name
);
3233 demand_empty_rest_of_line ();
3237 /* Parse a directive saving core registers. */
3240 s_arm_unwind_save_core (void)
3246 range
= parse_reg_list (&input_line_pointer
);
3249 as_bad (_("expected register list"));
3250 ignore_rest_of_line ();
3254 demand_empty_rest_of_line ();
3256 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3257 into .unwind_save {..., sp...}. We aren't bothered about the value of
3258 ip because it is clobbered by calls. */
3259 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3260 && (range
& 0x3000) == 0x1000)
3262 unwind
.opcode_count
--;
3263 unwind
.sp_restored
= 0;
3264 range
= (range
| 0x2000) & ~0x1000;
3265 unwind
.pending_offset
= 0;
3271 /* See if we can use the short opcodes. These pop a block of up to 8
3272 registers starting with r4, plus maybe r14. */
3273 for (n
= 0; n
< 8; n
++)
3275 /* Break at the first non-saved register. */
3276 if ((range
& (1 << (n
+ 4))) == 0)
3279 /* See if there are any other bits set. */
3280 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3282 /* Use the long form. */
3283 op
= 0x8000 | ((range
>> 4) & 0xfff);
3284 add_unwind_opcode (op
, 2);
3288 /* Use the short form. */
3290 op
= 0xa8; /* Pop r14. */
3292 op
= 0xa0; /* Do not pop r14. */
3294 add_unwind_opcode (op
, 1);
3301 op
= 0xb100 | (range
& 0xf);
3302 add_unwind_opcode (op
, 2);
3305 /* Record the number of bytes pushed. */
3306 for (n
= 0; n
< 16; n
++)
3308 if (range
& (1 << n
))
3309 unwind
.frame_size
+= 4;
3314 /* Parse a directive saving FPA registers. */
3317 s_arm_unwind_save_fpa (int reg
)
3323 /* Get Number of registers to transfer. */
3324 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3327 exp
.X_op
= O_illegal
;
3329 if (exp
.X_op
!= O_constant
)
3331 as_bad (_("expected , <constant>"));
3332 ignore_rest_of_line ();
3336 num_regs
= exp
.X_add_number
;
3338 if (num_regs
< 1 || num_regs
> 4)
3340 as_bad (_("number of registers must be in the range [1:4]"));
3341 ignore_rest_of_line ();
3345 demand_empty_rest_of_line ();
3350 op
= 0xb4 | (num_regs
- 1);
3351 add_unwind_opcode (op
, 1);
3356 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3357 add_unwind_opcode (op
, 2);
3359 unwind
.frame_size
+= num_regs
* 12;
3363 /* Parse a directive saving VFP registers for ARMv6 and above. */
3366 s_arm_unwind_save_vfp_armv6 (void)
3371 int num_vfpv3_regs
= 0;
3372 int num_regs_below_16
;
3374 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3377 as_bad (_("expected register list"));
3378 ignore_rest_of_line ();
3382 demand_empty_rest_of_line ();
3384 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3385 than FSTMX/FLDMX-style ones). */
3387 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3389 num_vfpv3_regs
= count
;
3390 else if (start
+ count
> 16)
3391 num_vfpv3_regs
= start
+ count
- 16;
3393 if (num_vfpv3_regs
> 0)
3395 int start_offset
= start
> 16 ? start
- 16 : 0;
3396 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3397 add_unwind_opcode (op
, 2);
3400 /* Generate opcode for registers numbered in the range 0 .. 15. */
3401 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3402 assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3403 if (num_regs_below_16
> 0)
3405 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3406 add_unwind_opcode (op
, 2);
3409 unwind
.frame_size
+= count
* 8;
3413 /* Parse a directive saving VFP registers for pre-ARMv6. */
3416 s_arm_unwind_save_vfp (void)
3422 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3425 as_bad (_("expected register list"));
3426 ignore_rest_of_line ();
3430 demand_empty_rest_of_line ();
3435 op
= 0xb8 | (count
- 1);
3436 add_unwind_opcode (op
, 1);
3441 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3442 add_unwind_opcode (op
, 2);
3444 unwind
.frame_size
+= count
* 8 + 4;
3448 /* Parse a directive saving iWMMXt data registers. */
3451 s_arm_unwind_save_mmxwr (void)
3459 if (*input_line_pointer
== '{')
3460 input_line_pointer
++;
3464 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3468 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3473 as_tsktsk (_("register list not in ascending order"));
3476 if (*input_line_pointer
== '-')
3478 input_line_pointer
++;
3479 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3482 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3485 else if (reg
>= hi_reg
)
3487 as_bad (_("bad register range"));
3490 for (; reg
< hi_reg
; reg
++)
3494 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3496 if (*input_line_pointer
== '}')
3497 input_line_pointer
++;
3499 demand_empty_rest_of_line ();
3501 /* Generate any deferred opcodes because we're going to be looking at
3503 flush_pending_unwind ();
3505 for (i
= 0; i
< 16; i
++)
3507 if (mask
& (1 << i
))
3508 unwind
.frame_size
+= 8;
3511 /* Attempt to combine with a previous opcode. We do this because gcc
3512 likes to output separate unwind directives for a single block of
3514 if (unwind
.opcode_count
> 0)
3516 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3517 if ((i
& 0xf8) == 0xc0)
3520 /* Only merge if the blocks are contiguous. */
3523 if ((mask
& 0xfe00) == (1 << 9))
3525 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3526 unwind
.opcode_count
--;
3529 else if (i
== 6 && unwind
.opcode_count
>= 2)
3531 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3535 op
= 0xffff << (reg
- 1);
3537 && ((mask
& op
) == (1u << (reg
- 1))))
3539 op
= (1 << (reg
+ i
+ 1)) - 1;
3540 op
&= ~((1 << reg
) - 1);
3542 unwind
.opcode_count
-= 2;
3549 /* We want to generate opcodes in the order the registers have been
3550 saved, ie. descending order. */
3551 for (reg
= 15; reg
>= -1; reg
--)
3553 /* Save registers in blocks. */
3555 || !(mask
& (1 << reg
)))
3557 /* We found an unsaved reg. Generate opcodes to save the
3564 op
= 0xc0 | (hi_reg
- 10);
3565 add_unwind_opcode (op
, 1);
3570 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3571 add_unwind_opcode (op
, 2);
3580 ignore_rest_of_line ();
3584 s_arm_unwind_save_mmxwcg (void)
3591 if (*input_line_pointer
== '{')
3592 input_line_pointer
++;
3596 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3600 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3606 as_tsktsk (_("register list not in ascending order"));
3609 if (*input_line_pointer
== '-')
3611 input_line_pointer
++;
3612 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3615 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3618 else if (reg
>= hi_reg
)
3620 as_bad (_("bad register range"));
3623 for (; reg
< hi_reg
; reg
++)
3627 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3629 if (*input_line_pointer
== '}')
3630 input_line_pointer
++;
3632 demand_empty_rest_of_line ();
3634 /* Generate any deferred opcodes because we're going to be looking at
3636 flush_pending_unwind ();
3638 for (reg
= 0; reg
< 16; reg
++)
3640 if (mask
& (1 << reg
))
3641 unwind
.frame_size
+= 4;
3644 add_unwind_opcode (op
, 2);
3647 ignore_rest_of_line ();
3651 /* Parse an unwind_save directive.
3652 If the argument is non-zero, this is a .vsave directive. */
3655 s_arm_unwind_save (int arch_v6
)
3658 struct reg_entry
*reg
;
3659 bfd_boolean had_brace
= FALSE
;
3661 /* Figure out what sort of save we have. */
3662 peek
= input_line_pointer
;
3670 reg
= arm_reg_parse_multi (&peek
);
3674 as_bad (_("register expected"));
3675 ignore_rest_of_line ();
3684 as_bad (_("FPA .unwind_save does not take a register list"));
3685 ignore_rest_of_line ();
3688 input_line_pointer
= peek
;
3689 s_arm_unwind_save_fpa (reg
->number
);
3692 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
3695 s_arm_unwind_save_vfp_armv6 ();
3697 s_arm_unwind_save_vfp ();
3699 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
3700 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
3703 as_bad (_(".unwind_save does not support this kind of register"));
3704 ignore_rest_of_line ();
3709 /* Parse an unwind_movsp directive. */
3712 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
3718 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3721 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
3722 ignore_rest_of_line ();
3726 /* Optional constant. */
3727 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3729 if (immediate_for_directive (&offset
) == FAIL
)
3735 demand_empty_rest_of_line ();
3737 if (reg
== REG_SP
|| reg
== REG_PC
)
3739 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
3743 if (unwind
.fp_reg
!= REG_SP
)
3744 as_bad (_("unexpected .unwind_movsp directive"));
3746 /* Generate opcode to restore the value. */
3748 add_unwind_opcode (op
, 1);
3750 /* Record the information for later. */
3751 unwind
.fp_reg
= reg
;
3752 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3753 unwind
.sp_restored
= 1;
3756 /* Parse an unwind_pad directive. */
3759 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
3763 if (immediate_for_directive (&offset
) == FAIL
)
3768 as_bad (_("stack increment must be multiple of 4"));
3769 ignore_rest_of_line ();
3773 /* Don't generate any opcodes, just record the details for later. */
3774 unwind
.frame_size
+= offset
;
3775 unwind
.pending_offset
+= offset
;
3777 demand_empty_rest_of_line ();
3780 /* Parse an unwind_setfp directive. */
3783 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
3789 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3790 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3793 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
3795 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
3797 as_bad (_("expected <reg>, <reg>"));
3798 ignore_rest_of_line ();
3802 /* Optional constant. */
3803 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3805 if (immediate_for_directive (&offset
) == FAIL
)
3811 demand_empty_rest_of_line ();
3813 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
3815 as_bad (_("register must be either sp or set by a previous"
3816 "unwind_movsp directive"));
3820 /* Don't generate any opcodes, just record the information for later. */
3821 unwind
.fp_reg
= fp_reg
;
3823 if (sp_reg
== REG_SP
)
3824 unwind
.fp_offset
= unwind
.frame_size
- offset
;
3826 unwind
.fp_offset
-= offset
;
3829 /* Parse an unwind_raw directive. */
3832 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
3835 /* This is an arbitrary limit. */
3836 unsigned char op
[16];
3840 if (exp
.X_op
== O_constant
3841 && skip_past_comma (&input_line_pointer
) != FAIL
)
3843 unwind
.frame_size
+= exp
.X_add_number
;
3847 exp
.X_op
= O_illegal
;
3849 if (exp
.X_op
!= O_constant
)
3851 as_bad (_("expected <offset>, <opcode>"));
3852 ignore_rest_of_line ();
3858 /* Parse the opcode. */
3863 as_bad (_("unwind opcode too long"));
3864 ignore_rest_of_line ();
3866 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
3868 as_bad (_("invalid unwind opcode"));
3869 ignore_rest_of_line ();
3872 op
[count
++] = exp
.X_add_number
;
3874 /* Parse the next byte. */
3875 if (skip_past_comma (&input_line_pointer
) == FAIL
)
3881 /* Add the opcode bytes in reverse order. */
3883 add_unwind_opcode (op
[count
], 1);
3885 demand_empty_rest_of_line ();
3889 /* Parse a .eabi_attribute directive. */
3892 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
3894 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
3896 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
3897 attributes_set_explicitly
[tag
] = 1;
3899 #endif /* OBJ_ELF */
3901 static void s_arm_arch (int);
3902 static void s_arm_object_arch (int);
3903 static void s_arm_cpu (int);
3904 static void s_arm_fpu (int);
3909 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
3916 if (exp
.X_op
== O_symbol
)
3917 exp
.X_op
= O_secrel
;
3919 emit_expr (&exp
, 4);
3921 while (*input_line_pointer
++ == ',');
3923 input_line_pointer
--;
3924 demand_empty_rest_of_line ();
3928 /* This table describes all the machine specific pseudo-ops the assembler
3929 has to support. The fields are:
3930 pseudo-op name without dot
3931 function to call to execute this pseudo-op
3932 Integer arg to pass to the function. */
3934 const pseudo_typeS md_pseudo_table
[] =
3936 /* Never called because '.req' does not start a line. */
3937 { "req", s_req
, 0 },
3938 /* Following two are likewise never called. */
3941 { "unreq", s_unreq
, 0 },
3942 { "bss", s_bss
, 0 },
3943 { "align", s_align
, 0 },
3944 { "arm", s_arm
, 0 },
3945 { "thumb", s_thumb
, 0 },
3946 { "code", s_code
, 0 },
3947 { "force_thumb", s_force_thumb
, 0 },
3948 { "thumb_func", s_thumb_func
, 0 },
3949 { "thumb_set", s_thumb_set
, 0 },
3950 { "even", s_even
, 0 },
3951 { "ltorg", s_ltorg
, 0 },
3952 { "pool", s_ltorg
, 0 },
3953 { "syntax", s_syntax
, 0 },
3954 { "cpu", s_arm_cpu
, 0 },
3955 { "arch", s_arm_arch
, 0 },
3956 { "object_arch", s_arm_object_arch
, 0 },
3957 { "fpu", s_arm_fpu
, 0 },
3959 { "word", s_arm_elf_cons
, 4 },
3960 { "long", s_arm_elf_cons
, 4 },
3961 { "rel31", s_arm_rel31
, 0 },
3962 { "fnstart", s_arm_unwind_fnstart
, 0 },
3963 { "fnend", s_arm_unwind_fnend
, 0 },
3964 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
3965 { "personality", s_arm_unwind_personality
, 0 },
3966 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
3967 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
3968 { "save", s_arm_unwind_save
, 0 },
3969 { "vsave", s_arm_unwind_save
, 1 },
3970 { "movsp", s_arm_unwind_movsp
, 0 },
3971 { "pad", s_arm_unwind_pad
, 0 },
3972 { "setfp", s_arm_unwind_setfp
, 0 },
3973 { "unwind_raw", s_arm_unwind_raw
, 0 },
3974 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
3978 /* These are used for dwarf. */
3982 /* These are used for dwarf2. */
3983 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
3984 { "loc", dwarf2_directive_loc
, 0 },
3985 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
3987 { "extend", float_cons
, 'x' },
3988 { "ldouble", float_cons
, 'x' },
3989 { "packed", float_cons
, 'p' },
3991 {"secrel32", pe_directive_secrel
, 0},
3996 /* Parser functions used exclusively in instruction operands. */
3998 /* Generic immediate-value read function for use in insn parsing.
3999 STR points to the beginning of the immediate (the leading #);
4000 VAL receives the value; if the value is outside [MIN, MAX]
4001 issue an error. PREFIX_OPT is true if the immediate prefix is
4005 parse_immediate (char **str
, int *val
, int min
, int max
,
4006 bfd_boolean prefix_opt
)
4009 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4010 if (exp
.X_op
!= O_constant
)
4012 inst
.error
= _("constant expression required");
4016 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4018 inst
.error
= _("immediate value out of range");
4022 *val
= exp
.X_add_number
;
4026 /* Less-generic immediate-value read function with the possibility of loading a
4027 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4028 instructions. Puts the result directly in inst.operands[i]. */
4031 parse_big_immediate (char **str
, int i
)
4036 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4038 if (exp
.X_op
== O_constant
)
4040 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4041 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4042 O_constant. We have to be careful not to break compilation for
4043 32-bit X_add_number, though. */
4044 if ((exp
.X_add_number
& ~0xffffffffl
) != 0)
4046 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4047 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4048 inst
.operands
[i
].regisimm
= 1;
4051 else if (exp
.X_op
== O_big
4052 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32
4053 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
<= 64)
4055 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4056 /* Bignums have their least significant bits in
4057 generic_bignum[0]. Make sure we put 32 bits in imm and
4058 32 bits in reg, in a (hopefully) portable way. */
4059 assert (parts
!= 0);
4060 inst
.operands
[i
].imm
= 0;
4061 for (j
= 0; j
< parts
; j
++, idx
++)
4062 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4063 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4064 inst
.operands
[i
].reg
= 0;
4065 for (j
= 0; j
< parts
; j
++, idx
++)
4066 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4067 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4068 inst
.operands
[i
].regisimm
= 1;
4078 /* Returns the pseudo-register number of an FPA immediate constant,
4079 or FAIL if there isn't a valid constant here. */
4082 parse_fpa_immediate (char ** str
)
4084 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4090 /* First try and match exact strings, this is to guarantee
4091 that some formats will work even for cross assembly. */
4093 for (i
= 0; fp_const
[i
]; i
++)
4095 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4099 *str
+= strlen (fp_const
[i
]);
4100 if (is_end_of_line
[(unsigned char) **str
])
4106 /* Just because we didn't get a match doesn't mean that the constant
4107 isn't valid, just that it is in a format that we don't
4108 automatically recognize. Try parsing it with the standard
4109 expression routines. */
4111 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4113 /* Look for a raw floating point number. */
4114 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4115 && is_end_of_line
[(unsigned char) *save_in
])
4117 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4119 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4121 if (words
[j
] != fp_values
[i
][j
])
4125 if (j
== MAX_LITTLENUMS
)
4133 /* Try and parse a more complex expression, this will probably fail
4134 unless the code uses a floating point prefix (eg "0f"). */
4135 save_in
= input_line_pointer
;
4136 input_line_pointer
= *str
;
4137 if (expression (&exp
) == absolute_section
4138 && exp
.X_op
== O_big
4139 && exp
.X_add_number
< 0)
4141 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4143 if (gen_to_words (words
, 5, (long) 15) == 0)
4145 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4147 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4149 if (words
[j
] != fp_values
[i
][j
])
4153 if (j
== MAX_LITTLENUMS
)
4155 *str
= input_line_pointer
;
4156 input_line_pointer
= save_in
;
4163 *str
= input_line_pointer
;
4164 input_line_pointer
= save_in
;
4165 inst
.error
= _("invalid FPA immediate expression");
4169 /* Returns 1 if a number has "quarter-precision" float format
4170 0baBbbbbbc defgh000 00000000 00000000. */
4173 is_quarter_float (unsigned imm
)
4175 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4176 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4179 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4180 0baBbbbbbc defgh000 00000000 00000000.
4181 The zero and minus-zero cases need special handling, since they can't be
4182 encoded in the "quarter-precision" float format, but can nonetheless be
4183 loaded as integer constants. */
4186 parse_qfloat_immediate (char **ccp
, int *immed
)
4190 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4191 int found_fpchar
= 0;
4193 skip_past_char (&str
, '#');
4195 /* We must not accidentally parse an integer as a floating-point number. Make
4196 sure that the value we parse is not an integer by checking for special
4197 characters '.' or 'e'.
4198 FIXME: This is a horrible hack, but doing better is tricky because type
4199 information isn't in a very usable state at parse time. */
4201 skip_whitespace (fpnum
);
4203 if (strncmp (fpnum
, "0x", 2) == 0)
4207 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4208 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4218 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4220 unsigned fpword
= 0;
4223 /* Our FP word must be 32 bits (single-precision FP). */
4224 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4226 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4230 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4243 /* Shift operands. */
4246 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4249 struct asm_shift_name
4252 enum shift_kind kind
;
4255 /* Third argument to parse_shift. */
4256 enum parse_shift_mode
4258 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4259 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4260 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4261 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4262 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4265 /* Parse a <shift> specifier on an ARM data processing instruction.
4266 This has three forms:
4268 (LSL|LSR|ASL|ASR|ROR) Rs
4269 (LSL|LSR|ASL|ASR|ROR) #imm
4272 Note that ASL is assimilated to LSL in the instruction encoding, and
4273 RRX to ROR #0 (which cannot be written as such). */
4276 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4278 const struct asm_shift_name
*shift_name
;
4279 enum shift_kind shift
;
4284 for (p
= *str
; ISALPHA (*p
); p
++)
4289 inst
.error
= _("shift expression expected");
4293 shift_name
= hash_find_n (arm_shift_hsh
, *str
, p
- *str
);
4295 if (shift_name
== NULL
)
4297 inst
.error
= _("shift expression expected");
4301 shift
= shift_name
->kind
;
4305 case NO_SHIFT_RESTRICT
:
4306 case SHIFT_IMMEDIATE
: break;
4308 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4309 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4311 inst
.error
= _("'LSL' or 'ASR' required");
4316 case SHIFT_LSL_IMMEDIATE
:
4317 if (shift
!= SHIFT_LSL
)
4319 inst
.error
= _("'LSL' required");
4324 case SHIFT_ASR_IMMEDIATE
:
4325 if (shift
!= SHIFT_ASR
)
4327 inst
.error
= _("'ASR' required");
4335 if (shift
!= SHIFT_RRX
)
4337 /* Whitespace can appear here if the next thing is a bare digit. */
4338 skip_whitespace (p
);
4340 if (mode
== NO_SHIFT_RESTRICT
4341 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4343 inst
.operands
[i
].imm
= reg
;
4344 inst
.operands
[i
].immisreg
= 1;
4346 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4349 inst
.operands
[i
].shift_kind
= shift
;
4350 inst
.operands
[i
].shifted
= 1;
4355 /* Parse a <shifter_operand> for an ARM data processing instruction:
4358 #<immediate>, <rotate>
4362 where <shift> is defined by parse_shift above, and <rotate> is a
4363 multiple of 2 between 0 and 30. Validation of immediate operands
4364 is deferred to md_apply_fix. */
4367 parse_shifter_operand (char **str
, int i
)
4372 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4374 inst
.operands
[i
].reg
= value
;
4375 inst
.operands
[i
].isreg
= 1;
4377 /* parse_shift will override this if appropriate */
4378 inst
.reloc
.exp
.X_op
= O_constant
;
4379 inst
.reloc
.exp
.X_add_number
= 0;
4381 if (skip_past_comma (str
) == FAIL
)
4384 /* Shift operation on register. */
4385 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4388 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4391 if (skip_past_comma (str
) == SUCCESS
)
4393 /* #x, y -- ie explicit rotation by Y. */
4394 if (my_get_expression (&expr
, str
, GE_NO_PREFIX
))
4397 if (expr
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4399 inst
.error
= _("constant expression expected");
4403 value
= expr
.X_add_number
;
4404 if (value
< 0 || value
> 30 || value
% 2 != 0)
4406 inst
.error
= _("invalid rotation");
4409 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4411 inst
.error
= _("invalid constant");
4415 /* Convert to decoded value. md_apply_fix will put it back. */
4416 inst
.reloc
.exp
.X_add_number
4417 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4418 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4421 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4422 inst
.reloc
.pc_rel
= 0;
4426 /* Group relocation information. Each entry in the table contains the
4427 textual name of the relocation as may appear in assembler source
4428 and must end with a colon.
4429 Along with this textual name are the relocation codes to be used if
4430 the corresponding instruction is an ALU instruction (ADD or SUB only),
4431 an LDR, an LDRS, or an LDC. */
4433 struct group_reloc_table_entry
4444 /* Varieties of non-ALU group relocation. */
4451 static struct group_reloc_table_entry group_reloc_table
[] =
4452 { /* Program counter relative: */
4454 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4459 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4460 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4461 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4462 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4464 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4469 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4470 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4471 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4472 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4474 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4475 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4476 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4477 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4478 /* Section base relative */
4480 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4485 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4486 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4487 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4488 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4490 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4495 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4496 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4497 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4498 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4500 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4501 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4502 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4503 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4505 /* Given the address of a pointer pointing to the textual name of a group
4506 relocation as may appear in assembler source, attempt to find its details
4507 in group_reloc_table. The pointer will be updated to the character after
4508 the trailing colon. On failure, FAIL will be returned; SUCCESS
4509 otherwise. On success, *entry will be updated to point at the relevant
4510 group_reloc_table entry. */
4513 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4516 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4518 int length
= strlen (group_reloc_table
[i
].name
);
4520 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4521 && (*str
)[length
] == ':')
4523 *out
= &group_reloc_table
[i
];
4524 *str
+= (length
+ 1);
4532 /* Parse a <shifter_operand> for an ARM data processing instruction
4533 (as for parse_shifter_operand) where group relocations are allowed:
4536 #<immediate>, <rotate>
4537 #:<group_reloc>:<expression>
4541 where <group_reloc> is one of the strings defined in group_reloc_table.
4542 The hashes are optional.
4544 Everything else is as for parse_shifter_operand. */
4546 static parse_operand_result
4547 parse_shifter_operand_group_reloc (char **str
, int i
)
4549 /* Determine if we have the sequence of characters #: or just :
4550 coming next. If we do, then we check for a group relocation.
4551 If we don't, punt the whole lot to parse_shifter_operand. */
4553 if (((*str
)[0] == '#' && (*str
)[1] == ':')
4554 || (*str
)[0] == ':')
4556 struct group_reloc_table_entry
*entry
;
4558 if ((*str
)[0] == '#')
4563 /* Try to parse a group relocation. Anything else is an error. */
4564 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
4566 inst
.error
= _("unknown group relocation");
4567 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4570 /* We now have the group relocation table entry corresponding to
4571 the name in the assembler source. Next, we parse the expression. */
4572 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
4573 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4575 /* Record the relocation type (always the ALU variant here). */
4576 inst
.reloc
.type
= entry
->alu_code
;
4577 assert (inst
.reloc
.type
!= 0);
4579 return PARSE_OPERAND_SUCCESS
;
4582 return parse_shifter_operand (str
, i
) == SUCCESS
4583 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
4585 /* Never reached. */
4588 /* Parse all forms of an ARM address expression. Information is written
4589 to inst.operands[i] and/or inst.reloc.
4591 Preindexed addressing (.preind=1):
4593 [Rn, #offset] .reg=Rn .reloc.exp=offset
4594 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4595 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4596 .shift_kind=shift .reloc.exp=shift_imm
4598 These three may have a trailing ! which causes .writeback to be set also.
4600 Postindexed addressing (.postind=1, .writeback=1):
4602 [Rn], #offset .reg=Rn .reloc.exp=offset
4603 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4604 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
4605 .shift_kind=shift .reloc.exp=shift_imm
4607 Unindexed addressing (.preind=0, .postind=0):
4609 [Rn], {option} .reg=Rn .imm=option .immisreg=0
4613 [Rn]{!} shorthand for [Rn,#0]{!}
4614 =immediate .isreg=0 .reloc.exp=immediate
4615 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
4617 It is the caller's responsibility to check for addressing modes not
4618 supported by the instruction, and to set inst.reloc.type. */
4620 static parse_operand_result
4621 parse_address_main (char **str
, int i
, int group_relocations
,
4622 group_reloc_type group_type
)
4627 if (skip_past_char (&p
, '[') == FAIL
)
4629 if (skip_past_char (&p
, '=') == FAIL
)
4631 /* bare address - translate to PC-relative offset */
4632 inst
.reloc
.pc_rel
= 1;
4633 inst
.operands
[i
].reg
= REG_PC
;
4634 inst
.operands
[i
].isreg
= 1;
4635 inst
.operands
[i
].preind
= 1;
4637 /* else a load-constant pseudo op, no special treatment needed here */
4639 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4640 return PARSE_OPERAND_FAIL
;
4643 return PARSE_OPERAND_SUCCESS
;
4646 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
4648 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
4649 return PARSE_OPERAND_FAIL
;
4651 inst
.operands
[i
].reg
= reg
;
4652 inst
.operands
[i
].isreg
= 1;
4654 if (skip_past_comma (&p
) == SUCCESS
)
4656 inst
.operands
[i
].preind
= 1;
4659 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4661 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4663 inst
.operands
[i
].imm
= reg
;
4664 inst
.operands
[i
].immisreg
= 1;
4666 if (skip_past_comma (&p
) == SUCCESS
)
4667 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4668 return PARSE_OPERAND_FAIL
;
4670 else if (skip_past_char (&p
, ':') == SUCCESS
)
4672 /* FIXME: '@' should be used here, but it's filtered out by generic
4673 code before we get to see it here. This may be subject to
4676 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
4677 if (exp
.X_op
!= O_constant
)
4679 inst
.error
= _("alignment must be constant");
4680 return PARSE_OPERAND_FAIL
;
4682 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
4683 inst
.operands
[i
].immisalign
= 1;
4684 /* Alignments are not pre-indexes. */
4685 inst
.operands
[i
].preind
= 0;
4689 if (inst
.operands
[i
].negative
)
4691 inst
.operands
[i
].negative
= 0;
4695 if (group_relocations
4696 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
4698 struct group_reloc_table_entry
*entry
;
4700 /* Skip over the #: or : sequence. */
4706 /* Try to parse a group relocation. Anything else is an
4708 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
4710 inst
.error
= _("unknown group relocation");
4711 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4714 /* We now have the group relocation table entry corresponding to
4715 the name in the assembler source. Next, we parse the
4717 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4718 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4720 /* Record the relocation type. */
4724 inst
.reloc
.type
= entry
->ldr_code
;
4728 inst
.reloc
.type
= entry
->ldrs_code
;
4732 inst
.reloc
.type
= entry
->ldc_code
;
4739 if (inst
.reloc
.type
== 0)
4741 inst
.error
= _("this group relocation is not allowed on this instruction");
4742 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
4746 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4747 return PARSE_OPERAND_FAIL
;
4751 if (skip_past_char (&p
, ']') == FAIL
)
4753 inst
.error
= _("']' expected");
4754 return PARSE_OPERAND_FAIL
;
4757 if (skip_past_char (&p
, '!') == SUCCESS
)
4758 inst
.operands
[i
].writeback
= 1;
4760 else if (skip_past_comma (&p
) == SUCCESS
)
4762 if (skip_past_char (&p
, '{') == SUCCESS
)
4764 /* [Rn], {expr} - unindexed, with option */
4765 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
4766 0, 255, TRUE
) == FAIL
)
4767 return PARSE_OPERAND_FAIL
;
4769 if (skip_past_char (&p
, '}') == FAIL
)
4771 inst
.error
= _("'}' expected at end of 'option' field");
4772 return PARSE_OPERAND_FAIL
;
4774 if (inst
.operands
[i
].preind
)
4776 inst
.error
= _("cannot combine index with option");
4777 return PARSE_OPERAND_FAIL
;
4780 return PARSE_OPERAND_SUCCESS
;
4784 inst
.operands
[i
].postind
= 1;
4785 inst
.operands
[i
].writeback
= 1;
4787 if (inst
.operands
[i
].preind
)
4789 inst
.error
= _("cannot combine pre- and post-indexing");
4790 return PARSE_OPERAND_FAIL
;
4794 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
4796 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4798 /* We might be using the immediate for alignment already. If we
4799 are, OR the register number into the low-order bits. */
4800 if (inst
.operands
[i
].immisalign
)
4801 inst
.operands
[i
].imm
|= reg
;
4803 inst
.operands
[i
].imm
= reg
;
4804 inst
.operands
[i
].immisreg
= 1;
4806 if (skip_past_comma (&p
) == SUCCESS
)
4807 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
4808 return PARSE_OPERAND_FAIL
;
4812 if (inst
.operands
[i
].negative
)
4814 inst
.operands
[i
].negative
= 0;
4817 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4818 return PARSE_OPERAND_FAIL
;
4823 /* If at this point neither .preind nor .postind is set, we have a
4824 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
4825 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
4827 inst
.operands
[i
].preind
= 1;
4828 inst
.reloc
.exp
.X_op
= O_constant
;
4829 inst
.reloc
.exp
.X_add_number
= 0;
4832 return PARSE_OPERAND_SUCCESS
;
4836 parse_address (char **str
, int i
)
4838 return parse_address_main (str
, i
, 0, 0) == PARSE_OPERAND_SUCCESS
4842 static parse_operand_result
4843 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
4845 return parse_address_main (str
, i
, 1, type
);
4848 /* Parse an operand for a MOVW or MOVT instruction. */
4850 parse_half (char **str
)
4855 skip_past_char (&p
, '#');
4856 if (strncasecmp (p
, ":lower16:", 9) == 0)
4857 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
4858 else if (strncasecmp (p
, ":upper16:", 9) == 0)
4859 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
4861 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
4864 skip_whitespace (p
);
4867 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
4870 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
4872 if (inst
.reloc
.exp
.X_op
!= O_constant
)
4874 inst
.error
= _("constant expression expected");
4877 if (inst
.reloc
.exp
.X_add_number
< 0
4878 || inst
.reloc
.exp
.X_add_number
> 0xffff)
4880 inst
.error
= _("immediate value out of range");
4888 /* Miscellaneous. */
4890 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
4891 or a bitmask suitable to be or-ed into the ARM msr instruction. */
4893 parse_psr (char **str
)
4896 unsigned long psr_field
;
4897 const struct asm_psr
*psr
;
4900 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
4901 feature for ease of use and backwards compatibility. */
4903 if (strncasecmp (p
, "SPSR", 4) == 0)
4904 psr_field
= SPSR_BIT
;
4905 else if (strncasecmp (p
, "CPSR", 4) == 0)
4912 while (ISALNUM (*p
) || *p
== '_');
4914 psr
= hash_find_n (arm_v7m_psr_hsh
, start
, p
- start
);
4925 /* A suffix follows. */
4931 while (ISALNUM (*p
) || *p
== '_');
4933 psr
= hash_find_n (arm_psr_hsh
, start
, p
- start
);
4937 psr_field
|= psr
->field
;
4942 goto error
; /* Garbage after "[CS]PSR". */
4944 psr_field
|= (PSR_c
| PSR_f
);
4950 inst
.error
= _("flag for {c}psr instruction expected");
4954 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
4955 value suitable for splatting into the AIF field of the instruction. */
4958 parse_cps_flags (char **str
)
4967 case '\0': case ',':
4970 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
4971 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
4972 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
4975 inst
.error
= _("unrecognized CPS flag");
4980 if (saw_a_flag
== 0)
4982 inst
.error
= _("missing CPS flags");
4990 /* Parse an endian specifier ("BE" or "LE", case insensitive);
4991 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
4994 parse_endian_specifier (char **str
)
4999 if (strncasecmp (s
, "BE", 2))
5001 else if (strncasecmp (s
, "LE", 2))
5005 inst
.error
= _("valid endian specifiers are be or le");
5009 if (ISALNUM (s
[2]) || s
[2] == '_')
5011 inst
.error
= _("valid endian specifiers are be or le");
5016 return little_endian
;
5019 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5020 value suitable for poking into the rotate field of an sxt or sxta
5021 instruction, or FAIL on error. */
5024 parse_ror (char **str
)
5029 if (strncasecmp (s
, "ROR", 3) == 0)
5033 inst
.error
= _("missing rotation field after comma");
5037 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5042 case 0: *str
= s
; return 0x0;
5043 case 8: *str
= s
; return 0x1;
5044 case 16: *str
= s
; return 0x2;
5045 case 24: *str
= s
; return 0x3;
5048 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5053 /* Parse a conditional code (from conds[] below). The value returned is in the
5054 range 0 .. 14, or FAIL. */
5056 parse_cond (char **str
)
5059 const struct asm_cond
*c
;
5061 /* Condition codes are always 2 characters, so matching up to
5062 3 characters is sufficient. */
5067 while (ISALPHA (*q
) && n
< 3)
5069 cond
[n
] = TOLOWER(*q
);
5074 c
= hash_find_n (arm_cond_hsh
, cond
, n
);
5077 inst
.error
= _("condition required");
5085 /* Parse an option for a barrier instruction. Returns the encoding for the
5088 parse_barrier (char **str
)
5091 const struct asm_barrier_opt
*o
;
5094 while (ISALPHA (*q
))
5097 o
= hash_find_n (arm_barrier_opt_hsh
, p
, q
- p
);
5105 /* Parse the operands of a table branch instruction. Similar to a memory
5108 parse_tb (char **str
)
5113 if (skip_past_char (&p
, '[') == FAIL
)
5115 inst
.error
= _("'[' expected");
5119 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5121 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5124 inst
.operands
[0].reg
= reg
;
5126 if (skip_past_comma (&p
) == FAIL
)
5128 inst
.error
= _("',' expected");
5132 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5134 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5137 inst
.operands
[0].imm
= reg
;
5139 if (skip_past_comma (&p
) == SUCCESS
)
5141 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5143 if (inst
.reloc
.exp
.X_add_number
!= 1)
5145 inst
.error
= _("invalid shift");
5148 inst
.operands
[0].shifted
= 1;
5151 if (skip_past_char (&p
, ']') == FAIL
)
5153 inst
.error
= _("']' expected");
5160 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5161 information on the types the operands can take and how they are encoded.
5162 Up to four operands may be read; this function handles setting the
5163 ".present" field for each read operand itself.
5164 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5165 else returns FAIL. */
5168 parse_neon_mov (char **str
, int *which_operand
)
5170 int i
= *which_operand
, val
;
5171 enum arm_reg_type rtype
;
5173 struct neon_type_el optype
;
5175 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5177 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5178 inst
.operands
[i
].reg
= val
;
5179 inst
.operands
[i
].isscalar
= 1;
5180 inst
.operands
[i
].vectype
= optype
;
5181 inst
.operands
[i
++].present
= 1;
5183 if (skip_past_comma (&ptr
) == FAIL
)
5186 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5189 inst
.operands
[i
].reg
= val
;
5190 inst
.operands
[i
].isreg
= 1;
5191 inst
.operands
[i
].present
= 1;
5193 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5196 /* Cases 0, 1, 2, 3, 5 (D only). */
5197 if (skip_past_comma (&ptr
) == FAIL
)
5200 inst
.operands
[i
].reg
= val
;
5201 inst
.operands
[i
].isreg
= 1;
5202 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5203 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5204 inst
.operands
[i
].isvec
= 1;
5205 inst
.operands
[i
].vectype
= optype
;
5206 inst
.operands
[i
++].present
= 1;
5208 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5210 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5211 Case 13: VMOV <Sd>, <Rm> */
5212 inst
.operands
[i
].reg
= val
;
5213 inst
.operands
[i
].isreg
= 1;
5214 inst
.operands
[i
].present
= 1;
5216 if (rtype
== REG_TYPE_NQ
)
5218 first_error (_("can't use Neon quad register here"));
5221 else if (rtype
!= REG_TYPE_VFS
)
5224 if (skip_past_comma (&ptr
) == FAIL
)
5226 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5228 inst
.operands
[i
].reg
= val
;
5229 inst
.operands
[i
].isreg
= 1;
5230 inst
.operands
[i
].present
= 1;
5233 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5236 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5237 Case 1: VMOV<c><q> <Dd>, <Dm>
5238 Case 8: VMOV.F32 <Sd>, <Sm>
5239 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5241 inst
.operands
[i
].reg
= val
;
5242 inst
.operands
[i
].isreg
= 1;
5243 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5244 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5245 inst
.operands
[i
].isvec
= 1;
5246 inst
.operands
[i
].vectype
= optype
;
5247 inst
.operands
[i
].present
= 1;
5249 if (skip_past_comma (&ptr
) == SUCCESS
)
5254 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5257 inst
.operands
[i
].reg
= val
;
5258 inst
.operands
[i
].isreg
= 1;
5259 inst
.operands
[i
++].present
= 1;
5261 if (skip_past_comma (&ptr
) == FAIL
)
5264 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5267 inst
.operands
[i
].reg
= val
;
5268 inst
.operands
[i
].isreg
= 1;
5269 inst
.operands
[i
++].present
= 1;
5272 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5273 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5274 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5275 Case 10: VMOV.F32 <Sd>, #<imm>
5276 Case 11: VMOV.F64 <Dd>, #<imm> */
5277 inst
.operands
[i
].immisfloat
= 1;
5278 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5279 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5280 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5284 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5288 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5291 inst
.operands
[i
].reg
= val
;
5292 inst
.operands
[i
].isreg
= 1;
5293 inst
.operands
[i
++].present
= 1;
5295 if (skip_past_comma (&ptr
) == FAIL
)
5298 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5300 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5301 inst
.operands
[i
].reg
= val
;
5302 inst
.operands
[i
].isscalar
= 1;
5303 inst
.operands
[i
].present
= 1;
5304 inst
.operands
[i
].vectype
= optype
;
5306 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5308 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5309 inst
.operands
[i
].reg
= val
;
5310 inst
.operands
[i
].isreg
= 1;
5311 inst
.operands
[i
++].present
= 1;
5313 if (skip_past_comma (&ptr
) == FAIL
)
5316 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5319 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5323 inst
.operands
[i
].reg
= val
;
5324 inst
.operands
[i
].isreg
= 1;
5325 inst
.operands
[i
].isvec
= 1;
5326 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5327 inst
.operands
[i
].vectype
= optype
;
5328 inst
.operands
[i
].present
= 1;
5330 if (rtype
== REG_TYPE_VFS
)
5334 if (skip_past_comma (&ptr
) == FAIL
)
5336 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5339 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5342 inst
.operands
[i
].reg
= val
;
5343 inst
.operands
[i
].isreg
= 1;
5344 inst
.operands
[i
].isvec
= 1;
5345 inst
.operands
[i
].issingle
= 1;
5346 inst
.operands
[i
].vectype
= optype
;
5347 inst
.operands
[i
].present
= 1;
5350 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
5354 inst
.operands
[i
].reg
= val
;
5355 inst
.operands
[i
].isreg
= 1;
5356 inst
.operands
[i
].isvec
= 1;
5357 inst
.operands
[i
].issingle
= 1;
5358 inst
.operands
[i
].vectype
= optype
;
5359 inst
.operands
[i
++].present
= 1;
5364 first_error (_("parse error"));
5368 /* Successfully parsed the operands. Update args. */
5374 first_error (_("expected comma"));
5378 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
5382 /* Matcher codes for parse_operands. */
5383 enum operand_parse_code
5385 OP_stop
, /* end of line */
5387 OP_RR
, /* ARM register */
5388 OP_RRnpc
, /* ARM register, not r15 */
5389 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
5390 OP_RRw
, /* ARM register, not r15, optional trailing ! */
5391 OP_RCP
, /* Coprocessor number */
5392 OP_RCN
, /* Coprocessor register */
5393 OP_RF
, /* FPA register */
5394 OP_RVS
, /* VFP single precision register */
5395 OP_RVD
, /* VFP double precision register (0..15) */
5396 OP_RND
, /* Neon double precision register (0..31) */
5397 OP_RNQ
, /* Neon quad precision register */
5398 OP_RVSD
, /* VFP single or double precision register */
5399 OP_RNDQ
, /* Neon double or quad precision register */
5400 OP_RNSDQ
, /* Neon single, double or quad precision register */
5401 OP_RNSC
, /* Neon scalar D[X] */
5402 OP_RVC
, /* VFP control register */
5403 OP_RMF
, /* Maverick F register */
5404 OP_RMD
, /* Maverick D register */
5405 OP_RMFX
, /* Maverick FX register */
5406 OP_RMDX
, /* Maverick DX register */
5407 OP_RMAX
, /* Maverick AX register */
5408 OP_RMDS
, /* Maverick DSPSC register */
5409 OP_RIWR
, /* iWMMXt wR register */
5410 OP_RIWC
, /* iWMMXt wC register */
5411 OP_RIWG
, /* iWMMXt wCG register */
5412 OP_RXA
, /* XScale accumulator register */
5414 OP_REGLST
, /* ARM register list */
5415 OP_VRSLST
, /* VFP single-precision register list */
5416 OP_VRDLST
, /* VFP double-precision register list */
5417 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
5418 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
5419 OP_NSTRLST
, /* Neon element/structure list */
5421 OP_NILO
, /* Neon immediate/logic operands 2 or 2+3. (VBIC, VORR...) */
5422 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
5423 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
5424 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
5425 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
5426 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
5427 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
5428 OP_VMOV
, /* Neon VMOV operands. */
5429 OP_RNDQ_IMVNb
,/* Neon D or Q reg, or immediate good for VMVN. */
5430 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
5431 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
5433 OP_I0
, /* immediate zero */
5434 OP_I7
, /* immediate value 0 .. 7 */
5435 OP_I15
, /* 0 .. 15 */
5436 OP_I16
, /* 1 .. 16 */
5437 OP_I16z
, /* 0 .. 16 */
5438 OP_I31
, /* 0 .. 31 */
5439 OP_I31w
, /* 0 .. 31, optional trailing ! */
5440 OP_I32
, /* 1 .. 32 */
5441 OP_I32z
, /* 0 .. 32 */
5442 OP_I63
, /* 0 .. 63 */
5443 OP_I63s
, /* -64 .. 63 */
5444 OP_I64
, /* 1 .. 64 */
5445 OP_I64z
, /* 0 .. 64 */
5446 OP_I255
, /* 0 .. 255 */
5448 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
5449 OP_I7b
, /* 0 .. 7 */
5450 OP_I15b
, /* 0 .. 15 */
5451 OP_I31b
, /* 0 .. 31 */
5453 OP_SH
, /* shifter operand */
5454 OP_SHG
, /* shifter operand with possible group relocation */
5455 OP_ADDR
, /* Memory address expression (any mode) */
5456 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
5457 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
5458 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
5459 OP_EXP
, /* arbitrary expression */
5460 OP_EXPi
, /* same, with optional immediate prefix */
5461 OP_EXPr
, /* same, with optional relocation suffix */
5462 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
5464 OP_CPSF
, /* CPS flags */
5465 OP_ENDI
, /* Endianness specifier */
5466 OP_PSR
, /* CPSR/SPSR mask for msr */
5467 OP_COND
, /* conditional code */
5468 OP_TB
, /* Table branch. */
5470 OP_RVC_PSR
, /* CPSR/SPSR mask for msr, or VFP control register. */
5471 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
5473 OP_RRnpc_I0
, /* ARM register or literal 0 */
5474 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
5475 OP_RR_EXi
, /* ARM register or expression with imm prefix */
5476 OP_RF_IF
, /* FPA register or immediate */
5477 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
5478 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
5480 /* Optional operands. */
5481 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
5482 OP_oI31b
, /* 0 .. 31 */
5483 OP_oI32b
, /* 1 .. 32 */
5484 OP_oIffffb
, /* 0 .. 65535 */
5485 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
5487 OP_oRR
, /* ARM register */
5488 OP_oRRnpc
, /* ARM register, not the PC */
5489 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
5490 OP_oRND
, /* Optional Neon double precision register */
5491 OP_oRNQ
, /* Optional Neon quad precision register */
5492 OP_oRNDQ
, /* Optional Neon double or quad precision register */
5493 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
5494 OP_oSHll
, /* LSL immediate */
5495 OP_oSHar
, /* ASR immediate */
5496 OP_oSHllar
, /* LSL or ASR immediate */
5497 OP_oROR
, /* ROR 0/8/16/24 */
5498 OP_oBARRIER
, /* Option argument for a barrier instruction. */
5500 OP_FIRST_OPTIONAL
= OP_oI7b
5503 /* Generic instruction operand parser. This does no encoding and no
5504 semantic validation; it merely squirrels values away in the inst
5505 structure. Returns SUCCESS or FAIL depending on whether the
5506 specified grammar matched. */
5508 parse_operands (char *str
, const unsigned char *pattern
)
5510 unsigned const char *upat
= pattern
;
5511 char *backtrack_pos
= 0;
5512 const char *backtrack_error
= 0;
5513 int i
, val
, backtrack_index
= 0;
5514 enum arm_reg_type rtype
;
5515 parse_operand_result result
;
5517 #define po_char_or_fail(chr) do { \
5518 if (skip_past_char (&str, chr) == FAIL) \
5522 #define po_reg_or_fail(regtype) do { \
5523 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5524 &inst.operands[i].vectype); \
5527 first_error (_(reg_expected_msgs[regtype])); \
5530 inst.operands[i].reg = val; \
5531 inst.operands[i].isreg = 1; \
5532 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5533 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5534 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5535 || rtype == REG_TYPE_VFD \
5536 || rtype == REG_TYPE_NQ); \
5539 #define po_reg_or_goto(regtype, label) do { \
5540 val = arm_typed_reg_parse (&str, regtype, &rtype, \
5541 &inst.operands[i].vectype); \
5545 inst.operands[i].reg = val; \
5546 inst.operands[i].isreg = 1; \
5547 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
5548 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
5549 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
5550 || rtype == REG_TYPE_VFD \
5551 || rtype == REG_TYPE_NQ); \
5554 #define po_imm_or_fail(min, max, popt) do { \
5555 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
5557 inst.operands[i].imm = val; \
5560 #define po_scalar_or_goto(elsz, label) do { \
5561 val = parse_scalar (&str, elsz, &inst.operands[i].vectype); \
5564 inst.operands[i].reg = val; \
5565 inst.operands[i].isscalar = 1; \
5568 #define po_misc_or_fail(expr) do { \
5573 #define po_misc_or_fail_no_backtrack(expr) do { \
5575 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK)\
5576 backtrack_pos = 0; \
5577 if (result != PARSE_OPERAND_SUCCESS) \
5581 skip_whitespace (str
);
5583 for (i
= 0; upat
[i
] != OP_stop
; i
++)
5585 if (upat
[i
] >= OP_FIRST_OPTIONAL
)
5587 /* Remember where we are in case we need to backtrack. */
5588 assert (!backtrack_pos
);
5589 backtrack_pos
= str
;
5590 backtrack_error
= inst
.error
;
5591 backtrack_index
= i
;
5594 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
5595 po_char_or_fail (',');
5603 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
5604 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
5605 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
5606 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
5607 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
5608 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
5610 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
5612 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
5614 /* Also accept generic coprocessor regs for unknown registers. */
5616 po_reg_or_fail (REG_TYPE_CN
);
5618 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
5619 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
5620 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
5621 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
5622 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
5623 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
5624 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
5625 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
5626 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
5627 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
5629 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
5631 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
5632 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
5634 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
5636 /* Neon scalar. Using an element size of 8 means that some invalid
5637 scalars are accepted here, so deal with those in later code. */
5638 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
5640 /* WARNING: We can expand to two operands here. This has the potential
5641 to totally confuse the backtracking mechanism! It will be OK at
5642 least as long as we don't try to use optional args as well,
5646 po_reg_or_goto (REG_TYPE_NDQ
, try_imm
);
5647 inst
.operands
[i
].present
= 1;
5649 skip_past_comma (&str
);
5650 po_reg_or_goto (REG_TYPE_NDQ
, one_reg_only
);
5653 /* Optional register operand was omitted. Unfortunately, it's in
5654 operands[i-1] and we need it to be in inst.operands[i]. Fix that
5655 here (this is a bit grotty). */
5656 inst
.operands
[i
] = inst
.operands
[i
-1];
5657 inst
.operands
[i
-1].present
= 0;
5660 /* There's a possibility of getting a 64-bit immediate here, so
5661 we need special handling. */
5662 if (parse_big_immediate (&str
, i
) == FAIL
)
5664 inst
.error
= _("immediate value is out of range");
5672 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
5675 po_imm_or_fail (0, 0, TRUE
);
5680 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
5685 po_scalar_or_goto (8, try_rr
);
5688 po_reg_or_fail (REG_TYPE_RN
);
5694 po_scalar_or_goto (8, try_nsdq
);
5697 po_reg_or_fail (REG_TYPE_NSDQ
);
5703 po_scalar_or_goto (8, try_ndq
);
5706 po_reg_or_fail (REG_TYPE_NDQ
);
5712 po_scalar_or_goto (8, try_vfd
);
5715 po_reg_or_fail (REG_TYPE_VFD
);
5720 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
5721 not careful then bad things might happen. */
5722 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
5727 po_reg_or_goto (REG_TYPE_NDQ
, try_mvnimm
);
5730 /* There's a possibility of getting a 64-bit immediate here, so
5731 we need special handling. */
5732 if (parse_big_immediate (&str
, i
) == FAIL
)
5734 inst
.error
= _("immediate value is out of range");
5742 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
5745 po_imm_or_fail (0, 63, TRUE
);
5750 po_char_or_fail ('[');
5751 po_reg_or_fail (REG_TYPE_RN
);
5752 po_char_or_fail (']');
5757 po_reg_or_fail (REG_TYPE_RN
);
5758 if (skip_past_char (&str
, '!') == SUCCESS
)
5759 inst
.operands
[i
].writeback
= 1;
5763 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
5764 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
5765 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
5766 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
5767 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
5768 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
5769 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
5770 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
5771 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
5772 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
5773 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
5774 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
5776 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
5778 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
5779 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
5781 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
5782 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
5783 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
5785 /* Immediate variants */
5787 po_char_or_fail ('{');
5788 po_imm_or_fail (0, 255, TRUE
);
5789 po_char_or_fail ('}');
5793 /* The expression parser chokes on a trailing !, so we have
5794 to find it first and zap it. */
5797 while (*s
&& *s
!= ',')
5802 inst
.operands
[i
].writeback
= 1;
5804 po_imm_or_fail (0, 31, TRUE
);
5812 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5817 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5822 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
5824 if (inst
.reloc
.exp
.X_op
== O_symbol
)
5826 val
= parse_reloc (&str
);
5829 inst
.error
= _("unrecognized relocation suffix");
5832 else if (val
!= BFD_RELOC_UNUSED
)
5834 inst
.operands
[i
].imm
= val
;
5835 inst
.operands
[i
].hasreloc
= 1;
5840 /* Operand for MOVW or MOVT. */
5842 po_misc_or_fail (parse_half (&str
));
5845 /* Register or expression */
5846 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
5847 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
5849 /* Register or immediate */
5850 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
5851 I0
: po_imm_or_fail (0, 0, FALSE
); break;
5853 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
5855 if (!is_immediate_prefix (*str
))
5858 val
= parse_fpa_immediate (&str
);
5861 /* FPA immediates are encoded as registers 8-15.
5862 parse_fpa_immediate has already applied the offset. */
5863 inst
.operands
[i
].reg
= val
;
5864 inst
.operands
[i
].isreg
= 1;
5867 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
5868 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
5870 /* Two kinds of register */
5873 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5875 || (rege
->type
!= REG_TYPE_MMXWR
5876 && rege
->type
!= REG_TYPE_MMXWC
5877 && rege
->type
!= REG_TYPE_MMXWCG
))
5879 inst
.error
= _("iWMMXt data or control register expected");
5882 inst
.operands
[i
].reg
= rege
->number
;
5883 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
5889 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
5891 || (rege
->type
!= REG_TYPE_MMXWC
5892 && rege
->type
!= REG_TYPE_MMXWCG
))
5894 inst
.error
= _("iWMMXt control register expected");
5897 inst
.operands
[i
].reg
= rege
->number
;
5898 inst
.operands
[i
].isreg
= 1;
5903 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
5904 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
5905 case OP_oROR
: val
= parse_ror (&str
); break;
5906 case OP_PSR
: val
= parse_psr (&str
); break;
5907 case OP_COND
: val
= parse_cond (&str
); break;
5908 case OP_oBARRIER
:val
= parse_barrier (&str
); break;
5911 po_reg_or_goto (REG_TYPE_VFC
, try_psr
);
5912 inst
.operands
[i
].isvec
= 1; /* Mark VFP control reg as vector. */
5915 val
= parse_psr (&str
);
5919 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
5922 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
5924 if (strncasecmp (str
, "APSR_", 5) == 0)
5931 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
5932 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
5933 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
5934 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
5935 default: found
= 16;
5939 inst
.operands
[i
].isvec
= 1;
5946 po_misc_or_fail (parse_tb (&str
));
5949 /* Register lists */
5951 val
= parse_reg_list (&str
);
5954 inst
.operands
[1].writeback
= 1;
5960 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
5964 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
5968 /* Allow Q registers too. */
5969 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5974 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5976 inst
.operands
[i
].issingle
= 1;
5981 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
5986 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
5987 &inst
.operands
[i
].vectype
);
5990 /* Addressing modes */
5992 po_misc_or_fail (parse_address (&str
, i
));
5996 po_misc_or_fail_no_backtrack (
5997 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6001 po_misc_or_fail_no_backtrack (
6002 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6006 po_misc_or_fail_no_backtrack (
6007 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6011 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6015 po_misc_or_fail_no_backtrack (
6016 parse_shifter_operand_group_reloc (&str
, i
));
6020 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6024 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6028 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6032 as_fatal (_("unhandled operand code %d"), upat
[i
]);
6035 /* Various value-based sanity checks and shared operations. We
6036 do not signal immediate failures for the register constraints;
6037 this allows a syntax error to take precedence. */
6046 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6047 inst
.error
= BAD_PC
;
6065 inst
.operands
[i
].imm
= val
;
6072 /* If we get here, this operand was successfully parsed. */
6073 inst
.operands
[i
].present
= 1;
6077 inst
.error
= BAD_ARGS
;
6082 /* The parse routine should already have set inst.error, but set a
6083 default here just in case. */
6085 inst
.error
= _("syntax error");
6089 /* Do not backtrack over a trailing optional argument that
6090 absorbed some text. We will only fail again, with the
6091 'garbage following instruction' error message, which is
6092 probably less helpful than the current one. */
6093 if (backtrack_index
== i
&& backtrack_pos
!= str
6094 && upat
[i
+1] == OP_stop
)
6097 inst
.error
= _("syntax error");
6101 /* Try again, skipping the optional argument at backtrack_pos. */
6102 str
= backtrack_pos
;
6103 inst
.error
= backtrack_error
;
6104 inst
.operands
[backtrack_index
].present
= 0;
6105 i
= backtrack_index
;
6109 /* Check that we have parsed all the arguments. */
6110 if (*str
!= '\0' && !inst
.error
)
6111 inst
.error
= _("garbage following instruction");
6113 return inst
.error
? FAIL
: SUCCESS
;
6116 #undef po_char_or_fail
6117 #undef po_reg_or_fail
6118 #undef po_reg_or_goto
6119 #undef po_imm_or_fail
6120 #undef po_scalar_or_fail
6122 /* Shorthand macro for instruction encoding functions issuing errors. */
6123 #define constraint(expr, err) do { \
6131 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6132 instructions are unpredictable if these registers are used. This
6133 is the BadReg predicate in ARM's Thumb-2 documentation. */
6134 #define reject_bad_reg(reg) \
6136 if (reg == REG_SP || reg == REG_PC) \
6138 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6143 /* If REG is R13 (the stack pointer), warn that its use is
6145 #define warn_deprecated_sp(reg) \
6147 if (warn_on_deprecated && reg == REG_SP) \
6148 as_warn (_("use of r13 is deprecated")); \
6151 /* Functions for operand encoding. ARM, then Thumb. */
6153 #define rotate_left(v, n) (v << n | v >> (32 - n))
6155 /* If VAL can be encoded in the immediate field of an ARM instruction,
6156 return the encoded form. Otherwise, return FAIL. */
6159 encode_arm_immediate (unsigned int val
)
6163 for (i
= 0; i
< 32; i
+= 2)
6164 if ((a
= rotate_left (val
, i
)) <= 0xff)
6165 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6170 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6171 return the encoded form. Otherwise, return FAIL. */
6173 encode_thumb32_immediate (unsigned int val
)
6180 for (i
= 1; i
<= 24; i
++)
6183 if ((val
& ~(0xff << i
)) == 0)
6184 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6188 if (val
== ((a
<< 16) | a
))
6190 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6194 if (val
== ((a
<< 16) | a
))
6195 return 0x200 | (a
>> 8);
6199 /* Encode a VFP SP or DP register number into inst.instruction. */
6202 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6204 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6207 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6210 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6213 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6218 first_error (_("D register out of range for selected VFP version"));
6226 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6230 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6234 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6238 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6242 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6246 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6254 /* Encode a <shift> in an ARM-format instruction. The immediate,
6255 if any, is handled by md_apply_fix. */
6257 encode_arm_shift (int i
)
6259 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6260 inst
.instruction
|= SHIFT_ROR
<< 5;
6263 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6264 if (inst
.operands
[i
].immisreg
)
6266 inst
.instruction
|= SHIFT_BY_REG
;
6267 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6270 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6275 encode_arm_shifter_operand (int i
)
6277 if (inst
.operands
[i
].isreg
)
6279 inst
.instruction
|= inst
.operands
[i
].reg
;
6280 encode_arm_shift (i
);
6283 inst
.instruction
|= INST_IMMEDIATE
;
6286 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
6288 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
6290 assert (inst
.operands
[i
].isreg
);
6291 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6293 if (inst
.operands
[i
].preind
)
6297 inst
.error
= _("instruction does not accept preindexed addressing");
6300 inst
.instruction
|= PRE_INDEX
;
6301 if (inst
.operands
[i
].writeback
)
6302 inst
.instruction
|= WRITE_BACK
;
6305 else if (inst
.operands
[i
].postind
)
6307 assert (inst
.operands
[i
].writeback
);
6309 inst
.instruction
|= WRITE_BACK
;
6311 else /* unindexed - only for coprocessor */
6313 inst
.error
= _("instruction does not accept unindexed addressing");
6317 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
6318 && (((inst
.instruction
& 0x000f0000) >> 16)
6319 == ((inst
.instruction
& 0x0000f000) >> 12)))
6320 as_warn ((inst
.instruction
& LOAD_BIT
)
6321 ? _("destination register same as write-back base")
6322 : _("source register same as write-back base"));
6325 /* inst.operands[i] was set up by parse_address. Encode it into an
6326 ARM-format mode 2 load or store instruction. If is_t is true,
6327 reject forms that cannot be used with a T instruction (i.e. not
6330 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
6332 encode_arm_addr_mode_common (i
, is_t
);
6334 if (inst
.operands
[i
].immisreg
)
6336 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
6337 inst
.instruction
|= inst
.operands
[i
].imm
;
6338 if (!inst
.operands
[i
].negative
)
6339 inst
.instruction
|= INDEX_UP
;
6340 if (inst
.operands
[i
].shifted
)
6342 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6343 inst
.instruction
|= SHIFT_ROR
<< 5;
6346 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6347 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6351 else /* immediate offset in inst.reloc */
6353 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6354 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
6358 /* inst.operands[i] was set up by parse_address. Encode it into an
6359 ARM-format mode 3 load or store instruction. Reject forms that
6360 cannot be used with such instructions. If is_t is true, reject
6361 forms that cannot be used with a T instruction (i.e. not
6364 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
6366 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
6368 inst
.error
= _("instruction does not accept scaled register index");
6372 encode_arm_addr_mode_common (i
, is_t
);
6374 if (inst
.operands
[i
].immisreg
)
6376 inst
.instruction
|= inst
.operands
[i
].imm
;
6377 if (!inst
.operands
[i
].negative
)
6378 inst
.instruction
|= INDEX_UP
;
6380 else /* immediate offset in inst.reloc */
6382 inst
.instruction
|= HWOFFSET_IMM
;
6383 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
6384 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
6388 /* inst.operands[i] was set up by parse_address. Encode it into an
6389 ARM-format instruction. Reject all forms which cannot be encoded
6390 into a coprocessor load/store instruction. If wb_ok is false,
6391 reject use of writeback; if unind_ok is false, reject use of
6392 unindexed addressing. If reloc_override is not 0, use it instead
6393 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
6394 (in which case it is preserved). */
6397 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
6399 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
6401 assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
6403 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
6405 assert (!inst
.operands
[i
].writeback
);
6408 inst
.error
= _("instruction does not support unindexed addressing");
6411 inst
.instruction
|= inst
.operands
[i
].imm
;
6412 inst
.instruction
|= INDEX_UP
;
6416 if (inst
.operands
[i
].preind
)
6417 inst
.instruction
|= PRE_INDEX
;
6419 if (inst
.operands
[i
].writeback
)
6421 if (inst
.operands
[i
].reg
== REG_PC
)
6423 inst
.error
= _("pc may not be used with write-back");
6428 inst
.error
= _("instruction does not support writeback");
6431 inst
.instruction
|= WRITE_BACK
;
6435 inst
.reloc
.type
= reloc_override
;
6436 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
6437 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
6438 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
6441 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
6443 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
6449 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
6450 Determine whether it can be performed with a move instruction; if
6451 it can, convert inst.instruction to that move instruction and
6452 return 1; if it can't, convert inst.instruction to a literal-pool
6453 load and return 0. If this is not a valid thing to do in the
6454 current context, set inst.error and return 1.
6456 inst.operands[i] describes the destination register. */
6459 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
6464 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
6468 if ((inst
.instruction
& tbit
) == 0)
6470 inst
.error
= _("invalid pseudo operation");
6473 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
6475 inst
.error
= _("constant expression expected");
6478 if (inst
.reloc
.exp
.X_op
== O_constant
)
6482 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
6484 /* This can be done with a mov(1) instruction. */
6485 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
6486 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
6492 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
6495 /* This can be done with a mov instruction. */
6496 inst
.instruction
&= LITERAL_MASK
;
6497 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
6498 inst
.instruction
|= value
& 0xfff;
6502 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
6505 /* This can be done with a mvn instruction. */
6506 inst
.instruction
&= LITERAL_MASK
;
6507 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
6508 inst
.instruction
|= value
& 0xfff;
6514 if (add_to_lit_pool () == FAIL
)
6516 inst
.error
= _("literal pool insertion failed");
6519 inst
.operands
[1].reg
= REG_PC
;
6520 inst
.operands
[1].isreg
= 1;
6521 inst
.operands
[1].preind
= 1;
6522 inst
.reloc
.pc_rel
= 1;
6523 inst
.reloc
.type
= (thumb_p
6524 ? BFD_RELOC_ARM_THUMB_OFFSET
6526 ? BFD_RELOC_ARM_HWLITERAL
6527 : BFD_RELOC_ARM_LITERAL
));
6531 /* Functions for instruction encoding, sorted by sub-architecture.
6532 First some generics; their names are taken from the conventional
6533 bit positions for register arguments in ARM format instructions. */
6543 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6550 inst
.instruction
|= inst
.operands
[1].reg
;
6556 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6557 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6563 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6564 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6570 unsigned Rn
= inst
.operands
[2].reg
;
6571 /* Enforce restrictions on SWP instruction. */
6572 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
6573 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
6574 _("Rn must not overlap other operands"));
6575 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6576 inst
.instruction
|= inst
.operands
[1].reg
;
6577 inst
.instruction
|= Rn
<< 16;
6583 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6584 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6585 inst
.instruction
|= inst
.operands
[2].reg
;
6591 inst
.instruction
|= inst
.operands
[0].reg
;
6592 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
6593 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
6599 inst
.instruction
|= inst
.operands
[0].imm
;
6605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6606 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
6609 /* ARM instructions, in alphabetical order by function name (except
6610 that wrapper functions appear immediately after the function they
6613 /* This is a pseudo-op of the form "adr rd, label" to be converted
6614 into a relative address of the form "add rd, pc, #label-.-8". */
6619 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6621 /* Frag hacking will turn this into a sub instruction if the offset turns
6622 out to be negative. */
6623 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
6624 inst
.reloc
.pc_rel
= 1;
6625 inst
.reloc
.exp
.X_add_number
-= 8;
6628 /* This is a pseudo-op of the form "adrl rd, label" to be converted
6629 into a relative address of the form:
6630 add rd, pc, #low(label-.-8)"
6631 add rd, rd, #high(label-.-8)" */
6636 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
6638 /* Frag hacking will turn this into a sub instruction if the offset turns
6639 out to be negative. */
6640 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
6641 inst
.reloc
.pc_rel
= 1;
6642 inst
.size
= INSN_SIZE
* 2;
6643 inst
.reloc
.exp
.X_add_number
-= 8;
6649 if (!inst
.operands
[1].present
)
6650 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
6651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6652 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
6653 encode_arm_shifter_operand (2);
6659 if (inst
.operands
[0].present
)
6661 constraint ((inst
.instruction
& 0xf0) != 0x40
6662 && inst
.operands
[0].imm
!= 0xf,
6663 _("bad barrier type"));
6664 inst
.instruction
|= inst
.operands
[0].imm
;
6667 inst
.instruction
|= 0xf;
6673 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
6674 constraint (msb
> 32, _("bit-field extends past end of register"));
6675 /* The instruction encoding stores the LSB and MSB,
6676 not the LSB and width. */
6677 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6678 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
6679 inst
.instruction
|= (msb
- 1) << 16;
6687 /* #0 in second position is alternative syntax for bfc, which is
6688 the same instruction but with REG_PC in the Rm field. */
6689 if (!inst
.operands
[1].isreg
)
6690 inst
.operands
[1].reg
= REG_PC
;
6692 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
6693 constraint (msb
> 32, _("bit-field extends past end of register"));
6694 /* The instruction encoding stores the LSB and MSB,
6695 not the LSB and width. */
6696 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6697 inst
.instruction
|= inst
.operands
[1].reg
;
6698 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6699 inst
.instruction
|= (msb
- 1) << 16;
6705 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
6706 _("bit-field extends past end of register"));
6707 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
6708 inst
.instruction
|= inst
.operands
[1].reg
;
6709 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
6710 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
6713 /* ARM V5 breakpoint instruction (argument parse)
6714 BKPT <16 bit unsigned immediate>
6715 Instruction is not conditional.
6716 The bit pattern given in insns[] has the COND_ALWAYS condition,
6717 and it is an error if the caller tried to override that. */
6722 /* Top 12 of 16 bits to bits 19:8. */
6723 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
6725 /* Bottom 4 of 16 bits to bits 3:0. */
6726 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
6730 encode_branch (int default_reloc
)
6732 if (inst
.operands
[0].hasreloc
)
6734 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
,
6735 _("the only suffix valid here is '(plt)'"));
6736 inst
.reloc
.type
= BFD_RELOC_ARM_PLT32
;
6740 inst
.reloc
.type
= default_reloc
;
6742 inst
.reloc
.pc_rel
= 1;
6749 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6750 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6753 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6760 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6762 if (inst
.cond
== COND_ALWAYS
)
6763 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6765 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
6769 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
6772 /* ARM V5 branch-link-exchange instruction (argument parse)
6773 BLX <target_addr> ie BLX(1)
6774 BLX{<condition>} <Rm> ie BLX(2)
6775 Unfortunately, there are two different opcodes for this mnemonic.
6776 So, the insns[].value is not used, and the code here zaps values
6777 into inst.instruction.
6778 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
6783 if (inst
.operands
[0].isreg
)
6785 /* Arg is a register; the opcode provided by insns[] is correct.
6786 It is not illegal to do "blx pc", just useless. */
6787 if (inst
.operands
[0].reg
== REG_PC
)
6788 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
6790 inst
.instruction
|= inst
.operands
[0].reg
;
6794 /* Arg is an address; this instruction cannot be executed
6795 conditionally, and the opcode must be adjusted. */
6796 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
6797 inst
.instruction
= 0xfa000000;
6799 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
6800 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
6803 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
6810 bfd_boolean want_reloc
;
6812 if (inst
.operands
[0].reg
== REG_PC
)
6813 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
6815 inst
.instruction
|= inst
.operands
[0].reg
;
6816 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
6817 it is for ARMv4t or earlier. */
6818 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
6819 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
6823 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
6828 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
6832 /* ARM v5TEJ. Jump to Jazelle code. */
6837 if (inst
.operands
[0].reg
== REG_PC
)
6838 as_tsktsk (_("use of r15 in bxj is not really useful"));
6840 inst
.instruction
|= inst
.operands
[0].reg
;
6843 /* Co-processor data operation:
6844 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
6845 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
6849 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6850 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
6851 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
6852 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6853 inst
.instruction
|= inst
.operands
[4].reg
;
6854 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6860 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
6861 encode_arm_shifter_operand (1);
6864 /* Transfer between coprocessor and ARM registers.
6865 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
6870 No special properties. */
6877 Rd
= inst
.operands
[2].reg
;
6880 if (inst
.instruction
== 0xee000010
6881 || inst
.instruction
== 0xfe000010)
6883 reject_bad_reg (Rd
);
6886 constraint (Rd
== REG_SP
, BAD_SP
);
6891 if (inst
.instruction
== 0xe000010)
6892 constraint (Rd
== REG_PC
, BAD_PC
);
6896 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6897 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
6898 inst
.instruction
|= Rd
<< 12;
6899 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
6900 inst
.instruction
|= inst
.operands
[4].reg
;
6901 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
6904 /* Transfer between coprocessor register and pair of ARM registers.
6905 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
6910 Two XScale instructions are special cases of these:
6912 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
6913 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
6915 Result unpredictable if Rd or Rn is R15. */
6922 Rd
= inst
.operands
[2].reg
;
6923 Rn
= inst
.operands
[3].reg
;
6927 reject_bad_reg (Rd
);
6928 reject_bad_reg (Rn
);
6932 constraint (Rd
== REG_PC
, BAD_PC
);
6933 constraint (Rn
== REG_PC
, BAD_PC
);
6936 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
6937 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
6938 inst
.instruction
|= Rd
<< 12;
6939 inst
.instruction
|= Rn
<< 16;
6940 inst
.instruction
|= inst
.operands
[4].reg
;
6946 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
6947 if (inst
.operands
[1].present
)
6949 inst
.instruction
|= CPSI_MMOD
;
6950 inst
.instruction
|= inst
.operands
[1].imm
;
6957 inst
.instruction
|= inst
.operands
[0].imm
;
6963 /* There is no IT instruction in ARM mode. We
6964 process it but do not generate code for it. */
6971 int base_reg
= inst
.operands
[0].reg
;
6972 int range
= inst
.operands
[1].imm
;
6974 inst
.instruction
|= base_reg
<< 16;
6975 inst
.instruction
|= range
;
6977 if (inst
.operands
[1].writeback
)
6978 inst
.instruction
|= LDM_TYPE_2_OR_3
;
6980 if (inst
.operands
[0].writeback
)
6982 inst
.instruction
|= WRITE_BACK
;
6983 /* Check for unpredictable uses of writeback. */
6984 if (inst
.instruction
& LOAD_BIT
)
6986 /* Not allowed in LDM type 2. */
6987 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
6988 && ((range
& (1 << REG_PC
)) == 0))
6989 as_warn (_("writeback of base register is UNPREDICTABLE"));
6990 /* Only allowed if base reg not in list for other types. */
6991 else if (range
& (1 << base_reg
))
6992 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
6996 /* Not allowed for type 2. */
6997 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
6998 as_warn (_("writeback of base register is UNPREDICTABLE"));
6999 /* Only allowed if base reg not in list, or first in list. */
7000 else if ((range
& (1 << base_reg
))
7001 && (range
& ((1 << base_reg
) - 1)))
7002 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7007 /* ARMv5TE load-consecutive (argument parse)
7016 constraint (inst
.operands
[0].reg
% 2 != 0,
7017 _("first destination register must be even"));
7018 constraint (inst
.operands
[1].present
7019 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7020 _("can only load two consecutive registers"));
7021 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7022 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7024 if (!inst
.operands
[1].present
)
7025 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7027 if (inst
.instruction
& LOAD_BIT
)
7029 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7030 register and the first register written; we have to diagnose
7031 overlap between the base and the second register written here. */
7033 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7034 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7035 as_warn (_("base register written back, and overlaps "
7036 "second destination register"));
7038 /* For an index-register load, the index register must not overlap the
7039 destination (even if not write-back). */
7040 else if (inst
.operands
[2].immisreg
7041 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7042 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7043 as_warn (_("index register overlaps destination register"));
7046 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7047 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7053 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7054 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7055 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7056 || inst
.operands
[1].negative
7057 /* This can arise if the programmer has written
7059 or if they have mistakenly used a register name as the last
7062 It is very difficult to distinguish between these two cases
7063 because "rX" might actually be a label. ie the register
7064 name has been occluded by a symbol of the same name. So we
7065 just generate a general 'bad addressing mode' type error
7066 message and leave it up to the programmer to discover the
7067 true cause and fix their mistake. */
7068 || (inst
.operands
[1].reg
== REG_PC
),
7071 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7072 || inst
.reloc
.exp
.X_add_number
!= 0,
7073 _("offset must be zero in ARM encoding"));
7075 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7076 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7077 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7083 constraint (inst
.operands
[0].reg
% 2 != 0,
7084 _("even register required"));
7085 constraint (inst
.operands
[1].present
7086 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7087 _("can only load two consecutive registers"));
7088 /* If op 1 were present and equal to PC, this function wouldn't
7089 have been called in the first place. */
7090 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7092 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7093 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7100 if (!inst
.operands
[1].isreg
)
7101 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7103 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7109 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7111 if (inst
.operands
[1].preind
)
7113 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7114 || inst
.reloc
.exp
.X_add_number
!= 0,
7115 _("this instruction requires a post-indexed address"));
7117 inst
.operands
[1].preind
= 0;
7118 inst
.operands
[1].postind
= 1;
7119 inst
.operands
[1].writeback
= 1;
7121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7122 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7125 /* Halfword and signed-byte load/store operations. */
7130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7131 if (!inst
.operands
[1].isreg
)
7132 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7134 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7140 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7142 if (inst
.operands
[1].preind
)
7144 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7145 || inst
.reloc
.exp
.X_add_number
!= 0,
7146 _("this instruction requires a post-indexed address"));
7148 inst
.operands
[1].preind
= 0;
7149 inst
.operands
[1].postind
= 1;
7150 inst
.operands
[1].writeback
= 1;
7152 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7153 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7156 /* Co-processor register load/store.
7157 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7161 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7162 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7163 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7169 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7170 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7171 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7172 && !(inst
.instruction
& 0x00400000))
7173 as_tsktsk (_("Rd and Rm should be different in mla"));
7175 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7176 inst
.instruction
|= inst
.operands
[1].reg
;
7177 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7178 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7185 encode_arm_shifter_operand (1);
7188 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
7195 top
= (inst
.instruction
& 0x00400000) != 0;
7196 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
7197 _(":lower16: not allowed this instruction"));
7198 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
7199 _(":upper16: not allowed instruction"));
7200 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7201 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7203 imm
= inst
.reloc
.exp
.X_add_number
;
7204 /* The value is in two pieces: 0:11, 16:19. */
7205 inst
.instruction
|= (imm
& 0x00000fff);
7206 inst
.instruction
|= (imm
& 0x0000f000) << 4;
7210 static void do_vfp_nsyn_opcode (const char *);
7213 do_vfp_nsyn_mrs (void)
7215 if (inst
.operands
[0].isvec
)
7217 if (inst
.operands
[1].reg
!= 1)
7218 first_error (_("operand 1 must be FPSCR"));
7219 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
7220 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
7221 do_vfp_nsyn_opcode ("fmstat");
7223 else if (inst
.operands
[1].isvec
)
7224 do_vfp_nsyn_opcode ("fmrx");
7232 do_vfp_nsyn_msr (void)
7234 if (inst
.operands
[0].isvec
)
7235 do_vfp_nsyn_opcode ("fmxr");
7245 if (do_vfp_nsyn_mrs () == SUCCESS
)
7248 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
7249 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
7251 _("'CPSR' or 'SPSR' expected"));
7252 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7253 inst
.instruction
|= (inst
.operands
[1].imm
& SPSR_BIT
);
7256 /* Two possible forms:
7257 "{C|S}PSR_<field>, Rm",
7258 "{C|S}PSR_f, #expression". */
7263 if (do_vfp_nsyn_msr () == SUCCESS
)
7266 inst
.instruction
|= inst
.operands
[0].imm
;
7267 if (inst
.operands
[1].isreg
)
7268 inst
.instruction
|= inst
.operands
[1].reg
;
7271 inst
.instruction
|= INST_IMMEDIATE
;
7272 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7273 inst
.reloc
.pc_rel
= 0;
7280 if (!inst
.operands
[2].present
)
7281 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
7282 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7283 inst
.instruction
|= inst
.operands
[1].reg
;
7284 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7286 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7287 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7288 as_tsktsk (_("Rd and Rm should be different in mul"));
7291 /* Long Multiply Parser
7292 UMULL RdLo, RdHi, Rm, Rs
7293 SMULL RdLo, RdHi, Rm, Rs
7294 UMLAL RdLo, RdHi, Rm, Rs
7295 SMLAL RdLo, RdHi, Rm, Rs. */
7300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7301 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7302 inst
.instruction
|= inst
.operands
[2].reg
;
7303 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7305 /* rdhi and rdlo must be different. */
7306 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7307 as_tsktsk (_("rdhi and rdlo must be different"));
7309 /* rdhi, rdlo and rm must all be different before armv6. */
7310 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
7311 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
7312 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7313 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
7319 if (inst
.operands
[0].present
)
7321 /* Architectural NOP hints are CPSR sets with no bits selected. */
7322 inst
.instruction
&= 0xf0000000;
7323 inst
.instruction
|= 0x0320f000 + inst
.operands
[0].imm
;
7327 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
7328 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
7329 Condition defaults to COND_ALWAYS.
7330 Error if Rd, Rn or Rm are R15. */
7335 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7336 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7337 inst
.instruction
|= inst
.operands
[2].reg
;
7338 if (inst
.operands
[3].present
)
7339 encode_arm_shift (3);
7342 /* ARM V6 PKHTB (Argument Parse). */
7347 if (!inst
.operands
[3].present
)
7349 /* If the shift specifier is omitted, turn the instruction
7350 into pkhbt rd, rm, rn. */
7351 inst
.instruction
&= 0xfff00010;
7352 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7353 inst
.instruction
|= inst
.operands
[1].reg
;
7354 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7358 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7359 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7360 inst
.instruction
|= inst
.operands
[2].reg
;
7361 encode_arm_shift (3);
7365 /* ARMv5TE: Preload-Cache
7369 Syntactically, like LDR with B=1, W=0, L=1. */
7374 constraint (!inst
.operands
[0].isreg
,
7375 _("'[' expected after PLD mnemonic"));
7376 constraint (inst
.operands
[0].postind
,
7377 _("post-indexed expression used in preload instruction"));
7378 constraint (inst
.operands
[0].writeback
,
7379 _("writeback used in preload instruction"));
7380 constraint (!inst
.operands
[0].preind
,
7381 _("unindexed addressing used in preload instruction"));
7382 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7385 /* ARMv7: PLI <addr_mode> */
7389 constraint (!inst
.operands
[0].isreg
,
7390 _("'[' expected after PLI mnemonic"));
7391 constraint (inst
.operands
[0].postind
,
7392 _("post-indexed expression used in preload instruction"));
7393 constraint (inst
.operands
[0].writeback
,
7394 _("writeback used in preload instruction"));
7395 constraint (!inst
.operands
[0].preind
,
7396 _("unindexed addressing used in preload instruction"));
7397 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
7398 inst
.instruction
&= ~PRE_INDEX
;
7404 inst
.operands
[1] = inst
.operands
[0];
7405 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
7406 inst
.operands
[0].isreg
= 1;
7407 inst
.operands
[0].writeback
= 1;
7408 inst
.operands
[0].reg
= REG_SP
;
7412 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
7413 word at the specified address and the following word
7415 Unconditionally executed.
7416 Error if Rn is R15. */
7421 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7422 if (inst
.operands
[0].writeback
)
7423 inst
.instruction
|= WRITE_BACK
;
7426 /* ARM V6 ssat (argument parse). */
7431 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7432 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
7433 inst
.instruction
|= inst
.operands
[2].reg
;
7435 if (inst
.operands
[3].present
)
7436 encode_arm_shift (3);
7439 /* ARM V6 usat (argument parse). */
7444 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7445 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7446 inst
.instruction
|= inst
.operands
[2].reg
;
7448 if (inst
.operands
[3].present
)
7449 encode_arm_shift (3);
7452 /* ARM V6 ssat16 (argument parse). */
7457 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7458 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
7459 inst
.instruction
|= inst
.operands
[2].reg
;
7465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7466 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
7467 inst
.instruction
|= inst
.operands
[2].reg
;
7470 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
7471 preserving the other bits.
7473 setend <endian_specifier>, where <endian_specifier> is either
7479 if (inst
.operands
[0].imm
)
7480 inst
.instruction
|= 0x200;
7486 unsigned int Rm
= (inst
.operands
[1].present
7487 ? inst
.operands
[1].reg
7488 : inst
.operands
[0].reg
);
7490 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7491 inst
.instruction
|= Rm
;
7492 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
7494 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7495 inst
.instruction
|= SHIFT_BY_REG
;
7498 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7504 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
7505 inst
.reloc
.pc_rel
= 0;
7511 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
7512 inst
.reloc
.pc_rel
= 0;
7515 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
7516 SMLAxy{cond} Rd,Rm,Rs,Rn
7517 SMLAWy{cond} Rd,Rm,Rs,Rn
7518 Error if any register is R15. */
7523 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7524 inst
.instruction
|= inst
.operands
[1].reg
;
7525 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7526 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7529 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
7530 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
7531 Error if any register is R15.
7532 Warning if Rdlo == Rdhi. */
7537 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7538 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7539 inst
.instruction
|= inst
.operands
[2].reg
;
7540 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
7542 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
7543 as_tsktsk (_("rdhi and rdlo must be different"));
7546 /* ARM V5E (El Segundo) signed-multiply (argument parse)
7547 SMULxy{cond} Rd,Rm,Rs
7548 Error if any register is R15. */
7553 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7554 inst
.instruction
|= inst
.operands
[1].reg
;
7555 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7558 /* ARM V6 srs (argument parse). The variable fields in the encoding are
7559 the same for both ARM and Thumb-2. */
7566 if (inst
.operands
[0].present
)
7568 reg
= inst
.operands
[0].reg
;
7569 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
7574 inst
.instruction
|= reg
<< 16;
7575 inst
.instruction
|= inst
.operands
[1].imm
;
7576 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
7577 inst
.instruction
|= WRITE_BACK
;
7580 /* ARM V6 strex (argument parse). */
7585 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
7586 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
7587 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
7588 || inst
.operands
[2].negative
7589 /* See comment in do_ldrex(). */
7590 || (inst
.operands
[2].reg
== REG_PC
),
7593 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7594 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
7596 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7597 || inst
.reloc
.exp
.X_add_number
!= 0,
7598 _("offset must be zero in ARM encoding"));
7600 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7601 inst
.instruction
|= inst
.operands
[1].reg
;
7602 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7603 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7609 constraint (inst
.operands
[1].reg
% 2 != 0,
7610 _("even register required"));
7611 constraint (inst
.operands
[2].present
7612 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
7613 _("can only store two consecutive registers"));
7614 /* If op 2 were present and equal to PC, this function wouldn't
7615 have been called in the first place. */
7616 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
7618 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
7619 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
7620 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
7623 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7624 inst
.instruction
|= inst
.operands
[1].reg
;
7625 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7628 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
7629 extends it to 32-bits, and adds the result to a value in another
7630 register. You can specify a rotation by 0, 8, 16, or 24 bits
7631 before extracting the 16-bit value.
7632 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
7633 Condition defaults to COND_ALWAYS.
7634 Error if any register uses R15. */
7639 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7640 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7641 inst
.instruction
|= inst
.operands
[2].reg
;
7642 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
7647 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
7648 Condition defaults to COND_ALWAYS.
7649 Error if any register uses R15. */
7654 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7655 inst
.instruction
|= inst
.operands
[1].reg
;
7656 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
7659 /* VFP instructions. In a logical order: SP variant first, monad
7660 before dyad, arithmetic then move then load/store. */
7663 do_vfp_sp_monadic (void)
7665 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7666 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7670 do_vfp_sp_dyadic (void)
7672 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7673 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7674 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7678 do_vfp_sp_compare_z (void)
7680 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7684 do_vfp_dp_sp_cvt (void)
7686 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7687 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
7691 do_vfp_sp_dp_cvt (void)
7693 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7694 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7698 do_vfp_reg_from_sp (void)
7700 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7701 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
7705 do_vfp_reg2_from_sp2 (void)
7707 constraint (inst
.operands
[2].imm
!= 2,
7708 _("only two consecutive VFP SP registers allowed here"));
7709 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7710 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7711 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
7715 do_vfp_sp_from_reg (void)
7717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
7718 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7722 do_vfp_sp2_from_reg2 (void)
7724 constraint (inst
.operands
[0].imm
!= 2,
7725 _("only two consecutive VFP SP registers allowed here"));
7726 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
7727 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7728 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7732 do_vfp_sp_ldst (void)
7734 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7735 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7739 do_vfp_dp_ldst (void)
7741 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7742 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
7747 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
7749 if (inst
.operands
[0].writeback
)
7750 inst
.instruction
|= WRITE_BACK
;
7752 constraint (ldstm_type
!= VFP_LDSTMIA
,
7753 _("this addressing mode requires base-register writeback"));
7754 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7755 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
7756 inst
.instruction
|= inst
.operands
[1].imm
;
7760 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
7764 if (inst
.operands
[0].writeback
)
7765 inst
.instruction
|= WRITE_BACK
;
7767 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
7768 _("this addressing mode requires base-register writeback"));
7770 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7771 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7773 count
= inst
.operands
[1].imm
<< 1;
7774 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
7777 inst
.instruction
|= count
;
7781 do_vfp_sp_ldstmia (void)
7783 vfp_sp_ldstm (VFP_LDSTMIA
);
7787 do_vfp_sp_ldstmdb (void)
7789 vfp_sp_ldstm (VFP_LDSTMDB
);
7793 do_vfp_dp_ldstmia (void)
7795 vfp_dp_ldstm (VFP_LDSTMIA
);
7799 do_vfp_dp_ldstmdb (void)
7801 vfp_dp_ldstm (VFP_LDSTMDB
);
7805 do_vfp_xp_ldstmia (void)
7807 vfp_dp_ldstm (VFP_LDSTMIAX
);
7811 do_vfp_xp_ldstmdb (void)
7813 vfp_dp_ldstm (VFP_LDSTMDBX
);
7817 do_vfp_dp_rd_rm (void)
7819 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7820 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
7824 do_vfp_dp_rn_rd (void)
7826 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
7827 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7831 do_vfp_dp_rd_rn (void)
7833 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7834 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7838 do_vfp_dp_rd_rn_rm (void)
7840 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7841 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
7842 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
7848 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7852 do_vfp_dp_rm_rd_rn (void)
7854 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
7855 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
7856 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
7859 /* VFPv3 instructions. */
7861 do_vfp_sp_const (void)
7863 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7864 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7865 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7869 do_vfp_dp_const (void)
7871 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7872 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
7873 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
7877 vfp_conv (int srcsize
)
7879 unsigned immbits
= srcsize
- inst
.operands
[1].imm
;
7880 inst
.instruction
|= (immbits
& 1) << 5;
7881 inst
.instruction
|= (immbits
>> 1);
7885 do_vfp_sp_conv_16 (void)
7887 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7892 do_vfp_dp_conv_16 (void)
7894 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7899 do_vfp_sp_conv_32 (void)
7901 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
7906 do_vfp_dp_conv_32 (void)
7908 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
7912 /* FPA instructions. Also in a logical order. */
7917 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7918 inst
.instruction
|= inst
.operands
[1].reg
;
7922 do_fpa_ldmstm (void)
7924 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7925 switch (inst
.operands
[1].imm
)
7927 case 1: inst
.instruction
|= CP_T_X
; break;
7928 case 2: inst
.instruction
|= CP_T_Y
; break;
7929 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
7934 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
7936 /* The instruction specified "ea" or "fd", so we can only accept
7937 [Rn]{!}. The instruction does not really support stacking or
7938 unstacking, so we have to emulate these by setting appropriate
7939 bits and offsets. */
7940 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7941 || inst
.reloc
.exp
.X_add_number
!= 0,
7942 _("this instruction does not support indexing"));
7944 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
7945 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
7947 if (!(inst
.instruction
& INDEX_UP
))
7948 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
7950 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
7952 inst
.operands
[2].preind
= 0;
7953 inst
.operands
[2].postind
= 1;
7957 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7960 /* iWMMXt instructions: strictly in alphabetical order. */
7963 do_iwmmxt_tandorc (void)
7965 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
7969 do_iwmmxt_textrc (void)
7971 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7972 inst
.instruction
|= inst
.operands
[1].imm
;
7976 do_iwmmxt_textrm (void)
7978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7979 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7980 inst
.instruction
|= inst
.operands
[2].imm
;
7984 do_iwmmxt_tinsr (void)
7986 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7987 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7988 inst
.instruction
|= inst
.operands
[2].imm
;
7992 do_iwmmxt_tmia (void)
7994 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
7995 inst
.instruction
|= inst
.operands
[1].reg
;
7996 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8000 do_iwmmxt_waligni (void)
8002 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8003 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8004 inst
.instruction
|= inst
.operands
[2].reg
;
8005 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8009 do_iwmmxt_wmerge (void)
8011 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8012 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8013 inst
.instruction
|= inst
.operands
[2].reg
;
8014 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8018 do_iwmmxt_wmov (void)
8020 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8023 inst
.instruction
|= inst
.operands
[1].reg
;
8027 do_iwmmxt_wldstbh (void)
8030 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8032 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8034 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8035 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8039 do_iwmmxt_wldstw (void)
8041 /* RIWR_RIWC clears .isreg for a control register. */
8042 if (!inst
.operands
[0].isreg
)
8044 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8045 inst
.instruction
|= 0xf0000000;
8048 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8049 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8053 do_iwmmxt_wldstd (void)
8055 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8056 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8057 && inst
.operands
[1].immisreg
)
8059 inst
.instruction
&= ~0x1a000ff;
8060 inst
.instruction
|= (0xf << 28);
8061 if (inst
.operands
[1].preind
)
8062 inst
.instruction
|= PRE_INDEX
;
8063 if (!inst
.operands
[1].negative
)
8064 inst
.instruction
|= INDEX_UP
;
8065 if (inst
.operands
[1].writeback
)
8066 inst
.instruction
|= WRITE_BACK
;
8067 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8068 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8069 inst
.instruction
|= inst
.operands
[1].imm
;
8072 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8076 do_iwmmxt_wshufh (void)
8078 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8079 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8080 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8081 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8085 do_iwmmxt_wzero (void)
8087 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8088 inst
.instruction
|= inst
.operands
[0].reg
;
8089 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8090 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8094 do_iwmmxt_wrwrwr_or_imm5 (void)
8096 if (inst
.operands
[2].isreg
)
8099 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8100 _("immediate operand requires iWMMXt2"));
8102 if (inst
.operands
[2].imm
== 0)
8104 switch ((inst
.instruction
>> 20) & 0xf)
8110 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
8111 inst
.operands
[2].imm
= 16;
8112 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
8118 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
8119 inst
.operands
[2].imm
= 32;
8120 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
8127 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
8129 wrn
= (inst
.instruction
>> 16) & 0xf;
8130 inst
.instruction
&= 0xff0fff0f;
8131 inst
.instruction
|= wrn
;
8132 /* Bail out here; the instruction is now assembled. */
8137 /* Map 32 -> 0, etc. */
8138 inst
.operands
[2].imm
&= 0x1f;
8139 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
8143 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
8144 operations first, then control, shift, and load/store. */
8146 /* Insns like "foo X,Y,Z". */
8149 do_mav_triple (void)
8151 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8152 inst
.instruction
|= inst
.operands
[1].reg
;
8153 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8156 /* Insns like "foo W,X,Y,Z".
8157 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
8162 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8163 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8164 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8165 inst
.instruction
|= inst
.operands
[3].reg
;
8168 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
8172 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8175 /* Maverick shift immediate instructions.
8176 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
8177 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
8182 int imm
= inst
.operands
[2].imm
;
8184 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8185 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8187 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
8188 Bits 5-7 of the insn should have bits 4-6 of the immediate.
8189 Bit 4 should be 0. */
8190 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
8192 inst
.instruction
|= imm
;
8195 /* XScale instructions. Also sorted arithmetic before move. */
8197 /* Xscale multiply-accumulate (argument parse)
8200 MIAxycc acc0,Rm,Rs. */
8205 inst
.instruction
|= inst
.operands
[1].reg
;
8206 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8209 /* Xscale move-accumulator-register (argument parse)
8211 MARcc acc0,RdLo,RdHi. */
8216 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8217 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8220 /* Xscale move-register-accumulator (argument parse)
8222 MRAcc RdLo,RdHi,acc0. */
8227 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
8228 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8229 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8232 /* Encoding functions relevant only to Thumb. */
8234 /* inst.operands[i] is a shifted-register operand; encode
8235 it into inst.instruction in the format used by Thumb32. */
8238 encode_thumb32_shifted_operand (int i
)
8240 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
8241 unsigned int shift
= inst
.operands
[i
].shift_kind
;
8243 constraint (inst
.operands
[i
].immisreg
,
8244 _("shift by register not allowed in thumb mode"));
8245 inst
.instruction
|= inst
.operands
[i
].reg
;
8246 if (shift
== SHIFT_RRX
)
8247 inst
.instruction
|= SHIFT_ROR
<< 4;
8250 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8251 _("expression too complex"));
8253 constraint (value
> 32
8254 || (value
== 32 && (shift
== SHIFT_LSL
8255 || shift
== SHIFT_ROR
)),
8256 _("shift expression is too large"));
8260 else if (value
== 32)
8263 inst
.instruction
|= shift
<< 4;
8264 inst
.instruction
|= (value
& 0x1c) << 10;
8265 inst
.instruction
|= (value
& 0x03) << 6;
8270 /* inst.operands[i] was set up by parse_address. Encode it into a
8271 Thumb32 format load or store instruction. Reject forms that cannot
8272 be used with such instructions. If is_t is true, reject forms that
8273 cannot be used with a T instruction; if is_d is true, reject forms
8274 that cannot be used with a D instruction. */
8277 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
8279 bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8281 constraint (!inst
.operands
[i
].isreg
,
8282 _("Instruction does not support =N addresses"));
8284 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8285 if (inst
.operands
[i
].immisreg
)
8287 constraint (is_pc
, _("cannot use register index with PC-relative addressing"));
8288 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
8289 constraint (inst
.operands
[i
].negative
,
8290 _("Thumb does not support negative register indexing"));
8291 constraint (inst
.operands
[i
].postind
,
8292 _("Thumb does not support register post-indexing"));
8293 constraint (inst
.operands
[i
].writeback
,
8294 _("Thumb does not support register indexing with writeback"));
8295 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
8296 _("Thumb supports only LSL in shifted register indexing"));
8298 inst
.instruction
|= inst
.operands
[i
].imm
;
8299 if (inst
.operands
[i
].shifted
)
8301 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8302 _("expression too complex"));
8303 constraint (inst
.reloc
.exp
.X_add_number
< 0
8304 || inst
.reloc
.exp
.X_add_number
> 3,
8305 _("shift out of range"));
8306 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8308 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8310 else if (inst
.operands
[i
].preind
)
8312 constraint (is_pc
&& inst
.operands
[i
].writeback
,
8313 _("cannot use writeback with PC-relative addressing"));
8314 constraint (is_t
&& inst
.operands
[i
].writeback
,
8315 _("cannot use writeback with this instruction"));
8319 inst
.instruction
|= 0x01000000;
8320 if (inst
.operands
[i
].writeback
)
8321 inst
.instruction
|= 0x00200000;
8325 inst
.instruction
|= 0x00000c00;
8326 if (inst
.operands
[i
].writeback
)
8327 inst
.instruction
|= 0x00000100;
8329 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8331 else if (inst
.operands
[i
].postind
)
8333 assert (inst
.operands
[i
].writeback
);
8334 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
8335 constraint (is_t
, _("cannot use post-indexing with this instruction"));
8338 inst
.instruction
|= 0x00200000;
8340 inst
.instruction
|= 0x00000900;
8341 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
8343 else /* unindexed - only for coprocessor */
8344 inst
.error
= _("instruction does not accept unindexed addressing");
8347 /* Table of Thumb instructions which exist in both 16- and 32-bit
8348 encodings (the latter only in post-V6T2 cores). The index is the
8349 value used in the insns table below. When there is more than one
8350 possible 16-bit encoding for the instruction, this table always
8352 Also contains several pseudo-instructions used during relaxation. */
8353 #define T16_32_TAB \
8354 X(adc, 4140, eb400000), \
8355 X(adcs, 4140, eb500000), \
8356 X(add, 1c00, eb000000), \
8357 X(adds, 1c00, eb100000), \
8358 X(addi, 0000, f1000000), \
8359 X(addis, 0000, f1100000), \
8360 X(add_pc,000f, f20f0000), \
8361 X(add_sp,000d, f10d0000), \
8362 X(adr, 000f, f20f0000), \
8363 X(and, 4000, ea000000), \
8364 X(ands, 4000, ea100000), \
8365 X(asr, 1000, fa40f000), \
8366 X(asrs, 1000, fa50f000), \
8367 X(b, e000, f000b000), \
8368 X(bcond, d000, f0008000), \
8369 X(bic, 4380, ea200000), \
8370 X(bics, 4380, ea300000), \
8371 X(cmn, 42c0, eb100f00), \
8372 X(cmp, 2800, ebb00f00), \
8373 X(cpsie, b660, f3af8400), \
8374 X(cpsid, b670, f3af8600), \
8375 X(cpy, 4600, ea4f0000), \
8376 X(dec_sp,80dd, f1ad0d00), \
8377 X(eor, 4040, ea800000), \
8378 X(eors, 4040, ea900000), \
8379 X(inc_sp,00dd, f10d0d00), \
8380 X(ldmia, c800, e8900000), \
8381 X(ldr, 6800, f8500000), \
8382 X(ldrb, 7800, f8100000), \
8383 X(ldrh, 8800, f8300000), \
8384 X(ldrsb, 5600, f9100000), \
8385 X(ldrsh, 5e00, f9300000), \
8386 X(ldr_pc,4800, f85f0000), \
8387 X(ldr_pc2,4800, f85f0000), \
8388 X(ldr_sp,9800, f85d0000), \
8389 X(lsl, 0000, fa00f000), \
8390 X(lsls, 0000, fa10f000), \
8391 X(lsr, 0800, fa20f000), \
8392 X(lsrs, 0800, fa30f000), \
8393 X(mov, 2000, ea4f0000), \
8394 X(movs, 2000, ea5f0000), \
8395 X(mul, 4340, fb00f000), \
8396 X(muls, 4340, ffffffff), /* no 32b muls */ \
8397 X(mvn, 43c0, ea6f0000), \
8398 X(mvns, 43c0, ea7f0000), \
8399 X(neg, 4240, f1c00000), /* rsb #0 */ \
8400 X(negs, 4240, f1d00000), /* rsbs #0 */ \
8401 X(orr, 4300, ea400000), \
8402 X(orrs, 4300, ea500000), \
8403 X(pop, bc00, e8bd0000), /* ldmia sp!,... */ \
8404 X(push, b400, e92d0000), /* stmdb sp!,... */ \
8405 X(rev, ba00, fa90f080), \
8406 X(rev16, ba40, fa90f090), \
8407 X(revsh, bac0, fa90f0b0), \
8408 X(ror, 41c0, fa60f000), \
8409 X(rors, 41c0, fa70f000), \
8410 X(sbc, 4180, eb600000), \
8411 X(sbcs, 4180, eb700000), \
8412 X(stmia, c000, e8800000), \
8413 X(str, 6000, f8400000), \
8414 X(strb, 7000, f8000000), \
8415 X(strh, 8000, f8200000), \
8416 X(str_sp,9000, f84d0000), \
8417 X(sub, 1e00, eba00000), \
8418 X(subs, 1e00, ebb00000), \
8419 X(subi, 8000, f1a00000), \
8420 X(subis, 8000, f1b00000), \
8421 X(sxtb, b240, fa4ff080), \
8422 X(sxth, b200, fa0ff080), \
8423 X(tst, 4200, ea100f00), \
8424 X(uxtb, b2c0, fa5ff080), \
8425 X(uxth, b280, fa1ff080), \
8426 X(nop, bf00, f3af8000), \
8427 X(yield, bf10, f3af8001), \
8428 X(wfe, bf20, f3af8002), \
8429 X(wfi, bf30, f3af8003), \
8430 X(sev, bf40, f3af9004), /* typo, 8004? */
8432 /* To catch errors in encoding functions, the codes are all offset by
8433 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
8434 as 16-bit instructions. */
8435 #define X(a,b,c) T_MNEM_##a
8436 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
8439 #define X(a,b,c) 0x##b
8440 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
8441 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
8444 #define X(a,b,c) 0x##c
8445 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
8446 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
8447 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
8451 /* Thumb instruction encoders, in alphabetical order. */
8455 do_t_add_sub_w (void)
8459 Rd
= inst
.operands
[0].reg
;
8460 Rn
= inst
.operands
[1].reg
;
8462 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this is the
8463 SP-{plus,minute}-immediate form of the instruction. */
8464 reject_bad_reg (Rd
);
8466 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
8467 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8470 /* Parse an add or subtract instruction. We get here with inst.instruction
8471 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
8478 Rd
= inst
.operands
[0].reg
;
8479 Rs
= (inst
.operands
[1].present
8480 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8481 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8489 flags
= (inst
.instruction
== T_MNEM_adds
8490 || inst
.instruction
== T_MNEM_subs
);
8492 narrow
= (current_it_mask
== 0);
8494 narrow
= (current_it_mask
!= 0);
8495 if (!inst
.operands
[2].isreg
)
8499 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8501 add
= (inst
.instruction
== T_MNEM_add
8502 || inst
.instruction
== T_MNEM_adds
);
8504 if (inst
.size_req
!= 4)
8506 /* Attempt to use a narrow opcode, with relaxation if
8508 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
8509 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
8510 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
8511 opcode
= T_MNEM_add_sp
;
8512 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
8513 opcode
= T_MNEM_add_pc
;
8514 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
8517 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
8519 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
8523 inst
.instruction
= THUMB_OP16(opcode
);
8524 inst
.instruction
|= (Rd
<< 4) | Rs
;
8525 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8526 if (inst
.size_req
!= 2)
8527 inst
.relax
= opcode
;
8530 constraint (inst
.size_req
== 2, BAD_HIREG
);
8532 if (inst
.size_req
== 4
8533 || (inst
.size_req
!= 2 && !opcode
))
8537 constraint (add
, BAD_PC
);
8538 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
8539 _("only SUBS PC, LR, #const allowed"));
8540 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
8541 _("expression too complex"));
8542 constraint (inst
.reloc
.exp
.X_add_number
< 0
8543 || inst
.reloc
.exp
.X_add_number
> 0xff,
8544 _("immediate value out of range"));
8545 inst
.instruction
= T2_SUBS_PC_LR
8546 | inst
.reloc
.exp
.X_add_number
;
8547 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8550 else if (Rs
== REG_PC
)
8552 /* Always use addw/subw. */
8553 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
8554 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
8558 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8559 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
8562 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8564 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
8566 inst
.instruction
|= Rd
<< 8;
8567 inst
.instruction
|= Rs
<< 16;
8572 Rn
= inst
.operands
[2].reg
;
8573 /* See if we can do this with a 16-bit instruction. */
8574 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
8576 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8581 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
8582 || inst
.instruction
== T_MNEM_add
)
8585 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8589 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
8591 /* Thumb-1 cores (except v6-M) require at least one high
8592 register in a narrow non flag setting add. */
8593 if (Rd
> 7 || Rn
> 7
8594 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
8595 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
8602 inst
.instruction
= T_OPCODE_ADD_HI
;
8603 inst
.instruction
|= (Rd
& 8) << 4;
8604 inst
.instruction
|= (Rd
& 7);
8605 inst
.instruction
|= Rn
<< 3;
8611 constraint (Rd
== REG_PC
, BAD_PC
);
8612 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
8613 constraint (Rs
== REG_PC
, BAD_PC
);
8614 reject_bad_reg (Rn
);
8616 /* If we get here, it can't be done in 16 bits. */
8617 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
8618 _("shift must be constant"));
8619 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8620 inst
.instruction
|= Rd
<< 8;
8621 inst
.instruction
|= Rs
<< 16;
8622 encode_thumb32_shifted_operand (2);
8627 constraint (inst
.instruction
== T_MNEM_adds
8628 || inst
.instruction
== T_MNEM_subs
,
8631 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
8633 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
8634 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
8637 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8639 inst
.instruction
|= (Rd
<< 4) | Rs
;
8640 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8644 Rn
= inst
.operands
[2].reg
;
8645 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
8647 /* We now have Rd, Rs, and Rn set to registers. */
8648 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
8650 /* Can't do this for SUB. */
8651 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
8652 inst
.instruction
= T_OPCODE_ADD_HI
;
8653 inst
.instruction
|= (Rd
& 8) << 4;
8654 inst
.instruction
|= (Rd
& 7);
8656 inst
.instruction
|= Rn
<< 3;
8658 inst
.instruction
|= Rs
<< 3;
8660 constraint (1, _("dest must overlap one source register"));
8664 inst
.instruction
= (inst
.instruction
== T_MNEM_add
8665 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
8666 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
8676 Rd
= inst
.operands
[0].reg
;
8677 reject_bad_reg (Rd
);
8679 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
8681 /* Defer to section relaxation. */
8682 inst
.relax
= inst
.instruction
;
8683 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8684 inst
.instruction
|= Rd
<< 4;
8686 else if (unified_syntax
&& inst
.size_req
!= 2)
8688 /* Generate a 32-bit opcode. */
8689 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8690 inst
.instruction
|= Rd
<< 8;
8691 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
8692 inst
.reloc
.pc_rel
= 1;
8696 /* Generate a 16-bit opcode. */
8697 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8698 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
8699 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
8700 inst
.reloc
.pc_rel
= 1;
8702 inst
.instruction
|= Rd
<< 4;
8706 /* Arithmetic instructions for which there is just one 16-bit
8707 instruction encoding, and it allows only two low registers.
8708 For maximal compatibility with ARM syntax, we allow three register
8709 operands even when Thumb-32 instructions are not available, as long
8710 as the first two are identical. For instance, both "sbc r0,r1" and
8711 "sbc r0,r0,r1" are allowed. */
8717 Rd
= inst
.operands
[0].reg
;
8718 Rs
= (inst
.operands
[1].present
8719 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8720 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8721 Rn
= inst
.operands
[2].reg
;
8723 reject_bad_reg (Rd
);
8724 reject_bad_reg (Rs
);
8725 if (inst
.operands
[2].isreg
)
8726 reject_bad_reg (Rn
);
8730 if (!inst
.operands
[2].isreg
)
8732 /* For an immediate, we always generate a 32-bit opcode;
8733 section relaxation will shrink it later if possible. */
8734 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8735 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8736 inst
.instruction
|= Rd
<< 8;
8737 inst
.instruction
|= Rs
<< 16;
8738 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8744 /* See if we can do this with a 16-bit instruction. */
8745 if (THUMB_SETS_FLAGS (inst
.instruction
))
8746 narrow
= current_it_mask
== 0;
8748 narrow
= current_it_mask
!= 0;
8750 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8752 if (inst
.operands
[2].shifted
)
8754 if (inst
.size_req
== 4)
8760 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8761 inst
.instruction
|= Rd
;
8762 inst
.instruction
|= Rn
<< 3;
8766 /* If we get here, it can't be done in 16 bits. */
8767 constraint (inst
.operands
[2].shifted
8768 && inst
.operands
[2].immisreg
,
8769 _("shift must be constant"));
8770 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8771 inst
.instruction
|= Rd
<< 8;
8772 inst
.instruction
|= Rs
<< 16;
8773 encode_thumb32_shifted_operand (2);
8778 /* On its face this is a lie - the instruction does set the
8779 flags. However, the only supported mnemonic in this mode
8781 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8783 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8784 _("unshifted register required"));
8785 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8786 constraint (Rd
!= Rs
,
8787 _("dest and source1 must be the same register"));
8789 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8790 inst
.instruction
|= Rd
;
8791 inst
.instruction
|= Rn
<< 3;
8795 /* Similarly, but for instructions where the arithmetic operation is
8796 commutative, so we can allow either of them to be different from
8797 the destination operand in a 16-bit instruction. For instance, all
8798 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
8805 Rd
= inst
.operands
[0].reg
;
8806 Rs
= (inst
.operands
[1].present
8807 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
8808 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
8809 Rn
= inst
.operands
[2].reg
;
8811 reject_bad_reg (Rd
);
8812 reject_bad_reg (Rs
);
8813 if (inst
.operands
[2].isreg
)
8814 reject_bad_reg (Rn
);
8818 if (!inst
.operands
[2].isreg
)
8820 /* For an immediate, we always generate a 32-bit opcode;
8821 section relaxation will shrink it later if possible. */
8822 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8823 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
8824 inst
.instruction
|= Rd
<< 8;
8825 inst
.instruction
|= Rs
<< 16;
8826 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
8832 /* See if we can do this with a 16-bit instruction. */
8833 if (THUMB_SETS_FLAGS (inst
.instruction
))
8834 narrow
= current_it_mask
== 0;
8836 narrow
= current_it_mask
!= 0;
8838 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
8840 if (inst
.operands
[2].shifted
)
8842 if (inst
.size_req
== 4)
8849 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8850 inst
.instruction
|= Rd
;
8851 inst
.instruction
|= Rn
<< 3;
8856 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8857 inst
.instruction
|= Rd
;
8858 inst
.instruction
|= Rs
<< 3;
8863 /* If we get here, it can't be done in 16 bits. */
8864 constraint (inst
.operands
[2].shifted
8865 && inst
.operands
[2].immisreg
,
8866 _("shift must be constant"));
8867 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
8868 inst
.instruction
|= Rd
<< 8;
8869 inst
.instruction
|= Rs
<< 16;
8870 encode_thumb32_shifted_operand (2);
8875 /* On its face this is a lie - the instruction does set the
8876 flags. However, the only supported mnemonic in this mode
8878 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
8880 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
8881 _("unshifted register required"));
8882 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
8884 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
8885 inst
.instruction
|= Rd
;
8888 inst
.instruction
|= Rn
<< 3;
8890 inst
.instruction
|= Rs
<< 3;
8892 constraint (1, _("dest must overlap one source register"));
8899 if (inst
.operands
[0].present
)
8901 constraint ((inst
.instruction
& 0xf0) != 0x40
8902 && inst
.operands
[0].imm
!= 0xf,
8903 _("bad barrier type"));
8904 inst
.instruction
|= inst
.operands
[0].imm
;
8907 inst
.instruction
|= 0xf;
8914 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8915 constraint (msb
> 32, _("bit-field extends past end of register"));
8916 /* The instruction encoding stores the LSB and MSB,
8917 not the LSB and width. */
8918 Rd
= inst
.operands
[0].reg
;
8919 reject_bad_reg (Rd
);
8920 inst
.instruction
|= Rd
<< 8;
8921 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
8922 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
8923 inst
.instruction
|= msb
- 1;
8932 Rd
= inst
.operands
[0].reg
;
8933 reject_bad_reg (Rd
);
8935 /* #0 in second position is alternative syntax for bfc, which is
8936 the same instruction but with REG_PC in the Rm field. */
8937 if (!inst
.operands
[1].isreg
)
8941 Rn
= inst
.operands
[1].reg
;
8942 reject_bad_reg (Rn
);
8945 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8946 constraint (msb
> 32, _("bit-field extends past end of register"));
8947 /* The instruction encoding stores the LSB and MSB,
8948 not the LSB and width. */
8949 inst
.instruction
|= Rd
<< 8;
8950 inst
.instruction
|= Rn
<< 16;
8951 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8952 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8953 inst
.instruction
|= msb
- 1;
8961 Rd
= inst
.operands
[0].reg
;
8962 Rn
= inst
.operands
[1].reg
;
8964 reject_bad_reg (Rd
);
8965 reject_bad_reg (Rn
);
8967 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8968 _("bit-field extends past end of register"));
8969 inst
.instruction
|= Rd
<< 8;
8970 inst
.instruction
|= Rn
<< 16;
8971 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
8972 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
8973 inst
.instruction
|= inst
.operands
[3].imm
- 1;
8976 /* ARM V5 Thumb BLX (argument parse)
8977 BLX <target_addr> which is BLX(1)
8978 BLX <Rm> which is BLX(2)
8979 Unfortunately, there are two different opcodes for this mnemonic.
8980 So, the insns[].value is not used, and the code here zaps values
8981 into inst.instruction.
8983 ??? How to take advantage of the additional two bits of displacement
8984 available in Thumb32 mode? Need new relocation? */
8989 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
8990 if (inst
.operands
[0].isreg
)
8992 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8993 /* We have a register, so this is BLX(2). */
8994 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
8998 /* No register. This must be BLX(1). */
8999 inst
.instruction
= 0xf000e800;
9001 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9002 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9005 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BLX
;
9006 inst
.reloc
.pc_rel
= 1;
9016 if (current_it_mask
)
9018 /* Conditional branches inside IT blocks are encoded as unconditional
9021 /* A branch must be the last instruction in an IT block. */
9022 constraint (current_it_mask
!= 0x10, BAD_BRANCH
);
9027 if (cond
!= COND_ALWAYS
)
9028 opcode
= T_MNEM_bcond
;
9030 opcode
= inst
.instruction
;
9032 if (unified_syntax
&& inst
.size_req
== 4)
9034 inst
.instruction
= THUMB_OP32(opcode
);
9035 if (cond
== COND_ALWAYS
)
9036 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9039 assert (cond
!= 0xF);
9040 inst
.instruction
|= cond
<< 22;
9041 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9046 inst
.instruction
= THUMB_OP16(opcode
);
9047 if (cond
== COND_ALWAYS
)
9048 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9051 inst
.instruction
|= cond
<< 8;
9052 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9054 /* Allow section relaxation. */
9055 if (unified_syntax
&& inst
.size_req
!= 2)
9056 inst
.relax
= opcode
;
9059 inst
.reloc
.pc_rel
= 1;
9065 constraint (inst
.cond
!= COND_ALWAYS
,
9066 _("instruction is always unconditional"));
9067 if (inst
.operands
[0].present
)
9069 constraint (inst
.operands
[0].imm
> 255,
9070 _("immediate value out of range"));
9071 inst
.instruction
|= inst
.operands
[0].imm
;
9076 do_t_branch23 (void)
9078 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9079 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9080 inst
.reloc
.pc_rel
= 1;
9082 /* If the destination of the branch is a defined symbol which does not have
9083 the THUMB_FUNC attribute, then we must be calling a function which has
9084 the (interfacearm) attribute. We look for the Thumb entry point to that
9085 function and change the branch to refer to that function instead. */
9086 if ( inst
.reloc
.exp
.X_op
== O_symbol
9087 && inst
.reloc
.exp
.X_add_symbol
!= NULL
9088 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
9089 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
9090 inst
.reloc
.exp
.X_add_symbol
=
9091 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
9097 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9098 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9099 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
9100 should cause the alignment to be checked once it is known. This is
9101 because BX PC only works if the instruction is word aligned. */
9109 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
9110 Rm
= inst
.operands
[0].reg
;
9111 reject_bad_reg (Rm
);
9112 inst
.instruction
|= Rm
<< 16;
9121 Rd
= inst
.operands
[0].reg
;
9122 Rm
= inst
.operands
[1].reg
;
9124 reject_bad_reg (Rd
);
9125 reject_bad_reg (Rm
);
9127 inst
.instruction
|= Rd
<< 8;
9128 inst
.instruction
|= Rm
<< 16;
9129 inst
.instruction
|= Rm
;
9135 constraint (current_it_mask
, BAD_NOT_IT
);
9136 inst
.instruction
|= inst
.operands
[0].imm
;
9142 constraint (current_it_mask
, BAD_NOT_IT
);
9144 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
9145 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
9147 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
9148 inst
.instruction
= 0xf3af8000;
9149 inst
.instruction
|= imod
<< 9;
9150 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
9151 if (inst
.operands
[1].present
)
9152 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
9156 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
9157 && (inst
.operands
[0].imm
& 4),
9158 _("selected processor does not support 'A' form "
9159 "of this instruction"));
9160 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
9161 _("Thumb does not support the 2-argument "
9162 "form of this instruction"));
9163 inst
.instruction
|= inst
.operands
[0].imm
;
9167 /* THUMB CPY instruction (argument parse). */
9172 if (inst
.size_req
== 4)
9174 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
9175 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9176 inst
.instruction
|= inst
.operands
[1].reg
;
9180 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
9181 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
9182 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9189 constraint (current_it_mask
, BAD_NOT_IT
);
9190 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9191 inst
.instruction
|= inst
.operands
[0].reg
;
9192 inst
.reloc
.pc_rel
= 1;
9193 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
9199 inst
.instruction
|= inst
.operands
[0].imm
;
9205 unsigned Rd
, Rn
, Rm
;
9207 Rd
= inst
.operands
[0].reg
;
9208 Rn
= (inst
.operands
[1].present
9209 ? inst
.operands
[1].reg
: Rd
);
9210 Rm
= inst
.operands
[2].reg
;
9212 reject_bad_reg (Rd
);
9213 reject_bad_reg (Rn
);
9214 reject_bad_reg (Rm
);
9216 inst
.instruction
|= Rd
<< 8;
9217 inst
.instruction
|= Rn
<< 16;
9218 inst
.instruction
|= Rm
;
9224 if (unified_syntax
&& inst
.size_req
== 4)
9225 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9227 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9233 unsigned int cond
= inst
.operands
[0].imm
;
9235 constraint (current_it_mask
, BAD_NOT_IT
);
9236 current_it_mask
= (inst
.instruction
& 0xf) | 0x10;
9239 /* If the condition is a negative condition, invert the mask. */
9240 if ((cond
& 0x1) == 0x0)
9242 unsigned int mask
= inst
.instruction
& 0x000f;
9244 if ((mask
& 0x7) == 0)
9245 /* no conversion needed */;
9246 else if ((mask
& 0x3) == 0)
9248 else if ((mask
& 0x1) == 0)
9253 inst
.instruction
&= 0xfff0;
9254 inst
.instruction
|= mask
;
9257 inst
.instruction
|= cond
<< 4;
9260 /* Helper function used for both push/pop and ldm/stm. */
9262 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
9266 load
= (inst
.instruction
& (1 << 20)) != 0;
9268 if (mask
& (1 << 13))
9269 inst
.error
= _("SP not allowed in register list");
9272 if (mask
& (1 << 14)
9273 && mask
& (1 << 15))
9274 inst
.error
= _("LR and PC should not both be in register list");
9276 if ((mask
& (1 << base
)) != 0
9278 as_warn (_("base register should not be in register list "
9279 "when written back"));
9283 if (mask
& (1 << 15))
9284 inst
.error
= _("PC not allowed in register list");
9286 if (mask
& (1 << base
))
9287 as_warn (_("value stored for r%d is UNPREDICTABLE"), base
);
9290 if ((mask
& (mask
- 1)) == 0)
9292 /* Single register transfers implemented as str/ldr. */
9295 if (inst
.instruction
& (1 << 23))
9296 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
9298 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
9302 if (inst
.instruction
& (1 << 23))
9303 inst
.instruction
= 0x00800000; /* ia -> [base] */
9305 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
9308 inst
.instruction
|= 0xf8400000;
9310 inst
.instruction
|= 0x00100000;
9312 mask
= ffs (mask
) - 1;
9316 inst
.instruction
|= WRITE_BACK
;
9318 inst
.instruction
|= mask
;
9319 inst
.instruction
|= base
<< 16;
9325 /* This really doesn't seem worth it. */
9326 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
9327 _("expression too complex"));
9328 constraint (inst
.operands
[1].writeback
,
9329 _("Thumb load/store multiple does not support {reglist}^"));
9337 /* See if we can use a 16-bit instruction. */
9338 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
9339 && inst
.size_req
!= 4
9340 && !(inst
.operands
[1].imm
& ~0xff))
9342 mask
= 1 << inst
.operands
[0].reg
;
9344 if (inst
.operands
[0].reg
<= 7
9345 && (inst
.instruction
== T_MNEM_stmia
9346 ? inst
.operands
[0].writeback
9347 : (inst
.operands
[0].writeback
9348 == !(inst
.operands
[1].imm
& mask
))))
9350 if (inst
.instruction
== T_MNEM_stmia
9351 && (inst
.operands
[1].imm
& mask
)
9352 && (inst
.operands
[1].imm
& (mask
- 1)))
9353 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9354 inst
.operands
[0].reg
);
9356 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9357 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9358 inst
.instruction
|= inst
.operands
[1].imm
;
9361 else if (inst
.operands
[0] .reg
== REG_SP
9362 && inst
.operands
[0].writeback
)
9364 inst
.instruction
= THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
9365 ? T_MNEM_push
: T_MNEM_pop
);
9366 inst
.instruction
|= inst
.operands
[1].imm
;
9373 if (inst
.instruction
< 0xffff)
9374 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9376 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
9377 inst
.operands
[0].writeback
);
9382 constraint (inst
.operands
[0].reg
> 7
9383 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
9384 constraint (inst
.instruction
!= T_MNEM_ldmia
9385 && inst
.instruction
!= T_MNEM_stmia
,
9386 _("Thumb-2 instruction only valid in unified syntax"));
9387 if (inst
.instruction
== T_MNEM_stmia
)
9389 if (!inst
.operands
[0].writeback
)
9390 as_warn (_("this instruction will write back the base register"));
9391 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
9392 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
9393 as_warn (_("value stored for r%d is UNPREDICTABLE"),
9394 inst
.operands
[0].reg
);
9398 if (!inst
.operands
[0].writeback
9399 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9400 as_warn (_("this instruction will write back the base register"));
9401 else if (inst
.operands
[0].writeback
9402 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
9403 as_warn (_("this instruction will not write back the base register"));
9406 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9407 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9408 inst
.instruction
|= inst
.operands
[1].imm
;
9415 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9416 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9417 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9418 || inst
.operands
[1].negative
,
9421 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9422 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9423 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
9429 if (!inst
.operands
[1].present
)
9431 constraint (inst
.operands
[0].reg
== REG_LR
,
9432 _("r14 not allowed as first register "
9433 "when second register is omitted"));
9434 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9436 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
9439 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9440 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9441 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9447 unsigned long opcode
;
9450 opcode
= inst
.instruction
;
9453 if (!inst
.operands
[1].isreg
)
9455 if (opcode
<= 0xffff)
9456 inst
.instruction
= THUMB_OP32 (opcode
);
9457 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9460 if (inst
.operands
[1].isreg
9461 && !inst
.operands
[1].writeback
9462 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
9463 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
9465 && inst
.size_req
!= 4)
9467 /* Insn may have a 16-bit form. */
9468 Rn
= inst
.operands
[1].reg
;
9469 if (inst
.operands
[1].immisreg
)
9471 inst
.instruction
= THUMB_OP16 (opcode
);
9473 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
9476 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
9477 && opcode
!= T_MNEM_ldrsb
)
9478 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
9479 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
9486 if (inst
.reloc
.pc_rel
)
9487 opcode
= T_MNEM_ldr_pc2
;
9489 opcode
= T_MNEM_ldr_pc
;
9493 if (opcode
== T_MNEM_ldr
)
9494 opcode
= T_MNEM_ldr_sp
;
9496 opcode
= T_MNEM_str_sp
;
9498 inst
.instruction
= inst
.operands
[0].reg
<< 8;
9502 inst
.instruction
= inst
.operands
[0].reg
;
9503 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9505 inst
.instruction
|= THUMB_OP16 (opcode
);
9506 if (inst
.size_req
== 2)
9507 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9509 inst
.relax
= opcode
;
9513 /* Definitely a 32-bit variant. */
9514 inst
.instruction
= THUMB_OP32 (opcode
);
9515 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9516 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
9520 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
9522 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
9524 /* Only [Rn,Rm] is acceptable. */
9525 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
9526 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
9527 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
9528 || inst
.operands
[1].negative
,
9529 _("Thumb does not support this addressing mode"));
9530 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9534 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9535 if (!inst
.operands
[1].isreg
)
9536 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
9539 constraint (!inst
.operands
[1].preind
9540 || inst
.operands
[1].shifted
9541 || inst
.operands
[1].writeback
,
9542 _("Thumb does not support this addressing mode"));
9543 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
9545 constraint (inst
.instruction
& 0x0600,
9546 _("byte or halfword not valid for base register"));
9547 constraint (inst
.operands
[1].reg
== REG_PC
9548 && !(inst
.instruction
& THUMB_LOAD_BIT
),
9549 _("r15 based store not allowed"));
9550 constraint (inst
.operands
[1].immisreg
,
9551 _("invalid base register for register offset"));
9553 if (inst
.operands
[1].reg
== REG_PC
)
9554 inst
.instruction
= T_OPCODE_LDR_PC
;
9555 else if (inst
.instruction
& THUMB_LOAD_BIT
)
9556 inst
.instruction
= T_OPCODE_LDR_SP
;
9558 inst
.instruction
= T_OPCODE_STR_SP
;
9560 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9561 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9565 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
9566 if (!inst
.operands
[1].immisreg
)
9568 /* Immediate offset. */
9569 inst
.instruction
|= inst
.operands
[0].reg
;
9570 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9571 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
9575 /* Register offset. */
9576 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
9577 constraint (inst
.operands
[1].negative
,
9578 _("Thumb does not support this addressing mode"));
9581 switch (inst
.instruction
)
9583 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
9584 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
9585 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
9586 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
9587 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
9588 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
9589 case 0x5600 /* ldrsb */:
9590 case 0x5e00 /* ldrsh */: break;
9594 inst
.instruction
|= inst
.operands
[0].reg
;
9595 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
9596 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
9602 if (!inst
.operands
[1].present
)
9604 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9605 constraint (inst
.operands
[0].reg
== REG_LR
,
9606 _("r14 not allowed here"));
9608 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9609 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
9610 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
9616 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9617 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
9623 unsigned Rd
, Rn
, Rm
, Ra
;
9625 Rd
= inst
.operands
[0].reg
;
9626 Rn
= inst
.operands
[1].reg
;
9627 Rm
= inst
.operands
[2].reg
;
9628 Ra
= inst
.operands
[3].reg
;
9630 reject_bad_reg (Rd
);
9631 reject_bad_reg (Rn
);
9632 reject_bad_reg (Rm
);
9633 reject_bad_reg (Ra
);
9635 inst
.instruction
|= Rd
<< 8;
9636 inst
.instruction
|= Rn
<< 16;
9637 inst
.instruction
|= Rm
;
9638 inst
.instruction
|= Ra
<< 12;
9644 unsigned RdLo
, RdHi
, Rn
, Rm
;
9646 RdLo
= inst
.operands
[0].reg
;
9647 RdHi
= inst
.operands
[1].reg
;
9648 Rn
= inst
.operands
[2].reg
;
9649 Rm
= inst
.operands
[3].reg
;
9651 reject_bad_reg (RdLo
);
9652 reject_bad_reg (RdHi
);
9653 reject_bad_reg (Rn
);
9654 reject_bad_reg (Rm
);
9656 inst
.instruction
|= RdLo
<< 12;
9657 inst
.instruction
|= RdHi
<< 8;
9658 inst
.instruction
|= Rn
<< 16;
9659 inst
.instruction
|= Rm
;
9667 Rn
= inst
.operands
[0].reg
;
9668 Rm
= inst
.operands
[1].reg
;
9672 int r0off
= (inst
.instruction
== T_MNEM_mov
9673 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
9674 unsigned long opcode
;
9676 bfd_boolean low_regs
;
9678 low_regs
= (Rn
<= 7 && Rm
<= 7);
9679 opcode
= inst
.instruction
;
9680 if (current_it_mask
)
9681 narrow
= opcode
!= T_MNEM_movs
;
9683 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
9684 if (inst
.size_req
== 4
9685 || inst
.operands
[1].shifted
)
9688 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
9689 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
9690 && !inst
.operands
[1].shifted
9694 inst
.instruction
= T2_SUBS_PC_LR
;
9698 if (opcode
== T_MNEM_cmp
)
9700 constraint (Rn
== REG_PC
, BAD_PC
);
9703 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
9705 warn_deprecated_sp (Rm
);
9706 /* R15 was documented as a valid choice for Rm in ARMv6,
9707 but as UNPREDICTABLE in ARMv7. ARM's proprietary
9708 tools reject R15, so we do too. */
9709 constraint (Rm
== REG_PC
, BAD_PC
);
9712 reject_bad_reg (Rm
);
9714 else if (opcode
== T_MNEM_mov
9715 || opcode
== T_MNEM_movs
)
9717 if (inst
.operands
[1].isreg
)
9719 if (opcode
== T_MNEM_movs
)
9721 reject_bad_reg (Rn
);
9722 reject_bad_reg (Rm
);
9724 else if ((Rn
== REG_SP
|| Rn
== REG_PC
)
9725 && (Rm
== REG_SP
|| Rm
== REG_PC
))
9726 reject_bad_reg (Rm
);
9729 reject_bad_reg (Rn
);
9732 if (!inst
.operands
[1].isreg
)
9734 /* Immediate operand. */
9735 if (current_it_mask
== 0 && opcode
== T_MNEM_mov
)
9737 if (low_regs
&& narrow
)
9739 inst
.instruction
= THUMB_OP16 (opcode
);
9740 inst
.instruction
|= Rn
<< 8;
9741 if (inst
.size_req
== 2)
9742 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9744 inst
.relax
= opcode
;
9748 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9749 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9750 inst
.instruction
|= Rn
<< r0off
;
9751 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9754 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
9755 && (inst
.instruction
== T_MNEM_mov
9756 || inst
.instruction
== T_MNEM_movs
))
9758 /* Register shifts are encoded as separate shift instructions. */
9759 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
9761 if (current_it_mask
)
9766 if (inst
.size_req
== 4)
9769 if (!low_regs
|| inst
.operands
[1].imm
> 7)
9775 switch (inst
.operands
[1].shift_kind
)
9778 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
9781 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
9784 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
9787 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
9793 inst
.instruction
= opcode
;
9796 inst
.instruction
|= Rn
;
9797 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
9802 inst
.instruction
|= CONDS_BIT
;
9804 inst
.instruction
|= Rn
<< 8;
9805 inst
.instruction
|= Rm
<< 16;
9806 inst
.instruction
|= inst
.operands
[1].imm
;
9811 /* Some mov with immediate shift have narrow variants.
9812 Register shifts are handled above. */
9813 if (low_regs
&& inst
.operands
[1].shifted
9814 && (inst
.instruction
== T_MNEM_mov
9815 || inst
.instruction
== T_MNEM_movs
))
9817 if (current_it_mask
)
9818 narrow
= (inst
.instruction
== T_MNEM_mov
);
9820 narrow
= (inst
.instruction
== T_MNEM_movs
);
9825 switch (inst
.operands
[1].shift_kind
)
9827 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
9828 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
9829 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
9830 default: narrow
= FALSE
; break;
9836 inst
.instruction
|= Rn
;
9837 inst
.instruction
|= Rm
<< 3;
9838 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
9842 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9843 inst
.instruction
|= Rn
<< r0off
;
9844 encode_thumb32_shifted_operand (1);
9848 switch (inst
.instruction
)
9851 inst
.instruction
= T_OPCODE_MOV_HR
;
9852 inst
.instruction
|= (Rn
& 0x8) << 4;
9853 inst
.instruction
|= (Rn
& 0x7);
9854 inst
.instruction
|= Rm
<< 3;
9858 /* We know we have low registers at this point.
9859 Generate ADD Rd, Rs, #0. */
9860 inst
.instruction
= T_OPCODE_ADD_I3
;
9861 inst
.instruction
|= Rn
;
9862 inst
.instruction
|= Rm
<< 3;
9868 inst
.instruction
= T_OPCODE_CMP_LR
;
9869 inst
.instruction
|= Rn
;
9870 inst
.instruction
|= Rm
<< 3;
9874 inst
.instruction
= T_OPCODE_CMP_HR
;
9875 inst
.instruction
|= (Rn
& 0x8) << 4;
9876 inst
.instruction
|= (Rn
& 0x7);
9877 inst
.instruction
|= Rm
<< 3;
9884 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9885 if (inst
.operands
[1].isreg
)
9887 if (Rn
< 8 && Rm
< 8)
9889 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
9890 since a MOV instruction produces unpredictable results. */
9891 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9892 inst
.instruction
= T_OPCODE_ADD_I3
;
9894 inst
.instruction
= T_OPCODE_CMP_LR
;
9896 inst
.instruction
|= Rn
;
9897 inst
.instruction
|= Rm
<< 3;
9901 if (inst
.instruction
== T_OPCODE_MOV_I8
)
9902 inst
.instruction
= T_OPCODE_MOV_HR
;
9904 inst
.instruction
= T_OPCODE_CMP_HR
;
9911 _("only lo regs allowed with immediate"));
9912 inst
.instruction
|= Rn
<< 8;
9913 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
9924 top
= (inst
.instruction
& 0x00800000) != 0;
9925 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
9927 constraint (top
, _(":lower16: not allowed this instruction"));
9928 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
9930 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
9932 constraint (!top
, _(":upper16: not allowed this instruction"));
9933 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
9936 Rd
= inst
.operands
[0].reg
;
9937 reject_bad_reg (Rd
);
9939 inst
.instruction
|= Rd
<< 8;
9940 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9942 imm
= inst
.reloc
.exp
.X_add_number
;
9943 inst
.instruction
|= (imm
& 0xf000) << 4;
9944 inst
.instruction
|= (imm
& 0x0800) << 15;
9945 inst
.instruction
|= (imm
& 0x0700) << 4;
9946 inst
.instruction
|= (imm
& 0x00ff);
9955 Rn
= inst
.operands
[0].reg
;
9956 Rm
= inst
.operands
[1].reg
;
9958 if (inst
.instruction
== T_MNEM_cmp
9959 || inst
.instruction
== T_MNEM_cmn
)
9960 constraint (Rn
== REG_PC
, BAD_PC
);
9962 reject_bad_reg (Rn
);
9963 reject_bad_reg (Rm
);
9967 int r0off
= (inst
.instruction
== T_MNEM_mvn
9968 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
9971 if (inst
.size_req
== 4
9972 || inst
.instruction
> 0xffff
9973 || inst
.operands
[1].shifted
9974 || Rn
> 7 || Rm
> 7)
9976 else if (inst
.instruction
== T_MNEM_cmn
)
9978 else if (THUMB_SETS_FLAGS (inst
.instruction
))
9979 narrow
= (current_it_mask
== 0);
9981 narrow
= (current_it_mask
!= 0);
9983 if (!inst
.operands
[1].isreg
)
9985 /* For an immediate, we always generate a 32-bit opcode;
9986 section relaxation will shrink it later if possible. */
9987 if (inst
.instruction
< 0xffff)
9988 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9989 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9990 inst
.instruction
|= Rn
<< r0off
;
9991 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9995 /* See if we can do this with a 16-bit instruction. */
9998 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9999 inst
.instruction
|= Rn
;
10000 inst
.instruction
|= Rm
<< 3;
10004 constraint (inst
.operands
[1].shifted
10005 && inst
.operands
[1].immisreg
,
10006 _("shift must be constant"));
10007 if (inst
.instruction
< 0xffff)
10008 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10009 inst
.instruction
|= Rn
<< r0off
;
10010 encode_thumb32_shifted_operand (1);
10016 constraint (inst
.instruction
> 0xffff
10017 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
10018 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
10019 _("unshifted register required"));
10020 constraint (Rn
> 7 || Rm
> 7,
10023 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10024 inst
.instruction
|= Rn
;
10025 inst
.instruction
|= Rm
<< 3;
10035 if (do_vfp_nsyn_mrs () == SUCCESS
)
10038 flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
10041 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10042 _("selected processor does not support "
10043 "requested special purpose register"));
10047 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10048 _("selected processor does not support "
10049 "requested special purpose register"));
10050 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10051 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
10052 _("'CPSR' or 'SPSR' expected"));
10055 Rd
= inst
.operands
[0].reg
;
10056 reject_bad_reg (Rd
);
10058 inst
.instruction
|= Rd
<< 8;
10059 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10060 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
10069 if (do_vfp_nsyn_msr () == SUCCESS
)
10072 constraint (!inst
.operands
[1].isreg
,
10073 _("Thumb encoding does not support an immediate here"));
10074 flags
= inst
.operands
[0].imm
;
10077 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
),
10078 _("selected processor does not support "
10079 "requested special purpose register"));
10083 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
),
10084 _("selected processor does not support "
10085 "requested special purpose register"));
10089 Rn
= inst
.operands
[1].reg
;
10090 reject_bad_reg (Rn
);
10092 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
10093 inst
.instruction
|= (flags
& ~SPSR_BIT
) >> 8;
10094 inst
.instruction
|= (flags
& 0xff);
10095 inst
.instruction
|= Rn
<< 16;
10101 bfd_boolean narrow
;
10102 unsigned Rd
, Rn
, Rm
;
10104 if (!inst
.operands
[2].present
)
10105 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10107 Rd
= inst
.operands
[0].reg
;
10108 Rn
= inst
.operands
[1].reg
;
10109 Rm
= inst
.operands
[2].reg
;
10111 if (unified_syntax
)
10113 if (inst
.size_req
== 4
10119 else if (inst
.instruction
== T_MNEM_muls
)
10120 narrow
= (current_it_mask
== 0);
10122 narrow
= (current_it_mask
!= 0);
10126 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
10127 constraint (Rn
> 7 || Rm
> 7,
10134 /* 16-bit MULS/Conditional MUL. */
10135 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10136 inst
.instruction
|= Rd
;
10139 inst
.instruction
|= Rm
<< 3;
10141 inst
.instruction
|= Rn
<< 3;
10143 constraint (1, _("dest must overlap one source register"));
10147 constraint(inst
.instruction
!= T_MNEM_mul
,
10148 _("Thumb-2 MUL must not set flags"));
10150 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10151 inst
.instruction
|= Rd
<< 8;
10152 inst
.instruction
|= Rn
<< 16;
10153 inst
.instruction
|= Rm
<< 0;
10155 reject_bad_reg (Rd
);
10156 reject_bad_reg (Rn
);
10157 reject_bad_reg (Rm
);
10164 unsigned RdLo
, RdHi
, Rn
, Rm
;
10166 RdLo
= inst
.operands
[0].reg
;
10167 RdHi
= inst
.operands
[1].reg
;
10168 Rn
= inst
.operands
[2].reg
;
10169 Rm
= inst
.operands
[3].reg
;
10171 reject_bad_reg (RdLo
);
10172 reject_bad_reg (RdHi
);
10173 reject_bad_reg (Rn
);
10174 reject_bad_reg (Rm
);
10176 inst
.instruction
|= RdLo
<< 12;
10177 inst
.instruction
|= RdHi
<< 8;
10178 inst
.instruction
|= Rn
<< 16;
10179 inst
.instruction
|= Rm
;
10182 as_tsktsk (_("rdhi and rdlo must be different"));
10188 if (unified_syntax
)
10190 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
10192 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10193 inst
.instruction
|= inst
.operands
[0].imm
;
10197 /* PR9722: Check for Thumb2 availability before
10198 generating a thumb2 nop instruction. */
10199 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
10201 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10202 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
10205 inst
.instruction
= 0x46c0;
10210 constraint (inst
.operands
[0].present
,
10211 _("Thumb does not support NOP with hints"));
10212 inst
.instruction
= 0x46c0;
10219 if (unified_syntax
)
10221 bfd_boolean narrow
;
10223 if (THUMB_SETS_FLAGS (inst
.instruction
))
10224 narrow
= (current_it_mask
== 0);
10226 narrow
= (current_it_mask
!= 0);
10227 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10229 if (inst
.size_req
== 4)
10234 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10235 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10236 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10240 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10241 inst
.instruction
|= inst
.operands
[0].reg
;
10242 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10247 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
10249 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10251 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10252 inst
.instruction
|= inst
.operands
[0].reg
;
10253 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10262 Rd
= inst
.operands
[0].reg
;
10263 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
10265 reject_bad_reg (Rd
);
10266 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
10267 reject_bad_reg (Rn
);
10269 inst
.instruction
|= Rd
<< 8;
10270 inst
.instruction
|= Rn
<< 16;
10272 if (!inst
.operands
[2].isreg
)
10274 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10275 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10281 Rm
= inst
.operands
[2].reg
;
10282 reject_bad_reg (Rm
);
10284 constraint (inst
.operands
[2].shifted
10285 && inst
.operands
[2].immisreg
,
10286 _("shift must be constant"));
10287 encode_thumb32_shifted_operand (2);
10294 unsigned Rd
, Rn
, Rm
;
10296 Rd
= inst
.operands
[0].reg
;
10297 Rn
= inst
.operands
[1].reg
;
10298 Rm
= inst
.operands
[2].reg
;
10300 reject_bad_reg (Rd
);
10301 reject_bad_reg (Rn
);
10302 reject_bad_reg (Rm
);
10304 inst
.instruction
|= Rd
<< 8;
10305 inst
.instruction
|= Rn
<< 16;
10306 inst
.instruction
|= Rm
;
10307 if (inst
.operands
[3].present
)
10309 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
10310 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10311 _("expression too complex"));
10312 inst
.instruction
|= (val
& 0x1c) << 10;
10313 inst
.instruction
|= (val
& 0x03) << 6;
10320 if (!inst
.operands
[3].present
)
10321 inst
.instruction
&= ~0x00000020;
10328 if (inst
.operands
[0].immisreg
)
10329 reject_bad_reg (inst
.operands
[0].imm
);
10331 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10335 do_t_push_pop (void)
10339 constraint (inst
.operands
[0].writeback
,
10340 _("push/pop do not support {reglist}^"));
10341 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10342 _("expression too complex"));
10344 mask
= inst
.operands
[0].imm
;
10345 if ((mask
& ~0xff) == 0)
10346 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
10347 else if ((inst
.instruction
== T_MNEM_push
10348 && (mask
& ~0xff) == 1 << REG_LR
)
10349 || (inst
.instruction
== T_MNEM_pop
10350 && (mask
& ~0xff) == 1 << REG_PC
))
10352 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10353 inst
.instruction
|= THUMB_PP_PC_LR
;
10354 inst
.instruction
|= mask
& 0xff;
10356 else if (unified_syntax
)
10358 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10359 encode_thumb2_ldmstm (13, mask
, TRUE
);
10363 inst
.error
= _("invalid register list to push/pop instruction");
10373 Rd
= inst
.operands
[0].reg
;
10374 Rm
= inst
.operands
[1].reg
;
10376 reject_bad_reg (Rd
);
10377 reject_bad_reg (Rm
);
10379 inst
.instruction
|= Rd
<< 8;
10380 inst
.instruction
|= Rm
<< 16;
10381 inst
.instruction
|= Rm
;
10389 Rd
= inst
.operands
[0].reg
;
10390 Rm
= inst
.operands
[1].reg
;
10392 reject_bad_reg (Rd
);
10393 reject_bad_reg (Rm
);
10395 if (Rd
<= 7 && Rm
<= 7
10396 && inst
.size_req
!= 4)
10398 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10399 inst
.instruction
|= Rd
;
10400 inst
.instruction
|= Rm
<< 3;
10402 else if (unified_syntax
)
10404 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10405 inst
.instruction
|= Rd
<< 8;
10406 inst
.instruction
|= Rm
<< 16;
10407 inst
.instruction
|= Rm
;
10410 inst
.error
= BAD_HIREG
;
10418 Rd
= inst
.operands
[0].reg
;
10419 Rm
= inst
.operands
[1].reg
;
10421 reject_bad_reg (Rd
);
10422 reject_bad_reg (Rm
);
10424 inst
.instruction
|= Rd
<< 8;
10425 inst
.instruction
|= Rm
;
10433 Rd
= inst
.operands
[0].reg
;
10434 Rs
= (inst
.operands
[1].present
10435 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10436 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10438 reject_bad_reg (Rd
);
10439 reject_bad_reg (Rs
);
10440 if (inst
.operands
[2].isreg
)
10441 reject_bad_reg (inst
.operands
[2].reg
);
10443 inst
.instruction
|= Rd
<< 8;
10444 inst
.instruction
|= Rs
<< 16;
10445 if (!inst
.operands
[2].isreg
)
10447 bfd_boolean narrow
;
10449 if ((inst
.instruction
& 0x00100000) != 0)
10450 narrow
= (current_it_mask
== 0);
10452 narrow
= (current_it_mask
!= 0);
10454 if (Rd
> 7 || Rs
> 7)
10457 if (inst
.size_req
== 4 || !unified_syntax
)
10460 if (inst
.reloc
.exp
.X_op
!= O_constant
10461 || inst
.reloc
.exp
.X_add_number
!= 0)
10464 /* Turn rsb #0 into 16-bit neg. We should probably do this via
10465 relaxation, but it doesn't seem worth the hassle. */
10468 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10469 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
10470 inst
.instruction
|= Rs
<< 3;
10471 inst
.instruction
|= Rd
;
10475 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10476 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10480 encode_thumb32_shifted_operand (2);
10486 constraint (current_it_mask
, BAD_NOT_IT
);
10487 if (inst
.operands
[0].imm
)
10488 inst
.instruction
|= 0x8;
10494 if (!inst
.operands
[1].present
)
10495 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
10497 if (unified_syntax
)
10499 bfd_boolean narrow
;
10502 switch (inst
.instruction
)
10505 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
10507 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
10509 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
10511 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
10515 if (THUMB_SETS_FLAGS (inst
.instruction
))
10516 narrow
= (current_it_mask
== 0);
10518 narrow
= (current_it_mask
!= 0);
10519 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
10521 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
10523 if (inst
.operands
[2].isreg
10524 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
10525 || inst
.operands
[2].reg
> 7))
10527 if (inst
.size_req
== 4)
10530 reject_bad_reg (inst
.operands
[0].reg
);
10531 reject_bad_reg (inst
.operands
[1].reg
);
10535 if (inst
.operands
[2].isreg
)
10537 reject_bad_reg (inst
.operands
[2].reg
);
10538 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10539 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10540 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10541 inst
.instruction
|= inst
.operands
[2].reg
;
10545 inst
.operands
[1].shifted
= 1;
10546 inst
.operands
[1].shift_kind
= shift_kind
;
10547 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
10548 ? T_MNEM_movs
: T_MNEM_mov
);
10549 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10550 encode_thumb32_shifted_operand (1);
10551 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
10552 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10557 if (inst
.operands
[2].isreg
)
10559 switch (shift_kind
)
10561 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10562 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10563 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10564 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10568 inst
.instruction
|= inst
.operands
[0].reg
;
10569 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10573 switch (shift_kind
)
10575 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10576 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10577 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10580 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10581 inst
.instruction
|= inst
.operands
[0].reg
;
10582 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10588 constraint (inst
.operands
[0].reg
> 7
10589 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
10590 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10592 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
10594 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
10595 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
10596 _("source1 and dest must be same register"));
10598 switch (inst
.instruction
)
10600 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
10601 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
10602 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
10603 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
10607 inst
.instruction
|= inst
.operands
[0].reg
;
10608 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
10612 switch (inst
.instruction
)
10614 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10615 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10616 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10617 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
10620 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10621 inst
.instruction
|= inst
.operands
[0].reg
;
10622 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10630 unsigned Rd
, Rn
, Rm
;
10632 Rd
= inst
.operands
[0].reg
;
10633 Rn
= inst
.operands
[1].reg
;
10634 Rm
= inst
.operands
[2].reg
;
10636 reject_bad_reg (Rd
);
10637 reject_bad_reg (Rn
);
10638 reject_bad_reg (Rm
);
10640 inst
.instruction
|= Rd
<< 8;
10641 inst
.instruction
|= Rn
<< 16;
10642 inst
.instruction
|= Rm
;
10648 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10649 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10650 _("expression too complex"));
10651 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10652 inst
.instruction
|= (value
& 0xf000) >> 12;
10653 inst
.instruction
|= (value
& 0x0ff0);
10654 inst
.instruction
|= (value
& 0x000f) << 16;
10662 Rd
= inst
.operands
[0].reg
;
10663 Rn
= inst
.operands
[2].reg
;
10665 reject_bad_reg (Rd
);
10666 reject_bad_reg (Rn
);
10668 inst
.instruction
|= Rd
<< 8;
10669 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10670 inst
.instruction
|= Rn
<< 16;
10672 if (inst
.operands
[3].present
)
10674 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10675 _("expression too complex"));
10677 if (inst
.reloc
.exp
.X_add_number
!= 0)
10679 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10680 inst
.instruction
|= 0x00200000; /* sh bit */
10681 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10682 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10684 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10693 Rd
= inst
.operands
[0].reg
;
10694 Rn
= inst
.operands
[2].reg
;
10696 reject_bad_reg (Rd
);
10697 reject_bad_reg (Rn
);
10699 inst
.instruction
|= Rd
<< 8;
10700 inst
.instruction
|= inst
.operands
[1].imm
- 1;
10701 inst
.instruction
|= Rn
<< 16;
10707 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10708 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10709 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10710 || inst
.operands
[2].negative
,
10713 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10714 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10715 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10716 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10722 if (!inst
.operands
[2].present
)
10723 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
10725 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10726 || inst
.operands
[0].reg
== inst
.operands
[2].reg
10727 || inst
.operands
[0].reg
== inst
.operands
[3].reg
10728 || inst
.operands
[1].reg
== inst
.operands
[2].reg
,
10731 inst
.instruction
|= inst
.operands
[0].reg
;
10732 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10733 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10734 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10740 unsigned Rd
, Rn
, Rm
;
10742 Rd
= inst
.operands
[0].reg
;
10743 Rn
= inst
.operands
[1].reg
;
10744 Rm
= inst
.operands
[2].reg
;
10746 reject_bad_reg (Rd
);
10747 reject_bad_reg (Rn
);
10748 reject_bad_reg (Rm
);
10750 inst
.instruction
|= Rd
<< 8;
10751 inst
.instruction
|= Rn
<< 16;
10752 inst
.instruction
|= Rm
;
10753 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
10761 Rd
= inst
.operands
[0].reg
;
10762 Rm
= inst
.operands
[1].reg
;
10764 reject_bad_reg (Rd
);
10765 reject_bad_reg (Rm
);
10767 if (inst
.instruction
<= 0xffff && inst
.size_req
!= 4
10768 && Rd
<= 7 && Rm
<= 7
10769 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
10771 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10772 inst
.instruction
|= Rd
;
10773 inst
.instruction
|= Rm
<< 3;
10775 else if (unified_syntax
)
10777 if (inst
.instruction
<= 0xffff)
10778 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10779 inst
.instruction
|= Rd
<< 8;
10780 inst
.instruction
|= Rm
;
10781 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
10785 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
10786 _("Thumb encoding does not support rotation"));
10787 constraint (1, BAD_HIREG
);
10794 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
10803 half
= (inst
.instruction
& 0x10) != 0;
10804 constraint (current_it_mask
&& current_it_mask
!= 0x10, BAD_BRANCH
);
10805 constraint (inst
.operands
[0].immisreg
,
10806 _("instruction requires register index"));
10808 Rn
= inst
.operands
[0].reg
;
10809 Rm
= inst
.operands
[0].imm
;
10811 constraint (Rn
== REG_SP
, BAD_SP
);
10812 reject_bad_reg (Rm
);
10814 constraint (!half
&& inst
.operands
[0].shifted
,
10815 _("instruction does not allow shifted index"));
10816 inst
.instruction
|= (Rn
<< 16) | Rm
;
10824 Rd
= inst
.operands
[0].reg
;
10825 Rn
= inst
.operands
[2].reg
;
10827 reject_bad_reg (Rd
);
10828 reject_bad_reg (Rn
);
10830 inst
.instruction
|= Rd
<< 8;
10831 inst
.instruction
|= inst
.operands
[1].imm
;
10832 inst
.instruction
|= Rn
<< 16;
10834 if (inst
.operands
[3].present
)
10836 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10837 _("expression too complex"));
10838 if (inst
.reloc
.exp
.X_add_number
!= 0)
10840 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
10841 inst
.instruction
|= 0x00200000; /* sh bit */
10843 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x1c) << 10;
10844 inst
.instruction
|= (inst
.reloc
.exp
.X_add_number
& 0x03) << 6;
10846 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10855 Rd
= inst
.operands
[0].reg
;
10856 Rn
= inst
.operands
[2].reg
;
10858 reject_bad_reg (Rd
);
10859 reject_bad_reg (Rn
);
10861 inst
.instruction
|= Rd
<< 8;
10862 inst
.instruction
|= inst
.operands
[1].imm
;
10863 inst
.instruction
|= Rn
<< 16;
10866 /* Neon instruction encoder helpers. */
10868 /* Encodings for the different types for various Neon opcodes. */
10870 /* An "invalid" code for the following tables. */
10873 struct neon_tab_entry
10876 unsigned float_or_poly
;
10877 unsigned scalar_or_imm
;
10880 /* Map overloaded Neon opcodes to their respective encodings. */
10881 #define NEON_ENC_TAB \
10882 X(vabd, 0x0000700, 0x1200d00, N_INV), \
10883 X(vmax, 0x0000600, 0x0000f00, N_INV), \
10884 X(vmin, 0x0000610, 0x0200f00, N_INV), \
10885 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
10886 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
10887 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
10888 X(vadd, 0x0000800, 0x0000d00, N_INV), \
10889 X(vsub, 0x1000800, 0x0200d00, N_INV), \
10890 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
10891 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
10892 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
10893 /* Register variants of the following two instructions are encoded as
10894 vcge / vcgt with the operands reversed. */ \
10895 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
10896 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
10897 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
10898 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
10899 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
10900 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
10901 X(vmlal, 0x0800800, N_INV, 0x0800240), \
10902 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
10903 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
10904 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
10905 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
10906 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
10907 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
10908 X(vshl, 0x0000400, N_INV, 0x0800510), \
10909 X(vqshl, 0x0000410, N_INV, 0x0800710), \
10910 X(vand, 0x0000110, N_INV, 0x0800030), \
10911 X(vbic, 0x0100110, N_INV, 0x0800030), \
10912 X(veor, 0x1000110, N_INV, N_INV), \
10913 X(vorn, 0x0300110, N_INV, 0x0800010), \
10914 X(vorr, 0x0200110, N_INV, 0x0800010), \
10915 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
10916 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
10917 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
10918 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
10919 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
10920 X(vst1, 0x0000000, 0x0800000, N_INV), \
10921 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
10922 X(vst2, 0x0000100, 0x0800100, N_INV), \
10923 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
10924 X(vst3, 0x0000200, 0x0800200, N_INV), \
10925 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
10926 X(vst4, 0x0000300, 0x0800300, N_INV), \
10927 X(vmovn, 0x1b20200, N_INV, N_INV), \
10928 X(vtrn, 0x1b20080, N_INV, N_INV), \
10929 X(vqmovn, 0x1b20200, N_INV, N_INV), \
10930 X(vqmovun, 0x1b20240, N_INV, N_INV), \
10931 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
10932 X(vnmla, 0xe000a40, 0xe000b40, N_INV), \
10933 X(vnmls, 0xe100a40, 0xe100b40, N_INV), \
10934 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
10935 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
10936 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
10937 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
10941 #define X(OPC,I,F,S) N_MNEM_##OPC
10946 static const struct neon_tab_entry neon_enc_tab
[] =
10948 #define X(OPC,I,F,S) { (I), (F), (S) }
10953 #define NEON_ENC_INTEGER(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10954 #define NEON_ENC_ARMREG(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10955 #define NEON_ENC_POLY(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10956 #define NEON_ENC_FLOAT(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10957 #define NEON_ENC_SCALAR(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10958 #define NEON_ENC_IMMED(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10959 #define NEON_ENC_INTERLV(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
10960 #define NEON_ENC_LANE(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
10961 #define NEON_ENC_DUP(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
10962 #define NEON_ENC_SINGLE(X) \
10963 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
10964 #define NEON_ENC_DOUBLE(X) \
10965 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
10967 /* Define shapes for instruction operands. The following mnemonic characters
10968 are used in this table:
10970 F - VFP S<n> register
10971 D - Neon D<n> register
10972 Q - Neon Q<n> register
10976 L - D<n> register list
10978 This table is used to generate various data:
10979 - enumerations of the form NS_DDR to be used as arguments to
10981 - a table classifying shapes into single, double, quad, mixed.
10982 - a table used to drive neon_select_shape. */
10984 #define NEON_SHAPE_DEF \
10985 X(3, (D, D, D), DOUBLE), \
10986 X(3, (Q, Q, Q), QUAD), \
10987 X(3, (D, D, I), DOUBLE), \
10988 X(3, (Q, Q, I), QUAD), \
10989 X(3, (D, D, S), DOUBLE), \
10990 X(3, (Q, Q, S), QUAD), \
10991 X(2, (D, D), DOUBLE), \
10992 X(2, (Q, Q), QUAD), \
10993 X(2, (D, S), DOUBLE), \
10994 X(2, (Q, S), QUAD), \
10995 X(2, (D, R), DOUBLE), \
10996 X(2, (Q, R), QUAD), \
10997 X(2, (D, I), DOUBLE), \
10998 X(2, (Q, I), QUAD), \
10999 X(3, (D, L, D), DOUBLE), \
11000 X(2, (D, Q), MIXED), \
11001 X(2, (Q, D), MIXED), \
11002 X(3, (D, Q, I), MIXED), \
11003 X(3, (Q, D, I), MIXED), \
11004 X(3, (Q, D, D), MIXED), \
11005 X(3, (D, Q, Q), MIXED), \
11006 X(3, (Q, Q, D), MIXED), \
11007 X(3, (Q, D, S), MIXED), \
11008 X(3, (D, Q, S), MIXED), \
11009 X(4, (D, D, D, I), DOUBLE), \
11010 X(4, (Q, Q, Q, I), QUAD), \
11011 X(2, (F, F), SINGLE), \
11012 X(3, (F, F, F), SINGLE), \
11013 X(2, (F, I), SINGLE), \
11014 X(2, (F, D), MIXED), \
11015 X(2, (D, F), MIXED), \
11016 X(3, (F, F, I), MIXED), \
11017 X(4, (R, R, F, F), SINGLE), \
11018 X(4, (F, F, R, R), SINGLE), \
11019 X(3, (D, R, R), DOUBLE), \
11020 X(3, (R, R, D), DOUBLE), \
11021 X(2, (S, R), SINGLE), \
11022 X(2, (R, S), SINGLE), \
11023 X(2, (F, R), SINGLE), \
11024 X(2, (R, F), SINGLE)
11026 #define S2(A,B) NS_##A##B
11027 #define S3(A,B,C) NS_##A##B##C
11028 #define S4(A,B,C,D) NS_##A##B##C##D
11030 #define X(N, L, C) S##N L
11043 enum neon_shape_class
11051 #define X(N, L, C) SC_##C
11053 static enum neon_shape_class neon_shape_class
[] =
11071 /* Register widths of above. */
11072 static unsigned neon_shape_el_size
[] =
11083 struct neon_shape_info
11086 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
11089 #define S2(A,B) { SE_##A, SE_##B }
11090 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
11091 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
11093 #define X(N, L, C) { N, S##N L }
11095 static struct neon_shape_info neon_shape_tab
[] =
11105 /* Bit masks used in type checking given instructions.
11106 'N_EQK' means the type must be the same as (or based on in some way) the key
11107 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
11108 set, various other bits can be set as well in order to modify the meaning of
11109 the type constraint. */
11111 enum neon_type_mask
11134 N_KEY
= 0x1000000, /* key element (main type specifier). */
11135 N_EQK
= 0x2000000, /* given operand has the same type & size as the key. */
11136 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
11137 N_DBL
= 0x0000001, /* if N_EQK, this operand is twice the size. */
11138 N_HLF
= 0x0000002, /* if N_EQK, this operand is half the size. */
11139 N_SGN
= 0x0000004, /* if N_EQK, this operand is forced to be signed. */
11140 N_UNS
= 0x0000008, /* if N_EQK, this operand is forced to be unsigned. */
11141 N_INT
= 0x0000010, /* if N_EQK, this operand is forced to be integer. */
11142 N_FLT
= 0x0000020, /* if N_EQK, this operand is forced to be float. */
11143 N_SIZ
= 0x0000040, /* if N_EQK, this operand is forced to be size-only. */
11145 N_MAX_NONSPECIAL
= N_F64
11148 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
11150 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
11151 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
11152 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
11153 #define N_SUF_32 (N_SU_32 | N_F32)
11154 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
11155 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
11157 /* Pass this as the first type argument to neon_check_type to ignore types
11159 #define N_IGNORE_TYPE (N_KEY | N_EQK)
11161 /* Select a "shape" for the current instruction (describing register types or
11162 sizes) from a list of alternatives. Return NS_NULL if the current instruction
11163 doesn't fit. For non-polymorphic shapes, checking is usually done as a
11164 function of operand parsing, so this function doesn't need to be called.
11165 Shapes should be listed in order of decreasing length. */
11167 static enum neon_shape
11168 neon_select_shape (enum neon_shape shape
, ...)
11171 enum neon_shape first_shape
= shape
;
11173 /* Fix missing optional operands. FIXME: we don't know at this point how
11174 many arguments we should have, so this makes the assumption that we have
11175 > 1. This is true of all current Neon opcodes, I think, but may not be
11176 true in the future. */
11177 if (!inst
.operands
[1].present
)
11178 inst
.operands
[1] = inst
.operands
[0];
11180 va_start (ap
, shape
);
11182 for (; shape
!= NS_NULL
; shape
= va_arg (ap
, int))
11187 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
11189 if (!inst
.operands
[j
].present
)
11195 switch (neon_shape_tab
[shape
].el
[j
])
11198 if (!(inst
.operands
[j
].isreg
11199 && inst
.operands
[j
].isvec
11200 && inst
.operands
[j
].issingle
11201 && !inst
.operands
[j
].isquad
))
11206 if (!(inst
.operands
[j
].isreg
11207 && inst
.operands
[j
].isvec
11208 && !inst
.operands
[j
].isquad
11209 && !inst
.operands
[j
].issingle
))
11214 if (!(inst
.operands
[j
].isreg
11215 && !inst
.operands
[j
].isvec
))
11220 if (!(inst
.operands
[j
].isreg
11221 && inst
.operands
[j
].isvec
11222 && inst
.operands
[j
].isquad
11223 && !inst
.operands
[j
].issingle
))
11228 if (!(!inst
.operands
[j
].isreg
11229 && !inst
.operands
[j
].isscalar
))
11234 if (!(!inst
.operands
[j
].isreg
11235 && inst
.operands
[j
].isscalar
))
11249 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
11250 first_error (_("invalid instruction shape"));
11255 /* True if SHAPE is predominantly a quadword operation (most of the time, this
11256 means the Q bit should be set). */
11259 neon_quad (enum neon_shape shape
)
11261 return neon_shape_class
[shape
] == SC_QUAD
;
11265 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
11268 /* Allow modification to be made to types which are constrained to be
11269 based on the key element, based on bits set alongside N_EQK. */
11270 if ((typebits
& N_EQK
) != 0)
11272 if ((typebits
& N_HLF
) != 0)
11274 else if ((typebits
& N_DBL
) != 0)
11276 if ((typebits
& N_SGN
) != 0)
11277 *g_type
= NT_signed
;
11278 else if ((typebits
& N_UNS
) != 0)
11279 *g_type
= NT_unsigned
;
11280 else if ((typebits
& N_INT
) != 0)
11281 *g_type
= NT_integer
;
11282 else if ((typebits
& N_FLT
) != 0)
11283 *g_type
= NT_float
;
11284 else if ((typebits
& N_SIZ
) != 0)
11285 *g_type
= NT_untyped
;
11289 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
11290 operand type, i.e. the single type specified in a Neon instruction when it
11291 is the only one given. */
11293 static struct neon_type_el
11294 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
11296 struct neon_type_el dest
= *key
;
11298 assert ((thisarg
& N_EQK
) != 0);
11300 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
11305 /* Convert Neon type and size into compact bitmask representation. */
11307 static enum neon_type_mask
11308 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
11315 case 8: return N_8
;
11316 case 16: return N_16
;
11317 case 32: return N_32
;
11318 case 64: return N_64
;
11326 case 8: return N_I8
;
11327 case 16: return N_I16
;
11328 case 32: return N_I32
;
11329 case 64: return N_I64
;
11337 case 16: return N_F16
;
11338 case 32: return N_F32
;
11339 case 64: return N_F64
;
11347 case 8: return N_P8
;
11348 case 16: return N_P16
;
11356 case 8: return N_S8
;
11357 case 16: return N_S16
;
11358 case 32: return N_S32
;
11359 case 64: return N_S64
;
11367 case 8: return N_U8
;
11368 case 16: return N_U16
;
11369 case 32: return N_U32
;
11370 case 64: return N_U64
;
11381 /* Convert compact Neon bitmask type representation to a type and size. Only
11382 handles the case where a single bit is set in the mask. */
11385 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
11386 enum neon_type_mask mask
)
11388 if ((mask
& N_EQK
) != 0)
11391 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
11393 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
11395 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
11397 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
11402 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
11404 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
11405 *type
= NT_unsigned
;
11406 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
11407 *type
= NT_integer
;
11408 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
11409 *type
= NT_untyped
;
11410 else if ((mask
& (N_P8
| N_P16
)) != 0)
11412 else if ((mask
& (N_F32
| N_F64
)) != 0)
11420 /* Modify a bitmask of allowed types. This is only needed for type
11424 modify_types_allowed (unsigned allowed
, unsigned mods
)
11427 enum neon_el_type type
;
11433 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
11435 if (el_type_of_type_chk (&type
, &size
, allowed
& i
) == SUCCESS
)
11437 neon_modify_type_size (mods
, &type
, &size
);
11438 destmask
|= type_chk_of_el_type (type
, size
);
11445 /* Check type and return type classification.
11446 The manual states (paraphrase): If one datatype is given, it indicates the
11448 - the second operand, if there is one
11449 - the operand, if there is no second operand
11450 - the result, if there are no operands.
11451 This isn't quite good enough though, so we use a concept of a "key" datatype
11452 which is set on a per-instruction basis, which is the one which matters when
11453 only one data type is written.
11454 Note: this function has side-effects (e.g. filling in missing operands). All
11455 Neon instructions should call it before performing bit encoding. */
11457 static struct neon_type_el
11458 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
11461 unsigned i
, pass
, key_el
= 0;
11462 unsigned types
[NEON_MAX_TYPE_ELS
];
11463 enum neon_el_type k_type
= NT_invtype
;
11464 unsigned k_size
= -1u;
11465 struct neon_type_el badtype
= {NT_invtype
, -1};
11466 unsigned key_allowed
= 0;
11468 /* Optional registers in Neon instructions are always (not) in operand 1.
11469 Fill in the missing operand here, if it was omitted. */
11470 if (els
> 1 && !inst
.operands
[1].present
)
11471 inst
.operands
[1] = inst
.operands
[0];
11473 /* Suck up all the varargs. */
11475 for (i
= 0; i
< els
; i
++)
11477 unsigned thisarg
= va_arg (ap
, unsigned);
11478 if (thisarg
== N_IGNORE_TYPE
)
11483 types
[i
] = thisarg
;
11484 if ((thisarg
& N_KEY
) != 0)
11489 if (inst
.vectype
.elems
> 0)
11490 for (i
= 0; i
< els
; i
++)
11491 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
11493 first_error (_("types specified in both the mnemonic and operands"));
11497 /* Duplicate inst.vectype elements here as necessary.
11498 FIXME: No idea if this is exactly the same as the ARM assembler,
11499 particularly when an insn takes one register and one non-register
11501 if (inst
.vectype
.elems
== 1 && els
> 1)
11504 inst
.vectype
.elems
= els
;
11505 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
11506 for (j
= 0; j
< els
; j
++)
11508 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11511 else if (inst
.vectype
.elems
== 0 && els
> 0)
11514 /* No types were given after the mnemonic, so look for types specified
11515 after each operand. We allow some flexibility here; as long as the
11516 "key" operand has a type, we can infer the others. */
11517 for (j
= 0; j
< els
; j
++)
11518 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
11519 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
11521 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
11523 for (j
= 0; j
< els
; j
++)
11524 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
11525 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
11530 first_error (_("operand types can't be inferred"));
11534 else if (inst
.vectype
.elems
!= els
)
11536 first_error (_("type specifier has the wrong number of parts"));
11540 for (pass
= 0; pass
< 2; pass
++)
11542 for (i
= 0; i
< els
; i
++)
11544 unsigned thisarg
= types
[i
];
11545 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
11546 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
11547 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
11548 unsigned g_size
= inst
.vectype
.el
[i
].size
;
11550 /* Decay more-specific signed & unsigned types to sign-insensitive
11551 integer types if sign-specific variants are unavailable. */
11552 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
11553 && (types_allowed
& N_SU_ALL
) == 0)
11554 g_type
= NT_integer
;
11556 /* If only untyped args are allowed, decay any more specific types to
11557 them. Some instructions only care about signs for some element
11558 sizes, so handle that properly. */
11559 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
11560 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
11561 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
11562 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
11563 g_type
= NT_untyped
;
11567 if ((thisarg
& N_KEY
) != 0)
11571 key_allowed
= thisarg
& ~N_KEY
;
11576 if ((thisarg
& N_VFP
) != 0)
11578 enum neon_shape_el regshape
= neon_shape_tab
[ns
].el
[i
];
11579 unsigned regwidth
= neon_shape_el_size
[regshape
], match
;
11581 /* In VFP mode, operands must match register widths. If we
11582 have a key operand, use its width, else use the width of
11583 the current operand. */
11589 if (regwidth
!= match
)
11591 first_error (_("operand size must match register width"));
11596 if ((thisarg
& N_EQK
) == 0)
11598 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
11600 if ((given_type
& types_allowed
) == 0)
11602 first_error (_("bad type in Neon instruction"));
11608 enum neon_el_type mod_k_type
= k_type
;
11609 unsigned mod_k_size
= k_size
;
11610 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
11611 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
11613 first_error (_("inconsistent types in Neon instruction"));
11621 return inst
.vectype
.el
[key_el
];
11624 /* Neon-style VFP instruction forwarding. */
11626 /* Thumb VFP instructions have 0xE in the condition field. */
11629 do_vfp_cond_or_thumb (void)
11632 inst
.instruction
|= 0xe0000000;
11634 inst
.instruction
|= inst
.cond
<< 28;
11637 /* Look up and encode a simple mnemonic, for use as a helper function for the
11638 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
11639 etc. It is assumed that operand parsing has already been done, and that the
11640 operands are in the form expected by the given opcode (this isn't necessarily
11641 the same as the form in which they were parsed, hence some massaging must
11642 take place before this function is called).
11643 Checks current arch version against that in the looked-up opcode. */
11646 do_vfp_nsyn_opcode (const char *opname
)
11648 const struct asm_opcode
*opcode
;
11650 opcode
= hash_find (arm_ops_hsh
, opname
);
11655 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
11656 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
11661 inst
.instruction
= opcode
->tvalue
;
11662 opcode
->tencode ();
11666 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
11667 opcode
->aencode ();
11672 do_vfp_nsyn_add_sub (enum neon_shape rs
)
11674 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
11679 do_vfp_nsyn_opcode ("fadds");
11681 do_vfp_nsyn_opcode ("fsubs");
11686 do_vfp_nsyn_opcode ("faddd");
11688 do_vfp_nsyn_opcode ("fsubd");
11692 /* Check operand types to see if this is a VFP instruction, and if so call
11696 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
11698 enum neon_shape rs
;
11699 struct neon_type_el et
;
11704 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11705 et
= neon_check_type (2, rs
,
11706 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11710 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11711 et
= neon_check_type (3, rs
,
11712 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11719 if (et
.type
!= NT_invtype
)
11731 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
11733 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
11738 do_vfp_nsyn_opcode ("fmacs");
11740 do_vfp_nsyn_opcode ("fmscs");
11745 do_vfp_nsyn_opcode ("fmacd");
11747 do_vfp_nsyn_opcode ("fmscd");
11752 do_vfp_nsyn_mul (enum neon_shape rs
)
11755 do_vfp_nsyn_opcode ("fmuls");
11757 do_vfp_nsyn_opcode ("fmuld");
11761 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
11763 int is_neg
= (inst
.instruction
& 0x80) != 0;
11764 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
11769 do_vfp_nsyn_opcode ("fnegs");
11771 do_vfp_nsyn_opcode ("fabss");
11776 do_vfp_nsyn_opcode ("fnegd");
11778 do_vfp_nsyn_opcode ("fabsd");
11782 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
11783 insns belong to Neon, and are handled elsewhere. */
11786 do_vfp_nsyn_ldm_stm (int is_dbmode
)
11788 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
11792 do_vfp_nsyn_opcode ("fldmdbs");
11794 do_vfp_nsyn_opcode ("fldmias");
11799 do_vfp_nsyn_opcode ("fstmdbs");
11801 do_vfp_nsyn_opcode ("fstmias");
11806 do_vfp_nsyn_sqrt (void)
11808 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11809 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11812 do_vfp_nsyn_opcode ("fsqrts");
11814 do_vfp_nsyn_opcode ("fsqrtd");
11818 do_vfp_nsyn_div (void)
11820 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11821 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11822 N_F32
| N_F64
| N_KEY
| N_VFP
);
11825 do_vfp_nsyn_opcode ("fdivs");
11827 do_vfp_nsyn_opcode ("fdivd");
11831 do_vfp_nsyn_nmul (void)
11833 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
11834 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
11835 N_F32
| N_F64
| N_KEY
| N_VFP
);
11839 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11840 do_vfp_sp_dyadic ();
11844 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11845 do_vfp_dp_rd_rn_rm ();
11847 do_vfp_cond_or_thumb ();
11851 do_vfp_nsyn_cmp (void)
11853 if (inst
.operands
[1].isreg
)
11855 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
11856 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
11860 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11861 do_vfp_sp_monadic ();
11865 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11866 do_vfp_dp_rd_rm ();
11871 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
11872 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
11874 switch (inst
.instruction
& 0x0fffffff)
11877 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
11880 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
11888 inst
.instruction
= NEON_ENC_SINGLE (inst
.instruction
);
11889 do_vfp_sp_compare_z ();
11893 inst
.instruction
= NEON_ENC_DOUBLE (inst
.instruction
);
11897 do_vfp_cond_or_thumb ();
11901 nsyn_insert_sp (void)
11903 inst
.operands
[1] = inst
.operands
[0];
11904 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
11905 inst
.operands
[0].reg
= REG_SP
;
11906 inst
.operands
[0].isreg
= 1;
11907 inst
.operands
[0].writeback
= 1;
11908 inst
.operands
[0].present
= 1;
11912 do_vfp_nsyn_push (void)
11915 if (inst
.operands
[1].issingle
)
11916 do_vfp_nsyn_opcode ("fstmdbs");
11918 do_vfp_nsyn_opcode ("fstmdbd");
11922 do_vfp_nsyn_pop (void)
11925 if (inst
.operands
[1].issingle
)
11926 do_vfp_nsyn_opcode ("fldmias");
11928 do_vfp_nsyn_opcode ("fldmiad");
11931 /* Fix up Neon data-processing instructions, ORing in the correct bits for
11932 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
11935 neon_dp_fixup (unsigned i
)
11939 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
11953 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
11957 neon_logbits (unsigned x
)
11959 return ffs (x
) - 4;
11962 #define LOW4(R) ((R) & 0xf)
11963 #define HI1(R) (((R) >> 4) & 1)
11965 /* Encode insns with bit pattern:
11967 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
11968 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
11970 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
11971 different meaning for some instruction. */
11974 neon_three_same (int isquad
, int ubit
, int size
)
11976 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
11977 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
11978 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
11979 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
11980 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
11981 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
11982 inst
.instruction
|= (isquad
!= 0) << 6;
11983 inst
.instruction
|= (ubit
!= 0) << 24;
11985 inst
.instruction
|= neon_logbits (size
) << 20;
11987 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
11990 /* Encode instructions of the form:
11992 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
11993 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
11995 Don't write size if SIZE == -1. */
11998 neon_two_same (int qbit
, int ubit
, int size
)
12000 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12001 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12002 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12003 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12004 inst
.instruction
|= (qbit
!= 0) << 6;
12005 inst
.instruction
|= (ubit
!= 0) << 24;
12008 inst
.instruction
|= neon_logbits (size
) << 18;
12010 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12013 /* Neon instruction encoders, in approximate order of appearance. */
12016 do_neon_dyadic_i_su (void)
12018 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12019 struct neon_type_el et
= neon_check_type (3, rs
,
12020 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
12021 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12025 do_neon_dyadic_i64_su (void)
12027 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12028 struct neon_type_el et
= neon_check_type (3, rs
,
12029 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12030 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12034 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
12037 unsigned size
= et
.size
>> 3;
12038 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12039 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12040 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12041 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12042 inst
.instruction
|= (isquad
!= 0) << 6;
12043 inst
.instruction
|= immbits
<< 16;
12044 inst
.instruction
|= (size
>> 3) << 7;
12045 inst
.instruction
|= (size
& 0x7) << 19;
12047 inst
.instruction
|= (uval
!= 0) << 24;
12049 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12053 do_neon_shl_imm (void)
12055 if (!inst
.operands
[2].isreg
)
12057 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12058 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
12059 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12060 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
12064 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12065 struct neon_type_el et
= neon_check_type (3, rs
,
12066 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12069 /* VSHL/VQSHL 3-register variants have syntax such as:
12071 whereas other 3-register operations encoded by neon_three_same have
12074 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
12076 tmp
= inst
.operands
[2].reg
;
12077 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12078 inst
.operands
[1].reg
= tmp
;
12079 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12080 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12085 do_neon_qshl_imm (void)
12087 if (!inst
.operands
[2].isreg
)
12089 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12090 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
12092 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12093 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
12094 inst
.operands
[2].imm
);
12098 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12099 struct neon_type_el et
= neon_check_type (3, rs
,
12100 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
12103 /* See note in do_neon_shl_imm. */
12104 tmp
= inst
.operands
[2].reg
;
12105 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12106 inst
.operands
[1].reg
= tmp
;
12107 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12108 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12113 do_neon_rshl (void)
12115 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12116 struct neon_type_el et
= neon_check_type (3, rs
,
12117 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
12120 tmp
= inst
.operands
[2].reg
;
12121 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
12122 inst
.operands
[1].reg
= tmp
;
12123 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
12127 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
12129 /* Handle .I8 pseudo-instructions. */
12132 /* Unfortunately, this will make everything apart from zero out-of-range.
12133 FIXME is this the intended semantics? There doesn't seem much point in
12134 accepting .I8 if so. */
12135 immediate
|= immediate
<< 8;
12141 if (immediate
== (immediate
& 0x000000ff))
12143 *immbits
= immediate
;
12146 else if (immediate
== (immediate
& 0x0000ff00))
12148 *immbits
= immediate
>> 8;
12151 else if (immediate
== (immediate
& 0x00ff0000))
12153 *immbits
= immediate
>> 16;
12156 else if (immediate
== (immediate
& 0xff000000))
12158 *immbits
= immediate
>> 24;
12161 if ((immediate
& 0xffff) != (immediate
>> 16))
12162 goto bad_immediate
;
12163 immediate
&= 0xffff;
12166 if (immediate
== (immediate
& 0x000000ff))
12168 *immbits
= immediate
;
12171 else if (immediate
== (immediate
& 0x0000ff00))
12173 *immbits
= immediate
>> 8;
12178 first_error (_("immediate value out of range"));
12182 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
12186 neon_bits_same_in_bytes (unsigned imm
)
12188 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
12189 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
12190 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
12191 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
12194 /* For immediate of above form, return 0bABCD. */
12197 neon_squash_bits (unsigned imm
)
12199 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
12200 | ((imm
& 0x01000000) >> 21);
12203 /* Compress quarter-float representation to 0b...000 abcdefgh. */
12206 neon_qfloat_bits (unsigned imm
)
12208 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
12211 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
12212 the instruction. *OP is passed as the initial value of the op field, and
12213 may be set to a different value depending on the constant (i.e.
12214 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
12215 MVN). If the immediate looks like a repeated pattern then also
12216 try smaller element sizes. */
12219 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
12220 unsigned *immbits
, int *op
, int size
,
12221 enum neon_el_type type
)
12223 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
12225 if (type
== NT_float
&& !float_p
)
12228 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
12230 if (size
!= 32 || *op
== 1)
12232 *immbits
= neon_qfloat_bits (immlo
);
12238 if (neon_bits_same_in_bytes (immhi
)
12239 && neon_bits_same_in_bytes (immlo
))
12243 *immbits
= (neon_squash_bits (immhi
) << 4)
12244 | neon_squash_bits (immlo
);
12249 if (immhi
!= immlo
)
12255 if (immlo
== (immlo
& 0x000000ff))
12260 else if (immlo
== (immlo
& 0x0000ff00))
12262 *immbits
= immlo
>> 8;
12265 else if (immlo
== (immlo
& 0x00ff0000))
12267 *immbits
= immlo
>> 16;
12270 else if (immlo
== (immlo
& 0xff000000))
12272 *immbits
= immlo
>> 24;
12275 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
12277 *immbits
= (immlo
>> 8) & 0xff;
12280 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
12282 *immbits
= (immlo
>> 16) & 0xff;
12286 if ((immlo
& 0xffff) != (immlo
>> 16))
12293 if (immlo
== (immlo
& 0x000000ff))
12298 else if (immlo
== (immlo
& 0x0000ff00))
12300 *immbits
= immlo
>> 8;
12304 if ((immlo
& 0xff) != (immlo
>> 8))
12309 if (immlo
== (immlo
& 0x000000ff))
12311 /* Don't allow MVN with 8-bit immediate. */
12321 /* Write immediate bits [7:0] to the following locations:
12323 |28/24|23 19|18 16|15 4|3 0|
12324 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
12326 This function is used by VMOV/VMVN/VORR/VBIC. */
12329 neon_write_immbits (unsigned immbits
)
12331 inst
.instruction
|= immbits
& 0xf;
12332 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
12333 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
12336 /* Invert low-order SIZE bits of XHI:XLO. */
12339 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
12341 unsigned immlo
= xlo
? *xlo
: 0;
12342 unsigned immhi
= xhi
? *xhi
: 0;
12347 immlo
= (~immlo
) & 0xff;
12351 immlo
= (~immlo
) & 0xffff;
12355 immhi
= (~immhi
) & 0xffffffff;
12356 /* fall through. */
12359 immlo
= (~immlo
) & 0xffffffff;
12374 do_neon_logic (void)
12376 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
12378 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12379 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12380 /* U bit and size field were set as part of the bitmask. */
12381 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12382 neon_three_same (neon_quad (rs
), 0, -1);
12386 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
12387 struct neon_type_el et
= neon_check_type (2, rs
,
12388 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
12389 enum neon_opc opcode
= inst
.instruction
& 0x0fffffff;
12393 if (et
.type
== NT_invtype
)
12396 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12398 immbits
= inst
.operands
[1].imm
;
12401 /* .i64 is a pseudo-op, so the immediate must be a repeating
12403 if (immbits
!= (inst
.operands
[1].regisimm
?
12404 inst
.operands
[1].reg
: 0))
12406 /* Set immbits to an invalid constant. */
12407 immbits
= 0xdeadbeef;
12414 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12418 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12422 /* Pseudo-instruction for VBIC. */
12423 neon_invert_size (&immbits
, 0, et
.size
);
12424 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12428 /* Pseudo-instruction for VORR. */
12429 neon_invert_size (&immbits
, 0, et
.size
);
12430 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
12440 inst
.instruction
|= neon_quad (rs
) << 6;
12441 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12442 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12443 inst
.instruction
|= cmode
<< 8;
12444 neon_write_immbits (immbits
);
12446 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12451 do_neon_bitfield (void)
12453 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12454 neon_check_type (3, rs
, N_IGNORE_TYPE
);
12455 neon_three_same (neon_quad (rs
), 0, -1);
12459 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
12462 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12463 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
12465 if (et
.type
== NT_float
)
12467 inst
.instruction
= NEON_ENC_FLOAT (inst
.instruction
);
12468 neon_three_same (neon_quad (rs
), 0, -1);
12472 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12473 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
12478 do_neon_dyadic_if_su (void)
12480 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12484 do_neon_dyadic_if_su_d (void)
12486 /* This version only allow D registers, but that constraint is enforced during
12487 operand parsing so we don't need to do anything extra here. */
12488 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
12492 do_neon_dyadic_if_i_d (void)
12494 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12495 affected if we specify unsigned args. */
12496 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12499 enum vfp_or_neon_is_neon_bits
12502 NEON_CHECK_ARCH
= 2
12505 /* Call this function if an instruction which may have belonged to the VFP or
12506 Neon instruction sets, but turned out to be a Neon instruction (due to the
12507 operand types involved, etc.). We have to check and/or fix-up a couple of
12510 - Make sure the user hasn't attempted to make a Neon instruction
12512 - Alter the value in the condition code field if necessary.
12513 - Make sure that the arch supports Neon instructions.
12515 Which of these operations take place depends on bits from enum
12516 vfp_or_neon_is_neon_bits.
12518 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
12519 current instruction's condition is COND_ALWAYS, the condition field is
12520 changed to inst.uncond_value. This is necessary because instructions shared
12521 between VFP and Neon may be conditional for the VFP variants only, and the
12522 unconditional Neon version must have, e.g., 0xF in the condition field. */
12525 vfp_or_neon_is_neon (unsigned check
)
12527 /* Conditions are always legal in Thumb mode (IT blocks). */
12528 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
12530 if (inst
.cond
!= COND_ALWAYS
)
12532 first_error (_(BAD_COND
));
12535 if (inst
.uncond_value
!= -1)
12536 inst
.instruction
|= inst
.uncond_value
<< 28;
12539 if ((check
& NEON_CHECK_ARCH
)
12540 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
12542 first_error (_(BAD_FPU
));
12550 do_neon_addsub_if_i (void)
12552 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
12555 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12558 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12559 affected if we specify unsigned args. */
12560 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
12563 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
12565 V<op> A,B (A is operand 0, B is operand 2)
12570 so handle that case specially. */
12573 neon_exchange_operands (void)
12575 void *scratch
= alloca (sizeof (inst
.operands
[0]));
12576 if (inst
.operands
[1].present
)
12578 /* Swap operands[1] and operands[2]. */
12579 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
12580 inst
.operands
[1] = inst
.operands
[2];
12581 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
12585 inst
.operands
[1] = inst
.operands
[2];
12586 inst
.operands
[2] = inst
.operands
[0];
12591 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
12593 if (inst
.operands
[2].isreg
)
12596 neon_exchange_operands ();
12597 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
12601 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12602 struct neon_type_el et
= neon_check_type (2, rs
,
12603 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
12605 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
12606 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12607 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12608 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12609 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12610 inst
.instruction
|= neon_quad (rs
) << 6;
12611 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12612 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12614 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12621 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
12625 do_neon_cmp_inv (void)
12627 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
12633 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
12636 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
12637 scalars, which are encoded in 5 bits, M : Rm.
12638 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
12639 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
12643 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
12645 unsigned regno
= NEON_SCALAR_REG (scalar
);
12646 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
12651 if (regno
> 7 || elno
> 3)
12653 return regno
| (elno
<< 3);
12656 if (regno
> 15 || elno
> 1)
12658 return regno
| (elno
<< 4);
12662 first_error (_("scalar out of range for multiply instruction"));
12668 /* Encode multiply / multiply-accumulate scalar instructions. */
12671 neon_mul_mac (struct neon_type_el et
, int ubit
)
12675 /* Give a more helpful error message if we have an invalid type. */
12676 if (et
.type
== NT_invtype
)
12679 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
12680 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12681 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12682 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
12683 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
12684 inst
.instruction
|= LOW4 (scalar
);
12685 inst
.instruction
|= HI1 (scalar
) << 5;
12686 inst
.instruction
|= (et
.type
== NT_float
) << 8;
12687 inst
.instruction
|= neon_logbits (et
.size
) << 20;
12688 inst
.instruction
|= (ubit
!= 0) << 24;
12690 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12694 do_neon_mac_maybe_scalar (void)
12696 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
12699 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12702 if (inst
.operands
[2].isscalar
)
12704 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12705 struct neon_type_el et
= neon_check_type (3, rs
,
12706 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
12707 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12708 neon_mul_mac (et
, neon_quad (rs
));
12712 /* The "untyped" case can't happen. Do this to stop the "U" bit being
12713 affected if we specify unsigned args. */
12714 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
12721 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12722 struct neon_type_el et
= neon_check_type (3, rs
,
12723 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
12724 neon_three_same (neon_quad (rs
), 0, et
.size
);
12727 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
12728 same types as the MAC equivalents. The polynomial type for this instruction
12729 is encoded the same as the integer type. */
12734 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
12737 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12740 if (inst
.operands
[2].isscalar
)
12741 do_neon_mac_maybe_scalar ();
12743 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
12747 do_neon_qdmulh (void)
12749 if (inst
.operands
[2].isscalar
)
12751 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
12752 struct neon_type_el et
= neon_check_type (3, rs
,
12753 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12754 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
12755 neon_mul_mac (et
, neon_quad (rs
));
12759 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12760 struct neon_type_el et
= neon_check_type (3, rs
,
12761 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
12762 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12763 /* The U bit (rounding) comes from bit mask. */
12764 neon_three_same (neon_quad (rs
), 0, et
.size
);
12769 do_neon_fcmp_absolute (void)
12771 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12772 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12773 /* Size field comes from bit mask. */
12774 neon_three_same (neon_quad (rs
), 1, -1);
12778 do_neon_fcmp_absolute_inv (void)
12780 neon_exchange_operands ();
12781 do_neon_fcmp_absolute ();
12785 do_neon_step (void)
12787 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
12788 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
12789 neon_three_same (neon_quad (rs
), 0, -1);
12793 do_neon_abs_neg (void)
12795 enum neon_shape rs
;
12796 struct neon_type_el et
;
12798 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
12801 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
12804 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
12805 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
12807 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12808 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12809 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12810 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12811 inst
.instruction
|= neon_quad (rs
) << 6;
12812 inst
.instruction
|= (et
.type
== NT_float
) << 10;
12813 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12815 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12821 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12822 struct neon_type_el et
= neon_check_type (2, rs
,
12823 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12824 int imm
= inst
.operands
[2].imm
;
12825 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12826 _("immediate out of range for insert"));
12827 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12833 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12834 struct neon_type_el et
= neon_check_type (2, rs
,
12835 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
12836 int imm
= inst
.operands
[2].imm
;
12837 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12838 _("immediate out of range for insert"));
12839 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
12843 do_neon_qshlu_imm (void)
12845 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
12846 struct neon_type_el et
= neon_check_type (2, rs
,
12847 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
12848 int imm
= inst
.operands
[2].imm
;
12849 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
12850 _("immediate out of range for shift"));
12851 /* Only encodes the 'U present' variant of the instruction.
12852 In this case, signed types have OP (bit 8) set to 0.
12853 Unsigned types have OP set to 1. */
12854 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
12855 /* The rest of the bits are the same as other immediate shifts. */
12856 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
12860 do_neon_qmovn (void)
12862 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12863 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12864 /* Saturating move where operands can be signed or unsigned, and the
12865 destination has the same signedness. */
12866 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12867 if (et
.type
== NT_unsigned
)
12868 inst
.instruction
|= 0xc0;
12870 inst
.instruction
|= 0x80;
12871 neon_two_same (0, 1, et
.size
/ 2);
12875 do_neon_qmovun (void)
12877 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12878 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12879 /* Saturating move with unsigned results. Operands must be signed. */
12880 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12881 neon_two_same (0, 1, et
.size
/ 2);
12885 do_neon_rshift_sat_narrow (void)
12887 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12888 or unsigned. If operands are unsigned, results must also be unsigned. */
12889 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12890 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
12891 int imm
= inst
.operands
[2].imm
;
12892 /* This gets the bounds check, size encoding and immediate bits calculation
12896 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
12897 VQMOVN.I<size> <Dd>, <Qm>. */
12900 inst
.operands
[2].present
= 0;
12901 inst
.instruction
= N_MNEM_vqmovn
;
12906 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12907 _("immediate out of range"));
12908 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
12912 do_neon_rshift_sat_narrow_u (void)
12914 /* FIXME: Types for narrowing. If operands are signed, results can be signed
12915 or unsigned. If operands are unsigned, results must also be unsigned. */
12916 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12917 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
12918 int imm
= inst
.operands
[2].imm
;
12919 /* This gets the bounds check, size encoding and immediate bits calculation
12923 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
12924 VQMOVUN.I<size> <Dd>, <Qm>. */
12927 inst
.operands
[2].present
= 0;
12928 inst
.instruction
= N_MNEM_vqmovun
;
12933 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12934 _("immediate out of range"));
12935 /* FIXME: The manual is kind of unclear about what value U should have in
12936 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
12938 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
12942 do_neon_movn (void)
12944 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
12945 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12946 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12947 neon_two_same (0, 1, et
.size
/ 2);
12951 do_neon_rshift_narrow (void)
12953 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
12954 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
12955 int imm
= inst
.operands
[2].imm
;
12956 /* This gets the bounds check, size encoding and immediate bits calculation
12960 /* If immediate is zero then we are a pseudo-instruction for
12961 VMOVN.I<size> <Dd>, <Qm> */
12964 inst
.operands
[2].present
= 0;
12965 inst
.instruction
= N_MNEM_vmovn
;
12970 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
12971 _("immediate out of range for narrowing operation"));
12972 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
12976 do_neon_shll (void)
12978 /* FIXME: Type checking when lengthening. */
12979 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
12980 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
12981 unsigned imm
= inst
.operands
[2].imm
;
12983 if (imm
== et
.size
)
12985 /* Maximum shift variant. */
12986 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
12987 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
12988 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
12989 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
12990 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
12991 inst
.instruction
|= neon_logbits (et
.size
) << 18;
12993 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
12997 /* A more-specific type check for non-max versions. */
12998 et
= neon_check_type (2, NS_QDI
,
12999 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13000 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13001 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
13005 /* Check the various types for the VCVT instruction, and return which version
13006 the current instruction is. */
13009 neon_cvt_flavour (enum neon_shape rs
)
13011 #define CVT_VAR(C,X,Y) \
13012 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
13013 if (et.type != NT_invtype) \
13015 inst.error = NULL; \
13018 struct neon_type_el et
;
13019 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
13020 || rs
== NS_FF
) ? N_VFP
: 0;
13021 /* The instruction versions which take an immediate take one register
13022 argument, which is extended to the width of the full register. Thus the
13023 "source" and "destination" registers must have the same width. Hack that
13024 here by making the size equal to the key (wider, in this case) operand. */
13025 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
13027 CVT_VAR (0, N_S32
, N_F32
);
13028 CVT_VAR (1, N_U32
, N_F32
);
13029 CVT_VAR (2, N_F32
, N_S32
);
13030 CVT_VAR (3, N_F32
, N_U32
);
13031 /* Half-precision conversions. */
13032 CVT_VAR (4, N_F32
, N_F16
);
13033 CVT_VAR (5, N_F16
, N_F32
);
13037 /* VFP instructions. */
13038 CVT_VAR (6, N_F32
, N_F64
);
13039 CVT_VAR (7, N_F64
, N_F32
);
13040 CVT_VAR (8, N_S32
, N_F64
| key
);
13041 CVT_VAR (9, N_U32
, N_F64
| key
);
13042 CVT_VAR (10, N_F64
| key
, N_S32
);
13043 CVT_VAR (11, N_F64
| key
, N_U32
);
13044 /* VFP instructions with bitshift. */
13045 CVT_VAR (12, N_F32
| key
, N_S16
);
13046 CVT_VAR (13, N_F32
| key
, N_U16
);
13047 CVT_VAR (14, N_F64
| key
, N_S16
);
13048 CVT_VAR (15, N_F64
| key
, N_U16
);
13049 CVT_VAR (16, N_S16
, N_F32
| key
);
13050 CVT_VAR (17, N_U16
, N_F32
| key
);
13051 CVT_VAR (18, N_S16
, N_F64
| key
);
13052 CVT_VAR (19, N_U16
, N_F64
| key
);
13058 /* Neon-syntax VFP conversions. */
13061 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
13063 const char *opname
= 0;
13065 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
13067 /* Conversions with immediate bitshift. */
13068 const char *enc
[] =
13092 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13094 opname
= enc
[flavour
];
13095 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13096 _("operands 0 and 1 must be the same register"));
13097 inst
.operands
[1] = inst
.operands
[2];
13098 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
13103 /* Conversions without bitshift. */
13104 const char *enc
[] =
13120 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
13121 opname
= enc
[flavour
];
13125 do_vfp_nsyn_opcode (opname
);
13129 do_vfp_nsyn_cvtz (void)
13131 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
13132 int flavour
= neon_cvt_flavour (rs
);
13133 const char *enc
[] =
13147 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
13148 do_vfp_nsyn_opcode (enc
[flavour
]);
13154 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
13155 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
13156 int flavour
= neon_cvt_flavour (rs
);
13158 /* VFP rather than Neon conversions. */
13161 do_vfp_nsyn_cvt (rs
, flavour
);
13171 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
13173 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13176 /* Fixed-point conversion with #0 immediate is encoded as an
13177 integer conversion. */
13178 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
13180 immbits
= 32 - inst
.operands
[2].imm
;
13181 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13183 inst
.instruction
|= enctab
[flavour
];
13184 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13185 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13186 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13187 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13188 inst
.instruction
|= neon_quad (rs
) << 6;
13189 inst
.instruction
|= 1 << 21;
13190 inst
.instruction
|= immbits
<< 16;
13192 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13200 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
13202 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13204 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13208 inst
.instruction
|= enctab
[flavour
];
13210 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13211 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13212 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13213 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13214 inst
.instruction
|= neon_quad (rs
) << 6;
13215 inst
.instruction
|= 2 << 18;
13217 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13221 /* Half-precision conversions for Advanced SIMD -- neon. */
13226 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
13228 as_bad (_("operand size must match register width"));
13233 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
13235 as_bad (_("operand size must match register width"));
13240 inst
.instruction
= 0x3b60600;
13242 inst
.instruction
= 0x3b60700;
13244 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13245 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13246 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13247 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13248 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13252 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
13253 do_vfp_nsyn_cvt (rs
, flavour
);
13258 do_neon_cvtb (void)
13260 inst
.instruction
= 0xeb20a40;
13262 /* The sizes are attached to the mnemonic. */
13263 if (inst
.vectype
.el
[0].type
!= NT_invtype
13264 && inst
.vectype
.el
[0].size
== 16)
13265 inst
.instruction
|= 0x00010000;
13267 /* Programmer's syntax: the sizes are attached to the operands. */
13268 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
13269 && inst
.operands
[0].vectype
.size
== 16)
13270 inst
.instruction
|= 0x00010000;
13272 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
13273 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
13274 do_vfp_cond_or_thumb ();
13279 do_neon_cvtt (void)
13282 inst
.instruction
|= 0x80;
13286 neon_move_immediate (void)
13288 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
13289 struct neon_type_el et
= neon_check_type (2, rs
,
13290 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13291 unsigned immlo
, immhi
= 0, immbits
;
13292 int op
, cmode
, float_p
;
13294 constraint (et
.type
== NT_invtype
,
13295 _("operand size must be specified for immediate VMOV"));
13297 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
13298 op
= (inst
.instruction
& (1 << 5)) != 0;
13300 immlo
= inst
.operands
[1].imm
;
13301 if (inst
.operands
[1].regisimm
)
13302 immhi
= inst
.operands
[1].reg
;
13304 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
13305 _("immediate has bits set outside the operand size"));
13307 float_p
= inst
.operands
[1].immisfloat
;
13309 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
13310 et
.size
, et
.type
)) == FAIL
)
13312 /* Invert relevant bits only. */
13313 neon_invert_size (&immlo
, &immhi
, et
.size
);
13314 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
13315 with one or the other; those cases are caught by
13316 neon_cmode_for_move_imm. */
13318 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
13319 &op
, et
.size
, et
.type
)) == FAIL
)
13321 first_error (_("immediate out of range"));
13326 inst
.instruction
&= ~(1 << 5);
13327 inst
.instruction
|= op
<< 5;
13329 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13330 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13331 inst
.instruction
|= neon_quad (rs
) << 6;
13332 inst
.instruction
|= cmode
<< 8;
13334 neon_write_immbits (immbits
);
13340 if (inst
.operands
[1].isreg
)
13342 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13344 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13345 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13346 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13347 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13348 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13349 inst
.instruction
|= neon_quad (rs
) << 6;
13353 inst
.instruction
= NEON_ENC_IMMED (inst
.instruction
);
13354 neon_move_immediate ();
13357 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13360 /* Encode instructions of form:
13362 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13363 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
13366 neon_mixed_length (struct neon_type_el et
, unsigned size
)
13368 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13369 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13370 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13371 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13372 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13373 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13374 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
13375 inst
.instruction
|= neon_logbits (size
) << 20;
13377 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13381 do_neon_dyadic_long (void)
13383 /* FIXME: Type checking for lengthening op. */
13384 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13385 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13386 neon_mixed_length (et
, et
.size
);
13390 do_neon_abal (void)
13392 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13393 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
13394 neon_mixed_length (et
, et
.size
);
13398 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
13400 if (inst
.operands
[2].isscalar
)
13402 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
13403 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
13404 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13405 neon_mul_mac (et
, et
.type
== NT_unsigned
);
13409 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13410 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
13411 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13412 neon_mixed_length (et
, et
.size
);
13417 do_neon_mac_maybe_scalar_long (void)
13419 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
13423 do_neon_dyadic_wide (void)
13425 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
13426 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13427 neon_mixed_length (et
, et
.size
);
13431 do_neon_dyadic_narrow (void)
13433 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13434 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
13435 /* Operand sign is unimportant, and the U bit is part of the opcode,
13436 so force the operand type to integer. */
13437 et
.type
= NT_integer
;
13438 neon_mixed_length (et
, et
.size
/ 2);
13442 do_neon_mul_sat_scalar_long (void)
13444 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
13448 do_neon_vmull (void)
13450 if (inst
.operands
[2].isscalar
)
13451 do_neon_mac_maybe_scalar_long ();
13454 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
13455 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
13456 if (et
.type
== NT_poly
)
13457 inst
.instruction
= NEON_ENC_POLY (inst
.instruction
);
13459 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13460 /* For polynomial encoding, size field must be 0b00 and the U bit must be
13461 zero. Should be OK as-is. */
13462 neon_mixed_length (et
, et
.size
);
13469 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
13470 struct neon_type_el et
= neon_check_type (3, rs
,
13471 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13472 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
13474 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
13475 _("shift out of range"));
13476 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13477 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13478 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13479 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13480 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13481 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13482 inst
.instruction
|= neon_quad (rs
) << 6;
13483 inst
.instruction
|= imm
<< 8;
13485 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13491 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13492 struct neon_type_el et
= neon_check_type (2, rs
,
13493 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13494 unsigned op
= (inst
.instruction
>> 7) & 3;
13495 /* N (width of reversed regions) is encoded as part of the bitmask. We
13496 extract it here to check the elements to be reversed are smaller.
13497 Otherwise we'd get a reserved instruction. */
13498 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
13499 assert (elsize
!= 0);
13500 constraint (et
.size
>= elsize
,
13501 _("elements must be smaller than reversal region"));
13502 neon_two_same (neon_quad (rs
), 1, et
.size
);
13508 if (inst
.operands
[1].isscalar
)
13510 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
13511 struct neon_type_el et
= neon_check_type (2, rs
,
13512 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13513 unsigned sizebits
= et
.size
>> 3;
13514 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13515 int logsize
= neon_logbits (et
.size
);
13516 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
13518 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
13521 inst
.instruction
= NEON_ENC_SCALAR (inst
.instruction
);
13522 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13523 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13524 inst
.instruction
|= LOW4 (dm
);
13525 inst
.instruction
|= HI1 (dm
) << 5;
13526 inst
.instruction
|= neon_quad (rs
) << 6;
13527 inst
.instruction
|= x
<< 17;
13528 inst
.instruction
|= sizebits
<< 16;
13530 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13534 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
13535 struct neon_type_el et
= neon_check_type (2, rs
,
13536 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13537 /* Duplicate ARM register to lanes of vector. */
13538 inst
.instruction
= NEON_ENC_ARMREG (inst
.instruction
);
13541 case 8: inst
.instruction
|= 0x400000; break;
13542 case 16: inst
.instruction
|= 0x000020; break;
13543 case 32: inst
.instruction
|= 0x000000; break;
13546 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13547 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
13548 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
13549 inst
.instruction
|= neon_quad (rs
) << 21;
13550 /* The encoding for this instruction is identical for the ARM and Thumb
13551 variants, except for the condition field. */
13552 do_vfp_cond_or_thumb ();
13556 /* VMOV has particularly many variations. It can be one of:
13557 0. VMOV<c><q> <Qd>, <Qm>
13558 1. VMOV<c><q> <Dd>, <Dm>
13559 (Register operations, which are VORR with Rm = Rn.)
13560 2. VMOV<c><q>.<dt> <Qd>, #<imm>
13561 3. VMOV<c><q>.<dt> <Dd>, #<imm>
13563 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
13564 (ARM register to scalar.)
13565 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
13566 (Two ARM registers to vector.)
13567 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
13568 (Scalar to ARM register.)
13569 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
13570 (Vector to two ARM registers.)
13571 8. VMOV.F32 <Sd>, <Sm>
13572 9. VMOV.F64 <Dd>, <Dm>
13573 (VFP register moves.)
13574 10. VMOV.F32 <Sd>, #imm
13575 11. VMOV.F64 <Dd>, #imm
13576 (VFP float immediate load.)
13577 12. VMOV <Rd>, <Sm>
13578 (VFP single to ARM reg.)
13579 13. VMOV <Sd>, <Rm>
13580 (ARM reg to VFP single.)
13581 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
13582 (Two ARM regs to two VFP singles.)
13583 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
13584 (Two VFP singles to two ARM regs.)
13586 These cases can be disambiguated using neon_select_shape, except cases 1/9
13587 and 3/11 which depend on the operand type too.
13589 All the encoded bits are hardcoded by this function.
13591 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
13592 Cases 5, 7 may be used with VFPv2 and above.
13594 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
13595 can specify a type where it doesn't make sense to, and is ignored). */
13600 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
13601 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
13603 struct neon_type_el et
;
13604 const char *ldconst
= 0;
13608 case NS_DD
: /* case 1/9. */
13609 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13610 /* It is not an error here if no type is given. */
13612 if (et
.type
== NT_float
&& et
.size
== 64)
13614 do_vfp_nsyn_opcode ("fcpyd");
13617 /* fall through. */
13619 case NS_QQ
: /* case 0/1. */
13621 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13623 /* The architecture manual I have doesn't explicitly state which
13624 value the U bit should have for register->register moves, but
13625 the equivalent VORR instruction has U = 0, so do that. */
13626 inst
.instruction
= 0x0200110;
13627 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13628 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13629 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13630 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13631 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13632 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13633 inst
.instruction
|= neon_quad (rs
) << 6;
13635 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13639 case NS_DI
: /* case 3/11. */
13640 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
13642 if (et
.type
== NT_float
&& et
.size
== 64)
13644 /* case 11 (fconstd). */
13645 ldconst
= "fconstd";
13646 goto encode_fconstd
;
13648 /* fall through. */
13650 case NS_QI
: /* case 2/3. */
13651 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13653 inst
.instruction
= 0x0800010;
13654 neon_move_immediate ();
13655 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13658 case NS_SR
: /* case 4. */
13660 unsigned bcdebits
= 0;
13661 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13662 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
13663 int logsize
= neon_logbits (et
.size
);
13664 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
13665 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
13667 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13669 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13670 && et
.size
!= 32, _(BAD_FPU
));
13671 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13672 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13676 case 8: bcdebits
= 0x8; break;
13677 case 16: bcdebits
= 0x1; break;
13678 case 32: bcdebits
= 0x0; break;
13682 bcdebits
|= x
<< logsize
;
13684 inst
.instruction
= 0xe000b10;
13685 do_vfp_cond_or_thumb ();
13686 inst
.instruction
|= LOW4 (dn
) << 16;
13687 inst
.instruction
|= HI1 (dn
) << 7;
13688 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13689 inst
.instruction
|= (bcdebits
& 3) << 5;
13690 inst
.instruction
|= (bcdebits
>> 2) << 21;
13694 case NS_DRR
: /* case 5 (fmdrr). */
13695 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13698 inst
.instruction
= 0xc400b10;
13699 do_vfp_cond_or_thumb ();
13700 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
13701 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
13702 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13703 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13706 case NS_RS
: /* case 6. */
13708 struct neon_type_el et
= neon_check_type (2, NS_NULL
,
13709 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
13710 unsigned logsize
= neon_logbits (et
.size
);
13711 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
13712 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
13713 unsigned abcdebits
= 0;
13715 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
13717 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
13718 && et
.size
!= 32, _(BAD_FPU
));
13719 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
13720 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
13724 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
13725 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
13726 case 32: abcdebits
= 0x00; break;
13730 abcdebits
|= x
<< logsize
;
13731 inst
.instruction
= 0xe100b10;
13732 do_vfp_cond_or_thumb ();
13733 inst
.instruction
|= LOW4 (dn
) << 16;
13734 inst
.instruction
|= HI1 (dn
) << 7;
13735 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13736 inst
.instruction
|= (abcdebits
& 3) << 5;
13737 inst
.instruction
|= (abcdebits
>> 2) << 21;
13741 case NS_RRD
: /* case 7 (fmrrd). */
13742 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
13745 inst
.instruction
= 0xc500b10;
13746 do_vfp_cond_or_thumb ();
13747 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
13748 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13749 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13750 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13753 case NS_FF
: /* case 8 (fcpys). */
13754 do_vfp_nsyn_opcode ("fcpys");
13757 case NS_FI
: /* case 10 (fconsts). */
13758 ldconst
= "fconsts";
13760 if (is_quarter_float (inst
.operands
[1].imm
))
13762 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
13763 do_vfp_nsyn_opcode (ldconst
);
13766 first_error (_("immediate out of range"));
13769 case NS_RF
: /* case 12 (fmrs). */
13770 do_vfp_nsyn_opcode ("fmrs");
13773 case NS_FR
: /* case 13 (fmsr). */
13774 do_vfp_nsyn_opcode ("fmsr");
13777 /* The encoders for the fmrrs and fmsrr instructions expect three operands
13778 (one of which is a list), but we have parsed four. Do some fiddling to
13779 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
13781 case NS_RRFF
: /* case 14 (fmrrs). */
13782 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
13783 _("VFP registers must be adjacent"));
13784 inst
.operands
[2].imm
= 2;
13785 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13786 do_vfp_nsyn_opcode ("fmrrs");
13789 case NS_FFRR
: /* case 15 (fmsrr). */
13790 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
13791 _("VFP registers must be adjacent"));
13792 inst
.operands
[1] = inst
.operands
[2];
13793 inst
.operands
[2] = inst
.operands
[3];
13794 inst
.operands
[0].imm
= 2;
13795 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
13796 do_vfp_nsyn_opcode ("fmsrr");
13805 do_neon_rshift_round_imm (void)
13807 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13808 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13809 int imm
= inst
.operands
[2].imm
;
13811 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
13814 inst
.operands
[2].present
= 0;
13819 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13820 _("immediate out of range for shift"));
13821 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13826 do_neon_movl (void)
13828 struct neon_type_el et
= neon_check_type (2, NS_QD
,
13829 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
13830 unsigned sizebits
= et
.size
>> 3;
13831 inst
.instruction
|= sizebits
<< 19;
13832 neon_two_same (0, et
.type
== NT_unsigned
, -1);
13838 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13839 struct neon_type_el et
= neon_check_type (2, rs
,
13840 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13841 inst
.instruction
= NEON_ENC_INTEGER (inst
.instruction
);
13842 neon_two_same (neon_quad (rs
), 1, et
.size
);
13846 do_neon_zip_uzp (void)
13848 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13849 struct neon_type_el et
= neon_check_type (2, rs
,
13850 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13851 if (rs
== NS_DD
&& et
.size
== 32)
13853 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
13854 inst
.instruction
= N_MNEM_vtrn
;
13858 neon_two_same (neon_quad (rs
), 1, et
.size
);
13862 do_neon_sat_abs_neg (void)
13864 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13865 struct neon_type_el et
= neon_check_type (2, rs
,
13866 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13867 neon_two_same (neon_quad (rs
), 1, et
.size
);
13871 do_neon_pair_long (void)
13873 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13874 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
13875 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
13876 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
13877 neon_two_same (neon_quad (rs
), 1, et
.size
);
13881 do_neon_recip_est (void)
13883 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13884 struct neon_type_el et
= neon_check_type (2, rs
,
13885 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
13886 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13887 neon_two_same (neon_quad (rs
), 1, et
.size
);
13893 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13894 struct neon_type_el et
= neon_check_type (2, rs
,
13895 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
13896 neon_two_same (neon_quad (rs
), 1, et
.size
);
13902 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13903 struct neon_type_el et
= neon_check_type (2, rs
,
13904 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
13905 neon_two_same (neon_quad (rs
), 1, et
.size
);
13911 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13912 struct neon_type_el et
= neon_check_type (2, rs
,
13913 N_EQK
| N_INT
, N_8
| N_KEY
);
13914 neon_two_same (neon_quad (rs
), 1, et
.size
);
13920 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13921 neon_two_same (neon_quad (rs
), 1, -1);
13925 do_neon_tbl_tbx (void)
13927 unsigned listlenbits
;
13928 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
13930 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
13932 first_error (_("bad list length for table lookup"));
13936 listlenbits
= inst
.operands
[1].imm
- 1;
13937 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13938 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13939 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13940 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13941 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13942 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13943 inst
.instruction
|= listlenbits
<< 8;
13945 inst
.instruction
= neon_dp_fixup (inst
.instruction
);
13949 do_neon_ldm_stm (void)
13951 /* P, U and L bits are part of bitmask. */
13952 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
13953 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
13955 if (inst
.operands
[1].issingle
)
13957 do_vfp_nsyn_ldm_stm (is_dbmode
);
13961 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
13962 _("writeback (!) must be used for VLDMDB and VSTMDB"));
13964 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
13965 _("register list must contain at least 1 and at most 16 "
13968 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
13969 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
13970 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
13971 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
13973 inst
.instruction
|= offsetbits
;
13975 do_vfp_cond_or_thumb ();
13979 do_neon_ldr_str (void)
13981 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
13983 if (inst
.operands
[0].issingle
)
13986 do_vfp_nsyn_opcode ("flds");
13988 do_vfp_nsyn_opcode ("fsts");
13993 do_vfp_nsyn_opcode ("fldd");
13995 do_vfp_nsyn_opcode ("fstd");
13999 /* "interleave" version also handles non-interleaving register VLD1/VST1
14003 do_neon_ld_st_interleave (void)
14005 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
14006 N_8
| N_16
| N_32
| N_64
);
14007 unsigned alignbits
= 0;
14009 /* The bits in this table go:
14010 0: register stride of one (0) or two (1)
14011 1,2: register list length, minus one (1, 2, 3, 4).
14012 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
14013 We use -1 for invalid entries. */
14014 const int typetable
[] =
14016 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
14017 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
14018 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
14019 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
14023 if (et
.type
== NT_invtype
)
14026 if (inst
.operands
[1].immisalign
)
14027 switch (inst
.operands
[1].imm
>> 8)
14029 case 64: alignbits
= 1; break;
14031 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14032 goto bad_alignment
;
14036 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) == 3)
14037 goto bad_alignment
;
14042 first_error (_("bad alignment"));
14046 inst
.instruction
|= alignbits
<< 4;
14047 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14049 /* Bits [4:6] of the immediate in a list specifier encode register stride
14050 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
14051 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
14052 up the right value for "type" in a table based on this value and the given
14053 list style, then stick it back. */
14054 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
14055 | (((inst
.instruction
>> 8) & 3) << 3);
14057 typebits
= typetable
[idx
];
14059 constraint (typebits
== -1, _("bad list type for instruction"));
14061 inst
.instruction
&= ~0xf00;
14062 inst
.instruction
|= typebits
<< 8;
14065 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
14066 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
14067 otherwise. The variable arguments are a list of pairs of legal (size, align)
14068 values, terminated with -1. */
14071 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
14074 int result
= FAIL
, thissize
, thisalign
;
14076 if (!inst
.operands
[1].immisalign
)
14082 va_start (ap
, do_align
);
14086 thissize
= va_arg (ap
, int);
14087 if (thissize
== -1)
14089 thisalign
= va_arg (ap
, int);
14091 if (size
== thissize
&& align
== thisalign
)
14094 while (result
!= SUCCESS
);
14098 if (result
== SUCCESS
)
14101 first_error (_("unsupported alignment for instruction"));
14107 do_neon_ld_st_lane (void)
14109 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14110 int align_good
, do_align
= 0;
14111 int logsize
= neon_logbits (et
.size
);
14112 int align
= inst
.operands
[1].imm
>> 8;
14113 int n
= (inst
.instruction
>> 8) & 3;
14114 int max_el
= 64 / et
.size
;
14116 if (et
.type
== NT_invtype
)
14119 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
14120 _("bad list length"));
14121 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
14122 _("scalar index out of range"));
14123 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
14125 _("stride of 2 unavailable when element size is 8"));
14129 case 0: /* VLD1 / VST1. */
14130 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
14132 if (align_good
== FAIL
)
14136 unsigned alignbits
= 0;
14139 case 16: alignbits
= 0x1; break;
14140 case 32: alignbits
= 0x3; break;
14143 inst
.instruction
|= alignbits
<< 4;
14147 case 1: /* VLD2 / VST2. */
14148 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
14150 if (align_good
== FAIL
)
14153 inst
.instruction
|= 1 << 4;
14156 case 2: /* VLD3 / VST3. */
14157 constraint (inst
.operands
[1].immisalign
,
14158 _("can't use alignment with this instruction"));
14161 case 3: /* VLD4 / VST4. */
14162 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14163 16, 64, 32, 64, 32, 128, -1);
14164 if (align_good
== FAIL
)
14168 unsigned alignbits
= 0;
14171 case 8: alignbits
= 0x1; break;
14172 case 16: alignbits
= 0x1; break;
14173 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
14176 inst
.instruction
|= alignbits
<< 4;
14183 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
14184 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14185 inst
.instruction
|= 1 << (4 + logsize
);
14187 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
14188 inst
.instruction
|= logsize
<< 10;
14191 /* Encode single n-element structure to all lanes VLD<n> instructions. */
14194 do_neon_ld_dup (void)
14196 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
14197 int align_good
, do_align
= 0;
14199 if (et
.type
== NT_invtype
)
14202 switch ((inst
.instruction
>> 8) & 3)
14204 case 0: /* VLD1. */
14205 assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
14206 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14207 &do_align
, 16, 16, 32, 32, -1);
14208 if (align_good
== FAIL
)
14210 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
14213 case 2: inst
.instruction
|= 1 << 5; break;
14214 default: first_error (_("bad list length")); return;
14216 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14219 case 1: /* VLD2. */
14220 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
14221 &do_align
, 8, 16, 16, 32, 32, 64, -1);
14222 if (align_good
== FAIL
)
14224 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
14225 _("bad list length"));
14226 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14227 inst
.instruction
|= 1 << 5;
14228 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14231 case 2: /* VLD3. */
14232 constraint (inst
.operands
[1].immisalign
,
14233 _("can't use alignment with this instruction"));
14234 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
14235 _("bad list length"));
14236 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14237 inst
.instruction
|= 1 << 5;
14238 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14241 case 3: /* VLD4. */
14243 int align
= inst
.operands
[1].imm
>> 8;
14244 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
14245 16, 64, 32, 64, 32, 128, -1);
14246 if (align_good
== FAIL
)
14248 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
14249 _("bad list length"));
14250 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
14251 inst
.instruction
|= 1 << 5;
14252 if (et
.size
== 32 && align
== 128)
14253 inst
.instruction
|= 0x3 << 6;
14255 inst
.instruction
|= neon_logbits (et
.size
) << 6;
14262 inst
.instruction
|= do_align
<< 4;
14265 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
14266 apart from bits [11:4]. */
14269 do_neon_ldx_stx (void)
14271 switch (NEON_LANE (inst
.operands
[0].imm
))
14273 case NEON_INTERLEAVE_LANES
:
14274 inst
.instruction
= NEON_ENC_INTERLV (inst
.instruction
);
14275 do_neon_ld_st_interleave ();
14278 case NEON_ALL_LANES
:
14279 inst
.instruction
= NEON_ENC_DUP (inst
.instruction
);
14284 inst
.instruction
= NEON_ENC_LANE (inst
.instruction
);
14285 do_neon_ld_st_lane ();
14288 /* L bit comes from bit mask. */
14289 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14290 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14291 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14293 if (inst
.operands
[1].postind
)
14295 int postreg
= inst
.operands
[1].imm
& 0xf;
14296 constraint (!inst
.operands
[1].immisreg
,
14297 _("post-index must be a register"));
14298 constraint (postreg
== 0xd || postreg
== 0xf,
14299 _("bad register for post-index"));
14300 inst
.instruction
|= postreg
;
14302 else if (inst
.operands
[1].writeback
)
14304 inst
.instruction
|= 0xd;
14307 inst
.instruction
|= 0xf;
14310 inst
.instruction
|= 0xf9000000;
14312 inst
.instruction
|= 0xf4000000;
14315 /* Overall per-instruction processing. */
14317 /* We need to be able to fix up arbitrary expressions in some statements.
14318 This is so that we can handle symbols that are an arbitrary distance from
14319 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
14320 which returns part of an address in a form which will be valid for
14321 a data instruction. We do this by pushing the expression into a symbol
14322 in the expr_section, and creating a fix for that. */
14325 fix_new_arm (fragS
* frag
,
14340 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
, reloc
);
14344 new_fix
= fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
14349 /* Mark whether the fix is to a THUMB instruction, or an ARM
14351 new_fix
->tc_fix_data
= thumb_mode
;
14354 /* Create a frg for an instruction requiring relaxation. */
14356 output_relax_insn (void)
14362 /* The size of the instruction is unknown, so tie the debug info to the
14363 start of the instruction. */
14364 dwarf2_emit_insn (0);
14366 switch (inst
.reloc
.exp
.X_op
)
14369 sym
= inst
.reloc
.exp
.X_add_symbol
;
14370 offset
= inst
.reloc
.exp
.X_add_number
;
14374 offset
= inst
.reloc
.exp
.X_add_number
;
14377 sym
= make_expr_symbol (&inst
.reloc
.exp
);
14381 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
14382 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
14383 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
14386 /* Write a 32-bit thumb instruction to buf. */
14388 put_thumb32_insn (char * buf
, unsigned long insn
)
14390 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
14391 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
14395 output_inst (const char * str
)
14401 as_bad ("%s -- `%s'", inst
.error
, str
);
14406 output_relax_insn ();
14409 if (inst
.size
== 0)
14412 to
= frag_more (inst
.size
);
14413 /* PR 9814: Record the thumb mode into the current frag so that we know
14414 what type of NOP padding to use, if necessary. We override any previous
14415 setting so that if the mode has changed then the NOPS that we use will
14416 match the encoding of the last instruction in the frag. */
14417 frag_now
->tc_frag_data
= thumb_mode
| MODE_RECORDED
;
14419 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
14421 assert (inst
.size
== (2 * THUMB_SIZE
));
14422 put_thumb32_insn (to
, inst
.instruction
);
14424 else if (inst
.size
> INSN_SIZE
)
14426 assert (inst
.size
== (2 * INSN_SIZE
));
14427 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
14428 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
14431 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
14433 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
14434 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
14435 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
14438 dwarf2_emit_insn (inst
.size
);
14441 /* Tag values used in struct asm_opcode's tag field. */
14444 OT_unconditional
, /* Instruction cannot be conditionalized.
14445 The ARM condition field is still 0xE. */
14446 OT_unconditionalF
, /* Instruction cannot be conditionalized
14447 and carries 0xF in its ARM condition field. */
14448 OT_csuffix
, /* Instruction takes a conditional suffix. */
14449 OT_csuffixF
, /* Some forms of the instruction take a conditional
14450 suffix, others place 0xF where the condition field
14452 OT_cinfix3
, /* Instruction takes a conditional infix,
14453 beginning at character index 3. (In
14454 unified mode, it becomes a suffix.) */
14455 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
14456 tsts, cmps, cmns, and teqs. */
14457 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
14458 character index 3, even in unified mode. Used for
14459 legacy instructions where suffix and infix forms
14460 may be ambiguous. */
14461 OT_csuf_or_in3
, /* Instruction takes either a conditional
14462 suffix or an infix at character index 3. */
14463 OT_odd_infix_unc
, /* This is the unconditional variant of an
14464 instruction that takes a conditional infix
14465 at an unusual position. In unified mode,
14466 this variant will accept a suffix. */
14467 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
14468 are the conditional variants of instructions that
14469 take conditional infixes in unusual positions.
14470 The infix appears at character index
14471 (tag - OT_odd_infix_0). These are not accepted
14472 in unified mode. */
14475 /* Subroutine of md_assemble, responsible for looking up the primary
14476 opcode from the mnemonic the user wrote. STR points to the
14477 beginning of the mnemonic.
14479 This is not simply a hash table lookup, because of conditional
14480 variants. Most instructions have conditional variants, which are
14481 expressed with a _conditional affix_ to the mnemonic. If we were
14482 to encode each conditional variant as a literal string in the opcode
14483 table, it would have approximately 20,000 entries.
14485 Most mnemonics take this affix as a suffix, and in unified syntax,
14486 'most' is upgraded to 'all'. However, in the divided syntax, some
14487 instructions take the affix as an infix, notably the s-variants of
14488 the arithmetic instructions. Of those instructions, all but six
14489 have the infix appear after the third character of the mnemonic.
14491 Accordingly, the algorithm for looking up primary opcodes given
14494 1. Look up the identifier in the opcode table.
14495 If we find a match, go to step U.
14497 2. Look up the last two characters of the identifier in the
14498 conditions table. If we find a match, look up the first N-2
14499 characters of the identifier in the opcode table. If we
14500 find a match, go to step CE.
14502 3. Look up the fourth and fifth characters of the identifier in
14503 the conditions table. If we find a match, extract those
14504 characters from the identifier, and look up the remaining
14505 characters in the opcode table. If we find a match, go
14510 U. Examine the tag field of the opcode structure, in case this is
14511 one of the six instructions with its conditional infix in an
14512 unusual place. If it is, the tag tells us where to find the
14513 infix; look it up in the conditions table and set inst.cond
14514 accordingly. Otherwise, this is an unconditional instruction.
14515 Again set inst.cond accordingly. Return the opcode structure.
14517 CE. Examine the tag field to make sure this is an instruction that
14518 should receive a conditional suffix. If it is not, fail.
14519 Otherwise, set inst.cond from the suffix we already looked up,
14520 and return the opcode structure.
14522 CM. Examine the tag field to make sure this is an instruction that
14523 should receive a conditional infix after the third character.
14524 If it is not, fail. Otherwise, undo the edits to the current
14525 line of input and proceed as for case CE. */
14527 static const struct asm_opcode
*
14528 opcode_lookup (char **str
)
14532 const struct asm_opcode
*opcode
;
14533 const struct asm_cond
*cond
;
14535 bfd_boolean neon_supported
;
14537 neon_supported
= ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
);
14539 /* Scan up to the end of the mnemonic, which must end in white space,
14540 '.' (in unified mode, or for Neon instructions), or end of string. */
14541 for (base
= end
= *str
; *end
!= '\0'; end
++)
14542 if (*end
== ' ' || ((unified_syntax
|| neon_supported
) && *end
== '.'))
14548 /* Handle a possible width suffix and/or Neon type suffix. */
14553 /* The .w and .n suffixes are only valid if the unified syntax is in
14555 if (unified_syntax
&& end
[1] == 'w')
14557 else if (unified_syntax
&& end
[1] == 'n')
14562 inst
.vectype
.elems
= 0;
14564 *str
= end
+ offset
;
14566 if (end
[offset
] == '.')
14568 /* See if we have a Neon type suffix (possible in either unified or
14569 non-unified ARM syntax mode). */
14570 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
14573 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
14579 /* Look for unaffixed or special-case affixed mnemonic. */
14580 opcode
= hash_find_n (arm_ops_hsh
, base
, end
- base
);
14584 if (opcode
->tag
< OT_odd_infix_0
)
14586 inst
.cond
= COND_ALWAYS
;
14590 if (warn_on_deprecated
&& unified_syntax
)
14591 as_warn (_("conditional infixes are deprecated in unified syntax"));
14592 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
14593 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14596 inst
.cond
= cond
->value
;
14600 /* Cannot have a conditional suffix on a mnemonic of less than two
14602 if (end
- base
< 3)
14605 /* Look for suffixed mnemonic. */
14607 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14608 opcode
= hash_find_n (arm_ops_hsh
, base
, affix
- base
);
14609 if (opcode
&& cond
)
14612 switch (opcode
->tag
)
14614 case OT_cinfix3_legacy
:
14615 /* Ignore conditional suffixes matched on infix only mnemonics. */
14619 case OT_cinfix3_deprecated
:
14620 case OT_odd_infix_unc
:
14621 if (!unified_syntax
)
14623 /* else fall through */
14627 case OT_csuf_or_in3
:
14628 inst
.cond
= cond
->value
;
14631 case OT_unconditional
:
14632 case OT_unconditionalF
:
14635 inst
.cond
= cond
->value
;
14639 /* delayed diagnostic */
14640 inst
.error
= BAD_COND
;
14641 inst
.cond
= COND_ALWAYS
;
14650 /* Cannot have a usual-position infix on a mnemonic of less than
14651 six characters (five would be a suffix). */
14652 if (end
- base
< 6)
14655 /* Look for infixed mnemonic in the usual position. */
14657 cond
= hash_find_n (arm_cond_hsh
, affix
, 2);
14661 memcpy (save
, affix
, 2);
14662 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
14663 opcode
= hash_find_n (arm_ops_hsh
, base
, (end
- base
) - 2);
14664 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
14665 memcpy (affix
, save
, 2);
14668 && (opcode
->tag
== OT_cinfix3
14669 || opcode
->tag
== OT_cinfix3_deprecated
14670 || opcode
->tag
== OT_csuf_or_in3
14671 || opcode
->tag
== OT_cinfix3_legacy
))
14674 if (warn_on_deprecated
&& unified_syntax
14675 && (opcode
->tag
== OT_cinfix3
14676 || opcode
->tag
== OT_cinfix3_deprecated
))
14677 as_warn (_("conditional infixes are deprecated in unified syntax"));
14679 inst
.cond
= cond
->value
;
14687 md_assemble (char *str
)
14690 const struct asm_opcode
* opcode
;
14692 /* Align the previous label if needed. */
14693 if (last_label_seen
!= NULL
)
14695 symbol_set_frag (last_label_seen
, frag_now
);
14696 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
14697 S_SET_SEGMENT (last_label_seen
, now_seg
);
14700 memset (&inst
, '\0', sizeof (inst
));
14701 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
14703 opcode
= opcode_lookup (&p
);
14706 /* It wasn't an instruction, but it might be a register alias of
14707 the form alias .req reg, or a Neon .dn/.qn directive. */
14708 if (!create_register_alias (str
, p
)
14709 && !create_neon_reg_alias (str
, p
))
14710 as_bad (_("bad instruction `%s'"), str
);
14715 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
14716 as_warn (_("s suffix on comparison instruction is deprecated"));
14718 /* The value which unconditional instructions should have in place of the
14719 condition field. */
14720 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
14724 arm_feature_set variant
;
14726 variant
= cpu_variant
;
14727 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
14728 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
14729 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
14730 /* Check that this instruction is supported for this CPU. */
14731 if (!opcode
->tvariant
14732 || (thumb_mode
== 1
14733 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
14735 as_bad (_("selected processor does not support `%s'"), str
);
14738 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
14739 && opcode
->tencode
!= do_t_branch
)
14741 as_bad (_("Thumb does not support conditional execution"));
14745 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
) && !inst
.size_req
)
14747 /* Implicit require narrow instructions on Thumb-1. This avoids
14748 relaxation accidentally introducing Thumb-2 instructions. */
14749 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
14750 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
14751 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
14755 /* Check conditional suffixes. */
14756 if (current_it_mask
)
14759 cond
= current_cc
^ ((current_it_mask
>> 4) & 1) ^ 1;
14760 current_it_mask
<<= 1;
14761 current_it_mask
&= 0x1f;
14762 /* The BKPT instruction is unconditional even in an IT block. */
14764 && cond
!= inst
.cond
&& opcode
->tencode
!= do_t_bkpt
)
14766 as_bad (_("incorrect condition in IT block"));
14770 else if (inst
.cond
!= COND_ALWAYS
&& opcode
->tencode
!= do_t_branch
)
14772 as_bad (_("thumb conditional instruction not in IT block"));
14776 mapping_state (MAP_THUMB
);
14777 inst
.instruction
= opcode
->tvalue
;
14779 if (!parse_operands (p
, opcode
->operands
))
14780 opcode
->tencode ();
14782 /* Clear current_it_mask at the end of an IT block. */
14783 if (current_it_mask
== 0x10)
14784 current_it_mask
= 0;
14786 if (!(inst
.error
|| inst
.relax
))
14788 assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
14789 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
14790 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
14792 as_bad (_("cannot honor width suffix -- `%s'"), str
);
14797 /* Something has gone badly wrong if we try to relax a fixed size
14799 assert (inst
.size_req
== 0 || !inst
.relax
);
14801 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14802 *opcode
->tvariant
);
14803 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
14804 set those bits when Thumb-2 32-bit instructions are seen. ie.
14805 anything other than bl/blx and v6-M instructions.
14806 This is overly pessimistic for relaxable instructions. */
14807 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
14809 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
14810 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
14811 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
14814 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
14818 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
14819 is_bx
= (opcode
->aencode
== do_bx
);
14821 /* Check that this instruction is supported for this CPU. */
14822 if (!(is_bx
&& fix_v4bx
)
14823 && !(opcode
->avariant
&&
14824 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
14826 as_bad (_("selected processor does not support `%s'"), str
);
14831 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
14835 mapping_state (MAP_ARM
);
14836 inst
.instruction
= opcode
->avalue
;
14837 if (opcode
->tag
== OT_unconditionalF
)
14838 inst
.instruction
|= 0xF << 28;
14840 inst
.instruction
|= inst
.cond
<< 28;
14841 inst
.size
= INSN_SIZE
;
14842 if (!parse_operands (p
, opcode
->operands
))
14843 opcode
->aencode ();
14844 /* Arm mode bx is marked as both v4T and v5 because it's still required
14845 on a hypothetical non-thumb v5 core. */
14847 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
14849 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
14850 *opcode
->avariant
);
14854 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
14861 /* Various frobbings of labels and their addresses. */
14864 arm_start_line_hook (void)
14866 last_label_seen
= NULL
;
14870 arm_frob_label (symbolS
* sym
)
14872 last_label_seen
= sym
;
14874 ARM_SET_THUMB (sym
, thumb_mode
);
14876 #if defined OBJ_COFF || defined OBJ_ELF
14877 ARM_SET_INTERWORK (sym
, support_interwork
);
14880 /* Note - do not allow local symbols (.Lxxx) to be labelled
14881 as Thumb functions. This is because these labels, whilst
14882 they exist inside Thumb code, are not the entry points for
14883 possible ARM->Thumb calls. Also, these labels can be used
14884 as part of a computed goto or switch statement. eg gcc
14885 can generate code that looks like this:
14887 ldr r2, [pc, .Laaa]
14897 The first instruction loads the address of the jump table.
14898 The second instruction converts a table index into a byte offset.
14899 The third instruction gets the jump address out of the table.
14900 The fourth instruction performs the jump.
14902 If the address stored at .Laaa is that of a symbol which has the
14903 Thumb_Func bit set, then the linker will arrange for this address
14904 to have the bottom bit set, which in turn would mean that the
14905 address computation performed by the third instruction would end
14906 up with the bottom bit set. Since the ARM is capable of unaligned
14907 word loads, the instruction would then load the incorrect address
14908 out of the jump table, and chaos would ensue. */
14909 if (label_is_thumb_function_name
14910 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
14911 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
14913 /* When the address of a Thumb function is taken the bottom
14914 bit of that address should be set. This will allow
14915 interworking between Arm and Thumb functions to work
14918 THUMB_SET_FUNC (sym
, 1);
14920 label_is_thumb_function_name
= FALSE
;
14923 dwarf2_emit_label (sym
);
14927 arm_data_in_code (void)
14929 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
14931 *input_line_pointer
= '/';
14932 input_line_pointer
+= 5;
14933 *input_line_pointer
= 0;
14941 arm_canonicalize_symbol_name (char * name
)
14945 if (thumb_mode
&& (len
= strlen (name
)) > 5
14946 && streq (name
+ len
- 5, "/data"))
14947 *(name
+ len
- 5) = 0;
14952 /* Table of all register names defined by default. The user can
14953 define additional names with .req. Note that all register names
14954 should appear in both upper and lowercase variants. Some registers
14955 also have mixed-case names. */
14957 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
14958 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
14959 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
14960 #define REGSET(p,t) \
14961 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
14962 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
14963 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
14964 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
14965 #define REGSETH(p,t) \
14966 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
14967 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
14968 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
14969 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
14970 #define REGSET2(p,t) \
14971 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
14972 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
14973 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
14974 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
14976 static const struct reg_entry reg_names
[] =
14978 /* ARM integer registers. */
14979 REGSET(r
, RN
), REGSET(R
, RN
),
14981 /* ATPCS synonyms. */
14982 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
14983 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
14984 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
14986 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
14987 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
14988 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
14990 /* Well-known aliases. */
14991 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
14992 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
14994 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
14995 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
14997 /* Coprocessor numbers. */
14998 REGSET(p
, CP
), REGSET(P
, CP
),
15000 /* Coprocessor register numbers. The "cr" variants are for backward
15002 REGSET(c
, CN
), REGSET(C
, CN
),
15003 REGSET(cr
, CN
), REGSET(CR
, CN
),
15005 /* FPA registers. */
15006 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
15007 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
15009 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
15010 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
15012 /* VFP SP registers. */
15013 REGSET(s
,VFS
), REGSET(S
,VFS
),
15014 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
15016 /* VFP DP Registers. */
15017 REGSET(d
,VFD
), REGSET(D
,VFD
),
15018 /* Extra Neon DP registers. */
15019 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
15021 /* Neon QP registers. */
15022 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
15024 /* VFP control registers. */
15025 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
15026 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
15027 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
15028 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
15029 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
15030 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
15032 /* Maverick DSP coprocessor registers. */
15033 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
15034 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
15036 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
15037 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
15038 REGDEF(dspsc
,0,DSPSC
),
15040 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
15041 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
15042 REGDEF(DSPSC
,0,DSPSC
),
15044 /* iWMMXt data registers - p0, c0-15. */
15045 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
15047 /* iWMMXt control registers - p1, c0-3. */
15048 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
15049 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
15050 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
15051 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
15053 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
15054 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
15055 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
15056 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
15057 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
15059 /* XScale accumulator registers. */
15060 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
15066 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
15067 within psr_required_here. */
15068 static const struct asm_psr psrs
[] =
15070 /* Backward compatibility notation. Note that "all" is no longer
15071 truly all possible PSR bits. */
15072 {"all", PSR_c
| PSR_f
},
15076 /* Individual flags. */
15081 /* Combinations of flags. */
15082 {"fs", PSR_f
| PSR_s
},
15083 {"fx", PSR_f
| PSR_x
},
15084 {"fc", PSR_f
| PSR_c
},
15085 {"sf", PSR_s
| PSR_f
},
15086 {"sx", PSR_s
| PSR_x
},
15087 {"sc", PSR_s
| PSR_c
},
15088 {"xf", PSR_x
| PSR_f
},
15089 {"xs", PSR_x
| PSR_s
},
15090 {"xc", PSR_x
| PSR_c
},
15091 {"cf", PSR_c
| PSR_f
},
15092 {"cs", PSR_c
| PSR_s
},
15093 {"cx", PSR_c
| PSR_x
},
15094 {"fsx", PSR_f
| PSR_s
| PSR_x
},
15095 {"fsc", PSR_f
| PSR_s
| PSR_c
},
15096 {"fxs", PSR_f
| PSR_x
| PSR_s
},
15097 {"fxc", PSR_f
| PSR_x
| PSR_c
},
15098 {"fcs", PSR_f
| PSR_c
| PSR_s
},
15099 {"fcx", PSR_f
| PSR_c
| PSR_x
},
15100 {"sfx", PSR_s
| PSR_f
| PSR_x
},
15101 {"sfc", PSR_s
| PSR_f
| PSR_c
},
15102 {"sxf", PSR_s
| PSR_x
| PSR_f
},
15103 {"sxc", PSR_s
| PSR_x
| PSR_c
},
15104 {"scf", PSR_s
| PSR_c
| PSR_f
},
15105 {"scx", PSR_s
| PSR_c
| PSR_x
},
15106 {"xfs", PSR_x
| PSR_f
| PSR_s
},
15107 {"xfc", PSR_x
| PSR_f
| PSR_c
},
15108 {"xsf", PSR_x
| PSR_s
| PSR_f
},
15109 {"xsc", PSR_x
| PSR_s
| PSR_c
},
15110 {"xcf", PSR_x
| PSR_c
| PSR_f
},
15111 {"xcs", PSR_x
| PSR_c
| PSR_s
},
15112 {"cfs", PSR_c
| PSR_f
| PSR_s
},
15113 {"cfx", PSR_c
| PSR_f
| PSR_x
},
15114 {"csf", PSR_c
| PSR_s
| PSR_f
},
15115 {"csx", PSR_c
| PSR_s
| PSR_x
},
15116 {"cxf", PSR_c
| PSR_x
| PSR_f
},
15117 {"cxs", PSR_c
| PSR_x
| PSR_s
},
15118 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
15119 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
15120 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
15121 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
15122 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
15123 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
15124 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
15125 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
15126 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
15127 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
15128 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
15129 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
15130 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
15131 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
15132 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
15133 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
15134 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
15135 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
15136 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
15137 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
15138 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
15139 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
15140 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
15141 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
15144 /* Table of V7M psr names. */
15145 static const struct asm_psr v7m_psrs
[] =
15147 {"apsr", 0 }, {"APSR", 0 },
15148 {"iapsr", 1 }, {"IAPSR", 1 },
15149 {"eapsr", 2 }, {"EAPSR", 2 },
15150 {"psr", 3 }, {"PSR", 3 },
15151 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
15152 {"ipsr", 5 }, {"IPSR", 5 },
15153 {"epsr", 6 }, {"EPSR", 6 },
15154 {"iepsr", 7 }, {"IEPSR", 7 },
15155 {"msp", 8 }, {"MSP", 8 },
15156 {"psp", 9 }, {"PSP", 9 },
15157 {"primask", 16}, {"PRIMASK", 16},
15158 {"basepri", 17}, {"BASEPRI", 17},
15159 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
15160 {"faultmask", 19}, {"FAULTMASK", 19},
15161 {"control", 20}, {"CONTROL", 20}
15164 /* Table of all shift-in-operand names. */
15165 static const struct asm_shift_name shift_names
[] =
15167 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
15168 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
15169 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
15170 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
15171 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
15172 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
15175 /* Table of all explicit relocation names. */
15177 static struct reloc_entry reloc_names
[] =
15179 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
15180 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
15181 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
15182 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
15183 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
15184 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
15185 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
15186 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
15187 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
15188 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
15189 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
}
15193 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
15194 static const struct asm_cond conds
[] =
15198 {"cs", 0x2}, {"hs", 0x2},
15199 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
15213 static struct asm_barrier_opt barrier_opt_names
[] =
15221 /* Table of ARM-format instructions. */
15223 /* Macros for gluing together operand strings. N.B. In all cases
15224 other than OPS0, the trailing OP_stop comes from default
15225 zero-initialization of the unspecified elements of the array. */
15226 #define OPS0() { OP_stop, }
15227 #define OPS1(a) { OP_##a, }
15228 #define OPS2(a,b) { OP_##a,OP_##b, }
15229 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
15230 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
15231 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
15232 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
15234 /* These macros abstract out the exact format of the mnemonic table and
15235 save some repeated characters. */
15237 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
15238 #define TxCE(mnem, op, top, nops, ops, ae, te) \
15239 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
15240 THUMB_VARIANT, do_##ae, do_##te }
15242 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
15243 a T_MNEM_xyz enumerator. */
15244 #define TCE(mnem, aop, top, nops, ops, ae, te) \
15245 TxCE(mnem, aop, 0x##top, nops, ops, ae, te)
15246 #define tCE(mnem, aop, top, nops, ops, ae, te) \
15247 TxCE(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15249 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
15250 infix after the third character. */
15251 #define TxC3(mnem, op, top, nops, ops, ae, te) \
15252 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
15253 THUMB_VARIANT, do_##ae, do_##te }
15254 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
15255 { #mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
15256 THUMB_VARIANT, do_##ae, do_##te }
15257 #define TC3(mnem, aop, top, nops, ops, ae, te) \
15258 TxC3(mnem, aop, 0x##top, nops, ops, ae, te)
15259 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
15260 TxC3w(mnem, aop, 0x##top, nops, ops, ae, te)
15261 #define tC3(mnem, aop, top, nops, ops, ae, te) \
15262 TxC3(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15263 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
15264 TxC3w(mnem, aop, T_MNEM_##top, nops, ops, ae, te)
15266 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
15267 appear in the condition table. */
15268 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
15269 { #m1 #m2 #m3, OPS##nops ops, sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
15270 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
15272 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
15273 TxCM_(m1, , m2, op, top, nops, ops, ae, te), \
15274 TxCM_(m1, eq, m2, op, top, nops, ops, ae, te), \
15275 TxCM_(m1, ne, m2, op, top, nops, ops, ae, te), \
15276 TxCM_(m1, cs, m2, op, top, nops, ops, ae, te), \
15277 TxCM_(m1, hs, m2, op, top, nops, ops, ae, te), \
15278 TxCM_(m1, cc, m2, op, top, nops, ops, ae, te), \
15279 TxCM_(m1, ul, m2, op, top, nops, ops, ae, te), \
15280 TxCM_(m1, lo, m2, op, top, nops, ops, ae, te), \
15281 TxCM_(m1, mi, m2, op, top, nops, ops, ae, te), \
15282 TxCM_(m1, pl, m2, op, top, nops, ops, ae, te), \
15283 TxCM_(m1, vs, m2, op, top, nops, ops, ae, te), \
15284 TxCM_(m1, vc, m2, op, top, nops, ops, ae, te), \
15285 TxCM_(m1, hi, m2, op, top, nops, ops, ae, te), \
15286 TxCM_(m1, ls, m2, op, top, nops, ops, ae, te), \
15287 TxCM_(m1, ge, m2, op, top, nops, ops, ae, te), \
15288 TxCM_(m1, lt, m2, op, top, nops, ops, ae, te), \
15289 TxCM_(m1, gt, m2, op, top, nops, ops, ae, te), \
15290 TxCM_(m1, le, m2, op, top, nops, ops, ae, te), \
15291 TxCM_(m1, al, m2, op, top, nops, ops, ae, te)
15293 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
15294 TxCM(m1,m2, aop, 0x##top, nops, ops, ae, te)
15295 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
15296 TxCM(m1,m2, aop, T_MNEM_##top, nops, ops, ae, te)
15298 /* Mnemonic that cannot be conditionalized. The ARM condition-code
15299 field is still 0xE. Many of the Thumb variants can be executed
15300 conditionally, so this is checked separately. */
15301 #define TUE(mnem, op, top, nops, ops, ae, te) \
15302 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
15303 THUMB_VARIANT, do_##ae, do_##te }
15305 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
15306 condition code field. */
15307 #define TUF(mnem, op, top, nops, ops, ae, te) \
15308 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
15309 THUMB_VARIANT, do_##ae, do_##te }
15311 /* ARM-only variants of all the above. */
15312 #define CE(mnem, op, nops, ops, ae) \
15313 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15315 #define C3(mnem, op, nops, ops, ae) \
15316 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15318 /* Legacy mnemonics that always have conditional infix after the third
15320 #define CL(mnem, op, nops, ops, ae) \
15321 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
15322 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15324 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
15325 #define cCE(mnem, op, nops, ops, ae) \
15326 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15328 /* Legacy coprocessor instructions where conditional infix and conditional
15329 suffix are ambiguous. For consistency this includes all FPA instructions,
15330 not just the potentially ambiguous ones. */
15331 #define cCL(mnem, op, nops, ops, ae) \
15332 { #mnem, OPS##nops ops, OT_cinfix3_legacy, \
15333 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15335 /* Coprocessor, takes either a suffix or a position-3 infix
15336 (for an FPA corner case). */
15337 #define C3E(mnem, op, nops, ops, ae) \
15338 { #mnem, OPS##nops ops, OT_csuf_or_in3, \
15339 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
15341 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
15342 { #m1 #m2 #m3, OPS##nops ops, \
15343 sizeof(#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof(#m1) - 1, \
15344 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
15346 #define CM(m1, m2, op, nops, ops, ae) \
15347 xCM_(m1, , m2, op, nops, ops, ae), \
15348 xCM_(m1, eq, m2, op, nops, ops, ae), \
15349 xCM_(m1, ne, m2, op, nops, ops, ae), \
15350 xCM_(m1, cs, m2, op, nops, ops, ae), \
15351 xCM_(m1, hs, m2, op, nops, ops, ae), \
15352 xCM_(m1, cc, m2, op, nops, ops, ae), \
15353 xCM_(m1, ul, m2, op, nops, ops, ae), \
15354 xCM_(m1, lo, m2, op, nops, ops, ae), \
15355 xCM_(m1, mi, m2, op, nops, ops, ae), \
15356 xCM_(m1, pl, m2, op, nops, ops, ae), \
15357 xCM_(m1, vs, m2, op, nops, ops, ae), \
15358 xCM_(m1, vc, m2, op, nops, ops, ae), \
15359 xCM_(m1, hi, m2, op, nops, ops, ae), \
15360 xCM_(m1, ls, m2, op, nops, ops, ae), \
15361 xCM_(m1, ge, m2, op, nops, ops, ae), \
15362 xCM_(m1, lt, m2, op, nops, ops, ae), \
15363 xCM_(m1, gt, m2, op, nops, ops, ae), \
15364 xCM_(m1, le, m2, op, nops, ops, ae), \
15365 xCM_(m1, al, m2, op, nops, ops, ae)
15367 #define UE(mnem, op, nops, ops, ae) \
15368 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
15370 #define UF(mnem, op, nops, ops, ae) \
15371 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
15373 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
15374 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
15375 use the same encoding function for each. */
15376 #define NUF(mnem, op, nops, ops, enc) \
15377 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
15378 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15380 /* Neon data processing, version which indirects through neon_enc_tab for
15381 the various overloaded versions of opcodes. */
15382 #define nUF(mnem, op, nops, ops, enc) \
15383 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM_##op, N_MNEM_##op, \
15384 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15386 /* Neon insn with conditional suffix for the ARM version, non-overloaded
15388 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
15389 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
15390 THUMB_VARIANT, do_##enc, do_##enc }
15392 #define NCE(mnem, op, nops, ops, enc) \
15393 NCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
15395 #define NCEF(mnem, op, nops, ops, enc) \
15396 NCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
15398 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
15399 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
15400 { #mnem, OPS##nops ops, tag, N_MNEM_##op, N_MNEM_##op, \
15401 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
15403 #define nCE(mnem, op, nops, ops, enc) \
15404 nCE_tag(mnem, op, nops, ops, enc, OT_csuffix)
15406 #define nCEF(mnem, op, nops, ops, enc) \
15407 nCE_tag(mnem, op, nops, ops, enc, OT_csuffixF)
15411 /* Thumb-only, unconditional. */
15412 #define UT(mnem, op, nops, ops, te) TUE(mnem, 0, op, nops, ops, 0, te)
15414 static const struct asm_opcode insns
[] =
15416 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
15417 #define THUMB_VARIANT &arm_ext_v4t
15418 tCE(and, 0000000, and, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15419 tC3(ands
, 0100000, ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15420 tCE(eor
, 0200000, eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15421 tC3(eors
, 0300000, eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15422 tCE(sub
, 0400000, sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
15423 tC3(subs
, 0500000, subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
15424 tCE(add
, 0800000, add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15425 tC3(adds
, 0900000, adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
15426 tCE(adc
, 0a00000
, adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15427 tC3(adcs
, 0b00000, adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15428 tCE(sbc
, 0c00000
, sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15429 tC3(sbcs
, 0d00000
, sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15430 tCE(orr
, 1800000, orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15431 tC3(orrs
, 1900000, orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
15432 tCE(bic
, 1c00000
, bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15433 tC3(bics
, 1d00000
, bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
15435 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
15436 for setting PSR flag bits. They are obsolete in V6 and do not
15437 have Thumb equivalents. */
15438 tCE(tst
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15439 tC3w(tsts
, 1100000, tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15440 CL(tstp
, 110f000
, 2, (RR
, SH
), cmp
),
15441 tCE(cmp
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15442 tC3w(cmps
, 1500000, cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
15443 CL(cmpp
, 150f000
, 2, (RR
, SH
), cmp
),
15444 tCE(cmn
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15445 tC3w(cmns
, 1700000, cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15446 CL(cmnp
, 170f000
, 2, (RR
, SH
), cmp
),
15448 tCE(mov
, 1a00000
, mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15449 tC3(movs
, 1b00000
, movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
15450 tCE(mvn
, 1e00000
, mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15451 tC3(mvns
, 1f00000
, mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
15453 tCE(ldr
, 4100000, ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15454 tC3(ldrb
, 4500000, ldrb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15455 tCE(str
, 4000000, str
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15456 tC3(strb
, 4400000, strb
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
15458 tCE(stm
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15459 tC3(stmia
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15460 tC3(stmea
, 8800000, stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15461 tCE(ldm
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15462 tC3(ldmia
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15463 tC3(ldmfd
, 8900000, ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15465 TCE(swi
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15466 TCE(svc
, f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
15467 tCE(b
, a000000
, b
, 1, (EXPr
), branch
, t_branch
),
15468 TCE(bl
, b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
15471 tCE(adr
, 28f0000
, adr
, 2, (RR
, EXP
), adr
, t_adr
),
15472 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
15473 tCE(nop
, 1a00000
, nop
, 1, (oI255c
), nop
, t_nop
),
15475 /* Thumb-compatibility pseudo ops. */
15476 tCE(lsl
, 1a00000
, lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15477 tC3(lsls
, 1b00000
, lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15478 tCE(lsr
, 1a00020
, lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15479 tC3(lsrs
, 1b00020
, lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15480 tCE(asr
, 1a00040
, asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15481 tC3(asrs
, 1b00040
, asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15482 tCE(ror
, 1a00060
, ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15483 tC3(rors
, 1b00060
, rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
15484 tCE(neg
, 2600000, neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
15485 tC3(negs
, 2700000, negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
15486 tCE(push
, 92d0000
, push
, 1, (REGLST
), push_pop
, t_push_pop
),
15487 tCE(pop
, 8bd0000
, pop
, 1, (REGLST
), push_pop
, t_push_pop
),
15489 /* These may simplify to neg. */
15490 TCE(rsb
, 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15491 TC3(rsbs
, 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
15493 #undef THUMB_VARIANT
15494 #define THUMB_VARIANT &arm_ext_v6
15495 TCE(cpy
, 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
15497 /* V1 instructions with no Thumb analogue prior to V6T2. */
15498 #undef THUMB_VARIANT
15499 #define THUMB_VARIANT &arm_ext_v6t2
15500 TCE(teq
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15501 TC3w(teqs
, 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
15502 CL(teqp
, 130f000
, 2, (RR
, SH
), cmp
),
15504 TC3(ldrt
, 4300000, f8500e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15505 TC3(ldrbt
, 4700000, f8100e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15506 TC3(strt
, 4200000, f8400e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15507 TC3(strbt
, 4600000, f8000e00
, 2, (RR
, ADDR
), ldstt
, t_ldstt
),
15509 TC3(stmdb
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15510 TC3(stmfd
, 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15512 TC3(ldmdb
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15513 TC3(ldmea
, 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
15515 /* V1 instructions with no Thumb analogue at all. */
15516 CE(rsc
, 0e00000
, 3, (RR
, oRR
, SH
), arit
),
15517 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
15519 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15520 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
15521 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15522 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
15523 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15524 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
15525 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15526 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
15529 #define ARM_VARIANT &arm_ext_v2 /* ARM 2 - multiplies. */
15530 #undef THUMB_VARIANT
15531 #define THUMB_VARIANT &arm_ext_v4t
15532 tCE(mul
, 0000090, mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15533 tC3(muls
, 0100090, muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
15535 #undef THUMB_VARIANT
15536 #define THUMB_VARIANT &arm_ext_v6t2
15537 TCE(mla
, 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15538 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
15540 /* Generic coprocessor instructions. */
15541 TCE(cdp
, e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15542 TCE(ldc
, c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15543 TC3(ldcl
, c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15544 TCE(stc
, c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15545 TC3(stcl
, c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15546 TCE(mcr
, e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15547 TCE(mrc
, e100010
, ee100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15550 #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
15551 CE(swp
, 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15552 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
15555 #define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
15556 #undef THUMB_VARIANT
15557 #define THUMB_VARIANT &arm_ext_msr
15558 TCE(mrs
, 10f0000
, f3ef8000
, 2, (APSR_RR
, RVC_PSR
), mrs
, t_mrs
),
15559 TCE(msr
, 120f000
, f3808000
, 2, (RVC_PSR
, RR_EXi
), msr
, t_msr
),
15562 #define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
15563 #undef THUMB_VARIANT
15564 #define THUMB_VARIANT &arm_ext_v6t2
15565 TCE(smull
, 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15566 CM(smull
,s
, 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15567 TCE(umull
, 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15568 CM(umull
,s
, 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15569 TCE(smlal
, 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15570 CM(smlal
,s
, 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15571 TCE(umlal
, 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
15572 CM(umlal
,s
, 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
15575 #define ARM_VARIANT &arm_ext_v4 /* ARM Architecture 4. */
15576 #undef THUMB_VARIANT
15577 #define THUMB_VARIANT &arm_ext_v4t
15578 tC3(ldrh
, 01000b0
, ldrh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15579 tC3(strh
, 00000b0
, strh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15580 tC3(ldrsh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15581 tC3(ldrsb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15582 tCM(ld
,sh
, 01000f0
, ldrsh
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15583 tCM(ld
,sb
, 01000d0
, ldrsb
, 2, (RR
, ADDRGLDRS
), ldstv4
, t_ldst
),
15586 #define ARM_VARIANT &arm_ext_v4t_5
15587 /* ARM Architecture 4T. */
15588 /* Note: bx (and blx) are required on V5, even if the processor does
15589 not support Thumb. */
15590 TCE(bx
, 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
15593 #define ARM_VARIANT &arm_ext_v5 /* ARM Architecture 5T. */
15594 #undef THUMB_VARIANT
15595 #define THUMB_VARIANT &arm_ext_v5t
15596 /* Note: blx has 2 variants; the .value coded here is for
15597 BLX(2). Only this variant has conditional execution. */
15598 TCE(blx
, 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
15599 TUE(bkpt
, 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
15601 #undef THUMB_VARIANT
15602 #define THUMB_VARIANT &arm_ext_v6t2
15603 TCE(clz
, 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
15604 TUF(ldc2
, c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15605 TUF(ldc2l
, c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15606 TUF(stc2
, c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15607 TUF(stc2l
, c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
15608 TUF(cdp2
, e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
15609 TUF(mcr2
, e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15610 TUF(mrc2
, e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
15613 #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
15614 TCE(smlabb
, 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15615 TCE(smlatb
, 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15616 TCE(smlabt
, 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15617 TCE(smlatt
, 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15619 TCE(smlawb
, 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15620 TCE(smlawt
, 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
15622 TCE(smlalbb
, 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15623 TCE(smlaltb
, 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15624 TCE(smlalbt
, 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15625 TCE(smlaltt
, 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
15627 TCE(smulbb
, 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15628 TCE(smultb
, 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15629 TCE(smulbt
, 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15630 TCE(smultt
, 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15632 TCE(smulwb
, 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15633 TCE(smulwt
, 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15635 TCE(qadd
, 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15636 TCE(qdadd
, 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15637 TCE(qsub
, 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15638 TCE(qdsub
, 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd
),
15641 #define ARM_VARIANT &arm_ext_v5e /* ARM Architecture 5TE. */
15642 TUF(pld
, 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
15643 TC3(ldrd
, 00000d0
, e8500000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15644 TC3(strd
, 00000f0
, e8400000
, 3, (RRnpc
, oRRnpc
, ADDRGLDRS
), ldrd
, t_ldstd
),
15646 TCE(mcrr
, c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15647 TCE(mrrc
, c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15650 #define ARM_VARIANT &arm_ext_v5j /* ARM Architecture 5TEJ. */
15651 TCE(bxj
, 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
15654 #define ARM_VARIANT &arm_ext_v6 /* ARM V6. */
15655 #undef THUMB_VARIANT
15656 #define THUMB_VARIANT &arm_ext_v6
15657 TUF(cpsie
, 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15658 TUF(cpsid
, 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
15659 tCE(rev
, 6bf0f30
, rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15660 tCE(rev16
, 6bf0fb0
, rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15661 tCE(revsh
, 6ff0fb0
, revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
15662 tCE(sxth
, 6bf0070
, sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15663 tCE(uxth
, 6ff0070
, uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15664 tCE(sxtb
, 6af0070
, sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15665 tCE(uxtb
, 6ef0070
, uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15666 TUF(setend
, 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
15668 #undef THUMB_VARIANT
15669 #define THUMB_VARIANT &arm_ext_v6t2
15670 TCE(ldrex
, 1900f9f
, e8500f00
, 2, (RRnpc
, ADDR
), ldrex
, t_ldrex
),
15671 TCE(strex
, 1800f90
, e8400000
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, t_strex
),
15672 TUF(mcrr2
, c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15673 TUF(mrrc2
, c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
15675 TCE(ssat
, 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
15676 TCE(usat
, 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
15678 /* ARM V6 not included in V7M (eg. integer SIMD). */
15679 #undef THUMB_VARIANT
15680 #define THUMB_VARIANT &arm_ext_v6_notm
15681 TUF(cps
, 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
15682 TCE(pkhbt
, 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
15683 TCE(pkhtb
, 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
15684 TCE(qadd16
, 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15685 TCE(qadd8
, 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15686 TCE(qasx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15687 /* Old name for QASX. */
15688 TCE(qaddsubx
, 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15689 TCE(qsax
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15690 /* Old name for QSAX. */
15691 TCE(qsubaddx
, 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15692 TCE(qsub16
, 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15693 TCE(qsub8
, 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15694 TCE(sadd16
, 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15695 TCE(sadd8
, 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15696 TCE(sasx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15697 /* Old name for SASX. */
15698 TCE(saddsubx
, 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15699 TCE(shadd16
, 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15700 TCE(shadd8
, 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15701 TCE(shasx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15702 /* Old name for SHASX. */
15703 TCE(shaddsubx
, 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15704 TCE(shsax
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15705 /* Old name for SHSAX. */
15706 TCE(shsubaddx
, 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15707 TCE(shsub16
, 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15708 TCE(shsub8
, 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15709 TCE(ssax
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15710 /* Old name for SSAX. */
15711 TCE(ssubaddx
, 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15712 TCE(ssub16
, 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15713 TCE(ssub8
, 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15714 TCE(uadd16
, 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15715 TCE(uadd8
, 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15716 TCE(uasx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15717 /* Old name for UASX. */
15718 TCE(uaddsubx
, 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15719 TCE(uhadd16
, 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15720 TCE(uhadd8
, 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15721 TCE(uhasx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15722 /* Old name for UHASX. */
15723 TCE(uhaddsubx
, 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15724 TCE(uhsax
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15725 /* Old name for UHSAX. */
15726 TCE(uhsubaddx
, 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15727 TCE(uhsub16
, 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15728 TCE(uhsub8
, 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15729 TCE(uqadd16
, 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15730 TCE(uqadd8
, 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15731 TCE(uqasx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15732 /* Old name for UQASX. */
15733 TCE(uqaddsubx
, 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15734 TCE(uqsax
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15735 /* Old name for UQSAX. */
15736 TCE(uqsubaddx
, 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15737 TCE(uqsub16
, 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15738 TCE(uqsub8
, 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15739 TCE(usub16
, 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15740 TCE(usax
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15741 /* Old name for USAX. */
15742 TCE(usubaddx
, 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15743 TCE(usub8
, 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15744 TUF(rfeia
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15745 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
15746 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
15747 TUF(rfedb
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15748 TUF(rfefd
, 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
15749 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
15750 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
15751 TUF(rfeed
, 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
15752 TCE(sxtah
, 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15753 TCE(sxtab16
, 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15754 TCE(sxtab
, 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15755 TCE(sxtb16
, 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15756 TCE(uxtah
, 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15757 TCE(uxtab16
, 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15758 TCE(uxtab
, 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
15759 TCE(uxtb16
, 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
15760 TCE(sel
, 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
15761 TCE(smlad
, 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15762 TCE(smladx
, 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15763 TCE(smlald
, 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15764 TCE(smlaldx
, 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15765 TCE(smlsd
, 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15766 TCE(smlsdx
, 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15767 TCE(smlsld
, 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15768 TCE(smlsldx
, 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
15769 TCE(smmla
, 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15770 TCE(smmlar
, 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15771 TCE(smmls
, 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15772 TCE(smmlsr
, 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15773 TCE(smmul
, 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15774 TCE(smmulr
, 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15775 TCE(smuad
, 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15776 TCE(smuadx
, 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15777 TCE(smusd
, 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15778 TCE(smusdx
, 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15779 TUF(srsia
, 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
15780 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
15781 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
15782 TUF(srsdb
, 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
15783 TCE(ssat16
, 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
15784 TCE(umaal
, 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
15785 TCE(usad8
, 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
15786 TCE(usada8
, 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
15787 TCE(usat16
, 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
15790 #define ARM_VARIANT &arm_ext_v6k
15791 #undef THUMB_VARIANT
15792 #define THUMB_VARIANT &arm_ext_v6k
15793 tCE(yield
, 320f001
, yield
, 0, (), noargs
, t_hint
),
15794 tCE(wfe
, 320f002
, wfe
, 0, (), noargs
, t_hint
),
15795 tCE(wfi
, 320f003
, wfi
, 0, (), noargs
, t_hint
),
15796 tCE(sev
, 320f004
, sev
, 0, (), noargs
, t_hint
),
15798 #undef THUMB_VARIANT
15799 #define THUMB_VARIANT &arm_ext_v6_notm
15800 TCE(ldrexd
, 1b00f9f
, e8d0007f
, 3, (RRnpc
, oRRnpc
, RRnpcb
), ldrexd
, t_ldrexd
),
15801 TCE(strexd
, 1a00f90
, e8c00070
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
), strexd
, t_strexd
),
15803 #undef THUMB_VARIANT
15804 #define THUMB_VARIANT &arm_ext_v6t2
15805 TCE(ldrexb
, 1d00f9f
, e8d00f4f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15806 TCE(ldrexh
, 1f00f9f
, e8d00f5f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
15807 TCE(strexb
, 1c00f90
, e8c00f40
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15808 TCE(strexh
, 1e00f90
, e8c00f50
, 3, (RRnpc
, RRnpc
, ADDR
), strex
, rm_rd_rn
),
15809 TUF(clrex
, 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
15812 #define ARM_VARIANT &arm_ext_v6z
15813 TCE(smc
, 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
15816 #define ARM_VARIANT &arm_ext_v6t2
15817 TCE(bfc
, 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
15818 TCE(bfi
, 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
15819 TCE(sbfx
, 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15820 TCE(ubfx
, 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
15822 TCE(mls
, 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
15823 TCE(movw
, 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15824 TCE(movt
, 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
15825 TCE(rbit
, 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
15827 TC3(ldrht
, 03000b0
, f8300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15828 TC3(ldrsht
, 03000f0
, f9300e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15829 TC3(ldrsbt
, 03000d0
, f9100e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15830 TC3(strht
, 02000b0
, f8200e00
, 2, (RR
, ADDR
), ldsttv4
, t_ldstt
),
15832 UT(cbnz
, b900
, 2, (RR
, EXP
), t_cbz
),
15833 UT(cbz
, b100
, 2, (RR
, EXP
), t_cbz
),
15834 /* ARM does not really have an IT instruction, so always allow it. */
15836 #define ARM_VARIANT &arm_ext_v1
15837 TUE(it
, 0, bf08
, 1, (COND
), it
, t_it
),
15838 TUE(itt
, 0, bf0c
, 1, (COND
), it
, t_it
),
15839 TUE(ite
, 0, bf04
, 1, (COND
), it
, t_it
),
15840 TUE(ittt
, 0, bf0e
, 1, (COND
), it
, t_it
),
15841 TUE(itet
, 0, bf06
, 1, (COND
), it
, t_it
),
15842 TUE(itte
, 0, bf0a
, 1, (COND
), it
, t_it
),
15843 TUE(itee
, 0, bf02
, 1, (COND
), it
, t_it
),
15844 TUE(itttt
, 0, bf0f
, 1, (COND
), it
, t_it
),
15845 TUE(itett
, 0, bf07
, 1, (COND
), it
, t_it
),
15846 TUE(ittet
, 0, bf0b
, 1, (COND
), it
, t_it
),
15847 TUE(iteet
, 0, bf03
, 1, (COND
), it
, t_it
),
15848 TUE(ittte
, 0, bf0d
, 1, (COND
), it
, t_it
),
15849 TUE(itete
, 0, bf05
, 1, (COND
), it
, t_it
),
15850 TUE(ittee
, 0, bf09
, 1, (COND
), it
, t_it
),
15851 TUE(iteee
, 0, bf01
, 1, (COND
), it
, t_it
),
15852 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
15853 TC3(rrx
, 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
15854 TC3(rrxs
, 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
15856 /* Thumb2 only instructions. */
15858 #define ARM_VARIANT NULL
15860 TCE(addw
, 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15861 TCE(subw
, 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
15862 TCE(orn
, 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
15863 TCE(orns
, 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
15864 TCE(tbb
, 0, e8d0f000
, 1, (TB
), 0, t_tb
),
15865 TCE(tbh
, 0, e8d0f010
, 1, (TB
), 0, t_tb
),
15867 /* Thumb-2 hardware division instructions (R and M profiles only). */
15868 #undef THUMB_VARIANT
15869 #define THUMB_VARIANT &arm_ext_div
15870 TCE(sdiv
, 0, fb90f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15871 TCE(udiv
, 0, fbb0f0f0
, 3, (RR
, oRR
, RR
), 0, t_div
),
15873 /* ARM V6M/V7 instructions. */
15875 #define ARM_VARIANT &arm_ext_barrier
15876 #undef THUMB_VARIANT
15877 #define THUMB_VARIANT &arm_ext_barrier
15878 TUF(dmb
, 57ff050
, f3bf8f50
, 1, (oBARRIER
), barrier
, t_barrier
),
15879 TUF(dsb
, 57ff040
, f3bf8f40
, 1, (oBARRIER
), barrier
, t_barrier
),
15880 TUF(isb
, 57ff060
, f3bf8f60
, 1, (oBARRIER
), barrier
, t_barrier
),
15882 /* ARM V7 instructions. */
15884 #define ARM_VARIANT &arm_ext_v7
15885 #undef THUMB_VARIANT
15886 #define THUMB_VARIANT &arm_ext_v7
15887 TUF(pli
, 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
15888 TCE(dbg
, 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
15891 #define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
15892 cCE(wfs
, e200110
, 1, (RR
), rd
),
15893 cCE(rfs
, e300110
, 1, (RR
), rd
),
15894 cCE(wfc
, e400110
, 1, (RR
), rd
),
15895 cCE(rfc
, e500110
, 1, (RR
), rd
),
15897 cCL(ldfs
, c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15898 cCL(ldfd
, c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15899 cCL(ldfe
, c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15900 cCL(ldfp
, c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15902 cCL(stfs
, c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15903 cCL(stfd
, c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15904 cCL(stfe
, c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15905 cCL(stfp
, c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
15907 cCL(mvfs
, e008100
, 2, (RF
, RF_IF
), rd_rm
),
15908 cCL(mvfsp
, e008120
, 2, (RF
, RF_IF
), rd_rm
),
15909 cCL(mvfsm
, e008140
, 2, (RF
, RF_IF
), rd_rm
),
15910 cCL(mvfsz
, e008160
, 2, (RF
, RF_IF
), rd_rm
),
15911 cCL(mvfd
, e008180
, 2, (RF
, RF_IF
), rd_rm
),
15912 cCL(mvfdp
, e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
15913 cCL(mvfdm
, e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
15914 cCL(mvfdz
, e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
15915 cCL(mvfe
, e088100
, 2, (RF
, RF_IF
), rd_rm
),
15916 cCL(mvfep
, e088120
, 2, (RF
, RF_IF
), rd_rm
),
15917 cCL(mvfem
, e088140
, 2, (RF
, RF_IF
), rd_rm
),
15918 cCL(mvfez
, e088160
, 2, (RF
, RF_IF
), rd_rm
),
15920 cCL(mnfs
, e108100
, 2, (RF
, RF_IF
), rd_rm
),
15921 cCL(mnfsp
, e108120
, 2, (RF
, RF_IF
), rd_rm
),
15922 cCL(mnfsm
, e108140
, 2, (RF
, RF_IF
), rd_rm
),
15923 cCL(mnfsz
, e108160
, 2, (RF
, RF_IF
), rd_rm
),
15924 cCL(mnfd
, e108180
, 2, (RF
, RF_IF
), rd_rm
),
15925 cCL(mnfdp
, e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
15926 cCL(mnfdm
, e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
15927 cCL(mnfdz
, e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
15928 cCL(mnfe
, e188100
, 2, (RF
, RF_IF
), rd_rm
),
15929 cCL(mnfep
, e188120
, 2, (RF
, RF_IF
), rd_rm
),
15930 cCL(mnfem
, e188140
, 2, (RF
, RF_IF
), rd_rm
),
15931 cCL(mnfez
, e188160
, 2, (RF
, RF_IF
), rd_rm
),
15933 cCL(abss
, e208100
, 2, (RF
, RF_IF
), rd_rm
),
15934 cCL(abssp
, e208120
, 2, (RF
, RF_IF
), rd_rm
),
15935 cCL(abssm
, e208140
, 2, (RF
, RF_IF
), rd_rm
),
15936 cCL(abssz
, e208160
, 2, (RF
, RF_IF
), rd_rm
),
15937 cCL(absd
, e208180
, 2, (RF
, RF_IF
), rd_rm
),
15938 cCL(absdp
, e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
15939 cCL(absdm
, e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
15940 cCL(absdz
, e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
15941 cCL(abse
, e288100
, 2, (RF
, RF_IF
), rd_rm
),
15942 cCL(absep
, e288120
, 2, (RF
, RF_IF
), rd_rm
),
15943 cCL(absem
, e288140
, 2, (RF
, RF_IF
), rd_rm
),
15944 cCL(absez
, e288160
, 2, (RF
, RF_IF
), rd_rm
),
15946 cCL(rnds
, e308100
, 2, (RF
, RF_IF
), rd_rm
),
15947 cCL(rndsp
, e308120
, 2, (RF
, RF_IF
), rd_rm
),
15948 cCL(rndsm
, e308140
, 2, (RF
, RF_IF
), rd_rm
),
15949 cCL(rndsz
, e308160
, 2, (RF
, RF_IF
), rd_rm
),
15950 cCL(rndd
, e308180
, 2, (RF
, RF_IF
), rd_rm
),
15951 cCL(rnddp
, e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
15952 cCL(rnddm
, e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
15953 cCL(rnddz
, e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
15954 cCL(rnde
, e388100
, 2, (RF
, RF_IF
), rd_rm
),
15955 cCL(rndep
, e388120
, 2, (RF
, RF_IF
), rd_rm
),
15956 cCL(rndem
, e388140
, 2, (RF
, RF_IF
), rd_rm
),
15957 cCL(rndez
, e388160
, 2, (RF
, RF_IF
), rd_rm
),
15959 cCL(sqts
, e408100
, 2, (RF
, RF_IF
), rd_rm
),
15960 cCL(sqtsp
, e408120
, 2, (RF
, RF_IF
), rd_rm
),
15961 cCL(sqtsm
, e408140
, 2, (RF
, RF_IF
), rd_rm
),
15962 cCL(sqtsz
, e408160
, 2, (RF
, RF_IF
), rd_rm
),
15963 cCL(sqtd
, e408180
, 2, (RF
, RF_IF
), rd_rm
),
15964 cCL(sqtdp
, e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
15965 cCL(sqtdm
, e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
15966 cCL(sqtdz
, e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
15967 cCL(sqte
, e488100
, 2, (RF
, RF_IF
), rd_rm
),
15968 cCL(sqtep
, e488120
, 2, (RF
, RF_IF
), rd_rm
),
15969 cCL(sqtem
, e488140
, 2, (RF
, RF_IF
), rd_rm
),
15970 cCL(sqtez
, e488160
, 2, (RF
, RF_IF
), rd_rm
),
15972 cCL(logs
, e508100
, 2, (RF
, RF_IF
), rd_rm
),
15973 cCL(logsp
, e508120
, 2, (RF
, RF_IF
), rd_rm
),
15974 cCL(logsm
, e508140
, 2, (RF
, RF_IF
), rd_rm
),
15975 cCL(logsz
, e508160
, 2, (RF
, RF_IF
), rd_rm
),
15976 cCL(logd
, e508180
, 2, (RF
, RF_IF
), rd_rm
),
15977 cCL(logdp
, e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
15978 cCL(logdm
, e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
15979 cCL(logdz
, e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
15980 cCL(loge
, e588100
, 2, (RF
, RF_IF
), rd_rm
),
15981 cCL(logep
, e588120
, 2, (RF
, RF_IF
), rd_rm
),
15982 cCL(logem
, e588140
, 2, (RF
, RF_IF
), rd_rm
),
15983 cCL(logez
, e588160
, 2, (RF
, RF_IF
), rd_rm
),
15985 cCL(lgns
, e608100
, 2, (RF
, RF_IF
), rd_rm
),
15986 cCL(lgnsp
, e608120
, 2, (RF
, RF_IF
), rd_rm
),
15987 cCL(lgnsm
, e608140
, 2, (RF
, RF_IF
), rd_rm
),
15988 cCL(lgnsz
, e608160
, 2, (RF
, RF_IF
), rd_rm
),
15989 cCL(lgnd
, e608180
, 2, (RF
, RF_IF
), rd_rm
),
15990 cCL(lgndp
, e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
15991 cCL(lgndm
, e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
15992 cCL(lgndz
, e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
15993 cCL(lgne
, e688100
, 2, (RF
, RF_IF
), rd_rm
),
15994 cCL(lgnep
, e688120
, 2, (RF
, RF_IF
), rd_rm
),
15995 cCL(lgnem
, e688140
, 2, (RF
, RF_IF
), rd_rm
),
15996 cCL(lgnez
, e688160
, 2, (RF
, RF_IF
), rd_rm
),
15998 cCL(exps
, e708100
, 2, (RF
, RF_IF
), rd_rm
),
15999 cCL(expsp
, e708120
, 2, (RF
, RF_IF
), rd_rm
),
16000 cCL(expsm
, e708140
, 2, (RF
, RF_IF
), rd_rm
),
16001 cCL(expsz
, e708160
, 2, (RF
, RF_IF
), rd_rm
),
16002 cCL(expd
, e708180
, 2, (RF
, RF_IF
), rd_rm
),
16003 cCL(expdp
, e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
16004 cCL(expdm
, e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
16005 cCL(expdz
, e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
16006 cCL(expe
, e788100
, 2, (RF
, RF_IF
), rd_rm
),
16007 cCL(expep
, e788120
, 2, (RF
, RF_IF
), rd_rm
),
16008 cCL(expem
, e788140
, 2, (RF
, RF_IF
), rd_rm
),
16009 cCL(expdz
, e788160
, 2, (RF
, RF_IF
), rd_rm
),
16011 cCL(sins
, e808100
, 2, (RF
, RF_IF
), rd_rm
),
16012 cCL(sinsp
, e808120
, 2, (RF
, RF_IF
), rd_rm
),
16013 cCL(sinsm
, e808140
, 2, (RF
, RF_IF
), rd_rm
),
16014 cCL(sinsz
, e808160
, 2, (RF
, RF_IF
), rd_rm
),
16015 cCL(sind
, e808180
, 2, (RF
, RF_IF
), rd_rm
),
16016 cCL(sindp
, e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
16017 cCL(sindm
, e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
16018 cCL(sindz
, e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
16019 cCL(sine
, e888100
, 2, (RF
, RF_IF
), rd_rm
),
16020 cCL(sinep
, e888120
, 2, (RF
, RF_IF
), rd_rm
),
16021 cCL(sinem
, e888140
, 2, (RF
, RF_IF
), rd_rm
),
16022 cCL(sinez
, e888160
, 2, (RF
, RF_IF
), rd_rm
),
16024 cCL(coss
, e908100
, 2, (RF
, RF_IF
), rd_rm
),
16025 cCL(cossp
, e908120
, 2, (RF
, RF_IF
), rd_rm
),
16026 cCL(cossm
, e908140
, 2, (RF
, RF_IF
), rd_rm
),
16027 cCL(cossz
, e908160
, 2, (RF
, RF_IF
), rd_rm
),
16028 cCL(cosd
, e908180
, 2, (RF
, RF_IF
), rd_rm
),
16029 cCL(cosdp
, e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
16030 cCL(cosdm
, e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
16031 cCL(cosdz
, e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
16032 cCL(cose
, e988100
, 2, (RF
, RF_IF
), rd_rm
),
16033 cCL(cosep
, e988120
, 2, (RF
, RF_IF
), rd_rm
),
16034 cCL(cosem
, e988140
, 2, (RF
, RF_IF
), rd_rm
),
16035 cCL(cosez
, e988160
, 2, (RF
, RF_IF
), rd_rm
),
16037 cCL(tans
, ea08100
, 2, (RF
, RF_IF
), rd_rm
),
16038 cCL(tansp
, ea08120
, 2, (RF
, RF_IF
), rd_rm
),
16039 cCL(tansm
, ea08140
, 2, (RF
, RF_IF
), rd_rm
),
16040 cCL(tansz
, ea08160
, 2, (RF
, RF_IF
), rd_rm
),
16041 cCL(tand
, ea08180
, 2, (RF
, RF_IF
), rd_rm
),
16042 cCL(tandp
, ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
16043 cCL(tandm
, ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
16044 cCL(tandz
, ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
16045 cCL(tane
, ea88100
, 2, (RF
, RF_IF
), rd_rm
),
16046 cCL(tanep
, ea88120
, 2, (RF
, RF_IF
), rd_rm
),
16047 cCL(tanem
, ea88140
, 2, (RF
, RF_IF
), rd_rm
),
16048 cCL(tanez
, ea88160
, 2, (RF
, RF_IF
), rd_rm
),
16050 cCL(asns
, eb08100
, 2, (RF
, RF_IF
), rd_rm
),
16051 cCL(asnsp
, eb08120
, 2, (RF
, RF_IF
), rd_rm
),
16052 cCL(asnsm
, eb08140
, 2, (RF
, RF_IF
), rd_rm
),
16053 cCL(asnsz
, eb08160
, 2, (RF
, RF_IF
), rd_rm
),
16054 cCL(asnd
, eb08180
, 2, (RF
, RF_IF
), rd_rm
),
16055 cCL(asndp
, eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
16056 cCL(asndm
, eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
16057 cCL(asndz
, eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
16058 cCL(asne
, eb88100
, 2, (RF
, RF_IF
), rd_rm
),
16059 cCL(asnep
, eb88120
, 2, (RF
, RF_IF
), rd_rm
),
16060 cCL(asnem
, eb88140
, 2, (RF
, RF_IF
), rd_rm
),
16061 cCL(asnez
, eb88160
, 2, (RF
, RF_IF
), rd_rm
),
16063 cCL(acss
, ec08100
, 2, (RF
, RF_IF
), rd_rm
),
16064 cCL(acssp
, ec08120
, 2, (RF
, RF_IF
), rd_rm
),
16065 cCL(acssm
, ec08140
, 2, (RF
, RF_IF
), rd_rm
),
16066 cCL(acssz
, ec08160
, 2, (RF
, RF_IF
), rd_rm
),
16067 cCL(acsd
, ec08180
, 2, (RF
, RF_IF
), rd_rm
),
16068 cCL(acsdp
, ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
16069 cCL(acsdm
, ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
16070 cCL(acsdz
, ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
16071 cCL(acse
, ec88100
, 2, (RF
, RF_IF
), rd_rm
),
16072 cCL(acsep
, ec88120
, 2, (RF
, RF_IF
), rd_rm
),
16073 cCL(acsem
, ec88140
, 2, (RF
, RF_IF
), rd_rm
),
16074 cCL(acsez
, ec88160
, 2, (RF
, RF_IF
), rd_rm
),
16076 cCL(atns
, ed08100
, 2, (RF
, RF_IF
), rd_rm
),
16077 cCL(atnsp
, ed08120
, 2, (RF
, RF_IF
), rd_rm
),
16078 cCL(atnsm
, ed08140
, 2, (RF
, RF_IF
), rd_rm
),
16079 cCL(atnsz
, ed08160
, 2, (RF
, RF_IF
), rd_rm
),
16080 cCL(atnd
, ed08180
, 2, (RF
, RF_IF
), rd_rm
),
16081 cCL(atndp
, ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
16082 cCL(atndm
, ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
16083 cCL(atndz
, ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
16084 cCL(atne
, ed88100
, 2, (RF
, RF_IF
), rd_rm
),
16085 cCL(atnep
, ed88120
, 2, (RF
, RF_IF
), rd_rm
),
16086 cCL(atnem
, ed88140
, 2, (RF
, RF_IF
), rd_rm
),
16087 cCL(atnez
, ed88160
, 2, (RF
, RF_IF
), rd_rm
),
16089 cCL(urds
, ee08100
, 2, (RF
, RF_IF
), rd_rm
),
16090 cCL(urdsp
, ee08120
, 2, (RF
, RF_IF
), rd_rm
),
16091 cCL(urdsm
, ee08140
, 2, (RF
, RF_IF
), rd_rm
),
16092 cCL(urdsz
, ee08160
, 2, (RF
, RF_IF
), rd_rm
),
16093 cCL(urdd
, ee08180
, 2, (RF
, RF_IF
), rd_rm
),
16094 cCL(urddp
, ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
16095 cCL(urddm
, ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
16096 cCL(urddz
, ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
16097 cCL(urde
, ee88100
, 2, (RF
, RF_IF
), rd_rm
),
16098 cCL(urdep
, ee88120
, 2, (RF
, RF_IF
), rd_rm
),
16099 cCL(urdem
, ee88140
, 2, (RF
, RF_IF
), rd_rm
),
16100 cCL(urdez
, ee88160
, 2, (RF
, RF_IF
), rd_rm
),
16102 cCL(nrms
, ef08100
, 2, (RF
, RF_IF
), rd_rm
),
16103 cCL(nrmsp
, ef08120
, 2, (RF
, RF_IF
), rd_rm
),
16104 cCL(nrmsm
, ef08140
, 2, (RF
, RF_IF
), rd_rm
),
16105 cCL(nrmsz
, ef08160
, 2, (RF
, RF_IF
), rd_rm
),
16106 cCL(nrmd
, ef08180
, 2, (RF
, RF_IF
), rd_rm
),
16107 cCL(nrmdp
, ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
16108 cCL(nrmdm
, ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
16109 cCL(nrmdz
, ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
16110 cCL(nrme
, ef88100
, 2, (RF
, RF_IF
), rd_rm
),
16111 cCL(nrmep
, ef88120
, 2, (RF
, RF_IF
), rd_rm
),
16112 cCL(nrmem
, ef88140
, 2, (RF
, RF_IF
), rd_rm
),
16113 cCL(nrmez
, ef88160
, 2, (RF
, RF_IF
), rd_rm
),
16115 cCL(adfs
, e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16116 cCL(adfsp
, e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16117 cCL(adfsm
, e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16118 cCL(adfsz
, e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16119 cCL(adfd
, e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16120 cCL(adfdp
, e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16121 cCL(adfdm
, e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16122 cCL(adfdz
, e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16123 cCL(adfe
, e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16124 cCL(adfep
, e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16125 cCL(adfem
, e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16126 cCL(adfez
, e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16128 cCL(sufs
, e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16129 cCL(sufsp
, e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16130 cCL(sufsm
, e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16131 cCL(sufsz
, e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16132 cCL(sufd
, e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16133 cCL(sufdp
, e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16134 cCL(sufdm
, e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16135 cCL(sufdz
, e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16136 cCL(sufe
, e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16137 cCL(sufep
, e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16138 cCL(sufem
, e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16139 cCL(sufez
, e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16141 cCL(rsfs
, e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16142 cCL(rsfsp
, e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16143 cCL(rsfsm
, e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16144 cCL(rsfsz
, e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16145 cCL(rsfd
, e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16146 cCL(rsfdp
, e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16147 cCL(rsfdm
, e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16148 cCL(rsfdz
, e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16149 cCL(rsfe
, e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16150 cCL(rsfep
, e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16151 cCL(rsfem
, e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16152 cCL(rsfez
, e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16154 cCL(mufs
, e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16155 cCL(mufsp
, e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16156 cCL(mufsm
, e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16157 cCL(mufsz
, e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16158 cCL(mufd
, e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16159 cCL(mufdp
, e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16160 cCL(mufdm
, e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16161 cCL(mufdz
, e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16162 cCL(mufe
, e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16163 cCL(mufep
, e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16164 cCL(mufem
, e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16165 cCL(mufez
, e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16167 cCL(dvfs
, e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16168 cCL(dvfsp
, e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16169 cCL(dvfsm
, e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16170 cCL(dvfsz
, e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16171 cCL(dvfd
, e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16172 cCL(dvfdp
, e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16173 cCL(dvfdm
, e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16174 cCL(dvfdz
, e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16175 cCL(dvfe
, e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16176 cCL(dvfep
, e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16177 cCL(dvfem
, e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16178 cCL(dvfez
, e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16180 cCL(rdfs
, e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16181 cCL(rdfsp
, e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16182 cCL(rdfsm
, e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16183 cCL(rdfsz
, e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16184 cCL(rdfd
, e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16185 cCL(rdfdp
, e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16186 cCL(rdfdm
, e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16187 cCL(rdfdz
, e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16188 cCL(rdfe
, e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16189 cCL(rdfep
, e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16190 cCL(rdfem
, e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16191 cCL(rdfez
, e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16193 cCL(pows
, e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16194 cCL(powsp
, e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16195 cCL(powsm
, e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16196 cCL(powsz
, e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16197 cCL(powd
, e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16198 cCL(powdp
, e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16199 cCL(powdm
, e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16200 cCL(powdz
, e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16201 cCL(powe
, e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16202 cCL(powep
, e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16203 cCL(powem
, e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16204 cCL(powez
, e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16206 cCL(rpws
, e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16207 cCL(rpwsp
, e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16208 cCL(rpwsm
, e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16209 cCL(rpwsz
, e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16210 cCL(rpwd
, e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16211 cCL(rpwdp
, e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16212 cCL(rpwdm
, e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16213 cCL(rpwdz
, e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16214 cCL(rpwe
, e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16215 cCL(rpwep
, e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16216 cCL(rpwem
, e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16217 cCL(rpwez
, e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16219 cCL(rmfs
, e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16220 cCL(rmfsp
, e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16221 cCL(rmfsm
, e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16222 cCL(rmfsz
, e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16223 cCL(rmfd
, e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16224 cCL(rmfdp
, e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16225 cCL(rmfdm
, e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16226 cCL(rmfdz
, e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16227 cCL(rmfe
, e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16228 cCL(rmfep
, e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16229 cCL(rmfem
, e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16230 cCL(rmfez
, e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16232 cCL(fmls
, e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16233 cCL(fmlsp
, e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16234 cCL(fmlsm
, e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16235 cCL(fmlsz
, e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16236 cCL(fmld
, e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16237 cCL(fmldp
, e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16238 cCL(fmldm
, e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16239 cCL(fmldz
, e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16240 cCL(fmle
, e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16241 cCL(fmlep
, e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16242 cCL(fmlem
, e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16243 cCL(fmlez
, e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16245 cCL(fdvs
, ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16246 cCL(fdvsp
, ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16247 cCL(fdvsm
, ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16248 cCL(fdvsz
, ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16249 cCL(fdvd
, ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16250 cCL(fdvdp
, ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16251 cCL(fdvdm
, ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16252 cCL(fdvdz
, ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16253 cCL(fdve
, ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16254 cCL(fdvep
, ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16255 cCL(fdvem
, ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16256 cCL(fdvez
, ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16258 cCL(frds
, eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16259 cCL(frdsp
, eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16260 cCL(frdsm
, eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16261 cCL(frdsz
, eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16262 cCL(frdd
, eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16263 cCL(frddp
, eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16264 cCL(frddm
, eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16265 cCL(frddz
, eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16266 cCL(frde
, eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16267 cCL(frdep
, eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16268 cCL(frdem
, eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16269 cCL(frdez
, eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16271 cCL(pols
, ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16272 cCL(polsp
, ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16273 cCL(polsm
, ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16274 cCL(polsz
, ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16275 cCL(pold
, ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16276 cCL(poldp
, ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16277 cCL(poldm
, ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16278 cCL(poldz
, ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16279 cCL(pole
, ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16280 cCL(polep
, ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16281 cCL(polem
, ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16282 cCL(polez
, ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
16284 cCE(cmf
, e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16285 C3E(cmfe
, ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16286 cCE(cnf
, eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16287 C3E(cnfe
, ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
16289 cCL(flts
, e000110
, 2, (RF
, RR
), rn_rd
),
16290 cCL(fltsp
, e000130
, 2, (RF
, RR
), rn_rd
),
16291 cCL(fltsm
, e000150
, 2, (RF
, RR
), rn_rd
),
16292 cCL(fltsz
, e000170
, 2, (RF
, RR
), rn_rd
),
16293 cCL(fltd
, e000190
, 2, (RF
, RR
), rn_rd
),
16294 cCL(fltdp
, e0001b0
, 2, (RF
, RR
), rn_rd
),
16295 cCL(fltdm
, e0001d0
, 2, (RF
, RR
), rn_rd
),
16296 cCL(fltdz
, e0001f0
, 2, (RF
, RR
), rn_rd
),
16297 cCL(flte
, e080110
, 2, (RF
, RR
), rn_rd
),
16298 cCL(fltep
, e080130
, 2, (RF
, RR
), rn_rd
),
16299 cCL(fltem
, e080150
, 2, (RF
, RR
), rn_rd
),
16300 cCL(fltez
, e080170
, 2, (RF
, RR
), rn_rd
),
16302 /* The implementation of the FIX instruction is broken on some
16303 assemblers, in that it accepts a precision specifier as well as a
16304 rounding specifier, despite the fact that this is meaningless.
16305 To be more compatible, we accept it as well, though of course it
16306 does not set any bits. */
16307 cCE(fix
, e100110
, 2, (RR
, RF
), rd_rm
),
16308 cCL(fixp
, e100130
, 2, (RR
, RF
), rd_rm
),
16309 cCL(fixm
, e100150
, 2, (RR
, RF
), rd_rm
),
16310 cCL(fixz
, e100170
, 2, (RR
, RF
), rd_rm
),
16311 cCL(fixsp
, e100130
, 2, (RR
, RF
), rd_rm
),
16312 cCL(fixsm
, e100150
, 2, (RR
, RF
), rd_rm
),
16313 cCL(fixsz
, e100170
, 2, (RR
, RF
), rd_rm
),
16314 cCL(fixdp
, e100130
, 2, (RR
, RF
), rd_rm
),
16315 cCL(fixdm
, e100150
, 2, (RR
, RF
), rd_rm
),
16316 cCL(fixdz
, e100170
, 2, (RR
, RF
), rd_rm
),
16317 cCL(fixep
, e100130
, 2, (RR
, RF
), rd_rm
),
16318 cCL(fixem
, e100150
, 2, (RR
, RF
), rd_rm
),
16319 cCL(fixez
, e100170
, 2, (RR
, RF
), rd_rm
),
16321 /* Instructions that were new with the real FPA, call them V2. */
16323 #define ARM_VARIANT &fpu_fpa_ext_v2
16324 cCE(lfm
, c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16325 cCL(lfmfd
, c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16326 cCL(lfmea
, d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16327 cCE(sfm
, c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16328 cCL(sfmfd
, d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16329 cCL(sfmea
, c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
16332 #define ARM_VARIANT &fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
16333 /* Moves and type conversions. */
16334 cCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16335 cCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
16336 cCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
16337 cCE(fmstat
, ef1fa10
, 0, (), noargs
),
16338 cCE(fsitos
, eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16339 cCE(fuitos
, eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16340 cCE(ftosis
, ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16341 cCE(ftosizs
, ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16342 cCE(ftouis
, ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16343 cCE(ftouizs
, ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16344 cCE(fmrx
, ef00a10
, 2, (RR
, RVC
), rd_rn
),
16345 cCE(fmxr
, ee00a10
, 2, (RVC
, RR
), rn_rd
),
16347 /* Memory operations. */
16348 cCE(flds
, d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
16349 cCE(fsts
, d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
16350 cCE(fldmias
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16351 cCE(fldmfds
, c900a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16352 cCE(fldmdbs
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16353 cCE(fldmeas
, d300a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16354 cCE(fldmiax
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16355 cCE(fldmfdx
, c900b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16356 cCE(fldmdbx
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16357 cCE(fldmeax
, d300b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16358 cCE(fstmias
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16359 cCE(fstmeas
, c800a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmia
),
16360 cCE(fstmdbs
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16361 cCE(fstmfds
, d200a00
, 2, (RRw
, VRSLST
), vfp_sp_ldstmdb
),
16362 cCE(fstmiax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16363 cCE(fstmeax
, c800b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmia
),
16364 cCE(fstmdbx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16365 cCE(fstmfdx
, d200b00
, 2, (RRw
, VRDLST
), vfp_xp_ldstmdb
),
16367 /* Monadic operations. */
16368 cCE(fabss
, eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16369 cCE(fnegs
, eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16370 cCE(fsqrts
, eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16372 /* Dyadic operations. */
16373 cCE(fadds
, e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16374 cCE(fsubs
, e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16375 cCE(fmuls
, e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16376 cCE(fdivs
, e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16377 cCE(fmacs
, e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16378 cCE(fmscs
, e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16379 cCE(fnmuls
, e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16380 cCE(fnmacs
, e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16381 cCE(fnmscs
, e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
16384 cCE(fcmps
, eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16385 cCE(fcmpzs
, eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
16386 cCE(fcmpes
, eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
16387 cCE(fcmpezs
, eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
16390 #define ARM_VARIANT &fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
16391 /* Moves and type conversions. */
16392 cCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16393 cCE(fcvtds
, eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16394 cCE(fcvtsd
, eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16395 cCE(fmdhr
, e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
16396 cCE(fmdlr
, e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
16397 cCE(fmrdh
, e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
16398 cCE(fmrdl
, e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
16399 cCE(fsitod
, eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16400 cCE(fuitod
, eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
16401 cCE(ftosid
, ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16402 cCE(ftosizd
, ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16403 cCE(ftouid
, ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16404 cCE(ftouizd
, ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
16406 /* Memory operations. */
16407 cCE(fldd
, d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
16408 cCE(fstd
, d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
16409 cCE(fldmiad
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16410 cCE(fldmfdd
, c900b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16411 cCE(fldmdbd
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16412 cCE(fldmead
, d300b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16413 cCE(fstmiad
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16414 cCE(fstmead
, c800b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmia
),
16415 cCE(fstmdbd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16416 cCE(fstmfdd
, d200b00
, 2, (RRw
, VRDLST
), vfp_dp_ldstmdb
),
16418 /* Monadic operations. */
16419 cCE(fabsd
, eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16420 cCE(fnegd
, eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16421 cCE(fsqrtd
, eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16423 /* Dyadic operations. */
16424 cCE(faddd
, e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16425 cCE(fsubd
, e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16426 cCE(fmuld
, e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16427 cCE(fdivd
, e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16428 cCE(fmacd
, e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16429 cCE(fmscd
, e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16430 cCE(fnmuld
, e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16431 cCE(fnmacd
, e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16432 cCE(fnmscd
, e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
16435 cCE(fcmpd
, eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16436 cCE(fcmpzd
, eb50b40
, 1, (RVD
), vfp_dp_rd
),
16437 cCE(fcmped
, eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
16438 cCE(fcmpezd
, eb50bc0
, 1, (RVD
), vfp_dp_rd
),
16441 #define ARM_VARIANT &fpu_vfp_ext_v2
16442 cCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
16443 cCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
16444 cCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
16445 cCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
16447 /* Instructions which may belong to either the Neon or VFP instruction sets.
16448 Individual encoder functions perform additional architecture checks. */
16450 #define ARM_VARIANT &fpu_vfp_ext_v1xd
16451 #undef THUMB_VARIANT
16452 #define THUMB_VARIANT &fpu_vfp_ext_v1xd
16453 /* These mnemonics are unique to VFP. */
16454 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
16455 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
16456 nCE(vnmul
, vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16457 nCE(vnmla
, vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16458 nCE(vnmls
, vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
16459 nCE(vcmp
, vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16460 nCE(vcmpe
, vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
16461 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
16462 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
16463 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
16465 /* Mnemonics shared by Neon and VFP. */
16466 nCEF(vmul
, vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
16467 nCEF(vmla
, vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16468 nCEF(vmls
, vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
16470 nCEF(vadd
, vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16471 nCEF(vsub
, vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
16473 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16474 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
16476 NCE(vldm
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16477 NCE(vldmia
, c900b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16478 NCE(vldmdb
, d100b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16479 NCE(vstm
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16480 NCE(vstmia
, c800b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16481 NCE(vstmdb
, d000b00
, 2, (RRw
, VRSDLST
), neon_ldm_stm
),
16482 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16483 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
16485 nCEF(vcvt
, vcvt
, 3, (RNSDQ
, RNSDQ
, oI32b
), neon_cvt
),
16486 nCEF(vcvtb
, vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
16487 nCEF(vcvtt
, vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
16490 /* NOTE: All VMOV encoding is special-cased! */
16491 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
16492 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
16494 #undef THUMB_VARIANT
16495 #define THUMB_VARIANT &fpu_neon_ext_v1
16497 #define ARM_VARIANT &fpu_neon_ext_v1
16498 /* Data processing with three registers of the same length. */
16499 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
16500 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
16501 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
16502 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16503 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16504 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16505 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16506 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
16507 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
16508 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
16509 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16510 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16511 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
16512 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
16513 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16514 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16515 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
16516 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
16517 /* If not immediate, fall back to neon_dyadic_i64_su.
16518 shl_imm should accept I8 I16 I32 I64,
16519 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
16520 nUF(vshl
, vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
16521 nUF(vshlq
, vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
16522 nUF(vqshl
, vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
16523 nUF(vqshlq
, vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
16524 /* Logic ops, types optional & ignored. */
16525 nUF(vand
, vand
, 2, (RNDQ
, NILO
), neon_logic
),
16526 nUF(vandq
, vand
, 2, (RNQ
, NILO
), neon_logic
),
16527 nUF(vbic
, vbic
, 2, (RNDQ
, NILO
), neon_logic
),
16528 nUF(vbicq
, vbic
, 2, (RNQ
, NILO
), neon_logic
),
16529 nUF(vorr
, vorr
, 2, (RNDQ
, NILO
), neon_logic
),
16530 nUF(vorrq
, vorr
, 2, (RNQ
, NILO
), neon_logic
),
16531 nUF(vorn
, vorn
, 2, (RNDQ
, NILO
), neon_logic
),
16532 nUF(vornq
, vorn
, 2, (RNQ
, NILO
), neon_logic
),
16533 nUF(veor
, veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
16534 nUF(veorq
, veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
16535 /* Bitfield ops, untyped. */
16536 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16537 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16538 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16539 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16540 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
16541 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
16542 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
16543 nUF(vabd
, vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16544 nUF(vabdq
, vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16545 nUF(vmax
, vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16546 nUF(vmaxq
, vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16547 nUF(vmin
, vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
16548 nUF(vminq
, vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
16549 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
16550 back to neon_dyadic_if_su. */
16551 nUF(vcge
, vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16552 nUF(vcgeq
, vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16553 nUF(vcgt
, vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
16554 nUF(vcgtq
, vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
16555 nUF(vclt
, vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16556 nUF(vcltq
, vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16557 nUF(vcle
, vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
16558 nUF(vcleq
, vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
16559 /* Comparison. Type I8 I16 I32 F32. */
16560 nUF(vceq
, vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
16561 nUF(vceqq
, vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
16562 /* As above, D registers only. */
16563 nUF(vpmax
, vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16564 nUF(vpmin
, vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
16565 /* Int and float variants, signedness unimportant. */
16566 nUF(vmlaq
, vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16567 nUF(vmlsq
, vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
16568 nUF(vpadd
, vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
16569 /* Add/sub take types I8 I16 I32 I64 F32. */
16570 nUF(vaddq
, vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16571 nUF(vsubq
, vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
16572 /* vtst takes sizes 8, 16, 32. */
16573 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
16574 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
16575 /* VMUL takes I8 I16 I32 F32 P8. */
16576 nUF(vmulq
, vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
16577 /* VQD{R}MULH takes S16 S32. */
16578 nUF(vqdmulh
, vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16579 nUF(vqdmulhq
, vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16580 nUF(vqrdmulh
, vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
16581 nUF(vqrdmulhq
, vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
16582 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16583 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16584 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
16585 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
16586 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16587 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16588 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
16589 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
16590 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16591 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16592 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
16593 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
16595 /* Two address, int/float. Types S8 S16 S32 F32. */
16596 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16597 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
16599 /* Data processing with two registers and a shift amount. */
16600 /* Right shifts, and variants with rounding.
16601 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
16602 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16603 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16604 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
16605 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
16606 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16607 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16608 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
16609 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
16610 /* Shift and insert. Sizes accepted 8 16 32 64. */
16611 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
16612 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
16613 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
16614 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
16615 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
16616 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
16617 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
16618 /* Right shift immediate, saturating & narrowing, with rounding variants.
16619 Types accepted S16 S32 S64 U16 U32 U64. */
16620 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16621 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
16622 /* As above, unsigned. Types accepted S16 S32 S64. */
16623 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16624 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
16625 /* Right shift narrowing. Types accepted I16 I32 I64. */
16626 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16627 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
16628 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
16629 nUF(vshll
, vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
16630 /* CVT with optional immediate for fixed-point variant. */
16631 nUF(vcvtq
, vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
16633 nUF(vmvn
, vmvn
, 2, (RNDQ
, RNDQ_IMVNb
), neon_mvn
),
16634 nUF(vmvnq
, vmvn
, 2, (RNQ
, RNDQ_IMVNb
), neon_mvn
),
16636 /* Data processing, three registers of different lengths. */
16637 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
16638 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
16639 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16640 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16641 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
16642 /* If not scalar, fall back to neon_dyadic_long.
16643 Vector types as above, scalar types S16 S32 U16 U32. */
16644 nUF(vmlal
, vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16645 nUF(vmlsl
, vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
16646 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
16647 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16648 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
16649 /* Dyadic, narrowing insns. Types I16 I32 I64. */
16650 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16651 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16652 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16653 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
16654 /* Saturating doubling multiplies. Types S16 S32. */
16655 nUF(vqdmlal
, vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16656 nUF(vqdmlsl
, vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16657 nUF(vqdmull
, vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
16658 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
16659 S16 S32 U16 U32. */
16660 nUF(vmull
, vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
16662 /* Extract. Size 8. */
16663 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
16664 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
16666 /* Two registers, miscellaneous. */
16667 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
16668 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
16669 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
16670 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
16671 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
16672 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
16673 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
16674 /* Vector replicate. Sizes 8 16 32. */
16675 nCE(vdup
, vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
16676 nCE(vdupq
, vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
16677 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
16678 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
16679 /* VMOVN. Types I16 I32 I64. */
16680 nUF(vmovn
, vmovn
, 2, (RND
, RNQ
), neon_movn
),
16681 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
16682 nUF(vqmovn
, vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
16683 /* VQMOVUN. Types S16 S32 S64. */
16684 nUF(vqmovun
, vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
16685 /* VZIP / VUZP. Sizes 8 16 32. */
16686 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16687 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16688 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
16689 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
16690 /* VQABS / VQNEG. Types S8 S16 S32. */
16691 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16692 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16693 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
16694 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
16695 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
16696 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16697 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
16698 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
16699 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
16700 /* Reciprocal estimates. Types U32 F32. */
16701 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16702 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
16703 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
16704 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
16705 /* VCLS. Types S8 S16 S32. */
16706 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
16707 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
16708 /* VCLZ. Types I8 I16 I32. */
16709 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
16710 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
16711 /* VCNT. Size 8. */
16712 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
16713 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
16714 /* Two address, untyped. */
16715 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
16716 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
16717 /* VTRN. Sizes 8 16 32. */
16718 nUF(vtrn
, vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
16719 nUF(vtrnq
, vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
16721 /* Table lookup. Size 8. */
16722 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16723 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
16725 #undef THUMB_VARIANT
16726 #define THUMB_VARIANT &fpu_vfp_v3_or_neon_ext
16728 #define ARM_VARIANT &fpu_vfp_v3_or_neon_ext
16729 /* Neon element/structure load/store. */
16730 nUF(vld1
, vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16731 nUF(vst1
, vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16732 nUF(vld2
, vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16733 nUF(vst2
, vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16734 nUF(vld3
, vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16735 nUF(vst3
, vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16736 nUF(vld4
, vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16737 nUF(vst4
, vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
16739 #undef THUMB_VARIANT
16740 #define THUMB_VARIANT &fpu_vfp_ext_v3
16742 #define ARM_VARIANT &fpu_vfp_ext_v3
16743 cCE(fconsts
, eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
16744 cCE(fconstd
, eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
16745 cCE(fshtos
, eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16746 cCE(fshtod
, eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16747 cCE(fsltos
, eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16748 cCE(fsltod
, eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16749 cCE(fuhtos
, ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16750 cCE(fuhtod
, ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16751 cCE(fultos
, ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16752 cCE(fultod
, ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16753 cCE(ftoshs
, ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16754 cCE(ftoshd
, ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16755 cCE(ftosls
, ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16756 cCE(ftosld
, ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16757 cCE(ftouhs
, ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
16758 cCE(ftouhd
, ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
16759 cCE(ftouls
, ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
16760 cCE(ftould
, ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
16762 #undef THUMB_VARIANT
16764 #define ARM_VARIANT &arm_cext_xscale /* Intel XScale extensions. */
16765 cCE(mia
, e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16766 cCE(miaph
, e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16767 cCE(miabb
, e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16768 cCE(miabt
, e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16769 cCE(miatb
, e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16770 cCE(miatt
, e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
16771 cCE(mar
, c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
16772 cCE(mra
, c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
16775 #define ARM_VARIANT &arm_cext_iwmmxt /* Intel Wireless MMX technology. */
16776 cCE(tandcb
, e13f130
, 1, (RR
), iwmmxt_tandorc
),
16777 cCE(tandch
, e53f130
, 1, (RR
), iwmmxt_tandorc
),
16778 cCE(tandcw
, e93f130
, 1, (RR
), iwmmxt_tandorc
),
16779 cCE(tbcstb
, e400010
, 2, (RIWR
, RR
), rn_rd
),
16780 cCE(tbcsth
, e400050
, 2, (RIWR
, RR
), rn_rd
),
16781 cCE(tbcstw
, e400090
, 2, (RIWR
, RR
), rn_rd
),
16782 cCE(textrcb
, e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
16783 cCE(textrch
, e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
16784 cCE(textrcw
, e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
16785 cCE(textrmub
, e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16786 cCE(textrmuh
, e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16787 cCE(textrmuw
, e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16788 cCE(textrmsb
, e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16789 cCE(textrmsh
, e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16790 cCE(textrmsw
, e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
16791 cCE(tinsrb
, e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16792 cCE(tinsrh
, e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16793 cCE(tinsrw
, e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
16794 cCE(tmcr
, e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
16795 cCE(tmcrr
, c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
16796 cCE(tmia
, e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16797 cCE(tmiaph
, e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16798 cCE(tmiabb
, e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16799 cCE(tmiabt
, e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16800 cCE(tmiatb
, e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16801 cCE(tmiatt
, e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
16802 cCE(tmovmskb
, e100030
, 2, (RR
, RIWR
), rd_rn
),
16803 cCE(tmovmskh
, e500030
, 2, (RR
, RIWR
), rd_rn
),
16804 cCE(tmovmskw
, e900030
, 2, (RR
, RIWR
), rd_rn
),
16805 cCE(tmrc
, e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
16806 cCE(tmrrc
, c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
16807 cCE(torcb
, e13f150
, 1, (RR
), iwmmxt_tandorc
),
16808 cCE(torch
, e53f150
, 1, (RR
), iwmmxt_tandorc
),
16809 cCE(torcw
, e93f150
, 1, (RR
), iwmmxt_tandorc
),
16810 cCE(waccb
, e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16811 cCE(wacch
, e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16812 cCE(waccw
, e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16813 cCE(waddbss
, e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16814 cCE(waddb
, e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16815 cCE(waddbus
, e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16816 cCE(waddhss
, e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16817 cCE(waddh
, e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16818 cCE(waddhus
, e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16819 cCE(waddwss
, eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16820 cCE(waddw
, e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16821 cCE(waddwus
, e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16822 cCE(waligni
, e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
16823 cCE(walignr0
, e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16824 cCE(walignr1
, e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16825 cCE(walignr2
, ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16826 cCE(walignr3
, eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16827 cCE(wand
, e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16828 cCE(wandn
, e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16829 cCE(wavg2b
, e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16830 cCE(wavg2br
, e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16831 cCE(wavg2h
, ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16832 cCE(wavg2hr
, ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16833 cCE(wcmpeqb
, e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16834 cCE(wcmpeqh
, e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16835 cCE(wcmpeqw
, e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16836 cCE(wcmpgtub
, e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16837 cCE(wcmpgtuh
, e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16838 cCE(wcmpgtuw
, e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16839 cCE(wcmpgtsb
, e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16840 cCE(wcmpgtsh
, e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16841 cCE(wcmpgtsw
, eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16842 cCE(wldrb
, c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16843 cCE(wldrh
, c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16844 cCE(wldrw
, c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16845 cCE(wldrd
, c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16846 cCE(wmacs
, e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16847 cCE(wmacsz
, e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16848 cCE(wmacu
, e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16849 cCE(wmacuz
, e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16850 cCE(wmadds
, ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16851 cCE(wmaddu
, e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16852 cCE(wmaxsb
, e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16853 cCE(wmaxsh
, e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16854 cCE(wmaxsw
, ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16855 cCE(wmaxub
, e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16856 cCE(wmaxuh
, e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16857 cCE(wmaxuw
, e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16858 cCE(wminsb
, e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16859 cCE(wminsh
, e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16860 cCE(wminsw
, eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16861 cCE(wminub
, e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16862 cCE(wminuh
, e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16863 cCE(wminuw
, e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16864 cCE(wmov
, e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
16865 cCE(wmulsm
, e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16866 cCE(wmulsl
, e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16867 cCE(wmulum
, e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16868 cCE(wmulul
, e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16869 cCE(wor
, e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16870 cCE(wpackhss
, e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16871 cCE(wpackhus
, e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16872 cCE(wpackwss
, eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16873 cCE(wpackwus
, e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16874 cCE(wpackdss
, ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16875 cCE(wpackdus
, ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16876 cCE(wrorh
, e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16877 cCE(wrorhg
, e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16878 cCE(wrorw
, eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16879 cCE(wrorwg
, eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16880 cCE(wrord
, ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16881 cCE(wrordg
, ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16882 cCE(wsadb
, e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16883 cCE(wsadbz
, e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16884 cCE(wsadh
, e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16885 cCE(wsadhz
, e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16886 cCE(wshufh
, e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
16887 cCE(wsllh
, e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16888 cCE(wsllhg
, e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16889 cCE(wsllw
, e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16890 cCE(wsllwg
, e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16891 cCE(wslld
, ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16892 cCE(wslldg
, ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16893 cCE(wsrah
, e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16894 cCE(wsrahg
, e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16895 cCE(wsraw
, e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16896 cCE(wsrawg
, e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16897 cCE(wsrad
, ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16898 cCE(wsradg
, ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16899 cCE(wsrlh
, e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16900 cCE(wsrlhg
, e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16901 cCE(wsrlw
, ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16902 cCE(wsrlwg
, ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16903 cCE(wsrld
, ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
16904 cCE(wsrldg
, ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
16905 cCE(wstrb
, c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16906 cCE(wstrh
, c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
16907 cCE(wstrw
, c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
16908 cCE(wstrd
, c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
16909 cCE(wsubbss
, e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16910 cCE(wsubb
, e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16911 cCE(wsubbus
, e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16912 cCE(wsubhss
, e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16913 cCE(wsubh
, e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16914 cCE(wsubhus
, e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16915 cCE(wsubwss
, eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16916 cCE(wsubw
, e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16917 cCE(wsubwus
, e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16918 cCE(wunpckehub
,e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16919 cCE(wunpckehuh
,e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16920 cCE(wunpckehuw
,e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16921 cCE(wunpckehsb
,e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16922 cCE(wunpckehsh
,e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16923 cCE(wunpckehsw
,ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
16924 cCE(wunpckihb
, e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16925 cCE(wunpckihh
, e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16926 cCE(wunpckihw
, e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16927 cCE(wunpckelub
,e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16928 cCE(wunpckeluh
,e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16929 cCE(wunpckeluw
,e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16930 cCE(wunpckelsb
,e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16931 cCE(wunpckelsh
,e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16932 cCE(wunpckelsw
,ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
16933 cCE(wunpckilb
, e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16934 cCE(wunpckilh
, e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16935 cCE(wunpckilw
, e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16936 cCE(wxor
, e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16937 cCE(wzero
, e300000
, 1, (RIWR
), iwmmxt_wzero
),
16940 #define ARM_VARIANT &arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
16941 cCE(torvscb
, e13f190
, 1, (RR
), iwmmxt_tandorc
),
16942 cCE(torvsch
, e53f190
, 1, (RR
), iwmmxt_tandorc
),
16943 cCE(torvscw
, e93f190
, 1, (RR
), iwmmxt_tandorc
),
16944 cCE(wabsb
, e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16945 cCE(wabsh
, e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16946 cCE(wabsw
, ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
16947 cCE(wabsdiffb
, e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16948 cCE(wabsdiffh
, e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16949 cCE(wabsdiffw
, e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16950 cCE(waddbhusl
, e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16951 cCE(waddbhusm
, e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16952 cCE(waddhc
, e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16953 cCE(waddwc
, ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16954 cCE(waddsubhx
, ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16955 cCE(wavg4
, e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16956 cCE(wavg4r
, e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16957 cCE(wmaddsn
, ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16958 cCE(wmaddsx
, eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16959 cCE(wmaddun
, ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16960 cCE(wmaddux
, e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16961 cCE(wmerge
, e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
16962 cCE(wmiabb
, e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16963 cCE(wmiabt
, e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16964 cCE(wmiatb
, e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16965 cCE(wmiatt
, e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16966 cCE(wmiabbn
, e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16967 cCE(wmiabtn
, e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16968 cCE(wmiatbn
, e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16969 cCE(wmiattn
, e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16970 cCE(wmiawbb
, e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16971 cCE(wmiawbt
, e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16972 cCE(wmiawtb
, ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16973 cCE(wmiawtt
, eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16974 cCE(wmiawbbn
, ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16975 cCE(wmiawbtn
, ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16976 cCE(wmiawtbn
, ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16977 cCE(wmiawttn
, ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16978 cCE(wmulsmr
, ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16979 cCE(wmulumr
, ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16980 cCE(wmulwumr
, ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16981 cCE(wmulwsmr
, ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16982 cCE(wmulwum
, ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16983 cCE(wmulwsm
, ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16984 cCE(wmulwl
, eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16985 cCE(wqmiabb
, e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16986 cCE(wqmiabt
, e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16987 cCE(wqmiatb
, ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16988 cCE(wqmiatt
, eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16989 cCE(wqmiabbn
, ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16990 cCE(wqmiabtn
, ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16991 cCE(wqmiatbn
, ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16992 cCE(wqmiattn
, ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16993 cCE(wqmulm
, e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16994 cCE(wqmulmr
, e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16995 cCE(wqmulwm
, ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16996 cCE(wqmulwmr
, ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
16997 cCE(wsubaddhx
, ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
17000 #define ARM_VARIANT &arm_cext_maverick /* Cirrus Maverick instructions. */
17001 cCE(cfldrs
, c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17002 cCE(cfldrd
, c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17003 cCE(cfldr32
, c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17004 cCE(cfldr64
, c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17005 cCE(cfstrs
, c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
17006 cCE(cfstrd
, c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
17007 cCE(cfstr32
, c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
17008 cCE(cfstr64
, c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
17009 cCE(cfmvsr
, e000450
, 2, (RMF
, RR
), rn_rd
),
17010 cCE(cfmvrs
, e100450
, 2, (RR
, RMF
), rd_rn
),
17011 cCE(cfmvdlr
, e000410
, 2, (RMD
, RR
), rn_rd
),
17012 cCE(cfmvrdl
, e100410
, 2, (RR
, RMD
), rd_rn
),
17013 cCE(cfmvdhr
, e000430
, 2, (RMD
, RR
), rn_rd
),
17014 cCE(cfmvrdh
, e100430
, 2, (RR
, RMD
), rd_rn
),
17015 cCE(cfmv64lr
, e000510
, 2, (RMDX
, RR
), rn_rd
),
17016 cCE(cfmvr64l
, e100510
, 2, (RR
, RMDX
), rd_rn
),
17017 cCE(cfmv64hr
, e000530
, 2, (RMDX
, RR
), rn_rd
),
17018 cCE(cfmvr64h
, e100530
, 2, (RR
, RMDX
), rd_rn
),
17019 cCE(cfmval32
, e200440
, 2, (RMAX
, RMFX
), rd_rn
),
17020 cCE(cfmv32al
, e100440
, 2, (RMFX
, RMAX
), rd_rn
),
17021 cCE(cfmvam32
, e200460
, 2, (RMAX
, RMFX
), rd_rn
),
17022 cCE(cfmv32am
, e100460
, 2, (RMFX
, RMAX
), rd_rn
),
17023 cCE(cfmvah32
, e200480
, 2, (RMAX
, RMFX
), rd_rn
),
17024 cCE(cfmv32ah
, e100480
, 2, (RMFX
, RMAX
), rd_rn
),
17025 cCE(cfmva32
, e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
17026 cCE(cfmv32a
, e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
17027 cCE(cfmva64
, e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
17028 cCE(cfmv64a
, e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
17029 cCE(cfmvsc32
, e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
17030 cCE(cfmv32sc
, e1004e0
, 2, (RMDX
, RMDS
), rd
),
17031 cCE(cfcpys
, e000400
, 2, (RMF
, RMF
), rd_rn
),
17032 cCE(cfcpyd
, e000420
, 2, (RMD
, RMD
), rd_rn
),
17033 cCE(cfcvtsd
, e000460
, 2, (RMD
, RMF
), rd_rn
),
17034 cCE(cfcvtds
, e000440
, 2, (RMF
, RMD
), rd_rn
),
17035 cCE(cfcvt32s
, e000480
, 2, (RMF
, RMFX
), rd_rn
),
17036 cCE(cfcvt32d
, e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
17037 cCE(cfcvt64s
, e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
17038 cCE(cfcvt64d
, e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
17039 cCE(cfcvts32
, e100580
, 2, (RMFX
, RMF
), rd_rn
),
17040 cCE(cfcvtd32
, e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
17041 cCE(cftruncs32
,e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
17042 cCE(cftruncd32
,e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
17043 cCE(cfrshl32
, e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
17044 cCE(cfrshl64
, e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
17045 cCE(cfsh32
, e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
17046 cCE(cfsh64
, e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
17047 cCE(cfcmps
, e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
17048 cCE(cfcmpd
, e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
17049 cCE(cfcmp32
, e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
17050 cCE(cfcmp64
, e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
17051 cCE(cfabss
, e300400
, 2, (RMF
, RMF
), rd_rn
),
17052 cCE(cfabsd
, e300420
, 2, (RMD
, RMD
), rd_rn
),
17053 cCE(cfnegs
, e300440
, 2, (RMF
, RMF
), rd_rn
),
17054 cCE(cfnegd
, e300460
, 2, (RMD
, RMD
), rd_rn
),
17055 cCE(cfadds
, e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17056 cCE(cfaddd
, e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17057 cCE(cfsubs
, e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17058 cCE(cfsubd
, e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17059 cCE(cfmuls
, e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
17060 cCE(cfmuld
, e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
17061 cCE(cfabs32
, e300500
, 2, (RMFX
, RMFX
), rd_rn
),
17062 cCE(cfabs64
, e300520
, 2, (RMDX
, RMDX
), rd_rn
),
17063 cCE(cfneg32
, e300540
, 2, (RMFX
, RMFX
), rd_rn
),
17064 cCE(cfneg64
, e300560
, 2, (RMDX
, RMDX
), rd_rn
),
17065 cCE(cfadd32
, e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17066 cCE(cfadd64
, e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17067 cCE(cfsub32
, e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17068 cCE(cfsub64
, e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17069 cCE(cfmul32
, e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17070 cCE(cfmul64
, e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
17071 cCE(cfmac32
, e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17072 cCE(cfmsc32
, e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
17073 cCE(cfmadd32
, e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17074 cCE(cfmsub32
, e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
17075 cCE(cfmadda32
, e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17076 cCE(cfmsuba32
, e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
17079 #undef THUMB_VARIANT
17106 /* MD interface: bits in the object file. */
17108 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
17109 for use in the a.out file, and stores them in the array pointed to by buf.
17110 This knows about the endian-ness of the target machine and does
17111 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
17112 2 (short) and 4 (long) Floating numbers are put out as a series of
17113 LITTLENUMS (shorts, here at least). */
17116 md_number_to_chars (char * buf
, valueT val
, int n
)
17118 if (target_big_endian
)
17119 number_to_chars_bigendian (buf
, val
, n
);
17121 number_to_chars_littleendian (buf
, val
, n
);
17125 md_chars_to_number (char * buf
, int n
)
17128 unsigned char * where
= (unsigned char *) buf
;
17130 if (target_big_endian
)
17135 result
|= (*where
++ & 255);
17143 result
|= (where
[n
] & 255);
17150 /* MD interface: Sections. */
17152 /* Estimate the size of a frag before relaxing. Assume everything fits in
17156 md_estimate_size_before_relax (fragS
* fragp
,
17157 segT segtype ATTRIBUTE_UNUSED
)
17163 /* Convert a machine dependent frag. */
17166 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
17168 unsigned long insn
;
17169 unsigned long old_op
;
17177 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17179 old_op
= bfd_get_16(abfd
, buf
);
17180 if (fragp
->fr_symbol
)
17182 exp
.X_op
= O_symbol
;
17183 exp
.X_add_symbol
= fragp
->fr_symbol
;
17187 exp
.X_op
= O_constant
;
17189 exp
.X_add_number
= fragp
->fr_offset
;
17190 opcode
= fragp
->fr_subtype
;
17193 case T_MNEM_ldr_pc
:
17194 case T_MNEM_ldr_pc2
:
17195 case T_MNEM_ldr_sp
:
17196 case T_MNEM_str_sp
:
17203 if (fragp
->fr_var
== 4)
17205 insn
= THUMB_OP32 (opcode
);
17206 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
17208 insn
|= (old_op
& 0x700) << 4;
17212 insn
|= (old_op
& 7) << 12;
17213 insn
|= (old_op
& 0x38) << 13;
17215 insn
|= 0x00000c00;
17216 put_thumb32_insn (buf
, insn
);
17217 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
17221 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
17223 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
17226 if (fragp
->fr_var
== 4)
17228 insn
= THUMB_OP32 (opcode
);
17229 insn
|= (old_op
& 0xf0) << 4;
17230 put_thumb32_insn (buf
, insn
);
17231 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
17235 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17236 exp
.X_add_number
-= 4;
17244 if (fragp
->fr_var
== 4)
17246 int r0off
= (opcode
== T_MNEM_mov
17247 || opcode
== T_MNEM_movs
) ? 0 : 8;
17248 insn
= THUMB_OP32 (opcode
);
17249 insn
= (insn
& 0xe1ffffff) | 0x10000000;
17250 insn
|= (old_op
& 0x700) << r0off
;
17251 put_thumb32_insn (buf
, insn
);
17252 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
17256 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
17261 if (fragp
->fr_var
== 4)
17263 insn
= THUMB_OP32(opcode
);
17264 put_thumb32_insn (buf
, insn
);
17265 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
17268 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
17272 if (fragp
->fr_var
== 4)
17274 insn
= THUMB_OP32(opcode
);
17275 insn
|= (old_op
& 0xf00) << 14;
17276 put_thumb32_insn (buf
, insn
);
17277 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
17280 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
17283 case T_MNEM_add_sp
:
17284 case T_MNEM_add_pc
:
17285 case T_MNEM_inc_sp
:
17286 case T_MNEM_dec_sp
:
17287 if (fragp
->fr_var
== 4)
17289 /* ??? Choose between add and addw. */
17290 insn
= THUMB_OP32 (opcode
);
17291 insn
|= (old_op
& 0xf0) << 4;
17292 put_thumb32_insn (buf
, insn
);
17293 if (opcode
== T_MNEM_add_pc
)
17294 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
17296 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
17299 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17307 if (fragp
->fr_var
== 4)
17309 insn
= THUMB_OP32 (opcode
);
17310 insn
|= (old_op
& 0xf0) << 4;
17311 insn
|= (old_op
& 0xf) << 16;
17312 put_thumb32_insn (buf
, insn
);
17313 if (insn
& (1 << 20))
17314 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
17316 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
17319 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
17325 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
17327 fixp
->fx_file
= fragp
->fr_file
;
17328 fixp
->fx_line
= fragp
->fr_line
;
17329 fragp
->fr_fix
+= fragp
->fr_var
;
17332 /* Return the size of a relaxable immediate operand instruction.
17333 SHIFT and SIZE specify the form of the allowable immediate. */
17335 relax_immediate (fragS
*fragp
, int size
, int shift
)
17341 /* ??? Should be able to do better than this. */
17342 if (fragp
->fr_symbol
)
17345 low
= (1 << shift
) - 1;
17346 mask
= (1 << (shift
+ size
)) - (1 << shift
);
17347 offset
= fragp
->fr_offset
;
17348 /* Force misaligned offsets to 32-bit variant. */
17351 if (offset
& ~mask
)
17356 /* Get the address of a symbol during relaxation. */
17358 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
17364 sym
= fragp
->fr_symbol
;
17365 sym_frag
= symbol_get_frag (sym
);
17366 know (S_GET_SEGMENT (sym
) != absolute_section
17367 || sym_frag
== &zero_address_frag
);
17368 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
17370 /* If frag has yet to be reached on this pass, assume it will
17371 move by STRETCH just as we did. If this is not so, it will
17372 be because some frag between grows, and that will force
17376 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
17380 /* Adjust stretch for any alignment frag. Note that if have
17381 been expanding the earlier code, the symbol may be
17382 defined in what appears to be an earlier frag. FIXME:
17383 This doesn't handle the fr_subtype field, which specifies
17384 a maximum number of bytes to skip when doing an
17386 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
17388 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
17391 stretch
= - ((- stretch
)
17392 & ~ ((1 << (int) f
->fr_offset
) - 1));
17394 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
17406 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
17409 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
17414 /* Assume worst case for symbols not known to be in the same section. */
17415 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17416 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17419 val
= relaxed_symbol_addr (fragp
, stretch
);
17420 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
17421 addr
= (addr
+ 4) & ~3;
17422 /* Force misaligned targets to 32-bit variant. */
17426 if (val
< 0 || val
> 1020)
17431 /* Return the size of a relaxable add/sub immediate instruction. */
17433 relax_addsub (fragS
*fragp
, asection
*sec
)
17438 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
17439 op
= bfd_get_16(sec
->owner
, buf
);
17440 if ((op
& 0xf) == ((op
>> 4) & 0xf))
17441 return relax_immediate (fragp
, 8, 0);
17443 return relax_immediate (fragp
, 3, 0);
17447 /* Return the size of a relaxable branch instruction. BITS is the
17448 size of the offset field in the narrow instruction. */
17451 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
17457 /* Assume worst case for symbols not known to be in the same section. */
17458 if (!S_IS_DEFINED (fragp
->fr_symbol
)
17459 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
))
17462 val
= relaxed_symbol_addr (fragp
, stretch
);
17463 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
17466 /* Offset is a signed value *2 */
17468 if (val
>= limit
|| val
< -limit
)
17474 /* Relax a machine dependent frag. This returns the amount by which
17475 the current size of the frag should change. */
17478 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
17483 oldsize
= fragp
->fr_var
;
17484 switch (fragp
->fr_subtype
)
17486 case T_MNEM_ldr_pc2
:
17487 newsize
= relax_adr (fragp
, sec
, stretch
);
17489 case T_MNEM_ldr_pc
:
17490 case T_MNEM_ldr_sp
:
17491 case T_MNEM_str_sp
:
17492 newsize
= relax_immediate (fragp
, 8, 2);
17496 newsize
= relax_immediate (fragp
, 5, 2);
17500 newsize
= relax_immediate (fragp
, 5, 1);
17504 newsize
= relax_immediate (fragp
, 5, 0);
17507 newsize
= relax_adr (fragp
, sec
, stretch
);
17513 newsize
= relax_immediate (fragp
, 8, 0);
17516 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
17519 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
17521 case T_MNEM_add_sp
:
17522 case T_MNEM_add_pc
:
17523 newsize
= relax_immediate (fragp
, 8, 2);
17525 case T_MNEM_inc_sp
:
17526 case T_MNEM_dec_sp
:
17527 newsize
= relax_immediate (fragp
, 7, 2);
17533 newsize
= relax_addsub (fragp
, sec
);
17539 fragp
->fr_var
= newsize
;
17540 /* Freeze wide instructions that are at or before the same location as
17541 in the previous pass. This avoids infinite loops.
17542 Don't freeze them unconditionally because targets may be artificially
17543 misaligned by the expansion of preceding frags. */
17544 if (stretch
<= 0 && newsize
> 2)
17546 md_convert_frag (sec
->owner
, sec
, fragp
);
17550 return newsize
- oldsize
;
17553 /* Round up a section size to the appropriate boundary. */
17556 md_section_align (segT segment ATTRIBUTE_UNUSED
,
17559 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
17560 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
17562 /* For a.out, force the section size to be aligned. If we don't do
17563 this, BFD will align it for us, but it will not write out the
17564 final bytes of the section. This may be a bug in BFD, but it is
17565 easier to fix it here since that is how the other a.out targets
17569 align
= bfd_get_section_alignment (stdoutput
, segment
);
17570 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
17577 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
17578 of an rs_align_code fragment. */
17581 arm_handle_align (fragS
* fragP
)
17583 static char const arm_noop
[4] = { 0x00, 0x00, 0xa0, 0xe1 };
17584 static char const thumb_noop
[2] = { 0xc0, 0x46 };
17585 static char const arm_bigend_noop
[4] = { 0xe1, 0xa0, 0x00, 0x00 };
17586 static char const thumb_bigend_noop
[2] = { 0x46, 0xc0 };
17588 int bytes
, fix
, noop_size
;
17592 if (fragP
->fr_type
!= rs_align_code
)
17595 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
17596 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
17599 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17600 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
17602 assert ((fragP
->tc_frag_data
& MODE_RECORDED
) != 0);
17604 if (fragP
->tc_frag_data
& (~ MODE_RECORDED
))
17606 if (target_big_endian
)
17607 noop
= thumb_bigend_noop
;
17610 noop_size
= sizeof (thumb_noop
);
17614 if (target_big_endian
)
17615 noop
= arm_bigend_noop
;
17618 noop_size
= sizeof (arm_noop
);
17621 if (bytes
& (noop_size
- 1))
17623 fix
= bytes
& (noop_size
- 1);
17624 memset (p
, 0, fix
);
17629 while (bytes
>= noop_size
)
17631 memcpy (p
, noop
, noop_size
);
17633 bytes
-= noop_size
;
17637 fragP
->fr_fix
+= fix
;
17638 fragP
->fr_var
= noop_size
;
17641 /* Called from md_do_align. Used to create an alignment
17642 frag in a code section. */
17645 arm_frag_align_code (int n
, int max
)
17649 /* We assume that there will never be a requirement
17650 to support alignments greater than 32 bytes. */
17651 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
17652 as_fatal (_("alignments greater than 32 bytes not supported in .text sections."));
17654 p
= frag_var (rs_align_code
,
17655 MAX_MEM_FOR_RS_ALIGN_CODE
,
17657 (relax_substateT
) max
,
17664 /* Perform target specific initialisation of a frag.
17665 Note - despite the name this initialisation is not done when the frag
17666 is created, but only when its type is assigned. A frag can be created
17667 and used a long time before its type is set, so beware of assuming that
17668 this initialisationis performed first. */
17671 arm_init_frag (fragS
* fragP
)
17673 /* If the current ARM vs THUMB mode has not already
17674 been recorded into this frag then do so now. */
17675 if ((fragP
->tc_frag_data
& MODE_RECORDED
) == 0)
17676 fragP
->tc_frag_data
= thumb_mode
| MODE_RECORDED
;
17680 /* When we change sections we need to issue a new mapping symbol. */
17683 arm_elf_change_section (void)
17686 segment_info_type
*seginfo
;
17688 /* Link an unlinked unwind index table section to the .text section. */
17689 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
17690 && elf_linked_to_section (now_seg
) == NULL
)
17691 elf_linked_to_section (now_seg
) = text_section
;
17693 if (!SEG_NORMAL (now_seg
))
17696 flags
= bfd_get_section_flags (stdoutput
, now_seg
);
17698 /* We can ignore sections that only contain debug info. */
17699 if ((flags
& SEC_ALLOC
) == 0)
17702 seginfo
= seg_info (now_seg
);
17703 mapstate
= seginfo
->tc_segment_info_data
.mapstate
;
17704 marked_pr_dependency
= seginfo
->tc_segment_info_data
.marked_pr_dependency
;
17708 arm_elf_section_type (const char * str
, size_t len
)
17710 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
17711 return SHT_ARM_EXIDX
;
17716 /* Code to deal with unwinding tables. */
17718 static void add_unwind_adjustsp (offsetT
);
17720 /* Generate any deferred unwind frame offset. */
17723 flush_pending_unwind (void)
17727 offset
= unwind
.pending_offset
;
17728 unwind
.pending_offset
= 0;
17730 add_unwind_adjustsp (offset
);
17733 /* Add an opcode to this list for this function. Two-byte opcodes should
17734 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
17738 add_unwind_opcode (valueT op
, int length
)
17740 /* Add any deferred stack adjustment. */
17741 if (unwind
.pending_offset
)
17742 flush_pending_unwind ();
17744 unwind
.sp_restored
= 0;
17746 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
17748 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
17749 if (unwind
.opcodes
)
17750 unwind
.opcodes
= xrealloc (unwind
.opcodes
,
17751 unwind
.opcode_alloc
);
17753 unwind
.opcodes
= xmalloc (unwind
.opcode_alloc
);
17758 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
17760 unwind
.opcode_count
++;
17764 /* Add unwind opcodes to adjust the stack pointer. */
17767 add_unwind_adjustsp (offsetT offset
)
17771 if (offset
> 0x200)
17773 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
17778 /* Long form: 0xb2, uleb128. */
17779 /* This might not fit in a word so add the individual bytes,
17780 remembering the list is built in reverse order. */
17781 o
= (valueT
) ((offset
- 0x204) >> 2);
17783 add_unwind_opcode (0, 1);
17785 /* Calculate the uleb128 encoding of the offset. */
17789 bytes
[n
] = o
& 0x7f;
17795 /* Add the insn. */
17797 add_unwind_opcode (bytes
[n
- 1], 1);
17798 add_unwind_opcode (0xb2, 1);
17800 else if (offset
> 0x100)
17802 /* Two short opcodes. */
17803 add_unwind_opcode (0x3f, 1);
17804 op
= (offset
- 0x104) >> 2;
17805 add_unwind_opcode (op
, 1);
17807 else if (offset
> 0)
17809 /* Short opcode. */
17810 op
= (offset
- 4) >> 2;
17811 add_unwind_opcode (op
, 1);
17813 else if (offset
< 0)
17816 while (offset
> 0x100)
17818 add_unwind_opcode (0x7f, 1);
17821 op
= ((offset
- 4) >> 2) | 0x40;
17822 add_unwind_opcode (op
, 1);
17826 /* Finish the list of unwind opcodes for this function. */
17828 finish_unwind_opcodes (void)
17832 if (unwind
.fp_used
)
17834 /* Adjust sp as necessary. */
17835 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
17836 flush_pending_unwind ();
17838 /* After restoring sp from the frame pointer. */
17839 op
= 0x90 | unwind
.fp_reg
;
17840 add_unwind_opcode (op
, 1);
17843 flush_pending_unwind ();
17847 /* Start an exception table entry. If idx is nonzero this is an index table
17851 start_unwind_section (const segT text_seg
, int idx
)
17853 const char * text_name
;
17854 const char * prefix
;
17855 const char * prefix_once
;
17856 const char * group_name
;
17860 size_t sec_name_len
;
17867 prefix
= ELF_STRING_ARM_unwind
;
17868 prefix_once
= ELF_STRING_ARM_unwind_once
;
17869 type
= SHT_ARM_EXIDX
;
17873 prefix
= ELF_STRING_ARM_unwind_info
;
17874 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
17875 type
= SHT_PROGBITS
;
17878 text_name
= segment_name (text_seg
);
17879 if (streq (text_name
, ".text"))
17882 if (strncmp (text_name
, ".gnu.linkonce.t.",
17883 strlen (".gnu.linkonce.t.")) == 0)
17885 prefix
= prefix_once
;
17886 text_name
+= strlen (".gnu.linkonce.t.");
17889 prefix_len
= strlen (prefix
);
17890 text_len
= strlen (text_name
);
17891 sec_name_len
= prefix_len
+ text_len
;
17892 sec_name
= xmalloc (sec_name_len
+ 1);
17893 memcpy (sec_name
, prefix
, prefix_len
);
17894 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
17895 sec_name
[prefix_len
+ text_len
] = '\0';
17901 /* Handle COMDAT group. */
17902 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
17904 group_name
= elf_group_name (text_seg
);
17905 if (group_name
== NULL
)
17907 as_bad (_("Group section `%s' has no group signature"),
17908 segment_name (text_seg
));
17909 ignore_rest_of_line ();
17912 flags
|= SHF_GROUP
;
17916 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
17918 /* Set the section link for index tables. */
17920 elf_linked_to_section (now_seg
) = text_seg
;
17924 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
17925 personality routine data. Returns zero, or the index table value for
17926 and inline entry. */
17929 create_unwind_entry (int have_data
)
17934 /* The current word of data. */
17936 /* The number of bytes left in this word. */
17939 finish_unwind_opcodes ();
17941 /* Remember the current text section. */
17942 unwind
.saved_seg
= now_seg
;
17943 unwind
.saved_subseg
= now_subseg
;
17945 start_unwind_section (now_seg
, 0);
17947 if (unwind
.personality_routine
== NULL
)
17949 if (unwind
.personality_index
== -2)
17952 as_bad (_("handlerdata in cantunwind frame"));
17953 return 1; /* EXIDX_CANTUNWIND. */
17956 /* Use a default personality routine if none is specified. */
17957 if (unwind
.personality_index
== -1)
17959 if (unwind
.opcode_count
> 3)
17960 unwind
.personality_index
= 1;
17962 unwind
.personality_index
= 0;
17965 /* Space for the personality routine entry. */
17966 if (unwind
.personality_index
== 0)
17968 if (unwind
.opcode_count
> 3)
17969 as_bad (_("too many unwind opcodes for personality routine 0"));
17973 /* All the data is inline in the index table. */
17976 while (unwind
.opcode_count
> 0)
17978 unwind
.opcode_count
--;
17979 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
17983 /* Pad with "finish" opcodes. */
17985 data
= (data
<< 8) | 0xb0;
17992 /* We get two opcodes "free" in the first word. */
17993 size
= unwind
.opcode_count
- 2;
17996 /* An extra byte is required for the opcode count. */
17997 size
= unwind
.opcode_count
+ 1;
17999 size
= (size
+ 3) >> 2;
18001 as_bad (_("too many unwind opcodes"));
18003 frag_align (2, 0, 0);
18004 record_alignment (now_seg
, 2);
18005 unwind
.table_entry
= expr_build_dot ();
18007 /* Allocate the table entry. */
18008 ptr
= frag_more ((size
<< 2) + 4);
18009 where
= frag_now_fix () - ((size
<< 2) + 4);
18011 switch (unwind
.personality_index
)
18014 /* ??? Should this be a PLT generating relocation? */
18015 /* Custom personality routine. */
18016 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
18017 BFD_RELOC_ARM_PREL31
);
18022 /* Set the first byte to the number of additional words. */
18027 /* ABI defined personality routines. */
18029 /* Three opcodes bytes are packed into the first word. */
18036 /* The size and first two opcode bytes go in the first word. */
18037 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
18042 /* Should never happen. */
18046 /* Pack the opcodes into words (MSB first), reversing the list at the same
18048 while (unwind
.opcode_count
> 0)
18052 md_number_to_chars (ptr
, data
, 4);
18057 unwind
.opcode_count
--;
18059 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
18062 /* Finish off the last word. */
18065 /* Pad with "finish" opcodes. */
18067 data
= (data
<< 8) | 0xb0;
18069 md_number_to_chars (ptr
, data
, 4);
18074 /* Add an empty descriptor if there is no user-specified data. */
18075 ptr
= frag_more (4);
18076 md_number_to_chars (ptr
, 0, 4);
18083 /* Initialize the DWARF-2 unwind information for this procedure. */
18086 tc_arm_frame_initial_instructions (void)
18088 cfi_add_CFA_def_cfa (REG_SP
, 0);
18090 #endif /* OBJ_ELF */
18092 /* Convert REGNAME to a DWARF-2 register number. */
18095 tc_arm_regname_to_dw2regnum (char *regname
)
18097 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
18107 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
18111 expr
.X_op
= O_secrel
;
18112 expr
.X_add_symbol
= symbol
;
18113 expr
.X_add_number
= 0;
18114 emit_expr (&expr
, size
);
18118 /* MD interface: Symbol and relocation handling. */
18120 /* Return the address within the segment that a PC-relative fixup is
18121 relative to. For ARM, PC-relative fixups applied to instructions
18122 are generally relative to the location of the fixup plus 8 bytes.
18123 Thumb branches are offset by 4, and Thumb loads relative to PC
18124 require special handling. */
18127 md_pcrel_from_section (fixS
* fixP
, segT seg
)
18129 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
18131 /* If this is pc-relative and we are going to emit a relocation
18132 then we just want to put out any pipeline compensation that the linker
18133 will need. Otherwise we want to use the calculated base.
18134 For WinCE we skip the bias for externals as well, since this
18135 is how the MS ARM-CE assembler behaves and we want to be compatible. */
18137 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18138 || (arm_force_relocation (fixP
)
18140 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
18145 switch (fixP
->fx_r_type
)
18147 /* PC relative addressing on the Thumb is slightly odd as the
18148 bottom two bits of the PC are forced to zero for the
18149 calculation. This happens *after* application of the
18150 pipeline offset. However, Thumb adrl already adjusts for
18151 this, so we need not do it again. */
18152 case BFD_RELOC_ARM_THUMB_ADD
:
18155 case BFD_RELOC_ARM_THUMB_OFFSET
:
18156 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18157 case BFD_RELOC_ARM_T32_ADD_PC12
:
18158 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
18159 return (base
+ 4) & ~3;
18161 /* Thumb branches are simply offset by +4. */
18162 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
18163 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
18164 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
18165 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
18166 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
18167 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
18168 case BFD_RELOC_THUMB_PCREL_BLX
:
18171 /* ARM mode branches are offset by +8. However, the Windows CE
18172 loader expects the relocation not to take this into account. */
18173 case BFD_RELOC_ARM_PCREL_BRANCH
:
18174 case BFD_RELOC_ARM_PCREL_CALL
:
18175 case BFD_RELOC_ARM_PCREL_JUMP
:
18176 case BFD_RELOC_ARM_PCREL_BLX
:
18177 case BFD_RELOC_ARM_PLT32
:
18179 /* When handling fixups immediately, because we have already
18180 discovered the value of a symbol, or the address of the frag involved
18181 we must account for the offset by +8, as the OS loader will never see the reloc.
18182 see fixup_segment() in write.c
18183 The S_IS_EXTERNAL test handles the case of global symbols.
18184 Those need the calculated base, not just the pipe compensation the linker will need. */
18186 && fixP
->fx_addsy
!= NULL
18187 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
18188 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
18195 /* ARM mode loads relative to PC are also offset by +8. Unlike
18196 branches, the Windows CE loader *does* expect the relocation
18197 to take this into account. */
18198 case BFD_RELOC_ARM_OFFSET_IMM
:
18199 case BFD_RELOC_ARM_OFFSET_IMM8
:
18200 case BFD_RELOC_ARM_HWLITERAL
:
18201 case BFD_RELOC_ARM_LITERAL
:
18202 case BFD_RELOC_ARM_CP_OFF_IMM
:
18206 /* Other PC-relative relocations are un-offset. */
18212 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
18213 Otherwise we have no need to default values of symbols. */
18216 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
18219 if (name
[0] == '_' && name
[1] == 'G'
18220 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
18224 if (symbol_find (name
))
18225 as_bad (_("GOT already in the symbol table"));
18227 GOT_symbol
= symbol_new (name
, undefined_section
,
18228 (valueT
) 0, & zero_address_frag
);
18238 /* Subroutine of md_apply_fix. Check to see if an immediate can be
18239 computed as two separate immediate values, added together. We
18240 already know that this value cannot be computed by just one ARM
18243 static unsigned int
18244 validate_immediate_twopart (unsigned int val
,
18245 unsigned int * highpart
)
18250 for (i
= 0; i
< 32; i
+= 2)
18251 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
18257 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
18259 else if (a
& 0xff0000)
18261 if (a
& 0xff000000)
18263 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
18267 assert (a
& 0xff000000);
18268 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
18271 return (a
& 0xff) | (i
<< 7);
18278 validate_offset_imm (unsigned int val
, int hwse
)
18280 if ((hwse
&& val
> 255) || val
> 4095)
18285 /* Subroutine of md_apply_fix. Do those data_ops which can take a
18286 negative immediate constant by altering the instruction. A bit of
18291 by inverting the second operand, and
18294 by negating the second operand. */
18297 negate_data_op (unsigned long * instruction
,
18298 unsigned long value
)
18301 unsigned long negated
, inverted
;
18303 negated
= encode_arm_immediate (-value
);
18304 inverted
= encode_arm_immediate (~value
);
18306 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
18309 /* First negates. */
18310 case OPCODE_SUB
: /* ADD <-> SUB */
18311 new_inst
= OPCODE_ADD
;
18316 new_inst
= OPCODE_SUB
;
18320 case OPCODE_CMP
: /* CMP <-> CMN */
18321 new_inst
= OPCODE_CMN
;
18326 new_inst
= OPCODE_CMP
;
18330 /* Now Inverted ops. */
18331 case OPCODE_MOV
: /* MOV <-> MVN */
18332 new_inst
= OPCODE_MVN
;
18337 new_inst
= OPCODE_MOV
;
18341 case OPCODE_AND
: /* AND <-> BIC */
18342 new_inst
= OPCODE_BIC
;
18347 new_inst
= OPCODE_AND
;
18351 case OPCODE_ADC
: /* ADC <-> SBC */
18352 new_inst
= OPCODE_SBC
;
18357 new_inst
= OPCODE_ADC
;
18361 /* We cannot do anything. */
18366 if (value
== (unsigned) FAIL
)
18369 *instruction
&= OPCODE_MASK
;
18370 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
18374 /* Like negate_data_op, but for Thumb-2. */
18376 static unsigned int
18377 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
18381 unsigned int negated
, inverted
;
18383 negated
= encode_thumb32_immediate (-value
);
18384 inverted
= encode_thumb32_immediate (~value
);
18386 rd
= (*instruction
>> 8) & 0xf;
18387 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
18390 /* ADD <-> SUB. Includes CMP <-> CMN. */
18391 case T2_OPCODE_SUB
:
18392 new_inst
= T2_OPCODE_ADD
;
18396 case T2_OPCODE_ADD
:
18397 new_inst
= T2_OPCODE_SUB
;
18401 /* ORR <-> ORN. Includes MOV <-> MVN. */
18402 case T2_OPCODE_ORR
:
18403 new_inst
= T2_OPCODE_ORN
;
18407 case T2_OPCODE_ORN
:
18408 new_inst
= T2_OPCODE_ORR
;
18412 /* AND <-> BIC. TST has no inverted equivalent. */
18413 case T2_OPCODE_AND
:
18414 new_inst
= T2_OPCODE_BIC
;
18421 case T2_OPCODE_BIC
:
18422 new_inst
= T2_OPCODE_AND
;
18427 case T2_OPCODE_ADC
:
18428 new_inst
= T2_OPCODE_SBC
;
18432 case T2_OPCODE_SBC
:
18433 new_inst
= T2_OPCODE_ADC
;
18437 /* We cannot do anything. */
18442 if (value
== (unsigned int)FAIL
)
18445 *instruction
&= T2_OPCODE_MASK
;
18446 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
18450 /* Read a 32-bit thumb instruction from buf. */
18451 static unsigned long
18452 get_thumb32_insn (char * buf
)
18454 unsigned long insn
;
18455 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
18456 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
18462 /* We usually want to set the low bit on the address of thumb function
18463 symbols. In particular .word foo - . should have the low bit set.
18464 Generic code tries to fold the difference of two symbols to
18465 a constant. Prevent this and force a relocation when the first symbols
18466 is a thumb function. */
18468 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
18470 if (op
== O_subtract
18471 && l
->X_op
== O_symbol
18472 && r
->X_op
== O_symbol
18473 && THUMB_IS_FUNC (l
->X_add_symbol
))
18475 l
->X_op
= O_subtract
;
18476 l
->X_op_symbol
= r
->X_add_symbol
;
18477 l
->X_add_number
-= r
->X_add_number
;
18480 /* Process as normal. */
18485 md_apply_fix (fixS
* fixP
,
18489 offsetT value
= * valP
;
18491 unsigned int newimm
;
18492 unsigned long temp
;
18494 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
18496 assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
18498 /* Note whether this will delete the relocation. */
18500 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
18503 /* On a 64-bit host, silently truncate 'value' to 32 bits for
18504 consistency with the behaviour on 32-bit hosts. Remember value
18506 value
&= 0xffffffff;
18507 value
^= 0x80000000;
18508 value
-= 0x80000000;
18511 fixP
->fx_addnumber
= value
;
18513 /* Same treatment for fixP->fx_offset. */
18514 fixP
->fx_offset
&= 0xffffffff;
18515 fixP
->fx_offset
^= 0x80000000;
18516 fixP
->fx_offset
-= 0x80000000;
18518 switch (fixP
->fx_r_type
)
18520 case BFD_RELOC_NONE
:
18521 /* This will need to go in the object file. */
18525 case BFD_RELOC_ARM_IMMEDIATE
:
18526 /* We claim that this fixup has been processed here,
18527 even if in fact we generate an error because we do
18528 not have a reloc for it, so tc_gen_reloc will reject it. */
18532 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18534 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18535 _("undefined symbol %s used as an immediate value"),
18536 S_GET_NAME (fixP
->fx_addsy
));
18541 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18543 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18544 _("symbol %s is in a different section"),
18545 S_GET_NAME (fixP
->fx_addsy
));
18549 newimm
= encode_arm_immediate (value
);
18550 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18552 /* If the instruction will fail, see if we can fix things up by
18553 changing the opcode. */
18554 if (newimm
== (unsigned int) FAIL
18555 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
18557 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18558 _("invalid constant (%lx) after fixup"),
18559 (unsigned long) value
);
18563 newimm
|= (temp
& 0xfffff000);
18564 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18567 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
18569 unsigned int highpart
= 0;
18570 unsigned int newinsn
= 0xe1a00000; /* nop. */
18573 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18575 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18576 _("undefined symbol %s used as an immediate value"),
18577 S_GET_NAME (fixP
->fx_addsy
));
18582 && S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
18584 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18585 _("symbol %s is in a different section"),
18586 S_GET_NAME (fixP
->fx_addsy
));
18590 newimm
= encode_arm_immediate (value
);
18591 temp
= md_chars_to_number (buf
, INSN_SIZE
);
18593 /* If the instruction will fail, see if we can fix things up by
18594 changing the opcode. */
18595 if (newimm
== (unsigned int) FAIL
18596 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
18598 /* No ? OK - try using two ADD instructions to generate
18600 newimm
= validate_immediate_twopart (value
, & highpart
);
18602 /* Yes - then make sure that the second instruction is
18604 if (newimm
!= (unsigned int) FAIL
)
18606 /* Still No ? Try using a negated value. */
18607 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
18608 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
18609 /* Otherwise - give up. */
18612 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18613 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
18618 /* Replace the first operand in the 2nd instruction (which
18619 is the PC) with the destination register. We have
18620 already added in the PC in the first instruction and we
18621 do not want to do it again. */
18622 newinsn
&= ~ 0xf0000;
18623 newinsn
|= ((newinsn
& 0x0f000) << 4);
18626 newimm
|= (temp
& 0xfffff000);
18627 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
18629 highpart
|= (newinsn
& 0xfffff000);
18630 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
18634 case BFD_RELOC_ARM_OFFSET_IMM
:
18635 if (!fixP
->fx_done
&& seg
->use_rela_p
)
18638 case BFD_RELOC_ARM_LITERAL
:
18644 if (validate_offset_imm (value
, 0) == FAIL
)
18646 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
18647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18648 _("invalid literal constant: pool needs to be closer"));
18650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18651 _("bad immediate value for offset (%ld)"),
18656 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18657 newval
&= 0xff7ff000;
18658 newval
|= value
| (sign
? INDEX_UP
: 0);
18659 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18662 case BFD_RELOC_ARM_OFFSET_IMM8
:
18663 case BFD_RELOC_ARM_HWLITERAL
:
18669 if (validate_offset_imm (value
, 1) == FAIL
)
18671 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
18672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18673 _("invalid literal constant: pool needs to be closer"));
18675 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
18680 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18681 newval
&= 0xff7ff0f0;
18682 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
18683 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18686 case BFD_RELOC_ARM_T32_OFFSET_U8
:
18687 if (value
< 0 || value
> 1020 || value
% 4 != 0)
18688 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18689 _("bad immediate value for offset (%ld)"), (long) value
);
18692 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
18694 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
18697 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
18698 /* This is a complicated relocation used for all varieties of Thumb32
18699 load/store instruction with immediate offset:
18701 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
18702 *4, optional writeback(W)
18703 (doubleword load/store)
18705 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
18706 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
18707 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
18708 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
18709 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
18711 Uppercase letters indicate bits that are already encoded at
18712 this point. Lowercase letters are our problem. For the
18713 second block of instructions, the secondary opcode nybble
18714 (bits 8..11) is present, and bit 23 is zero, even if this is
18715 a PC-relative operation. */
18716 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18718 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
18720 if ((newval
& 0xf0000000) == 0xe0000000)
18722 /* Doubleword load/store: 8-bit offset, scaled by 4. */
18724 newval
|= (1 << 23);
18727 if (value
% 4 != 0)
18729 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18730 _("offset not a multiple of 4"));
18736 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18737 _("offset out of range"));
18742 else if ((newval
& 0x000f0000) == 0x000f0000)
18744 /* PC-relative, 12-bit offset. */
18746 newval
|= (1 << 23);
18751 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18752 _("offset out of range"));
18757 else if ((newval
& 0x00000100) == 0x00000100)
18759 /* Writeback: 8-bit, +/- offset. */
18761 newval
|= (1 << 9);
18766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18767 _("offset out of range"));
18772 else if ((newval
& 0x00000f00) == 0x00000e00)
18774 /* T-instruction: positive 8-bit offset. */
18775 if (value
< 0 || value
> 0xff)
18777 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18778 _("offset out of range"));
18786 /* Positive 12-bit or negative 8-bit offset. */
18790 newval
|= (1 << 23);
18800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18801 _("offset out of range"));
18808 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
18809 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
18812 case BFD_RELOC_ARM_SHIFT_IMM
:
18813 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18814 if (((unsigned long) value
) > 32
18816 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
18818 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18819 _("shift expression is too large"));
18824 /* Shifts of zero must be done as lsl. */
18826 else if (value
== 32)
18828 newval
&= 0xfffff07f;
18829 newval
|= (value
& 0x1f) << 7;
18830 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18833 case BFD_RELOC_ARM_T32_IMMEDIATE
:
18834 case BFD_RELOC_ARM_T32_ADD_IMM
:
18835 case BFD_RELOC_ARM_T32_IMM12
:
18836 case BFD_RELOC_ARM_T32_ADD_PC12
:
18837 /* We claim that this fixup has been processed here,
18838 even if in fact we generate an error because we do
18839 not have a reloc for it, so tc_gen_reloc will reject it. */
18843 && ! S_IS_DEFINED (fixP
->fx_addsy
))
18845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18846 _("undefined symbol %s used as an immediate value"),
18847 S_GET_NAME (fixP
->fx_addsy
));
18851 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18853 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
18856 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
18857 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18859 newimm
= encode_thumb32_immediate (value
);
18860 if (newimm
== (unsigned int) FAIL
)
18861 newimm
= thumb32_negate_data_op (&newval
, value
);
18863 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
18864 && newimm
== (unsigned int) FAIL
)
18866 /* Turn add/sum into addw/subw. */
18867 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
18868 newval
= (newval
& 0xfeffffff) | 0x02000000;
18870 /* 12 bit immediate for addw/subw. */
18874 newval
^= 0x00a00000;
18877 newimm
= (unsigned int) FAIL
;
18882 if (newimm
== (unsigned int)FAIL
)
18884 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18885 _("invalid constant (%lx) after fixup"),
18886 (unsigned long) value
);
18890 newval
|= (newimm
& 0x800) << 15;
18891 newval
|= (newimm
& 0x700) << 4;
18892 newval
|= (newimm
& 0x0ff);
18894 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
18895 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
18898 case BFD_RELOC_ARM_SMC
:
18899 if (((unsigned long) value
) > 0xffff)
18900 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18901 _("invalid smc expression"));
18902 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18903 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
18904 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18907 case BFD_RELOC_ARM_SWI
:
18908 if (fixP
->tc_fix_data
!= 0)
18910 if (((unsigned long) value
) > 0xff)
18911 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18912 _("invalid swi expression"));
18913 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18915 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
18919 if (((unsigned long) value
) > 0x00ffffff)
18920 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18921 _("invalid swi expression"));
18922 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18924 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18928 case BFD_RELOC_ARM_MULTI
:
18929 if (((unsigned long) value
) > 0xffff)
18930 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18931 _("invalid expression in load/store multiple"));
18932 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
18933 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18937 case BFD_RELOC_ARM_PCREL_CALL
:
18938 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18939 if ((newval
& 0xf0000000) == 0xf0000000)
18943 goto arm_branch_common
;
18945 case BFD_RELOC_ARM_PCREL_JUMP
:
18946 case BFD_RELOC_ARM_PLT32
:
18948 case BFD_RELOC_ARM_PCREL_BRANCH
:
18950 goto arm_branch_common
;
18952 case BFD_RELOC_ARM_PCREL_BLX
:
18955 /* We are going to store value (shifted right by two) in the
18956 instruction, in a 24 bit, signed field. Bits 26 through 32 either
18957 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
18958 also be be clear. */
18960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18961 _("misaligned branch destination"));
18962 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
18963 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
18964 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
18965 _("branch out of range"));
18967 if (fixP
->fx_done
|| !seg
->use_rela_p
)
18969 newval
= md_chars_to_number (buf
, INSN_SIZE
);
18970 newval
|= (value
>> 2) & 0x00ffffff;
18971 /* Set the H bit on BLX instructions. */
18975 newval
|= 0x01000000;
18977 newval
&= ~0x01000000;
18979 md_number_to_chars (buf
, newval
, INSN_SIZE
);
18983 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
18984 /* CBZ can only branch forward. */
18986 /* Attempts to use CBZ to branch to the next instruction
18987 (which, strictly speaking, are prohibited) will be turned into
18990 FIXME: It may be better to remove the instruction completely and
18991 perform relaxation. */
18994 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
18995 newval
= 0xbf00; /* NOP encoding T1 */
18996 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19001 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19002 _("branch out of range"));
19004 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19006 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19007 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
19008 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19013 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
19014 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
19015 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19016 _("branch out of range"));
19018 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19020 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19021 newval
|= (value
& 0x1ff) >> 1;
19022 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19026 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
19027 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
19028 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19029 _("branch out of range"));
19031 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19033 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19034 newval
|= (value
& 0xfff) >> 1;
19035 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19039 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19040 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
19041 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19042 _("conditional branch out of range"));
19044 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19047 addressT S
, J1
, J2
, lo
, hi
;
19049 S
= (value
& 0x00100000) >> 20;
19050 J2
= (value
& 0x00080000) >> 19;
19051 J1
= (value
& 0x00040000) >> 18;
19052 hi
= (value
& 0x0003f000) >> 12;
19053 lo
= (value
& 0x00000ffe) >> 1;
19055 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19056 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19057 newval
|= (S
<< 10) | hi
;
19058 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
19059 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19060 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19064 case BFD_RELOC_THUMB_PCREL_BLX
:
19065 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19066 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
19067 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19068 _("branch out of range"));
19070 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
19071 /* For a BLX instruction, make sure that the relocation is rounded up
19072 to a word boundary. This follows the semantics of the instruction
19073 which specifies that bit 1 of the target address will come from bit
19074 1 of the base address. */
19075 value
= (value
+ 1) & ~ 1;
19077 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19081 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19082 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19083 newval
|= (value
& 0x7fffff) >> 12;
19084 newval2
|= (value
& 0xfff) >> 1;
19085 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19086 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19090 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19091 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
19092 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19093 _("branch out of range"));
19095 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19098 addressT S
, I1
, I2
, lo
, hi
;
19100 S
= (value
& 0x01000000) >> 24;
19101 I1
= (value
& 0x00800000) >> 23;
19102 I2
= (value
& 0x00400000) >> 22;
19103 hi
= (value
& 0x003ff000) >> 12;
19104 lo
= (value
& 0x00000ffe) >> 1;
19109 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19110 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
19111 newval
|= (S
<< 10) | hi
;
19112 newval2
|= (I1
<< 13) | (I2
<< 11) | lo
;
19113 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19114 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
19119 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19120 md_number_to_chars (buf
, value
, 1);
19124 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19125 md_number_to_chars (buf
, value
, 2);
19129 case BFD_RELOC_ARM_TLS_GD32
:
19130 case BFD_RELOC_ARM_TLS_LE32
:
19131 case BFD_RELOC_ARM_TLS_IE32
:
19132 case BFD_RELOC_ARM_TLS_LDM32
:
19133 case BFD_RELOC_ARM_TLS_LDO32
:
19134 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
19137 case BFD_RELOC_ARM_GOT32
:
19138 case BFD_RELOC_ARM_GOTOFF
:
19139 case BFD_RELOC_ARM_TARGET2
:
19140 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19141 md_number_to_chars (buf
, 0, 4);
19145 case BFD_RELOC_RVA
:
19147 case BFD_RELOC_ARM_TARGET1
:
19148 case BFD_RELOC_ARM_ROSEGREL32
:
19149 case BFD_RELOC_ARM_SBREL32
:
19150 case BFD_RELOC_32_PCREL
:
19152 case BFD_RELOC_32_SECREL
:
19154 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19156 /* For WinCE we only do this for pcrel fixups. */
19157 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
19159 md_number_to_chars (buf
, value
, 4);
19163 case BFD_RELOC_ARM_PREL31
:
19164 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19166 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
19167 if ((value
^ (value
>> 1)) & 0x40000000)
19169 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19170 _("rel31 relocation overflow"));
19172 newval
|= value
& 0x7fffffff;
19173 md_number_to_chars (buf
, newval
, 4);
19178 case BFD_RELOC_ARM_CP_OFF_IMM
:
19179 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
19180 if (value
< -1023 || value
> 1023 || (value
& 3))
19181 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19182 _("co-processor offset out of range"));
19187 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
19188 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
19189 newval
= md_chars_to_number (buf
, INSN_SIZE
);
19191 newval
= get_thumb32_insn (buf
);
19192 newval
&= 0xff7fff00;
19193 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
19194 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
19195 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
19196 md_number_to_chars (buf
, newval
, INSN_SIZE
);
19198 put_thumb32_insn (buf
, newval
);
19201 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
19202 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
19203 if (value
< -255 || value
> 255)
19204 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19205 _("co-processor offset out of range"));
19207 goto cp_off_common
;
19209 case BFD_RELOC_ARM_THUMB_OFFSET
:
19210 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19211 /* Exactly what ranges, and where the offset is inserted depends
19212 on the type of instruction, we can establish this from the
19214 switch (newval
>> 12)
19216 case 4: /* PC load. */
19217 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
19218 forced to zero for these loads; md_pcrel_from has already
19219 compensated for this. */
19221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19222 _("invalid offset, target not word aligned (0x%08lX)"),
19223 (((unsigned long) fixP
->fx_frag
->fr_address
19224 + (unsigned long) fixP
->fx_where
) & ~3)
19225 + (unsigned long) value
);
19227 if (value
& ~0x3fc)
19228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19229 _("invalid offset, value too big (0x%08lX)"),
19232 newval
|= value
>> 2;
19235 case 9: /* SP load/store. */
19236 if (value
& ~0x3fc)
19237 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19238 _("invalid offset, value too big (0x%08lX)"),
19240 newval
|= value
>> 2;
19243 case 6: /* Word load/store. */
19245 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19246 _("invalid offset, value too big (0x%08lX)"),
19248 newval
|= value
<< 4; /* 6 - 2. */
19251 case 7: /* Byte load/store. */
19253 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19254 _("invalid offset, value too big (0x%08lX)"),
19256 newval
|= value
<< 6;
19259 case 8: /* Halfword load/store. */
19261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19262 _("invalid offset, value too big (0x%08lX)"),
19264 newval
|= value
<< 5; /* 6 - 1. */
19268 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19269 "Unable to process relocation for thumb opcode: %lx",
19270 (unsigned long) newval
);
19273 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19276 case BFD_RELOC_ARM_THUMB_ADD
:
19277 /* This is a complicated relocation, since we use it for all of
19278 the following immediate relocations:
19282 9bit ADD/SUB SP word-aligned
19283 10bit ADD PC/SP word-aligned
19285 The type of instruction being processed is encoded in the
19292 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19294 int rd
= (newval
>> 4) & 0xf;
19295 int rs
= newval
& 0xf;
19296 int subtract
= !!(newval
& 0x8000);
19298 /* Check for HI regs, only very restricted cases allowed:
19299 Adjusting SP, and using PC or SP to get an address. */
19300 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
19301 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
19302 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19303 _("invalid Hi register with immediate"));
19305 /* If value is negative, choose the opposite instruction. */
19309 subtract
= !subtract
;
19311 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19312 _("immediate value out of range"));
19317 if (value
& ~0x1fc)
19318 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19319 _("invalid immediate for stack address calculation"));
19320 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
19321 newval
|= value
>> 2;
19323 else if (rs
== REG_PC
|| rs
== REG_SP
)
19325 if (subtract
|| value
& ~0x3fc)
19326 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19327 _("invalid immediate for address calculation (value = 0x%08lX)"),
19328 (unsigned long) value
);
19329 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
19331 newval
|= value
>> 2;
19336 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19337 _("immediate value out of range"));
19338 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
19339 newval
|= (rd
<< 8) | value
;
19344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19345 _("immediate value out of range"));
19346 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
19347 newval
|= rd
| (rs
<< 3) | (value
<< 6);
19350 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19353 case BFD_RELOC_ARM_THUMB_IMM
:
19354 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
19355 if (value
< 0 || value
> 255)
19356 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19357 _("invalid immediate: %ld is out of range"),
19360 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19363 case BFD_RELOC_ARM_THUMB_SHIFT
:
19364 /* 5bit shift value (0..32). LSL cannot take 32. */
19365 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
19366 temp
= newval
& 0xf800;
19367 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
19368 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19369 _("invalid shift value: %ld"), (long) value
);
19370 /* Shifts of zero must be encoded as LSL. */
19372 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
19373 /* Shifts of 32 are encoded as zero. */
19374 else if (value
== 32)
19376 newval
|= value
<< 6;
19377 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
19380 case BFD_RELOC_VTABLE_INHERIT
:
19381 case BFD_RELOC_VTABLE_ENTRY
:
19385 case BFD_RELOC_ARM_MOVW
:
19386 case BFD_RELOC_ARM_MOVT
:
19387 case BFD_RELOC_ARM_THUMB_MOVW
:
19388 case BFD_RELOC_ARM_THUMB_MOVT
:
19389 if (fixP
->fx_done
|| !seg
->use_rela_p
)
19391 /* REL format relocations are limited to a 16-bit addend. */
19392 if (!fixP
->fx_done
)
19394 if (value
< -0x8000 || value
> 0x7fff)
19395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19396 _("offset out of range"));
19398 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
19399 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
19404 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
19405 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
19407 newval
= get_thumb32_insn (buf
);
19408 newval
&= 0xfbf08f00;
19409 newval
|= (value
& 0xf000) << 4;
19410 newval
|= (value
& 0x0800) << 15;
19411 newval
|= (value
& 0x0700) << 4;
19412 newval
|= (value
& 0x00ff);
19413 put_thumb32_insn (buf
, newval
);
19417 newval
= md_chars_to_number (buf
, 4);
19418 newval
&= 0xfff0f000;
19419 newval
|= value
& 0x0fff;
19420 newval
|= (value
& 0xf000) << 4;
19421 md_number_to_chars (buf
, newval
, 4);
19426 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19427 case BFD_RELOC_ARM_ALU_PC_G0
:
19428 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19429 case BFD_RELOC_ARM_ALU_PC_G1
:
19430 case BFD_RELOC_ARM_ALU_PC_G2
:
19431 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19432 case BFD_RELOC_ARM_ALU_SB_G0
:
19433 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19434 case BFD_RELOC_ARM_ALU_SB_G1
:
19435 case BFD_RELOC_ARM_ALU_SB_G2
:
19436 assert (!fixP
->fx_done
);
19437 if (!seg
->use_rela_p
)
19440 bfd_vma encoded_addend
;
19441 bfd_vma addend_abs
= abs (value
);
19443 /* Check that the absolute value of the addend can be
19444 expressed as an 8-bit constant plus a rotation. */
19445 encoded_addend
= encode_arm_immediate (addend_abs
);
19446 if (encoded_addend
== (unsigned int) FAIL
)
19447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19448 _("the offset 0x%08lX is not representable"),
19449 (unsigned long) addend_abs
);
19451 /* Extract the instruction. */
19452 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19454 /* If the addend is positive, use an ADD instruction.
19455 Otherwise use a SUB. Take care not to destroy the S bit. */
19456 insn
&= 0xff1fffff;
19462 /* Place the encoded addend into the first 12 bits of the
19464 insn
&= 0xfffff000;
19465 insn
|= encoded_addend
;
19467 /* Update the instruction. */
19468 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19472 case BFD_RELOC_ARM_LDR_PC_G0
:
19473 case BFD_RELOC_ARM_LDR_PC_G1
:
19474 case BFD_RELOC_ARM_LDR_PC_G2
:
19475 case BFD_RELOC_ARM_LDR_SB_G0
:
19476 case BFD_RELOC_ARM_LDR_SB_G1
:
19477 case BFD_RELOC_ARM_LDR_SB_G2
:
19478 assert (!fixP
->fx_done
);
19479 if (!seg
->use_rela_p
)
19482 bfd_vma addend_abs
= abs (value
);
19484 /* Check that the absolute value of the addend can be
19485 encoded in 12 bits. */
19486 if (addend_abs
>= 0x1000)
19487 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19488 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
19489 (unsigned long) addend_abs
);
19491 /* Extract the instruction. */
19492 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19494 /* If the addend is negative, clear bit 23 of the instruction.
19495 Otherwise set it. */
19497 insn
&= ~(1 << 23);
19501 /* Place the absolute value of the addend into the first 12 bits
19502 of the instruction. */
19503 insn
&= 0xfffff000;
19504 insn
|= addend_abs
;
19506 /* Update the instruction. */
19507 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19511 case BFD_RELOC_ARM_LDRS_PC_G0
:
19512 case BFD_RELOC_ARM_LDRS_PC_G1
:
19513 case BFD_RELOC_ARM_LDRS_PC_G2
:
19514 case BFD_RELOC_ARM_LDRS_SB_G0
:
19515 case BFD_RELOC_ARM_LDRS_SB_G1
:
19516 case BFD_RELOC_ARM_LDRS_SB_G2
:
19517 assert (!fixP
->fx_done
);
19518 if (!seg
->use_rela_p
)
19521 bfd_vma addend_abs
= abs (value
);
19523 /* Check that the absolute value of the addend can be
19524 encoded in 8 bits. */
19525 if (addend_abs
>= 0x100)
19526 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19527 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
19528 (unsigned long) addend_abs
);
19530 /* Extract the instruction. */
19531 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19533 /* If the addend is negative, clear bit 23 of the instruction.
19534 Otherwise set it. */
19536 insn
&= ~(1 << 23);
19540 /* Place the first four bits of the absolute value of the addend
19541 into the first 4 bits of the instruction, and the remaining
19542 four into bits 8 .. 11. */
19543 insn
&= 0xfffff0f0;
19544 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
19546 /* Update the instruction. */
19547 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19551 case BFD_RELOC_ARM_LDC_PC_G0
:
19552 case BFD_RELOC_ARM_LDC_PC_G1
:
19553 case BFD_RELOC_ARM_LDC_PC_G2
:
19554 case BFD_RELOC_ARM_LDC_SB_G0
:
19555 case BFD_RELOC_ARM_LDC_SB_G1
:
19556 case BFD_RELOC_ARM_LDC_SB_G2
:
19557 assert (!fixP
->fx_done
);
19558 if (!seg
->use_rela_p
)
19561 bfd_vma addend_abs
= abs (value
);
19563 /* Check that the absolute value of the addend is a multiple of
19564 four and, when divided by four, fits in 8 bits. */
19565 if (addend_abs
& 0x3)
19566 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19567 _("bad offset 0x%08lX (must be word-aligned)"),
19568 (unsigned long) addend_abs
);
19570 if ((addend_abs
>> 2) > 0xff)
19571 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19572 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
19573 (unsigned long) addend_abs
);
19575 /* Extract the instruction. */
19576 insn
= md_chars_to_number (buf
, INSN_SIZE
);
19578 /* If the addend is negative, clear bit 23 of the instruction.
19579 Otherwise set it. */
19581 insn
&= ~(1 << 23);
19585 /* Place the addend (divided by four) into the first eight
19586 bits of the instruction. */
19587 insn
&= 0xfffffff0;
19588 insn
|= addend_abs
>> 2;
19590 /* Update the instruction. */
19591 md_number_to_chars (buf
, insn
, INSN_SIZE
);
19595 case BFD_RELOC_ARM_V4BX
:
19596 /* This will need to go in the object file. */
19600 case BFD_RELOC_UNUSED
:
19602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
19603 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
19607 /* Translate internal representation of relocation info to BFD target
19611 tc_gen_reloc (asection
*section
, fixS
*fixp
)
19614 bfd_reloc_code_real_type code
;
19616 reloc
= xmalloc (sizeof (arelent
));
19618 reloc
->sym_ptr_ptr
= xmalloc (sizeof (asymbol
*));
19619 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
19620 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
19622 if (fixp
->fx_pcrel
)
19624 if (section
->use_rela_p
)
19625 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
19627 fixp
->fx_offset
= reloc
->address
;
19629 reloc
->addend
= fixp
->fx_offset
;
19631 switch (fixp
->fx_r_type
)
19634 if (fixp
->fx_pcrel
)
19636 code
= BFD_RELOC_8_PCREL
;
19641 if (fixp
->fx_pcrel
)
19643 code
= BFD_RELOC_16_PCREL
;
19648 if (fixp
->fx_pcrel
)
19650 code
= BFD_RELOC_32_PCREL
;
19654 case BFD_RELOC_ARM_MOVW
:
19655 if (fixp
->fx_pcrel
)
19657 code
= BFD_RELOC_ARM_MOVW_PCREL
;
19661 case BFD_RELOC_ARM_MOVT
:
19662 if (fixp
->fx_pcrel
)
19664 code
= BFD_RELOC_ARM_MOVT_PCREL
;
19668 case BFD_RELOC_ARM_THUMB_MOVW
:
19669 if (fixp
->fx_pcrel
)
19671 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
19675 case BFD_RELOC_ARM_THUMB_MOVT
:
19676 if (fixp
->fx_pcrel
)
19678 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
19682 case BFD_RELOC_NONE
:
19683 case BFD_RELOC_ARM_PCREL_BRANCH
:
19684 case BFD_RELOC_ARM_PCREL_BLX
:
19685 case BFD_RELOC_RVA
:
19686 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
19687 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
19688 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
19689 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
19690 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
19691 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
19692 case BFD_RELOC_THUMB_PCREL_BLX
:
19693 case BFD_RELOC_VTABLE_ENTRY
:
19694 case BFD_RELOC_VTABLE_INHERIT
:
19696 case BFD_RELOC_32_SECREL
:
19698 code
= fixp
->fx_r_type
;
19701 case BFD_RELOC_ARM_LITERAL
:
19702 case BFD_RELOC_ARM_HWLITERAL
:
19703 /* If this is called then the a literal has
19704 been referenced across a section boundary. */
19705 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19706 _("literal referenced across section boundary"));
19710 case BFD_RELOC_ARM_GOT32
:
19711 case BFD_RELOC_ARM_GOTOFF
:
19712 case BFD_RELOC_ARM_PLT32
:
19713 case BFD_RELOC_ARM_TARGET1
:
19714 case BFD_RELOC_ARM_ROSEGREL32
:
19715 case BFD_RELOC_ARM_SBREL32
:
19716 case BFD_RELOC_ARM_PREL31
:
19717 case BFD_RELOC_ARM_TARGET2
:
19718 case BFD_RELOC_ARM_TLS_LE32
:
19719 case BFD_RELOC_ARM_TLS_LDO32
:
19720 case BFD_RELOC_ARM_PCREL_CALL
:
19721 case BFD_RELOC_ARM_PCREL_JUMP
:
19722 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
19723 case BFD_RELOC_ARM_ALU_PC_G0
:
19724 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
19725 case BFD_RELOC_ARM_ALU_PC_G1
:
19726 case BFD_RELOC_ARM_ALU_PC_G2
:
19727 case BFD_RELOC_ARM_LDR_PC_G0
:
19728 case BFD_RELOC_ARM_LDR_PC_G1
:
19729 case BFD_RELOC_ARM_LDR_PC_G2
:
19730 case BFD_RELOC_ARM_LDRS_PC_G0
:
19731 case BFD_RELOC_ARM_LDRS_PC_G1
:
19732 case BFD_RELOC_ARM_LDRS_PC_G2
:
19733 case BFD_RELOC_ARM_LDC_PC_G0
:
19734 case BFD_RELOC_ARM_LDC_PC_G1
:
19735 case BFD_RELOC_ARM_LDC_PC_G2
:
19736 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
19737 case BFD_RELOC_ARM_ALU_SB_G0
:
19738 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
19739 case BFD_RELOC_ARM_ALU_SB_G1
:
19740 case BFD_RELOC_ARM_ALU_SB_G2
:
19741 case BFD_RELOC_ARM_LDR_SB_G0
:
19742 case BFD_RELOC_ARM_LDR_SB_G1
:
19743 case BFD_RELOC_ARM_LDR_SB_G2
:
19744 case BFD_RELOC_ARM_LDRS_SB_G0
:
19745 case BFD_RELOC_ARM_LDRS_SB_G1
:
19746 case BFD_RELOC_ARM_LDRS_SB_G2
:
19747 case BFD_RELOC_ARM_LDC_SB_G0
:
19748 case BFD_RELOC_ARM_LDC_SB_G1
:
19749 case BFD_RELOC_ARM_LDC_SB_G2
:
19750 case BFD_RELOC_ARM_V4BX
:
19751 code
= fixp
->fx_r_type
;
19754 case BFD_RELOC_ARM_TLS_GD32
:
19755 case BFD_RELOC_ARM_TLS_IE32
:
19756 case BFD_RELOC_ARM_TLS_LDM32
:
19757 /* BFD will include the symbol's address in the addend.
19758 But we don't want that, so subtract it out again here. */
19759 if (!S_IS_COMMON (fixp
->fx_addsy
))
19760 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
19761 code
= fixp
->fx_r_type
;
19765 case BFD_RELOC_ARM_IMMEDIATE
:
19766 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19767 _("internal relocation (type: IMMEDIATE) not fixed up"));
19770 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
19771 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19772 _("ADRL used for a symbol not defined in the same file"));
19775 case BFD_RELOC_ARM_OFFSET_IMM
:
19776 if (section
->use_rela_p
)
19778 code
= fixp
->fx_r_type
;
19782 if (fixp
->fx_addsy
!= NULL
19783 && !S_IS_DEFINED (fixp
->fx_addsy
)
19784 && S_IS_LOCAL (fixp
->fx_addsy
))
19786 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19787 _("undefined local label `%s'"),
19788 S_GET_NAME (fixp
->fx_addsy
));
19792 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19793 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
19800 switch (fixp
->fx_r_type
)
19802 case BFD_RELOC_NONE
: type
= "NONE"; break;
19803 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
19804 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
19805 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
19806 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
19807 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
19808 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
19809 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
19810 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
19811 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
19812 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
19813 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
19814 default: type
= _("<unknown>"); break;
19816 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19817 _("cannot represent %s relocation in this object file format"),
19824 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
19826 && fixp
->fx_addsy
== GOT_symbol
)
19828 code
= BFD_RELOC_ARM_GOTPC
;
19829 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
19833 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
19835 if (reloc
->howto
== NULL
)
19837 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
19838 _("cannot represent %s relocation in this object file format"),
19839 bfd_get_reloc_code_name (code
));
19843 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
19844 vtable entry to be used in the relocation's section offset. */
19845 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19846 reloc
->address
= fixp
->fx_offset
;
19851 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
19854 cons_fix_new_arm (fragS
* frag
,
19859 bfd_reloc_code_real_type type
;
19863 FIXME: @@ Should look at CPU word size. */
19867 type
= BFD_RELOC_8
;
19870 type
= BFD_RELOC_16
;
19874 type
= BFD_RELOC_32
;
19877 type
= BFD_RELOC_64
;
19882 if (exp
->X_op
== O_secrel
)
19884 exp
->X_op
= O_symbol
;
19885 type
= BFD_RELOC_32_SECREL
;
19889 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
19892 #if defined OBJ_COFF || defined OBJ_ELF
19894 arm_validate_fix (fixS
* fixP
)
19896 /* If the destination of the branch is a defined symbol which does not have
19897 the THUMB_FUNC attribute, then we must be calling a function which has
19898 the (interfacearm) attribute. We look for the Thumb entry point to that
19899 function and change the branch to refer to that function instead. */
19900 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
19901 && fixP
->fx_addsy
!= NULL
19902 && S_IS_DEFINED (fixP
->fx_addsy
)
19903 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
19905 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
19911 arm_force_relocation (struct fix
* fixp
)
19913 #if defined (OBJ_COFF) && defined (TE_PE)
19914 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
19918 /* Resolve these relocations even if the symbol is extern or weak. */
19919 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
19920 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
19921 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
19922 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
19923 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
19924 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
19925 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
)
19928 /* Always leave these relocations for the linker. */
19929 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19930 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19931 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19934 /* Always generate relocations against function symbols. */
19935 if (fixp
->fx_r_type
== BFD_RELOC_32
19937 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
19940 return generic_force_reloc (fixp
);
19943 #if defined (OBJ_ELF) || defined (OBJ_COFF)
19944 /* Relocations against function names must be left unadjusted,
19945 so that the linker can use this information to generate interworking
19946 stubs. The MIPS version of this function
19947 also prevents relocations that are mips-16 specific, but I do not
19948 know why it does this.
19951 There is one other problem that ought to be addressed here, but
19952 which currently is not: Taking the address of a label (rather
19953 than a function) and then later jumping to that address. Such
19954 addresses also ought to have their bottom bit set (assuming that
19955 they reside in Thumb code), but at the moment they will not. */
19958 arm_fix_adjustable (fixS
* fixP
)
19960 if (fixP
->fx_addsy
== NULL
)
19963 /* Preserve relocations against symbols with function type. */
19964 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
19967 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
19968 && fixP
->fx_subsy
== NULL
)
19971 /* We need the symbol name for the VTABLE entries. */
19972 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
19973 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
19976 /* Don't allow symbols to be discarded on GOT related relocs. */
19977 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
19978 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
19979 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
19980 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
19981 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
19982 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
19983 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
19984 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
19985 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
19988 /* Similarly for group relocations. */
19989 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
19990 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
19991 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
19994 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
19995 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
19996 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
19997 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
19998 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
19999 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
20000 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
20001 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
20002 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
20007 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
20012 elf32_arm_target_format (void)
20015 return (target_big_endian
20016 ? "elf32-bigarm-symbian"
20017 : "elf32-littlearm-symbian");
20018 #elif defined (TE_VXWORKS)
20019 return (target_big_endian
20020 ? "elf32-bigarm-vxworks"
20021 : "elf32-littlearm-vxworks");
20023 if (target_big_endian
)
20024 return "elf32-bigarm";
20026 return "elf32-littlearm";
20031 armelf_frob_symbol (symbolS
* symp
,
20034 elf_frob_symbol (symp
, puntp
);
20038 /* MD interface: Finalization. */
20040 /* A good place to do this, although this was probably not intended
20041 for this kind of use. We need to dump the literal pool before
20042 references are made to a null symbol pointer. */
20047 literal_pool
* pool
;
20049 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
20051 /* Put it at the end of the relevant section. */
20052 subseg_set (pool
->section
, pool
->sub_section
);
20054 arm_elf_change_section ();
20060 /* Adjust the symbol table. This marks Thumb symbols as distinct from
20064 arm_adjust_symtab (void)
20069 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
20071 if (ARM_IS_THUMB (sym
))
20073 if (THUMB_IS_FUNC (sym
))
20075 /* Mark the symbol as a Thumb function. */
20076 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
20077 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
20078 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
20080 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
20081 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
20083 as_bad (_("%s: unexpected function type: %d"),
20084 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
20086 else switch (S_GET_STORAGE_CLASS (sym
))
20089 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
20092 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
20095 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
20103 if (ARM_IS_INTERWORK (sym
))
20104 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
20111 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
20113 if (ARM_IS_THUMB (sym
))
20115 elf_symbol_type
* elf_sym
;
20117 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
20118 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
20120 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
20121 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
20123 /* If it's a .thumb_func, declare it as so,
20124 otherwise tag label as .code 16. */
20125 if (THUMB_IS_FUNC (sym
))
20126 elf_sym
->internal_elf_sym
.st_info
=
20127 ELF_ST_INFO (bind
, STT_ARM_TFUNC
);
20128 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
20129 elf_sym
->internal_elf_sym
.st_info
=
20130 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
20137 /* MD interface: Initialization. */
20140 set_constant_flonums (void)
20144 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
20145 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
20149 /* Auto-select Thumb mode if it's the only available instruction set for the
20150 given architecture. */
20153 autoselect_thumb_from_cpu_variant (void)
20155 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
20156 opcode_select (16);
20165 if ( (arm_ops_hsh
= hash_new ()) == NULL
20166 || (arm_cond_hsh
= hash_new ()) == NULL
20167 || (arm_shift_hsh
= hash_new ()) == NULL
20168 || (arm_psr_hsh
= hash_new ()) == NULL
20169 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
20170 || (arm_reg_hsh
= hash_new ()) == NULL
20171 || (arm_reloc_hsh
= hash_new ()) == NULL
20172 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
20173 as_fatal (_("virtual memory exhausted"));
20175 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
20176 hash_insert (arm_ops_hsh
, insns
[i
].template, (void *) (insns
+ i
));
20177 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
20178 hash_insert (arm_cond_hsh
, conds
[i
].template, (void *) (conds
+ i
));
20179 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
20180 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
20181 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
20182 hash_insert (arm_psr_hsh
, psrs
[i
].template, (void *) (psrs
+ i
));
20183 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
20184 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template, (void *) (v7m_psrs
+ i
));
20185 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
20186 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
20188 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
20190 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template,
20191 (void *) (barrier_opt_names
+ i
));
20193 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
20194 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
20197 set_constant_flonums ();
20199 /* Set the cpu variant based on the command-line options. We prefer
20200 -mcpu= over -march= if both are set (as for GCC); and we prefer
20201 -mfpu= over any other way of setting the floating point unit.
20202 Use of legacy options with new options are faulted. */
20205 if (mcpu_cpu_opt
|| march_cpu_opt
)
20206 as_bad (_("use of old and new-style options to set CPU type"));
20208 mcpu_cpu_opt
= legacy_cpu
;
20210 else if (!mcpu_cpu_opt
)
20211 mcpu_cpu_opt
= march_cpu_opt
;
20216 as_bad (_("use of old and new-style options to set FPU type"));
20218 mfpu_opt
= legacy_fpu
;
20220 else if (!mfpu_opt
)
20222 #if !(defined (TE_LINUX) || defined (TE_NetBSD) || defined (TE_VXWORKS))
20223 /* Some environments specify a default FPU. If they don't, infer it
20224 from the processor. */
20226 mfpu_opt
= mcpu_fpu_opt
;
20228 mfpu_opt
= march_fpu_opt
;
20230 mfpu_opt
= &fpu_default
;
20236 if (mcpu_cpu_opt
!= NULL
)
20237 mfpu_opt
= &fpu_default
;
20238 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
20239 mfpu_opt
= &fpu_arch_vfp_v2
;
20241 mfpu_opt
= &fpu_arch_fpa
;
20247 mcpu_cpu_opt
= &cpu_default
;
20248 selected_cpu
= cpu_default
;
20252 selected_cpu
= *mcpu_cpu_opt
;
20254 mcpu_cpu_opt
= &arm_arch_any
;
20257 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
20259 autoselect_thumb_from_cpu_variant ();
20261 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
20263 #if defined OBJ_COFF || defined OBJ_ELF
20265 unsigned int flags
= 0;
20267 #if defined OBJ_ELF
20268 flags
= meabi_flags
;
20270 switch (meabi_flags
)
20272 case EF_ARM_EABI_UNKNOWN
:
20274 /* Set the flags in the private structure. */
20275 if (uses_apcs_26
) flags
|= F_APCS26
;
20276 if (support_interwork
) flags
|= F_INTERWORK
;
20277 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
20278 if (pic_code
) flags
|= F_PIC
;
20279 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
20280 flags
|= F_SOFT_FLOAT
;
20282 switch (mfloat_abi_opt
)
20284 case ARM_FLOAT_ABI_SOFT
:
20285 case ARM_FLOAT_ABI_SOFTFP
:
20286 flags
|= F_SOFT_FLOAT
;
20289 case ARM_FLOAT_ABI_HARD
:
20290 if (flags
& F_SOFT_FLOAT
)
20291 as_bad (_("hard-float conflicts with specified fpu"));
20295 /* Using pure-endian doubles (even if soft-float). */
20296 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
20297 flags
|= F_VFP_FLOAT
;
20299 #if defined OBJ_ELF
20300 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
20301 flags
|= EF_ARM_MAVERICK_FLOAT
;
20304 case EF_ARM_EABI_VER4
:
20305 case EF_ARM_EABI_VER5
:
20306 /* No additional flags to set. */
20313 bfd_set_private_flags (stdoutput
, flags
);
20315 /* We have run out flags in the COFF header to encode the
20316 status of ATPCS support, so instead we create a dummy,
20317 empty, debug section called .arm.atpcs. */
20322 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
20326 bfd_set_section_flags
20327 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
20328 bfd_set_section_size (stdoutput
, sec
, 0);
20329 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
20335 /* Record the CPU type as well. */
20336 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
20337 mach
= bfd_mach_arm_iWMMXt2
;
20338 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
20339 mach
= bfd_mach_arm_iWMMXt
;
20340 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
20341 mach
= bfd_mach_arm_XScale
;
20342 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
20343 mach
= bfd_mach_arm_ep9312
;
20344 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
20345 mach
= bfd_mach_arm_5TE
;
20346 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
20348 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
20349 mach
= bfd_mach_arm_5T
;
20351 mach
= bfd_mach_arm_5
;
20353 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
20355 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
20356 mach
= bfd_mach_arm_4T
;
20358 mach
= bfd_mach_arm_4
;
20360 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
20361 mach
= bfd_mach_arm_3M
;
20362 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
20363 mach
= bfd_mach_arm_3
;
20364 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
20365 mach
= bfd_mach_arm_2a
;
20366 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
20367 mach
= bfd_mach_arm_2
;
20369 mach
= bfd_mach_arm_unknown
;
20371 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
20374 /* Command line processing. */
20377 Invocation line includes a switch not recognized by the base assembler.
20378 See if it's a processor-specific option.
20380 This routine is somewhat complicated by the need for backwards
20381 compatibility (since older releases of gcc can't be changed).
20382 The new options try to make the interface as compatible as
20385 New options (supported) are:
20387 -mcpu=<cpu name> Assemble for selected processor
20388 -march=<architecture name> Assemble for selected architecture
20389 -mfpu=<fpu architecture> Assemble for selected FPU.
20390 -EB/-mbig-endian Big-endian
20391 -EL/-mlittle-endian Little-endian
20392 -k Generate PIC code
20393 -mthumb Start in Thumb mode
20394 -mthumb-interwork Code supports ARM/Thumb interworking
20396 -m[no-]warn-deprecated Warn about deprecated features
20398 For now we will also provide support for:
20400 -mapcs-32 32-bit Program counter
20401 -mapcs-26 26-bit Program counter
20402 -macps-float Floats passed in FP registers
20403 -mapcs-reentrant Reentrant code
20405 (sometime these will probably be replaced with -mapcs=<list of options>
20406 and -matpcs=<list of options>)
20408 The remaining options are only supported for back-wards compatibility.
20409 Cpu variants, the arm part is optional:
20410 -m[arm]1 Currently not supported.
20411 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
20412 -m[arm]3 Arm 3 processor
20413 -m[arm]6[xx], Arm 6 processors
20414 -m[arm]7[xx][t][[d]m] Arm 7 processors
20415 -m[arm]8[10] Arm 8 processors
20416 -m[arm]9[20][tdmi] Arm 9 processors
20417 -mstrongarm[110[0]] StrongARM processors
20418 -mxscale XScale processors
20419 -m[arm]v[2345[t[e]]] Arm architectures
20420 -mall All (except the ARM1)
20422 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
20423 -mfpe-old (No float load/store multiples)
20424 -mvfpxd VFP Single precision
20426 -mno-fpu Disable all floating point instructions
20428 The following CPU names are recognized:
20429 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
20430 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
20431 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
20432 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
20433 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
20434 arm10t arm10e, arm1020t, arm1020e, arm10200e,
20435 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
20439 const char * md_shortopts
= "m:k";
20441 #ifdef ARM_BI_ENDIAN
20442 #define OPTION_EB (OPTION_MD_BASE + 0)
20443 #define OPTION_EL (OPTION_MD_BASE + 1)
20445 #if TARGET_BYTES_BIG_ENDIAN
20446 #define OPTION_EB (OPTION_MD_BASE + 0)
20448 #define OPTION_EL (OPTION_MD_BASE + 1)
20451 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
20453 struct option md_longopts
[] =
20456 {"EB", no_argument
, NULL
, OPTION_EB
},
20459 {"EL", no_argument
, NULL
, OPTION_EL
},
20461 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
20462 {NULL
, no_argument
, NULL
, 0}
20465 size_t md_longopts_size
= sizeof (md_longopts
);
20467 struct arm_option_table
20469 char *option
; /* Option name to match. */
20470 char *help
; /* Help information. */
20471 int *var
; /* Variable to change. */
20472 int value
; /* What to change it to. */
20473 char *deprecated
; /* If non-null, print this message. */
20476 struct arm_option_table arm_opts
[] =
20478 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
20479 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
20480 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
20481 &support_interwork
, 1, NULL
},
20482 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
20483 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
20484 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
20486 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
20487 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
20488 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
20489 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
20492 /* These are recognized by the assembler, but have no affect on code. */
20493 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
20494 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
20496 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
20497 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
20498 &warn_on_deprecated
, 0, NULL
},
20499 {NULL
, NULL
, NULL
, 0, NULL
}
20502 struct arm_legacy_option_table
20504 char *option
; /* Option name to match. */
20505 const arm_feature_set
**var
; /* Variable to change. */
20506 const arm_feature_set value
; /* What to change it to. */
20507 char *deprecated
; /* If non-null, print this message. */
20510 const struct arm_legacy_option_table arm_legacy_opts
[] =
20512 /* DON'T add any new processors to this list -- we want the whole list
20513 to go away... Add them to the processors table instead. */
20514 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20515 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
20516 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20517 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
20518 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20519 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
20520 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20521 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
20522 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20523 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
20524 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20525 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
20526 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20527 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
20528 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20529 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
20530 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20531 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
20532 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20533 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
20534 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20535 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
20536 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20537 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
20538 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20539 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
20540 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20541 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
20542 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20543 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
20544 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20545 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
20546 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20547 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
20548 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20549 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
20550 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20551 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
20552 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20553 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
20554 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20555 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
20556 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20557 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
20558 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20559 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
20560 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20561 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20562 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20563 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
20564 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20565 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
20566 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20567 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
20568 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20569 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
20570 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20571 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
20572 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20573 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
20574 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20575 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
20576 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20577 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
20578 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20579 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
20580 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20581 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
20582 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
20583 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
20584 N_("use -mcpu=strongarm110")},
20585 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
20586 N_("use -mcpu=strongarm1100")},
20587 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
20588 N_("use -mcpu=strongarm1110")},
20589 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
20590 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
20591 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
20593 /* Architecture variants -- don't add any more to this list either. */
20594 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20595 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
20596 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20597 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
20598 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20599 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
20600 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20601 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
20602 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20603 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
20604 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20605 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
20606 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20607 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
20608 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20609 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
20610 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20611 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
20613 /* Floating point variants -- don't add any more to this list either. */
20614 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
20615 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
20616 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
20617 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
20618 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
20620 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
20623 struct arm_cpu_option_table
20626 const arm_feature_set value
;
20627 /* For some CPUs we assume an FPU unless the user explicitly sets
20629 const arm_feature_set default_fpu
;
20630 /* The canonical name of the CPU, or NULL to use NAME converted to upper
20632 const char *canonical_name
;
20635 /* This list should, at a minimum, contain all the cpu names
20636 recognized by GCC. */
20637 static const struct arm_cpu_option_table arm_cpus
[] =
20639 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
20640 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
20641 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
20642 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20643 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
20644 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20645 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20646 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20647 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20648 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20649 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20650 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20651 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20652 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20653 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20654 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
20655 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20656 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20657 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20658 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20659 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20660 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20661 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20662 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20663 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20664 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20665 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20666 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
20667 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20668 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20669 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20670 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20671 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20672 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20673 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20674 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20675 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20676 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20677 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20678 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
20679 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20680 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20681 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20682 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
20683 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20684 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
20685 /* For V5 or later processors we default to using VFP; but the user
20686 should really set the FPU type explicitly. */
20687 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20688 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20689 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20690 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
20691 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20692 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20693 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
20694 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20695 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
20696 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
20697 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20698 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20699 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20700 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20701 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20702 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
20703 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
20704 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20705 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20706 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
20707 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
20708 {"fa626te", ARM_ARCH_V5TE
, FPU_NONE
, NULL
},
20709 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
20710 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
20711 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
20712 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
20713 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
20714 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, NULL
},
20715 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, NULL
},
20716 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
20717 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
20718 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
20719 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
20720 {"cortex-a8", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20721 | FPU_NEON_EXT_V1
),
20723 {"cortex-a9", ARM_ARCH_V7A
, ARM_FEATURE(0, FPU_VFP_V3
20724 | FPU_NEON_EXT_V1
),
20726 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, NULL
},
20727 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, NULL
},
20728 {"cortex-m1", ARM_ARCH_V6M
, FPU_NONE
, NULL
},
20729 /* ??? XSCALE is really an architecture. */
20730 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20731 /* ??? iwmmxt is not a processor. */
20732 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
20733 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
20734 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
20736 {"ep9312", ARM_FEATURE(ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
20737 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
20740 struct arm_arch_option_table
20743 const arm_feature_set value
;
20744 const arm_feature_set default_fpu
;
20747 /* This list should, at a minimum, contain all the architecture names
20748 recognized by GCC. */
20749 static const struct arm_arch_option_table arm_archs
[] =
20751 {"all", ARM_ANY
, FPU_ARCH_FPA
},
20752 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
20753 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
20754 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20755 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
20756 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
20757 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
20758 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
20759 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
20760 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
20761 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
20762 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
20763 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
20764 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
20765 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
20766 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
20767 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
20768 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20769 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
20770 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
20771 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
20772 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
20773 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
20774 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
20775 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
20776 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
20777 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
20778 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
20779 /* The official spelling of the ARMv7 profile variants is the dashed form.
20780 Accept the non-dashed form for compatibility with old toolchains. */
20781 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20782 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20783 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20784 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
20785 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
20786 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
20787 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
20788 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
20789 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
20790 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
20793 /* ISA extensions in the co-processor space. */
20794 struct arm_option_cpu_value_table
20797 const arm_feature_set value
;
20800 static const struct arm_option_cpu_value_table arm_extensions
[] =
20802 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
)},
20803 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
)},
20804 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
)},
20805 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
)},
20806 {NULL
, ARM_ARCH_NONE
}
20809 /* This list should, at a minimum, contain all the fpu names
20810 recognized by GCC. */
20811 static const struct arm_option_cpu_value_table arm_fpus
[] =
20813 {"softfpa", FPU_NONE
},
20814 {"fpe", FPU_ARCH_FPE
},
20815 {"fpe2", FPU_ARCH_FPE
},
20816 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
20817 {"fpa", FPU_ARCH_FPA
},
20818 {"fpa10", FPU_ARCH_FPA
},
20819 {"fpa11", FPU_ARCH_FPA
},
20820 {"arm7500fe", FPU_ARCH_FPA
},
20821 {"softvfp", FPU_ARCH_VFP
},
20822 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
20823 {"vfp", FPU_ARCH_VFP_V2
},
20824 {"vfp9", FPU_ARCH_VFP_V2
},
20825 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
20826 {"vfp10", FPU_ARCH_VFP_V2
},
20827 {"vfp10-r0", FPU_ARCH_VFP_V1
},
20828 {"vfpxd", FPU_ARCH_VFP_V1xD
},
20829 {"vfpv2", FPU_ARCH_VFP_V2
},
20830 {"vfpv3", FPU_ARCH_VFP_V3
},
20831 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
20832 {"arm1020t", FPU_ARCH_VFP_V1
},
20833 {"arm1020e", FPU_ARCH_VFP_V2
},
20834 {"arm1136jfs", FPU_ARCH_VFP_V2
},
20835 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
20836 {"maverick", FPU_ARCH_MAVERICK
},
20837 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
20838 {"neon-fp16", FPU_ARCH_NEON_FP16
},
20839 {NULL
, ARM_ARCH_NONE
}
20842 struct arm_option_value_table
20848 static const struct arm_option_value_table arm_float_abis
[] =
20850 {"hard", ARM_FLOAT_ABI_HARD
},
20851 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
20852 {"soft", ARM_FLOAT_ABI_SOFT
},
20857 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
20858 static const struct arm_option_value_table arm_eabis
[] =
20860 {"gnu", EF_ARM_EABI_UNKNOWN
},
20861 {"4", EF_ARM_EABI_VER4
},
20862 {"5", EF_ARM_EABI_VER5
},
20867 struct arm_long_option_table
20869 char * option
; /* Substring to match. */
20870 char * help
; /* Help information. */
20871 int (* func
) (char * subopt
); /* Function to decode sub-option. */
20872 char * deprecated
; /* If non-null, print this message. */
20876 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
20878 arm_feature_set
*ext_set
= xmalloc (sizeof (arm_feature_set
));
20880 /* Copy the feature set, so that we can modify it. */
20881 *ext_set
= **opt_p
;
20884 while (str
!= NULL
&& *str
!= 0)
20886 const struct arm_option_cpu_value_table
* opt
;
20892 as_bad (_("invalid architectural extension"));
20897 ext
= strchr (str
, '+');
20900 optlen
= ext
- str
;
20902 optlen
= strlen (str
);
20906 as_bad (_("missing architectural extension"));
20910 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
20911 if (strncmp (opt
->name
, str
, optlen
) == 0)
20913 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
20917 if (opt
->name
== NULL
)
20919 as_bad (_("unknown architectural extension `%s'"), str
);
20930 arm_parse_cpu (char * str
)
20932 const struct arm_cpu_option_table
* opt
;
20933 char * ext
= strchr (str
, '+');
20937 optlen
= ext
- str
;
20939 optlen
= strlen (str
);
20943 as_bad (_("missing cpu name `%s'"), str
);
20947 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
20948 if (strncmp (opt
->name
, str
, optlen
) == 0)
20950 mcpu_cpu_opt
= &opt
->value
;
20951 mcpu_fpu_opt
= &opt
->default_fpu
;
20952 if (opt
->canonical_name
)
20953 strcpy (selected_cpu_name
, opt
->canonical_name
);
20957 for (i
= 0; i
< optlen
; i
++)
20958 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
20959 selected_cpu_name
[i
] = 0;
20963 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
20968 as_bad (_("unknown cpu `%s'"), str
);
20973 arm_parse_arch (char * str
)
20975 const struct arm_arch_option_table
*opt
;
20976 char *ext
= strchr (str
, '+');
20980 optlen
= ext
- str
;
20982 optlen
= strlen (str
);
20986 as_bad (_("missing architecture name `%s'"), str
);
20990 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
20991 if (streq (opt
->name
, str
))
20993 march_cpu_opt
= &opt
->value
;
20994 march_fpu_opt
= &opt
->default_fpu
;
20995 strcpy (selected_cpu_name
, opt
->name
);
20998 return arm_parse_extension (ext
, &march_cpu_opt
);
21003 as_bad (_("unknown architecture `%s'\n"), str
);
21008 arm_parse_fpu (char * str
)
21010 const struct arm_option_cpu_value_table
* opt
;
21012 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
21013 if (streq (opt
->name
, str
))
21015 mfpu_opt
= &opt
->value
;
21019 as_bad (_("unknown floating point format `%s'\n"), str
);
21024 arm_parse_float_abi (char * str
)
21026 const struct arm_option_value_table
* opt
;
21028 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
21029 if (streq (opt
->name
, str
))
21031 mfloat_abi_opt
= opt
->value
;
21035 as_bad (_("unknown floating point abi `%s'\n"), str
);
21041 arm_parse_eabi (char * str
)
21043 const struct arm_option_value_table
*opt
;
21045 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
21046 if (streq (opt
->name
, str
))
21048 meabi_flags
= opt
->value
;
21051 as_bad (_("unknown EABI `%s'\n"), str
);
21056 struct arm_long_option_table arm_long_opts
[] =
21058 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
21059 arm_parse_cpu
, NULL
},
21060 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
21061 arm_parse_arch
, NULL
},
21062 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
21063 arm_parse_fpu
, NULL
},
21064 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
21065 arm_parse_float_abi
, NULL
},
21067 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
21068 arm_parse_eabi
, NULL
},
21070 {NULL
, NULL
, 0, NULL
}
21074 md_parse_option (int c
, char * arg
)
21076 struct arm_option_table
*opt
;
21077 const struct arm_legacy_option_table
*fopt
;
21078 struct arm_long_option_table
*lopt
;
21084 target_big_endian
= 1;
21090 target_big_endian
= 0;
21094 case OPTION_FIX_V4BX
:
21099 /* Listing option. Just ignore these, we don't support additional
21104 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
21106 if (c
== opt
->option
[0]
21107 && ((arg
== NULL
&& opt
->option
[1] == 0)
21108 || streq (arg
, opt
->option
+ 1)))
21110 /* If the option is deprecated, tell the user. */
21111 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
21112 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
21113 arg
? arg
: "", _(opt
->deprecated
));
21115 if (opt
->var
!= NULL
)
21116 *opt
->var
= opt
->value
;
21122 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
21124 if (c
== fopt
->option
[0]
21125 && ((arg
== NULL
&& fopt
->option
[1] == 0)
21126 || streq (arg
, fopt
->option
+ 1)))
21128 /* If the option is deprecated, tell the user. */
21129 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
21130 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
21131 arg
? arg
: "", _(fopt
->deprecated
));
21133 if (fopt
->var
!= NULL
)
21134 *fopt
->var
= &fopt
->value
;
21140 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
21142 /* These options are expected to have an argument. */
21143 if (c
== lopt
->option
[0]
21145 && strncmp (arg
, lopt
->option
+ 1,
21146 strlen (lopt
->option
+ 1)) == 0)
21148 /* If the option is deprecated, tell the user. */
21149 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
21150 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
21151 _(lopt
->deprecated
));
21153 /* Call the sup-option parser. */
21154 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
21165 md_show_usage (FILE * fp
)
21167 struct arm_option_table
*opt
;
21168 struct arm_long_option_table
*lopt
;
21170 fprintf (fp
, _(" ARM-specific assembler options:\n"));
21172 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
21173 if (opt
->help
!= NULL
)
21174 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
21176 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
21177 if (lopt
->help
!= NULL
)
21178 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
21182 -EB assemble code for a big-endian cpu\n"));
21187 -EL assemble code for a little-endian cpu\n"));
21191 --fix-v4bx Allow BX in ARMv4 code\n"));
21199 arm_feature_set flags
;
21200 } cpu_arch_ver_table
;
21202 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
21203 least features first. */
21204 static const cpu_arch_ver_table cpu_arch_ver
[] =
21210 {4, ARM_ARCH_V5TE
},
21211 {5, ARM_ARCH_V5TEJ
},
21215 {11, ARM_ARCH_V6M
},
21216 {8, ARM_ARCH_V6T2
},
21217 {10, ARM_ARCH_V7A
},
21218 {10, ARM_ARCH_V7R
},
21219 {10, ARM_ARCH_V7M
},
21223 /* Set an attribute if it has not already been set by the user. */
21225 aeabi_set_attribute_int (int tag
, int value
)
21228 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
21229 || !attributes_set_explicitly
[tag
])
21230 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
21234 aeabi_set_attribute_string (int tag
, const char *value
)
21237 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
21238 || !attributes_set_explicitly
[tag
])
21239 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
21242 /* Set the public EABI object attributes. */
21244 aeabi_set_public_attributes (void)
21247 arm_feature_set flags
;
21248 arm_feature_set tmp
;
21249 const cpu_arch_ver_table
*p
;
21251 /* Choose the architecture based on the capabilities of the requested cpu
21252 (if any) and/or the instructions actually used. */
21253 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
21254 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
21255 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
21256 /*Allow the user to override the reported architecture. */
21259 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
21260 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
21265 for (p
= cpu_arch_ver
; p
->val
; p
++)
21267 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
21270 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
21274 /* Tag_CPU_name. */
21275 if (selected_cpu_name
[0])
21279 p
= selected_cpu_name
;
21280 if (strncmp (p
, "armv", 4) == 0)
21285 for (i
= 0; p
[i
]; i
++)
21286 p
[i
] = TOUPPER (p
[i
]);
21288 aeabi_set_attribute_string (Tag_CPU_name
, p
);
21290 /* Tag_CPU_arch. */
21291 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
21292 /* Tag_CPU_arch_profile. */
21293 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
21294 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
21295 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
21296 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
21297 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
21298 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
21299 /* Tag_ARM_ISA_use. */
21300 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
21302 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
21303 /* Tag_THUMB_ISA_use. */
21304 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
21306 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
21307 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
21308 /* Tag_VFP_arch. */
21309 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
21310 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
21311 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3
))
21312 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
21313 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
21314 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
21315 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
21316 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
21317 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
21318 /* Tag_WMMX_arch. */
21319 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
21320 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
21321 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
21322 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
21323 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
21324 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
21325 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
21326 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
21327 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_fp16
))
21328 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
21331 /* Add the default contents for the .ARM.attributes section. */
21335 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
21338 aeabi_set_public_attributes ();
21340 #endif /* OBJ_ELF */
21343 /* Parse a .cpu directive. */
21346 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
21348 const struct arm_cpu_option_table
*opt
;
21352 name
= input_line_pointer
;
21353 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21354 input_line_pointer
++;
21355 saved_char
= *input_line_pointer
;
21356 *input_line_pointer
= 0;
21358 /* Skip the first "all" entry. */
21359 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
21360 if (streq (opt
->name
, name
))
21362 mcpu_cpu_opt
= &opt
->value
;
21363 selected_cpu
= opt
->value
;
21364 if (opt
->canonical_name
)
21365 strcpy (selected_cpu_name
, opt
->canonical_name
);
21369 for (i
= 0; opt
->name
[i
]; i
++)
21370 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
21371 selected_cpu_name
[i
] = 0;
21373 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21374 *input_line_pointer
= saved_char
;
21375 demand_empty_rest_of_line ();
21378 as_bad (_("unknown cpu `%s'"), name
);
21379 *input_line_pointer
= saved_char
;
21380 ignore_rest_of_line ();
21384 /* Parse a .arch directive. */
21387 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
21389 const struct arm_arch_option_table
*opt
;
21393 name
= input_line_pointer
;
21394 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21395 input_line_pointer
++;
21396 saved_char
= *input_line_pointer
;
21397 *input_line_pointer
= 0;
21399 /* Skip the first "all" entry. */
21400 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
21401 if (streq (opt
->name
, name
))
21403 mcpu_cpu_opt
= &opt
->value
;
21404 selected_cpu
= opt
->value
;
21405 strcpy (selected_cpu_name
, opt
->name
);
21406 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21407 *input_line_pointer
= saved_char
;
21408 demand_empty_rest_of_line ();
21412 as_bad (_("unknown architecture `%s'\n"), name
);
21413 *input_line_pointer
= saved_char
;
21414 ignore_rest_of_line ();
21418 /* Parse a .object_arch directive. */
21421 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
21423 const struct arm_arch_option_table
*opt
;
21427 name
= input_line_pointer
;
21428 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21429 input_line_pointer
++;
21430 saved_char
= *input_line_pointer
;
21431 *input_line_pointer
= 0;
21433 /* Skip the first "all" entry. */
21434 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
21435 if (streq (opt
->name
, name
))
21437 object_arch
= &opt
->value
;
21438 *input_line_pointer
= saved_char
;
21439 demand_empty_rest_of_line ();
21443 as_bad (_("unknown architecture `%s'\n"), name
);
21444 *input_line_pointer
= saved_char
;
21445 ignore_rest_of_line ();
21448 /* Parse a .fpu directive. */
21451 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
21453 const struct arm_option_cpu_value_table
*opt
;
21457 name
= input_line_pointer
;
21458 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
21459 input_line_pointer
++;
21460 saved_char
= *input_line_pointer
;
21461 *input_line_pointer
= 0;
21463 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
21464 if (streq (opt
->name
, name
))
21466 mfpu_opt
= &opt
->value
;
21467 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
21468 *input_line_pointer
= saved_char
;
21469 demand_empty_rest_of_line ();
21473 as_bad (_("unknown floating point format `%s'\n"), name
);
21474 *input_line_pointer
= saved_char
;
21475 ignore_rest_of_line ();
21478 /* Copy symbol information. */
21481 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
21483 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
21487 /* Given a symbolic attribute NAME, return the proper integer value.
21488 Returns -1 if the attribute is not known. */
21491 arm_convert_symbolic_attribute (const char *name
)
21493 static const struct
21498 attribute_table
[] =
21500 /* When you modify this table you should
21501 also modify the list in doc/c-arm.texi. */
21502 #define T(tag) {#tag, tag}
21503 T (Tag_CPU_raw_name
),
21506 T (Tag_CPU_arch_profile
),
21507 T (Tag_ARM_ISA_use
),
21508 T (Tag_THUMB_ISA_use
),
21511 T (Tag_Advanced_SIMD_arch
),
21512 T (Tag_PCS_config
),
21513 T (Tag_ABI_PCS_R9_use
),
21514 T (Tag_ABI_PCS_RW_data
),
21515 T (Tag_ABI_PCS_RO_data
),
21516 T (Tag_ABI_PCS_GOT_use
),
21517 T (Tag_ABI_PCS_wchar_t
),
21518 T (Tag_ABI_FP_rounding
),
21519 T (Tag_ABI_FP_denormal
),
21520 T (Tag_ABI_FP_exceptions
),
21521 T (Tag_ABI_FP_user_exceptions
),
21522 T (Tag_ABI_FP_number_model
),
21523 T (Tag_ABI_align8_needed
),
21524 T (Tag_ABI_align8_preserved
),
21525 T (Tag_ABI_enum_size
),
21526 T (Tag_ABI_HardFP_use
),
21527 T (Tag_ABI_VFP_args
),
21528 T (Tag_ABI_WMMX_args
),
21529 T (Tag_ABI_optimization_goals
),
21530 T (Tag_ABI_FP_optimization_goals
),
21531 T (Tag_compatibility
),
21532 T (Tag_CPU_unaligned_access
),
21533 T (Tag_VFP_HP_extension
),
21534 T (Tag_ABI_FP_16bit_format
),
21535 T (Tag_nodefaults
),
21536 T (Tag_also_compatible_with
),
21537 T (Tag_conformance
),
21539 T (Tag_Virtualization_use
),
21540 T (Tag_MPextension_use
)
21548 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
21549 if (strcmp (name
, attribute_table
[i
].name
) == 0)
21550 return attribute_table
[i
].tag
;
21554 #endif /* OBJ_ELF */