1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2014 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 static arm_feature_set cpu_variant
;
127 static arm_feature_set arm_arch_used
;
128 static arm_feature_set thumb_arch_used
;
130 /* Flags stored in private area of BFD structure. */
131 static int uses_apcs_26
= FALSE
;
132 static int atpcs
= FALSE
;
133 static int support_interwork
= FALSE
;
134 static int uses_apcs_float
= FALSE
;
135 static int pic_code
= FALSE
;
136 static int fix_v4bx
= FALSE
;
137 /* Warn on using deprecated features. */
138 static int warn_on_deprecated
= TRUE
;
140 /* Understand CodeComposer Studio assembly syntax. */
141 bfd_boolean codecomposer_syntax
= FALSE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_v8
= ARM_FEATURE (ARM_EXT_V8
, 0);
199 static const arm_feature_set arm_ext_m
=
200 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
201 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
202 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
203 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
204 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
205 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
207 static const arm_feature_set arm_arch_any
= ARM_ANY
;
208 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
209 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
210 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
211 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
213 static const arm_feature_set arm_cext_iwmmxt2
=
214 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
215 static const arm_feature_set arm_cext_iwmmxt
=
216 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
217 static const arm_feature_set arm_cext_xscale
=
218 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
219 static const arm_feature_set arm_cext_maverick
=
220 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
221 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
222 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
223 static const arm_feature_set fpu_vfp_ext_v1xd
=
224 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
225 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
226 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
227 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
228 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
229 static const arm_feature_set fpu_vfp_ext_d32
=
230 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
231 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
232 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
233 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
234 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
235 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
236 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static const arm_feature_set fpu_vfp_ext_armv8
=
238 ARM_FEATURE (0, FPU_VFP_EXT_ARMV8
);
239 static const arm_feature_set fpu_neon_ext_armv8
=
240 ARM_FEATURE (0, FPU_NEON_EXT_ARMV8
);
241 static const arm_feature_set fpu_crypto_ext_armv8
=
242 ARM_FEATURE (0, FPU_CRYPTO_EXT_ARMV8
);
243 static const arm_feature_set crc_ext_armv8
=
244 ARM_FEATURE (0, CRC_EXT_ARMV8
);
246 static int mfloat_abi_opt
= -1;
247 /* Record user cpu selection for object attributes. */
248 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
249 /* Must be long enough to hold any of the names in arm_cpus. */
250 static char selected_cpu_name
[16];
252 /* Return if no cpu was selected on command-line. */
254 no_cpu_selected (void)
256 return selected_cpu
.core
== arm_arch_none
.core
257 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
262 static int meabi_flags
= EABI_DEFAULT
;
264 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
267 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
272 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
277 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
278 symbolS
* GOT_symbol
;
281 /* 0: assemble for ARM,
282 1: assemble for Thumb,
283 2: assemble for Thumb even though target CPU does not support thumb
285 static int thumb_mode
= 0;
286 /* A value distinct from the possible values for thumb_mode that we
287 can use to record whether thumb_mode has been copied into the
288 tc_frag_data field of a frag. */
289 #define MODE_RECORDED (1 << 4)
291 /* Specifies the intrinsic IT insn behavior mode. */
292 enum implicit_it_mode
294 IMPLICIT_IT_MODE_NEVER
= 0x00,
295 IMPLICIT_IT_MODE_ARM
= 0x01,
296 IMPLICIT_IT_MODE_THUMB
= 0x02,
297 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
299 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
301 /* If unified_syntax is true, we are processing the new unified
302 ARM/Thumb syntax. Important differences from the old ARM mode:
304 - Immediate operands do not require a # prefix.
305 - Conditional affixes always appear at the end of the
306 instruction. (For backward compatibility, those instructions
307 that formerly had them in the middle, continue to accept them
309 - The IT instruction may appear, and if it does is validated
310 against subsequent conditional affixes. It does not generate
313 Important differences from the old Thumb mode:
315 - Immediate operands do not require a # prefix.
316 - Most of the V6T2 instructions are only available in unified mode.
317 - The .N and .W suffixes are recognized and honored (it is an error
318 if they cannot be honored).
319 - All instructions set the flags if and only if they have an 's' affix.
320 - Conditional affixes may be used. They are validated against
321 preceding IT instructions. Unlike ARM mode, you cannot use a
322 conditional affix except in the scope of an IT instruction. */
324 static bfd_boolean unified_syntax
= FALSE
;
326 /* An immediate operand can start with #, and ld*, st*, pld operands
327 can contain [ and ]. We need to tell APP not to elide whitespace
328 before a [, which can appear as the first operand for pld.
329 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
330 const char arm_symbol_chars
[] = "#[]{}";
345 enum neon_el_type type
;
349 #define NEON_MAX_TYPE_ELS 4
353 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
357 enum it_instruction_type
362 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
363 if inside, should be the last one. */
364 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
365 i.e. BKPT and NOP. */
366 IT_INSN
/* The IT insn has been parsed. */
369 /* The maximum number of operands we need. */
370 #define ARM_IT_MAX_OPERANDS 6
375 unsigned long instruction
;
379 /* "uncond_value" is set to the value in place of the conditional field in
380 unconditional versions of the instruction, or -1 if nothing is
383 struct neon_type vectype
;
384 /* This does not indicate an actual NEON instruction, only that
385 the mnemonic accepts neon-style type suffixes. */
387 /* Set to the opcode if the instruction needs relaxation.
388 Zero if the instruction is not relaxed. */
392 bfd_reloc_code_real_type type
;
397 enum it_instruction_type it_insn_type
;
403 struct neon_type_el vectype
;
404 unsigned present
: 1; /* Operand present. */
405 unsigned isreg
: 1; /* Operand was a register. */
406 unsigned immisreg
: 1; /* .imm field is a second register. */
407 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
408 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
409 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
410 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
411 instructions. This allows us to disambiguate ARM <-> vector insns. */
412 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
413 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
414 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
415 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
416 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
417 unsigned writeback
: 1; /* Operand has trailing ! */
418 unsigned preind
: 1; /* Preindexed address. */
419 unsigned postind
: 1; /* Postindexed address. */
420 unsigned negative
: 1; /* Index register was negated. */
421 unsigned shifted
: 1; /* Shift applied to operation. */
422 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
423 } operands
[ARM_IT_MAX_OPERANDS
];
426 static struct arm_it inst
;
428 #define NUM_FLOAT_VALS 8
430 const char * fp_const
[] =
432 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
435 /* Number of littlenums required to hold an extended precision number. */
436 #define MAX_LITTLENUMS 6
438 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
448 #define CP_T_X 0x00008000
449 #define CP_T_Y 0x00400000
451 #define CONDS_BIT 0x00100000
452 #define LOAD_BIT 0x00100000
454 #define DOUBLE_LOAD_FLAG 0x00000001
458 const char * template_name
;
462 #define COND_ALWAYS 0xE
466 const char * template_name
;
470 struct asm_barrier_opt
472 const char * template_name
;
474 const arm_feature_set arch
;
477 /* The bit that distinguishes CPSR and SPSR. */
478 #define SPSR_BIT (1 << 22)
480 /* The individual PSR flag bits. */
481 #define PSR_c (1 << 16)
482 #define PSR_x (1 << 17)
483 #define PSR_s (1 << 18)
484 #define PSR_f (1 << 19)
489 bfd_reloc_code_real_type reloc
;
494 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
495 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
500 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
503 /* Bits for DEFINED field in neon_typed_alias. */
504 #define NTA_HASTYPE 1
505 #define NTA_HASINDEX 2
507 struct neon_typed_alias
509 unsigned char defined
;
511 struct neon_type_el eltype
;
514 /* ARM register categories. This includes coprocessor numbers and various
515 architecture extensions' registers. */
542 /* Structure for a hash table entry for a register.
543 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
544 information which states whether a vector type or index is specified (for a
545 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
551 unsigned char builtin
;
552 struct neon_typed_alias
* neon
;
555 /* Diagnostics used when we don't get a register of the expected type. */
556 const char * const reg_expected_msgs
[] =
558 N_("ARM register expected"),
559 N_("bad or missing co-processor number"),
560 N_("co-processor register expected"),
561 N_("FPA register expected"),
562 N_("VFP single precision register expected"),
563 N_("VFP/Neon double precision register expected"),
564 N_("Neon quad precision register expected"),
565 N_("VFP single or double precision register expected"),
566 N_("Neon double or quad precision register expected"),
567 N_("VFP single, double or Neon quad precision register expected"),
568 N_("VFP system register expected"),
569 N_("Maverick MVF register expected"),
570 N_("Maverick MVD register expected"),
571 N_("Maverick MVFX register expected"),
572 N_("Maverick MVDX register expected"),
573 N_("Maverick MVAX register expected"),
574 N_("Maverick DSPSC register expected"),
575 N_("iWMMXt data register expected"),
576 N_("iWMMXt control register expected"),
577 N_("iWMMXt scalar register expected"),
578 N_("XScale accumulator register expected"),
581 /* Some well known registers that we refer to directly elsewhere. */
587 /* ARM instructions take 4bytes in the object file, Thumb instructions
593 /* Basic string to match. */
594 const char * template_name
;
596 /* Parameters to instruction. */
597 unsigned int operands
[8];
599 /* Conditional tag - see opcode_lookup. */
600 unsigned int tag
: 4;
602 /* Basic instruction code. */
603 unsigned int avalue
: 28;
605 /* Thumb-format instruction code. */
608 /* Which architecture variant provides this instruction. */
609 const arm_feature_set
* avariant
;
610 const arm_feature_set
* tvariant
;
612 /* Function to call to encode instruction in ARM format. */
613 void (* aencode
) (void);
615 /* Function to call to encode instruction in Thumb format. */
616 void (* tencode
) (void);
619 /* Defines for various bits that we will want to toggle. */
620 #define INST_IMMEDIATE 0x02000000
621 #define OFFSET_REG 0x02000000
622 #define HWOFFSET_IMM 0x00400000
623 #define SHIFT_BY_REG 0x00000010
624 #define PRE_INDEX 0x01000000
625 #define INDEX_UP 0x00800000
626 #define WRITE_BACK 0x00200000
627 #define LDM_TYPE_2_OR_3 0x00400000
628 #define CPSI_MMOD 0x00020000
630 #define LITERAL_MASK 0xf000f000
631 #define OPCODE_MASK 0xfe1fffff
632 #define V4_STR_BIT 0x00000020
634 #define T2_SUBS_PC_LR 0xf3de8f00
636 #define DATA_OP_SHIFT 21
638 #define T2_OPCODE_MASK 0xfe1fffff
639 #define T2_DATA_OP_SHIFT 21
641 #define A_COND_MASK 0xf0000000
642 #define A_PUSH_POP_OP_MASK 0x0fff0000
644 /* Opcodes for pushing/poping registers to/from the stack. */
645 #define A1_OPCODE_PUSH 0x092d0000
646 #define A2_OPCODE_PUSH 0x052d0004
647 #define A2_OPCODE_POP 0x049d0004
649 /* Codes to distinguish the arithmetic instructions. */
660 #define OPCODE_CMP 10
661 #define OPCODE_CMN 11
662 #define OPCODE_ORR 12
663 #define OPCODE_MOV 13
664 #define OPCODE_BIC 14
665 #define OPCODE_MVN 15
667 #define T2_OPCODE_AND 0
668 #define T2_OPCODE_BIC 1
669 #define T2_OPCODE_ORR 2
670 #define T2_OPCODE_ORN 3
671 #define T2_OPCODE_EOR 4
672 #define T2_OPCODE_ADD 8
673 #define T2_OPCODE_ADC 10
674 #define T2_OPCODE_SBC 11
675 #define T2_OPCODE_SUB 13
676 #define T2_OPCODE_RSB 14
678 #define T_OPCODE_MUL 0x4340
679 #define T_OPCODE_TST 0x4200
680 #define T_OPCODE_CMN 0x42c0
681 #define T_OPCODE_NEG 0x4240
682 #define T_OPCODE_MVN 0x43c0
684 #define T_OPCODE_ADD_R3 0x1800
685 #define T_OPCODE_SUB_R3 0x1a00
686 #define T_OPCODE_ADD_HI 0x4400
687 #define T_OPCODE_ADD_ST 0xb000
688 #define T_OPCODE_SUB_ST 0xb080
689 #define T_OPCODE_ADD_SP 0xa800
690 #define T_OPCODE_ADD_PC 0xa000
691 #define T_OPCODE_ADD_I8 0x3000
692 #define T_OPCODE_SUB_I8 0x3800
693 #define T_OPCODE_ADD_I3 0x1c00
694 #define T_OPCODE_SUB_I3 0x1e00
696 #define T_OPCODE_ASR_R 0x4100
697 #define T_OPCODE_LSL_R 0x4080
698 #define T_OPCODE_LSR_R 0x40c0
699 #define T_OPCODE_ROR_R 0x41c0
700 #define T_OPCODE_ASR_I 0x1000
701 #define T_OPCODE_LSL_I 0x0000
702 #define T_OPCODE_LSR_I 0x0800
704 #define T_OPCODE_MOV_I8 0x2000
705 #define T_OPCODE_CMP_I8 0x2800
706 #define T_OPCODE_CMP_LR 0x4280
707 #define T_OPCODE_MOV_HR 0x4600
708 #define T_OPCODE_CMP_HR 0x4500
710 #define T_OPCODE_LDR_PC 0x4800
711 #define T_OPCODE_LDR_SP 0x9800
712 #define T_OPCODE_STR_SP 0x9000
713 #define T_OPCODE_LDR_IW 0x6800
714 #define T_OPCODE_STR_IW 0x6000
715 #define T_OPCODE_LDR_IH 0x8800
716 #define T_OPCODE_STR_IH 0x8000
717 #define T_OPCODE_LDR_IB 0x7800
718 #define T_OPCODE_STR_IB 0x7000
719 #define T_OPCODE_LDR_RW 0x5800
720 #define T_OPCODE_STR_RW 0x5000
721 #define T_OPCODE_LDR_RH 0x5a00
722 #define T_OPCODE_STR_RH 0x5200
723 #define T_OPCODE_LDR_RB 0x5c00
724 #define T_OPCODE_STR_RB 0x5400
726 #define T_OPCODE_PUSH 0xb400
727 #define T_OPCODE_POP 0xbc00
729 #define T_OPCODE_BRANCH 0xe000
731 #define THUMB_SIZE 2 /* Size of thumb instruction. */
732 #define THUMB_PP_PC_LR 0x0100
733 #define THUMB_LOAD_BIT 0x0800
734 #define THUMB2_LOAD_BIT 0x00100000
736 #define BAD_ARGS _("bad arguments to instruction")
737 #define BAD_SP _("r13 not allowed here")
738 #define BAD_PC _("r15 not allowed here")
739 #define BAD_COND _("instruction cannot be conditional")
740 #define BAD_OVERLAP _("registers may not be the same")
741 #define BAD_HIREG _("lo register required")
742 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
743 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
744 #define BAD_BRANCH _("branch must be last instruction in IT block")
745 #define BAD_NOT_IT _("instruction not allowed in IT block")
746 #define BAD_FPU _("selected FPU does not support instruction")
747 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
748 #define BAD_IT_COND _("incorrect condition in IT block")
749 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
750 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
751 #define BAD_PC_ADDRESSING \
752 _("cannot use register index with PC-relative addressing")
753 #define BAD_PC_WRITEBACK \
754 _("cannot use writeback with PC-relative addressing")
755 #define BAD_RANGE _("branch out of range")
756 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
758 static struct hash_control
* arm_ops_hsh
;
759 static struct hash_control
* arm_cond_hsh
;
760 static struct hash_control
* arm_shift_hsh
;
761 static struct hash_control
* arm_psr_hsh
;
762 static struct hash_control
* arm_v7m_psr_hsh
;
763 static struct hash_control
* arm_reg_hsh
;
764 static struct hash_control
* arm_reloc_hsh
;
765 static struct hash_control
* arm_barrier_opt_hsh
;
767 /* Stuff needed to resolve the label ambiguity
776 symbolS
* last_label_seen
;
777 static int label_is_thumb_function_name
= FALSE
;
779 /* Literal pool structure. Held on a per-section
780 and per-sub-section basis. */
782 #define MAX_LITERAL_POOL_SIZE 1024
783 typedef struct literal_pool
785 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
786 unsigned int next_free_entry
;
792 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
794 struct literal_pool
* next
;
797 /* Pointer to a linked list of literal pools. */
798 literal_pool
* list_of_pools
= NULL
;
800 typedef enum asmfunc_states
803 WAITING_ASMFUNC_NAME
,
807 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
810 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
812 static struct current_it now_it
;
816 now_it_compatible (int cond
)
818 return (cond
& ~1) == (now_it
.cc
& ~1);
822 conditional_insn (void)
824 return inst
.cond
!= COND_ALWAYS
;
827 static int in_it_block (void);
829 static int handle_it_state (void);
831 static void force_automatic_it_block_close (void);
833 static void it_fsm_post_encode (void);
835 #define set_it_insn_type(type) \
838 inst.it_insn_type = type; \
839 if (handle_it_state () == FAIL) \
844 #define set_it_insn_type_nonvoid(type, failret) \
847 inst.it_insn_type = type; \
848 if (handle_it_state () == FAIL) \
853 #define set_it_insn_type_last() \
856 if (inst.cond == COND_ALWAYS) \
857 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
859 set_it_insn_type (INSIDE_IT_LAST_INSN); \
865 /* This array holds the chars that always start a comment. If the
866 pre-processor is disabled, these aren't very useful. */
867 char arm_comment_chars
[] = "@";
869 /* This array holds the chars that only start a comment at the beginning of
870 a line. If the line seems to have the form '# 123 filename'
871 .line and .file directives will appear in the pre-processed output. */
872 /* Note that input_file.c hand checks for '#' at the beginning of the
873 first line of the input file. This is because the compiler outputs
874 #NO_APP at the beginning of its output. */
875 /* Also note that comments like this one will always work. */
876 const char line_comment_chars
[] = "#";
878 char arm_line_separator_chars
[] = ";";
880 /* Chars that can be used to separate mant
881 from exp in floating point numbers. */
882 const char EXP_CHARS
[] = "eE";
884 /* Chars that mean this number is a floating point constant. */
888 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
890 /* Prefix characters that indicate the start of an immediate
892 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
894 /* Separator character handling. */
896 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
899 skip_past_char (char ** str
, char c
)
901 /* PR gas/14987: Allow for whitespace before the expected character. */
902 skip_whitespace (*str
);
913 #define skip_past_comma(str) skip_past_char (str, ',')
915 /* Arithmetic expressions (possibly involving symbols). */
917 /* Return TRUE if anything in the expression is a bignum. */
920 walk_no_bignums (symbolS
* sp
)
922 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
925 if (symbol_get_value_expression (sp
)->X_add_symbol
)
927 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
928 || (symbol_get_value_expression (sp
)->X_op_symbol
929 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
935 static int in_my_get_expression
= 0;
937 /* Third argument to my_get_expression. */
938 #define GE_NO_PREFIX 0
939 #define GE_IMM_PREFIX 1
940 #define GE_OPT_PREFIX 2
941 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
942 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
943 #define GE_OPT_PREFIX_BIG 3
946 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
951 /* In unified syntax, all prefixes are optional. */
953 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
958 case GE_NO_PREFIX
: break;
960 if (!is_immediate_prefix (**str
))
962 inst
.error
= _("immediate expression requires a # prefix");
968 case GE_OPT_PREFIX_BIG
:
969 if (is_immediate_prefix (**str
))
975 memset (ep
, 0, sizeof (expressionS
));
977 save_in
= input_line_pointer
;
978 input_line_pointer
= *str
;
979 in_my_get_expression
= 1;
980 seg
= expression (ep
);
981 in_my_get_expression
= 0;
983 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
985 /* We found a bad or missing expression in md_operand(). */
986 *str
= input_line_pointer
;
987 input_line_pointer
= save_in
;
988 if (inst
.error
== NULL
)
989 inst
.error
= (ep
->X_op
== O_absent
990 ? _("missing expression") :_("bad expression"));
995 if (seg
!= absolute_section
996 && seg
!= text_section
997 && seg
!= data_section
998 && seg
!= bss_section
999 && seg
!= undefined_section
)
1001 inst
.error
= _("bad segment");
1002 *str
= input_line_pointer
;
1003 input_line_pointer
= save_in
;
1010 /* Get rid of any bignums now, so that we don't generate an error for which
1011 we can't establish a line number later on. Big numbers are never valid
1012 in instructions, which is where this routine is always called. */
1013 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1014 && (ep
->X_op
== O_big
1015 || (ep
->X_add_symbol
1016 && (walk_no_bignums (ep
->X_add_symbol
)
1018 && walk_no_bignums (ep
->X_op_symbol
))))))
1020 inst
.error
= _("invalid constant");
1021 *str
= input_line_pointer
;
1022 input_line_pointer
= save_in
;
1026 *str
= input_line_pointer
;
1027 input_line_pointer
= save_in
;
1031 /* Turn a string in input_line_pointer into a floating point constant
1032 of type TYPE, and store the appropriate bytes in *LITP. The number
1033 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1034 returned, or NULL on OK.
1036 Note that fp constants aren't represent in the normal way on the ARM.
1037 In big endian mode, things are as expected. However, in little endian
1038 mode fp constants are big-endian word-wise, and little-endian byte-wise
1039 within the words. For example, (double) 1.1 in big endian mode is
1040 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1041 the byte sequence 99 99 f1 3f 9a 99 99 99.
1043 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1046 md_atof (int type
, char * litP
, int * sizeP
)
1049 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1081 return _("Unrecognized or unsupported floating point constant");
1084 t
= atof_ieee (input_line_pointer
, type
, words
);
1086 input_line_pointer
= t
;
1087 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1089 if (target_big_endian
)
1091 for (i
= 0; i
< prec
; i
++)
1093 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1094 litP
+= sizeof (LITTLENUM_TYPE
);
1099 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1100 for (i
= prec
- 1; i
>= 0; i
--)
1102 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1103 litP
+= sizeof (LITTLENUM_TYPE
);
1106 /* For a 4 byte float the order of elements in `words' is 1 0.
1107 For an 8 byte float the order is 1 0 3 2. */
1108 for (i
= 0; i
< prec
; i
+= 2)
1110 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1111 sizeof (LITTLENUM_TYPE
));
1112 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1113 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1114 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1121 /* We handle all bad expressions here, so that we can report the faulty
1122 instruction in the error message. */
1124 md_operand (expressionS
* exp
)
1126 if (in_my_get_expression
)
1127 exp
->X_op
= O_illegal
;
1130 /* Immediate values. */
1132 /* Generic immediate-value read function for use in directives.
1133 Accepts anything that 'expression' can fold to a constant.
1134 *val receives the number. */
1137 immediate_for_directive (int *val
)
1140 exp
.X_op
= O_illegal
;
1142 if (is_immediate_prefix (*input_line_pointer
))
1144 input_line_pointer
++;
1148 if (exp
.X_op
!= O_constant
)
1150 as_bad (_("expected #constant"));
1151 ignore_rest_of_line ();
1154 *val
= exp
.X_add_number
;
1159 /* Register parsing. */
1161 /* Generic register parser. CCP points to what should be the
1162 beginning of a register name. If it is indeed a valid register
1163 name, advance CCP over it and return the reg_entry structure;
1164 otherwise return NULL. Does not issue diagnostics. */
1166 static struct reg_entry
*
1167 arm_reg_parse_multi (char **ccp
)
1171 struct reg_entry
*reg
;
1173 skip_whitespace (start
);
1175 #ifdef REGISTER_PREFIX
1176 if (*start
!= REGISTER_PREFIX
)
1180 #ifdef OPTIONAL_REGISTER_PREFIX
1181 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1186 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1191 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1193 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1203 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1204 enum arm_reg_type type
)
1206 /* Alternative syntaxes are accepted for a few register classes. */
1213 /* Generic coprocessor register names are allowed for these. */
1214 if (reg
&& reg
->type
== REG_TYPE_CN
)
1219 /* For backward compatibility, a bare number is valid here. */
1221 unsigned long processor
= strtoul (start
, ccp
, 10);
1222 if (*ccp
!= start
&& processor
<= 15)
1226 case REG_TYPE_MMXWC
:
1227 /* WC includes WCG. ??? I'm not sure this is true for all
1228 instructions that take WC registers. */
1229 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1240 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1241 return value is the register number or FAIL. */
1244 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1247 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1250 /* Do not allow a scalar (reg+index) to parse as a register. */
1251 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1254 if (reg
&& reg
->type
== type
)
1257 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1264 /* Parse a Neon type specifier. *STR should point at the leading '.'
1265 character. Does no verification at this stage that the type fits the opcode
1272 Can all be legally parsed by this function.
1274 Fills in neon_type struct pointer with parsed information, and updates STR
1275 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1276 type, FAIL if not. */
1279 parse_neon_type (struct neon_type
*type
, char **str
)
1286 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1288 enum neon_el_type thistype
= NT_untyped
;
1289 unsigned thissize
= -1u;
1296 /* Just a size without an explicit type. */
1300 switch (TOLOWER (*ptr
))
1302 case 'i': thistype
= NT_integer
; break;
1303 case 'f': thistype
= NT_float
; break;
1304 case 'p': thistype
= NT_poly
; break;
1305 case 's': thistype
= NT_signed
; break;
1306 case 'u': thistype
= NT_unsigned
; break;
1308 thistype
= NT_float
;
1313 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1319 /* .f is an abbreviation for .f32. */
1320 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1325 thissize
= strtoul (ptr
, &ptr
, 10);
1327 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1330 as_bad (_("bad size %d in type specifier"), thissize
);
1338 type
->el
[type
->elems
].type
= thistype
;
1339 type
->el
[type
->elems
].size
= thissize
;
1344 /* Empty/missing type is not a successful parse. */
1345 if (type
->elems
== 0)
1353 /* Errors may be set multiple times during parsing or bit encoding
1354 (particularly in the Neon bits), but usually the earliest error which is set
1355 will be the most meaningful. Avoid overwriting it with later (cascading)
1356 errors by calling this function. */
1359 first_error (const char *err
)
1365 /* Parse a single type, e.g. ".s32", leading period included. */
1367 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1370 struct neon_type optype
;
1374 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1376 if (optype
.elems
== 1)
1377 *vectype
= optype
.el
[0];
1380 first_error (_("only one type should be specified for operand"));
1386 first_error (_("vector type expected"));
1398 /* Special meanings for indices (which have a range of 0-7), which will fit into
1401 #define NEON_ALL_LANES 15
1402 #define NEON_INTERLEAVE_LANES 14
1404 /* Parse either a register or a scalar, with an optional type. Return the
1405 register number, and optionally fill in the actual type of the register
1406 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1407 type/index information in *TYPEINFO. */
1410 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1411 enum arm_reg_type
*rtype
,
1412 struct neon_typed_alias
*typeinfo
)
1415 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1416 struct neon_typed_alias atype
;
1417 struct neon_type_el parsetype
;
1421 atype
.eltype
.type
= NT_invtype
;
1422 atype
.eltype
.size
= -1;
1424 /* Try alternate syntax for some types of register. Note these are mutually
1425 exclusive with the Neon syntax extensions. */
1428 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1436 /* Undo polymorphism when a set of register types may be accepted. */
1437 if ((type
== REG_TYPE_NDQ
1438 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1439 || (type
== REG_TYPE_VFSD
1440 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1441 || (type
== REG_TYPE_NSDQ
1442 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1443 || reg
->type
== REG_TYPE_NQ
))
1444 || (type
== REG_TYPE_MMXWC
1445 && (reg
->type
== REG_TYPE_MMXWCG
)))
1446 type
= (enum arm_reg_type
) reg
->type
;
1448 if (type
!= reg
->type
)
1454 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1456 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1458 first_error (_("can't redefine type for operand"));
1461 atype
.defined
|= NTA_HASTYPE
;
1462 atype
.eltype
= parsetype
;
1465 if (skip_past_char (&str
, '[') == SUCCESS
)
1467 if (type
!= REG_TYPE_VFD
)
1469 first_error (_("only D registers may be indexed"));
1473 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1475 first_error (_("can't change index for operand"));
1479 atype
.defined
|= NTA_HASINDEX
;
1481 if (skip_past_char (&str
, ']') == SUCCESS
)
1482 atype
.index
= NEON_ALL_LANES
;
1487 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1489 if (exp
.X_op
!= O_constant
)
1491 first_error (_("constant expression required"));
1495 if (skip_past_char (&str
, ']') == FAIL
)
1498 atype
.index
= exp
.X_add_number
;
1513 /* Like arm_reg_parse, but allow allow the following extra features:
1514 - If RTYPE is non-zero, return the (possibly restricted) type of the
1515 register (e.g. Neon double or quad reg when either has been requested).
1516 - If this is a Neon vector type with additional type information, fill
1517 in the struct pointed to by VECTYPE (if non-NULL).
1518 This function will fault on encountering a scalar. */
1521 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1522 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1524 struct neon_typed_alias atype
;
1526 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1531 /* Do not allow regname(... to parse as a register. */
1535 /* Do not allow a scalar (reg+index) to parse as a register. */
1536 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1538 first_error (_("register operand expected, but got scalar"));
1543 *vectype
= atype
.eltype
;
1550 #define NEON_SCALAR_REG(X) ((X) >> 4)
1551 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1553 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1554 have enough information to be able to do a good job bounds-checking. So, we
1555 just do easy checks here, and do further checks later. */
1558 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1562 struct neon_typed_alias atype
;
1564 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1566 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1569 if (atype
.index
== NEON_ALL_LANES
)
1571 first_error (_("scalar must have an index"));
1574 else if (atype
.index
>= 64 / elsize
)
1576 first_error (_("scalar index out of range"));
1581 *type
= atype
.eltype
;
1585 return reg
* 16 + atype
.index
;
1588 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1591 parse_reg_list (char ** strp
)
1593 char * str
= * strp
;
1597 /* We come back here if we get ranges concatenated by '+' or '|'. */
1600 skip_whitespace (str
);
1614 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1616 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1626 first_error (_("bad range in register list"));
1630 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1632 if (range
& (1 << i
))
1634 (_("Warning: duplicated register (r%d) in register list"),
1642 if (range
& (1 << reg
))
1643 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1645 else if (reg
<= cur_reg
)
1646 as_tsktsk (_("Warning: register range not in ascending order"));
1651 while (skip_past_comma (&str
) != FAIL
1652 || (in_range
= 1, *str
++ == '-'));
1655 if (skip_past_char (&str
, '}') == FAIL
)
1657 first_error (_("missing `}'"));
1665 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1668 if (exp
.X_op
== O_constant
)
1670 if (exp
.X_add_number
1671 != (exp
.X_add_number
& 0x0000ffff))
1673 inst
.error
= _("invalid register mask");
1677 if ((range
& exp
.X_add_number
) != 0)
1679 int regno
= range
& exp
.X_add_number
;
1682 regno
= (1 << regno
) - 1;
1684 (_("Warning: duplicated register (r%d) in register list"),
1688 range
|= exp
.X_add_number
;
1692 if (inst
.reloc
.type
!= 0)
1694 inst
.error
= _("expression too complex");
1698 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1699 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1700 inst
.reloc
.pc_rel
= 0;
1704 if (*str
== '|' || *str
== '+')
1710 while (another_range
);
1716 /* Types of registers in a list. */
1725 /* Parse a VFP register list. If the string is invalid return FAIL.
1726 Otherwise return the number of registers, and set PBASE to the first
1727 register. Parses registers of type ETYPE.
1728 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1729 - Q registers can be used to specify pairs of D registers
1730 - { } can be omitted from around a singleton register list
1731 FIXME: This is not implemented, as it would require backtracking in
1734 This could be done (the meaning isn't really ambiguous), but doesn't
1735 fit in well with the current parsing framework.
1736 - 32 D registers may be used (also true for VFPv3).
1737 FIXME: Types are ignored in these register lists, which is probably a
1741 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1746 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1750 unsigned long mask
= 0;
1753 if (skip_past_char (&str
, '{') == FAIL
)
1755 inst
.error
= _("expecting {");
1762 regtype
= REG_TYPE_VFS
;
1767 regtype
= REG_TYPE_VFD
;
1770 case REGLIST_NEON_D
:
1771 regtype
= REG_TYPE_NDQ
;
1775 if (etype
!= REGLIST_VFP_S
)
1777 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1778 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1782 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1785 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1792 base_reg
= max_regs
;
1796 int setmask
= 1, addregs
= 1;
1798 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1800 if (new_base
== FAIL
)
1802 first_error (_(reg_expected_msgs
[regtype
]));
1806 if (new_base
>= max_regs
)
1808 first_error (_("register out of range in list"));
1812 /* Note: a value of 2 * n is returned for the register Q<n>. */
1813 if (regtype
== REG_TYPE_NQ
)
1819 if (new_base
< base_reg
)
1820 base_reg
= new_base
;
1822 if (mask
& (setmask
<< new_base
))
1824 first_error (_("invalid register list"));
1828 if ((mask
>> new_base
) != 0 && ! warned
)
1830 as_tsktsk (_("register list not in ascending order"));
1834 mask
|= setmask
<< new_base
;
1837 if (*str
== '-') /* We have the start of a range expression */
1843 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1846 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1850 if (high_range
>= max_regs
)
1852 first_error (_("register out of range in list"));
1856 if (regtype
== REG_TYPE_NQ
)
1857 high_range
= high_range
+ 1;
1859 if (high_range
<= new_base
)
1861 inst
.error
= _("register range not in ascending order");
1865 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1867 if (mask
& (setmask
<< new_base
))
1869 inst
.error
= _("invalid register list");
1873 mask
|= setmask
<< new_base
;
1878 while (skip_past_comma (&str
) != FAIL
);
1882 /* Sanity check -- should have raised a parse error above. */
1883 if (count
== 0 || count
> max_regs
)
1888 /* Final test -- the registers must be consecutive. */
1890 for (i
= 0; i
< count
; i
++)
1892 if ((mask
& (1u << i
)) == 0)
1894 inst
.error
= _("non-contiguous register range");
1904 /* True if two alias types are the same. */
1907 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1915 if (a
->defined
!= b
->defined
)
1918 if ((a
->defined
& NTA_HASTYPE
) != 0
1919 && (a
->eltype
.type
!= b
->eltype
.type
1920 || a
->eltype
.size
!= b
->eltype
.size
))
1923 if ((a
->defined
& NTA_HASINDEX
) != 0
1924 && (a
->index
!= b
->index
))
1930 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1931 The base register is put in *PBASE.
1932 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1934 The register stride (minus one) is put in bit 4 of the return value.
1935 Bits [6:5] encode the list length (minus one).
1936 The type of the list elements is put in *ELTYPE, if non-NULL. */
1938 #define NEON_LANE(X) ((X) & 0xf)
1939 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1940 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1943 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1944 struct neon_type_el
*eltype
)
1951 int leading_brace
= 0;
1952 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1953 const char *const incr_error
= _("register stride must be 1 or 2");
1954 const char *const type_error
= _("mismatched element/structure types in list");
1955 struct neon_typed_alias firsttype
;
1957 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1962 struct neon_typed_alias atype
;
1963 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1967 first_error (_(reg_expected_msgs
[rtype
]));
1974 if (rtype
== REG_TYPE_NQ
)
1980 else if (reg_incr
== -1)
1982 reg_incr
= getreg
- base_reg
;
1983 if (reg_incr
< 1 || reg_incr
> 2)
1985 first_error (_(incr_error
));
1989 else if (getreg
!= base_reg
+ reg_incr
* count
)
1991 first_error (_(incr_error
));
1995 if (! neon_alias_types_same (&atype
, &firsttype
))
1997 first_error (_(type_error
));
2001 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2005 struct neon_typed_alias htype
;
2006 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2008 lane
= NEON_INTERLEAVE_LANES
;
2009 else if (lane
!= NEON_INTERLEAVE_LANES
)
2011 first_error (_(type_error
));
2016 else if (reg_incr
!= 1)
2018 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2022 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2025 first_error (_(reg_expected_msgs
[rtype
]));
2028 if (! neon_alias_types_same (&htype
, &firsttype
))
2030 first_error (_(type_error
));
2033 count
+= hireg
+ dregs
- getreg
;
2037 /* If we're using Q registers, we can't use [] or [n] syntax. */
2038 if (rtype
== REG_TYPE_NQ
)
2044 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2048 else if (lane
!= atype
.index
)
2050 first_error (_(type_error
));
2054 else if (lane
== -1)
2055 lane
= NEON_INTERLEAVE_LANES
;
2056 else if (lane
!= NEON_INTERLEAVE_LANES
)
2058 first_error (_(type_error
));
2063 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2065 /* No lane set by [x]. We must be interleaving structures. */
2067 lane
= NEON_INTERLEAVE_LANES
;
2070 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2071 || (count
> 1 && reg_incr
== -1))
2073 first_error (_("error parsing element/structure list"));
2077 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2079 first_error (_("expected }"));
2087 *eltype
= firsttype
.eltype
;
2092 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2095 /* Parse an explicit relocation suffix on an expression. This is
2096 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2097 arm_reloc_hsh contains no entries, so this function can only
2098 succeed if there is no () after the word. Returns -1 on error,
2099 BFD_RELOC_UNUSED if there wasn't any suffix. */
2102 parse_reloc (char **str
)
2104 struct reloc_entry
*r
;
2108 return BFD_RELOC_UNUSED
;
2113 while (*q
&& *q
!= ')' && *q
!= ',')
2118 if ((r
= (struct reloc_entry
*)
2119 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2126 /* Directives: register aliases. */
2128 static struct reg_entry
*
2129 insert_reg_alias (char *str
, unsigned number
, int type
)
2131 struct reg_entry
*new_reg
;
2134 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2136 if (new_reg
->builtin
)
2137 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2139 /* Only warn about a redefinition if it's not defined as the
2141 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2142 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2147 name
= xstrdup (str
);
2148 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2150 new_reg
->name
= name
;
2151 new_reg
->number
= number
;
2152 new_reg
->type
= type
;
2153 new_reg
->builtin
= FALSE
;
2154 new_reg
->neon
= NULL
;
2156 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2163 insert_neon_reg_alias (char *str
, int number
, int type
,
2164 struct neon_typed_alias
*atype
)
2166 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2170 first_error (_("attempt to redefine typed alias"));
2176 reg
->neon
= (struct neon_typed_alias
*)
2177 xmalloc (sizeof (struct neon_typed_alias
));
2178 *reg
->neon
= *atype
;
2182 /* Look for the .req directive. This is of the form:
2184 new_register_name .req existing_register_name
2186 If we find one, or if it looks sufficiently like one that we want to
2187 handle any error here, return TRUE. Otherwise return FALSE. */
2190 create_register_alias (char * newname
, char *p
)
2192 struct reg_entry
*old
;
2193 char *oldname
, *nbuf
;
2196 /* The input scrubber ensures that whitespace after the mnemonic is
2197 collapsed to single spaces. */
2199 if (strncmp (oldname
, " .req ", 6) != 0)
2203 if (*oldname
== '\0')
2206 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2209 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2213 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2214 the desired alias name, and p points to its end. If not, then
2215 the desired alias name is in the global original_case_string. */
2216 #ifdef TC_CASE_SENSITIVE
2219 newname
= original_case_string
;
2220 nlen
= strlen (newname
);
2223 nbuf
= (char *) alloca (nlen
+ 1);
2224 memcpy (nbuf
, newname
, nlen
);
2227 /* Create aliases under the new name as stated; an all-lowercase
2228 version of the new name; and an all-uppercase version of the new
2230 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2232 for (p
= nbuf
; *p
; p
++)
2235 if (strncmp (nbuf
, newname
, nlen
))
2237 /* If this attempt to create an additional alias fails, do not bother
2238 trying to create the all-lower case alias. We will fail and issue
2239 a second, duplicate error message. This situation arises when the
2240 programmer does something like:
2243 The second .req creates the "Foo" alias but then fails to create
2244 the artificial FOO alias because it has already been created by the
2246 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2250 for (p
= nbuf
; *p
; p
++)
2253 if (strncmp (nbuf
, newname
, nlen
))
2254 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2260 /* Create a Neon typed/indexed register alias using directives, e.g.:
2265 These typed registers can be used instead of the types specified after the
2266 Neon mnemonic, so long as all operands given have types. Types can also be
2267 specified directly, e.g.:
2268 vadd d0.s32, d1.s32, d2.s32 */
2271 create_neon_reg_alias (char *newname
, char *p
)
2273 enum arm_reg_type basetype
;
2274 struct reg_entry
*basereg
;
2275 struct reg_entry mybasereg
;
2276 struct neon_type ntype
;
2277 struct neon_typed_alias typeinfo
;
2278 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2281 typeinfo
.defined
= 0;
2282 typeinfo
.eltype
.type
= NT_invtype
;
2283 typeinfo
.eltype
.size
= -1;
2284 typeinfo
.index
= -1;
2288 if (strncmp (p
, " .dn ", 5) == 0)
2289 basetype
= REG_TYPE_VFD
;
2290 else if (strncmp (p
, " .qn ", 5) == 0)
2291 basetype
= REG_TYPE_NQ
;
2300 basereg
= arm_reg_parse_multi (&p
);
2302 if (basereg
&& basereg
->type
!= basetype
)
2304 as_bad (_("bad type for register"));
2308 if (basereg
== NULL
)
2311 /* Try parsing as an integer. */
2312 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2313 if (exp
.X_op
!= O_constant
)
2315 as_bad (_("expression must be constant"));
2318 basereg
= &mybasereg
;
2319 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2325 typeinfo
= *basereg
->neon
;
2327 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2329 /* We got a type. */
2330 if (typeinfo
.defined
& NTA_HASTYPE
)
2332 as_bad (_("can't redefine the type of a register alias"));
2336 typeinfo
.defined
|= NTA_HASTYPE
;
2337 if (ntype
.elems
!= 1)
2339 as_bad (_("you must specify a single type only"));
2342 typeinfo
.eltype
= ntype
.el
[0];
2345 if (skip_past_char (&p
, '[') == SUCCESS
)
2348 /* We got a scalar index. */
2350 if (typeinfo
.defined
& NTA_HASINDEX
)
2352 as_bad (_("can't redefine the index of a scalar alias"));
2356 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2358 if (exp
.X_op
!= O_constant
)
2360 as_bad (_("scalar index must be constant"));
2364 typeinfo
.defined
|= NTA_HASINDEX
;
2365 typeinfo
.index
= exp
.X_add_number
;
2367 if (skip_past_char (&p
, ']') == FAIL
)
2369 as_bad (_("expecting ]"));
2374 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2375 the desired alias name, and p points to its end. If not, then
2376 the desired alias name is in the global original_case_string. */
2377 #ifdef TC_CASE_SENSITIVE
2378 namelen
= nameend
- newname
;
2380 newname
= original_case_string
;
2381 namelen
= strlen (newname
);
2384 namebuf
= (char *) alloca (namelen
+ 1);
2385 strncpy (namebuf
, newname
, namelen
);
2386 namebuf
[namelen
] = '\0';
2388 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2389 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2391 /* Insert name in all uppercase. */
2392 for (p
= namebuf
; *p
; p
++)
2395 if (strncmp (namebuf
, newname
, namelen
))
2396 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2397 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2399 /* Insert name in all lowercase. */
2400 for (p
= namebuf
; *p
; p
++)
2403 if (strncmp (namebuf
, newname
, namelen
))
2404 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2405 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2410 /* Should never be called, as .req goes between the alias and the
2411 register name, not at the beginning of the line. */
2414 s_req (int a ATTRIBUTE_UNUSED
)
2416 as_bad (_("invalid syntax for .req directive"));
2420 s_dn (int a ATTRIBUTE_UNUSED
)
2422 as_bad (_("invalid syntax for .dn directive"));
2426 s_qn (int a ATTRIBUTE_UNUSED
)
2428 as_bad (_("invalid syntax for .qn directive"));
2431 /* The .unreq directive deletes an alias which was previously defined
2432 by .req. For example:
2438 s_unreq (int a ATTRIBUTE_UNUSED
)
2443 name
= input_line_pointer
;
2445 while (*input_line_pointer
!= 0
2446 && *input_line_pointer
!= ' '
2447 && *input_line_pointer
!= '\n')
2448 ++input_line_pointer
;
2450 saved_char
= *input_line_pointer
;
2451 *input_line_pointer
= 0;
2454 as_bad (_("invalid syntax for .unreq directive"));
2457 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2461 as_bad (_("unknown register alias '%s'"), name
);
2462 else if (reg
->builtin
)
2463 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2470 hash_delete (arm_reg_hsh
, name
, FALSE
);
2471 free ((char *) reg
->name
);
2476 /* Also locate the all upper case and all lower case versions.
2477 Do not complain if we cannot find one or the other as it
2478 was probably deleted above. */
2480 nbuf
= strdup (name
);
2481 for (p
= nbuf
; *p
; p
++)
2483 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2486 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2487 free ((char *) reg
->name
);
2493 for (p
= nbuf
; *p
; p
++)
2495 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2498 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2499 free ((char *) reg
->name
);
2509 *input_line_pointer
= saved_char
;
2510 demand_empty_rest_of_line ();
2513 /* Directives: Instruction set selection. */
2516 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2517 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2518 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2519 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2521 /* Create a new mapping symbol for the transition to STATE. */
2524 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2527 const char * symname
;
2534 type
= BSF_NO_FLAGS
;
2538 type
= BSF_NO_FLAGS
;
2542 type
= BSF_NO_FLAGS
;
2548 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2549 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2554 THUMB_SET_FUNC (symbolP
, 0);
2555 ARM_SET_THUMB (symbolP
, 0);
2556 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2560 THUMB_SET_FUNC (symbolP
, 1);
2561 ARM_SET_THUMB (symbolP
, 1);
2562 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2570 /* Save the mapping symbols for future reference. Also check that
2571 we do not place two mapping symbols at the same offset within a
2572 frag. We'll handle overlap between frags in
2573 check_mapping_symbols.
2575 If .fill or other data filling directive generates zero sized data,
2576 the mapping symbol for the following code will have the same value
2577 as the one generated for the data filling directive. In this case,
2578 we replace the old symbol with the new one at the same address. */
2581 if (frag
->tc_frag_data
.first_map
!= NULL
)
2583 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2584 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2586 frag
->tc_frag_data
.first_map
= symbolP
;
2588 if (frag
->tc_frag_data
.last_map
!= NULL
)
2590 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2591 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2592 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2594 frag
->tc_frag_data
.last_map
= symbolP
;
2597 /* We must sometimes convert a region marked as code to data during
2598 code alignment, if an odd number of bytes have to be padded. The
2599 code mapping symbol is pushed to an aligned address. */
2602 insert_data_mapping_symbol (enum mstate state
,
2603 valueT value
, fragS
*frag
, offsetT bytes
)
2605 /* If there was already a mapping symbol, remove it. */
2606 if (frag
->tc_frag_data
.last_map
!= NULL
2607 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2609 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2613 know (frag
->tc_frag_data
.first_map
== symp
);
2614 frag
->tc_frag_data
.first_map
= NULL
;
2616 frag
->tc_frag_data
.last_map
= NULL
;
2617 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2620 make_mapping_symbol (MAP_DATA
, value
, frag
);
2621 make_mapping_symbol (state
, value
+ bytes
, frag
);
2624 static void mapping_state_2 (enum mstate state
, int max_chars
);
2626 /* Set the mapping state to STATE. Only call this when about to
2627 emit some STATE bytes to the file. */
2630 mapping_state (enum mstate state
)
2632 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2634 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2636 if (mapstate
== state
)
2637 /* The mapping symbol has already been emitted.
2638 There is nothing else to do. */
2641 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2643 All ARM instructions require 4-byte alignment.
2644 (Almost) all Thumb instructions require 2-byte alignment.
2646 When emitting instructions into any section, mark the section
2649 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2650 but themselves require 2-byte alignment; this applies to some
2651 PC- relative forms. However, these cases will invovle implicit
2652 literal pool generation or an explicit .align >=2, both of
2653 which will cause the section to me marked with sufficient
2654 alignment. Thus, we don't handle those cases here. */
2655 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2657 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2658 /* This case will be evaluated later in the next else. */
2660 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2661 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2663 /* Only add the symbol if the offset is > 0:
2664 if we're at the first frag, check it's size > 0;
2665 if we're not at the first frag, then for sure
2666 the offset is > 0. */
2667 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2668 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2671 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2674 mapping_state_2 (state
, 0);
2678 /* Same as mapping_state, but MAX_CHARS bytes have already been
2679 allocated. Put the mapping symbol that far back. */
2682 mapping_state_2 (enum mstate state
, int max_chars
)
2684 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2686 if (!SEG_NORMAL (now_seg
))
2689 if (mapstate
== state
)
2690 /* The mapping symbol has already been emitted.
2691 There is nothing else to do. */
2694 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2695 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2698 #define mapping_state(x) ((void)0)
2699 #define mapping_state_2(x, y) ((void)0)
2702 /* Find the real, Thumb encoded start of a Thumb function. */
2706 find_real_start (symbolS
* symbolP
)
2709 const char * name
= S_GET_NAME (symbolP
);
2710 symbolS
* new_target
;
2712 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2713 #define STUB_NAME ".real_start_of"
2718 /* The compiler may generate BL instructions to local labels because
2719 it needs to perform a branch to a far away location. These labels
2720 do not have a corresponding ".real_start_of" label. We check
2721 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2722 the ".real_start_of" convention for nonlocal branches. */
2723 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2726 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2727 new_target
= symbol_find (real_start
);
2729 if (new_target
== NULL
)
2731 as_warn (_("Failed to find real start of function: %s\n"), name
);
2732 new_target
= symbolP
;
2740 opcode_select (int width
)
2747 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2748 as_bad (_("selected processor does not support THUMB opcodes"));
2751 /* No need to force the alignment, since we will have been
2752 coming from ARM mode, which is word-aligned. */
2753 record_alignment (now_seg
, 1);
2760 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2761 as_bad (_("selected processor does not support ARM opcodes"));
2766 frag_align (2, 0, 0);
2768 record_alignment (now_seg
, 1);
2773 as_bad (_("invalid instruction size selected (%d)"), width
);
2778 s_arm (int ignore ATTRIBUTE_UNUSED
)
2781 demand_empty_rest_of_line ();
2785 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2788 demand_empty_rest_of_line ();
2792 s_code (int unused ATTRIBUTE_UNUSED
)
2796 temp
= get_absolute_expression ();
2801 opcode_select (temp
);
2805 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2810 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2812 /* If we are not already in thumb mode go into it, EVEN if
2813 the target processor does not support thumb instructions.
2814 This is used by gcc/config/arm/lib1funcs.asm for example
2815 to compile interworking support functions even if the
2816 target processor should not support interworking. */
2820 record_alignment (now_seg
, 1);
2823 demand_empty_rest_of_line ();
2827 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2831 /* The following label is the name/address of the start of a Thumb function.
2832 We need to know this for the interworking support. */
2833 label_is_thumb_function_name
= TRUE
;
2836 /* Perform a .set directive, but also mark the alias as
2837 being a thumb function. */
2840 s_thumb_set (int equiv
)
2842 /* XXX the following is a duplicate of the code for s_set() in read.c
2843 We cannot just call that code as we need to get at the symbol that
2850 /* Especial apologies for the random logic:
2851 This just grew, and could be parsed much more simply!
2853 name
= input_line_pointer
;
2854 delim
= get_symbol_end ();
2855 end_name
= input_line_pointer
;
2858 if (*input_line_pointer
!= ',')
2861 as_bad (_("expected comma after name \"%s\""), name
);
2863 ignore_rest_of_line ();
2867 input_line_pointer
++;
2870 if (name
[0] == '.' && name
[1] == '\0')
2872 /* XXX - this should not happen to .thumb_set. */
2876 if ((symbolP
= symbol_find (name
)) == NULL
2877 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2880 /* When doing symbol listings, play games with dummy fragments living
2881 outside the normal fragment chain to record the file and line info
2883 if (listing
& LISTING_SYMBOLS
)
2885 extern struct list_info_struct
* listing_tail
;
2886 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2888 memset (dummy_frag
, 0, sizeof (fragS
));
2889 dummy_frag
->fr_type
= rs_fill
;
2890 dummy_frag
->line
= listing_tail
;
2891 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2892 dummy_frag
->fr_symbol
= symbolP
;
2896 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2899 /* "set" symbols are local unless otherwise specified. */
2900 SF_SET_LOCAL (symbolP
);
2901 #endif /* OBJ_COFF */
2902 } /* Make a new symbol. */
2904 symbol_table_insert (symbolP
);
2909 && S_IS_DEFINED (symbolP
)
2910 && S_GET_SEGMENT (symbolP
) != reg_section
)
2911 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2913 pseudo_set (symbolP
);
2915 demand_empty_rest_of_line ();
2917 /* XXX Now we come to the Thumb specific bit of code. */
2919 THUMB_SET_FUNC (symbolP
, 1);
2920 ARM_SET_THUMB (symbolP
, 1);
2921 #if defined OBJ_ELF || defined OBJ_COFF
2922 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2926 /* Directives: Mode selection. */
2928 /* .syntax [unified|divided] - choose the new unified syntax
2929 (same for Arm and Thumb encoding, modulo slight differences in what
2930 can be represented) or the old divergent syntax for each mode. */
2932 s_syntax (int unused ATTRIBUTE_UNUSED
)
2936 name
= input_line_pointer
;
2937 delim
= get_symbol_end ();
2939 if (!strcasecmp (name
, "unified"))
2940 unified_syntax
= TRUE
;
2941 else if (!strcasecmp (name
, "divided"))
2942 unified_syntax
= FALSE
;
2945 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2948 *input_line_pointer
= delim
;
2949 demand_empty_rest_of_line ();
2952 /* Directives: sectioning and alignment. */
2954 /* Same as s_align_ptwo but align 0 => align 2. */
2957 s_align (int unused ATTRIBUTE_UNUSED
)
2962 long max_alignment
= 15;
2964 temp
= get_absolute_expression ();
2965 if (temp
> max_alignment
)
2966 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2969 as_bad (_("alignment negative. 0 assumed."));
2973 if (*input_line_pointer
== ',')
2975 input_line_pointer
++;
2976 temp_fill
= get_absolute_expression ();
2988 /* Only make a frag if we HAVE to. */
2989 if (temp
&& !need_pass_2
)
2991 if (!fill_p
&& subseg_text_p (now_seg
))
2992 frag_align_code (temp
, 0);
2994 frag_align (temp
, (int) temp_fill
, 0);
2996 demand_empty_rest_of_line ();
2998 record_alignment (now_seg
, temp
);
3002 s_bss (int ignore ATTRIBUTE_UNUSED
)
3004 /* We don't support putting frags in the BSS segment, we fake it by
3005 marking in_bss, then looking at s_skip for clues. */
3006 subseg_set (bss_section
, 0);
3007 demand_empty_rest_of_line ();
3009 #ifdef md_elf_section_change_hook
3010 md_elf_section_change_hook ();
3015 s_even (int ignore ATTRIBUTE_UNUSED
)
3017 /* Never make frag if expect extra pass. */
3019 frag_align (1, 0, 0);
3021 record_alignment (now_seg
, 1);
3023 demand_empty_rest_of_line ();
3026 /* Directives: CodeComposer Studio. */
3028 /* .ref (for CodeComposer Studio syntax only). */
3030 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3032 if (codecomposer_syntax
)
3033 ignore_rest_of_line ();
3035 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3038 /* If name is not NULL, then it is used for marking the beginning of a
3039 function, wherease if it is NULL then it means the function end. */
3041 asmfunc_debug (const char * name
)
3043 static const char * last_name
= NULL
;
3047 gas_assert (last_name
== NULL
);
3050 if (debug_type
== DEBUG_STABS
)
3051 stabs_generate_asm_func (name
, name
);
3055 gas_assert (last_name
!= NULL
);
3057 if (debug_type
== DEBUG_STABS
)
3058 stabs_generate_asm_endfunc (last_name
, last_name
);
3065 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3067 if (codecomposer_syntax
)
3069 switch (asmfunc_state
)
3071 case OUTSIDE_ASMFUNC
:
3072 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3075 case WAITING_ASMFUNC_NAME
:
3076 as_bad (_(".asmfunc repeated."));
3079 case WAITING_ENDASMFUNC
:
3080 as_bad (_(".asmfunc without function."));
3083 demand_empty_rest_of_line ();
3086 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3090 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3092 if (codecomposer_syntax
)
3094 switch (asmfunc_state
)
3096 case OUTSIDE_ASMFUNC
:
3097 as_bad (_(".endasmfunc without a .asmfunc."));
3100 case WAITING_ASMFUNC_NAME
:
3101 as_bad (_(".endasmfunc without function."));
3104 case WAITING_ENDASMFUNC
:
3105 asmfunc_state
= OUTSIDE_ASMFUNC
;
3106 asmfunc_debug (NULL
);
3109 demand_empty_rest_of_line ();
3112 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3116 s_ccs_def (int name
)
3118 if (codecomposer_syntax
)
3121 as_bad (_(".def pseudo-op only available with -mccs flag."));
3124 /* Directives: Literal pools. */
3126 static literal_pool
*
3127 find_literal_pool (void)
3129 literal_pool
* pool
;
3131 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3133 if (pool
->section
== now_seg
3134 && pool
->sub_section
== now_subseg
)
3141 static literal_pool
*
3142 find_or_make_literal_pool (void)
3144 /* Next literal pool ID number. */
3145 static unsigned int latest_pool_num
= 1;
3146 literal_pool
* pool
;
3148 pool
= find_literal_pool ();
3152 /* Create a new pool. */
3153 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3157 pool
->next_free_entry
= 0;
3158 pool
->section
= now_seg
;
3159 pool
->sub_section
= now_subseg
;
3160 pool
->next
= list_of_pools
;
3161 pool
->symbol
= NULL
;
3163 /* Add it to the list. */
3164 list_of_pools
= pool
;
3167 /* New pools, and emptied pools, will have a NULL symbol. */
3168 if (pool
->symbol
== NULL
)
3170 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3171 (valueT
) 0, &zero_address_frag
);
3172 pool
->id
= latest_pool_num
++;
3179 /* Add the literal in the global 'inst'
3180 structure to the relevant literal pool. */
3183 add_to_lit_pool (void)
3185 literal_pool
* pool
;
3188 pool
= find_or_make_literal_pool ();
3190 /* Check if this literal value is already in the pool. */
3191 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3193 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3194 && (inst
.reloc
.exp
.X_op
== O_constant
)
3195 && (pool
->literals
[entry
].X_add_number
3196 == inst
.reloc
.exp
.X_add_number
)
3197 && (pool
->literals
[entry
].X_unsigned
3198 == inst
.reloc
.exp
.X_unsigned
))
3201 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3202 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3203 && (pool
->literals
[entry
].X_add_number
3204 == inst
.reloc
.exp
.X_add_number
)
3205 && (pool
->literals
[entry
].X_add_symbol
3206 == inst
.reloc
.exp
.X_add_symbol
)
3207 && (pool
->literals
[entry
].X_op_symbol
3208 == inst
.reloc
.exp
.X_op_symbol
))
3212 /* Do we need to create a new entry? */
3213 if (entry
== pool
->next_free_entry
)
3215 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3217 inst
.error
= _("literal pool overflow");
3221 pool
->literals
[entry
] = inst
.reloc
.exp
;
3223 /* PR ld/12974: Record the location of the first source line to reference
3224 this entry in the literal pool. If it turns out during linking that the
3225 symbol does not exist we will be able to give an accurate line number for
3226 the (first use of the) missing reference. */
3227 if (debug_type
== DEBUG_DWARF2
)
3228 dwarf2_where (pool
->locs
+ entry
);
3230 pool
->next_free_entry
+= 1;
3233 inst
.reloc
.exp
.X_op
= O_symbol
;
3234 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3235 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3241 tc_start_label_without_colon (char unused1 ATTRIBUTE_UNUSED
, const char * rest
)
3243 bfd_boolean ret
= TRUE
;
3245 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3247 const char *label
= rest
;
3249 while (!is_end_of_line
[(int) label
[-1]])
3254 as_bad (_("Invalid label '%s'"), label
);
3258 asmfunc_debug (label
);
3260 asmfunc_state
= WAITING_ENDASMFUNC
;
3266 /* Can't use symbol_new here, so have to create a symbol and then at
3267 a later date assign it a value. Thats what these functions do. */
3270 symbol_locate (symbolS
* symbolP
,
3271 const char * name
, /* It is copied, the caller can modify. */
3272 segT segment
, /* Segment identifier (SEG_<something>). */
3273 valueT valu
, /* Symbol value. */
3274 fragS
* frag
) /* Associated fragment. */
3276 unsigned int name_length
;
3277 char * preserved_copy_of_name
;
3279 name_length
= strlen (name
) + 1; /* +1 for \0. */
3280 obstack_grow (¬es
, name
, name_length
);
3281 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3283 #ifdef tc_canonicalize_symbol_name
3284 preserved_copy_of_name
=
3285 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3288 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3290 S_SET_SEGMENT (symbolP
, segment
);
3291 S_SET_VALUE (symbolP
, valu
);
3292 symbol_clear_list_pointers (symbolP
);
3294 symbol_set_frag (symbolP
, frag
);
3296 /* Link to end of symbol chain. */
3298 extern int symbol_table_frozen
;
3300 if (symbol_table_frozen
)
3304 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3306 obj_symbol_new_hook (symbolP
);
3308 #ifdef tc_symbol_new_hook
3309 tc_symbol_new_hook (symbolP
);
3313 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3314 #endif /* DEBUG_SYMS */
3319 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3322 literal_pool
* pool
;
3325 pool
= find_literal_pool ();
3327 || pool
->symbol
== NULL
3328 || pool
->next_free_entry
== 0)
3331 /* Align pool as you have word accesses.
3332 Only make a frag if we have to. */
3334 frag_align (2, 0, 0);
3336 record_alignment (now_seg
, 2);
3338 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3339 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3341 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3343 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3344 (valueT
) frag_now_fix (), frag_now
);
3345 symbol_table_insert (pool
->symbol
);
3347 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3349 #if defined OBJ_COFF || defined OBJ_ELF
3350 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3353 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3356 if (debug_type
== DEBUG_DWARF2
)
3357 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3359 /* First output the expression in the instruction to the pool. */
3360 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3363 /* Mark the pool as empty. */
3364 pool
->next_free_entry
= 0;
3365 pool
->symbol
= NULL
;
3369 /* Forward declarations for functions below, in the MD interface
3371 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3372 static valueT
create_unwind_entry (int);
3373 static void start_unwind_section (const segT
, int);
3374 static void add_unwind_opcode (valueT
, int);
3375 static void flush_pending_unwind (void);
3377 /* Directives: Data. */
3380 s_arm_elf_cons (int nbytes
)
3384 #ifdef md_flush_pending_output
3385 md_flush_pending_output ();
3388 if (is_it_end_of_statement ())
3390 demand_empty_rest_of_line ();
3394 #ifdef md_cons_align
3395 md_cons_align (nbytes
);
3398 mapping_state (MAP_DATA
);
3402 char *base
= input_line_pointer
;
3406 if (exp
.X_op
!= O_symbol
)
3407 emit_expr (&exp
, (unsigned int) nbytes
);
3410 char *before_reloc
= input_line_pointer
;
3411 reloc
= parse_reloc (&input_line_pointer
);
3414 as_bad (_("unrecognized relocation suffix"));
3415 ignore_rest_of_line ();
3418 else if (reloc
== BFD_RELOC_UNUSED
)
3419 emit_expr (&exp
, (unsigned int) nbytes
);
3422 reloc_howto_type
*howto
= (reloc_howto_type
*)
3423 bfd_reloc_type_lookup (stdoutput
,
3424 (bfd_reloc_code_real_type
) reloc
);
3425 int size
= bfd_get_reloc_size (howto
);
3427 if (reloc
== BFD_RELOC_ARM_PLT32
)
3429 as_bad (_("(plt) is only valid on branch targets"));
3430 reloc
= BFD_RELOC_UNUSED
;
3435 as_bad (_("%s relocations do not fit in %d bytes"),
3436 howto
->name
, nbytes
);
3439 /* We've parsed an expression stopping at O_symbol.
3440 But there may be more expression left now that we
3441 have parsed the relocation marker. Parse it again.
3442 XXX Surely there is a cleaner way to do this. */
3443 char *p
= input_line_pointer
;
3445 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3446 memcpy (save_buf
, base
, input_line_pointer
- base
);
3447 memmove (base
+ (input_line_pointer
- before_reloc
),
3448 base
, before_reloc
- base
);
3450 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3452 memcpy (base
, save_buf
, p
- base
);
3454 offset
= nbytes
- size
;
3455 p
= frag_more ((int) nbytes
);
3456 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3457 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3462 while (*input_line_pointer
++ == ',');
3464 /* Put terminator back into stream. */
3465 input_line_pointer
--;
3466 demand_empty_rest_of_line ();
3469 /* Emit an expression containing a 32-bit thumb instruction.
3470 Implementation based on put_thumb32_insn. */
3473 emit_thumb32_expr (expressionS
* exp
)
3475 expressionS exp_high
= *exp
;
3477 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3478 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3479 exp
->X_add_number
&= 0xffff;
3480 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3483 /* Guess the instruction size based on the opcode. */
3486 thumb_insn_size (int opcode
)
3488 if ((unsigned int) opcode
< 0xe800u
)
3490 else if ((unsigned int) opcode
>= 0xe8000000u
)
3497 emit_insn (expressionS
*exp
, int nbytes
)
3501 if (exp
->X_op
== O_constant
)
3506 size
= thumb_insn_size (exp
->X_add_number
);
3510 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3512 as_bad (_(".inst.n operand too big. "\
3513 "Use .inst.w instead"));
3518 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3519 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3521 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3523 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3524 emit_thumb32_expr (exp
);
3526 emit_expr (exp
, (unsigned int) size
);
3528 it_fsm_post_encode ();
3532 as_bad (_("cannot determine Thumb instruction size. " \
3533 "Use .inst.n/.inst.w instead"));
3536 as_bad (_("constant expression required"));
3541 /* Like s_arm_elf_cons but do not use md_cons_align and
3542 set the mapping state to MAP_ARM/MAP_THUMB. */
3545 s_arm_elf_inst (int nbytes
)
3547 if (is_it_end_of_statement ())
3549 demand_empty_rest_of_line ();
3553 /* Calling mapping_state () here will not change ARM/THUMB,
3554 but will ensure not to be in DATA state. */
3557 mapping_state (MAP_THUMB
);
3562 as_bad (_("width suffixes are invalid in ARM mode"));
3563 ignore_rest_of_line ();
3569 mapping_state (MAP_ARM
);
3578 if (! emit_insn (& exp
, nbytes
))
3580 ignore_rest_of_line ();
3584 while (*input_line_pointer
++ == ',');
3586 /* Put terminator back into stream. */
3587 input_line_pointer
--;
3588 demand_empty_rest_of_line ();
3591 /* Parse a .rel31 directive. */
3594 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3601 if (*input_line_pointer
== '1')
3602 highbit
= 0x80000000;
3603 else if (*input_line_pointer
!= '0')
3604 as_bad (_("expected 0 or 1"));
3606 input_line_pointer
++;
3607 if (*input_line_pointer
!= ',')
3608 as_bad (_("missing comma"));
3609 input_line_pointer
++;
3611 #ifdef md_flush_pending_output
3612 md_flush_pending_output ();
3615 #ifdef md_cons_align
3619 mapping_state (MAP_DATA
);
3624 md_number_to_chars (p
, highbit
, 4);
3625 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3626 BFD_RELOC_ARM_PREL31
);
3628 demand_empty_rest_of_line ();
3631 /* Directives: AEABI stack-unwind tables. */
3633 /* Parse an unwind_fnstart directive. Simply records the current location. */
3636 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3638 demand_empty_rest_of_line ();
3639 if (unwind
.proc_start
)
3641 as_bad (_("duplicate .fnstart directive"));
3645 /* Mark the start of the function. */
3646 unwind
.proc_start
= expr_build_dot ();
3648 /* Reset the rest of the unwind info. */
3649 unwind
.opcode_count
= 0;
3650 unwind
.table_entry
= NULL
;
3651 unwind
.personality_routine
= NULL
;
3652 unwind
.personality_index
= -1;
3653 unwind
.frame_size
= 0;
3654 unwind
.fp_offset
= 0;
3655 unwind
.fp_reg
= REG_SP
;
3657 unwind
.sp_restored
= 0;
3661 /* Parse a handlerdata directive. Creates the exception handling table entry
3662 for the function. */
3665 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3667 demand_empty_rest_of_line ();
3668 if (!unwind
.proc_start
)
3669 as_bad (MISSING_FNSTART
);
3671 if (unwind
.table_entry
)
3672 as_bad (_("duplicate .handlerdata directive"));
3674 create_unwind_entry (1);
3677 /* Parse an unwind_fnend directive. Generates the index table entry. */
3680 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3685 unsigned int marked_pr_dependency
;
3687 demand_empty_rest_of_line ();
3689 if (!unwind
.proc_start
)
3691 as_bad (_(".fnend directive without .fnstart"));
3695 /* Add eh table entry. */
3696 if (unwind
.table_entry
== NULL
)
3697 val
= create_unwind_entry (0);
3701 /* Add index table entry. This is two words. */
3702 start_unwind_section (unwind
.saved_seg
, 1);
3703 frag_align (2, 0, 0);
3704 record_alignment (now_seg
, 2);
3706 ptr
= frag_more (8);
3708 where
= frag_now_fix () - 8;
3710 /* Self relative offset of the function start. */
3711 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3712 BFD_RELOC_ARM_PREL31
);
3714 /* Indicate dependency on EHABI-defined personality routines to the
3715 linker, if it hasn't been done already. */
3716 marked_pr_dependency
3717 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3718 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3719 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3721 static const char *const name
[] =
3723 "__aeabi_unwind_cpp_pr0",
3724 "__aeabi_unwind_cpp_pr1",
3725 "__aeabi_unwind_cpp_pr2"
3727 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3728 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3729 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3730 |= 1 << unwind
.personality_index
;
3734 /* Inline exception table entry. */
3735 md_number_to_chars (ptr
+ 4, val
, 4);
3737 /* Self relative offset of the table entry. */
3738 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3739 BFD_RELOC_ARM_PREL31
);
3741 /* Restore the original section. */
3742 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3744 unwind
.proc_start
= NULL
;
3748 /* Parse an unwind_cantunwind directive. */
3751 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3753 demand_empty_rest_of_line ();
3754 if (!unwind
.proc_start
)
3755 as_bad (MISSING_FNSTART
);
3757 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3758 as_bad (_("personality routine specified for cantunwind frame"));
3760 unwind
.personality_index
= -2;
3764 /* Parse a personalityindex directive. */
3767 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3771 if (!unwind
.proc_start
)
3772 as_bad (MISSING_FNSTART
);
3774 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3775 as_bad (_("duplicate .personalityindex directive"));
3779 if (exp
.X_op
!= O_constant
3780 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3782 as_bad (_("bad personality routine number"));
3783 ignore_rest_of_line ();
3787 unwind
.personality_index
= exp
.X_add_number
;
3789 demand_empty_rest_of_line ();
3793 /* Parse a personality directive. */
3796 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3800 if (!unwind
.proc_start
)
3801 as_bad (MISSING_FNSTART
);
3803 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3804 as_bad (_("duplicate .personality directive"));
3806 name
= input_line_pointer
;
3807 c
= get_symbol_end ();
3808 p
= input_line_pointer
;
3809 unwind
.personality_routine
= symbol_find_or_make (name
);
3811 demand_empty_rest_of_line ();
3815 /* Parse a directive saving core registers. */
3818 s_arm_unwind_save_core (void)
3824 range
= parse_reg_list (&input_line_pointer
);
3827 as_bad (_("expected register list"));
3828 ignore_rest_of_line ();
3832 demand_empty_rest_of_line ();
3834 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3835 into .unwind_save {..., sp...}. We aren't bothered about the value of
3836 ip because it is clobbered by calls. */
3837 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3838 && (range
& 0x3000) == 0x1000)
3840 unwind
.opcode_count
--;
3841 unwind
.sp_restored
= 0;
3842 range
= (range
| 0x2000) & ~0x1000;
3843 unwind
.pending_offset
= 0;
3849 /* See if we can use the short opcodes. These pop a block of up to 8
3850 registers starting with r4, plus maybe r14. */
3851 for (n
= 0; n
< 8; n
++)
3853 /* Break at the first non-saved register. */
3854 if ((range
& (1 << (n
+ 4))) == 0)
3857 /* See if there are any other bits set. */
3858 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3860 /* Use the long form. */
3861 op
= 0x8000 | ((range
>> 4) & 0xfff);
3862 add_unwind_opcode (op
, 2);
3866 /* Use the short form. */
3868 op
= 0xa8; /* Pop r14. */
3870 op
= 0xa0; /* Do not pop r14. */
3872 add_unwind_opcode (op
, 1);
3879 op
= 0xb100 | (range
& 0xf);
3880 add_unwind_opcode (op
, 2);
3883 /* Record the number of bytes pushed. */
3884 for (n
= 0; n
< 16; n
++)
3886 if (range
& (1 << n
))
3887 unwind
.frame_size
+= 4;
3892 /* Parse a directive saving FPA registers. */
3895 s_arm_unwind_save_fpa (int reg
)
3901 /* Get Number of registers to transfer. */
3902 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3905 exp
.X_op
= O_illegal
;
3907 if (exp
.X_op
!= O_constant
)
3909 as_bad (_("expected , <constant>"));
3910 ignore_rest_of_line ();
3914 num_regs
= exp
.X_add_number
;
3916 if (num_regs
< 1 || num_regs
> 4)
3918 as_bad (_("number of registers must be in the range [1:4]"));
3919 ignore_rest_of_line ();
3923 demand_empty_rest_of_line ();
3928 op
= 0xb4 | (num_regs
- 1);
3929 add_unwind_opcode (op
, 1);
3934 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3935 add_unwind_opcode (op
, 2);
3937 unwind
.frame_size
+= num_regs
* 12;
3941 /* Parse a directive saving VFP registers for ARMv6 and above. */
3944 s_arm_unwind_save_vfp_armv6 (void)
3949 int num_vfpv3_regs
= 0;
3950 int num_regs_below_16
;
3952 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3955 as_bad (_("expected register list"));
3956 ignore_rest_of_line ();
3960 demand_empty_rest_of_line ();
3962 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3963 than FSTMX/FLDMX-style ones). */
3965 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3967 num_vfpv3_regs
= count
;
3968 else if (start
+ count
> 16)
3969 num_vfpv3_regs
= start
+ count
- 16;
3971 if (num_vfpv3_regs
> 0)
3973 int start_offset
= start
> 16 ? start
- 16 : 0;
3974 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3975 add_unwind_opcode (op
, 2);
3978 /* Generate opcode for registers numbered in the range 0 .. 15. */
3979 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3980 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3981 if (num_regs_below_16
> 0)
3983 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3984 add_unwind_opcode (op
, 2);
3987 unwind
.frame_size
+= count
* 8;
3991 /* Parse a directive saving VFP registers for pre-ARMv6. */
3994 s_arm_unwind_save_vfp (void)
4000 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4003 as_bad (_("expected register list"));
4004 ignore_rest_of_line ();
4008 demand_empty_rest_of_line ();
4013 op
= 0xb8 | (count
- 1);
4014 add_unwind_opcode (op
, 1);
4019 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4020 add_unwind_opcode (op
, 2);
4022 unwind
.frame_size
+= count
* 8 + 4;
4026 /* Parse a directive saving iWMMXt data registers. */
4029 s_arm_unwind_save_mmxwr (void)
4037 if (*input_line_pointer
== '{')
4038 input_line_pointer
++;
4042 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4046 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4051 as_tsktsk (_("register list not in ascending order"));
4054 if (*input_line_pointer
== '-')
4056 input_line_pointer
++;
4057 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4060 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4063 else if (reg
>= hi_reg
)
4065 as_bad (_("bad register range"));
4068 for (; reg
< hi_reg
; reg
++)
4072 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4074 skip_past_char (&input_line_pointer
, '}');
4076 demand_empty_rest_of_line ();
4078 /* Generate any deferred opcodes because we're going to be looking at
4080 flush_pending_unwind ();
4082 for (i
= 0; i
< 16; i
++)
4084 if (mask
& (1 << i
))
4085 unwind
.frame_size
+= 8;
4088 /* Attempt to combine with a previous opcode. We do this because gcc
4089 likes to output separate unwind directives for a single block of
4091 if (unwind
.opcode_count
> 0)
4093 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4094 if ((i
& 0xf8) == 0xc0)
4097 /* Only merge if the blocks are contiguous. */
4100 if ((mask
& 0xfe00) == (1 << 9))
4102 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4103 unwind
.opcode_count
--;
4106 else if (i
== 6 && unwind
.opcode_count
>= 2)
4108 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4112 op
= 0xffff << (reg
- 1);
4114 && ((mask
& op
) == (1u << (reg
- 1))))
4116 op
= (1 << (reg
+ i
+ 1)) - 1;
4117 op
&= ~((1 << reg
) - 1);
4119 unwind
.opcode_count
-= 2;
4126 /* We want to generate opcodes in the order the registers have been
4127 saved, ie. descending order. */
4128 for (reg
= 15; reg
>= -1; reg
--)
4130 /* Save registers in blocks. */
4132 || !(mask
& (1 << reg
)))
4134 /* We found an unsaved reg. Generate opcodes to save the
4141 op
= 0xc0 | (hi_reg
- 10);
4142 add_unwind_opcode (op
, 1);
4147 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4148 add_unwind_opcode (op
, 2);
4157 ignore_rest_of_line ();
4161 s_arm_unwind_save_mmxwcg (void)
4168 if (*input_line_pointer
== '{')
4169 input_line_pointer
++;
4171 skip_whitespace (input_line_pointer
);
4175 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4179 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4185 as_tsktsk (_("register list not in ascending order"));
4188 if (*input_line_pointer
== '-')
4190 input_line_pointer
++;
4191 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4194 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4197 else if (reg
>= hi_reg
)
4199 as_bad (_("bad register range"));
4202 for (; reg
< hi_reg
; reg
++)
4206 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4208 skip_past_char (&input_line_pointer
, '}');
4210 demand_empty_rest_of_line ();
4212 /* Generate any deferred opcodes because we're going to be looking at
4214 flush_pending_unwind ();
4216 for (reg
= 0; reg
< 16; reg
++)
4218 if (mask
& (1 << reg
))
4219 unwind
.frame_size
+= 4;
4222 add_unwind_opcode (op
, 2);
4225 ignore_rest_of_line ();
4229 /* Parse an unwind_save directive.
4230 If the argument is non-zero, this is a .vsave directive. */
4233 s_arm_unwind_save (int arch_v6
)
4236 struct reg_entry
*reg
;
4237 bfd_boolean had_brace
= FALSE
;
4239 if (!unwind
.proc_start
)
4240 as_bad (MISSING_FNSTART
);
4242 /* Figure out what sort of save we have. */
4243 peek
= input_line_pointer
;
4251 reg
= arm_reg_parse_multi (&peek
);
4255 as_bad (_("register expected"));
4256 ignore_rest_of_line ();
4265 as_bad (_("FPA .unwind_save does not take a register list"));
4266 ignore_rest_of_line ();
4269 input_line_pointer
= peek
;
4270 s_arm_unwind_save_fpa (reg
->number
);
4274 s_arm_unwind_save_core ();
4279 s_arm_unwind_save_vfp_armv6 ();
4281 s_arm_unwind_save_vfp ();
4284 case REG_TYPE_MMXWR
:
4285 s_arm_unwind_save_mmxwr ();
4288 case REG_TYPE_MMXWCG
:
4289 s_arm_unwind_save_mmxwcg ();
4293 as_bad (_(".unwind_save does not support this kind of register"));
4294 ignore_rest_of_line ();
4299 /* Parse an unwind_movsp directive. */
4302 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4308 if (!unwind
.proc_start
)
4309 as_bad (MISSING_FNSTART
);
4311 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4314 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4315 ignore_rest_of_line ();
4319 /* Optional constant. */
4320 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4322 if (immediate_for_directive (&offset
) == FAIL
)
4328 demand_empty_rest_of_line ();
4330 if (reg
== REG_SP
|| reg
== REG_PC
)
4332 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4336 if (unwind
.fp_reg
!= REG_SP
)
4337 as_bad (_("unexpected .unwind_movsp directive"));
4339 /* Generate opcode to restore the value. */
4341 add_unwind_opcode (op
, 1);
4343 /* Record the information for later. */
4344 unwind
.fp_reg
= reg
;
4345 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4346 unwind
.sp_restored
= 1;
4349 /* Parse an unwind_pad directive. */
4352 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4356 if (!unwind
.proc_start
)
4357 as_bad (MISSING_FNSTART
);
4359 if (immediate_for_directive (&offset
) == FAIL
)
4364 as_bad (_("stack increment must be multiple of 4"));
4365 ignore_rest_of_line ();
4369 /* Don't generate any opcodes, just record the details for later. */
4370 unwind
.frame_size
+= offset
;
4371 unwind
.pending_offset
+= offset
;
4373 demand_empty_rest_of_line ();
4376 /* Parse an unwind_setfp directive. */
4379 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4385 if (!unwind
.proc_start
)
4386 as_bad (MISSING_FNSTART
);
4388 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4389 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4392 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4394 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4396 as_bad (_("expected <reg>, <reg>"));
4397 ignore_rest_of_line ();
4401 /* Optional constant. */
4402 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4404 if (immediate_for_directive (&offset
) == FAIL
)
4410 demand_empty_rest_of_line ();
4412 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4414 as_bad (_("register must be either sp or set by a previous"
4415 "unwind_movsp directive"));
4419 /* Don't generate any opcodes, just record the information for later. */
4420 unwind
.fp_reg
= fp_reg
;
4422 if (sp_reg
== REG_SP
)
4423 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4425 unwind
.fp_offset
-= offset
;
4428 /* Parse an unwind_raw directive. */
4431 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4434 /* This is an arbitrary limit. */
4435 unsigned char op
[16];
4438 if (!unwind
.proc_start
)
4439 as_bad (MISSING_FNSTART
);
4442 if (exp
.X_op
== O_constant
4443 && skip_past_comma (&input_line_pointer
) != FAIL
)
4445 unwind
.frame_size
+= exp
.X_add_number
;
4449 exp
.X_op
= O_illegal
;
4451 if (exp
.X_op
!= O_constant
)
4453 as_bad (_("expected <offset>, <opcode>"));
4454 ignore_rest_of_line ();
4460 /* Parse the opcode. */
4465 as_bad (_("unwind opcode too long"));
4466 ignore_rest_of_line ();
4468 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4470 as_bad (_("invalid unwind opcode"));
4471 ignore_rest_of_line ();
4474 op
[count
++] = exp
.X_add_number
;
4476 /* Parse the next byte. */
4477 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4483 /* Add the opcode bytes in reverse order. */
4485 add_unwind_opcode (op
[count
], 1);
4487 demand_empty_rest_of_line ();
4491 /* Parse a .eabi_attribute directive. */
4494 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4496 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4498 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4499 attributes_set_explicitly
[tag
] = 1;
4502 /* Emit a tls fix for the symbol. */
4505 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4509 #ifdef md_flush_pending_output
4510 md_flush_pending_output ();
4513 #ifdef md_cons_align
4517 /* Since we're just labelling the code, there's no need to define a
4520 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4521 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4522 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4523 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4525 #endif /* OBJ_ELF */
4527 static void s_arm_arch (int);
4528 static void s_arm_object_arch (int);
4529 static void s_arm_cpu (int);
4530 static void s_arm_fpu (int);
4531 static void s_arm_arch_extension (int);
4536 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4543 if (exp
.X_op
== O_symbol
)
4544 exp
.X_op
= O_secrel
;
4546 emit_expr (&exp
, 4);
4548 while (*input_line_pointer
++ == ',');
4550 input_line_pointer
--;
4551 demand_empty_rest_of_line ();
4555 /* This table describes all the machine specific pseudo-ops the assembler
4556 has to support. The fields are:
4557 pseudo-op name without dot
4558 function to call to execute this pseudo-op
4559 Integer arg to pass to the function. */
4561 const pseudo_typeS md_pseudo_table
[] =
4563 /* Never called because '.req' does not start a line. */
4564 { "req", s_req
, 0 },
4565 /* Following two are likewise never called. */
4568 { "unreq", s_unreq
, 0 },
4569 { "bss", s_bss
, 0 },
4570 { "align", s_align
, 0 },
4571 { "arm", s_arm
, 0 },
4572 { "thumb", s_thumb
, 0 },
4573 { "code", s_code
, 0 },
4574 { "force_thumb", s_force_thumb
, 0 },
4575 { "thumb_func", s_thumb_func
, 0 },
4576 { "thumb_set", s_thumb_set
, 0 },
4577 { "even", s_even
, 0 },
4578 { "ltorg", s_ltorg
, 0 },
4579 { "pool", s_ltorg
, 0 },
4580 { "syntax", s_syntax
, 0 },
4581 { "cpu", s_arm_cpu
, 0 },
4582 { "arch", s_arm_arch
, 0 },
4583 { "object_arch", s_arm_object_arch
, 0 },
4584 { "fpu", s_arm_fpu
, 0 },
4585 { "arch_extension", s_arm_arch_extension
, 0 },
4587 { "word", s_arm_elf_cons
, 4 },
4588 { "long", s_arm_elf_cons
, 4 },
4589 { "inst.n", s_arm_elf_inst
, 2 },
4590 { "inst.w", s_arm_elf_inst
, 4 },
4591 { "inst", s_arm_elf_inst
, 0 },
4592 { "rel31", s_arm_rel31
, 0 },
4593 { "fnstart", s_arm_unwind_fnstart
, 0 },
4594 { "fnend", s_arm_unwind_fnend
, 0 },
4595 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4596 { "personality", s_arm_unwind_personality
, 0 },
4597 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4598 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4599 { "save", s_arm_unwind_save
, 0 },
4600 { "vsave", s_arm_unwind_save
, 1 },
4601 { "movsp", s_arm_unwind_movsp
, 0 },
4602 { "pad", s_arm_unwind_pad
, 0 },
4603 { "setfp", s_arm_unwind_setfp
, 0 },
4604 { "unwind_raw", s_arm_unwind_raw
, 0 },
4605 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4606 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4610 /* These are used for dwarf. */
4614 /* These are used for dwarf2. */
4615 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4616 { "loc", dwarf2_directive_loc
, 0 },
4617 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4619 { "extend", float_cons
, 'x' },
4620 { "ldouble", float_cons
, 'x' },
4621 { "packed", float_cons
, 'p' },
4623 {"secrel32", pe_directive_secrel
, 0},
4626 /* These are for compatibility with CodeComposer Studio. */
4627 {"ref", s_ccs_ref
, 0},
4628 {"def", s_ccs_def
, 0},
4629 {"asmfunc", s_ccs_asmfunc
, 0},
4630 {"endasmfunc", s_ccs_endasmfunc
, 0},
4635 /* Parser functions used exclusively in instruction operands. */
4637 /* Generic immediate-value read function for use in insn parsing.
4638 STR points to the beginning of the immediate (the leading #);
4639 VAL receives the value; if the value is outside [MIN, MAX]
4640 issue an error. PREFIX_OPT is true if the immediate prefix is
4644 parse_immediate (char **str
, int *val
, int min
, int max
,
4645 bfd_boolean prefix_opt
)
4648 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4649 if (exp
.X_op
!= O_constant
)
4651 inst
.error
= _("constant expression required");
4655 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4657 inst
.error
= _("immediate value out of range");
4661 *val
= exp
.X_add_number
;
4665 /* Less-generic immediate-value read function with the possibility of loading a
4666 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4667 instructions. Puts the result directly in inst.operands[i]. */
4670 parse_big_immediate (char **str
, int i
)
4675 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4677 if (exp
.X_op
== O_constant
)
4679 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4680 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4681 O_constant. We have to be careful not to break compilation for
4682 32-bit X_add_number, though. */
4683 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4685 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4686 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4687 inst
.operands
[i
].regisimm
= 1;
4690 else if (exp
.X_op
== O_big
4691 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4693 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4695 /* Bignums have their least significant bits in
4696 generic_bignum[0]. Make sure we put 32 bits in imm and
4697 32 bits in reg, in a (hopefully) portable way. */
4698 gas_assert (parts
!= 0);
4700 /* Make sure that the number is not too big.
4701 PR 11972: Bignums can now be sign-extended to the
4702 size of a .octa so check that the out of range bits
4703 are all zero or all one. */
4704 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4706 LITTLENUM_TYPE m
= -1;
4708 if (generic_bignum
[parts
* 2] != 0
4709 && generic_bignum
[parts
* 2] != m
)
4712 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4713 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4717 inst
.operands
[i
].imm
= 0;
4718 for (j
= 0; j
< parts
; j
++, idx
++)
4719 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4720 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4721 inst
.operands
[i
].reg
= 0;
4722 for (j
= 0; j
< parts
; j
++, idx
++)
4723 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4724 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4725 inst
.operands
[i
].regisimm
= 1;
4735 /* Returns the pseudo-register number of an FPA immediate constant,
4736 or FAIL if there isn't a valid constant here. */
4739 parse_fpa_immediate (char ** str
)
4741 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4747 /* First try and match exact strings, this is to guarantee
4748 that some formats will work even for cross assembly. */
4750 for (i
= 0; fp_const
[i
]; i
++)
4752 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4756 *str
+= strlen (fp_const
[i
]);
4757 if (is_end_of_line
[(unsigned char) **str
])
4763 /* Just because we didn't get a match doesn't mean that the constant
4764 isn't valid, just that it is in a format that we don't
4765 automatically recognize. Try parsing it with the standard
4766 expression routines. */
4768 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4770 /* Look for a raw floating point number. */
4771 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4772 && is_end_of_line
[(unsigned char) *save_in
])
4774 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4776 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4778 if (words
[j
] != fp_values
[i
][j
])
4782 if (j
== MAX_LITTLENUMS
)
4790 /* Try and parse a more complex expression, this will probably fail
4791 unless the code uses a floating point prefix (eg "0f"). */
4792 save_in
= input_line_pointer
;
4793 input_line_pointer
= *str
;
4794 if (expression (&exp
) == absolute_section
4795 && exp
.X_op
== O_big
4796 && exp
.X_add_number
< 0)
4798 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4800 if (gen_to_words (words
, 5, (long) 15) == 0)
4802 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4804 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4806 if (words
[j
] != fp_values
[i
][j
])
4810 if (j
== MAX_LITTLENUMS
)
4812 *str
= input_line_pointer
;
4813 input_line_pointer
= save_in
;
4820 *str
= input_line_pointer
;
4821 input_line_pointer
= save_in
;
4822 inst
.error
= _("invalid FPA immediate expression");
4826 /* Returns 1 if a number has "quarter-precision" float format
4827 0baBbbbbbc defgh000 00000000 00000000. */
4830 is_quarter_float (unsigned imm
)
4832 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4833 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4836 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4837 0baBbbbbbc defgh000 00000000 00000000.
4838 The zero and minus-zero cases need special handling, since they can't be
4839 encoded in the "quarter-precision" float format, but can nonetheless be
4840 loaded as integer constants. */
4843 parse_qfloat_immediate (char **ccp
, int *immed
)
4847 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4848 int found_fpchar
= 0;
4850 skip_past_char (&str
, '#');
4852 /* We must not accidentally parse an integer as a floating-point number. Make
4853 sure that the value we parse is not an integer by checking for special
4854 characters '.' or 'e'.
4855 FIXME: This is a horrible hack, but doing better is tricky because type
4856 information isn't in a very usable state at parse time. */
4858 skip_whitespace (fpnum
);
4860 if (strncmp (fpnum
, "0x", 2) == 0)
4864 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4865 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4875 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4877 unsigned fpword
= 0;
4880 /* Our FP word must be 32 bits (single-precision FP). */
4881 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4883 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4887 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4900 /* Shift operands. */
4903 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4906 struct asm_shift_name
4909 enum shift_kind kind
;
4912 /* Third argument to parse_shift. */
4913 enum parse_shift_mode
4915 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4916 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4917 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4918 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4919 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4922 /* Parse a <shift> specifier on an ARM data processing instruction.
4923 This has three forms:
4925 (LSL|LSR|ASL|ASR|ROR) Rs
4926 (LSL|LSR|ASL|ASR|ROR) #imm
4929 Note that ASL is assimilated to LSL in the instruction encoding, and
4930 RRX to ROR #0 (which cannot be written as such). */
4933 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4935 const struct asm_shift_name
*shift_name
;
4936 enum shift_kind shift
;
4941 for (p
= *str
; ISALPHA (*p
); p
++)
4946 inst
.error
= _("shift expression expected");
4950 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4953 if (shift_name
== NULL
)
4955 inst
.error
= _("shift expression expected");
4959 shift
= shift_name
->kind
;
4963 case NO_SHIFT_RESTRICT
:
4964 case SHIFT_IMMEDIATE
: break;
4966 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4967 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4969 inst
.error
= _("'LSL' or 'ASR' required");
4974 case SHIFT_LSL_IMMEDIATE
:
4975 if (shift
!= SHIFT_LSL
)
4977 inst
.error
= _("'LSL' required");
4982 case SHIFT_ASR_IMMEDIATE
:
4983 if (shift
!= SHIFT_ASR
)
4985 inst
.error
= _("'ASR' required");
4993 if (shift
!= SHIFT_RRX
)
4995 /* Whitespace can appear here if the next thing is a bare digit. */
4996 skip_whitespace (p
);
4998 if (mode
== NO_SHIFT_RESTRICT
4999 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5001 inst
.operands
[i
].imm
= reg
;
5002 inst
.operands
[i
].immisreg
= 1;
5004 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5007 inst
.operands
[i
].shift_kind
= shift
;
5008 inst
.operands
[i
].shifted
= 1;
5013 /* Parse a <shifter_operand> for an ARM data processing instruction:
5016 #<immediate>, <rotate>
5020 where <shift> is defined by parse_shift above, and <rotate> is a
5021 multiple of 2 between 0 and 30. Validation of immediate operands
5022 is deferred to md_apply_fix. */
5025 parse_shifter_operand (char **str
, int i
)
5030 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5032 inst
.operands
[i
].reg
= value
;
5033 inst
.operands
[i
].isreg
= 1;
5035 /* parse_shift will override this if appropriate */
5036 inst
.reloc
.exp
.X_op
= O_constant
;
5037 inst
.reloc
.exp
.X_add_number
= 0;
5039 if (skip_past_comma (str
) == FAIL
)
5042 /* Shift operation on register. */
5043 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5046 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5049 if (skip_past_comma (str
) == SUCCESS
)
5051 /* #x, y -- ie explicit rotation by Y. */
5052 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5055 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5057 inst
.error
= _("constant expression expected");
5061 value
= exp
.X_add_number
;
5062 if (value
< 0 || value
> 30 || value
% 2 != 0)
5064 inst
.error
= _("invalid rotation");
5067 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5069 inst
.error
= _("invalid constant");
5073 /* Encode as specified. */
5074 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5078 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5079 inst
.reloc
.pc_rel
= 0;
5083 /* Group relocation information. Each entry in the table contains the
5084 textual name of the relocation as may appear in assembler source
5085 and must end with a colon.
5086 Along with this textual name are the relocation codes to be used if
5087 the corresponding instruction is an ALU instruction (ADD or SUB only),
5088 an LDR, an LDRS, or an LDC. */
5090 struct group_reloc_table_entry
5101 /* Varieties of non-ALU group relocation. */
5108 static struct group_reloc_table_entry group_reloc_table
[] =
5109 { /* Program counter relative: */
5111 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5116 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5117 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5118 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5119 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5121 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5126 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5127 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5128 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5129 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5131 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5132 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5133 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5134 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5135 /* Section base relative */
5137 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5142 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5143 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5144 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5145 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5147 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5152 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5153 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5154 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5155 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5157 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5158 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5159 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5160 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
5162 /* Given the address of a pointer pointing to the textual name of a group
5163 relocation as may appear in assembler source, attempt to find its details
5164 in group_reloc_table. The pointer will be updated to the character after
5165 the trailing colon. On failure, FAIL will be returned; SUCCESS
5166 otherwise. On success, *entry will be updated to point at the relevant
5167 group_reloc_table entry. */
5170 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5173 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5175 int length
= strlen (group_reloc_table
[i
].name
);
5177 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5178 && (*str
)[length
] == ':')
5180 *out
= &group_reloc_table
[i
];
5181 *str
+= (length
+ 1);
5189 /* Parse a <shifter_operand> for an ARM data processing instruction
5190 (as for parse_shifter_operand) where group relocations are allowed:
5193 #<immediate>, <rotate>
5194 #:<group_reloc>:<expression>
5198 where <group_reloc> is one of the strings defined in group_reloc_table.
5199 The hashes are optional.
5201 Everything else is as for parse_shifter_operand. */
5203 static parse_operand_result
5204 parse_shifter_operand_group_reloc (char **str
, int i
)
5206 /* Determine if we have the sequence of characters #: or just :
5207 coming next. If we do, then we check for a group relocation.
5208 If we don't, punt the whole lot to parse_shifter_operand. */
5210 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5211 || (*str
)[0] == ':')
5213 struct group_reloc_table_entry
*entry
;
5215 if ((*str
)[0] == '#')
5220 /* Try to parse a group relocation. Anything else is an error. */
5221 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5223 inst
.error
= _("unknown group relocation");
5224 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5227 /* We now have the group relocation table entry corresponding to
5228 the name in the assembler source. Next, we parse the expression. */
5229 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5230 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5232 /* Record the relocation type (always the ALU variant here). */
5233 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5234 gas_assert (inst
.reloc
.type
!= 0);
5236 return PARSE_OPERAND_SUCCESS
;
5239 return parse_shifter_operand (str
, i
) == SUCCESS
5240 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5242 /* Never reached. */
5245 /* Parse a Neon alignment expression. Information is written to
5246 inst.operands[i]. We assume the initial ':' has been skipped.
5248 align .imm = align << 8, .immisalign=1, .preind=0 */
5249 static parse_operand_result
5250 parse_neon_alignment (char **str
, int i
)
5255 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5257 if (exp
.X_op
!= O_constant
)
5259 inst
.error
= _("alignment must be constant");
5260 return PARSE_OPERAND_FAIL
;
5263 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5264 inst
.operands
[i
].immisalign
= 1;
5265 /* Alignments are not pre-indexes. */
5266 inst
.operands
[i
].preind
= 0;
5269 return PARSE_OPERAND_SUCCESS
;
5272 /* Parse all forms of an ARM address expression. Information is written
5273 to inst.operands[i] and/or inst.reloc.
5275 Preindexed addressing (.preind=1):
5277 [Rn, #offset] .reg=Rn .reloc.exp=offset
5278 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5279 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5280 .shift_kind=shift .reloc.exp=shift_imm
5282 These three may have a trailing ! which causes .writeback to be set also.
5284 Postindexed addressing (.postind=1, .writeback=1):
5286 [Rn], #offset .reg=Rn .reloc.exp=offset
5287 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5288 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5289 .shift_kind=shift .reloc.exp=shift_imm
5291 Unindexed addressing (.preind=0, .postind=0):
5293 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5297 [Rn]{!} shorthand for [Rn,#0]{!}
5298 =immediate .isreg=0 .reloc.exp=immediate
5299 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5301 It is the caller's responsibility to check for addressing modes not
5302 supported by the instruction, and to set inst.reloc.type. */
5304 static parse_operand_result
5305 parse_address_main (char **str
, int i
, int group_relocations
,
5306 group_reloc_type group_type
)
5311 if (skip_past_char (&p
, '[') == FAIL
)
5313 if (skip_past_char (&p
, '=') == FAIL
)
5315 /* Bare address - translate to PC-relative offset. */
5316 inst
.reloc
.pc_rel
= 1;
5317 inst
.operands
[i
].reg
= REG_PC
;
5318 inst
.operands
[i
].isreg
= 1;
5319 inst
.operands
[i
].preind
= 1;
5321 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5323 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5324 return PARSE_OPERAND_FAIL
;
5327 return PARSE_OPERAND_SUCCESS
;
5330 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5331 skip_whitespace (p
);
5333 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5335 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5336 return PARSE_OPERAND_FAIL
;
5338 inst
.operands
[i
].reg
= reg
;
5339 inst
.operands
[i
].isreg
= 1;
5341 if (skip_past_comma (&p
) == SUCCESS
)
5343 inst
.operands
[i
].preind
= 1;
5346 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5348 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5350 inst
.operands
[i
].imm
= reg
;
5351 inst
.operands
[i
].immisreg
= 1;
5353 if (skip_past_comma (&p
) == SUCCESS
)
5354 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5355 return PARSE_OPERAND_FAIL
;
5357 else if (skip_past_char (&p
, ':') == SUCCESS
)
5359 /* FIXME: '@' should be used here, but it's filtered out by generic
5360 code before we get to see it here. This may be subject to
5362 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5364 if (result
!= PARSE_OPERAND_SUCCESS
)
5369 if (inst
.operands
[i
].negative
)
5371 inst
.operands
[i
].negative
= 0;
5375 if (group_relocations
5376 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5378 struct group_reloc_table_entry
*entry
;
5380 /* Skip over the #: or : sequence. */
5386 /* Try to parse a group relocation. Anything else is an
5388 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5390 inst
.error
= _("unknown group relocation");
5391 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5394 /* We now have the group relocation table entry corresponding to
5395 the name in the assembler source. Next, we parse the
5397 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5398 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5400 /* Record the relocation type. */
5404 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5408 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5412 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5419 if (inst
.reloc
.type
== 0)
5421 inst
.error
= _("this group relocation is not allowed on this instruction");
5422 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5428 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5429 return PARSE_OPERAND_FAIL
;
5430 /* If the offset is 0, find out if it's a +0 or -0. */
5431 if (inst
.reloc
.exp
.X_op
== O_constant
5432 && inst
.reloc
.exp
.X_add_number
== 0)
5434 skip_whitespace (q
);
5438 skip_whitespace (q
);
5441 inst
.operands
[i
].negative
= 1;
5446 else if (skip_past_char (&p
, ':') == SUCCESS
)
5448 /* FIXME: '@' should be used here, but it's filtered out by generic code
5449 before we get to see it here. This may be subject to change. */
5450 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5452 if (result
!= PARSE_OPERAND_SUCCESS
)
5456 if (skip_past_char (&p
, ']') == FAIL
)
5458 inst
.error
= _("']' expected");
5459 return PARSE_OPERAND_FAIL
;
5462 if (skip_past_char (&p
, '!') == SUCCESS
)
5463 inst
.operands
[i
].writeback
= 1;
5465 else if (skip_past_comma (&p
) == SUCCESS
)
5467 if (skip_past_char (&p
, '{') == SUCCESS
)
5469 /* [Rn], {expr} - unindexed, with option */
5470 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5471 0, 255, TRUE
) == FAIL
)
5472 return PARSE_OPERAND_FAIL
;
5474 if (skip_past_char (&p
, '}') == FAIL
)
5476 inst
.error
= _("'}' expected at end of 'option' field");
5477 return PARSE_OPERAND_FAIL
;
5479 if (inst
.operands
[i
].preind
)
5481 inst
.error
= _("cannot combine index with option");
5482 return PARSE_OPERAND_FAIL
;
5485 return PARSE_OPERAND_SUCCESS
;
5489 inst
.operands
[i
].postind
= 1;
5490 inst
.operands
[i
].writeback
= 1;
5492 if (inst
.operands
[i
].preind
)
5494 inst
.error
= _("cannot combine pre- and post-indexing");
5495 return PARSE_OPERAND_FAIL
;
5499 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5501 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5503 /* We might be using the immediate for alignment already. If we
5504 are, OR the register number into the low-order bits. */
5505 if (inst
.operands
[i
].immisalign
)
5506 inst
.operands
[i
].imm
|= reg
;
5508 inst
.operands
[i
].imm
= reg
;
5509 inst
.operands
[i
].immisreg
= 1;
5511 if (skip_past_comma (&p
) == SUCCESS
)
5512 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5513 return PARSE_OPERAND_FAIL
;
5518 if (inst
.operands
[i
].negative
)
5520 inst
.operands
[i
].negative
= 0;
5523 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5524 return PARSE_OPERAND_FAIL
;
5525 /* If the offset is 0, find out if it's a +0 or -0. */
5526 if (inst
.reloc
.exp
.X_op
== O_constant
5527 && inst
.reloc
.exp
.X_add_number
== 0)
5529 skip_whitespace (q
);
5533 skip_whitespace (q
);
5536 inst
.operands
[i
].negative
= 1;
5542 /* If at this point neither .preind nor .postind is set, we have a
5543 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5544 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5546 inst
.operands
[i
].preind
= 1;
5547 inst
.reloc
.exp
.X_op
= O_constant
;
5548 inst
.reloc
.exp
.X_add_number
= 0;
5551 return PARSE_OPERAND_SUCCESS
;
5555 parse_address (char **str
, int i
)
5557 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5561 static parse_operand_result
5562 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5564 return parse_address_main (str
, i
, 1, type
);
5567 /* Parse an operand for a MOVW or MOVT instruction. */
5569 parse_half (char **str
)
5574 skip_past_char (&p
, '#');
5575 if (strncasecmp (p
, ":lower16:", 9) == 0)
5576 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5577 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5578 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5580 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5583 skip_whitespace (p
);
5586 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5589 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5591 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5593 inst
.error
= _("constant expression expected");
5596 if (inst
.reloc
.exp
.X_add_number
< 0
5597 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5599 inst
.error
= _("immediate value out of range");
5607 /* Miscellaneous. */
5609 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5610 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5612 parse_psr (char **str
, bfd_boolean lhs
)
5615 unsigned long psr_field
;
5616 const struct asm_psr
*psr
;
5618 bfd_boolean is_apsr
= FALSE
;
5619 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5621 /* PR gas/12698: If the user has specified -march=all then m_profile will
5622 be TRUE, but we want to ignore it in this case as we are building for any
5623 CPU type, including non-m variants. */
5624 if (selected_cpu
.core
== arm_arch_any
.core
)
5627 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5628 feature for ease of use and backwards compatibility. */
5630 if (strncasecmp (p
, "SPSR", 4) == 0)
5633 goto unsupported_psr
;
5635 psr_field
= SPSR_BIT
;
5637 else if (strncasecmp (p
, "CPSR", 4) == 0)
5640 goto unsupported_psr
;
5644 else if (strncasecmp (p
, "APSR", 4) == 0)
5646 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5647 and ARMv7-R architecture CPUs. */
5656 while (ISALNUM (*p
) || *p
== '_');
5658 if (strncasecmp (start
, "iapsr", 5) == 0
5659 || strncasecmp (start
, "eapsr", 5) == 0
5660 || strncasecmp (start
, "xpsr", 4) == 0
5661 || strncasecmp (start
, "psr", 3) == 0)
5662 p
= start
+ strcspn (start
, "rR") + 1;
5664 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5670 /* If APSR is being written, a bitfield may be specified. Note that
5671 APSR itself is handled above. */
5672 if (psr
->field
<= 3)
5674 psr_field
= psr
->field
;
5680 /* M-profile MSR instructions have the mask field set to "10", except
5681 *PSR variants which modify APSR, which may use a different mask (and
5682 have been handled already). Do that by setting the PSR_f field
5684 return psr
->field
| (lhs
? PSR_f
: 0);
5687 goto unsupported_psr
;
5693 /* A suffix follows. */
5699 while (ISALNUM (*p
) || *p
== '_');
5703 /* APSR uses a notation for bits, rather than fields. */
5704 unsigned int nzcvq_bits
= 0;
5705 unsigned int g_bit
= 0;
5708 for (bit
= start
; bit
!= p
; bit
++)
5710 switch (TOLOWER (*bit
))
5713 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5717 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5721 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5725 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5729 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5733 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5737 inst
.error
= _("unexpected bit specified after APSR");
5742 if (nzcvq_bits
== 0x1f)
5747 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5749 inst
.error
= _("selected processor does not "
5750 "support DSP extension");
5757 if ((nzcvq_bits
& 0x20) != 0
5758 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5759 || (g_bit
& 0x2) != 0)
5761 inst
.error
= _("bad bitmask specified after APSR");
5767 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5772 psr_field
|= psr
->field
;
5778 goto error
; /* Garbage after "[CS]PSR". */
5780 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5781 is deprecated, but allow it anyway. */
5785 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5788 else if (!m_profile
)
5789 /* These bits are never right for M-profile devices: don't set them
5790 (only code paths which read/write APSR reach here). */
5791 psr_field
|= (PSR_c
| PSR_f
);
5797 inst
.error
= _("selected processor does not support requested special "
5798 "purpose register");
5802 inst
.error
= _("flag for {c}psr instruction expected");
5806 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5807 value suitable for splatting into the AIF field of the instruction. */
5810 parse_cps_flags (char **str
)
5819 case '\0': case ',':
5822 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5823 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5824 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5827 inst
.error
= _("unrecognized CPS flag");
5832 if (saw_a_flag
== 0)
5834 inst
.error
= _("missing CPS flags");
5842 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5843 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5846 parse_endian_specifier (char **str
)
5851 if (strncasecmp (s
, "BE", 2))
5853 else if (strncasecmp (s
, "LE", 2))
5857 inst
.error
= _("valid endian specifiers are be or le");
5861 if (ISALNUM (s
[2]) || s
[2] == '_')
5863 inst
.error
= _("valid endian specifiers are be or le");
5868 return little_endian
;
5871 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5872 value suitable for poking into the rotate field of an sxt or sxta
5873 instruction, or FAIL on error. */
5876 parse_ror (char **str
)
5881 if (strncasecmp (s
, "ROR", 3) == 0)
5885 inst
.error
= _("missing rotation field after comma");
5889 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5894 case 0: *str
= s
; return 0x0;
5895 case 8: *str
= s
; return 0x1;
5896 case 16: *str
= s
; return 0x2;
5897 case 24: *str
= s
; return 0x3;
5900 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5905 /* Parse a conditional code (from conds[] below). The value returned is in the
5906 range 0 .. 14, or FAIL. */
5908 parse_cond (char **str
)
5911 const struct asm_cond
*c
;
5913 /* Condition codes are always 2 characters, so matching up to
5914 3 characters is sufficient. */
5919 while (ISALPHA (*q
) && n
< 3)
5921 cond
[n
] = TOLOWER (*q
);
5926 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5929 inst
.error
= _("condition required");
5937 /* If the given feature available in the selected CPU, mark it as used.
5938 Returns TRUE iff feature is available. */
5940 mark_feature_used (const arm_feature_set
*feature
)
5942 /* Ensure the option is valid on the current architecture. */
5943 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
5946 /* Add the appropriate architecture feature for the barrier option used.
5949 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
5951 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
5956 /* Parse an option for a barrier instruction. Returns the encoding for the
5959 parse_barrier (char **str
)
5962 const struct asm_barrier_opt
*o
;
5965 while (ISALPHA (*q
))
5968 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5973 if (!mark_feature_used (&o
->arch
))
5980 /* Parse the operands of a table branch instruction. Similar to a memory
5983 parse_tb (char **str
)
5988 if (skip_past_char (&p
, '[') == FAIL
)
5990 inst
.error
= _("'[' expected");
5994 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5996 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5999 inst
.operands
[0].reg
= reg
;
6001 if (skip_past_comma (&p
) == FAIL
)
6003 inst
.error
= _("',' expected");
6007 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6009 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6012 inst
.operands
[0].imm
= reg
;
6014 if (skip_past_comma (&p
) == SUCCESS
)
6016 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6018 if (inst
.reloc
.exp
.X_add_number
!= 1)
6020 inst
.error
= _("invalid shift");
6023 inst
.operands
[0].shifted
= 1;
6026 if (skip_past_char (&p
, ']') == FAIL
)
6028 inst
.error
= _("']' expected");
6035 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6036 information on the types the operands can take and how they are encoded.
6037 Up to four operands may be read; this function handles setting the
6038 ".present" field for each read operand itself.
6039 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6040 else returns FAIL. */
6043 parse_neon_mov (char **str
, int *which_operand
)
6045 int i
= *which_operand
, val
;
6046 enum arm_reg_type rtype
;
6048 struct neon_type_el optype
;
6050 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6052 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6053 inst
.operands
[i
].reg
= val
;
6054 inst
.operands
[i
].isscalar
= 1;
6055 inst
.operands
[i
].vectype
= optype
;
6056 inst
.operands
[i
++].present
= 1;
6058 if (skip_past_comma (&ptr
) == FAIL
)
6061 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6064 inst
.operands
[i
].reg
= val
;
6065 inst
.operands
[i
].isreg
= 1;
6066 inst
.operands
[i
].present
= 1;
6068 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6071 /* Cases 0, 1, 2, 3, 5 (D only). */
6072 if (skip_past_comma (&ptr
) == FAIL
)
6075 inst
.operands
[i
].reg
= val
;
6076 inst
.operands
[i
].isreg
= 1;
6077 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6078 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6079 inst
.operands
[i
].isvec
= 1;
6080 inst
.operands
[i
].vectype
= optype
;
6081 inst
.operands
[i
++].present
= 1;
6083 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6085 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6086 Case 13: VMOV <Sd>, <Rm> */
6087 inst
.operands
[i
].reg
= val
;
6088 inst
.operands
[i
].isreg
= 1;
6089 inst
.operands
[i
].present
= 1;
6091 if (rtype
== REG_TYPE_NQ
)
6093 first_error (_("can't use Neon quad register here"));
6096 else if (rtype
!= REG_TYPE_VFS
)
6099 if (skip_past_comma (&ptr
) == FAIL
)
6101 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6103 inst
.operands
[i
].reg
= val
;
6104 inst
.operands
[i
].isreg
= 1;
6105 inst
.operands
[i
].present
= 1;
6108 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6111 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6112 Case 1: VMOV<c><q> <Dd>, <Dm>
6113 Case 8: VMOV.F32 <Sd>, <Sm>
6114 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6116 inst
.operands
[i
].reg
= val
;
6117 inst
.operands
[i
].isreg
= 1;
6118 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6119 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6120 inst
.operands
[i
].isvec
= 1;
6121 inst
.operands
[i
].vectype
= optype
;
6122 inst
.operands
[i
].present
= 1;
6124 if (skip_past_comma (&ptr
) == SUCCESS
)
6129 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6132 inst
.operands
[i
].reg
= val
;
6133 inst
.operands
[i
].isreg
= 1;
6134 inst
.operands
[i
++].present
= 1;
6136 if (skip_past_comma (&ptr
) == FAIL
)
6139 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6142 inst
.operands
[i
].reg
= val
;
6143 inst
.operands
[i
].isreg
= 1;
6144 inst
.operands
[i
].present
= 1;
6147 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6148 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6149 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6150 Case 10: VMOV.F32 <Sd>, #<imm>
6151 Case 11: VMOV.F64 <Dd>, #<imm> */
6152 inst
.operands
[i
].immisfloat
= 1;
6153 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
6154 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6155 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6159 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6163 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6166 inst
.operands
[i
].reg
= val
;
6167 inst
.operands
[i
].isreg
= 1;
6168 inst
.operands
[i
++].present
= 1;
6170 if (skip_past_comma (&ptr
) == FAIL
)
6173 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6175 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6176 inst
.operands
[i
].reg
= val
;
6177 inst
.operands
[i
].isscalar
= 1;
6178 inst
.operands
[i
].present
= 1;
6179 inst
.operands
[i
].vectype
= optype
;
6181 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6183 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6184 inst
.operands
[i
].reg
= val
;
6185 inst
.operands
[i
].isreg
= 1;
6186 inst
.operands
[i
++].present
= 1;
6188 if (skip_past_comma (&ptr
) == FAIL
)
6191 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6194 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6198 inst
.operands
[i
].reg
= val
;
6199 inst
.operands
[i
].isreg
= 1;
6200 inst
.operands
[i
].isvec
= 1;
6201 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6202 inst
.operands
[i
].vectype
= optype
;
6203 inst
.operands
[i
].present
= 1;
6205 if (rtype
== REG_TYPE_VFS
)
6209 if (skip_past_comma (&ptr
) == FAIL
)
6211 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6214 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6217 inst
.operands
[i
].reg
= val
;
6218 inst
.operands
[i
].isreg
= 1;
6219 inst
.operands
[i
].isvec
= 1;
6220 inst
.operands
[i
].issingle
= 1;
6221 inst
.operands
[i
].vectype
= optype
;
6222 inst
.operands
[i
].present
= 1;
6225 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6229 inst
.operands
[i
].reg
= val
;
6230 inst
.operands
[i
].isreg
= 1;
6231 inst
.operands
[i
].isvec
= 1;
6232 inst
.operands
[i
].issingle
= 1;
6233 inst
.operands
[i
].vectype
= optype
;
6234 inst
.operands
[i
].present
= 1;
6239 first_error (_("parse error"));
6243 /* Successfully parsed the operands. Update args. */
6249 first_error (_("expected comma"));
6253 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6257 /* Use this macro when the operand constraints are different
6258 for ARM and THUMB (e.g. ldrd). */
6259 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6260 ((arm_operand) | ((thumb_operand) << 16))
6262 /* Matcher codes for parse_operands. */
6263 enum operand_parse_code
6265 OP_stop
, /* end of line */
6267 OP_RR
, /* ARM register */
6268 OP_RRnpc
, /* ARM register, not r15 */
6269 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6270 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6271 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6272 optional trailing ! */
6273 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6274 OP_RCP
, /* Coprocessor number */
6275 OP_RCN
, /* Coprocessor register */
6276 OP_RF
, /* FPA register */
6277 OP_RVS
, /* VFP single precision register */
6278 OP_RVD
, /* VFP double precision register (0..15) */
6279 OP_RND
, /* Neon double precision register (0..31) */
6280 OP_RNQ
, /* Neon quad precision register */
6281 OP_RVSD
, /* VFP single or double precision register */
6282 OP_RNDQ
, /* Neon double or quad precision register */
6283 OP_RNSDQ
, /* Neon single, double or quad precision register */
6284 OP_RNSC
, /* Neon scalar D[X] */
6285 OP_RVC
, /* VFP control register */
6286 OP_RMF
, /* Maverick F register */
6287 OP_RMD
, /* Maverick D register */
6288 OP_RMFX
, /* Maverick FX register */
6289 OP_RMDX
, /* Maverick DX register */
6290 OP_RMAX
, /* Maverick AX register */
6291 OP_RMDS
, /* Maverick DSPSC register */
6292 OP_RIWR
, /* iWMMXt wR register */
6293 OP_RIWC
, /* iWMMXt wC register */
6294 OP_RIWG
, /* iWMMXt wCG register */
6295 OP_RXA
, /* XScale accumulator register */
6297 OP_REGLST
, /* ARM register list */
6298 OP_VRSLST
, /* VFP single-precision register list */
6299 OP_VRDLST
, /* VFP double-precision register list */
6300 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6301 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6302 OP_NSTRLST
, /* Neon element/structure list */
6304 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6305 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6306 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6307 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6308 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6309 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6310 OP_VMOV
, /* Neon VMOV operands. */
6311 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6312 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6313 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6315 OP_I0
, /* immediate zero */
6316 OP_I7
, /* immediate value 0 .. 7 */
6317 OP_I15
, /* 0 .. 15 */
6318 OP_I16
, /* 1 .. 16 */
6319 OP_I16z
, /* 0 .. 16 */
6320 OP_I31
, /* 0 .. 31 */
6321 OP_I31w
, /* 0 .. 31, optional trailing ! */
6322 OP_I32
, /* 1 .. 32 */
6323 OP_I32z
, /* 0 .. 32 */
6324 OP_I63
, /* 0 .. 63 */
6325 OP_I63s
, /* -64 .. 63 */
6326 OP_I64
, /* 1 .. 64 */
6327 OP_I64z
, /* 0 .. 64 */
6328 OP_I255
, /* 0 .. 255 */
6330 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6331 OP_I7b
, /* 0 .. 7 */
6332 OP_I15b
, /* 0 .. 15 */
6333 OP_I31b
, /* 0 .. 31 */
6335 OP_SH
, /* shifter operand */
6336 OP_SHG
, /* shifter operand with possible group relocation */
6337 OP_ADDR
, /* Memory address expression (any mode) */
6338 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6339 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6340 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6341 OP_EXP
, /* arbitrary expression */
6342 OP_EXPi
, /* same, with optional immediate prefix */
6343 OP_EXPr
, /* same, with optional relocation suffix */
6344 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6346 OP_CPSF
, /* CPS flags */
6347 OP_ENDI
, /* Endianness specifier */
6348 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6349 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6350 OP_COND
, /* conditional code */
6351 OP_TB
, /* Table branch. */
6353 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6355 OP_RRnpc_I0
, /* ARM register or literal 0 */
6356 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6357 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6358 OP_RF_IF
, /* FPA register or immediate */
6359 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6360 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6362 /* Optional operands. */
6363 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6364 OP_oI31b
, /* 0 .. 31 */
6365 OP_oI32b
, /* 1 .. 32 */
6366 OP_oI32z
, /* 0 .. 32 */
6367 OP_oIffffb
, /* 0 .. 65535 */
6368 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6370 OP_oRR
, /* ARM register */
6371 OP_oRRnpc
, /* ARM register, not the PC */
6372 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6373 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6374 OP_oRND
, /* Optional Neon double precision register */
6375 OP_oRNQ
, /* Optional Neon quad precision register */
6376 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6377 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6378 OP_oSHll
, /* LSL immediate */
6379 OP_oSHar
, /* ASR immediate */
6380 OP_oSHllar
, /* LSL or ASR immediate */
6381 OP_oROR
, /* ROR 0/8/16/24 */
6382 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6384 /* Some pre-defined mixed (ARM/THUMB) operands. */
6385 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6386 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6387 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6389 OP_FIRST_OPTIONAL
= OP_oI7b
6392 /* Generic instruction operand parser. This does no encoding and no
6393 semantic validation; it merely squirrels values away in the inst
6394 structure. Returns SUCCESS or FAIL depending on whether the
6395 specified grammar matched. */
6397 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6399 unsigned const int *upat
= pattern
;
6400 char *backtrack_pos
= 0;
6401 const char *backtrack_error
= 0;
6402 int i
, val
= 0, backtrack_index
= 0;
6403 enum arm_reg_type rtype
;
6404 parse_operand_result result
;
6405 unsigned int op_parse_code
;
6407 #define po_char_or_fail(chr) \
6410 if (skip_past_char (&str, chr) == FAIL) \
6415 #define po_reg_or_fail(regtype) \
6418 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6419 & inst.operands[i].vectype); \
6422 first_error (_(reg_expected_msgs[regtype])); \
6425 inst.operands[i].reg = val; \
6426 inst.operands[i].isreg = 1; \
6427 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6428 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6429 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6430 || rtype == REG_TYPE_VFD \
6431 || rtype == REG_TYPE_NQ); \
6435 #define po_reg_or_goto(regtype, label) \
6438 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6439 & inst.operands[i].vectype); \
6443 inst.operands[i].reg = val; \
6444 inst.operands[i].isreg = 1; \
6445 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6446 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6447 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6448 || rtype == REG_TYPE_VFD \
6449 || rtype == REG_TYPE_NQ); \
6453 #define po_imm_or_fail(min, max, popt) \
6456 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6458 inst.operands[i].imm = val; \
6462 #define po_scalar_or_goto(elsz, label) \
6465 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6468 inst.operands[i].reg = val; \
6469 inst.operands[i].isscalar = 1; \
6473 #define po_misc_or_fail(expr) \
6481 #define po_misc_or_fail_no_backtrack(expr) \
6485 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6486 backtrack_pos = 0; \
6487 if (result != PARSE_OPERAND_SUCCESS) \
6492 #define po_barrier_or_imm(str) \
6495 val = parse_barrier (&str); \
6496 if (val == FAIL && ! ISALPHA (*str)) \
6499 /* ISB can only take SY as an option. */ \
6500 || ((inst.instruction & 0xf0) == 0x60 \
6503 inst.error = _("invalid barrier type"); \
6504 backtrack_pos = 0; \
6510 skip_whitespace (str
);
6512 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6514 op_parse_code
= upat
[i
];
6515 if (op_parse_code
>= 1<<16)
6516 op_parse_code
= thumb
? (op_parse_code
>> 16)
6517 : (op_parse_code
& ((1<<16)-1));
6519 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6521 /* Remember where we are in case we need to backtrack. */
6522 gas_assert (!backtrack_pos
);
6523 backtrack_pos
= str
;
6524 backtrack_error
= inst
.error
;
6525 backtrack_index
= i
;
6528 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6529 po_char_or_fail (',');
6531 switch (op_parse_code
)
6539 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6540 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6541 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6542 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6543 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6544 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6546 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6548 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6550 /* Also accept generic coprocessor regs for unknown registers. */
6552 po_reg_or_fail (REG_TYPE_CN
);
6554 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6555 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6556 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6557 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6558 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6559 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6560 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6561 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6562 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6563 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6565 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6567 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6568 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6570 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6572 /* Neon scalar. Using an element size of 8 means that some invalid
6573 scalars are accepted here, so deal with those in later code. */
6574 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6578 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6581 po_imm_or_fail (0, 0, TRUE
);
6586 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6591 po_scalar_or_goto (8, try_rr
);
6594 po_reg_or_fail (REG_TYPE_RN
);
6600 po_scalar_or_goto (8, try_nsdq
);
6603 po_reg_or_fail (REG_TYPE_NSDQ
);
6609 po_scalar_or_goto (8, try_ndq
);
6612 po_reg_or_fail (REG_TYPE_NDQ
);
6618 po_scalar_or_goto (8, try_vfd
);
6621 po_reg_or_fail (REG_TYPE_VFD
);
6626 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6627 not careful then bad things might happen. */
6628 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6633 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6636 /* There's a possibility of getting a 64-bit immediate here, so
6637 we need special handling. */
6638 if (parse_big_immediate (&str
, i
) == FAIL
)
6640 inst
.error
= _("immediate value is out of range");
6648 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6651 po_imm_or_fail (0, 63, TRUE
);
6656 po_char_or_fail ('[');
6657 po_reg_or_fail (REG_TYPE_RN
);
6658 po_char_or_fail (']');
6664 po_reg_or_fail (REG_TYPE_RN
);
6665 if (skip_past_char (&str
, '!') == SUCCESS
)
6666 inst
.operands
[i
].writeback
= 1;
6670 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6671 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6672 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6673 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6674 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6675 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6676 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6677 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6678 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6679 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6680 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6681 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6683 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6685 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6686 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6688 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6689 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6690 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6691 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6693 /* Immediate variants */
6695 po_char_or_fail ('{');
6696 po_imm_or_fail (0, 255, TRUE
);
6697 po_char_or_fail ('}');
6701 /* The expression parser chokes on a trailing !, so we have
6702 to find it first and zap it. */
6705 while (*s
&& *s
!= ',')
6710 inst
.operands
[i
].writeback
= 1;
6712 po_imm_or_fail (0, 31, TRUE
);
6720 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6725 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6730 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6732 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6734 val
= parse_reloc (&str
);
6737 inst
.error
= _("unrecognized relocation suffix");
6740 else if (val
!= BFD_RELOC_UNUSED
)
6742 inst
.operands
[i
].imm
= val
;
6743 inst
.operands
[i
].hasreloc
= 1;
6748 /* Operand for MOVW or MOVT. */
6750 po_misc_or_fail (parse_half (&str
));
6753 /* Register or expression. */
6754 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6755 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6757 /* Register or immediate. */
6758 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6759 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6761 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6763 if (!is_immediate_prefix (*str
))
6766 val
= parse_fpa_immediate (&str
);
6769 /* FPA immediates are encoded as registers 8-15.
6770 parse_fpa_immediate has already applied the offset. */
6771 inst
.operands
[i
].reg
= val
;
6772 inst
.operands
[i
].isreg
= 1;
6775 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6776 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6778 /* Two kinds of register. */
6781 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6783 || (rege
->type
!= REG_TYPE_MMXWR
6784 && rege
->type
!= REG_TYPE_MMXWC
6785 && rege
->type
!= REG_TYPE_MMXWCG
))
6787 inst
.error
= _("iWMMXt data or control register expected");
6790 inst
.operands
[i
].reg
= rege
->number
;
6791 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6797 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6799 || (rege
->type
!= REG_TYPE_MMXWC
6800 && rege
->type
!= REG_TYPE_MMXWCG
))
6802 inst
.error
= _("iWMMXt control register expected");
6805 inst
.operands
[i
].reg
= rege
->number
;
6806 inst
.operands
[i
].isreg
= 1;
6811 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6812 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6813 case OP_oROR
: val
= parse_ror (&str
); break;
6814 case OP_COND
: val
= parse_cond (&str
); break;
6815 case OP_oBARRIER_I15
:
6816 po_barrier_or_imm (str
); break;
6818 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6824 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6825 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6827 inst
.error
= _("Banked registers are not available with this "
6833 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6837 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6840 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6842 if (strncasecmp (str
, "APSR_", 5) == 0)
6849 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6850 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6851 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6852 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6853 default: found
= 16;
6857 inst
.operands
[i
].isvec
= 1;
6858 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6859 inst
.operands
[i
].reg
= REG_PC
;
6866 po_misc_or_fail (parse_tb (&str
));
6869 /* Register lists. */
6871 val
= parse_reg_list (&str
);
6874 inst
.operands
[1].writeback
= 1;
6880 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6884 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6888 /* Allow Q registers too. */
6889 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6894 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6896 inst
.operands
[i
].issingle
= 1;
6901 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6906 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6907 &inst
.operands
[i
].vectype
);
6910 /* Addressing modes */
6912 po_misc_or_fail (parse_address (&str
, i
));
6916 po_misc_or_fail_no_backtrack (
6917 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6921 po_misc_or_fail_no_backtrack (
6922 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6926 po_misc_or_fail_no_backtrack (
6927 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6931 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6935 po_misc_or_fail_no_backtrack (
6936 parse_shifter_operand_group_reloc (&str
, i
));
6940 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6944 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6948 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6952 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6955 /* Various value-based sanity checks and shared operations. We
6956 do not signal immediate failures for the register constraints;
6957 this allows a syntax error to take precedence. */
6958 switch (op_parse_code
)
6966 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6967 inst
.error
= BAD_PC
;
6972 if (inst
.operands
[i
].isreg
)
6974 if (inst
.operands
[i
].reg
== REG_PC
)
6975 inst
.error
= BAD_PC
;
6976 else if (inst
.operands
[i
].reg
== REG_SP
)
6977 inst
.error
= BAD_SP
;
6982 if (inst
.operands
[i
].isreg
6983 && inst
.operands
[i
].reg
== REG_PC
6984 && (inst
.operands
[i
].writeback
|| thumb
))
6985 inst
.error
= BAD_PC
;
6994 case OP_oBARRIER_I15
:
7003 inst
.operands
[i
].imm
= val
;
7010 /* If we get here, this operand was successfully parsed. */
7011 inst
.operands
[i
].present
= 1;
7015 inst
.error
= BAD_ARGS
;
7020 /* The parse routine should already have set inst.error, but set a
7021 default here just in case. */
7023 inst
.error
= _("syntax error");
7027 /* Do not backtrack over a trailing optional argument that
7028 absorbed some text. We will only fail again, with the
7029 'garbage following instruction' error message, which is
7030 probably less helpful than the current one. */
7031 if (backtrack_index
== i
&& backtrack_pos
!= str
7032 && upat
[i
+1] == OP_stop
)
7035 inst
.error
= _("syntax error");
7039 /* Try again, skipping the optional argument at backtrack_pos. */
7040 str
= backtrack_pos
;
7041 inst
.error
= backtrack_error
;
7042 inst
.operands
[backtrack_index
].present
= 0;
7043 i
= backtrack_index
;
7047 /* Check that we have parsed all the arguments. */
7048 if (*str
!= '\0' && !inst
.error
)
7049 inst
.error
= _("garbage following instruction");
7051 return inst
.error
? FAIL
: SUCCESS
;
7054 #undef po_char_or_fail
7055 #undef po_reg_or_fail
7056 #undef po_reg_or_goto
7057 #undef po_imm_or_fail
7058 #undef po_scalar_or_fail
7059 #undef po_barrier_or_imm
7061 /* Shorthand macro for instruction encoding functions issuing errors. */
7062 #define constraint(expr, err) \
7073 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7074 instructions are unpredictable if these registers are used. This
7075 is the BadReg predicate in ARM's Thumb-2 documentation. */
7076 #define reject_bad_reg(reg) \
7078 if (reg == REG_SP || reg == REG_PC) \
7080 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
7085 /* If REG is R13 (the stack pointer), warn that its use is
7087 #define warn_deprecated_sp(reg) \
7089 if (warn_on_deprecated && reg == REG_SP) \
7090 as_warn (_("use of r13 is deprecated")); \
7093 /* Functions for operand encoding. ARM, then Thumb. */
7095 #define rotate_left(v, n) (v << n | v >> (32 - n))
7097 /* If VAL can be encoded in the immediate field of an ARM instruction,
7098 return the encoded form. Otherwise, return FAIL. */
7101 encode_arm_immediate (unsigned int val
)
7105 for (i
= 0; i
< 32; i
+= 2)
7106 if ((a
= rotate_left (val
, i
)) <= 0xff)
7107 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7112 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7113 return the encoded form. Otherwise, return FAIL. */
7115 encode_thumb32_immediate (unsigned int val
)
7122 for (i
= 1; i
<= 24; i
++)
7125 if ((val
& ~(0xff << i
)) == 0)
7126 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7130 if (val
== ((a
<< 16) | a
))
7132 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7136 if (val
== ((a
<< 16) | a
))
7137 return 0x200 | (a
>> 8);
7141 /* Encode a VFP SP or DP register number into inst.instruction. */
7144 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7146 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7149 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7152 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7155 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7160 first_error (_("D register out of range for selected VFP version"));
7168 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7172 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7176 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7180 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7184 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7188 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7196 /* Encode a <shift> in an ARM-format instruction. The immediate,
7197 if any, is handled by md_apply_fix. */
7199 encode_arm_shift (int i
)
7201 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7202 inst
.instruction
|= SHIFT_ROR
<< 5;
7205 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7206 if (inst
.operands
[i
].immisreg
)
7208 inst
.instruction
|= SHIFT_BY_REG
;
7209 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7212 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7217 encode_arm_shifter_operand (int i
)
7219 if (inst
.operands
[i
].isreg
)
7221 inst
.instruction
|= inst
.operands
[i
].reg
;
7222 encode_arm_shift (i
);
7226 inst
.instruction
|= INST_IMMEDIATE
;
7227 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7228 inst
.instruction
|= inst
.operands
[i
].imm
;
7232 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7234 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7237 Generate an error if the operand is not a register. */
7238 constraint (!inst
.operands
[i
].isreg
,
7239 _("Instruction does not support =N addresses"));
7241 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7243 if (inst
.operands
[i
].preind
)
7247 inst
.error
= _("instruction does not accept preindexed addressing");
7250 inst
.instruction
|= PRE_INDEX
;
7251 if (inst
.operands
[i
].writeback
)
7252 inst
.instruction
|= WRITE_BACK
;
7255 else if (inst
.operands
[i
].postind
)
7257 gas_assert (inst
.operands
[i
].writeback
);
7259 inst
.instruction
|= WRITE_BACK
;
7261 else /* unindexed - only for coprocessor */
7263 inst
.error
= _("instruction does not accept unindexed addressing");
7267 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7268 && (((inst
.instruction
& 0x000f0000) >> 16)
7269 == ((inst
.instruction
& 0x0000f000) >> 12)))
7270 as_warn ((inst
.instruction
& LOAD_BIT
)
7271 ? _("destination register same as write-back base")
7272 : _("source register same as write-back base"));
7275 /* inst.operands[i] was set up by parse_address. Encode it into an
7276 ARM-format mode 2 load or store instruction. If is_t is true,
7277 reject forms that cannot be used with a T instruction (i.e. not
7280 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7282 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7284 encode_arm_addr_mode_common (i
, is_t
);
7286 if (inst
.operands
[i
].immisreg
)
7288 constraint ((inst
.operands
[i
].imm
== REG_PC
7289 || (is_pc
&& inst
.operands
[i
].writeback
)),
7291 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7292 inst
.instruction
|= inst
.operands
[i
].imm
;
7293 if (!inst
.operands
[i
].negative
)
7294 inst
.instruction
|= INDEX_UP
;
7295 if (inst
.operands
[i
].shifted
)
7297 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7298 inst
.instruction
|= SHIFT_ROR
<< 5;
7301 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7302 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7306 else /* immediate offset in inst.reloc */
7308 if (is_pc
&& !inst
.reloc
.pc_rel
)
7310 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7312 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7313 cannot use PC in addressing.
7314 PC cannot be used in writeback addressing, either. */
7315 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7318 /* Use of PC in str is deprecated for ARMv7. */
7319 if (warn_on_deprecated
7321 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7322 as_warn (_("use of PC in this instruction is deprecated"));
7325 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7327 /* Prefer + for zero encoded value. */
7328 if (!inst
.operands
[i
].negative
)
7329 inst
.instruction
|= INDEX_UP
;
7330 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7335 /* inst.operands[i] was set up by parse_address. Encode it into an
7336 ARM-format mode 3 load or store instruction. Reject forms that
7337 cannot be used with such instructions. If is_t is true, reject
7338 forms that cannot be used with a T instruction (i.e. not
7341 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7343 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7345 inst
.error
= _("instruction does not accept scaled register index");
7349 encode_arm_addr_mode_common (i
, is_t
);
7351 if (inst
.operands
[i
].immisreg
)
7353 constraint ((inst
.operands
[i
].imm
== REG_PC
7354 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7356 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7358 inst
.instruction
|= inst
.operands
[i
].imm
;
7359 if (!inst
.operands
[i
].negative
)
7360 inst
.instruction
|= INDEX_UP
;
7362 else /* immediate offset in inst.reloc */
7364 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7365 && inst
.operands
[i
].writeback
),
7367 inst
.instruction
|= HWOFFSET_IMM
;
7368 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7370 /* Prefer + for zero encoded value. */
7371 if (!inst
.operands
[i
].negative
)
7372 inst
.instruction
|= INDEX_UP
;
7374 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7379 /* inst.operands[i] was set up by parse_address. Encode it into an
7380 ARM-format instruction. Reject all forms which cannot be encoded
7381 into a coprocessor load/store instruction. If wb_ok is false,
7382 reject use of writeback; if unind_ok is false, reject use of
7383 unindexed addressing. If reloc_override is not 0, use it instead
7384 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7385 (in which case it is preserved). */
7388 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7390 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7392 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7394 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7396 gas_assert (!inst
.operands
[i
].writeback
);
7399 inst
.error
= _("instruction does not support unindexed addressing");
7402 inst
.instruction
|= inst
.operands
[i
].imm
;
7403 inst
.instruction
|= INDEX_UP
;
7407 if (inst
.operands
[i
].preind
)
7408 inst
.instruction
|= PRE_INDEX
;
7410 if (inst
.operands
[i
].writeback
)
7412 if (inst
.operands
[i
].reg
== REG_PC
)
7414 inst
.error
= _("pc may not be used with write-back");
7419 inst
.error
= _("instruction does not support writeback");
7422 inst
.instruction
|= WRITE_BACK
;
7426 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7427 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7428 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7429 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7432 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7434 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7437 /* Prefer + for zero encoded value. */
7438 if (!inst
.operands
[i
].negative
)
7439 inst
.instruction
|= INDEX_UP
;
7444 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7445 Determine whether it can be performed with a move instruction; if
7446 it can, convert inst.instruction to that move instruction and
7447 return TRUE; if it can't, convert inst.instruction to a literal-pool
7448 load and return FALSE. If this is not a valid thing to do in the
7449 current context, set inst.error and return TRUE.
7451 inst.operands[i] describes the destination register. */
7454 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7459 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7463 if ((inst
.instruction
& tbit
) == 0)
7465 inst
.error
= _("invalid pseudo operation");
7468 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7470 inst
.error
= _("constant expression expected");
7473 if (inst
.reloc
.exp
.X_op
== O_constant
)
7477 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7479 /* This can be done with a mov(1) instruction. */
7480 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7481 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7487 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7490 /* This can be done with a mov instruction. */
7491 inst
.instruction
&= LITERAL_MASK
;
7492 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7493 inst
.instruction
|= value
& 0xfff;
7497 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7500 /* This can be done with a mvn instruction. */
7501 inst
.instruction
&= LITERAL_MASK
;
7502 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7503 inst
.instruction
|= value
& 0xfff;
7509 if (add_to_lit_pool () == FAIL
)
7511 inst
.error
= _("literal pool insertion failed");
7514 inst
.operands
[1].reg
= REG_PC
;
7515 inst
.operands
[1].isreg
= 1;
7516 inst
.operands
[1].preind
= 1;
7517 inst
.reloc
.pc_rel
= 1;
7518 inst
.reloc
.type
= (thumb_p
7519 ? BFD_RELOC_ARM_THUMB_OFFSET
7521 ? BFD_RELOC_ARM_HWLITERAL
7522 : BFD_RELOC_ARM_LITERAL
));
7526 /* Functions for instruction encoding, sorted by sub-architecture.
7527 First some generics; their names are taken from the conventional
7528 bit positions for register arguments in ARM format instructions. */
7538 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7544 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7545 inst
.instruction
|= inst
.operands
[1].reg
;
7551 inst
.instruction
|= inst
.operands
[0].reg
;
7552 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7558 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7559 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7565 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7566 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7570 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
7572 if (ARM_CPU_IS_ANY (cpu_variant
))
7574 as_warn ("%s", msg
);
7577 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
7589 unsigned Rn
= inst
.operands
[2].reg
;
7590 /* Enforce restrictions on SWP instruction. */
7591 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7593 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7594 _("Rn must not overlap other operands"));
7596 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
7598 if (!check_obsolete (&arm_ext_v8
,
7599 _("swp{b} use is obsoleted for ARMv8 and later"))
7600 && warn_on_deprecated
7601 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
7602 as_warn (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
7605 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7606 inst
.instruction
|= inst
.operands
[1].reg
;
7607 inst
.instruction
|= Rn
<< 16;
7613 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7614 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7615 inst
.instruction
|= inst
.operands
[2].reg
;
7621 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7622 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7623 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7624 || inst
.reloc
.exp
.X_add_number
!= 0),
7626 inst
.instruction
|= inst
.operands
[0].reg
;
7627 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7628 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7634 inst
.instruction
|= inst
.operands
[0].imm
;
7640 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7641 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7644 /* ARM instructions, in alphabetical order by function name (except
7645 that wrapper functions appear immediately after the function they
7648 /* This is a pseudo-op of the form "adr rd, label" to be converted
7649 into a relative address of the form "add rd, pc, #label-.-8". */
7654 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7656 /* Frag hacking will turn this into a sub instruction if the offset turns
7657 out to be negative. */
7658 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7659 inst
.reloc
.pc_rel
= 1;
7660 inst
.reloc
.exp
.X_add_number
-= 8;
7663 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7664 into a relative address of the form:
7665 add rd, pc, #low(label-.-8)"
7666 add rd, rd, #high(label-.-8)" */
7671 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7673 /* Frag hacking will turn this into a sub instruction if the offset turns
7674 out to be negative. */
7675 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7676 inst
.reloc
.pc_rel
= 1;
7677 inst
.size
= INSN_SIZE
* 2;
7678 inst
.reloc
.exp
.X_add_number
-= 8;
7684 if (!inst
.operands
[1].present
)
7685 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7686 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7687 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7688 encode_arm_shifter_operand (2);
7694 if (inst
.operands
[0].present
)
7695 inst
.instruction
|= inst
.operands
[0].imm
;
7697 inst
.instruction
|= 0xf;
7703 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7704 constraint (msb
> 32, _("bit-field extends past end of register"));
7705 /* The instruction encoding stores the LSB and MSB,
7706 not the LSB and width. */
7707 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7708 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7709 inst
.instruction
|= (msb
- 1) << 16;
7717 /* #0 in second position is alternative syntax for bfc, which is
7718 the same instruction but with REG_PC in the Rm field. */
7719 if (!inst
.operands
[1].isreg
)
7720 inst
.operands
[1].reg
= REG_PC
;
7722 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7723 constraint (msb
> 32, _("bit-field extends past end of register"));
7724 /* The instruction encoding stores the LSB and MSB,
7725 not the LSB and width. */
7726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7727 inst
.instruction
|= inst
.operands
[1].reg
;
7728 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7729 inst
.instruction
|= (msb
- 1) << 16;
7735 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7736 _("bit-field extends past end of register"));
7737 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7738 inst
.instruction
|= inst
.operands
[1].reg
;
7739 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7740 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7743 /* ARM V5 breakpoint instruction (argument parse)
7744 BKPT <16 bit unsigned immediate>
7745 Instruction is not conditional.
7746 The bit pattern given in insns[] has the COND_ALWAYS condition,
7747 and it is an error if the caller tried to override that. */
7752 /* Top 12 of 16 bits to bits 19:8. */
7753 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7755 /* Bottom 4 of 16 bits to bits 3:0. */
7756 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7760 encode_branch (int default_reloc
)
7762 if (inst
.operands
[0].hasreloc
)
7764 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7765 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7766 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7767 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7768 ? BFD_RELOC_ARM_PLT32
7769 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7772 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7773 inst
.reloc
.pc_rel
= 1;
7780 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7781 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7784 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7791 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7793 if (inst
.cond
== COND_ALWAYS
)
7794 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7796 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7800 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7803 /* ARM V5 branch-link-exchange instruction (argument parse)
7804 BLX <target_addr> ie BLX(1)
7805 BLX{<condition>} <Rm> ie BLX(2)
7806 Unfortunately, there are two different opcodes for this mnemonic.
7807 So, the insns[].value is not used, and the code here zaps values
7808 into inst.instruction.
7809 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7814 if (inst
.operands
[0].isreg
)
7816 /* Arg is a register; the opcode provided by insns[] is correct.
7817 It is not illegal to do "blx pc", just useless. */
7818 if (inst
.operands
[0].reg
== REG_PC
)
7819 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7821 inst
.instruction
|= inst
.operands
[0].reg
;
7825 /* Arg is an address; this instruction cannot be executed
7826 conditionally, and the opcode must be adjusted.
7827 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7828 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7829 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7830 inst
.instruction
= 0xfa000000;
7831 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7838 bfd_boolean want_reloc
;
7840 if (inst
.operands
[0].reg
== REG_PC
)
7841 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7843 inst
.instruction
|= inst
.operands
[0].reg
;
7844 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7845 it is for ARMv4t or earlier. */
7846 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7847 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7851 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7856 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7860 /* ARM v5TEJ. Jump to Jazelle code. */
7865 if (inst
.operands
[0].reg
== REG_PC
)
7866 as_tsktsk (_("use of r15 in bxj is not really useful"));
7868 inst
.instruction
|= inst
.operands
[0].reg
;
7871 /* Co-processor data operation:
7872 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7873 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7877 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7878 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7879 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7880 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7881 inst
.instruction
|= inst
.operands
[4].reg
;
7882 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7888 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7889 encode_arm_shifter_operand (1);
7892 /* Transfer between coprocessor and ARM registers.
7893 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7898 No special properties. */
7900 struct deprecated_coproc_regs_s
7907 arm_feature_set deprecated
;
7908 arm_feature_set obsoleted
;
7909 const char *dep_msg
;
7910 const char *obs_msg
;
7913 #define DEPR_ACCESS_V8 \
7914 N_("This coprocessor register access is deprecated in ARMv8")
7916 /* Table of all deprecated coprocessor registers. */
7917 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
7919 {15, 0, 7, 10, 5, /* CP15DMB. */
7920 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7921 DEPR_ACCESS_V8
, NULL
},
7922 {15, 0, 7, 10, 4, /* CP15DSB. */
7923 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7924 DEPR_ACCESS_V8
, NULL
},
7925 {15, 0, 7, 5, 4, /* CP15ISB. */
7926 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7927 DEPR_ACCESS_V8
, NULL
},
7928 {14, 6, 1, 0, 0, /* TEEHBR. */
7929 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7930 DEPR_ACCESS_V8
, NULL
},
7931 {14, 6, 0, 0, 0, /* TEECR. */
7932 ARM_FEATURE (ARM_EXT_V8
, 0), ARM_FEATURE (0, 0),
7933 DEPR_ACCESS_V8
, NULL
},
7936 #undef DEPR_ACCESS_V8
7938 static const size_t deprecated_coproc_reg_count
=
7939 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
7947 Rd
= inst
.operands
[2].reg
;
7950 if (inst
.instruction
== 0xee000010
7951 || inst
.instruction
== 0xfe000010)
7953 reject_bad_reg (Rd
);
7956 constraint (Rd
== REG_SP
, BAD_SP
);
7961 if (inst
.instruction
== 0xe000010)
7962 constraint (Rd
== REG_PC
, BAD_PC
);
7965 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
7967 const struct deprecated_coproc_regs_s
*r
=
7968 deprecated_coproc_regs
+ i
;
7970 if (inst
.operands
[0].reg
== r
->cp
7971 && inst
.operands
[1].imm
== r
->opc1
7972 && inst
.operands
[3].reg
== r
->crn
7973 && inst
.operands
[4].reg
== r
->crm
7974 && inst
.operands
[5].imm
== r
->opc2
)
7976 if (! ARM_CPU_IS_ANY (cpu_variant
)
7977 && warn_on_deprecated
7978 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
7979 as_warn ("%s", r
->dep_msg
);
7983 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7984 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7985 inst
.instruction
|= Rd
<< 12;
7986 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7987 inst
.instruction
|= inst
.operands
[4].reg
;
7988 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7991 /* Transfer between coprocessor register and pair of ARM registers.
7992 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7997 Two XScale instructions are special cases of these:
7999 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8000 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8002 Result unpredictable if Rd or Rn is R15. */
8009 Rd
= inst
.operands
[2].reg
;
8010 Rn
= inst
.operands
[3].reg
;
8014 reject_bad_reg (Rd
);
8015 reject_bad_reg (Rn
);
8019 constraint (Rd
== REG_PC
, BAD_PC
);
8020 constraint (Rn
== REG_PC
, BAD_PC
);
8023 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8024 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8025 inst
.instruction
|= Rd
<< 12;
8026 inst
.instruction
|= Rn
<< 16;
8027 inst
.instruction
|= inst
.operands
[4].reg
;
8033 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8034 if (inst
.operands
[1].present
)
8036 inst
.instruction
|= CPSI_MMOD
;
8037 inst
.instruction
|= inst
.operands
[1].imm
;
8044 inst
.instruction
|= inst
.operands
[0].imm
;
8050 unsigned Rd
, Rn
, Rm
;
8052 Rd
= inst
.operands
[0].reg
;
8053 Rn
= (inst
.operands
[1].present
8054 ? inst
.operands
[1].reg
: Rd
);
8055 Rm
= inst
.operands
[2].reg
;
8057 constraint ((Rd
== REG_PC
), BAD_PC
);
8058 constraint ((Rn
== REG_PC
), BAD_PC
);
8059 constraint ((Rm
== REG_PC
), BAD_PC
);
8061 inst
.instruction
|= Rd
<< 16;
8062 inst
.instruction
|= Rn
<< 0;
8063 inst
.instruction
|= Rm
<< 8;
8069 /* There is no IT instruction in ARM mode. We
8070 process it to do the validation as if in
8071 thumb mode, just in case the code gets
8072 assembled for thumb using the unified syntax. */
8077 set_it_insn_type (IT_INSN
);
8078 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8079 now_it
.cc
= inst
.operands
[0].imm
;
8083 /* If there is only one register in the register list,
8084 then return its register number. Otherwise return -1. */
8086 only_one_reg_in_list (int range
)
8088 int i
= ffs (range
) - 1;
8089 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8093 encode_ldmstm(int from_push_pop_mnem
)
8095 int base_reg
= inst
.operands
[0].reg
;
8096 int range
= inst
.operands
[1].imm
;
8099 inst
.instruction
|= base_reg
<< 16;
8100 inst
.instruction
|= range
;
8102 if (inst
.operands
[1].writeback
)
8103 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8105 if (inst
.operands
[0].writeback
)
8107 inst
.instruction
|= WRITE_BACK
;
8108 /* Check for unpredictable uses of writeback. */
8109 if (inst
.instruction
& LOAD_BIT
)
8111 /* Not allowed in LDM type 2. */
8112 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8113 && ((range
& (1 << REG_PC
)) == 0))
8114 as_warn (_("writeback of base register is UNPREDICTABLE"));
8115 /* Only allowed if base reg not in list for other types. */
8116 else if (range
& (1 << base_reg
))
8117 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8121 /* Not allowed for type 2. */
8122 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8123 as_warn (_("writeback of base register is UNPREDICTABLE"));
8124 /* Only allowed if base reg not in list, or first in list. */
8125 else if ((range
& (1 << base_reg
))
8126 && (range
& ((1 << base_reg
) - 1)))
8127 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8131 /* If PUSH/POP has only one register, then use the A2 encoding. */
8132 one_reg
= only_one_reg_in_list (range
);
8133 if (from_push_pop_mnem
&& one_reg
>= 0)
8135 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8137 inst
.instruction
&= A_COND_MASK
;
8138 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8139 inst
.instruction
|= one_reg
<< 12;
8146 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8149 /* ARMv5TE load-consecutive (argument parse)
8158 constraint (inst
.operands
[0].reg
% 2 != 0,
8159 _("first transfer register must be even"));
8160 constraint (inst
.operands
[1].present
8161 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8162 _("can only transfer two consecutive registers"));
8163 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8164 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8166 if (!inst
.operands
[1].present
)
8167 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8169 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8170 register and the first register written; we have to diagnose
8171 overlap between the base and the second register written here. */
8173 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8174 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8175 as_warn (_("base register written back, and overlaps "
8176 "second transfer register"));
8178 if (!(inst
.instruction
& V4_STR_BIT
))
8180 /* For an index-register load, the index register must not overlap the
8181 destination (even if not write-back). */
8182 if (inst
.operands
[2].immisreg
8183 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8184 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8185 as_warn (_("index register overlaps transfer register"));
8187 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8188 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8194 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8195 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8196 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
8197 || inst
.operands
[1].negative
8198 /* This can arise if the programmer has written
8200 or if they have mistakenly used a register name as the last
8203 It is very difficult to distinguish between these two cases
8204 because "rX" might actually be a label. ie the register
8205 name has been occluded by a symbol of the same name. So we
8206 just generate a general 'bad addressing mode' type error
8207 message and leave it up to the programmer to discover the
8208 true cause and fix their mistake. */
8209 || (inst
.operands
[1].reg
== REG_PC
),
8212 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8213 || inst
.reloc
.exp
.X_add_number
!= 0,
8214 _("offset must be zero in ARM encoding"));
8216 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
8218 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8219 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8220 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8226 constraint (inst
.operands
[0].reg
% 2 != 0,
8227 _("even register required"));
8228 constraint (inst
.operands
[1].present
8229 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8230 _("can only load two consecutive registers"));
8231 /* If op 1 were present and equal to PC, this function wouldn't
8232 have been called in the first place. */
8233 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8235 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8236 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8239 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
8240 which is not a multiple of four is UNPREDICTABLE. */
8242 check_ldr_r15_aligned (void)
8244 constraint (!(inst
.operands
[1].immisreg
)
8245 && (inst
.operands
[0].reg
== REG_PC
8246 && inst
.operands
[1].reg
== REG_PC
8247 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
8248 _("ldr to register 15 must be 4-byte alligned"));
8254 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8255 if (!inst
.operands
[1].isreg
)
8256 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
8258 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
8259 check_ldr_r15_aligned ();
8265 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8267 if (inst
.operands
[1].preind
)
8269 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8270 || inst
.reloc
.exp
.X_add_number
!= 0,
8271 _("this instruction requires a post-indexed address"));
8273 inst
.operands
[1].preind
= 0;
8274 inst
.operands
[1].postind
= 1;
8275 inst
.operands
[1].writeback
= 1;
8277 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8278 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
8281 /* Halfword and signed-byte load/store operations. */
8286 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8288 if (!inst
.operands
[1].isreg
)
8289 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
8291 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
8297 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
8299 if (inst
.operands
[1].preind
)
8301 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8302 || inst
.reloc
.exp
.X_add_number
!= 0,
8303 _("this instruction requires a post-indexed address"));
8305 inst
.operands
[1].preind
= 0;
8306 inst
.operands
[1].postind
= 1;
8307 inst
.operands
[1].writeback
= 1;
8309 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8310 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
8313 /* Co-processor register load/store.
8314 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
8318 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8319 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8320 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8326 /* This restriction does not apply to mls (nor to mla in v6 or later). */
8327 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8328 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
8329 && !(inst
.instruction
& 0x00400000))
8330 as_tsktsk (_("Rd and Rm should be different in mla"));
8332 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8333 inst
.instruction
|= inst
.operands
[1].reg
;
8334 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8335 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8341 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8342 encode_arm_shifter_operand (1);
8345 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8352 top
= (inst
.instruction
& 0x00400000) != 0;
8353 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8354 _(":lower16: not allowed this instruction"));
8355 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8356 _(":upper16: not allowed instruction"));
8357 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8358 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8360 imm
= inst
.reloc
.exp
.X_add_number
;
8361 /* The value is in two pieces: 0:11, 16:19. */
8362 inst
.instruction
|= (imm
& 0x00000fff);
8363 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8367 static void do_vfp_nsyn_opcode (const char *);
8370 do_vfp_nsyn_mrs (void)
8372 if (inst
.operands
[0].isvec
)
8374 if (inst
.operands
[1].reg
!= 1)
8375 first_error (_("operand 1 must be FPSCR"));
8376 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8377 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8378 do_vfp_nsyn_opcode ("fmstat");
8380 else if (inst
.operands
[1].isvec
)
8381 do_vfp_nsyn_opcode ("fmrx");
8389 do_vfp_nsyn_msr (void)
8391 if (inst
.operands
[0].isvec
)
8392 do_vfp_nsyn_opcode ("fmxr");
8402 unsigned Rt
= inst
.operands
[0].reg
;
8404 if (thumb_mode
&& Rt
== REG_SP
)
8406 inst
.error
= BAD_SP
;
8410 /* APSR_ sets isvec. All other refs to PC are illegal. */
8411 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
8413 inst
.error
= BAD_PC
;
8417 /* If we get through parsing the register name, we just insert the number
8418 generated into the instruction without further validation. */
8419 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
8420 inst
.instruction
|= (Rt
<< 12);
8426 unsigned Rt
= inst
.operands
[1].reg
;
8429 reject_bad_reg (Rt
);
8430 else if (Rt
== REG_PC
)
8432 inst
.error
= BAD_PC
;
8436 /* If we get through parsing the register name, we just insert the number
8437 generated into the instruction without further validation. */
8438 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
8439 inst
.instruction
|= (Rt
<< 12);
8447 if (do_vfp_nsyn_mrs () == SUCCESS
)
8450 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8451 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8453 if (inst
.operands
[1].isreg
)
8455 br
= inst
.operands
[1].reg
;
8456 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8457 as_bad (_("bad register for mrs"));
8461 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8462 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8464 _("'APSR', 'CPSR' or 'SPSR' expected"));
8465 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8468 inst
.instruction
|= br
;
8471 /* Two possible forms:
8472 "{C|S}PSR_<field>, Rm",
8473 "{C|S}PSR_f, #expression". */
8478 if (do_vfp_nsyn_msr () == SUCCESS
)
8481 inst
.instruction
|= inst
.operands
[0].imm
;
8482 if (inst
.operands
[1].isreg
)
8483 inst
.instruction
|= inst
.operands
[1].reg
;
8486 inst
.instruction
|= INST_IMMEDIATE
;
8487 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8488 inst
.reloc
.pc_rel
= 0;
8495 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8497 if (!inst
.operands
[2].present
)
8498 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8499 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8500 inst
.instruction
|= inst
.operands
[1].reg
;
8501 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8503 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8504 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8505 as_tsktsk (_("Rd and Rm should be different in mul"));
8508 /* Long Multiply Parser
8509 UMULL RdLo, RdHi, Rm, Rs
8510 SMULL RdLo, RdHi, Rm, Rs
8511 UMLAL RdLo, RdHi, Rm, Rs
8512 SMLAL RdLo, RdHi, Rm, Rs. */
8517 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8518 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8519 inst
.instruction
|= inst
.operands
[2].reg
;
8520 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8522 /* rdhi and rdlo must be different. */
8523 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8524 as_tsktsk (_("rdhi and rdlo must be different"));
8526 /* rdhi, rdlo and rm must all be different before armv6. */
8527 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8528 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8529 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8530 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8536 if (inst
.operands
[0].present
8537 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8539 /* Architectural NOP hints are CPSR sets with no bits selected. */
8540 inst
.instruction
&= 0xf0000000;
8541 inst
.instruction
|= 0x0320f000;
8542 if (inst
.operands
[0].present
)
8543 inst
.instruction
|= inst
.operands
[0].imm
;
8547 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8548 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8549 Condition defaults to COND_ALWAYS.
8550 Error if Rd, Rn or Rm are R15. */
8555 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8556 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8557 inst
.instruction
|= inst
.operands
[2].reg
;
8558 if (inst
.operands
[3].present
)
8559 encode_arm_shift (3);
8562 /* ARM V6 PKHTB (Argument Parse). */
8567 if (!inst
.operands
[3].present
)
8569 /* If the shift specifier is omitted, turn the instruction
8570 into pkhbt rd, rm, rn. */
8571 inst
.instruction
&= 0xfff00010;
8572 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8573 inst
.instruction
|= inst
.operands
[1].reg
;
8574 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8578 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8579 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8580 inst
.instruction
|= inst
.operands
[2].reg
;
8581 encode_arm_shift (3);
8585 /* ARMv5TE: Preload-Cache
8586 MP Extensions: Preload for write
8590 Syntactically, like LDR with B=1, W=0, L=1. */
8595 constraint (!inst
.operands
[0].isreg
,
8596 _("'[' expected after PLD mnemonic"));
8597 constraint (inst
.operands
[0].postind
,
8598 _("post-indexed expression used in preload instruction"));
8599 constraint (inst
.operands
[0].writeback
,
8600 _("writeback used in preload instruction"));
8601 constraint (!inst
.operands
[0].preind
,
8602 _("unindexed addressing used in preload instruction"));
8603 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8606 /* ARMv7: PLI <addr_mode> */
8610 constraint (!inst
.operands
[0].isreg
,
8611 _("'[' expected after PLI mnemonic"));
8612 constraint (inst
.operands
[0].postind
,
8613 _("post-indexed expression used in preload instruction"));
8614 constraint (inst
.operands
[0].writeback
,
8615 _("writeback used in preload instruction"));
8616 constraint (!inst
.operands
[0].preind
,
8617 _("unindexed addressing used in preload instruction"));
8618 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8619 inst
.instruction
&= ~PRE_INDEX
;
8625 inst
.operands
[1] = inst
.operands
[0];
8626 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8627 inst
.operands
[0].isreg
= 1;
8628 inst
.operands
[0].writeback
= 1;
8629 inst
.operands
[0].reg
= REG_SP
;
8630 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
8633 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8634 word at the specified address and the following word
8636 Unconditionally executed.
8637 Error if Rn is R15. */
8642 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8643 if (inst
.operands
[0].writeback
)
8644 inst
.instruction
|= WRITE_BACK
;
8647 /* ARM V6 ssat (argument parse). */
8652 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8653 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8654 inst
.instruction
|= inst
.operands
[2].reg
;
8656 if (inst
.operands
[3].present
)
8657 encode_arm_shift (3);
8660 /* ARM V6 usat (argument parse). */
8665 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8666 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8667 inst
.instruction
|= inst
.operands
[2].reg
;
8669 if (inst
.operands
[3].present
)
8670 encode_arm_shift (3);
8673 /* ARM V6 ssat16 (argument parse). */
8678 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8679 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8680 inst
.instruction
|= inst
.operands
[2].reg
;
8686 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8687 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8688 inst
.instruction
|= inst
.operands
[2].reg
;
8691 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8692 preserving the other bits.
8694 setend <endian_specifier>, where <endian_specifier> is either
8700 if (warn_on_deprecated
8701 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8702 as_warn (_("setend use is deprecated for ARMv8"));
8704 if (inst
.operands
[0].imm
)
8705 inst
.instruction
|= 0x200;
8711 unsigned int Rm
= (inst
.operands
[1].present
8712 ? inst
.operands
[1].reg
8713 : inst
.operands
[0].reg
);
8715 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8716 inst
.instruction
|= Rm
;
8717 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8719 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8720 inst
.instruction
|= SHIFT_BY_REG
;
8721 /* PR 12854: Error on extraneous shifts. */
8722 constraint (inst
.operands
[2].shifted
,
8723 _("extraneous shift as part of operand to shift insn"));
8726 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8732 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8733 inst
.reloc
.pc_rel
= 0;
8739 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8740 inst
.reloc
.pc_rel
= 0;
8746 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8747 inst
.reloc
.pc_rel
= 0;
8750 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8751 SMLAxy{cond} Rd,Rm,Rs,Rn
8752 SMLAWy{cond} Rd,Rm,Rs,Rn
8753 Error if any register is R15. */
8758 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8759 inst
.instruction
|= inst
.operands
[1].reg
;
8760 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8761 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8764 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8765 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8766 Error if any register is R15.
8767 Warning if Rdlo == Rdhi. */
8772 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8773 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8774 inst
.instruction
|= inst
.operands
[2].reg
;
8775 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8777 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8778 as_tsktsk (_("rdhi and rdlo must be different"));
8781 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8782 SMULxy{cond} Rd,Rm,Rs
8783 Error if any register is R15. */
8788 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8789 inst
.instruction
|= inst
.operands
[1].reg
;
8790 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8793 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8794 the same for both ARM and Thumb-2. */
8801 if (inst
.operands
[0].present
)
8803 reg
= inst
.operands
[0].reg
;
8804 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8809 inst
.instruction
|= reg
<< 16;
8810 inst
.instruction
|= inst
.operands
[1].imm
;
8811 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8812 inst
.instruction
|= WRITE_BACK
;
8815 /* ARM V6 strex (argument parse). */
8820 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8821 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8822 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8823 || inst
.operands
[2].negative
8824 /* See comment in do_ldrex(). */
8825 || (inst
.operands
[2].reg
== REG_PC
),
8828 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8829 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8831 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8832 || inst
.reloc
.exp
.X_add_number
!= 0,
8833 _("offset must be zero in ARM encoding"));
8835 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8836 inst
.instruction
|= inst
.operands
[1].reg
;
8837 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8838 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8844 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8845 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8846 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8847 || inst
.operands
[2].negative
,
8850 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8851 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8859 constraint (inst
.operands
[1].reg
% 2 != 0,
8860 _("even register required"));
8861 constraint (inst
.operands
[2].present
8862 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8863 _("can only store two consecutive registers"));
8864 /* If op 2 were present and equal to PC, this function wouldn't
8865 have been called in the first place. */
8866 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8868 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8869 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8870 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8874 inst
.instruction
|= inst
.operands
[1].reg
;
8875 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8882 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8883 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8891 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8892 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8897 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8898 extends it to 32-bits, and adds the result to a value in another
8899 register. You can specify a rotation by 0, 8, 16, or 24 bits
8900 before extracting the 16-bit value.
8901 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8902 Condition defaults to COND_ALWAYS.
8903 Error if any register uses R15. */
8908 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8909 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8910 inst
.instruction
|= inst
.operands
[2].reg
;
8911 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8916 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8917 Condition defaults to COND_ALWAYS.
8918 Error if any register uses R15. */
8923 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8924 inst
.instruction
|= inst
.operands
[1].reg
;
8925 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8928 /* VFP instructions. In a logical order: SP variant first, monad
8929 before dyad, arithmetic then move then load/store. */
8932 do_vfp_sp_monadic (void)
8934 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8935 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8939 do_vfp_sp_dyadic (void)
8941 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8942 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8943 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8947 do_vfp_sp_compare_z (void)
8949 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8953 do_vfp_dp_sp_cvt (void)
8955 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8956 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8960 do_vfp_sp_dp_cvt (void)
8962 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8963 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8967 do_vfp_reg_from_sp (void)
8969 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8970 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8974 do_vfp_reg2_from_sp2 (void)
8976 constraint (inst
.operands
[2].imm
!= 2,
8977 _("only two consecutive VFP SP registers allowed here"));
8978 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8979 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8980 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8984 do_vfp_sp_from_reg (void)
8986 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8987 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8991 do_vfp_sp2_from_reg2 (void)
8993 constraint (inst
.operands
[0].imm
!= 2,
8994 _("only two consecutive VFP SP registers allowed here"));
8995 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8996 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8997 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9001 do_vfp_sp_ldst (void)
9003 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9004 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9008 do_vfp_dp_ldst (void)
9010 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9011 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9016 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9018 if (inst
.operands
[0].writeback
)
9019 inst
.instruction
|= WRITE_BACK
;
9021 constraint (ldstm_type
!= VFP_LDSTMIA
,
9022 _("this addressing mode requires base-register writeback"));
9023 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9024 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9025 inst
.instruction
|= inst
.operands
[1].imm
;
9029 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9033 if (inst
.operands
[0].writeback
)
9034 inst
.instruction
|= WRITE_BACK
;
9036 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9037 _("this addressing mode requires base-register writeback"));
9039 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9040 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9042 count
= inst
.operands
[1].imm
<< 1;
9043 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9046 inst
.instruction
|= count
;
9050 do_vfp_sp_ldstmia (void)
9052 vfp_sp_ldstm (VFP_LDSTMIA
);
9056 do_vfp_sp_ldstmdb (void)
9058 vfp_sp_ldstm (VFP_LDSTMDB
);
9062 do_vfp_dp_ldstmia (void)
9064 vfp_dp_ldstm (VFP_LDSTMIA
);
9068 do_vfp_dp_ldstmdb (void)
9070 vfp_dp_ldstm (VFP_LDSTMDB
);
9074 do_vfp_xp_ldstmia (void)
9076 vfp_dp_ldstm (VFP_LDSTMIAX
);
9080 do_vfp_xp_ldstmdb (void)
9082 vfp_dp_ldstm (VFP_LDSTMDBX
);
9086 do_vfp_dp_rd_rm (void)
9088 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9089 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9093 do_vfp_dp_rn_rd (void)
9095 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9096 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9100 do_vfp_dp_rd_rn (void)
9102 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9103 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9107 do_vfp_dp_rd_rn_rm (void)
9109 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9110 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9111 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9117 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9121 do_vfp_dp_rm_rd_rn (void)
9123 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9124 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9125 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9128 /* VFPv3 instructions. */
9130 do_vfp_sp_const (void)
9132 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9133 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9134 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9138 do_vfp_dp_const (void)
9140 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9141 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9142 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9146 vfp_conv (int srcsize
)
9148 int immbits
= srcsize
- inst
.operands
[1].imm
;
9150 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9152 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9153 i.e. immbits must be in range 0 - 16. */
9154 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9157 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9159 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9160 i.e. immbits must be in range 0 - 31. */
9161 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9165 inst
.instruction
|= (immbits
& 1) << 5;
9166 inst
.instruction
|= (immbits
>> 1);
9170 do_vfp_sp_conv_16 (void)
9172 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9177 do_vfp_dp_conv_16 (void)
9179 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9184 do_vfp_sp_conv_32 (void)
9186 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9191 do_vfp_dp_conv_32 (void)
9193 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9197 /* FPA instructions. Also in a logical order. */
9202 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9203 inst
.instruction
|= inst
.operands
[1].reg
;
9207 do_fpa_ldmstm (void)
9209 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9210 switch (inst
.operands
[1].imm
)
9212 case 1: inst
.instruction
|= CP_T_X
; break;
9213 case 2: inst
.instruction
|= CP_T_Y
; break;
9214 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
9219 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
9221 /* The instruction specified "ea" or "fd", so we can only accept
9222 [Rn]{!}. The instruction does not really support stacking or
9223 unstacking, so we have to emulate these by setting appropriate
9224 bits and offsets. */
9225 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9226 || inst
.reloc
.exp
.X_add_number
!= 0,
9227 _("this instruction does not support indexing"));
9229 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
9230 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
9232 if (!(inst
.instruction
& INDEX_UP
))
9233 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
9235 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
9237 inst
.operands
[2].preind
= 0;
9238 inst
.operands
[2].postind
= 1;
9242 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9245 /* iWMMXt instructions: strictly in alphabetical order. */
9248 do_iwmmxt_tandorc (void)
9250 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
9254 do_iwmmxt_textrc (void)
9256 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9257 inst
.instruction
|= inst
.operands
[1].imm
;
9261 do_iwmmxt_textrm (void)
9263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9264 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9265 inst
.instruction
|= inst
.operands
[2].imm
;
9269 do_iwmmxt_tinsr (void)
9271 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9272 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9273 inst
.instruction
|= inst
.operands
[2].imm
;
9277 do_iwmmxt_tmia (void)
9279 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9280 inst
.instruction
|= inst
.operands
[1].reg
;
9281 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9285 do_iwmmxt_waligni (void)
9287 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9288 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9289 inst
.instruction
|= inst
.operands
[2].reg
;
9290 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
9294 do_iwmmxt_wmerge (void)
9296 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9297 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9298 inst
.instruction
|= inst
.operands
[2].reg
;
9299 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
9303 do_iwmmxt_wmov (void)
9305 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
9306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9307 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9308 inst
.instruction
|= inst
.operands
[1].reg
;
9312 do_iwmmxt_wldstbh (void)
9315 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9317 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
9319 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
9320 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
9324 do_iwmmxt_wldstw (void)
9326 /* RIWR_RIWC clears .isreg for a control register. */
9327 if (!inst
.operands
[0].isreg
)
9329 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9330 inst
.instruction
|= 0xf0000000;
9333 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9334 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9338 do_iwmmxt_wldstd (void)
9340 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9341 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
9342 && inst
.operands
[1].immisreg
)
9344 inst
.instruction
&= ~0x1a000ff;
9345 inst
.instruction
|= (0xf << 28);
9346 if (inst
.operands
[1].preind
)
9347 inst
.instruction
|= PRE_INDEX
;
9348 if (!inst
.operands
[1].negative
)
9349 inst
.instruction
|= INDEX_UP
;
9350 if (inst
.operands
[1].writeback
)
9351 inst
.instruction
|= WRITE_BACK
;
9352 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9353 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9354 inst
.instruction
|= inst
.operands
[1].imm
;
9357 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
9361 do_iwmmxt_wshufh (void)
9363 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9364 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9365 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
9366 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
9370 do_iwmmxt_wzero (void)
9372 /* WZERO reg is an alias for WANDN reg, reg, reg. */
9373 inst
.instruction
|= inst
.operands
[0].reg
;
9374 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9375 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9379 do_iwmmxt_wrwrwr_or_imm5 (void)
9381 if (inst
.operands
[2].isreg
)
9384 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
9385 _("immediate operand requires iWMMXt2"));
9387 if (inst
.operands
[2].imm
== 0)
9389 switch ((inst
.instruction
>> 20) & 0xf)
9395 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9396 inst
.operands
[2].imm
= 16;
9397 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9403 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9404 inst
.operands
[2].imm
= 32;
9405 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9412 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9414 wrn
= (inst
.instruction
>> 16) & 0xf;
9415 inst
.instruction
&= 0xff0fff0f;
9416 inst
.instruction
|= wrn
;
9417 /* Bail out here; the instruction is now assembled. */
9422 /* Map 32 -> 0, etc. */
9423 inst
.operands
[2].imm
&= 0x1f;
9424 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9428 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9429 operations first, then control, shift, and load/store. */
9431 /* Insns like "foo X,Y,Z". */
9434 do_mav_triple (void)
9436 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9437 inst
.instruction
|= inst
.operands
[1].reg
;
9438 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9441 /* Insns like "foo W,X,Y,Z".
9442 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9447 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9448 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9449 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9450 inst
.instruction
|= inst
.operands
[3].reg
;
9453 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9457 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9460 /* Maverick shift immediate instructions.
9461 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9462 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9467 int imm
= inst
.operands
[2].imm
;
9469 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9470 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9472 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9473 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9474 Bit 4 should be 0. */
9475 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9477 inst
.instruction
|= imm
;
9480 /* XScale instructions. Also sorted arithmetic before move. */
9482 /* Xscale multiply-accumulate (argument parse)
9485 MIAxycc acc0,Rm,Rs. */
9490 inst
.instruction
|= inst
.operands
[1].reg
;
9491 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9494 /* Xscale move-accumulator-register (argument parse)
9496 MARcc acc0,RdLo,RdHi. */
9501 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9502 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9505 /* Xscale move-register-accumulator (argument parse)
9507 MRAcc RdLo,RdHi,acc0. */
9512 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9513 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9514 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9517 /* Encoding functions relevant only to Thumb. */
9519 /* inst.operands[i] is a shifted-register operand; encode
9520 it into inst.instruction in the format used by Thumb32. */
9523 encode_thumb32_shifted_operand (int i
)
9525 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9526 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9528 constraint (inst
.operands
[i
].immisreg
,
9529 _("shift by register not allowed in thumb mode"));
9530 inst
.instruction
|= inst
.operands
[i
].reg
;
9531 if (shift
== SHIFT_RRX
)
9532 inst
.instruction
|= SHIFT_ROR
<< 4;
9535 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9536 _("expression too complex"));
9538 constraint (value
> 32
9539 || (value
== 32 && (shift
== SHIFT_LSL
9540 || shift
== SHIFT_ROR
)),
9541 _("shift expression is too large"));
9545 else if (value
== 32)
9548 inst
.instruction
|= shift
<< 4;
9549 inst
.instruction
|= (value
& 0x1c) << 10;
9550 inst
.instruction
|= (value
& 0x03) << 6;
9555 /* inst.operands[i] was set up by parse_address. Encode it into a
9556 Thumb32 format load or store instruction. Reject forms that cannot
9557 be used with such instructions. If is_t is true, reject forms that
9558 cannot be used with a T instruction; if is_d is true, reject forms
9559 that cannot be used with a D instruction. If it is a store insn,
9563 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9565 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9567 constraint (!inst
.operands
[i
].isreg
,
9568 _("Instruction does not support =N addresses"));
9570 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9571 if (inst
.operands
[i
].immisreg
)
9573 constraint (is_pc
, BAD_PC_ADDRESSING
);
9574 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9575 constraint (inst
.operands
[i
].negative
,
9576 _("Thumb does not support negative register indexing"));
9577 constraint (inst
.operands
[i
].postind
,
9578 _("Thumb does not support register post-indexing"));
9579 constraint (inst
.operands
[i
].writeback
,
9580 _("Thumb does not support register indexing with writeback"));
9581 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9582 _("Thumb supports only LSL in shifted register indexing"));
9584 inst
.instruction
|= inst
.operands
[i
].imm
;
9585 if (inst
.operands
[i
].shifted
)
9587 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9588 _("expression too complex"));
9589 constraint (inst
.reloc
.exp
.X_add_number
< 0
9590 || inst
.reloc
.exp
.X_add_number
> 3,
9591 _("shift out of range"));
9592 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9594 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9596 else if (inst
.operands
[i
].preind
)
9598 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9599 constraint (is_t
&& inst
.operands
[i
].writeback
,
9600 _("cannot use writeback with this instruction"));
9601 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
9606 inst
.instruction
|= 0x01000000;
9607 if (inst
.operands
[i
].writeback
)
9608 inst
.instruction
|= 0x00200000;
9612 inst
.instruction
|= 0x00000c00;
9613 if (inst
.operands
[i
].writeback
)
9614 inst
.instruction
|= 0x00000100;
9616 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9618 else if (inst
.operands
[i
].postind
)
9620 gas_assert (inst
.operands
[i
].writeback
);
9621 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9622 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9625 inst
.instruction
|= 0x00200000;
9627 inst
.instruction
|= 0x00000900;
9628 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9630 else /* unindexed - only for coprocessor */
9631 inst
.error
= _("instruction does not accept unindexed addressing");
9634 /* Table of Thumb instructions which exist in both 16- and 32-bit
9635 encodings (the latter only in post-V6T2 cores). The index is the
9636 value used in the insns table below. When there is more than one
9637 possible 16-bit encoding for the instruction, this table always
9639 Also contains several pseudo-instructions used during relaxation. */
9640 #define T16_32_TAB \
9641 X(_adc, 4140, eb400000), \
9642 X(_adcs, 4140, eb500000), \
9643 X(_add, 1c00, eb000000), \
9644 X(_adds, 1c00, eb100000), \
9645 X(_addi, 0000, f1000000), \
9646 X(_addis, 0000, f1100000), \
9647 X(_add_pc,000f, f20f0000), \
9648 X(_add_sp,000d, f10d0000), \
9649 X(_adr, 000f, f20f0000), \
9650 X(_and, 4000, ea000000), \
9651 X(_ands, 4000, ea100000), \
9652 X(_asr, 1000, fa40f000), \
9653 X(_asrs, 1000, fa50f000), \
9654 X(_b, e000, f000b000), \
9655 X(_bcond, d000, f0008000), \
9656 X(_bic, 4380, ea200000), \
9657 X(_bics, 4380, ea300000), \
9658 X(_cmn, 42c0, eb100f00), \
9659 X(_cmp, 2800, ebb00f00), \
9660 X(_cpsie, b660, f3af8400), \
9661 X(_cpsid, b670, f3af8600), \
9662 X(_cpy, 4600, ea4f0000), \
9663 X(_dec_sp,80dd, f1ad0d00), \
9664 X(_eor, 4040, ea800000), \
9665 X(_eors, 4040, ea900000), \
9666 X(_inc_sp,00dd, f10d0d00), \
9667 X(_ldmia, c800, e8900000), \
9668 X(_ldr, 6800, f8500000), \
9669 X(_ldrb, 7800, f8100000), \
9670 X(_ldrh, 8800, f8300000), \
9671 X(_ldrsb, 5600, f9100000), \
9672 X(_ldrsh, 5e00, f9300000), \
9673 X(_ldr_pc,4800, f85f0000), \
9674 X(_ldr_pc2,4800, f85f0000), \
9675 X(_ldr_sp,9800, f85d0000), \
9676 X(_lsl, 0000, fa00f000), \
9677 X(_lsls, 0000, fa10f000), \
9678 X(_lsr, 0800, fa20f000), \
9679 X(_lsrs, 0800, fa30f000), \
9680 X(_mov, 2000, ea4f0000), \
9681 X(_movs, 2000, ea5f0000), \
9682 X(_mul, 4340, fb00f000), \
9683 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9684 X(_mvn, 43c0, ea6f0000), \
9685 X(_mvns, 43c0, ea7f0000), \
9686 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9687 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9688 X(_orr, 4300, ea400000), \
9689 X(_orrs, 4300, ea500000), \
9690 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9691 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9692 X(_rev, ba00, fa90f080), \
9693 X(_rev16, ba40, fa90f090), \
9694 X(_revsh, bac0, fa90f0b0), \
9695 X(_ror, 41c0, fa60f000), \
9696 X(_rors, 41c0, fa70f000), \
9697 X(_sbc, 4180, eb600000), \
9698 X(_sbcs, 4180, eb700000), \
9699 X(_stmia, c000, e8800000), \
9700 X(_str, 6000, f8400000), \
9701 X(_strb, 7000, f8000000), \
9702 X(_strh, 8000, f8200000), \
9703 X(_str_sp,9000, f84d0000), \
9704 X(_sub, 1e00, eba00000), \
9705 X(_subs, 1e00, ebb00000), \
9706 X(_subi, 8000, f1a00000), \
9707 X(_subis, 8000, f1b00000), \
9708 X(_sxtb, b240, fa4ff080), \
9709 X(_sxth, b200, fa0ff080), \
9710 X(_tst, 4200, ea100f00), \
9711 X(_uxtb, b2c0, fa5ff080), \
9712 X(_uxth, b280, fa1ff080), \
9713 X(_nop, bf00, f3af8000), \
9714 X(_yield, bf10, f3af8001), \
9715 X(_wfe, bf20, f3af8002), \
9716 X(_wfi, bf30, f3af8003), \
9717 X(_sev, bf40, f3af8004), \
9718 X(_sevl, bf50, f3af8005), \
9719 X(_udf, de00, f7f0a000)
9721 /* To catch errors in encoding functions, the codes are all offset by
9722 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9723 as 16-bit instructions. */
9724 #define X(a,b,c) T_MNEM##a
9725 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9728 #define X(a,b,c) 0x##b
9729 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9730 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9733 #define X(a,b,c) 0x##c
9734 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9735 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9736 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9740 /* Thumb instruction encoders, in alphabetical order. */
9745 do_t_add_sub_w (void)
9749 Rd
= inst
.operands
[0].reg
;
9750 Rn
= inst
.operands
[1].reg
;
9752 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9753 is the SP-{plus,minus}-immediate form of the instruction. */
9755 constraint (Rd
== REG_PC
, BAD_PC
);
9757 reject_bad_reg (Rd
);
9759 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9760 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9763 /* Parse an add or subtract instruction. We get here with inst.instruction
9764 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9771 Rd
= inst
.operands
[0].reg
;
9772 Rs
= (inst
.operands
[1].present
9773 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9774 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9777 set_it_insn_type_last ();
9785 flags
= (inst
.instruction
== T_MNEM_adds
9786 || inst
.instruction
== T_MNEM_subs
);
9788 narrow
= !in_it_block ();
9790 narrow
= in_it_block ();
9791 if (!inst
.operands
[2].isreg
)
9795 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9797 add
= (inst
.instruction
== T_MNEM_add
9798 || inst
.instruction
== T_MNEM_adds
);
9800 if (inst
.size_req
!= 4)
9802 /* Attempt to use a narrow opcode, with relaxation if
9804 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9805 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9806 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9807 opcode
= T_MNEM_add_sp
;
9808 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9809 opcode
= T_MNEM_add_pc
;
9810 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9813 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9815 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9819 inst
.instruction
= THUMB_OP16(opcode
);
9820 inst
.instruction
|= (Rd
<< 4) | Rs
;
9821 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9822 if (inst
.size_req
!= 2)
9823 inst
.relax
= opcode
;
9826 constraint (inst
.size_req
== 2, BAD_HIREG
);
9828 if (inst
.size_req
== 4
9829 || (inst
.size_req
!= 2 && !opcode
))
9833 constraint (add
, BAD_PC
);
9834 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9835 _("only SUBS PC, LR, #const allowed"));
9836 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9837 _("expression too complex"));
9838 constraint (inst
.reloc
.exp
.X_add_number
< 0
9839 || inst
.reloc
.exp
.X_add_number
> 0xff,
9840 _("immediate value out of range"));
9841 inst
.instruction
= T2_SUBS_PC_LR
9842 | inst
.reloc
.exp
.X_add_number
;
9843 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9846 else if (Rs
== REG_PC
)
9848 /* Always use addw/subw. */
9849 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9850 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9854 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9855 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9858 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9860 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9862 inst
.instruction
|= Rd
<< 8;
9863 inst
.instruction
|= Rs
<< 16;
9868 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9869 unsigned int shift
= inst
.operands
[2].shift_kind
;
9871 Rn
= inst
.operands
[2].reg
;
9872 /* See if we can do this with a 16-bit instruction. */
9873 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9875 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9880 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9881 || inst
.instruction
== T_MNEM_add
)
9884 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9888 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9890 /* Thumb-1 cores (except v6-M) require at least one high
9891 register in a narrow non flag setting add. */
9892 if (Rd
> 7 || Rn
> 7
9893 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9894 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9901 inst
.instruction
= T_OPCODE_ADD_HI
;
9902 inst
.instruction
|= (Rd
& 8) << 4;
9903 inst
.instruction
|= (Rd
& 7);
9904 inst
.instruction
|= Rn
<< 3;
9910 constraint (Rd
== REG_PC
, BAD_PC
);
9911 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9912 constraint (Rs
== REG_PC
, BAD_PC
);
9913 reject_bad_reg (Rn
);
9915 /* If we get here, it can't be done in 16 bits. */
9916 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9917 _("shift must be constant"));
9918 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9919 inst
.instruction
|= Rd
<< 8;
9920 inst
.instruction
|= Rs
<< 16;
9921 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
9922 _("shift value over 3 not allowed in thumb mode"));
9923 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
9924 _("only LSL shift allowed in thumb mode"));
9925 encode_thumb32_shifted_operand (2);
9930 constraint (inst
.instruction
== T_MNEM_adds
9931 || inst
.instruction
== T_MNEM_subs
,
9934 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9936 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9937 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9940 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9942 inst
.instruction
|= (Rd
<< 4) | Rs
;
9943 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9947 Rn
= inst
.operands
[2].reg
;
9948 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9950 /* We now have Rd, Rs, and Rn set to registers. */
9951 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9953 /* Can't do this for SUB. */
9954 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9955 inst
.instruction
= T_OPCODE_ADD_HI
;
9956 inst
.instruction
|= (Rd
& 8) << 4;
9957 inst
.instruction
|= (Rd
& 7);
9959 inst
.instruction
|= Rn
<< 3;
9961 inst
.instruction
|= Rs
<< 3;
9963 constraint (1, _("dest must overlap one source register"));
9967 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9968 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9969 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9979 Rd
= inst
.operands
[0].reg
;
9980 reject_bad_reg (Rd
);
9982 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9984 /* Defer to section relaxation. */
9985 inst
.relax
= inst
.instruction
;
9986 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9987 inst
.instruction
|= Rd
<< 4;
9989 else if (unified_syntax
&& inst
.size_req
!= 2)
9991 /* Generate a 32-bit opcode. */
9992 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9993 inst
.instruction
|= Rd
<< 8;
9994 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9995 inst
.reloc
.pc_rel
= 1;
9999 /* Generate a 16-bit opcode. */
10000 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10001 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10002 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10003 inst
.reloc
.pc_rel
= 1;
10005 inst
.instruction
|= Rd
<< 4;
10009 /* Arithmetic instructions for which there is just one 16-bit
10010 instruction encoding, and it allows only two low registers.
10011 For maximal compatibility with ARM syntax, we allow three register
10012 operands even when Thumb-32 instructions are not available, as long
10013 as the first two are identical. For instance, both "sbc r0,r1" and
10014 "sbc r0,r0,r1" are allowed. */
10020 Rd
= inst
.operands
[0].reg
;
10021 Rs
= (inst
.operands
[1].present
10022 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10023 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10024 Rn
= inst
.operands
[2].reg
;
10026 reject_bad_reg (Rd
);
10027 reject_bad_reg (Rs
);
10028 if (inst
.operands
[2].isreg
)
10029 reject_bad_reg (Rn
);
10031 if (unified_syntax
)
10033 if (!inst
.operands
[2].isreg
)
10035 /* For an immediate, we always generate a 32-bit opcode;
10036 section relaxation will shrink it later if possible. */
10037 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10038 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10039 inst
.instruction
|= Rd
<< 8;
10040 inst
.instruction
|= Rs
<< 16;
10041 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10045 bfd_boolean narrow
;
10047 /* See if we can do this with a 16-bit instruction. */
10048 if (THUMB_SETS_FLAGS (inst
.instruction
))
10049 narrow
= !in_it_block ();
10051 narrow
= in_it_block ();
10053 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10055 if (inst
.operands
[2].shifted
)
10057 if (inst
.size_req
== 4)
10063 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10064 inst
.instruction
|= Rd
;
10065 inst
.instruction
|= Rn
<< 3;
10069 /* If we get here, it can't be done in 16 bits. */
10070 constraint (inst
.operands
[2].shifted
10071 && inst
.operands
[2].immisreg
,
10072 _("shift must be constant"));
10073 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10074 inst
.instruction
|= Rd
<< 8;
10075 inst
.instruction
|= Rs
<< 16;
10076 encode_thumb32_shifted_operand (2);
10081 /* On its face this is a lie - the instruction does set the
10082 flags. However, the only supported mnemonic in this mode
10083 says it doesn't. */
10084 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10086 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10087 _("unshifted register required"));
10088 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10089 constraint (Rd
!= Rs
,
10090 _("dest and source1 must be the same register"));
10092 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10093 inst
.instruction
|= Rd
;
10094 inst
.instruction
|= Rn
<< 3;
10098 /* Similarly, but for instructions where the arithmetic operation is
10099 commutative, so we can allow either of them to be different from
10100 the destination operand in a 16-bit instruction. For instance, all
10101 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10108 Rd
= inst
.operands
[0].reg
;
10109 Rs
= (inst
.operands
[1].present
10110 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10111 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10112 Rn
= inst
.operands
[2].reg
;
10114 reject_bad_reg (Rd
);
10115 reject_bad_reg (Rs
);
10116 if (inst
.operands
[2].isreg
)
10117 reject_bad_reg (Rn
);
10119 if (unified_syntax
)
10121 if (!inst
.operands
[2].isreg
)
10123 /* For an immediate, we always generate a 32-bit opcode;
10124 section relaxation will shrink it later if possible. */
10125 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10126 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10127 inst
.instruction
|= Rd
<< 8;
10128 inst
.instruction
|= Rs
<< 16;
10129 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10133 bfd_boolean narrow
;
10135 /* See if we can do this with a 16-bit instruction. */
10136 if (THUMB_SETS_FLAGS (inst
.instruction
))
10137 narrow
= !in_it_block ();
10139 narrow
= in_it_block ();
10141 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10143 if (inst
.operands
[2].shifted
)
10145 if (inst
.size_req
== 4)
10152 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10153 inst
.instruction
|= Rd
;
10154 inst
.instruction
|= Rn
<< 3;
10159 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10160 inst
.instruction
|= Rd
;
10161 inst
.instruction
|= Rs
<< 3;
10166 /* If we get here, it can't be done in 16 bits. */
10167 constraint (inst
.operands
[2].shifted
10168 && inst
.operands
[2].immisreg
,
10169 _("shift must be constant"));
10170 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10171 inst
.instruction
|= Rd
<< 8;
10172 inst
.instruction
|= Rs
<< 16;
10173 encode_thumb32_shifted_operand (2);
10178 /* On its face this is a lie - the instruction does set the
10179 flags. However, the only supported mnemonic in this mode
10180 says it doesn't. */
10181 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10183 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10184 _("unshifted register required"));
10185 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10187 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10188 inst
.instruction
|= Rd
;
10191 inst
.instruction
|= Rn
<< 3;
10193 inst
.instruction
|= Rs
<< 3;
10195 constraint (1, _("dest must overlap one source register"));
10203 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
10204 constraint (msb
> 32, _("bit-field extends past end of register"));
10205 /* The instruction encoding stores the LSB and MSB,
10206 not the LSB and width. */
10207 Rd
= inst
.operands
[0].reg
;
10208 reject_bad_reg (Rd
);
10209 inst
.instruction
|= Rd
<< 8;
10210 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
10211 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
10212 inst
.instruction
|= msb
- 1;
10221 Rd
= inst
.operands
[0].reg
;
10222 reject_bad_reg (Rd
);
10224 /* #0 in second position is alternative syntax for bfc, which is
10225 the same instruction but with REG_PC in the Rm field. */
10226 if (!inst
.operands
[1].isreg
)
10230 Rn
= inst
.operands
[1].reg
;
10231 reject_bad_reg (Rn
);
10234 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
10235 constraint (msb
> 32, _("bit-field extends past end of register"));
10236 /* The instruction encoding stores the LSB and MSB,
10237 not the LSB and width. */
10238 inst
.instruction
|= Rd
<< 8;
10239 inst
.instruction
|= Rn
<< 16;
10240 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10241 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10242 inst
.instruction
|= msb
- 1;
10250 Rd
= inst
.operands
[0].reg
;
10251 Rn
= inst
.operands
[1].reg
;
10253 reject_bad_reg (Rd
);
10254 reject_bad_reg (Rn
);
10256 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
10257 _("bit-field extends past end of register"));
10258 inst
.instruction
|= Rd
<< 8;
10259 inst
.instruction
|= Rn
<< 16;
10260 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
10261 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
10262 inst
.instruction
|= inst
.operands
[3].imm
- 1;
10265 /* ARM V5 Thumb BLX (argument parse)
10266 BLX <target_addr> which is BLX(1)
10267 BLX <Rm> which is BLX(2)
10268 Unfortunately, there are two different opcodes for this mnemonic.
10269 So, the insns[].value is not used, and the code here zaps values
10270 into inst.instruction.
10272 ??? How to take advantage of the additional two bits of displacement
10273 available in Thumb32 mode? Need new relocation? */
10278 set_it_insn_type_last ();
10280 if (inst
.operands
[0].isreg
)
10282 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10283 /* We have a register, so this is BLX(2). */
10284 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10288 /* No register. This must be BLX(1). */
10289 inst
.instruction
= 0xf000e800;
10290 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
10302 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
10304 if (in_it_block ())
10306 /* Conditional branches inside IT blocks are encoded as unconditional
10308 cond
= COND_ALWAYS
;
10313 if (cond
!= COND_ALWAYS
)
10314 opcode
= T_MNEM_bcond
;
10316 opcode
= inst
.instruction
;
10319 && (inst
.size_req
== 4
10320 || (inst
.size_req
!= 2
10321 && (inst
.operands
[0].hasreloc
10322 || inst
.reloc
.exp
.X_op
== O_constant
))))
10324 inst
.instruction
= THUMB_OP32(opcode
);
10325 if (cond
== COND_ALWAYS
)
10326 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
10329 gas_assert (cond
!= 0xF);
10330 inst
.instruction
|= cond
<< 22;
10331 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
10336 inst
.instruction
= THUMB_OP16(opcode
);
10337 if (cond
== COND_ALWAYS
)
10338 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
10341 inst
.instruction
|= cond
<< 8;
10342 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
10344 /* Allow section relaxation. */
10345 if (unified_syntax
&& inst
.size_req
!= 2)
10346 inst
.relax
= opcode
;
10348 inst
.reloc
.type
= reloc
;
10349 inst
.reloc
.pc_rel
= 1;
10352 /* Actually do the work for Thumb state bkpt and hlt. The only difference
10353 between the two is the maximum immediate allowed - which is passed in
10356 do_t_bkpt_hlt1 (int range
)
10358 constraint (inst
.cond
!= COND_ALWAYS
,
10359 _("instruction is always unconditional"));
10360 if (inst
.operands
[0].present
)
10362 constraint (inst
.operands
[0].imm
> range
,
10363 _("immediate value out of range"));
10364 inst
.instruction
|= inst
.operands
[0].imm
;
10367 set_it_insn_type (NEUTRAL_IT_INSN
);
10373 do_t_bkpt_hlt1 (63);
10379 do_t_bkpt_hlt1 (255);
10383 do_t_branch23 (void)
10385 set_it_insn_type_last ();
10386 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
10388 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
10389 this file. We used to simply ignore the PLT reloc type here --
10390 the branch encoding is now needed to deal with TLSCALL relocs.
10391 So if we see a PLT reloc now, put it back to how it used to be to
10392 keep the preexisting behaviour. */
10393 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
10394 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
10396 #if defined(OBJ_COFF)
10397 /* If the destination of the branch is a defined symbol which does not have
10398 the THUMB_FUNC attribute, then we must be calling a function which has
10399 the (interfacearm) attribute. We look for the Thumb entry point to that
10400 function and change the branch to refer to that function instead. */
10401 if ( inst
.reloc
.exp
.X_op
== O_symbol
10402 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10403 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10404 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10405 inst
.reloc
.exp
.X_add_symbol
=
10406 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10413 set_it_insn_type_last ();
10414 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10415 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10416 should cause the alignment to be checked once it is known. This is
10417 because BX PC only works if the instruction is word aligned. */
10425 set_it_insn_type_last ();
10426 Rm
= inst
.operands
[0].reg
;
10427 reject_bad_reg (Rm
);
10428 inst
.instruction
|= Rm
<< 16;
10437 Rd
= inst
.operands
[0].reg
;
10438 Rm
= inst
.operands
[1].reg
;
10440 reject_bad_reg (Rd
);
10441 reject_bad_reg (Rm
);
10443 inst
.instruction
|= Rd
<< 8;
10444 inst
.instruction
|= Rm
<< 16;
10445 inst
.instruction
|= Rm
;
10451 set_it_insn_type (OUTSIDE_IT_INSN
);
10452 inst
.instruction
|= inst
.operands
[0].imm
;
10458 set_it_insn_type (OUTSIDE_IT_INSN
);
10460 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10461 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10463 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10464 inst
.instruction
= 0xf3af8000;
10465 inst
.instruction
|= imod
<< 9;
10466 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10467 if (inst
.operands
[1].present
)
10468 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10472 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10473 && (inst
.operands
[0].imm
& 4),
10474 _("selected processor does not support 'A' form "
10475 "of this instruction"));
10476 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10477 _("Thumb does not support the 2-argument "
10478 "form of this instruction"));
10479 inst
.instruction
|= inst
.operands
[0].imm
;
10483 /* THUMB CPY instruction (argument parse). */
10488 if (inst
.size_req
== 4)
10490 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10491 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10492 inst
.instruction
|= inst
.operands
[1].reg
;
10496 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10497 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10498 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10505 set_it_insn_type (OUTSIDE_IT_INSN
);
10506 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10507 inst
.instruction
|= inst
.operands
[0].reg
;
10508 inst
.reloc
.pc_rel
= 1;
10509 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10515 inst
.instruction
|= inst
.operands
[0].imm
;
10521 unsigned Rd
, Rn
, Rm
;
10523 Rd
= inst
.operands
[0].reg
;
10524 Rn
= (inst
.operands
[1].present
10525 ? inst
.operands
[1].reg
: Rd
);
10526 Rm
= inst
.operands
[2].reg
;
10528 reject_bad_reg (Rd
);
10529 reject_bad_reg (Rn
);
10530 reject_bad_reg (Rm
);
10532 inst
.instruction
|= Rd
<< 8;
10533 inst
.instruction
|= Rn
<< 16;
10534 inst
.instruction
|= Rm
;
10540 if (unified_syntax
&& inst
.size_req
== 4)
10541 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10543 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10549 unsigned int cond
= inst
.operands
[0].imm
;
10551 set_it_insn_type (IT_INSN
);
10552 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10554 now_it
.warn_deprecated
= FALSE
;
10556 /* If the condition is a negative condition, invert the mask. */
10557 if ((cond
& 0x1) == 0x0)
10559 unsigned int mask
= inst
.instruction
& 0x000f;
10561 if ((mask
& 0x7) == 0)
10563 /* No conversion needed. */
10564 now_it
.block_length
= 1;
10566 else if ((mask
& 0x3) == 0)
10569 now_it
.block_length
= 2;
10571 else if ((mask
& 0x1) == 0)
10574 now_it
.block_length
= 3;
10579 now_it
.block_length
= 4;
10582 inst
.instruction
&= 0xfff0;
10583 inst
.instruction
|= mask
;
10586 inst
.instruction
|= cond
<< 4;
10589 /* Helper function used for both push/pop and ldm/stm. */
10591 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10595 load
= (inst
.instruction
& (1 << 20)) != 0;
10597 if (mask
& (1 << 13))
10598 inst
.error
= _("SP not allowed in register list");
10600 if ((mask
& (1 << base
)) != 0
10602 inst
.error
= _("having the base register in the register list when "
10603 "using write back is UNPREDICTABLE");
10607 if (mask
& (1 << 15))
10609 if (mask
& (1 << 14))
10610 inst
.error
= _("LR and PC should not both be in register list");
10612 set_it_insn_type_last ();
10617 if (mask
& (1 << 15))
10618 inst
.error
= _("PC not allowed in register list");
10621 if ((mask
& (mask
- 1)) == 0)
10623 /* Single register transfers implemented as str/ldr. */
10626 if (inst
.instruction
& (1 << 23))
10627 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10629 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10633 if (inst
.instruction
& (1 << 23))
10634 inst
.instruction
= 0x00800000; /* ia -> [base] */
10636 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10639 inst
.instruction
|= 0xf8400000;
10641 inst
.instruction
|= 0x00100000;
10643 mask
= ffs (mask
) - 1;
10646 else if (writeback
)
10647 inst
.instruction
|= WRITE_BACK
;
10649 inst
.instruction
|= mask
;
10650 inst
.instruction
|= base
<< 16;
10656 /* This really doesn't seem worth it. */
10657 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10658 _("expression too complex"));
10659 constraint (inst
.operands
[1].writeback
,
10660 _("Thumb load/store multiple does not support {reglist}^"));
10662 if (unified_syntax
)
10664 bfd_boolean narrow
;
10668 /* See if we can use a 16-bit instruction. */
10669 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10670 && inst
.size_req
!= 4
10671 && !(inst
.operands
[1].imm
& ~0xff))
10673 mask
= 1 << inst
.operands
[0].reg
;
10675 if (inst
.operands
[0].reg
<= 7)
10677 if (inst
.instruction
== T_MNEM_stmia
10678 ? inst
.operands
[0].writeback
10679 : (inst
.operands
[0].writeback
10680 == !(inst
.operands
[1].imm
& mask
)))
10682 if (inst
.instruction
== T_MNEM_stmia
10683 && (inst
.operands
[1].imm
& mask
)
10684 && (inst
.operands
[1].imm
& (mask
- 1)))
10685 as_warn (_("value stored for r%d is UNKNOWN"),
10686 inst
.operands
[0].reg
);
10688 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10689 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10690 inst
.instruction
|= inst
.operands
[1].imm
;
10693 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10695 /* This means 1 register in reg list one of 3 situations:
10696 1. Instruction is stmia, but without writeback.
10697 2. lmdia without writeback, but with Rn not in
10699 3. ldmia with writeback, but with Rn in reglist.
10700 Case 3 is UNPREDICTABLE behaviour, so we handle
10701 case 1 and 2 which can be converted into a 16-bit
10702 str or ldr. The SP cases are handled below. */
10703 unsigned long opcode
;
10704 /* First, record an error for Case 3. */
10705 if (inst
.operands
[1].imm
& mask
10706 && inst
.operands
[0].writeback
)
10708 _("having the base register in the register list when "
10709 "using write back is UNPREDICTABLE");
10711 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10713 inst
.instruction
= THUMB_OP16 (opcode
);
10714 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10715 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10719 else if (inst
.operands
[0] .reg
== REG_SP
)
10721 if (inst
.operands
[0].writeback
)
10724 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10725 ? T_MNEM_push
: T_MNEM_pop
);
10726 inst
.instruction
|= inst
.operands
[1].imm
;
10729 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10732 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10733 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10734 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10742 if (inst
.instruction
< 0xffff)
10743 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10745 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10746 inst
.operands
[0].writeback
);
10751 constraint (inst
.operands
[0].reg
> 7
10752 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10753 constraint (inst
.instruction
!= T_MNEM_ldmia
10754 && inst
.instruction
!= T_MNEM_stmia
,
10755 _("Thumb-2 instruction only valid in unified syntax"));
10756 if (inst
.instruction
== T_MNEM_stmia
)
10758 if (!inst
.operands
[0].writeback
)
10759 as_warn (_("this instruction will write back the base register"));
10760 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10761 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10762 as_warn (_("value stored for r%d is UNKNOWN"),
10763 inst
.operands
[0].reg
);
10767 if (!inst
.operands
[0].writeback
10768 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10769 as_warn (_("this instruction will write back the base register"));
10770 else if (inst
.operands
[0].writeback
10771 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10772 as_warn (_("this instruction will not write back the base register"));
10775 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10776 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10777 inst
.instruction
|= inst
.operands
[1].imm
;
10784 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10785 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10786 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10787 || inst
.operands
[1].negative
,
10790 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10792 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10793 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10794 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10800 if (!inst
.operands
[1].present
)
10802 constraint (inst
.operands
[0].reg
== REG_LR
,
10803 _("r14 not allowed as first register "
10804 "when second register is omitted"));
10805 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10807 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10810 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10811 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10812 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10818 unsigned long opcode
;
10821 if (inst
.operands
[0].isreg
10822 && !inst
.operands
[0].preind
10823 && inst
.operands
[0].reg
== REG_PC
)
10824 set_it_insn_type_last ();
10826 opcode
= inst
.instruction
;
10827 if (unified_syntax
)
10829 if (!inst
.operands
[1].isreg
)
10831 if (opcode
<= 0xffff)
10832 inst
.instruction
= THUMB_OP32 (opcode
);
10833 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10836 if (inst
.operands
[1].isreg
10837 && !inst
.operands
[1].writeback
10838 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10839 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10840 && opcode
<= 0xffff
10841 && inst
.size_req
!= 4)
10843 /* Insn may have a 16-bit form. */
10844 Rn
= inst
.operands
[1].reg
;
10845 if (inst
.operands
[1].immisreg
)
10847 inst
.instruction
= THUMB_OP16 (opcode
);
10849 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10851 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10852 reject_bad_reg (inst
.operands
[1].imm
);
10854 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10855 && opcode
!= T_MNEM_ldrsb
)
10856 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10857 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10864 if (inst
.reloc
.pc_rel
)
10865 opcode
= T_MNEM_ldr_pc2
;
10867 opcode
= T_MNEM_ldr_pc
;
10871 if (opcode
== T_MNEM_ldr
)
10872 opcode
= T_MNEM_ldr_sp
;
10874 opcode
= T_MNEM_str_sp
;
10876 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10880 inst
.instruction
= inst
.operands
[0].reg
;
10881 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10883 inst
.instruction
|= THUMB_OP16 (opcode
);
10884 if (inst
.size_req
== 2)
10885 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10887 inst
.relax
= opcode
;
10891 /* Definitely a 32-bit variant. */
10893 /* Warning for Erratum 752419. */
10894 if (opcode
== T_MNEM_ldr
10895 && inst
.operands
[0].reg
== REG_SP
10896 && inst
.operands
[1].writeback
== 1
10897 && !inst
.operands
[1].immisreg
)
10899 if (no_cpu_selected ()
10900 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10901 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10902 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10903 as_warn (_("This instruction may be unpredictable "
10904 "if executed on M-profile cores "
10905 "with interrupts enabled."));
10908 /* Do some validations regarding addressing modes. */
10909 if (inst
.operands
[1].immisreg
)
10910 reject_bad_reg (inst
.operands
[1].imm
);
10912 constraint (inst
.operands
[1].writeback
== 1
10913 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10916 inst
.instruction
= THUMB_OP32 (opcode
);
10917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10918 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10919 check_ldr_r15_aligned ();
10923 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10925 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10927 /* Only [Rn,Rm] is acceptable. */
10928 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10929 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10930 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10931 || inst
.operands
[1].negative
,
10932 _("Thumb does not support this addressing mode"));
10933 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10937 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10938 if (!inst
.operands
[1].isreg
)
10939 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10942 constraint (!inst
.operands
[1].preind
10943 || inst
.operands
[1].shifted
10944 || inst
.operands
[1].writeback
,
10945 _("Thumb does not support this addressing mode"));
10946 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10948 constraint (inst
.instruction
& 0x0600,
10949 _("byte or halfword not valid for base register"));
10950 constraint (inst
.operands
[1].reg
== REG_PC
10951 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10952 _("r15 based store not allowed"));
10953 constraint (inst
.operands
[1].immisreg
,
10954 _("invalid base register for register offset"));
10956 if (inst
.operands
[1].reg
== REG_PC
)
10957 inst
.instruction
= T_OPCODE_LDR_PC
;
10958 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10959 inst
.instruction
= T_OPCODE_LDR_SP
;
10961 inst
.instruction
= T_OPCODE_STR_SP
;
10963 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10964 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10968 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10969 if (!inst
.operands
[1].immisreg
)
10971 /* Immediate offset. */
10972 inst
.instruction
|= inst
.operands
[0].reg
;
10973 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10974 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10978 /* Register offset. */
10979 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10980 constraint (inst
.operands
[1].negative
,
10981 _("Thumb does not support this addressing mode"));
10984 switch (inst
.instruction
)
10986 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10987 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10988 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10989 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10990 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10991 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10992 case 0x5600 /* ldrsb */:
10993 case 0x5e00 /* ldrsh */: break;
10997 inst
.instruction
|= inst
.operands
[0].reg
;
10998 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10999 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11005 if (!inst
.operands
[1].present
)
11007 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11008 constraint (inst
.operands
[0].reg
== REG_LR
,
11009 _("r14 not allowed here"));
11010 constraint (inst
.operands
[0].reg
== REG_R12
,
11011 _("r12 not allowed here"));
11014 if (inst
.operands
[2].writeback
11015 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11016 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11017 as_warn (_("base register written back, and overlaps "
11018 "one of transfer registers"));
11020 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11021 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11022 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11028 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11029 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11035 unsigned Rd
, Rn
, Rm
, Ra
;
11037 Rd
= inst
.operands
[0].reg
;
11038 Rn
= inst
.operands
[1].reg
;
11039 Rm
= inst
.operands
[2].reg
;
11040 Ra
= inst
.operands
[3].reg
;
11042 reject_bad_reg (Rd
);
11043 reject_bad_reg (Rn
);
11044 reject_bad_reg (Rm
);
11045 reject_bad_reg (Ra
);
11047 inst
.instruction
|= Rd
<< 8;
11048 inst
.instruction
|= Rn
<< 16;
11049 inst
.instruction
|= Rm
;
11050 inst
.instruction
|= Ra
<< 12;
11056 unsigned RdLo
, RdHi
, Rn
, Rm
;
11058 RdLo
= inst
.operands
[0].reg
;
11059 RdHi
= inst
.operands
[1].reg
;
11060 Rn
= inst
.operands
[2].reg
;
11061 Rm
= inst
.operands
[3].reg
;
11063 reject_bad_reg (RdLo
);
11064 reject_bad_reg (RdHi
);
11065 reject_bad_reg (Rn
);
11066 reject_bad_reg (Rm
);
11068 inst
.instruction
|= RdLo
<< 12;
11069 inst
.instruction
|= RdHi
<< 8;
11070 inst
.instruction
|= Rn
<< 16;
11071 inst
.instruction
|= Rm
;
11075 do_t_mov_cmp (void)
11079 Rn
= inst
.operands
[0].reg
;
11080 Rm
= inst
.operands
[1].reg
;
11083 set_it_insn_type_last ();
11085 if (unified_syntax
)
11087 int r0off
= (inst
.instruction
== T_MNEM_mov
11088 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11089 unsigned long opcode
;
11090 bfd_boolean narrow
;
11091 bfd_boolean low_regs
;
11093 low_regs
= (Rn
<= 7 && Rm
<= 7);
11094 opcode
= inst
.instruction
;
11095 if (in_it_block ())
11096 narrow
= opcode
!= T_MNEM_movs
;
11098 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11099 if (inst
.size_req
== 4
11100 || inst
.operands
[1].shifted
)
11103 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11104 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11105 && !inst
.operands
[1].shifted
11109 inst
.instruction
= T2_SUBS_PC_LR
;
11113 if (opcode
== T_MNEM_cmp
)
11115 constraint (Rn
== REG_PC
, BAD_PC
);
11118 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11120 warn_deprecated_sp (Rm
);
11121 /* R15 was documented as a valid choice for Rm in ARMv6,
11122 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11123 tools reject R15, so we do too. */
11124 constraint (Rm
== REG_PC
, BAD_PC
);
11127 reject_bad_reg (Rm
);
11129 else if (opcode
== T_MNEM_mov
11130 || opcode
== T_MNEM_movs
)
11132 if (inst
.operands
[1].isreg
)
11134 if (opcode
== T_MNEM_movs
)
11136 reject_bad_reg (Rn
);
11137 reject_bad_reg (Rm
);
11141 /* This is mov.n. */
11142 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
11143 && (Rm
== REG_SP
|| Rm
== REG_PC
))
11145 as_warn (_("Use of r%u as a source register is "
11146 "deprecated when r%u is the destination "
11147 "register."), Rm
, Rn
);
11152 /* This is mov.w. */
11153 constraint (Rn
== REG_PC
, BAD_PC
);
11154 constraint (Rm
== REG_PC
, BAD_PC
);
11155 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
11159 reject_bad_reg (Rn
);
11162 if (!inst
.operands
[1].isreg
)
11164 /* Immediate operand. */
11165 if (!in_it_block () && opcode
== T_MNEM_mov
)
11167 if (low_regs
&& narrow
)
11169 inst
.instruction
= THUMB_OP16 (opcode
);
11170 inst
.instruction
|= Rn
<< 8;
11171 if (inst
.size_req
== 2)
11172 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11174 inst
.relax
= opcode
;
11178 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11179 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11180 inst
.instruction
|= Rn
<< r0off
;
11181 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11184 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
11185 && (inst
.instruction
== T_MNEM_mov
11186 || inst
.instruction
== T_MNEM_movs
))
11188 /* Register shifts are encoded as separate shift instructions. */
11189 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
11191 if (in_it_block ())
11196 if (inst
.size_req
== 4)
11199 if (!low_regs
|| inst
.operands
[1].imm
> 7)
11205 switch (inst
.operands
[1].shift_kind
)
11208 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
11211 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
11214 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
11217 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
11223 inst
.instruction
= opcode
;
11226 inst
.instruction
|= Rn
;
11227 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
11232 inst
.instruction
|= CONDS_BIT
;
11234 inst
.instruction
|= Rn
<< 8;
11235 inst
.instruction
|= Rm
<< 16;
11236 inst
.instruction
|= inst
.operands
[1].imm
;
11241 /* Some mov with immediate shift have narrow variants.
11242 Register shifts are handled above. */
11243 if (low_regs
&& inst
.operands
[1].shifted
11244 && (inst
.instruction
== T_MNEM_mov
11245 || inst
.instruction
== T_MNEM_movs
))
11247 if (in_it_block ())
11248 narrow
= (inst
.instruction
== T_MNEM_mov
);
11250 narrow
= (inst
.instruction
== T_MNEM_movs
);
11255 switch (inst
.operands
[1].shift_kind
)
11257 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11258 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11259 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11260 default: narrow
= FALSE
; break;
11266 inst
.instruction
|= Rn
;
11267 inst
.instruction
|= Rm
<< 3;
11268 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11272 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11273 inst
.instruction
|= Rn
<< r0off
;
11274 encode_thumb32_shifted_operand (1);
11278 switch (inst
.instruction
)
11281 /* In v4t or v5t a move of two lowregs produces unpredictable
11282 results. Don't allow this. */
11285 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
11286 "MOV Rd, Rs with two low registers is not "
11287 "permitted on this architecture");
11288 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
11292 inst
.instruction
= T_OPCODE_MOV_HR
;
11293 inst
.instruction
|= (Rn
& 0x8) << 4;
11294 inst
.instruction
|= (Rn
& 0x7);
11295 inst
.instruction
|= Rm
<< 3;
11299 /* We know we have low registers at this point.
11300 Generate LSLS Rd, Rs, #0. */
11301 inst
.instruction
= T_OPCODE_LSL_I
;
11302 inst
.instruction
|= Rn
;
11303 inst
.instruction
|= Rm
<< 3;
11309 inst
.instruction
= T_OPCODE_CMP_LR
;
11310 inst
.instruction
|= Rn
;
11311 inst
.instruction
|= Rm
<< 3;
11315 inst
.instruction
= T_OPCODE_CMP_HR
;
11316 inst
.instruction
|= (Rn
& 0x8) << 4;
11317 inst
.instruction
|= (Rn
& 0x7);
11318 inst
.instruction
|= Rm
<< 3;
11325 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11327 /* PR 10443: Do not silently ignore shifted operands. */
11328 constraint (inst
.operands
[1].shifted
,
11329 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
11331 if (inst
.operands
[1].isreg
)
11333 if (Rn
< 8 && Rm
< 8)
11335 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
11336 since a MOV instruction produces unpredictable results. */
11337 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11338 inst
.instruction
= T_OPCODE_ADD_I3
;
11340 inst
.instruction
= T_OPCODE_CMP_LR
;
11342 inst
.instruction
|= Rn
;
11343 inst
.instruction
|= Rm
<< 3;
11347 if (inst
.instruction
== T_OPCODE_MOV_I8
)
11348 inst
.instruction
= T_OPCODE_MOV_HR
;
11350 inst
.instruction
= T_OPCODE_CMP_HR
;
11356 constraint (Rn
> 7,
11357 _("only lo regs allowed with immediate"));
11358 inst
.instruction
|= Rn
<< 8;
11359 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
11370 top
= (inst
.instruction
& 0x00800000) != 0;
11371 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
11373 constraint (top
, _(":lower16: not allowed this instruction"));
11374 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
11376 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
11378 constraint (!top
, _(":upper16: not allowed this instruction"));
11379 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
11382 Rd
= inst
.operands
[0].reg
;
11383 reject_bad_reg (Rd
);
11385 inst
.instruction
|= Rd
<< 8;
11386 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
11388 imm
= inst
.reloc
.exp
.X_add_number
;
11389 inst
.instruction
|= (imm
& 0xf000) << 4;
11390 inst
.instruction
|= (imm
& 0x0800) << 15;
11391 inst
.instruction
|= (imm
& 0x0700) << 4;
11392 inst
.instruction
|= (imm
& 0x00ff);
11397 do_t_mvn_tst (void)
11401 Rn
= inst
.operands
[0].reg
;
11402 Rm
= inst
.operands
[1].reg
;
11404 if (inst
.instruction
== T_MNEM_cmp
11405 || inst
.instruction
== T_MNEM_cmn
)
11406 constraint (Rn
== REG_PC
, BAD_PC
);
11408 reject_bad_reg (Rn
);
11409 reject_bad_reg (Rm
);
11411 if (unified_syntax
)
11413 int r0off
= (inst
.instruction
== T_MNEM_mvn
11414 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
11415 bfd_boolean narrow
;
11417 if (inst
.size_req
== 4
11418 || inst
.instruction
> 0xffff
11419 || inst
.operands
[1].shifted
11420 || Rn
> 7 || Rm
> 7)
11422 else if (inst
.instruction
== T_MNEM_cmn
11423 || inst
.instruction
== T_MNEM_tst
)
11425 else if (THUMB_SETS_FLAGS (inst
.instruction
))
11426 narrow
= !in_it_block ();
11428 narrow
= in_it_block ();
11430 if (!inst
.operands
[1].isreg
)
11432 /* For an immediate, we always generate a 32-bit opcode;
11433 section relaxation will shrink it later if possible. */
11434 if (inst
.instruction
< 0xffff)
11435 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11436 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11437 inst
.instruction
|= Rn
<< r0off
;
11438 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11442 /* See if we can do this with a 16-bit instruction. */
11445 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11446 inst
.instruction
|= Rn
;
11447 inst
.instruction
|= Rm
<< 3;
11451 constraint (inst
.operands
[1].shifted
11452 && inst
.operands
[1].immisreg
,
11453 _("shift must be constant"));
11454 if (inst
.instruction
< 0xffff)
11455 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11456 inst
.instruction
|= Rn
<< r0off
;
11457 encode_thumb32_shifted_operand (1);
11463 constraint (inst
.instruction
> 0xffff
11464 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11465 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11466 _("unshifted register required"));
11467 constraint (Rn
> 7 || Rm
> 7,
11470 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11471 inst
.instruction
|= Rn
;
11472 inst
.instruction
|= Rm
<< 3;
11481 if (do_vfp_nsyn_mrs () == SUCCESS
)
11484 Rd
= inst
.operands
[0].reg
;
11485 reject_bad_reg (Rd
);
11486 inst
.instruction
|= Rd
<< 8;
11488 if (inst
.operands
[1].isreg
)
11490 unsigned br
= inst
.operands
[1].reg
;
11491 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11492 as_bad (_("bad register for mrs"));
11494 inst
.instruction
|= br
& (0xf << 16);
11495 inst
.instruction
|= (br
& 0x300) >> 4;
11496 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11500 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11502 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11504 /* PR gas/12698: The constraint is only applied for m_profile.
11505 If the user has specified -march=all, we want to ignore it as
11506 we are building for any CPU type, including non-m variants. */
11507 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11508 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
11509 "not support requested special purpose register"));
11512 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11514 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11515 _("'APSR', 'CPSR' or 'SPSR' expected"));
11517 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11518 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11519 inst
.instruction
|= 0xf0000;
11529 if (do_vfp_nsyn_msr () == SUCCESS
)
11532 constraint (!inst
.operands
[1].isreg
,
11533 _("Thumb encoding does not support an immediate here"));
11535 if (inst
.operands
[0].isreg
)
11536 flags
= (int)(inst
.operands
[0].reg
);
11538 flags
= inst
.operands
[0].imm
;
11540 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11542 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11544 /* PR gas/12698: The constraint is only applied for m_profile.
11545 If the user has specified -march=all, we want to ignore it as
11546 we are building for any CPU type, including non-m variants. */
11547 bfd_boolean m_profile
= selected_cpu
.core
!= arm_arch_any
.core
;
11548 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11549 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11550 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11551 && bits
!= PSR_f
)) && m_profile
,
11552 _("selected processor does not support requested special "
11553 "purpose register"));
11556 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11557 "requested special purpose register"));
11559 Rn
= inst
.operands
[1].reg
;
11560 reject_bad_reg (Rn
);
11562 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11563 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11564 inst
.instruction
|= (flags
& 0x300) >> 4;
11565 inst
.instruction
|= (flags
& 0xff);
11566 inst
.instruction
|= Rn
<< 16;
11572 bfd_boolean narrow
;
11573 unsigned Rd
, Rn
, Rm
;
11575 if (!inst
.operands
[2].present
)
11576 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11578 Rd
= inst
.operands
[0].reg
;
11579 Rn
= inst
.operands
[1].reg
;
11580 Rm
= inst
.operands
[2].reg
;
11582 if (unified_syntax
)
11584 if (inst
.size_req
== 4
11590 else if (inst
.instruction
== T_MNEM_muls
)
11591 narrow
= !in_it_block ();
11593 narrow
= in_it_block ();
11597 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11598 constraint (Rn
> 7 || Rm
> 7,
11605 /* 16-bit MULS/Conditional MUL. */
11606 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11607 inst
.instruction
|= Rd
;
11610 inst
.instruction
|= Rm
<< 3;
11612 inst
.instruction
|= Rn
<< 3;
11614 constraint (1, _("dest must overlap one source register"));
11618 constraint (inst
.instruction
!= T_MNEM_mul
,
11619 _("Thumb-2 MUL must not set flags"));
11621 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11622 inst
.instruction
|= Rd
<< 8;
11623 inst
.instruction
|= Rn
<< 16;
11624 inst
.instruction
|= Rm
<< 0;
11626 reject_bad_reg (Rd
);
11627 reject_bad_reg (Rn
);
11628 reject_bad_reg (Rm
);
11635 unsigned RdLo
, RdHi
, Rn
, Rm
;
11637 RdLo
= inst
.operands
[0].reg
;
11638 RdHi
= inst
.operands
[1].reg
;
11639 Rn
= inst
.operands
[2].reg
;
11640 Rm
= inst
.operands
[3].reg
;
11642 reject_bad_reg (RdLo
);
11643 reject_bad_reg (RdHi
);
11644 reject_bad_reg (Rn
);
11645 reject_bad_reg (Rm
);
11647 inst
.instruction
|= RdLo
<< 12;
11648 inst
.instruction
|= RdHi
<< 8;
11649 inst
.instruction
|= Rn
<< 16;
11650 inst
.instruction
|= Rm
;
11653 as_tsktsk (_("rdhi and rdlo must be different"));
11659 set_it_insn_type (NEUTRAL_IT_INSN
);
11661 if (unified_syntax
)
11663 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11665 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11666 inst
.instruction
|= inst
.operands
[0].imm
;
11670 /* PR9722: Check for Thumb2 availability before
11671 generating a thumb2 nop instruction. */
11672 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11674 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11675 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11678 inst
.instruction
= 0x46c0;
11683 constraint (inst
.operands
[0].present
,
11684 _("Thumb does not support NOP with hints"));
11685 inst
.instruction
= 0x46c0;
11692 if (unified_syntax
)
11694 bfd_boolean narrow
;
11696 if (THUMB_SETS_FLAGS (inst
.instruction
))
11697 narrow
= !in_it_block ();
11699 narrow
= in_it_block ();
11700 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11702 if (inst
.size_req
== 4)
11707 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11708 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11709 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11713 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11714 inst
.instruction
|= inst
.operands
[0].reg
;
11715 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11720 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11722 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11724 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11725 inst
.instruction
|= inst
.operands
[0].reg
;
11726 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11735 Rd
= inst
.operands
[0].reg
;
11736 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11738 reject_bad_reg (Rd
);
11739 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11740 reject_bad_reg (Rn
);
11742 inst
.instruction
|= Rd
<< 8;
11743 inst
.instruction
|= Rn
<< 16;
11745 if (!inst
.operands
[2].isreg
)
11747 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11748 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11754 Rm
= inst
.operands
[2].reg
;
11755 reject_bad_reg (Rm
);
11757 constraint (inst
.operands
[2].shifted
11758 && inst
.operands
[2].immisreg
,
11759 _("shift must be constant"));
11760 encode_thumb32_shifted_operand (2);
11767 unsigned Rd
, Rn
, Rm
;
11769 Rd
= inst
.operands
[0].reg
;
11770 Rn
= inst
.operands
[1].reg
;
11771 Rm
= inst
.operands
[2].reg
;
11773 reject_bad_reg (Rd
);
11774 reject_bad_reg (Rn
);
11775 reject_bad_reg (Rm
);
11777 inst
.instruction
|= Rd
<< 8;
11778 inst
.instruction
|= Rn
<< 16;
11779 inst
.instruction
|= Rm
;
11780 if (inst
.operands
[3].present
)
11782 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11783 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11784 _("expression too complex"));
11785 inst
.instruction
|= (val
& 0x1c) << 10;
11786 inst
.instruction
|= (val
& 0x03) << 6;
11793 if (!inst
.operands
[3].present
)
11797 inst
.instruction
&= ~0x00000020;
11799 /* PR 10168. Swap the Rm and Rn registers. */
11800 Rtmp
= inst
.operands
[1].reg
;
11801 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11802 inst
.operands
[2].reg
= Rtmp
;
11810 if (inst
.operands
[0].immisreg
)
11811 reject_bad_reg (inst
.operands
[0].imm
);
11813 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11817 do_t_push_pop (void)
11821 constraint (inst
.operands
[0].writeback
,
11822 _("push/pop do not support {reglist}^"));
11823 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11824 _("expression too complex"));
11826 mask
= inst
.operands
[0].imm
;
11827 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
11828 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11829 else if (inst
.size_req
!= 4
11830 && (mask
& ~0xff) == (1 << (inst
.instruction
== T_MNEM_push
11831 ? REG_LR
: REG_PC
)))
11833 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11834 inst
.instruction
|= THUMB_PP_PC_LR
;
11835 inst
.instruction
|= mask
& 0xff;
11837 else if (unified_syntax
)
11839 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11840 encode_thumb2_ldmstm (13, mask
, TRUE
);
11844 inst
.error
= _("invalid register list to push/pop instruction");
11854 Rd
= inst
.operands
[0].reg
;
11855 Rm
= inst
.operands
[1].reg
;
11857 reject_bad_reg (Rd
);
11858 reject_bad_reg (Rm
);
11860 inst
.instruction
|= Rd
<< 8;
11861 inst
.instruction
|= Rm
<< 16;
11862 inst
.instruction
|= Rm
;
11870 Rd
= inst
.operands
[0].reg
;
11871 Rm
= inst
.operands
[1].reg
;
11873 reject_bad_reg (Rd
);
11874 reject_bad_reg (Rm
);
11876 if (Rd
<= 7 && Rm
<= 7
11877 && inst
.size_req
!= 4)
11879 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11880 inst
.instruction
|= Rd
;
11881 inst
.instruction
|= Rm
<< 3;
11883 else if (unified_syntax
)
11885 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11886 inst
.instruction
|= Rd
<< 8;
11887 inst
.instruction
|= Rm
<< 16;
11888 inst
.instruction
|= Rm
;
11891 inst
.error
= BAD_HIREG
;
11899 Rd
= inst
.operands
[0].reg
;
11900 Rm
= inst
.operands
[1].reg
;
11902 reject_bad_reg (Rd
);
11903 reject_bad_reg (Rm
);
11905 inst
.instruction
|= Rd
<< 8;
11906 inst
.instruction
|= Rm
;
11914 Rd
= inst
.operands
[0].reg
;
11915 Rs
= (inst
.operands
[1].present
11916 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11917 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11919 reject_bad_reg (Rd
);
11920 reject_bad_reg (Rs
);
11921 if (inst
.operands
[2].isreg
)
11922 reject_bad_reg (inst
.operands
[2].reg
);
11924 inst
.instruction
|= Rd
<< 8;
11925 inst
.instruction
|= Rs
<< 16;
11926 if (!inst
.operands
[2].isreg
)
11928 bfd_boolean narrow
;
11930 if ((inst
.instruction
& 0x00100000) != 0)
11931 narrow
= !in_it_block ();
11933 narrow
= in_it_block ();
11935 if (Rd
> 7 || Rs
> 7)
11938 if (inst
.size_req
== 4 || !unified_syntax
)
11941 if (inst
.reloc
.exp
.X_op
!= O_constant
11942 || inst
.reloc
.exp
.X_add_number
!= 0)
11945 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11946 relaxation, but it doesn't seem worth the hassle. */
11949 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11950 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11951 inst
.instruction
|= Rs
<< 3;
11952 inst
.instruction
|= Rd
;
11956 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11957 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11961 encode_thumb32_shifted_operand (2);
11967 if (warn_on_deprecated
11968 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11969 as_warn (_("setend use is deprecated for ARMv8"));
11971 set_it_insn_type (OUTSIDE_IT_INSN
);
11972 if (inst
.operands
[0].imm
)
11973 inst
.instruction
|= 0x8;
11979 if (!inst
.operands
[1].present
)
11980 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11982 if (unified_syntax
)
11984 bfd_boolean narrow
;
11987 switch (inst
.instruction
)
11990 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11992 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11994 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11996 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12000 if (THUMB_SETS_FLAGS (inst
.instruction
))
12001 narrow
= !in_it_block ();
12003 narrow
= in_it_block ();
12004 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12006 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12008 if (inst
.operands
[2].isreg
12009 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12010 || inst
.operands
[2].reg
> 7))
12012 if (inst
.size_req
== 4)
12015 reject_bad_reg (inst
.operands
[0].reg
);
12016 reject_bad_reg (inst
.operands
[1].reg
);
12020 if (inst
.operands
[2].isreg
)
12022 reject_bad_reg (inst
.operands
[2].reg
);
12023 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12024 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12025 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12026 inst
.instruction
|= inst
.operands
[2].reg
;
12028 /* PR 12854: Error on extraneous shifts. */
12029 constraint (inst
.operands
[2].shifted
,
12030 _("extraneous shift as part of operand to shift insn"));
12034 inst
.operands
[1].shifted
= 1;
12035 inst
.operands
[1].shift_kind
= shift_kind
;
12036 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12037 ? T_MNEM_movs
: T_MNEM_mov
);
12038 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12039 encode_thumb32_shifted_operand (1);
12040 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12041 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12046 if (inst
.operands
[2].isreg
)
12048 switch (shift_kind
)
12050 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12051 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12052 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12053 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12057 inst
.instruction
|= inst
.operands
[0].reg
;
12058 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12060 /* PR 12854: Error on extraneous shifts. */
12061 constraint (inst
.operands
[2].shifted
,
12062 _("extraneous shift as part of operand to shift insn"));
12066 switch (shift_kind
)
12068 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12069 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12070 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12073 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12074 inst
.instruction
|= inst
.operands
[0].reg
;
12075 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12081 constraint (inst
.operands
[0].reg
> 7
12082 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12083 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12085 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12087 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12088 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12089 _("source1 and dest must be same register"));
12091 switch (inst
.instruction
)
12093 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12094 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12095 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12096 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12100 inst
.instruction
|= inst
.operands
[0].reg
;
12101 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12103 /* PR 12854: Error on extraneous shifts. */
12104 constraint (inst
.operands
[2].shifted
,
12105 _("extraneous shift as part of operand to shift insn"));
12109 switch (inst
.instruction
)
12111 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12112 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12113 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12114 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12117 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12118 inst
.instruction
|= inst
.operands
[0].reg
;
12119 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12127 unsigned Rd
, Rn
, Rm
;
12129 Rd
= inst
.operands
[0].reg
;
12130 Rn
= inst
.operands
[1].reg
;
12131 Rm
= inst
.operands
[2].reg
;
12133 reject_bad_reg (Rd
);
12134 reject_bad_reg (Rn
);
12135 reject_bad_reg (Rm
);
12137 inst
.instruction
|= Rd
<< 8;
12138 inst
.instruction
|= Rn
<< 16;
12139 inst
.instruction
|= Rm
;
12145 unsigned Rd
, Rn
, Rm
;
12147 Rd
= inst
.operands
[0].reg
;
12148 Rm
= inst
.operands
[1].reg
;
12149 Rn
= inst
.operands
[2].reg
;
12151 reject_bad_reg (Rd
);
12152 reject_bad_reg (Rn
);
12153 reject_bad_reg (Rm
);
12155 inst
.instruction
|= Rd
<< 8;
12156 inst
.instruction
|= Rn
<< 16;
12157 inst
.instruction
|= Rm
;
12163 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12164 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
12165 _("SMC is not permitted on this architecture"));
12166 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12167 _("expression too complex"));
12168 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12169 inst
.instruction
|= (value
& 0xf000) >> 12;
12170 inst
.instruction
|= (value
& 0x0ff0);
12171 inst
.instruction
|= (value
& 0x000f) << 16;
12172 /* PR gas/15623: SMC instructions must be last in an IT block. */
12173 set_it_insn_type_last ();
12179 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
12181 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12182 inst
.instruction
|= (value
& 0x0fff);
12183 inst
.instruction
|= (value
& 0xf000) << 4;
12187 do_t_ssat_usat (int bias
)
12191 Rd
= inst
.operands
[0].reg
;
12192 Rn
= inst
.operands
[2].reg
;
12194 reject_bad_reg (Rd
);
12195 reject_bad_reg (Rn
);
12197 inst
.instruction
|= Rd
<< 8;
12198 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
12199 inst
.instruction
|= Rn
<< 16;
12201 if (inst
.operands
[3].present
)
12203 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
12205 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12207 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12208 _("expression too complex"));
12210 if (shift_amount
!= 0)
12212 constraint (shift_amount
> 31,
12213 _("shift expression is too large"));
12215 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
12216 inst
.instruction
|= 0x00200000; /* sh bit. */
12218 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
12219 inst
.instruction
|= (shift_amount
& 0x03) << 6;
12227 do_t_ssat_usat (1);
12235 Rd
= inst
.operands
[0].reg
;
12236 Rn
= inst
.operands
[2].reg
;
12238 reject_bad_reg (Rd
);
12239 reject_bad_reg (Rn
);
12241 inst
.instruction
|= Rd
<< 8;
12242 inst
.instruction
|= inst
.operands
[1].imm
- 1;
12243 inst
.instruction
|= Rn
<< 16;
12249 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
12250 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
12251 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
12252 || inst
.operands
[2].negative
,
12255 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
12257 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12258 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12259 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12260 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12266 if (!inst
.operands
[2].present
)
12267 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
12269 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
12270 || inst
.operands
[0].reg
== inst
.operands
[2].reg
12271 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
12274 inst
.instruction
|= inst
.operands
[0].reg
;
12275 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
12276 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
12277 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
12283 unsigned Rd
, Rn
, Rm
;
12285 Rd
= inst
.operands
[0].reg
;
12286 Rn
= inst
.operands
[1].reg
;
12287 Rm
= inst
.operands
[2].reg
;
12289 reject_bad_reg (Rd
);
12290 reject_bad_reg (Rn
);
12291 reject_bad_reg (Rm
);
12293 inst
.instruction
|= Rd
<< 8;
12294 inst
.instruction
|= Rn
<< 16;
12295 inst
.instruction
|= Rm
;
12296 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
12304 Rd
= inst
.operands
[0].reg
;
12305 Rm
= inst
.operands
[1].reg
;
12307 reject_bad_reg (Rd
);
12308 reject_bad_reg (Rm
);
12310 if (inst
.instruction
<= 0xffff
12311 && inst
.size_req
!= 4
12312 && Rd
<= 7 && Rm
<= 7
12313 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
12315 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12316 inst
.instruction
|= Rd
;
12317 inst
.instruction
|= Rm
<< 3;
12319 else if (unified_syntax
)
12321 if (inst
.instruction
<= 0xffff)
12322 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12323 inst
.instruction
|= Rd
<< 8;
12324 inst
.instruction
|= Rm
;
12325 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
12329 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
12330 _("Thumb encoding does not support rotation"));
12331 constraint (1, BAD_HIREG
);
12338 /* We have to do the following check manually as ARM_EXT_OS only applies
12340 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
12342 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
12343 /* This only applies to the v6m howver, not later architectures. */
12344 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
12345 as_bad (_("SVC is not permitted on this architecture"));
12346 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
12349 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
12358 half
= (inst
.instruction
& 0x10) != 0;
12359 set_it_insn_type_last ();
12360 constraint (inst
.operands
[0].immisreg
,
12361 _("instruction requires register index"));
12363 Rn
= inst
.operands
[0].reg
;
12364 Rm
= inst
.operands
[0].imm
;
12366 constraint (Rn
== REG_SP
, BAD_SP
);
12367 reject_bad_reg (Rm
);
12369 constraint (!half
&& inst
.operands
[0].shifted
,
12370 _("instruction does not allow shifted index"));
12371 inst
.instruction
|= (Rn
<< 16) | Rm
;
12377 if (!inst
.operands
[0].present
)
12378 inst
.operands
[0].imm
= 0;
12380 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
12382 constraint (inst
.size_req
== 2,
12383 _("immediate value out of range"));
12384 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12385 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
12386 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
12390 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12391 inst
.instruction
|= inst
.operands
[0].imm
;
12394 set_it_insn_type (NEUTRAL_IT_INSN
);
12401 do_t_ssat_usat (0);
12409 Rd
= inst
.operands
[0].reg
;
12410 Rn
= inst
.operands
[2].reg
;
12412 reject_bad_reg (Rd
);
12413 reject_bad_reg (Rn
);
12415 inst
.instruction
|= Rd
<< 8;
12416 inst
.instruction
|= inst
.operands
[1].imm
;
12417 inst
.instruction
|= Rn
<< 16;
12420 /* Neon instruction encoder helpers. */
12422 /* Encodings for the different types for various Neon opcodes. */
12424 /* An "invalid" code for the following tables. */
12427 struct neon_tab_entry
12430 unsigned float_or_poly
;
12431 unsigned scalar_or_imm
;
12434 /* Map overloaded Neon opcodes to their respective encodings. */
12435 #define NEON_ENC_TAB \
12436 X(vabd, 0x0000700, 0x1200d00, N_INV), \
12437 X(vmax, 0x0000600, 0x0000f00, N_INV), \
12438 X(vmin, 0x0000610, 0x0200f00, N_INV), \
12439 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
12440 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
12441 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
12442 X(vadd, 0x0000800, 0x0000d00, N_INV), \
12443 X(vsub, 0x1000800, 0x0200d00, N_INV), \
12444 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
12445 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
12446 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
12447 /* Register variants of the following two instructions are encoded as
12448 vcge / vcgt with the operands reversed. */ \
12449 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
12450 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
12451 X(vfma, N_INV, 0x0000c10, N_INV), \
12452 X(vfms, N_INV, 0x0200c10, N_INV), \
12453 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
12454 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
12455 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
12456 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
12457 X(vmlal, 0x0800800, N_INV, 0x0800240), \
12458 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
12459 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
12460 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
12461 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
12462 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
12463 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
12464 X(vshl, 0x0000400, N_INV, 0x0800510), \
12465 X(vqshl, 0x0000410, N_INV, 0x0800710), \
12466 X(vand, 0x0000110, N_INV, 0x0800030), \
12467 X(vbic, 0x0100110, N_INV, 0x0800030), \
12468 X(veor, 0x1000110, N_INV, N_INV), \
12469 X(vorn, 0x0300110, N_INV, 0x0800010), \
12470 X(vorr, 0x0200110, N_INV, 0x0800010), \
12471 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
12472 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
12473 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
12474 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
12475 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
12476 X(vst1, 0x0000000, 0x0800000, N_INV), \
12477 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12478 X(vst2, 0x0000100, 0x0800100, N_INV), \
12479 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12480 X(vst3, 0x0000200, 0x0800200, N_INV), \
12481 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12482 X(vst4, 0x0000300, 0x0800300, N_INV), \
12483 X(vmovn, 0x1b20200, N_INV, N_INV), \
12484 X(vtrn, 0x1b20080, N_INV, N_INV), \
12485 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12486 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12487 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12488 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12489 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12490 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12491 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12492 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12493 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12494 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12495 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
12496 X(vseleq, 0xe000a00, N_INV, N_INV), \
12497 X(vselvs, 0xe100a00, N_INV, N_INV), \
12498 X(vselge, 0xe200a00, N_INV, N_INV), \
12499 X(vselgt, 0xe300a00, N_INV, N_INV), \
12500 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
12501 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
12502 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
12503 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
12504 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
12505 X(aes, 0x3b00300, N_INV, N_INV), \
12506 X(sha3op, 0x2000c00, N_INV, N_INV), \
12507 X(sha1h, 0x3b902c0, N_INV, N_INV), \
12508 X(sha2op, 0x3ba0380, N_INV, N_INV)
12512 #define X(OPC,I,F,S) N_MNEM_##OPC
12517 static const struct neon_tab_entry neon_enc_tab
[] =
12519 #define X(OPC,I,F,S) { (I), (F), (S) }
12524 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12525 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12526 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12527 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12528 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12529 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12530 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12531 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12532 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12533 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12534 #define NEON_ENC_SINGLE_(X) \
12535 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12536 #define NEON_ENC_DOUBLE_(X) \
12537 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12538 #define NEON_ENC_FPV8_(X) \
12539 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
12541 #define NEON_ENCODE(type, inst) \
12544 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12545 inst.is_neon = 1; \
12549 #define check_neon_suffixes \
12552 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12554 as_bad (_("invalid neon suffix for non neon instruction")); \
12560 /* Define shapes for instruction operands. The following mnemonic characters
12561 are used in this table:
12563 F - VFP S<n> register
12564 D - Neon D<n> register
12565 Q - Neon Q<n> register
12569 L - D<n> register list
12571 This table is used to generate various data:
12572 - enumerations of the form NS_DDR to be used as arguments to
12574 - a table classifying shapes into single, double, quad, mixed.
12575 - a table used to drive neon_select_shape. */
12577 #define NEON_SHAPE_DEF \
12578 X(3, (D, D, D), DOUBLE), \
12579 X(3, (Q, Q, Q), QUAD), \
12580 X(3, (D, D, I), DOUBLE), \
12581 X(3, (Q, Q, I), QUAD), \
12582 X(3, (D, D, S), DOUBLE), \
12583 X(3, (Q, Q, S), QUAD), \
12584 X(2, (D, D), DOUBLE), \
12585 X(2, (Q, Q), QUAD), \
12586 X(2, (D, S), DOUBLE), \
12587 X(2, (Q, S), QUAD), \
12588 X(2, (D, R), DOUBLE), \
12589 X(2, (Q, R), QUAD), \
12590 X(2, (D, I), DOUBLE), \
12591 X(2, (Q, I), QUAD), \
12592 X(3, (D, L, D), DOUBLE), \
12593 X(2, (D, Q), MIXED), \
12594 X(2, (Q, D), MIXED), \
12595 X(3, (D, Q, I), MIXED), \
12596 X(3, (Q, D, I), MIXED), \
12597 X(3, (Q, D, D), MIXED), \
12598 X(3, (D, Q, Q), MIXED), \
12599 X(3, (Q, Q, D), MIXED), \
12600 X(3, (Q, D, S), MIXED), \
12601 X(3, (D, Q, S), MIXED), \
12602 X(4, (D, D, D, I), DOUBLE), \
12603 X(4, (Q, Q, Q, I), QUAD), \
12604 X(2, (F, F), SINGLE), \
12605 X(3, (F, F, F), SINGLE), \
12606 X(2, (F, I), SINGLE), \
12607 X(2, (F, D), MIXED), \
12608 X(2, (D, F), MIXED), \
12609 X(3, (F, F, I), MIXED), \
12610 X(4, (R, R, F, F), SINGLE), \
12611 X(4, (F, F, R, R), SINGLE), \
12612 X(3, (D, R, R), DOUBLE), \
12613 X(3, (R, R, D), DOUBLE), \
12614 X(2, (S, R), SINGLE), \
12615 X(2, (R, S), SINGLE), \
12616 X(2, (F, R), SINGLE), \
12617 X(2, (R, F), SINGLE)
12619 #define S2(A,B) NS_##A##B
12620 #define S3(A,B,C) NS_##A##B##C
12621 #define S4(A,B,C,D) NS_##A##B##C##D
12623 #define X(N, L, C) S##N L
12636 enum neon_shape_class
12644 #define X(N, L, C) SC_##C
12646 static enum neon_shape_class neon_shape_class
[] =
12664 /* Register widths of above. */
12665 static unsigned neon_shape_el_size
[] =
12676 struct neon_shape_info
12679 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12682 #define S2(A,B) { SE_##A, SE_##B }
12683 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12684 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12686 #define X(N, L, C) { N, S##N L }
12688 static struct neon_shape_info neon_shape_tab
[] =
12698 /* Bit masks used in type checking given instructions.
12699 'N_EQK' means the type must be the same as (or based on in some way) the key
12700 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12701 set, various other bits can be set as well in order to modify the meaning of
12702 the type constraint. */
12704 enum neon_type_mask
12728 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12729 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12730 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12731 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
12732 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12733 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12734 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12735 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12736 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12737 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12738 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12740 N_MAX_NONSPECIAL
= N_P64
12743 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12745 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12746 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12747 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12748 #define N_SUF_32 (N_SU_32 | N_F32)
12749 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12750 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12752 /* Pass this as the first type argument to neon_check_type to ignore types
12754 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12756 /* Select a "shape" for the current instruction (describing register types or
12757 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12758 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12759 function of operand parsing, so this function doesn't need to be called.
12760 Shapes should be listed in order of decreasing length. */
12762 static enum neon_shape
12763 neon_select_shape (enum neon_shape shape
, ...)
12766 enum neon_shape first_shape
= shape
;
12768 /* Fix missing optional operands. FIXME: we don't know at this point how
12769 many arguments we should have, so this makes the assumption that we have
12770 > 1. This is true of all current Neon opcodes, I think, but may not be
12771 true in the future. */
12772 if (!inst
.operands
[1].present
)
12773 inst
.operands
[1] = inst
.operands
[0];
12775 va_start (ap
, shape
);
12777 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12782 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12784 if (!inst
.operands
[j
].present
)
12790 switch (neon_shape_tab
[shape
].el
[j
])
12793 if (!(inst
.operands
[j
].isreg
12794 && inst
.operands
[j
].isvec
12795 && inst
.operands
[j
].issingle
12796 && !inst
.operands
[j
].isquad
))
12801 if (!(inst
.operands
[j
].isreg
12802 && inst
.operands
[j
].isvec
12803 && !inst
.operands
[j
].isquad
12804 && !inst
.operands
[j
].issingle
))
12809 if (!(inst
.operands
[j
].isreg
12810 && !inst
.operands
[j
].isvec
))
12815 if (!(inst
.operands
[j
].isreg
12816 && inst
.operands
[j
].isvec
12817 && inst
.operands
[j
].isquad
12818 && !inst
.operands
[j
].issingle
))
12823 if (!(!inst
.operands
[j
].isreg
12824 && !inst
.operands
[j
].isscalar
))
12829 if (!(!inst
.operands
[j
].isreg
12830 && inst
.operands
[j
].isscalar
))
12840 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
12841 /* We've matched all the entries in the shape table, and we don't
12842 have any left over operands which have not been matched. */
12848 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12849 first_error (_("invalid instruction shape"));
12854 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12855 means the Q bit should be set). */
12858 neon_quad (enum neon_shape shape
)
12860 return neon_shape_class
[shape
] == SC_QUAD
;
12864 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12867 /* Allow modification to be made to types which are constrained to be
12868 based on the key element, based on bits set alongside N_EQK. */
12869 if ((typebits
& N_EQK
) != 0)
12871 if ((typebits
& N_HLF
) != 0)
12873 else if ((typebits
& N_DBL
) != 0)
12875 if ((typebits
& N_SGN
) != 0)
12876 *g_type
= NT_signed
;
12877 else if ((typebits
& N_UNS
) != 0)
12878 *g_type
= NT_unsigned
;
12879 else if ((typebits
& N_INT
) != 0)
12880 *g_type
= NT_integer
;
12881 else if ((typebits
& N_FLT
) != 0)
12882 *g_type
= NT_float
;
12883 else if ((typebits
& N_SIZ
) != 0)
12884 *g_type
= NT_untyped
;
12888 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12889 operand type, i.e. the single type specified in a Neon instruction when it
12890 is the only one given. */
12892 static struct neon_type_el
12893 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12895 struct neon_type_el dest
= *key
;
12897 gas_assert ((thisarg
& N_EQK
) != 0);
12899 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12904 /* Convert Neon type and size into compact bitmask representation. */
12906 static enum neon_type_mask
12907 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12914 case 8: return N_8
;
12915 case 16: return N_16
;
12916 case 32: return N_32
;
12917 case 64: return N_64
;
12925 case 8: return N_I8
;
12926 case 16: return N_I16
;
12927 case 32: return N_I32
;
12928 case 64: return N_I64
;
12936 case 16: return N_F16
;
12937 case 32: return N_F32
;
12938 case 64: return N_F64
;
12946 case 8: return N_P8
;
12947 case 16: return N_P16
;
12948 case 64: return N_P64
;
12956 case 8: return N_S8
;
12957 case 16: return N_S16
;
12958 case 32: return N_S32
;
12959 case 64: return N_S64
;
12967 case 8: return N_U8
;
12968 case 16: return N_U16
;
12969 case 32: return N_U32
;
12970 case 64: return N_U64
;
12981 /* Convert compact Neon bitmask type representation to a type and size. Only
12982 handles the case where a single bit is set in the mask. */
12985 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12986 enum neon_type_mask mask
)
12988 if ((mask
& N_EQK
) != 0)
12991 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12993 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
12995 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12997 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13002 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13004 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13005 *type
= NT_unsigned
;
13006 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13007 *type
= NT_integer
;
13008 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13009 *type
= NT_untyped
;
13010 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13012 else if ((mask
& (N_F16
| N_F32
| N_F64
)) != 0)
13020 /* Modify a bitmask of allowed types. This is only needed for type
13024 modify_types_allowed (unsigned allowed
, unsigned mods
)
13027 enum neon_el_type type
;
13033 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13035 if (el_type_of_type_chk (&type
, &size
,
13036 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13038 neon_modify_type_size (mods
, &type
, &size
);
13039 destmask
|= type_chk_of_el_type (type
, size
);
13046 /* Check type and return type classification.
13047 The manual states (paraphrase): If one datatype is given, it indicates the
13049 - the second operand, if there is one
13050 - the operand, if there is no second operand
13051 - the result, if there are no operands.
13052 This isn't quite good enough though, so we use a concept of a "key" datatype
13053 which is set on a per-instruction basis, which is the one which matters when
13054 only one data type is written.
13055 Note: this function has side-effects (e.g. filling in missing operands). All
13056 Neon instructions should call it before performing bit encoding. */
13058 static struct neon_type_el
13059 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13062 unsigned i
, pass
, key_el
= 0;
13063 unsigned types
[NEON_MAX_TYPE_ELS
];
13064 enum neon_el_type k_type
= NT_invtype
;
13065 unsigned k_size
= -1u;
13066 struct neon_type_el badtype
= {NT_invtype
, -1};
13067 unsigned key_allowed
= 0;
13069 /* Optional registers in Neon instructions are always (not) in operand 1.
13070 Fill in the missing operand here, if it was omitted. */
13071 if (els
> 1 && !inst
.operands
[1].present
)
13072 inst
.operands
[1] = inst
.operands
[0];
13074 /* Suck up all the varargs. */
13076 for (i
= 0; i
< els
; i
++)
13078 unsigned thisarg
= va_arg (ap
, unsigned);
13079 if (thisarg
== N_IGNORE_TYPE
)
13084 types
[i
] = thisarg
;
13085 if ((thisarg
& N_KEY
) != 0)
13090 if (inst
.vectype
.elems
> 0)
13091 for (i
= 0; i
< els
; i
++)
13092 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
13094 first_error (_("types specified in both the mnemonic and operands"));
13098 /* Duplicate inst.vectype elements here as necessary.
13099 FIXME: No idea if this is exactly the same as the ARM assembler,
13100 particularly when an insn takes one register and one non-register
13102 if (inst
.vectype
.elems
== 1 && els
> 1)
13105 inst
.vectype
.elems
= els
;
13106 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
13107 for (j
= 0; j
< els
; j
++)
13109 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13112 else if (inst
.vectype
.elems
== 0 && els
> 0)
13115 /* No types were given after the mnemonic, so look for types specified
13116 after each operand. We allow some flexibility here; as long as the
13117 "key" operand has a type, we can infer the others. */
13118 for (j
= 0; j
< els
; j
++)
13119 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
13120 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
13122 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
13124 for (j
= 0; j
< els
; j
++)
13125 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
13126 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
13131 first_error (_("operand types can't be inferred"));
13135 else if (inst
.vectype
.elems
!= els
)
13137 first_error (_("type specifier has the wrong number of parts"));
13141 for (pass
= 0; pass
< 2; pass
++)
13143 for (i
= 0; i
< els
; i
++)
13145 unsigned thisarg
= types
[i
];
13146 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
13147 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
13148 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
13149 unsigned g_size
= inst
.vectype
.el
[i
].size
;
13151 /* Decay more-specific signed & unsigned types to sign-insensitive
13152 integer types if sign-specific variants are unavailable. */
13153 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
13154 && (types_allowed
& N_SU_ALL
) == 0)
13155 g_type
= NT_integer
;
13157 /* If only untyped args are allowed, decay any more specific types to
13158 them. Some instructions only care about signs for some element
13159 sizes, so handle that properly. */
13160 if (((types_allowed
& N_UNT
) == 0)
13161 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
13162 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
13163 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
13164 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
13165 g_type
= NT_untyped
;
13169 if ((thisarg
& N_KEY
) != 0)
13173 key_allowed
= thisarg
& ~N_KEY
;
13178 if ((thisarg
& N_VFP
) != 0)
13180 enum neon_shape_el regshape
;
13181 unsigned regwidth
, match
;
13183 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
13186 first_error (_("invalid instruction shape"));
13189 regshape
= neon_shape_tab
[ns
].el
[i
];
13190 regwidth
= neon_shape_el_size
[regshape
];
13192 /* In VFP mode, operands must match register widths. If we
13193 have a key operand, use its width, else use the width of
13194 the current operand. */
13200 if (regwidth
!= match
)
13202 first_error (_("operand size must match register width"));
13207 if ((thisarg
& N_EQK
) == 0)
13209 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
13211 if ((given_type
& types_allowed
) == 0)
13213 first_error (_("bad type in Neon instruction"));
13219 enum neon_el_type mod_k_type
= k_type
;
13220 unsigned mod_k_size
= k_size
;
13221 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
13222 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
13224 first_error (_("inconsistent types in Neon instruction"));
13232 return inst
.vectype
.el
[key_el
];
13235 /* Neon-style VFP instruction forwarding. */
13237 /* Thumb VFP instructions have 0xE in the condition field. */
13240 do_vfp_cond_or_thumb (void)
13245 inst
.instruction
|= 0xe0000000;
13247 inst
.instruction
|= inst
.cond
<< 28;
13250 /* Look up and encode a simple mnemonic, for use as a helper function for the
13251 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
13252 etc. It is assumed that operand parsing has already been done, and that the
13253 operands are in the form expected by the given opcode (this isn't necessarily
13254 the same as the form in which they were parsed, hence some massaging must
13255 take place before this function is called).
13256 Checks current arch version against that in the looked-up opcode. */
13259 do_vfp_nsyn_opcode (const char *opname
)
13261 const struct asm_opcode
*opcode
;
13263 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
13268 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
13269 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
13276 inst
.instruction
= opcode
->tvalue
;
13277 opcode
->tencode ();
13281 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
13282 opcode
->aencode ();
13287 do_vfp_nsyn_add_sub (enum neon_shape rs
)
13289 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
13294 do_vfp_nsyn_opcode ("fadds");
13296 do_vfp_nsyn_opcode ("fsubs");
13301 do_vfp_nsyn_opcode ("faddd");
13303 do_vfp_nsyn_opcode ("fsubd");
13307 /* Check operand types to see if this is a VFP instruction, and if so call
13311 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
13313 enum neon_shape rs
;
13314 struct neon_type_el et
;
13319 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13320 et
= neon_check_type (2, rs
,
13321 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13325 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13326 et
= neon_check_type (3, rs
,
13327 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13334 if (et
.type
!= NT_invtype
)
13345 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
13347 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
13352 do_vfp_nsyn_opcode ("fmacs");
13354 do_vfp_nsyn_opcode ("fnmacs");
13359 do_vfp_nsyn_opcode ("fmacd");
13361 do_vfp_nsyn_opcode ("fnmacd");
13366 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
13368 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
13373 do_vfp_nsyn_opcode ("ffmas");
13375 do_vfp_nsyn_opcode ("ffnmas");
13380 do_vfp_nsyn_opcode ("ffmad");
13382 do_vfp_nsyn_opcode ("ffnmad");
13387 do_vfp_nsyn_mul (enum neon_shape rs
)
13390 do_vfp_nsyn_opcode ("fmuls");
13392 do_vfp_nsyn_opcode ("fmuld");
13396 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
13398 int is_neg
= (inst
.instruction
& 0x80) != 0;
13399 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
13404 do_vfp_nsyn_opcode ("fnegs");
13406 do_vfp_nsyn_opcode ("fabss");
13411 do_vfp_nsyn_opcode ("fnegd");
13413 do_vfp_nsyn_opcode ("fabsd");
13417 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
13418 insns belong to Neon, and are handled elsewhere. */
13421 do_vfp_nsyn_ldm_stm (int is_dbmode
)
13423 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
13427 do_vfp_nsyn_opcode ("fldmdbs");
13429 do_vfp_nsyn_opcode ("fldmias");
13434 do_vfp_nsyn_opcode ("fstmdbs");
13436 do_vfp_nsyn_opcode ("fstmias");
13441 do_vfp_nsyn_sqrt (void)
13443 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13444 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13447 do_vfp_nsyn_opcode ("fsqrts");
13449 do_vfp_nsyn_opcode ("fsqrtd");
13453 do_vfp_nsyn_div (void)
13455 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13456 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13457 N_F32
| N_F64
| N_KEY
| N_VFP
);
13460 do_vfp_nsyn_opcode ("fdivs");
13462 do_vfp_nsyn_opcode ("fdivd");
13466 do_vfp_nsyn_nmul (void)
13468 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
13469 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
13470 N_F32
| N_F64
| N_KEY
| N_VFP
);
13474 NEON_ENCODE (SINGLE
, inst
);
13475 do_vfp_sp_dyadic ();
13479 NEON_ENCODE (DOUBLE
, inst
);
13480 do_vfp_dp_rd_rn_rm ();
13482 do_vfp_cond_or_thumb ();
13486 do_vfp_nsyn_cmp (void)
13488 if (inst
.operands
[1].isreg
)
13490 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
13491 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
13495 NEON_ENCODE (SINGLE
, inst
);
13496 do_vfp_sp_monadic ();
13500 NEON_ENCODE (DOUBLE
, inst
);
13501 do_vfp_dp_rd_rm ();
13506 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13507 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13509 switch (inst
.instruction
& 0x0fffffff)
13512 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13515 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13523 NEON_ENCODE (SINGLE
, inst
);
13524 do_vfp_sp_compare_z ();
13528 NEON_ENCODE (DOUBLE
, inst
);
13532 do_vfp_cond_or_thumb ();
13536 nsyn_insert_sp (void)
13538 inst
.operands
[1] = inst
.operands
[0];
13539 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13540 inst
.operands
[0].reg
= REG_SP
;
13541 inst
.operands
[0].isreg
= 1;
13542 inst
.operands
[0].writeback
= 1;
13543 inst
.operands
[0].present
= 1;
13547 do_vfp_nsyn_push (void)
13550 if (inst
.operands
[1].issingle
)
13551 do_vfp_nsyn_opcode ("fstmdbs");
13553 do_vfp_nsyn_opcode ("fstmdbd");
13557 do_vfp_nsyn_pop (void)
13560 if (inst
.operands
[1].issingle
)
13561 do_vfp_nsyn_opcode ("fldmias");
13563 do_vfp_nsyn_opcode ("fldmiad");
13566 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13567 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13570 neon_dp_fixup (struct arm_it
* insn
)
13572 unsigned int i
= insn
->instruction
;
13577 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13588 insn
->instruction
= i
;
13591 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13595 neon_logbits (unsigned x
)
13597 return ffs (x
) - 4;
13600 #define LOW4(R) ((R) & 0xf)
13601 #define HI1(R) (((R) >> 4) & 1)
13603 /* Encode insns with bit pattern:
13605 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13606 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13608 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13609 different meaning for some instruction. */
13612 neon_three_same (int isquad
, int ubit
, int size
)
13614 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13615 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13616 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13617 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13618 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13619 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13620 inst
.instruction
|= (isquad
!= 0) << 6;
13621 inst
.instruction
|= (ubit
!= 0) << 24;
13623 inst
.instruction
|= neon_logbits (size
) << 20;
13625 neon_dp_fixup (&inst
);
13628 /* Encode instructions of the form:
13630 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13631 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13633 Don't write size if SIZE == -1. */
13636 neon_two_same (int qbit
, int ubit
, int size
)
13638 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13639 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13640 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13641 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13642 inst
.instruction
|= (qbit
!= 0) << 6;
13643 inst
.instruction
|= (ubit
!= 0) << 24;
13646 inst
.instruction
|= neon_logbits (size
) << 18;
13648 neon_dp_fixup (&inst
);
13651 /* Neon instruction encoders, in approximate order of appearance. */
13654 do_neon_dyadic_i_su (void)
13656 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13657 struct neon_type_el et
= neon_check_type (3, rs
,
13658 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13659 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13663 do_neon_dyadic_i64_su (void)
13665 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13666 struct neon_type_el et
= neon_check_type (3, rs
,
13667 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13668 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13672 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13675 unsigned size
= et
.size
>> 3;
13676 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13677 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13678 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13679 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13680 inst
.instruction
|= (isquad
!= 0) << 6;
13681 inst
.instruction
|= immbits
<< 16;
13682 inst
.instruction
|= (size
>> 3) << 7;
13683 inst
.instruction
|= (size
& 0x7) << 19;
13685 inst
.instruction
|= (uval
!= 0) << 24;
13687 neon_dp_fixup (&inst
);
13691 do_neon_shl_imm (void)
13693 if (!inst
.operands
[2].isreg
)
13695 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13696 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13697 NEON_ENCODE (IMMED
, inst
);
13698 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13702 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13703 struct neon_type_el et
= neon_check_type (3, rs
,
13704 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13707 /* VSHL/VQSHL 3-register variants have syntax such as:
13709 whereas other 3-register operations encoded by neon_three_same have
13712 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13714 tmp
= inst
.operands
[2].reg
;
13715 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13716 inst
.operands
[1].reg
= tmp
;
13717 NEON_ENCODE (INTEGER
, inst
);
13718 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13723 do_neon_qshl_imm (void)
13725 if (!inst
.operands
[2].isreg
)
13727 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13728 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13730 NEON_ENCODE (IMMED
, inst
);
13731 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13732 inst
.operands
[2].imm
);
13736 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13737 struct neon_type_el et
= neon_check_type (3, rs
,
13738 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13741 /* See note in do_neon_shl_imm. */
13742 tmp
= inst
.operands
[2].reg
;
13743 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13744 inst
.operands
[1].reg
= tmp
;
13745 NEON_ENCODE (INTEGER
, inst
);
13746 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13751 do_neon_rshl (void)
13753 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13754 struct neon_type_el et
= neon_check_type (3, rs
,
13755 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13758 tmp
= inst
.operands
[2].reg
;
13759 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13760 inst
.operands
[1].reg
= tmp
;
13761 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13765 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13767 /* Handle .I8 pseudo-instructions. */
13770 /* Unfortunately, this will make everything apart from zero out-of-range.
13771 FIXME is this the intended semantics? There doesn't seem much point in
13772 accepting .I8 if so. */
13773 immediate
|= immediate
<< 8;
13779 if (immediate
== (immediate
& 0x000000ff))
13781 *immbits
= immediate
;
13784 else if (immediate
== (immediate
& 0x0000ff00))
13786 *immbits
= immediate
>> 8;
13789 else if (immediate
== (immediate
& 0x00ff0000))
13791 *immbits
= immediate
>> 16;
13794 else if (immediate
== (immediate
& 0xff000000))
13796 *immbits
= immediate
>> 24;
13799 if ((immediate
& 0xffff) != (immediate
>> 16))
13800 goto bad_immediate
;
13801 immediate
&= 0xffff;
13804 if (immediate
== (immediate
& 0x000000ff))
13806 *immbits
= immediate
;
13809 else if (immediate
== (immediate
& 0x0000ff00))
13811 *immbits
= immediate
>> 8;
13816 first_error (_("immediate value out of range"));
13820 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13824 neon_bits_same_in_bytes (unsigned imm
)
13826 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13827 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13828 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13829 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13832 /* For immediate of above form, return 0bABCD. */
13835 neon_squash_bits (unsigned imm
)
13837 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13838 | ((imm
& 0x01000000) >> 21);
13841 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13844 neon_qfloat_bits (unsigned imm
)
13846 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13849 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13850 the instruction. *OP is passed as the initial value of the op field, and
13851 may be set to a different value depending on the constant (i.e.
13852 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13853 MVN). If the immediate looks like a repeated pattern then also
13854 try smaller element sizes. */
13857 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13858 unsigned *immbits
, int *op
, int size
,
13859 enum neon_el_type type
)
13861 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13863 if (type
== NT_float
&& !float_p
)
13866 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13868 if (size
!= 32 || *op
== 1)
13870 *immbits
= neon_qfloat_bits (immlo
);
13876 if (neon_bits_same_in_bytes (immhi
)
13877 && neon_bits_same_in_bytes (immlo
))
13881 *immbits
= (neon_squash_bits (immhi
) << 4)
13882 | neon_squash_bits (immlo
);
13887 if (immhi
!= immlo
)
13893 if (immlo
== (immlo
& 0x000000ff))
13898 else if (immlo
== (immlo
& 0x0000ff00))
13900 *immbits
= immlo
>> 8;
13903 else if (immlo
== (immlo
& 0x00ff0000))
13905 *immbits
= immlo
>> 16;
13908 else if (immlo
== (immlo
& 0xff000000))
13910 *immbits
= immlo
>> 24;
13913 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13915 *immbits
= (immlo
>> 8) & 0xff;
13918 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13920 *immbits
= (immlo
>> 16) & 0xff;
13924 if ((immlo
& 0xffff) != (immlo
>> 16))
13931 if (immlo
== (immlo
& 0x000000ff))
13936 else if (immlo
== (immlo
& 0x0000ff00))
13938 *immbits
= immlo
>> 8;
13942 if ((immlo
& 0xff) != (immlo
>> 8))
13947 if (immlo
== (immlo
& 0x000000ff))
13949 /* Don't allow MVN with 8-bit immediate. */
13959 /* Write immediate bits [7:0] to the following locations:
13961 |28/24|23 19|18 16|15 4|3 0|
13962 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13964 This function is used by VMOV/VMVN/VORR/VBIC. */
13967 neon_write_immbits (unsigned immbits
)
13969 inst
.instruction
|= immbits
& 0xf;
13970 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13971 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13974 /* Invert low-order SIZE bits of XHI:XLO. */
13977 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13979 unsigned immlo
= xlo
? *xlo
: 0;
13980 unsigned immhi
= xhi
? *xhi
: 0;
13985 immlo
= (~immlo
) & 0xff;
13989 immlo
= (~immlo
) & 0xffff;
13993 immhi
= (~immhi
) & 0xffffffff;
13994 /* fall through. */
13997 immlo
= (~immlo
) & 0xffffffff;
14012 do_neon_logic (void)
14014 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14016 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14017 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14018 /* U bit and size field were set as part of the bitmask. */
14019 NEON_ENCODE (INTEGER
, inst
);
14020 neon_three_same (neon_quad (rs
), 0, -1);
14024 const int three_ops_form
= (inst
.operands
[2].present
14025 && !inst
.operands
[2].isreg
);
14026 const int immoperand
= (three_ops_form
? 2 : 1);
14027 enum neon_shape rs
= (three_ops_form
14028 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14029 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14030 struct neon_type_el et
= neon_check_type (2, rs
,
14031 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14032 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14036 if (et
.type
== NT_invtype
)
14039 if (three_ops_form
)
14040 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14041 _("first and second operands shall be the same register"));
14043 NEON_ENCODE (IMMED
, inst
);
14045 immbits
= inst
.operands
[immoperand
].imm
;
14048 /* .i64 is a pseudo-op, so the immediate must be a repeating
14050 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14051 inst
.operands
[immoperand
].reg
: 0))
14053 /* Set immbits to an invalid constant. */
14054 immbits
= 0xdeadbeef;
14061 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14065 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14069 /* Pseudo-instruction for VBIC. */
14070 neon_invert_size (&immbits
, 0, et
.size
);
14071 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14075 /* Pseudo-instruction for VORR. */
14076 neon_invert_size (&immbits
, 0, et
.size
);
14077 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14087 inst
.instruction
|= neon_quad (rs
) << 6;
14088 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14089 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14090 inst
.instruction
|= cmode
<< 8;
14091 neon_write_immbits (immbits
);
14093 neon_dp_fixup (&inst
);
14098 do_neon_bitfield (void)
14100 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14101 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14102 neon_three_same (neon_quad (rs
), 0, -1);
14106 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14109 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14110 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14112 if (et
.type
== NT_float
)
14114 NEON_ENCODE (FLOAT
, inst
);
14115 neon_three_same (neon_quad (rs
), 0, -1);
14119 NEON_ENCODE (INTEGER
, inst
);
14120 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14125 do_neon_dyadic_if_su (void)
14127 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14131 do_neon_dyadic_if_su_d (void)
14133 /* This version only allow D registers, but that constraint is enforced during
14134 operand parsing so we don't need to do anything extra here. */
14135 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14139 do_neon_dyadic_if_i_d (void)
14141 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14142 affected if we specify unsigned args. */
14143 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14146 enum vfp_or_neon_is_neon_bits
14149 NEON_CHECK_ARCH
= 2,
14150 NEON_CHECK_ARCH8
= 4
14153 /* Call this function if an instruction which may have belonged to the VFP or
14154 Neon instruction sets, but turned out to be a Neon instruction (due to the
14155 operand types involved, etc.). We have to check and/or fix-up a couple of
14158 - Make sure the user hasn't attempted to make a Neon instruction
14160 - Alter the value in the condition code field if necessary.
14161 - Make sure that the arch supports Neon instructions.
14163 Which of these operations take place depends on bits from enum
14164 vfp_or_neon_is_neon_bits.
14166 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14167 current instruction's condition is COND_ALWAYS, the condition field is
14168 changed to inst.uncond_value. This is necessary because instructions shared
14169 between VFP and Neon may be conditional for the VFP variants only, and the
14170 unconditional Neon version must have, e.g., 0xF in the condition field. */
14173 vfp_or_neon_is_neon (unsigned check
)
14175 /* Conditions are always legal in Thumb mode (IT blocks). */
14176 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14178 if (inst
.cond
!= COND_ALWAYS
)
14180 first_error (_(BAD_COND
));
14183 if (inst
.uncond_value
!= -1)
14184 inst
.instruction
|= inst
.uncond_value
<< 28;
14187 if ((check
& NEON_CHECK_ARCH
)
14188 && !mark_feature_used (&fpu_neon_ext_v1
))
14190 first_error (_(BAD_FPU
));
14194 if ((check
& NEON_CHECK_ARCH8
)
14195 && !mark_feature_used (&fpu_neon_ext_armv8
))
14197 first_error (_(BAD_FPU
));
14205 do_neon_addsub_if_i (void)
14207 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
14210 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14213 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14214 affected if we specify unsigned args. */
14215 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
14218 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
14220 V<op> A,B (A is operand 0, B is operand 2)
14225 so handle that case specially. */
14228 neon_exchange_operands (void)
14230 void *scratch
= alloca (sizeof (inst
.operands
[0]));
14231 if (inst
.operands
[1].present
)
14233 /* Swap operands[1] and operands[2]. */
14234 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
14235 inst
.operands
[1] = inst
.operands
[2];
14236 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
14240 inst
.operands
[1] = inst
.operands
[2];
14241 inst
.operands
[2] = inst
.operands
[0];
14246 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
14248 if (inst
.operands
[2].isreg
)
14251 neon_exchange_operands ();
14252 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
14256 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14257 struct neon_type_el et
= neon_check_type (2, rs
,
14258 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
14260 NEON_ENCODE (IMMED
, inst
);
14261 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14262 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14263 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14264 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14265 inst
.instruction
|= neon_quad (rs
) << 6;
14266 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14267 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14269 neon_dp_fixup (&inst
);
14276 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
14280 do_neon_cmp_inv (void)
14282 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
14288 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
14291 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
14292 scalars, which are encoded in 5 bits, M : Rm.
14293 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
14294 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
14298 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
14300 unsigned regno
= NEON_SCALAR_REG (scalar
);
14301 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
14306 if (regno
> 7 || elno
> 3)
14308 return regno
| (elno
<< 3);
14311 if (regno
> 15 || elno
> 1)
14313 return regno
| (elno
<< 4);
14317 first_error (_("scalar out of range for multiply instruction"));
14323 /* Encode multiply / multiply-accumulate scalar instructions. */
14326 neon_mul_mac (struct neon_type_el et
, int ubit
)
14330 /* Give a more helpful error message if we have an invalid type. */
14331 if (et
.type
== NT_invtype
)
14334 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
14335 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14336 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14337 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14338 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14339 inst
.instruction
|= LOW4 (scalar
);
14340 inst
.instruction
|= HI1 (scalar
) << 5;
14341 inst
.instruction
|= (et
.type
== NT_float
) << 8;
14342 inst
.instruction
|= neon_logbits (et
.size
) << 20;
14343 inst
.instruction
|= (ubit
!= 0) << 24;
14345 neon_dp_fixup (&inst
);
14349 do_neon_mac_maybe_scalar (void)
14351 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
14354 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14357 if (inst
.operands
[2].isscalar
)
14359 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14360 struct neon_type_el et
= neon_check_type (3, rs
,
14361 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
14362 NEON_ENCODE (SCALAR
, inst
);
14363 neon_mul_mac (et
, neon_quad (rs
));
14367 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14368 affected if we specify unsigned args. */
14369 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14374 do_neon_fmac (void)
14376 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
14379 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14382 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14388 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14389 struct neon_type_el et
= neon_check_type (3, rs
,
14390 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14391 neon_three_same (neon_quad (rs
), 0, et
.size
);
14394 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
14395 same types as the MAC equivalents. The polynomial type for this instruction
14396 is encoded the same as the integer type. */
14401 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
14404 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14407 if (inst
.operands
[2].isscalar
)
14408 do_neon_mac_maybe_scalar ();
14410 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
14414 do_neon_qdmulh (void)
14416 if (inst
.operands
[2].isscalar
)
14418 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
14419 struct neon_type_el et
= neon_check_type (3, rs
,
14420 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14421 NEON_ENCODE (SCALAR
, inst
);
14422 neon_mul_mac (et
, neon_quad (rs
));
14426 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14427 struct neon_type_el et
= neon_check_type (3, rs
,
14428 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
14429 NEON_ENCODE (INTEGER
, inst
);
14430 /* The U bit (rounding) comes from bit mask. */
14431 neon_three_same (neon_quad (rs
), 0, et
.size
);
14436 do_neon_fcmp_absolute (void)
14438 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14439 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14440 /* Size field comes from bit mask. */
14441 neon_three_same (neon_quad (rs
), 1, -1);
14445 do_neon_fcmp_absolute_inv (void)
14447 neon_exchange_operands ();
14448 do_neon_fcmp_absolute ();
14452 do_neon_step (void)
14454 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14455 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
14456 neon_three_same (neon_quad (rs
), 0, -1);
14460 do_neon_abs_neg (void)
14462 enum neon_shape rs
;
14463 struct neon_type_el et
;
14465 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
14468 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14471 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14472 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
14474 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14475 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14476 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14477 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14478 inst
.instruction
|= neon_quad (rs
) << 6;
14479 inst
.instruction
|= (et
.type
== NT_float
) << 10;
14480 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14482 neon_dp_fixup (&inst
);
14488 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14489 struct neon_type_el et
= neon_check_type (2, rs
,
14490 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14491 int imm
= inst
.operands
[2].imm
;
14492 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14493 _("immediate out of range for insert"));
14494 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14500 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14501 struct neon_type_el et
= neon_check_type (2, rs
,
14502 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14503 int imm
= inst
.operands
[2].imm
;
14504 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14505 _("immediate out of range for insert"));
14506 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14510 do_neon_qshlu_imm (void)
14512 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14513 struct neon_type_el et
= neon_check_type (2, rs
,
14514 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14515 int imm
= inst
.operands
[2].imm
;
14516 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14517 _("immediate out of range for shift"));
14518 /* Only encodes the 'U present' variant of the instruction.
14519 In this case, signed types have OP (bit 8) set to 0.
14520 Unsigned types have OP set to 1. */
14521 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14522 /* The rest of the bits are the same as other immediate shifts. */
14523 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14527 do_neon_qmovn (void)
14529 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14530 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14531 /* Saturating move where operands can be signed or unsigned, and the
14532 destination has the same signedness. */
14533 NEON_ENCODE (INTEGER
, inst
);
14534 if (et
.type
== NT_unsigned
)
14535 inst
.instruction
|= 0xc0;
14537 inst
.instruction
|= 0x80;
14538 neon_two_same (0, 1, et
.size
/ 2);
14542 do_neon_qmovun (void)
14544 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14545 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14546 /* Saturating move with unsigned results. Operands must be signed. */
14547 NEON_ENCODE (INTEGER
, inst
);
14548 neon_two_same (0, 1, et
.size
/ 2);
14552 do_neon_rshift_sat_narrow (void)
14554 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14555 or unsigned. If operands are unsigned, results must also be unsigned. */
14556 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14557 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14558 int imm
= inst
.operands
[2].imm
;
14559 /* This gets the bounds check, size encoding and immediate bits calculation
14563 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14564 VQMOVN.I<size> <Dd>, <Qm>. */
14567 inst
.operands
[2].present
= 0;
14568 inst
.instruction
= N_MNEM_vqmovn
;
14573 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14574 _("immediate out of range"));
14575 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14579 do_neon_rshift_sat_narrow_u (void)
14581 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14582 or unsigned. If operands are unsigned, results must also be unsigned. */
14583 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14584 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14585 int imm
= inst
.operands
[2].imm
;
14586 /* This gets the bounds check, size encoding and immediate bits calculation
14590 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14591 VQMOVUN.I<size> <Dd>, <Qm>. */
14594 inst
.operands
[2].present
= 0;
14595 inst
.instruction
= N_MNEM_vqmovun
;
14600 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14601 _("immediate out of range"));
14602 /* FIXME: The manual is kind of unclear about what value U should have in
14603 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14605 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14609 do_neon_movn (void)
14611 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14612 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14613 NEON_ENCODE (INTEGER
, inst
);
14614 neon_two_same (0, 1, et
.size
/ 2);
14618 do_neon_rshift_narrow (void)
14620 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14621 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14622 int imm
= inst
.operands
[2].imm
;
14623 /* This gets the bounds check, size encoding and immediate bits calculation
14627 /* If immediate is zero then we are a pseudo-instruction for
14628 VMOVN.I<size> <Dd>, <Qm> */
14631 inst
.operands
[2].present
= 0;
14632 inst
.instruction
= N_MNEM_vmovn
;
14637 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14638 _("immediate out of range for narrowing operation"));
14639 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14643 do_neon_shll (void)
14645 /* FIXME: Type checking when lengthening. */
14646 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14647 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14648 unsigned imm
= inst
.operands
[2].imm
;
14650 if (imm
== et
.size
)
14652 /* Maximum shift variant. */
14653 NEON_ENCODE (INTEGER
, inst
);
14654 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14655 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14656 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14657 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14658 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14660 neon_dp_fixup (&inst
);
14664 /* A more-specific type check for non-max versions. */
14665 et
= neon_check_type (2, NS_QDI
,
14666 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14667 NEON_ENCODE (IMMED
, inst
);
14668 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14672 /* Check the various types for the VCVT instruction, and return which version
14673 the current instruction is. */
14675 #define CVT_FLAVOUR_VAR \
14676 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
14677 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
14678 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
14679 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
14680 /* Half-precision conversions. */ \
14681 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
14682 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
14683 /* VFP instructions. */ \
14684 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
14685 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
14686 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
14687 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
14688 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
14689 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
14690 /* VFP instructions with bitshift. */ \
14691 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
14692 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
14693 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
14694 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
14695 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
14696 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
14697 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
14698 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
14700 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
14701 neon_cvt_flavour_##C,
14703 /* The different types of conversions we can do. */
14704 enum neon_cvt_flavour
14707 neon_cvt_flavour_invalid
,
14708 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
14713 static enum neon_cvt_flavour
14714 get_neon_cvt_flavour (enum neon_shape rs
)
14716 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
14717 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
14718 if (et.type != NT_invtype) \
14720 inst.error = NULL; \
14721 return (neon_cvt_flavour_##C); \
14724 struct neon_type_el et
;
14725 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14726 || rs
== NS_FF
) ? N_VFP
: 0;
14727 /* The instruction versions which take an immediate take one register
14728 argument, which is extended to the width of the full register. Thus the
14729 "source" and "destination" registers must have the same width. Hack that
14730 here by making the size equal to the key (wider, in this case) operand. */
14731 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14735 return neon_cvt_flavour_invalid
;
14750 /* Neon-syntax VFP conversions. */
14753 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
14755 const char *opname
= 0;
14757 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14759 /* Conversions with immediate bitshift. */
14760 const char *enc
[] =
14762 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
14768 if (flavour
< (int) ARRAY_SIZE (enc
))
14770 opname
= enc
[flavour
];
14771 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14772 _("operands 0 and 1 must be the same register"));
14773 inst
.operands
[1] = inst
.operands
[2];
14774 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14779 /* Conversions without bitshift. */
14780 const char *enc
[] =
14782 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
14788 if (flavour
< (int) ARRAY_SIZE (enc
))
14789 opname
= enc
[flavour
];
14793 do_vfp_nsyn_opcode (opname
);
14797 do_vfp_nsyn_cvtz (void)
14799 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14800 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
14801 const char *enc
[] =
14803 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
14809 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14810 do_vfp_nsyn_opcode (enc
[flavour
]);
14814 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
14815 enum neon_cvt_mode mode
)
14820 set_it_insn_type (OUTSIDE_IT_INSN
);
14824 case neon_cvt_flavour_s32_f64
:
14828 case neon_cvt_flavour_s32_f32
:
14832 case neon_cvt_flavour_u32_f64
:
14836 case neon_cvt_flavour_u32_f32
:
14841 first_error (_("invalid instruction shape"));
14847 case neon_cvt_mode_a
: rm
= 0; break;
14848 case neon_cvt_mode_n
: rm
= 1; break;
14849 case neon_cvt_mode_p
: rm
= 2; break;
14850 case neon_cvt_mode_m
: rm
= 3; break;
14851 default: first_error (_("invalid rounding mode")); return;
14854 NEON_ENCODE (FPV8
, inst
);
14855 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14856 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
14857 inst
.instruction
|= sz
<< 8;
14858 inst
.instruction
|= op
<< 7;
14859 inst
.instruction
|= rm
<< 16;
14860 inst
.instruction
|= 0xf0000000;
14861 inst
.is_neon
= TRUE
;
14865 do_neon_cvt_1 (enum neon_cvt_mode mode
)
14867 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14868 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14869 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
14871 /* PR11109: Handle round-to-zero for VCVT conversions. */
14872 if (mode
== neon_cvt_mode_z
14873 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14874 && (flavour
== neon_cvt_flavour_s32_f32
14875 || flavour
== neon_cvt_flavour_u32_f32
14876 || flavour
== neon_cvt_flavour_s32_f64
14877 || flavour
== neon_cvt_flavour_u32_f64
)
14878 && (rs
== NS_FD
|| rs
== NS_FF
))
14880 do_vfp_nsyn_cvtz ();
14884 /* VFP rather than Neon conversions. */
14885 if (flavour
>= neon_cvt_flavour_first_fp
)
14887 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
14888 do_vfp_nsyn_cvt (rs
, flavour
);
14890 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
14901 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14903 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14906 /* Fixed-point conversion with #0 immediate is encoded as an
14907 integer conversion. */
14908 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14910 immbits
= 32 - inst
.operands
[2].imm
;
14911 NEON_ENCODE (IMMED
, inst
);
14912 if (flavour
!= neon_cvt_flavour_invalid
)
14913 inst
.instruction
|= enctab
[flavour
];
14914 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14915 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14916 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14917 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14918 inst
.instruction
|= neon_quad (rs
) << 6;
14919 inst
.instruction
|= 1 << 21;
14920 inst
.instruction
|= immbits
<< 16;
14922 neon_dp_fixup (&inst
);
14928 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
14930 NEON_ENCODE (FLOAT
, inst
);
14931 set_it_insn_type (OUTSIDE_IT_INSN
);
14933 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
14936 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14937 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14938 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14939 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14940 inst
.instruction
|= neon_quad (rs
) << 6;
14941 inst
.instruction
|= (flavour
== neon_cvt_flavour_u32_f32
) << 7;
14942 inst
.instruction
|= mode
<< 8;
14944 inst
.instruction
|= 0xfc000000;
14946 inst
.instruction
|= 0xf0000000;
14952 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14954 NEON_ENCODE (INTEGER
, inst
);
14956 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14959 if (flavour
!= neon_cvt_flavour_invalid
)
14960 inst
.instruction
|= enctab
[flavour
];
14962 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14963 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14964 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14965 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14966 inst
.instruction
|= neon_quad (rs
) << 6;
14967 inst
.instruction
|= 2 << 18;
14969 neon_dp_fixup (&inst
);
14974 /* Half-precision conversions for Advanced SIMD -- neon. */
14979 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14981 as_bad (_("operand size must match register width"));
14986 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14988 as_bad (_("operand size must match register width"));
14993 inst
.instruction
= 0x3b60600;
14995 inst
.instruction
= 0x3b60700;
14997 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14998 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14999 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15000 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15001 neon_dp_fixup (&inst
);
15005 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15006 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15007 do_vfp_nsyn_cvt (rs
, flavour
);
15009 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15014 do_neon_cvtr (void)
15016 do_neon_cvt_1 (neon_cvt_mode_x
);
15022 do_neon_cvt_1 (neon_cvt_mode_z
);
15026 do_neon_cvta (void)
15028 do_neon_cvt_1 (neon_cvt_mode_a
);
15032 do_neon_cvtn (void)
15034 do_neon_cvt_1 (neon_cvt_mode_n
);
15038 do_neon_cvtp (void)
15040 do_neon_cvt_1 (neon_cvt_mode_p
);
15044 do_neon_cvtm (void)
15046 do_neon_cvt_1 (neon_cvt_mode_m
);
15050 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
15053 mark_feature_used (&fpu_vfp_ext_armv8
);
15055 encode_arm_vfp_reg (inst
.operands
[0].reg
,
15056 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
15057 encode_arm_vfp_reg (inst
.operands
[1].reg
,
15058 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
15059 inst
.instruction
|= to
? 0x10000 : 0;
15060 inst
.instruction
|= t
? 0x80 : 0;
15061 inst
.instruction
|= is_double
? 0x100 : 0;
15062 do_vfp_cond_or_thumb ();
15066 do_neon_cvttb_1 (bfd_boolean t
)
15068 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_DF
, NS_NULL
);
15072 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
15075 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
15077 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
15080 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
15082 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
15085 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
15087 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
15090 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
15097 do_neon_cvtb (void)
15099 do_neon_cvttb_1 (FALSE
);
15104 do_neon_cvtt (void)
15106 do_neon_cvttb_1 (TRUE
);
15110 neon_move_immediate (void)
15112 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
15113 struct neon_type_el et
= neon_check_type (2, rs
,
15114 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
15115 unsigned immlo
, immhi
= 0, immbits
;
15116 int op
, cmode
, float_p
;
15118 constraint (et
.type
== NT_invtype
,
15119 _("operand size must be specified for immediate VMOV"));
15121 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
15122 op
= (inst
.instruction
& (1 << 5)) != 0;
15124 immlo
= inst
.operands
[1].imm
;
15125 if (inst
.operands
[1].regisimm
)
15126 immhi
= inst
.operands
[1].reg
;
15128 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
15129 _("immediate has bits set outside the operand size"));
15131 float_p
= inst
.operands
[1].immisfloat
;
15133 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
15134 et
.size
, et
.type
)) == FAIL
)
15136 /* Invert relevant bits only. */
15137 neon_invert_size (&immlo
, &immhi
, et
.size
);
15138 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
15139 with one or the other; those cases are caught by
15140 neon_cmode_for_move_imm. */
15142 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
15143 &op
, et
.size
, et
.type
)) == FAIL
)
15145 first_error (_("immediate out of range"));
15150 inst
.instruction
&= ~(1 << 5);
15151 inst
.instruction
|= op
<< 5;
15153 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15154 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15155 inst
.instruction
|= neon_quad (rs
) << 6;
15156 inst
.instruction
|= cmode
<< 8;
15158 neon_write_immbits (immbits
);
15164 if (inst
.operands
[1].isreg
)
15166 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15168 NEON_ENCODE (INTEGER
, inst
);
15169 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15170 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15171 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15172 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15173 inst
.instruction
|= neon_quad (rs
) << 6;
15177 NEON_ENCODE (IMMED
, inst
);
15178 neon_move_immediate ();
15181 neon_dp_fixup (&inst
);
15184 /* Encode instructions of form:
15186 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
15187 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
15190 neon_mixed_length (struct neon_type_el et
, unsigned size
)
15192 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15193 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15194 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15195 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15196 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15197 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15198 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
15199 inst
.instruction
|= neon_logbits (size
) << 20;
15201 neon_dp_fixup (&inst
);
15205 do_neon_dyadic_long (void)
15207 /* FIXME: Type checking for lengthening op. */
15208 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15209 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15210 neon_mixed_length (et
, et
.size
);
15214 do_neon_abal (void)
15216 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15217 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
15218 neon_mixed_length (et
, et
.size
);
15222 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
15224 if (inst
.operands
[2].isscalar
)
15226 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
15227 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
15228 NEON_ENCODE (SCALAR
, inst
);
15229 neon_mul_mac (et
, et
.type
== NT_unsigned
);
15233 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15234 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
15235 NEON_ENCODE (INTEGER
, inst
);
15236 neon_mixed_length (et
, et
.size
);
15241 do_neon_mac_maybe_scalar_long (void)
15243 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
15247 do_neon_dyadic_wide (void)
15249 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
15250 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15251 neon_mixed_length (et
, et
.size
);
15255 do_neon_dyadic_narrow (void)
15257 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15258 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
15259 /* Operand sign is unimportant, and the U bit is part of the opcode,
15260 so force the operand type to integer. */
15261 et
.type
= NT_integer
;
15262 neon_mixed_length (et
, et
.size
/ 2);
15266 do_neon_mul_sat_scalar_long (void)
15268 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
15272 do_neon_vmull (void)
15274 if (inst
.operands
[2].isscalar
)
15275 do_neon_mac_maybe_scalar_long ();
15278 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
15279 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
15281 if (et
.type
== NT_poly
)
15282 NEON_ENCODE (POLY
, inst
);
15284 NEON_ENCODE (INTEGER
, inst
);
15286 /* For polynomial encoding the U bit must be zero, and the size must
15287 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
15288 obviously, as 0b10). */
15291 /* Check we're on the correct architecture. */
15292 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
15294 _("Instruction form not available on this architecture.");
15299 neon_mixed_length (et
, et
.size
);
15306 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
15307 struct neon_type_el et
= neon_check_type (3, rs
,
15308 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15309 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
15311 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
15312 _("shift out of range"));
15313 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15314 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15315 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15316 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15317 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15318 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15319 inst
.instruction
|= neon_quad (rs
) << 6;
15320 inst
.instruction
|= imm
<< 8;
15322 neon_dp_fixup (&inst
);
15328 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15329 struct neon_type_el et
= neon_check_type (2, rs
,
15330 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15331 unsigned op
= (inst
.instruction
>> 7) & 3;
15332 /* N (width of reversed regions) is encoded as part of the bitmask. We
15333 extract it here to check the elements to be reversed are smaller.
15334 Otherwise we'd get a reserved instruction. */
15335 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
15336 gas_assert (elsize
!= 0);
15337 constraint (et
.size
>= elsize
,
15338 _("elements must be smaller than reversal region"));
15339 neon_two_same (neon_quad (rs
), 1, et
.size
);
15345 if (inst
.operands
[1].isscalar
)
15347 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
15348 struct neon_type_el et
= neon_check_type (2, rs
,
15349 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15350 unsigned sizebits
= et
.size
>> 3;
15351 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15352 int logsize
= neon_logbits (et
.size
);
15353 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
15355 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
15358 NEON_ENCODE (SCALAR
, inst
);
15359 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15360 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15361 inst
.instruction
|= LOW4 (dm
);
15362 inst
.instruction
|= HI1 (dm
) << 5;
15363 inst
.instruction
|= neon_quad (rs
) << 6;
15364 inst
.instruction
|= x
<< 17;
15365 inst
.instruction
|= sizebits
<< 16;
15367 neon_dp_fixup (&inst
);
15371 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
15372 struct neon_type_el et
= neon_check_type (2, rs
,
15373 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15374 /* Duplicate ARM register to lanes of vector. */
15375 NEON_ENCODE (ARMREG
, inst
);
15378 case 8: inst
.instruction
|= 0x400000; break;
15379 case 16: inst
.instruction
|= 0x000020; break;
15380 case 32: inst
.instruction
|= 0x000000; break;
15383 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15384 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
15385 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
15386 inst
.instruction
|= neon_quad (rs
) << 21;
15387 /* The encoding for this instruction is identical for the ARM and Thumb
15388 variants, except for the condition field. */
15389 do_vfp_cond_or_thumb ();
15393 /* VMOV has particularly many variations. It can be one of:
15394 0. VMOV<c><q> <Qd>, <Qm>
15395 1. VMOV<c><q> <Dd>, <Dm>
15396 (Register operations, which are VORR with Rm = Rn.)
15397 2. VMOV<c><q>.<dt> <Qd>, #<imm>
15398 3. VMOV<c><q>.<dt> <Dd>, #<imm>
15400 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
15401 (ARM register to scalar.)
15402 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
15403 (Two ARM registers to vector.)
15404 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
15405 (Scalar to ARM register.)
15406 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
15407 (Vector to two ARM registers.)
15408 8. VMOV.F32 <Sd>, <Sm>
15409 9. VMOV.F64 <Dd>, <Dm>
15410 (VFP register moves.)
15411 10. VMOV.F32 <Sd>, #imm
15412 11. VMOV.F64 <Dd>, #imm
15413 (VFP float immediate load.)
15414 12. VMOV <Rd>, <Sm>
15415 (VFP single to ARM reg.)
15416 13. VMOV <Sd>, <Rm>
15417 (ARM reg to VFP single.)
15418 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
15419 (Two ARM regs to two VFP singles.)
15420 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
15421 (Two VFP singles to two ARM regs.)
15423 These cases can be disambiguated using neon_select_shape, except cases 1/9
15424 and 3/11 which depend on the operand type too.
15426 All the encoded bits are hardcoded by this function.
15428 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
15429 Cases 5, 7 may be used with VFPv2 and above.
15431 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
15432 can specify a type where it doesn't make sense to, and is ignored). */
15437 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
15438 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
15440 struct neon_type_el et
;
15441 const char *ldconst
= 0;
15445 case NS_DD
: /* case 1/9. */
15446 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15447 /* It is not an error here if no type is given. */
15449 if (et
.type
== NT_float
&& et
.size
== 64)
15451 do_vfp_nsyn_opcode ("fcpyd");
15454 /* fall through. */
15456 case NS_QQ
: /* case 0/1. */
15458 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15460 /* The architecture manual I have doesn't explicitly state which
15461 value the U bit should have for register->register moves, but
15462 the equivalent VORR instruction has U = 0, so do that. */
15463 inst
.instruction
= 0x0200110;
15464 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15465 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15466 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15467 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15468 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15469 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15470 inst
.instruction
|= neon_quad (rs
) << 6;
15472 neon_dp_fixup (&inst
);
15476 case NS_DI
: /* case 3/11. */
15477 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
15479 if (et
.type
== NT_float
&& et
.size
== 64)
15481 /* case 11 (fconstd). */
15482 ldconst
= "fconstd";
15483 goto encode_fconstd
;
15485 /* fall through. */
15487 case NS_QI
: /* case 2/3. */
15488 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15490 inst
.instruction
= 0x0800010;
15491 neon_move_immediate ();
15492 neon_dp_fixup (&inst
);
15495 case NS_SR
: /* case 4. */
15497 unsigned bcdebits
= 0;
15499 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
15500 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
15502 /* .<size> is optional here, defaulting to .32. */
15503 if (inst
.vectype
.elems
== 0
15504 && inst
.operands
[0].vectype
.type
== NT_invtype
15505 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15507 inst
.vectype
.el
[0].type
= NT_untyped
;
15508 inst
.vectype
.el
[0].size
= 32;
15509 inst
.vectype
.elems
= 1;
15512 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
15513 logsize
= neon_logbits (et
.size
);
15515 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15517 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15518 && et
.size
!= 32, _(BAD_FPU
));
15519 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15520 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15524 case 8: bcdebits
= 0x8; break;
15525 case 16: bcdebits
= 0x1; break;
15526 case 32: bcdebits
= 0x0; break;
15530 bcdebits
|= x
<< logsize
;
15532 inst
.instruction
= 0xe000b10;
15533 do_vfp_cond_or_thumb ();
15534 inst
.instruction
|= LOW4 (dn
) << 16;
15535 inst
.instruction
|= HI1 (dn
) << 7;
15536 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15537 inst
.instruction
|= (bcdebits
& 3) << 5;
15538 inst
.instruction
|= (bcdebits
>> 2) << 21;
15542 case NS_DRR
: /* case 5 (fmdrr). */
15543 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15546 inst
.instruction
= 0xc400b10;
15547 do_vfp_cond_or_thumb ();
15548 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
15549 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
15550 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
15551 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
15554 case NS_RS
: /* case 6. */
15557 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
15558 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
15559 unsigned abcdebits
= 0;
15561 /* .<dt> is optional here, defaulting to .32. */
15562 if (inst
.vectype
.elems
== 0
15563 && inst
.operands
[0].vectype
.type
== NT_invtype
15564 && inst
.operands
[1].vectype
.type
== NT_invtype
)
15566 inst
.vectype
.el
[0].type
= NT_untyped
;
15567 inst
.vectype
.el
[0].size
= 32;
15568 inst
.vectype
.elems
= 1;
15571 et
= neon_check_type (2, NS_NULL
,
15572 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
15573 logsize
= neon_logbits (et
.size
);
15575 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
15577 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
15578 && et
.size
!= 32, _(BAD_FPU
));
15579 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
15580 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
15584 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
15585 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
15586 case 32: abcdebits
= 0x00; break;
15590 abcdebits
|= x
<< logsize
;
15591 inst
.instruction
= 0xe100b10;
15592 do_vfp_cond_or_thumb ();
15593 inst
.instruction
|= LOW4 (dn
) << 16;
15594 inst
.instruction
|= HI1 (dn
) << 7;
15595 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15596 inst
.instruction
|= (abcdebits
& 3) << 5;
15597 inst
.instruction
|= (abcdebits
>> 2) << 21;
15601 case NS_RRD
: /* case 7 (fmrrd). */
15602 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
15605 inst
.instruction
= 0xc500b10;
15606 do_vfp_cond_or_thumb ();
15607 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
15608 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15609 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15610 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15613 case NS_FF
: /* case 8 (fcpys). */
15614 do_vfp_nsyn_opcode ("fcpys");
15617 case NS_FI
: /* case 10 (fconsts). */
15618 ldconst
= "fconsts";
15620 if (is_quarter_float (inst
.operands
[1].imm
))
15622 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
15623 do_vfp_nsyn_opcode (ldconst
);
15626 first_error (_("immediate out of range"));
15629 case NS_RF
: /* case 12 (fmrs). */
15630 do_vfp_nsyn_opcode ("fmrs");
15633 case NS_FR
: /* case 13 (fmsr). */
15634 do_vfp_nsyn_opcode ("fmsr");
15637 /* The encoders for the fmrrs and fmsrr instructions expect three operands
15638 (one of which is a list), but we have parsed four. Do some fiddling to
15639 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
15641 case NS_RRFF
: /* case 14 (fmrrs). */
15642 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
15643 _("VFP registers must be adjacent"));
15644 inst
.operands
[2].imm
= 2;
15645 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15646 do_vfp_nsyn_opcode ("fmrrs");
15649 case NS_FFRR
: /* case 15 (fmsrr). */
15650 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
15651 _("VFP registers must be adjacent"));
15652 inst
.operands
[1] = inst
.operands
[2];
15653 inst
.operands
[2] = inst
.operands
[3];
15654 inst
.operands
[0].imm
= 2;
15655 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
15656 do_vfp_nsyn_opcode ("fmsrr");
15660 /* neon_select_shape has determined that the instruction
15661 shape is wrong and has already set the error message. */
15670 do_neon_rshift_round_imm (void)
15672 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15673 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
15674 int imm
= inst
.operands
[2].imm
;
15676 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15679 inst
.operands
[2].present
= 0;
15684 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15685 _("immediate out of range for shift"));
15686 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15691 do_neon_movl (void)
15693 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15694 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15695 unsigned sizebits
= et
.size
>> 3;
15696 inst
.instruction
|= sizebits
<< 19;
15697 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15703 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15704 struct neon_type_el et
= neon_check_type (2, rs
,
15705 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15706 NEON_ENCODE (INTEGER
, inst
);
15707 neon_two_same (neon_quad (rs
), 1, et
.size
);
15711 do_neon_zip_uzp (void)
15713 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15714 struct neon_type_el et
= neon_check_type (2, rs
,
15715 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15716 if (rs
== NS_DD
&& et
.size
== 32)
15718 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15719 inst
.instruction
= N_MNEM_vtrn
;
15723 neon_two_same (neon_quad (rs
), 1, et
.size
);
15727 do_neon_sat_abs_neg (void)
15729 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15730 struct neon_type_el et
= neon_check_type (2, rs
,
15731 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15732 neon_two_same (neon_quad (rs
), 1, et
.size
);
15736 do_neon_pair_long (void)
15738 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15739 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15740 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15741 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15742 neon_two_same (neon_quad (rs
), 1, et
.size
);
15746 do_neon_recip_est (void)
15748 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15749 struct neon_type_el et
= neon_check_type (2, rs
,
15750 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15751 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15752 neon_two_same (neon_quad (rs
), 1, et
.size
);
15758 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15759 struct neon_type_el et
= neon_check_type (2, rs
,
15760 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15761 neon_two_same (neon_quad (rs
), 1, et
.size
);
15767 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15768 struct neon_type_el et
= neon_check_type (2, rs
,
15769 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15770 neon_two_same (neon_quad (rs
), 1, et
.size
);
15776 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15777 struct neon_type_el et
= neon_check_type (2, rs
,
15778 N_EQK
| N_INT
, N_8
| N_KEY
);
15779 neon_two_same (neon_quad (rs
), 1, et
.size
);
15785 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15786 neon_two_same (neon_quad (rs
), 1, -1);
15790 do_neon_tbl_tbx (void)
15792 unsigned listlenbits
;
15793 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15795 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15797 first_error (_("bad list length for table lookup"));
15801 listlenbits
= inst
.operands
[1].imm
- 1;
15802 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15803 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15804 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15805 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15806 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15807 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15808 inst
.instruction
|= listlenbits
<< 8;
15810 neon_dp_fixup (&inst
);
15814 do_neon_ldm_stm (void)
15816 /* P, U and L bits are part of bitmask. */
15817 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15818 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15820 if (inst
.operands
[1].issingle
)
15822 do_vfp_nsyn_ldm_stm (is_dbmode
);
15826 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15827 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15829 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15830 _("register list must contain at least 1 and at most 16 "
15833 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15834 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15835 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15836 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15838 inst
.instruction
|= offsetbits
;
15840 do_vfp_cond_or_thumb ();
15844 do_neon_ldr_str (void)
15846 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15848 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15849 And is UNPREDICTABLE in thumb mode. */
15851 && inst
.operands
[1].reg
== REG_PC
15852 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
15855 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15856 else if (warn_on_deprecated
)
15857 as_warn (_("Use of PC here is deprecated"));
15860 if (inst
.operands
[0].issingle
)
15863 do_vfp_nsyn_opcode ("flds");
15865 do_vfp_nsyn_opcode ("fsts");
15870 do_vfp_nsyn_opcode ("fldd");
15872 do_vfp_nsyn_opcode ("fstd");
15876 /* "interleave" version also handles non-interleaving register VLD1/VST1
15880 do_neon_ld_st_interleave (void)
15882 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15883 N_8
| N_16
| N_32
| N_64
);
15884 unsigned alignbits
= 0;
15886 /* The bits in this table go:
15887 0: register stride of one (0) or two (1)
15888 1,2: register list length, minus one (1, 2, 3, 4).
15889 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15890 We use -1 for invalid entries. */
15891 const int typetable
[] =
15893 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15894 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15895 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15896 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15900 if (et
.type
== NT_invtype
)
15903 if (inst
.operands
[1].immisalign
)
15904 switch (inst
.operands
[1].imm
>> 8)
15906 case 64: alignbits
= 1; break;
15908 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15909 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15910 goto bad_alignment
;
15914 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15915 goto bad_alignment
;
15920 first_error (_("bad alignment"));
15924 inst
.instruction
|= alignbits
<< 4;
15925 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15927 /* Bits [4:6] of the immediate in a list specifier encode register stride
15928 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15929 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15930 up the right value for "type" in a table based on this value and the given
15931 list style, then stick it back. */
15932 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15933 | (((inst
.instruction
>> 8) & 3) << 3);
15935 typebits
= typetable
[idx
];
15937 constraint (typebits
== -1, _("bad list type for instruction"));
15938 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
15939 _("bad element type for instruction"));
15941 inst
.instruction
&= ~0xf00;
15942 inst
.instruction
|= typebits
<< 8;
15945 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15946 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15947 otherwise. The variable arguments are a list of pairs of legal (size, align)
15948 values, terminated with -1. */
15951 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15954 int result
= FAIL
, thissize
, thisalign
;
15956 if (!inst
.operands
[1].immisalign
)
15962 va_start (ap
, do_align
);
15966 thissize
= va_arg (ap
, int);
15967 if (thissize
== -1)
15969 thisalign
= va_arg (ap
, int);
15971 if (size
== thissize
&& align
== thisalign
)
15974 while (result
!= SUCCESS
);
15978 if (result
== SUCCESS
)
15981 first_error (_("unsupported alignment for instruction"));
15987 do_neon_ld_st_lane (void)
15989 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15990 int align_good
, do_align
= 0;
15991 int logsize
= neon_logbits (et
.size
);
15992 int align
= inst
.operands
[1].imm
>> 8;
15993 int n
= (inst
.instruction
>> 8) & 3;
15994 int max_el
= 64 / et
.size
;
15996 if (et
.type
== NT_invtype
)
15999 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
16000 _("bad list length"));
16001 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
16002 _("scalar index out of range"));
16003 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
16005 _("stride of 2 unavailable when element size is 8"));
16009 case 0: /* VLD1 / VST1. */
16010 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
16012 if (align_good
== FAIL
)
16016 unsigned alignbits
= 0;
16019 case 16: alignbits
= 0x1; break;
16020 case 32: alignbits
= 0x3; break;
16023 inst
.instruction
|= alignbits
<< 4;
16027 case 1: /* VLD2 / VST2. */
16028 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
16030 if (align_good
== FAIL
)
16033 inst
.instruction
|= 1 << 4;
16036 case 2: /* VLD3 / VST3. */
16037 constraint (inst
.operands
[1].immisalign
,
16038 _("can't use alignment with this instruction"));
16041 case 3: /* VLD4 / VST4. */
16042 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16043 16, 64, 32, 64, 32, 128, -1);
16044 if (align_good
== FAIL
)
16048 unsigned alignbits
= 0;
16051 case 8: alignbits
= 0x1; break;
16052 case 16: alignbits
= 0x1; break;
16053 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
16056 inst
.instruction
|= alignbits
<< 4;
16063 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
16064 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16065 inst
.instruction
|= 1 << (4 + logsize
);
16067 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
16068 inst
.instruction
|= logsize
<< 10;
16071 /* Encode single n-element structure to all lanes VLD<n> instructions. */
16074 do_neon_ld_dup (void)
16076 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
16077 int align_good
, do_align
= 0;
16079 if (et
.type
== NT_invtype
)
16082 switch ((inst
.instruction
>> 8) & 3)
16084 case 0: /* VLD1. */
16085 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
16086 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16087 &do_align
, 16, 16, 32, 32, -1);
16088 if (align_good
== FAIL
)
16090 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
16093 case 2: inst
.instruction
|= 1 << 5; break;
16094 default: first_error (_("bad list length")); return;
16096 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16099 case 1: /* VLD2. */
16100 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
16101 &do_align
, 8, 16, 16, 32, 32, 64, -1);
16102 if (align_good
== FAIL
)
16104 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
16105 _("bad list length"));
16106 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16107 inst
.instruction
|= 1 << 5;
16108 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16111 case 2: /* VLD3. */
16112 constraint (inst
.operands
[1].immisalign
,
16113 _("can't use alignment with this instruction"));
16114 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
16115 _("bad list length"));
16116 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16117 inst
.instruction
|= 1 << 5;
16118 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16121 case 3: /* VLD4. */
16123 int align
= inst
.operands
[1].imm
>> 8;
16124 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
16125 16, 64, 32, 64, 32, 128, -1);
16126 if (align_good
== FAIL
)
16128 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
16129 _("bad list length"));
16130 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
16131 inst
.instruction
|= 1 << 5;
16132 if (et
.size
== 32 && align
== 128)
16133 inst
.instruction
|= 0x3 << 6;
16135 inst
.instruction
|= neon_logbits (et
.size
) << 6;
16142 inst
.instruction
|= do_align
<< 4;
16145 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
16146 apart from bits [11:4]. */
16149 do_neon_ldx_stx (void)
16151 if (inst
.operands
[1].isreg
)
16152 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16154 switch (NEON_LANE (inst
.operands
[0].imm
))
16156 case NEON_INTERLEAVE_LANES
:
16157 NEON_ENCODE (INTERLV
, inst
);
16158 do_neon_ld_st_interleave ();
16161 case NEON_ALL_LANES
:
16162 NEON_ENCODE (DUP
, inst
);
16163 if (inst
.instruction
== N_INV
)
16165 first_error ("only loads support such operands");
16172 NEON_ENCODE (LANE
, inst
);
16173 do_neon_ld_st_lane ();
16176 /* L bit comes from bit mask. */
16177 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16178 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16179 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16181 if (inst
.operands
[1].postind
)
16183 int postreg
= inst
.operands
[1].imm
& 0xf;
16184 constraint (!inst
.operands
[1].immisreg
,
16185 _("post-index must be a register"));
16186 constraint (postreg
== 0xd || postreg
== 0xf,
16187 _("bad register for post-index"));
16188 inst
.instruction
|= postreg
;
16192 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
16193 constraint (inst
.reloc
.exp
.X_op
!= O_constant
16194 || inst
.reloc
.exp
.X_add_number
!= 0,
16197 if (inst
.operands
[1].writeback
)
16199 inst
.instruction
|= 0xd;
16202 inst
.instruction
|= 0xf;
16206 inst
.instruction
|= 0xf9000000;
16208 inst
.instruction
|= 0xf4000000;
16213 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
16215 NEON_ENCODE (FPV8
, inst
);
16218 do_vfp_sp_dyadic ();
16220 do_vfp_dp_rd_rn_rm ();
16223 inst
.instruction
|= 0x100;
16225 inst
.instruction
|= 0xf0000000;
16231 set_it_insn_type (OUTSIDE_IT_INSN
);
16233 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
16234 first_error (_("invalid instruction shape"));
16240 set_it_insn_type (OUTSIDE_IT_INSN
);
16242 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
16245 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16248 neon_dyadic_misc (NT_untyped
, N_F32
, 0);
16252 do_vrint_1 (enum neon_cvt_mode mode
)
16254 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
16255 struct neon_type_el et
;
16260 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
16261 if (et
.type
!= NT_invtype
)
16263 /* VFP encodings. */
16264 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
16265 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
16266 set_it_insn_type (OUTSIDE_IT_INSN
);
16268 NEON_ENCODE (FPV8
, inst
);
16270 do_vfp_sp_monadic ();
16272 do_vfp_dp_rd_rm ();
16276 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
16277 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
16278 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
16279 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
16280 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
16281 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
16282 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
16286 inst
.instruction
|= (rs
== NS_DD
) << 8;
16287 do_vfp_cond_or_thumb ();
16291 /* Neon encodings (or something broken...). */
16293 et
= neon_check_type (2, rs
, N_EQK
, N_F32
| N_KEY
);
16295 if (et
.type
== NT_invtype
)
16298 set_it_insn_type (OUTSIDE_IT_INSN
);
16299 NEON_ENCODE (FLOAT
, inst
);
16301 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
16304 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16305 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16306 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16307 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16308 inst
.instruction
|= neon_quad (rs
) << 6;
16311 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
16312 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
16313 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
16314 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
16315 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
16316 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
16317 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
16322 inst
.instruction
|= 0xfc000000;
16324 inst
.instruction
|= 0xf0000000;
16331 do_vrint_1 (neon_cvt_mode_x
);
16337 do_vrint_1 (neon_cvt_mode_z
);
16343 do_vrint_1 (neon_cvt_mode_r
);
16349 do_vrint_1 (neon_cvt_mode_a
);
16355 do_vrint_1 (neon_cvt_mode_n
);
16361 do_vrint_1 (neon_cvt_mode_p
);
16367 do_vrint_1 (neon_cvt_mode_m
);
16370 /* Crypto v1 instructions. */
16372 do_crypto_2op_1 (unsigned elttype
, int op
)
16374 set_it_insn_type (OUTSIDE_IT_INSN
);
16376 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
16382 NEON_ENCODE (INTEGER
, inst
);
16383 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16384 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16385 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16386 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16388 inst
.instruction
|= op
<< 6;
16391 inst
.instruction
|= 0xfc000000;
16393 inst
.instruction
|= 0xf0000000;
16397 do_crypto_3op_1 (int u
, int op
)
16399 set_it_insn_type (OUTSIDE_IT_INSN
);
16401 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
16402 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
16407 NEON_ENCODE (INTEGER
, inst
);
16408 neon_three_same (1, u
, 8 << op
);
16414 do_crypto_2op_1 (N_8
, 0);
16420 do_crypto_2op_1 (N_8
, 1);
16426 do_crypto_2op_1 (N_8
, 2);
16432 do_crypto_2op_1 (N_8
, 3);
16438 do_crypto_3op_1 (0, 0);
16444 do_crypto_3op_1 (0, 1);
16450 do_crypto_3op_1 (0, 2);
16456 do_crypto_3op_1 (0, 3);
16462 do_crypto_3op_1 (1, 0);
16468 do_crypto_3op_1 (1, 1);
16472 do_sha256su1 (void)
16474 do_crypto_3op_1 (1, 2);
16480 do_crypto_2op_1 (N_32
, -1);
16486 do_crypto_2op_1 (N_32
, 0);
16490 do_sha256su0 (void)
16492 do_crypto_2op_1 (N_32
, 1);
16496 do_crc32_1 (unsigned int poly
, unsigned int sz
)
16498 unsigned int Rd
= inst
.operands
[0].reg
;
16499 unsigned int Rn
= inst
.operands
[1].reg
;
16500 unsigned int Rm
= inst
.operands
[2].reg
;
16502 set_it_insn_type (OUTSIDE_IT_INSN
);
16503 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
16504 inst
.instruction
|= LOW4 (Rn
) << 16;
16505 inst
.instruction
|= LOW4 (Rm
);
16506 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
16507 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
16509 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
16510 as_warn (UNPRED_REG ("r15"));
16511 if (thumb_mode
&& (Rd
== REG_SP
|| Rn
== REG_SP
|| Rm
== REG_SP
))
16512 as_warn (UNPRED_REG ("r13"));
16552 /* Overall per-instruction processing. */
16554 /* We need to be able to fix up arbitrary expressions in some statements.
16555 This is so that we can handle symbols that are an arbitrary distance from
16556 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
16557 which returns part of an address in a form which will be valid for
16558 a data instruction. We do this by pushing the expression into a symbol
16559 in the expr_section, and creating a fix for that. */
16562 fix_new_arm (fragS
* frag
,
16576 /* Create an absolute valued symbol, so we have something to
16577 refer to in the object file. Unfortunately for us, gas's
16578 generic expression parsing will already have folded out
16579 any use of .set foo/.type foo %function that may have
16580 been used to set type information of the target location,
16581 that's being specified symbolically. We have to presume
16582 the user knows what they are doing. */
16586 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
16588 symbol
= symbol_find_or_make (name
);
16589 S_SET_SEGMENT (symbol
, absolute_section
);
16590 symbol_set_frag (symbol
, &zero_address_frag
);
16591 S_SET_VALUE (symbol
, exp
->X_add_number
);
16592 exp
->X_op
= O_symbol
;
16593 exp
->X_add_symbol
= symbol
;
16594 exp
->X_add_number
= 0;
16600 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
16601 (enum bfd_reloc_code_real
) reloc
);
16605 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
16606 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
16610 /* Mark whether the fix is to a THUMB instruction, or an ARM
16612 new_fix
->tc_fix_data
= thumb_mode
;
16615 /* Create a frg for an instruction requiring relaxation. */
16617 output_relax_insn (void)
16623 /* The size of the instruction is unknown, so tie the debug info to the
16624 start of the instruction. */
16625 dwarf2_emit_insn (0);
16627 switch (inst
.reloc
.exp
.X_op
)
16630 sym
= inst
.reloc
.exp
.X_add_symbol
;
16631 offset
= inst
.reloc
.exp
.X_add_number
;
16635 offset
= inst
.reloc
.exp
.X_add_number
;
16638 sym
= make_expr_symbol (&inst
.reloc
.exp
);
16642 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
16643 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
16644 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
16647 /* Write a 32-bit thumb instruction to buf. */
16649 put_thumb32_insn (char * buf
, unsigned long insn
)
16651 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
16652 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
16656 output_inst (const char * str
)
16662 as_bad ("%s -- `%s'", inst
.error
, str
);
16667 output_relax_insn ();
16670 if (inst
.size
== 0)
16673 to
= frag_more (inst
.size
);
16674 /* PR 9814: Record the thumb mode into the current frag so that we know
16675 what type of NOP padding to use, if necessary. We override any previous
16676 setting so that if the mode has changed then the NOPS that we use will
16677 match the encoding of the last instruction in the frag. */
16678 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
16680 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
16682 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
16683 put_thumb32_insn (to
, inst
.instruction
);
16685 else if (inst
.size
> INSN_SIZE
)
16687 gas_assert (inst
.size
== (2 * INSN_SIZE
));
16688 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
16689 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
16692 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
16694 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
16695 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
16696 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
16699 dwarf2_emit_insn (inst
.size
);
16703 output_it_inst (int cond
, int mask
, char * to
)
16705 unsigned long instruction
= 0xbf00;
16708 instruction
|= mask
;
16709 instruction
|= cond
<< 4;
16713 to
= frag_more (2);
16715 dwarf2_emit_insn (2);
16719 md_number_to_chars (to
, instruction
, 2);
16724 /* Tag values used in struct asm_opcode's tag field. */
16727 OT_unconditional
, /* Instruction cannot be conditionalized.
16728 The ARM condition field is still 0xE. */
16729 OT_unconditionalF
, /* Instruction cannot be conditionalized
16730 and carries 0xF in its ARM condition field. */
16731 OT_csuffix
, /* Instruction takes a conditional suffix. */
16732 OT_csuffixF
, /* Some forms of the instruction take a conditional
16733 suffix, others place 0xF where the condition field
16735 OT_cinfix3
, /* Instruction takes a conditional infix,
16736 beginning at character index 3. (In
16737 unified mode, it becomes a suffix.) */
16738 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
16739 tsts, cmps, cmns, and teqs. */
16740 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
16741 character index 3, even in unified mode. Used for
16742 legacy instructions where suffix and infix forms
16743 may be ambiguous. */
16744 OT_csuf_or_in3
, /* Instruction takes either a conditional
16745 suffix or an infix at character index 3. */
16746 OT_odd_infix_unc
, /* This is the unconditional variant of an
16747 instruction that takes a conditional infix
16748 at an unusual position. In unified mode,
16749 this variant will accept a suffix. */
16750 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
16751 are the conditional variants of instructions that
16752 take conditional infixes in unusual positions.
16753 The infix appears at character index
16754 (tag - OT_odd_infix_0). These are not accepted
16755 in unified mode. */
16758 /* Subroutine of md_assemble, responsible for looking up the primary
16759 opcode from the mnemonic the user wrote. STR points to the
16760 beginning of the mnemonic.
16762 This is not simply a hash table lookup, because of conditional
16763 variants. Most instructions have conditional variants, which are
16764 expressed with a _conditional affix_ to the mnemonic. If we were
16765 to encode each conditional variant as a literal string in the opcode
16766 table, it would have approximately 20,000 entries.
16768 Most mnemonics take this affix as a suffix, and in unified syntax,
16769 'most' is upgraded to 'all'. However, in the divided syntax, some
16770 instructions take the affix as an infix, notably the s-variants of
16771 the arithmetic instructions. Of those instructions, all but six
16772 have the infix appear after the third character of the mnemonic.
16774 Accordingly, the algorithm for looking up primary opcodes given
16777 1. Look up the identifier in the opcode table.
16778 If we find a match, go to step U.
16780 2. Look up the last two characters of the identifier in the
16781 conditions table. If we find a match, look up the first N-2
16782 characters of the identifier in the opcode table. If we
16783 find a match, go to step CE.
16785 3. Look up the fourth and fifth characters of the identifier in
16786 the conditions table. If we find a match, extract those
16787 characters from the identifier, and look up the remaining
16788 characters in the opcode table. If we find a match, go
16793 U. Examine the tag field of the opcode structure, in case this is
16794 one of the six instructions with its conditional infix in an
16795 unusual place. If it is, the tag tells us where to find the
16796 infix; look it up in the conditions table and set inst.cond
16797 accordingly. Otherwise, this is an unconditional instruction.
16798 Again set inst.cond accordingly. Return the opcode structure.
16800 CE. Examine the tag field to make sure this is an instruction that
16801 should receive a conditional suffix. If it is not, fail.
16802 Otherwise, set inst.cond from the suffix we already looked up,
16803 and return the opcode structure.
16805 CM. Examine the tag field to make sure this is an instruction that
16806 should receive a conditional infix after the third character.
16807 If it is not, fail. Otherwise, undo the edits to the current
16808 line of input and proceed as for case CE. */
16810 static const struct asm_opcode
*
16811 opcode_lookup (char **str
)
16815 const struct asm_opcode
*opcode
;
16816 const struct asm_cond
*cond
;
16819 /* Scan up to the end of the mnemonic, which must end in white space,
16820 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
16821 for (base
= end
= *str
; *end
!= '\0'; end
++)
16822 if (*end
== ' ' || *end
== '.')
16828 /* Handle a possible width suffix and/or Neon type suffix. */
16833 /* The .w and .n suffixes are only valid if the unified syntax is in
16835 if (unified_syntax
&& end
[1] == 'w')
16837 else if (unified_syntax
&& end
[1] == 'n')
16842 inst
.vectype
.elems
= 0;
16844 *str
= end
+ offset
;
16846 if (end
[offset
] == '.')
16848 /* See if we have a Neon type suffix (possible in either unified or
16849 non-unified ARM syntax mode). */
16850 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
16853 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
16859 /* Look for unaffixed or special-case affixed mnemonic. */
16860 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16865 if (opcode
->tag
< OT_odd_infix_0
)
16867 inst
.cond
= COND_ALWAYS
;
16871 if (warn_on_deprecated
&& unified_syntax
)
16872 as_warn (_("conditional infixes are deprecated in unified syntax"));
16873 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
16874 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16877 inst
.cond
= cond
->value
;
16881 /* Cannot have a conditional suffix on a mnemonic of less than two
16883 if (end
- base
< 3)
16886 /* Look for suffixed mnemonic. */
16888 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16889 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16891 if (opcode
&& cond
)
16894 switch (opcode
->tag
)
16896 case OT_cinfix3_legacy
:
16897 /* Ignore conditional suffixes matched on infix only mnemonics. */
16901 case OT_cinfix3_deprecated
:
16902 case OT_odd_infix_unc
:
16903 if (!unified_syntax
)
16905 /* else fall through */
16909 case OT_csuf_or_in3
:
16910 inst
.cond
= cond
->value
;
16913 case OT_unconditional
:
16914 case OT_unconditionalF
:
16916 inst
.cond
= cond
->value
;
16919 /* Delayed diagnostic. */
16920 inst
.error
= BAD_COND
;
16921 inst
.cond
= COND_ALWAYS
;
16930 /* Cannot have a usual-position infix on a mnemonic of less than
16931 six characters (five would be a suffix). */
16932 if (end
- base
< 6)
16935 /* Look for infixed mnemonic in the usual position. */
16937 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
16941 memcpy (save
, affix
, 2);
16942 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
16943 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
16945 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
16946 memcpy (affix
, save
, 2);
16949 && (opcode
->tag
== OT_cinfix3
16950 || opcode
->tag
== OT_cinfix3_deprecated
16951 || opcode
->tag
== OT_csuf_or_in3
16952 || opcode
->tag
== OT_cinfix3_legacy
))
16955 if (warn_on_deprecated
&& unified_syntax
16956 && (opcode
->tag
== OT_cinfix3
16957 || opcode
->tag
== OT_cinfix3_deprecated
))
16958 as_warn (_("conditional infixes are deprecated in unified syntax"));
16960 inst
.cond
= cond
->value
;
16967 /* This function generates an initial IT instruction, leaving its block
16968 virtually open for the new instructions. Eventually,
16969 the mask will be updated by now_it_add_mask () each time
16970 a new instruction needs to be included in the IT block.
16971 Finally, the block is closed with close_automatic_it_block ().
16972 The block closure can be requested either from md_assemble (),
16973 a tencode (), or due to a label hook. */
16976 new_automatic_it_block (int cond
)
16978 now_it
.state
= AUTOMATIC_IT_BLOCK
;
16979 now_it
.mask
= 0x18;
16981 now_it
.block_length
= 1;
16982 mapping_state (MAP_THUMB
);
16983 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
16984 now_it
.warn_deprecated
= FALSE
;
16985 now_it
.insn_cond
= TRUE
;
16988 /* Close an automatic IT block.
16989 See comments in new_automatic_it_block (). */
16992 close_automatic_it_block (void)
16994 now_it
.mask
= 0x10;
16995 now_it
.block_length
= 0;
16998 /* Update the mask of the current automatically-generated IT
16999 instruction. See comments in new_automatic_it_block (). */
17002 now_it_add_mask (int cond
)
17004 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
17005 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
17006 | ((bitvalue) << (nbit)))
17007 const int resulting_bit
= (cond
& 1);
17009 now_it
.mask
&= 0xf;
17010 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17012 (5 - now_it
.block_length
));
17013 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
17015 ((5 - now_it
.block_length
) - 1) );
17016 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
17019 #undef SET_BIT_VALUE
17022 /* The IT blocks handling machinery is accessed through the these functions:
17023 it_fsm_pre_encode () from md_assemble ()
17024 set_it_insn_type () optional, from the tencode functions
17025 set_it_insn_type_last () ditto
17026 in_it_block () ditto
17027 it_fsm_post_encode () from md_assemble ()
17028 force_automatic_it_block_close () from label habdling functions
17031 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
17032 initializing the IT insn type with a generic initial value depending
17033 on the inst.condition.
17034 2) During the tencode function, two things may happen:
17035 a) The tencode function overrides the IT insn type by
17036 calling either set_it_insn_type (type) or set_it_insn_type_last ().
17037 b) The tencode function queries the IT block state by
17038 calling in_it_block () (i.e. to determine narrow/not narrow mode).
17040 Both set_it_insn_type and in_it_block run the internal FSM state
17041 handling function (handle_it_state), because: a) setting the IT insn
17042 type may incur in an invalid state (exiting the function),
17043 and b) querying the state requires the FSM to be updated.
17044 Specifically we want to avoid creating an IT block for conditional
17045 branches, so it_fsm_pre_encode is actually a guess and we can't
17046 determine whether an IT block is required until the tencode () routine
17047 has decided what type of instruction this actually it.
17048 Because of this, if set_it_insn_type and in_it_block have to be used,
17049 set_it_insn_type has to be called first.
17051 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
17052 determines the insn IT type depending on the inst.cond code.
17053 When a tencode () routine encodes an instruction that can be
17054 either outside an IT block, or, in the case of being inside, has to be
17055 the last one, set_it_insn_type_last () will determine the proper
17056 IT instruction type based on the inst.cond code. Otherwise,
17057 set_it_insn_type can be called for overriding that logic or
17058 for covering other cases.
17060 Calling handle_it_state () may not transition the IT block state to
17061 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
17062 still queried. Instead, if the FSM determines that the state should
17063 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
17064 after the tencode () function: that's what it_fsm_post_encode () does.
17066 Since in_it_block () calls the state handling function to get an
17067 updated state, an error may occur (due to invalid insns combination).
17068 In that case, inst.error is set.
17069 Therefore, inst.error has to be checked after the execution of
17070 the tencode () routine.
17072 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
17073 any pending state change (if any) that didn't take place in
17074 handle_it_state () as explained above. */
17077 it_fsm_pre_encode (void)
17079 if (inst
.cond
!= COND_ALWAYS
)
17080 inst
.it_insn_type
= INSIDE_IT_INSN
;
17082 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
17084 now_it
.state_handled
= 0;
17087 /* IT state FSM handling function. */
17090 handle_it_state (void)
17092 now_it
.state_handled
= 1;
17093 now_it
.insn_cond
= FALSE
;
17095 switch (now_it
.state
)
17097 case OUTSIDE_IT_BLOCK
:
17098 switch (inst
.it_insn_type
)
17100 case OUTSIDE_IT_INSN
:
17103 case INSIDE_IT_INSN
:
17104 case INSIDE_IT_LAST_INSN
:
17105 if (thumb_mode
== 0)
17108 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
17109 as_tsktsk (_("Warning: conditional outside an IT block"\
17114 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
17115 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
17117 /* Automatically generate the IT instruction. */
17118 new_automatic_it_block (inst
.cond
);
17119 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
17120 close_automatic_it_block ();
17124 inst
.error
= BAD_OUT_IT
;
17130 case IF_INSIDE_IT_LAST_INSN
:
17131 case NEUTRAL_IT_INSN
:
17135 now_it
.state
= MANUAL_IT_BLOCK
;
17136 now_it
.block_length
= 0;
17141 case AUTOMATIC_IT_BLOCK
:
17142 /* Three things may happen now:
17143 a) We should increment current it block size;
17144 b) We should close current it block (closing insn or 4 insns);
17145 c) We should close current it block and start a new one (due
17146 to incompatible conditions or
17147 4 insns-length block reached). */
17149 switch (inst
.it_insn_type
)
17151 case OUTSIDE_IT_INSN
:
17152 /* The closure of the block shall happen immediatelly,
17153 so any in_it_block () call reports the block as closed. */
17154 force_automatic_it_block_close ();
17157 case INSIDE_IT_INSN
:
17158 case INSIDE_IT_LAST_INSN
:
17159 case IF_INSIDE_IT_LAST_INSN
:
17160 now_it
.block_length
++;
17162 if (now_it
.block_length
> 4
17163 || !now_it_compatible (inst
.cond
))
17165 force_automatic_it_block_close ();
17166 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
17167 new_automatic_it_block (inst
.cond
);
17171 now_it
.insn_cond
= TRUE
;
17172 now_it_add_mask (inst
.cond
);
17175 if (now_it
.state
== AUTOMATIC_IT_BLOCK
17176 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
17177 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
17178 close_automatic_it_block ();
17181 case NEUTRAL_IT_INSN
:
17182 now_it
.block_length
++;
17183 now_it
.insn_cond
= TRUE
;
17185 if (now_it
.block_length
> 4)
17186 force_automatic_it_block_close ();
17188 now_it_add_mask (now_it
.cc
& 1);
17192 close_automatic_it_block ();
17193 now_it
.state
= MANUAL_IT_BLOCK
;
17198 case MANUAL_IT_BLOCK
:
17200 /* Check conditional suffixes. */
17201 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
17204 now_it
.mask
&= 0x1f;
17205 is_last
= (now_it
.mask
== 0x10);
17206 now_it
.insn_cond
= TRUE
;
17208 switch (inst
.it_insn_type
)
17210 case OUTSIDE_IT_INSN
:
17211 inst
.error
= BAD_NOT_IT
;
17214 case INSIDE_IT_INSN
:
17215 if (cond
!= inst
.cond
)
17217 inst
.error
= BAD_IT_COND
;
17222 case INSIDE_IT_LAST_INSN
:
17223 case IF_INSIDE_IT_LAST_INSN
:
17224 if (cond
!= inst
.cond
)
17226 inst
.error
= BAD_IT_COND
;
17231 inst
.error
= BAD_BRANCH
;
17236 case NEUTRAL_IT_INSN
:
17237 /* The BKPT instruction is unconditional even in an IT block. */
17241 inst
.error
= BAD_IT_IT
;
17251 struct depr_insn_mask
17253 unsigned long pattern
;
17254 unsigned long mask
;
17255 const char* description
;
17258 /* List of 16-bit instruction patterns deprecated in an IT block in
17260 static const struct depr_insn_mask depr_it_insns
[] = {
17261 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
17262 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
17263 { 0xa000, 0xb800, N_("ADR") },
17264 { 0x4800, 0xf800, N_("Literal loads") },
17265 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
17266 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
17271 it_fsm_post_encode (void)
17275 if (!now_it
.state_handled
)
17276 handle_it_state ();
17278 if (now_it
.insn_cond
17279 && !now_it
.warn_deprecated
17280 && warn_on_deprecated
17281 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
17283 if (inst
.instruction
>= 0x10000)
17285 as_warn (_("IT blocks containing 32-bit Thumb instructions are "
17286 "deprecated in ARMv8"));
17287 now_it
.warn_deprecated
= TRUE
;
17291 const struct depr_insn_mask
*p
= depr_it_insns
;
17293 while (p
->mask
!= 0)
17295 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
17297 as_warn (_("IT blocks containing 16-bit Thumb instructions "
17298 "of the following class are deprecated in ARMv8: "
17299 "%s"), p
->description
);
17300 now_it
.warn_deprecated
= TRUE
;
17308 if (now_it
.block_length
> 1)
17310 as_warn (_("IT blocks containing more than one conditional "
17311 "instruction are deprecated in ARMv8"));
17312 now_it
.warn_deprecated
= TRUE
;
17316 is_last
= (now_it
.mask
== 0x10);
17319 now_it
.state
= OUTSIDE_IT_BLOCK
;
17325 force_automatic_it_block_close (void)
17327 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
17329 close_automatic_it_block ();
17330 now_it
.state
= OUTSIDE_IT_BLOCK
;
17338 if (!now_it
.state_handled
)
17339 handle_it_state ();
17341 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
17345 md_assemble (char *str
)
17348 const struct asm_opcode
* opcode
;
17350 /* Align the previous label if needed. */
17351 if (last_label_seen
!= NULL
)
17353 symbol_set_frag (last_label_seen
, frag_now
);
17354 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
17355 S_SET_SEGMENT (last_label_seen
, now_seg
);
17358 memset (&inst
, '\0', sizeof (inst
));
17359 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
17361 opcode
= opcode_lookup (&p
);
17364 /* It wasn't an instruction, but it might be a register alias of
17365 the form alias .req reg, or a Neon .dn/.qn directive. */
17366 if (! create_register_alias (str
, p
)
17367 && ! create_neon_reg_alias (str
, p
))
17368 as_bad (_("bad instruction `%s'"), str
);
17373 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
17374 as_warn (_("s suffix on comparison instruction is deprecated"));
17376 /* The value which unconditional instructions should have in place of the
17377 condition field. */
17378 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
17382 arm_feature_set variant
;
17384 variant
= cpu_variant
;
17385 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
17386 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
17387 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
17388 /* Check that this instruction is supported for this CPU. */
17389 if (!opcode
->tvariant
17390 || (thumb_mode
== 1
17391 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
17393 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
17396 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
17397 && opcode
->tencode
!= do_t_branch
)
17399 as_bad (_("Thumb does not support conditional execution"));
17403 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
17405 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
17406 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
17407 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
17409 /* Two things are addressed here.
17410 1) Implicit require narrow instructions on Thumb-1.
17411 This avoids relaxation accidentally introducing Thumb-2
17413 2) Reject wide instructions in non Thumb-2 cores. */
17414 if (inst
.size_req
== 0)
17416 else if (inst
.size_req
== 4)
17418 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
17424 inst
.instruction
= opcode
->tvalue
;
17426 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
17428 /* Prepare the it_insn_type for those encodings that don't set
17430 it_fsm_pre_encode ();
17432 opcode
->tencode ();
17434 it_fsm_post_encode ();
17437 if (!(inst
.error
|| inst
.relax
))
17439 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
17440 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
17441 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
17443 as_bad (_("cannot honor width suffix -- `%s'"), str
);
17448 /* Something has gone badly wrong if we try to relax a fixed size
17450 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
17452 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17453 *opcode
->tvariant
);
17454 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
17455 set those bits when Thumb-2 32-bit instructions are seen. ie.
17456 anything other than bl/blx and v6-M instructions.
17457 This is overly pessimistic for relaxable instructions. */
17458 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
17460 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
17461 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
17462 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
17465 check_neon_suffixes
;
17469 mapping_state (MAP_THUMB
);
17472 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
17476 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
17477 is_bx
= (opcode
->aencode
== do_bx
);
17479 /* Check that this instruction is supported for this CPU. */
17480 if (!(is_bx
&& fix_v4bx
)
17481 && !(opcode
->avariant
&&
17482 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
17484 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
17489 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
17493 inst
.instruction
= opcode
->avalue
;
17494 if (opcode
->tag
== OT_unconditionalF
)
17495 inst
.instruction
|= 0xF << 28;
17497 inst
.instruction
|= inst
.cond
<< 28;
17498 inst
.size
= INSN_SIZE
;
17499 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
17501 it_fsm_pre_encode ();
17502 opcode
->aencode ();
17503 it_fsm_post_encode ();
17505 /* Arm mode bx is marked as both v4T and v5 because it's still required
17506 on a hypothetical non-thumb v5 core. */
17508 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
17510 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
17511 *opcode
->avariant
);
17513 check_neon_suffixes
;
17517 mapping_state (MAP_ARM
);
17522 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
17530 check_it_blocks_finished (void)
17535 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
17536 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
17537 == MANUAL_IT_BLOCK
)
17539 as_warn (_("section '%s' finished with an open IT block."),
17543 if (now_it
.state
== MANUAL_IT_BLOCK
)
17544 as_warn (_("file finished with an open IT block."));
17548 /* Various frobbings of labels and their addresses. */
17551 arm_start_line_hook (void)
17553 last_label_seen
= NULL
;
17557 arm_frob_label (symbolS
* sym
)
17559 last_label_seen
= sym
;
17561 ARM_SET_THUMB (sym
, thumb_mode
);
17563 #if defined OBJ_COFF || defined OBJ_ELF
17564 ARM_SET_INTERWORK (sym
, support_interwork
);
17567 force_automatic_it_block_close ();
17569 /* Note - do not allow local symbols (.Lxxx) to be labelled
17570 as Thumb functions. This is because these labels, whilst
17571 they exist inside Thumb code, are not the entry points for
17572 possible ARM->Thumb calls. Also, these labels can be used
17573 as part of a computed goto or switch statement. eg gcc
17574 can generate code that looks like this:
17576 ldr r2, [pc, .Laaa]
17586 The first instruction loads the address of the jump table.
17587 The second instruction converts a table index into a byte offset.
17588 The third instruction gets the jump address out of the table.
17589 The fourth instruction performs the jump.
17591 If the address stored at .Laaa is that of a symbol which has the
17592 Thumb_Func bit set, then the linker will arrange for this address
17593 to have the bottom bit set, which in turn would mean that the
17594 address computation performed by the third instruction would end
17595 up with the bottom bit set. Since the ARM is capable of unaligned
17596 word loads, the instruction would then load the incorrect address
17597 out of the jump table, and chaos would ensue. */
17598 if (label_is_thumb_function_name
17599 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
17600 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
17602 /* When the address of a Thumb function is taken the bottom
17603 bit of that address should be set. This will allow
17604 interworking between Arm and Thumb functions to work
17607 THUMB_SET_FUNC (sym
, 1);
17609 label_is_thumb_function_name
= FALSE
;
17612 dwarf2_emit_label (sym
);
17616 arm_data_in_code (void)
17618 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
17620 *input_line_pointer
= '/';
17621 input_line_pointer
+= 5;
17622 *input_line_pointer
= 0;
17630 arm_canonicalize_symbol_name (char * name
)
17634 if (thumb_mode
&& (len
= strlen (name
)) > 5
17635 && streq (name
+ len
- 5, "/data"))
17636 *(name
+ len
- 5) = 0;
17641 /* Table of all register names defined by default. The user can
17642 define additional names with .req. Note that all register names
17643 should appear in both upper and lowercase variants. Some registers
17644 also have mixed-case names. */
17646 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
17647 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
17648 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
17649 #define REGSET(p,t) \
17650 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
17651 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
17652 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
17653 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
17654 #define REGSETH(p,t) \
17655 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
17656 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
17657 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
17658 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
17659 #define REGSET2(p,t) \
17660 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
17661 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
17662 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
17663 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
17664 #define SPLRBANK(base,bank,t) \
17665 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
17666 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
17667 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
17668 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
17669 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
17670 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
17672 static const struct reg_entry reg_names
[] =
17674 /* ARM integer registers. */
17675 REGSET(r
, RN
), REGSET(R
, RN
),
17677 /* ATPCS synonyms. */
17678 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
17679 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
17680 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
17682 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
17683 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
17684 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
17686 /* Well-known aliases. */
17687 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
17688 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
17690 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
17691 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
17693 /* Coprocessor numbers. */
17694 REGSET(p
, CP
), REGSET(P
, CP
),
17696 /* Coprocessor register numbers. The "cr" variants are for backward
17698 REGSET(c
, CN
), REGSET(C
, CN
),
17699 REGSET(cr
, CN
), REGSET(CR
, CN
),
17701 /* ARM banked registers. */
17702 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
17703 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
17704 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
17705 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
17706 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
17707 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
17708 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
17710 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
17711 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
17712 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
17713 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
17714 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
17715 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
17716 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
17717 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
17719 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
17720 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
17721 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
17722 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
17723 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
17724 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
17725 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
17726 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17727 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
17729 /* FPA registers. */
17730 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
17731 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
17733 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
17734 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
17736 /* VFP SP registers. */
17737 REGSET(s
,VFS
), REGSET(S
,VFS
),
17738 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
17740 /* VFP DP Registers. */
17741 REGSET(d
,VFD
), REGSET(D
,VFD
),
17742 /* Extra Neon DP registers. */
17743 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
17745 /* Neon QP registers. */
17746 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
17748 /* VFP control registers. */
17749 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
17750 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
17751 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
17752 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
17753 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
17754 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
17756 /* Maverick DSP coprocessor registers. */
17757 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
17758 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
17760 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
17761 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
17762 REGDEF(dspsc
,0,DSPSC
),
17764 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
17765 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
17766 REGDEF(DSPSC
,0,DSPSC
),
17768 /* iWMMXt data registers - p0, c0-15. */
17769 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
17771 /* iWMMXt control registers - p1, c0-3. */
17772 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
17773 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
17774 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
17775 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
17777 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
17778 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
17779 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
17780 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
17781 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
17783 /* XScale accumulator registers. */
17784 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
17790 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
17791 within psr_required_here. */
17792 static const struct asm_psr psrs
[] =
17794 /* Backward compatibility notation. Note that "all" is no longer
17795 truly all possible PSR bits. */
17796 {"all", PSR_c
| PSR_f
},
17800 /* Individual flags. */
17806 /* Combinations of flags. */
17807 {"fs", PSR_f
| PSR_s
},
17808 {"fx", PSR_f
| PSR_x
},
17809 {"fc", PSR_f
| PSR_c
},
17810 {"sf", PSR_s
| PSR_f
},
17811 {"sx", PSR_s
| PSR_x
},
17812 {"sc", PSR_s
| PSR_c
},
17813 {"xf", PSR_x
| PSR_f
},
17814 {"xs", PSR_x
| PSR_s
},
17815 {"xc", PSR_x
| PSR_c
},
17816 {"cf", PSR_c
| PSR_f
},
17817 {"cs", PSR_c
| PSR_s
},
17818 {"cx", PSR_c
| PSR_x
},
17819 {"fsx", PSR_f
| PSR_s
| PSR_x
},
17820 {"fsc", PSR_f
| PSR_s
| PSR_c
},
17821 {"fxs", PSR_f
| PSR_x
| PSR_s
},
17822 {"fxc", PSR_f
| PSR_x
| PSR_c
},
17823 {"fcs", PSR_f
| PSR_c
| PSR_s
},
17824 {"fcx", PSR_f
| PSR_c
| PSR_x
},
17825 {"sfx", PSR_s
| PSR_f
| PSR_x
},
17826 {"sfc", PSR_s
| PSR_f
| PSR_c
},
17827 {"sxf", PSR_s
| PSR_x
| PSR_f
},
17828 {"sxc", PSR_s
| PSR_x
| PSR_c
},
17829 {"scf", PSR_s
| PSR_c
| PSR_f
},
17830 {"scx", PSR_s
| PSR_c
| PSR_x
},
17831 {"xfs", PSR_x
| PSR_f
| PSR_s
},
17832 {"xfc", PSR_x
| PSR_f
| PSR_c
},
17833 {"xsf", PSR_x
| PSR_s
| PSR_f
},
17834 {"xsc", PSR_x
| PSR_s
| PSR_c
},
17835 {"xcf", PSR_x
| PSR_c
| PSR_f
},
17836 {"xcs", PSR_x
| PSR_c
| PSR_s
},
17837 {"cfs", PSR_c
| PSR_f
| PSR_s
},
17838 {"cfx", PSR_c
| PSR_f
| PSR_x
},
17839 {"csf", PSR_c
| PSR_s
| PSR_f
},
17840 {"csx", PSR_c
| PSR_s
| PSR_x
},
17841 {"cxf", PSR_c
| PSR_x
| PSR_f
},
17842 {"cxs", PSR_c
| PSR_x
| PSR_s
},
17843 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
17844 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
17845 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
17846 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
17847 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
17848 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
17849 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
17850 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
17851 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
17852 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
17853 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
17854 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
17855 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
17856 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
17857 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
17858 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
17859 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
17860 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
17861 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
17862 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
17863 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
17864 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
17865 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
17866 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
17869 /* Table of V7M psr names. */
17870 static const struct asm_psr v7m_psrs
[] =
17872 {"apsr", 0 }, {"APSR", 0 },
17873 {"iapsr", 1 }, {"IAPSR", 1 },
17874 {"eapsr", 2 }, {"EAPSR", 2 },
17875 {"psr", 3 }, {"PSR", 3 },
17876 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
17877 {"ipsr", 5 }, {"IPSR", 5 },
17878 {"epsr", 6 }, {"EPSR", 6 },
17879 {"iepsr", 7 }, {"IEPSR", 7 },
17880 {"msp", 8 }, {"MSP", 8 },
17881 {"psp", 9 }, {"PSP", 9 },
17882 {"primask", 16}, {"PRIMASK", 16},
17883 {"basepri", 17}, {"BASEPRI", 17},
17884 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
17885 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
17886 {"faultmask", 19}, {"FAULTMASK", 19},
17887 {"control", 20}, {"CONTROL", 20}
17890 /* Table of all shift-in-operand names. */
17891 static const struct asm_shift_name shift_names
[] =
17893 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
17894 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
17895 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
17896 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
17897 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
17898 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
17901 /* Table of all explicit relocation names. */
17903 static struct reloc_entry reloc_names
[] =
17905 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
17906 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
17907 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
17908 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
17909 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
17910 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
17911 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
17912 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
17913 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
17914 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
17915 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
17916 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
17917 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
17918 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
17919 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
17920 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
17921 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
17922 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
17926 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
17927 static const struct asm_cond conds
[] =
17931 {"cs", 0x2}, {"hs", 0x2},
17932 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
17946 #define UL_BARRIER(L,U,CODE,FEAT) \
17947 { L, CODE, ARM_FEATURE (FEAT, 0) }, \
17948 { U, CODE, ARM_FEATURE (FEAT, 0) }
17950 static struct asm_barrier_opt barrier_opt_names
[] =
17952 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
17953 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
17954 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
17955 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
17956 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
17957 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
17958 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
17959 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
17960 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
17961 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
17962 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
17963 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
17964 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
17965 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
17966 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
17967 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
17972 /* Table of ARM-format instructions. */
17974 /* Macros for gluing together operand strings. N.B. In all cases
17975 other than OPS0, the trailing OP_stop comes from default
17976 zero-initialization of the unspecified elements of the array. */
17977 #define OPS0() { OP_stop, }
17978 #define OPS1(a) { OP_##a, }
17979 #define OPS2(a,b) { OP_##a,OP_##b, }
17980 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
17981 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
17982 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
17983 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
17985 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
17986 This is useful when mixing operands for ARM and THUMB, i.e. using the
17987 MIX_ARM_THUMB_OPERANDS macro.
17988 In order to use these macros, prefix the number of operands with _
17990 #define OPS_1(a) { a, }
17991 #define OPS_2(a,b) { a,b, }
17992 #define OPS_3(a,b,c) { a,b,c, }
17993 #define OPS_4(a,b,c,d) { a,b,c,d, }
17994 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
17995 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
17997 /* These macros abstract out the exact format of the mnemonic table and
17998 save some repeated characters. */
18000 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
18001 #define TxCE(mnem, op, top, nops, ops, ae, te) \
18002 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
18003 THUMB_VARIANT, do_##ae, do_##te }
18005 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
18006 a T_MNEM_xyz enumerator. */
18007 #define TCE(mnem, aop, top, nops, ops, ae, te) \
18008 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
18009 #define tCE(mnem, aop, top, nops, ops, ae, te) \
18010 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18012 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
18013 infix after the third character. */
18014 #define TxC3(mnem, op, top, nops, ops, ae, te) \
18015 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
18016 THUMB_VARIANT, do_##ae, do_##te }
18017 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
18018 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
18019 THUMB_VARIANT, do_##ae, do_##te }
18020 #define TC3(mnem, aop, top, nops, ops, ae, te) \
18021 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
18022 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
18023 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
18024 #define tC3(mnem, aop, top, nops, ops, ae, te) \
18025 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18026 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
18027 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
18029 /* Mnemonic that cannot be conditionalized. The ARM condition-code
18030 field is still 0xE. Many of the Thumb variants can be executed
18031 conditionally, so this is checked separately. */
18032 #define TUE(mnem, op, top, nops, ops, ae, te) \
18033 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18034 THUMB_VARIANT, do_##ae, do_##te }
18036 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
18037 Used by mnemonics that have very minimal differences in the encoding for
18038 ARM and Thumb variants and can be handled in a common function. */
18039 #define TUEc(mnem, op, top, nops, ops, en) \
18040 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
18041 THUMB_VARIANT, do_##en, do_##en }
18043 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
18044 condition code field. */
18045 #define TUF(mnem, op, top, nops, ops, ae, te) \
18046 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
18047 THUMB_VARIANT, do_##ae, do_##te }
18049 /* ARM-only variants of all the above. */
18050 #define CE(mnem, op, nops, ops, ae) \
18051 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18053 #define C3(mnem, op, nops, ops, ae) \
18054 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18056 /* Legacy mnemonics that always have conditional infix after the third
18058 #define CL(mnem, op, nops, ops, ae) \
18059 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18060 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18062 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
18063 #define cCE(mnem, op, nops, ops, ae) \
18064 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18066 /* Legacy coprocessor instructions where conditional infix and conditional
18067 suffix are ambiguous. For consistency this includes all FPA instructions,
18068 not just the potentially ambiguous ones. */
18069 #define cCL(mnem, op, nops, ops, ae) \
18070 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
18071 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18073 /* Coprocessor, takes either a suffix or a position-3 infix
18074 (for an FPA corner case). */
18075 #define C3E(mnem, op, nops, ops, ae) \
18076 { mnem, OPS##nops ops, OT_csuf_or_in3, \
18077 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
18079 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
18080 { m1 #m2 m3, OPS##nops ops, \
18081 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
18082 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
18084 #define CM(m1, m2, op, nops, ops, ae) \
18085 xCM_ (m1, , m2, op, nops, ops, ae), \
18086 xCM_ (m1, eq, m2, op, nops, ops, ae), \
18087 xCM_ (m1, ne, m2, op, nops, ops, ae), \
18088 xCM_ (m1, cs, m2, op, nops, ops, ae), \
18089 xCM_ (m1, hs, m2, op, nops, ops, ae), \
18090 xCM_ (m1, cc, m2, op, nops, ops, ae), \
18091 xCM_ (m1, ul, m2, op, nops, ops, ae), \
18092 xCM_ (m1, lo, m2, op, nops, ops, ae), \
18093 xCM_ (m1, mi, m2, op, nops, ops, ae), \
18094 xCM_ (m1, pl, m2, op, nops, ops, ae), \
18095 xCM_ (m1, vs, m2, op, nops, ops, ae), \
18096 xCM_ (m1, vc, m2, op, nops, ops, ae), \
18097 xCM_ (m1, hi, m2, op, nops, ops, ae), \
18098 xCM_ (m1, ls, m2, op, nops, ops, ae), \
18099 xCM_ (m1, ge, m2, op, nops, ops, ae), \
18100 xCM_ (m1, lt, m2, op, nops, ops, ae), \
18101 xCM_ (m1, gt, m2, op, nops, ops, ae), \
18102 xCM_ (m1, le, m2, op, nops, ops, ae), \
18103 xCM_ (m1, al, m2, op, nops, ops, ae)
18105 #define UE(mnem, op, nops, ops, ae) \
18106 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18108 #define UF(mnem, op, nops, ops, ae) \
18109 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
18111 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
18112 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
18113 use the same encoding function for each. */
18114 #define NUF(mnem, op, nops, ops, enc) \
18115 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
18116 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18118 /* Neon data processing, version which indirects through neon_enc_tab for
18119 the various overloaded versions of opcodes. */
18120 #define nUF(mnem, op, nops, ops, enc) \
18121 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
18122 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18124 /* Neon insn with conditional suffix for the ARM version, non-overloaded
18126 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
18127 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
18128 THUMB_VARIANT, do_##enc, do_##enc }
18130 #define NCE(mnem, op, nops, ops, enc) \
18131 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18133 #define NCEF(mnem, op, nops, ops, enc) \
18134 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18136 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
18137 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
18138 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
18139 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
18141 #define nCE(mnem, op, nops, ops, enc) \
18142 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
18144 #define nCEF(mnem, op, nops, ops, enc) \
18145 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
18149 static const struct asm_opcode insns
[] =
18151 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
18152 #define THUMB_VARIANT & arm_ext_v4t
18153 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18154 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18155 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18156 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18157 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18158 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
18159 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18160 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
18161 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18162 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18163 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18164 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18165 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18166 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
18167 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18168 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
18170 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
18171 for setting PSR flag bits. They are obsolete in V6 and do not
18172 have Thumb equivalents. */
18173 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18174 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18175 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
18176 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18177 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
18178 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
18179 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18180 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18181 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
18183 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18184 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
18185 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18186 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
18188 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
18189 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18190 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
18192 OP_ADDRGLDR
),ldst
, t_ldst
),
18193 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
18195 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18196 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18197 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18198 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18199 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18200 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18202 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18203 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
18204 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
18205 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
18208 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
18209 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
18210 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
18211 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
18213 /* Thumb-compatibility pseudo ops. */
18214 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18215 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18216 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18217 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18218 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18219 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18220 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18221 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
18222 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
18223 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
18224 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
18225 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
18227 /* These may simplify to neg. */
18228 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18229 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
18231 #undef THUMB_VARIANT
18232 #define THUMB_VARIANT & arm_ext_v6
18234 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
18236 /* V1 instructions with no Thumb analogue prior to V6T2. */
18237 #undef THUMB_VARIANT
18238 #define THUMB_VARIANT & arm_ext_v6t2
18240 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18241 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
18242 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
18244 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18245 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18246 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
18247 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
18249 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18250 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18252 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18253 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
18255 /* V1 instructions with no Thumb analogue at all. */
18256 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
18257 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
18259 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18260 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
18261 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18262 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
18263 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18264 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
18265 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18266 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
18269 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
18270 #undef THUMB_VARIANT
18271 #define THUMB_VARIANT & arm_ext_v4t
18273 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18274 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
18276 #undef THUMB_VARIANT
18277 #define THUMB_VARIANT & arm_ext_v6t2
18279 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18280 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
18282 /* Generic coprocessor instructions. */
18283 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18284 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18285 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18286 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18287 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18288 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18289 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18292 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
18294 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18295 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
18298 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
18299 #undef THUMB_VARIANT
18300 #define THUMB_VARIANT & arm_ext_msr
18302 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
18303 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
18306 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
18307 #undef THUMB_VARIANT
18308 #define THUMB_VARIANT & arm_ext_v6t2
18310 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18311 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18312 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18313 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18314 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18315 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18316 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
18317 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
18320 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
18321 #undef THUMB_VARIANT
18322 #define THUMB_VARIANT & arm_ext_v4t
18324 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18325 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18326 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18327 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18328 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18329 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
18332 #define ARM_VARIANT & arm_ext_v4t_5
18334 /* ARM Architecture 4T. */
18335 /* Note: bx (and blx) are required on V5, even if the processor does
18336 not support Thumb. */
18337 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
18340 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
18341 #undef THUMB_VARIANT
18342 #define THUMB_VARIANT & arm_ext_v5t
18344 /* Note: blx has 2 variants; the .value coded here is for
18345 BLX(2). Only this variant has conditional execution. */
18346 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
18347 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
18349 #undef THUMB_VARIANT
18350 #define THUMB_VARIANT & arm_ext_v6t2
18352 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
18353 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18354 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18355 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18356 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
18357 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
18358 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18359 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
18362 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
18363 #undef THUMB_VARIANT
18364 #define THUMB_VARIANT & arm_ext_v5exp
18366 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18367 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18368 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18369 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18371 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18372 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
18374 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18375 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18376 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18377 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
18379 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18380 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18381 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18382 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18384 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18385 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18387 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18388 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18389 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18390 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
18393 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
18394 #undef THUMB_VARIANT
18395 #define THUMB_VARIANT & arm_ext_v6t2
18397 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
18398 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
18400 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
18401 ADDRGLDRS
), ldrd
, t_ldstd
),
18403 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18404 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18407 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
18409 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
18412 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
18413 #undef THUMB_VARIANT
18414 #define THUMB_VARIANT & arm_ext_v6
18416 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18417 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
18418 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18419 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18420 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
18421 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18422 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18423 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18424 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18425 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
18427 #undef THUMB_VARIANT
18428 #define THUMB_VARIANT & arm_ext_v6t2
18430 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
18431 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18433 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18434 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
18436 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
18437 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
18439 /* ARM V6 not included in V7M. */
18440 #undef THUMB_VARIANT
18441 #define THUMB_VARIANT & arm_ext_v6_notm
18442 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18443 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18444 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
18445 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
18446 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18447 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
18448 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
18449 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
18450 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
18451 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18452 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18453 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
18454 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18455 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
18456 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
18457 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
18458 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18459 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
18461 /* ARM V6 not included in V7M (eg. integer SIMD). */
18462 #undef THUMB_VARIANT
18463 #define THUMB_VARIANT & arm_ext_v6_dsp
18464 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
18465 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
18466 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
18467 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18468 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18469 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18470 /* Old name for QASX. */
18471 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18472 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18473 /* Old name for QSAX. */
18474 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18475 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18476 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18477 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18478 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18479 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18480 /* Old name for SASX. */
18481 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18482 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18483 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18484 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18485 /* Old name for SHASX. */
18486 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18487 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18488 /* Old name for SHSAX. */
18489 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18490 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18491 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18492 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18493 /* Old name for SSAX. */
18494 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18495 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18496 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18497 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18498 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18499 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18500 /* Old name for UASX. */
18501 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18502 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18503 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18504 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18505 /* Old name for UHASX. */
18506 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18507 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18508 /* Old name for UHSAX. */
18509 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18510 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18511 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18512 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18513 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18514 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18515 /* Old name for UQASX. */
18516 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18517 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18518 /* Old name for UQSAX. */
18519 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18520 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18521 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18522 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18523 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18524 /* Old name for USAX. */
18525 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18526 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18527 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18528 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18529 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18530 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18531 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18532 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18533 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
18534 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
18535 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
18536 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18537 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18538 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18539 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18540 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18541 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18542 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18543 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
18544 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18545 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18546 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18547 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18548 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18549 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18550 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18551 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18552 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18553 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18554 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
18555 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
18556 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
18557 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
18558 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
18561 #define ARM_VARIANT & arm_ext_v6k
18562 #undef THUMB_VARIANT
18563 #define THUMB_VARIANT & arm_ext_v6k
18565 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
18566 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
18567 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
18568 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
18570 #undef THUMB_VARIANT
18571 #define THUMB_VARIANT & arm_ext_v6_notm
18572 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
18574 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
18575 RRnpcb
), strexd
, t_strexd
),
18577 #undef THUMB_VARIANT
18578 #define THUMB_VARIANT & arm_ext_v6t2
18579 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
18581 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
18583 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18585 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
18587 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
18590 #define ARM_VARIANT & arm_ext_sec
18591 #undef THUMB_VARIANT
18592 #define THUMB_VARIANT & arm_ext_sec
18594 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
18597 #define ARM_VARIANT & arm_ext_virt
18598 #undef THUMB_VARIANT
18599 #define THUMB_VARIANT & arm_ext_virt
18601 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
18602 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
18605 #define ARM_VARIANT & arm_ext_v6t2
18606 #undef THUMB_VARIANT
18607 #define THUMB_VARIANT & arm_ext_v6t2
18609 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
18610 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
18611 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18612 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
18614 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
18615 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18616 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
18617 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
18619 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18620 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18621 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18622 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
18624 /* Thumb-only instructions. */
18626 #define ARM_VARIANT NULL
18627 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
18628 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
18630 /* ARM does not really have an IT instruction, so always allow it.
18631 The opcode is copied from Thumb in order to allow warnings in
18632 -mimplicit-it=[never | arm] modes. */
18634 #define ARM_VARIANT & arm_ext_v1
18636 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
18637 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
18638 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
18639 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
18640 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
18641 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
18642 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
18643 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
18644 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
18645 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
18646 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
18647 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
18648 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
18649 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
18650 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
18651 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
18652 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18653 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
18655 /* Thumb2 only instructions. */
18657 #define ARM_VARIANT NULL
18659 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18660 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
18661 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18662 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
18663 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
18664 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
18666 /* Hardware division instructions. */
18668 #define ARM_VARIANT & arm_ext_adiv
18669 #undef THUMB_VARIANT
18670 #define THUMB_VARIANT & arm_ext_div
18672 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18673 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
18675 /* ARM V6M/V7 instructions. */
18677 #define ARM_VARIANT & arm_ext_barrier
18678 #undef THUMB_VARIANT
18679 #define THUMB_VARIANT & arm_ext_barrier
18681 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
18682 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
18683 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
18685 /* ARM V7 instructions. */
18687 #define ARM_VARIANT & arm_ext_v7
18688 #undef THUMB_VARIANT
18689 #define THUMB_VARIANT & arm_ext_v7
18691 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
18692 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
18695 #define ARM_VARIANT & arm_ext_mp
18696 #undef THUMB_VARIANT
18697 #define THUMB_VARIANT & arm_ext_mp
18699 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
18701 /* AArchv8 instructions. */
18703 #define ARM_VARIANT & arm_ext_v8
18704 #undef THUMB_VARIANT
18705 #define THUMB_VARIANT & arm_ext_v8
18707 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
18708 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
18709 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18710 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
18712 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
18713 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18714 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18716 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
18718 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18720 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
18722 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18723 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18724 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
18725 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18726 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18727 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
18729 /* ARMv8 T32 only. */
18731 #define ARM_VARIANT NULL
18732 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
18733 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
18734 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
18736 /* FP for ARMv8. */
18738 #define ARM_VARIANT & fpu_vfp_ext_armv8
18739 #undef THUMB_VARIANT
18740 #define THUMB_VARIANT & fpu_vfp_ext_armv8
18742 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18743 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18744 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18745 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
18746 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
18747 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
18748 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
18749 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
18750 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
18751 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
18752 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
18753 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
18754 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
18755 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
18756 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
18757 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
18758 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
18760 /* Crypto v1 extensions. */
18762 #define ARM_VARIANT & fpu_crypto_ext_armv8
18763 #undef THUMB_VARIANT
18764 #define THUMB_VARIANT & fpu_crypto_ext_armv8
18766 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
18767 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
18768 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
18769 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
18770 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
18771 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
18772 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
18773 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
18774 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
18775 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
18776 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
18777 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
18778 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
18779 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
18782 #define ARM_VARIANT & crc_ext_armv8
18783 #undef THUMB_VARIANT
18784 #define THUMB_VARIANT & crc_ext_armv8
18785 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
18786 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
18787 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
18788 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
18789 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
18790 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
18793 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
18794 #undef THUMB_VARIANT
18795 #define THUMB_VARIANT NULL
18797 cCE("wfs", e200110
, 1, (RR
), rd
),
18798 cCE("rfs", e300110
, 1, (RR
), rd
),
18799 cCE("wfc", e400110
, 1, (RR
), rd
),
18800 cCE("rfc", e500110
, 1, (RR
), rd
),
18802 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18803 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18804 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18805 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18807 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18808 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18809 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18810 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
18812 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
18813 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
18814 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
18815 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
18816 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
18817 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
18818 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
18819 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
18820 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
18821 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
18822 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
18823 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
18825 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
18826 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
18827 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
18828 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
18829 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
18830 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
18831 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
18832 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
18833 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
18834 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
18835 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
18836 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
18838 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
18839 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
18840 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
18841 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
18842 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
18843 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
18844 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
18845 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
18846 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
18847 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
18848 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
18849 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
18851 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
18852 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
18853 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
18854 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
18855 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
18856 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
18857 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
18858 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
18859 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
18860 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
18861 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
18862 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
18864 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
18865 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
18866 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
18867 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
18868 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
18869 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
18870 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
18871 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
18872 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
18873 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
18874 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
18875 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
18877 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
18878 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
18879 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
18880 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
18881 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
18882 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
18883 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
18884 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
18885 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
18886 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
18887 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
18888 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
18890 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
18891 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
18892 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
18893 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
18894 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
18895 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
18896 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
18897 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
18898 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
18899 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
18900 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
18901 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
18903 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
18904 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
18905 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
18906 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
18907 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
18908 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
18909 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
18910 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
18911 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
18912 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
18913 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
18914 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
18916 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
18917 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
18918 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
18919 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
18920 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
18921 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
18922 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
18923 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
18924 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
18925 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
18926 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
18927 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
18929 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
18930 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
18931 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
18932 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
18933 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
18934 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
18935 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
18936 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
18937 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
18938 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
18939 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
18940 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
18942 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
18943 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
18944 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
18945 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
18946 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
18947 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
18948 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
18949 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
18950 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
18951 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
18952 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
18953 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
18955 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
18956 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
18957 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
18958 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
18959 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
18960 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
18961 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
18962 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
18963 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
18964 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
18965 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
18966 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
18968 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
18969 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
18970 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
18971 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
18972 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
18973 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
18974 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
18975 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
18976 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
18977 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
18978 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
18979 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
18981 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
18982 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
18983 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
18984 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
18985 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
18986 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
18987 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
18988 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
18989 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
18990 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
18991 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
18992 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
18994 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
18995 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
18996 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
18997 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
18998 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
18999 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
19000 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
19001 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
19002 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
19003 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
19004 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
19005 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
19007 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
19008 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
19009 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
19010 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
19011 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
19012 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
19013 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
19014 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
19015 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
19016 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
19017 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
19018 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
19020 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19021 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19022 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19023 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19024 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19025 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19026 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19027 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19028 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19029 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19030 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19031 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19033 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19034 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19035 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19036 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19037 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19038 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19039 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19040 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19041 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19042 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19043 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19044 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19046 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19047 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19048 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19049 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19050 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19051 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19052 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19053 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19054 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19055 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19056 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19057 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19059 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19060 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19061 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19062 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19063 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19064 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19065 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19066 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19067 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19068 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19069 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19070 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19072 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19073 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19074 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19075 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19076 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19077 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19078 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19079 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19080 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19081 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19082 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19083 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19085 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19086 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19087 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19088 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19089 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19090 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19091 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19092 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19093 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19094 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19095 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19096 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19098 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19099 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19100 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19101 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19102 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19103 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19104 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19105 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19106 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19107 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19108 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19109 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19111 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19112 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19113 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19114 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19115 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19116 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19117 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19118 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19119 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19120 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19121 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19122 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19124 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19125 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19126 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19127 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19128 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19129 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19130 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19131 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19132 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19133 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19134 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19135 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19137 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19138 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19139 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19140 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19141 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19142 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19143 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19144 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19145 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19146 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19147 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19148 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19150 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19151 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19152 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19153 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19154 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19155 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19156 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19157 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19158 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19159 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19160 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19161 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19163 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19164 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19165 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19166 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19167 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19168 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19169 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19170 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19171 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19172 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19173 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19174 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19176 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19177 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19178 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19179 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19180 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19181 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19182 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19183 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19184 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19185 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19186 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19187 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
19189 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19190 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19191 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19192 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
19194 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
19195 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
19196 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
19197 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
19198 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
19199 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
19200 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
19201 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
19202 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
19203 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
19204 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
19205 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
19207 /* The implementation of the FIX instruction is broken on some
19208 assemblers, in that it accepts a precision specifier as well as a
19209 rounding specifier, despite the fact that this is meaningless.
19210 To be more compatible, we accept it as well, though of course it
19211 does not set any bits. */
19212 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
19213 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
19214 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
19215 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
19216 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
19217 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
19218 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
19219 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
19220 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
19221 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
19222 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
19223 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
19224 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
19226 /* Instructions that were new with the real FPA, call them V2. */
19228 #define ARM_VARIANT & fpu_fpa_ext_v2
19230 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19231 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19232 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19233 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19234 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19235 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
19238 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
19240 /* Moves and type conversions. */
19241 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19242 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
19243 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
19244 cCE("fmstat", ef1fa10
, 0, (), noargs
),
19245 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
19246 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
19247 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19248 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19249 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19250 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19251 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19252 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19253 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
19254 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
19256 /* Memory operations. */
19257 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19258 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
19259 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19260 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19261 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19262 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19263 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19264 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19265 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19266 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19267 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19268 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
19269 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19270 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
19271 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19272 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
19273 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19274 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
19276 /* Monadic operations. */
19277 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19278 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19279 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19281 /* Dyadic operations. */
19282 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19283 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19284 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19285 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19286 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19287 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19288 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19289 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19290 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19293 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19294 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
19295 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
19296 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
19298 /* Double precision load/store are still present on single precision
19299 implementations. */
19300 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19301 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
19302 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19303 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19304 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19305 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19306 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19307 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
19308 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19309 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
19312 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
19314 /* Moves and type conversions. */
19315 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19316 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19317 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19318 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19319 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
19320 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19321 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
19322 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19323 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
19324 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19325 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19326 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19327 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
19329 /* Monadic operations. */
19330 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19331 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19332 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19334 /* Dyadic operations. */
19335 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19336 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19337 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19338 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19339 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19340 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19341 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19342 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19343 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19346 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19347 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
19348 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
19349 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
19352 #define ARM_VARIANT & fpu_vfp_ext_v2
19354 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
19355 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
19356 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
19357 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
19359 /* Instructions which may belong to either the Neon or VFP instruction sets.
19360 Individual encoder functions perform additional architecture checks. */
19362 #define ARM_VARIANT & fpu_vfp_ext_v1xd
19363 #undef THUMB_VARIANT
19364 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
19366 /* These mnemonics are unique to VFP. */
19367 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
19368 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
19369 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19370 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19371 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19372 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
19373 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
19374 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
19375 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
19376 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
19378 /* Mnemonics shared by Neon and VFP. */
19379 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
19380 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19381 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
19383 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19384 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
19386 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19387 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
19389 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19390 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19391 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19392 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19393 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19394 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
19395 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19396 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
19398 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
19399 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
19400 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
19401 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
19404 /* NOTE: All VMOV encoding is special-cased! */
19405 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
19406 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
19408 #undef THUMB_VARIANT
19409 #define THUMB_VARIANT & fpu_neon_ext_v1
19411 #define ARM_VARIANT & fpu_neon_ext_v1
19413 /* Data processing with three registers of the same length. */
19414 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
19415 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
19416 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
19417 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19418 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19419 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19420 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19421 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
19422 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
19423 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
19424 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19425 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19426 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
19427 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
19428 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19429 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19430 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
19431 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
19432 /* If not immediate, fall back to neon_dyadic_i64_su.
19433 shl_imm should accept I8 I16 I32 I64,
19434 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
19435 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
19436 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
19437 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
19438 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
19439 /* Logic ops, types optional & ignored. */
19440 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19441 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19442 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19443 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19444 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19445 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19446 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
19447 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
19448 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
19449 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
19450 /* Bitfield ops, untyped. */
19451 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19452 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19453 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19454 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19455 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
19456 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
19457 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
19458 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19459 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19460 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19461 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19462 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
19463 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
19464 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
19465 back to neon_dyadic_if_su. */
19466 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19467 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19468 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
19469 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
19470 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19471 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19472 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
19473 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
19474 /* Comparison. Type I8 I16 I32 F32. */
19475 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
19476 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
19477 /* As above, D registers only. */
19478 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19479 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
19480 /* Int and float variants, signedness unimportant. */
19481 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19482 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
19483 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
19484 /* Add/sub take types I8 I16 I32 I64 F32. */
19485 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19486 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
19487 /* vtst takes sizes 8, 16, 32. */
19488 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
19489 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
19490 /* VMUL takes I8 I16 I32 F32 P8. */
19491 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
19492 /* VQD{R}MULH takes S16 S32. */
19493 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19494 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19495 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
19496 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
19497 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19498 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19499 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
19500 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
19501 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19502 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19503 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
19504 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
19505 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19506 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19507 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
19508 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
19510 /* Two address, int/float. Types S8 S16 S32 F32. */
19511 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19512 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
19514 /* Data processing with two registers and a shift amount. */
19515 /* Right shifts, and variants with rounding.
19516 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
19517 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19518 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19519 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
19520 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
19521 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19522 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19523 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
19524 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
19525 /* Shift and insert. Sizes accepted 8 16 32 64. */
19526 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
19527 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
19528 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
19529 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
19530 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
19531 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
19532 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
19533 /* Right shift immediate, saturating & narrowing, with rounding variants.
19534 Types accepted S16 S32 S64 U16 U32 U64. */
19535 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19536 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
19537 /* As above, unsigned. Types accepted S16 S32 S64. */
19538 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19539 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
19540 /* Right shift narrowing. Types accepted I16 I32 I64. */
19541 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19542 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
19543 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
19544 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
19545 /* CVT with optional immediate for fixed-point variant. */
19546 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
19548 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
19549 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
19551 /* Data processing, three registers of different lengths. */
19552 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
19553 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
19554 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19555 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19556 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
19557 /* If not scalar, fall back to neon_dyadic_long.
19558 Vector types as above, scalar types S16 S32 U16 U32. */
19559 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19560 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
19561 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
19562 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19563 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
19564 /* Dyadic, narrowing insns. Types I16 I32 I64. */
19565 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19566 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19567 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19568 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
19569 /* Saturating doubling multiplies. Types S16 S32. */
19570 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19571 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19572 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
19573 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
19574 S16 S32 U16 U32. */
19575 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
19577 /* Extract. Size 8. */
19578 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
19579 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
19581 /* Two registers, miscellaneous. */
19582 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
19583 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
19584 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
19585 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
19586 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
19587 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
19588 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
19589 /* Vector replicate. Sizes 8 16 32. */
19590 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
19591 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
19592 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
19593 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
19594 /* VMOVN. Types I16 I32 I64. */
19595 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
19596 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
19597 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
19598 /* VQMOVUN. Types S16 S32 S64. */
19599 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
19600 /* VZIP / VUZP. Sizes 8 16 32. */
19601 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19602 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19603 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
19604 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
19605 /* VQABS / VQNEG. Types S8 S16 S32. */
19606 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19607 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19608 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
19609 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
19610 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
19611 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19612 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
19613 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
19614 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
19615 /* Reciprocal estimates. Types U32 F32. */
19616 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19617 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
19618 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
19619 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
19620 /* VCLS. Types S8 S16 S32. */
19621 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
19622 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
19623 /* VCLZ. Types I8 I16 I32. */
19624 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
19625 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
19626 /* VCNT. Size 8. */
19627 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
19628 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
19629 /* Two address, untyped. */
19630 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
19631 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
19632 /* VTRN. Sizes 8 16 32. */
19633 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
19634 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
19636 /* Table lookup. Size 8. */
19637 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19638 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
19640 #undef THUMB_VARIANT
19641 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
19643 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
19645 /* Neon element/structure load/store. */
19646 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19647 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19648 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19649 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19650 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19651 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19652 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19653 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
19655 #undef THUMB_VARIANT
19656 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
19658 #define ARM_VARIANT & fpu_vfp_ext_v3xd
19659 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
19660 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19661 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19662 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19663 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19664 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19665 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19666 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
19667 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
19669 #undef THUMB_VARIANT
19670 #define THUMB_VARIANT & fpu_vfp_ext_v3
19672 #define ARM_VARIANT & fpu_vfp_ext_v3
19674 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
19675 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19676 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19677 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19678 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19679 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19680 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19681 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
19682 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
19685 #define ARM_VARIANT & fpu_vfp_ext_fma
19686 #undef THUMB_VARIANT
19687 #define THUMB_VARIANT & fpu_vfp_ext_fma
19688 /* Mnemonics shared by Neon and VFP. These are included in the
19689 VFP FMA variant; NEON and VFP FMA always includes the NEON
19690 FMA instructions. */
19691 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19692 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
19693 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
19694 the v form should always be used. */
19695 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19696 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
19697 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19698 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
19699 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19700 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
19702 #undef THUMB_VARIANT
19704 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
19706 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19707 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19708 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19709 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19710 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19711 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
19712 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
19713 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
19716 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
19718 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
19719 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
19720 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
19721 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
19722 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
19723 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
19724 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
19725 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
19726 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
19727 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19728 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19729 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19730 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19731 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19732 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
19733 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19734 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19735 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
19736 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
19737 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
19738 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19739 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19740 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19741 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19742 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19743 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
19744 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
19745 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
19746 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
19747 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
19748 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
19749 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
19750 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
19751 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
19752 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19753 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19754 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19755 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19756 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19757 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19758 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19759 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19760 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19761 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19762 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19763 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19764 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
19765 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19766 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19767 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19768 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19769 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19770 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19771 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19772 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19773 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19774 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19775 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19776 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19777 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19778 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19779 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19780 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19781 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19782 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19783 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19784 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19785 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19786 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19787 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19788 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19789 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19790 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19791 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19792 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19793 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19794 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19795 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19796 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19797 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19798 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19799 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19800 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19801 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19802 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19803 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19804 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19805 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19806 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
19807 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19808 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19809 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19810 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19811 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19812 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19813 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19814 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19815 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19816 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19817 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19818 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19819 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19820 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19821 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19822 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19823 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19824 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19825 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19826 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19827 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19828 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
19829 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19830 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19831 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19832 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19833 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19834 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19835 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19836 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19837 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19838 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19839 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19840 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19841 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19842 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19843 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19844 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19845 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
19846 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
19847 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19848 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
19849 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
19850 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
19851 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19852 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19853 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19854 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19855 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19856 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19857 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19858 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19859 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19860 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19861 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19862 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19863 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19864 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19865 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
19866 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19867 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19868 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19869 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19870 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19871 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19872 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19873 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19874 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
19875 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19876 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19877 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19878 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19879 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
19882 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
19884 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
19885 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
19886 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
19887 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19888 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19889 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
19890 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19891 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19892 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19893 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19894 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19895 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19896 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19897 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19898 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19899 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19900 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19901 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19902 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19903 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19904 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
19905 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19906 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19907 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19908 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19909 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19910 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19911 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19912 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19913 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19914 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19915 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19916 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19917 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19918 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19919 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19920 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19921 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19922 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19923 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19924 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19925 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19926 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19927 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19928 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19929 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19930 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19931 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19932 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19933 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19934 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19935 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19936 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19937 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19938 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19939 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19940 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
19943 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
19945 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19946 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19947 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19948 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19949 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
19950 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
19951 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
19952 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
19953 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
19954 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
19955 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
19956 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
19957 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
19958 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
19959 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
19960 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
19961 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
19962 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
19963 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
19964 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
19965 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
19966 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
19967 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
19968 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
19969 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
19970 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
19971 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
19972 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
19973 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
19974 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
19975 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
19976 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
19977 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
19978 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
19979 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
19980 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
19981 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
19982 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
19983 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
19984 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
19985 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
19986 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
19987 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
19988 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
19989 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
19990 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
19991 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
19992 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
19993 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
19994 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
19995 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
19996 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
19997 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
19998 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
19999 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20000 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20001 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20002 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20003 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
20004 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
20005 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
20006 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
20007 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
20008 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
20009 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20010 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20011 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20012 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20013 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20014 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
20015 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20016 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
20017 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20018 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
20019 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20020 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
20023 #undef THUMB_VARIANT
20049 /* MD interface: bits in the object file. */
20051 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
20052 for use in the a.out file, and stores them in the array pointed to by buf.
20053 This knows about the endian-ness of the target machine and does
20054 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
20055 2 (short) and 4 (long) Floating numbers are put out as a series of
20056 LITTLENUMS (shorts, here at least). */
20059 md_number_to_chars (char * buf
, valueT val
, int n
)
20061 if (target_big_endian
)
20062 number_to_chars_bigendian (buf
, val
, n
);
20064 number_to_chars_littleendian (buf
, val
, n
);
20068 md_chars_to_number (char * buf
, int n
)
20071 unsigned char * where
= (unsigned char *) buf
;
20073 if (target_big_endian
)
20078 result
|= (*where
++ & 255);
20086 result
|= (where
[n
] & 255);
20093 /* MD interface: Sections. */
20095 /* Calculate the maximum variable size (i.e., excluding fr_fix)
20096 that an rs_machine_dependent frag may reach. */
20099 arm_frag_max_var (fragS
*fragp
)
20101 /* We only use rs_machine_dependent for variable-size Thumb instructions,
20102 which are either THUMB_SIZE (2) or INSN_SIZE (4).
20104 Note that we generate relaxable instructions even for cases that don't
20105 really need it, like an immediate that's a trivial constant. So we're
20106 overestimating the instruction size for some of those cases. Rather
20107 than putting more intelligence here, it would probably be better to
20108 avoid generating a relaxation frag in the first place when it can be
20109 determined up front that a short instruction will suffice. */
20111 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
20115 /* Estimate the size of a frag before relaxing. Assume everything fits in
20119 md_estimate_size_before_relax (fragS
* fragp
,
20120 segT segtype ATTRIBUTE_UNUSED
)
20126 /* Convert a machine dependent frag. */
20129 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
20131 unsigned long insn
;
20132 unsigned long old_op
;
20140 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20142 old_op
= bfd_get_16(abfd
, buf
);
20143 if (fragp
->fr_symbol
)
20145 exp
.X_op
= O_symbol
;
20146 exp
.X_add_symbol
= fragp
->fr_symbol
;
20150 exp
.X_op
= O_constant
;
20152 exp
.X_add_number
= fragp
->fr_offset
;
20153 opcode
= fragp
->fr_subtype
;
20156 case T_MNEM_ldr_pc
:
20157 case T_MNEM_ldr_pc2
:
20158 case T_MNEM_ldr_sp
:
20159 case T_MNEM_str_sp
:
20166 if (fragp
->fr_var
== 4)
20168 insn
= THUMB_OP32 (opcode
);
20169 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
20171 insn
|= (old_op
& 0x700) << 4;
20175 insn
|= (old_op
& 7) << 12;
20176 insn
|= (old_op
& 0x38) << 13;
20178 insn
|= 0x00000c00;
20179 put_thumb32_insn (buf
, insn
);
20180 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
20184 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
20186 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
20189 if (fragp
->fr_var
== 4)
20191 insn
= THUMB_OP32 (opcode
);
20192 insn
|= (old_op
& 0xf0) << 4;
20193 put_thumb32_insn (buf
, insn
);
20194 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
20198 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20199 exp
.X_add_number
-= 4;
20207 if (fragp
->fr_var
== 4)
20209 int r0off
= (opcode
== T_MNEM_mov
20210 || opcode
== T_MNEM_movs
) ? 0 : 8;
20211 insn
= THUMB_OP32 (opcode
);
20212 insn
= (insn
& 0xe1ffffff) | 0x10000000;
20213 insn
|= (old_op
& 0x700) << r0off
;
20214 put_thumb32_insn (buf
, insn
);
20215 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20219 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
20224 if (fragp
->fr_var
== 4)
20226 insn
= THUMB_OP32(opcode
);
20227 put_thumb32_insn (buf
, insn
);
20228 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
20231 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
20235 if (fragp
->fr_var
== 4)
20237 insn
= THUMB_OP32(opcode
);
20238 insn
|= (old_op
& 0xf00) << 14;
20239 put_thumb32_insn (buf
, insn
);
20240 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
20243 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
20246 case T_MNEM_add_sp
:
20247 case T_MNEM_add_pc
:
20248 case T_MNEM_inc_sp
:
20249 case T_MNEM_dec_sp
:
20250 if (fragp
->fr_var
== 4)
20252 /* ??? Choose between add and addw. */
20253 insn
= THUMB_OP32 (opcode
);
20254 insn
|= (old_op
& 0xf0) << 4;
20255 put_thumb32_insn (buf
, insn
);
20256 if (opcode
== T_MNEM_add_pc
)
20257 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
20259 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20262 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20270 if (fragp
->fr_var
== 4)
20272 insn
= THUMB_OP32 (opcode
);
20273 insn
|= (old_op
& 0xf0) << 4;
20274 insn
|= (old_op
& 0xf) << 16;
20275 put_thumb32_insn (buf
, insn
);
20276 if (insn
& (1 << 20))
20277 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
20279 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
20282 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
20288 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
20289 (enum bfd_reloc_code_real
) reloc_type
);
20290 fixp
->fx_file
= fragp
->fr_file
;
20291 fixp
->fx_line
= fragp
->fr_line
;
20292 fragp
->fr_fix
+= fragp
->fr_var
;
20295 /* Return the size of a relaxable immediate operand instruction.
20296 SHIFT and SIZE specify the form of the allowable immediate. */
20298 relax_immediate (fragS
*fragp
, int size
, int shift
)
20304 /* ??? Should be able to do better than this. */
20305 if (fragp
->fr_symbol
)
20308 low
= (1 << shift
) - 1;
20309 mask
= (1 << (shift
+ size
)) - (1 << shift
);
20310 offset
= fragp
->fr_offset
;
20311 /* Force misaligned offsets to 32-bit variant. */
20314 if (offset
& ~mask
)
20319 /* Get the address of a symbol during relaxation. */
20321 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
20327 sym
= fragp
->fr_symbol
;
20328 sym_frag
= symbol_get_frag (sym
);
20329 know (S_GET_SEGMENT (sym
) != absolute_section
20330 || sym_frag
== &zero_address_frag
);
20331 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
20333 /* If frag has yet to be reached on this pass, assume it will
20334 move by STRETCH just as we did. If this is not so, it will
20335 be because some frag between grows, and that will force
20339 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
20343 /* Adjust stretch for any alignment frag. Note that if have
20344 been expanding the earlier code, the symbol may be
20345 defined in what appears to be an earlier frag. FIXME:
20346 This doesn't handle the fr_subtype field, which specifies
20347 a maximum number of bytes to skip when doing an
20349 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
20351 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
20354 stretch
= - ((- stretch
)
20355 & ~ ((1 << (int) f
->fr_offset
) - 1));
20357 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
20369 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
20372 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
20377 /* Assume worst case for symbols not known to be in the same section. */
20378 if (fragp
->fr_symbol
== NULL
20379 || !S_IS_DEFINED (fragp
->fr_symbol
)
20380 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20381 || S_IS_WEAK (fragp
->fr_symbol
))
20384 val
= relaxed_symbol_addr (fragp
, stretch
);
20385 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
20386 addr
= (addr
+ 4) & ~3;
20387 /* Force misaligned targets to 32-bit variant. */
20391 if (val
< 0 || val
> 1020)
20396 /* Return the size of a relaxable add/sub immediate instruction. */
20398 relax_addsub (fragS
*fragp
, asection
*sec
)
20403 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
20404 op
= bfd_get_16(sec
->owner
, buf
);
20405 if ((op
& 0xf) == ((op
>> 4) & 0xf))
20406 return relax_immediate (fragp
, 8, 0);
20408 return relax_immediate (fragp
, 3, 0);
20411 /* Return TRUE iff the definition of symbol S could be pre-empted
20412 (overridden) at link or load time. */
20414 symbol_preemptible (symbolS
*s
)
20416 /* Weak symbols can always be pre-empted. */
20420 /* Non-global symbols cannot be pre-empted. */
20421 if (! S_IS_EXTERNAL (s
))
20425 /* In ELF, a global symbol can be marked protected, or private. In that
20426 case it can't be pre-empted (other definitions in the same link unit
20427 would violate the ODR). */
20428 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
20432 /* Other global symbols might be pre-empted. */
20436 /* Return the size of a relaxable branch instruction. BITS is the
20437 size of the offset field in the narrow instruction. */
20440 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
20446 /* Assume worst case for symbols not known to be in the same section. */
20447 if (!S_IS_DEFINED (fragp
->fr_symbol
)
20448 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
20449 || S_IS_WEAK (fragp
->fr_symbol
))
20453 /* A branch to a function in ARM state will require interworking. */
20454 if (S_IS_DEFINED (fragp
->fr_symbol
)
20455 && ARM_IS_FUNC (fragp
->fr_symbol
))
20459 if (symbol_preemptible (fragp
->fr_symbol
))
20462 val
= relaxed_symbol_addr (fragp
, stretch
);
20463 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
20466 /* Offset is a signed value *2 */
20468 if (val
>= limit
|| val
< -limit
)
20474 /* Relax a machine dependent frag. This returns the amount by which
20475 the current size of the frag should change. */
20478 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
20483 oldsize
= fragp
->fr_var
;
20484 switch (fragp
->fr_subtype
)
20486 case T_MNEM_ldr_pc2
:
20487 newsize
= relax_adr (fragp
, sec
, stretch
);
20489 case T_MNEM_ldr_pc
:
20490 case T_MNEM_ldr_sp
:
20491 case T_MNEM_str_sp
:
20492 newsize
= relax_immediate (fragp
, 8, 2);
20496 newsize
= relax_immediate (fragp
, 5, 2);
20500 newsize
= relax_immediate (fragp
, 5, 1);
20504 newsize
= relax_immediate (fragp
, 5, 0);
20507 newsize
= relax_adr (fragp
, sec
, stretch
);
20513 newsize
= relax_immediate (fragp
, 8, 0);
20516 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
20519 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
20521 case T_MNEM_add_sp
:
20522 case T_MNEM_add_pc
:
20523 newsize
= relax_immediate (fragp
, 8, 2);
20525 case T_MNEM_inc_sp
:
20526 case T_MNEM_dec_sp
:
20527 newsize
= relax_immediate (fragp
, 7, 2);
20533 newsize
= relax_addsub (fragp
, sec
);
20539 fragp
->fr_var
= newsize
;
20540 /* Freeze wide instructions that are at or before the same location as
20541 in the previous pass. This avoids infinite loops.
20542 Don't freeze them unconditionally because targets may be artificially
20543 misaligned by the expansion of preceding frags. */
20544 if (stretch
<= 0 && newsize
> 2)
20546 md_convert_frag (sec
->owner
, sec
, fragp
);
20550 return newsize
- oldsize
;
20553 /* Round up a section size to the appropriate boundary. */
20556 md_section_align (segT segment ATTRIBUTE_UNUSED
,
20559 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
20560 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
20562 /* For a.out, force the section size to be aligned. If we don't do
20563 this, BFD will align it for us, but it will not write out the
20564 final bytes of the section. This may be a bug in BFD, but it is
20565 easier to fix it here since that is how the other a.out targets
20569 align
= bfd_get_section_alignment (stdoutput
, segment
);
20570 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
20577 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
20578 of an rs_align_code fragment. */
20581 arm_handle_align (fragS
* fragP
)
20583 static char const arm_noop
[2][2][4] =
20586 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
20587 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
20590 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
20591 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
20594 static char const thumb_noop
[2][2][2] =
20597 {0xc0, 0x46}, /* LE */
20598 {0x46, 0xc0}, /* BE */
20601 {0x00, 0xbf}, /* LE */
20602 {0xbf, 0x00} /* BE */
20605 static char const wide_thumb_noop
[2][4] =
20606 { /* Wide Thumb-2 */
20607 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
20608 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
20611 unsigned bytes
, fix
, noop_size
;
20614 const char *narrow_noop
= NULL
;
20619 if (fragP
->fr_type
!= rs_align_code
)
20622 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
20623 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
20626 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20627 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
20629 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
20631 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
20633 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
20635 narrow_noop
= thumb_noop
[1][target_big_endian
];
20636 noop
= wide_thumb_noop
[target_big_endian
];
20639 noop
= thumb_noop
[0][target_big_endian
];
20647 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
20648 [target_big_endian
];
20655 fragP
->fr_var
= noop_size
;
20657 if (bytes
& (noop_size
- 1))
20659 fix
= bytes
& (noop_size
- 1);
20661 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
20663 memset (p
, 0, fix
);
20670 if (bytes
& noop_size
)
20672 /* Insert a narrow noop. */
20673 memcpy (p
, narrow_noop
, noop_size
);
20675 bytes
-= noop_size
;
20679 /* Use wide noops for the remainder */
20683 while (bytes
>= noop_size
)
20685 memcpy (p
, noop
, noop_size
);
20687 bytes
-= noop_size
;
20691 fragP
->fr_fix
+= fix
;
20694 /* Called from md_do_align. Used to create an alignment
20695 frag in a code section. */
20698 arm_frag_align_code (int n
, int max
)
20702 /* We assume that there will never be a requirement
20703 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
20704 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
20709 _("alignments greater than %d bytes not supported in .text sections."),
20710 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
20711 as_fatal ("%s", err_msg
);
20714 p
= frag_var (rs_align_code
,
20715 MAX_MEM_FOR_RS_ALIGN_CODE
,
20717 (relax_substateT
) max
,
20724 /* Perform target specific initialisation of a frag.
20725 Note - despite the name this initialisation is not done when the frag
20726 is created, but only when its type is assigned. A frag can be created
20727 and used a long time before its type is set, so beware of assuming that
20728 this initialisationis performed first. */
20732 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
20734 /* Record whether this frag is in an ARM or a THUMB area. */
20735 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20738 #else /* OBJ_ELF is defined. */
20740 arm_init_frag (fragS
* fragP
, int max_chars
)
20742 /* If the current ARM vs THUMB mode has not already
20743 been recorded into this frag then do so now. */
20744 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
20746 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
20748 /* Record a mapping symbol for alignment frags. We will delete this
20749 later if the alignment ends up empty. */
20750 switch (fragP
->fr_type
)
20753 case rs_align_test
:
20755 mapping_state_2 (MAP_DATA
, max_chars
);
20757 case rs_align_code
:
20758 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
20766 /* When we change sections we need to issue a new mapping symbol. */
20769 arm_elf_change_section (void)
20771 /* Link an unlinked unwind index table section to the .text section. */
20772 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
20773 && elf_linked_to_section (now_seg
) == NULL
)
20774 elf_linked_to_section (now_seg
) = text_section
;
20778 arm_elf_section_type (const char * str
, size_t len
)
20780 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
20781 return SHT_ARM_EXIDX
;
20786 /* Code to deal with unwinding tables. */
20788 static void add_unwind_adjustsp (offsetT
);
20790 /* Generate any deferred unwind frame offset. */
20793 flush_pending_unwind (void)
20797 offset
= unwind
.pending_offset
;
20798 unwind
.pending_offset
= 0;
20800 add_unwind_adjustsp (offset
);
20803 /* Add an opcode to this list for this function. Two-byte opcodes should
20804 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
20808 add_unwind_opcode (valueT op
, int length
)
20810 /* Add any deferred stack adjustment. */
20811 if (unwind
.pending_offset
)
20812 flush_pending_unwind ();
20814 unwind
.sp_restored
= 0;
20816 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
20818 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
20819 if (unwind
.opcodes
)
20820 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
20821 unwind
.opcode_alloc
);
20823 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
20828 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
20830 unwind
.opcode_count
++;
20834 /* Add unwind opcodes to adjust the stack pointer. */
20837 add_unwind_adjustsp (offsetT offset
)
20841 if (offset
> 0x200)
20843 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
20848 /* Long form: 0xb2, uleb128. */
20849 /* This might not fit in a word so add the individual bytes,
20850 remembering the list is built in reverse order. */
20851 o
= (valueT
) ((offset
- 0x204) >> 2);
20853 add_unwind_opcode (0, 1);
20855 /* Calculate the uleb128 encoding of the offset. */
20859 bytes
[n
] = o
& 0x7f;
20865 /* Add the insn. */
20867 add_unwind_opcode (bytes
[n
- 1], 1);
20868 add_unwind_opcode (0xb2, 1);
20870 else if (offset
> 0x100)
20872 /* Two short opcodes. */
20873 add_unwind_opcode (0x3f, 1);
20874 op
= (offset
- 0x104) >> 2;
20875 add_unwind_opcode (op
, 1);
20877 else if (offset
> 0)
20879 /* Short opcode. */
20880 op
= (offset
- 4) >> 2;
20881 add_unwind_opcode (op
, 1);
20883 else if (offset
< 0)
20886 while (offset
> 0x100)
20888 add_unwind_opcode (0x7f, 1);
20891 op
= ((offset
- 4) >> 2) | 0x40;
20892 add_unwind_opcode (op
, 1);
20896 /* Finish the list of unwind opcodes for this function. */
20898 finish_unwind_opcodes (void)
20902 if (unwind
.fp_used
)
20904 /* Adjust sp as necessary. */
20905 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
20906 flush_pending_unwind ();
20908 /* After restoring sp from the frame pointer. */
20909 op
= 0x90 | unwind
.fp_reg
;
20910 add_unwind_opcode (op
, 1);
20913 flush_pending_unwind ();
20917 /* Start an exception table entry. If idx is nonzero this is an index table
20921 start_unwind_section (const segT text_seg
, int idx
)
20923 const char * text_name
;
20924 const char * prefix
;
20925 const char * prefix_once
;
20926 const char * group_name
;
20930 size_t sec_name_len
;
20937 prefix
= ELF_STRING_ARM_unwind
;
20938 prefix_once
= ELF_STRING_ARM_unwind_once
;
20939 type
= SHT_ARM_EXIDX
;
20943 prefix
= ELF_STRING_ARM_unwind_info
;
20944 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
20945 type
= SHT_PROGBITS
;
20948 text_name
= segment_name (text_seg
);
20949 if (streq (text_name
, ".text"))
20952 if (strncmp (text_name
, ".gnu.linkonce.t.",
20953 strlen (".gnu.linkonce.t.")) == 0)
20955 prefix
= prefix_once
;
20956 text_name
+= strlen (".gnu.linkonce.t.");
20959 prefix_len
= strlen (prefix
);
20960 text_len
= strlen (text_name
);
20961 sec_name_len
= prefix_len
+ text_len
;
20962 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
20963 memcpy (sec_name
, prefix
, prefix_len
);
20964 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
20965 sec_name
[prefix_len
+ text_len
] = '\0';
20971 /* Handle COMDAT group. */
20972 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
20974 group_name
= elf_group_name (text_seg
);
20975 if (group_name
== NULL
)
20977 as_bad (_("Group section `%s' has no group signature"),
20978 segment_name (text_seg
));
20979 ignore_rest_of_line ();
20982 flags
|= SHF_GROUP
;
20986 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
20988 /* Set the section link for index tables. */
20990 elf_linked_to_section (now_seg
) = text_seg
;
20994 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
20995 personality routine data. Returns zero, or the index table value for
20996 an inline entry. */
20999 create_unwind_entry (int have_data
)
21004 /* The current word of data. */
21006 /* The number of bytes left in this word. */
21009 finish_unwind_opcodes ();
21011 /* Remember the current text section. */
21012 unwind
.saved_seg
= now_seg
;
21013 unwind
.saved_subseg
= now_subseg
;
21015 start_unwind_section (now_seg
, 0);
21017 if (unwind
.personality_routine
== NULL
)
21019 if (unwind
.personality_index
== -2)
21022 as_bad (_("handlerdata in cantunwind frame"));
21023 return 1; /* EXIDX_CANTUNWIND. */
21026 /* Use a default personality routine if none is specified. */
21027 if (unwind
.personality_index
== -1)
21029 if (unwind
.opcode_count
> 3)
21030 unwind
.personality_index
= 1;
21032 unwind
.personality_index
= 0;
21035 /* Space for the personality routine entry. */
21036 if (unwind
.personality_index
== 0)
21038 if (unwind
.opcode_count
> 3)
21039 as_bad (_("too many unwind opcodes for personality routine 0"));
21043 /* All the data is inline in the index table. */
21046 while (unwind
.opcode_count
> 0)
21048 unwind
.opcode_count
--;
21049 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21053 /* Pad with "finish" opcodes. */
21055 data
= (data
<< 8) | 0xb0;
21062 /* We get two opcodes "free" in the first word. */
21063 size
= unwind
.opcode_count
- 2;
21067 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
21068 if (unwind
.personality_index
!= -1)
21070 as_bad (_("attempt to recreate an unwind entry"));
21074 /* An extra byte is required for the opcode count. */
21075 size
= unwind
.opcode_count
+ 1;
21078 size
= (size
+ 3) >> 2;
21080 as_bad (_("too many unwind opcodes"));
21082 frag_align (2, 0, 0);
21083 record_alignment (now_seg
, 2);
21084 unwind
.table_entry
= expr_build_dot ();
21086 /* Allocate the table entry. */
21087 ptr
= frag_more ((size
<< 2) + 4);
21088 /* PR 13449: Zero the table entries in case some of them are not used. */
21089 memset (ptr
, 0, (size
<< 2) + 4);
21090 where
= frag_now_fix () - ((size
<< 2) + 4);
21092 switch (unwind
.personality_index
)
21095 /* ??? Should this be a PLT generating relocation? */
21096 /* Custom personality routine. */
21097 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
21098 BFD_RELOC_ARM_PREL31
);
21103 /* Set the first byte to the number of additional words. */
21104 data
= size
> 0 ? size
- 1 : 0;
21108 /* ABI defined personality routines. */
21110 /* Three opcodes bytes are packed into the first word. */
21117 /* The size and first two opcode bytes go in the first word. */
21118 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
21123 /* Should never happen. */
21127 /* Pack the opcodes into words (MSB first), reversing the list at the same
21129 while (unwind
.opcode_count
> 0)
21133 md_number_to_chars (ptr
, data
, 4);
21138 unwind
.opcode_count
--;
21140 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
21143 /* Finish off the last word. */
21146 /* Pad with "finish" opcodes. */
21148 data
= (data
<< 8) | 0xb0;
21150 md_number_to_chars (ptr
, data
, 4);
21155 /* Add an empty descriptor if there is no user-specified data. */
21156 ptr
= frag_more (4);
21157 md_number_to_chars (ptr
, 0, 4);
21164 /* Initialize the DWARF-2 unwind information for this procedure. */
21167 tc_arm_frame_initial_instructions (void)
21169 cfi_add_CFA_def_cfa (REG_SP
, 0);
21171 #endif /* OBJ_ELF */
21173 /* Convert REGNAME to a DWARF-2 register number. */
21176 tc_arm_regname_to_dw2regnum (char *regname
)
21178 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
21182 /* PR 16694: Allow VFP registers as well. */
21183 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
21187 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
21196 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
21200 exp
.X_op
= O_secrel
;
21201 exp
.X_add_symbol
= symbol
;
21202 exp
.X_add_number
= 0;
21203 emit_expr (&exp
, size
);
21207 /* MD interface: Symbol and relocation handling. */
21209 /* Return the address within the segment that a PC-relative fixup is
21210 relative to. For ARM, PC-relative fixups applied to instructions
21211 are generally relative to the location of the fixup plus 8 bytes.
21212 Thumb branches are offset by 4, and Thumb loads relative to PC
21213 require special handling. */
21216 md_pcrel_from_section (fixS
* fixP
, segT seg
)
21218 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21220 /* If this is pc-relative and we are going to emit a relocation
21221 then we just want to put out any pipeline compensation that the linker
21222 will need. Otherwise we want to use the calculated base.
21223 For WinCE we skip the bias for externals as well, since this
21224 is how the MS ARM-CE assembler behaves and we want to be compatible. */
21226 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21227 || (arm_force_relocation (fixP
)
21229 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
21235 switch (fixP
->fx_r_type
)
21237 /* PC relative addressing on the Thumb is slightly odd as the
21238 bottom two bits of the PC are forced to zero for the
21239 calculation. This happens *after* application of the
21240 pipeline offset. However, Thumb adrl already adjusts for
21241 this, so we need not do it again. */
21242 case BFD_RELOC_ARM_THUMB_ADD
:
21245 case BFD_RELOC_ARM_THUMB_OFFSET
:
21246 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21247 case BFD_RELOC_ARM_T32_ADD_PC12
:
21248 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21249 return (base
+ 4) & ~3;
21251 /* Thumb branches are simply offset by +4. */
21252 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21253 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21254 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21255 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21256 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21259 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21261 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21262 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21263 && ARM_IS_FUNC (fixP
->fx_addsy
)
21264 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21265 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21268 /* BLX is like branches above, but forces the low two bits of PC to
21270 case BFD_RELOC_THUMB_PCREL_BLX
:
21272 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21273 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21274 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21275 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21276 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21277 return (base
+ 4) & ~3;
21279 /* ARM mode branches are offset by +8. However, the Windows CE
21280 loader expects the relocation not to take this into account. */
21281 case BFD_RELOC_ARM_PCREL_BLX
:
21283 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21284 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21285 && ARM_IS_FUNC (fixP
->fx_addsy
)
21286 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21287 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21290 case BFD_RELOC_ARM_PCREL_CALL
:
21292 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21293 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21294 && THUMB_IS_FUNC (fixP
->fx_addsy
)
21295 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21296 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
21299 case BFD_RELOC_ARM_PCREL_BRANCH
:
21300 case BFD_RELOC_ARM_PCREL_JUMP
:
21301 case BFD_RELOC_ARM_PLT32
:
21303 /* When handling fixups immediately, because we have already
21304 discovered the value of a symbol, or the address of the frag involved
21305 we must account for the offset by +8, as the OS loader will never see the reloc.
21306 see fixup_segment() in write.c
21307 The S_IS_EXTERNAL test handles the case of global symbols.
21308 Those need the calculated base, not just the pipe compensation the linker will need. */
21310 && fixP
->fx_addsy
!= NULL
21311 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21312 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
21320 /* ARM mode loads relative to PC are also offset by +8. Unlike
21321 branches, the Windows CE loader *does* expect the relocation
21322 to take this into account. */
21323 case BFD_RELOC_ARM_OFFSET_IMM
:
21324 case BFD_RELOC_ARM_OFFSET_IMM8
:
21325 case BFD_RELOC_ARM_HWLITERAL
:
21326 case BFD_RELOC_ARM_LITERAL
:
21327 case BFD_RELOC_ARM_CP_OFF_IMM
:
21331 /* Other PC-relative relocations are un-offset. */
21337 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
21338 Otherwise we have no need to default values of symbols. */
21341 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
21344 if (name
[0] == '_' && name
[1] == 'G'
21345 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
21349 if (symbol_find (name
))
21350 as_bad (_("GOT already in the symbol table"));
21352 GOT_symbol
= symbol_new (name
, undefined_section
,
21353 (valueT
) 0, & zero_address_frag
);
21363 /* Subroutine of md_apply_fix. Check to see if an immediate can be
21364 computed as two separate immediate values, added together. We
21365 already know that this value cannot be computed by just one ARM
21368 static unsigned int
21369 validate_immediate_twopart (unsigned int val
,
21370 unsigned int * highpart
)
21375 for (i
= 0; i
< 32; i
+= 2)
21376 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
21382 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
21384 else if (a
& 0xff0000)
21386 if (a
& 0xff000000)
21388 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
21392 gas_assert (a
& 0xff000000);
21393 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
21396 return (a
& 0xff) | (i
<< 7);
21403 validate_offset_imm (unsigned int val
, int hwse
)
21405 if ((hwse
&& val
> 255) || val
> 4095)
21410 /* Subroutine of md_apply_fix. Do those data_ops which can take a
21411 negative immediate constant by altering the instruction. A bit of
21416 by inverting the second operand, and
21419 by negating the second operand. */
21422 negate_data_op (unsigned long * instruction
,
21423 unsigned long value
)
21426 unsigned long negated
, inverted
;
21428 negated
= encode_arm_immediate (-value
);
21429 inverted
= encode_arm_immediate (~value
);
21431 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
21434 /* First negates. */
21435 case OPCODE_SUB
: /* ADD <-> SUB */
21436 new_inst
= OPCODE_ADD
;
21441 new_inst
= OPCODE_SUB
;
21445 case OPCODE_CMP
: /* CMP <-> CMN */
21446 new_inst
= OPCODE_CMN
;
21451 new_inst
= OPCODE_CMP
;
21455 /* Now Inverted ops. */
21456 case OPCODE_MOV
: /* MOV <-> MVN */
21457 new_inst
= OPCODE_MVN
;
21462 new_inst
= OPCODE_MOV
;
21466 case OPCODE_AND
: /* AND <-> BIC */
21467 new_inst
= OPCODE_BIC
;
21472 new_inst
= OPCODE_AND
;
21476 case OPCODE_ADC
: /* ADC <-> SBC */
21477 new_inst
= OPCODE_SBC
;
21482 new_inst
= OPCODE_ADC
;
21486 /* We cannot do anything. */
21491 if (value
== (unsigned) FAIL
)
21494 *instruction
&= OPCODE_MASK
;
21495 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
21499 /* Like negate_data_op, but for Thumb-2. */
21501 static unsigned int
21502 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
21506 unsigned int negated
, inverted
;
21508 negated
= encode_thumb32_immediate (-value
);
21509 inverted
= encode_thumb32_immediate (~value
);
21511 rd
= (*instruction
>> 8) & 0xf;
21512 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
21515 /* ADD <-> SUB. Includes CMP <-> CMN. */
21516 case T2_OPCODE_SUB
:
21517 new_inst
= T2_OPCODE_ADD
;
21521 case T2_OPCODE_ADD
:
21522 new_inst
= T2_OPCODE_SUB
;
21526 /* ORR <-> ORN. Includes MOV <-> MVN. */
21527 case T2_OPCODE_ORR
:
21528 new_inst
= T2_OPCODE_ORN
;
21532 case T2_OPCODE_ORN
:
21533 new_inst
= T2_OPCODE_ORR
;
21537 /* AND <-> BIC. TST has no inverted equivalent. */
21538 case T2_OPCODE_AND
:
21539 new_inst
= T2_OPCODE_BIC
;
21546 case T2_OPCODE_BIC
:
21547 new_inst
= T2_OPCODE_AND
;
21552 case T2_OPCODE_ADC
:
21553 new_inst
= T2_OPCODE_SBC
;
21557 case T2_OPCODE_SBC
:
21558 new_inst
= T2_OPCODE_ADC
;
21562 /* We cannot do anything. */
21567 if (value
== (unsigned int)FAIL
)
21570 *instruction
&= T2_OPCODE_MASK
;
21571 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
21575 /* Read a 32-bit thumb instruction from buf. */
21576 static unsigned long
21577 get_thumb32_insn (char * buf
)
21579 unsigned long insn
;
21580 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
21581 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21587 /* We usually want to set the low bit on the address of thumb function
21588 symbols. In particular .word foo - . should have the low bit set.
21589 Generic code tries to fold the difference of two symbols to
21590 a constant. Prevent this and force a relocation when the first symbols
21591 is a thumb function. */
21594 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
21596 if (op
== O_subtract
21597 && l
->X_op
== O_symbol
21598 && r
->X_op
== O_symbol
21599 && THUMB_IS_FUNC (l
->X_add_symbol
))
21601 l
->X_op
= O_subtract
;
21602 l
->X_op_symbol
= r
->X_add_symbol
;
21603 l
->X_add_number
-= r
->X_add_number
;
21607 /* Process as normal. */
21611 /* Encode Thumb2 unconditional branches and calls. The encoding
21612 for the 2 are identical for the immediate values. */
21615 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
21617 #define T2I1I2MASK ((1 << 13) | (1 << 11))
21620 addressT S
, I1
, I2
, lo
, hi
;
21622 S
= (value
>> 24) & 0x01;
21623 I1
= (value
>> 23) & 0x01;
21624 I2
= (value
>> 22) & 0x01;
21625 hi
= (value
>> 12) & 0x3ff;
21626 lo
= (value
>> 1) & 0x7ff;
21627 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21628 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21629 newval
|= (S
<< 10) | hi
;
21630 newval2
&= ~T2I1I2MASK
;
21631 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
21632 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21633 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21637 md_apply_fix (fixS
* fixP
,
21641 offsetT value
= * valP
;
21643 unsigned int newimm
;
21644 unsigned long temp
;
21646 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
21648 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
21650 /* Note whether this will delete the relocation. */
21652 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
21655 /* On a 64-bit host, silently truncate 'value' to 32 bits for
21656 consistency with the behaviour on 32-bit hosts. Remember value
21658 value
&= 0xffffffff;
21659 value
^= 0x80000000;
21660 value
-= 0x80000000;
21663 fixP
->fx_addnumber
= value
;
21665 /* Same treatment for fixP->fx_offset. */
21666 fixP
->fx_offset
&= 0xffffffff;
21667 fixP
->fx_offset
^= 0x80000000;
21668 fixP
->fx_offset
-= 0x80000000;
21670 switch (fixP
->fx_r_type
)
21672 case BFD_RELOC_NONE
:
21673 /* This will need to go in the object file. */
21677 case BFD_RELOC_ARM_IMMEDIATE
:
21678 /* We claim that this fixup has been processed here,
21679 even if in fact we generate an error because we do
21680 not have a reloc for it, so tc_gen_reloc will reject it. */
21683 if (fixP
->fx_addsy
)
21685 const char *msg
= 0;
21687 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21688 msg
= _("undefined symbol %s used as an immediate value");
21689 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21690 msg
= _("symbol %s is in a different section");
21691 else if (S_IS_WEAK (fixP
->fx_addsy
))
21692 msg
= _("symbol %s is weak and may be overridden later");
21696 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21697 msg
, S_GET_NAME (fixP
->fx_addsy
));
21702 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21704 /* If the offset is negative, we should use encoding A2 for ADR. */
21705 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
21706 newimm
= negate_data_op (&temp
, value
);
21709 newimm
= encode_arm_immediate (value
);
21711 /* If the instruction will fail, see if we can fix things up by
21712 changing the opcode. */
21713 if (newimm
== (unsigned int) FAIL
)
21714 newimm
= negate_data_op (&temp
, value
);
21717 if (newimm
== (unsigned int) FAIL
)
21719 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21720 _("invalid constant (%lx) after fixup"),
21721 (unsigned long) value
);
21725 newimm
|= (temp
& 0xfffff000);
21726 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21729 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21731 unsigned int highpart
= 0;
21732 unsigned int newinsn
= 0xe1a00000; /* nop. */
21734 if (fixP
->fx_addsy
)
21736 const char *msg
= 0;
21738 if (! S_IS_DEFINED (fixP
->fx_addsy
))
21739 msg
= _("undefined symbol %s used as an immediate value");
21740 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
21741 msg
= _("symbol %s is in a different section");
21742 else if (S_IS_WEAK (fixP
->fx_addsy
))
21743 msg
= _("symbol %s is weak and may be overridden later");
21747 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21748 msg
, S_GET_NAME (fixP
->fx_addsy
));
21753 newimm
= encode_arm_immediate (value
);
21754 temp
= md_chars_to_number (buf
, INSN_SIZE
);
21756 /* If the instruction will fail, see if we can fix things up by
21757 changing the opcode. */
21758 if (newimm
== (unsigned int) FAIL
21759 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
21761 /* No ? OK - try using two ADD instructions to generate
21763 newimm
= validate_immediate_twopart (value
, & highpart
);
21765 /* Yes - then make sure that the second instruction is
21767 if (newimm
!= (unsigned int) FAIL
)
21769 /* Still No ? Try using a negated value. */
21770 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
21771 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
21772 /* Otherwise - give up. */
21775 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21776 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
21781 /* Replace the first operand in the 2nd instruction (which
21782 is the PC) with the destination register. We have
21783 already added in the PC in the first instruction and we
21784 do not want to do it again. */
21785 newinsn
&= ~ 0xf0000;
21786 newinsn
|= ((newinsn
& 0x0f000) << 4);
21789 newimm
|= (temp
& 0xfffff000);
21790 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
21792 highpart
|= (newinsn
& 0xfffff000);
21793 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
21797 case BFD_RELOC_ARM_OFFSET_IMM
:
21798 if (!fixP
->fx_done
&& seg
->use_rela_p
)
21801 case BFD_RELOC_ARM_LITERAL
:
21807 if (validate_offset_imm (value
, 0) == FAIL
)
21809 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
21810 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21811 _("invalid literal constant: pool needs to be closer"));
21813 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21814 _("bad immediate value for offset (%ld)"),
21819 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21821 newval
&= 0xfffff000;
21824 newval
&= 0xff7ff000;
21825 newval
|= value
| (sign
? INDEX_UP
: 0);
21827 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21830 case BFD_RELOC_ARM_OFFSET_IMM8
:
21831 case BFD_RELOC_ARM_HWLITERAL
:
21837 if (validate_offset_imm (value
, 1) == FAIL
)
21839 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
21840 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21841 _("invalid literal constant: pool needs to be closer"));
21843 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21844 _("bad immediate value for 8-bit offset (%ld)"),
21849 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21851 newval
&= 0xfffff0f0;
21854 newval
&= 0xff7ff0f0;
21855 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
21857 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21860 case BFD_RELOC_ARM_T32_OFFSET_U8
:
21861 if (value
< 0 || value
> 1020 || value
% 4 != 0)
21862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21863 _("bad immediate value for offset (%ld)"), (long) value
);
21866 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
21868 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
21871 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
21872 /* This is a complicated relocation used for all varieties of Thumb32
21873 load/store instruction with immediate offset:
21875 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
21876 *4, optional writeback(W)
21877 (doubleword load/store)
21879 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
21880 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
21881 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
21882 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
21883 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
21885 Uppercase letters indicate bits that are already encoded at
21886 this point. Lowercase letters are our problem. For the
21887 second block of instructions, the secondary opcode nybble
21888 (bits 8..11) is present, and bit 23 is zero, even if this is
21889 a PC-relative operation. */
21890 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21892 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
21894 if ((newval
& 0xf0000000) == 0xe0000000)
21896 /* Doubleword load/store: 8-bit offset, scaled by 4. */
21898 newval
|= (1 << 23);
21901 if (value
% 4 != 0)
21903 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21904 _("offset not a multiple of 4"));
21910 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21911 _("offset out of range"));
21916 else if ((newval
& 0x000f0000) == 0x000f0000)
21918 /* PC-relative, 12-bit offset. */
21920 newval
|= (1 << 23);
21925 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21926 _("offset out of range"));
21931 else if ((newval
& 0x00000100) == 0x00000100)
21933 /* Writeback: 8-bit, +/- offset. */
21935 newval
|= (1 << 9);
21940 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21941 _("offset out of range"));
21946 else if ((newval
& 0x00000f00) == 0x00000e00)
21948 /* T-instruction: positive 8-bit offset. */
21949 if (value
< 0 || value
> 0xff)
21951 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21952 _("offset out of range"));
21960 /* Positive 12-bit or negative 8-bit offset. */
21964 newval
|= (1 << 23);
21974 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21975 _("offset out of range"));
21982 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
21983 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
21986 case BFD_RELOC_ARM_SHIFT_IMM
:
21987 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21988 if (((unsigned long) value
) > 32
21990 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
21992 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21993 _("shift expression is too large"));
21998 /* Shifts of zero must be done as lsl. */
22000 else if (value
== 32)
22002 newval
&= 0xfffff07f;
22003 newval
|= (value
& 0x1f) << 7;
22004 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22007 case BFD_RELOC_ARM_T32_IMMEDIATE
:
22008 case BFD_RELOC_ARM_T32_ADD_IMM
:
22009 case BFD_RELOC_ARM_T32_IMM12
:
22010 case BFD_RELOC_ARM_T32_ADD_PC12
:
22011 /* We claim that this fixup has been processed here,
22012 even if in fact we generate an error because we do
22013 not have a reloc for it, so tc_gen_reloc will reject it. */
22017 && ! S_IS_DEFINED (fixP
->fx_addsy
))
22019 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22020 _("undefined symbol %s used as an immediate value"),
22021 S_GET_NAME (fixP
->fx_addsy
));
22025 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22027 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
22030 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22031 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22033 newimm
= encode_thumb32_immediate (value
);
22034 if (newimm
== (unsigned int) FAIL
)
22035 newimm
= thumb32_negate_data_op (&newval
, value
);
22037 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
22038 && newimm
== (unsigned int) FAIL
)
22040 /* Turn add/sum into addw/subw. */
22041 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
22042 newval
= (newval
& 0xfeffffff) | 0x02000000;
22043 /* No flat 12-bit imm encoding for addsw/subsw. */
22044 if ((newval
& 0x00100000) == 0)
22046 /* 12 bit immediate for addw/subw. */
22050 newval
^= 0x00a00000;
22053 newimm
= (unsigned int) FAIL
;
22059 if (newimm
== (unsigned int)FAIL
)
22061 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22062 _("invalid constant (%lx) after fixup"),
22063 (unsigned long) value
);
22067 newval
|= (newimm
& 0x800) << 15;
22068 newval
|= (newimm
& 0x700) << 4;
22069 newval
|= (newimm
& 0x0ff);
22071 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
22072 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
22075 case BFD_RELOC_ARM_SMC
:
22076 if (((unsigned long) value
) > 0xffff)
22077 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22078 _("invalid smc expression"));
22079 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22080 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22081 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22084 case BFD_RELOC_ARM_HVC
:
22085 if (((unsigned long) value
) > 0xffff)
22086 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22087 _("invalid hvc expression"));
22088 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22089 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
22090 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22093 case BFD_RELOC_ARM_SWI
:
22094 if (fixP
->tc_fix_data
!= 0)
22096 if (((unsigned long) value
) > 0xff)
22097 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22098 _("invalid swi expression"));
22099 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22101 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22105 if (((unsigned long) value
) > 0x00ffffff)
22106 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22107 _("invalid swi expression"));
22108 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22110 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22114 case BFD_RELOC_ARM_MULTI
:
22115 if (((unsigned long) value
) > 0xffff)
22116 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22117 _("invalid expression in load/store multiple"));
22118 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
22119 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22123 case BFD_RELOC_ARM_PCREL_CALL
:
22125 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22127 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22128 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22129 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22130 /* Flip the bl to blx. This is a simple flip
22131 bit here because we generate PCREL_CALL for
22132 unconditional bls. */
22134 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22135 newval
= newval
| 0x10000000;
22136 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22142 goto arm_branch_common
;
22144 case BFD_RELOC_ARM_PCREL_JUMP
:
22145 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22147 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22148 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22149 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22151 /* This would map to a bl<cond>, b<cond>,
22152 b<always> to a Thumb function. We
22153 need to force a relocation for this particular
22155 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22159 case BFD_RELOC_ARM_PLT32
:
22161 case BFD_RELOC_ARM_PCREL_BRANCH
:
22163 goto arm_branch_common
;
22165 case BFD_RELOC_ARM_PCREL_BLX
:
22168 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
22170 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22171 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22172 && ARM_IS_FUNC (fixP
->fx_addsy
))
22174 /* Flip the blx to a bl and warn. */
22175 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22176 newval
= 0xeb000000;
22177 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22178 _("blx to '%s' an ARM ISA state function changed to bl"),
22180 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22186 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22187 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
22191 /* We are going to store value (shifted right by two) in the
22192 instruction, in a 24 bit, signed field. Bits 26 through 32 either
22193 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
22194 also be be clear. */
22196 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22197 _("misaligned branch destination"));
22198 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
22199 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
22200 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22202 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22204 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22205 newval
|= (value
>> 2) & 0x00ffffff;
22206 /* Set the H bit on BLX instructions. */
22210 newval
|= 0x01000000;
22212 newval
&= ~0x01000000;
22214 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22218 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
22219 /* CBZ can only branch forward. */
22221 /* Attempts to use CBZ to branch to the next instruction
22222 (which, strictly speaking, are prohibited) will be turned into
22225 FIXME: It may be better to remove the instruction completely and
22226 perform relaxation. */
22229 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22230 newval
= 0xbf00; /* NOP encoding T1 */
22231 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22236 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22238 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22240 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22241 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
22242 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22247 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
22248 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
22249 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22251 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22253 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22254 newval
|= (value
& 0x1ff) >> 1;
22255 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22259 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
22260 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
22261 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22263 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22265 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22266 newval
|= (value
& 0xfff) >> 1;
22267 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22271 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22273 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22274 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22275 && ARM_IS_FUNC (fixP
->fx_addsy
)
22276 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22278 /* Force a relocation for a branch 20 bits wide. */
22281 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
22282 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22283 _("conditional branch out of range"));
22285 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22288 addressT S
, J1
, J2
, lo
, hi
;
22290 S
= (value
& 0x00100000) >> 20;
22291 J2
= (value
& 0x00080000) >> 19;
22292 J1
= (value
& 0x00040000) >> 18;
22293 hi
= (value
& 0x0003f000) >> 12;
22294 lo
= (value
& 0x00000ffe) >> 1;
22296 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22297 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22298 newval
|= (S
<< 10) | hi
;
22299 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
22300 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22301 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
22305 case BFD_RELOC_THUMB_PCREL_BLX
:
22306 /* If there is a blx from a thumb state function to
22307 another thumb function flip this to a bl and warn
22311 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22312 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22313 && THUMB_IS_FUNC (fixP
->fx_addsy
))
22315 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
22316 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
22317 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
22319 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22320 newval
= newval
| 0x1000;
22321 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22322 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22327 goto thumb_bl_common
;
22329 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22330 /* A bl from Thumb state ISA to an internal ARM state function
22331 is converted to a blx. */
22333 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22334 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22335 && ARM_IS_FUNC (fixP
->fx_addsy
)
22336 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22338 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
22339 newval
= newval
& ~0x1000;
22340 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
22341 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
22347 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22348 /* For a BLX instruction, make sure that the relocation is rounded up
22349 to a word boundary. This follows the semantics of the instruction
22350 which specifies that bit 1 of the target address will come from bit
22351 1 of the base address. */
22352 value
= (value
+ 3) & ~ 3;
22355 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
22356 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
22357 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22360 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
22362 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
22363 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22364 else if ((value
& ~0x1ffffff)
22365 && ((value
& ~0x1ffffff) != ~0x1ffffff))
22366 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22367 _("Thumb2 branch out of range"));
22370 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22371 encode_thumb2_b_bl_offset (buf
, value
);
22375 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22376 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
22377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
22379 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22380 encode_thumb2_b_bl_offset (buf
, value
);
22385 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22386 md_number_to_chars (buf
, value
, 1);
22390 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22391 md_number_to_chars (buf
, value
, 2);
22395 case BFD_RELOC_ARM_TLS_CALL
:
22396 case BFD_RELOC_ARM_THM_TLS_CALL
:
22397 case BFD_RELOC_ARM_TLS_DESCSEQ
:
22398 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
22399 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22402 case BFD_RELOC_ARM_TLS_GOTDESC
:
22403 case BFD_RELOC_ARM_TLS_GD32
:
22404 case BFD_RELOC_ARM_TLS_LE32
:
22405 case BFD_RELOC_ARM_TLS_IE32
:
22406 case BFD_RELOC_ARM_TLS_LDM32
:
22407 case BFD_RELOC_ARM_TLS_LDO32
:
22408 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
22411 case BFD_RELOC_ARM_GOT32
:
22412 case BFD_RELOC_ARM_GOTOFF
:
22413 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22414 md_number_to_chars (buf
, 0, 4);
22417 case BFD_RELOC_ARM_GOT_PREL
:
22418 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22419 md_number_to_chars (buf
, value
, 4);
22422 case BFD_RELOC_ARM_TARGET2
:
22423 /* TARGET2 is not partial-inplace, so we need to write the
22424 addend here for REL targets, because it won't be written out
22425 during reloc processing later. */
22426 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22427 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
22431 case BFD_RELOC_RVA
:
22433 case BFD_RELOC_ARM_TARGET1
:
22434 case BFD_RELOC_ARM_ROSEGREL32
:
22435 case BFD_RELOC_ARM_SBREL32
:
22436 case BFD_RELOC_32_PCREL
:
22438 case BFD_RELOC_32_SECREL
:
22440 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22442 /* For WinCE we only do this for pcrel fixups. */
22443 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
22445 md_number_to_chars (buf
, value
, 4);
22449 case BFD_RELOC_ARM_PREL31
:
22450 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22452 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
22453 if ((value
^ (value
>> 1)) & 0x40000000)
22455 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22456 _("rel31 relocation overflow"));
22458 newval
|= value
& 0x7fffffff;
22459 md_number_to_chars (buf
, newval
, 4);
22464 case BFD_RELOC_ARM_CP_OFF_IMM
:
22465 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22466 if (value
< -1023 || value
> 1023 || (value
& 3))
22467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22468 _("co-processor offset out of range"));
22473 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22474 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22475 newval
= md_chars_to_number (buf
, INSN_SIZE
);
22477 newval
= get_thumb32_insn (buf
);
22479 newval
&= 0xffffff00;
22482 newval
&= 0xff7fff00;
22483 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
22485 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22486 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
22487 md_number_to_chars (buf
, newval
, INSN_SIZE
);
22489 put_thumb32_insn (buf
, newval
);
22492 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
22493 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
22494 if (value
< -255 || value
> 255)
22495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22496 _("co-processor offset out of range"));
22498 goto cp_off_common
;
22500 case BFD_RELOC_ARM_THUMB_OFFSET
:
22501 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22502 /* Exactly what ranges, and where the offset is inserted depends
22503 on the type of instruction, we can establish this from the
22505 switch (newval
>> 12)
22507 case 4: /* PC load. */
22508 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
22509 forced to zero for these loads; md_pcrel_from has already
22510 compensated for this. */
22512 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22513 _("invalid offset, target not word aligned (0x%08lX)"),
22514 (((unsigned long) fixP
->fx_frag
->fr_address
22515 + (unsigned long) fixP
->fx_where
) & ~3)
22516 + (unsigned long) value
);
22518 if (value
& ~0x3fc)
22519 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22520 _("invalid offset, value too big (0x%08lX)"),
22523 newval
|= value
>> 2;
22526 case 9: /* SP load/store. */
22527 if (value
& ~0x3fc)
22528 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22529 _("invalid offset, value too big (0x%08lX)"),
22531 newval
|= value
>> 2;
22534 case 6: /* Word load/store. */
22536 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22537 _("invalid offset, value too big (0x%08lX)"),
22539 newval
|= value
<< 4; /* 6 - 2. */
22542 case 7: /* Byte load/store. */
22544 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22545 _("invalid offset, value too big (0x%08lX)"),
22547 newval
|= value
<< 6;
22550 case 8: /* Halfword load/store. */
22552 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22553 _("invalid offset, value too big (0x%08lX)"),
22555 newval
|= value
<< 5; /* 6 - 1. */
22559 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22560 "Unable to process relocation for thumb opcode: %lx",
22561 (unsigned long) newval
);
22564 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22567 case BFD_RELOC_ARM_THUMB_ADD
:
22568 /* This is a complicated relocation, since we use it for all of
22569 the following immediate relocations:
22573 9bit ADD/SUB SP word-aligned
22574 10bit ADD PC/SP word-aligned
22576 The type of instruction being processed is encoded in the
22583 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22585 int rd
= (newval
>> 4) & 0xf;
22586 int rs
= newval
& 0xf;
22587 int subtract
= !!(newval
& 0x8000);
22589 /* Check for HI regs, only very restricted cases allowed:
22590 Adjusting SP, and using PC or SP to get an address. */
22591 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
22592 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
22593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22594 _("invalid Hi register with immediate"));
22596 /* If value is negative, choose the opposite instruction. */
22600 subtract
= !subtract
;
22602 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22603 _("immediate value out of range"));
22608 if (value
& ~0x1fc)
22609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22610 _("invalid immediate for stack address calculation"));
22611 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
22612 newval
|= value
>> 2;
22614 else if (rs
== REG_PC
|| rs
== REG_SP
)
22616 if (subtract
|| value
& ~0x3fc)
22617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22618 _("invalid immediate for address calculation (value = 0x%08lX)"),
22619 (unsigned long) value
);
22620 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
22622 newval
|= value
>> 2;
22627 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22628 _("immediate value out of range"));
22629 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
22630 newval
|= (rd
<< 8) | value
;
22635 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22636 _("immediate value out of range"));
22637 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
22638 newval
|= rd
| (rs
<< 3) | (value
<< 6);
22641 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22644 case BFD_RELOC_ARM_THUMB_IMM
:
22645 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
22646 if (value
< 0 || value
> 255)
22647 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22648 _("invalid immediate: %ld is out of range"),
22651 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22654 case BFD_RELOC_ARM_THUMB_SHIFT
:
22655 /* 5bit shift value (0..32). LSL cannot take 32. */
22656 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
22657 temp
= newval
& 0xf800;
22658 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
22659 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22660 _("invalid shift value: %ld"), (long) value
);
22661 /* Shifts of zero must be encoded as LSL. */
22663 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
22664 /* Shifts of 32 are encoded as zero. */
22665 else if (value
== 32)
22667 newval
|= value
<< 6;
22668 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
22671 case BFD_RELOC_VTABLE_INHERIT
:
22672 case BFD_RELOC_VTABLE_ENTRY
:
22676 case BFD_RELOC_ARM_MOVW
:
22677 case BFD_RELOC_ARM_MOVT
:
22678 case BFD_RELOC_ARM_THUMB_MOVW
:
22679 case BFD_RELOC_ARM_THUMB_MOVT
:
22680 if (fixP
->fx_done
|| !seg
->use_rela_p
)
22682 /* REL format relocations are limited to a 16-bit addend. */
22683 if (!fixP
->fx_done
)
22685 if (value
< -0x8000 || value
> 0x7fff)
22686 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22687 _("offset out of range"));
22689 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22690 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22695 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22696 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
22698 newval
= get_thumb32_insn (buf
);
22699 newval
&= 0xfbf08f00;
22700 newval
|= (value
& 0xf000) << 4;
22701 newval
|= (value
& 0x0800) << 15;
22702 newval
|= (value
& 0x0700) << 4;
22703 newval
|= (value
& 0x00ff);
22704 put_thumb32_insn (buf
, newval
);
22708 newval
= md_chars_to_number (buf
, 4);
22709 newval
&= 0xfff0f000;
22710 newval
|= value
& 0x0fff;
22711 newval
|= (value
& 0xf000) << 4;
22712 md_number_to_chars (buf
, newval
, 4);
22717 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
22718 case BFD_RELOC_ARM_ALU_PC_G0
:
22719 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
22720 case BFD_RELOC_ARM_ALU_PC_G1
:
22721 case BFD_RELOC_ARM_ALU_PC_G2
:
22722 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
22723 case BFD_RELOC_ARM_ALU_SB_G0
:
22724 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
22725 case BFD_RELOC_ARM_ALU_SB_G1
:
22726 case BFD_RELOC_ARM_ALU_SB_G2
:
22727 gas_assert (!fixP
->fx_done
);
22728 if (!seg
->use_rela_p
)
22731 bfd_vma encoded_addend
;
22732 bfd_vma addend_abs
= abs (value
);
22734 /* Check that the absolute value of the addend can be
22735 expressed as an 8-bit constant plus a rotation. */
22736 encoded_addend
= encode_arm_immediate (addend_abs
);
22737 if (encoded_addend
== (unsigned int) FAIL
)
22738 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22739 _("the offset 0x%08lX is not representable"),
22740 (unsigned long) addend_abs
);
22742 /* Extract the instruction. */
22743 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22745 /* If the addend is positive, use an ADD instruction.
22746 Otherwise use a SUB. Take care not to destroy the S bit. */
22747 insn
&= 0xff1fffff;
22753 /* Place the encoded addend into the first 12 bits of the
22755 insn
&= 0xfffff000;
22756 insn
|= encoded_addend
;
22758 /* Update the instruction. */
22759 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22763 case BFD_RELOC_ARM_LDR_PC_G0
:
22764 case BFD_RELOC_ARM_LDR_PC_G1
:
22765 case BFD_RELOC_ARM_LDR_PC_G2
:
22766 case BFD_RELOC_ARM_LDR_SB_G0
:
22767 case BFD_RELOC_ARM_LDR_SB_G1
:
22768 case BFD_RELOC_ARM_LDR_SB_G2
:
22769 gas_assert (!fixP
->fx_done
);
22770 if (!seg
->use_rela_p
)
22773 bfd_vma addend_abs
= abs (value
);
22775 /* Check that the absolute value of the addend can be
22776 encoded in 12 bits. */
22777 if (addend_abs
>= 0x1000)
22778 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22779 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
22780 (unsigned long) addend_abs
);
22782 /* Extract the instruction. */
22783 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22785 /* If the addend is negative, clear bit 23 of the instruction.
22786 Otherwise set it. */
22788 insn
&= ~(1 << 23);
22792 /* Place the absolute value of the addend into the first 12 bits
22793 of the instruction. */
22794 insn
&= 0xfffff000;
22795 insn
|= addend_abs
;
22797 /* Update the instruction. */
22798 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22802 case BFD_RELOC_ARM_LDRS_PC_G0
:
22803 case BFD_RELOC_ARM_LDRS_PC_G1
:
22804 case BFD_RELOC_ARM_LDRS_PC_G2
:
22805 case BFD_RELOC_ARM_LDRS_SB_G0
:
22806 case BFD_RELOC_ARM_LDRS_SB_G1
:
22807 case BFD_RELOC_ARM_LDRS_SB_G2
:
22808 gas_assert (!fixP
->fx_done
);
22809 if (!seg
->use_rela_p
)
22812 bfd_vma addend_abs
= abs (value
);
22814 /* Check that the absolute value of the addend can be
22815 encoded in 8 bits. */
22816 if (addend_abs
>= 0x100)
22817 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22818 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
22819 (unsigned long) addend_abs
);
22821 /* Extract the instruction. */
22822 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22824 /* If the addend is negative, clear bit 23 of the instruction.
22825 Otherwise set it. */
22827 insn
&= ~(1 << 23);
22831 /* Place the first four bits of the absolute value of the addend
22832 into the first 4 bits of the instruction, and the remaining
22833 four into bits 8 .. 11. */
22834 insn
&= 0xfffff0f0;
22835 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
22837 /* Update the instruction. */
22838 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22842 case BFD_RELOC_ARM_LDC_PC_G0
:
22843 case BFD_RELOC_ARM_LDC_PC_G1
:
22844 case BFD_RELOC_ARM_LDC_PC_G2
:
22845 case BFD_RELOC_ARM_LDC_SB_G0
:
22846 case BFD_RELOC_ARM_LDC_SB_G1
:
22847 case BFD_RELOC_ARM_LDC_SB_G2
:
22848 gas_assert (!fixP
->fx_done
);
22849 if (!seg
->use_rela_p
)
22852 bfd_vma addend_abs
= abs (value
);
22854 /* Check that the absolute value of the addend is a multiple of
22855 four and, when divided by four, fits in 8 bits. */
22856 if (addend_abs
& 0x3)
22857 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22858 _("bad offset 0x%08lX (must be word-aligned)"),
22859 (unsigned long) addend_abs
);
22861 if ((addend_abs
>> 2) > 0xff)
22862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22863 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
22864 (unsigned long) addend_abs
);
22866 /* Extract the instruction. */
22867 insn
= md_chars_to_number (buf
, INSN_SIZE
);
22869 /* If the addend is negative, clear bit 23 of the instruction.
22870 Otherwise set it. */
22872 insn
&= ~(1 << 23);
22876 /* Place the addend (divided by four) into the first eight
22877 bits of the instruction. */
22878 insn
&= 0xfffffff0;
22879 insn
|= addend_abs
>> 2;
22881 /* Update the instruction. */
22882 md_number_to_chars (buf
, insn
, INSN_SIZE
);
22886 case BFD_RELOC_ARM_V4BX
:
22887 /* This will need to go in the object file. */
22891 case BFD_RELOC_UNUSED
:
22893 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
22894 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
22898 /* Translate internal representation of relocation info to BFD target
22902 tc_gen_reloc (asection
*section
, fixS
*fixp
)
22905 bfd_reloc_code_real_type code
;
22907 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
22909 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
22910 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
22911 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
22913 if (fixp
->fx_pcrel
)
22915 if (section
->use_rela_p
)
22916 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
22918 fixp
->fx_offset
= reloc
->address
;
22920 reloc
->addend
= fixp
->fx_offset
;
22922 switch (fixp
->fx_r_type
)
22925 if (fixp
->fx_pcrel
)
22927 code
= BFD_RELOC_8_PCREL
;
22932 if (fixp
->fx_pcrel
)
22934 code
= BFD_RELOC_16_PCREL
;
22939 if (fixp
->fx_pcrel
)
22941 code
= BFD_RELOC_32_PCREL
;
22945 case BFD_RELOC_ARM_MOVW
:
22946 if (fixp
->fx_pcrel
)
22948 code
= BFD_RELOC_ARM_MOVW_PCREL
;
22952 case BFD_RELOC_ARM_MOVT
:
22953 if (fixp
->fx_pcrel
)
22955 code
= BFD_RELOC_ARM_MOVT_PCREL
;
22959 case BFD_RELOC_ARM_THUMB_MOVW
:
22960 if (fixp
->fx_pcrel
)
22962 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
22966 case BFD_RELOC_ARM_THUMB_MOVT
:
22967 if (fixp
->fx_pcrel
)
22969 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
22973 case BFD_RELOC_NONE
:
22974 case BFD_RELOC_ARM_PCREL_BRANCH
:
22975 case BFD_RELOC_ARM_PCREL_BLX
:
22976 case BFD_RELOC_RVA
:
22977 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22978 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22979 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22980 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22981 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22982 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22983 case BFD_RELOC_VTABLE_ENTRY
:
22984 case BFD_RELOC_VTABLE_INHERIT
:
22986 case BFD_RELOC_32_SECREL
:
22988 code
= fixp
->fx_r_type
;
22991 case BFD_RELOC_THUMB_PCREL_BLX
:
22993 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
22994 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
22997 code
= BFD_RELOC_THUMB_PCREL_BLX
;
23000 case BFD_RELOC_ARM_LITERAL
:
23001 case BFD_RELOC_ARM_HWLITERAL
:
23002 /* If this is called then the a literal has
23003 been referenced across a section boundary. */
23004 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23005 _("literal referenced across section boundary"));
23009 case BFD_RELOC_ARM_TLS_CALL
:
23010 case BFD_RELOC_ARM_THM_TLS_CALL
:
23011 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23012 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23013 case BFD_RELOC_ARM_GOT32
:
23014 case BFD_RELOC_ARM_GOTOFF
:
23015 case BFD_RELOC_ARM_GOT_PREL
:
23016 case BFD_RELOC_ARM_PLT32
:
23017 case BFD_RELOC_ARM_TARGET1
:
23018 case BFD_RELOC_ARM_ROSEGREL32
:
23019 case BFD_RELOC_ARM_SBREL32
:
23020 case BFD_RELOC_ARM_PREL31
:
23021 case BFD_RELOC_ARM_TARGET2
:
23022 case BFD_RELOC_ARM_TLS_LE32
:
23023 case BFD_RELOC_ARM_TLS_LDO32
:
23024 case BFD_RELOC_ARM_PCREL_CALL
:
23025 case BFD_RELOC_ARM_PCREL_JUMP
:
23026 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
23027 case BFD_RELOC_ARM_ALU_PC_G0
:
23028 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
23029 case BFD_RELOC_ARM_ALU_PC_G1
:
23030 case BFD_RELOC_ARM_ALU_PC_G2
:
23031 case BFD_RELOC_ARM_LDR_PC_G0
:
23032 case BFD_RELOC_ARM_LDR_PC_G1
:
23033 case BFD_RELOC_ARM_LDR_PC_G2
:
23034 case BFD_RELOC_ARM_LDRS_PC_G0
:
23035 case BFD_RELOC_ARM_LDRS_PC_G1
:
23036 case BFD_RELOC_ARM_LDRS_PC_G2
:
23037 case BFD_RELOC_ARM_LDC_PC_G0
:
23038 case BFD_RELOC_ARM_LDC_PC_G1
:
23039 case BFD_RELOC_ARM_LDC_PC_G2
:
23040 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
23041 case BFD_RELOC_ARM_ALU_SB_G0
:
23042 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
23043 case BFD_RELOC_ARM_ALU_SB_G1
:
23044 case BFD_RELOC_ARM_ALU_SB_G2
:
23045 case BFD_RELOC_ARM_LDR_SB_G0
:
23046 case BFD_RELOC_ARM_LDR_SB_G1
:
23047 case BFD_RELOC_ARM_LDR_SB_G2
:
23048 case BFD_RELOC_ARM_LDRS_SB_G0
:
23049 case BFD_RELOC_ARM_LDRS_SB_G1
:
23050 case BFD_RELOC_ARM_LDRS_SB_G2
:
23051 case BFD_RELOC_ARM_LDC_SB_G0
:
23052 case BFD_RELOC_ARM_LDC_SB_G1
:
23053 case BFD_RELOC_ARM_LDC_SB_G2
:
23054 case BFD_RELOC_ARM_V4BX
:
23055 code
= fixp
->fx_r_type
;
23058 case BFD_RELOC_ARM_TLS_GOTDESC
:
23059 case BFD_RELOC_ARM_TLS_GD32
:
23060 case BFD_RELOC_ARM_TLS_IE32
:
23061 case BFD_RELOC_ARM_TLS_LDM32
:
23062 /* BFD will include the symbol's address in the addend.
23063 But we don't want that, so subtract it out again here. */
23064 if (!S_IS_COMMON (fixp
->fx_addsy
))
23065 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
23066 code
= fixp
->fx_r_type
;
23070 case BFD_RELOC_ARM_IMMEDIATE
:
23071 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23072 _("internal relocation (type: IMMEDIATE) not fixed up"));
23075 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23076 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23077 _("ADRL used for a symbol not defined in the same file"));
23080 case BFD_RELOC_ARM_OFFSET_IMM
:
23081 if (section
->use_rela_p
)
23083 code
= fixp
->fx_r_type
;
23087 if (fixp
->fx_addsy
!= NULL
23088 && !S_IS_DEFINED (fixp
->fx_addsy
)
23089 && S_IS_LOCAL (fixp
->fx_addsy
))
23091 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23092 _("undefined local label `%s'"),
23093 S_GET_NAME (fixp
->fx_addsy
));
23097 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23098 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
23105 switch (fixp
->fx_r_type
)
23107 case BFD_RELOC_NONE
: type
= "NONE"; break;
23108 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
23109 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
23110 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
23111 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
23112 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
23113 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
23114 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
23115 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
23116 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
23117 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
23118 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
23119 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
23120 default: type
= _("<unknown>"); break;
23122 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23123 _("cannot represent %s relocation in this object file format"),
23130 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
23132 && fixp
->fx_addsy
== GOT_symbol
)
23134 code
= BFD_RELOC_ARM_GOTPC
;
23135 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
23139 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
23141 if (reloc
->howto
== NULL
)
23143 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
23144 _("cannot represent %s relocation in this object file format"),
23145 bfd_get_reloc_code_name (code
));
23149 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
23150 vtable entry to be used in the relocation's section offset. */
23151 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23152 reloc
->address
= fixp
->fx_offset
;
23157 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
23160 cons_fix_new_arm (fragS
* frag
,
23164 bfd_reloc_code_real_type reloc
)
23169 FIXME: @@ Should look at CPU word size. */
23173 reloc
= BFD_RELOC_8
;
23176 reloc
= BFD_RELOC_16
;
23180 reloc
= BFD_RELOC_32
;
23183 reloc
= BFD_RELOC_64
;
23188 if (exp
->X_op
== O_secrel
)
23190 exp
->X_op
= O_symbol
;
23191 reloc
= BFD_RELOC_32_SECREL
;
23195 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
23198 #if defined (OBJ_COFF)
23200 arm_validate_fix (fixS
* fixP
)
23202 /* If the destination of the branch is a defined symbol which does not have
23203 the THUMB_FUNC attribute, then we must be calling a function which has
23204 the (interfacearm) attribute. We look for the Thumb entry point to that
23205 function and change the branch to refer to that function instead. */
23206 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
23207 && fixP
->fx_addsy
!= NULL
23208 && S_IS_DEFINED (fixP
->fx_addsy
)
23209 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
23211 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
23218 arm_force_relocation (struct fix
* fixp
)
23220 #if defined (OBJ_COFF) && defined (TE_PE)
23221 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
23225 /* In case we have a call or a branch to a function in ARM ISA mode from
23226 a thumb function or vice-versa force the relocation. These relocations
23227 are cleared off for some cores that might have blx and simple transformations
23231 switch (fixp
->fx_r_type
)
23233 case BFD_RELOC_ARM_PCREL_JUMP
:
23234 case BFD_RELOC_ARM_PCREL_CALL
:
23235 case BFD_RELOC_THUMB_PCREL_BLX
:
23236 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
23240 case BFD_RELOC_ARM_PCREL_BLX
:
23241 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23242 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23243 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23244 if (ARM_IS_FUNC (fixp
->fx_addsy
))
23253 /* Resolve these relocations even if the symbol is extern or weak.
23254 Technically this is probably wrong due to symbol preemption.
23255 In practice these relocations do not have enough range to be useful
23256 at dynamic link time, and some code (e.g. in the Linux kernel)
23257 expects these references to be resolved. */
23258 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
23259 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
23260 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
23261 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
23262 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
23263 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
23264 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
23265 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
23266 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23267 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
23268 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
23269 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
23270 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
23271 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
23274 /* Always leave these relocations for the linker. */
23275 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23276 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23277 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23280 /* Always generate relocations against function symbols. */
23281 if (fixp
->fx_r_type
== BFD_RELOC_32
23283 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
23286 return generic_force_reloc (fixp
);
23289 #if defined (OBJ_ELF) || defined (OBJ_COFF)
23290 /* Relocations against function names must be left unadjusted,
23291 so that the linker can use this information to generate interworking
23292 stubs. The MIPS version of this function
23293 also prevents relocations that are mips-16 specific, but I do not
23294 know why it does this.
23297 There is one other problem that ought to be addressed here, but
23298 which currently is not: Taking the address of a label (rather
23299 than a function) and then later jumping to that address. Such
23300 addresses also ought to have their bottom bit set (assuming that
23301 they reside in Thumb code), but at the moment they will not. */
23304 arm_fix_adjustable (fixS
* fixP
)
23306 if (fixP
->fx_addsy
== NULL
)
23309 /* Preserve relocations against symbols with function type. */
23310 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
23313 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
23314 && fixP
->fx_subsy
== NULL
)
23317 /* We need the symbol name for the VTABLE entries. */
23318 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
23319 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
23322 /* Don't allow symbols to be discarded on GOT related relocs. */
23323 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
23324 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
23325 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
23326 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
23327 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
23328 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
23329 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
23330 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
23331 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
23332 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
23333 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
23334 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
23335 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
23336 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
23339 /* Similarly for group relocations. */
23340 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
23341 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
23342 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
23345 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
23346 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
23347 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
23348 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
23349 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
23350 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
23351 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
23352 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
23353 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
23358 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
23363 elf32_arm_target_format (void)
23366 return (target_big_endian
23367 ? "elf32-bigarm-symbian"
23368 : "elf32-littlearm-symbian");
23369 #elif defined (TE_VXWORKS)
23370 return (target_big_endian
23371 ? "elf32-bigarm-vxworks"
23372 : "elf32-littlearm-vxworks");
23373 #elif defined (TE_NACL)
23374 return (target_big_endian
23375 ? "elf32-bigarm-nacl"
23376 : "elf32-littlearm-nacl");
23378 if (target_big_endian
)
23379 return "elf32-bigarm";
23381 return "elf32-littlearm";
23386 armelf_frob_symbol (symbolS
* symp
,
23389 elf_frob_symbol (symp
, puntp
);
23393 /* MD interface: Finalization. */
23398 literal_pool
* pool
;
23400 /* Ensure that all the IT blocks are properly closed. */
23401 check_it_blocks_finished ();
23403 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
23405 /* Put it at the end of the relevant section. */
23406 subseg_set (pool
->section
, pool
->sub_section
);
23408 arm_elf_change_section ();
23415 /* Remove any excess mapping symbols generated for alignment frags in
23416 SEC. We may have created a mapping symbol before a zero byte
23417 alignment; remove it if there's a mapping symbol after the
23420 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
23421 void *dummy ATTRIBUTE_UNUSED
)
23423 segment_info_type
*seginfo
= seg_info (sec
);
23426 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
23429 for (fragp
= seginfo
->frchainP
->frch_root
;
23431 fragp
= fragp
->fr_next
)
23433 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
23434 fragS
*next
= fragp
->fr_next
;
23436 /* Variable-sized frags have been converted to fixed size by
23437 this point. But if this was variable-sized to start with,
23438 there will be a fixed-size frag after it. So don't handle
23440 if (sym
== NULL
|| next
== NULL
)
23443 if (S_GET_VALUE (sym
) < next
->fr_address
)
23444 /* Not at the end of this frag. */
23446 know (S_GET_VALUE (sym
) == next
->fr_address
);
23450 if (next
->tc_frag_data
.first_map
!= NULL
)
23452 /* Next frag starts with a mapping symbol. Discard this
23454 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23458 if (next
->fr_next
== NULL
)
23460 /* This mapping symbol is at the end of the section. Discard
23462 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
23463 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
23467 /* As long as we have empty frags without any mapping symbols,
23469 /* If the next frag is non-empty and does not start with a
23470 mapping symbol, then this mapping symbol is required. */
23471 if (next
->fr_address
!= next
->fr_next
->fr_address
)
23474 next
= next
->fr_next
;
23476 while (next
!= NULL
);
23481 /* Adjust the symbol table. This marks Thumb symbols as distinct from
23485 arm_adjust_symtab (void)
23490 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23492 if (ARM_IS_THUMB (sym
))
23494 if (THUMB_IS_FUNC (sym
))
23496 /* Mark the symbol as a Thumb function. */
23497 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
23498 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
23499 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
23501 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
23502 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
23504 as_bad (_("%s: unexpected function type: %d"),
23505 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
23507 else switch (S_GET_STORAGE_CLASS (sym
))
23510 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
23513 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
23516 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
23524 if (ARM_IS_INTERWORK (sym
))
23525 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
23532 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
23534 if (ARM_IS_THUMB (sym
))
23536 elf_symbol_type
* elf_sym
;
23538 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
23539 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
23541 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
23542 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
23544 /* If it's a .thumb_func, declare it as so,
23545 otherwise tag label as .code 16. */
23546 if (THUMB_IS_FUNC (sym
))
23547 elf_sym
->internal_elf_sym
.st_target_internal
23548 = ST_BRANCH_TO_THUMB
;
23549 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23550 elf_sym
->internal_elf_sym
.st_info
=
23551 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
23556 /* Remove any overlapping mapping symbols generated by alignment frags. */
23557 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
23558 /* Now do generic ELF adjustments. */
23559 elf_adjust_symtab ();
23563 /* MD interface: Initialization. */
23566 set_constant_flonums (void)
23570 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
23571 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
23575 /* Auto-select Thumb mode if it's the only available instruction set for the
23576 given architecture. */
23579 autoselect_thumb_from_cpu_variant (void)
23581 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
23582 opcode_select (16);
23591 if ( (arm_ops_hsh
= hash_new ()) == NULL
23592 || (arm_cond_hsh
= hash_new ()) == NULL
23593 || (arm_shift_hsh
= hash_new ()) == NULL
23594 || (arm_psr_hsh
= hash_new ()) == NULL
23595 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
23596 || (arm_reg_hsh
= hash_new ()) == NULL
23597 || (arm_reloc_hsh
= hash_new ()) == NULL
23598 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
23599 as_fatal (_("virtual memory exhausted"));
23601 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
23602 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
23603 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
23604 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
23605 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
23606 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
23607 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
23608 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
23609 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
23610 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
23611 (void *) (v7m_psrs
+ i
));
23612 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
23613 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
23615 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
23617 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
23618 (void *) (barrier_opt_names
+ i
));
23620 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
23622 struct reloc_entry
* entry
= reloc_names
+ i
;
23624 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
23625 /* This makes encode_branch() use the EABI versions of this relocation. */
23626 entry
->reloc
= BFD_RELOC_UNUSED
;
23628 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
23632 set_constant_flonums ();
23634 /* Set the cpu variant based on the command-line options. We prefer
23635 -mcpu= over -march= if both are set (as for GCC); and we prefer
23636 -mfpu= over any other way of setting the floating point unit.
23637 Use of legacy options with new options are faulted. */
23640 if (mcpu_cpu_opt
|| march_cpu_opt
)
23641 as_bad (_("use of old and new-style options to set CPU type"));
23643 mcpu_cpu_opt
= legacy_cpu
;
23645 else if (!mcpu_cpu_opt
)
23646 mcpu_cpu_opt
= march_cpu_opt
;
23651 as_bad (_("use of old and new-style options to set FPU type"));
23653 mfpu_opt
= legacy_fpu
;
23655 else if (!mfpu_opt
)
23657 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
23658 || defined (TE_NetBSD) || defined (TE_VXWORKS))
23659 /* Some environments specify a default FPU. If they don't, infer it
23660 from the processor. */
23662 mfpu_opt
= mcpu_fpu_opt
;
23664 mfpu_opt
= march_fpu_opt
;
23666 mfpu_opt
= &fpu_default
;
23672 if (mcpu_cpu_opt
!= NULL
)
23673 mfpu_opt
= &fpu_default
;
23674 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
23675 mfpu_opt
= &fpu_arch_vfp_v2
;
23677 mfpu_opt
= &fpu_arch_fpa
;
23683 mcpu_cpu_opt
= &cpu_default
;
23684 selected_cpu
= cpu_default
;
23688 selected_cpu
= *mcpu_cpu_opt
;
23690 mcpu_cpu_opt
= &arm_arch_any
;
23693 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23695 autoselect_thumb_from_cpu_variant ();
23697 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
23699 #if defined OBJ_COFF || defined OBJ_ELF
23701 unsigned int flags
= 0;
23703 #if defined OBJ_ELF
23704 flags
= meabi_flags
;
23706 switch (meabi_flags
)
23708 case EF_ARM_EABI_UNKNOWN
:
23710 /* Set the flags in the private structure. */
23711 if (uses_apcs_26
) flags
|= F_APCS26
;
23712 if (support_interwork
) flags
|= F_INTERWORK
;
23713 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
23714 if (pic_code
) flags
|= F_PIC
;
23715 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
23716 flags
|= F_SOFT_FLOAT
;
23718 switch (mfloat_abi_opt
)
23720 case ARM_FLOAT_ABI_SOFT
:
23721 case ARM_FLOAT_ABI_SOFTFP
:
23722 flags
|= F_SOFT_FLOAT
;
23725 case ARM_FLOAT_ABI_HARD
:
23726 if (flags
& F_SOFT_FLOAT
)
23727 as_bad (_("hard-float conflicts with specified fpu"));
23731 /* Using pure-endian doubles (even if soft-float). */
23732 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
23733 flags
|= F_VFP_FLOAT
;
23735 #if defined OBJ_ELF
23736 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
23737 flags
|= EF_ARM_MAVERICK_FLOAT
;
23740 case EF_ARM_EABI_VER4
:
23741 case EF_ARM_EABI_VER5
:
23742 /* No additional flags to set. */
23749 bfd_set_private_flags (stdoutput
, flags
);
23751 /* We have run out flags in the COFF header to encode the
23752 status of ATPCS support, so instead we create a dummy,
23753 empty, debug section called .arm.atpcs. */
23758 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
23762 bfd_set_section_flags
23763 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
23764 bfd_set_section_size (stdoutput
, sec
, 0);
23765 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
23771 /* Record the CPU type as well. */
23772 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
23773 mach
= bfd_mach_arm_iWMMXt2
;
23774 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
23775 mach
= bfd_mach_arm_iWMMXt
;
23776 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
23777 mach
= bfd_mach_arm_XScale
;
23778 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
23779 mach
= bfd_mach_arm_ep9312
;
23780 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
23781 mach
= bfd_mach_arm_5TE
;
23782 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
23784 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
23785 mach
= bfd_mach_arm_5T
;
23787 mach
= bfd_mach_arm_5
;
23789 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
23791 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
23792 mach
= bfd_mach_arm_4T
;
23794 mach
= bfd_mach_arm_4
;
23796 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
23797 mach
= bfd_mach_arm_3M
;
23798 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
23799 mach
= bfd_mach_arm_3
;
23800 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
23801 mach
= bfd_mach_arm_2a
;
23802 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
23803 mach
= bfd_mach_arm_2
;
23805 mach
= bfd_mach_arm_unknown
;
23807 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
23810 /* Command line processing. */
23813 Invocation line includes a switch not recognized by the base assembler.
23814 See if it's a processor-specific option.
23816 This routine is somewhat complicated by the need for backwards
23817 compatibility (since older releases of gcc can't be changed).
23818 The new options try to make the interface as compatible as
23821 New options (supported) are:
23823 -mcpu=<cpu name> Assemble for selected processor
23824 -march=<architecture name> Assemble for selected architecture
23825 -mfpu=<fpu architecture> Assemble for selected FPU.
23826 -EB/-mbig-endian Big-endian
23827 -EL/-mlittle-endian Little-endian
23828 -k Generate PIC code
23829 -mthumb Start in Thumb mode
23830 -mthumb-interwork Code supports ARM/Thumb interworking
23832 -m[no-]warn-deprecated Warn about deprecated features
23834 For now we will also provide support for:
23836 -mapcs-32 32-bit Program counter
23837 -mapcs-26 26-bit Program counter
23838 -macps-float Floats passed in FP registers
23839 -mapcs-reentrant Reentrant code
23841 (sometime these will probably be replaced with -mapcs=<list of options>
23842 and -matpcs=<list of options>)
23844 The remaining options are only supported for back-wards compatibility.
23845 Cpu variants, the arm part is optional:
23846 -m[arm]1 Currently not supported.
23847 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
23848 -m[arm]3 Arm 3 processor
23849 -m[arm]6[xx], Arm 6 processors
23850 -m[arm]7[xx][t][[d]m] Arm 7 processors
23851 -m[arm]8[10] Arm 8 processors
23852 -m[arm]9[20][tdmi] Arm 9 processors
23853 -mstrongarm[110[0]] StrongARM processors
23854 -mxscale XScale processors
23855 -m[arm]v[2345[t[e]]] Arm architectures
23856 -mall All (except the ARM1)
23858 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
23859 -mfpe-old (No float load/store multiples)
23860 -mvfpxd VFP Single precision
23862 -mno-fpu Disable all floating point instructions
23864 The following CPU names are recognized:
23865 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
23866 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
23867 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
23868 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
23869 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
23870 arm10t arm10e, arm1020t, arm1020e, arm10200e,
23871 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
23875 const char * md_shortopts
= "m:k";
23877 #ifdef ARM_BI_ENDIAN
23878 #define OPTION_EB (OPTION_MD_BASE + 0)
23879 #define OPTION_EL (OPTION_MD_BASE + 1)
23881 #if TARGET_BYTES_BIG_ENDIAN
23882 #define OPTION_EB (OPTION_MD_BASE + 0)
23884 #define OPTION_EL (OPTION_MD_BASE + 1)
23887 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
23889 struct option md_longopts
[] =
23892 {"EB", no_argument
, NULL
, OPTION_EB
},
23895 {"EL", no_argument
, NULL
, OPTION_EL
},
23897 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
23898 {NULL
, no_argument
, NULL
, 0}
23901 size_t md_longopts_size
= sizeof (md_longopts
);
23903 struct arm_option_table
23905 char *option
; /* Option name to match. */
23906 char *help
; /* Help information. */
23907 int *var
; /* Variable to change. */
23908 int value
; /* What to change it to. */
23909 char *deprecated
; /* If non-null, print this message. */
23912 struct arm_option_table arm_opts
[] =
23914 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
23915 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
23916 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
23917 &support_interwork
, 1, NULL
},
23918 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
23919 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
23920 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
23922 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
23923 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
23924 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
23925 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
23928 /* These are recognized by the assembler, but have no affect on code. */
23929 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
23930 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
23932 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
23933 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
23934 &warn_on_deprecated
, 0, NULL
},
23935 {NULL
, NULL
, NULL
, 0, NULL
}
23938 struct arm_legacy_option_table
23940 char *option
; /* Option name to match. */
23941 const arm_feature_set
**var
; /* Variable to change. */
23942 const arm_feature_set value
; /* What to change it to. */
23943 char *deprecated
; /* If non-null, print this message. */
23946 const struct arm_legacy_option_table arm_legacy_opts
[] =
23948 /* DON'T add any new processors to this list -- we want the whole list
23949 to go away... Add them to the processors table instead. */
23950 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23951 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
23952 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23953 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
23954 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23955 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
23956 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23957 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
23958 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23959 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
23960 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23961 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
23962 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23963 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
23964 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23965 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
23966 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23967 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
23968 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23969 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
23970 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23971 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
23972 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23973 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
23974 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23975 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
23976 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23977 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
23978 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23979 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
23980 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23981 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
23982 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23983 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
23984 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23985 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
23986 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23987 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
23988 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23989 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
23990 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23991 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
23992 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23993 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
23994 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23995 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
23996 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23997 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23998 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
23999 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
24000 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24001 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
24002 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24003 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
24004 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24005 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
24006 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24007 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
24008 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24009 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
24010 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24011 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
24012 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24013 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
24014 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24015 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
24016 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24017 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
24018 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
24019 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
24020 N_("use -mcpu=strongarm110")},
24021 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
24022 N_("use -mcpu=strongarm1100")},
24023 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
24024 N_("use -mcpu=strongarm1110")},
24025 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
24026 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
24027 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
24029 /* Architecture variants -- don't add any more to this list either. */
24030 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24031 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
24032 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24033 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
24034 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24035 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
24036 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24037 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
24038 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24039 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
24040 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24041 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
24042 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24043 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
24044 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24045 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
24046 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24047 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
24049 /* Floating point variants -- don't add any more to this list either. */
24050 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
24051 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
24052 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
24053 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
24054 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
24056 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
24059 struct arm_cpu_option_table
24063 const arm_feature_set value
;
24064 /* For some CPUs we assume an FPU unless the user explicitly sets
24066 const arm_feature_set default_fpu
;
24067 /* The canonical name of the CPU, or NULL to use NAME converted to upper
24069 const char *canonical_name
;
24072 /* This list should, at a minimum, contain all the cpu names
24073 recognized by GCC. */
24074 #define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
24075 static const struct arm_cpu_option_table arm_cpus
[] =
24077 ARM_CPU_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
, NULL
),
24078 ARM_CPU_OPT ("arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
),
24079 ARM_CPU_OPT ("arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
),
24080 ARM_CPU_OPT ("arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24081 ARM_CPU_OPT ("arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
),
24082 ARM_CPU_OPT ("arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24083 ARM_CPU_OPT ("arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24084 ARM_CPU_OPT ("arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24085 ARM_CPU_OPT ("arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24086 ARM_CPU_OPT ("arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24087 ARM_CPU_OPT ("arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24088 ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24089 ARM_CPU_OPT ("arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24090 ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24091 ARM_CPU_OPT ("arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24092 ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
),
24093 ARM_CPU_OPT ("arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24094 ARM_CPU_OPT ("arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24095 ARM_CPU_OPT ("arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24096 ARM_CPU_OPT ("arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24097 ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24098 ARM_CPU_OPT ("arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24099 ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24100 ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24101 ARM_CPU_OPT ("arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24102 ARM_CPU_OPT ("arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24103 ARM_CPU_OPT ("arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24104 ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
),
24105 ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24106 ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24107 ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24108 ARM_CPU_OPT ("arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24109 ARM_CPU_OPT ("arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24110 ARM_CPU_OPT ("strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24111 ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24112 ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24113 ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24114 ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24115 ARM_CPU_OPT ("arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24116 ARM_CPU_OPT ("arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"),
24117 ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24118 ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24119 ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24120 ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
),
24121 ARM_CPU_OPT ("fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24122 ARM_CPU_OPT ("fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
),
24123 /* For V5 or later processors we default to using VFP; but the user
24124 should really set the FPU type explicitly. */
24125 ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24126 ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24127 ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24128 ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"),
24129 ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24130 ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24131 ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"),
24132 ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24133 ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
),
24134 ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"),
24135 ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24136 ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24137 ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24138 ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24139 ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24140 ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"),
24141 ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
),
24142 ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24143 ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24144 ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
,
24146 ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
),
24147 ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24148 ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24149 ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24150 ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24151 ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
),
24152 ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"),
24153 ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
),
24154 ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
,
24156 ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
),
24157 ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"),
24158 ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"),
24159 ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
),
24160 ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
),
24161 ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
),
24162 ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
),
24163 ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC
,
24164 FPU_NONE
, "Cortex-A5"),
24165 ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24167 ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC
,
24168 ARM_FEATURE (0, FPU_VFP_V3
24169 | FPU_NEON_EXT_V1
),
24171 ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC
,
24172 ARM_FEATURE (0, FPU_VFP_V3
24173 | FPU_NEON_EXT_V1
),
24175 ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24177 ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE
, FPU_ARCH_NEON_VFP_V4
,
24179 ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24181 ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A
, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24183 ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"),
24184 ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
24186 ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV
,
24187 FPU_NONE
, "Cortex-R5"),
24188 ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV
,
24189 FPU_ARCH_VFP_V3D16
,
24191 ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"),
24192 ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"),
24193 ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"),
24194 ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"),
24195 ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0+"),
24196 /* ??? XSCALE is really an architecture. */
24197 ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24198 /* ??? iwmmxt is not a processor. */
24199 ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
),
24200 ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
),
24201 ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
),
24203 ARM_CPU_OPT ("ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
24204 FPU_ARCH_MAVERICK
, "ARM920T"),
24205 /* Marvell processors. */
24206 ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE (ARM_AEXT_V7A
| ARM_EXT_MP
| ARM_EXT_SEC
, 0),
24207 FPU_ARCH_VFP_V3D16
, NULL
),
24209 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
24213 struct arm_arch_option_table
24217 const arm_feature_set value
;
24218 const arm_feature_set default_fpu
;
24221 /* This list should, at a minimum, contain all the architecture names
24222 recognized by GCC. */
24223 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
24224 static const struct arm_arch_option_table arm_archs
[] =
24226 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
24227 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
24228 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
24229 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24230 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
24231 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
24232 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
24233 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
24234 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
24235 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
24236 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
24237 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
24238 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
24239 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
24240 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
24241 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
24242 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
24243 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24244 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
24245 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
24246 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
24247 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
),
24248 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
24249 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
24250 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
24251 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
),
24252 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
24253 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
24254 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
24255 /* The official spelling of the ARMv7 profile variants is the dashed form.
24256 Accept the non-dashed form for compatibility with old toolchains. */
24257 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24258 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
24259 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24260 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24261 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
24262 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
24263 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
24264 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
24265 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
24266 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
24267 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
24268 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
24269 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24271 #undef ARM_ARCH_OPT
24273 /* ISA extensions in the co-processor and main instruction set space. */
24274 struct arm_option_extension_value_table
24278 const arm_feature_set value
;
24279 const arm_feature_set allowed_archs
;
24282 /* The following table must be in alphabetical order with a NULL last entry.
24284 #define ARM_EXT_OPT(N, V, AA) { N, sizeof (N) - 1, V, AA }
24285 static const struct arm_option_extension_value_table arm_extensions
[] =
24287 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE (ARM_EXT_V8
, 0)),
24288 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
24289 ARM_FEATURE (ARM_EXT_V8
, 0)),
24290 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
,
24291 ARM_FEATURE (ARM_EXT_V8
, 0)),
24292 ARM_EXT_OPT ("idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
24293 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24294 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
),
24295 ARM_EXT_OPT ("iwmmxt2",
24296 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
),
24297 ARM_EXT_OPT ("maverick",
24298 ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
),
24299 ARM_EXT_OPT ("mp", ARM_FEATURE (ARM_EXT_MP
, 0),
24300 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)),
24301 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
24302 ARM_FEATURE (ARM_EXT_V8
, 0)),
24303 ARM_EXT_OPT ("os", ARM_FEATURE (ARM_EXT_OS
, 0),
24304 ARM_FEATURE (ARM_EXT_V6M
, 0)),
24305 ARM_EXT_OPT ("sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
24306 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)),
24307 ARM_EXT_OPT ("virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
24309 ARM_FEATURE (ARM_EXT_V7A
, 0)),
24310 ARM_EXT_OPT ("xscale",ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
),
24311 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
24315 /* ISA floating-point and Advanced SIMD extensions. */
24316 struct arm_option_fpu_value_table
24319 const arm_feature_set value
;
24322 /* This list should, at a minimum, contain all the fpu names
24323 recognized by GCC. */
24324 static const struct arm_option_fpu_value_table arm_fpus
[] =
24326 {"softfpa", FPU_NONE
},
24327 {"fpe", FPU_ARCH_FPE
},
24328 {"fpe2", FPU_ARCH_FPE
},
24329 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
24330 {"fpa", FPU_ARCH_FPA
},
24331 {"fpa10", FPU_ARCH_FPA
},
24332 {"fpa11", FPU_ARCH_FPA
},
24333 {"arm7500fe", FPU_ARCH_FPA
},
24334 {"softvfp", FPU_ARCH_VFP
},
24335 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
24336 {"vfp", FPU_ARCH_VFP_V2
},
24337 {"vfp9", FPU_ARCH_VFP_V2
},
24338 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
24339 {"vfp10", FPU_ARCH_VFP_V2
},
24340 {"vfp10-r0", FPU_ARCH_VFP_V1
},
24341 {"vfpxd", FPU_ARCH_VFP_V1xD
},
24342 {"vfpv2", FPU_ARCH_VFP_V2
},
24343 {"vfpv3", FPU_ARCH_VFP_V3
},
24344 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
24345 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
24346 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
24347 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
24348 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
24349 {"arm1020t", FPU_ARCH_VFP_V1
},
24350 {"arm1020e", FPU_ARCH_VFP_V2
},
24351 {"arm1136jfs", FPU_ARCH_VFP_V2
},
24352 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
24353 {"maverick", FPU_ARCH_MAVERICK
},
24354 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
24355 {"neon-fp16", FPU_ARCH_NEON_FP16
},
24356 {"vfpv4", FPU_ARCH_VFP_V4
},
24357 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
24358 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
24359 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
24360 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
24361 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
24362 {"crypto-neon-fp-armv8",
24363 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
24364 {NULL
, ARM_ARCH_NONE
}
24367 struct arm_option_value_table
24373 static const struct arm_option_value_table arm_float_abis
[] =
24375 {"hard", ARM_FLOAT_ABI_HARD
},
24376 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
24377 {"soft", ARM_FLOAT_ABI_SOFT
},
24382 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
24383 static const struct arm_option_value_table arm_eabis
[] =
24385 {"gnu", EF_ARM_EABI_UNKNOWN
},
24386 {"4", EF_ARM_EABI_VER4
},
24387 {"5", EF_ARM_EABI_VER5
},
24392 struct arm_long_option_table
24394 char * option
; /* Substring to match. */
24395 char * help
; /* Help information. */
24396 int (* func
) (char * subopt
); /* Function to decode sub-option. */
24397 char * deprecated
; /* If non-null, print this message. */
24401 arm_parse_extension (char *str
, const arm_feature_set
**opt_p
)
24403 arm_feature_set
*ext_set
= (arm_feature_set
*)
24404 xmalloc (sizeof (arm_feature_set
));
24406 /* We insist on extensions being specified in alphabetical order, and with
24407 extensions being added before being removed. We achieve this by having
24408 the global ARM_EXTENSIONS table in alphabetical order, and using the
24409 ADDING_VALUE variable to indicate whether we are adding an extension (1)
24410 or removing it (0) and only allowing it to change in the order
24412 const struct arm_option_extension_value_table
* opt
= NULL
;
24413 int adding_value
= -1;
24415 /* Copy the feature set, so that we can modify it. */
24416 *ext_set
= **opt_p
;
24419 while (str
!= NULL
&& *str
!= 0)
24426 as_bad (_("invalid architectural extension"));
24431 ext
= strchr (str
, '+');
24436 len
= strlen (str
);
24438 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
24440 if (adding_value
!= 0)
24443 opt
= arm_extensions
;
24451 if (adding_value
== -1)
24454 opt
= arm_extensions
;
24456 else if (adding_value
!= 1)
24458 as_bad (_("must specify extensions to add before specifying "
24459 "those to remove"));
24466 as_bad (_("missing architectural extension"));
24470 gas_assert (adding_value
!= -1);
24471 gas_assert (opt
!= NULL
);
24473 /* Scan over the options table trying to find an exact match. */
24474 for (; opt
->name
!= NULL
; opt
++)
24475 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24477 /* Check we can apply the extension to this architecture. */
24478 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
24480 as_bad (_("extension does not apply to the base architecture"));
24484 /* Add or remove the extension. */
24486 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
24488 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
24493 if (opt
->name
== NULL
)
24495 /* Did we fail to find an extension because it wasn't specified in
24496 alphabetical order, or because it does not exist? */
24498 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
24499 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24502 if (opt
->name
== NULL
)
24503 as_bad (_("unknown architectural extension `%s'"), str
);
24505 as_bad (_("architectural extensions must be specified in "
24506 "alphabetical order"));
24512 /* We should skip the extension we've just matched the next time
24524 arm_parse_cpu (char *str
)
24526 const struct arm_cpu_option_table
*opt
;
24527 char *ext
= strchr (str
, '+');
24533 len
= strlen (str
);
24537 as_bad (_("missing cpu name `%s'"), str
);
24541 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
24542 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24544 mcpu_cpu_opt
= &opt
->value
;
24545 mcpu_fpu_opt
= &opt
->default_fpu
;
24546 if (opt
->canonical_name
)
24547 strcpy (selected_cpu_name
, opt
->canonical_name
);
24552 for (i
= 0; i
< len
; i
++)
24553 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
24554 selected_cpu_name
[i
] = 0;
24558 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
24563 as_bad (_("unknown cpu `%s'"), str
);
24568 arm_parse_arch (char *str
)
24570 const struct arm_arch_option_table
*opt
;
24571 char *ext
= strchr (str
, '+');
24577 len
= strlen (str
);
24581 as_bad (_("missing architecture name `%s'"), str
);
24585 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
24586 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
24588 march_cpu_opt
= &opt
->value
;
24589 march_fpu_opt
= &opt
->default_fpu
;
24590 strcpy (selected_cpu_name
, opt
->name
);
24593 return arm_parse_extension (ext
, &march_cpu_opt
);
24598 as_bad (_("unknown architecture `%s'\n"), str
);
24603 arm_parse_fpu (char * str
)
24605 const struct arm_option_fpu_value_table
* opt
;
24607 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
24608 if (streq (opt
->name
, str
))
24610 mfpu_opt
= &opt
->value
;
24614 as_bad (_("unknown floating point format `%s'\n"), str
);
24619 arm_parse_float_abi (char * str
)
24621 const struct arm_option_value_table
* opt
;
24623 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
24624 if (streq (opt
->name
, str
))
24626 mfloat_abi_opt
= opt
->value
;
24630 as_bad (_("unknown floating point abi `%s'\n"), str
);
24636 arm_parse_eabi (char * str
)
24638 const struct arm_option_value_table
*opt
;
24640 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
24641 if (streq (opt
->name
, str
))
24643 meabi_flags
= opt
->value
;
24646 as_bad (_("unknown EABI `%s'\n"), str
);
24652 arm_parse_it_mode (char * str
)
24654 bfd_boolean ret
= TRUE
;
24656 if (streq ("arm", str
))
24657 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
24658 else if (streq ("thumb", str
))
24659 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
24660 else if (streq ("always", str
))
24661 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
24662 else if (streq ("never", str
))
24663 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
24666 as_bad (_("unknown implicit IT mode `%s', should be "\
24667 "arm, thumb, always, or never."), str
);
24675 arm_ccs_mode (char * unused ATTRIBUTE_UNUSED
)
24677 codecomposer_syntax
= TRUE
;
24678 arm_comment_chars
[0] = ';';
24679 arm_line_separator_chars
[0] = 0;
24683 struct arm_long_option_table arm_long_opts
[] =
24685 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
24686 arm_parse_cpu
, NULL
},
24687 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
24688 arm_parse_arch
, NULL
},
24689 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
24690 arm_parse_fpu
, NULL
},
24691 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
24692 arm_parse_float_abi
, NULL
},
24694 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
24695 arm_parse_eabi
, NULL
},
24697 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
24698 arm_parse_it_mode
, NULL
},
24699 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
24700 arm_ccs_mode
, NULL
},
24701 {NULL
, NULL
, 0, NULL
}
24705 md_parse_option (int c
, char * arg
)
24707 struct arm_option_table
*opt
;
24708 const struct arm_legacy_option_table
*fopt
;
24709 struct arm_long_option_table
*lopt
;
24715 target_big_endian
= 1;
24721 target_big_endian
= 0;
24725 case OPTION_FIX_V4BX
:
24730 /* Listing option. Just ignore these, we don't support additional
24735 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
24737 if (c
== opt
->option
[0]
24738 && ((arg
== NULL
&& opt
->option
[1] == 0)
24739 || streq (arg
, opt
->option
+ 1)))
24741 /* If the option is deprecated, tell the user. */
24742 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
24743 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
24744 arg
? arg
: "", _(opt
->deprecated
));
24746 if (opt
->var
!= NULL
)
24747 *opt
->var
= opt
->value
;
24753 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
24755 if (c
== fopt
->option
[0]
24756 && ((arg
== NULL
&& fopt
->option
[1] == 0)
24757 || streq (arg
, fopt
->option
+ 1)))
24759 /* If the option is deprecated, tell the user. */
24760 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
24761 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
24762 arg
? arg
: "", _(fopt
->deprecated
));
24764 if (fopt
->var
!= NULL
)
24765 *fopt
->var
= &fopt
->value
;
24771 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
24773 /* These options are expected to have an argument. */
24774 if (c
== lopt
->option
[0]
24776 && strncmp (arg
, lopt
->option
+ 1,
24777 strlen (lopt
->option
+ 1)) == 0)
24779 /* If the option is deprecated, tell the user. */
24780 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
24781 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
24782 _(lopt
->deprecated
));
24784 /* Call the sup-option parser. */
24785 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
24796 md_show_usage (FILE * fp
)
24798 struct arm_option_table
*opt
;
24799 struct arm_long_option_table
*lopt
;
24801 fprintf (fp
, _(" ARM-specific assembler options:\n"));
24803 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
24804 if (opt
->help
!= NULL
)
24805 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
24807 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
24808 if (lopt
->help
!= NULL
)
24809 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
24813 -EB assemble code for a big-endian cpu\n"));
24818 -EL assemble code for a little-endian cpu\n"));
24822 --fix-v4bx Allow BX in ARMv4 code\n"));
24830 arm_feature_set flags
;
24831 } cpu_arch_ver_table
;
24833 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
24834 least features first. */
24835 static const cpu_arch_ver_table cpu_arch_ver
[] =
24841 {4, ARM_ARCH_V5TE
},
24842 {5, ARM_ARCH_V5TEJ
},
24846 {11, ARM_ARCH_V6M
},
24847 {12, ARM_ARCH_V6SM
},
24848 {8, ARM_ARCH_V6T2
},
24849 {10, ARM_ARCH_V7VE
},
24850 {10, ARM_ARCH_V7R
},
24851 {10, ARM_ARCH_V7M
},
24852 {14, ARM_ARCH_V8A
},
24856 /* Set an attribute if it has not already been set by the user. */
24858 aeabi_set_attribute_int (int tag
, int value
)
24861 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24862 || !attributes_set_explicitly
[tag
])
24863 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
24867 aeabi_set_attribute_string (int tag
, const char *value
)
24870 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
24871 || !attributes_set_explicitly
[tag
])
24872 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
24875 /* Set the public EABI object attributes. */
24877 aeabi_set_public_attributes (void)
24882 int fp16_optional
= 0;
24883 arm_feature_set flags
;
24884 arm_feature_set tmp
;
24885 const cpu_arch_ver_table
*p
;
24887 /* Choose the architecture based on the capabilities of the requested cpu
24888 (if any) and/or the instructions actually used. */
24889 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
24890 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
24891 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
24893 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
24894 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
24896 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
24897 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
24899 /* Allow the user to override the reported architecture. */
24902 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
24903 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
24906 /* We need to make sure that the attributes do not identify us as v6S-M
24907 when the only v6S-M feature in use is the Operating System Extensions. */
24908 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
24909 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
24910 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
24914 for (p
= cpu_arch_ver
; p
->val
; p
++)
24916 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
24919 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
24923 /* The table lookup above finds the last architecture to contribute
24924 a new feature. Unfortunately, Tag13 is a subset of the union of
24925 v6T2 and v7-M, so it is never seen as contributing a new feature.
24926 We can not search for the last entry which is entirely used,
24927 because if no CPU is specified we build up only those flags
24928 actually used. Perhaps we should separate out the specified
24929 and implicit cases. Avoid taking this path for -march=all by
24930 checking for contradictory v7-A / v7-M features. */
24932 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
24933 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
24934 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
24937 /* Tag_CPU_name. */
24938 if (selected_cpu_name
[0])
24942 q
= selected_cpu_name
;
24943 if (strncmp (q
, "armv", 4) == 0)
24948 for (i
= 0; q
[i
]; i
++)
24949 q
[i
] = TOUPPER (q
[i
]);
24951 aeabi_set_attribute_string (Tag_CPU_name
, q
);
24954 /* Tag_CPU_arch. */
24955 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
24957 /* Tag_CPU_arch_profile. */
24958 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
24960 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
24962 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
24967 if (profile
!= '\0')
24968 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
24970 /* Tag_ARM_ISA_use. */
24971 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
24973 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
24975 /* Tag_THUMB_ISA_use. */
24976 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
24978 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
24979 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
24981 /* Tag_VFP_arch. */
24982 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8
))
24983 aeabi_set_attribute_int (Tag_VFP_arch
, 7);
24984 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
24985 aeabi_set_attribute_int (Tag_VFP_arch
,
24986 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
24988 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
24991 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
24993 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
24995 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
24998 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
24999 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
25000 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
25001 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
25002 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
25004 /* Tag_ABI_HardFP_use. */
25005 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
25006 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
25007 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
25009 /* Tag_WMMX_arch. */
25010 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
25011 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
25012 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
25013 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
25015 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
25016 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
25017 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
25018 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
25020 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
25022 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
25026 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
25031 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
25032 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
25033 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
25037 We set Tag_DIV_use to two when integer divide instructions have been used
25038 in ARM state, or when Thumb integer divide instructions have been used,
25039 but we have no architecture profile set, nor have we any ARM instructions.
25041 For ARMv8 we set the tag to 0 as integer divide is implied by the base
25044 For new architectures we will have to check these tests. */
25045 gas_assert (arch
<= TAG_CPU_ARCH_V8
);
25046 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
))
25047 aeabi_set_attribute_int (Tag_DIV_use
, 0);
25048 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
25049 || (profile
== '\0'
25050 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
25051 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
25052 aeabi_set_attribute_int (Tag_DIV_use
, 2);
25054 /* Tag_MP_extension_use. */
25055 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
25056 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
25058 /* Tag Virtualization_use. */
25059 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
25061 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
25064 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
25067 /* Add the default contents for the .ARM.attributes section. */
25071 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25074 aeabi_set_public_attributes ();
25076 #endif /* OBJ_ELF */
25079 /* Parse a .cpu directive. */
25082 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
25084 const struct arm_cpu_option_table
*opt
;
25088 name
= input_line_pointer
;
25089 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25090 input_line_pointer
++;
25091 saved_char
= *input_line_pointer
;
25092 *input_line_pointer
= 0;
25094 /* Skip the first "all" entry. */
25095 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
25096 if (streq (opt
->name
, name
))
25098 mcpu_cpu_opt
= &opt
->value
;
25099 selected_cpu
= opt
->value
;
25100 if (opt
->canonical_name
)
25101 strcpy (selected_cpu_name
, opt
->canonical_name
);
25105 for (i
= 0; opt
->name
[i
]; i
++)
25106 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
25108 selected_cpu_name
[i
] = 0;
25110 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25111 *input_line_pointer
= saved_char
;
25112 demand_empty_rest_of_line ();
25115 as_bad (_("unknown cpu `%s'"), name
);
25116 *input_line_pointer
= saved_char
;
25117 ignore_rest_of_line ();
25121 /* Parse a .arch directive. */
25124 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
25126 const struct arm_arch_option_table
*opt
;
25130 name
= input_line_pointer
;
25131 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25132 input_line_pointer
++;
25133 saved_char
= *input_line_pointer
;
25134 *input_line_pointer
= 0;
25136 /* Skip the first "all" entry. */
25137 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25138 if (streq (opt
->name
, name
))
25140 mcpu_cpu_opt
= &opt
->value
;
25141 selected_cpu
= opt
->value
;
25142 strcpy (selected_cpu_name
, opt
->name
);
25143 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25144 *input_line_pointer
= saved_char
;
25145 demand_empty_rest_of_line ();
25149 as_bad (_("unknown architecture `%s'\n"), name
);
25150 *input_line_pointer
= saved_char
;
25151 ignore_rest_of_line ();
25155 /* Parse a .object_arch directive. */
25158 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
25160 const struct arm_arch_option_table
*opt
;
25164 name
= input_line_pointer
;
25165 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25166 input_line_pointer
++;
25167 saved_char
= *input_line_pointer
;
25168 *input_line_pointer
= 0;
25170 /* Skip the first "all" entry. */
25171 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
25172 if (streq (opt
->name
, name
))
25174 object_arch
= &opt
->value
;
25175 *input_line_pointer
= saved_char
;
25176 demand_empty_rest_of_line ();
25180 as_bad (_("unknown architecture `%s'\n"), name
);
25181 *input_line_pointer
= saved_char
;
25182 ignore_rest_of_line ();
25185 /* Parse a .arch_extension directive. */
25188 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
25190 const struct arm_option_extension_value_table
*opt
;
25193 int adding_value
= 1;
25195 name
= input_line_pointer
;
25196 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25197 input_line_pointer
++;
25198 saved_char
= *input_line_pointer
;
25199 *input_line_pointer
= 0;
25201 if (strlen (name
) >= 2
25202 && strncmp (name
, "no", 2) == 0)
25208 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
25209 if (streq (opt
->name
, name
))
25211 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
25213 as_bad (_("architectural extension `%s' is not allowed for the "
25214 "current base architecture"), name
);
25219 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
25221 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
25223 mcpu_cpu_opt
= &selected_cpu
;
25224 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25225 *input_line_pointer
= saved_char
;
25226 demand_empty_rest_of_line ();
25230 if (opt
->name
== NULL
)
25231 as_bad (_("unknown architecture extension `%s'\n"), name
);
25233 *input_line_pointer
= saved_char
;
25234 ignore_rest_of_line ();
25237 /* Parse a .fpu directive. */
25240 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
25242 const struct arm_option_fpu_value_table
*opt
;
25246 name
= input_line_pointer
;
25247 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
25248 input_line_pointer
++;
25249 saved_char
= *input_line_pointer
;
25250 *input_line_pointer
= 0;
25252 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
25253 if (streq (opt
->name
, name
))
25255 mfpu_opt
= &opt
->value
;
25256 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
25257 *input_line_pointer
= saved_char
;
25258 demand_empty_rest_of_line ();
25262 as_bad (_("unknown floating point format `%s'\n"), name
);
25263 *input_line_pointer
= saved_char
;
25264 ignore_rest_of_line ();
25267 /* Copy symbol information. */
25270 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
25272 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
25276 /* Given a symbolic attribute NAME, return the proper integer value.
25277 Returns -1 if the attribute is not known. */
25280 arm_convert_symbolic_attribute (const char *name
)
25282 static const struct
25287 attribute_table
[] =
25289 /* When you modify this table you should
25290 also modify the list in doc/c-arm.texi. */
25291 #define T(tag) {#tag, tag}
25292 T (Tag_CPU_raw_name
),
25295 T (Tag_CPU_arch_profile
),
25296 T (Tag_ARM_ISA_use
),
25297 T (Tag_THUMB_ISA_use
),
25301 T (Tag_Advanced_SIMD_arch
),
25302 T (Tag_PCS_config
),
25303 T (Tag_ABI_PCS_R9_use
),
25304 T (Tag_ABI_PCS_RW_data
),
25305 T (Tag_ABI_PCS_RO_data
),
25306 T (Tag_ABI_PCS_GOT_use
),
25307 T (Tag_ABI_PCS_wchar_t
),
25308 T (Tag_ABI_FP_rounding
),
25309 T (Tag_ABI_FP_denormal
),
25310 T (Tag_ABI_FP_exceptions
),
25311 T (Tag_ABI_FP_user_exceptions
),
25312 T (Tag_ABI_FP_number_model
),
25313 T (Tag_ABI_align_needed
),
25314 T (Tag_ABI_align8_needed
),
25315 T (Tag_ABI_align_preserved
),
25316 T (Tag_ABI_align8_preserved
),
25317 T (Tag_ABI_enum_size
),
25318 T (Tag_ABI_HardFP_use
),
25319 T (Tag_ABI_VFP_args
),
25320 T (Tag_ABI_WMMX_args
),
25321 T (Tag_ABI_optimization_goals
),
25322 T (Tag_ABI_FP_optimization_goals
),
25323 T (Tag_compatibility
),
25324 T (Tag_CPU_unaligned_access
),
25325 T (Tag_FP_HP_extension
),
25326 T (Tag_VFP_HP_extension
),
25327 T (Tag_ABI_FP_16bit_format
),
25328 T (Tag_MPextension_use
),
25330 T (Tag_nodefaults
),
25331 T (Tag_also_compatible_with
),
25332 T (Tag_conformance
),
25334 T (Tag_Virtualization_use
),
25335 /* We deliberately do not include Tag_MPextension_use_legacy. */
25343 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
25344 if (streq (name
, attribute_table
[i
].name
))
25345 return attribute_table
[i
].tag
;
25351 /* Apply sym value for relocations only in the case that
25352 they are for local symbols and you have the respective
25353 architectural feature for blx and simple switches. */
25355 arm_apply_sym_value (struct fix
* fixP
)
25358 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
25359 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
25361 switch (fixP
->fx_r_type
)
25363 case BFD_RELOC_ARM_PCREL_BLX
:
25364 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
25365 if (ARM_IS_FUNC (fixP
->fx_addsy
))
25369 case BFD_RELOC_ARM_PCREL_CALL
:
25370 case BFD_RELOC_THUMB_PCREL_BLX
:
25371 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
25382 #endif /* OBJ_ELF */