1 /* tc-arm.c -- Assemble for the ARM
2 Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
6 Modified by David Taylor (dtaylor@armltd.co.uk)
7 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
8 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
9 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
11 This file is part of GAS, the GNU Assembler.
13 GAS is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 3, or (at your option)
18 GAS is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with GAS; see the file COPYING. If not, write to the Free
25 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
32 #include "safe-ctype.h"
36 #include "opcode/arm.h"
40 #include "dw2gencfi.h"
43 #include "dwarf2dbg.h"
46 /* Must be at least the size of the largest unwind opcode (currently two). */
47 #define ARM_OPCODE_CHUNK_SIZE 8
49 /* This structure holds the unwinding state. */
54 symbolS
* table_entry
;
55 symbolS
* personality_routine
;
56 int personality_index
;
57 /* The segment containing the function. */
60 /* Opcodes generated from this function. */
61 unsigned char * opcodes
;
64 /* The number of bytes pushed to the stack. */
66 /* We don't add stack adjustment opcodes immediately so that we can merge
67 multiple adjustments. We can also omit the final adjustment
68 when using a frame pointer. */
69 offsetT pending_offset
;
70 /* These two fields are set by both unwind_movsp and unwind_setfp. They
71 hold the reg+offset to use when restoring sp from a frame pointer. */
74 /* Nonzero if an unwind_setfp directive has been seen. */
76 /* Nonzero if the last opcode restores sp from fp_reg. */
77 unsigned sp_restored
:1;
82 /* Results from operand parsing worker functions. */
86 PARSE_OPERAND_SUCCESS
,
88 PARSE_OPERAND_FAIL_NO_BACKTRACK
89 } parse_operand_result
;
98 /* Types of processor to assemble for. */
100 /* The code that was here used to select a default CPU depending on compiler
101 pre-defines which were only present when doing native builds, thus
102 changing gas' default behaviour depending upon the build host.
104 If you have a target that requires a default CPU option then the you
105 should define CPU_DEFAULT here. */
110 # define FPU_DEFAULT FPU_ARCH_FPA
111 # elif defined (TE_NetBSD)
113 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
115 /* Legacy a.out format. */
116 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
118 # elif defined (TE_VXWORKS)
119 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
121 /* For backwards compatibility, default to FPA. */
122 # define FPU_DEFAULT FPU_ARCH_FPA
124 #endif /* ifndef FPU_DEFAULT */
126 #define streq(a, b) (strcmp (a, b) == 0)
128 static arm_feature_set cpu_variant
;
129 static arm_feature_set arm_arch_used
;
130 static arm_feature_set thumb_arch_used
;
132 /* Flags stored in private area of BFD structure. */
133 static int uses_apcs_26
= FALSE
;
134 static int atpcs
= FALSE
;
135 static int support_interwork
= FALSE
;
136 static int uses_apcs_float
= FALSE
;
137 static int pic_code
= FALSE
;
138 static int fix_v4bx
= FALSE
;
139 /* Warn on using deprecated features. */
140 static int warn_on_deprecated
= TRUE
;
143 /* Variables that we set while parsing command-line options. Once all
144 options have been read we re-process these values to set the real
146 static const arm_feature_set
*legacy_cpu
= NULL
;
147 static const arm_feature_set
*legacy_fpu
= NULL
;
149 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
150 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
151 static const arm_feature_set
*march_cpu_opt
= NULL
;
152 static const arm_feature_set
*march_fpu_opt
= NULL
;
153 static const arm_feature_set
*mfpu_opt
= NULL
;
154 static const arm_feature_set
*object_arch
= NULL
;
156 /* Constants for known architecture features. */
157 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
158 static const arm_feature_set fpu_arch_vfp_v1
= FPU_ARCH_VFP_V1
;
159 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
160 static const arm_feature_set fpu_arch_vfp_v3
= FPU_ARCH_VFP_V3
;
161 static const arm_feature_set fpu_arch_neon_v1
= FPU_ARCH_NEON_V1
;
162 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
163 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
164 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
165 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
168 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
171 static const arm_feature_set arm_ext_v1
= ARM_FEATURE (ARM_EXT_V1
, 0);
172 static const arm_feature_set arm_ext_v2
= ARM_FEATURE (ARM_EXT_V1
, 0);
173 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE (ARM_EXT_V2S
, 0);
174 static const arm_feature_set arm_ext_v3
= ARM_FEATURE (ARM_EXT_V3
, 0);
175 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE (ARM_EXT_V3M
, 0);
176 static const arm_feature_set arm_ext_v4
= ARM_FEATURE (ARM_EXT_V4
, 0);
177 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE (ARM_EXT_V4T
, 0);
178 static const arm_feature_set arm_ext_v5
= ARM_FEATURE (ARM_EXT_V5
, 0);
179 static const arm_feature_set arm_ext_v4t_5
=
180 ARM_FEATURE (ARM_EXT_V4T
| ARM_EXT_V5
, 0);
181 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE (ARM_EXT_V5T
, 0);
182 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE (ARM_EXT_V5E
, 0);
183 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE (ARM_EXT_V5ExP
, 0);
184 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE (ARM_EXT_V5J
, 0);
185 static const arm_feature_set arm_ext_v6
= ARM_FEATURE (ARM_EXT_V6
, 0);
186 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE (ARM_EXT_V6K
, 0);
187 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE (ARM_EXT_V6T2
, 0);
188 static const arm_feature_set arm_ext_v6m
= ARM_FEATURE (ARM_EXT_V6M
, 0);
189 static const arm_feature_set arm_ext_v6_notm
= ARM_FEATURE (ARM_EXT_V6_NOTM
, 0);
190 static const arm_feature_set arm_ext_v6_dsp
= ARM_FEATURE (ARM_EXT_V6_DSP
, 0);
191 static const arm_feature_set arm_ext_barrier
= ARM_FEATURE (ARM_EXT_BARRIER
, 0);
192 static const arm_feature_set arm_ext_msr
= ARM_FEATURE (ARM_EXT_THUMB_MSR
, 0);
193 static const arm_feature_set arm_ext_div
= ARM_FEATURE (ARM_EXT_DIV
, 0);
194 static const arm_feature_set arm_ext_v7
= ARM_FEATURE (ARM_EXT_V7
, 0);
195 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE (ARM_EXT_V7A
, 0);
196 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE (ARM_EXT_V7R
, 0);
197 static const arm_feature_set arm_ext_v7m
= ARM_FEATURE (ARM_EXT_V7M
, 0);
198 static const arm_feature_set arm_ext_m
=
199 ARM_FEATURE (ARM_EXT_V6M
| ARM_EXT_OS
| ARM_EXT_V7M
, 0);
200 static const arm_feature_set arm_ext_mp
= ARM_FEATURE (ARM_EXT_MP
, 0);
201 static const arm_feature_set arm_ext_sec
= ARM_FEATURE (ARM_EXT_SEC
, 0);
202 static const arm_feature_set arm_ext_os
= ARM_FEATURE (ARM_EXT_OS
, 0);
203 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE (ARM_EXT_ADIV
, 0);
204 static const arm_feature_set arm_ext_virt
= ARM_FEATURE (ARM_EXT_VIRT
, 0);
206 static const arm_feature_set arm_arch_any
= ARM_ANY
;
207 static const arm_feature_set arm_arch_full
= ARM_FEATURE (-1, -1);
208 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
209 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
210 static const arm_feature_set arm_arch_v6m_only
= ARM_ARCH_V6M_ONLY
;
212 static const arm_feature_set arm_cext_iwmmxt2
=
213 ARM_FEATURE (0, ARM_CEXT_IWMMXT2
);
214 static const arm_feature_set arm_cext_iwmmxt
=
215 ARM_FEATURE (0, ARM_CEXT_IWMMXT
);
216 static const arm_feature_set arm_cext_xscale
=
217 ARM_FEATURE (0, ARM_CEXT_XSCALE
);
218 static const arm_feature_set arm_cext_maverick
=
219 ARM_FEATURE (0, ARM_CEXT_MAVERICK
);
220 static const arm_feature_set fpu_fpa_ext_v1
= ARM_FEATURE (0, FPU_FPA_EXT_V1
);
221 static const arm_feature_set fpu_fpa_ext_v2
= ARM_FEATURE (0, FPU_FPA_EXT_V2
);
222 static const arm_feature_set fpu_vfp_ext_v1xd
=
223 ARM_FEATURE (0, FPU_VFP_EXT_V1xD
);
224 static const arm_feature_set fpu_vfp_ext_v1
= ARM_FEATURE (0, FPU_VFP_EXT_V1
);
225 static const arm_feature_set fpu_vfp_ext_v2
= ARM_FEATURE (0, FPU_VFP_EXT_V2
);
226 static const arm_feature_set fpu_vfp_ext_v3xd
= ARM_FEATURE (0, FPU_VFP_EXT_V3xD
);
227 static const arm_feature_set fpu_vfp_ext_v3
= ARM_FEATURE (0, FPU_VFP_EXT_V3
);
228 static const arm_feature_set fpu_vfp_ext_d32
=
229 ARM_FEATURE (0, FPU_VFP_EXT_D32
);
230 static const arm_feature_set fpu_neon_ext_v1
= ARM_FEATURE (0, FPU_NEON_EXT_V1
);
231 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
232 ARM_FEATURE (0, FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
233 static const arm_feature_set fpu_vfp_fp16
= ARM_FEATURE (0, FPU_VFP_EXT_FP16
);
234 static const arm_feature_set fpu_neon_ext_fma
= ARM_FEATURE (0, FPU_NEON_EXT_FMA
);
235 static const arm_feature_set fpu_vfp_ext_fma
= ARM_FEATURE (0, FPU_VFP_EXT_FMA
);
237 static int mfloat_abi_opt
= -1;
238 /* Record user cpu selection for object attributes. */
239 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
240 /* Must be long enough to hold any of the names in arm_cpus. */
241 static char selected_cpu_name
[16];
243 /* Return if no cpu was selected on command-line. */
245 no_cpu_selected (void)
247 return selected_cpu
.core
== arm_arch_none
.core
248 && selected_cpu
.coproc
== arm_arch_none
.coproc
;
253 static int meabi_flags
= EABI_DEFAULT
;
255 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
258 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
263 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
268 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
269 symbolS
* GOT_symbol
;
272 /* 0: assemble for ARM,
273 1: assemble for Thumb,
274 2: assemble for Thumb even though target CPU does not support thumb
276 static int thumb_mode
= 0;
277 /* A value distinct from the possible values for thumb_mode that we
278 can use to record whether thumb_mode has been copied into the
279 tc_frag_data field of a frag. */
280 #define MODE_RECORDED (1 << 4)
282 /* Specifies the intrinsic IT insn behavior mode. */
283 enum implicit_it_mode
285 IMPLICIT_IT_MODE_NEVER
= 0x00,
286 IMPLICIT_IT_MODE_ARM
= 0x01,
287 IMPLICIT_IT_MODE_THUMB
= 0x02,
288 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
290 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
292 /* If unified_syntax is true, we are processing the new unified
293 ARM/Thumb syntax. Important differences from the old ARM mode:
295 - Immediate operands do not require a # prefix.
296 - Conditional affixes always appear at the end of the
297 instruction. (For backward compatibility, those instructions
298 that formerly had them in the middle, continue to accept them
300 - The IT instruction may appear, and if it does is validated
301 against subsequent conditional affixes. It does not generate
304 Important differences from the old Thumb mode:
306 - Immediate operands do not require a # prefix.
307 - Most of the V6T2 instructions are only available in unified mode.
308 - The .N and .W suffixes are recognized and honored (it is an error
309 if they cannot be honored).
310 - All instructions set the flags if and only if they have an 's' affix.
311 - Conditional affixes may be used. They are validated against
312 preceding IT instructions. Unlike ARM mode, you cannot use a
313 conditional affix except in the scope of an IT instruction. */
315 static bfd_boolean unified_syntax
= FALSE
;
330 enum neon_el_type type
;
334 #define NEON_MAX_TYPE_ELS 4
338 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
342 enum it_instruction_type
347 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
348 if inside, should be the last one. */
349 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
350 i.e. BKPT and NOP. */
351 IT_INSN
/* The IT insn has been parsed. */
357 unsigned long instruction
;
361 /* "uncond_value" is set to the value in place of the conditional field in
362 unconditional versions of the instruction, or -1 if nothing is
365 struct neon_type vectype
;
366 /* This does not indicate an actual NEON instruction, only that
367 the mnemonic accepts neon-style type suffixes. */
369 /* Set to the opcode if the instruction needs relaxation.
370 Zero if the instruction is not relaxed. */
374 bfd_reloc_code_real_type type
;
379 enum it_instruction_type it_insn_type
;
385 struct neon_type_el vectype
;
386 unsigned present
: 1; /* Operand present. */
387 unsigned isreg
: 1; /* Operand was a register. */
388 unsigned immisreg
: 1; /* .imm field is a second register. */
389 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
390 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
391 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
392 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
393 instructions. This allows us to disambiguate ARM <-> vector insns. */
394 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
395 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
396 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
397 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
398 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
399 unsigned writeback
: 1; /* Operand has trailing ! */
400 unsigned preind
: 1; /* Preindexed address. */
401 unsigned postind
: 1; /* Postindexed address. */
402 unsigned negative
: 1; /* Index register was negated. */
403 unsigned shifted
: 1; /* Shift applied to operation. */
404 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
408 static struct arm_it inst
;
410 #define NUM_FLOAT_VALS 8
412 const char * fp_const
[] =
414 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
417 /* Number of littlenums required to hold an extended precision number. */
418 #define MAX_LITTLENUMS 6
420 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
430 #define CP_T_X 0x00008000
431 #define CP_T_Y 0x00400000
433 #define CONDS_BIT 0x00100000
434 #define LOAD_BIT 0x00100000
436 #define DOUBLE_LOAD_FLAG 0x00000001
440 const char * template_name
;
444 #define COND_ALWAYS 0xE
448 const char * template_name
;
452 struct asm_barrier_opt
454 const char * template_name
;
458 /* The bit that distinguishes CPSR and SPSR. */
459 #define SPSR_BIT (1 << 22)
461 /* The individual PSR flag bits. */
462 #define PSR_c (1 << 16)
463 #define PSR_x (1 << 17)
464 #define PSR_s (1 << 18)
465 #define PSR_f (1 << 19)
470 bfd_reloc_code_real_type reloc
;
475 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
476 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
481 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
484 /* Bits for DEFINED field in neon_typed_alias. */
485 #define NTA_HASTYPE 1
486 #define NTA_HASINDEX 2
488 struct neon_typed_alias
490 unsigned char defined
;
492 struct neon_type_el eltype
;
495 /* ARM register categories. This includes coprocessor numbers and various
496 architecture extensions' registers. */
523 /* Structure for a hash table entry for a register.
524 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
525 information which states whether a vector type or index is specified (for a
526 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
532 unsigned char builtin
;
533 struct neon_typed_alias
* neon
;
536 /* Diagnostics used when we don't get a register of the expected type. */
537 const char * const reg_expected_msgs
[] =
539 N_("ARM register expected"),
540 N_("bad or missing co-processor number"),
541 N_("co-processor register expected"),
542 N_("FPA register expected"),
543 N_("VFP single precision register expected"),
544 N_("VFP/Neon double precision register expected"),
545 N_("Neon quad precision register expected"),
546 N_("VFP single or double precision register expected"),
547 N_("Neon double or quad precision register expected"),
548 N_("VFP single, double or Neon quad precision register expected"),
549 N_("VFP system register expected"),
550 N_("Maverick MVF register expected"),
551 N_("Maverick MVD register expected"),
552 N_("Maverick MVFX register expected"),
553 N_("Maverick MVDX register expected"),
554 N_("Maverick MVAX register expected"),
555 N_("Maverick DSPSC register expected"),
556 N_("iWMMXt data register expected"),
557 N_("iWMMXt control register expected"),
558 N_("iWMMXt scalar register expected"),
559 N_("XScale accumulator register expected"),
562 /* Some well known registers that we refer to directly elsewhere. */
567 /* ARM instructions take 4bytes in the object file, Thumb instructions
573 /* Basic string to match. */
574 const char * template_name
;
576 /* Parameters to instruction. */
577 unsigned int operands
[8];
579 /* Conditional tag - see opcode_lookup. */
580 unsigned int tag
: 4;
582 /* Basic instruction code. */
583 unsigned int avalue
: 28;
585 /* Thumb-format instruction code. */
588 /* Which architecture variant provides this instruction. */
589 const arm_feature_set
* avariant
;
590 const arm_feature_set
* tvariant
;
592 /* Function to call to encode instruction in ARM format. */
593 void (* aencode
) (void);
595 /* Function to call to encode instruction in Thumb format. */
596 void (* tencode
) (void);
599 /* Defines for various bits that we will want to toggle. */
600 #define INST_IMMEDIATE 0x02000000
601 #define OFFSET_REG 0x02000000
602 #define HWOFFSET_IMM 0x00400000
603 #define SHIFT_BY_REG 0x00000010
604 #define PRE_INDEX 0x01000000
605 #define INDEX_UP 0x00800000
606 #define WRITE_BACK 0x00200000
607 #define LDM_TYPE_2_OR_3 0x00400000
608 #define CPSI_MMOD 0x00020000
610 #define LITERAL_MASK 0xf000f000
611 #define OPCODE_MASK 0xfe1fffff
612 #define V4_STR_BIT 0x00000020
614 #define T2_SUBS_PC_LR 0xf3de8f00
616 #define DATA_OP_SHIFT 21
618 #define T2_OPCODE_MASK 0xfe1fffff
619 #define T2_DATA_OP_SHIFT 21
621 /* Codes to distinguish the arithmetic instructions. */
632 #define OPCODE_CMP 10
633 #define OPCODE_CMN 11
634 #define OPCODE_ORR 12
635 #define OPCODE_MOV 13
636 #define OPCODE_BIC 14
637 #define OPCODE_MVN 15
639 #define T2_OPCODE_AND 0
640 #define T2_OPCODE_BIC 1
641 #define T2_OPCODE_ORR 2
642 #define T2_OPCODE_ORN 3
643 #define T2_OPCODE_EOR 4
644 #define T2_OPCODE_ADD 8
645 #define T2_OPCODE_ADC 10
646 #define T2_OPCODE_SBC 11
647 #define T2_OPCODE_SUB 13
648 #define T2_OPCODE_RSB 14
650 #define T_OPCODE_MUL 0x4340
651 #define T_OPCODE_TST 0x4200
652 #define T_OPCODE_CMN 0x42c0
653 #define T_OPCODE_NEG 0x4240
654 #define T_OPCODE_MVN 0x43c0
656 #define T_OPCODE_ADD_R3 0x1800
657 #define T_OPCODE_SUB_R3 0x1a00
658 #define T_OPCODE_ADD_HI 0x4400
659 #define T_OPCODE_ADD_ST 0xb000
660 #define T_OPCODE_SUB_ST 0xb080
661 #define T_OPCODE_ADD_SP 0xa800
662 #define T_OPCODE_ADD_PC 0xa000
663 #define T_OPCODE_ADD_I8 0x3000
664 #define T_OPCODE_SUB_I8 0x3800
665 #define T_OPCODE_ADD_I3 0x1c00
666 #define T_OPCODE_SUB_I3 0x1e00
668 #define T_OPCODE_ASR_R 0x4100
669 #define T_OPCODE_LSL_R 0x4080
670 #define T_OPCODE_LSR_R 0x40c0
671 #define T_OPCODE_ROR_R 0x41c0
672 #define T_OPCODE_ASR_I 0x1000
673 #define T_OPCODE_LSL_I 0x0000
674 #define T_OPCODE_LSR_I 0x0800
676 #define T_OPCODE_MOV_I8 0x2000
677 #define T_OPCODE_CMP_I8 0x2800
678 #define T_OPCODE_CMP_LR 0x4280
679 #define T_OPCODE_MOV_HR 0x4600
680 #define T_OPCODE_CMP_HR 0x4500
682 #define T_OPCODE_LDR_PC 0x4800
683 #define T_OPCODE_LDR_SP 0x9800
684 #define T_OPCODE_STR_SP 0x9000
685 #define T_OPCODE_LDR_IW 0x6800
686 #define T_OPCODE_STR_IW 0x6000
687 #define T_OPCODE_LDR_IH 0x8800
688 #define T_OPCODE_STR_IH 0x8000
689 #define T_OPCODE_LDR_IB 0x7800
690 #define T_OPCODE_STR_IB 0x7000
691 #define T_OPCODE_LDR_RW 0x5800
692 #define T_OPCODE_STR_RW 0x5000
693 #define T_OPCODE_LDR_RH 0x5a00
694 #define T_OPCODE_STR_RH 0x5200
695 #define T_OPCODE_LDR_RB 0x5c00
696 #define T_OPCODE_STR_RB 0x5400
698 #define T_OPCODE_PUSH 0xb400
699 #define T_OPCODE_POP 0xbc00
701 #define T_OPCODE_BRANCH 0xe000
703 #define THUMB_SIZE 2 /* Size of thumb instruction. */
704 #define THUMB_PP_PC_LR 0x0100
705 #define THUMB_LOAD_BIT 0x0800
706 #define THUMB2_LOAD_BIT 0x00100000
708 #define BAD_ARGS _("bad arguments to instruction")
709 #define BAD_SP _("r13 not allowed here")
710 #define BAD_PC _("r15 not allowed here")
711 #define BAD_COND _("instruction cannot be conditional")
712 #define BAD_OVERLAP _("registers may not be the same")
713 #define BAD_HIREG _("lo register required")
714 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
715 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
716 #define BAD_BRANCH _("branch must be last instruction in IT block")
717 #define BAD_NOT_IT _("instruction not allowed in IT block")
718 #define BAD_FPU _("selected FPU does not support instruction")
719 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
720 #define BAD_IT_COND _("incorrect condition in IT block")
721 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
722 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
723 #define BAD_PC_ADDRESSING \
724 _("cannot use register index with PC-relative addressing")
725 #define BAD_PC_WRITEBACK \
726 _("cannot use writeback with PC-relative addressing")
728 static struct hash_control
* arm_ops_hsh
;
729 static struct hash_control
* arm_cond_hsh
;
730 static struct hash_control
* arm_shift_hsh
;
731 static struct hash_control
* arm_psr_hsh
;
732 static struct hash_control
* arm_v7m_psr_hsh
;
733 static struct hash_control
* arm_reg_hsh
;
734 static struct hash_control
* arm_reloc_hsh
;
735 static struct hash_control
* arm_barrier_opt_hsh
;
737 /* Stuff needed to resolve the label ambiguity
746 symbolS
* last_label_seen
;
747 static int label_is_thumb_function_name
= FALSE
;
749 /* Literal pool structure. Held on a per-section
750 and per-sub-section basis. */
752 #define MAX_LITERAL_POOL_SIZE 1024
753 typedef struct literal_pool
755 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
756 unsigned int next_free_entry
;
761 struct literal_pool
* next
;
764 /* Pointer to a linked list of literal pools. */
765 literal_pool
* list_of_pools
= NULL
;
768 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
770 static struct current_it now_it
;
774 now_it_compatible (int cond
)
776 return (cond
& ~1) == (now_it
.cc
& ~1);
780 conditional_insn (void)
782 return inst
.cond
!= COND_ALWAYS
;
785 static int in_it_block (void);
787 static int handle_it_state (void);
789 static void force_automatic_it_block_close (void);
791 static void it_fsm_post_encode (void);
793 #define set_it_insn_type(type) \
796 inst.it_insn_type = type; \
797 if (handle_it_state () == FAIL) \
802 #define set_it_insn_type_nonvoid(type, failret) \
805 inst.it_insn_type = type; \
806 if (handle_it_state () == FAIL) \
811 #define set_it_insn_type_last() \
814 if (inst.cond == COND_ALWAYS) \
815 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
817 set_it_insn_type (INSIDE_IT_LAST_INSN); \
823 /* This array holds the chars that always start a comment. If the
824 pre-processor is disabled, these aren't very useful. */
825 const char comment_chars
[] = "@";
827 /* This array holds the chars that only start a comment at the beginning of
828 a line. If the line seems to have the form '# 123 filename'
829 .line and .file directives will appear in the pre-processed output. */
830 /* Note that input_file.c hand checks for '#' at the beginning of the
831 first line of the input file. This is because the compiler outputs
832 #NO_APP at the beginning of its output. */
833 /* Also note that comments like this one will always work. */
834 const char line_comment_chars
[] = "#";
836 const char line_separator_chars
[] = ";";
838 /* Chars that can be used to separate mant
839 from exp in floating point numbers. */
840 const char EXP_CHARS
[] = "eE";
842 /* Chars that mean this number is a floating point constant. */
846 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
848 /* Prefix characters that indicate the start of an immediate
850 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
852 /* Separator character handling. */
854 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
857 skip_past_char (char ** str
, char c
)
868 #define skip_past_comma(str) skip_past_char (str, ',')
870 /* Arithmetic expressions (possibly involving symbols). */
872 /* Return TRUE if anything in the expression is a bignum. */
875 walk_no_bignums (symbolS
* sp
)
877 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
880 if (symbol_get_value_expression (sp
)->X_add_symbol
)
882 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
883 || (symbol_get_value_expression (sp
)->X_op_symbol
884 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
890 static int in_my_get_expression
= 0;
892 /* Third argument to my_get_expression. */
893 #define GE_NO_PREFIX 0
894 #define GE_IMM_PREFIX 1
895 #define GE_OPT_PREFIX 2
896 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
897 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
898 #define GE_OPT_PREFIX_BIG 3
901 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
906 /* In unified syntax, all prefixes are optional. */
908 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
913 case GE_NO_PREFIX
: break;
915 if (!is_immediate_prefix (**str
))
917 inst
.error
= _("immediate expression requires a # prefix");
923 case GE_OPT_PREFIX_BIG
:
924 if (is_immediate_prefix (**str
))
930 memset (ep
, 0, sizeof (expressionS
));
932 save_in
= input_line_pointer
;
933 input_line_pointer
= *str
;
934 in_my_get_expression
= 1;
935 seg
= expression (ep
);
936 in_my_get_expression
= 0;
938 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
940 /* We found a bad or missing expression in md_operand(). */
941 *str
= input_line_pointer
;
942 input_line_pointer
= save_in
;
943 if (inst
.error
== NULL
)
944 inst
.error
= (ep
->X_op
== O_absent
945 ? _("missing expression") :_("bad expression"));
950 if (seg
!= absolute_section
951 && seg
!= text_section
952 && seg
!= data_section
953 && seg
!= bss_section
954 && seg
!= undefined_section
)
956 inst
.error
= _("bad segment");
957 *str
= input_line_pointer
;
958 input_line_pointer
= save_in
;
965 /* Get rid of any bignums now, so that we don't generate an error for which
966 we can't establish a line number later on. Big numbers are never valid
967 in instructions, which is where this routine is always called. */
968 if (prefix_mode
!= GE_OPT_PREFIX_BIG
969 && (ep
->X_op
== O_big
971 && (walk_no_bignums (ep
->X_add_symbol
)
973 && walk_no_bignums (ep
->X_op_symbol
))))))
975 inst
.error
= _("invalid constant");
976 *str
= input_line_pointer
;
977 input_line_pointer
= save_in
;
981 *str
= input_line_pointer
;
982 input_line_pointer
= save_in
;
986 /* Turn a string in input_line_pointer into a floating point constant
987 of type TYPE, and store the appropriate bytes in *LITP. The number
988 of LITTLENUMS emitted is stored in *SIZEP. An error message is
989 returned, or NULL on OK.
991 Note that fp constants aren't represent in the normal way on the ARM.
992 In big endian mode, things are as expected. However, in little endian
993 mode fp constants are big-endian word-wise, and little-endian byte-wise
994 within the words. For example, (double) 1.1 in big endian mode is
995 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
996 the byte sequence 99 99 f1 3f 9a 99 99 99.
998 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1001 md_atof (int type
, char * litP
, int * sizeP
)
1004 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1036 return _("Unrecognized or unsupported floating point constant");
1039 t
= atof_ieee (input_line_pointer
, type
, words
);
1041 input_line_pointer
= t
;
1042 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1044 if (target_big_endian
)
1046 for (i
= 0; i
< prec
; i
++)
1048 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1049 litP
+= sizeof (LITTLENUM_TYPE
);
1054 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1055 for (i
= prec
- 1; i
>= 0; i
--)
1057 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1058 litP
+= sizeof (LITTLENUM_TYPE
);
1061 /* For a 4 byte float the order of elements in `words' is 1 0.
1062 For an 8 byte float the order is 1 0 3 2. */
1063 for (i
= 0; i
< prec
; i
+= 2)
1065 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1066 sizeof (LITTLENUM_TYPE
));
1067 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1068 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1069 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1076 /* We handle all bad expressions here, so that we can report the faulty
1077 instruction in the error message. */
1079 md_operand (expressionS
* exp
)
1081 if (in_my_get_expression
)
1082 exp
->X_op
= O_illegal
;
1085 /* Immediate values. */
1087 /* Generic immediate-value read function for use in directives.
1088 Accepts anything that 'expression' can fold to a constant.
1089 *val receives the number. */
1092 immediate_for_directive (int *val
)
1095 exp
.X_op
= O_illegal
;
1097 if (is_immediate_prefix (*input_line_pointer
))
1099 input_line_pointer
++;
1103 if (exp
.X_op
!= O_constant
)
1105 as_bad (_("expected #constant"));
1106 ignore_rest_of_line ();
1109 *val
= exp
.X_add_number
;
1114 /* Register parsing. */
1116 /* Generic register parser. CCP points to what should be the
1117 beginning of a register name. If it is indeed a valid register
1118 name, advance CCP over it and return the reg_entry structure;
1119 otherwise return NULL. Does not issue diagnostics. */
1121 static struct reg_entry
*
1122 arm_reg_parse_multi (char **ccp
)
1126 struct reg_entry
*reg
;
1128 #ifdef REGISTER_PREFIX
1129 if (*start
!= REGISTER_PREFIX
)
1133 #ifdef OPTIONAL_REGISTER_PREFIX
1134 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1139 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1144 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1146 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1156 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1157 enum arm_reg_type type
)
1159 /* Alternative syntaxes are accepted for a few register classes. */
1166 /* Generic coprocessor register names are allowed for these. */
1167 if (reg
&& reg
->type
== REG_TYPE_CN
)
1172 /* For backward compatibility, a bare number is valid here. */
1174 unsigned long processor
= strtoul (start
, ccp
, 10);
1175 if (*ccp
!= start
&& processor
<= 15)
1179 case REG_TYPE_MMXWC
:
1180 /* WC includes WCG. ??? I'm not sure this is true for all
1181 instructions that take WC registers. */
1182 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1193 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1194 return value is the register number or FAIL. */
1197 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1200 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1203 /* Do not allow a scalar (reg+index) to parse as a register. */
1204 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1207 if (reg
&& reg
->type
== type
)
1210 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1217 /* Parse a Neon type specifier. *STR should point at the leading '.'
1218 character. Does no verification at this stage that the type fits the opcode
1225 Can all be legally parsed by this function.
1227 Fills in neon_type struct pointer with parsed information, and updates STR
1228 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1229 type, FAIL if not. */
1232 parse_neon_type (struct neon_type
*type
, char **str
)
1239 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1241 enum neon_el_type thistype
= NT_untyped
;
1242 unsigned thissize
= -1u;
1249 /* Just a size without an explicit type. */
1253 switch (TOLOWER (*ptr
))
1255 case 'i': thistype
= NT_integer
; break;
1256 case 'f': thistype
= NT_float
; break;
1257 case 'p': thistype
= NT_poly
; break;
1258 case 's': thistype
= NT_signed
; break;
1259 case 'u': thistype
= NT_unsigned
; break;
1261 thistype
= NT_float
;
1266 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1272 /* .f is an abbreviation for .f32. */
1273 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1278 thissize
= strtoul (ptr
, &ptr
, 10);
1280 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1283 as_bad (_("bad size %d in type specifier"), thissize
);
1291 type
->el
[type
->elems
].type
= thistype
;
1292 type
->el
[type
->elems
].size
= thissize
;
1297 /* Empty/missing type is not a successful parse. */
1298 if (type
->elems
== 0)
1306 /* Errors may be set multiple times during parsing or bit encoding
1307 (particularly in the Neon bits), but usually the earliest error which is set
1308 will be the most meaningful. Avoid overwriting it with later (cascading)
1309 errors by calling this function. */
1312 first_error (const char *err
)
1318 /* Parse a single type, e.g. ".s32", leading period included. */
1320 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1323 struct neon_type optype
;
1327 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1329 if (optype
.elems
== 1)
1330 *vectype
= optype
.el
[0];
1333 first_error (_("only one type should be specified for operand"));
1339 first_error (_("vector type expected"));
1351 /* Special meanings for indices (which have a range of 0-7), which will fit into
1354 #define NEON_ALL_LANES 15
1355 #define NEON_INTERLEAVE_LANES 14
1357 /* Parse either a register or a scalar, with an optional type. Return the
1358 register number, and optionally fill in the actual type of the register
1359 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1360 type/index information in *TYPEINFO. */
1363 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1364 enum arm_reg_type
*rtype
,
1365 struct neon_typed_alias
*typeinfo
)
1368 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1369 struct neon_typed_alias atype
;
1370 struct neon_type_el parsetype
;
1374 atype
.eltype
.type
= NT_invtype
;
1375 atype
.eltype
.size
= -1;
1377 /* Try alternate syntax for some types of register. Note these are mutually
1378 exclusive with the Neon syntax extensions. */
1381 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1389 /* Undo polymorphism when a set of register types may be accepted. */
1390 if ((type
== REG_TYPE_NDQ
1391 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1392 || (type
== REG_TYPE_VFSD
1393 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1394 || (type
== REG_TYPE_NSDQ
1395 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1396 || reg
->type
== REG_TYPE_NQ
))
1397 || (type
== REG_TYPE_MMXWC
1398 && (reg
->type
== REG_TYPE_MMXWCG
)))
1399 type
= (enum arm_reg_type
) reg
->type
;
1401 if (type
!= reg
->type
)
1407 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1409 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1411 first_error (_("can't redefine type for operand"));
1414 atype
.defined
|= NTA_HASTYPE
;
1415 atype
.eltype
= parsetype
;
1418 if (skip_past_char (&str
, '[') == SUCCESS
)
1420 if (type
!= REG_TYPE_VFD
)
1422 first_error (_("only D registers may be indexed"));
1426 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1428 first_error (_("can't change index for operand"));
1432 atype
.defined
|= NTA_HASINDEX
;
1434 if (skip_past_char (&str
, ']') == SUCCESS
)
1435 atype
.index
= NEON_ALL_LANES
;
1440 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1442 if (exp
.X_op
!= O_constant
)
1444 first_error (_("constant expression required"));
1448 if (skip_past_char (&str
, ']') == FAIL
)
1451 atype
.index
= exp
.X_add_number
;
1466 /* Like arm_reg_parse, but allow allow the following extra features:
1467 - If RTYPE is non-zero, return the (possibly restricted) type of the
1468 register (e.g. Neon double or quad reg when either has been requested).
1469 - If this is a Neon vector type with additional type information, fill
1470 in the struct pointed to by VECTYPE (if non-NULL).
1471 This function will fault on encountering a scalar. */
1474 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1475 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1477 struct neon_typed_alias atype
;
1479 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1484 /* Do not allow regname(... to parse as a register. */
1488 /* Do not allow a scalar (reg+index) to parse as a register. */
1489 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1491 first_error (_("register operand expected, but got scalar"));
1496 *vectype
= atype
.eltype
;
1503 #define NEON_SCALAR_REG(X) ((X) >> 4)
1504 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1506 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1507 have enough information to be able to do a good job bounds-checking. So, we
1508 just do easy checks here, and do further checks later. */
1511 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1515 struct neon_typed_alias atype
;
1517 reg
= parse_typed_reg_or_scalar (&str
, REG_TYPE_VFD
, NULL
, &atype
);
1519 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1522 if (atype
.index
== NEON_ALL_LANES
)
1524 first_error (_("scalar must have an index"));
1527 else if (atype
.index
>= 64 / elsize
)
1529 first_error (_("scalar index out of range"));
1534 *type
= atype
.eltype
;
1538 return reg
* 16 + atype
.index
;
1541 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1544 parse_reg_list (char ** strp
)
1546 char * str
= * strp
;
1550 /* We come back here if we get ranges concatenated by '+' or '|'. */
1565 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1567 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1577 first_error (_("bad range in register list"));
1581 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1583 if (range
& (1 << i
))
1585 (_("Warning: duplicated register (r%d) in register list"),
1593 if (range
& (1 << reg
))
1594 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1596 else if (reg
<= cur_reg
)
1597 as_tsktsk (_("Warning: register range not in ascending order"));
1602 while (skip_past_comma (&str
) != FAIL
1603 || (in_range
= 1, *str
++ == '-'));
1608 first_error (_("missing `}'"));
1616 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1619 if (exp
.X_op
== O_constant
)
1621 if (exp
.X_add_number
1622 != (exp
.X_add_number
& 0x0000ffff))
1624 inst
.error
= _("invalid register mask");
1628 if ((range
& exp
.X_add_number
) != 0)
1630 int regno
= range
& exp
.X_add_number
;
1633 regno
= (1 << regno
) - 1;
1635 (_("Warning: duplicated register (r%d) in register list"),
1639 range
|= exp
.X_add_number
;
1643 if (inst
.reloc
.type
!= 0)
1645 inst
.error
= _("expression too complex");
1649 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1650 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1651 inst
.reloc
.pc_rel
= 0;
1655 if (*str
== '|' || *str
== '+')
1661 while (another_range
);
1667 /* Types of registers in a list. */
1676 /* Parse a VFP register list. If the string is invalid return FAIL.
1677 Otherwise return the number of registers, and set PBASE to the first
1678 register. Parses registers of type ETYPE.
1679 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1680 - Q registers can be used to specify pairs of D registers
1681 - { } can be omitted from around a singleton register list
1682 FIXME: This is not implemented, as it would require backtracking in
1685 This could be done (the meaning isn't really ambiguous), but doesn't
1686 fit in well with the current parsing framework.
1687 - 32 D registers may be used (also true for VFPv3).
1688 FIXME: Types are ignored in these register lists, which is probably a
1692 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1697 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1701 unsigned long mask
= 0;
1706 inst
.error
= _("expecting {");
1715 regtype
= REG_TYPE_VFS
;
1720 regtype
= REG_TYPE_VFD
;
1723 case REGLIST_NEON_D
:
1724 regtype
= REG_TYPE_NDQ
;
1728 if (etype
!= REGLIST_VFP_S
)
1730 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1731 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1735 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1738 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1745 base_reg
= max_regs
;
1749 int setmask
= 1, addregs
= 1;
1751 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1753 if (new_base
== FAIL
)
1755 first_error (_(reg_expected_msgs
[regtype
]));
1759 if (new_base
>= max_regs
)
1761 first_error (_("register out of range in list"));
1765 /* Note: a value of 2 * n is returned for the register Q<n>. */
1766 if (regtype
== REG_TYPE_NQ
)
1772 if (new_base
< base_reg
)
1773 base_reg
= new_base
;
1775 if (mask
& (setmask
<< new_base
))
1777 first_error (_("invalid register list"));
1781 if ((mask
>> new_base
) != 0 && ! warned
)
1783 as_tsktsk (_("register list not in ascending order"));
1787 mask
|= setmask
<< new_base
;
1790 if (*str
== '-') /* We have the start of a range expression */
1796 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1799 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1803 if (high_range
>= max_regs
)
1805 first_error (_("register out of range in list"));
1809 if (regtype
== REG_TYPE_NQ
)
1810 high_range
= high_range
+ 1;
1812 if (high_range
<= new_base
)
1814 inst
.error
= _("register range not in ascending order");
1818 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1820 if (mask
& (setmask
<< new_base
))
1822 inst
.error
= _("invalid register list");
1826 mask
|= setmask
<< new_base
;
1831 while (skip_past_comma (&str
) != FAIL
);
1835 /* Sanity check -- should have raised a parse error above. */
1836 if (count
== 0 || count
> max_regs
)
1841 /* Final test -- the registers must be consecutive. */
1843 for (i
= 0; i
< count
; i
++)
1845 if ((mask
& (1u << i
)) == 0)
1847 inst
.error
= _("non-contiguous register range");
1857 /* True if two alias types are the same. */
1860 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
1868 if (a
->defined
!= b
->defined
)
1871 if ((a
->defined
& NTA_HASTYPE
) != 0
1872 && (a
->eltype
.type
!= b
->eltype
.type
1873 || a
->eltype
.size
!= b
->eltype
.size
))
1876 if ((a
->defined
& NTA_HASINDEX
) != 0
1877 && (a
->index
!= b
->index
))
1883 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
1884 The base register is put in *PBASE.
1885 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
1887 The register stride (minus one) is put in bit 4 of the return value.
1888 Bits [6:5] encode the list length (minus one).
1889 The type of the list elements is put in *ELTYPE, if non-NULL. */
1891 #define NEON_LANE(X) ((X) & 0xf)
1892 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
1893 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
1896 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
1897 struct neon_type_el
*eltype
)
1904 int leading_brace
= 0;
1905 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
1906 const char *const incr_error
= _("register stride must be 1 or 2");
1907 const char *const type_error
= _("mismatched element/structure types in list");
1908 struct neon_typed_alias firsttype
;
1910 if (skip_past_char (&ptr
, '{') == SUCCESS
)
1915 struct neon_typed_alias atype
;
1916 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
1920 first_error (_(reg_expected_msgs
[rtype
]));
1927 if (rtype
== REG_TYPE_NQ
)
1933 else if (reg_incr
== -1)
1935 reg_incr
= getreg
- base_reg
;
1936 if (reg_incr
< 1 || reg_incr
> 2)
1938 first_error (_(incr_error
));
1942 else if (getreg
!= base_reg
+ reg_incr
* count
)
1944 first_error (_(incr_error
));
1948 if (! neon_alias_types_same (&atype
, &firsttype
))
1950 first_error (_(type_error
));
1954 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
1958 struct neon_typed_alias htype
;
1959 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
1961 lane
= NEON_INTERLEAVE_LANES
;
1962 else if (lane
!= NEON_INTERLEAVE_LANES
)
1964 first_error (_(type_error
));
1969 else if (reg_incr
!= 1)
1971 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
1975 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
1978 first_error (_(reg_expected_msgs
[rtype
]));
1981 if (! neon_alias_types_same (&htype
, &firsttype
))
1983 first_error (_(type_error
));
1986 count
+= hireg
+ dregs
- getreg
;
1990 /* If we're using Q registers, we can't use [] or [n] syntax. */
1991 if (rtype
== REG_TYPE_NQ
)
1997 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2001 else if (lane
!= atype
.index
)
2003 first_error (_(type_error
));
2007 else if (lane
== -1)
2008 lane
= NEON_INTERLEAVE_LANES
;
2009 else if (lane
!= NEON_INTERLEAVE_LANES
)
2011 first_error (_(type_error
));
2016 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2018 /* No lane set by [x]. We must be interleaving structures. */
2020 lane
= NEON_INTERLEAVE_LANES
;
2023 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2024 || (count
> 1 && reg_incr
== -1))
2026 first_error (_("error parsing element/structure list"));
2030 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2032 first_error (_("expected }"));
2040 *eltype
= firsttype
.eltype
;
2045 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2048 /* Parse an explicit relocation suffix on an expression. This is
2049 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2050 arm_reloc_hsh contains no entries, so this function can only
2051 succeed if there is no () after the word. Returns -1 on error,
2052 BFD_RELOC_UNUSED if there wasn't any suffix. */
2054 parse_reloc (char **str
)
2056 struct reloc_entry
*r
;
2060 return BFD_RELOC_UNUSED
;
2065 while (*q
&& *q
!= ')' && *q
!= ',')
2070 if ((r
= (struct reloc_entry
*)
2071 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2078 /* Directives: register aliases. */
2080 static struct reg_entry
*
2081 insert_reg_alias (char *str
, unsigned number
, int type
)
2083 struct reg_entry
*new_reg
;
2086 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2088 if (new_reg
->builtin
)
2089 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2091 /* Only warn about a redefinition if it's not defined as the
2093 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2094 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2099 name
= xstrdup (str
);
2100 new_reg
= (struct reg_entry
*) xmalloc (sizeof (struct reg_entry
));
2102 new_reg
->name
= name
;
2103 new_reg
->number
= number
;
2104 new_reg
->type
= type
;
2105 new_reg
->builtin
= FALSE
;
2106 new_reg
->neon
= NULL
;
2108 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2115 insert_neon_reg_alias (char *str
, int number
, int type
,
2116 struct neon_typed_alias
*atype
)
2118 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2122 first_error (_("attempt to redefine typed alias"));
2128 reg
->neon
= (struct neon_typed_alias
*)
2129 xmalloc (sizeof (struct neon_typed_alias
));
2130 *reg
->neon
= *atype
;
2134 /* Look for the .req directive. This is of the form:
2136 new_register_name .req existing_register_name
2138 If we find one, or if it looks sufficiently like one that we want to
2139 handle any error here, return TRUE. Otherwise return FALSE. */
2142 create_register_alias (char * newname
, char *p
)
2144 struct reg_entry
*old
;
2145 char *oldname
, *nbuf
;
2148 /* The input scrubber ensures that whitespace after the mnemonic is
2149 collapsed to single spaces. */
2151 if (strncmp (oldname
, " .req ", 6) != 0)
2155 if (*oldname
== '\0')
2158 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2161 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2165 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2166 the desired alias name, and p points to its end. If not, then
2167 the desired alias name is in the global original_case_string. */
2168 #ifdef TC_CASE_SENSITIVE
2171 newname
= original_case_string
;
2172 nlen
= strlen (newname
);
2175 nbuf
= (char *) alloca (nlen
+ 1);
2176 memcpy (nbuf
, newname
, nlen
);
2179 /* Create aliases under the new name as stated; an all-lowercase
2180 version of the new name; and an all-uppercase version of the new
2182 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2184 for (p
= nbuf
; *p
; p
++)
2187 if (strncmp (nbuf
, newname
, nlen
))
2189 /* If this attempt to create an additional alias fails, do not bother
2190 trying to create the all-lower case alias. We will fail and issue
2191 a second, duplicate error message. This situation arises when the
2192 programmer does something like:
2195 The second .req creates the "Foo" alias but then fails to create
2196 the artificial FOO alias because it has already been created by the
2198 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2202 for (p
= nbuf
; *p
; p
++)
2205 if (strncmp (nbuf
, newname
, nlen
))
2206 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2212 /* Create a Neon typed/indexed register alias using directives, e.g.:
2217 These typed registers can be used instead of the types specified after the
2218 Neon mnemonic, so long as all operands given have types. Types can also be
2219 specified directly, e.g.:
2220 vadd d0.s32, d1.s32, d2.s32 */
2223 create_neon_reg_alias (char *newname
, char *p
)
2225 enum arm_reg_type basetype
;
2226 struct reg_entry
*basereg
;
2227 struct reg_entry mybasereg
;
2228 struct neon_type ntype
;
2229 struct neon_typed_alias typeinfo
;
2230 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2233 typeinfo
.defined
= 0;
2234 typeinfo
.eltype
.type
= NT_invtype
;
2235 typeinfo
.eltype
.size
= -1;
2236 typeinfo
.index
= -1;
2240 if (strncmp (p
, " .dn ", 5) == 0)
2241 basetype
= REG_TYPE_VFD
;
2242 else if (strncmp (p
, " .qn ", 5) == 0)
2243 basetype
= REG_TYPE_NQ
;
2252 basereg
= arm_reg_parse_multi (&p
);
2254 if (basereg
&& basereg
->type
!= basetype
)
2256 as_bad (_("bad type for register"));
2260 if (basereg
== NULL
)
2263 /* Try parsing as an integer. */
2264 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2265 if (exp
.X_op
!= O_constant
)
2267 as_bad (_("expression must be constant"));
2270 basereg
= &mybasereg
;
2271 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2277 typeinfo
= *basereg
->neon
;
2279 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2281 /* We got a type. */
2282 if (typeinfo
.defined
& NTA_HASTYPE
)
2284 as_bad (_("can't redefine the type of a register alias"));
2288 typeinfo
.defined
|= NTA_HASTYPE
;
2289 if (ntype
.elems
!= 1)
2291 as_bad (_("you must specify a single type only"));
2294 typeinfo
.eltype
= ntype
.el
[0];
2297 if (skip_past_char (&p
, '[') == SUCCESS
)
2300 /* We got a scalar index. */
2302 if (typeinfo
.defined
& NTA_HASINDEX
)
2304 as_bad (_("can't redefine the index of a scalar alias"));
2308 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2310 if (exp
.X_op
!= O_constant
)
2312 as_bad (_("scalar index must be constant"));
2316 typeinfo
.defined
|= NTA_HASINDEX
;
2317 typeinfo
.index
= exp
.X_add_number
;
2319 if (skip_past_char (&p
, ']') == FAIL
)
2321 as_bad (_("expecting ]"));
2326 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2327 the desired alias name, and p points to its end. If not, then
2328 the desired alias name is in the global original_case_string. */
2329 #ifdef TC_CASE_SENSITIVE
2330 namelen
= nameend
- newname
;
2332 newname
= original_case_string
;
2333 namelen
= strlen (newname
);
2336 namebuf
= (char *) alloca (namelen
+ 1);
2337 strncpy (namebuf
, newname
, namelen
);
2338 namebuf
[namelen
] = '\0';
2340 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2341 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2343 /* Insert name in all uppercase. */
2344 for (p
= namebuf
; *p
; p
++)
2347 if (strncmp (namebuf
, newname
, namelen
))
2348 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2349 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2351 /* Insert name in all lowercase. */
2352 for (p
= namebuf
; *p
; p
++)
2355 if (strncmp (namebuf
, newname
, namelen
))
2356 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2357 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2362 /* Should never be called, as .req goes between the alias and the
2363 register name, not at the beginning of the line. */
2366 s_req (int a ATTRIBUTE_UNUSED
)
2368 as_bad (_("invalid syntax for .req directive"));
2372 s_dn (int a ATTRIBUTE_UNUSED
)
2374 as_bad (_("invalid syntax for .dn directive"));
2378 s_qn (int a ATTRIBUTE_UNUSED
)
2380 as_bad (_("invalid syntax for .qn directive"));
2383 /* The .unreq directive deletes an alias which was previously defined
2384 by .req. For example:
2390 s_unreq (int a ATTRIBUTE_UNUSED
)
2395 name
= input_line_pointer
;
2397 while (*input_line_pointer
!= 0
2398 && *input_line_pointer
!= ' '
2399 && *input_line_pointer
!= '\n')
2400 ++input_line_pointer
;
2402 saved_char
= *input_line_pointer
;
2403 *input_line_pointer
= 0;
2406 as_bad (_("invalid syntax for .unreq directive"));
2409 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2413 as_bad (_("unknown register alias '%s'"), name
);
2414 else if (reg
->builtin
)
2415 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2422 hash_delete (arm_reg_hsh
, name
, FALSE
);
2423 free ((char *) reg
->name
);
2428 /* Also locate the all upper case and all lower case versions.
2429 Do not complain if we cannot find one or the other as it
2430 was probably deleted above. */
2432 nbuf
= strdup (name
);
2433 for (p
= nbuf
; *p
; p
++)
2435 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2438 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2439 free ((char *) reg
->name
);
2445 for (p
= nbuf
; *p
; p
++)
2447 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2450 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2451 free ((char *) reg
->name
);
2461 *input_line_pointer
= saved_char
;
2462 demand_empty_rest_of_line ();
2465 /* Directives: Instruction set selection. */
2468 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2469 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2470 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2471 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2473 /* Create a new mapping symbol for the transition to STATE. */
2476 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2479 const char * symname
;
2486 type
= BSF_NO_FLAGS
;
2490 type
= BSF_NO_FLAGS
;
2494 type
= BSF_NO_FLAGS
;
2500 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2501 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2506 THUMB_SET_FUNC (symbolP
, 0);
2507 ARM_SET_THUMB (symbolP
, 0);
2508 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2512 THUMB_SET_FUNC (symbolP
, 1);
2513 ARM_SET_THUMB (symbolP
, 1);
2514 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2522 /* Save the mapping symbols for future reference. Also check that
2523 we do not place two mapping symbols at the same offset within a
2524 frag. We'll handle overlap between frags in
2525 check_mapping_symbols.
2527 If .fill or other data filling directive generates zero sized data,
2528 the mapping symbol for the following code will have the same value
2529 as the one generated for the data filling directive. In this case,
2530 we replace the old symbol with the new one at the same address. */
2533 if (frag
->tc_frag_data
.first_map
!= NULL
)
2535 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2536 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2538 frag
->tc_frag_data
.first_map
= symbolP
;
2540 if (frag
->tc_frag_data
.last_map
!= NULL
)
2542 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2543 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2544 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2546 frag
->tc_frag_data
.last_map
= symbolP
;
2549 /* We must sometimes convert a region marked as code to data during
2550 code alignment, if an odd number of bytes have to be padded. The
2551 code mapping symbol is pushed to an aligned address. */
2554 insert_data_mapping_symbol (enum mstate state
,
2555 valueT value
, fragS
*frag
, offsetT bytes
)
2557 /* If there was already a mapping symbol, remove it. */
2558 if (frag
->tc_frag_data
.last_map
!= NULL
2559 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2561 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2565 know (frag
->tc_frag_data
.first_map
== symp
);
2566 frag
->tc_frag_data
.first_map
= NULL
;
2568 frag
->tc_frag_data
.last_map
= NULL
;
2569 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2572 make_mapping_symbol (MAP_DATA
, value
, frag
);
2573 make_mapping_symbol (state
, value
+ bytes
, frag
);
2576 static void mapping_state_2 (enum mstate state
, int max_chars
);
2578 /* Set the mapping state to STATE. Only call this when about to
2579 emit some STATE bytes to the file. */
2582 mapping_state (enum mstate state
)
2584 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2586 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2588 if (mapstate
== state
)
2589 /* The mapping symbol has already been emitted.
2590 There is nothing else to do. */
2593 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2595 All ARM instructions require 4-byte alignment.
2596 (Almost) all Thumb instructions require 2-byte alignment.
2598 When emitting instructions into any section, mark the section
2601 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2602 but themselves require 2-byte alignment; this applies to some
2603 PC- relative forms. However, these cases will invovle implicit
2604 literal pool generation or an explicit .align >=2, both of
2605 which will cause the section to me marked with sufficient
2606 alignment. Thus, we don't handle those cases here. */
2607 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2609 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2610 /* This case will be evaluated later in the next else. */
2612 else if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2613 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2615 /* Only add the symbol if the offset is > 0:
2616 if we're at the first frag, check it's size > 0;
2617 if we're not at the first frag, then for sure
2618 the offset is > 0. */
2619 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2620 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2623 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2626 mapping_state_2 (state
, 0);
2630 /* Same as mapping_state, but MAX_CHARS bytes have already been
2631 allocated. Put the mapping symbol that far back. */
2634 mapping_state_2 (enum mstate state
, int max_chars
)
2636 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2638 if (!SEG_NORMAL (now_seg
))
2641 if (mapstate
== state
)
2642 /* The mapping symbol has already been emitted.
2643 There is nothing else to do. */
2646 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2647 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2650 #define mapping_state(x) ((void)0)
2651 #define mapping_state_2(x, y) ((void)0)
2654 /* Find the real, Thumb encoded start of a Thumb function. */
2658 find_real_start (symbolS
* symbolP
)
2661 const char * name
= S_GET_NAME (symbolP
);
2662 symbolS
* new_target
;
2664 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2665 #define STUB_NAME ".real_start_of"
2670 /* The compiler may generate BL instructions to local labels because
2671 it needs to perform a branch to a far away location. These labels
2672 do not have a corresponding ".real_start_of" label. We check
2673 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2674 the ".real_start_of" convention for nonlocal branches. */
2675 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2678 real_start
= ACONCAT ((STUB_NAME
, name
, NULL
));
2679 new_target
= symbol_find (real_start
);
2681 if (new_target
== NULL
)
2683 as_warn (_("Failed to find real start of function: %s\n"), name
);
2684 new_target
= symbolP
;
2692 opcode_select (int width
)
2699 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2700 as_bad (_("selected processor does not support THUMB opcodes"));
2703 /* No need to force the alignment, since we will have been
2704 coming from ARM mode, which is word-aligned. */
2705 record_alignment (now_seg
, 1);
2712 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2713 as_bad (_("selected processor does not support ARM opcodes"));
2718 frag_align (2, 0, 0);
2720 record_alignment (now_seg
, 1);
2725 as_bad (_("invalid instruction size selected (%d)"), width
);
2730 s_arm (int ignore ATTRIBUTE_UNUSED
)
2733 demand_empty_rest_of_line ();
2737 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2740 demand_empty_rest_of_line ();
2744 s_code (int unused ATTRIBUTE_UNUSED
)
2748 temp
= get_absolute_expression ();
2753 opcode_select (temp
);
2757 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2762 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2764 /* If we are not already in thumb mode go into it, EVEN if
2765 the target processor does not support thumb instructions.
2766 This is used by gcc/config/arm/lib1funcs.asm for example
2767 to compile interworking support functions even if the
2768 target processor should not support interworking. */
2772 record_alignment (now_seg
, 1);
2775 demand_empty_rest_of_line ();
2779 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2783 /* The following label is the name/address of the start of a Thumb function.
2784 We need to know this for the interworking support. */
2785 label_is_thumb_function_name
= TRUE
;
2788 /* Perform a .set directive, but also mark the alias as
2789 being a thumb function. */
2792 s_thumb_set (int equiv
)
2794 /* XXX the following is a duplicate of the code for s_set() in read.c
2795 We cannot just call that code as we need to get at the symbol that
2802 /* Especial apologies for the random logic:
2803 This just grew, and could be parsed much more simply!
2805 name
= input_line_pointer
;
2806 delim
= get_symbol_end ();
2807 end_name
= input_line_pointer
;
2810 if (*input_line_pointer
!= ',')
2813 as_bad (_("expected comma after name \"%s\""), name
);
2815 ignore_rest_of_line ();
2819 input_line_pointer
++;
2822 if (name
[0] == '.' && name
[1] == '\0')
2824 /* XXX - this should not happen to .thumb_set. */
2828 if ((symbolP
= symbol_find (name
)) == NULL
2829 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2832 /* When doing symbol listings, play games with dummy fragments living
2833 outside the normal fragment chain to record the file and line info
2835 if (listing
& LISTING_SYMBOLS
)
2837 extern struct list_info_struct
* listing_tail
;
2838 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2840 memset (dummy_frag
, 0, sizeof (fragS
));
2841 dummy_frag
->fr_type
= rs_fill
;
2842 dummy_frag
->line
= listing_tail
;
2843 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2844 dummy_frag
->fr_symbol
= symbolP
;
2848 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
2851 /* "set" symbols are local unless otherwise specified. */
2852 SF_SET_LOCAL (symbolP
);
2853 #endif /* OBJ_COFF */
2854 } /* Make a new symbol. */
2856 symbol_table_insert (symbolP
);
2861 && S_IS_DEFINED (symbolP
)
2862 && S_GET_SEGMENT (symbolP
) != reg_section
)
2863 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
2865 pseudo_set (symbolP
);
2867 demand_empty_rest_of_line ();
2869 /* XXX Now we come to the Thumb specific bit of code. */
2871 THUMB_SET_FUNC (symbolP
, 1);
2872 ARM_SET_THUMB (symbolP
, 1);
2873 #if defined OBJ_ELF || defined OBJ_COFF
2874 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2878 /* Directives: Mode selection. */
2880 /* .syntax [unified|divided] - choose the new unified syntax
2881 (same for Arm and Thumb encoding, modulo slight differences in what
2882 can be represented) or the old divergent syntax for each mode. */
2884 s_syntax (int unused ATTRIBUTE_UNUSED
)
2888 name
= input_line_pointer
;
2889 delim
= get_symbol_end ();
2891 if (!strcasecmp (name
, "unified"))
2892 unified_syntax
= TRUE
;
2893 else if (!strcasecmp (name
, "divided"))
2894 unified_syntax
= FALSE
;
2897 as_bad (_("unrecognized syntax mode \"%s\""), name
);
2900 *input_line_pointer
= delim
;
2901 demand_empty_rest_of_line ();
2904 /* Directives: sectioning and alignment. */
2906 /* Same as s_align_ptwo but align 0 => align 2. */
2909 s_align (int unused ATTRIBUTE_UNUSED
)
2914 long max_alignment
= 15;
2916 temp
= get_absolute_expression ();
2917 if (temp
> max_alignment
)
2918 as_bad (_("alignment too large: %d assumed"), temp
= max_alignment
);
2921 as_bad (_("alignment negative. 0 assumed."));
2925 if (*input_line_pointer
== ',')
2927 input_line_pointer
++;
2928 temp_fill
= get_absolute_expression ();
2940 /* Only make a frag if we HAVE to. */
2941 if (temp
&& !need_pass_2
)
2943 if (!fill_p
&& subseg_text_p (now_seg
))
2944 frag_align_code (temp
, 0);
2946 frag_align (temp
, (int) temp_fill
, 0);
2948 demand_empty_rest_of_line ();
2950 record_alignment (now_seg
, temp
);
2954 s_bss (int ignore ATTRIBUTE_UNUSED
)
2956 /* We don't support putting frags in the BSS segment, we fake it by
2957 marking in_bss, then looking at s_skip for clues. */
2958 subseg_set (bss_section
, 0);
2959 demand_empty_rest_of_line ();
2961 #ifdef md_elf_section_change_hook
2962 md_elf_section_change_hook ();
2967 s_even (int ignore ATTRIBUTE_UNUSED
)
2969 /* Never make frag if expect extra pass. */
2971 frag_align (1, 0, 0);
2973 record_alignment (now_seg
, 1);
2975 demand_empty_rest_of_line ();
2978 /* Directives: Literal pools. */
2980 static literal_pool
*
2981 find_literal_pool (void)
2983 literal_pool
* pool
;
2985 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
2987 if (pool
->section
== now_seg
2988 && pool
->sub_section
== now_subseg
)
2995 static literal_pool
*
2996 find_or_make_literal_pool (void)
2998 /* Next literal pool ID number. */
2999 static unsigned int latest_pool_num
= 1;
3000 literal_pool
* pool
;
3002 pool
= find_literal_pool ();
3006 /* Create a new pool. */
3007 pool
= (literal_pool
*) xmalloc (sizeof (* pool
));
3011 pool
->next_free_entry
= 0;
3012 pool
->section
= now_seg
;
3013 pool
->sub_section
= now_subseg
;
3014 pool
->next
= list_of_pools
;
3015 pool
->symbol
= NULL
;
3017 /* Add it to the list. */
3018 list_of_pools
= pool
;
3021 /* New pools, and emptied pools, will have a NULL symbol. */
3022 if (pool
->symbol
== NULL
)
3024 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3025 (valueT
) 0, &zero_address_frag
);
3026 pool
->id
= latest_pool_num
++;
3033 /* Add the literal in the global 'inst'
3034 structure to the relevant literal pool. */
3037 add_to_lit_pool (void)
3039 literal_pool
* pool
;
3042 pool
= find_or_make_literal_pool ();
3044 /* Check if this literal value is already in the pool. */
3045 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3047 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3048 && (inst
.reloc
.exp
.X_op
== O_constant
)
3049 && (pool
->literals
[entry
].X_add_number
3050 == inst
.reloc
.exp
.X_add_number
)
3051 && (pool
->literals
[entry
].X_unsigned
3052 == inst
.reloc
.exp
.X_unsigned
))
3055 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3056 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3057 && (pool
->literals
[entry
].X_add_number
3058 == inst
.reloc
.exp
.X_add_number
)
3059 && (pool
->literals
[entry
].X_add_symbol
3060 == inst
.reloc
.exp
.X_add_symbol
)
3061 && (pool
->literals
[entry
].X_op_symbol
3062 == inst
.reloc
.exp
.X_op_symbol
))
3066 /* Do we need to create a new entry? */
3067 if (entry
== pool
->next_free_entry
)
3069 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3071 inst
.error
= _("literal pool overflow");
3075 pool
->literals
[entry
] = inst
.reloc
.exp
;
3076 pool
->next_free_entry
+= 1;
3079 inst
.reloc
.exp
.X_op
= O_symbol
;
3080 inst
.reloc
.exp
.X_add_number
= ((int) entry
) * 4;
3081 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3086 /* Can't use symbol_new here, so have to create a symbol and then at
3087 a later date assign it a value. Thats what these functions do. */
3090 symbol_locate (symbolS
* symbolP
,
3091 const char * name
, /* It is copied, the caller can modify. */
3092 segT segment
, /* Segment identifier (SEG_<something>). */
3093 valueT valu
, /* Symbol value. */
3094 fragS
* frag
) /* Associated fragment. */
3096 unsigned int name_length
;
3097 char * preserved_copy_of_name
;
3099 name_length
= strlen (name
) + 1; /* +1 for \0. */
3100 obstack_grow (¬es
, name
, name_length
);
3101 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3103 #ifdef tc_canonicalize_symbol_name
3104 preserved_copy_of_name
=
3105 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3108 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3110 S_SET_SEGMENT (symbolP
, segment
);
3111 S_SET_VALUE (symbolP
, valu
);
3112 symbol_clear_list_pointers (symbolP
);
3114 symbol_set_frag (symbolP
, frag
);
3116 /* Link to end of symbol chain. */
3118 extern int symbol_table_frozen
;
3120 if (symbol_table_frozen
)
3124 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3126 obj_symbol_new_hook (symbolP
);
3128 #ifdef tc_symbol_new_hook
3129 tc_symbol_new_hook (symbolP
);
3133 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3134 #endif /* DEBUG_SYMS */
3139 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3142 literal_pool
* pool
;
3145 pool
= find_literal_pool ();
3147 || pool
->symbol
== NULL
3148 || pool
->next_free_entry
== 0)
3151 mapping_state (MAP_DATA
);
3153 /* Align pool as you have word accesses.
3154 Only make a frag if we have to. */
3156 frag_align (2, 0, 0);
3158 record_alignment (now_seg
, 2);
3160 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3162 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3163 (valueT
) frag_now_fix (), frag_now
);
3164 symbol_table_insert (pool
->symbol
);
3166 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3168 #if defined OBJ_COFF || defined OBJ_ELF
3169 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3172 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3173 /* First output the expression in the instruction to the pool. */
3174 emit_expr (&(pool
->literals
[entry
]), 4); /* .word */
3176 /* Mark the pool as empty. */
3177 pool
->next_free_entry
= 0;
3178 pool
->symbol
= NULL
;
3182 /* Forward declarations for functions below, in the MD interface
3184 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3185 static valueT
create_unwind_entry (int);
3186 static void start_unwind_section (const segT
, int);
3187 static void add_unwind_opcode (valueT
, int);
3188 static void flush_pending_unwind (void);
3190 /* Directives: Data. */
3193 s_arm_elf_cons (int nbytes
)
3197 #ifdef md_flush_pending_output
3198 md_flush_pending_output ();
3201 if (is_it_end_of_statement ())
3203 demand_empty_rest_of_line ();
3207 #ifdef md_cons_align
3208 md_cons_align (nbytes
);
3211 mapping_state (MAP_DATA
);
3215 char *base
= input_line_pointer
;
3219 if (exp
.X_op
!= O_symbol
)
3220 emit_expr (&exp
, (unsigned int) nbytes
);
3223 char *before_reloc
= input_line_pointer
;
3224 reloc
= parse_reloc (&input_line_pointer
);
3227 as_bad (_("unrecognized relocation suffix"));
3228 ignore_rest_of_line ();
3231 else if (reloc
== BFD_RELOC_UNUSED
)
3232 emit_expr (&exp
, (unsigned int) nbytes
);
3235 reloc_howto_type
*howto
= (reloc_howto_type
*)
3236 bfd_reloc_type_lookup (stdoutput
,
3237 (bfd_reloc_code_real_type
) reloc
);
3238 int size
= bfd_get_reloc_size (howto
);
3240 if (reloc
== BFD_RELOC_ARM_PLT32
)
3242 as_bad (_("(plt) is only valid on branch targets"));
3243 reloc
= BFD_RELOC_UNUSED
;
3248 as_bad (_("%s relocations do not fit in %d bytes"),
3249 howto
->name
, nbytes
);
3252 /* We've parsed an expression stopping at O_symbol.
3253 But there may be more expression left now that we
3254 have parsed the relocation marker. Parse it again.
3255 XXX Surely there is a cleaner way to do this. */
3256 char *p
= input_line_pointer
;
3258 char *save_buf
= (char *) alloca (input_line_pointer
- base
);
3259 memcpy (save_buf
, base
, input_line_pointer
- base
);
3260 memmove (base
+ (input_line_pointer
- before_reloc
),
3261 base
, before_reloc
- base
);
3263 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3265 memcpy (base
, save_buf
, p
- base
);
3267 offset
= nbytes
- size
;
3268 p
= frag_more ((int) nbytes
);
3269 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3270 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3275 while (*input_line_pointer
++ == ',');
3277 /* Put terminator back into stream. */
3278 input_line_pointer
--;
3279 demand_empty_rest_of_line ();
3282 /* Emit an expression containing a 32-bit thumb instruction.
3283 Implementation based on put_thumb32_insn. */
3286 emit_thumb32_expr (expressionS
* exp
)
3288 expressionS exp_high
= *exp
;
3290 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3291 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3292 exp
->X_add_number
&= 0xffff;
3293 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3296 /* Guess the instruction size based on the opcode. */
3299 thumb_insn_size (int opcode
)
3301 if ((unsigned int) opcode
< 0xe800u
)
3303 else if ((unsigned int) opcode
>= 0xe8000000u
)
3310 emit_insn (expressionS
*exp
, int nbytes
)
3314 if (exp
->X_op
== O_constant
)
3319 size
= thumb_insn_size (exp
->X_add_number
);
3323 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3325 as_bad (_(".inst.n operand too big. "\
3326 "Use .inst.w instead"));
3331 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3332 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3334 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3336 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3337 emit_thumb32_expr (exp
);
3339 emit_expr (exp
, (unsigned int) size
);
3341 it_fsm_post_encode ();
3345 as_bad (_("cannot determine Thumb instruction size. " \
3346 "Use .inst.n/.inst.w instead"));
3349 as_bad (_("constant expression required"));
3354 /* Like s_arm_elf_cons but do not use md_cons_align and
3355 set the mapping state to MAP_ARM/MAP_THUMB. */
3358 s_arm_elf_inst (int nbytes
)
3360 if (is_it_end_of_statement ())
3362 demand_empty_rest_of_line ();
3366 /* Calling mapping_state () here will not change ARM/THUMB,
3367 but will ensure not to be in DATA state. */
3370 mapping_state (MAP_THUMB
);
3375 as_bad (_("width suffixes are invalid in ARM mode"));
3376 ignore_rest_of_line ();
3382 mapping_state (MAP_ARM
);
3391 if (! emit_insn (& exp
, nbytes
))
3393 ignore_rest_of_line ();
3397 while (*input_line_pointer
++ == ',');
3399 /* Put terminator back into stream. */
3400 input_line_pointer
--;
3401 demand_empty_rest_of_line ();
3404 /* Parse a .rel31 directive. */
3407 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3414 if (*input_line_pointer
== '1')
3415 highbit
= 0x80000000;
3416 else if (*input_line_pointer
!= '0')
3417 as_bad (_("expected 0 or 1"));
3419 input_line_pointer
++;
3420 if (*input_line_pointer
!= ',')
3421 as_bad (_("missing comma"));
3422 input_line_pointer
++;
3424 #ifdef md_flush_pending_output
3425 md_flush_pending_output ();
3428 #ifdef md_cons_align
3432 mapping_state (MAP_DATA
);
3437 md_number_to_chars (p
, highbit
, 4);
3438 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3439 BFD_RELOC_ARM_PREL31
);
3441 demand_empty_rest_of_line ();
3444 /* Directives: AEABI stack-unwind tables. */
3446 /* Parse an unwind_fnstart directive. Simply records the current location. */
3449 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3451 demand_empty_rest_of_line ();
3452 if (unwind
.proc_start
)
3454 as_bad (_("duplicate .fnstart directive"));
3458 /* Mark the start of the function. */
3459 unwind
.proc_start
= expr_build_dot ();
3461 /* Reset the rest of the unwind info. */
3462 unwind
.opcode_count
= 0;
3463 unwind
.table_entry
= NULL
;
3464 unwind
.personality_routine
= NULL
;
3465 unwind
.personality_index
= -1;
3466 unwind
.frame_size
= 0;
3467 unwind
.fp_offset
= 0;
3468 unwind
.fp_reg
= REG_SP
;
3470 unwind
.sp_restored
= 0;
3474 /* Parse a handlerdata directive. Creates the exception handling table entry
3475 for the function. */
3478 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3480 demand_empty_rest_of_line ();
3481 if (!unwind
.proc_start
)
3482 as_bad (MISSING_FNSTART
);
3484 if (unwind
.table_entry
)
3485 as_bad (_("duplicate .handlerdata directive"));
3487 create_unwind_entry (1);
3490 /* Parse an unwind_fnend directive. Generates the index table entry. */
3493 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3498 unsigned int marked_pr_dependency
;
3500 demand_empty_rest_of_line ();
3502 if (!unwind
.proc_start
)
3504 as_bad (_(".fnend directive without .fnstart"));
3508 /* Add eh table entry. */
3509 if (unwind
.table_entry
== NULL
)
3510 val
= create_unwind_entry (0);
3514 /* Add index table entry. This is two words. */
3515 start_unwind_section (unwind
.saved_seg
, 1);
3516 frag_align (2, 0, 0);
3517 record_alignment (now_seg
, 2);
3519 ptr
= frag_more (8);
3520 where
= frag_now_fix () - 8;
3522 /* Self relative offset of the function start. */
3523 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3524 BFD_RELOC_ARM_PREL31
);
3526 /* Indicate dependency on EHABI-defined personality routines to the
3527 linker, if it hasn't been done already. */
3528 marked_pr_dependency
3529 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3530 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3531 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3533 static const char *const name
[] =
3535 "__aeabi_unwind_cpp_pr0",
3536 "__aeabi_unwind_cpp_pr1",
3537 "__aeabi_unwind_cpp_pr2"
3539 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3540 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3541 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3542 |= 1 << unwind
.personality_index
;
3546 /* Inline exception table entry. */
3547 md_number_to_chars (ptr
+ 4, val
, 4);
3549 /* Self relative offset of the table entry. */
3550 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3551 BFD_RELOC_ARM_PREL31
);
3553 /* Restore the original section. */
3554 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3556 unwind
.proc_start
= NULL
;
3560 /* Parse an unwind_cantunwind directive. */
3563 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3565 demand_empty_rest_of_line ();
3566 if (!unwind
.proc_start
)
3567 as_bad (MISSING_FNSTART
);
3569 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3570 as_bad (_("personality routine specified for cantunwind frame"));
3572 unwind
.personality_index
= -2;
3576 /* Parse a personalityindex directive. */
3579 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3583 if (!unwind
.proc_start
)
3584 as_bad (MISSING_FNSTART
);
3586 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3587 as_bad (_("duplicate .personalityindex directive"));
3591 if (exp
.X_op
!= O_constant
3592 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3594 as_bad (_("bad personality routine number"));
3595 ignore_rest_of_line ();
3599 unwind
.personality_index
= exp
.X_add_number
;
3601 demand_empty_rest_of_line ();
3605 /* Parse a personality directive. */
3608 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3612 if (!unwind
.proc_start
)
3613 as_bad (MISSING_FNSTART
);
3615 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3616 as_bad (_("duplicate .personality directive"));
3618 name
= input_line_pointer
;
3619 c
= get_symbol_end ();
3620 p
= input_line_pointer
;
3621 unwind
.personality_routine
= symbol_find_or_make (name
);
3623 demand_empty_rest_of_line ();
3627 /* Parse a directive saving core registers. */
3630 s_arm_unwind_save_core (void)
3636 range
= parse_reg_list (&input_line_pointer
);
3639 as_bad (_("expected register list"));
3640 ignore_rest_of_line ();
3644 demand_empty_rest_of_line ();
3646 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
3647 into .unwind_save {..., sp...}. We aren't bothered about the value of
3648 ip because it is clobbered by calls. */
3649 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
3650 && (range
& 0x3000) == 0x1000)
3652 unwind
.opcode_count
--;
3653 unwind
.sp_restored
= 0;
3654 range
= (range
| 0x2000) & ~0x1000;
3655 unwind
.pending_offset
= 0;
3661 /* See if we can use the short opcodes. These pop a block of up to 8
3662 registers starting with r4, plus maybe r14. */
3663 for (n
= 0; n
< 8; n
++)
3665 /* Break at the first non-saved register. */
3666 if ((range
& (1 << (n
+ 4))) == 0)
3669 /* See if there are any other bits set. */
3670 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
3672 /* Use the long form. */
3673 op
= 0x8000 | ((range
>> 4) & 0xfff);
3674 add_unwind_opcode (op
, 2);
3678 /* Use the short form. */
3680 op
= 0xa8; /* Pop r14. */
3682 op
= 0xa0; /* Do not pop r14. */
3684 add_unwind_opcode (op
, 1);
3691 op
= 0xb100 | (range
& 0xf);
3692 add_unwind_opcode (op
, 2);
3695 /* Record the number of bytes pushed. */
3696 for (n
= 0; n
< 16; n
++)
3698 if (range
& (1 << n
))
3699 unwind
.frame_size
+= 4;
3704 /* Parse a directive saving FPA registers. */
3707 s_arm_unwind_save_fpa (int reg
)
3713 /* Get Number of registers to transfer. */
3714 if (skip_past_comma (&input_line_pointer
) != FAIL
)
3717 exp
.X_op
= O_illegal
;
3719 if (exp
.X_op
!= O_constant
)
3721 as_bad (_("expected , <constant>"));
3722 ignore_rest_of_line ();
3726 num_regs
= exp
.X_add_number
;
3728 if (num_regs
< 1 || num_regs
> 4)
3730 as_bad (_("number of registers must be in the range [1:4]"));
3731 ignore_rest_of_line ();
3735 demand_empty_rest_of_line ();
3740 op
= 0xb4 | (num_regs
- 1);
3741 add_unwind_opcode (op
, 1);
3746 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
3747 add_unwind_opcode (op
, 2);
3749 unwind
.frame_size
+= num_regs
* 12;
3753 /* Parse a directive saving VFP registers for ARMv6 and above. */
3756 s_arm_unwind_save_vfp_armv6 (void)
3761 int num_vfpv3_regs
= 0;
3762 int num_regs_below_16
;
3764 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
3767 as_bad (_("expected register list"));
3768 ignore_rest_of_line ();
3772 demand_empty_rest_of_line ();
3774 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
3775 than FSTMX/FLDMX-style ones). */
3777 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
3779 num_vfpv3_regs
= count
;
3780 else if (start
+ count
> 16)
3781 num_vfpv3_regs
= start
+ count
- 16;
3783 if (num_vfpv3_regs
> 0)
3785 int start_offset
= start
> 16 ? start
- 16 : 0;
3786 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
3787 add_unwind_opcode (op
, 2);
3790 /* Generate opcode for registers numbered in the range 0 .. 15. */
3791 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
3792 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
3793 if (num_regs_below_16
> 0)
3795 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
3796 add_unwind_opcode (op
, 2);
3799 unwind
.frame_size
+= count
* 8;
3803 /* Parse a directive saving VFP registers for pre-ARMv6. */
3806 s_arm_unwind_save_vfp (void)
3812 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
3815 as_bad (_("expected register list"));
3816 ignore_rest_of_line ();
3820 demand_empty_rest_of_line ();
3825 op
= 0xb8 | (count
- 1);
3826 add_unwind_opcode (op
, 1);
3831 op
= 0xb300 | (reg
<< 4) | (count
- 1);
3832 add_unwind_opcode (op
, 2);
3834 unwind
.frame_size
+= count
* 8 + 4;
3838 /* Parse a directive saving iWMMXt data registers. */
3841 s_arm_unwind_save_mmxwr (void)
3849 if (*input_line_pointer
== '{')
3850 input_line_pointer
++;
3854 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3858 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3863 as_tsktsk (_("register list not in ascending order"));
3866 if (*input_line_pointer
== '-')
3868 input_line_pointer
++;
3869 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
3872 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
3875 else if (reg
>= hi_reg
)
3877 as_bad (_("bad register range"));
3880 for (; reg
< hi_reg
; reg
++)
3884 while (skip_past_comma (&input_line_pointer
) != FAIL
);
3886 if (*input_line_pointer
== '}')
3887 input_line_pointer
++;
3889 demand_empty_rest_of_line ();
3891 /* Generate any deferred opcodes because we're going to be looking at
3893 flush_pending_unwind ();
3895 for (i
= 0; i
< 16; i
++)
3897 if (mask
& (1 << i
))
3898 unwind
.frame_size
+= 8;
3901 /* Attempt to combine with a previous opcode. We do this because gcc
3902 likes to output separate unwind directives for a single block of
3904 if (unwind
.opcode_count
> 0)
3906 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
3907 if ((i
& 0xf8) == 0xc0)
3910 /* Only merge if the blocks are contiguous. */
3913 if ((mask
& 0xfe00) == (1 << 9))
3915 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
3916 unwind
.opcode_count
--;
3919 else if (i
== 6 && unwind
.opcode_count
>= 2)
3921 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
3925 op
= 0xffff << (reg
- 1);
3927 && ((mask
& op
) == (1u << (reg
- 1))))
3929 op
= (1 << (reg
+ i
+ 1)) - 1;
3930 op
&= ~((1 << reg
) - 1);
3932 unwind
.opcode_count
-= 2;
3939 /* We want to generate opcodes in the order the registers have been
3940 saved, ie. descending order. */
3941 for (reg
= 15; reg
>= -1; reg
--)
3943 /* Save registers in blocks. */
3945 || !(mask
& (1 << reg
)))
3947 /* We found an unsaved reg. Generate opcodes to save the
3954 op
= 0xc0 | (hi_reg
- 10);
3955 add_unwind_opcode (op
, 1);
3960 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
3961 add_unwind_opcode (op
, 2);
3970 ignore_rest_of_line ();
3974 s_arm_unwind_save_mmxwcg (void)
3981 if (*input_line_pointer
== '{')
3982 input_line_pointer
++;
3986 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
3990 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
3996 as_tsktsk (_("register list not in ascending order"));
3999 if (*input_line_pointer
== '-')
4001 input_line_pointer
++;
4002 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4005 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4008 else if (reg
>= hi_reg
)
4010 as_bad (_("bad register range"));
4013 for (; reg
< hi_reg
; reg
++)
4017 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4019 if (*input_line_pointer
== '}')
4020 input_line_pointer
++;
4022 demand_empty_rest_of_line ();
4024 /* Generate any deferred opcodes because we're going to be looking at
4026 flush_pending_unwind ();
4028 for (reg
= 0; reg
< 16; reg
++)
4030 if (mask
& (1 << reg
))
4031 unwind
.frame_size
+= 4;
4034 add_unwind_opcode (op
, 2);
4037 ignore_rest_of_line ();
4041 /* Parse an unwind_save directive.
4042 If the argument is non-zero, this is a .vsave directive. */
4045 s_arm_unwind_save (int arch_v6
)
4048 struct reg_entry
*reg
;
4049 bfd_boolean had_brace
= FALSE
;
4051 if (!unwind
.proc_start
)
4052 as_bad (MISSING_FNSTART
);
4054 /* Figure out what sort of save we have. */
4055 peek
= input_line_pointer
;
4063 reg
= arm_reg_parse_multi (&peek
);
4067 as_bad (_("register expected"));
4068 ignore_rest_of_line ();
4077 as_bad (_("FPA .unwind_save does not take a register list"));
4078 ignore_rest_of_line ();
4081 input_line_pointer
= peek
;
4082 s_arm_unwind_save_fpa (reg
->number
);
4085 case REG_TYPE_RN
: s_arm_unwind_save_core (); return;
4088 s_arm_unwind_save_vfp_armv6 ();
4090 s_arm_unwind_save_vfp ();
4092 case REG_TYPE_MMXWR
: s_arm_unwind_save_mmxwr (); return;
4093 case REG_TYPE_MMXWCG
: s_arm_unwind_save_mmxwcg (); return;
4096 as_bad (_(".unwind_save does not support this kind of register"));
4097 ignore_rest_of_line ();
4102 /* Parse an unwind_movsp directive. */
4105 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4111 if (!unwind
.proc_start
)
4112 as_bad (MISSING_FNSTART
);
4114 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4117 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4118 ignore_rest_of_line ();
4122 /* Optional constant. */
4123 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4125 if (immediate_for_directive (&offset
) == FAIL
)
4131 demand_empty_rest_of_line ();
4133 if (reg
== REG_SP
|| reg
== REG_PC
)
4135 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4139 if (unwind
.fp_reg
!= REG_SP
)
4140 as_bad (_("unexpected .unwind_movsp directive"));
4142 /* Generate opcode to restore the value. */
4144 add_unwind_opcode (op
, 1);
4146 /* Record the information for later. */
4147 unwind
.fp_reg
= reg
;
4148 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4149 unwind
.sp_restored
= 1;
4152 /* Parse an unwind_pad directive. */
4155 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4159 if (!unwind
.proc_start
)
4160 as_bad (MISSING_FNSTART
);
4162 if (immediate_for_directive (&offset
) == FAIL
)
4167 as_bad (_("stack increment must be multiple of 4"));
4168 ignore_rest_of_line ();
4172 /* Don't generate any opcodes, just record the details for later. */
4173 unwind
.frame_size
+= offset
;
4174 unwind
.pending_offset
+= offset
;
4176 demand_empty_rest_of_line ();
4179 /* Parse an unwind_setfp directive. */
4182 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4188 if (!unwind
.proc_start
)
4189 as_bad (MISSING_FNSTART
);
4191 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4192 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4195 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4197 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4199 as_bad (_("expected <reg>, <reg>"));
4200 ignore_rest_of_line ();
4204 /* Optional constant. */
4205 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4207 if (immediate_for_directive (&offset
) == FAIL
)
4213 demand_empty_rest_of_line ();
4215 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4217 as_bad (_("register must be either sp or set by a previous"
4218 "unwind_movsp directive"));
4222 /* Don't generate any opcodes, just record the information for later. */
4223 unwind
.fp_reg
= fp_reg
;
4225 if (sp_reg
== REG_SP
)
4226 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4228 unwind
.fp_offset
-= offset
;
4231 /* Parse an unwind_raw directive. */
4234 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4237 /* This is an arbitrary limit. */
4238 unsigned char op
[16];
4241 if (!unwind
.proc_start
)
4242 as_bad (MISSING_FNSTART
);
4245 if (exp
.X_op
== O_constant
4246 && skip_past_comma (&input_line_pointer
) != FAIL
)
4248 unwind
.frame_size
+= exp
.X_add_number
;
4252 exp
.X_op
= O_illegal
;
4254 if (exp
.X_op
!= O_constant
)
4256 as_bad (_("expected <offset>, <opcode>"));
4257 ignore_rest_of_line ();
4263 /* Parse the opcode. */
4268 as_bad (_("unwind opcode too long"));
4269 ignore_rest_of_line ();
4271 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4273 as_bad (_("invalid unwind opcode"));
4274 ignore_rest_of_line ();
4277 op
[count
++] = exp
.X_add_number
;
4279 /* Parse the next byte. */
4280 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4286 /* Add the opcode bytes in reverse order. */
4288 add_unwind_opcode (op
[count
], 1);
4290 demand_empty_rest_of_line ();
4294 /* Parse a .eabi_attribute directive. */
4297 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4299 int tag
= s_vendor_attribute (OBJ_ATTR_PROC
);
4301 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4302 attributes_set_explicitly
[tag
] = 1;
4305 /* Emit a tls fix for the symbol. */
4308 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4312 #ifdef md_flush_pending_output
4313 md_flush_pending_output ();
4316 #ifdef md_cons_align
4320 /* Since we're just labelling the code, there's no need to define a
4323 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4324 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4325 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4326 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4328 #endif /* OBJ_ELF */
4330 static void s_arm_arch (int);
4331 static void s_arm_object_arch (int);
4332 static void s_arm_cpu (int);
4333 static void s_arm_fpu (int);
4334 static void s_arm_arch_extension (int);
4339 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4346 if (exp
.X_op
== O_symbol
)
4347 exp
.X_op
= O_secrel
;
4349 emit_expr (&exp
, 4);
4351 while (*input_line_pointer
++ == ',');
4353 input_line_pointer
--;
4354 demand_empty_rest_of_line ();
4358 /* This table describes all the machine specific pseudo-ops the assembler
4359 has to support. The fields are:
4360 pseudo-op name without dot
4361 function to call to execute this pseudo-op
4362 Integer arg to pass to the function. */
4364 const pseudo_typeS md_pseudo_table
[] =
4366 /* Never called because '.req' does not start a line. */
4367 { "req", s_req
, 0 },
4368 /* Following two are likewise never called. */
4371 { "unreq", s_unreq
, 0 },
4372 { "bss", s_bss
, 0 },
4373 { "align", s_align
, 0 },
4374 { "arm", s_arm
, 0 },
4375 { "thumb", s_thumb
, 0 },
4376 { "code", s_code
, 0 },
4377 { "force_thumb", s_force_thumb
, 0 },
4378 { "thumb_func", s_thumb_func
, 0 },
4379 { "thumb_set", s_thumb_set
, 0 },
4380 { "even", s_even
, 0 },
4381 { "ltorg", s_ltorg
, 0 },
4382 { "pool", s_ltorg
, 0 },
4383 { "syntax", s_syntax
, 0 },
4384 { "cpu", s_arm_cpu
, 0 },
4385 { "arch", s_arm_arch
, 0 },
4386 { "object_arch", s_arm_object_arch
, 0 },
4387 { "fpu", s_arm_fpu
, 0 },
4388 { "arch_extension", s_arm_arch_extension
, 0 },
4390 { "word", s_arm_elf_cons
, 4 },
4391 { "long", s_arm_elf_cons
, 4 },
4392 { "inst.n", s_arm_elf_inst
, 2 },
4393 { "inst.w", s_arm_elf_inst
, 4 },
4394 { "inst", s_arm_elf_inst
, 0 },
4395 { "rel31", s_arm_rel31
, 0 },
4396 { "fnstart", s_arm_unwind_fnstart
, 0 },
4397 { "fnend", s_arm_unwind_fnend
, 0 },
4398 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4399 { "personality", s_arm_unwind_personality
, 0 },
4400 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4401 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4402 { "save", s_arm_unwind_save
, 0 },
4403 { "vsave", s_arm_unwind_save
, 1 },
4404 { "movsp", s_arm_unwind_movsp
, 0 },
4405 { "pad", s_arm_unwind_pad
, 0 },
4406 { "setfp", s_arm_unwind_setfp
, 0 },
4407 { "unwind_raw", s_arm_unwind_raw
, 0 },
4408 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4409 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4413 /* These are used for dwarf. */
4417 /* These are used for dwarf2. */
4418 { "file", (void (*) (int)) dwarf2_directive_file
, 0 },
4419 { "loc", dwarf2_directive_loc
, 0 },
4420 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4422 { "extend", float_cons
, 'x' },
4423 { "ldouble", float_cons
, 'x' },
4424 { "packed", float_cons
, 'p' },
4426 {"secrel32", pe_directive_secrel
, 0},
4431 /* Parser functions used exclusively in instruction operands. */
4433 /* Generic immediate-value read function for use in insn parsing.
4434 STR points to the beginning of the immediate (the leading #);
4435 VAL receives the value; if the value is outside [MIN, MAX]
4436 issue an error. PREFIX_OPT is true if the immediate prefix is
4440 parse_immediate (char **str
, int *val
, int min
, int max
,
4441 bfd_boolean prefix_opt
)
4444 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4445 if (exp
.X_op
!= O_constant
)
4447 inst
.error
= _("constant expression required");
4451 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4453 inst
.error
= _("immediate value out of range");
4457 *val
= exp
.X_add_number
;
4461 /* Less-generic immediate-value read function with the possibility of loading a
4462 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4463 instructions. Puts the result directly in inst.operands[i]. */
4466 parse_big_immediate (char **str
, int i
)
4471 my_get_expression (&exp
, &ptr
, GE_OPT_PREFIX_BIG
);
4473 if (exp
.X_op
== O_constant
)
4475 inst
.operands
[i
].imm
= exp
.X_add_number
& 0xffffffff;
4476 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4477 O_constant. We have to be careful not to break compilation for
4478 32-bit X_add_number, though. */
4479 if ((exp
.X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4481 /* X >> 32 is illegal if sizeof (exp.X_add_number) == 4. */
4482 inst
.operands
[i
].reg
= ((exp
.X_add_number
>> 16) >> 16) & 0xffffffff;
4483 inst
.operands
[i
].regisimm
= 1;
4486 else if (exp
.X_op
== O_big
4487 && LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 32)
4489 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4491 /* Bignums have their least significant bits in
4492 generic_bignum[0]. Make sure we put 32 bits in imm and
4493 32 bits in reg, in a (hopefully) portable way. */
4494 gas_assert (parts
!= 0);
4496 /* Make sure that the number is not too big.
4497 PR 11972: Bignums can now be sign-extended to the
4498 size of a .octa so check that the out of range bits
4499 are all zero or all one. */
4500 if (LITTLENUM_NUMBER_OF_BITS
* exp
.X_add_number
> 64)
4502 LITTLENUM_TYPE m
= -1;
4504 if (generic_bignum
[parts
* 2] != 0
4505 && generic_bignum
[parts
* 2] != m
)
4508 for (j
= parts
* 2 + 1; j
< (unsigned) exp
.X_add_number
; j
++)
4509 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4513 inst
.operands
[i
].imm
= 0;
4514 for (j
= 0; j
< parts
; j
++, idx
++)
4515 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4516 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4517 inst
.operands
[i
].reg
= 0;
4518 for (j
= 0; j
< parts
; j
++, idx
++)
4519 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4520 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4521 inst
.operands
[i
].regisimm
= 1;
4531 /* Returns the pseudo-register number of an FPA immediate constant,
4532 or FAIL if there isn't a valid constant here. */
4535 parse_fpa_immediate (char ** str
)
4537 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4543 /* First try and match exact strings, this is to guarantee
4544 that some formats will work even for cross assembly. */
4546 for (i
= 0; fp_const
[i
]; i
++)
4548 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4552 *str
+= strlen (fp_const
[i
]);
4553 if (is_end_of_line
[(unsigned char) **str
])
4559 /* Just because we didn't get a match doesn't mean that the constant
4560 isn't valid, just that it is in a format that we don't
4561 automatically recognize. Try parsing it with the standard
4562 expression routines. */
4564 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4566 /* Look for a raw floating point number. */
4567 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4568 && is_end_of_line
[(unsigned char) *save_in
])
4570 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4572 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4574 if (words
[j
] != fp_values
[i
][j
])
4578 if (j
== MAX_LITTLENUMS
)
4586 /* Try and parse a more complex expression, this will probably fail
4587 unless the code uses a floating point prefix (eg "0f"). */
4588 save_in
= input_line_pointer
;
4589 input_line_pointer
= *str
;
4590 if (expression (&exp
) == absolute_section
4591 && exp
.X_op
== O_big
4592 && exp
.X_add_number
< 0)
4594 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4596 if (gen_to_words (words
, 5, (long) 15) == 0)
4598 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4600 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4602 if (words
[j
] != fp_values
[i
][j
])
4606 if (j
== MAX_LITTLENUMS
)
4608 *str
= input_line_pointer
;
4609 input_line_pointer
= save_in
;
4616 *str
= input_line_pointer
;
4617 input_line_pointer
= save_in
;
4618 inst
.error
= _("invalid FPA immediate expression");
4622 /* Returns 1 if a number has "quarter-precision" float format
4623 0baBbbbbbc defgh000 00000000 00000000. */
4626 is_quarter_float (unsigned imm
)
4628 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
4629 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
4632 /* Parse an 8-bit "quarter-precision" floating point number of the form:
4633 0baBbbbbbc defgh000 00000000 00000000.
4634 The zero and minus-zero cases need special handling, since they can't be
4635 encoded in the "quarter-precision" float format, but can nonetheless be
4636 loaded as integer constants. */
4639 parse_qfloat_immediate (char **ccp
, int *immed
)
4643 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4644 int found_fpchar
= 0;
4646 skip_past_char (&str
, '#');
4648 /* We must not accidentally parse an integer as a floating-point number. Make
4649 sure that the value we parse is not an integer by checking for special
4650 characters '.' or 'e'.
4651 FIXME: This is a horrible hack, but doing better is tricky because type
4652 information isn't in a very usable state at parse time. */
4654 skip_whitespace (fpnum
);
4656 if (strncmp (fpnum
, "0x", 2) == 0)
4660 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
4661 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
4671 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
4673 unsigned fpword
= 0;
4676 /* Our FP word must be 32 bits (single-precision FP). */
4677 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
4679 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
4683 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
4696 /* Shift operands. */
4699 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
4702 struct asm_shift_name
4705 enum shift_kind kind
;
4708 /* Third argument to parse_shift. */
4709 enum parse_shift_mode
4711 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
4712 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
4713 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
4714 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
4715 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
4718 /* Parse a <shift> specifier on an ARM data processing instruction.
4719 This has three forms:
4721 (LSL|LSR|ASL|ASR|ROR) Rs
4722 (LSL|LSR|ASL|ASR|ROR) #imm
4725 Note that ASL is assimilated to LSL in the instruction encoding, and
4726 RRX to ROR #0 (which cannot be written as such). */
4729 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
4731 const struct asm_shift_name
*shift_name
;
4732 enum shift_kind shift
;
4737 for (p
= *str
; ISALPHA (*p
); p
++)
4742 inst
.error
= _("shift expression expected");
4746 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
4749 if (shift_name
== NULL
)
4751 inst
.error
= _("shift expression expected");
4755 shift
= shift_name
->kind
;
4759 case NO_SHIFT_RESTRICT
:
4760 case SHIFT_IMMEDIATE
: break;
4762 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
4763 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
4765 inst
.error
= _("'LSL' or 'ASR' required");
4770 case SHIFT_LSL_IMMEDIATE
:
4771 if (shift
!= SHIFT_LSL
)
4773 inst
.error
= _("'LSL' required");
4778 case SHIFT_ASR_IMMEDIATE
:
4779 if (shift
!= SHIFT_ASR
)
4781 inst
.error
= _("'ASR' required");
4789 if (shift
!= SHIFT_RRX
)
4791 /* Whitespace can appear here if the next thing is a bare digit. */
4792 skip_whitespace (p
);
4794 if (mode
== NO_SHIFT_RESTRICT
4795 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
4797 inst
.operands
[i
].imm
= reg
;
4798 inst
.operands
[i
].immisreg
= 1;
4800 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
4803 inst
.operands
[i
].shift_kind
= shift
;
4804 inst
.operands
[i
].shifted
= 1;
4809 /* Parse a <shifter_operand> for an ARM data processing instruction:
4812 #<immediate>, <rotate>
4816 where <shift> is defined by parse_shift above, and <rotate> is a
4817 multiple of 2 between 0 and 30. Validation of immediate operands
4818 is deferred to md_apply_fix. */
4821 parse_shifter_operand (char **str
, int i
)
4826 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
4828 inst
.operands
[i
].reg
= value
;
4829 inst
.operands
[i
].isreg
= 1;
4831 /* parse_shift will override this if appropriate */
4832 inst
.reloc
.exp
.X_op
= O_constant
;
4833 inst
.reloc
.exp
.X_add_number
= 0;
4835 if (skip_past_comma (str
) == FAIL
)
4838 /* Shift operation on register. */
4839 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
4842 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
4845 if (skip_past_comma (str
) == SUCCESS
)
4847 /* #x, y -- ie explicit rotation by Y. */
4848 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
4851 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
4853 inst
.error
= _("constant expression expected");
4857 value
= exp
.X_add_number
;
4858 if (value
< 0 || value
> 30 || value
% 2 != 0)
4860 inst
.error
= _("invalid rotation");
4863 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
4865 inst
.error
= _("invalid constant");
4869 /* Convert to decoded value. md_apply_fix will put it back. */
4870 inst
.reloc
.exp
.X_add_number
4871 = (((inst
.reloc
.exp
.X_add_number
<< (32 - value
))
4872 | (inst
.reloc
.exp
.X_add_number
>> value
)) & 0xffffffff);
4875 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
4876 inst
.reloc
.pc_rel
= 0;
4880 /* Group relocation information. Each entry in the table contains the
4881 textual name of the relocation as may appear in assembler source
4882 and must end with a colon.
4883 Along with this textual name are the relocation codes to be used if
4884 the corresponding instruction is an ALU instruction (ADD or SUB only),
4885 an LDR, an LDRS, or an LDC. */
4887 struct group_reloc_table_entry
4898 /* Varieties of non-ALU group relocation. */
4905 static struct group_reloc_table_entry group_reloc_table
[] =
4906 { /* Program counter relative: */
4908 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
4913 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
4914 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
4915 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
4916 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
4918 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
4923 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
4924 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
4925 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
4926 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
4928 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
4929 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
4930 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
4931 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
4932 /* Section base relative */
4934 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
4939 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
4940 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
4941 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
4942 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
4944 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
4949 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
4950 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
4951 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
4952 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
4954 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
4955 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
4956 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
4957 BFD_RELOC_ARM_LDC_SB_G2
} }; /* LDC */
4959 /* Given the address of a pointer pointing to the textual name of a group
4960 relocation as may appear in assembler source, attempt to find its details
4961 in group_reloc_table. The pointer will be updated to the character after
4962 the trailing colon. On failure, FAIL will be returned; SUCCESS
4963 otherwise. On success, *entry will be updated to point at the relevant
4964 group_reloc_table entry. */
4967 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
4970 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
4972 int length
= strlen (group_reloc_table
[i
].name
);
4974 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
4975 && (*str
)[length
] == ':')
4977 *out
= &group_reloc_table
[i
];
4978 *str
+= (length
+ 1);
4986 /* Parse a <shifter_operand> for an ARM data processing instruction
4987 (as for parse_shifter_operand) where group relocations are allowed:
4990 #<immediate>, <rotate>
4991 #:<group_reloc>:<expression>
4995 where <group_reloc> is one of the strings defined in group_reloc_table.
4996 The hashes are optional.
4998 Everything else is as for parse_shifter_operand. */
5000 static parse_operand_result
5001 parse_shifter_operand_group_reloc (char **str
, int i
)
5003 /* Determine if we have the sequence of characters #: or just :
5004 coming next. If we do, then we check for a group relocation.
5005 If we don't, punt the whole lot to parse_shifter_operand. */
5007 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5008 || (*str
)[0] == ':')
5010 struct group_reloc_table_entry
*entry
;
5012 if ((*str
)[0] == '#')
5017 /* Try to parse a group relocation. Anything else is an error. */
5018 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5020 inst
.error
= _("unknown group relocation");
5021 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5024 /* We now have the group relocation table entry corresponding to
5025 the name in the assembler source. Next, we parse the expression. */
5026 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5027 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5029 /* Record the relocation type (always the ALU variant here). */
5030 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5031 gas_assert (inst
.reloc
.type
!= 0);
5033 return PARSE_OPERAND_SUCCESS
;
5036 return parse_shifter_operand (str
, i
) == SUCCESS
5037 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5039 /* Never reached. */
5042 /* Parse a Neon alignment expression. Information is written to
5043 inst.operands[i]. We assume the initial ':' has been skipped.
5045 align .imm = align << 8, .immisalign=1, .preind=0 */
5046 static parse_operand_result
5047 parse_neon_alignment (char **str
, int i
)
5052 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5054 if (exp
.X_op
!= O_constant
)
5056 inst
.error
= _("alignment must be constant");
5057 return PARSE_OPERAND_FAIL
;
5060 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5061 inst
.operands
[i
].immisalign
= 1;
5062 /* Alignments are not pre-indexes. */
5063 inst
.operands
[i
].preind
= 0;
5066 return PARSE_OPERAND_SUCCESS
;
5069 /* Parse all forms of an ARM address expression. Information is written
5070 to inst.operands[i] and/or inst.reloc.
5072 Preindexed addressing (.preind=1):
5074 [Rn, #offset] .reg=Rn .reloc.exp=offset
5075 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5076 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5077 .shift_kind=shift .reloc.exp=shift_imm
5079 These three may have a trailing ! which causes .writeback to be set also.
5081 Postindexed addressing (.postind=1, .writeback=1):
5083 [Rn], #offset .reg=Rn .reloc.exp=offset
5084 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5085 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5086 .shift_kind=shift .reloc.exp=shift_imm
5088 Unindexed addressing (.preind=0, .postind=0):
5090 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5094 [Rn]{!} shorthand for [Rn,#0]{!}
5095 =immediate .isreg=0 .reloc.exp=immediate
5096 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5098 It is the caller's responsibility to check for addressing modes not
5099 supported by the instruction, and to set inst.reloc.type. */
5101 static parse_operand_result
5102 parse_address_main (char **str
, int i
, int group_relocations
,
5103 group_reloc_type group_type
)
5108 if (skip_past_char (&p
, '[') == FAIL
)
5110 if (skip_past_char (&p
, '=') == FAIL
)
5112 /* Bare address - translate to PC-relative offset. */
5113 inst
.reloc
.pc_rel
= 1;
5114 inst
.operands
[i
].reg
= REG_PC
;
5115 inst
.operands
[i
].isreg
= 1;
5116 inst
.operands
[i
].preind
= 1;
5118 /* Otherwise a load-constant pseudo op, no special treatment needed here. */
5120 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5121 return PARSE_OPERAND_FAIL
;
5124 return PARSE_OPERAND_SUCCESS
;
5127 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5129 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5130 return PARSE_OPERAND_FAIL
;
5132 inst
.operands
[i
].reg
= reg
;
5133 inst
.operands
[i
].isreg
= 1;
5135 if (skip_past_comma (&p
) == SUCCESS
)
5137 inst
.operands
[i
].preind
= 1;
5140 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5142 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5144 inst
.operands
[i
].imm
= reg
;
5145 inst
.operands
[i
].immisreg
= 1;
5147 if (skip_past_comma (&p
) == SUCCESS
)
5148 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5149 return PARSE_OPERAND_FAIL
;
5151 else if (skip_past_char (&p
, ':') == SUCCESS
)
5153 /* FIXME: '@' should be used here, but it's filtered out by generic
5154 code before we get to see it here. This may be subject to
5156 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5158 if (result
!= PARSE_OPERAND_SUCCESS
)
5163 if (inst
.operands
[i
].negative
)
5165 inst
.operands
[i
].negative
= 0;
5169 if (group_relocations
5170 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5172 struct group_reloc_table_entry
*entry
;
5174 /* Skip over the #: or : sequence. */
5180 /* Try to parse a group relocation. Anything else is an
5182 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5184 inst
.error
= _("unknown group relocation");
5185 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5188 /* We now have the group relocation table entry corresponding to
5189 the name in the assembler source. Next, we parse the
5191 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5192 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5194 /* Record the relocation type. */
5198 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5202 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5206 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5213 if (inst
.reloc
.type
== 0)
5215 inst
.error
= _("this group relocation is not allowed on this instruction");
5216 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5222 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5223 return PARSE_OPERAND_FAIL
;
5224 /* If the offset is 0, find out if it's a +0 or -0. */
5225 if (inst
.reloc
.exp
.X_op
== O_constant
5226 && inst
.reloc
.exp
.X_add_number
== 0)
5228 skip_whitespace (q
);
5232 skip_whitespace (q
);
5235 inst
.operands
[i
].negative
= 1;
5240 else if (skip_past_char (&p
, ':') == SUCCESS
)
5242 /* FIXME: '@' should be used here, but it's filtered out by generic code
5243 before we get to see it here. This may be subject to change. */
5244 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5246 if (result
!= PARSE_OPERAND_SUCCESS
)
5250 if (skip_past_char (&p
, ']') == FAIL
)
5252 inst
.error
= _("']' expected");
5253 return PARSE_OPERAND_FAIL
;
5256 if (skip_past_char (&p
, '!') == SUCCESS
)
5257 inst
.operands
[i
].writeback
= 1;
5259 else if (skip_past_comma (&p
) == SUCCESS
)
5261 if (skip_past_char (&p
, '{') == SUCCESS
)
5263 /* [Rn], {expr} - unindexed, with option */
5264 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5265 0, 255, TRUE
) == FAIL
)
5266 return PARSE_OPERAND_FAIL
;
5268 if (skip_past_char (&p
, '}') == FAIL
)
5270 inst
.error
= _("'}' expected at end of 'option' field");
5271 return PARSE_OPERAND_FAIL
;
5273 if (inst
.operands
[i
].preind
)
5275 inst
.error
= _("cannot combine index with option");
5276 return PARSE_OPERAND_FAIL
;
5279 return PARSE_OPERAND_SUCCESS
;
5283 inst
.operands
[i
].postind
= 1;
5284 inst
.operands
[i
].writeback
= 1;
5286 if (inst
.operands
[i
].preind
)
5288 inst
.error
= _("cannot combine pre- and post-indexing");
5289 return PARSE_OPERAND_FAIL
;
5293 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5295 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5297 /* We might be using the immediate for alignment already. If we
5298 are, OR the register number into the low-order bits. */
5299 if (inst
.operands
[i
].immisalign
)
5300 inst
.operands
[i
].imm
|= reg
;
5302 inst
.operands
[i
].imm
= reg
;
5303 inst
.operands
[i
].immisreg
= 1;
5305 if (skip_past_comma (&p
) == SUCCESS
)
5306 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5307 return PARSE_OPERAND_FAIL
;
5312 if (inst
.operands
[i
].negative
)
5314 inst
.operands
[i
].negative
= 0;
5317 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5318 return PARSE_OPERAND_FAIL
;
5319 /* If the offset is 0, find out if it's a +0 or -0. */
5320 if (inst
.reloc
.exp
.X_op
== O_constant
5321 && inst
.reloc
.exp
.X_add_number
== 0)
5323 skip_whitespace (q
);
5327 skip_whitespace (q
);
5330 inst
.operands
[i
].negative
= 1;
5336 /* If at this point neither .preind nor .postind is set, we have a
5337 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5338 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5340 inst
.operands
[i
].preind
= 1;
5341 inst
.reloc
.exp
.X_op
= O_constant
;
5342 inst
.reloc
.exp
.X_add_number
= 0;
5345 return PARSE_OPERAND_SUCCESS
;
5349 parse_address (char **str
, int i
)
5351 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5355 static parse_operand_result
5356 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5358 return parse_address_main (str
, i
, 1, type
);
5361 /* Parse an operand for a MOVW or MOVT instruction. */
5363 parse_half (char **str
)
5368 skip_past_char (&p
, '#');
5369 if (strncasecmp (p
, ":lower16:", 9) == 0)
5370 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5371 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5372 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5374 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5377 skip_whitespace (p
);
5380 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5383 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5385 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5387 inst
.error
= _("constant expression expected");
5390 if (inst
.reloc
.exp
.X_add_number
< 0
5391 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5393 inst
.error
= _("immediate value out of range");
5401 /* Miscellaneous. */
5403 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5404 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5406 parse_psr (char **str
, bfd_boolean lhs
)
5409 unsigned long psr_field
;
5410 const struct asm_psr
*psr
;
5412 bfd_boolean is_apsr
= FALSE
;
5413 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5415 /* PR gas/12698: If the user has specified -march=all then m_profile will
5416 be TRUE, but we want to ignore it in this case as we are building for any
5417 CPU type, including non-m variants. */
5418 if (selected_cpu
.core
== arm_arch_any
.core
)
5421 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5422 feature for ease of use and backwards compatibility. */
5424 if (strncasecmp (p
, "SPSR", 4) == 0)
5427 goto unsupported_psr
;
5429 psr_field
= SPSR_BIT
;
5431 else if (strncasecmp (p
, "CPSR", 4) == 0)
5434 goto unsupported_psr
;
5438 else if (strncasecmp (p
, "APSR", 4) == 0)
5440 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5441 and ARMv7-R architecture CPUs. */
5450 while (ISALNUM (*p
) || *p
== '_');
5452 if (strncasecmp (start
, "iapsr", 5) == 0
5453 || strncasecmp (start
, "eapsr", 5) == 0
5454 || strncasecmp (start
, "xpsr", 4) == 0
5455 || strncasecmp (start
, "psr", 3) == 0)
5456 p
= start
+ strcspn (start
, "rR") + 1;
5458 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5464 /* If APSR is being written, a bitfield may be specified. Note that
5465 APSR itself is handled above. */
5466 if (psr
->field
<= 3)
5468 psr_field
= psr
->field
;
5474 /* M-profile MSR instructions have the mask field set to "10", except
5475 *PSR variants which modify APSR, which may use a different mask (and
5476 have been handled already). Do that by setting the PSR_f field
5478 return psr
->field
| (lhs
? PSR_f
: 0);
5481 goto unsupported_psr
;
5487 /* A suffix follows. */
5493 while (ISALNUM (*p
) || *p
== '_');
5497 /* APSR uses a notation for bits, rather than fields. */
5498 unsigned int nzcvq_bits
= 0;
5499 unsigned int g_bit
= 0;
5502 for (bit
= start
; bit
!= p
; bit
++)
5504 switch (TOLOWER (*bit
))
5507 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5511 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5515 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5519 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5523 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5527 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5531 inst
.error
= _("unexpected bit specified after APSR");
5536 if (nzcvq_bits
== 0x1f)
5541 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5543 inst
.error
= _("selected processor does not "
5544 "support DSP extension");
5551 if ((nzcvq_bits
& 0x20) != 0
5552 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5553 || (g_bit
& 0x2) != 0)
5555 inst
.error
= _("bad bitmask specified after APSR");
5561 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
5566 psr_field
|= psr
->field
;
5572 goto error
; /* Garbage after "[CS]PSR". */
5574 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
5575 is deprecated, but allow it anyway. */
5579 as_tsktsk (_("writing to APSR without specifying a bitmask is "
5582 else if (!m_profile
)
5583 /* These bits are never right for M-profile devices: don't set them
5584 (only code paths which read/write APSR reach here). */
5585 psr_field
|= (PSR_c
| PSR_f
);
5591 inst
.error
= _("selected processor does not support requested special "
5592 "purpose register");
5596 inst
.error
= _("flag for {c}psr instruction expected");
5600 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
5601 value suitable for splatting into the AIF field of the instruction. */
5604 parse_cps_flags (char **str
)
5613 case '\0': case ',':
5616 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
5617 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
5618 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
5621 inst
.error
= _("unrecognized CPS flag");
5626 if (saw_a_flag
== 0)
5628 inst
.error
= _("missing CPS flags");
5636 /* Parse an endian specifier ("BE" or "LE", case insensitive);
5637 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
5640 parse_endian_specifier (char **str
)
5645 if (strncasecmp (s
, "BE", 2))
5647 else if (strncasecmp (s
, "LE", 2))
5651 inst
.error
= _("valid endian specifiers are be or le");
5655 if (ISALNUM (s
[2]) || s
[2] == '_')
5657 inst
.error
= _("valid endian specifiers are be or le");
5662 return little_endian
;
5665 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
5666 value suitable for poking into the rotate field of an sxt or sxta
5667 instruction, or FAIL on error. */
5670 parse_ror (char **str
)
5675 if (strncasecmp (s
, "ROR", 3) == 0)
5679 inst
.error
= _("missing rotation field after comma");
5683 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
5688 case 0: *str
= s
; return 0x0;
5689 case 8: *str
= s
; return 0x1;
5690 case 16: *str
= s
; return 0x2;
5691 case 24: *str
= s
; return 0x3;
5694 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
5699 /* Parse a conditional code (from conds[] below). The value returned is in the
5700 range 0 .. 14, or FAIL. */
5702 parse_cond (char **str
)
5705 const struct asm_cond
*c
;
5707 /* Condition codes are always 2 characters, so matching up to
5708 3 characters is sufficient. */
5713 while (ISALPHA (*q
) && n
< 3)
5715 cond
[n
] = TOLOWER (*q
);
5720 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
5723 inst
.error
= _("condition required");
5731 /* Parse an option for a barrier instruction. Returns the encoding for the
5734 parse_barrier (char **str
)
5737 const struct asm_barrier_opt
*o
;
5740 while (ISALPHA (*q
))
5743 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
5752 /* Parse the operands of a table branch instruction. Similar to a memory
5755 parse_tb (char **str
)
5760 if (skip_past_char (&p
, '[') == FAIL
)
5762 inst
.error
= _("'[' expected");
5766 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5768 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5771 inst
.operands
[0].reg
= reg
;
5773 if (skip_past_comma (&p
) == FAIL
)
5775 inst
.error
= _("',' expected");
5779 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5781 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5784 inst
.operands
[0].imm
= reg
;
5786 if (skip_past_comma (&p
) == SUCCESS
)
5788 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
5790 if (inst
.reloc
.exp
.X_add_number
!= 1)
5792 inst
.error
= _("invalid shift");
5795 inst
.operands
[0].shifted
= 1;
5798 if (skip_past_char (&p
, ']') == FAIL
)
5800 inst
.error
= _("']' expected");
5807 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
5808 information on the types the operands can take and how they are encoded.
5809 Up to four operands may be read; this function handles setting the
5810 ".present" field for each read operand itself.
5811 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
5812 else returns FAIL. */
5815 parse_neon_mov (char **str
, int *which_operand
)
5817 int i
= *which_operand
, val
;
5818 enum arm_reg_type rtype
;
5820 struct neon_type_el optype
;
5822 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5824 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
5825 inst
.operands
[i
].reg
= val
;
5826 inst
.operands
[i
].isscalar
= 1;
5827 inst
.operands
[i
].vectype
= optype
;
5828 inst
.operands
[i
++].present
= 1;
5830 if (skip_past_comma (&ptr
) == FAIL
)
5833 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5836 inst
.operands
[i
].reg
= val
;
5837 inst
.operands
[i
].isreg
= 1;
5838 inst
.operands
[i
].present
= 1;
5840 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
5843 /* Cases 0, 1, 2, 3, 5 (D only). */
5844 if (skip_past_comma (&ptr
) == FAIL
)
5847 inst
.operands
[i
].reg
= val
;
5848 inst
.operands
[i
].isreg
= 1;
5849 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5850 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5851 inst
.operands
[i
].isvec
= 1;
5852 inst
.operands
[i
].vectype
= optype
;
5853 inst
.operands
[i
++].present
= 1;
5855 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5857 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
5858 Case 13: VMOV <Sd>, <Rm> */
5859 inst
.operands
[i
].reg
= val
;
5860 inst
.operands
[i
].isreg
= 1;
5861 inst
.operands
[i
].present
= 1;
5863 if (rtype
== REG_TYPE_NQ
)
5865 first_error (_("can't use Neon quad register here"));
5868 else if (rtype
!= REG_TYPE_VFS
)
5871 if (skip_past_comma (&ptr
) == FAIL
)
5873 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5875 inst
.operands
[i
].reg
= val
;
5876 inst
.operands
[i
].isreg
= 1;
5877 inst
.operands
[i
].present
= 1;
5880 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
5883 /* Case 0: VMOV<c><q> <Qd>, <Qm>
5884 Case 1: VMOV<c><q> <Dd>, <Dm>
5885 Case 8: VMOV.F32 <Sd>, <Sm>
5886 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
5888 inst
.operands
[i
].reg
= val
;
5889 inst
.operands
[i
].isreg
= 1;
5890 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
5891 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5892 inst
.operands
[i
].isvec
= 1;
5893 inst
.operands
[i
].vectype
= optype
;
5894 inst
.operands
[i
].present
= 1;
5896 if (skip_past_comma (&ptr
) == SUCCESS
)
5901 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5904 inst
.operands
[i
].reg
= val
;
5905 inst
.operands
[i
].isreg
= 1;
5906 inst
.operands
[i
++].present
= 1;
5908 if (skip_past_comma (&ptr
) == FAIL
)
5911 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
5914 inst
.operands
[i
].reg
= val
;
5915 inst
.operands
[i
].isreg
= 1;
5916 inst
.operands
[i
++].present
= 1;
5919 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
5920 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
5921 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
5922 Case 10: VMOV.F32 <Sd>, #<imm>
5923 Case 11: VMOV.F64 <Dd>, #<imm> */
5924 inst
.operands
[i
].immisfloat
= 1;
5925 else if (parse_big_immediate (&ptr
, i
) == SUCCESS
)
5926 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
5927 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
5931 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
5935 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5938 inst
.operands
[i
].reg
= val
;
5939 inst
.operands
[i
].isreg
= 1;
5940 inst
.operands
[i
++].present
= 1;
5942 if (skip_past_comma (&ptr
) == FAIL
)
5945 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
5947 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
5948 inst
.operands
[i
].reg
= val
;
5949 inst
.operands
[i
].isscalar
= 1;
5950 inst
.operands
[i
].present
= 1;
5951 inst
.operands
[i
].vectype
= optype
;
5953 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
5955 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
5956 inst
.operands
[i
].reg
= val
;
5957 inst
.operands
[i
].isreg
= 1;
5958 inst
.operands
[i
++].present
= 1;
5960 if (skip_past_comma (&ptr
) == FAIL
)
5963 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
5966 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
5970 inst
.operands
[i
].reg
= val
;
5971 inst
.operands
[i
].isreg
= 1;
5972 inst
.operands
[i
].isvec
= 1;
5973 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
5974 inst
.operands
[i
].vectype
= optype
;
5975 inst
.operands
[i
].present
= 1;
5977 if (rtype
== REG_TYPE_VFS
)
5981 if (skip_past_comma (&ptr
) == FAIL
)
5983 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
5986 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
5989 inst
.operands
[i
].reg
= val
;
5990 inst
.operands
[i
].isreg
= 1;
5991 inst
.operands
[i
].isvec
= 1;
5992 inst
.operands
[i
].issingle
= 1;
5993 inst
.operands
[i
].vectype
= optype
;
5994 inst
.operands
[i
].present
= 1;
5997 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6001 inst
.operands
[i
].reg
= val
;
6002 inst
.operands
[i
].isreg
= 1;
6003 inst
.operands
[i
].isvec
= 1;
6004 inst
.operands
[i
].issingle
= 1;
6005 inst
.operands
[i
].vectype
= optype
;
6006 inst
.operands
[i
++].present
= 1;
6011 first_error (_("parse error"));
6015 /* Successfully parsed the operands. Update args. */
6021 first_error (_("expected comma"));
6025 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6029 /* Use this macro when the operand constraints are different
6030 for ARM and THUMB (e.g. ldrd). */
6031 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6032 ((arm_operand) | ((thumb_operand) << 16))
6034 /* Matcher codes for parse_operands. */
6035 enum operand_parse_code
6037 OP_stop
, /* end of line */
6039 OP_RR
, /* ARM register */
6040 OP_RRnpc
, /* ARM register, not r15 */
6041 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6042 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6043 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6044 optional trailing ! */
6045 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6046 OP_RCP
, /* Coprocessor number */
6047 OP_RCN
, /* Coprocessor register */
6048 OP_RF
, /* FPA register */
6049 OP_RVS
, /* VFP single precision register */
6050 OP_RVD
, /* VFP double precision register (0..15) */
6051 OP_RND
, /* Neon double precision register (0..31) */
6052 OP_RNQ
, /* Neon quad precision register */
6053 OP_RVSD
, /* VFP single or double precision register */
6054 OP_RNDQ
, /* Neon double or quad precision register */
6055 OP_RNSDQ
, /* Neon single, double or quad precision register */
6056 OP_RNSC
, /* Neon scalar D[X] */
6057 OP_RVC
, /* VFP control register */
6058 OP_RMF
, /* Maverick F register */
6059 OP_RMD
, /* Maverick D register */
6060 OP_RMFX
, /* Maverick FX register */
6061 OP_RMDX
, /* Maverick DX register */
6062 OP_RMAX
, /* Maverick AX register */
6063 OP_RMDS
, /* Maverick DSPSC register */
6064 OP_RIWR
, /* iWMMXt wR register */
6065 OP_RIWC
, /* iWMMXt wC register */
6066 OP_RIWG
, /* iWMMXt wCG register */
6067 OP_RXA
, /* XScale accumulator register */
6069 OP_REGLST
, /* ARM register list */
6070 OP_VRSLST
, /* VFP single-precision register list */
6071 OP_VRDLST
, /* VFP double-precision register list */
6072 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6073 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6074 OP_NSTRLST
, /* Neon element/structure list */
6076 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6077 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6078 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6079 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6080 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6081 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6082 OP_VMOV
, /* Neon VMOV operands. */
6083 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6084 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6085 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6087 OP_I0
, /* immediate zero */
6088 OP_I7
, /* immediate value 0 .. 7 */
6089 OP_I15
, /* 0 .. 15 */
6090 OP_I16
, /* 1 .. 16 */
6091 OP_I16z
, /* 0 .. 16 */
6092 OP_I31
, /* 0 .. 31 */
6093 OP_I31w
, /* 0 .. 31, optional trailing ! */
6094 OP_I32
, /* 1 .. 32 */
6095 OP_I32z
, /* 0 .. 32 */
6096 OP_I63
, /* 0 .. 63 */
6097 OP_I63s
, /* -64 .. 63 */
6098 OP_I64
, /* 1 .. 64 */
6099 OP_I64z
, /* 0 .. 64 */
6100 OP_I255
, /* 0 .. 255 */
6102 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6103 OP_I7b
, /* 0 .. 7 */
6104 OP_I15b
, /* 0 .. 15 */
6105 OP_I31b
, /* 0 .. 31 */
6107 OP_SH
, /* shifter operand */
6108 OP_SHG
, /* shifter operand with possible group relocation */
6109 OP_ADDR
, /* Memory address expression (any mode) */
6110 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6111 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6112 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6113 OP_EXP
, /* arbitrary expression */
6114 OP_EXPi
, /* same, with optional immediate prefix */
6115 OP_EXPr
, /* same, with optional relocation suffix */
6116 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6118 OP_CPSF
, /* CPS flags */
6119 OP_ENDI
, /* Endianness specifier */
6120 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6121 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6122 OP_COND
, /* conditional code */
6123 OP_TB
, /* Table branch. */
6125 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6127 OP_RRnpc_I0
, /* ARM register or literal 0 */
6128 OP_RR_EXr
, /* ARM register or expression with opt. reloc suff. */
6129 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6130 OP_RF_IF
, /* FPA register or immediate */
6131 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6132 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6134 /* Optional operands. */
6135 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6136 OP_oI31b
, /* 0 .. 31 */
6137 OP_oI32b
, /* 1 .. 32 */
6138 OP_oI32z
, /* 0 .. 32 */
6139 OP_oIffffb
, /* 0 .. 65535 */
6140 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6142 OP_oRR
, /* ARM register */
6143 OP_oRRnpc
, /* ARM register, not the PC */
6144 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6145 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6146 OP_oRND
, /* Optional Neon double precision register */
6147 OP_oRNQ
, /* Optional Neon quad precision register */
6148 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6149 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6150 OP_oSHll
, /* LSL immediate */
6151 OP_oSHar
, /* ASR immediate */
6152 OP_oSHllar
, /* LSL or ASR immediate */
6153 OP_oROR
, /* ROR 0/8/16/24 */
6154 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6156 /* Some pre-defined mixed (ARM/THUMB) operands. */
6157 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6158 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6159 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6161 OP_FIRST_OPTIONAL
= OP_oI7b
6164 /* Generic instruction operand parser. This does no encoding and no
6165 semantic validation; it merely squirrels values away in the inst
6166 structure. Returns SUCCESS or FAIL depending on whether the
6167 specified grammar matched. */
6169 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6171 unsigned const int *upat
= pattern
;
6172 char *backtrack_pos
= 0;
6173 const char *backtrack_error
= 0;
6174 int i
, val
, backtrack_index
= 0;
6175 enum arm_reg_type rtype
;
6176 parse_operand_result result
;
6177 unsigned int op_parse_code
;
6179 #define po_char_or_fail(chr) \
6182 if (skip_past_char (&str, chr) == FAIL) \
6187 #define po_reg_or_fail(regtype) \
6190 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6191 & inst.operands[i].vectype); \
6194 first_error (_(reg_expected_msgs[regtype])); \
6197 inst.operands[i].reg = val; \
6198 inst.operands[i].isreg = 1; \
6199 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6200 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6201 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6202 || rtype == REG_TYPE_VFD \
6203 || rtype == REG_TYPE_NQ); \
6207 #define po_reg_or_goto(regtype, label) \
6210 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6211 & inst.operands[i].vectype); \
6215 inst.operands[i].reg = val; \
6216 inst.operands[i].isreg = 1; \
6217 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6218 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6219 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6220 || rtype == REG_TYPE_VFD \
6221 || rtype == REG_TYPE_NQ); \
6225 #define po_imm_or_fail(min, max, popt) \
6228 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6230 inst.operands[i].imm = val; \
6234 #define po_scalar_or_goto(elsz, label) \
6237 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6240 inst.operands[i].reg = val; \
6241 inst.operands[i].isscalar = 1; \
6245 #define po_misc_or_fail(expr) \
6253 #define po_misc_or_fail_no_backtrack(expr) \
6257 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6258 backtrack_pos = 0; \
6259 if (result != PARSE_OPERAND_SUCCESS) \
6264 #define po_barrier_or_imm(str) \
6267 val = parse_barrier (&str); \
6270 if (ISALPHA (*str)) \
6277 if ((inst.instruction & 0xf0) == 0x60 \
6280 /* ISB can only take SY as an option. */ \
6281 inst.error = _("invalid barrier type"); \
6288 skip_whitespace (str
);
6290 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6292 op_parse_code
= upat
[i
];
6293 if (op_parse_code
>= 1<<16)
6294 op_parse_code
= thumb
? (op_parse_code
>> 16)
6295 : (op_parse_code
& ((1<<16)-1));
6297 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6299 /* Remember where we are in case we need to backtrack. */
6300 gas_assert (!backtrack_pos
);
6301 backtrack_pos
= str
;
6302 backtrack_error
= inst
.error
;
6303 backtrack_index
= i
;
6306 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6307 po_char_or_fail (',');
6309 switch (op_parse_code
)
6317 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6318 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6319 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6320 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6321 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6322 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6324 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6326 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6328 /* Also accept generic coprocessor regs for unknown registers. */
6330 po_reg_or_fail (REG_TYPE_CN
);
6332 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6333 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6334 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6335 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6336 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6337 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6338 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6339 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6340 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6341 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6343 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6345 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6346 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6348 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6350 /* Neon scalar. Using an element size of 8 means that some invalid
6351 scalars are accepted here, so deal with those in later code. */
6352 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6356 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6359 po_imm_or_fail (0, 0, TRUE
);
6364 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6369 po_scalar_or_goto (8, try_rr
);
6372 po_reg_or_fail (REG_TYPE_RN
);
6378 po_scalar_or_goto (8, try_nsdq
);
6381 po_reg_or_fail (REG_TYPE_NSDQ
);
6387 po_scalar_or_goto (8, try_ndq
);
6390 po_reg_or_fail (REG_TYPE_NDQ
);
6396 po_scalar_or_goto (8, try_vfd
);
6399 po_reg_or_fail (REG_TYPE_VFD
);
6404 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6405 not careful then bad things might happen. */
6406 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6411 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6414 /* There's a possibility of getting a 64-bit immediate here, so
6415 we need special handling. */
6416 if (parse_big_immediate (&str
, i
) == FAIL
)
6418 inst
.error
= _("immediate value is out of range");
6426 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6429 po_imm_or_fail (0, 63, TRUE
);
6434 po_char_or_fail ('[');
6435 po_reg_or_fail (REG_TYPE_RN
);
6436 po_char_or_fail (']');
6442 po_reg_or_fail (REG_TYPE_RN
);
6443 if (skip_past_char (&str
, '!') == SUCCESS
)
6444 inst
.operands
[i
].writeback
= 1;
6448 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6449 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6450 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6451 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6452 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6453 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6454 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6455 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6456 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6457 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6458 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6459 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6461 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6463 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6464 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6466 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6467 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6468 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6469 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6471 /* Immediate variants */
6473 po_char_or_fail ('{');
6474 po_imm_or_fail (0, 255, TRUE
);
6475 po_char_or_fail ('}');
6479 /* The expression parser chokes on a trailing !, so we have
6480 to find it first and zap it. */
6483 while (*s
&& *s
!= ',')
6488 inst
.operands
[i
].writeback
= 1;
6490 po_imm_or_fail (0, 31, TRUE
);
6498 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6503 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6508 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
6510 if (inst
.reloc
.exp
.X_op
== O_symbol
)
6512 val
= parse_reloc (&str
);
6515 inst
.error
= _("unrecognized relocation suffix");
6518 else if (val
!= BFD_RELOC_UNUSED
)
6520 inst
.operands
[i
].imm
= val
;
6521 inst
.operands
[i
].hasreloc
= 1;
6526 /* Operand for MOVW or MOVT. */
6528 po_misc_or_fail (parse_half (&str
));
6531 /* Register or expression. */
6532 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
6533 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
6535 /* Register or immediate. */
6536 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
6537 I0
: po_imm_or_fail (0, 0, FALSE
); break;
6539 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
6541 if (!is_immediate_prefix (*str
))
6544 val
= parse_fpa_immediate (&str
);
6547 /* FPA immediates are encoded as registers 8-15.
6548 parse_fpa_immediate has already applied the offset. */
6549 inst
.operands
[i
].reg
= val
;
6550 inst
.operands
[i
].isreg
= 1;
6553 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
6554 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
6556 /* Two kinds of register. */
6559 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6561 || (rege
->type
!= REG_TYPE_MMXWR
6562 && rege
->type
!= REG_TYPE_MMXWC
6563 && rege
->type
!= REG_TYPE_MMXWCG
))
6565 inst
.error
= _("iWMMXt data or control register expected");
6568 inst
.operands
[i
].reg
= rege
->number
;
6569 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
6575 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
6577 || (rege
->type
!= REG_TYPE_MMXWC
6578 && rege
->type
!= REG_TYPE_MMXWCG
))
6580 inst
.error
= _("iWMMXt control register expected");
6583 inst
.operands
[i
].reg
= rege
->number
;
6584 inst
.operands
[i
].isreg
= 1;
6589 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
6590 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
6591 case OP_oROR
: val
= parse_ror (&str
); break;
6592 case OP_COND
: val
= parse_cond (&str
); break;
6593 case OP_oBARRIER_I15
:
6594 po_barrier_or_imm (str
); break;
6596 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
6602 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
6603 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
6605 inst
.error
= _("Banked registers are not available with this "
6611 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
6615 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
6618 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
6620 if (strncasecmp (str
, "APSR_", 5) == 0)
6627 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
6628 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
6629 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
6630 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
6631 default: found
= 16;
6635 inst
.operands
[i
].isvec
= 1;
6636 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
6637 inst
.operands
[i
].reg
= REG_PC
;
6644 po_misc_or_fail (parse_tb (&str
));
6647 /* Register lists. */
6649 val
= parse_reg_list (&str
);
6652 inst
.operands
[1].writeback
= 1;
6658 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
6662 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
6666 /* Allow Q registers too. */
6667 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6672 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6674 inst
.operands
[i
].issingle
= 1;
6679 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
6684 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
6685 &inst
.operands
[i
].vectype
);
6688 /* Addressing modes */
6690 po_misc_or_fail (parse_address (&str
, i
));
6694 po_misc_or_fail_no_backtrack (
6695 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
6699 po_misc_or_fail_no_backtrack (
6700 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
6704 po_misc_or_fail_no_backtrack (
6705 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
6709 po_misc_or_fail (parse_shifter_operand (&str
, i
));
6713 po_misc_or_fail_no_backtrack (
6714 parse_shifter_operand_group_reloc (&str
, i
));
6718 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
6722 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
6726 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
6730 as_fatal (_("unhandled operand code %d"), op_parse_code
);
6733 /* Various value-based sanity checks and shared operations. We
6734 do not signal immediate failures for the register constraints;
6735 this allows a syntax error to take precedence. */
6736 switch (op_parse_code
)
6744 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
6745 inst
.error
= BAD_PC
;
6750 if (inst
.operands
[i
].isreg
)
6752 if (inst
.operands
[i
].reg
== REG_PC
)
6753 inst
.error
= BAD_PC
;
6754 else if (inst
.operands
[i
].reg
== REG_SP
)
6755 inst
.error
= BAD_SP
;
6760 if (inst
.operands
[i
].isreg
6761 && inst
.operands
[i
].reg
== REG_PC
6762 && (inst
.operands
[i
].writeback
|| thumb
))
6763 inst
.error
= BAD_PC
;
6772 case OP_oBARRIER_I15
:
6781 inst
.operands
[i
].imm
= val
;
6788 /* If we get here, this operand was successfully parsed. */
6789 inst
.operands
[i
].present
= 1;
6793 inst
.error
= BAD_ARGS
;
6798 /* The parse routine should already have set inst.error, but set a
6799 default here just in case. */
6801 inst
.error
= _("syntax error");
6805 /* Do not backtrack over a trailing optional argument that
6806 absorbed some text. We will only fail again, with the
6807 'garbage following instruction' error message, which is
6808 probably less helpful than the current one. */
6809 if (backtrack_index
== i
&& backtrack_pos
!= str
6810 && upat
[i
+1] == OP_stop
)
6813 inst
.error
= _("syntax error");
6817 /* Try again, skipping the optional argument at backtrack_pos. */
6818 str
= backtrack_pos
;
6819 inst
.error
= backtrack_error
;
6820 inst
.operands
[backtrack_index
].present
= 0;
6821 i
= backtrack_index
;
6825 /* Check that we have parsed all the arguments. */
6826 if (*str
!= '\0' && !inst
.error
)
6827 inst
.error
= _("garbage following instruction");
6829 return inst
.error
? FAIL
: SUCCESS
;
6832 #undef po_char_or_fail
6833 #undef po_reg_or_fail
6834 #undef po_reg_or_goto
6835 #undef po_imm_or_fail
6836 #undef po_scalar_or_fail
6837 #undef po_barrier_or_imm
6839 /* Shorthand macro for instruction encoding functions issuing errors. */
6840 #define constraint(expr, err) \
6851 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
6852 instructions are unpredictable if these registers are used. This
6853 is the BadReg predicate in ARM's Thumb-2 documentation. */
6854 #define reject_bad_reg(reg) \
6856 if (reg == REG_SP || reg == REG_PC) \
6858 inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
6863 /* If REG is R13 (the stack pointer), warn that its use is
6865 #define warn_deprecated_sp(reg) \
6867 if (warn_on_deprecated && reg == REG_SP) \
6868 as_warn (_("use of r13 is deprecated")); \
6871 /* Functions for operand encoding. ARM, then Thumb. */
6873 #define rotate_left(v, n) (v << n | v >> (32 - n))
6875 /* If VAL can be encoded in the immediate field of an ARM instruction,
6876 return the encoded form. Otherwise, return FAIL. */
6879 encode_arm_immediate (unsigned int val
)
6883 for (i
= 0; i
< 32; i
+= 2)
6884 if ((a
= rotate_left (val
, i
)) <= 0xff)
6885 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
6890 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
6891 return the encoded form. Otherwise, return FAIL. */
6893 encode_thumb32_immediate (unsigned int val
)
6900 for (i
= 1; i
<= 24; i
++)
6903 if ((val
& ~(0xff << i
)) == 0)
6904 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
6908 if (val
== ((a
<< 16) | a
))
6910 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
6914 if (val
== ((a
<< 16) | a
))
6915 return 0x200 | (a
>> 8);
6919 /* Encode a VFP SP or DP register number into inst.instruction. */
6922 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
6924 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
6927 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
6930 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
6933 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
6938 first_error (_("D register out of range for selected VFP version"));
6946 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
6950 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
6954 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
6958 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
6962 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
6966 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
6974 /* Encode a <shift> in an ARM-format instruction. The immediate,
6975 if any, is handled by md_apply_fix. */
6977 encode_arm_shift (int i
)
6979 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
6980 inst
.instruction
|= SHIFT_ROR
<< 5;
6983 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
6984 if (inst
.operands
[i
].immisreg
)
6986 inst
.instruction
|= SHIFT_BY_REG
;
6987 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
6990 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
6995 encode_arm_shifter_operand (int i
)
6997 if (inst
.operands
[i
].isreg
)
6999 inst
.instruction
|= inst
.operands
[i
].reg
;
7000 encode_arm_shift (i
);
7003 inst
.instruction
|= INST_IMMEDIATE
;
7006 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7008 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7010 gas_assert (inst
.operands
[i
].isreg
);
7011 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7013 if (inst
.operands
[i
].preind
)
7017 inst
.error
= _("instruction does not accept preindexed addressing");
7020 inst
.instruction
|= PRE_INDEX
;
7021 if (inst
.operands
[i
].writeback
)
7022 inst
.instruction
|= WRITE_BACK
;
7025 else if (inst
.operands
[i
].postind
)
7027 gas_assert (inst
.operands
[i
].writeback
);
7029 inst
.instruction
|= WRITE_BACK
;
7031 else /* unindexed - only for coprocessor */
7033 inst
.error
= _("instruction does not accept unindexed addressing");
7037 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7038 && (((inst
.instruction
& 0x000f0000) >> 16)
7039 == ((inst
.instruction
& 0x0000f000) >> 12)))
7040 as_warn ((inst
.instruction
& LOAD_BIT
)
7041 ? _("destination register same as write-back base")
7042 : _("source register same as write-back base"));
7045 /* inst.operands[i] was set up by parse_address. Encode it into an
7046 ARM-format mode 2 load or store instruction. If is_t is true,
7047 reject forms that cannot be used with a T instruction (i.e. not
7050 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7052 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7054 encode_arm_addr_mode_common (i
, is_t
);
7056 if (inst
.operands
[i
].immisreg
)
7058 constraint ((inst
.operands
[i
].imm
== REG_PC
7059 || (is_pc
&& inst
.operands
[i
].writeback
)),
7061 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7062 inst
.instruction
|= inst
.operands
[i
].imm
;
7063 if (!inst
.operands
[i
].negative
)
7064 inst
.instruction
|= INDEX_UP
;
7065 if (inst
.operands
[i
].shifted
)
7067 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7068 inst
.instruction
|= SHIFT_ROR
<< 5;
7071 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7072 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7076 else /* immediate offset in inst.reloc */
7078 if (is_pc
&& !inst
.reloc
.pc_rel
)
7080 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7082 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7083 cannot use PC in addressing.
7084 PC cannot be used in writeback addressing, either. */
7085 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7088 /* Use of PC in str is deprecated for ARMv7. */
7089 if (warn_on_deprecated
7091 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7092 as_warn (_("use of PC in this instruction is deprecated"));
7095 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7097 /* Prefer + for zero encoded value. */
7098 if (!inst
.operands
[i
].negative
)
7099 inst
.instruction
|= INDEX_UP
;
7100 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7105 /* inst.operands[i] was set up by parse_address. Encode it into an
7106 ARM-format mode 3 load or store instruction. Reject forms that
7107 cannot be used with such instructions. If is_t is true, reject
7108 forms that cannot be used with a T instruction (i.e. not
7111 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7113 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7115 inst
.error
= _("instruction does not accept scaled register index");
7119 encode_arm_addr_mode_common (i
, is_t
);
7121 if (inst
.operands
[i
].immisreg
)
7123 constraint ((inst
.operands
[i
].imm
== REG_PC
7124 || inst
.operands
[i
].reg
== REG_PC
),
7126 inst
.instruction
|= inst
.operands
[i
].imm
;
7127 if (!inst
.operands
[i
].negative
)
7128 inst
.instruction
|= INDEX_UP
;
7130 else /* immediate offset in inst.reloc */
7132 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7133 && inst
.operands
[i
].writeback
),
7135 inst
.instruction
|= HWOFFSET_IMM
;
7136 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7138 /* Prefer + for zero encoded value. */
7139 if (!inst
.operands
[i
].negative
)
7140 inst
.instruction
|= INDEX_UP
;
7142 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7147 /* inst.operands[i] was set up by parse_address. Encode it into an
7148 ARM-format instruction. Reject all forms which cannot be encoded
7149 into a coprocessor load/store instruction. If wb_ok is false,
7150 reject use of writeback; if unind_ok is false, reject use of
7151 unindexed addressing. If reloc_override is not 0, use it instead
7152 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
7153 (in which case it is preserved). */
7156 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
7158 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7160 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
7162 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
7164 gas_assert (!inst
.operands
[i
].writeback
);
7167 inst
.error
= _("instruction does not support unindexed addressing");
7170 inst
.instruction
|= inst
.operands
[i
].imm
;
7171 inst
.instruction
|= INDEX_UP
;
7175 if (inst
.operands
[i
].preind
)
7176 inst
.instruction
|= PRE_INDEX
;
7178 if (inst
.operands
[i
].writeback
)
7180 if (inst
.operands
[i
].reg
== REG_PC
)
7182 inst
.error
= _("pc may not be used with write-back");
7187 inst
.error
= _("instruction does not support writeback");
7190 inst
.instruction
|= WRITE_BACK
;
7194 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
7195 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
7196 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
7197 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
7200 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
7202 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
7205 /* Prefer + for zero encoded value. */
7206 if (!inst
.operands
[i
].negative
)
7207 inst
.instruction
|= INDEX_UP
;
7212 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7213 Determine whether it can be performed with a move instruction; if
7214 it can, convert inst.instruction to that move instruction and
7215 return TRUE; if it can't, convert inst.instruction to a literal-pool
7216 load and return FALSE. If this is not a valid thing to do in the
7217 current context, set inst.error and return TRUE.
7219 inst.operands[i] describes the destination register. */
7222 move_or_literal_pool (int i
, bfd_boolean thumb_p
, bfd_boolean mode_3
)
7227 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7231 if ((inst
.instruction
& tbit
) == 0)
7233 inst
.error
= _("invalid pseudo operation");
7236 if (inst
.reloc
.exp
.X_op
!= O_constant
&& inst
.reloc
.exp
.X_op
!= O_symbol
)
7238 inst
.error
= _("constant expression expected");
7241 if (inst
.reloc
.exp
.X_op
== O_constant
)
7245 if (!unified_syntax
&& (inst
.reloc
.exp
.X_add_number
& ~0xFF) == 0)
7247 /* This can be done with a mov(1) instruction. */
7248 inst
.instruction
= T_OPCODE_MOV_I8
| (inst
.operands
[i
].reg
<< 8);
7249 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
;
7255 int value
= encode_arm_immediate (inst
.reloc
.exp
.X_add_number
);
7258 /* This can be done with a mov instruction. */
7259 inst
.instruction
&= LITERAL_MASK
;
7260 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
7261 inst
.instruction
|= value
& 0xfff;
7265 value
= encode_arm_immediate (~inst
.reloc
.exp
.X_add_number
);
7268 /* This can be done with a mvn instruction. */
7269 inst
.instruction
&= LITERAL_MASK
;
7270 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
7271 inst
.instruction
|= value
& 0xfff;
7277 if (add_to_lit_pool () == FAIL
)
7279 inst
.error
= _("literal pool insertion failed");
7282 inst
.operands
[1].reg
= REG_PC
;
7283 inst
.operands
[1].isreg
= 1;
7284 inst
.operands
[1].preind
= 1;
7285 inst
.reloc
.pc_rel
= 1;
7286 inst
.reloc
.type
= (thumb_p
7287 ? BFD_RELOC_ARM_THUMB_OFFSET
7289 ? BFD_RELOC_ARM_HWLITERAL
7290 : BFD_RELOC_ARM_LITERAL
));
7294 /* Functions for instruction encoding, sorted by sub-architecture.
7295 First some generics; their names are taken from the conventional
7296 bit positions for register arguments in ARM format instructions. */
7306 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7312 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7313 inst
.instruction
|= inst
.operands
[1].reg
;
7319 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7320 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7326 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7327 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7333 unsigned Rn
= inst
.operands
[2].reg
;
7334 /* Enforce restrictions on SWP instruction. */
7335 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
7337 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
7338 _("Rn must not overlap other operands"));
7340 /* SWP{b} is deprecated for ARMv6* and ARMv7. */
7341 if (warn_on_deprecated
7342 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
7343 as_warn (_("swp{b} use is deprecated for this architecture"));
7346 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7347 inst
.instruction
|= inst
.operands
[1].reg
;
7348 inst
.instruction
|= Rn
<< 16;
7354 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7355 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7356 inst
.instruction
|= inst
.operands
[2].reg
;
7362 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
7363 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
7364 && inst
.reloc
.exp
.X_op
!= O_illegal
)
7365 || inst
.reloc
.exp
.X_add_number
!= 0),
7367 inst
.instruction
|= inst
.operands
[0].reg
;
7368 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7369 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7375 inst
.instruction
|= inst
.operands
[0].imm
;
7381 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7382 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
7385 /* ARM instructions, in alphabetical order by function name (except
7386 that wrapper functions appear immediately after the function they
7389 /* This is a pseudo-op of the form "adr rd, label" to be converted
7390 into a relative address of the form "add rd, pc, #label-.-8". */
7395 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7397 /* Frag hacking will turn this into a sub instruction if the offset turns
7398 out to be negative. */
7399 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
7400 inst
.reloc
.pc_rel
= 1;
7401 inst
.reloc
.exp
.X_add_number
-= 8;
7404 /* This is a pseudo-op of the form "adrl rd, label" to be converted
7405 into a relative address of the form:
7406 add rd, pc, #low(label-.-8)"
7407 add rd, rd, #high(label-.-8)" */
7412 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
7414 /* Frag hacking will turn this into a sub instruction if the offset turns
7415 out to be negative. */
7416 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
7417 inst
.reloc
.pc_rel
= 1;
7418 inst
.size
= INSN_SIZE
* 2;
7419 inst
.reloc
.exp
.X_add_number
-= 8;
7425 if (!inst
.operands
[1].present
)
7426 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
7427 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7428 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7429 encode_arm_shifter_operand (2);
7435 if (inst
.operands
[0].present
)
7437 constraint ((inst
.instruction
& 0xf0) != 0x40
7438 && inst
.operands
[0].imm
> 0xf
7439 && inst
.operands
[0].imm
< 0x0,
7440 _("bad barrier type"));
7441 inst
.instruction
|= inst
.operands
[0].imm
;
7444 inst
.instruction
|= 0xf;
7450 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
7451 constraint (msb
> 32, _("bit-field extends past end of register"));
7452 /* The instruction encoding stores the LSB and MSB,
7453 not the LSB and width. */
7454 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7455 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
7456 inst
.instruction
|= (msb
- 1) << 16;
7464 /* #0 in second position is alternative syntax for bfc, which is
7465 the same instruction but with REG_PC in the Rm field. */
7466 if (!inst
.operands
[1].isreg
)
7467 inst
.operands
[1].reg
= REG_PC
;
7469 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
7470 constraint (msb
> 32, _("bit-field extends past end of register"));
7471 /* The instruction encoding stores the LSB and MSB,
7472 not the LSB and width. */
7473 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7474 inst
.instruction
|= inst
.operands
[1].reg
;
7475 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7476 inst
.instruction
|= (msb
- 1) << 16;
7482 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
7483 _("bit-field extends past end of register"));
7484 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7485 inst
.instruction
|= inst
.operands
[1].reg
;
7486 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
7487 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
7490 /* ARM V5 breakpoint instruction (argument parse)
7491 BKPT <16 bit unsigned immediate>
7492 Instruction is not conditional.
7493 The bit pattern given in insns[] has the COND_ALWAYS condition,
7494 and it is an error if the caller tried to override that. */
7499 /* Top 12 of 16 bits to bits 19:8. */
7500 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
7502 /* Bottom 4 of 16 bits to bits 3:0. */
7503 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
7507 encode_branch (int default_reloc
)
7509 if (inst
.operands
[0].hasreloc
)
7511 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
7512 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
7513 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
7514 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
7515 ? BFD_RELOC_ARM_PLT32
7516 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
7519 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
7520 inst
.reloc
.pc_rel
= 1;
7527 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7528 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7531 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7538 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
7540 if (inst
.cond
== COND_ALWAYS
)
7541 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
7543 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
7547 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
7550 /* ARM V5 branch-link-exchange instruction (argument parse)
7551 BLX <target_addr> ie BLX(1)
7552 BLX{<condition>} <Rm> ie BLX(2)
7553 Unfortunately, there are two different opcodes for this mnemonic.
7554 So, the insns[].value is not used, and the code here zaps values
7555 into inst.instruction.
7556 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
7561 if (inst
.operands
[0].isreg
)
7563 /* Arg is a register; the opcode provided by insns[] is correct.
7564 It is not illegal to do "blx pc", just useless. */
7565 if (inst
.operands
[0].reg
== REG_PC
)
7566 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
7568 inst
.instruction
|= inst
.operands
[0].reg
;
7572 /* Arg is an address; this instruction cannot be executed
7573 conditionally, and the opcode must be adjusted.
7574 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
7575 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
7576 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
7577 inst
.instruction
= 0xfa000000;
7578 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
7585 bfd_boolean want_reloc
;
7587 if (inst
.operands
[0].reg
== REG_PC
)
7588 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
7590 inst
.instruction
|= inst
.operands
[0].reg
;
7591 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
7592 it is for ARMv4t or earlier. */
7593 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
7594 if (object_arch
&& !ARM_CPU_HAS_FEATURE (*object_arch
, arm_ext_v5
))
7598 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
7603 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
7607 /* ARM v5TEJ. Jump to Jazelle code. */
7612 if (inst
.operands
[0].reg
== REG_PC
)
7613 as_tsktsk (_("use of r15 in bxj is not really useful"));
7615 inst
.instruction
|= inst
.operands
[0].reg
;
7618 /* Co-processor data operation:
7619 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
7620 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
7624 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7625 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
7626 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
7627 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7628 inst
.instruction
|= inst
.operands
[4].reg
;
7629 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7635 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7636 encode_arm_shifter_operand (1);
7639 /* Transfer between coprocessor and ARM registers.
7640 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
7645 No special properties. */
7652 Rd
= inst
.operands
[2].reg
;
7655 if (inst
.instruction
== 0xee000010
7656 || inst
.instruction
== 0xfe000010)
7658 reject_bad_reg (Rd
);
7661 constraint (Rd
== REG_SP
, BAD_SP
);
7666 if (inst
.instruction
== 0xe000010)
7667 constraint (Rd
== REG_PC
, BAD_PC
);
7671 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7672 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
7673 inst
.instruction
|= Rd
<< 12;
7674 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
7675 inst
.instruction
|= inst
.operands
[4].reg
;
7676 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
7679 /* Transfer between coprocessor register and pair of ARM registers.
7680 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
7685 Two XScale instructions are special cases of these:
7687 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
7688 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
7690 Result unpredictable if Rd or Rn is R15. */
7697 Rd
= inst
.operands
[2].reg
;
7698 Rn
= inst
.operands
[3].reg
;
7702 reject_bad_reg (Rd
);
7703 reject_bad_reg (Rn
);
7707 constraint (Rd
== REG_PC
, BAD_PC
);
7708 constraint (Rn
== REG_PC
, BAD_PC
);
7711 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7712 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
7713 inst
.instruction
|= Rd
<< 12;
7714 inst
.instruction
|= Rn
<< 16;
7715 inst
.instruction
|= inst
.operands
[4].reg
;
7721 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
7722 if (inst
.operands
[1].present
)
7724 inst
.instruction
|= CPSI_MMOD
;
7725 inst
.instruction
|= inst
.operands
[1].imm
;
7732 inst
.instruction
|= inst
.operands
[0].imm
;
7738 unsigned Rd
, Rn
, Rm
;
7740 Rd
= inst
.operands
[0].reg
;
7741 Rn
= (inst
.operands
[1].present
7742 ? inst
.operands
[1].reg
: Rd
);
7743 Rm
= inst
.operands
[2].reg
;
7745 constraint ((Rd
== REG_PC
), BAD_PC
);
7746 constraint ((Rn
== REG_PC
), BAD_PC
);
7747 constraint ((Rm
== REG_PC
), BAD_PC
);
7749 inst
.instruction
|= Rd
<< 16;
7750 inst
.instruction
|= Rn
<< 0;
7751 inst
.instruction
|= Rm
<< 8;
7757 /* There is no IT instruction in ARM mode. We
7758 process it to do the validation as if in
7759 thumb mode, just in case the code gets
7760 assembled for thumb using the unified syntax. */
7765 set_it_insn_type (IT_INSN
);
7766 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
7767 now_it
.cc
= inst
.operands
[0].imm
;
7774 int base_reg
= inst
.operands
[0].reg
;
7775 int range
= inst
.operands
[1].imm
;
7777 inst
.instruction
|= base_reg
<< 16;
7778 inst
.instruction
|= range
;
7780 if (inst
.operands
[1].writeback
)
7781 inst
.instruction
|= LDM_TYPE_2_OR_3
;
7783 if (inst
.operands
[0].writeback
)
7785 inst
.instruction
|= WRITE_BACK
;
7786 /* Check for unpredictable uses of writeback. */
7787 if (inst
.instruction
& LOAD_BIT
)
7789 /* Not allowed in LDM type 2. */
7790 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
7791 && ((range
& (1 << REG_PC
)) == 0))
7792 as_warn (_("writeback of base register is UNPREDICTABLE"));
7793 /* Only allowed if base reg not in list for other types. */
7794 else if (range
& (1 << base_reg
))
7795 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
7799 /* Not allowed for type 2. */
7800 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
7801 as_warn (_("writeback of base register is UNPREDICTABLE"));
7802 /* Only allowed if base reg not in list, or first in list. */
7803 else if ((range
& (1 << base_reg
))
7804 && (range
& ((1 << base_reg
) - 1)))
7805 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
7810 /* ARMv5TE load-consecutive (argument parse)
7819 constraint (inst
.operands
[0].reg
% 2 != 0,
7820 _("first transfer register must be even"));
7821 constraint (inst
.operands
[1].present
7822 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7823 _("can only transfer two consecutive registers"));
7824 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7825 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
7827 if (!inst
.operands
[1].present
)
7828 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
7830 /* encode_arm_addr_mode_3 will diagnose overlap between the base
7831 register and the first register written; we have to diagnose
7832 overlap between the base and the second register written here. */
7834 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
7835 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
7836 as_warn (_("base register written back, and overlaps "
7837 "second transfer register"));
7839 if (!(inst
.instruction
& V4_STR_BIT
))
7841 /* For an index-register load, the index register must not overlap the
7842 destination (even if not write-back). */
7843 if (inst
.operands
[2].immisreg
7844 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
7845 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
7846 as_warn (_("index register overlaps transfer register"));
7848 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7849 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
7855 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
7856 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
7857 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
7858 || inst
.operands
[1].negative
7859 /* This can arise if the programmer has written
7861 or if they have mistakenly used a register name as the last
7864 It is very difficult to distinguish between these two cases
7865 because "rX" might actually be a label. ie the register
7866 name has been occluded by a symbol of the same name. So we
7867 just generate a general 'bad addressing mode' type error
7868 message and leave it up to the programmer to discover the
7869 true cause and fix their mistake. */
7870 || (inst
.operands
[1].reg
== REG_PC
),
7873 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7874 || inst
.reloc
.exp
.X_add_number
!= 0,
7875 _("offset must be zero in ARM encoding"));
7877 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
7879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7880 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
7881 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
7887 constraint (inst
.operands
[0].reg
% 2 != 0,
7888 _("even register required"));
7889 constraint (inst
.operands
[1].present
7890 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
7891 _("can only load two consecutive registers"));
7892 /* If op 1 were present and equal to PC, this function wouldn't
7893 have been called in the first place. */
7894 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
7896 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7897 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
7903 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7904 if (!inst
.operands
[1].isreg
)
7905 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/FALSE
))
7907 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
7913 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7915 if (inst
.operands
[1].preind
)
7917 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7918 || inst
.reloc
.exp
.X_add_number
!= 0,
7919 _("this instruction requires a post-indexed address"));
7921 inst
.operands
[1].preind
= 0;
7922 inst
.operands
[1].postind
= 1;
7923 inst
.operands
[1].writeback
= 1;
7925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7926 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
7929 /* Halfword and signed-byte load/store operations. */
7934 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
7935 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7936 if (!inst
.operands
[1].isreg
)
7937 if (move_or_literal_pool (0, /*thumb_p=*/FALSE
, /*mode_3=*/TRUE
))
7939 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
7945 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
7947 if (inst
.operands
[1].preind
)
7949 constraint (inst
.reloc
.exp
.X_op
!= O_constant
7950 || inst
.reloc
.exp
.X_add_number
!= 0,
7951 _("this instruction requires a post-indexed address"));
7953 inst
.operands
[1].preind
= 0;
7954 inst
.operands
[1].postind
= 1;
7955 inst
.operands
[1].writeback
= 1;
7957 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7958 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
7961 /* Co-processor register load/store.
7962 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
7966 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
7967 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
7968 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
7974 /* This restriction does not apply to mls (nor to mla in v6 or later). */
7975 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
7976 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
7977 && !(inst
.instruction
& 0x00400000))
7978 as_tsktsk (_("Rd and Rm should be different in mla"));
7980 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
7981 inst
.instruction
|= inst
.operands
[1].reg
;
7982 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
7983 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
7989 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
7990 encode_arm_shifter_operand (1);
7993 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
8000 top
= (inst
.instruction
& 0x00400000) != 0;
8001 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
8002 _(":lower16: not allowed this instruction"));
8003 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
8004 _(":upper16: not allowed instruction"));
8005 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8006 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
8008 imm
= inst
.reloc
.exp
.X_add_number
;
8009 /* The value is in two pieces: 0:11, 16:19. */
8010 inst
.instruction
|= (imm
& 0x00000fff);
8011 inst
.instruction
|= (imm
& 0x0000f000) << 4;
8015 static void do_vfp_nsyn_opcode (const char *);
8018 do_vfp_nsyn_mrs (void)
8020 if (inst
.operands
[0].isvec
)
8022 if (inst
.operands
[1].reg
!= 1)
8023 first_error (_("operand 1 must be FPSCR"));
8024 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
8025 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
8026 do_vfp_nsyn_opcode ("fmstat");
8028 else if (inst
.operands
[1].isvec
)
8029 do_vfp_nsyn_opcode ("fmrx");
8037 do_vfp_nsyn_msr (void)
8039 if (inst
.operands
[0].isvec
)
8040 do_vfp_nsyn_opcode ("fmxr");
8050 unsigned Rt
= inst
.operands
[0].reg
;
8052 if (thumb_mode
&& inst
.operands
[0].reg
== REG_SP
)
8054 inst
.error
= BAD_SP
;
8058 /* APSR_ sets isvec. All other refs to PC are illegal. */
8059 if (!inst
.operands
[0].isvec
&& inst
.operands
[0].reg
== REG_PC
)
8061 inst
.error
= BAD_PC
;
8065 if (inst
.operands
[1].reg
!= 1)
8066 first_error (_("operand 1 must be FPSCR"));
8068 inst
.instruction
|= (Rt
<< 12);
8074 unsigned Rt
= inst
.operands
[1].reg
;
8077 reject_bad_reg (Rt
);
8078 else if (Rt
== REG_PC
)
8080 inst
.error
= BAD_PC
;
8084 if (inst
.operands
[0].reg
!= 1)
8085 first_error (_("operand 0 must be FPSCR"));
8087 inst
.instruction
|= (Rt
<< 12);
8095 if (do_vfp_nsyn_mrs () == SUCCESS
)
8098 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
8099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8101 if (inst
.operands
[1].isreg
)
8103 br
= inst
.operands
[1].reg
;
8104 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf000))
8105 as_bad (_("bad register for mrs"));
8109 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
8110 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
8112 _("'APSR', 'CPSR' or 'SPSR' expected"));
8113 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
8116 inst
.instruction
|= br
;
8119 /* Two possible forms:
8120 "{C|S}PSR_<field>, Rm",
8121 "{C|S}PSR_f, #expression". */
8126 if (do_vfp_nsyn_msr () == SUCCESS
)
8129 inst
.instruction
|= inst
.operands
[0].imm
;
8130 if (inst
.operands
[1].isreg
)
8131 inst
.instruction
|= inst
.operands
[1].reg
;
8134 inst
.instruction
|= INST_IMMEDIATE
;
8135 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8136 inst
.reloc
.pc_rel
= 0;
8143 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
8145 if (!inst
.operands
[2].present
)
8146 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
8147 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8148 inst
.instruction
|= inst
.operands
[1].reg
;
8149 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8151 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
8152 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8153 as_tsktsk (_("Rd and Rm should be different in mul"));
8156 /* Long Multiply Parser
8157 UMULL RdLo, RdHi, Rm, Rs
8158 SMULL RdLo, RdHi, Rm, Rs
8159 UMLAL RdLo, RdHi, Rm, Rs
8160 SMLAL RdLo, RdHi, Rm, Rs. */
8165 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8166 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8167 inst
.instruction
|= inst
.operands
[2].reg
;
8168 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8170 /* rdhi and rdlo must be different. */
8171 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8172 as_tsktsk (_("rdhi and rdlo must be different"));
8174 /* rdhi, rdlo and rm must all be different before armv6. */
8175 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
8176 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
8177 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
8178 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
8184 if (inst
.operands
[0].present
8185 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
8187 /* Architectural NOP hints are CPSR sets with no bits selected. */
8188 inst
.instruction
&= 0xf0000000;
8189 inst
.instruction
|= 0x0320f000;
8190 if (inst
.operands
[0].present
)
8191 inst
.instruction
|= inst
.operands
[0].imm
;
8195 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
8196 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
8197 Condition defaults to COND_ALWAYS.
8198 Error if Rd, Rn or Rm are R15. */
8203 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8204 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8205 inst
.instruction
|= inst
.operands
[2].reg
;
8206 if (inst
.operands
[3].present
)
8207 encode_arm_shift (3);
8210 /* ARM V6 PKHTB (Argument Parse). */
8215 if (!inst
.operands
[3].present
)
8217 /* If the shift specifier is omitted, turn the instruction
8218 into pkhbt rd, rm, rn. */
8219 inst
.instruction
&= 0xfff00010;
8220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8221 inst
.instruction
|= inst
.operands
[1].reg
;
8222 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8226 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8227 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8228 inst
.instruction
|= inst
.operands
[2].reg
;
8229 encode_arm_shift (3);
8233 /* ARMv5TE: Preload-Cache
8234 MP Extensions: Preload for write
8238 Syntactically, like LDR with B=1, W=0, L=1. */
8243 constraint (!inst
.operands
[0].isreg
,
8244 _("'[' expected after PLD mnemonic"));
8245 constraint (inst
.operands
[0].postind
,
8246 _("post-indexed expression used in preload instruction"));
8247 constraint (inst
.operands
[0].writeback
,
8248 _("writeback used in preload instruction"));
8249 constraint (!inst
.operands
[0].preind
,
8250 _("unindexed addressing used in preload instruction"));
8251 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8254 /* ARMv7: PLI <addr_mode> */
8258 constraint (!inst
.operands
[0].isreg
,
8259 _("'[' expected after PLI mnemonic"));
8260 constraint (inst
.operands
[0].postind
,
8261 _("post-indexed expression used in preload instruction"));
8262 constraint (inst
.operands
[0].writeback
,
8263 _("writeback used in preload instruction"));
8264 constraint (!inst
.operands
[0].preind
,
8265 _("unindexed addressing used in preload instruction"));
8266 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
8267 inst
.instruction
&= ~PRE_INDEX
;
8273 inst
.operands
[1] = inst
.operands
[0];
8274 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
8275 inst
.operands
[0].isreg
= 1;
8276 inst
.operands
[0].writeback
= 1;
8277 inst
.operands
[0].reg
= REG_SP
;
8281 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
8282 word at the specified address and the following word
8284 Unconditionally executed.
8285 Error if Rn is R15. */
8290 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8291 if (inst
.operands
[0].writeback
)
8292 inst
.instruction
|= WRITE_BACK
;
8295 /* ARM V6 ssat (argument parse). */
8300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8301 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
8302 inst
.instruction
|= inst
.operands
[2].reg
;
8304 if (inst
.operands
[3].present
)
8305 encode_arm_shift (3);
8308 /* ARM V6 usat (argument parse). */
8313 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8314 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8315 inst
.instruction
|= inst
.operands
[2].reg
;
8317 if (inst
.operands
[3].present
)
8318 encode_arm_shift (3);
8321 /* ARM V6 ssat16 (argument parse). */
8326 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8327 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
8328 inst
.instruction
|= inst
.operands
[2].reg
;
8334 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8335 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
8336 inst
.instruction
|= inst
.operands
[2].reg
;
8339 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
8340 preserving the other bits.
8342 setend <endian_specifier>, where <endian_specifier> is either
8348 if (inst
.operands
[0].imm
)
8349 inst
.instruction
|= 0x200;
8355 unsigned int Rm
= (inst
.operands
[1].present
8356 ? inst
.operands
[1].reg
8357 : inst
.operands
[0].reg
);
8359 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8360 inst
.instruction
|= Rm
;
8361 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
8363 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8364 inst
.instruction
|= SHIFT_BY_REG
;
8365 /* PR 12854: Error on extraneous shifts. */
8366 constraint (inst
.operands
[2].shifted
,
8367 _("extraneous shift as part of operand to shift insn"));
8370 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
8376 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
8377 inst
.reloc
.pc_rel
= 0;
8383 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
8384 inst
.reloc
.pc_rel
= 0;
8390 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
8391 inst
.reloc
.pc_rel
= 0;
8394 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
8395 SMLAxy{cond} Rd,Rm,Rs,Rn
8396 SMLAWy{cond} Rd,Rm,Rs,Rn
8397 Error if any register is R15. */
8402 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8403 inst
.instruction
|= inst
.operands
[1].reg
;
8404 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8405 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
8408 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
8409 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
8410 Error if any register is R15.
8411 Warning if Rdlo == Rdhi. */
8416 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8417 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8418 inst
.instruction
|= inst
.operands
[2].reg
;
8419 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
8421 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
8422 as_tsktsk (_("rdhi and rdlo must be different"));
8425 /* ARM V5E (El Segundo) signed-multiply (argument parse)
8426 SMULxy{cond} Rd,Rm,Rs
8427 Error if any register is R15. */
8432 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8433 inst
.instruction
|= inst
.operands
[1].reg
;
8434 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
8437 /* ARM V6 srs (argument parse). The variable fields in the encoding are
8438 the same for both ARM and Thumb-2. */
8445 if (inst
.operands
[0].present
)
8447 reg
= inst
.operands
[0].reg
;
8448 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
8453 inst
.instruction
|= reg
<< 16;
8454 inst
.instruction
|= inst
.operands
[1].imm
;
8455 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
8456 inst
.instruction
|= WRITE_BACK
;
8459 /* ARM V6 strex (argument parse). */
8464 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
8465 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
8466 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
8467 || inst
.operands
[2].negative
8468 /* See comment in do_ldrex(). */
8469 || (inst
.operands
[2].reg
== REG_PC
),
8472 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8473 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
8475 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8476 || inst
.reloc
.exp
.X_add_number
!= 0,
8477 _("offset must be zero in ARM encoding"));
8479 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8480 inst
.instruction
|= inst
.operands
[1].reg
;
8481 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8482 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
8488 constraint (inst
.operands
[1].reg
% 2 != 0,
8489 _("even register required"));
8490 constraint (inst
.operands
[2].present
8491 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
8492 _("can only store two consecutive registers"));
8493 /* If op 2 were present and equal to PC, this function wouldn't
8494 have been called in the first place. */
8495 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
8497 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
8498 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
8499 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
8502 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8503 inst
.instruction
|= inst
.operands
[1].reg
;
8504 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8507 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
8508 extends it to 32-bits, and adds the result to a value in another
8509 register. You can specify a rotation by 0, 8, 16, or 24 bits
8510 before extracting the 16-bit value.
8511 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
8512 Condition defaults to COND_ALWAYS.
8513 Error if any register uses R15. */
8518 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8519 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8520 inst
.instruction
|= inst
.operands
[2].reg
;
8521 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
8526 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
8527 Condition defaults to COND_ALWAYS.
8528 Error if any register uses R15. */
8533 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8534 inst
.instruction
|= inst
.operands
[1].reg
;
8535 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
8538 /* VFP instructions. In a logical order: SP variant first, monad
8539 before dyad, arithmetic then move then load/store. */
8542 do_vfp_sp_monadic (void)
8544 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8545 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8549 do_vfp_sp_dyadic (void)
8551 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8552 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8553 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8557 do_vfp_sp_compare_z (void)
8559 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8563 do_vfp_dp_sp_cvt (void)
8565 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8566 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
8570 do_vfp_sp_dp_cvt (void)
8572 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8573 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8577 do_vfp_reg_from_sp (void)
8579 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8580 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
8584 do_vfp_reg2_from_sp2 (void)
8586 constraint (inst
.operands
[2].imm
!= 2,
8587 _("only two consecutive VFP SP registers allowed here"));
8588 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8589 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8590 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
8594 do_vfp_sp_from_reg (void)
8596 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
8597 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8601 do_vfp_sp2_from_reg2 (void)
8603 constraint (inst
.operands
[0].imm
!= 2,
8604 _("only two consecutive VFP SP registers allowed here"));
8605 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
8606 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8607 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8611 do_vfp_sp_ldst (void)
8613 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8614 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8618 do_vfp_dp_ldst (void)
8620 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8621 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
8626 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
8628 if (inst
.operands
[0].writeback
)
8629 inst
.instruction
|= WRITE_BACK
;
8631 constraint (ldstm_type
!= VFP_LDSTMIA
,
8632 _("this addressing mode requires base-register writeback"));
8633 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8634 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
8635 inst
.instruction
|= inst
.operands
[1].imm
;
8639 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
8643 if (inst
.operands
[0].writeback
)
8644 inst
.instruction
|= WRITE_BACK
;
8646 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
8647 _("this addressing mode requires base-register writeback"));
8649 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8650 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8652 count
= inst
.operands
[1].imm
<< 1;
8653 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
8656 inst
.instruction
|= count
;
8660 do_vfp_sp_ldstmia (void)
8662 vfp_sp_ldstm (VFP_LDSTMIA
);
8666 do_vfp_sp_ldstmdb (void)
8668 vfp_sp_ldstm (VFP_LDSTMDB
);
8672 do_vfp_dp_ldstmia (void)
8674 vfp_dp_ldstm (VFP_LDSTMIA
);
8678 do_vfp_dp_ldstmdb (void)
8680 vfp_dp_ldstm (VFP_LDSTMDB
);
8684 do_vfp_xp_ldstmia (void)
8686 vfp_dp_ldstm (VFP_LDSTMIAX
);
8690 do_vfp_xp_ldstmdb (void)
8692 vfp_dp_ldstm (VFP_LDSTMDBX
);
8696 do_vfp_dp_rd_rm (void)
8698 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8699 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
8703 do_vfp_dp_rn_rd (void)
8705 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
8706 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8710 do_vfp_dp_rd_rn (void)
8712 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8713 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8717 do_vfp_dp_rd_rn_rm (void)
8719 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8720 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
8721 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
8727 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8731 do_vfp_dp_rm_rd_rn (void)
8733 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
8734 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
8735 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
8738 /* VFPv3 instructions. */
8740 do_vfp_sp_const (void)
8742 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8743 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8744 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8748 do_vfp_dp_const (void)
8750 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8751 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
8752 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
8756 vfp_conv (int srcsize
)
8758 int immbits
= srcsize
- inst
.operands
[1].imm
;
8760 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
8762 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
8763 i.e. immbits must be in range 0 - 16. */
8764 inst
.error
= _("immediate value out of range, expected range [0, 16]");
8767 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
8769 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
8770 i.e. immbits must be in range 0 - 31. */
8771 inst
.error
= _("immediate value out of range, expected range [1, 32]");
8775 inst
.instruction
|= (immbits
& 1) << 5;
8776 inst
.instruction
|= (immbits
>> 1);
8780 do_vfp_sp_conv_16 (void)
8782 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8787 do_vfp_dp_conv_16 (void)
8789 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8794 do_vfp_sp_conv_32 (void)
8796 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
8801 do_vfp_dp_conv_32 (void)
8803 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
8807 /* FPA instructions. Also in a logical order. */
8812 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8813 inst
.instruction
|= inst
.operands
[1].reg
;
8817 do_fpa_ldmstm (void)
8819 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8820 switch (inst
.operands
[1].imm
)
8822 case 1: inst
.instruction
|= CP_T_X
; break;
8823 case 2: inst
.instruction
|= CP_T_Y
; break;
8824 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
8829 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
8831 /* The instruction specified "ea" or "fd", so we can only accept
8832 [Rn]{!}. The instruction does not really support stacking or
8833 unstacking, so we have to emulate these by setting appropriate
8834 bits and offsets. */
8835 constraint (inst
.reloc
.exp
.X_op
!= O_constant
8836 || inst
.reloc
.exp
.X_add_number
!= 0,
8837 _("this instruction does not support indexing"));
8839 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
8840 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
8842 if (!(inst
.instruction
& INDEX_UP
))
8843 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
8845 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
8847 inst
.operands
[2].preind
= 0;
8848 inst
.operands
[2].postind
= 1;
8852 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
8855 /* iWMMXt instructions: strictly in alphabetical order. */
8858 do_iwmmxt_tandorc (void)
8860 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
8864 do_iwmmxt_textrc (void)
8866 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8867 inst
.instruction
|= inst
.operands
[1].imm
;
8871 do_iwmmxt_textrm (void)
8873 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8874 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8875 inst
.instruction
|= inst
.operands
[2].imm
;
8879 do_iwmmxt_tinsr (void)
8881 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8882 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8883 inst
.instruction
|= inst
.operands
[2].imm
;
8887 do_iwmmxt_tmia (void)
8889 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
8890 inst
.instruction
|= inst
.operands
[1].reg
;
8891 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8895 do_iwmmxt_waligni (void)
8897 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8898 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8899 inst
.instruction
|= inst
.operands
[2].reg
;
8900 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
8904 do_iwmmxt_wmerge (void)
8906 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8907 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8908 inst
.instruction
|= inst
.operands
[2].reg
;
8909 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
8913 do_iwmmxt_wmov (void)
8915 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
8916 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8917 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8918 inst
.instruction
|= inst
.operands
[1].reg
;
8922 do_iwmmxt_wldstbh (void)
8925 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8927 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
8929 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
8930 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
8934 do_iwmmxt_wldstw (void)
8936 /* RIWR_RIWC clears .isreg for a control register. */
8937 if (!inst
.operands
[0].isreg
)
8939 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8940 inst
.instruction
|= 0xf0000000;
8943 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8944 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8948 do_iwmmxt_wldstd (void)
8950 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8951 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
8952 && inst
.operands
[1].immisreg
)
8954 inst
.instruction
&= ~0x1a000ff;
8955 inst
.instruction
|= (0xf << 28);
8956 if (inst
.operands
[1].preind
)
8957 inst
.instruction
|= PRE_INDEX
;
8958 if (!inst
.operands
[1].negative
)
8959 inst
.instruction
|= INDEX_UP
;
8960 if (inst
.operands
[1].writeback
)
8961 inst
.instruction
|= WRITE_BACK
;
8962 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8963 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
8964 inst
.instruction
|= inst
.operands
[1].imm
;
8967 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
8971 do_iwmmxt_wshufh (void)
8973 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8974 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8975 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
8976 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
8980 do_iwmmxt_wzero (void)
8982 /* WZERO reg is an alias for WANDN reg, reg, reg. */
8983 inst
.instruction
|= inst
.operands
[0].reg
;
8984 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8985 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8989 do_iwmmxt_wrwrwr_or_imm5 (void)
8991 if (inst
.operands
[2].isreg
)
8994 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
8995 _("immediate operand requires iWMMXt2"));
8997 if (inst
.operands
[2].imm
== 0)
8999 switch ((inst
.instruction
>> 20) & 0xf)
9005 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
9006 inst
.operands
[2].imm
= 16;
9007 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
9013 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
9014 inst
.operands
[2].imm
= 32;
9015 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
9022 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
9024 wrn
= (inst
.instruction
>> 16) & 0xf;
9025 inst
.instruction
&= 0xff0fff0f;
9026 inst
.instruction
|= wrn
;
9027 /* Bail out here; the instruction is now assembled. */
9032 /* Map 32 -> 0, etc. */
9033 inst
.operands
[2].imm
&= 0x1f;
9034 inst
.instruction
|= (0xf << 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
9038 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
9039 operations first, then control, shift, and load/store. */
9041 /* Insns like "foo X,Y,Z". */
9044 do_mav_triple (void)
9046 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9047 inst
.instruction
|= inst
.operands
[1].reg
;
9048 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9051 /* Insns like "foo W,X,Y,Z".
9052 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
9057 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
9058 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9059 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9060 inst
.instruction
|= inst
.operands
[3].reg
;
9063 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
9067 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9070 /* Maverick shift immediate instructions.
9071 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
9072 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
9077 int imm
= inst
.operands
[2].imm
;
9079 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9080 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9082 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
9083 Bits 5-7 of the insn should have bits 4-6 of the immediate.
9084 Bit 4 should be 0. */
9085 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
9087 inst
.instruction
|= imm
;
9090 /* XScale instructions. Also sorted arithmetic before move. */
9092 /* Xscale multiply-accumulate (argument parse)
9095 MIAxycc acc0,Rm,Rs. */
9100 inst
.instruction
|= inst
.operands
[1].reg
;
9101 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9104 /* Xscale move-accumulator-register (argument parse)
9106 MARcc acc0,RdLo,RdHi. */
9111 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9112 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9115 /* Xscale move-register-accumulator (argument parse)
9117 MRAcc RdLo,RdHi,acc0. */
9122 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
9123 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9124 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9127 /* Encoding functions relevant only to Thumb. */
9129 /* inst.operands[i] is a shifted-register operand; encode
9130 it into inst.instruction in the format used by Thumb32. */
9133 encode_thumb32_shifted_operand (int i
)
9135 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
9136 unsigned int shift
= inst
.operands
[i
].shift_kind
;
9138 constraint (inst
.operands
[i
].immisreg
,
9139 _("shift by register not allowed in thumb mode"));
9140 inst
.instruction
|= inst
.operands
[i
].reg
;
9141 if (shift
== SHIFT_RRX
)
9142 inst
.instruction
|= SHIFT_ROR
<< 4;
9145 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9146 _("expression too complex"));
9148 constraint (value
> 32
9149 || (value
== 32 && (shift
== SHIFT_LSL
9150 || shift
== SHIFT_ROR
)),
9151 _("shift expression is too large"));
9155 else if (value
== 32)
9158 inst
.instruction
|= shift
<< 4;
9159 inst
.instruction
|= (value
& 0x1c) << 10;
9160 inst
.instruction
|= (value
& 0x03) << 6;
9165 /* inst.operands[i] was set up by parse_address. Encode it into a
9166 Thumb32 format load or store instruction. Reject forms that cannot
9167 be used with such instructions. If is_t is true, reject forms that
9168 cannot be used with a T instruction; if is_d is true, reject forms
9169 that cannot be used with a D instruction. If it is a store insn,
9173 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
9175 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
9177 constraint (!inst
.operands
[i
].isreg
,
9178 _("Instruction does not support =N addresses"));
9180 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
9181 if (inst
.operands
[i
].immisreg
)
9183 constraint (is_pc
, BAD_PC_ADDRESSING
);
9184 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
9185 constraint (inst
.operands
[i
].negative
,
9186 _("Thumb does not support negative register indexing"));
9187 constraint (inst
.operands
[i
].postind
,
9188 _("Thumb does not support register post-indexing"));
9189 constraint (inst
.operands
[i
].writeback
,
9190 _("Thumb does not support register indexing with writeback"));
9191 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
9192 _("Thumb supports only LSL in shifted register indexing"));
9194 inst
.instruction
|= inst
.operands
[i
].imm
;
9195 if (inst
.operands
[i
].shifted
)
9197 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9198 _("expression too complex"));
9199 constraint (inst
.reloc
.exp
.X_add_number
< 0
9200 || inst
.reloc
.exp
.X_add_number
> 3,
9201 _("shift out of range"));
9202 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
9204 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9206 else if (inst
.operands
[i
].preind
)
9208 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
9209 constraint (is_t
&& inst
.operands
[i
].writeback
,
9210 _("cannot use writeback with this instruction"));
9211 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0)
9212 && !inst
.reloc
.pc_rel
, BAD_PC_ADDRESSING
);
9216 inst
.instruction
|= 0x01000000;
9217 if (inst
.operands
[i
].writeback
)
9218 inst
.instruction
|= 0x00200000;
9222 inst
.instruction
|= 0x00000c00;
9223 if (inst
.operands
[i
].writeback
)
9224 inst
.instruction
|= 0x00000100;
9226 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9228 else if (inst
.operands
[i
].postind
)
9230 gas_assert (inst
.operands
[i
].writeback
);
9231 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
9232 constraint (is_t
, _("cannot use post-indexing with this instruction"));
9235 inst
.instruction
|= 0x00200000;
9237 inst
.instruction
|= 0x00000900;
9238 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
9240 else /* unindexed - only for coprocessor */
9241 inst
.error
= _("instruction does not accept unindexed addressing");
9244 /* Table of Thumb instructions which exist in both 16- and 32-bit
9245 encodings (the latter only in post-V6T2 cores). The index is the
9246 value used in the insns table below. When there is more than one
9247 possible 16-bit encoding for the instruction, this table always
9249 Also contains several pseudo-instructions used during relaxation. */
9250 #define T16_32_TAB \
9251 X(_adc, 4140, eb400000), \
9252 X(_adcs, 4140, eb500000), \
9253 X(_add, 1c00, eb000000), \
9254 X(_adds, 1c00, eb100000), \
9255 X(_addi, 0000, f1000000), \
9256 X(_addis, 0000, f1100000), \
9257 X(_add_pc,000f, f20f0000), \
9258 X(_add_sp,000d, f10d0000), \
9259 X(_adr, 000f, f20f0000), \
9260 X(_and, 4000, ea000000), \
9261 X(_ands, 4000, ea100000), \
9262 X(_asr, 1000, fa40f000), \
9263 X(_asrs, 1000, fa50f000), \
9264 X(_b, e000, f000b000), \
9265 X(_bcond, d000, f0008000), \
9266 X(_bic, 4380, ea200000), \
9267 X(_bics, 4380, ea300000), \
9268 X(_cmn, 42c0, eb100f00), \
9269 X(_cmp, 2800, ebb00f00), \
9270 X(_cpsie, b660, f3af8400), \
9271 X(_cpsid, b670, f3af8600), \
9272 X(_cpy, 4600, ea4f0000), \
9273 X(_dec_sp,80dd, f1ad0d00), \
9274 X(_eor, 4040, ea800000), \
9275 X(_eors, 4040, ea900000), \
9276 X(_inc_sp,00dd, f10d0d00), \
9277 X(_ldmia, c800, e8900000), \
9278 X(_ldr, 6800, f8500000), \
9279 X(_ldrb, 7800, f8100000), \
9280 X(_ldrh, 8800, f8300000), \
9281 X(_ldrsb, 5600, f9100000), \
9282 X(_ldrsh, 5e00, f9300000), \
9283 X(_ldr_pc,4800, f85f0000), \
9284 X(_ldr_pc2,4800, f85f0000), \
9285 X(_ldr_sp,9800, f85d0000), \
9286 X(_lsl, 0000, fa00f000), \
9287 X(_lsls, 0000, fa10f000), \
9288 X(_lsr, 0800, fa20f000), \
9289 X(_lsrs, 0800, fa30f000), \
9290 X(_mov, 2000, ea4f0000), \
9291 X(_movs, 2000, ea5f0000), \
9292 X(_mul, 4340, fb00f000), \
9293 X(_muls, 4340, ffffffff), /* no 32b muls */ \
9294 X(_mvn, 43c0, ea6f0000), \
9295 X(_mvns, 43c0, ea7f0000), \
9296 X(_neg, 4240, f1c00000), /* rsb #0 */ \
9297 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
9298 X(_orr, 4300, ea400000), \
9299 X(_orrs, 4300, ea500000), \
9300 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
9301 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
9302 X(_rev, ba00, fa90f080), \
9303 X(_rev16, ba40, fa90f090), \
9304 X(_revsh, bac0, fa90f0b0), \
9305 X(_ror, 41c0, fa60f000), \
9306 X(_rors, 41c0, fa70f000), \
9307 X(_sbc, 4180, eb600000), \
9308 X(_sbcs, 4180, eb700000), \
9309 X(_stmia, c000, e8800000), \
9310 X(_str, 6000, f8400000), \
9311 X(_strb, 7000, f8000000), \
9312 X(_strh, 8000, f8200000), \
9313 X(_str_sp,9000, f84d0000), \
9314 X(_sub, 1e00, eba00000), \
9315 X(_subs, 1e00, ebb00000), \
9316 X(_subi, 8000, f1a00000), \
9317 X(_subis, 8000, f1b00000), \
9318 X(_sxtb, b240, fa4ff080), \
9319 X(_sxth, b200, fa0ff080), \
9320 X(_tst, 4200, ea100f00), \
9321 X(_uxtb, b2c0, fa5ff080), \
9322 X(_uxth, b280, fa1ff080), \
9323 X(_nop, bf00, f3af8000), \
9324 X(_yield, bf10, f3af8001), \
9325 X(_wfe, bf20, f3af8002), \
9326 X(_wfi, bf30, f3af8003), \
9327 X(_sev, bf40, f3af8004),
9329 /* To catch errors in encoding functions, the codes are all offset by
9330 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
9331 as 16-bit instructions. */
9332 #define X(a,b,c) T_MNEM##a
9333 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
9336 #define X(a,b,c) 0x##b
9337 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
9338 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
9341 #define X(a,b,c) 0x##c
9342 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
9343 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
9344 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
9348 /* Thumb instruction encoders, in alphabetical order. */
9353 do_t_add_sub_w (void)
9357 Rd
= inst
.operands
[0].reg
;
9358 Rn
= inst
.operands
[1].reg
;
9360 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
9361 is the SP-{plus,minus}-immediate form of the instruction. */
9363 constraint (Rd
== REG_PC
, BAD_PC
);
9365 reject_bad_reg (Rd
);
9367 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
9368 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9371 /* Parse an add or subtract instruction. We get here with inst.instruction
9372 equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
9379 Rd
= inst
.operands
[0].reg
;
9380 Rs
= (inst
.operands
[1].present
9381 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9382 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9385 set_it_insn_type_last ();
9393 flags
= (inst
.instruction
== T_MNEM_adds
9394 || inst
.instruction
== T_MNEM_subs
);
9396 narrow
= !in_it_block ();
9398 narrow
= in_it_block ();
9399 if (!inst
.operands
[2].isreg
)
9403 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9405 add
= (inst
.instruction
== T_MNEM_add
9406 || inst
.instruction
== T_MNEM_adds
);
9408 if (inst
.size_req
!= 4)
9410 /* Attempt to use a narrow opcode, with relaxation if
9412 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
9413 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
9414 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
9415 opcode
= T_MNEM_add_sp
;
9416 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
9417 opcode
= T_MNEM_add_pc
;
9418 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
9421 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
9423 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
9427 inst
.instruction
= THUMB_OP16(opcode
);
9428 inst
.instruction
|= (Rd
<< 4) | Rs
;
9429 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9430 if (inst
.size_req
!= 2)
9431 inst
.relax
= opcode
;
9434 constraint (inst
.size_req
== 2, BAD_HIREG
);
9436 if (inst
.size_req
== 4
9437 || (inst
.size_req
!= 2 && !opcode
))
9441 constraint (add
, BAD_PC
);
9442 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
9443 _("only SUBS PC, LR, #const allowed"));
9444 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
9445 _("expression too complex"));
9446 constraint (inst
.reloc
.exp
.X_add_number
< 0
9447 || inst
.reloc
.exp
.X_add_number
> 0xff,
9448 _("immediate value out of range"));
9449 inst
.instruction
= T2_SUBS_PC_LR
9450 | inst
.reloc
.exp
.X_add_number
;
9451 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9454 else if (Rs
== REG_PC
)
9456 /* Always use addw/subw. */
9457 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
9458 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
9462 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9463 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
9466 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9468 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
9470 inst
.instruction
|= Rd
<< 8;
9471 inst
.instruction
|= Rs
<< 16;
9476 Rn
= inst
.operands
[2].reg
;
9477 /* See if we can do this with a 16-bit instruction. */
9478 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
9480 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9485 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
9486 || inst
.instruction
== T_MNEM_add
)
9489 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9493 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
9495 /* Thumb-1 cores (except v6-M) require at least one high
9496 register in a narrow non flag setting add. */
9497 if (Rd
> 7 || Rn
> 7
9498 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
9499 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
9506 inst
.instruction
= T_OPCODE_ADD_HI
;
9507 inst
.instruction
|= (Rd
& 8) << 4;
9508 inst
.instruction
|= (Rd
& 7);
9509 inst
.instruction
|= Rn
<< 3;
9515 constraint (Rd
== REG_PC
, BAD_PC
);
9516 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
9517 constraint (Rs
== REG_PC
, BAD_PC
);
9518 reject_bad_reg (Rn
);
9520 /* If we get here, it can't be done in 16 bits. */
9521 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
9522 _("shift must be constant"));
9523 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9524 inst
.instruction
|= Rd
<< 8;
9525 inst
.instruction
|= Rs
<< 16;
9526 encode_thumb32_shifted_operand (2);
9531 constraint (inst
.instruction
== T_MNEM_adds
9532 || inst
.instruction
== T_MNEM_subs
,
9535 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
9537 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
9538 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
9541 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9543 inst
.instruction
|= (Rd
<< 4) | Rs
;
9544 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9548 Rn
= inst
.operands
[2].reg
;
9549 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
9551 /* We now have Rd, Rs, and Rn set to registers. */
9552 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
9554 /* Can't do this for SUB. */
9555 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
9556 inst
.instruction
= T_OPCODE_ADD_HI
;
9557 inst
.instruction
|= (Rd
& 8) << 4;
9558 inst
.instruction
|= (Rd
& 7);
9560 inst
.instruction
|= Rn
<< 3;
9562 inst
.instruction
|= Rs
<< 3;
9564 constraint (1, _("dest must overlap one source register"));
9568 inst
.instruction
= (inst
.instruction
== T_MNEM_add
9569 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
9570 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
9580 Rd
= inst
.operands
[0].reg
;
9581 reject_bad_reg (Rd
);
9583 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
9585 /* Defer to section relaxation. */
9586 inst
.relax
= inst
.instruction
;
9587 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9588 inst
.instruction
|= Rd
<< 4;
9590 else if (unified_syntax
&& inst
.size_req
!= 2)
9592 /* Generate a 32-bit opcode. */
9593 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9594 inst
.instruction
|= Rd
<< 8;
9595 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
9596 inst
.reloc
.pc_rel
= 1;
9600 /* Generate a 16-bit opcode. */
9601 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9602 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
9603 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
9604 inst
.reloc
.pc_rel
= 1;
9606 inst
.instruction
|= Rd
<< 4;
9610 /* Arithmetic instructions for which there is just one 16-bit
9611 instruction encoding, and it allows only two low registers.
9612 For maximal compatibility with ARM syntax, we allow three register
9613 operands even when Thumb-32 instructions are not available, as long
9614 as the first two are identical. For instance, both "sbc r0,r1" and
9615 "sbc r0,r0,r1" are allowed. */
9621 Rd
= inst
.operands
[0].reg
;
9622 Rs
= (inst
.operands
[1].present
9623 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9624 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9625 Rn
= inst
.operands
[2].reg
;
9627 reject_bad_reg (Rd
);
9628 reject_bad_reg (Rs
);
9629 if (inst
.operands
[2].isreg
)
9630 reject_bad_reg (Rn
);
9634 if (!inst
.operands
[2].isreg
)
9636 /* For an immediate, we always generate a 32-bit opcode;
9637 section relaxation will shrink it later if possible. */
9638 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9639 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9640 inst
.instruction
|= Rd
<< 8;
9641 inst
.instruction
|= Rs
<< 16;
9642 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9648 /* See if we can do this with a 16-bit instruction. */
9649 if (THUMB_SETS_FLAGS (inst
.instruction
))
9650 narrow
= !in_it_block ();
9652 narrow
= in_it_block ();
9654 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9656 if (inst
.operands
[2].shifted
)
9658 if (inst
.size_req
== 4)
9664 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9665 inst
.instruction
|= Rd
;
9666 inst
.instruction
|= Rn
<< 3;
9670 /* If we get here, it can't be done in 16 bits. */
9671 constraint (inst
.operands
[2].shifted
9672 && inst
.operands
[2].immisreg
,
9673 _("shift must be constant"));
9674 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9675 inst
.instruction
|= Rd
<< 8;
9676 inst
.instruction
|= Rs
<< 16;
9677 encode_thumb32_shifted_operand (2);
9682 /* On its face this is a lie - the instruction does set the
9683 flags. However, the only supported mnemonic in this mode
9685 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9687 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9688 _("unshifted register required"));
9689 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9690 constraint (Rd
!= Rs
,
9691 _("dest and source1 must be the same register"));
9693 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9694 inst
.instruction
|= Rd
;
9695 inst
.instruction
|= Rn
<< 3;
9699 /* Similarly, but for instructions where the arithmetic operation is
9700 commutative, so we can allow either of them to be different from
9701 the destination operand in a 16-bit instruction. For instance, all
9702 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
9709 Rd
= inst
.operands
[0].reg
;
9710 Rs
= (inst
.operands
[1].present
9711 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
9712 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
9713 Rn
= inst
.operands
[2].reg
;
9715 reject_bad_reg (Rd
);
9716 reject_bad_reg (Rs
);
9717 if (inst
.operands
[2].isreg
)
9718 reject_bad_reg (Rn
);
9722 if (!inst
.operands
[2].isreg
)
9724 /* For an immediate, we always generate a 32-bit opcode;
9725 section relaxation will shrink it later if possible. */
9726 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9727 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
9728 inst
.instruction
|= Rd
<< 8;
9729 inst
.instruction
|= Rs
<< 16;
9730 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
9736 /* See if we can do this with a 16-bit instruction. */
9737 if (THUMB_SETS_FLAGS (inst
.instruction
))
9738 narrow
= !in_it_block ();
9740 narrow
= in_it_block ();
9742 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
9744 if (inst
.operands
[2].shifted
)
9746 if (inst
.size_req
== 4)
9753 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9754 inst
.instruction
|= Rd
;
9755 inst
.instruction
|= Rn
<< 3;
9760 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9761 inst
.instruction
|= Rd
;
9762 inst
.instruction
|= Rs
<< 3;
9767 /* If we get here, it can't be done in 16 bits. */
9768 constraint (inst
.operands
[2].shifted
9769 && inst
.operands
[2].immisreg
,
9770 _("shift must be constant"));
9771 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
9772 inst
.instruction
|= Rd
<< 8;
9773 inst
.instruction
|= Rs
<< 16;
9774 encode_thumb32_shifted_operand (2);
9779 /* On its face this is a lie - the instruction does set the
9780 flags. However, the only supported mnemonic in this mode
9782 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
9784 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
9785 _("unshifted register required"));
9786 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
9788 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
9789 inst
.instruction
|= Rd
;
9792 inst
.instruction
|= Rn
<< 3;
9794 inst
.instruction
|= Rs
<< 3;
9796 constraint (1, _("dest must overlap one source register"));
9803 if (inst
.operands
[0].present
)
9805 constraint ((inst
.instruction
& 0xf0) != 0x40
9806 && inst
.operands
[0].imm
> 0xf
9807 && inst
.operands
[0].imm
< 0x0,
9808 _("bad barrier type"));
9809 inst
.instruction
|= inst
.operands
[0].imm
;
9812 inst
.instruction
|= 0xf;
9819 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9820 constraint (msb
> 32, _("bit-field extends past end of register"));
9821 /* The instruction encoding stores the LSB and MSB,
9822 not the LSB and width. */
9823 Rd
= inst
.operands
[0].reg
;
9824 reject_bad_reg (Rd
);
9825 inst
.instruction
|= Rd
<< 8;
9826 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
9827 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
9828 inst
.instruction
|= msb
- 1;
9837 Rd
= inst
.operands
[0].reg
;
9838 reject_bad_reg (Rd
);
9840 /* #0 in second position is alternative syntax for bfc, which is
9841 the same instruction but with REG_PC in the Rm field. */
9842 if (!inst
.operands
[1].isreg
)
9846 Rn
= inst
.operands
[1].reg
;
9847 reject_bad_reg (Rn
);
9850 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9851 constraint (msb
> 32, _("bit-field extends past end of register"));
9852 /* The instruction encoding stores the LSB and MSB,
9853 not the LSB and width. */
9854 inst
.instruction
|= Rd
<< 8;
9855 inst
.instruction
|= Rn
<< 16;
9856 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9857 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9858 inst
.instruction
|= msb
- 1;
9866 Rd
= inst
.operands
[0].reg
;
9867 Rn
= inst
.operands
[1].reg
;
9869 reject_bad_reg (Rd
);
9870 reject_bad_reg (Rn
);
9872 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9873 _("bit-field extends past end of register"));
9874 inst
.instruction
|= Rd
<< 8;
9875 inst
.instruction
|= Rn
<< 16;
9876 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
9877 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
9878 inst
.instruction
|= inst
.operands
[3].imm
- 1;
9881 /* ARM V5 Thumb BLX (argument parse)
9882 BLX <target_addr> which is BLX(1)
9883 BLX <Rm> which is BLX(2)
9884 Unfortunately, there are two different opcodes for this mnemonic.
9885 So, the insns[].value is not used, and the code here zaps values
9886 into inst.instruction.
9888 ??? How to take advantage of the additional two bits of displacement
9889 available in Thumb32 mode? Need new relocation? */
9894 set_it_insn_type_last ();
9896 if (inst
.operands
[0].isreg
)
9898 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9899 /* We have a register, so this is BLX(2). */
9900 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
9904 /* No register. This must be BLX(1). */
9905 inst
.instruction
= 0xf000e800;
9906 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
9918 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
9922 /* Conditional branches inside IT blocks are encoded as unconditional
9929 if (cond
!= COND_ALWAYS
)
9930 opcode
= T_MNEM_bcond
;
9932 opcode
= inst
.instruction
;
9935 && (inst
.size_req
== 4
9936 || (inst
.size_req
!= 2
9937 && (inst
.operands
[0].hasreloc
9938 || inst
.reloc
.exp
.X_op
== O_constant
))))
9940 inst
.instruction
= THUMB_OP32(opcode
);
9941 if (cond
== COND_ALWAYS
)
9942 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
9945 gas_assert (cond
!= 0xF);
9946 inst
.instruction
|= cond
<< 22;
9947 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
9952 inst
.instruction
= THUMB_OP16(opcode
);
9953 if (cond
== COND_ALWAYS
)
9954 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
9957 inst
.instruction
|= cond
<< 8;
9958 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
9960 /* Allow section relaxation. */
9961 if (unified_syntax
&& inst
.size_req
!= 2)
9962 inst
.relax
= opcode
;
9964 inst
.reloc
.type
= reloc
;
9965 inst
.reloc
.pc_rel
= 1;
9971 constraint (inst
.cond
!= COND_ALWAYS
,
9972 _("instruction is always unconditional"));
9973 if (inst
.operands
[0].present
)
9975 constraint (inst
.operands
[0].imm
> 255,
9976 _("immediate value out of range"));
9977 inst
.instruction
|= inst
.operands
[0].imm
;
9978 set_it_insn_type (NEUTRAL_IT_INSN
);
9983 do_t_branch23 (void)
9985 set_it_insn_type_last ();
9986 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
9988 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
9989 this file. We used to simply ignore the PLT reloc type here --
9990 the branch encoding is now needed to deal with TLSCALL relocs.
9991 So if we see a PLT reloc now, put it back to how it used to be to
9992 keep the preexisting behaviour. */
9993 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
9994 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
9996 #if defined(OBJ_COFF)
9997 /* If the destination of the branch is a defined symbol which does not have
9998 the THUMB_FUNC attribute, then we must be calling a function which has
9999 the (interfacearm) attribute. We look for the Thumb entry point to that
10000 function and change the branch to refer to that function instead. */
10001 if ( inst
.reloc
.exp
.X_op
== O_symbol
10002 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10003 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10004 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10005 inst
.reloc
.exp
.X_add_symbol
=
10006 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
10013 set_it_insn_type_last ();
10014 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10015 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
10016 should cause the alignment to be checked once it is known. This is
10017 because BX PC only works if the instruction is word aligned. */
10025 set_it_insn_type_last ();
10026 Rm
= inst
.operands
[0].reg
;
10027 reject_bad_reg (Rm
);
10028 inst
.instruction
|= Rm
<< 16;
10037 Rd
= inst
.operands
[0].reg
;
10038 Rm
= inst
.operands
[1].reg
;
10040 reject_bad_reg (Rd
);
10041 reject_bad_reg (Rm
);
10043 inst
.instruction
|= Rd
<< 8;
10044 inst
.instruction
|= Rm
<< 16;
10045 inst
.instruction
|= Rm
;
10051 set_it_insn_type (OUTSIDE_IT_INSN
);
10052 inst
.instruction
|= inst
.operands
[0].imm
;
10058 set_it_insn_type (OUTSIDE_IT_INSN
);
10060 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
10061 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
10063 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
10064 inst
.instruction
= 0xf3af8000;
10065 inst
.instruction
|= imod
<< 9;
10066 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
10067 if (inst
.operands
[1].present
)
10068 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
10072 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
10073 && (inst
.operands
[0].imm
& 4),
10074 _("selected processor does not support 'A' form "
10075 "of this instruction"));
10076 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
10077 _("Thumb does not support the 2-argument "
10078 "form of this instruction"));
10079 inst
.instruction
|= inst
.operands
[0].imm
;
10083 /* THUMB CPY instruction (argument parse). */
10088 if (inst
.size_req
== 4)
10090 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
10091 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10092 inst
.instruction
|= inst
.operands
[1].reg
;
10096 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
10097 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
10098 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10105 set_it_insn_type (OUTSIDE_IT_INSN
);
10106 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10107 inst
.instruction
|= inst
.operands
[0].reg
;
10108 inst
.reloc
.pc_rel
= 1;
10109 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
10115 inst
.instruction
|= inst
.operands
[0].imm
;
10121 unsigned Rd
, Rn
, Rm
;
10123 Rd
= inst
.operands
[0].reg
;
10124 Rn
= (inst
.operands
[1].present
10125 ? inst
.operands
[1].reg
: Rd
);
10126 Rm
= inst
.operands
[2].reg
;
10128 reject_bad_reg (Rd
);
10129 reject_bad_reg (Rn
);
10130 reject_bad_reg (Rm
);
10132 inst
.instruction
|= Rd
<< 8;
10133 inst
.instruction
|= Rn
<< 16;
10134 inst
.instruction
|= Rm
;
10140 if (unified_syntax
&& inst
.size_req
== 4)
10141 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10143 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10149 unsigned int cond
= inst
.operands
[0].imm
;
10151 set_it_insn_type (IT_INSN
);
10152 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
10155 /* If the condition is a negative condition, invert the mask. */
10156 if ((cond
& 0x1) == 0x0)
10158 unsigned int mask
= inst
.instruction
& 0x000f;
10160 if ((mask
& 0x7) == 0)
10161 /* no conversion needed */;
10162 else if ((mask
& 0x3) == 0)
10164 else if ((mask
& 0x1) == 0)
10169 inst
.instruction
&= 0xfff0;
10170 inst
.instruction
|= mask
;
10173 inst
.instruction
|= cond
<< 4;
10176 /* Helper function used for both push/pop and ldm/stm. */
10178 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
10182 load
= (inst
.instruction
& (1 << 20)) != 0;
10184 if (mask
& (1 << 13))
10185 inst
.error
= _("SP not allowed in register list");
10187 if ((mask
& (1 << base
)) != 0
10189 inst
.error
= _("having the base register in the register list when "
10190 "using write back is UNPREDICTABLE");
10194 if (mask
& (1 << 15))
10196 if (mask
& (1 << 14))
10197 inst
.error
= _("LR and PC should not both be in register list");
10199 set_it_insn_type_last ();
10204 if (mask
& (1 << 15))
10205 inst
.error
= _("PC not allowed in register list");
10208 if ((mask
& (mask
- 1)) == 0)
10210 /* Single register transfers implemented as str/ldr. */
10213 if (inst
.instruction
& (1 << 23))
10214 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
10216 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
10220 if (inst
.instruction
& (1 << 23))
10221 inst
.instruction
= 0x00800000; /* ia -> [base] */
10223 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
10226 inst
.instruction
|= 0xf8400000;
10228 inst
.instruction
|= 0x00100000;
10230 mask
= ffs (mask
) - 1;
10233 else if (writeback
)
10234 inst
.instruction
|= WRITE_BACK
;
10236 inst
.instruction
|= mask
;
10237 inst
.instruction
|= base
<< 16;
10243 /* This really doesn't seem worth it. */
10244 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
10245 _("expression too complex"));
10246 constraint (inst
.operands
[1].writeback
,
10247 _("Thumb load/store multiple does not support {reglist}^"));
10249 if (unified_syntax
)
10251 bfd_boolean narrow
;
10255 /* See if we can use a 16-bit instruction. */
10256 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
10257 && inst
.size_req
!= 4
10258 && !(inst
.operands
[1].imm
& ~0xff))
10260 mask
= 1 << inst
.operands
[0].reg
;
10262 if (inst
.operands
[0].reg
<= 7)
10264 if (inst
.instruction
== T_MNEM_stmia
10265 ? inst
.operands
[0].writeback
10266 : (inst
.operands
[0].writeback
10267 == !(inst
.operands
[1].imm
& mask
)))
10269 if (inst
.instruction
== T_MNEM_stmia
10270 && (inst
.operands
[1].imm
& mask
)
10271 && (inst
.operands
[1].imm
& (mask
- 1)))
10272 as_warn (_("value stored for r%d is UNKNOWN"),
10273 inst
.operands
[0].reg
);
10275 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10276 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10277 inst
.instruction
|= inst
.operands
[1].imm
;
10280 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10282 /* This means 1 register in reg list one of 3 situations:
10283 1. Instruction is stmia, but without writeback.
10284 2. lmdia without writeback, but with Rn not in
10286 3. ldmia with writeback, but with Rn in reglist.
10287 Case 3 is UNPREDICTABLE behaviour, so we handle
10288 case 1 and 2 which can be converted into a 16-bit
10289 str or ldr. The SP cases are handled below. */
10290 unsigned long opcode
;
10291 /* First, record an error for Case 3. */
10292 if (inst
.operands
[1].imm
& mask
10293 && inst
.operands
[0].writeback
)
10295 _("having the base register in the register list when "
10296 "using write back is UNPREDICTABLE");
10298 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
10300 inst
.instruction
= THUMB_OP16 (opcode
);
10301 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
10302 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
10306 else if (inst
.operands
[0] .reg
== REG_SP
)
10308 if (inst
.operands
[0].writeback
)
10311 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10312 ? T_MNEM_push
: T_MNEM_pop
);
10313 inst
.instruction
|= inst
.operands
[1].imm
;
10316 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
10319 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
10320 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
10321 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
10329 if (inst
.instruction
< 0xffff)
10330 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10332 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
10333 inst
.operands
[0].writeback
);
10338 constraint (inst
.operands
[0].reg
> 7
10339 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
10340 constraint (inst
.instruction
!= T_MNEM_ldmia
10341 && inst
.instruction
!= T_MNEM_stmia
,
10342 _("Thumb-2 instruction only valid in unified syntax"));
10343 if (inst
.instruction
== T_MNEM_stmia
)
10345 if (!inst
.operands
[0].writeback
)
10346 as_warn (_("this instruction will write back the base register"));
10347 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
10348 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
10349 as_warn (_("value stored for r%d is UNKNOWN"),
10350 inst
.operands
[0].reg
);
10354 if (!inst
.operands
[0].writeback
10355 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10356 as_warn (_("this instruction will write back the base register"));
10357 else if (inst
.operands
[0].writeback
10358 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
10359 as_warn (_("this instruction will not write back the base register"));
10362 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10363 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10364 inst
.instruction
|= inst
.operands
[1].imm
;
10371 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
10372 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
10373 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
10374 || inst
.operands
[1].negative
,
10377 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
10379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10380 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10381 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
10387 if (!inst
.operands
[1].present
)
10389 constraint (inst
.operands
[0].reg
== REG_LR
,
10390 _("r14 not allowed as first register "
10391 "when second register is omitted"));
10392 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10394 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
10397 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10398 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10399 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10405 unsigned long opcode
;
10408 if (inst
.operands
[0].isreg
10409 && !inst
.operands
[0].preind
10410 && inst
.operands
[0].reg
== REG_PC
)
10411 set_it_insn_type_last ();
10413 opcode
= inst
.instruction
;
10414 if (unified_syntax
)
10416 if (!inst
.operands
[1].isreg
)
10418 if (opcode
<= 0xffff)
10419 inst
.instruction
= THUMB_OP32 (opcode
);
10420 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10423 if (inst
.operands
[1].isreg
10424 && !inst
.operands
[1].writeback
10425 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
10426 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
10427 && opcode
<= 0xffff
10428 && inst
.size_req
!= 4)
10430 /* Insn may have a 16-bit form. */
10431 Rn
= inst
.operands
[1].reg
;
10432 if (inst
.operands
[1].immisreg
)
10434 inst
.instruction
= THUMB_OP16 (opcode
);
10436 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
10438 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
10439 reject_bad_reg (inst
.operands
[1].imm
);
10441 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
10442 && opcode
!= T_MNEM_ldrsb
)
10443 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
10444 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
10451 if (inst
.reloc
.pc_rel
)
10452 opcode
= T_MNEM_ldr_pc2
;
10454 opcode
= T_MNEM_ldr_pc
;
10458 if (opcode
== T_MNEM_ldr
)
10459 opcode
= T_MNEM_ldr_sp
;
10461 opcode
= T_MNEM_str_sp
;
10463 inst
.instruction
= inst
.operands
[0].reg
<< 8;
10467 inst
.instruction
= inst
.operands
[0].reg
;
10468 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10470 inst
.instruction
|= THUMB_OP16 (opcode
);
10471 if (inst
.size_req
== 2)
10472 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10474 inst
.relax
= opcode
;
10478 /* Definitely a 32-bit variant. */
10480 /* Warning for Erratum 752419. */
10481 if (opcode
== T_MNEM_ldr
10482 && inst
.operands
[0].reg
== REG_SP
10483 && inst
.operands
[1].writeback
== 1
10484 && !inst
.operands
[1].immisreg
)
10486 if (no_cpu_selected ()
10487 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
10488 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
10489 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
10490 as_warn (_("This instruction may be unpredictable "
10491 "if executed on M-profile cores "
10492 "with interrupts enabled."));
10495 /* Do some validations regarding addressing modes. */
10496 if (inst
.operands
[1].immisreg
&& opcode
!= T_MNEM_ldr
10497 && opcode
!= T_MNEM_str
)
10498 reject_bad_reg (inst
.operands
[1].imm
);
10500 inst
.instruction
= THUMB_OP32 (opcode
);
10501 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10502 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
10506 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
10508 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
10510 /* Only [Rn,Rm] is acceptable. */
10511 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
10512 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
10513 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
10514 || inst
.operands
[1].negative
,
10515 _("Thumb does not support this addressing mode"));
10516 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10520 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10521 if (!inst
.operands
[1].isreg
)
10522 if (move_or_literal_pool (0, /*thumb_p=*/TRUE
, /*mode_3=*/FALSE
))
10525 constraint (!inst
.operands
[1].preind
10526 || inst
.operands
[1].shifted
10527 || inst
.operands
[1].writeback
,
10528 _("Thumb does not support this addressing mode"));
10529 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
10531 constraint (inst
.instruction
& 0x0600,
10532 _("byte or halfword not valid for base register"));
10533 constraint (inst
.operands
[1].reg
== REG_PC
10534 && !(inst
.instruction
& THUMB_LOAD_BIT
),
10535 _("r15 based store not allowed"));
10536 constraint (inst
.operands
[1].immisreg
,
10537 _("invalid base register for register offset"));
10539 if (inst
.operands
[1].reg
== REG_PC
)
10540 inst
.instruction
= T_OPCODE_LDR_PC
;
10541 else if (inst
.instruction
& THUMB_LOAD_BIT
)
10542 inst
.instruction
= T_OPCODE_LDR_SP
;
10544 inst
.instruction
= T_OPCODE_STR_SP
;
10546 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
10547 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10551 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
10552 if (!inst
.operands
[1].immisreg
)
10554 /* Immediate offset. */
10555 inst
.instruction
|= inst
.operands
[0].reg
;
10556 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10557 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
10561 /* Register offset. */
10562 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
10563 constraint (inst
.operands
[1].negative
,
10564 _("Thumb does not support this addressing mode"));
10567 switch (inst
.instruction
)
10569 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
10570 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
10571 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
10572 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
10573 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
10574 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
10575 case 0x5600 /* ldrsb */:
10576 case 0x5e00 /* ldrsh */: break;
10580 inst
.instruction
|= inst
.operands
[0].reg
;
10581 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
10582 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
10588 if (!inst
.operands
[1].present
)
10590 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
10591 constraint (inst
.operands
[0].reg
== REG_LR
,
10592 _("r14 not allowed here"));
10594 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10595 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
10596 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
10602 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10603 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
10609 unsigned Rd
, Rn
, Rm
, Ra
;
10611 Rd
= inst
.operands
[0].reg
;
10612 Rn
= inst
.operands
[1].reg
;
10613 Rm
= inst
.operands
[2].reg
;
10614 Ra
= inst
.operands
[3].reg
;
10616 reject_bad_reg (Rd
);
10617 reject_bad_reg (Rn
);
10618 reject_bad_reg (Rm
);
10619 reject_bad_reg (Ra
);
10621 inst
.instruction
|= Rd
<< 8;
10622 inst
.instruction
|= Rn
<< 16;
10623 inst
.instruction
|= Rm
;
10624 inst
.instruction
|= Ra
<< 12;
10630 unsigned RdLo
, RdHi
, Rn
, Rm
;
10632 RdLo
= inst
.operands
[0].reg
;
10633 RdHi
= inst
.operands
[1].reg
;
10634 Rn
= inst
.operands
[2].reg
;
10635 Rm
= inst
.operands
[3].reg
;
10637 reject_bad_reg (RdLo
);
10638 reject_bad_reg (RdHi
);
10639 reject_bad_reg (Rn
);
10640 reject_bad_reg (Rm
);
10642 inst
.instruction
|= RdLo
<< 12;
10643 inst
.instruction
|= RdHi
<< 8;
10644 inst
.instruction
|= Rn
<< 16;
10645 inst
.instruction
|= Rm
;
10649 do_t_mov_cmp (void)
10653 Rn
= inst
.operands
[0].reg
;
10654 Rm
= inst
.operands
[1].reg
;
10657 set_it_insn_type_last ();
10659 if (unified_syntax
)
10661 int r0off
= (inst
.instruction
== T_MNEM_mov
10662 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
10663 unsigned long opcode
;
10664 bfd_boolean narrow
;
10665 bfd_boolean low_regs
;
10667 low_regs
= (Rn
<= 7 && Rm
<= 7);
10668 opcode
= inst
.instruction
;
10669 if (in_it_block ())
10670 narrow
= opcode
!= T_MNEM_movs
;
10672 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
10673 if (inst
.size_req
== 4
10674 || inst
.operands
[1].shifted
)
10677 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
10678 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
10679 && !inst
.operands
[1].shifted
10683 inst
.instruction
= T2_SUBS_PC_LR
;
10687 if (opcode
== T_MNEM_cmp
)
10689 constraint (Rn
== REG_PC
, BAD_PC
);
10692 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
10694 warn_deprecated_sp (Rm
);
10695 /* R15 was documented as a valid choice for Rm in ARMv6,
10696 but as UNPREDICTABLE in ARMv7. ARM's proprietary
10697 tools reject R15, so we do too. */
10698 constraint (Rm
== REG_PC
, BAD_PC
);
10701 reject_bad_reg (Rm
);
10703 else if (opcode
== T_MNEM_mov
10704 || opcode
== T_MNEM_movs
)
10706 if (inst
.operands
[1].isreg
)
10708 if (opcode
== T_MNEM_movs
)
10710 reject_bad_reg (Rn
);
10711 reject_bad_reg (Rm
);
10715 /* This is mov.n. */
10716 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
10717 && (Rm
== REG_SP
|| Rm
== REG_PC
))
10719 as_warn (_("Use of r%u as a source register is "
10720 "deprecated when r%u is the destination "
10721 "register."), Rm
, Rn
);
10726 /* This is mov.w. */
10727 constraint (Rn
== REG_PC
, BAD_PC
);
10728 constraint (Rm
== REG_PC
, BAD_PC
);
10729 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
10733 reject_bad_reg (Rn
);
10736 if (!inst
.operands
[1].isreg
)
10738 /* Immediate operand. */
10739 if (!in_it_block () && opcode
== T_MNEM_mov
)
10741 if (low_regs
&& narrow
)
10743 inst
.instruction
= THUMB_OP16 (opcode
);
10744 inst
.instruction
|= Rn
<< 8;
10745 if (inst
.size_req
== 2)
10746 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10748 inst
.relax
= opcode
;
10752 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10753 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10754 inst
.instruction
|= Rn
<< r0off
;
10755 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10758 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
10759 && (inst
.instruction
== T_MNEM_mov
10760 || inst
.instruction
== T_MNEM_movs
))
10762 /* Register shifts are encoded as separate shift instructions. */
10763 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
10765 if (in_it_block ())
10770 if (inst
.size_req
== 4)
10773 if (!low_regs
|| inst
.operands
[1].imm
> 7)
10779 switch (inst
.operands
[1].shift_kind
)
10782 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
10785 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
10788 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
10791 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
10797 inst
.instruction
= opcode
;
10800 inst
.instruction
|= Rn
;
10801 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
10806 inst
.instruction
|= CONDS_BIT
;
10808 inst
.instruction
|= Rn
<< 8;
10809 inst
.instruction
|= Rm
<< 16;
10810 inst
.instruction
|= inst
.operands
[1].imm
;
10815 /* Some mov with immediate shift have narrow variants.
10816 Register shifts are handled above. */
10817 if (low_regs
&& inst
.operands
[1].shifted
10818 && (inst
.instruction
== T_MNEM_mov
10819 || inst
.instruction
== T_MNEM_movs
))
10821 if (in_it_block ())
10822 narrow
= (inst
.instruction
== T_MNEM_mov
);
10824 narrow
= (inst
.instruction
== T_MNEM_movs
);
10829 switch (inst
.operands
[1].shift_kind
)
10831 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
10832 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
10833 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
10834 default: narrow
= FALSE
; break;
10840 inst
.instruction
|= Rn
;
10841 inst
.instruction
|= Rm
<< 3;
10842 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
10846 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10847 inst
.instruction
|= Rn
<< r0off
;
10848 encode_thumb32_shifted_operand (1);
10852 switch (inst
.instruction
)
10855 inst
.instruction
= T_OPCODE_MOV_HR
;
10856 inst
.instruction
|= (Rn
& 0x8) << 4;
10857 inst
.instruction
|= (Rn
& 0x7);
10858 inst
.instruction
|= Rm
<< 3;
10862 /* We know we have low registers at this point.
10863 Generate LSLS Rd, Rs, #0. */
10864 inst
.instruction
= T_OPCODE_LSL_I
;
10865 inst
.instruction
|= Rn
;
10866 inst
.instruction
|= Rm
<< 3;
10872 inst
.instruction
= T_OPCODE_CMP_LR
;
10873 inst
.instruction
|= Rn
;
10874 inst
.instruction
|= Rm
<< 3;
10878 inst
.instruction
= T_OPCODE_CMP_HR
;
10879 inst
.instruction
|= (Rn
& 0x8) << 4;
10880 inst
.instruction
|= (Rn
& 0x7);
10881 inst
.instruction
|= Rm
<< 3;
10888 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10890 /* PR 10443: Do not silently ignore shifted operands. */
10891 constraint (inst
.operands
[1].shifted
,
10892 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
10894 if (inst
.operands
[1].isreg
)
10896 if (Rn
< 8 && Rm
< 8)
10898 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
10899 since a MOV instruction produces unpredictable results. */
10900 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10901 inst
.instruction
= T_OPCODE_ADD_I3
;
10903 inst
.instruction
= T_OPCODE_CMP_LR
;
10905 inst
.instruction
|= Rn
;
10906 inst
.instruction
|= Rm
<< 3;
10910 if (inst
.instruction
== T_OPCODE_MOV_I8
)
10911 inst
.instruction
= T_OPCODE_MOV_HR
;
10913 inst
.instruction
= T_OPCODE_CMP_HR
;
10919 constraint (Rn
> 7,
10920 _("only lo regs allowed with immediate"));
10921 inst
.instruction
|= Rn
<< 8;
10922 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
10933 top
= (inst
.instruction
& 0x00800000) != 0;
10934 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
10936 constraint (top
, _(":lower16: not allowed this instruction"));
10937 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
10939 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
10941 constraint (!top
, _(":upper16: not allowed this instruction"));
10942 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
10945 Rd
= inst
.operands
[0].reg
;
10946 reject_bad_reg (Rd
);
10948 inst
.instruction
|= Rd
<< 8;
10949 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
10951 imm
= inst
.reloc
.exp
.X_add_number
;
10952 inst
.instruction
|= (imm
& 0xf000) << 4;
10953 inst
.instruction
|= (imm
& 0x0800) << 15;
10954 inst
.instruction
|= (imm
& 0x0700) << 4;
10955 inst
.instruction
|= (imm
& 0x00ff);
10960 do_t_mvn_tst (void)
10964 Rn
= inst
.operands
[0].reg
;
10965 Rm
= inst
.operands
[1].reg
;
10967 if (inst
.instruction
== T_MNEM_cmp
10968 || inst
.instruction
== T_MNEM_cmn
)
10969 constraint (Rn
== REG_PC
, BAD_PC
);
10971 reject_bad_reg (Rn
);
10972 reject_bad_reg (Rm
);
10974 if (unified_syntax
)
10976 int r0off
= (inst
.instruction
== T_MNEM_mvn
10977 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
10978 bfd_boolean narrow
;
10980 if (inst
.size_req
== 4
10981 || inst
.instruction
> 0xffff
10982 || inst
.operands
[1].shifted
10983 || Rn
> 7 || Rm
> 7)
10985 else if (inst
.instruction
== T_MNEM_cmn
)
10987 else if (THUMB_SETS_FLAGS (inst
.instruction
))
10988 narrow
= !in_it_block ();
10990 narrow
= in_it_block ();
10992 if (!inst
.operands
[1].isreg
)
10994 /* For an immediate, we always generate a 32-bit opcode;
10995 section relaxation will shrink it later if possible. */
10996 if (inst
.instruction
< 0xffff)
10997 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10998 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10999 inst
.instruction
|= Rn
<< r0off
;
11000 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11004 /* See if we can do this with a 16-bit instruction. */
11007 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11008 inst
.instruction
|= Rn
;
11009 inst
.instruction
|= Rm
<< 3;
11013 constraint (inst
.operands
[1].shifted
11014 && inst
.operands
[1].immisreg
,
11015 _("shift must be constant"));
11016 if (inst
.instruction
< 0xffff)
11017 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11018 inst
.instruction
|= Rn
<< r0off
;
11019 encode_thumb32_shifted_operand (1);
11025 constraint (inst
.instruction
> 0xffff
11026 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
11027 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
11028 _("unshifted register required"));
11029 constraint (Rn
> 7 || Rm
> 7,
11032 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11033 inst
.instruction
|= Rn
;
11034 inst
.instruction
|= Rm
<< 3;
11043 if (do_vfp_nsyn_mrs () == SUCCESS
)
11046 Rd
= inst
.operands
[0].reg
;
11047 reject_bad_reg (Rd
);
11048 inst
.instruction
|= Rd
<< 8;
11050 if (inst
.operands
[1].isreg
)
11052 unsigned br
= inst
.operands
[1].reg
;
11053 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
11054 as_bad (_("bad register for mrs"));
11056 inst
.instruction
|= br
& (0xf << 16);
11057 inst
.instruction
|= (br
& 0x300) >> 4;
11058 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
11062 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11064 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11065 constraint (flags
!= 0, _("selected processor does not support "
11066 "requested special purpose register"));
11068 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
11070 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
11071 _("'APSR', 'CPSR' or 'SPSR' expected"));
11073 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11074 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
11075 inst
.instruction
|= 0xf0000;
11085 if (do_vfp_nsyn_msr () == SUCCESS
)
11088 constraint (!inst
.operands
[1].isreg
,
11089 _("Thumb encoding does not support an immediate here"));
11091 if (inst
.operands
[0].isreg
)
11092 flags
= (int)(inst
.operands
[0].reg
);
11094 flags
= inst
.operands
[0].imm
;
11096 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
11098 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
11100 constraint ((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11101 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
11102 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
11104 _("selected processor does not support requested special "
11105 "purpose register"));
11108 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
11109 "requested special purpose register"));
11111 Rn
= inst
.operands
[1].reg
;
11112 reject_bad_reg (Rn
);
11114 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
11115 inst
.instruction
|= (flags
& 0xf0000) >> 8;
11116 inst
.instruction
|= (flags
& 0x300) >> 4;
11117 inst
.instruction
|= (flags
& 0xff);
11118 inst
.instruction
|= Rn
<< 16;
11124 bfd_boolean narrow
;
11125 unsigned Rd
, Rn
, Rm
;
11127 if (!inst
.operands
[2].present
)
11128 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
11130 Rd
= inst
.operands
[0].reg
;
11131 Rn
= inst
.operands
[1].reg
;
11132 Rm
= inst
.operands
[2].reg
;
11134 if (unified_syntax
)
11136 if (inst
.size_req
== 4
11142 else if (inst
.instruction
== T_MNEM_muls
)
11143 narrow
= !in_it_block ();
11145 narrow
= in_it_block ();
11149 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
11150 constraint (Rn
> 7 || Rm
> 7,
11157 /* 16-bit MULS/Conditional MUL. */
11158 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11159 inst
.instruction
|= Rd
;
11162 inst
.instruction
|= Rm
<< 3;
11164 inst
.instruction
|= Rn
<< 3;
11166 constraint (1, _("dest must overlap one source register"));
11170 constraint (inst
.instruction
!= T_MNEM_mul
,
11171 _("Thumb-2 MUL must not set flags"));
11173 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11174 inst
.instruction
|= Rd
<< 8;
11175 inst
.instruction
|= Rn
<< 16;
11176 inst
.instruction
|= Rm
<< 0;
11178 reject_bad_reg (Rd
);
11179 reject_bad_reg (Rn
);
11180 reject_bad_reg (Rm
);
11187 unsigned RdLo
, RdHi
, Rn
, Rm
;
11189 RdLo
= inst
.operands
[0].reg
;
11190 RdHi
= inst
.operands
[1].reg
;
11191 Rn
= inst
.operands
[2].reg
;
11192 Rm
= inst
.operands
[3].reg
;
11194 reject_bad_reg (RdLo
);
11195 reject_bad_reg (RdHi
);
11196 reject_bad_reg (Rn
);
11197 reject_bad_reg (Rm
);
11199 inst
.instruction
|= RdLo
<< 12;
11200 inst
.instruction
|= RdHi
<< 8;
11201 inst
.instruction
|= Rn
<< 16;
11202 inst
.instruction
|= Rm
;
11205 as_tsktsk (_("rdhi and rdlo must be different"));
11211 set_it_insn_type (NEUTRAL_IT_INSN
);
11213 if (unified_syntax
)
11215 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
11217 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11218 inst
.instruction
|= inst
.operands
[0].imm
;
11222 /* PR9722: Check for Thumb2 availability before
11223 generating a thumb2 nop instruction. */
11224 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
11226 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11227 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
11230 inst
.instruction
= 0x46c0;
11235 constraint (inst
.operands
[0].present
,
11236 _("Thumb does not support NOP with hints"));
11237 inst
.instruction
= 0x46c0;
11244 if (unified_syntax
)
11246 bfd_boolean narrow
;
11248 if (THUMB_SETS_FLAGS (inst
.instruction
))
11249 narrow
= !in_it_block ();
11251 narrow
= in_it_block ();
11252 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11254 if (inst
.size_req
== 4)
11259 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11260 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11261 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11265 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11266 inst
.instruction
|= inst
.operands
[0].reg
;
11267 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11272 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
11274 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11276 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11277 inst
.instruction
|= inst
.operands
[0].reg
;
11278 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11287 Rd
= inst
.operands
[0].reg
;
11288 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
11290 reject_bad_reg (Rd
);
11291 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
11292 reject_bad_reg (Rn
);
11294 inst
.instruction
|= Rd
<< 8;
11295 inst
.instruction
|= Rn
<< 16;
11297 if (!inst
.operands
[2].isreg
)
11299 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11300 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11306 Rm
= inst
.operands
[2].reg
;
11307 reject_bad_reg (Rm
);
11309 constraint (inst
.operands
[2].shifted
11310 && inst
.operands
[2].immisreg
,
11311 _("shift must be constant"));
11312 encode_thumb32_shifted_operand (2);
11319 unsigned Rd
, Rn
, Rm
;
11321 Rd
= inst
.operands
[0].reg
;
11322 Rn
= inst
.operands
[1].reg
;
11323 Rm
= inst
.operands
[2].reg
;
11325 reject_bad_reg (Rd
);
11326 reject_bad_reg (Rn
);
11327 reject_bad_reg (Rm
);
11329 inst
.instruction
|= Rd
<< 8;
11330 inst
.instruction
|= Rn
<< 16;
11331 inst
.instruction
|= Rm
;
11332 if (inst
.operands
[3].present
)
11334 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
11335 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11336 _("expression too complex"));
11337 inst
.instruction
|= (val
& 0x1c) << 10;
11338 inst
.instruction
|= (val
& 0x03) << 6;
11345 if (!inst
.operands
[3].present
)
11349 inst
.instruction
&= ~0x00000020;
11351 /* PR 10168. Swap the Rm and Rn registers. */
11352 Rtmp
= inst
.operands
[1].reg
;
11353 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
11354 inst
.operands
[2].reg
= Rtmp
;
11362 if (inst
.operands
[0].immisreg
)
11363 reject_bad_reg (inst
.operands
[0].imm
);
11365 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11369 do_t_push_pop (void)
11373 constraint (inst
.operands
[0].writeback
,
11374 _("push/pop do not support {reglist}^"));
11375 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11376 _("expression too complex"));
11378 mask
= inst
.operands
[0].imm
;
11379 if ((mask
& ~0xff) == 0)
11380 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
11381 else if ((inst
.instruction
== T_MNEM_push
11382 && (mask
& ~0xff) == 1 << REG_LR
)
11383 || (inst
.instruction
== T_MNEM_pop
11384 && (mask
& ~0xff) == 1 << REG_PC
))
11386 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11387 inst
.instruction
|= THUMB_PP_PC_LR
;
11388 inst
.instruction
|= mask
& 0xff;
11390 else if (unified_syntax
)
11392 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11393 encode_thumb2_ldmstm (13, mask
, TRUE
);
11397 inst
.error
= _("invalid register list to push/pop instruction");
11407 Rd
= inst
.operands
[0].reg
;
11408 Rm
= inst
.operands
[1].reg
;
11410 reject_bad_reg (Rd
);
11411 reject_bad_reg (Rm
);
11413 inst
.instruction
|= Rd
<< 8;
11414 inst
.instruction
|= Rm
<< 16;
11415 inst
.instruction
|= Rm
;
11423 Rd
= inst
.operands
[0].reg
;
11424 Rm
= inst
.operands
[1].reg
;
11426 reject_bad_reg (Rd
);
11427 reject_bad_reg (Rm
);
11429 if (Rd
<= 7 && Rm
<= 7
11430 && inst
.size_req
!= 4)
11432 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11433 inst
.instruction
|= Rd
;
11434 inst
.instruction
|= Rm
<< 3;
11436 else if (unified_syntax
)
11438 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11439 inst
.instruction
|= Rd
<< 8;
11440 inst
.instruction
|= Rm
<< 16;
11441 inst
.instruction
|= Rm
;
11444 inst
.error
= BAD_HIREG
;
11452 Rd
= inst
.operands
[0].reg
;
11453 Rm
= inst
.operands
[1].reg
;
11455 reject_bad_reg (Rd
);
11456 reject_bad_reg (Rm
);
11458 inst
.instruction
|= Rd
<< 8;
11459 inst
.instruction
|= Rm
;
11467 Rd
= inst
.operands
[0].reg
;
11468 Rs
= (inst
.operands
[1].present
11469 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11470 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11472 reject_bad_reg (Rd
);
11473 reject_bad_reg (Rs
);
11474 if (inst
.operands
[2].isreg
)
11475 reject_bad_reg (inst
.operands
[2].reg
);
11477 inst
.instruction
|= Rd
<< 8;
11478 inst
.instruction
|= Rs
<< 16;
11479 if (!inst
.operands
[2].isreg
)
11481 bfd_boolean narrow
;
11483 if ((inst
.instruction
& 0x00100000) != 0)
11484 narrow
= !in_it_block ();
11486 narrow
= in_it_block ();
11488 if (Rd
> 7 || Rs
> 7)
11491 if (inst
.size_req
== 4 || !unified_syntax
)
11494 if (inst
.reloc
.exp
.X_op
!= O_constant
11495 || inst
.reloc
.exp
.X_add_number
!= 0)
11498 /* Turn rsb #0 into 16-bit neg. We should probably do this via
11499 relaxation, but it doesn't seem worth the hassle. */
11502 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11503 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
11504 inst
.instruction
|= Rs
<< 3;
11505 inst
.instruction
|= Rd
;
11509 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11510 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11514 encode_thumb32_shifted_operand (2);
11520 set_it_insn_type (OUTSIDE_IT_INSN
);
11521 if (inst
.operands
[0].imm
)
11522 inst
.instruction
|= 0x8;
11528 if (!inst
.operands
[1].present
)
11529 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
11531 if (unified_syntax
)
11533 bfd_boolean narrow
;
11536 switch (inst
.instruction
)
11539 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
11541 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
11543 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
11545 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
11549 if (THUMB_SETS_FLAGS (inst
.instruction
))
11550 narrow
= !in_it_block ();
11552 narrow
= in_it_block ();
11553 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
11555 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
11557 if (inst
.operands
[2].isreg
11558 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
11559 || inst
.operands
[2].reg
> 7))
11561 if (inst
.size_req
== 4)
11564 reject_bad_reg (inst
.operands
[0].reg
);
11565 reject_bad_reg (inst
.operands
[1].reg
);
11569 if (inst
.operands
[2].isreg
)
11571 reject_bad_reg (inst
.operands
[2].reg
);
11572 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11573 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11574 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11575 inst
.instruction
|= inst
.operands
[2].reg
;
11577 /* PR 12854: Error on extraneous shifts. */
11578 constraint (inst
.operands
[2].shifted
,
11579 _("extraneous shift as part of operand to shift insn"));
11583 inst
.operands
[1].shifted
= 1;
11584 inst
.operands
[1].shift_kind
= shift_kind
;
11585 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
11586 ? T_MNEM_movs
: T_MNEM_mov
);
11587 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11588 encode_thumb32_shifted_operand (1);
11589 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
11590 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11595 if (inst
.operands
[2].isreg
)
11597 switch (shift_kind
)
11599 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11600 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11601 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11602 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11606 inst
.instruction
|= inst
.operands
[0].reg
;
11607 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11609 /* PR 12854: Error on extraneous shifts. */
11610 constraint (inst
.operands
[2].shifted
,
11611 _("extraneous shift as part of operand to shift insn"));
11615 switch (shift_kind
)
11617 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11618 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11619 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11622 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11623 inst
.instruction
|= inst
.operands
[0].reg
;
11624 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11630 constraint (inst
.operands
[0].reg
> 7
11631 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
11632 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11634 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
11636 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
11637 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
11638 _("source1 and dest must be same register"));
11640 switch (inst
.instruction
)
11642 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
11643 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
11644 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
11645 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
11649 inst
.instruction
|= inst
.operands
[0].reg
;
11650 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
11652 /* PR 12854: Error on extraneous shifts. */
11653 constraint (inst
.operands
[2].shifted
,
11654 _("extraneous shift as part of operand to shift insn"));
11658 switch (inst
.instruction
)
11660 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
11661 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
11662 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
11663 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
11666 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
11667 inst
.instruction
|= inst
.operands
[0].reg
;
11668 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11676 unsigned Rd
, Rn
, Rm
;
11678 Rd
= inst
.operands
[0].reg
;
11679 Rn
= inst
.operands
[1].reg
;
11680 Rm
= inst
.operands
[2].reg
;
11682 reject_bad_reg (Rd
);
11683 reject_bad_reg (Rn
);
11684 reject_bad_reg (Rm
);
11686 inst
.instruction
|= Rd
<< 8;
11687 inst
.instruction
|= Rn
<< 16;
11688 inst
.instruction
|= Rm
;
11694 unsigned Rd
, Rn
, Rm
;
11696 Rd
= inst
.operands
[0].reg
;
11697 Rm
= inst
.operands
[1].reg
;
11698 Rn
= inst
.operands
[2].reg
;
11700 reject_bad_reg (Rd
);
11701 reject_bad_reg (Rn
);
11702 reject_bad_reg (Rm
);
11704 inst
.instruction
|= Rd
<< 8;
11705 inst
.instruction
|= Rn
<< 16;
11706 inst
.instruction
|= Rm
;
11712 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11713 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
11714 _("SMC is not permitted on this architecture"));
11715 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11716 _("expression too complex"));
11717 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11718 inst
.instruction
|= (value
& 0xf000) >> 12;
11719 inst
.instruction
|= (value
& 0x0ff0);
11720 inst
.instruction
|= (value
& 0x000f) << 16;
11726 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
11728 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11729 inst
.instruction
|= (value
& 0x0fff);
11730 inst
.instruction
|= (value
& 0xf000) << 4;
11734 do_t_ssat_usat (int bias
)
11738 Rd
= inst
.operands
[0].reg
;
11739 Rn
= inst
.operands
[2].reg
;
11741 reject_bad_reg (Rd
);
11742 reject_bad_reg (Rn
);
11744 inst
.instruction
|= Rd
<< 8;
11745 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
11746 inst
.instruction
|= Rn
<< 16;
11748 if (inst
.operands
[3].present
)
11750 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
11752 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
11754 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
11755 _("expression too complex"));
11757 if (shift_amount
!= 0)
11759 constraint (shift_amount
> 31,
11760 _("shift expression is too large"));
11762 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
11763 inst
.instruction
|= 0x00200000; /* sh bit. */
11765 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
11766 inst
.instruction
|= (shift_amount
& 0x03) << 6;
11774 do_t_ssat_usat (1);
11782 Rd
= inst
.operands
[0].reg
;
11783 Rn
= inst
.operands
[2].reg
;
11785 reject_bad_reg (Rd
);
11786 reject_bad_reg (Rn
);
11788 inst
.instruction
|= Rd
<< 8;
11789 inst
.instruction
|= inst
.operands
[1].imm
- 1;
11790 inst
.instruction
|= Rn
<< 16;
11796 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
11797 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
11798 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
11799 || inst
.operands
[2].negative
,
11802 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
11804 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11805 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11806 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11807 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11813 if (!inst
.operands
[2].present
)
11814 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
11816 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
11817 || inst
.operands
[0].reg
== inst
.operands
[2].reg
11818 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
11821 inst
.instruction
|= inst
.operands
[0].reg
;
11822 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11823 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
11824 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
11830 unsigned Rd
, Rn
, Rm
;
11832 Rd
= inst
.operands
[0].reg
;
11833 Rn
= inst
.operands
[1].reg
;
11834 Rm
= inst
.operands
[2].reg
;
11836 reject_bad_reg (Rd
);
11837 reject_bad_reg (Rn
);
11838 reject_bad_reg (Rm
);
11840 inst
.instruction
|= Rd
<< 8;
11841 inst
.instruction
|= Rn
<< 16;
11842 inst
.instruction
|= Rm
;
11843 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
11851 Rd
= inst
.operands
[0].reg
;
11852 Rm
= inst
.operands
[1].reg
;
11854 reject_bad_reg (Rd
);
11855 reject_bad_reg (Rm
);
11857 if (inst
.instruction
<= 0xffff
11858 && inst
.size_req
!= 4
11859 && Rd
<= 7 && Rm
<= 7
11860 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
11862 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11863 inst
.instruction
|= Rd
;
11864 inst
.instruction
|= Rm
<< 3;
11866 else if (unified_syntax
)
11868 if (inst
.instruction
<= 0xffff)
11869 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11870 inst
.instruction
|= Rd
<< 8;
11871 inst
.instruction
|= Rm
;
11872 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
11876 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
11877 _("Thumb encoding does not support rotation"));
11878 constraint (1, BAD_HIREG
);
11885 /* We have to do the following check manually as ARM_EXT_OS only applies
11887 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6m
))
11889 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_os
)
11890 /* This only applies to the v6m howver, not later architectures. */
11891 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
))
11892 as_bad (_("SVC is not permitted on this architecture"));
11893 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, arm_ext_os
);
11896 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
11905 half
= (inst
.instruction
& 0x10) != 0;
11906 set_it_insn_type_last ();
11907 constraint (inst
.operands
[0].immisreg
,
11908 _("instruction requires register index"));
11910 Rn
= inst
.operands
[0].reg
;
11911 Rm
= inst
.operands
[0].imm
;
11913 constraint (Rn
== REG_SP
, BAD_SP
);
11914 reject_bad_reg (Rm
);
11916 constraint (!half
&& inst
.operands
[0].shifted
,
11917 _("instruction does not allow shifted index"));
11918 inst
.instruction
|= (Rn
<< 16) | Rm
;
11924 do_t_ssat_usat (0);
11932 Rd
= inst
.operands
[0].reg
;
11933 Rn
= inst
.operands
[2].reg
;
11935 reject_bad_reg (Rd
);
11936 reject_bad_reg (Rn
);
11938 inst
.instruction
|= Rd
<< 8;
11939 inst
.instruction
|= inst
.operands
[1].imm
;
11940 inst
.instruction
|= Rn
<< 16;
11943 /* Neon instruction encoder helpers. */
11945 /* Encodings for the different types for various Neon opcodes. */
11947 /* An "invalid" code for the following tables. */
11950 struct neon_tab_entry
11953 unsigned float_or_poly
;
11954 unsigned scalar_or_imm
;
11957 /* Map overloaded Neon opcodes to their respective encodings. */
11958 #define NEON_ENC_TAB \
11959 X(vabd, 0x0000700, 0x1200d00, N_INV), \
11960 X(vmax, 0x0000600, 0x0000f00, N_INV), \
11961 X(vmin, 0x0000610, 0x0200f00, N_INV), \
11962 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
11963 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
11964 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
11965 X(vadd, 0x0000800, 0x0000d00, N_INV), \
11966 X(vsub, 0x1000800, 0x0200d00, N_INV), \
11967 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
11968 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
11969 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
11970 /* Register variants of the following two instructions are encoded as
11971 vcge / vcgt with the operands reversed. */ \
11972 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
11973 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
11974 X(vfma, N_INV, 0x0000c10, N_INV), \
11975 X(vfms, N_INV, 0x0200c10, N_INV), \
11976 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
11977 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
11978 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
11979 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
11980 X(vmlal, 0x0800800, N_INV, 0x0800240), \
11981 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
11982 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
11983 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
11984 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
11985 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
11986 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
11987 X(vshl, 0x0000400, N_INV, 0x0800510), \
11988 X(vqshl, 0x0000410, N_INV, 0x0800710), \
11989 X(vand, 0x0000110, N_INV, 0x0800030), \
11990 X(vbic, 0x0100110, N_INV, 0x0800030), \
11991 X(veor, 0x1000110, N_INV, N_INV), \
11992 X(vorn, 0x0300110, N_INV, 0x0800010), \
11993 X(vorr, 0x0200110, N_INV, 0x0800010), \
11994 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
11995 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
11996 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
11997 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
11998 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
11999 X(vst1, 0x0000000, 0x0800000, N_INV), \
12000 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
12001 X(vst2, 0x0000100, 0x0800100, N_INV), \
12002 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
12003 X(vst3, 0x0000200, 0x0800200, N_INV), \
12004 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
12005 X(vst4, 0x0000300, 0x0800300, N_INV), \
12006 X(vmovn, 0x1b20200, N_INV, N_INV), \
12007 X(vtrn, 0x1b20080, N_INV, N_INV), \
12008 X(vqmovn, 0x1b20200, N_INV, N_INV), \
12009 X(vqmovun, 0x1b20240, N_INV, N_INV), \
12010 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
12011 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
12012 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
12013 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
12014 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
12015 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
12016 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
12017 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
12018 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV)
12022 #define X(OPC,I,F,S) N_MNEM_##OPC
12027 static const struct neon_tab_entry neon_enc_tab
[] =
12029 #define X(OPC,I,F,S) { (I), (F), (S) }
12034 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
12035 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12036 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12037 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12038 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12039 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12040 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12041 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
12042 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
12043 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
12044 #define NEON_ENC_SINGLE_(X) \
12045 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
12046 #define NEON_ENC_DOUBLE_(X) \
12047 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
12049 #define NEON_ENCODE(type, inst) \
12052 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
12053 inst.is_neon = 1; \
12057 #define check_neon_suffixes \
12060 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
12062 as_bad (_("invalid neon suffix for non neon instruction")); \
12068 /* Define shapes for instruction operands. The following mnemonic characters
12069 are used in this table:
12071 F - VFP S<n> register
12072 D - Neon D<n> register
12073 Q - Neon Q<n> register
12077 L - D<n> register list
12079 This table is used to generate various data:
12080 - enumerations of the form NS_DDR to be used as arguments to
12082 - a table classifying shapes into single, double, quad, mixed.
12083 - a table used to drive neon_select_shape. */
12085 #define NEON_SHAPE_DEF \
12086 X(3, (D, D, D), DOUBLE), \
12087 X(3, (Q, Q, Q), QUAD), \
12088 X(3, (D, D, I), DOUBLE), \
12089 X(3, (Q, Q, I), QUAD), \
12090 X(3, (D, D, S), DOUBLE), \
12091 X(3, (Q, Q, S), QUAD), \
12092 X(2, (D, D), DOUBLE), \
12093 X(2, (Q, Q), QUAD), \
12094 X(2, (D, S), DOUBLE), \
12095 X(2, (Q, S), QUAD), \
12096 X(2, (D, R), DOUBLE), \
12097 X(2, (Q, R), QUAD), \
12098 X(2, (D, I), DOUBLE), \
12099 X(2, (Q, I), QUAD), \
12100 X(3, (D, L, D), DOUBLE), \
12101 X(2, (D, Q), MIXED), \
12102 X(2, (Q, D), MIXED), \
12103 X(3, (D, Q, I), MIXED), \
12104 X(3, (Q, D, I), MIXED), \
12105 X(3, (Q, D, D), MIXED), \
12106 X(3, (D, Q, Q), MIXED), \
12107 X(3, (Q, Q, D), MIXED), \
12108 X(3, (Q, D, S), MIXED), \
12109 X(3, (D, Q, S), MIXED), \
12110 X(4, (D, D, D, I), DOUBLE), \
12111 X(4, (Q, Q, Q, I), QUAD), \
12112 X(2, (F, F), SINGLE), \
12113 X(3, (F, F, F), SINGLE), \
12114 X(2, (F, I), SINGLE), \
12115 X(2, (F, D), MIXED), \
12116 X(2, (D, F), MIXED), \
12117 X(3, (F, F, I), MIXED), \
12118 X(4, (R, R, F, F), SINGLE), \
12119 X(4, (F, F, R, R), SINGLE), \
12120 X(3, (D, R, R), DOUBLE), \
12121 X(3, (R, R, D), DOUBLE), \
12122 X(2, (S, R), SINGLE), \
12123 X(2, (R, S), SINGLE), \
12124 X(2, (F, R), SINGLE), \
12125 X(2, (R, F), SINGLE)
12127 #define S2(A,B) NS_##A##B
12128 #define S3(A,B,C) NS_##A##B##C
12129 #define S4(A,B,C,D) NS_##A##B##C##D
12131 #define X(N, L, C) S##N L
12144 enum neon_shape_class
12152 #define X(N, L, C) SC_##C
12154 static enum neon_shape_class neon_shape_class
[] =
12172 /* Register widths of above. */
12173 static unsigned neon_shape_el_size
[] =
12184 struct neon_shape_info
12187 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
12190 #define S2(A,B) { SE_##A, SE_##B }
12191 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
12192 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
12194 #define X(N, L, C) { N, S##N L }
12196 static struct neon_shape_info neon_shape_tab
[] =
12206 /* Bit masks used in type checking given instructions.
12207 'N_EQK' means the type must be the same as (or based on in some way) the key
12208 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
12209 set, various other bits can be set as well in order to modify the meaning of
12210 the type constraint. */
12212 enum neon_type_mask
12235 N_KEY
= 0x1000000, /* Key element (main type specifier). */
12236 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
12237 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
12238 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
12239 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
12240 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
12241 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
12242 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
12243 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
12244 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
12246 N_MAX_NONSPECIAL
= N_F64
12249 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
12251 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
12252 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
12253 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
12254 #define N_SUF_32 (N_SU_32 | N_F32)
12255 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
12256 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F32)
12258 /* Pass this as the first type argument to neon_check_type to ignore types
12260 #define N_IGNORE_TYPE (N_KEY | N_EQK)
12262 /* Select a "shape" for the current instruction (describing register types or
12263 sizes) from a list of alternatives. Return NS_NULL if the current instruction
12264 doesn't fit. For non-polymorphic shapes, checking is usually done as a
12265 function of operand parsing, so this function doesn't need to be called.
12266 Shapes should be listed in order of decreasing length. */
12268 static enum neon_shape
12269 neon_select_shape (enum neon_shape shape
, ...)
12272 enum neon_shape first_shape
= shape
;
12274 /* Fix missing optional operands. FIXME: we don't know at this point how
12275 many arguments we should have, so this makes the assumption that we have
12276 > 1. This is true of all current Neon opcodes, I think, but may not be
12277 true in the future. */
12278 if (!inst
.operands
[1].present
)
12279 inst
.operands
[1] = inst
.operands
[0];
12281 va_start (ap
, shape
);
12283 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
12288 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
12290 if (!inst
.operands
[j
].present
)
12296 switch (neon_shape_tab
[shape
].el
[j
])
12299 if (!(inst
.operands
[j
].isreg
12300 && inst
.operands
[j
].isvec
12301 && inst
.operands
[j
].issingle
12302 && !inst
.operands
[j
].isquad
))
12307 if (!(inst
.operands
[j
].isreg
12308 && inst
.operands
[j
].isvec
12309 && !inst
.operands
[j
].isquad
12310 && !inst
.operands
[j
].issingle
))
12315 if (!(inst
.operands
[j
].isreg
12316 && !inst
.operands
[j
].isvec
))
12321 if (!(inst
.operands
[j
].isreg
12322 && inst
.operands
[j
].isvec
12323 && inst
.operands
[j
].isquad
12324 && !inst
.operands
[j
].issingle
))
12329 if (!(!inst
.operands
[j
].isreg
12330 && !inst
.operands
[j
].isscalar
))
12335 if (!(!inst
.operands
[j
].isreg
12336 && inst
.operands
[j
].isscalar
))
12352 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
12353 first_error (_("invalid instruction shape"));
12358 /* True if SHAPE is predominantly a quadword operation (most of the time, this
12359 means the Q bit should be set). */
12362 neon_quad (enum neon_shape shape
)
12364 return neon_shape_class
[shape
] == SC_QUAD
;
12368 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
12371 /* Allow modification to be made to types which are constrained to be
12372 based on the key element, based on bits set alongside N_EQK. */
12373 if ((typebits
& N_EQK
) != 0)
12375 if ((typebits
& N_HLF
) != 0)
12377 else if ((typebits
& N_DBL
) != 0)
12379 if ((typebits
& N_SGN
) != 0)
12380 *g_type
= NT_signed
;
12381 else if ((typebits
& N_UNS
) != 0)
12382 *g_type
= NT_unsigned
;
12383 else if ((typebits
& N_INT
) != 0)
12384 *g_type
= NT_integer
;
12385 else if ((typebits
& N_FLT
) != 0)
12386 *g_type
= NT_float
;
12387 else if ((typebits
& N_SIZ
) != 0)
12388 *g_type
= NT_untyped
;
12392 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
12393 operand type, i.e. the single type specified in a Neon instruction when it
12394 is the only one given. */
12396 static struct neon_type_el
12397 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
12399 struct neon_type_el dest
= *key
;
12401 gas_assert ((thisarg
& N_EQK
) != 0);
12403 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
12408 /* Convert Neon type and size into compact bitmask representation. */
12410 static enum neon_type_mask
12411 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
12418 case 8: return N_8
;
12419 case 16: return N_16
;
12420 case 32: return N_32
;
12421 case 64: return N_64
;
12429 case 8: return N_I8
;
12430 case 16: return N_I16
;
12431 case 32: return N_I32
;
12432 case 64: return N_I64
;
12440 case 16: return N_F16
;
12441 case 32: return N_F32
;
12442 case 64: return N_F64
;
12450 case 8: return N_P8
;
12451 case 16: return N_P16
;
12459 case 8: return N_S8
;
12460 case 16: return N_S16
;
12461 case 32: return N_S32
;
12462 case 64: return N_S64
;
12470 case 8: return N_U8
;
12471 case 16: return N_U16
;
12472 case 32: return N_U32
;
12473 case 64: return N_U64
;
12484 /* Convert compact Neon bitmask type representation to a type and size. Only
12485 handles the case where a single bit is set in the mask. */
12488 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
12489 enum neon_type_mask mask
)
12491 if ((mask
& N_EQK
) != 0)
12494 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
12496 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_P16
)) != 0)
12498 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
12500 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
)) != 0)
12505 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
12507 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
12508 *type
= NT_unsigned
;
12509 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
12510 *type
= NT_integer
;
12511 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
12512 *type
= NT_untyped
;
12513 else if ((mask
& (N_P8
| N_P16
)) != 0)
12515 else if ((mask
& (N_F32
| N_F64
)) != 0)
12523 /* Modify a bitmask of allowed types. This is only needed for type
12527 modify_types_allowed (unsigned allowed
, unsigned mods
)
12530 enum neon_el_type type
;
12536 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
12538 if (el_type_of_type_chk (&type
, &size
,
12539 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
12541 neon_modify_type_size (mods
, &type
, &size
);
12542 destmask
|= type_chk_of_el_type (type
, size
);
12549 /* Check type and return type classification.
12550 The manual states (paraphrase): If one datatype is given, it indicates the
12552 - the second operand, if there is one
12553 - the operand, if there is no second operand
12554 - the result, if there are no operands.
12555 This isn't quite good enough though, so we use a concept of a "key" datatype
12556 which is set on a per-instruction basis, which is the one which matters when
12557 only one data type is written.
12558 Note: this function has side-effects (e.g. filling in missing operands). All
12559 Neon instructions should call it before performing bit encoding. */
12561 static struct neon_type_el
12562 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
12565 unsigned i
, pass
, key_el
= 0;
12566 unsigned types
[NEON_MAX_TYPE_ELS
];
12567 enum neon_el_type k_type
= NT_invtype
;
12568 unsigned k_size
= -1u;
12569 struct neon_type_el badtype
= {NT_invtype
, -1};
12570 unsigned key_allowed
= 0;
12572 /* Optional registers in Neon instructions are always (not) in operand 1.
12573 Fill in the missing operand here, if it was omitted. */
12574 if (els
> 1 && !inst
.operands
[1].present
)
12575 inst
.operands
[1] = inst
.operands
[0];
12577 /* Suck up all the varargs. */
12579 for (i
= 0; i
< els
; i
++)
12581 unsigned thisarg
= va_arg (ap
, unsigned);
12582 if (thisarg
== N_IGNORE_TYPE
)
12587 types
[i
] = thisarg
;
12588 if ((thisarg
& N_KEY
) != 0)
12593 if (inst
.vectype
.elems
> 0)
12594 for (i
= 0; i
< els
; i
++)
12595 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
12597 first_error (_("types specified in both the mnemonic and operands"));
12601 /* Duplicate inst.vectype elements here as necessary.
12602 FIXME: No idea if this is exactly the same as the ARM assembler,
12603 particularly when an insn takes one register and one non-register
12605 if (inst
.vectype
.elems
== 1 && els
> 1)
12608 inst
.vectype
.elems
= els
;
12609 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
12610 for (j
= 0; j
< els
; j
++)
12612 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12615 else if (inst
.vectype
.elems
== 0 && els
> 0)
12618 /* No types were given after the mnemonic, so look for types specified
12619 after each operand. We allow some flexibility here; as long as the
12620 "key" operand has a type, we can infer the others. */
12621 for (j
= 0; j
< els
; j
++)
12622 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
12623 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
12625 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
12627 for (j
= 0; j
< els
; j
++)
12628 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
12629 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
12634 first_error (_("operand types can't be inferred"));
12638 else if (inst
.vectype
.elems
!= els
)
12640 first_error (_("type specifier has the wrong number of parts"));
12644 for (pass
= 0; pass
< 2; pass
++)
12646 for (i
= 0; i
< els
; i
++)
12648 unsigned thisarg
= types
[i
];
12649 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
12650 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
12651 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
12652 unsigned g_size
= inst
.vectype
.el
[i
].size
;
12654 /* Decay more-specific signed & unsigned types to sign-insensitive
12655 integer types if sign-specific variants are unavailable. */
12656 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
12657 && (types_allowed
& N_SU_ALL
) == 0)
12658 g_type
= NT_integer
;
12660 /* If only untyped args are allowed, decay any more specific types to
12661 them. Some instructions only care about signs for some element
12662 sizes, so handle that properly. */
12663 if ((g_size
== 8 && (types_allowed
& N_8
) != 0)
12664 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
12665 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
12666 || (g_size
== 64 && (types_allowed
& N_64
) != 0))
12667 g_type
= NT_untyped
;
12671 if ((thisarg
& N_KEY
) != 0)
12675 key_allowed
= thisarg
& ~N_KEY
;
12680 if ((thisarg
& N_VFP
) != 0)
12682 enum neon_shape_el regshape
;
12683 unsigned regwidth
, match
;
12685 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
12688 first_error (_("invalid instruction shape"));
12691 regshape
= neon_shape_tab
[ns
].el
[i
];
12692 regwidth
= neon_shape_el_size
[regshape
];
12694 /* In VFP mode, operands must match register widths. If we
12695 have a key operand, use its width, else use the width of
12696 the current operand. */
12702 if (regwidth
!= match
)
12704 first_error (_("operand size must match register width"));
12709 if ((thisarg
& N_EQK
) == 0)
12711 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
12713 if ((given_type
& types_allowed
) == 0)
12715 first_error (_("bad type in Neon instruction"));
12721 enum neon_el_type mod_k_type
= k_type
;
12722 unsigned mod_k_size
= k_size
;
12723 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
12724 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
12726 first_error (_("inconsistent types in Neon instruction"));
12734 return inst
.vectype
.el
[key_el
];
12737 /* Neon-style VFP instruction forwarding. */
12739 /* Thumb VFP instructions have 0xE in the condition field. */
12742 do_vfp_cond_or_thumb (void)
12747 inst
.instruction
|= 0xe0000000;
12749 inst
.instruction
|= inst
.cond
<< 28;
12752 /* Look up and encode a simple mnemonic, for use as a helper function for the
12753 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
12754 etc. It is assumed that operand parsing has already been done, and that the
12755 operands are in the form expected by the given opcode (this isn't necessarily
12756 the same as the form in which they were parsed, hence some massaging must
12757 take place before this function is called).
12758 Checks current arch version against that in the looked-up opcode. */
12761 do_vfp_nsyn_opcode (const char *opname
)
12763 const struct asm_opcode
*opcode
;
12765 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
12770 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
12771 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
12778 inst
.instruction
= opcode
->tvalue
;
12779 opcode
->tencode ();
12783 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
12784 opcode
->aencode ();
12789 do_vfp_nsyn_add_sub (enum neon_shape rs
)
12791 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
12796 do_vfp_nsyn_opcode ("fadds");
12798 do_vfp_nsyn_opcode ("fsubs");
12803 do_vfp_nsyn_opcode ("faddd");
12805 do_vfp_nsyn_opcode ("fsubd");
12809 /* Check operand types to see if this is a VFP instruction, and if so call
12813 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
12815 enum neon_shape rs
;
12816 struct neon_type_el et
;
12821 rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12822 et
= neon_check_type (2, rs
,
12823 N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12827 rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12828 et
= neon_check_type (3, rs
,
12829 N_EQK
| N_VFP
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12836 if (et
.type
!= NT_invtype
)
12847 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
12849 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
12854 do_vfp_nsyn_opcode ("fmacs");
12856 do_vfp_nsyn_opcode ("fnmacs");
12861 do_vfp_nsyn_opcode ("fmacd");
12863 do_vfp_nsyn_opcode ("fnmacd");
12868 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
12870 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
12875 do_vfp_nsyn_opcode ("ffmas");
12877 do_vfp_nsyn_opcode ("ffnmas");
12882 do_vfp_nsyn_opcode ("ffmad");
12884 do_vfp_nsyn_opcode ("ffnmad");
12889 do_vfp_nsyn_mul (enum neon_shape rs
)
12892 do_vfp_nsyn_opcode ("fmuls");
12894 do_vfp_nsyn_opcode ("fmuld");
12898 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
12900 int is_neg
= (inst
.instruction
& 0x80) != 0;
12901 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_VFP
| N_KEY
);
12906 do_vfp_nsyn_opcode ("fnegs");
12908 do_vfp_nsyn_opcode ("fabss");
12913 do_vfp_nsyn_opcode ("fnegd");
12915 do_vfp_nsyn_opcode ("fabsd");
12919 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
12920 insns belong to Neon, and are handled elsewhere. */
12923 do_vfp_nsyn_ldm_stm (int is_dbmode
)
12925 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
12929 do_vfp_nsyn_opcode ("fldmdbs");
12931 do_vfp_nsyn_opcode ("fldmias");
12936 do_vfp_nsyn_opcode ("fstmdbs");
12938 do_vfp_nsyn_opcode ("fstmias");
12943 do_vfp_nsyn_sqrt (void)
12945 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12946 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12949 do_vfp_nsyn_opcode ("fsqrts");
12951 do_vfp_nsyn_opcode ("fsqrtd");
12955 do_vfp_nsyn_div (void)
12957 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12958 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12959 N_F32
| N_F64
| N_KEY
| N_VFP
);
12962 do_vfp_nsyn_opcode ("fdivs");
12964 do_vfp_nsyn_opcode ("fdivd");
12968 do_vfp_nsyn_nmul (void)
12970 enum neon_shape rs
= neon_select_shape (NS_FFF
, NS_DDD
, NS_NULL
);
12971 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
12972 N_F32
| N_F64
| N_KEY
| N_VFP
);
12976 NEON_ENCODE (SINGLE
, inst
);
12977 do_vfp_sp_dyadic ();
12981 NEON_ENCODE (DOUBLE
, inst
);
12982 do_vfp_dp_rd_rn_rm ();
12984 do_vfp_cond_or_thumb ();
12988 do_vfp_nsyn_cmp (void)
12990 if (inst
.operands
[1].isreg
)
12992 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_DD
, NS_NULL
);
12993 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F32
| N_F64
| N_KEY
| N_VFP
);
12997 NEON_ENCODE (SINGLE
, inst
);
12998 do_vfp_sp_monadic ();
13002 NEON_ENCODE (DOUBLE
, inst
);
13003 do_vfp_dp_rd_rm ();
13008 enum neon_shape rs
= neon_select_shape (NS_FI
, NS_DI
, NS_NULL
);
13009 neon_check_type (2, rs
, N_F32
| N_F64
| N_KEY
| N_VFP
, N_EQK
);
13011 switch (inst
.instruction
& 0x0fffffff)
13014 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
13017 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
13025 NEON_ENCODE (SINGLE
, inst
);
13026 do_vfp_sp_compare_z ();
13030 NEON_ENCODE (DOUBLE
, inst
);
13034 do_vfp_cond_or_thumb ();
13038 nsyn_insert_sp (void)
13040 inst
.operands
[1] = inst
.operands
[0];
13041 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
13042 inst
.operands
[0].reg
= REG_SP
;
13043 inst
.operands
[0].isreg
= 1;
13044 inst
.operands
[0].writeback
= 1;
13045 inst
.operands
[0].present
= 1;
13049 do_vfp_nsyn_push (void)
13052 if (inst
.operands
[1].issingle
)
13053 do_vfp_nsyn_opcode ("fstmdbs");
13055 do_vfp_nsyn_opcode ("fstmdbd");
13059 do_vfp_nsyn_pop (void)
13062 if (inst
.operands
[1].issingle
)
13063 do_vfp_nsyn_opcode ("fldmias");
13065 do_vfp_nsyn_opcode ("fldmiad");
13068 /* Fix up Neon data-processing instructions, ORing in the correct bits for
13069 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
13072 neon_dp_fixup (struct arm_it
* insn
)
13074 unsigned int i
= insn
->instruction
;
13079 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
13090 insn
->instruction
= i
;
13093 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
13097 neon_logbits (unsigned x
)
13099 return ffs (x
) - 4;
13102 #define LOW4(R) ((R) & 0xf)
13103 #define HI1(R) (((R) >> 4) & 1)
13105 /* Encode insns with bit pattern:
13107 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
13108 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
13110 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
13111 different meaning for some instruction. */
13114 neon_three_same (int isquad
, int ubit
, int size
)
13116 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13117 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13118 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13119 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13120 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
13121 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
13122 inst
.instruction
|= (isquad
!= 0) << 6;
13123 inst
.instruction
|= (ubit
!= 0) << 24;
13125 inst
.instruction
|= neon_logbits (size
) << 20;
13127 neon_dp_fixup (&inst
);
13130 /* Encode instructions of the form:
13132 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
13133 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
13135 Don't write size if SIZE == -1. */
13138 neon_two_same (int qbit
, int ubit
, int size
)
13140 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13141 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13142 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13143 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13144 inst
.instruction
|= (qbit
!= 0) << 6;
13145 inst
.instruction
|= (ubit
!= 0) << 24;
13148 inst
.instruction
|= neon_logbits (size
) << 18;
13150 neon_dp_fixup (&inst
);
13153 /* Neon instruction encoders, in approximate order of appearance. */
13156 do_neon_dyadic_i_su (void)
13158 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13159 struct neon_type_el et
= neon_check_type (3, rs
,
13160 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
13161 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13165 do_neon_dyadic_i64_su (void)
13167 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13168 struct neon_type_el et
= neon_check_type (3, rs
,
13169 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13170 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13174 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
13177 unsigned size
= et
.size
>> 3;
13178 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13179 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13180 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13181 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13182 inst
.instruction
|= (isquad
!= 0) << 6;
13183 inst
.instruction
|= immbits
<< 16;
13184 inst
.instruction
|= (size
>> 3) << 7;
13185 inst
.instruction
|= (size
& 0x7) << 19;
13187 inst
.instruction
|= (uval
!= 0) << 24;
13189 neon_dp_fixup (&inst
);
13193 do_neon_shl_imm (void)
13195 if (!inst
.operands
[2].isreg
)
13197 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13198 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
13199 NEON_ENCODE (IMMED
, inst
);
13200 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, inst
.operands
[2].imm
);
13204 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13205 struct neon_type_el et
= neon_check_type (3, rs
,
13206 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13209 /* VSHL/VQSHL 3-register variants have syntax such as:
13211 whereas other 3-register operations encoded by neon_three_same have
13214 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
13216 tmp
= inst
.operands
[2].reg
;
13217 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13218 inst
.operands
[1].reg
= tmp
;
13219 NEON_ENCODE (INTEGER
, inst
);
13220 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13225 do_neon_qshl_imm (void)
13227 if (!inst
.operands
[2].isreg
)
13229 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13230 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
13232 NEON_ENCODE (IMMED
, inst
);
13233 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
13234 inst
.operands
[2].imm
);
13238 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13239 struct neon_type_el et
= neon_check_type (3, rs
,
13240 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
13243 /* See note in do_neon_shl_imm. */
13244 tmp
= inst
.operands
[2].reg
;
13245 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13246 inst
.operands
[1].reg
= tmp
;
13247 NEON_ENCODE (INTEGER
, inst
);
13248 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13253 do_neon_rshl (void)
13255 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13256 struct neon_type_el et
= neon_check_type (3, rs
,
13257 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
13260 tmp
= inst
.operands
[2].reg
;
13261 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
13262 inst
.operands
[1].reg
= tmp
;
13263 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
13267 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
13269 /* Handle .I8 pseudo-instructions. */
13272 /* Unfortunately, this will make everything apart from zero out-of-range.
13273 FIXME is this the intended semantics? There doesn't seem much point in
13274 accepting .I8 if so. */
13275 immediate
|= immediate
<< 8;
13281 if (immediate
== (immediate
& 0x000000ff))
13283 *immbits
= immediate
;
13286 else if (immediate
== (immediate
& 0x0000ff00))
13288 *immbits
= immediate
>> 8;
13291 else if (immediate
== (immediate
& 0x00ff0000))
13293 *immbits
= immediate
>> 16;
13296 else if (immediate
== (immediate
& 0xff000000))
13298 *immbits
= immediate
>> 24;
13301 if ((immediate
& 0xffff) != (immediate
>> 16))
13302 goto bad_immediate
;
13303 immediate
&= 0xffff;
13306 if (immediate
== (immediate
& 0x000000ff))
13308 *immbits
= immediate
;
13311 else if (immediate
== (immediate
& 0x0000ff00))
13313 *immbits
= immediate
>> 8;
13318 first_error (_("immediate value out of range"));
13322 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
13326 neon_bits_same_in_bytes (unsigned imm
)
13328 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
13329 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
13330 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
13331 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
13334 /* For immediate of above form, return 0bABCD. */
13337 neon_squash_bits (unsigned imm
)
13339 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
13340 | ((imm
& 0x01000000) >> 21);
13343 /* Compress quarter-float representation to 0b...000 abcdefgh. */
13346 neon_qfloat_bits (unsigned imm
)
13348 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
13351 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
13352 the instruction. *OP is passed as the initial value of the op field, and
13353 may be set to a different value depending on the constant (i.e.
13354 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
13355 MVN). If the immediate looks like a repeated pattern then also
13356 try smaller element sizes. */
13359 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
13360 unsigned *immbits
, int *op
, int size
,
13361 enum neon_el_type type
)
13363 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
13365 if (type
== NT_float
&& !float_p
)
13368 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
13370 if (size
!= 32 || *op
== 1)
13372 *immbits
= neon_qfloat_bits (immlo
);
13378 if (neon_bits_same_in_bytes (immhi
)
13379 && neon_bits_same_in_bytes (immlo
))
13383 *immbits
= (neon_squash_bits (immhi
) << 4)
13384 | neon_squash_bits (immlo
);
13389 if (immhi
!= immlo
)
13395 if (immlo
== (immlo
& 0x000000ff))
13400 else if (immlo
== (immlo
& 0x0000ff00))
13402 *immbits
= immlo
>> 8;
13405 else if (immlo
== (immlo
& 0x00ff0000))
13407 *immbits
= immlo
>> 16;
13410 else if (immlo
== (immlo
& 0xff000000))
13412 *immbits
= immlo
>> 24;
13415 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
13417 *immbits
= (immlo
>> 8) & 0xff;
13420 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
13422 *immbits
= (immlo
>> 16) & 0xff;
13426 if ((immlo
& 0xffff) != (immlo
>> 16))
13433 if (immlo
== (immlo
& 0x000000ff))
13438 else if (immlo
== (immlo
& 0x0000ff00))
13440 *immbits
= immlo
>> 8;
13444 if ((immlo
& 0xff) != (immlo
>> 8))
13449 if (immlo
== (immlo
& 0x000000ff))
13451 /* Don't allow MVN with 8-bit immediate. */
13461 /* Write immediate bits [7:0] to the following locations:
13463 |28/24|23 19|18 16|15 4|3 0|
13464 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
13466 This function is used by VMOV/VMVN/VORR/VBIC. */
13469 neon_write_immbits (unsigned immbits
)
13471 inst
.instruction
|= immbits
& 0xf;
13472 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
13473 inst
.instruction
|= ((immbits
>> 7) & 0x1) << 24;
13476 /* Invert low-order SIZE bits of XHI:XLO. */
13479 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
13481 unsigned immlo
= xlo
? *xlo
: 0;
13482 unsigned immhi
= xhi
? *xhi
: 0;
13487 immlo
= (~immlo
) & 0xff;
13491 immlo
= (~immlo
) & 0xffff;
13495 immhi
= (~immhi
) & 0xffffffff;
13496 /* fall through. */
13499 immlo
= (~immlo
) & 0xffffffff;
13514 do_neon_logic (void)
13516 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
13518 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13519 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13520 /* U bit and size field were set as part of the bitmask. */
13521 NEON_ENCODE (INTEGER
, inst
);
13522 neon_three_same (neon_quad (rs
), 0, -1);
13526 const int three_ops_form
= (inst
.operands
[2].present
13527 && !inst
.operands
[2].isreg
);
13528 const int immoperand
= (three_ops_form
? 2 : 1);
13529 enum neon_shape rs
= (three_ops_form
13530 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
13531 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
13532 struct neon_type_el et
= neon_check_type (2, rs
,
13533 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
13534 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
13538 if (et
.type
== NT_invtype
)
13541 if (three_ops_form
)
13542 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13543 _("first and second operands shall be the same register"));
13545 NEON_ENCODE (IMMED
, inst
);
13547 immbits
= inst
.operands
[immoperand
].imm
;
13550 /* .i64 is a pseudo-op, so the immediate must be a repeating
13552 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
13553 inst
.operands
[immoperand
].reg
: 0))
13555 /* Set immbits to an invalid constant. */
13556 immbits
= 0xdeadbeef;
13563 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13567 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13571 /* Pseudo-instruction for VBIC. */
13572 neon_invert_size (&immbits
, 0, et
.size
);
13573 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13577 /* Pseudo-instruction for VORR. */
13578 neon_invert_size (&immbits
, 0, et
.size
);
13579 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
13589 inst
.instruction
|= neon_quad (rs
) << 6;
13590 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13591 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13592 inst
.instruction
|= cmode
<< 8;
13593 neon_write_immbits (immbits
);
13595 neon_dp_fixup (&inst
);
13600 do_neon_bitfield (void)
13602 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13603 neon_check_type (3, rs
, N_IGNORE_TYPE
);
13604 neon_three_same (neon_quad (rs
), 0, -1);
13608 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
13611 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13612 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
13614 if (et
.type
== NT_float
)
13616 NEON_ENCODE (FLOAT
, inst
);
13617 neon_three_same (neon_quad (rs
), 0, -1);
13621 NEON_ENCODE (INTEGER
, inst
);
13622 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
13627 do_neon_dyadic_if_su (void)
13629 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13633 do_neon_dyadic_if_su_d (void)
13635 /* This version only allow D registers, but that constraint is enforced during
13636 operand parsing so we don't need to do anything extra here. */
13637 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
13641 do_neon_dyadic_if_i_d (void)
13643 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13644 affected if we specify unsigned args. */
13645 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13648 enum vfp_or_neon_is_neon_bits
13651 NEON_CHECK_ARCH
= 2
13654 /* Call this function if an instruction which may have belonged to the VFP or
13655 Neon instruction sets, but turned out to be a Neon instruction (due to the
13656 operand types involved, etc.). We have to check and/or fix-up a couple of
13659 - Make sure the user hasn't attempted to make a Neon instruction
13661 - Alter the value in the condition code field if necessary.
13662 - Make sure that the arch supports Neon instructions.
13664 Which of these operations take place depends on bits from enum
13665 vfp_or_neon_is_neon_bits.
13667 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
13668 current instruction's condition is COND_ALWAYS, the condition field is
13669 changed to inst.uncond_value. This is necessary because instructions shared
13670 between VFP and Neon may be conditional for the VFP variants only, and the
13671 unconditional Neon version must have, e.g., 0xF in the condition field. */
13674 vfp_or_neon_is_neon (unsigned check
)
13676 /* Conditions are always legal in Thumb mode (IT blocks). */
13677 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
13679 if (inst
.cond
!= COND_ALWAYS
)
13681 first_error (_(BAD_COND
));
13684 if (inst
.uncond_value
!= -1)
13685 inst
.instruction
|= inst
.uncond_value
<< 28;
13688 if ((check
& NEON_CHECK_ARCH
)
13689 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
13691 first_error (_(BAD_FPU
));
13699 do_neon_addsub_if_i (void)
13701 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
13704 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13707 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13708 affected if we specify unsigned args. */
13709 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
13712 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
13714 V<op> A,B (A is operand 0, B is operand 2)
13719 so handle that case specially. */
13722 neon_exchange_operands (void)
13724 void *scratch
= alloca (sizeof (inst
.operands
[0]));
13725 if (inst
.operands
[1].present
)
13727 /* Swap operands[1] and operands[2]. */
13728 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
13729 inst
.operands
[1] = inst
.operands
[2];
13730 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
13734 inst
.operands
[1] = inst
.operands
[2];
13735 inst
.operands
[2] = inst
.operands
[0];
13740 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
13742 if (inst
.operands
[2].isreg
)
13745 neon_exchange_operands ();
13746 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
13750 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13751 struct neon_type_el et
= neon_check_type (2, rs
,
13752 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
13754 NEON_ENCODE (IMMED
, inst
);
13755 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13756 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13757 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13758 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13759 inst
.instruction
|= neon_quad (rs
) << 6;
13760 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13761 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13763 neon_dp_fixup (&inst
);
13770 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, FALSE
);
13774 do_neon_cmp_inv (void)
13776 neon_compare (N_SUF_32
, N_S8
| N_S16
| N_S32
| N_F32
, TRUE
);
13782 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
13785 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
13786 scalars, which are encoded in 5 bits, M : Rm.
13787 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
13788 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
13792 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
13794 unsigned regno
= NEON_SCALAR_REG (scalar
);
13795 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
13800 if (regno
> 7 || elno
> 3)
13802 return regno
| (elno
<< 3);
13805 if (regno
> 15 || elno
> 1)
13807 return regno
| (elno
<< 4);
13811 first_error (_("scalar out of range for multiply instruction"));
13817 /* Encode multiply / multiply-accumulate scalar instructions. */
13820 neon_mul_mac (struct neon_type_el et
, int ubit
)
13824 /* Give a more helpful error message if we have an invalid type. */
13825 if (et
.type
== NT_invtype
)
13828 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
13829 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13830 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13831 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
13832 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
13833 inst
.instruction
|= LOW4 (scalar
);
13834 inst
.instruction
|= HI1 (scalar
) << 5;
13835 inst
.instruction
|= (et
.type
== NT_float
) << 8;
13836 inst
.instruction
|= neon_logbits (et
.size
) << 20;
13837 inst
.instruction
|= (ubit
!= 0) << 24;
13839 neon_dp_fixup (&inst
);
13843 do_neon_mac_maybe_scalar (void)
13845 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
13848 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13851 if (inst
.operands
[2].isscalar
)
13853 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13854 struct neon_type_el et
= neon_check_type (3, rs
,
13855 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F32
| N_KEY
);
13856 NEON_ENCODE (SCALAR
, inst
);
13857 neon_mul_mac (et
, neon_quad (rs
));
13861 /* The "untyped" case can't happen. Do this to stop the "U" bit being
13862 affected if we specify unsigned args. */
13863 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13868 do_neon_fmac (void)
13870 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
13873 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13876 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
13882 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13883 struct neon_type_el et
= neon_check_type (3, rs
,
13884 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
13885 neon_three_same (neon_quad (rs
), 0, et
.size
);
13888 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
13889 same types as the MAC equivalents. The polynomial type for this instruction
13890 is encoded the same as the integer type. */
13895 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
13898 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13901 if (inst
.operands
[2].isscalar
)
13902 do_neon_mac_maybe_scalar ();
13904 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F32
| N_P8
, 0);
13908 do_neon_qdmulh (void)
13910 if (inst
.operands
[2].isscalar
)
13912 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
13913 struct neon_type_el et
= neon_check_type (3, rs
,
13914 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13915 NEON_ENCODE (SCALAR
, inst
);
13916 neon_mul_mac (et
, neon_quad (rs
));
13920 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13921 struct neon_type_el et
= neon_check_type (3, rs
,
13922 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
13923 NEON_ENCODE (INTEGER
, inst
);
13924 /* The U bit (rounding) comes from bit mask. */
13925 neon_three_same (neon_quad (rs
), 0, et
.size
);
13930 do_neon_fcmp_absolute (void)
13932 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13933 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13934 /* Size field comes from bit mask. */
13935 neon_three_same (neon_quad (rs
), 1, -1);
13939 do_neon_fcmp_absolute_inv (void)
13941 neon_exchange_operands ();
13942 do_neon_fcmp_absolute ();
13946 do_neon_step (void)
13948 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
13949 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F32
| N_KEY
);
13950 neon_three_same (neon_quad (rs
), 0, -1);
13954 do_neon_abs_neg (void)
13956 enum neon_shape rs
;
13957 struct neon_type_el et
;
13959 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
13962 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
13965 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
13966 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_F32
| N_KEY
);
13968 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
13969 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
13970 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
13971 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
13972 inst
.instruction
|= neon_quad (rs
) << 6;
13973 inst
.instruction
|= (et
.type
== NT_float
) << 10;
13974 inst
.instruction
|= neon_logbits (et
.size
) << 18;
13976 neon_dp_fixup (&inst
);
13982 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13983 struct neon_type_el et
= neon_check_type (2, rs
,
13984 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13985 int imm
= inst
.operands
[2].imm
;
13986 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
13987 _("immediate out of range for insert"));
13988 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
13994 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
13995 struct neon_type_el et
= neon_check_type (2, rs
,
13996 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
13997 int imm
= inst
.operands
[2].imm
;
13998 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
13999 _("immediate out of range for insert"));
14000 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
14004 do_neon_qshlu_imm (void)
14006 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14007 struct neon_type_el et
= neon_check_type (2, rs
,
14008 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
14009 int imm
= inst
.operands
[2].imm
;
14010 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14011 _("immediate out of range for shift"));
14012 /* Only encodes the 'U present' variant of the instruction.
14013 In this case, signed types have OP (bit 8) set to 0.
14014 Unsigned types have OP set to 1. */
14015 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
14016 /* The rest of the bits are the same as other immediate shifts. */
14017 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14021 do_neon_qmovn (void)
14023 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14024 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14025 /* Saturating move where operands can be signed or unsigned, and the
14026 destination has the same signedness. */
14027 NEON_ENCODE (INTEGER
, inst
);
14028 if (et
.type
== NT_unsigned
)
14029 inst
.instruction
|= 0xc0;
14031 inst
.instruction
|= 0x80;
14032 neon_two_same (0, 1, et
.size
/ 2);
14036 do_neon_qmovun (void)
14038 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14039 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14040 /* Saturating move with unsigned results. Operands must be signed. */
14041 NEON_ENCODE (INTEGER
, inst
);
14042 neon_two_same (0, 1, et
.size
/ 2);
14046 do_neon_rshift_sat_narrow (void)
14048 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14049 or unsigned. If operands are unsigned, results must also be unsigned. */
14050 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14051 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
14052 int imm
= inst
.operands
[2].imm
;
14053 /* This gets the bounds check, size encoding and immediate bits calculation
14057 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
14058 VQMOVN.I<size> <Dd>, <Qm>. */
14061 inst
.operands
[2].present
= 0;
14062 inst
.instruction
= N_MNEM_vqmovn
;
14067 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14068 _("immediate out of range"));
14069 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
14073 do_neon_rshift_sat_narrow_u (void)
14075 /* FIXME: Types for narrowing. If operands are signed, results can be signed
14076 or unsigned. If operands are unsigned, results must also be unsigned. */
14077 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14078 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
14079 int imm
= inst
.operands
[2].imm
;
14080 /* This gets the bounds check, size encoding and immediate bits calculation
14084 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
14085 VQMOVUN.I<size> <Dd>, <Qm>. */
14088 inst
.operands
[2].present
= 0;
14089 inst
.instruction
= N_MNEM_vqmovun
;
14094 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14095 _("immediate out of range"));
14096 /* FIXME: The manual is kind of unclear about what value U should have in
14097 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
14099 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
14103 do_neon_movn (void)
14105 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
14106 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14107 NEON_ENCODE (INTEGER
, inst
);
14108 neon_two_same (0, 1, et
.size
/ 2);
14112 do_neon_rshift_narrow (void)
14114 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
14115 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
14116 int imm
= inst
.operands
[2].imm
;
14117 /* This gets the bounds check, size encoding and immediate bits calculation
14121 /* If immediate is zero then we are a pseudo-instruction for
14122 VMOVN.I<size> <Dd>, <Qm> */
14125 inst
.operands
[2].present
= 0;
14126 inst
.instruction
= N_MNEM_vmovn
;
14131 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
14132 _("immediate out of range for narrowing operation"));
14133 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
14137 do_neon_shll (void)
14139 /* FIXME: Type checking when lengthening. */
14140 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
14141 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
14142 unsigned imm
= inst
.operands
[2].imm
;
14144 if (imm
== et
.size
)
14146 /* Maximum shift variant. */
14147 NEON_ENCODE (INTEGER
, inst
);
14148 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14149 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14150 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14151 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14152 inst
.instruction
|= neon_logbits (et
.size
) << 18;
14154 neon_dp_fixup (&inst
);
14158 /* A more-specific type check for non-max versions. */
14159 et
= neon_check_type (2, NS_QDI
,
14160 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14161 NEON_ENCODE (IMMED
, inst
);
14162 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
14166 /* Check the various types for the VCVT instruction, and return which version
14167 the current instruction is. */
14170 neon_cvt_flavour (enum neon_shape rs
)
14172 #define CVT_VAR(C,X,Y) \
14173 et = neon_check_type (2, rs, whole_reg | (X), whole_reg | (Y)); \
14174 if (et.type != NT_invtype) \
14176 inst.error = NULL; \
14179 struct neon_type_el et
;
14180 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
14181 || rs
== NS_FF
) ? N_VFP
: 0;
14182 /* The instruction versions which take an immediate take one register
14183 argument, which is extended to the width of the full register. Thus the
14184 "source" and "destination" registers must have the same width. Hack that
14185 here by making the size equal to the key (wider, in this case) operand. */
14186 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
14188 CVT_VAR (0, N_S32
, N_F32
);
14189 CVT_VAR (1, N_U32
, N_F32
);
14190 CVT_VAR (2, N_F32
, N_S32
);
14191 CVT_VAR (3, N_F32
, N_U32
);
14192 /* Half-precision conversions. */
14193 CVT_VAR (4, N_F32
, N_F16
);
14194 CVT_VAR (5, N_F16
, N_F32
);
14198 /* VFP instructions. */
14199 CVT_VAR (6, N_F32
, N_F64
);
14200 CVT_VAR (7, N_F64
, N_F32
);
14201 CVT_VAR (8, N_S32
, N_F64
| key
);
14202 CVT_VAR (9, N_U32
, N_F64
| key
);
14203 CVT_VAR (10, N_F64
| key
, N_S32
);
14204 CVT_VAR (11, N_F64
| key
, N_U32
);
14205 /* VFP instructions with bitshift. */
14206 CVT_VAR (12, N_F32
| key
, N_S16
);
14207 CVT_VAR (13, N_F32
| key
, N_U16
);
14208 CVT_VAR (14, N_F64
| key
, N_S16
);
14209 CVT_VAR (15, N_F64
| key
, N_U16
);
14210 CVT_VAR (16, N_S16
, N_F32
| key
);
14211 CVT_VAR (17, N_U16
, N_F32
| key
);
14212 CVT_VAR (18, N_S16
, N_F64
| key
);
14213 CVT_VAR (19, N_U16
, N_F64
| key
);
14219 /* Neon-syntax VFP conversions. */
14222 do_vfp_nsyn_cvt (enum neon_shape rs
, int flavour
)
14224 const char *opname
= 0;
14226 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
)
14228 /* Conversions with immediate bitshift. */
14229 const char *enc
[] =
14253 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14255 opname
= enc
[flavour
];
14256 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14257 _("operands 0 and 1 must be the same register"));
14258 inst
.operands
[1] = inst
.operands
[2];
14259 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
14264 /* Conversions without bitshift. */
14265 const char *enc
[] =
14281 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
))
14282 opname
= enc
[flavour
];
14286 do_vfp_nsyn_opcode (opname
);
14290 do_vfp_nsyn_cvtz (void)
14292 enum neon_shape rs
= neon_select_shape (NS_FF
, NS_FD
, NS_NULL
);
14293 int flavour
= neon_cvt_flavour (rs
);
14294 const char *enc
[] =
14308 if (flavour
>= 0 && flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
14309 do_vfp_nsyn_opcode (enc
[flavour
]);
14313 do_neon_cvt_1 (bfd_boolean round_to_zero ATTRIBUTE_UNUSED
)
14315 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
14316 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
, NS_NULL
);
14317 int flavour
= neon_cvt_flavour (rs
);
14319 /* PR11109: Handle round-to-zero for VCVT conversions. */
14321 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
14322 && (flavour
== 0 || flavour
== 1 || flavour
== 8 || flavour
== 9)
14323 && (rs
== NS_FD
|| rs
== NS_FF
))
14325 do_vfp_nsyn_cvtz ();
14329 /* VFP rather than Neon conversions. */
14332 do_vfp_nsyn_cvt (rs
, flavour
);
14342 unsigned enctab
[] = { 0x0000100, 0x1000100, 0x0, 0x1000000 };
14344 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14347 /* Fixed-point conversion with #0 immediate is encoded as an
14348 integer conversion. */
14349 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
14351 immbits
= 32 - inst
.operands
[2].imm
;
14352 NEON_ENCODE (IMMED
, inst
);
14354 inst
.instruction
|= enctab
[flavour
];
14355 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14356 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14357 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14358 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14359 inst
.instruction
|= neon_quad (rs
) << 6;
14360 inst
.instruction
|= 1 << 21;
14361 inst
.instruction
|= immbits
<< 16;
14363 neon_dp_fixup (&inst
);
14371 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080 };
14373 NEON_ENCODE (INTEGER
, inst
);
14375 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14379 inst
.instruction
|= enctab
[flavour
];
14381 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14382 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14383 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14384 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14385 inst
.instruction
|= neon_quad (rs
) << 6;
14386 inst
.instruction
|= 2 << 18;
14388 neon_dp_fixup (&inst
);
14392 /* Half-precision conversions for Advanced SIMD -- neon. */
14397 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
14399 as_bad (_("operand size must match register width"));
14404 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
14406 as_bad (_("operand size must match register width"));
14411 inst
.instruction
= 0x3b60600;
14413 inst
.instruction
= 0x3b60700;
14415 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14416 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14417 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14418 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14419 neon_dp_fixup (&inst
);
14423 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
14424 do_vfp_nsyn_cvt (rs
, flavour
);
14429 do_neon_cvtr (void)
14431 do_neon_cvt_1 (FALSE
);
14437 do_neon_cvt_1 (TRUE
);
14441 do_neon_cvtb (void)
14443 inst
.instruction
= 0xeb20a40;
14445 /* The sizes are attached to the mnemonic. */
14446 if (inst
.vectype
.el
[0].type
!= NT_invtype
14447 && inst
.vectype
.el
[0].size
== 16)
14448 inst
.instruction
|= 0x00010000;
14450 /* Programmer's syntax: the sizes are attached to the operands. */
14451 else if (inst
.operands
[0].vectype
.type
!= NT_invtype
14452 && inst
.operands
[0].vectype
.size
== 16)
14453 inst
.instruction
|= 0x00010000;
14455 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
14456 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
14457 do_vfp_cond_or_thumb ();
14462 do_neon_cvtt (void)
14465 inst
.instruction
|= 0x80;
14469 neon_move_immediate (void)
14471 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
14472 struct neon_type_el et
= neon_check_type (2, rs
,
14473 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14474 unsigned immlo
, immhi
= 0, immbits
;
14475 int op
, cmode
, float_p
;
14477 constraint (et
.type
== NT_invtype
,
14478 _("operand size must be specified for immediate VMOV"));
14480 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
14481 op
= (inst
.instruction
& (1 << 5)) != 0;
14483 immlo
= inst
.operands
[1].imm
;
14484 if (inst
.operands
[1].regisimm
)
14485 immhi
= inst
.operands
[1].reg
;
14487 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
14488 _("immediate has bits set outside the operand size"));
14490 float_p
= inst
.operands
[1].immisfloat
;
14492 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
14493 et
.size
, et
.type
)) == FAIL
)
14495 /* Invert relevant bits only. */
14496 neon_invert_size (&immlo
, &immhi
, et
.size
);
14497 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
14498 with one or the other; those cases are caught by
14499 neon_cmode_for_move_imm. */
14501 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
14502 &op
, et
.size
, et
.type
)) == FAIL
)
14504 first_error (_("immediate out of range"));
14509 inst
.instruction
&= ~(1 << 5);
14510 inst
.instruction
|= op
<< 5;
14512 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14513 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14514 inst
.instruction
|= neon_quad (rs
) << 6;
14515 inst
.instruction
|= cmode
<< 8;
14517 neon_write_immbits (immbits
);
14523 if (inst
.operands
[1].isreg
)
14525 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14527 NEON_ENCODE (INTEGER
, inst
);
14528 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14529 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14530 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14531 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14532 inst
.instruction
|= neon_quad (rs
) << 6;
14536 NEON_ENCODE (IMMED
, inst
);
14537 neon_move_immediate ();
14540 neon_dp_fixup (&inst
);
14543 /* Encode instructions of form:
14545 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14546 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
14549 neon_mixed_length (struct neon_type_el et
, unsigned size
)
14551 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14552 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14553 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14554 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14555 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14556 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14557 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
14558 inst
.instruction
|= neon_logbits (size
) << 20;
14560 neon_dp_fixup (&inst
);
14564 do_neon_dyadic_long (void)
14566 /* FIXME: Type checking for lengthening op. */
14567 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14568 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14569 neon_mixed_length (et
, et
.size
);
14573 do_neon_abal (void)
14575 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14576 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
14577 neon_mixed_length (et
, et
.size
);
14581 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
14583 if (inst
.operands
[2].isscalar
)
14585 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
14586 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
14587 NEON_ENCODE (SCALAR
, inst
);
14588 neon_mul_mac (et
, et
.type
== NT_unsigned
);
14592 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14593 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
14594 NEON_ENCODE (INTEGER
, inst
);
14595 neon_mixed_length (et
, et
.size
);
14600 do_neon_mac_maybe_scalar_long (void)
14602 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
14606 do_neon_dyadic_wide (void)
14608 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
14609 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
14610 neon_mixed_length (et
, et
.size
);
14614 do_neon_dyadic_narrow (void)
14616 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14617 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
14618 /* Operand sign is unimportant, and the U bit is part of the opcode,
14619 so force the operand type to integer. */
14620 et
.type
= NT_integer
;
14621 neon_mixed_length (et
, et
.size
/ 2);
14625 do_neon_mul_sat_scalar_long (void)
14627 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
14631 do_neon_vmull (void)
14633 if (inst
.operands
[2].isscalar
)
14634 do_neon_mac_maybe_scalar_long ();
14637 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
14638 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_KEY
);
14639 if (et
.type
== NT_poly
)
14640 NEON_ENCODE (POLY
, inst
);
14642 NEON_ENCODE (INTEGER
, inst
);
14643 /* For polynomial encoding, size field must be 0b00 and the U bit must be
14644 zero. Should be OK as-is. */
14645 neon_mixed_length (et
, et
.size
);
14652 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
14653 struct neon_type_el et
= neon_check_type (3, rs
,
14654 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
14655 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
14657 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
14658 _("shift out of range"));
14659 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14660 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14661 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14662 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14663 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14664 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14665 inst
.instruction
|= neon_quad (rs
) << 6;
14666 inst
.instruction
|= imm
<< 8;
14668 neon_dp_fixup (&inst
);
14674 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
14675 struct neon_type_el et
= neon_check_type (2, rs
,
14676 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14677 unsigned op
= (inst
.instruction
>> 7) & 3;
14678 /* N (width of reversed regions) is encoded as part of the bitmask. We
14679 extract it here to check the elements to be reversed are smaller.
14680 Otherwise we'd get a reserved instruction. */
14681 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
14682 gas_assert (elsize
!= 0);
14683 constraint (et
.size
>= elsize
,
14684 _("elements must be smaller than reversal region"));
14685 neon_two_same (neon_quad (rs
), 1, et
.size
);
14691 if (inst
.operands
[1].isscalar
)
14693 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
14694 struct neon_type_el et
= neon_check_type (2, rs
,
14695 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
14696 unsigned sizebits
= et
.size
>> 3;
14697 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14698 int logsize
= neon_logbits (et
.size
);
14699 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
14701 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
14704 NEON_ENCODE (SCALAR
, inst
);
14705 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14706 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14707 inst
.instruction
|= LOW4 (dm
);
14708 inst
.instruction
|= HI1 (dm
) << 5;
14709 inst
.instruction
|= neon_quad (rs
) << 6;
14710 inst
.instruction
|= x
<< 17;
14711 inst
.instruction
|= sizebits
<< 16;
14713 neon_dp_fixup (&inst
);
14717 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
14718 struct neon_type_el et
= neon_check_type (2, rs
,
14719 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14720 /* Duplicate ARM register to lanes of vector. */
14721 NEON_ENCODE (ARMREG
, inst
);
14724 case 8: inst
.instruction
|= 0x400000; break;
14725 case 16: inst
.instruction
|= 0x000020; break;
14726 case 32: inst
.instruction
|= 0x000000; break;
14729 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
14730 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
14731 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
14732 inst
.instruction
|= neon_quad (rs
) << 21;
14733 /* The encoding for this instruction is identical for the ARM and Thumb
14734 variants, except for the condition field. */
14735 do_vfp_cond_or_thumb ();
14739 /* VMOV has particularly many variations. It can be one of:
14740 0. VMOV<c><q> <Qd>, <Qm>
14741 1. VMOV<c><q> <Dd>, <Dm>
14742 (Register operations, which are VORR with Rm = Rn.)
14743 2. VMOV<c><q>.<dt> <Qd>, #<imm>
14744 3. VMOV<c><q>.<dt> <Dd>, #<imm>
14746 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
14747 (ARM register to scalar.)
14748 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
14749 (Two ARM registers to vector.)
14750 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
14751 (Scalar to ARM register.)
14752 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
14753 (Vector to two ARM registers.)
14754 8. VMOV.F32 <Sd>, <Sm>
14755 9. VMOV.F64 <Dd>, <Dm>
14756 (VFP register moves.)
14757 10. VMOV.F32 <Sd>, #imm
14758 11. VMOV.F64 <Dd>, #imm
14759 (VFP float immediate load.)
14760 12. VMOV <Rd>, <Sm>
14761 (VFP single to ARM reg.)
14762 13. VMOV <Sd>, <Rm>
14763 (ARM reg to VFP single.)
14764 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
14765 (Two ARM regs to two VFP singles.)
14766 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
14767 (Two VFP singles to two ARM regs.)
14769 These cases can be disambiguated using neon_select_shape, except cases 1/9
14770 and 3/11 which depend on the operand type too.
14772 All the encoded bits are hardcoded by this function.
14774 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
14775 Cases 5, 7 may be used with VFPv2 and above.
14777 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
14778 can specify a type where it doesn't make sense to, and is ignored). */
14783 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
14784 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
14786 struct neon_type_el et
;
14787 const char *ldconst
= 0;
14791 case NS_DD
: /* case 1/9. */
14792 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14793 /* It is not an error here if no type is given. */
14795 if (et
.type
== NT_float
&& et
.size
== 64)
14797 do_vfp_nsyn_opcode ("fcpyd");
14800 /* fall through. */
14802 case NS_QQ
: /* case 0/1. */
14804 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14806 /* The architecture manual I have doesn't explicitly state which
14807 value the U bit should have for register->register moves, but
14808 the equivalent VORR instruction has U = 0, so do that. */
14809 inst
.instruction
= 0x0200110;
14810 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14811 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14812 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14813 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14814 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14815 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14816 inst
.instruction
|= neon_quad (rs
) << 6;
14818 neon_dp_fixup (&inst
);
14822 case NS_DI
: /* case 3/11. */
14823 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
14825 if (et
.type
== NT_float
&& et
.size
== 64)
14827 /* case 11 (fconstd). */
14828 ldconst
= "fconstd";
14829 goto encode_fconstd
;
14831 /* fall through. */
14833 case NS_QI
: /* case 2/3. */
14834 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
14836 inst
.instruction
= 0x0800010;
14837 neon_move_immediate ();
14838 neon_dp_fixup (&inst
);
14841 case NS_SR
: /* case 4. */
14843 unsigned bcdebits
= 0;
14845 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
14846 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
14848 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
14849 logsize
= neon_logbits (et
.size
);
14851 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14853 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14854 && et
.size
!= 32, _(BAD_FPU
));
14855 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14856 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14860 case 8: bcdebits
= 0x8; break;
14861 case 16: bcdebits
= 0x1; break;
14862 case 32: bcdebits
= 0x0; break;
14866 bcdebits
|= x
<< logsize
;
14868 inst
.instruction
= 0xe000b10;
14869 do_vfp_cond_or_thumb ();
14870 inst
.instruction
|= LOW4 (dn
) << 16;
14871 inst
.instruction
|= HI1 (dn
) << 7;
14872 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14873 inst
.instruction
|= (bcdebits
& 3) << 5;
14874 inst
.instruction
|= (bcdebits
>> 2) << 21;
14878 case NS_DRR
: /* case 5 (fmdrr). */
14879 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14882 inst
.instruction
= 0xc400b10;
14883 do_vfp_cond_or_thumb ();
14884 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
14885 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
14886 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14887 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14890 case NS_RS
: /* case 6. */
14893 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
14894 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
14895 unsigned abcdebits
= 0;
14897 et
= neon_check_type (2, NS_NULL
,
14898 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
14899 logsize
= neon_logbits (et
.size
);
14901 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
14903 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
14904 && et
.size
!= 32, _(BAD_FPU
));
14905 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
14906 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
14910 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
14911 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
14912 case 32: abcdebits
= 0x00; break;
14916 abcdebits
|= x
<< logsize
;
14917 inst
.instruction
= 0xe100b10;
14918 do_vfp_cond_or_thumb ();
14919 inst
.instruction
|= LOW4 (dn
) << 16;
14920 inst
.instruction
|= HI1 (dn
) << 7;
14921 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14922 inst
.instruction
|= (abcdebits
& 3) << 5;
14923 inst
.instruction
|= (abcdebits
>> 2) << 21;
14927 case NS_RRD
: /* case 7 (fmrrd). */
14928 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
14931 inst
.instruction
= 0xc500b10;
14932 do_vfp_cond_or_thumb ();
14933 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
14934 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14935 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14936 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14939 case NS_FF
: /* case 8 (fcpys). */
14940 do_vfp_nsyn_opcode ("fcpys");
14943 case NS_FI
: /* case 10 (fconsts). */
14944 ldconst
= "fconsts";
14946 if (is_quarter_float (inst
.operands
[1].imm
))
14948 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
14949 do_vfp_nsyn_opcode (ldconst
);
14952 first_error (_("immediate out of range"));
14955 case NS_RF
: /* case 12 (fmrs). */
14956 do_vfp_nsyn_opcode ("fmrs");
14959 case NS_FR
: /* case 13 (fmsr). */
14960 do_vfp_nsyn_opcode ("fmsr");
14963 /* The encoders for the fmrrs and fmsrr instructions expect three operands
14964 (one of which is a list), but we have parsed four. Do some fiddling to
14965 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
14967 case NS_RRFF
: /* case 14 (fmrrs). */
14968 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
14969 _("VFP registers must be adjacent"));
14970 inst
.operands
[2].imm
= 2;
14971 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14972 do_vfp_nsyn_opcode ("fmrrs");
14975 case NS_FFRR
: /* case 15 (fmsrr). */
14976 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
14977 _("VFP registers must be adjacent"));
14978 inst
.operands
[1] = inst
.operands
[2];
14979 inst
.operands
[2] = inst
.operands
[3];
14980 inst
.operands
[0].imm
= 2;
14981 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
14982 do_vfp_nsyn_opcode ("fmsrr");
14991 do_neon_rshift_round_imm (void)
14993 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14994 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14995 int imm
= inst
.operands
[2].imm
;
14997 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
15000 inst
.operands
[2].present
= 0;
15005 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15006 _("immediate out of range for shift"));
15007 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
15012 do_neon_movl (void)
15014 struct neon_type_el et
= neon_check_type (2, NS_QD
,
15015 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15016 unsigned sizebits
= et
.size
>> 3;
15017 inst
.instruction
|= sizebits
<< 19;
15018 neon_two_same (0, et
.type
== NT_unsigned
, -1);
15024 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15025 struct neon_type_el et
= neon_check_type (2, rs
,
15026 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15027 NEON_ENCODE (INTEGER
, inst
);
15028 neon_two_same (neon_quad (rs
), 1, et
.size
);
15032 do_neon_zip_uzp (void)
15034 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15035 struct neon_type_el et
= neon_check_type (2, rs
,
15036 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15037 if (rs
== NS_DD
&& et
.size
== 32)
15039 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
15040 inst
.instruction
= N_MNEM_vtrn
;
15044 neon_two_same (neon_quad (rs
), 1, et
.size
);
15048 do_neon_sat_abs_neg (void)
15050 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15051 struct neon_type_el et
= neon_check_type (2, rs
,
15052 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15053 neon_two_same (neon_quad (rs
), 1, et
.size
);
15057 do_neon_pair_long (void)
15059 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15060 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
15061 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
15062 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
15063 neon_two_same (neon_quad (rs
), 1, et
.size
);
15067 do_neon_recip_est (void)
15069 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15070 struct neon_type_el et
= neon_check_type (2, rs
,
15071 N_EQK
| N_FLT
, N_F32
| N_U32
| N_KEY
);
15072 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15073 neon_two_same (neon_quad (rs
), 1, et
.size
);
15079 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15080 struct neon_type_el et
= neon_check_type (2, rs
,
15081 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
15082 neon_two_same (neon_quad (rs
), 1, et
.size
);
15088 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15089 struct neon_type_el et
= neon_check_type (2, rs
,
15090 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
15091 neon_two_same (neon_quad (rs
), 1, et
.size
);
15097 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15098 struct neon_type_el et
= neon_check_type (2, rs
,
15099 N_EQK
| N_INT
, N_8
| N_KEY
);
15100 neon_two_same (neon_quad (rs
), 1, et
.size
);
15106 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15107 neon_two_same (neon_quad (rs
), 1, -1);
15111 do_neon_tbl_tbx (void)
15113 unsigned listlenbits
;
15114 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
15116 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
15118 first_error (_("bad list length for table lookup"));
15122 listlenbits
= inst
.operands
[1].imm
- 1;
15123 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15124 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15125 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15126 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15127 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15128 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15129 inst
.instruction
|= listlenbits
<< 8;
15131 neon_dp_fixup (&inst
);
15135 do_neon_ldm_stm (void)
15137 /* P, U and L bits are part of bitmask. */
15138 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
15139 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
15141 if (inst
.operands
[1].issingle
)
15143 do_vfp_nsyn_ldm_stm (is_dbmode
);
15147 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
15148 _("writeback (!) must be used for VLDMDB and VSTMDB"));
15150 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
15151 _("register list must contain at least 1 and at most 16 "
15154 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
15155 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
15156 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
15157 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
15159 inst
.instruction
|= offsetbits
;
15161 do_vfp_cond_or_thumb ();
15165 do_neon_ldr_str (void)
15167 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
15169 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
15170 And is UNPREDICTABLE in thumb mode. */
15172 && inst
.operands
[1].reg
== REG_PC
15173 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
15175 if (!thumb_mode
&& warn_on_deprecated
)
15176 as_warn (_("Use of PC here is deprecated"));
15178 inst
.error
= _("Use of PC here is UNPREDICTABLE");
15181 if (inst
.operands
[0].issingle
)
15184 do_vfp_nsyn_opcode ("flds");
15186 do_vfp_nsyn_opcode ("fsts");
15191 do_vfp_nsyn_opcode ("fldd");
15193 do_vfp_nsyn_opcode ("fstd");
15197 /* "interleave" version also handles non-interleaving register VLD1/VST1
15201 do_neon_ld_st_interleave (void)
15203 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
15204 N_8
| N_16
| N_32
| N_64
);
15205 unsigned alignbits
= 0;
15207 /* The bits in this table go:
15208 0: register stride of one (0) or two (1)
15209 1,2: register list length, minus one (1, 2, 3, 4).
15210 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
15211 We use -1 for invalid entries. */
15212 const int typetable
[] =
15214 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
15215 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
15216 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
15217 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
15221 if (et
.type
== NT_invtype
)
15224 if (inst
.operands
[1].immisalign
)
15225 switch (inst
.operands
[1].imm
>> 8)
15227 case 64: alignbits
= 1; break;
15229 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
15230 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15231 goto bad_alignment
;
15235 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
15236 goto bad_alignment
;
15241 first_error (_("bad alignment"));
15245 inst
.instruction
|= alignbits
<< 4;
15246 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15248 /* Bits [4:6] of the immediate in a list specifier encode register stride
15249 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
15250 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
15251 up the right value for "type" in a table based on this value and the given
15252 list style, then stick it back. */
15253 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
15254 | (((inst
.instruction
>> 8) & 3) << 3);
15256 typebits
= typetable
[idx
];
15258 constraint (typebits
== -1, _("bad list type for instruction"));
15260 inst
.instruction
&= ~0xf00;
15261 inst
.instruction
|= typebits
<< 8;
15264 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
15265 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
15266 otherwise. The variable arguments are a list of pairs of legal (size, align)
15267 values, terminated with -1. */
15270 neon_alignment_bit (int size
, int align
, int *do_align
, ...)
15273 int result
= FAIL
, thissize
, thisalign
;
15275 if (!inst
.operands
[1].immisalign
)
15281 va_start (ap
, do_align
);
15285 thissize
= va_arg (ap
, int);
15286 if (thissize
== -1)
15288 thisalign
= va_arg (ap
, int);
15290 if (size
== thissize
&& align
== thisalign
)
15293 while (result
!= SUCCESS
);
15297 if (result
== SUCCESS
)
15300 first_error (_("unsupported alignment for instruction"));
15306 do_neon_ld_st_lane (void)
15308 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15309 int align_good
, do_align
= 0;
15310 int logsize
= neon_logbits (et
.size
);
15311 int align
= inst
.operands
[1].imm
>> 8;
15312 int n
= (inst
.instruction
>> 8) & 3;
15313 int max_el
= 64 / et
.size
;
15315 if (et
.type
== NT_invtype
)
15318 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
15319 _("bad list length"));
15320 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
15321 _("scalar index out of range"));
15322 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
15324 _("stride of 2 unavailable when element size is 8"));
15328 case 0: /* VLD1 / VST1. */
15329 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 16, 16,
15331 if (align_good
== FAIL
)
15335 unsigned alignbits
= 0;
15338 case 16: alignbits
= 0x1; break;
15339 case 32: alignbits
= 0x3; break;
15342 inst
.instruction
|= alignbits
<< 4;
15346 case 1: /* VLD2 / VST2. */
15347 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 16, 16, 32,
15349 if (align_good
== FAIL
)
15352 inst
.instruction
|= 1 << 4;
15355 case 2: /* VLD3 / VST3. */
15356 constraint (inst
.operands
[1].immisalign
,
15357 _("can't use alignment with this instruction"));
15360 case 3: /* VLD4 / VST4. */
15361 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15362 16, 64, 32, 64, 32, 128, -1);
15363 if (align_good
== FAIL
)
15367 unsigned alignbits
= 0;
15370 case 8: alignbits
= 0x1; break;
15371 case 16: alignbits
= 0x1; break;
15372 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
15375 inst
.instruction
|= alignbits
<< 4;
15382 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
15383 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15384 inst
.instruction
|= 1 << (4 + logsize
);
15386 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
15387 inst
.instruction
|= logsize
<< 10;
15390 /* Encode single n-element structure to all lanes VLD<n> instructions. */
15393 do_neon_ld_dup (void)
15395 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
15396 int align_good
, do_align
= 0;
15398 if (et
.type
== NT_invtype
)
15401 switch ((inst
.instruction
>> 8) & 3)
15403 case 0: /* VLD1. */
15404 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
15405 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15406 &do_align
, 16, 16, 32, 32, -1);
15407 if (align_good
== FAIL
)
15409 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
15412 case 2: inst
.instruction
|= 1 << 5; break;
15413 default: first_error (_("bad list length")); return;
15415 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15418 case 1: /* VLD2. */
15419 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
15420 &do_align
, 8, 16, 16, 32, 32, 64, -1);
15421 if (align_good
== FAIL
)
15423 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
15424 _("bad list length"));
15425 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15426 inst
.instruction
|= 1 << 5;
15427 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15430 case 2: /* VLD3. */
15431 constraint (inst
.operands
[1].immisalign
,
15432 _("can't use alignment with this instruction"));
15433 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
15434 _("bad list length"));
15435 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15436 inst
.instruction
|= 1 << 5;
15437 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15440 case 3: /* VLD4. */
15442 int align
= inst
.operands
[1].imm
>> 8;
15443 align_good
= neon_alignment_bit (et
.size
, align
, &do_align
, 8, 32,
15444 16, 64, 32, 64, 32, 128, -1);
15445 if (align_good
== FAIL
)
15447 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
15448 _("bad list length"));
15449 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
15450 inst
.instruction
|= 1 << 5;
15451 if (et
.size
== 32 && align
== 128)
15452 inst
.instruction
|= 0x3 << 6;
15454 inst
.instruction
|= neon_logbits (et
.size
) << 6;
15461 inst
.instruction
|= do_align
<< 4;
15464 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
15465 apart from bits [11:4]. */
15468 do_neon_ldx_stx (void)
15470 if (inst
.operands
[1].isreg
)
15471 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
15473 switch (NEON_LANE (inst
.operands
[0].imm
))
15475 case NEON_INTERLEAVE_LANES
:
15476 NEON_ENCODE (INTERLV
, inst
);
15477 do_neon_ld_st_interleave ();
15480 case NEON_ALL_LANES
:
15481 NEON_ENCODE (DUP
, inst
);
15486 NEON_ENCODE (LANE
, inst
);
15487 do_neon_ld_st_lane ();
15490 /* L bit comes from bit mask. */
15491 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15492 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15493 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15495 if (inst
.operands
[1].postind
)
15497 int postreg
= inst
.operands
[1].imm
& 0xf;
15498 constraint (!inst
.operands
[1].immisreg
,
15499 _("post-index must be a register"));
15500 constraint (postreg
== 0xd || postreg
== 0xf,
15501 _("bad register for post-index"));
15502 inst
.instruction
|= postreg
;
15504 else if (inst
.operands
[1].writeback
)
15506 inst
.instruction
|= 0xd;
15509 inst
.instruction
|= 0xf;
15512 inst
.instruction
|= 0xf9000000;
15514 inst
.instruction
|= 0xf4000000;
15517 /* Overall per-instruction processing. */
15519 /* We need to be able to fix up arbitrary expressions in some statements.
15520 This is so that we can handle symbols that are an arbitrary distance from
15521 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
15522 which returns part of an address in a form which will be valid for
15523 a data instruction. We do this by pushing the expression into a symbol
15524 in the expr_section, and creating a fix for that. */
15527 fix_new_arm (fragS
* frag
,
15541 /* Create an absolute valued symbol, so we have something to
15542 refer to in the object file. Unfortunately for us, gas's
15543 generic expression parsing will already have folded out
15544 any use of .set foo/.type foo %function that may have
15545 been used to set type information of the target location,
15546 that's being specified symbolically. We have to presume
15547 the user knows what they are doing. */
15551 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
15553 symbol
= symbol_find_or_make (name
);
15554 S_SET_SEGMENT (symbol
, absolute_section
);
15555 symbol_set_frag (symbol
, &zero_address_frag
);
15556 S_SET_VALUE (symbol
, exp
->X_add_number
);
15557 exp
->X_op
= O_symbol
;
15558 exp
->X_add_symbol
= symbol
;
15559 exp
->X_add_number
= 0;
15565 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
15566 (enum bfd_reloc_code_real
) reloc
);
15570 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
15571 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
15575 /* Mark whether the fix is to a THUMB instruction, or an ARM
15577 new_fix
->tc_fix_data
= thumb_mode
;
15580 /* Create a frg for an instruction requiring relaxation. */
15582 output_relax_insn (void)
15588 /* The size of the instruction is unknown, so tie the debug info to the
15589 start of the instruction. */
15590 dwarf2_emit_insn (0);
15592 switch (inst
.reloc
.exp
.X_op
)
15595 sym
= inst
.reloc
.exp
.X_add_symbol
;
15596 offset
= inst
.reloc
.exp
.X_add_number
;
15600 offset
= inst
.reloc
.exp
.X_add_number
;
15603 sym
= make_expr_symbol (&inst
.reloc
.exp
);
15607 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
15608 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
15609 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
15612 /* Write a 32-bit thumb instruction to buf. */
15614 put_thumb32_insn (char * buf
, unsigned long insn
)
15616 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
15617 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
15621 output_inst (const char * str
)
15627 as_bad ("%s -- `%s'", inst
.error
, str
);
15632 output_relax_insn ();
15635 if (inst
.size
== 0)
15638 to
= frag_more (inst
.size
);
15639 /* PR 9814: Record the thumb mode into the current frag so that we know
15640 what type of NOP padding to use, if necessary. We override any previous
15641 setting so that if the mode has changed then the NOPS that we use will
15642 match the encoding of the last instruction in the frag. */
15643 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
15645 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
15647 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
15648 put_thumb32_insn (to
, inst
.instruction
);
15650 else if (inst
.size
> INSN_SIZE
)
15652 gas_assert (inst
.size
== (2 * INSN_SIZE
));
15653 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
15654 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
15657 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
15659 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
15660 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
15661 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
15664 dwarf2_emit_insn (inst
.size
);
15668 output_it_inst (int cond
, int mask
, char * to
)
15670 unsigned long instruction
= 0xbf00;
15673 instruction
|= mask
;
15674 instruction
|= cond
<< 4;
15678 to
= frag_more (2);
15680 dwarf2_emit_insn (2);
15684 md_number_to_chars (to
, instruction
, 2);
15689 /* Tag values used in struct asm_opcode's tag field. */
15692 OT_unconditional
, /* Instruction cannot be conditionalized.
15693 The ARM condition field is still 0xE. */
15694 OT_unconditionalF
, /* Instruction cannot be conditionalized
15695 and carries 0xF in its ARM condition field. */
15696 OT_csuffix
, /* Instruction takes a conditional suffix. */
15697 OT_csuffixF
, /* Some forms of the instruction take a conditional
15698 suffix, others place 0xF where the condition field
15700 OT_cinfix3
, /* Instruction takes a conditional infix,
15701 beginning at character index 3. (In
15702 unified mode, it becomes a suffix.) */
15703 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
15704 tsts, cmps, cmns, and teqs. */
15705 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
15706 character index 3, even in unified mode. Used for
15707 legacy instructions where suffix and infix forms
15708 may be ambiguous. */
15709 OT_csuf_or_in3
, /* Instruction takes either a conditional
15710 suffix or an infix at character index 3. */
15711 OT_odd_infix_unc
, /* This is the unconditional variant of an
15712 instruction that takes a conditional infix
15713 at an unusual position. In unified mode,
15714 this variant will accept a suffix. */
15715 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
15716 are the conditional variants of instructions that
15717 take conditional infixes in unusual positions.
15718 The infix appears at character index
15719 (tag - OT_odd_infix_0). These are not accepted
15720 in unified mode. */
15723 /* Subroutine of md_assemble, responsible for looking up the primary
15724 opcode from the mnemonic the user wrote. STR points to the
15725 beginning of the mnemonic.
15727 This is not simply a hash table lookup, because of conditional
15728 variants. Most instructions have conditional variants, which are
15729 expressed with a _conditional affix_ to the mnemonic. If we were
15730 to encode each conditional variant as a literal string in the opcode
15731 table, it would have approximately 20,000 entries.
15733 Most mnemonics take this affix as a suffix, and in unified syntax,
15734 'most' is upgraded to 'all'. However, in the divided syntax, some
15735 instructions take the affix as an infix, notably the s-variants of
15736 the arithmetic instructions. Of those instructions, all but six
15737 have the infix appear after the third character of the mnemonic.
15739 Accordingly, the algorithm for looking up primary opcodes given
15742 1. Look up the identifier in the opcode table.
15743 If we find a match, go to step U.
15745 2. Look up the last two characters of the identifier in the
15746 conditions table. If we find a match, look up the first N-2
15747 characters of the identifier in the opcode table. If we
15748 find a match, go to step CE.
15750 3. Look up the fourth and fifth characters of the identifier in
15751 the conditions table. If we find a match, extract those
15752 characters from the identifier, and look up the remaining
15753 characters in the opcode table. If we find a match, go
15758 U. Examine the tag field of the opcode structure, in case this is
15759 one of the six instructions with its conditional infix in an
15760 unusual place. If it is, the tag tells us where to find the
15761 infix; look it up in the conditions table and set inst.cond
15762 accordingly. Otherwise, this is an unconditional instruction.
15763 Again set inst.cond accordingly. Return the opcode structure.
15765 CE. Examine the tag field to make sure this is an instruction that
15766 should receive a conditional suffix. If it is not, fail.
15767 Otherwise, set inst.cond from the suffix we already looked up,
15768 and return the opcode structure.
15770 CM. Examine the tag field to make sure this is an instruction that
15771 should receive a conditional infix after the third character.
15772 If it is not, fail. Otherwise, undo the edits to the current
15773 line of input and proceed as for case CE. */
15775 static const struct asm_opcode
*
15776 opcode_lookup (char **str
)
15780 const struct asm_opcode
*opcode
;
15781 const struct asm_cond
*cond
;
15784 /* Scan up to the end of the mnemonic, which must end in white space,
15785 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
15786 for (base
= end
= *str
; *end
!= '\0'; end
++)
15787 if (*end
== ' ' || *end
== '.')
15793 /* Handle a possible width suffix and/or Neon type suffix. */
15798 /* The .w and .n suffixes are only valid if the unified syntax is in
15800 if (unified_syntax
&& end
[1] == 'w')
15802 else if (unified_syntax
&& end
[1] == 'n')
15807 inst
.vectype
.elems
= 0;
15809 *str
= end
+ offset
;
15811 if (end
[offset
] == '.')
15813 /* See if we have a Neon type suffix (possible in either unified or
15814 non-unified ARM syntax mode). */
15815 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
15818 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
15824 /* Look for unaffixed or special-case affixed mnemonic. */
15825 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15830 if (opcode
->tag
< OT_odd_infix_0
)
15832 inst
.cond
= COND_ALWAYS
;
15836 if (warn_on_deprecated
&& unified_syntax
)
15837 as_warn (_("conditional infixes are deprecated in unified syntax"));
15838 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
15839 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15842 inst
.cond
= cond
->value
;
15846 /* Cannot have a conditional suffix on a mnemonic of less than two
15848 if (end
- base
< 3)
15851 /* Look for suffixed mnemonic. */
15853 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15854 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15856 if (opcode
&& cond
)
15859 switch (opcode
->tag
)
15861 case OT_cinfix3_legacy
:
15862 /* Ignore conditional suffixes matched on infix only mnemonics. */
15866 case OT_cinfix3_deprecated
:
15867 case OT_odd_infix_unc
:
15868 if (!unified_syntax
)
15870 /* else fall through */
15874 case OT_csuf_or_in3
:
15875 inst
.cond
= cond
->value
;
15878 case OT_unconditional
:
15879 case OT_unconditionalF
:
15881 inst
.cond
= cond
->value
;
15884 /* Delayed diagnostic. */
15885 inst
.error
= BAD_COND
;
15886 inst
.cond
= COND_ALWAYS
;
15895 /* Cannot have a usual-position infix on a mnemonic of less than
15896 six characters (five would be a suffix). */
15897 if (end
- base
< 6)
15900 /* Look for infixed mnemonic in the usual position. */
15902 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
15906 memcpy (save
, affix
, 2);
15907 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
15908 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
15910 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
15911 memcpy (affix
, save
, 2);
15914 && (opcode
->tag
== OT_cinfix3
15915 || opcode
->tag
== OT_cinfix3_deprecated
15916 || opcode
->tag
== OT_csuf_or_in3
15917 || opcode
->tag
== OT_cinfix3_legacy
))
15920 if (warn_on_deprecated
&& unified_syntax
15921 && (opcode
->tag
== OT_cinfix3
15922 || opcode
->tag
== OT_cinfix3_deprecated
))
15923 as_warn (_("conditional infixes are deprecated in unified syntax"));
15925 inst
.cond
= cond
->value
;
15932 /* This function generates an initial IT instruction, leaving its block
15933 virtually open for the new instructions. Eventually,
15934 the mask will be updated by now_it_add_mask () each time
15935 a new instruction needs to be included in the IT block.
15936 Finally, the block is closed with close_automatic_it_block ().
15937 The block closure can be requested either from md_assemble (),
15938 a tencode (), or due to a label hook. */
15941 new_automatic_it_block (int cond
)
15943 now_it
.state
= AUTOMATIC_IT_BLOCK
;
15944 now_it
.mask
= 0x18;
15946 now_it
.block_length
= 1;
15947 mapping_state (MAP_THUMB
);
15948 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
15951 /* Close an automatic IT block.
15952 See comments in new_automatic_it_block (). */
15955 close_automatic_it_block (void)
15957 now_it
.mask
= 0x10;
15958 now_it
.block_length
= 0;
15961 /* Update the mask of the current automatically-generated IT
15962 instruction. See comments in new_automatic_it_block (). */
15965 now_it_add_mask (int cond
)
15967 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
15968 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
15969 | ((bitvalue) << (nbit)))
15970 const int resulting_bit
= (cond
& 1);
15972 now_it
.mask
&= 0xf;
15973 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15975 (5 - now_it
.block_length
));
15976 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
15978 ((5 - now_it
.block_length
) - 1) );
15979 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
15982 #undef SET_BIT_VALUE
15985 /* The IT blocks handling machinery is accessed through the these functions:
15986 it_fsm_pre_encode () from md_assemble ()
15987 set_it_insn_type () optional, from the tencode functions
15988 set_it_insn_type_last () ditto
15989 in_it_block () ditto
15990 it_fsm_post_encode () from md_assemble ()
15991 force_automatic_it_block_close () from label habdling functions
15994 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
15995 initializing the IT insn type with a generic initial value depending
15996 on the inst.condition.
15997 2) During the tencode function, two things may happen:
15998 a) The tencode function overrides the IT insn type by
15999 calling either set_it_insn_type (type) or set_it_insn_type_last ().
16000 b) The tencode function queries the IT block state by
16001 calling in_it_block () (i.e. to determine narrow/not narrow mode).
16003 Both set_it_insn_type and in_it_block run the internal FSM state
16004 handling function (handle_it_state), because: a) setting the IT insn
16005 type may incur in an invalid state (exiting the function),
16006 and b) querying the state requires the FSM to be updated.
16007 Specifically we want to avoid creating an IT block for conditional
16008 branches, so it_fsm_pre_encode is actually a guess and we can't
16009 determine whether an IT block is required until the tencode () routine
16010 has decided what type of instruction this actually it.
16011 Because of this, if set_it_insn_type and in_it_block have to be used,
16012 set_it_insn_type has to be called first.
16014 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
16015 determines the insn IT type depending on the inst.cond code.
16016 When a tencode () routine encodes an instruction that can be
16017 either outside an IT block, or, in the case of being inside, has to be
16018 the last one, set_it_insn_type_last () will determine the proper
16019 IT instruction type based on the inst.cond code. Otherwise,
16020 set_it_insn_type can be called for overriding that logic or
16021 for covering other cases.
16023 Calling handle_it_state () may not transition the IT block state to
16024 OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
16025 still queried. Instead, if the FSM determines that the state should
16026 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
16027 after the tencode () function: that's what it_fsm_post_encode () does.
16029 Since in_it_block () calls the state handling function to get an
16030 updated state, an error may occur (due to invalid insns combination).
16031 In that case, inst.error is set.
16032 Therefore, inst.error has to be checked after the execution of
16033 the tencode () routine.
16035 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
16036 any pending state change (if any) that didn't take place in
16037 handle_it_state () as explained above. */
16040 it_fsm_pre_encode (void)
16042 if (inst
.cond
!= COND_ALWAYS
)
16043 inst
.it_insn_type
= INSIDE_IT_INSN
;
16045 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
16047 now_it
.state_handled
= 0;
16050 /* IT state FSM handling function. */
16053 handle_it_state (void)
16055 now_it
.state_handled
= 1;
16057 switch (now_it
.state
)
16059 case OUTSIDE_IT_BLOCK
:
16060 switch (inst
.it_insn_type
)
16062 case OUTSIDE_IT_INSN
:
16065 case INSIDE_IT_INSN
:
16066 case INSIDE_IT_LAST_INSN
:
16067 if (thumb_mode
== 0)
16070 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
16071 as_tsktsk (_("Warning: conditional outside an IT block"\
16076 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
16077 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
))
16079 /* Automatically generate the IT instruction. */
16080 new_automatic_it_block (inst
.cond
);
16081 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
16082 close_automatic_it_block ();
16086 inst
.error
= BAD_OUT_IT
;
16092 case IF_INSIDE_IT_LAST_INSN
:
16093 case NEUTRAL_IT_INSN
:
16097 now_it
.state
= MANUAL_IT_BLOCK
;
16098 now_it
.block_length
= 0;
16103 case AUTOMATIC_IT_BLOCK
:
16104 /* Three things may happen now:
16105 a) We should increment current it block size;
16106 b) We should close current it block (closing insn or 4 insns);
16107 c) We should close current it block and start a new one (due
16108 to incompatible conditions or
16109 4 insns-length block reached). */
16111 switch (inst
.it_insn_type
)
16113 case OUTSIDE_IT_INSN
:
16114 /* The closure of the block shall happen immediatelly,
16115 so any in_it_block () call reports the block as closed. */
16116 force_automatic_it_block_close ();
16119 case INSIDE_IT_INSN
:
16120 case INSIDE_IT_LAST_INSN
:
16121 case IF_INSIDE_IT_LAST_INSN
:
16122 now_it
.block_length
++;
16124 if (now_it
.block_length
> 4
16125 || !now_it_compatible (inst
.cond
))
16127 force_automatic_it_block_close ();
16128 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
16129 new_automatic_it_block (inst
.cond
);
16133 now_it_add_mask (inst
.cond
);
16136 if (now_it
.state
== AUTOMATIC_IT_BLOCK
16137 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
16138 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
16139 close_automatic_it_block ();
16142 case NEUTRAL_IT_INSN
:
16143 now_it
.block_length
++;
16145 if (now_it
.block_length
> 4)
16146 force_automatic_it_block_close ();
16148 now_it_add_mask (now_it
.cc
& 1);
16152 close_automatic_it_block ();
16153 now_it
.state
= MANUAL_IT_BLOCK
;
16158 case MANUAL_IT_BLOCK
:
16160 /* Check conditional suffixes. */
16161 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
16164 now_it
.mask
&= 0x1f;
16165 is_last
= (now_it
.mask
== 0x10);
16167 switch (inst
.it_insn_type
)
16169 case OUTSIDE_IT_INSN
:
16170 inst
.error
= BAD_NOT_IT
;
16173 case INSIDE_IT_INSN
:
16174 if (cond
!= inst
.cond
)
16176 inst
.error
= BAD_IT_COND
;
16181 case INSIDE_IT_LAST_INSN
:
16182 case IF_INSIDE_IT_LAST_INSN
:
16183 if (cond
!= inst
.cond
)
16185 inst
.error
= BAD_IT_COND
;
16190 inst
.error
= BAD_BRANCH
;
16195 case NEUTRAL_IT_INSN
:
16196 /* The BKPT instruction is unconditional even in an IT block. */
16200 inst
.error
= BAD_IT_IT
;
16211 it_fsm_post_encode (void)
16215 if (!now_it
.state_handled
)
16216 handle_it_state ();
16218 is_last
= (now_it
.mask
== 0x10);
16221 now_it
.state
= OUTSIDE_IT_BLOCK
;
16227 force_automatic_it_block_close (void)
16229 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
16231 close_automatic_it_block ();
16232 now_it
.state
= OUTSIDE_IT_BLOCK
;
16240 if (!now_it
.state_handled
)
16241 handle_it_state ();
16243 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
16247 md_assemble (char *str
)
16250 const struct asm_opcode
* opcode
;
16252 /* Align the previous label if needed. */
16253 if (last_label_seen
!= NULL
)
16255 symbol_set_frag (last_label_seen
, frag_now
);
16256 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
16257 S_SET_SEGMENT (last_label_seen
, now_seg
);
16260 memset (&inst
, '\0', sizeof (inst
));
16261 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
16263 opcode
= opcode_lookup (&p
);
16266 /* It wasn't an instruction, but it might be a register alias of
16267 the form alias .req reg, or a Neon .dn/.qn directive. */
16268 if (! create_register_alias (str
, p
)
16269 && ! create_neon_reg_alias (str
, p
))
16270 as_bad (_("bad instruction `%s'"), str
);
16275 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
16276 as_warn (_("s suffix on comparison instruction is deprecated"));
16278 /* The value which unconditional instructions should have in place of the
16279 condition field. */
16280 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
16284 arm_feature_set variant
;
16286 variant
= cpu_variant
;
16287 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
16288 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
16289 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
16290 /* Check that this instruction is supported for this CPU. */
16291 if (!opcode
->tvariant
16292 || (thumb_mode
== 1
16293 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
16295 as_bad (_("selected processor does not support Thumb mode `%s'"), str
);
16298 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
16299 && opcode
->tencode
!= do_t_branch
)
16301 as_bad (_("Thumb does not support conditional execution"));
16305 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
))
16307 if (opcode
->tencode
!= do_t_blx
&& opcode
->tencode
!= do_t_branch23
16308 && !(ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_msr
)
16309 || ARM_CPU_HAS_FEATURE(*opcode
->tvariant
, arm_ext_barrier
)))
16311 /* Two things are addressed here.
16312 1) Implicit require narrow instructions on Thumb-1.
16313 This avoids relaxation accidentally introducing Thumb-2
16315 2) Reject wide instructions in non Thumb-2 cores. */
16316 if (inst
.size_req
== 0)
16318 else if (inst
.size_req
== 4)
16320 as_bad (_("selected processor does not support Thumb-2 mode `%s'"), str
);
16326 inst
.instruction
= opcode
->tvalue
;
16328 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
16330 /* Prepare the it_insn_type for those encodings that don't set
16332 it_fsm_pre_encode ();
16334 opcode
->tencode ();
16336 it_fsm_post_encode ();
16339 if (!(inst
.error
|| inst
.relax
))
16341 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
16342 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
16343 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
16345 as_bad (_("cannot honor width suffix -- `%s'"), str
);
16350 /* Something has gone badly wrong if we try to relax a fixed size
16352 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
16354 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16355 *opcode
->tvariant
);
16356 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
16357 set those bits when Thumb-2 32-bit instructions are seen. ie.
16358 anything other than bl/blx and v6-M instructions.
16359 This is overly pessimistic for relaxable instructions. */
16360 if (((inst
.size
== 4 && (inst
.instruction
& 0xf800e800) != 0xf000e800)
16362 && !(ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
16363 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
)))
16364 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
16367 check_neon_suffixes
;
16371 mapping_state (MAP_THUMB
);
16374 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
16378 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
16379 is_bx
= (opcode
->aencode
== do_bx
);
16381 /* Check that this instruction is supported for this CPU. */
16382 if (!(is_bx
&& fix_v4bx
)
16383 && !(opcode
->avariant
&&
16384 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
16386 as_bad (_("selected processor does not support ARM mode `%s'"), str
);
16391 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
16395 inst
.instruction
= opcode
->avalue
;
16396 if (opcode
->tag
== OT_unconditionalF
)
16397 inst
.instruction
|= 0xF << 28;
16399 inst
.instruction
|= inst
.cond
<< 28;
16400 inst
.size
= INSN_SIZE
;
16401 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
16403 it_fsm_pre_encode ();
16404 opcode
->aencode ();
16405 it_fsm_post_encode ();
16407 /* Arm mode bx is marked as both v4T and v5 because it's still required
16408 on a hypothetical non-thumb v5 core. */
16410 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
16412 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
16413 *opcode
->avariant
);
16415 check_neon_suffixes
;
16419 mapping_state (MAP_ARM
);
16424 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
16432 check_it_blocks_finished (void)
16437 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
16438 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
16439 == MANUAL_IT_BLOCK
)
16441 as_warn (_("section '%s' finished with an open IT block."),
16445 if (now_it
.state
== MANUAL_IT_BLOCK
)
16446 as_warn (_("file finished with an open IT block."));
16450 /* Various frobbings of labels and their addresses. */
16453 arm_start_line_hook (void)
16455 last_label_seen
= NULL
;
16459 arm_frob_label (symbolS
* sym
)
16461 last_label_seen
= sym
;
16463 ARM_SET_THUMB (sym
, thumb_mode
);
16465 #if defined OBJ_COFF || defined OBJ_ELF
16466 ARM_SET_INTERWORK (sym
, support_interwork
);
16469 force_automatic_it_block_close ();
16471 /* Note - do not allow local symbols (.Lxxx) to be labelled
16472 as Thumb functions. This is because these labels, whilst
16473 they exist inside Thumb code, are not the entry points for
16474 possible ARM->Thumb calls. Also, these labels can be used
16475 as part of a computed goto or switch statement. eg gcc
16476 can generate code that looks like this:
16478 ldr r2, [pc, .Laaa]
16488 The first instruction loads the address of the jump table.
16489 The second instruction converts a table index into a byte offset.
16490 The third instruction gets the jump address out of the table.
16491 The fourth instruction performs the jump.
16493 If the address stored at .Laaa is that of a symbol which has the
16494 Thumb_Func bit set, then the linker will arrange for this address
16495 to have the bottom bit set, which in turn would mean that the
16496 address computation performed by the third instruction would end
16497 up with the bottom bit set. Since the ARM is capable of unaligned
16498 word loads, the instruction would then load the incorrect address
16499 out of the jump table, and chaos would ensue. */
16500 if (label_is_thumb_function_name
16501 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
16502 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
16504 /* When the address of a Thumb function is taken the bottom
16505 bit of that address should be set. This will allow
16506 interworking between Arm and Thumb functions to work
16509 THUMB_SET_FUNC (sym
, 1);
16511 label_is_thumb_function_name
= FALSE
;
16514 dwarf2_emit_label (sym
);
16518 arm_data_in_code (void)
16520 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
16522 *input_line_pointer
= '/';
16523 input_line_pointer
+= 5;
16524 *input_line_pointer
= 0;
16532 arm_canonicalize_symbol_name (char * name
)
16536 if (thumb_mode
&& (len
= strlen (name
)) > 5
16537 && streq (name
+ len
- 5, "/data"))
16538 *(name
+ len
- 5) = 0;
16543 /* Table of all register names defined by default. The user can
16544 define additional names with .req. Note that all register names
16545 should appear in both upper and lowercase variants. Some registers
16546 also have mixed-case names. */
16548 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
16549 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
16550 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
16551 #define REGSET(p,t) \
16552 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
16553 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
16554 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
16555 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
16556 #define REGSETH(p,t) \
16557 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
16558 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
16559 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
16560 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
16561 #define REGSET2(p,t) \
16562 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
16563 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
16564 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
16565 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
16566 #define SPLRBANK(base,bank,t) \
16567 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
16568 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
16569 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
16570 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
16571 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
16572 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
16574 static const struct reg_entry reg_names
[] =
16576 /* ARM integer registers. */
16577 REGSET(r
, RN
), REGSET(R
, RN
),
16579 /* ATPCS synonyms. */
16580 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
16581 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
16582 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
16584 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
16585 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
16586 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
16588 /* Well-known aliases. */
16589 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
16590 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
16592 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
16593 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
16595 /* Coprocessor numbers. */
16596 REGSET(p
, CP
), REGSET(P
, CP
),
16598 /* Coprocessor register numbers. The "cr" variants are for backward
16600 REGSET(c
, CN
), REGSET(C
, CN
),
16601 REGSET(cr
, CN
), REGSET(CR
, CN
),
16603 /* ARM banked registers. */
16604 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
16605 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
16606 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
16607 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
16608 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
16609 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
16610 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
16612 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
16613 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
16614 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
16615 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
16616 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
16617 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(SP_fiq
,512|(13<<16),RNB
),
16618 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
16619 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
16621 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
16622 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
16623 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
16624 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
16625 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
16626 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
16627 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
16628 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16629 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
16631 /* FPA registers. */
16632 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
16633 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
16635 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
16636 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
16638 /* VFP SP registers. */
16639 REGSET(s
,VFS
), REGSET(S
,VFS
),
16640 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
16642 /* VFP DP Registers. */
16643 REGSET(d
,VFD
), REGSET(D
,VFD
),
16644 /* Extra Neon DP registers. */
16645 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
16647 /* Neon QP registers. */
16648 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
16650 /* VFP control registers. */
16651 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
16652 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
16653 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
16654 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
16655 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
16656 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
16658 /* Maverick DSP coprocessor registers. */
16659 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
16660 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
16662 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
16663 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
16664 REGDEF(dspsc
,0,DSPSC
),
16666 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
16667 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
16668 REGDEF(DSPSC
,0,DSPSC
),
16670 /* iWMMXt data registers - p0, c0-15. */
16671 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
16673 /* iWMMXt control registers - p1, c0-3. */
16674 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
16675 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
16676 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
16677 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
16679 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
16680 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
16681 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
16682 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
16683 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
16685 /* XScale accumulator registers. */
16686 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
16692 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
16693 within psr_required_here. */
16694 static const struct asm_psr psrs
[] =
16696 /* Backward compatibility notation. Note that "all" is no longer
16697 truly all possible PSR bits. */
16698 {"all", PSR_c
| PSR_f
},
16702 /* Individual flags. */
16708 /* Combinations of flags. */
16709 {"fs", PSR_f
| PSR_s
},
16710 {"fx", PSR_f
| PSR_x
},
16711 {"fc", PSR_f
| PSR_c
},
16712 {"sf", PSR_s
| PSR_f
},
16713 {"sx", PSR_s
| PSR_x
},
16714 {"sc", PSR_s
| PSR_c
},
16715 {"xf", PSR_x
| PSR_f
},
16716 {"xs", PSR_x
| PSR_s
},
16717 {"xc", PSR_x
| PSR_c
},
16718 {"cf", PSR_c
| PSR_f
},
16719 {"cs", PSR_c
| PSR_s
},
16720 {"cx", PSR_c
| PSR_x
},
16721 {"fsx", PSR_f
| PSR_s
| PSR_x
},
16722 {"fsc", PSR_f
| PSR_s
| PSR_c
},
16723 {"fxs", PSR_f
| PSR_x
| PSR_s
},
16724 {"fxc", PSR_f
| PSR_x
| PSR_c
},
16725 {"fcs", PSR_f
| PSR_c
| PSR_s
},
16726 {"fcx", PSR_f
| PSR_c
| PSR_x
},
16727 {"sfx", PSR_s
| PSR_f
| PSR_x
},
16728 {"sfc", PSR_s
| PSR_f
| PSR_c
},
16729 {"sxf", PSR_s
| PSR_x
| PSR_f
},
16730 {"sxc", PSR_s
| PSR_x
| PSR_c
},
16731 {"scf", PSR_s
| PSR_c
| PSR_f
},
16732 {"scx", PSR_s
| PSR_c
| PSR_x
},
16733 {"xfs", PSR_x
| PSR_f
| PSR_s
},
16734 {"xfc", PSR_x
| PSR_f
| PSR_c
},
16735 {"xsf", PSR_x
| PSR_s
| PSR_f
},
16736 {"xsc", PSR_x
| PSR_s
| PSR_c
},
16737 {"xcf", PSR_x
| PSR_c
| PSR_f
},
16738 {"xcs", PSR_x
| PSR_c
| PSR_s
},
16739 {"cfs", PSR_c
| PSR_f
| PSR_s
},
16740 {"cfx", PSR_c
| PSR_f
| PSR_x
},
16741 {"csf", PSR_c
| PSR_s
| PSR_f
},
16742 {"csx", PSR_c
| PSR_s
| PSR_x
},
16743 {"cxf", PSR_c
| PSR_x
| PSR_f
},
16744 {"cxs", PSR_c
| PSR_x
| PSR_s
},
16745 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
16746 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
16747 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
16748 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
16749 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
16750 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
16751 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
16752 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
16753 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
16754 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
16755 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
16756 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
16757 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
16758 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
16759 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
16760 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
16761 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
16762 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
16763 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
16764 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
16765 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
16766 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
16767 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
16768 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
16771 /* Table of V7M psr names. */
16772 static const struct asm_psr v7m_psrs
[] =
16774 {"apsr", 0 }, {"APSR", 0 },
16775 {"iapsr", 1 }, {"IAPSR", 1 },
16776 {"eapsr", 2 }, {"EAPSR", 2 },
16777 {"psr", 3 }, {"PSR", 3 },
16778 {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
16779 {"ipsr", 5 }, {"IPSR", 5 },
16780 {"epsr", 6 }, {"EPSR", 6 },
16781 {"iepsr", 7 }, {"IEPSR", 7 },
16782 {"msp", 8 }, {"MSP", 8 },
16783 {"psp", 9 }, {"PSP", 9 },
16784 {"primask", 16}, {"PRIMASK", 16},
16785 {"basepri", 17}, {"BASEPRI", 17},
16786 {"basepri_max", 18}, {"BASEPRI_MAX", 18},
16787 {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
16788 {"faultmask", 19}, {"FAULTMASK", 19},
16789 {"control", 20}, {"CONTROL", 20}
16792 /* Table of all shift-in-operand names. */
16793 static const struct asm_shift_name shift_names
[] =
16795 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
16796 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
16797 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
16798 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
16799 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
16800 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
16803 /* Table of all explicit relocation names. */
16805 static struct reloc_entry reloc_names
[] =
16807 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
16808 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
16809 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
16810 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
16811 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
16812 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
16813 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
16814 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
16815 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
16816 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
16817 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
16818 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
16819 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
16820 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
16821 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
16822 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
16823 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
16824 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
16828 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
16829 static const struct asm_cond conds
[] =
16833 {"cs", 0x2}, {"hs", 0x2},
16834 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
16848 static struct asm_barrier_opt barrier_opt_names
[] =
16850 { "sy", 0xf }, { "SY", 0xf },
16851 { "un", 0x7 }, { "UN", 0x7 },
16852 { "st", 0xe }, { "ST", 0xe },
16853 { "unst", 0x6 }, { "UNST", 0x6 },
16854 { "ish", 0xb }, { "ISH", 0xb },
16855 { "sh", 0xb }, { "SH", 0xb },
16856 { "ishst", 0xa }, { "ISHST", 0xa },
16857 { "shst", 0xa }, { "SHST", 0xa },
16858 { "nsh", 0x7 }, { "NSH", 0x7 },
16859 { "nshst", 0x6 }, { "NSHST", 0x6 },
16860 { "osh", 0x3 }, { "OSH", 0x3 },
16861 { "oshst", 0x2 }, { "OSHST", 0x2 }
16864 /* Table of ARM-format instructions. */
16866 /* Macros for gluing together operand strings. N.B. In all cases
16867 other than OPS0, the trailing OP_stop comes from default
16868 zero-initialization of the unspecified elements of the array. */
16869 #define OPS0() { OP_stop, }
16870 #define OPS1(a) { OP_##a, }
16871 #define OPS2(a,b) { OP_##a,OP_##b, }
16872 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
16873 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
16874 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
16875 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
16877 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
16878 This is useful when mixing operands for ARM and THUMB, i.e. using the
16879 MIX_ARM_THUMB_OPERANDS macro.
16880 In order to use these macros, prefix the number of operands with _
16882 #define OPS_1(a) { a, }
16883 #define OPS_2(a,b) { a,b, }
16884 #define OPS_3(a,b,c) { a,b,c, }
16885 #define OPS_4(a,b,c,d) { a,b,c,d, }
16886 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
16887 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
16889 /* These macros abstract out the exact format of the mnemonic table and
16890 save some repeated characters. */
16892 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
16893 #define TxCE(mnem, op, top, nops, ops, ae, te) \
16894 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
16895 THUMB_VARIANT, do_##ae, do_##te }
16897 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
16898 a T_MNEM_xyz enumerator. */
16899 #define TCE(mnem, aop, top, nops, ops, ae, te) \
16900 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
16901 #define tCE(mnem, aop, top, nops, ops, ae, te) \
16902 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16904 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
16905 infix after the third character. */
16906 #define TxC3(mnem, op, top, nops, ops, ae, te) \
16907 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
16908 THUMB_VARIANT, do_##ae, do_##te }
16909 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
16910 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
16911 THUMB_VARIANT, do_##ae, do_##te }
16912 #define TC3(mnem, aop, top, nops, ops, ae, te) \
16913 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
16914 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
16915 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
16916 #define tC3(mnem, aop, top, nops, ops, ae, te) \
16917 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16918 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
16919 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
16921 /* Mnemonic with a conditional infix in an unusual place. Each and every variant has to
16922 appear in the condition table. */
16923 #define TxCM_(m1, m2, m3, op, top, nops, ops, ae, te) \
16924 { m1 #m2 m3, OPS##nops ops, sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16925 0x##op, top, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##te }
16927 #define TxCM(m1, m2, op, top, nops, ops, ae, te) \
16928 TxCM_ (m1, , m2, op, top, nops, ops, ae, te), \
16929 TxCM_ (m1, eq, m2, op, top, nops, ops, ae, te), \
16930 TxCM_ (m1, ne, m2, op, top, nops, ops, ae, te), \
16931 TxCM_ (m1, cs, m2, op, top, nops, ops, ae, te), \
16932 TxCM_ (m1, hs, m2, op, top, nops, ops, ae, te), \
16933 TxCM_ (m1, cc, m2, op, top, nops, ops, ae, te), \
16934 TxCM_ (m1, ul, m2, op, top, nops, ops, ae, te), \
16935 TxCM_ (m1, lo, m2, op, top, nops, ops, ae, te), \
16936 TxCM_ (m1, mi, m2, op, top, nops, ops, ae, te), \
16937 TxCM_ (m1, pl, m2, op, top, nops, ops, ae, te), \
16938 TxCM_ (m1, vs, m2, op, top, nops, ops, ae, te), \
16939 TxCM_ (m1, vc, m2, op, top, nops, ops, ae, te), \
16940 TxCM_ (m1, hi, m2, op, top, nops, ops, ae, te), \
16941 TxCM_ (m1, ls, m2, op, top, nops, ops, ae, te), \
16942 TxCM_ (m1, ge, m2, op, top, nops, ops, ae, te), \
16943 TxCM_ (m1, lt, m2, op, top, nops, ops, ae, te), \
16944 TxCM_ (m1, gt, m2, op, top, nops, ops, ae, te), \
16945 TxCM_ (m1, le, m2, op, top, nops, ops, ae, te), \
16946 TxCM_ (m1, al, m2, op, top, nops, ops, ae, te)
16948 #define TCM(m1,m2, aop, top, nops, ops, ae, te) \
16949 TxCM (m1,m2, aop, 0x##top, nops, ops, ae, te)
16950 #define tCM(m1,m2, aop, top, nops, ops, ae, te) \
16951 TxCM (m1,m2, aop, T_MNEM##top, nops, ops, ae, te)
16953 /* Mnemonic that cannot be conditionalized. The ARM condition-code
16954 field is still 0xE. Many of the Thumb variants can be executed
16955 conditionally, so this is checked separately. */
16956 #define TUE(mnem, op, top, nops, ops, ae, te) \
16957 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
16958 THUMB_VARIANT, do_##ae, do_##te }
16960 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
16961 condition code field. */
16962 #define TUF(mnem, op, top, nops, ops, ae, te) \
16963 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
16964 THUMB_VARIANT, do_##ae, do_##te }
16966 /* ARM-only variants of all the above. */
16967 #define CE(mnem, op, nops, ops, ae) \
16968 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16970 #define C3(mnem, op, nops, ops, ae) \
16971 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16973 /* Legacy mnemonics that always have conditional infix after the third
16975 #define CL(mnem, op, nops, ops, ae) \
16976 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16977 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
16979 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
16980 #define cCE(mnem, op, nops, ops, ae) \
16981 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16983 /* Legacy coprocessor instructions where conditional infix and conditional
16984 suffix are ambiguous. For consistency this includes all FPA instructions,
16985 not just the potentially ambiguous ones. */
16986 #define cCL(mnem, op, nops, ops, ae) \
16987 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
16988 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16990 /* Coprocessor, takes either a suffix or a position-3 infix
16991 (for an FPA corner case). */
16992 #define C3E(mnem, op, nops, ops, ae) \
16993 { mnem, OPS##nops ops, OT_csuf_or_in3, \
16994 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
16996 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
16997 { m1 #m2 m3, OPS##nops ops, \
16998 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
16999 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
17001 #define CM(m1, m2, op, nops, ops, ae) \
17002 xCM_ (m1, , m2, op, nops, ops, ae), \
17003 xCM_ (m1, eq, m2, op, nops, ops, ae), \
17004 xCM_ (m1, ne, m2, op, nops, ops, ae), \
17005 xCM_ (m1, cs, m2, op, nops, ops, ae), \
17006 xCM_ (m1, hs, m2, op, nops, ops, ae), \
17007 xCM_ (m1, cc, m2, op, nops, ops, ae), \
17008 xCM_ (m1, ul, m2, op, nops, ops, ae), \
17009 xCM_ (m1, lo, m2, op, nops, ops, ae), \
17010 xCM_ (m1, mi, m2, op, nops, ops, ae), \
17011 xCM_ (m1, pl, m2, op, nops, ops, ae), \
17012 xCM_ (m1, vs, m2, op, nops, ops, ae), \
17013 xCM_ (m1, vc, m2, op, nops, ops, ae), \
17014 xCM_ (m1, hi, m2, op, nops, ops, ae), \
17015 xCM_ (m1, ls, m2, op, nops, ops, ae), \
17016 xCM_ (m1, ge, m2, op, nops, ops, ae), \
17017 xCM_ (m1, lt, m2, op, nops, ops, ae), \
17018 xCM_ (m1, gt, m2, op, nops, ops, ae), \
17019 xCM_ (m1, le, m2, op, nops, ops, ae), \
17020 xCM_ (m1, al, m2, op, nops, ops, ae)
17022 #define UE(mnem, op, nops, ops, ae) \
17023 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17025 #define UF(mnem, op, nops, ops, ae) \
17026 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
17028 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
17029 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
17030 use the same encoding function for each. */
17031 #define NUF(mnem, op, nops, ops, enc) \
17032 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
17033 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17035 /* Neon data processing, version which indirects through neon_enc_tab for
17036 the various overloaded versions of opcodes. */
17037 #define nUF(mnem, op, nops, ops, enc) \
17038 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
17039 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17041 /* Neon insn with conditional suffix for the ARM version, non-overloaded
17043 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
17044 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
17045 THUMB_VARIANT, do_##enc, do_##enc }
17047 #define NCE(mnem, op, nops, ops, enc) \
17048 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17050 #define NCEF(mnem, op, nops, ops, enc) \
17051 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17053 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
17054 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
17055 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
17056 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
17058 #define nCE(mnem, op, nops, ops, enc) \
17059 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
17061 #define nCEF(mnem, op, nops, ops, enc) \
17062 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
17066 static const struct asm_opcode insns
[] =
17068 #define ARM_VARIANT &arm_ext_v1 /* Core ARM Instructions. */
17069 #define THUMB_VARIANT &arm_ext_v4t
17070 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17071 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17072 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17073 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17074 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17075 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
17076 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17077 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
17078 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17079 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17080 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17081 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17082 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17083 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
17084 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17085 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
17087 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
17088 for setting PSR flag bits. They are obsolete in V6 and do not
17089 have Thumb equivalents. */
17090 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17091 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17092 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
17093 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17094 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
17095 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
17096 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17097 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17098 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
17100 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17101 tC3("movs", 1b00000
, _movs
, 2, (RR
, SH
), mov
, t_mov_cmp
),
17102 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17103 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
17105 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
17106 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17107 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
17109 OP_ADDRGLDR
),ldst
, t_ldst
),
17110 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
17112 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17113 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17114 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17115 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17116 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17117 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17119 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17120 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
17121 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
17122 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
17125 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
17126 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
17127 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
17129 /* Thumb-compatibility pseudo ops. */
17130 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17131 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17132 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17133 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17134 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17135 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17136 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17137 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
17138 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
17139 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
17140 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
17141 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
17143 /* These may simplify to neg. */
17144 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17145 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
17147 #undef THUMB_VARIANT
17148 #define THUMB_VARIANT & arm_ext_v6
17150 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
17152 /* V1 instructions with no Thumb analogue prior to V6T2. */
17153 #undef THUMB_VARIANT
17154 #define THUMB_VARIANT & arm_ext_v6t2
17156 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17157 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
17158 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
17160 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17161 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17162 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
17163 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
17165 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17166 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17168 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17169 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
17171 /* V1 instructions with no Thumb analogue at all. */
17172 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
17173 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
17175 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17176 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
17177 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17178 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
17179 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17180 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
17181 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17182 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
17185 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
17186 #undef THUMB_VARIANT
17187 #define THUMB_VARIANT & arm_ext_v4t
17189 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17190 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
17192 #undef THUMB_VARIANT
17193 #define THUMB_VARIANT & arm_ext_v6t2
17195 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17196 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
17198 /* Generic coprocessor instructions. */
17199 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17200 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17201 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17202 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17203 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17204 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17205 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17208 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
17210 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17211 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
17214 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
17215 #undef THUMB_VARIANT
17216 #define THUMB_VARIANT & arm_ext_msr
17218 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
17219 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
17222 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
17223 #undef THUMB_VARIANT
17224 #define THUMB_VARIANT & arm_ext_v6t2
17226 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17227 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17228 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17229 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17230 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17231 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17232 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
17233 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
17236 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
17237 #undef THUMB_VARIANT
17238 #define THUMB_VARIANT & arm_ext_v4t
17240 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17241 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17242 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17243 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17244 tCM("ld","sh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17245 tCM("ld","sb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
17248 #define ARM_VARIANT & arm_ext_v4t_5
17250 /* ARM Architecture 4T. */
17251 /* Note: bx (and blx) are required on V5, even if the processor does
17252 not support Thumb. */
17253 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
17256 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
17257 #undef THUMB_VARIANT
17258 #define THUMB_VARIANT & arm_ext_v5t
17260 /* Note: blx has 2 variants; the .value coded here is for
17261 BLX(2). Only this variant has conditional execution. */
17262 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
17263 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
17265 #undef THUMB_VARIANT
17266 #define THUMB_VARIANT & arm_ext_v6t2
17268 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
17269 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17270 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17271 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17272 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
17273 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
17274 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17275 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
17278 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
17279 #undef THUMB_VARIANT
17280 #define THUMB_VARIANT &arm_ext_v5exp
17282 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17283 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17284 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17285 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17287 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17288 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
17290 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17291 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17292 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17293 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
17295 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17296 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17297 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17298 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17300 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17301 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17303 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17304 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17305 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17306 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
17309 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
17310 #undef THUMB_VARIANT
17311 #define THUMB_VARIANT &arm_ext_v6t2
17313 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
17314 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
17316 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
17317 ADDRGLDRS
), ldrd
, t_ldstd
),
17319 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17320 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17323 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
17325 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
17328 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
17329 #undef THUMB_VARIANT
17330 #define THUMB_VARIANT & arm_ext_v6
17332 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17333 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
17334 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17335 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17336 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
17337 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17338 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17339 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17340 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17341 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
17343 #undef THUMB_VARIANT
17344 #define THUMB_VARIANT & arm_ext_v6t2
17346 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
17347 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17349 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17350 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
17352 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
17353 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
17355 /* ARM V6 not included in V7M. */
17356 #undef THUMB_VARIANT
17357 #define THUMB_VARIANT & arm_ext_v6_notm
17358 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17359 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
17360 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
17361 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17362 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
17363 UF(rfefa
, 9900a00
, 1, (RRw
), rfe
),
17364 UF(rfeea
, 8100a00
, 1, (RRw
), rfe
),
17365 TUF("rfeed", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
17366 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
17367 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
17368 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
17369 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
17371 /* ARM V6 not included in V7M (eg. integer SIMD). */
17372 #undef THUMB_VARIANT
17373 #define THUMB_VARIANT & arm_ext_v6_dsp
17374 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
17375 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
17376 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
17377 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17378 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17379 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17380 /* Old name for QASX. */
17381 TCE("qaddsubx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17382 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17383 /* Old name for QSAX. */
17384 TCE("qsubaddx", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17385 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17386 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17387 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17388 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17389 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17390 /* Old name for SASX. */
17391 TCE("saddsubx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17392 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17393 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17394 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17395 /* Old name for SHASX. */
17396 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17397 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17398 /* Old name for SHSAX. */
17399 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17400 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17401 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17402 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17403 /* Old name for SSAX. */
17404 TCE("ssubaddx", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17405 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17406 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17407 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17408 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17409 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17410 /* Old name for UASX. */
17411 TCE("uaddsubx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17412 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17413 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17414 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17415 /* Old name for UHASX. */
17416 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17417 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17418 /* Old name for UHSAX. */
17419 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17420 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17421 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17422 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17423 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17424 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17425 /* Old name for UQASX. */
17426 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17427 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17428 /* Old name for UQSAX. */
17429 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17430 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17431 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17432 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17433 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17434 /* Old name for USAX. */
17435 TCE("usubaddx", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17436 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17437 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17438 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17439 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17440 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17441 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17442 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17443 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
17444 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
17445 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
17446 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17447 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17448 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17449 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17450 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17451 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17452 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17453 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
17454 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17455 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17456 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17457 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17458 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17459 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17460 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17461 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17462 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17463 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17464 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
17465 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
17466 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
17467 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
17468 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
17471 #define ARM_VARIANT & arm_ext_v6k
17472 #undef THUMB_VARIANT
17473 #define THUMB_VARIANT & arm_ext_v6k
17475 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
17476 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
17477 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
17478 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
17480 #undef THUMB_VARIANT
17481 #define THUMB_VARIANT & arm_ext_v6_notm
17482 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
17484 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
17485 RRnpcb
), strexd
, t_strexd
),
17487 #undef THUMB_VARIANT
17488 #define THUMB_VARIANT & arm_ext_v6t2
17489 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
17491 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
17493 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17495 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
17497 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
17500 #define ARM_VARIANT & arm_ext_sec
17501 #undef THUMB_VARIANT
17502 #define THUMB_VARIANT & arm_ext_sec
17504 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
17507 #define ARM_VARIANT & arm_ext_virt
17508 #undef THUMB_VARIANT
17509 #define THUMB_VARIANT & arm_ext_virt
17511 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
17512 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
17515 #define ARM_VARIANT & arm_ext_v6t2
17516 #undef THUMB_VARIANT
17517 #define THUMB_VARIANT & arm_ext_v6t2
17519 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
17520 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
17521 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17522 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
17524 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
17525 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17526 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
17527 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
17529 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17530 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17531 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17532 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
17534 /* Thumb-only instructions. */
17536 #define ARM_VARIANT NULL
17537 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
17538 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
17540 /* ARM does not really have an IT instruction, so always allow it.
17541 The opcode is copied from Thumb in order to allow warnings in
17542 -mimplicit-it=[never | arm] modes. */
17544 #define ARM_VARIANT & arm_ext_v1
17546 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
17547 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
17548 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
17549 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
17550 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
17551 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
17552 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
17553 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
17554 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
17555 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
17556 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
17557 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
17558 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
17559 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
17560 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
17561 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
17562 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17563 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
17565 /* Thumb2 only instructions. */
17567 #define ARM_VARIANT NULL
17569 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17570 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
17571 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17572 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
17573 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
17574 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
17576 /* Hardware division instructions. */
17578 #define ARM_VARIANT & arm_ext_adiv
17579 #undef THUMB_VARIANT
17580 #define THUMB_VARIANT & arm_ext_div
17582 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17583 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
17585 /* ARM V6M/V7 instructions. */
17587 #define ARM_VARIANT & arm_ext_barrier
17588 #undef THUMB_VARIANT
17589 #define THUMB_VARIANT & arm_ext_barrier
17591 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17592 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17593 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, t_barrier
),
17595 /* ARM V7 instructions. */
17597 #define ARM_VARIANT & arm_ext_v7
17598 #undef THUMB_VARIANT
17599 #define THUMB_VARIANT & arm_ext_v7
17601 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
17602 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
17605 #define ARM_VARIANT & arm_ext_mp
17606 #undef THUMB_VARIANT
17607 #define THUMB_VARIANT & arm_ext_mp
17609 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
17612 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
17614 cCE("wfs", e200110
, 1, (RR
), rd
),
17615 cCE("rfs", e300110
, 1, (RR
), rd
),
17616 cCE("wfc", e400110
, 1, (RR
), rd
),
17617 cCE("rfc", e500110
, 1, (RR
), rd
),
17619 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17620 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17621 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17622 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17624 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17625 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17626 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17627 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
17629 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
17630 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
17631 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
17632 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
17633 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
17634 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
17635 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
17636 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
17637 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
17638 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
17639 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
17640 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
17642 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
17643 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
17644 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
17645 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
17646 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
17647 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
17648 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
17649 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
17650 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
17651 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
17652 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
17653 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
17655 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
17656 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
17657 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
17658 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
17659 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
17660 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
17661 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
17662 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
17663 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
17664 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
17665 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
17666 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
17668 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
17669 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
17670 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
17671 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
17672 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
17673 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
17674 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
17675 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
17676 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
17677 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
17678 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
17679 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
17681 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
17682 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
17683 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
17684 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
17685 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
17686 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
17687 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
17688 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
17689 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
17690 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
17691 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
17692 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
17694 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
17695 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
17696 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
17697 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
17698 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
17699 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
17700 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
17701 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
17702 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
17703 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
17704 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
17705 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
17707 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
17708 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
17709 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
17710 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
17711 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
17712 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
17713 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
17714 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
17715 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
17716 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
17717 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
17718 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
17720 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
17721 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
17722 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
17723 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
17724 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
17725 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
17726 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
17727 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
17728 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
17729 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
17730 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
17731 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
17733 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
17734 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
17735 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
17736 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
17737 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
17738 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
17739 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
17740 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
17741 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
17742 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
17743 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
17744 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
17746 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
17747 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
17748 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
17749 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
17750 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
17751 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
17752 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
17753 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
17754 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
17755 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
17756 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
17757 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
17759 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
17760 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
17761 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
17762 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
17763 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
17764 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
17765 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
17766 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
17767 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
17768 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
17769 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
17770 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
17772 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
17773 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
17774 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
17775 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
17776 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
17777 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
17778 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
17779 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
17780 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
17781 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
17782 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
17783 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
17785 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
17786 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
17787 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
17788 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
17789 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
17790 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
17791 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
17792 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
17793 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
17794 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
17795 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
17796 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
17798 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
17799 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
17800 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
17801 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
17802 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
17803 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
17804 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
17805 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
17806 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
17807 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
17808 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
17809 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
17811 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
17812 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
17813 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
17814 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
17815 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
17816 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
17817 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
17818 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
17819 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
17820 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
17821 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
17822 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
17824 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
17825 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
17826 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
17827 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
17828 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
17829 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
17830 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
17831 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
17832 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
17833 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
17834 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
17835 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
17837 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17838 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17839 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17840 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17841 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17842 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17843 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17844 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17845 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17846 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17847 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17848 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17850 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17851 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17852 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17853 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17854 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17855 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17856 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17857 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17858 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17859 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17860 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17861 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17863 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17864 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17865 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17866 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17867 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17868 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17869 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17870 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17871 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17872 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17873 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17874 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17876 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17877 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17878 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17879 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17880 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17881 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17882 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17883 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17884 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17885 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17886 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17887 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17889 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17890 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17891 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17892 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17893 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17894 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17895 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17896 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17897 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17898 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17899 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17900 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17902 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17903 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17904 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17905 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17906 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17907 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17908 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17909 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17910 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17911 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17912 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17913 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17915 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17916 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17917 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17918 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17919 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17920 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17921 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17922 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17923 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17924 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17925 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17926 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17928 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17929 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17930 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17931 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17932 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17933 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17934 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17935 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17936 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17937 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17938 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17939 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17941 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17942 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17943 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17944 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17945 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17946 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17947 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17948 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17949 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17950 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17951 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17952 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17954 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17955 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17956 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17957 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17958 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17959 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17960 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17961 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17962 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17963 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17964 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17965 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17967 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17968 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17969 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17970 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17971 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17972 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17973 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17974 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17975 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17976 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17977 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17978 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17980 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17981 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17982 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17983 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17984 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17985 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17986 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17987 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17988 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17989 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17990 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17991 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17993 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17994 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17995 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17996 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17997 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17998 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
17999 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18000 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18001 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18002 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18003 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18004 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
18006 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18007 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18008 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18009 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
18011 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
18012 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
18013 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
18014 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
18015 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
18016 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
18017 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
18018 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
18019 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
18020 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
18021 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
18022 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
18024 /* The implementation of the FIX instruction is broken on some
18025 assemblers, in that it accepts a precision specifier as well as a
18026 rounding specifier, despite the fact that this is meaningless.
18027 To be more compatible, we accept it as well, though of course it
18028 does not set any bits. */
18029 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
18030 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
18031 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
18032 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
18033 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
18034 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
18035 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
18036 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
18037 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
18038 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
18039 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
18040 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
18041 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
18043 /* Instructions that were new with the real FPA, call them V2. */
18045 #define ARM_VARIANT & fpu_fpa_ext_v2
18047 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18048 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18049 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18050 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18051 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18052 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
18055 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
18057 /* Moves and type conversions. */
18058 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18059 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
18060 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
18061 cCE("fmstat", ef1fa10
, 0, (), noargs
),
18062 cCE("vmrs", ef10a10
, 2, (APSR_RR
, RVC
), vmrs
),
18063 cCE("vmsr", ee10a10
, 2, (RVC
, RR
), vmsr
),
18064 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18065 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18066 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18067 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18068 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18069 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18070 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
18071 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
18073 /* Memory operations. */
18074 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18075 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
18076 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18077 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18078 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18079 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18080 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18081 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18082 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18083 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18084 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18085 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
18086 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18087 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
18088 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18089 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
18090 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18091 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
18093 /* Monadic operations. */
18094 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18095 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18096 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18098 /* Dyadic operations. */
18099 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18100 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18101 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18102 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18103 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18104 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18105 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18106 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18107 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18110 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18111 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
18112 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
18113 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
18115 /* Double precision load/store are still present on single precision
18116 implementations. */
18117 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18118 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
18119 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18120 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18121 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18122 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18123 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18124 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
18125 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18126 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
18129 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
18131 /* Moves and type conversions. */
18132 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18133 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18134 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18135 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18136 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
18137 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18138 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
18139 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18140 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
18141 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18142 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18143 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18144 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
18146 /* Monadic operations. */
18147 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18148 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18149 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18151 /* Dyadic operations. */
18152 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18153 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18154 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18155 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18156 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18157 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18158 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18159 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18160 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18163 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18164 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
18165 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
18166 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
18169 #define ARM_VARIANT & fpu_vfp_ext_v2
18171 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
18172 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
18173 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
18174 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
18176 /* Instructions which may belong to either the Neon or VFP instruction sets.
18177 Individual encoder functions perform additional architecture checks. */
18179 #define ARM_VARIANT & fpu_vfp_ext_v1xd
18180 #undef THUMB_VARIANT
18181 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
18183 /* These mnemonics are unique to VFP. */
18184 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
18185 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
18186 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18187 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18188 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18189 nCE(vcmp
, _vcmp
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18190 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RVSD_I0
), vfp_nsyn_cmp
),
18191 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
18192 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
18193 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
18195 /* Mnemonics shared by Neon and VFP. */
18196 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
18197 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18198 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
18200 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18201 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
18203 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18204 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
18206 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18207 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18208 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18209 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18210 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18211 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
18212 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18213 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
18215 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
18216 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
18217 nCEF(vcvtb
, _vcvt
, 2, (RVS
, RVS
), neon_cvtb
),
18218 nCEF(vcvtt
, _vcvt
, 2, (RVS
, RVS
), neon_cvtt
),
18221 /* NOTE: All VMOV encoding is special-cased! */
18222 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
18223 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
18225 #undef THUMB_VARIANT
18226 #define THUMB_VARIANT & fpu_neon_ext_v1
18228 #define ARM_VARIANT & fpu_neon_ext_v1
18230 /* Data processing with three registers of the same length. */
18231 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
18232 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
18233 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
18234 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18235 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18236 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18237 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18238 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
18239 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
18240 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
18241 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18242 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18243 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
18244 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
18245 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18246 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18247 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
18248 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
18249 /* If not immediate, fall back to neon_dyadic_i64_su.
18250 shl_imm should accept I8 I16 I32 I64,
18251 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
18252 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
18253 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
18254 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
18255 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
18256 /* Logic ops, types optional & ignored. */
18257 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18258 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18259 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18260 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18261 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18262 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18263 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
18264 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
18265 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
18266 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
18267 /* Bitfield ops, untyped. */
18268 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18269 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18270 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18271 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18272 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
18273 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
18274 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F32. */
18275 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18276 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18277 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18278 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18279 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
18280 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
18281 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
18282 back to neon_dyadic_if_su. */
18283 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18284 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18285 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
18286 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
18287 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18288 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18289 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
18290 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
18291 /* Comparison. Type I8 I16 I32 F32. */
18292 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
18293 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
18294 /* As above, D registers only. */
18295 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18296 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
18297 /* Int and float variants, signedness unimportant. */
18298 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18299 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
18300 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
18301 /* Add/sub take types I8 I16 I32 I64 F32. */
18302 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18303 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
18304 /* vtst takes sizes 8, 16, 32. */
18305 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
18306 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
18307 /* VMUL takes I8 I16 I32 F32 P8. */
18308 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
18309 /* VQD{R}MULH takes S16 S32. */
18310 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18311 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18312 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
18313 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
18314 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18315 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18316 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
18317 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
18318 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18319 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18320 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
18321 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
18322 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18323 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18324 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
18325 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
18327 /* Two address, int/float. Types S8 S16 S32 F32. */
18328 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18329 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
18331 /* Data processing with two registers and a shift amount. */
18332 /* Right shifts, and variants with rounding.
18333 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
18334 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18335 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18336 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
18337 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
18338 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18339 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18340 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
18341 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
18342 /* Shift and insert. Sizes accepted 8 16 32 64. */
18343 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
18344 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
18345 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
18346 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
18347 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
18348 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
18349 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
18350 /* Right shift immediate, saturating & narrowing, with rounding variants.
18351 Types accepted S16 S32 S64 U16 U32 U64. */
18352 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18353 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
18354 /* As above, unsigned. Types accepted S16 S32 S64. */
18355 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18356 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
18357 /* Right shift narrowing. Types accepted I16 I32 I64. */
18358 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18359 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
18360 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
18361 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
18362 /* CVT with optional immediate for fixed-point variant. */
18363 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
18365 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
18366 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
18368 /* Data processing, three registers of different lengths. */
18369 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
18370 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
18371 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18372 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18373 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
18374 /* If not scalar, fall back to neon_dyadic_long.
18375 Vector types as above, scalar types S16 S32 U16 U32. */
18376 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18377 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
18378 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
18379 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18380 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
18381 /* Dyadic, narrowing insns. Types I16 I32 I64. */
18382 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18383 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18384 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18385 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
18386 /* Saturating doubling multiplies. Types S16 S32. */
18387 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18388 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18389 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
18390 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
18391 S16 S32 U16 U32. */
18392 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
18394 /* Extract. Size 8. */
18395 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
18396 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
18398 /* Two registers, miscellaneous. */
18399 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
18400 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
18401 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
18402 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
18403 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
18404 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
18405 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
18406 /* Vector replicate. Sizes 8 16 32. */
18407 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
18408 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
18409 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
18410 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
18411 /* VMOVN. Types I16 I32 I64. */
18412 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
18413 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
18414 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
18415 /* VQMOVUN. Types S16 S32 S64. */
18416 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
18417 /* VZIP / VUZP. Sizes 8 16 32. */
18418 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18419 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18420 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
18421 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
18422 /* VQABS / VQNEG. Types S8 S16 S32. */
18423 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18424 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18425 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
18426 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
18427 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
18428 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18429 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
18430 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
18431 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
18432 /* Reciprocal estimates. Types U32 F32. */
18433 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18434 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
18435 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
18436 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
18437 /* VCLS. Types S8 S16 S32. */
18438 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
18439 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
18440 /* VCLZ. Types I8 I16 I32. */
18441 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
18442 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
18443 /* VCNT. Size 8. */
18444 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
18445 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
18446 /* Two address, untyped. */
18447 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
18448 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
18449 /* VTRN. Sizes 8 16 32. */
18450 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
18451 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
18453 /* Table lookup. Size 8. */
18454 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18455 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
18457 #undef THUMB_VARIANT
18458 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
18460 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
18462 /* Neon element/structure load/store. */
18463 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18464 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18465 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18466 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18467 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18468 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18469 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18470 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
18472 #undef THUMB_VARIANT
18473 #define THUMB_VARIANT &fpu_vfp_ext_v3xd
18475 #define ARM_VARIANT &fpu_vfp_ext_v3xd
18476 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
18477 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18478 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18479 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18480 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18481 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18482 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18483 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
18484 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
18486 #undef THUMB_VARIANT
18487 #define THUMB_VARIANT & fpu_vfp_ext_v3
18489 #define ARM_VARIANT & fpu_vfp_ext_v3
18491 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
18492 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18493 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18494 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18495 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18496 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18497 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18498 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
18499 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
18502 #define ARM_VARIANT &fpu_vfp_ext_fma
18503 #undef THUMB_VARIANT
18504 #define THUMB_VARIANT &fpu_vfp_ext_fma
18505 /* Mnemonics shared by Neon and VFP. These are included in the
18506 VFP FMA variant; NEON and VFP FMA always includes the NEON
18507 FMA instructions. */
18508 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18509 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
18510 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
18511 the v form should always be used. */
18512 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18513 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
18514 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18515 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
18516 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18517 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
18519 #undef THUMB_VARIANT
18521 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
18523 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18524 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18525 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18526 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18527 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18528 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
18529 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
18530 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
18533 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
18535 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
18536 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
18537 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
18538 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
18539 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
18540 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
18541 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
18542 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
18543 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
18544 cCE("textrmub", e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18545 cCE("textrmuh", e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18546 cCE("textrmuw", e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18547 cCE("textrmsb", e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18548 cCE("textrmsh", e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18549 cCE("textrmsw", e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
18550 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18551 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18552 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
18553 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
18554 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
18555 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18556 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18557 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18558 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18559 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18560 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
18561 cCE("tmovmskb", e100030
, 2, (RR
, RIWR
), rd_rn
),
18562 cCE("tmovmskh", e500030
, 2, (RR
, RIWR
), rd_rn
),
18563 cCE("tmovmskw", e900030
, 2, (RR
, RIWR
), rd_rn
),
18564 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
18565 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
18566 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
18567 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
18568 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
18569 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18570 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18571 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18572 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18573 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18574 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18575 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18576 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18577 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18578 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18579 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18580 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18581 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
18582 cCE("walignr0", e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18583 cCE("walignr1", e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18584 cCE("walignr2", ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18585 cCE("walignr3", eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18586 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18587 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18588 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18589 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18590 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18591 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18592 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18593 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18594 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18595 cCE("wcmpgtub", e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18596 cCE("wcmpgtuh", e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18597 cCE("wcmpgtuw", e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18598 cCE("wcmpgtsb", e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18599 cCE("wcmpgtsh", e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18600 cCE("wcmpgtsw", eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18601 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18602 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18603 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18604 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18605 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18606 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18607 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18608 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18609 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18610 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18611 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18612 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18613 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18614 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18615 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18616 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18617 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18618 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18619 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18620 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18621 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18622 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18623 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
18624 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18625 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18626 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18627 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18628 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18629 cCE("wpackhss", e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18630 cCE("wpackhus", e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18631 cCE("wpackwss", eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18632 cCE("wpackwus", e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18633 cCE("wpackdss", ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18634 cCE("wpackdus", ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18635 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18636 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18637 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18638 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18639 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18640 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18641 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18642 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18643 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18644 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18645 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
18646 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18647 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18648 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18649 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18650 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18651 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18652 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18653 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18654 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18655 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18656 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18657 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18658 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18659 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18660 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18661 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18662 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
18663 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
18664 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18665 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
18666 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
18667 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
18668 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18669 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18670 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18671 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18672 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18673 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18674 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18675 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18676 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18677 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18678 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18679 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18680 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18681 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18682 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
18683 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18684 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18685 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18686 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18687 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18688 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18689 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18690 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18691 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
18692 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18693 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18694 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18695 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18696 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
18699 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
18701 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
18702 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
18703 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
18704 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18705 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18706 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
18707 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18708 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18709 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18710 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18711 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18712 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18713 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18714 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18715 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18716 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18717 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18718 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18719 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18720 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18721 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
18722 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18723 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18724 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18725 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18726 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18727 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18728 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18729 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18730 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18731 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18732 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18733 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18734 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18735 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18736 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18737 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18738 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18739 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18740 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18741 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18742 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18743 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18744 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18745 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18746 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18747 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18748 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18749 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18750 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18751 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18752 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18753 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18754 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18755 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18756 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18757 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
18760 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
18762 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18763 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18764 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18765 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18766 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
18767 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
18768 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
18769 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
18770 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
18771 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
18772 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
18773 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
18774 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
18775 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
18776 cCE("cfmv64lr", e000510
, 2, (RMDX
, RR
), rn_rd
),
18777 cCE("cfmvr64l", e100510
, 2, (RR
, RMDX
), rd_rn
),
18778 cCE("cfmv64hr", e000530
, 2, (RMDX
, RR
), rn_rd
),
18779 cCE("cfmvr64h", e100530
, 2, (RR
, RMDX
), rd_rn
),
18780 cCE("cfmval32", e200440
, 2, (RMAX
, RMFX
), rd_rn
),
18781 cCE("cfmv32al", e100440
, 2, (RMFX
, RMAX
), rd_rn
),
18782 cCE("cfmvam32", e200460
, 2, (RMAX
, RMFX
), rd_rn
),
18783 cCE("cfmv32am", e100460
, 2, (RMFX
, RMAX
), rd_rn
),
18784 cCE("cfmvah32", e200480
, 2, (RMAX
, RMFX
), rd_rn
),
18785 cCE("cfmv32ah", e100480
, 2, (RMFX
, RMAX
), rd_rn
),
18786 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
18787 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
18788 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
18789 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
18790 cCE("cfmvsc32", e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
18791 cCE("cfmv32sc", e1004e0
, 2, (RMDX
, RMDS
), rd
),
18792 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
18793 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
18794 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
18795 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
18796 cCE("cfcvt32s", e000480
, 2, (RMF
, RMFX
), rd_rn
),
18797 cCE("cfcvt32d", e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
18798 cCE("cfcvt64s", e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
18799 cCE("cfcvt64d", e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
18800 cCE("cfcvts32", e100580
, 2, (RMFX
, RMF
), rd_rn
),
18801 cCE("cfcvtd32", e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
18802 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
18803 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
18804 cCE("cfrshl32", e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
18805 cCE("cfrshl64", e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
18806 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
18807 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
18808 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
18809 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
18810 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
18811 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
18812 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
18813 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
18814 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
18815 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
18816 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18817 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18818 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18819 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18820 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
18821 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
18822 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
18823 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
18824 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
18825 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
18826 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18827 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18828 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18829 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18830 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18831 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
18832 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18833 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
18834 cCE("cfmadd32", e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18835 cCE("cfmsub32", e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
18836 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18837 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
18840 #undef THUMB_VARIANT
18867 /* MD interface: bits in the object file. */
18869 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
18870 for use in the a.out file, and stores them in the array pointed to by buf.
18871 This knows about the endian-ness of the target machine and does
18872 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
18873 2 (short) and 4 (long) Floating numbers are put out as a series of
18874 LITTLENUMS (shorts, here at least). */
18877 md_number_to_chars (char * buf
, valueT val
, int n
)
18879 if (target_big_endian
)
18880 number_to_chars_bigendian (buf
, val
, n
);
18882 number_to_chars_littleendian (buf
, val
, n
);
18886 md_chars_to_number (char * buf
, int n
)
18889 unsigned char * where
= (unsigned char *) buf
;
18891 if (target_big_endian
)
18896 result
|= (*where
++ & 255);
18904 result
|= (where
[n
] & 255);
18911 /* MD interface: Sections. */
18913 /* Estimate the size of a frag before relaxing. Assume everything fits in
18917 md_estimate_size_before_relax (fragS
* fragp
,
18918 segT segtype ATTRIBUTE_UNUSED
)
18924 /* Convert a machine dependent frag. */
18927 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
18929 unsigned long insn
;
18930 unsigned long old_op
;
18938 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
18940 old_op
= bfd_get_16(abfd
, buf
);
18941 if (fragp
->fr_symbol
)
18943 exp
.X_op
= O_symbol
;
18944 exp
.X_add_symbol
= fragp
->fr_symbol
;
18948 exp
.X_op
= O_constant
;
18950 exp
.X_add_number
= fragp
->fr_offset
;
18951 opcode
= fragp
->fr_subtype
;
18954 case T_MNEM_ldr_pc
:
18955 case T_MNEM_ldr_pc2
:
18956 case T_MNEM_ldr_sp
:
18957 case T_MNEM_str_sp
:
18964 if (fragp
->fr_var
== 4)
18966 insn
= THUMB_OP32 (opcode
);
18967 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
18969 insn
|= (old_op
& 0x700) << 4;
18973 insn
|= (old_op
& 7) << 12;
18974 insn
|= (old_op
& 0x38) << 13;
18976 insn
|= 0x00000c00;
18977 put_thumb32_insn (buf
, insn
);
18978 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
18982 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
18984 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
18987 if (fragp
->fr_var
== 4)
18989 insn
= THUMB_OP32 (opcode
);
18990 insn
|= (old_op
& 0xf0) << 4;
18991 put_thumb32_insn (buf
, insn
);
18992 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
18996 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
18997 exp
.X_add_number
-= 4;
19005 if (fragp
->fr_var
== 4)
19007 int r0off
= (opcode
== T_MNEM_mov
19008 || opcode
== T_MNEM_movs
) ? 0 : 8;
19009 insn
= THUMB_OP32 (opcode
);
19010 insn
= (insn
& 0xe1ffffff) | 0x10000000;
19011 insn
|= (old_op
& 0x700) << r0off
;
19012 put_thumb32_insn (buf
, insn
);
19013 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19017 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
19022 if (fragp
->fr_var
== 4)
19024 insn
= THUMB_OP32(opcode
);
19025 put_thumb32_insn (buf
, insn
);
19026 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
19029 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
19033 if (fragp
->fr_var
== 4)
19035 insn
= THUMB_OP32(opcode
);
19036 insn
|= (old_op
& 0xf00) << 14;
19037 put_thumb32_insn (buf
, insn
);
19038 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
19041 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
19044 case T_MNEM_add_sp
:
19045 case T_MNEM_add_pc
:
19046 case T_MNEM_inc_sp
:
19047 case T_MNEM_dec_sp
:
19048 if (fragp
->fr_var
== 4)
19050 /* ??? Choose between add and addw. */
19051 insn
= THUMB_OP32 (opcode
);
19052 insn
|= (old_op
& 0xf0) << 4;
19053 put_thumb32_insn (buf
, insn
);
19054 if (opcode
== T_MNEM_add_pc
)
19055 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
19057 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19060 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19068 if (fragp
->fr_var
== 4)
19070 insn
= THUMB_OP32 (opcode
);
19071 insn
|= (old_op
& 0xf0) << 4;
19072 insn
|= (old_op
& 0xf) << 16;
19073 put_thumb32_insn (buf
, insn
);
19074 if (insn
& (1 << 20))
19075 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
19077 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
19080 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
19086 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
19087 (enum bfd_reloc_code_real
) reloc_type
);
19088 fixp
->fx_file
= fragp
->fr_file
;
19089 fixp
->fx_line
= fragp
->fr_line
;
19090 fragp
->fr_fix
+= fragp
->fr_var
;
19093 /* Return the size of a relaxable immediate operand instruction.
19094 SHIFT and SIZE specify the form of the allowable immediate. */
19096 relax_immediate (fragS
*fragp
, int size
, int shift
)
19102 /* ??? Should be able to do better than this. */
19103 if (fragp
->fr_symbol
)
19106 low
= (1 << shift
) - 1;
19107 mask
= (1 << (shift
+ size
)) - (1 << shift
);
19108 offset
= fragp
->fr_offset
;
19109 /* Force misaligned offsets to 32-bit variant. */
19112 if (offset
& ~mask
)
19117 /* Get the address of a symbol during relaxation. */
19119 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
19125 sym
= fragp
->fr_symbol
;
19126 sym_frag
= symbol_get_frag (sym
);
19127 know (S_GET_SEGMENT (sym
) != absolute_section
19128 || sym_frag
== &zero_address_frag
);
19129 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
19131 /* If frag has yet to be reached on this pass, assume it will
19132 move by STRETCH just as we did. If this is not so, it will
19133 be because some frag between grows, and that will force
19137 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
19141 /* Adjust stretch for any alignment frag. Note that if have
19142 been expanding the earlier code, the symbol may be
19143 defined in what appears to be an earlier frag. FIXME:
19144 This doesn't handle the fr_subtype field, which specifies
19145 a maximum number of bytes to skip when doing an
19147 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
19149 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
19152 stretch
= - ((- stretch
)
19153 & ~ ((1 << (int) f
->fr_offset
) - 1));
19155 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
19167 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
19170 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
19175 /* Assume worst case for symbols not known to be in the same section. */
19176 if (fragp
->fr_symbol
== NULL
19177 || !S_IS_DEFINED (fragp
->fr_symbol
)
19178 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19179 || S_IS_WEAK (fragp
->fr_symbol
))
19182 val
= relaxed_symbol_addr (fragp
, stretch
);
19183 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
19184 addr
= (addr
+ 4) & ~3;
19185 /* Force misaligned targets to 32-bit variant. */
19189 if (val
< 0 || val
> 1020)
19194 /* Return the size of a relaxable add/sub immediate instruction. */
19196 relax_addsub (fragS
*fragp
, asection
*sec
)
19201 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
19202 op
= bfd_get_16(sec
->owner
, buf
);
19203 if ((op
& 0xf) == ((op
>> 4) & 0xf))
19204 return relax_immediate (fragp
, 8, 0);
19206 return relax_immediate (fragp
, 3, 0);
19210 /* Return the size of a relaxable branch instruction. BITS is the
19211 size of the offset field in the narrow instruction. */
19214 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
19220 /* Assume worst case for symbols not known to be in the same section. */
19221 if (!S_IS_DEFINED (fragp
->fr_symbol
)
19222 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
19223 || S_IS_WEAK (fragp
->fr_symbol
))
19227 if (S_IS_DEFINED (fragp
->fr_symbol
)
19228 && ARM_IS_FUNC (fragp
->fr_symbol
))
19231 /* PR 12532. Global symbols with default visibility might
19232 be preempted, so do not relax relocations to them. */
19233 if ((ELF_ST_VISIBILITY (S_GET_OTHER (fragp
->fr_symbol
)) == STV_DEFAULT
)
19234 && (! S_IS_LOCAL (fragp
->fr_symbol
)))
19238 val
= relaxed_symbol_addr (fragp
, stretch
);
19239 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
19242 /* Offset is a signed value *2 */
19244 if (val
>= limit
|| val
< -limit
)
19250 /* Relax a machine dependent frag. This returns the amount by which
19251 the current size of the frag should change. */
19254 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
19259 oldsize
= fragp
->fr_var
;
19260 switch (fragp
->fr_subtype
)
19262 case T_MNEM_ldr_pc2
:
19263 newsize
= relax_adr (fragp
, sec
, stretch
);
19265 case T_MNEM_ldr_pc
:
19266 case T_MNEM_ldr_sp
:
19267 case T_MNEM_str_sp
:
19268 newsize
= relax_immediate (fragp
, 8, 2);
19272 newsize
= relax_immediate (fragp
, 5, 2);
19276 newsize
= relax_immediate (fragp
, 5, 1);
19280 newsize
= relax_immediate (fragp
, 5, 0);
19283 newsize
= relax_adr (fragp
, sec
, stretch
);
19289 newsize
= relax_immediate (fragp
, 8, 0);
19292 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
19295 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
19297 case T_MNEM_add_sp
:
19298 case T_MNEM_add_pc
:
19299 newsize
= relax_immediate (fragp
, 8, 2);
19301 case T_MNEM_inc_sp
:
19302 case T_MNEM_dec_sp
:
19303 newsize
= relax_immediate (fragp
, 7, 2);
19309 newsize
= relax_addsub (fragp
, sec
);
19315 fragp
->fr_var
= newsize
;
19316 /* Freeze wide instructions that are at or before the same location as
19317 in the previous pass. This avoids infinite loops.
19318 Don't freeze them unconditionally because targets may be artificially
19319 misaligned by the expansion of preceding frags. */
19320 if (stretch
<= 0 && newsize
> 2)
19322 md_convert_frag (sec
->owner
, sec
, fragp
);
19326 return newsize
- oldsize
;
19329 /* Round up a section size to the appropriate boundary. */
19332 md_section_align (segT segment ATTRIBUTE_UNUSED
,
19335 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
19336 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
19338 /* For a.out, force the section size to be aligned. If we don't do
19339 this, BFD will align it for us, but it will not write out the
19340 final bytes of the section. This may be a bug in BFD, but it is
19341 easier to fix it here since that is how the other a.out targets
19345 align
= bfd_get_section_alignment (stdoutput
, segment
);
19346 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
19353 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
19354 of an rs_align_code fragment. */
19357 arm_handle_align (fragS
* fragP
)
19359 static char const arm_noop
[2][2][4] =
19362 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
19363 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
19366 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
19367 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
19370 static char const thumb_noop
[2][2][2] =
19373 {0xc0, 0x46}, /* LE */
19374 {0x46, 0xc0}, /* BE */
19377 {0x00, 0xbf}, /* LE */
19378 {0xbf, 0x00} /* BE */
19381 static char const wide_thumb_noop
[2][4] =
19382 { /* Wide Thumb-2 */
19383 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
19384 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
19387 unsigned bytes
, fix
, noop_size
;
19390 const char *narrow_noop
= NULL
;
19395 if (fragP
->fr_type
!= rs_align_code
)
19398 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
19399 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
19402 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19403 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
19405 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
19407 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
19409 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
19411 narrow_noop
= thumb_noop
[1][target_big_endian
];
19412 noop
= wide_thumb_noop
[target_big_endian
];
19415 noop
= thumb_noop
[0][target_big_endian
];
19423 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
) != 0]
19424 [target_big_endian
];
19431 fragP
->fr_var
= noop_size
;
19433 if (bytes
& (noop_size
- 1))
19435 fix
= bytes
& (noop_size
- 1);
19437 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
19439 memset (p
, 0, fix
);
19446 if (bytes
& noop_size
)
19448 /* Insert a narrow noop. */
19449 memcpy (p
, narrow_noop
, noop_size
);
19451 bytes
-= noop_size
;
19455 /* Use wide noops for the remainder */
19459 while (bytes
>= noop_size
)
19461 memcpy (p
, noop
, noop_size
);
19463 bytes
-= noop_size
;
19467 fragP
->fr_fix
+= fix
;
19470 /* Called from md_do_align. Used to create an alignment
19471 frag in a code section. */
19474 arm_frag_align_code (int n
, int max
)
19478 /* We assume that there will never be a requirement
19479 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
19480 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
19485 _("alignments greater than %d bytes not supported in .text sections."),
19486 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
19487 as_fatal ("%s", err_msg
);
19490 p
= frag_var (rs_align_code
,
19491 MAX_MEM_FOR_RS_ALIGN_CODE
,
19493 (relax_substateT
) max
,
19500 /* Perform target specific initialisation of a frag.
19501 Note - despite the name this initialisation is not done when the frag
19502 is created, but only when its type is assigned. A frag can be created
19503 and used a long time before its type is set, so beware of assuming that
19504 this initialisationis performed first. */
19508 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
19510 /* Record whether this frag is in an ARM or a THUMB area. */
19511 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19514 #else /* OBJ_ELF is defined. */
19516 arm_init_frag (fragS
* fragP
, int max_chars
)
19518 /* If the current ARM vs THUMB mode has not already
19519 been recorded into this frag then do so now. */
19520 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
19522 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
19524 /* Record a mapping symbol for alignment frags. We will delete this
19525 later if the alignment ends up empty. */
19526 switch (fragP
->fr_type
)
19529 case rs_align_test
:
19531 mapping_state_2 (MAP_DATA
, max_chars
);
19533 case rs_align_code
:
19534 mapping_state_2 (thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
19542 /* When we change sections we need to issue a new mapping symbol. */
19545 arm_elf_change_section (void)
19547 /* Link an unlinked unwind index table section to the .text section. */
19548 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
19549 && elf_linked_to_section (now_seg
) == NULL
)
19550 elf_linked_to_section (now_seg
) = text_section
;
19554 arm_elf_section_type (const char * str
, size_t len
)
19556 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
19557 return SHT_ARM_EXIDX
;
19562 /* Code to deal with unwinding tables. */
19564 static void add_unwind_adjustsp (offsetT
);
19566 /* Generate any deferred unwind frame offset. */
19569 flush_pending_unwind (void)
19573 offset
= unwind
.pending_offset
;
19574 unwind
.pending_offset
= 0;
19576 add_unwind_adjustsp (offset
);
19579 /* Add an opcode to this list for this function. Two-byte opcodes should
19580 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
19584 add_unwind_opcode (valueT op
, int length
)
19586 /* Add any deferred stack adjustment. */
19587 if (unwind
.pending_offset
)
19588 flush_pending_unwind ();
19590 unwind
.sp_restored
= 0;
19592 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
19594 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
19595 if (unwind
.opcodes
)
19596 unwind
.opcodes
= (unsigned char *) xrealloc (unwind
.opcodes
,
19597 unwind
.opcode_alloc
);
19599 unwind
.opcodes
= (unsigned char *) xmalloc (unwind
.opcode_alloc
);
19604 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
19606 unwind
.opcode_count
++;
19610 /* Add unwind opcodes to adjust the stack pointer. */
19613 add_unwind_adjustsp (offsetT offset
)
19617 if (offset
> 0x200)
19619 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
19624 /* Long form: 0xb2, uleb128. */
19625 /* This might not fit in a word so add the individual bytes,
19626 remembering the list is built in reverse order. */
19627 o
= (valueT
) ((offset
- 0x204) >> 2);
19629 add_unwind_opcode (0, 1);
19631 /* Calculate the uleb128 encoding of the offset. */
19635 bytes
[n
] = o
& 0x7f;
19641 /* Add the insn. */
19643 add_unwind_opcode (bytes
[n
- 1], 1);
19644 add_unwind_opcode (0xb2, 1);
19646 else if (offset
> 0x100)
19648 /* Two short opcodes. */
19649 add_unwind_opcode (0x3f, 1);
19650 op
= (offset
- 0x104) >> 2;
19651 add_unwind_opcode (op
, 1);
19653 else if (offset
> 0)
19655 /* Short opcode. */
19656 op
= (offset
- 4) >> 2;
19657 add_unwind_opcode (op
, 1);
19659 else if (offset
< 0)
19662 while (offset
> 0x100)
19664 add_unwind_opcode (0x7f, 1);
19667 op
= ((offset
- 4) >> 2) | 0x40;
19668 add_unwind_opcode (op
, 1);
19672 /* Finish the list of unwind opcodes for this function. */
19674 finish_unwind_opcodes (void)
19678 if (unwind
.fp_used
)
19680 /* Adjust sp as necessary. */
19681 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
19682 flush_pending_unwind ();
19684 /* After restoring sp from the frame pointer. */
19685 op
= 0x90 | unwind
.fp_reg
;
19686 add_unwind_opcode (op
, 1);
19689 flush_pending_unwind ();
19693 /* Start an exception table entry. If idx is nonzero this is an index table
19697 start_unwind_section (const segT text_seg
, int idx
)
19699 const char * text_name
;
19700 const char * prefix
;
19701 const char * prefix_once
;
19702 const char * group_name
;
19706 size_t sec_name_len
;
19713 prefix
= ELF_STRING_ARM_unwind
;
19714 prefix_once
= ELF_STRING_ARM_unwind_once
;
19715 type
= SHT_ARM_EXIDX
;
19719 prefix
= ELF_STRING_ARM_unwind_info
;
19720 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
19721 type
= SHT_PROGBITS
;
19724 text_name
= segment_name (text_seg
);
19725 if (streq (text_name
, ".text"))
19728 if (strncmp (text_name
, ".gnu.linkonce.t.",
19729 strlen (".gnu.linkonce.t.")) == 0)
19731 prefix
= prefix_once
;
19732 text_name
+= strlen (".gnu.linkonce.t.");
19735 prefix_len
= strlen (prefix
);
19736 text_len
= strlen (text_name
);
19737 sec_name_len
= prefix_len
+ text_len
;
19738 sec_name
= (char *) xmalloc (sec_name_len
+ 1);
19739 memcpy (sec_name
, prefix
, prefix_len
);
19740 memcpy (sec_name
+ prefix_len
, text_name
, text_len
);
19741 sec_name
[prefix_len
+ text_len
] = '\0';
19747 /* Handle COMDAT group. */
19748 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
19750 group_name
= elf_group_name (text_seg
);
19751 if (group_name
== NULL
)
19753 as_bad (_("Group section `%s' has no group signature"),
19754 segment_name (text_seg
));
19755 ignore_rest_of_line ();
19758 flags
|= SHF_GROUP
;
19762 obj_elf_change_section (sec_name
, type
, flags
, 0, group_name
, linkonce
, 0);
19764 /* Set the section link for index tables. */
19766 elf_linked_to_section (now_seg
) = text_seg
;
19770 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
19771 personality routine data. Returns zero, or the index table value for
19772 and inline entry. */
19775 create_unwind_entry (int have_data
)
19780 /* The current word of data. */
19782 /* The number of bytes left in this word. */
19785 finish_unwind_opcodes ();
19787 /* Remember the current text section. */
19788 unwind
.saved_seg
= now_seg
;
19789 unwind
.saved_subseg
= now_subseg
;
19791 start_unwind_section (now_seg
, 0);
19793 if (unwind
.personality_routine
== NULL
)
19795 if (unwind
.personality_index
== -2)
19798 as_bad (_("handlerdata in cantunwind frame"));
19799 return 1; /* EXIDX_CANTUNWIND. */
19802 /* Use a default personality routine if none is specified. */
19803 if (unwind
.personality_index
== -1)
19805 if (unwind
.opcode_count
> 3)
19806 unwind
.personality_index
= 1;
19808 unwind
.personality_index
= 0;
19811 /* Space for the personality routine entry. */
19812 if (unwind
.personality_index
== 0)
19814 if (unwind
.opcode_count
> 3)
19815 as_bad (_("too many unwind opcodes for personality routine 0"));
19819 /* All the data is inline in the index table. */
19822 while (unwind
.opcode_count
> 0)
19824 unwind
.opcode_count
--;
19825 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19829 /* Pad with "finish" opcodes. */
19831 data
= (data
<< 8) | 0xb0;
19838 /* We get two opcodes "free" in the first word. */
19839 size
= unwind
.opcode_count
- 2;
19842 /* An extra byte is required for the opcode count. */
19843 size
= unwind
.opcode_count
+ 1;
19845 size
= (size
+ 3) >> 2;
19847 as_bad (_("too many unwind opcodes"));
19849 frag_align (2, 0, 0);
19850 record_alignment (now_seg
, 2);
19851 unwind
.table_entry
= expr_build_dot ();
19853 /* Allocate the table entry. */
19854 ptr
= frag_more ((size
<< 2) + 4);
19855 where
= frag_now_fix () - ((size
<< 2) + 4);
19857 switch (unwind
.personality_index
)
19860 /* ??? Should this be a PLT generating relocation? */
19861 /* Custom personality routine. */
19862 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
19863 BFD_RELOC_ARM_PREL31
);
19868 /* Set the first byte to the number of additional words. */
19873 /* ABI defined personality routines. */
19875 /* Three opcodes bytes are packed into the first word. */
19882 /* The size and first two opcode bytes go in the first word. */
19883 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
19888 /* Should never happen. */
19892 /* Pack the opcodes into words (MSB first), reversing the list at the same
19894 while (unwind
.opcode_count
> 0)
19898 md_number_to_chars (ptr
, data
, 4);
19903 unwind
.opcode_count
--;
19905 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
19908 /* Finish off the last word. */
19911 /* Pad with "finish" opcodes. */
19913 data
= (data
<< 8) | 0xb0;
19915 md_number_to_chars (ptr
, data
, 4);
19920 /* Add an empty descriptor if there is no user-specified data. */
19921 ptr
= frag_more (4);
19922 md_number_to_chars (ptr
, 0, 4);
19929 /* Initialize the DWARF-2 unwind information for this procedure. */
19932 tc_arm_frame_initial_instructions (void)
19934 cfi_add_CFA_def_cfa (REG_SP
, 0);
19936 #endif /* OBJ_ELF */
19938 /* Convert REGNAME to a DWARF-2 register number. */
19941 tc_arm_regname_to_dw2regnum (char *regname
)
19943 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
19953 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
19957 exp
.X_op
= O_secrel
;
19958 exp
.X_add_symbol
= symbol
;
19959 exp
.X_add_number
= 0;
19960 emit_expr (&exp
, size
);
19964 /* MD interface: Symbol and relocation handling. */
19966 /* Return the address within the segment that a PC-relative fixup is
19967 relative to. For ARM, PC-relative fixups applied to instructions
19968 are generally relative to the location of the fixup plus 8 bytes.
19969 Thumb branches are offset by 4, and Thumb loads relative to PC
19970 require special handling. */
19973 md_pcrel_from_section (fixS
* fixP
, segT seg
)
19975 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
19977 /* If this is pc-relative and we are going to emit a relocation
19978 then we just want to put out any pipeline compensation that the linker
19979 will need. Otherwise we want to use the calculated base.
19980 For WinCE we skip the bias for externals as well, since this
19981 is how the MS ARM-CE assembler behaves and we want to be compatible. */
19983 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
19984 || (arm_force_relocation (fixP
)
19986 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
19992 switch (fixP
->fx_r_type
)
19994 /* PC relative addressing on the Thumb is slightly odd as the
19995 bottom two bits of the PC are forced to zero for the
19996 calculation. This happens *after* application of the
19997 pipeline offset. However, Thumb adrl already adjusts for
19998 this, so we need not do it again. */
19999 case BFD_RELOC_ARM_THUMB_ADD
:
20002 case BFD_RELOC_ARM_THUMB_OFFSET
:
20003 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20004 case BFD_RELOC_ARM_T32_ADD_PC12
:
20005 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
20006 return (base
+ 4) & ~3;
20008 /* Thumb branches are simply offset by +4. */
20009 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
20010 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
20011 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
20012 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
20013 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
20016 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
20018 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20019 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20020 && ARM_IS_FUNC (fixP
->fx_addsy
)
20021 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20022 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20025 /* BLX is like branches above, but forces the low two bits of PC to
20027 case BFD_RELOC_THUMB_PCREL_BLX
:
20029 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20030 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20031 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20032 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20033 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20034 return (base
+ 4) & ~3;
20036 /* ARM mode branches are offset by +8. However, the Windows CE
20037 loader expects the relocation not to take this into account. */
20038 case BFD_RELOC_ARM_PCREL_BLX
:
20040 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20041 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20042 && ARM_IS_FUNC (fixP
->fx_addsy
)
20043 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20044 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20047 case BFD_RELOC_ARM_PCREL_CALL
:
20049 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20050 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20051 && THUMB_IS_FUNC (fixP
->fx_addsy
)
20052 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
20053 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
20056 case BFD_RELOC_ARM_PCREL_BRANCH
:
20057 case BFD_RELOC_ARM_PCREL_JUMP
:
20058 case BFD_RELOC_ARM_PLT32
:
20060 /* When handling fixups immediately, because we have already
20061 discovered the value of a symbol, or the address of the frag involved
20062 we must account for the offset by +8, as the OS loader will never see the reloc.
20063 see fixup_segment() in write.c
20064 The S_IS_EXTERNAL test handles the case of global symbols.
20065 Those need the calculated base, not just the pipe compensation the linker will need. */
20067 && fixP
->fx_addsy
!= NULL
20068 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20069 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
20077 /* ARM mode loads relative to PC are also offset by +8. Unlike
20078 branches, the Windows CE loader *does* expect the relocation
20079 to take this into account. */
20080 case BFD_RELOC_ARM_OFFSET_IMM
:
20081 case BFD_RELOC_ARM_OFFSET_IMM8
:
20082 case BFD_RELOC_ARM_HWLITERAL
:
20083 case BFD_RELOC_ARM_LITERAL
:
20084 case BFD_RELOC_ARM_CP_OFF_IMM
:
20088 /* Other PC-relative relocations are un-offset. */
20094 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
20095 Otherwise we have no need to default values of symbols. */
20098 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
20101 if (name
[0] == '_' && name
[1] == 'G'
20102 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
20106 if (symbol_find (name
))
20107 as_bad (_("GOT already in the symbol table"));
20109 GOT_symbol
= symbol_new (name
, undefined_section
,
20110 (valueT
) 0, & zero_address_frag
);
20120 /* Subroutine of md_apply_fix. Check to see if an immediate can be
20121 computed as two separate immediate values, added together. We
20122 already know that this value cannot be computed by just one ARM
20125 static unsigned int
20126 validate_immediate_twopart (unsigned int val
,
20127 unsigned int * highpart
)
20132 for (i
= 0; i
< 32; i
+= 2)
20133 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
20139 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
20141 else if (a
& 0xff0000)
20143 if (a
& 0xff000000)
20145 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
20149 gas_assert (a
& 0xff000000);
20150 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
20153 return (a
& 0xff) | (i
<< 7);
20160 validate_offset_imm (unsigned int val
, int hwse
)
20162 if ((hwse
&& val
> 255) || val
> 4095)
20167 /* Subroutine of md_apply_fix. Do those data_ops which can take a
20168 negative immediate constant by altering the instruction. A bit of
20173 by inverting the second operand, and
20176 by negating the second operand. */
20179 negate_data_op (unsigned long * instruction
,
20180 unsigned long value
)
20183 unsigned long negated
, inverted
;
20185 negated
= encode_arm_immediate (-value
);
20186 inverted
= encode_arm_immediate (~value
);
20188 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
20191 /* First negates. */
20192 case OPCODE_SUB
: /* ADD <-> SUB */
20193 new_inst
= OPCODE_ADD
;
20198 new_inst
= OPCODE_SUB
;
20202 case OPCODE_CMP
: /* CMP <-> CMN */
20203 new_inst
= OPCODE_CMN
;
20208 new_inst
= OPCODE_CMP
;
20212 /* Now Inverted ops. */
20213 case OPCODE_MOV
: /* MOV <-> MVN */
20214 new_inst
= OPCODE_MVN
;
20219 new_inst
= OPCODE_MOV
;
20223 case OPCODE_AND
: /* AND <-> BIC */
20224 new_inst
= OPCODE_BIC
;
20229 new_inst
= OPCODE_AND
;
20233 case OPCODE_ADC
: /* ADC <-> SBC */
20234 new_inst
= OPCODE_SBC
;
20239 new_inst
= OPCODE_ADC
;
20243 /* We cannot do anything. */
20248 if (value
== (unsigned) FAIL
)
20251 *instruction
&= OPCODE_MASK
;
20252 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
20256 /* Like negate_data_op, but for Thumb-2. */
20258 static unsigned int
20259 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
20263 unsigned int negated
, inverted
;
20265 negated
= encode_thumb32_immediate (-value
);
20266 inverted
= encode_thumb32_immediate (~value
);
20268 rd
= (*instruction
>> 8) & 0xf;
20269 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
20272 /* ADD <-> SUB. Includes CMP <-> CMN. */
20273 case T2_OPCODE_SUB
:
20274 new_inst
= T2_OPCODE_ADD
;
20278 case T2_OPCODE_ADD
:
20279 new_inst
= T2_OPCODE_SUB
;
20283 /* ORR <-> ORN. Includes MOV <-> MVN. */
20284 case T2_OPCODE_ORR
:
20285 new_inst
= T2_OPCODE_ORN
;
20289 case T2_OPCODE_ORN
:
20290 new_inst
= T2_OPCODE_ORR
;
20294 /* AND <-> BIC. TST has no inverted equivalent. */
20295 case T2_OPCODE_AND
:
20296 new_inst
= T2_OPCODE_BIC
;
20303 case T2_OPCODE_BIC
:
20304 new_inst
= T2_OPCODE_AND
;
20309 case T2_OPCODE_ADC
:
20310 new_inst
= T2_OPCODE_SBC
;
20314 case T2_OPCODE_SBC
:
20315 new_inst
= T2_OPCODE_ADC
;
20319 /* We cannot do anything. */
20324 if (value
== (unsigned int)FAIL
)
20327 *instruction
&= T2_OPCODE_MASK
;
20328 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
20332 /* Read a 32-bit thumb instruction from buf. */
20333 static unsigned long
20334 get_thumb32_insn (char * buf
)
20336 unsigned long insn
;
20337 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
20338 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20344 /* We usually want to set the low bit on the address of thumb function
20345 symbols. In particular .word foo - . should have the low bit set.
20346 Generic code tries to fold the difference of two symbols to
20347 a constant. Prevent this and force a relocation when the first symbols
20348 is a thumb function. */
20351 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
20353 if (op
== O_subtract
20354 && l
->X_op
== O_symbol
20355 && r
->X_op
== O_symbol
20356 && THUMB_IS_FUNC (l
->X_add_symbol
))
20358 l
->X_op
= O_subtract
;
20359 l
->X_op_symbol
= r
->X_add_symbol
;
20360 l
->X_add_number
-= r
->X_add_number
;
20364 /* Process as normal. */
20368 /* Encode Thumb2 unconditional branches and calls. The encoding
20369 for the 2 are identical for the immediate values. */
20372 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
20374 #define T2I1I2MASK ((1 << 13) | (1 << 11))
20377 addressT S
, I1
, I2
, lo
, hi
;
20379 S
= (value
>> 24) & 0x01;
20380 I1
= (value
>> 23) & 0x01;
20381 I2
= (value
>> 22) & 0x01;
20382 hi
= (value
>> 12) & 0x3ff;
20383 lo
= (value
>> 1) & 0x7ff;
20384 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20385 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
20386 newval
|= (S
<< 10) | hi
;
20387 newval2
&= ~T2I1I2MASK
;
20388 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
20389 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20390 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
20394 md_apply_fix (fixS
* fixP
,
20398 offsetT value
= * valP
;
20400 unsigned int newimm
;
20401 unsigned long temp
;
20403 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
20405 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
20407 /* Note whether this will delete the relocation. */
20409 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
20412 /* On a 64-bit host, silently truncate 'value' to 32 bits for
20413 consistency with the behaviour on 32-bit hosts. Remember value
20415 value
&= 0xffffffff;
20416 value
^= 0x80000000;
20417 value
-= 0x80000000;
20420 fixP
->fx_addnumber
= value
;
20422 /* Same treatment for fixP->fx_offset. */
20423 fixP
->fx_offset
&= 0xffffffff;
20424 fixP
->fx_offset
^= 0x80000000;
20425 fixP
->fx_offset
-= 0x80000000;
20427 switch (fixP
->fx_r_type
)
20429 case BFD_RELOC_NONE
:
20430 /* This will need to go in the object file. */
20434 case BFD_RELOC_ARM_IMMEDIATE
:
20435 /* We claim that this fixup has been processed here,
20436 even if in fact we generate an error because we do
20437 not have a reloc for it, so tc_gen_reloc will reject it. */
20440 if (fixP
->fx_addsy
)
20442 const char *msg
= 0;
20444 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20445 msg
= _("undefined symbol %s used as an immediate value");
20446 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20447 msg
= _("symbol %s is in a different section");
20448 else if (S_IS_WEAK (fixP
->fx_addsy
))
20449 msg
= _("symbol %s is weak and may be overridden later");
20453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20454 msg
, S_GET_NAME (fixP
->fx_addsy
));
20459 newimm
= encode_arm_immediate (value
);
20460 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20462 /* If the instruction will fail, see if we can fix things up by
20463 changing the opcode. */
20464 if (newimm
== (unsigned int) FAIL
20465 && (newimm
= negate_data_op (&temp
, value
)) == (unsigned int) FAIL
)
20467 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20468 _("invalid constant (%lx) after fixup"),
20469 (unsigned long) value
);
20473 newimm
|= (temp
& 0xfffff000);
20474 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20477 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
20479 unsigned int highpart
= 0;
20480 unsigned int newinsn
= 0xe1a00000; /* nop. */
20482 if (fixP
->fx_addsy
)
20484 const char *msg
= 0;
20486 if (! S_IS_DEFINED (fixP
->fx_addsy
))
20487 msg
= _("undefined symbol %s used as an immediate value");
20488 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
20489 msg
= _("symbol %s is in a different section");
20490 else if (S_IS_WEAK (fixP
->fx_addsy
))
20491 msg
= _("symbol %s is weak and may be overridden later");
20495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20496 msg
, S_GET_NAME (fixP
->fx_addsy
));
20501 newimm
= encode_arm_immediate (value
);
20502 temp
= md_chars_to_number (buf
, INSN_SIZE
);
20504 /* If the instruction will fail, see if we can fix things up by
20505 changing the opcode. */
20506 if (newimm
== (unsigned int) FAIL
20507 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
20509 /* No ? OK - try using two ADD instructions to generate
20511 newimm
= validate_immediate_twopart (value
, & highpart
);
20513 /* Yes - then make sure that the second instruction is
20515 if (newimm
!= (unsigned int) FAIL
)
20517 /* Still No ? Try using a negated value. */
20518 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
20519 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
20520 /* Otherwise - give up. */
20523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20524 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
20529 /* Replace the first operand in the 2nd instruction (which
20530 is the PC) with the destination register. We have
20531 already added in the PC in the first instruction and we
20532 do not want to do it again. */
20533 newinsn
&= ~ 0xf0000;
20534 newinsn
|= ((newinsn
& 0x0f000) << 4);
20537 newimm
|= (temp
& 0xfffff000);
20538 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
20540 highpart
|= (newinsn
& 0xfffff000);
20541 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
20545 case BFD_RELOC_ARM_OFFSET_IMM
:
20546 if (!fixP
->fx_done
&& seg
->use_rela_p
)
20549 case BFD_RELOC_ARM_LITERAL
:
20555 if (validate_offset_imm (value
, 0) == FAIL
)
20557 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
20558 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20559 _("invalid literal constant: pool needs to be closer"));
20561 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20562 _("bad immediate value for offset (%ld)"),
20567 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20569 newval
&= 0xfffff000;
20572 newval
&= 0xff7ff000;
20573 newval
|= value
| (sign
? INDEX_UP
: 0);
20575 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20578 case BFD_RELOC_ARM_OFFSET_IMM8
:
20579 case BFD_RELOC_ARM_HWLITERAL
:
20585 if (validate_offset_imm (value
, 1) == FAIL
)
20587 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
20588 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20589 _("invalid literal constant: pool needs to be closer"));
20591 as_bad (_("bad immediate value for 8-bit offset (%ld)"),
20596 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20598 newval
&= 0xfffff0f0;
20601 newval
&= 0xff7ff0f0;
20602 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
20604 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20607 case BFD_RELOC_ARM_T32_OFFSET_U8
:
20608 if (value
< 0 || value
> 1020 || value
% 4 != 0)
20609 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20610 _("bad immediate value for offset (%ld)"), (long) value
);
20613 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
20615 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
20618 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
20619 /* This is a complicated relocation used for all varieties of Thumb32
20620 load/store instruction with immediate offset:
20622 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
20623 *4, optional writeback(W)
20624 (doubleword load/store)
20626 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
20627 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
20628 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
20629 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
20630 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
20632 Uppercase letters indicate bits that are already encoded at
20633 this point. Lowercase letters are our problem. For the
20634 second block of instructions, the secondary opcode nybble
20635 (bits 8..11) is present, and bit 23 is zero, even if this is
20636 a PC-relative operation. */
20637 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20639 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
20641 if ((newval
& 0xf0000000) == 0xe0000000)
20643 /* Doubleword load/store: 8-bit offset, scaled by 4. */
20645 newval
|= (1 << 23);
20648 if (value
% 4 != 0)
20650 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20651 _("offset not a multiple of 4"));
20657 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20658 _("offset out of range"));
20663 else if ((newval
& 0x000f0000) == 0x000f0000)
20665 /* PC-relative, 12-bit offset. */
20667 newval
|= (1 << 23);
20672 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20673 _("offset out of range"));
20678 else if ((newval
& 0x00000100) == 0x00000100)
20680 /* Writeback: 8-bit, +/- offset. */
20682 newval
|= (1 << 9);
20687 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20688 _("offset out of range"));
20693 else if ((newval
& 0x00000f00) == 0x00000e00)
20695 /* T-instruction: positive 8-bit offset. */
20696 if (value
< 0 || value
> 0xff)
20698 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20699 _("offset out of range"));
20707 /* Positive 12-bit or negative 8-bit offset. */
20711 newval
|= (1 << 23);
20721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20722 _("offset out of range"));
20729 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
20730 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
20733 case BFD_RELOC_ARM_SHIFT_IMM
:
20734 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20735 if (((unsigned long) value
) > 32
20737 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
20739 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20740 _("shift expression is too large"));
20745 /* Shifts of zero must be done as lsl. */
20747 else if (value
== 32)
20749 newval
&= 0xfffff07f;
20750 newval
|= (value
& 0x1f) << 7;
20751 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20754 case BFD_RELOC_ARM_T32_IMMEDIATE
:
20755 case BFD_RELOC_ARM_T32_ADD_IMM
:
20756 case BFD_RELOC_ARM_T32_IMM12
:
20757 case BFD_RELOC_ARM_T32_ADD_PC12
:
20758 /* We claim that this fixup has been processed here,
20759 even if in fact we generate an error because we do
20760 not have a reloc for it, so tc_gen_reloc will reject it. */
20764 && ! S_IS_DEFINED (fixP
->fx_addsy
))
20766 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20767 _("undefined symbol %s used as an immediate value"),
20768 S_GET_NAME (fixP
->fx_addsy
));
20772 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20774 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
20777 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
20778 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20780 newimm
= encode_thumb32_immediate (value
);
20781 if (newimm
== (unsigned int) FAIL
)
20782 newimm
= thumb32_negate_data_op (&newval
, value
);
20784 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
20785 && newimm
== (unsigned int) FAIL
)
20787 /* Turn add/sum into addw/subw. */
20788 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
20789 newval
= (newval
& 0xfeffffff) | 0x02000000;
20790 /* No flat 12-bit imm encoding for addsw/subsw. */
20791 if ((newval
& 0x00100000) == 0)
20793 /* 12 bit immediate for addw/subw. */
20797 newval
^= 0x00a00000;
20800 newimm
= (unsigned int) FAIL
;
20806 if (newimm
== (unsigned int)FAIL
)
20808 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20809 _("invalid constant (%lx) after fixup"),
20810 (unsigned long) value
);
20814 newval
|= (newimm
& 0x800) << 15;
20815 newval
|= (newimm
& 0x700) << 4;
20816 newval
|= (newimm
& 0x0ff);
20818 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
20819 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
20822 case BFD_RELOC_ARM_SMC
:
20823 if (((unsigned long) value
) > 0xffff)
20824 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20825 _("invalid smc expression"));
20826 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20827 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20828 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20831 case BFD_RELOC_ARM_HVC
:
20832 if (((unsigned long) value
) > 0xffff)
20833 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20834 _("invalid hvc expression"));
20835 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20836 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
20837 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20840 case BFD_RELOC_ARM_SWI
:
20841 if (fixP
->tc_fix_data
!= 0)
20843 if (((unsigned long) value
) > 0xff)
20844 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20845 _("invalid swi expression"));
20846 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20848 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20852 if (((unsigned long) value
) > 0x00ffffff)
20853 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20854 _("invalid swi expression"));
20855 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20857 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20861 case BFD_RELOC_ARM_MULTI
:
20862 if (((unsigned long) value
) > 0xffff)
20863 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20864 _("invalid expression in load/store multiple"));
20865 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
20866 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20870 case BFD_RELOC_ARM_PCREL_CALL
:
20872 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20874 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20875 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20876 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20877 /* Flip the bl to blx. This is a simple flip
20878 bit here because we generate PCREL_CALL for
20879 unconditional bls. */
20881 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20882 newval
= newval
| 0x10000000;
20883 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20889 goto arm_branch_common
;
20891 case BFD_RELOC_ARM_PCREL_JUMP
:
20892 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20894 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20895 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20896 && THUMB_IS_FUNC (fixP
->fx_addsy
))
20898 /* This would map to a bl<cond>, b<cond>,
20899 b<always> to a Thumb function. We
20900 need to force a relocation for this particular
20902 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20906 case BFD_RELOC_ARM_PLT32
:
20908 case BFD_RELOC_ARM_PCREL_BRANCH
:
20910 goto arm_branch_common
;
20912 case BFD_RELOC_ARM_PCREL_BLX
:
20915 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
20917 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
20918 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
20919 && ARM_IS_FUNC (fixP
->fx_addsy
))
20921 /* Flip the blx to a bl and warn. */
20922 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
20923 newval
= 0xeb000000;
20924 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
20925 _("blx to '%s' an ARM ISA state function changed to bl"),
20927 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20933 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
20934 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
20938 /* We are going to store value (shifted right by two) in the
20939 instruction, in a 24 bit, signed field. Bits 26 through 32 either
20940 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
20941 also be be clear. */
20943 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20944 _("misaligned branch destination"));
20945 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
20946 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
20947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20948 _("branch out of range"));
20950 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20952 newval
= md_chars_to_number (buf
, INSN_SIZE
);
20953 newval
|= (value
>> 2) & 0x00ffffff;
20954 /* Set the H bit on BLX instructions. */
20958 newval
|= 0x01000000;
20960 newval
&= ~0x01000000;
20962 md_number_to_chars (buf
, newval
, INSN_SIZE
);
20966 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
20967 /* CBZ can only branch forward. */
20969 /* Attempts to use CBZ to branch to the next instruction
20970 (which, strictly speaking, are prohibited) will be turned into
20973 FIXME: It may be better to remove the instruction completely and
20974 perform relaxation. */
20977 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20978 newval
= 0xbf00; /* NOP encoding T1 */
20979 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20984 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20985 _("branch out of range"));
20987 if (fixP
->fx_done
|| !seg
->use_rela_p
)
20989 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
20990 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
20991 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
20996 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
20997 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
20998 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
20999 _("branch out of range"));
21001 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21003 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21004 newval
|= (value
& 0x1ff) >> 1;
21005 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21009 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
21010 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
21011 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21012 _("branch out of range"));
21014 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21016 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21017 newval
|= (value
& 0xfff) >> 1;
21018 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21022 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21024 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21025 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21026 && ARM_IS_FUNC (fixP
->fx_addsy
)
21027 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21029 /* Force a relocation for a branch 20 bits wide. */
21032 if ((value
& ~0x1fffff) && ((value
& ~0x1fffff) != ~0x1fffff))
21033 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21034 _("conditional branch out of range"));
21036 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21039 addressT S
, J1
, J2
, lo
, hi
;
21041 S
= (value
& 0x00100000) >> 20;
21042 J2
= (value
& 0x00080000) >> 19;
21043 J1
= (value
& 0x00040000) >> 18;
21044 hi
= (value
& 0x0003f000) >> 12;
21045 lo
= (value
& 0x00000ffe) >> 1;
21047 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21048 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21049 newval
|= (S
<< 10) | hi
;
21050 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
21051 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21052 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
21056 case BFD_RELOC_THUMB_PCREL_BLX
:
21058 /* If there is a blx from a thumb state function to
21059 another thumb function flip this to a bl and warn
21063 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21064 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21065 && THUMB_IS_FUNC (fixP
->fx_addsy
))
21067 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
21068 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
21069 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
21071 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21072 newval
= newval
| 0x1000;
21073 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21074 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21079 goto thumb_bl_common
;
21081 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21083 /* A bl from Thumb state ISA to an internal ARM state function
21084 is converted to a blx. */
21086 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
21087 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
21088 && ARM_IS_FUNC (fixP
->fx_addsy
)
21089 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
21091 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
21092 newval
= newval
& ~0x1000;
21093 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
21094 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
21101 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
&&
21102 fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21103 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21106 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
21107 /* For a BLX instruction, make sure that the relocation is rounded up
21108 to a word boundary. This follows the semantics of the instruction
21109 which specifies that bit 1 of the target address will come from bit
21110 1 of the base address. */
21111 value
= (value
+ 1) & ~ 1;
21114 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
21116 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_arch_t2
)))
21118 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21119 _("branch out of range"));
21121 else if ((value
& ~0x1ffffff)
21122 && ((value
& ~0x1ffffff) != ~0x1ffffff))
21124 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21125 _("Thumb2 branch out of range"));
21129 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21130 encode_thumb2_b_bl_offset (buf
, value
);
21134 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21135 if ((value
& ~0x1ffffff) && ((value
& ~0x1ffffff) != ~0x1ffffff))
21136 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21137 _("branch out of range"));
21139 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21140 encode_thumb2_b_bl_offset (buf
, value
);
21145 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21146 md_number_to_chars (buf
, value
, 1);
21150 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21151 md_number_to_chars (buf
, value
, 2);
21155 case BFD_RELOC_ARM_TLS_CALL
:
21156 case BFD_RELOC_ARM_THM_TLS_CALL
:
21157 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21158 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21159 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21162 case BFD_RELOC_ARM_TLS_GOTDESC
:
21163 case BFD_RELOC_ARM_TLS_GD32
:
21164 case BFD_RELOC_ARM_TLS_LE32
:
21165 case BFD_RELOC_ARM_TLS_IE32
:
21166 case BFD_RELOC_ARM_TLS_LDM32
:
21167 case BFD_RELOC_ARM_TLS_LDO32
:
21168 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
21171 case BFD_RELOC_ARM_GOT32
:
21172 case BFD_RELOC_ARM_GOTOFF
:
21173 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21174 md_number_to_chars (buf
, 0, 4);
21177 case BFD_RELOC_ARM_GOT_PREL
:
21178 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21179 md_number_to_chars (buf
, value
, 4);
21182 case BFD_RELOC_ARM_TARGET2
:
21183 /* TARGET2 is not partial-inplace, so we need to write the
21184 addend here for REL targets, because it won't be written out
21185 during reloc processing later. */
21186 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21187 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
21191 case BFD_RELOC_RVA
:
21193 case BFD_RELOC_ARM_TARGET1
:
21194 case BFD_RELOC_ARM_ROSEGREL32
:
21195 case BFD_RELOC_ARM_SBREL32
:
21196 case BFD_RELOC_32_PCREL
:
21198 case BFD_RELOC_32_SECREL
:
21200 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21202 /* For WinCE we only do this for pcrel fixups. */
21203 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
21205 md_number_to_chars (buf
, value
, 4);
21209 case BFD_RELOC_ARM_PREL31
:
21210 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21212 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
21213 if ((value
^ (value
>> 1)) & 0x40000000)
21215 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21216 _("rel31 relocation overflow"));
21218 newval
|= value
& 0x7fffffff;
21219 md_number_to_chars (buf
, newval
, 4);
21224 case BFD_RELOC_ARM_CP_OFF_IMM
:
21225 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
21226 if (value
< -1023 || value
> 1023 || (value
& 3))
21227 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21228 _("co-processor offset out of range"));
21233 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21234 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21235 newval
= md_chars_to_number (buf
, INSN_SIZE
);
21237 newval
= get_thumb32_insn (buf
);
21239 newval
&= 0xffffff00;
21242 newval
&= 0xff7fff00;
21243 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
21245 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
21246 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
21247 md_number_to_chars (buf
, newval
, INSN_SIZE
);
21249 put_thumb32_insn (buf
, newval
);
21252 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
21253 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
21254 if (value
< -255 || value
> 255)
21255 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21256 _("co-processor offset out of range"));
21258 goto cp_off_common
;
21260 case BFD_RELOC_ARM_THUMB_OFFSET
:
21261 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21262 /* Exactly what ranges, and where the offset is inserted depends
21263 on the type of instruction, we can establish this from the
21265 switch (newval
>> 12)
21267 case 4: /* PC load. */
21268 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
21269 forced to zero for these loads; md_pcrel_from has already
21270 compensated for this. */
21272 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21273 _("invalid offset, target not word aligned (0x%08lX)"),
21274 (((unsigned long) fixP
->fx_frag
->fr_address
21275 + (unsigned long) fixP
->fx_where
) & ~3)
21276 + (unsigned long) value
);
21278 if (value
& ~0x3fc)
21279 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21280 _("invalid offset, value too big (0x%08lX)"),
21283 newval
|= value
>> 2;
21286 case 9: /* SP load/store. */
21287 if (value
& ~0x3fc)
21288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21289 _("invalid offset, value too big (0x%08lX)"),
21291 newval
|= value
>> 2;
21294 case 6: /* Word load/store. */
21296 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21297 _("invalid offset, value too big (0x%08lX)"),
21299 newval
|= value
<< 4; /* 6 - 2. */
21302 case 7: /* Byte load/store. */
21304 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21305 _("invalid offset, value too big (0x%08lX)"),
21307 newval
|= value
<< 6;
21310 case 8: /* Halfword load/store. */
21312 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21313 _("invalid offset, value too big (0x%08lX)"),
21315 newval
|= value
<< 5; /* 6 - 1. */
21319 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21320 "Unable to process relocation for thumb opcode: %lx",
21321 (unsigned long) newval
);
21324 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21327 case BFD_RELOC_ARM_THUMB_ADD
:
21328 /* This is a complicated relocation, since we use it for all of
21329 the following immediate relocations:
21333 9bit ADD/SUB SP word-aligned
21334 10bit ADD PC/SP word-aligned
21336 The type of instruction being processed is encoded in the
21343 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21345 int rd
= (newval
>> 4) & 0xf;
21346 int rs
= newval
& 0xf;
21347 int subtract
= !!(newval
& 0x8000);
21349 /* Check for HI regs, only very restricted cases allowed:
21350 Adjusting SP, and using PC or SP to get an address. */
21351 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
21352 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
21353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21354 _("invalid Hi register with immediate"));
21356 /* If value is negative, choose the opposite instruction. */
21360 subtract
= !subtract
;
21362 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21363 _("immediate value out of range"));
21368 if (value
& ~0x1fc)
21369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21370 _("invalid immediate for stack address calculation"));
21371 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
21372 newval
|= value
>> 2;
21374 else if (rs
== REG_PC
|| rs
== REG_SP
)
21376 if (subtract
|| value
& ~0x3fc)
21377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21378 _("invalid immediate for address calculation (value = 0x%08lX)"),
21379 (unsigned long) value
);
21380 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
21382 newval
|= value
>> 2;
21387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21388 _("immediate value out of range"));
21389 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
21390 newval
|= (rd
<< 8) | value
;
21395 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21396 _("immediate value out of range"));
21397 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
21398 newval
|= rd
| (rs
<< 3) | (value
<< 6);
21401 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21404 case BFD_RELOC_ARM_THUMB_IMM
:
21405 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
21406 if (value
< 0 || value
> 255)
21407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21408 _("invalid immediate: %ld is out of range"),
21411 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21414 case BFD_RELOC_ARM_THUMB_SHIFT
:
21415 /* 5bit shift value (0..32). LSL cannot take 32. */
21416 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
21417 temp
= newval
& 0xf800;
21418 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
21419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21420 _("invalid shift value: %ld"), (long) value
);
21421 /* Shifts of zero must be encoded as LSL. */
21423 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
21424 /* Shifts of 32 are encoded as zero. */
21425 else if (value
== 32)
21427 newval
|= value
<< 6;
21428 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
21431 case BFD_RELOC_VTABLE_INHERIT
:
21432 case BFD_RELOC_VTABLE_ENTRY
:
21436 case BFD_RELOC_ARM_MOVW
:
21437 case BFD_RELOC_ARM_MOVT
:
21438 case BFD_RELOC_ARM_THUMB_MOVW
:
21439 case BFD_RELOC_ARM_THUMB_MOVT
:
21440 if (fixP
->fx_done
|| !seg
->use_rela_p
)
21442 /* REL format relocations are limited to a 16-bit addend. */
21443 if (!fixP
->fx_done
)
21445 if (value
< -0x8000 || value
> 0x7fff)
21446 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21447 _("offset out of range"));
21449 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
21450 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21455 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
21456 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
21458 newval
= get_thumb32_insn (buf
);
21459 newval
&= 0xfbf08f00;
21460 newval
|= (value
& 0xf000) << 4;
21461 newval
|= (value
& 0x0800) << 15;
21462 newval
|= (value
& 0x0700) << 4;
21463 newval
|= (value
& 0x00ff);
21464 put_thumb32_insn (buf
, newval
);
21468 newval
= md_chars_to_number (buf
, 4);
21469 newval
&= 0xfff0f000;
21470 newval
|= value
& 0x0fff;
21471 newval
|= (value
& 0xf000) << 4;
21472 md_number_to_chars (buf
, newval
, 4);
21477 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21478 case BFD_RELOC_ARM_ALU_PC_G0
:
21479 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21480 case BFD_RELOC_ARM_ALU_PC_G1
:
21481 case BFD_RELOC_ARM_ALU_PC_G2
:
21482 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21483 case BFD_RELOC_ARM_ALU_SB_G0
:
21484 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21485 case BFD_RELOC_ARM_ALU_SB_G1
:
21486 case BFD_RELOC_ARM_ALU_SB_G2
:
21487 gas_assert (!fixP
->fx_done
);
21488 if (!seg
->use_rela_p
)
21491 bfd_vma encoded_addend
;
21492 bfd_vma addend_abs
= abs (value
);
21494 /* Check that the absolute value of the addend can be
21495 expressed as an 8-bit constant plus a rotation. */
21496 encoded_addend
= encode_arm_immediate (addend_abs
);
21497 if (encoded_addend
== (unsigned int) FAIL
)
21498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21499 _("the offset 0x%08lX is not representable"),
21500 (unsigned long) addend_abs
);
21502 /* Extract the instruction. */
21503 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21505 /* If the addend is positive, use an ADD instruction.
21506 Otherwise use a SUB. Take care not to destroy the S bit. */
21507 insn
&= 0xff1fffff;
21513 /* Place the encoded addend into the first 12 bits of the
21515 insn
&= 0xfffff000;
21516 insn
|= encoded_addend
;
21518 /* Update the instruction. */
21519 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21523 case BFD_RELOC_ARM_LDR_PC_G0
:
21524 case BFD_RELOC_ARM_LDR_PC_G1
:
21525 case BFD_RELOC_ARM_LDR_PC_G2
:
21526 case BFD_RELOC_ARM_LDR_SB_G0
:
21527 case BFD_RELOC_ARM_LDR_SB_G1
:
21528 case BFD_RELOC_ARM_LDR_SB_G2
:
21529 gas_assert (!fixP
->fx_done
);
21530 if (!seg
->use_rela_p
)
21533 bfd_vma addend_abs
= abs (value
);
21535 /* Check that the absolute value of the addend can be
21536 encoded in 12 bits. */
21537 if (addend_abs
>= 0x1000)
21538 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21539 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
21540 (unsigned long) addend_abs
);
21542 /* Extract the instruction. */
21543 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21545 /* If the addend is negative, clear bit 23 of the instruction.
21546 Otherwise set it. */
21548 insn
&= ~(1 << 23);
21552 /* Place the absolute value of the addend into the first 12 bits
21553 of the instruction. */
21554 insn
&= 0xfffff000;
21555 insn
|= addend_abs
;
21557 /* Update the instruction. */
21558 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21562 case BFD_RELOC_ARM_LDRS_PC_G0
:
21563 case BFD_RELOC_ARM_LDRS_PC_G1
:
21564 case BFD_RELOC_ARM_LDRS_PC_G2
:
21565 case BFD_RELOC_ARM_LDRS_SB_G0
:
21566 case BFD_RELOC_ARM_LDRS_SB_G1
:
21567 case BFD_RELOC_ARM_LDRS_SB_G2
:
21568 gas_assert (!fixP
->fx_done
);
21569 if (!seg
->use_rela_p
)
21572 bfd_vma addend_abs
= abs (value
);
21574 /* Check that the absolute value of the addend can be
21575 encoded in 8 bits. */
21576 if (addend_abs
>= 0x100)
21577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21578 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
21579 (unsigned long) addend_abs
);
21581 /* Extract the instruction. */
21582 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21584 /* If the addend is negative, clear bit 23 of the instruction.
21585 Otherwise set it. */
21587 insn
&= ~(1 << 23);
21591 /* Place the first four bits of the absolute value of the addend
21592 into the first 4 bits of the instruction, and the remaining
21593 four into bits 8 .. 11. */
21594 insn
&= 0xfffff0f0;
21595 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
21597 /* Update the instruction. */
21598 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21602 case BFD_RELOC_ARM_LDC_PC_G0
:
21603 case BFD_RELOC_ARM_LDC_PC_G1
:
21604 case BFD_RELOC_ARM_LDC_PC_G2
:
21605 case BFD_RELOC_ARM_LDC_SB_G0
:
21606 case BFD_RELOC_ARM_LDC_SB_G1
:
21607 case BFD_RELOC_ARM_LDC_SB_G2
:
21608 gas_assert (!fixP
->fx_done
);
21609 if (!seg
->use_rela_p
)
21612 bfd_vma addend_abs
= abs (value
);
21614 /* Check that the absolute value of the addend is a multiple of
21615 four and, when divided by four, fits in 8 bits. */
21616 if (addend_abs
& 0x3)
21617 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21618 _("bad offset 0x%08lX (must be word-aligned)"),
21619 (unsigned long) addend_abs
);
21621 if ((addend_abs
>> 2) > 0xff)
21622 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21623 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
21624 (unsigned long) addend_abs
);
21626 /* Extract the instruction. */
21627 insn
= md_chars_to_number (buf
, INSN_SIZE
);
21629 /* If the addend is negative, clear bit 23 of the instruction.
21630 Otherwise set it. */
21632 insn
&= ~(1 << 23);
21636 /* Place the addend (divided by four) into the first eight
21637 bits of the instruction. */
21638 insn
&= 0xfffffff0;
21639 insn
|= addend_abs
>> 2;
21641 /* Update the instruction. */
21642 md_number_to_chars (buf
, insn
, INSN_SIZE
);
21646 case BFD_RELOC_ARM_V4BX
:
21647 /* This will need to go in the object file. */
21651 case BFD_RELOC_UNUSED
:
21653 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
21654 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
21658 /* Translate internal representation of relocation info to BFD target
21662 tc_gen_reloc (asection
*section
, fixS
*fixp
)
21665 bfd_reloc_code_real_type code
;
21667 reloc
= (arelent
*) xmalloc (sizeof (arelent
));
21669 reloc
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
21670 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
21671 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
21673 if (fixp
->fx_pcrel
)
21675 if (section
->use_rela_p
)
21676 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
21678 fixp
->fx_offset
= reloc
->address
;
21680 reloc
->addend
= fixp
->fx_offset
;
21682 switch (fixp
->fx_r_type
)
21685 if (fixp
->fx_pcrel
)
21687 code
= BFD_RELOC_8_PCREL
;
21692 if (fixp
->fx_pcrel
)
21694 code
= BFD_RELOC_16_PCREL
;
21699 if (fixp
->fx_pcrel
)
21701 code
= BFD_RELOC_32_PCREL
;
21705 case BFD_RELOC_ARM_MOVW
:
21706 if (fixp
->fx_pcrel
)
21708 code
= BFD_RELOC_ARM_MOVW_PCREL
;
21712 case BFD_RELOC_ARM_MOVT
:
21713 if (fixp
->fx_pcrel
)
21715 code
= BFD_RELOC_ARM_MOVT_PCREL
;
21719 case BFD_RELOC_ARM_THUMB_MOVW
:
21720 if (fixp
->fx_pcrel
)
21722 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
21726 case BFD_RELOC_ARM_THUMB_MOVT
:
21727 if (fixp
->fx_pcrel
)
21729 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
21733 case BFD_RELOC_NONE
:
21734 case BFD_RELOC_ARM_PCREL_BRANCH
:
21735 case BFD_RELOC_ARM_PCREL_BLX
:
21736 case BFD_RELOC_RVA
:
21737 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
21738 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
21739 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
21740 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
21741 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
21742 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
21743 case BFD_RELOC_VTABLE_ENTRY
:
21744 case BFD_RELOC_VTABLE_INHERIT
:
21746 case BFD_RELOC_32_SECREL
:
21748 code
= fixp
->fx_r_type
;
21751 case BFD_RELOC_THUMB_PCREL_BLX
:
21753 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
21754 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
21757 code
= BFD_RELOC_THUMB_PCREL_BLX
;
21760 case BFD_RELOC_ARM_LITERAL
:
21761 case BFD_RELOC_ARM_HWLITERAL
:
21762 /* If this is called then the a literal has
21763 been referenced across a section boundary. */
21764 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21765 _("literal referenced across section boundary"));
21769 case BFD_RELOC_ARM_TLS_CALL
:
21770 case BFD_RELOC_ARM_THM_TLS_CALL
:
21771 case BFD_RELOC_ARM_TLS_DESCSEQ
:
21772 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
21773 case BFD_RELOC_ARM_GOT32
:
21774 case BFD_RELOC_ARM_GOTOFF
:
21775 case BFD_RELOC_ARM_GOT_PREL
:
21776 case BFD_RELOC_ARM_PLT32
:
21777 case BFD_RELOC_ARM_TARGET1
:
21778 case BFD_RELOC_ARM_ROSEGREL32
:
21779 case BFD_RELOC_ARM_SBREL32
:
21780 case BFD_RELOC_ARM_PREL31
:
21781 case BFD_RELOC_ARM_TARGET2
:
21782 case BFD_RELOC_ARM_TLS_LE32
:
21783 case BFD_RELOC_ARM_TLS_LDO32
:
21784 case BFD_RELOC_ARM_PCREL_CALL
:
21785 case BFD_RELOC_ARM_PCREL_JUMP
:
21786 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
21787 case BFD_RELOC_ARM_ALU_PC_G0
:
21788 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
21789 case BFD_RELOC_ARM_ALU_PC_G1
:
21790 case BFD_RELOC_ARM_ALU_PC_G2
:
21791 case BFD_RELOC_ARM_LDR_PC_G0
:
21792 case BFD_RELOC_ARM_LDR_PC_G1
:
21793 case BFD_RELOC_ARM_LDR_PC_G2
:
21794 case BFD_RELOC_ARM_LDRS_PC_G0
:
21795 case BFD_RELOC_ARM_LDRS_PC_G1
:
21796 case BFD_RELOC_ARM_LDRS_PC_G2
:
21797 case BFD_RELOC_ARM_LDC_PC_G0
:
21798 case BFD_RELOC_ARM_LDC_PC_G1
:
21799 case BFD_RELOC_ARM_LDC_PC_G2
:
21800 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
21801 case BFD_RELOC_ARM_ALU_SB_G0
:
21802 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
21803 case BFD_RELOC_ARM_ALU_SB_G1
:
21804 case BFD_RELOC_ARM_ALU_SB_G2
:
21805 case BFD_RELOC_ARM_LDR_SB_G0
:
21806 case BFD_RELOC_ARM_LDR_SB_G1
:
21807 case BFD_RELOC_ARM_LDR_SB_G2
:
21808 case BFD_RELOC_ARM_LDRS_SB_G0
:
21809 case BFD_RELOC_ARM_LDRS_SB_G1
:
21810 case BFD_RELOC_ARM_LDRS_SB_G2
:
21811 case BFD_RELOC_ARM_LDC_SB_G0
:
21812 case BFD_RELOC_ARM_LDC_SB_G1
:
21813 case BFD_RELOC_ARM_LDC_SB_G2
:
21814 case BFD_RELOC_ARM_V4BX
:
21815 code
= fixp
->fx_r_type
;
21818 case BFD_RELOC_ARM_TLS_GOTDESC
:
21819 case BFD_RELOC_ARM_TLS_GD32
:
21820 case BFD_RELOC_ARM_TLS_IE32
:
21821 case BFD_RELOC_ARM_TLS_LDM32
:
21822 /* BFD will include the symbol's address in the addend.
21823 But we don't want that, so subtract it out again here. */
21824 if (!S_IS_COMMON (fixp
->fx_addsy
))
21825 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
21826 code
= fixp
->fx_r_type
;
21830 case BFD_RELOC_ARM_IMMEDIATE
:
21831 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21832 _("internal relocation (type: IMMEDIATE) not fixed up"));
21835 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
21836 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21837 _("ADRL used for a symbol not defined in the same file"));
21840 case BFD_RELOC_ARM_OFFSET_IMM
:
21841 if (section
->use_rela_p
)
21843 code
= fixp
->fx_r_type
;
21847 if (fixp
->fx_addsy
!= NULL
21848 && !S_IS_DEFINED (fixp
->fx_addsy
)
21849 && S_IS_LOCAL (fixp
->fx_addsy
))
21851 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21852 _("undefined local label `%s'"),
21853 S_GET_NAME (fixp
->fx_addsy
));
21857 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21858 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
21865 switch (fixp
->fx_r_type
)
21867 case BFD_RELOC_NONE
: type
= "NONE"; break;
21868 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
21869 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
21870 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
21871 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
21872 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
21873 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
21874 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
21875 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
21876 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
21877 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
21878 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
21879 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
21880 default: type
= _("<unknown>"); break;
21882 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21883 _("cannot represent %s relocation in this object file format"),
21890 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
21892 && fixp
->fx_addsy
== GOT_symbol
)
21894 code
= BFD_RELOC_ARM_GOTPC
;
21895 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
21899 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
21901 if (reloc
->howto
== NULL
)
21903 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
21904 _("cannot represent %s relocation in this object file format"),
21905 bfd_get_reloc_code_name (code
));
21909 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
21910 vtable entry to be used in the relocation's section offset. */
21911 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
21912 reloc
->address
= fixp
->fx_offset
;
21917 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
21920 cons_fix_new_arm (fragS
* frag
,
21925 bfd_reloc_code_real_type type
;
21929 FIXME: @@ Should look at CPU word size. */
21933 type
= BFD_RELOC_8
;
21936 type
= BFD_RELOC_16
;
21940 type
= BFD_RELOC_32
;
21943 type
= BFD_RELOC_64
;
21948 if (exp
->X_op
== O_secrel
)
21950 exp
->X_op
= O_symbol
;
21951 type
= BFD_RELOC_32_SECREL
;
21955 fix_new_exp (frag
, where
, (int) size
, exp
, pcrel
, type
);
21958 #if defined (OBJ_COFF)
21960 arm_validate_fix (fixS
* fixP
)
21962 /* If the destination of the branch is a defined symbol which does not have
21963 the THUMB_FUNC attribute, then we must be calling a function which has
21964 the (interfacearm) attribute. We look for the Thumb entry point to that
21965 function and change the branch to refer to that function instead. */
21966 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
21967 && fixP
->fx_addsy
!= NULL
21968 && S_IS_DEFINED (fixP
->fx_addsy
)
21969 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
21971 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
21978 arm_force_relocation (struct fix
* fixp
)
21980 #if defined (OBJ_COFF) && defined (TE_PE)
21981 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
21985 /* In case we have a call or a branch to a function in ARM ISA mode from
21986 a thumb function or vice-versa force the relocation. These relocations
21987 are cleared off for some cores that might have blx and simple transformations
21991 switch (fixp
->fx_r_type
)
21993 case BFD_RELOC_ARM_PCREL_JUMP
:
21994 case BFD_RELOC_ARM_PCREL_CALL
:
21995 case BFD_RELOC_THUMB_PCREL_BLX
:
21996 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
22000 case BFD_RELOC_ARM_PCREL_BLX
:
22001 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22002 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22003 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22004 if (ARM_IS_FUNC (fixp
->fx_addsy
))
22013 /* Resolve these relocations even if the symbol is extern or weak.
22014 Technically this is probably wrong due to symbol preemption.
22015 In practice these relocations do not have enough range to be useful
22016 at dynamic link time, and some code (e.g. in the Linux kernel)
22017 expects these references to be resolved. */
22018 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
22019 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
22020 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
22021 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
22022 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
22023 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
22024 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
22025 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
22026 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
22027 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
22028 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
22029 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
22030 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
22031 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
22034 /* Always leave these relocations for the linker. */
22035 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22036 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22037 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22040 /* Always generate relocations against function symbols. */
22041 if (fixp
->fx_r_type
== BFD_RELOC_32
22043 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
22046 return generic_force_reloc (fixp
);
22049 #if defined (OBJ_ELF) || defined (OBJ_COFF)
22050 /* Relocations against function names must be left unadjusted,
22051 so that the linker can use this information to generate interworking
22052 stubs. The MIPS version of this function
22053 also prevents relocations that are mips-16 specific, but I do not
22054 know why it does this.
22057 There is one other problem that ought to be addressed here, but
22058 which currently is not: Taking the address of a label (rather
22059 than a function) and then later jumping to that address. Such
22060 addresses also ought to have their bottom bit set (assuming that
22061 they reside in Thumb code), but at the moment they will not. */
22064 arm_fix_adjustable (fixS
* fixP
)
22066 if (fixP
->fx_addsy
== NULL
)
22069 /* Preserve relocations against symbols with function type. */
22070 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
22073 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
22074 && fixP
->fx_subsy
== NULL
)
22077 /* We need the symbol name for the VTABLE entries. */
22078 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
22079 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
22082 /* Don't allow symbols to be discarded on GOT related relocs. */
22083 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
22084 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
22085 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
22086 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
22087 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
22088 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
22089 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
22090 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
22091 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
22092 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
22093 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
22094 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
22095 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
22096 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
22099 /* Similarly for group relocations. */
22100 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
22101 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
22102 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
22105 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
22106 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
22107 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
22108 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
22109 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
22110 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
22111 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
22112 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
22113 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
22118 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
22123 elf32_arm_target_format (void)
22126 return (target_big_endian
22127 ? "elf32-bigarm-symbian"
22128 : "elf32-littlearm-symbian");
22129 #elif defined (TE_VXWORKS)
22130 return (target_big_endian
22131 ? "elf32-bigarm-vxworks"
22132 : "elf32-littlearm-vxworks");
22134 if (target_big_endian
)
22135 return "elf32-bigarm";
22137 return "elf32-littlearm";
22142 armelf_frob_symbol (symbolS
* symp
,
22145 elf_frob_symbol (symp
, puntp
);
22149 /* MD interface: Finalization. */
22154 literal_pool
* pool
;
22156 /* Ensure that all the IT blocks are properly closed. */
22157 check_it_blocks_finished ();
22159 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
22161 /* Put it at the end of the relevant section. */
22162 subseg_set (pool
->section
, pool
->sub_section
);
22164 arm_elf_change_section ();
22171 /* Remove any excess mapping symbols generated for alignment frags in
22172 SEC. We may have created a mapping symbol before a zero byte
22173 alignment; remove it if there's a mapping symbol after the
22176 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
22177 void *dummy ATTRIBUTE_UNUSED
)
22179 segment_info_type
*seginfo
= seg_info (sec
);
22182 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
22185 for (fragp
= seginfo
->frchainP
->frch_root
;
22187 fragp
= fragp
->fr_next
)
22189 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
22190 fragS
*next
= fragp
->fr_next
;
22192 /* Variable-sized frags have been converted to fixed size by
22193 this point. But if this was variable-sized to start with,
22194 there will be a fixed-size frag after it. So don't handle
22196 if (sym
== NULL
|| next
== NULL
)
22199 if (S_GET_VALUE (sym
) < next
->fr_address
)
22200 /* Not at the end of this frag. */
22202 know (S_GET_VALUE (sym
) == next
->fr_address
);
22206 if (next
->tc_frag_data
.first_map
!= NULL
)
22208 /* Next frag starts with a mapping symbol. Discard this
22210 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22214 if (next
->fr_next
== NULL
)
22216 /* This mapping symbol is at the end of the section. Discard
22218 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
22219 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
22223 /* As long as we have empty frags without any mapping symbols,
22225 /* If the next frag is non-empty and does not start with a
22226 mapping symbol, then this mapping symbol is required. */
22227 if (next
->fr_address
!= next
->fr_next
->fr_address
)
22230 next
= next
->fr_next
;
22232 while (next
!= NULL
);
22237 /* Adjust the symbol table. This marks Thumb symbols as distinct from
22241 arm_adjust_symtab (void)
22246 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22248 if (ARM_IS_THUMB (sym
))
22250 if (THUMB_IS_FUNC (sym
))
22252 /* Mark the symbol as a Thumb function. */
22253 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
22254 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
22255 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
22257 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
22258 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
22260 as_bad (_("%s: unexpected function type: %d"),
22261 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
22263 else switch (S_GET_STORAGE_CLASS (sym
))
22266 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
22269 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
22272 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
22280 if (ARM_IS_INTERWORK (sym
))
22281 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
22288 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
22290 if (ARM_IS_THUMB (sym
))
22292 elf_symbol_type
* elf_sym
;
22294 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
22295 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
22297 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
22298 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
22300 /* If it's a .thumb_func, declare it as so,
22301 otherwise tag label as .code 16. */
22302 if (THUMB_IS_FUNC (sym
))
22303 elf_sym
->internal_elf_sym
.st_target_internal
22304 = ST_BRANCH_TO_THUMB
;
22305 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
22306 elf_sym
->internal_elf_sym
.st_info
=
22307 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
22312 /* Remove any overlapping mapping symbols generated by alignment frags. */
22313 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
22314 /* Now do generic ELF adjustments. */
22315 elf_adjust_symtab ();
22319 /* MD interface: Initialization. */
22322 set_constant_flonums (void)
22326 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
22327 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
22331 /* Auto-select Thumb mode if it's the only available instruction set for the
22332 given architecture. */
22335 autoselect_thumb_from_cpu_variant (void)
22337 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22338 opcode_select (16);
22347 if ( (arm_ops_hsh
= hash_new ()) == NULL
22348 || (arm_cond_hsh
= hash_new ()) == NULL
22349 || (arm_shift_hsh
= hash_new ()) == NULL
22350 || (arm_psr_hsh
= hash_new ()) == NULL
22351 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
22352 || (arm_reg_hsh
= hash_new ()) == NULL
22353 || (arm_reloc_hsh
= hash_new ()) == NULL
22354 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
22355 as_fatal (_("virtual memory exhausted"));
22357 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
22358 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
22359 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
22360 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
22361 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
22362 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
22363 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
22364 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
22365 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
22366 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
22367 (void *) (v7m_psrs
+ i
));
22368 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
22369 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
22371 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
22373 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
22374 (void *) (barrier_opt_names
+ i
));
22376 for (i
= 0; i
< sizeof (reloc_names
) / sizeof (struct reloc_entry
); i
++)
22377 hash_insert (arm_reloc_hsh
, reloc_names
[i
].name
, (void *) (reloc_names
+ i
));
22380 set_constant_flonums ();
22382 /* Set the cpu variant based on the command-line options. We prefer
22383 -mcpu= over -march= if both are set (as for GCC); and we prefer
22384 -mfpu= over any other way of setting the floating point unit.
22385 Use of legacy options with new options are faulted. */
22388 if (mcpu_cpu_opt
|| march_cpu_opt
)
22389 as_bad (_("use of old and new-style options to set CPU type"));
22391 mcpu_cpu_opt
= legacy_cpu
;
22393 else if (!mcpu_cpu_opt
)
22394 mcpu_cpu_opt
= march_cpu_opt
;
22399 as_bad (_("use of old and new-style options to set FPU type"));
22401 mfpu_opt
= legacy_fpu
;
22403 else if (!mfpu_opt
)
22405 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
22406 || defined (TE_NetBSD) || defined (TE_VXWORKS))
22407 /* Some environments specify a default FPU. If they don't, infer it
22408 from the processor. */
22410 mfpu_opt
= mcpu_fpu_opt
;
22412 mfpu_opt
= march_fpu_opt
;
22414 mfpu_opt
= &fpu_default
;
22420 if (mcpu_cpu_opt
!= NULL
)
22421 mfpu_opt
= &fpu_default
;
22422 else if (mcpu_fpu_opt
!= NULL
&& ARM_CPU_HAS_FEATURE (*mcpu_fpu_opt
, arm_ext_v5
))
22423 mfpu_opt
= &fpu_arch_vfp_v2
;
22425 mfpu_opt
= &fpu_arch_fpa
;
22431 mcpu_cpu_opt
= &cpu_default
;
22432 selected_cpu
= cpu_default
;
22436 selected_cpu
= *mcpu_cpu_opt
;
22438 mcpu_cpu_opt
= &arm_arch_any
;
22441 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
22443 autoselect_thumb_from_cpu_variant ();
22445 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
22447 #if defined OBJ_COFF || defined OBJ_ELF
22449 unsigned int flags
= 0;
22451 #if defined OBJ_ELF
22452 flags
= meabi_flags
;
22454 switch (meabi_flags
)
22456 case EF_ARM_EABI_UNKNOWN
:
22458 /* Set the flags in the private structure. */
22459 if (uses_apcs_26
) flags
|= F_APCS26
;
22460 if (support_interwork
) flags
|= F_INTERWORK
;
22461 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
22462 if (pic_code
) flags
|= F_PIC
;
22463 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
22464 flags
|= F_SOFT_FLOAT
;
22466 switch (mfloat_abi_opt
)
22468 case ARM_FLOAT_ABI_SOFT
:
22469 case ARM_FLOAT_ABI_SOFTFP
:
22470 flags
|= F_SOFT_FLOAT
;
22473 case ARM_FLOAT_ABI_HARD
:
22474 if (flags
& F_SOFT_FLOAT
)
22475 as_bad (_("hard-float conflicts with specified fpu"));
22479 /* Using pure-endian doubles (even if soft-float). */
22480 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
22481 flags
|= F_VFP_FLOAT
;
22483 #if defined OBJ_ELF
22484 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
22485 flags
|= EF_ARM_MAVERICK_FLOAT
;
22488 case EF_ARM_EABI_VER4
:
22489 case EF_ARM_EABI_VER5
:
22490 /* No additional flags to set. */
22497 bfd_set_private_flags (stdoutput
, flags
);
22499 /* We have run out flags in the COFF header to encode the
22500 status of ATPCS support, so instead we create a dummy,
22501 empty, debug section called .arm.atpcs. */
22506 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
22510 bfd_set_section_flags
22511 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
22512 bfd_set_section_size (stdoutput
, sec
, 0);
22513 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
22519 /* Record the CPU type as well. */
22520 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
22521 mach
= bfd_mach_arm_iWMMXt2
;
22522 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
22523 mach
= bfd_mach_arm_iWMMXt
;
22524 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
22525 mach
= bfd_mach_arm_XScale
;
22526 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
22527 mach
= bfd_mach_arm_ep9312
;
22528 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
22529 mach
= bfd_mach_arm_5TE
;
22530 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
22532 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22533 mach
= bfd_mach_arm_5T
;
22535 mach
= bfd_mach_arm_5
;
22537 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
22539 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
22540 mach
= bfd_mach_arm_4T
;
22542 mach
= bfd_mach_arm_4
;
22544 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
22545 mach
= bfd_mach_arm_3M
;
22546 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
22547 mach
= bfd_mach_arm_3
;
22548 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
22549 mach
= bfd_mach_arm_2a
;
22550 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
22551 mach
= bfd_mach_arm_2
;
22553 mach
= bfd_mach_arm_unknown
;
22555 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
22558 /* Command line processing. */
22561 Invocation line includes a switch not recognized by the base assembler.
22562 See if it's a processor-specific option.
22564 This routine is somewhat complicated by the need for backwards
22565 compatibility (since older releases of gcc can't be changed).
22566 The new options try to make the interface as compatible as
22569 New options (supported) are:
22571 -mcpu=<cpu name> Assemble for selected processor
22572 -march=<architecture name> Assemble for selected architecture
22573 -mfpu=<fpu architecture> Assemble for selected FPU.
22574 -EB/-mbig-endian Big-endian
22575 -EL/-mlittle-endian Little-endian
22576 -k Generate PIC code
22577 -mthumb Start in Thumb mode
22578 -mthumb-interwork Code supports ARM/Thumb interworking
22580 -m[no-]warn-deprecated Warn about deprecated features
22582 For now we will also provide support for:
22584 -mapcs-32 32-bit Program counter
22585 -mapcs-26 26-bit Program counter
22586 -macps-float Floats passed in FP registers
22587 -mapcs-reentrant Reentrant code
22589 (sometime these will probably be replaced with -mapcs=<list of options>
22590 and -matpcs=<list of options>)
22592 The remaining options are only supported for back-wards compatibility.
22593 Cpu variants, the arm part is optional:
22594 -m[arm]1 Currently not supported.
22595 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
22596 -m[arm]3 Arm 3 processor
22597 -m[arm]6[xx], Arm 6 processors
22598 -m[arm]7[xx][t][[d]m] Arm 7 processors
22599 -m[arm]8[10] Arm 8 processors
22600 -m[arm]9[20][tdmi] Arm 9 processors
22601 -mstrongarm[110[0]] StrongARM processors
22602 -mxscale XScale processors
22603 -m[arm]v[2345[t[e]]] Arm architectures
22604 -mall All (except the ARM1)
22606 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
22607 -mfpe-old (No float load/store multiples)
22608 -mvfpxd VFP Single precision
22610 -mno-fpu Disable all floating point instructions
22612 The following CPU names are recognized:
22613 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
22614 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
22615 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
22616 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
22617 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
22618 arm10t arm10e, arm1020t, arm1020e, arm10200e,
22619 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
22623 const char * md_shortopts
= "m:k";
22625 #ifdef ARM_BI_ENDIAN
22626 #define OPTION_EB (OPTION_MD_BASE + 0)
22627 #define OPTION_EL (OPTION_MD_BASE + 1)
22629 #if TARGET_BYTES_BIG_ENDIAN
22630 #define OPTION_EB (OPTION_MD_BASE + 0)
22632 #define OPTION_EL (OPTION_MD_BASE + 1)
22635 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
22637 struct option md_longopts
[] =
22640 {"EB", no_argument
, NULL
, OPTION_EB
},
22643 {"EL", no_argument
, NULL
, OPTION_EL
},
22645 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
22646 {NULL
, no_argument
, NULL
, 0}
22649 size_t md_longopts_size
= sizeof (md_longopts
);
22651 struct arm_option_table
22653 char *option
; /* Option name to match. */
22654 char *help
; /* Help information. */
22655 int *var
; /* Variable to change. */
22656 int value
; /* What to change it to. */
22657 char *deprecated
; /* If non-null, print this message. */
22660 struct arm_option_table arm_opts
[] =
22662 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
22663 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
22664 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
22665 &support_interwork
, 1, NULL
},
22666 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
22667 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
22668 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
22670 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
22671 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
22672 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
22673 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
22676 /* These are recognized by the assembler, but have no affect on code. */
22677 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
22678 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
22680 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
22681 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
22682 &warn_on_deprecated
, 0, NULL
},
22683 {NULL
, NULL
, NULL
, 0, NULL
}
22686 struct arm_legacy_option_table
22688 char *option
; /* Option name to match. */
22689 const arm_feature_set
**var
; /* Variable to change. */
22690 const arm_feature_set value
; /* What to change it to. */
22691 char *deprecated
; /* If non-null, print this message. */
22694 const struct arm_legacy_option_table arm_legacy_opts
[] =
22696 /* DON'T add any new processors to this list -- we want the whole list
22697 to go away... Add them to the processors table instead. */
22698 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22699 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
22700 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22701 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
22702 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22703 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
22704 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22705 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
22706 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22707 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
22708 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22709 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
22710 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22711 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
22712 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22713 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
22714 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22715 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
22716 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22717 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
22718 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22719 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
22720 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22721 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
22722 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22723 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
22724 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22725 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
22726 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22727 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
22728 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22729 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
22730 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22731 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
22732 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22733 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
22734 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22735 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
22736 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22737 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
22738 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22739 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
22740 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22741 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
22742 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22743 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
22744 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22745 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22746 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22747 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
22748 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22749 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
22750 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22751 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
22752 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22753 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
22754 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22755 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
22756 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22757 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
22758 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22759 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
22760 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22761 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
22762 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22763 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
22764 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22765 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
22766 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
22767 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
22768 N_("use -mcpu=strongarm110")},
22769 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
22770 N_("use -mcpu=strongarm1100")},
22771 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
22772 N_("use -mcpu=strongarm1110")},
22773 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
22774 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
22775 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
22777 /* Architecture variants -- don't add any more to this list either. */
22778 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22779 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
22780 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22781 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
22782 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22783 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
22784 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22785 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
22786 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22787 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
22788 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22789 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
22790 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22791 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
22792 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22793 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
22794 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22795 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
22797 /* Floating point variants -- don't add any more to this list either. */
22798 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
22799 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
22800 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
22801 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
22802 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
22804 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
22807 struct arm_cpu_option_table
22810 const arm_feature_set value
;
22811 /* For some CPUs we assume an FPU unless the user explicitly sets
22813 const arm_feature_set default_fpu
;
22814 /* The canonical name of the CPU, or NULL to use NAME converted to upper
22816 const char *canonical_name
;
22819 /* This list should, at a minimum, contain all the cpu names
22820 recognized by GCC. */
22821 static const struct arm_cpu_option_table arm_cpus
[] =
22823 {"all", ARM_ANY
, FPU_ARCH_FPA
, NULL
},
22824 {"arm1", ARM_ARCH_V1
, FPU_ARCH_FPA
, NULL
},
22825 {"arm2", ARM_ARCH_V2
, FPU_ARCH_FPA
, NULL
},
22826 {"arm250", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22827 {"arm3", ARM_ARCH_V2S
, FPU_ARCH_FPA
, NULL
},
22828 {"arm6", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22829 {"arm60", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22830 {"arm600", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22831 {"arm610", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22832 {"arm620", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22833 {"arm7", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22834 {"arm7m", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22835 {"arm7d", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22836 {"arm7dm", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22837 {"arm7di", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22838 {"arm7dmi", ARM_ARCH_V3M
, FPU_ARCH_FPA
, NULL
},
22839 {"arm70", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22840 {"arm700", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22841 {"arm700i", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22842 {"arm710", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22843 {"arm710t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22844 {"arm720", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22845 {"arm720t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22846 {"arm740t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22847 {"arm710c", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22848 {"arm7100", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22849 {"arm7500", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22850 {"arm7500fe", ARM_ARCH_V3
, FPU_ARCH_FPA
, NULL
},
22851 {"arm7t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22852 {"arm7tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22853 {"arm7tdmi-s", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22854 {"arm8", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22855 {"arm810", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22856 {"strongarm", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22857 {"strongarm1", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22858 {"strongarm110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22859 {"strongarm1100", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22860 {"strongarm1110", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22861 {"arm9", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22862 {"arm920", ARM_ARCH_V4T
, FPU_ARCH_FPA
, "ARM920T"},
22863 {"arm920t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22864 {"arm922t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22865 {"arm940t", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22866 {"arm9tdmi", ARM_ARCH_V4T
, FPU_ARCH_FPA
, NULL
},
22867 {"fa526", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22868 {"fa626", ARM_ARCH_V4
, FPU_ARCH_FPA
, NULL
},
22869 /* For V5 or later processors we default to using VFP; but the user
22870 should really set the FPU type explicitly. */
22871 {"arm9e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22872 {"arm9e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22873 {"arm926ej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22874 {"arm926ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM926EJ-S"},
22875 {"arm926ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22876 {"arm946e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22877 {"arm946e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM946E-S"},
22878 {"arm946e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22879 {"arm966e-r0", ARM_ARCH_V5TExP
, FPU_ARCH_VFP_V2
, NULL
},
22880 {"arm966e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM966E-S"},
22881 {"arm966e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22882 {"arm968e-s", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22883 {"arm10t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22884 {"arm10tdmi", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22885 {"arm10e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22886 {"arm1020", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, "ARM1020E"},
22887 {"arm1020t", ARM_ARCH_V5T
, FPU_ARCH_VFP_V1
, NULL
},
22888 {"arm1020e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22889 {"arm1022e", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22890 {"arm1026ejs", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, "ARM1026EJ-S"},
22891 {"arm1026ej-s", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP_V2
, NULL
},
22892 {"fa606te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22893 {"fa616te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22894 {"fa626te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22895 {"fmp626", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22896 {"fa726te", ARM_ARCH_V5TE
, FPU_ARCH_VFP_V2
, NULL
},
22897 {"arm1136js", ARM_ARCH_V6
, FPU_NONE
, "ARM1136J-S"},
22898 {"arm1136j-s", ARM_ARCH_V6
, FPU_NONE
, NULL
},
22899 {"arm1136jfs", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, "ARM1136JF-S"},
22900 {"arm1136jf-s", ARM_ARCH_V6
, FPU_ARCH_VFP_V2
, NULL
},
22901 {"mpcore", ARM_ARCH_V6K
, FPU_ARCH_VFP_V2
, "MPCore"},
22902 {"mpcorenovfp", ARM_ARCH_V6K
, FPU_NONE
, "MPCore"},
22903 {"arm1156t2-s", ARM_ARCH_V6T2
, FPU_NONE
, NULL
},
22904 {"arm1156t2f-s", ARM_ARCH_V6T2
, FPU_ARCH_VFP_V2
, NULL
},
22905 {"arm1176jz-s", ARM_ARCH_V6ZK
, FPU_NONE
, NULL
},
22906 {"arm1176jzf-s", ARM_ARCH_V6ZK
, FPU_ARCH_VFP_V2
, NULL
},
22907 {"cortex-a5", ARM_ARCH_V7A_MP_SEC
,
22908 FPU_NONE
, "Cortex-A5"},
22909 {"cortex-a8", ARM_ARCH_V7A_SEC
,
22910 ARM_FEATURE (0, FPU_VFP_V3
22911 | FPU_NEON_EXT_V1
),
22913 {"cortex-a9", ARM_ARCH_V7A_MP_SEC
,
22914 ARM_FEATURE (0, FPU_VFP_V3
22915 | FPU_NEON_EXT_V1
),
22917 {"cortex-a15", ARM_ARCH_V7A_IDIV_MP_SEC_VIRT
,
22918 FPU_ARCH_NEON_VFP_V4
,
22920 {"cortex-r4", ARM_ARCH_V7R
, FPU_NONE
, "Cortex-R4"},
22921 {"cortex-r4f", ARM_ARCH_V7R
, FPU_ARCH_VFP_V3D16
,
22923 {"cortex-r5", ARM_ARCH_V7R_IDIV
,
22924 FPU_NONE
, "Cortex-R5"},
22925 {"cortex-m4", ARM_ARCH_V7EM
, FPU_NONE
, "Cortex-M4"},
22926 {"cortex-m3", ARM_ARCH_V7M
, FPU_NONE
, "Cortex-M3"},
22927 {"cortex-m1", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M1"},
22928 {"cortex-m0", ARM_ARCH_V6SM
, FPU_NONE
, "Cortex-M0"},
22929 /* ??? XSCALE is really an architecture. */
22930 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22931 /* ??? iwmmxt is not a processor. */
22932 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP_V2
, NULL
},
22933 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP_V2
, NULL
},
22934 {"i80200", ARM_ARCH_XSCALE
, FPU_ARCH_VFP_V2
, NULL
},
22936 {"ep9312", ARM_FEATURE (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
), FPU_ARCH_MAVERICK
, "ARM920T"},
22937 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
22940 struct arm_arch_option_table
22943 const arm_feature_set value
;
22944 const arm_feature_set default_fpu
;
22947 /* This list should, at a minimum, contain all the architecture names
22948 recognized by GCC. */
22949 static const struct arm_arch_option_table arm_archs
[] =
22951 {"all", ARM_ANY
, FPU_ARCH_FPA
},
22952 {"armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
},
22953 {"armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
},
22954 {"armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22955 {"armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
},
22956 {"armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
},
22957 {"armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
},
22958 {"armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
},
22959 {"armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
},
22960 {"armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
},
22961 {"armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
},
22962 {"armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
},
22963 {"armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
},
22964 {"armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
},
22965 {"armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
},
22966 {"armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
},
22967 {"armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
},
22968 {"armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22969 {"armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
},
22970 {"armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
},
22971 {"armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
},
22972 {"armv6zk", ARM_ARCH_V6ZK
, FPU_ARCH_VFP
},
22973 {"armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
},
22974 {"armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
},
22975 {"armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
},
22976 {"armv6zkt2", ARM_ARCH_V6ZKT2
, FPU_ARCH_VFP
},
22977 {"armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
},
22978 {"armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
},
22979 {"armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
},
22980 /* The official spelling of the ARMv7 profile variants is the dashed form.
22981 Accept the non-dashed form for compatibility with old toolchains. */
22982 {"armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22983 {"armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22984 {"armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22985 {"armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
},
22986 {"armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
},
22987 {"armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
},
22988 {"armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
},
22989 {"xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
},
22990 {"iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
},
22991 {"iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
},
22992 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
22995 /* ISA extensions in the co-processor and main instruction set space. */
22996 struct arm_option_extension_value_table
22999 const arm_feature_set value
;
23000 const arm_feature_set allowed_archs
;
23003 /* The following table must be in alphabetical order with a NULL last entry.
23005 static const struct arm_option_extension_value_table arm_extensions
[] =
23007 {"idiv", ARM_FEATURE (ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
23008 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
23009 {"iwmmxt", ARM_FEATURE (0, ARM_CEXT_IWMMXT
), ARM_ANY
},
23010 {"iwmmxt2", ARM_FEATURE (0, ARM_CEXT_IWMMXT2
), ARM_ANY
},
23011 {"maverick", ARM_FEATURE (0, ARM_CEXT_MAVERICK
), ARM_ANY
},
23012 {"mp", ARM_FEATURE (ARM_EXT_MP
, 0),
23013 ARM_FEATURE (ARM_EXT_V7A
| ARM_EXT_V7R
, 0)},
23014 {"os", ARM_FEATURE (ARM_EXT_OS
, 0),
23015 ARM_FEATURE (ARM_EXT_V6M
, 0)},
23016 {"sec", ARM_FEATURE (ARM_EXT_SEC
, 0),
23017 ARM_FEATURE (ARM_EXT_V6K
| ARM_EXT_V7A
, 0)},
23018 {"virt", ARM_FEATURE (ARM_EXT_VIRT
| ARM_EXT_ADIV
| ARM_EXT_DIV
, 0),
23019 ARM_FEATURE (ARM_EXT_V7A
, 0)},
23020 {"xscale", ARM_FEATURE (0, ARM_CEXT_XSCALE
), ARM_ANY
},
23021 {NULL
, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
23024 /* ISA floating-point and Advanced SIMD extensions. */
23025 struct arm_option_fpu_value_table
23028 const arm_feature_set value
;
23031 /* This list should, at a minimum, contain all the fpu names
23032 recognized by GCC. */
23033 static const struct arm_option_fpu_value_table arm_fpus
[] =
23035 {"softfpa", FPU_NONE
},
23036 {"fpe", FPU_ARCH_FPE
},
23037 {"fpe2", FPU_ARCH_FPE
},
23038 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
23039 {"fpa", FPU_ARCH_FPA
},
23040 {"fpa10", FPU_ARCH_FPA
},
23041 {"fpa11", FPU_ARCH_FPA
},
23042 {"arm7500fe", FPU_ARCH_FPA
},
23043 {"softvfp", FPU_ARCH_VFP
},
23044 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
23045 {"vfp", FPU_ARCH_VFP_V2
},
23046 {"vfp9", FPU_ARCH_VFP_V2
},
23047 {"vfp3", FPU_ARCH_VFP_V3
}, /* For backwards compatbility. */
23048 {"vfp10", FPU_ARCH_VFP_V2
},
23049 {"vfp10-r0", FPU_ARCH_VFP_V1
},
23050 {"vfpxd", FPU_ARCH_VFP_V1xD
},
23051 {"vfpv2", FPU_ARCH_VFP_V2
},
23052 {"vfpv3", FPU_ARCH_VFP_V3
},
23053 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
23054 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
23055 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
23056 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
23057 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
23058 {"arm1020t", FPU_ARCH_VFP_V1
},
23059 {"arm1020e", FPU_ARCH_VFP_V2
},
23060 {"arm1136jfs", FPU_ARCH_VFP_V2
},
23061 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
23062 {"maverick", FPU_ARCH_MAVERICK
},
23063 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
23064 {"neon-fp16", FPU_ARCH_NEON_FP16
},
23065 {"vfpv4", FPU_ARCH_VFP_V4
},
23066 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
23067 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
23068 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
23069 {NULL
, ARM_ARCH_NONE
}
23072 struct arm_option_value_table
23078 static const struct arm_option_value_table arm_float_abis
[] =
23080 {"hard", ARM_FLOAT_ABI_HARD
},
23081 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
23082 {"soft", ARM_FLOAT_ABI_SOFT
},
23087 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
23088 static const struct arm_option_value_table arm_eabis
[] =
23090 {"gnu", EF_ARM_EABI_UNKNOWN
},
23091 {"4", EF_ARM_EABI_VER4
},
23092 {"5", EF_ARM_EABI_VER5
},
23097 struct arm_long_option_table
23099 char * option
; /* Substring to match. */
23100 char * help
; /* Help information. */
23101 int (* func
) (char * subopt
); /* Function to decode sub-option. */
23102 char * deprecated
; /* If non-null, print this message. */
23106 arm_parse_extension (char * str
, const arm_feature_set
**opt_p
)
23108 arm_feature_set
*ext_set
= (arm_feature_set
*)
23109 xmalloc (sizeof (arm_feature_set
));
23111 /* We insist on extensions being specified in alphabetical order, and with
23112 extensions being added before being removed. We achieve this by having
23113 the global ARM_EXTENSIONS table in alphabetical order, and using the
23114 ADDING_VALUE variable to indicate whether we are adding an extension (1)
23115 or removing it (0) and only allowing it to change in the order
23117 const struct arm_option_extension_value_table
* opt
= NULL
;
23118 int adding_value
= -1;
23120 /* Copy the feature set, so that we can modify it. */
23121 *ext_set
= **opt_p
;
23124 while (str
!= NULL
&& *str
!= 0)
23131 as_bad (_("invalid architectural extension"));
23136 ext
= strchr (str
, '+');
23139 optlen
= ext
- str
;
23141 optlen
= strlen (str
);
23144 && strncmp (str
, "no", 2) == 0)
23146 if (adding_value
!= 0)
23149 opt
= arm_extensions
;
23155 else if (optlen
> 0)
23157 if (adding_value
== -1)
23160 opt
= arm_extensions
;
23162 else if (adding_value
!= 1)
23164 as_bad (_("must specify extensions to add before specifying "
23165 "those to remove"));
23172 as_bad (_("missing architectural extension"));
23176 gas_assert (adding_value
!= -1);
23177 gas_assert (opt
!= NULL
);
23179 /* Scan over the options table trying to find an exact match. */
23180 for (; opt
->name
!= NULL
; opt
++)
23181 if (strncmp (opt
->name
, str
, optlen
) == 0
23182 && strlen (opt
->name
) == optlen
)
23184 /* Check we can apply the extension to this architecture. */
23185 if (!ARM_CPU_HAS_FEATURE (*ext_set
, opt
->allowed_archs
))
23187 as_bad (_("extension does not apply to the base architecture"));
23191 /* Add or remove the extension. */
23193 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->value
);
23195 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->value
);
23200 if (opt
->name
== NULL
)
23202 /* Did we fail to find an extension because it wasn't specified in
23203 alphabetical order, or because it does not exist? */
23205 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23206 if (strncmp (opt
->name
, str
, optlen
) == 0)
23209 if (opt
->name
== NULL
)
23210 as_bad (_("unknown architectural extension `%s'"), str
);
23212 as_bad (_("architectural extensions must be specified in "
23213 "alphabetical order"));
23219 /* We should skip the extension we've just matched the next time
23231 arm_parse_cpu (char * str
)
23233 const struct arm_cpu_option_table
* opt
;
23234 char * ext
= strchr (str
, '+');
23238 optlen
= ext
- str
;
23240 optlen
= strlen (str
);
23244 as_bad (_("missing cpu name `%s'"), str
);
23248 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
23249 if (strncmp (opt
->name
, str
, optlen
) == 0)
23251 mcpu_cpu_opt
= &opt
->value
;
23252 mcpu_fpu_opt
= &opt
->default_fpu
;
23253 if (opt
->canonical_name
)
23254 strcpy (selected_cpu_name
, opt
->canonical_name
);
23259 for (i
= 0; i
< optlen
; i
++)
23260 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23261 selected_cpu_name
[i
] = 0;
23265 return arm_parse_extension (ext
, &mcpu_cpu_opt
);
23270 as_bad (_("unknown cpu `%s'"), str
);
23275 arm_parse_arch (char * str
)
23277 const struct arm_arch_option_table
*opt
;
23278 char *ext
= strchr (str
, '+');
23282 optlen
= ext
- str
;
23284 optlen
= strlen (str
);
23288 as_bad (_("missing architecture name `%s'"), str
);
23292 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
23293 if (strncmp (opt
->name
, str
, optlen
) == 0)
23295 march_cpu_opt
= &opt
->value
;
23296 march_fpu_opt
= &opt
->default_fpu
;
23297 strcpy (selected_cpu_name
, opt
->name
);
23300 return arm_parse_extension (ext
, &march_cpu_opt
);
23305 as_bad (_("unknown architecture `%s'\n"), str
);
23310 arm_parse_fpu (char * str
)
23312 const struct arm_option_fpu_value_table
* opt
;
23314 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23315 if (streq (opt
->name
, str
))
23317 mfpu_opt
= &opt
->value
;
23321 as_bad (_("unknown floating point format `%s'\n"), str
);
23326 arm_parse_float_abi (char * str
)
23328 const struct arm_option_value_table
* opt
;
23330 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
23331 if (streq (opt
->name
, str
))
23333 mfloat_abi_opt
= opt
->value
;
23337 as_bad (_("unknown floating point abi `%s'\n"), str
);
23343 arm_parse_eabi (char * str
)
23345 const struct arm_option_value_table
*opt
;
23347 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
23348 if (streq (opt
->name
, str
))
23350 meabi_flags
= opt
->value
;
23353 as_bad (_("unknown EABI `%s'\n"), str
);
23359 arm_parse_it_mode (char * str
)
23361 bfd_boolean ret
= TRUE
;
23363 if (streq ("arm", str
))
23364 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
23365 else if (streq ("thumb", str
))
23366 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
23367 else if (streq ("always", str
))
23368 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
23369 else if (streq ("never", str
))
23370 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
23373 as_bad (_("unknown implicit IT mode `%s', should be "\
23374 "arm, thumb, always, or never."), str
);
23381 struct arm_long_option_table arm_long_opts
[] =
23383 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
23384 arm_parse_cpu
, NULL
},
23385 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
23386 arm_parse_arch
, NULL
},
23387 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
23388 arm_parse_fpu
, NULL
},
23389 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
23390 arm_parse_float_abi
, NULL
},
23392 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
23393 arm_parse_eabi
, NULL
},
23395 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
23396 arm_parse_it_mode
, NULL
},
23397 {NULL
, NULL
, 0, NULL
}
23401 md_parse_option (int c
, char * arg
)
23403 struct arm_option_table
*opt
;
23404 const struct arm_legacy_option_table
*fopt
;
23405 struct arm_long_option_table
*lopt
;
23411 target_big_endian
= 1;
23417 target_big_endian
= 0;
23421 case OPTION_FIX_V4BX
:
23426 /* Listing option. Just ignore these, we don't support additional
23431 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23433 if (c
== opt
->option
[0]
23434 && ((arg
== NULL
&& opt
->option
[1] == 0)
23435 || streq (arg
, opt
->option
+ 1)))
23437 /* If the option is deprecated, tell the user. */
23438 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
23439 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23440 arg
? arg
: "", _(opt
->deprecated
));
23442 if (opt
->var
!= NULL
)
23443 *opt
->var
= opt
->value
;
23449 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
23451 if (c
== fopt
->option
[0]
23452 && ((arg
== NULL
&& fopt
->option
[1] == 0)
23453 || streq (arg
, fopt
->option
+ 1)))
23455 /* If the option is deprecated, tell the user. */
23456 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
23457 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
23458 arg
? arg
: "", _(fopt
->deprecated
));
23460 if (fopt
->var
!= NULL
)
23461 *fopt
->var
= &fopt
->value
;
23467 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23469 /* These options are expected to have an argument. */
23470 if (c
== lopt
->option
[0]
23472 && strncmp (arg
, lopt
->option
+ 1,
23473 strlen (lopt
->option
+ 1)) == 0)
23475 /* If the option is deprecated, tell the user. */
23476 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
23477 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
23478 _(lopt
->deprecated
));
23480 /* Call the sup-option parser. */
23481 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
23492 md_show_usage (FILE * fp
)
23494 struct arm_option_table
*opt
;
23495 struct arm_long_option_table
*lopt
;
23497 fprintf (fp
, _(" ARM-specific assembler options:\n"));
23499 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
23500 if (opt
->help
!= NULL
)
23501 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
23503 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
23504 if (lopt
->help
!= NULL
)
23505 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
23509 -EB assemble code for a big-endian cpu\n"));
23514 -EL assemble code for a little-endian cpu\n"));
23518 --fix-v4bx Allow BX in ARMv4 code\n"));
23526 arm_feature_set flags
;
23527 } cpu_arch_ver_table
;
23529 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
23530 least features first. */
23531 static const cpu_arch_ver_table cpu_arch_ver
[] =
23537 {4, ARM_ARCH_V5TE
},
23538 {5, ARM_ARCH_V5TEJ
},
23542 {11, ARM_ARCH_V6M
},
23543 {12, ARM_ARCH_V6SM
},
23544 {8, ARM_ARCH_V6T2
},
23545 {10, ARM_ARCH_V7A
},
23546 {10, ARM_ARCH_V7R
},
23547 {10, ARM_ARCH_V7M
},
23551 /* Set an attribute if it has not already been set by the user. */
23553 aeabi_set_attribute_int (int tag
, int value
)
23556 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23557 || !attributes_set_explicitly
[tag
])
23558 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
23562 aeabi_set_attribute_string (int tag
, const char *value
)
23565 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
23566 || !attributes_set_explicitly
[tag
])
23567 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
23570 /* Set the public EABI object attributes. */
23572 aeabi_set_public_attributes (void)
23576 arm_feature_set flags
;
23577 arm_feature_set tmp
;
23578 const cpu_arch_ver_table
*p
;
23580 /* Choose the architecture based on the capabilities of the requested cpu
23581 (if any) and/or the instructions actually used. */
23582 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
23583 ARM_MERGE_FEATURE_SETS (flags
, flags
, *mfpu_opt
);
23584 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_cpu
);
23585 /*Allow the user to override the reported architecture. */
23588 ARM_CLEAR_FEATURE (flags
, flags
, arm_arch_any
);
23589 ARM_MERGE_FEATURE_SETS (flags
, flags
, *object_arch
);
23592 /* We need to make sure that the attributes do not identify us as v6S-M
23593 when the only v6S-M feature in use is the Operating System Extensions. */
23594 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_os
))
23595 if (!ARM_CPU_HAS_FEATURE (flags
, arm_arch_v6m_only
))
23596 ARM_CLEAR_FEATURE (flags
, flags
, arm_ext_os
);
23600 for (p
= cpu_arch_ver
; p
->val
; p
++)
23602 if (ARM_CPU_HAS_FEATURE (tmp
, p
->flags
))
23605 ARM_CLEAR_FEATURE (tmp
, tmp
, p
->flags
);
23609 /* The table lookup above finds the last architecture to contribute
23610 a new feature. Unfortunately, Tag13 is a subset of the union of
23611 v6T2 and v7-M, so it is never seen as contributing a new feature.
23612 We can not search for the last entry which is entirely used,
23613 because if no CPU is specified we build up only those flags
23614 actually used. Perhaps we should separate out the specified
23615 and implicit cases. Avoid taking this path for -march=all by
23616 checking for contradictory v7-A / v7-M features. */
23618 && !ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
)
23619 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7m
)
23620 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v6_dsp
))
23623 /* Tag_CPU_name. */
23624 if (selected_cpu_name
[0])
23628 q
= selected_cpu_name
;
23629 if (strncmp (q
, "armv", 4) == 0)
23634 for (i
= 0; q
[i
]; i
++)
23635 q
[i
] = TOUPPER (q
[i
]);
23637 aeabi_set_attribute_string (Tag_CPU_name
, q
);
23640 /* Tag_CPU_arch. */
23641 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
23643 /* Tag_CPU_arch_profile. */
23644 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7a
))
23645 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'A');
23646 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v7r
))
23647 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'R');
23648 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_m
))
23649 aeabi_set_attribute_int (Tag_CPU_arch_profile
, 'M');
23651 /* Tag_ARM_ISA_use. */
23652 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
23654 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
23656 /* Tag_THUMB_ISA_use. */
23657 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
23659 aeabi_set_attribute_int (Tag_THUMB_ISA_use
,
23660 ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
) ? 2 : 1);
23662 /* Tag_VFP_arch. */
23663 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
23664 aeabi_set_attribute_int (Tag_VFP_arch
,
23665 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
23667 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
23668 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
23669 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
23670 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
23671 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
23672 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
23673 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
23674 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
23675 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
23677 /* Tag_ABI_HardFP_use. */
23678 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
23679 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
23680 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
23682 /* Tag_WMMX_arch. */
23683 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
23684 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
23685 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
23686 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
23688 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
23689 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
23690 aeabi_set_attribute_int
23691 (Tag_Advanced_SIMD_arch
, (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
)
23694 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
23695 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
))
23696 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
23699 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
))
23700 aeabi_set_attribute_int (Tag_DIV_use
, 2);
23701 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
))
23702 aeabi_set_attribute_int (Tag_DIV_use
, 0);
23704 aeabi_set_attribute_int (Tag_DIV_use
, 1);
23706 /* Tag_MP_extension_use. */
23707 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
23708 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
23710 /* Tag Virtualization_use. */
23711 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
23713 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
23716 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
23719 /* Add the default contents for the .ARM.attributes section. */
23723 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
23726 aeabi_set_public_attributes ();
23728 #endif /* OBJ_ELF */
23731 /* Parse a .cpu directive. */
23734 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
23736 const struct arm_cpu_option_table
*opt
;
23740 name
= input_line_pointer
;
23741 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23742 input_line_pointer
++;
23743 saved_char
= *input_line_pointer
;
23744 *input_line_pointer
= 0;
23746 /* Skip the first "all" entry. */
23747 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
23748 if (streq (opt
->name
, name
))
23750 mcpu_cpu_opt
= &opt
->value
;
23751 selected_cpu
= opt
->value
;
23752 if (opt
->canonical_name
)
23753 strcpy (selected_cpu_name
, opt
->canonical_name
);
23757 for (i
= 0; opt
->name
[i
]; i
++)
23758 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
23759 selected_cpu_name
[i
] = 0;
23761 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23762 *input_line_pointer
= saved_char
;
23763 demand_empty_rest_of_line ();
23766 as_bad (_("unknown cpu `%s'"), name
);
23767 *input_line_pointer
= saved_char
;
23768 ignore_rest_of_line ();
23772 /* Parse a .arch directive. */
23775 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
23777 const struct arm_arch_option_table
*opt
;
23781 name
= input_line_pointer
;
23782 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23783 input_line_pointer
++;
23784 saved_char
= *input_line_pointer
;
23785 *input_line_pointer
= 0;
23787 /* Skip the first "all" entry. */
23788 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23789 if (streq (opt
->name
, name
))
23791 mcpu_cpu_opt
= &opt
->value
;
23792 selected_cpu
= opt
->value
;
23793 strcpy (selected_cpu_name
, opt
->name
);
23794 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23795 *input_line_pointer
= saved_char
;
23796 demand_empty_rest_of_line ();
23800 as_bad (_("unknown architecture `%s'\n"), name
);
23801 *input_line_pointer
= saved_char
;
23802 ignore_rest_of_line ();
23806 /* Parse a .object_arch directive. */
23809 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
23811 const struct arm_arch_option_table
*opt
;
23815 name
= input_line_pointer
;
23816 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23817 input_line_pointer
++;
23818 saved_char
= *input_line_pointer
;
23819 *input_line_pointer
= 0;
23821 /* Skip the first "all" entry. */
23822 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
23823 if (streq (opt
->name
, name
))
23825 object_arch
= &opt
->value
;
23826 *input_line_pointer
= saved_char
;
23827 demand_empty_rest_of_line ();
23831 as_bad (_("unknown architecture `%s'\n"), name
);
23832 *input_line_pointer
= saved_char
;
23833 ignore_rest_of_line ();
23836 /* Parse a .arch_extension directive. */
23839 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
23841 const struct arm_option_extension_value_table
*opt
;
23844 int adding_value
= 1;
23846 name
= input_line_pointer
;
23847 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23848 input_line_pointer
++;
23849 saved_char
= *input_line_pointer
;
23850 *input_line_pointer
= 0;
23852 if (strlen (name
) >= 2
23853 && strncmp (name
, "no", 2) == 0)
23859 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
23860 if (streq (opt
->name
, name
))
23862 if (!ARM_CPU_HAS_FEATURE (*mcpu_cpu_opt
, opt
->allowed_archs
))
23864 as_bad (_("architectural extension `%s' is not allowed for the "
23865 "current base architecture"), name
);
23870 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_cpu
, opt
->value
);
23872 ARM_CLEAR_FEATURE (selected_cpu
, selected_cpu
, opt
->value
);
23874 mcpu_cpu_opt
= &selected_cpu
;
23875 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23876 *input_line_pointer
= saved_char
;
23877 demand_empty_rest_of_line ();
23881 if (opt
->name
== NULL
)
23882 as_bad (_("unknown architecture `%s'\n"), name
);
23884 *input_line_pointer
= saved_char
;
23885 ignore_rest_of_line ();
23888 /* Parse a .fpu directive. */
23891 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
23893 const struct arm_option_fpu_value_table
*opt
;
23897 name
= input_line_pointer
;
23898 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
23899 input_line_pointer
++;
23900 saved_char
= *input_line_pointer
;
23901 *input_line_pointer
= 0;
23903 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
23904 if (streq (opt
->name
, name
))
23906 mfpu_opt
= &opt
->value
;
23907 ARM_MERGE_FEATURE_SETS (cpu_variant
, *mcpu_cpu_opt
, *mfpu_opt
);
23908 *input_line_pointer
= saved_char
;
23909 demand_empty_rest_of_line ();
23913 as_bad (_("unknown floating point format `%s'\n"), name
);
23914 *input_line_pointer
= saved_char
;
23915 ignore_rest_of_line ();
23918 /* Copy symbol information. */
23921 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
23923 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
23927 /* Given a symbolic attribute NAME, return the proper integer value.
23928 Returns -1 if the attribute is not known. */
23931 arm_convert_symbolic_attribute (const char *name
)
23933 static const struct
23938 attribute_table
[] =
23940 /* When you modify this table you should
23941 also modify the list in doc/c-arm.texi. */
23942 #define T(tag) {#tag, tag}
23943 T (Tag_CPU_raw_name
),
23946 T (Tag_CPU_arch_profile
),
23947 T (Tag_ARM_ISA_use
),
23948 T (Tag_THUMB_ISA_use
),
23952 T (Tag_Advanced_SIMD_arch
),
23953 T (Tag_PCS_config
),
23954 T (Tag_ABI_PCS_R9_use
),
23955 T (Tag_ABI_PCS_RW_data
),
23956 T (Tag_ABI_PCS_RO_data
),
23957 T (Tag_ABI_PCS_GOT_use
),
23958 T (Tag_ABI_PCS_wchar_t
),
23959 T (Tag_ABI_FP_rounding
),
23960 T (Tag_ABI_FP_denormal
),
23961 T (Tag_ABI_FP_exceptions
),
23962 T (Tag_ABI_FP_user_exceptions
),
23963 T (Tag_ABI_FP_number_model
),
23964 T (Tag_ABI_align_needed
),
23965 T (Tag_ABI_align8_needed
),
23966 T (Tag_ABI_align_preserved
),
23967 T (Tag_ABI_align8_preserved
),
23968 T (Tag_ABI_enum_size
),
23969 T (Tag_ABI_HardFP_use
),
23970 T (Tag_ABI_VFP_args
),
23971 T (Tag_ABI_WMMX_args
),
23972 T (Tag_ABI_optimization_goals
),
23973 T (Tag_ABI_FP_optimization_goals
),
23974 T (Tag_compatibility
),
23975 T (Tag_CPU_unaligned_access
),
23976 T (Tag_FP_HP_extension
),
23977 T (Tag_VFP_HP_extension
),
23978 T (Tag_ABI_FP_16bit_format
),
23979 T (Tag_MPextension_use
),
23981 T (Tag_nodefaults
),
23982 T (Tag_also_compatible_with
),
23983 T (Tag_conformance
),
23985 T (Tag_Virtualization_use
),
23986 /* We deliberately do not include Tag_MPextension_use_legacy. */
23994 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
23995 if (streq (name
, attribute_table
[i
].name
))
23996 return attribute_table
[i
].tag
;
24002 /* Apply sym value for relocations only in the case that
24003 they are for local symbols and you have the respective
24004 architectural feature for blx and simple switches. */
24006 arm_apply_sym_value (struct fix
* fixP
)
24009 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
24010 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
24012 switch (fixP
->fx_r_type
)
24014 case BFD_RELOC_ARM_PCREL_BLX
:
24015 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24016 if (ARM_IS_FUNC (fixP
->fx_addsy
))
24020 case BFD_RELOC_ARM_PCREL_CALL
:
24021 case BFD_RELOC_THUMB_PCREL_BLX
:
24022 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
24033 #endif /* OBJ_ELF */