1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2018 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
80 /* Results from operand parsing worker functions. */
84 PARSE_OPERAND_SUCCESS
,
86 PARSE_OPERAND_FAIL_NO_BACKTRACK
87 } parse_operand_result
;
96 /* Types of processor to assemble for. */
98 /* The code that was here used to select a default CPU depending on compiler
99 pre-defines which were only present when doing native builds, thus
100 changing gas' default behaviour depending upon the build host.
102 If you have a target that requires a default CPU option then the you
103 should define CPU_DEFAULT here. */
108 # define FPU_DEFAULT FPU_ARCH_FPA
109 # elif defined (TE_NetBSD)
111 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
113 /* Legacy a.out format. */
114 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
116 # elif defined (TE_VXWORKS)
117 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
119 /* For backwards compatibility, default to FPA. */
120 # define FPU_DEFAULT FPU_ARCH_FPA
122 #endif /* ifndef FPU_DEFAULT */
124 #define streq(a, b) (strcmp (a, b) == 0)
126 /* Current set of feature bits available (CPU+FPU). Different from
127 selected_cpu + selected_fpu in case of autodetection since the CPU
128 feature bits are then all set. */
129 static arm_feature_set cpu_variant
;
130 /* Feature bits used in each execution state. Used to set build attribute
131 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
132 static arm_feature_set arm_arch_used
;
133 static arm_feature_set thumb_arch_used
;
135 /* Flags stored in private area of BFD structure. */
136 static int uses_apcs_26
= FALSE
;
137 static int atpcs
= FALSE
;
138 static int support_interwork
= FALSE
;
139 static int uses_apcs_float
= FALSE
;
140 static int pic_code
= FALSE
;
141 static int fix_v4bx
= FALSE
;
142 /* Warn on using deprecated features. */
143 static int warn_on_deprecated
= TRUE
;
145 /* Understand CodeComposer Studio assembly syntax. */
146 bfd_boolean codecomposer_syntax
= FALSE
;
148 /* Variables that we set while parsing command-line options. Once all
149 options have been read we re-process these values to set the real
152 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
153 instead of -mcpu=arm1). */
154 static const arm_feature_set
*legacy_cpu
= NULL
;
155 static const arm_feature_set
*legacy_fpu
= NULL
;
157 /* CPU, extension and FPU feature bits selected by -mcpu. */
158 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
159 static arm_feature_set
*mcpu_ext_opt
= NULL
;
160 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
162 /* CPU, extension and FPU feature bits selected by -march. */
163 static const arm_feature_set
*march_cpu_opt
= NULL
;
164 static arm_feature_set
*march_ext_opt
= NULL
;
165 static const arm_feature_set
*march_fpu_opt
= NULL
;
167 /* Feature bits selected by -mfpu. */
168 static const arm_feature_set
*mfpu_opt
= NULL
;
170 /* Constants for known architecture features. */
171 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
172 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
173 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
174 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
175 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
176 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
177 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
179 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
181 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
184 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
187 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
188 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
189 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
190 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
191 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
192 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
193 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
194 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
195 static const arm_feature_set arm_ext_v4t_5
=
196 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
197 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
198 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
199 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
200 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
201 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
202 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
203 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
204 static const arm_feature_set arm_ext_v6_notm
=
205 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
206 static const arm_feature_set arm_ext_v6_dsp
=
207 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
208 static const arm_feature_set arm_ext_barrier
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
210 static const arm_feature_set arm_ext_msr
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
212 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
213 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
214 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
215 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
217 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
219 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
220 static const arm_feature_set arm_ext_m
=
221 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
222 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
223 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
224 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
225 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
226 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
227 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
228 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
229 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
230 static const arm_feature_set arm_ext_v8m_main
=
231 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
232 /* Instructions in ARMv8-M only found in M profile architectures. */
233 static const arm_feature_set arm_ext_v8m_m_only
=
234 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
235 static const arm_feature_set arm_ext_v6t2_v8m
=
236 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
237 /* Instructions shared between ARMv8-A and ARMv8-M. */
238 static const arm_feature_set arm_ext_atomics
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
241 /* DSP instructions Tag_DSP_extension refers to. */
242 static const arm_feature_set arm_ext_dsp
=
243 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
245 static const arm_feature_set arm_ext_ras
=
246 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
247 /* FP16 instructions. */
248 static const arm_feature_set arm_ext_fp16
=
249 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
250 static const arm_feature_set arm_ext_fp16_fml
=
251 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
252 static const arm_feature_set arm_ext_v8_2
=
253 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
254 static const arm_feature_set arm_ext_v8_3
=
255 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
257 static const arm_feature_set arm_arch_any
= ARM_ANY
;
259 static const arm_feature_set fpu_any
= FPU_ANY
;
261 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
262 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
263 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
265 static const arm_feature_set arm_cext_iwmmxt2
=
266 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
267 static const arm_feature_set arm_cext_iwmmxt
=
268 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
269 static const arm_feature_set arm_cext_xscale
=
270 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
271 static const arm_feature_set arm_cext_maverick
=
272 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
273 static const arm_feature_set fpu_fpa_ext_v1
=
274 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
275 static const arm_feature_set fpu_fpa_ext_v2
=
276 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
277 static const arm_feature_set fpu_vfp_ext_v1xd
=
278 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
279 static const arm_feature_set fpu_vfp_ext_v1
=
280 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
281 static const arm_feature_set fpu_vfp_ext_v2
=
282 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
283 static const arm_feature_set fpu_vfp_ext_v3xd
=
284 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
285 static const arm_feature_set fpu_vfp_ext_v3
=
286 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
287 static const arm_feature_set fpu_vfp_ext_d32
=
288 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
289 static const arm_feature_set fpu_neon_ext_v1
=
290 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
291 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
292 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
294 static const arm_feature_set fpu_vfp_fp16
=
295 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
296 static const arm_feature_set fpu_neon_ext_fma
=
297 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
299 static const arm_feature_set fpu_vfp_ext_fma
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
301 static const arm_feature_set fpu_vfp_ext_armv8
=
302 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
303 static const arm_feature_set fpu_vfp_ext_armv8xd
=
304 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
305 static const arm_feature_set fpu_neon_ext_armv8
=
306 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
307 static const arm_feature_set fpu_crypto_ext_armv8
=
308 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
309 static const arm_feature_set crc_ext_armv8
=
310 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
311 static const arm_feature_set fpu_neon_ext_v8_1
=
312 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
313 static const arm_feature_set fpu_neon_ext_dotprod
=
314 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
316 static int mfloat_abi_opt
= -1;
317 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
319 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
320 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
322 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
323 /* Feature bits selected by the last -mcpu/-march or by the combination of the
324 last .cpu/.arch directive .arch_extension directives since that
326 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
327 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
328 static arm_feature_set selected_fpu
= FPU_NONE
;
329 /* Feature bits selected by the last .object_arch directive. */
330 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
331 /* Must be long enough to hold any of the names in arm_cpus. */
332 static char selected_cpu_name
[20];
334 extern FLONUM_TYPE generic_floating_point_number
;
336 /* Return if no cpu was selected on command-line. */
338 no_cpu_selected (void)
340 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
345 static int meabi_flags
= EABI_DEFAULT
;
347 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
350 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
355 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
360 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
361 symbolS
* GOT_symbol
;
364 /* 0: assemble for ARM,
365 1: assemble for Thumb,
366 2: assemble for Thumb even though target CPU does not support thumb
368 static int thumb_mode
= 0;
369 /* A value distinct from the possible values for thumb_mode that we
370 can use to record whether thumb_mode has been copied into the
371 tc_frag_data field of a frag. */
372 #define MODE_RECORDED (1 << 4)
374 /* Specifies the intrinsic IT insn behavior mode. */
375 enum implicit_it_mode
377 IMPLICIT_IT_MODE_NEVER
= 0x00,
378 IMPLICIT_IT_MODE_ARM
= 0x01,
379 IMPLICIT_IT_MODE_THUMB
= 0x02,
380 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
382 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
384 /* If unified_syntax is true, we are processing the new unified
385 ARM/Thumb syntax. Important differences from the old ARM mode:
387 - Immediate operands do not require a # prefix.
388 - Conditional affixes always appear at the end of the
389 instruction. (For backward compatibility, those instructions
390 that formerly had them in the middle, continue to accept them
392 - The IT instruction may appear, and if it does is validated
393 against subsequent conditional affixes. It does not generate
396 Important differences from the old Thumb mode:
398 - Immediate operands do not require a # prefix.
399 - Most of the V6T2 instructions are only available in unified mode.
400 - The .N and .W suffixes are recognized and honored (it is an error
401 if they cannot be honored).
402 - All instructions set the flags if and only if they have an 's' affix.
403 - Conditional affixes may be used. They are validated against
404 preceding IT instructions. Unlike ARM mode, you cannot use a
405 conditional affix except in the scope of an IT instruction. */
407 static bfd_boolean unified_syntax
= FALSE
;
409 /* An immediate operand can start with #, and ld*, st*, pld operands
410 can contain [ and ]. We need to tell APP not to elide whitespace
411 before a [, which can appear as the first operand for pld.
412 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
413 const char arm_symbol_chars
[] = "#[]{}";
428 enum neon_el_type type
;
432 #define NEON_MAX_TYPE_ELS 4
436 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
440 enum it_instruction_type
445 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
446 if inside, should be the last one. */
447 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
448 i.e. BKPT and NOP. */
449 IT_INSN
/* The IT insn has been parsed. */
452 /* The maximum number of operands we need. */
453 #define ARM_IT_MAX_OPERANDS 6
458 unsigned long instruction
;
462 /* "uncond_value" is set to the value in place of the conditional field in
463 unconditional versions of the instruction, or -1 if nothing is
466 struct neon_type vectype
;
467 /* This does not indicate an actual NEON instruction, only that
468 the mnemonic accepts neon-style type suffixes. */
470 /* Set to the opcode if the instruction needs relaxation.
471 Zero if the instruction is not relaxed. */
475 bfd_reloc_code_real_type type
;
480 enum it_instruction_type it_insn_type
;
486 struct neon_type_el vectype
;
487 unsigned present
: 1; /* Operand present. */
488 unsigned isreg
: 1; /* Operand was a register. */
489 unsigned immisreg
: 1; /* .imm field is a second register. */
490 unsigned isscalar
: 1; /* Operand is a (Neon) scalar. */
491 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
492 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
493 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
494 instructions. This allows us to disambiguate ARM <-> vector insns. */
495 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
496 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
497 unsigned isquad
: 1; /* Operand is Neon quad-precision register. */
498 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
499 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
500 unsigned writeback
: 1; /* Operand has trailing ! */
501 unsigned preind
: 1; /* Preindexed address. */
502 unsigned postind
: 1; /* Postindexed address. */
503 unsigned negative
: 1; /* Index register was negated. */
504 unsigned shifted
: 1; /* Shift applied to operation. */
505 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
506 } operands
[ARM_IT_MAX_OPERANDS
];
509 static struct arm_it inst
;
511 #define NUM_FLOAT_VALS 8
513 const char * fp_const
[] =
515 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
518 /* Number of littlenums required to hold an extended precision number. */
519 #define MAX_LITTLENUMS 6
521 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
531 #define CP_T_X 0x00008000
532 #define CP_T_Y 0x00400000
534 #define CONDS_BIT 0x00100000
535 #define LOAD_BIT 0x00100000
537 #define DOUBLE_LOAD_FLAG 0x00000001
541 const char * template_name
;
545 #define COND_ALWAYS 0xE
549 const char * template_name
;
553 struct asm_barrier_opt
555 const char * template_name
;
557 const arm_feature_set arch
;
560 /* The bit that distinguishes CPSR and SPSR. */
561 #define SPSR_BIT (1 << 22)
563 /* The individual PSR flag bits. */
564 #define PSR_c (1 << 16)
565 #define PSR_x (1 << 17)
566 #define PSR_s (1 << 18)
567 #define PSR_f (1 << 19)
572 bfd_reloc_code_real_type reloc
;
577 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
578 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
583 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
586 /* Bits for DEFINED field in neon_typed_alias. */
587 #define NTA_HASTYPE 1
588 #define NTA_HASINDEX 2
590 struct neon_typed_alias
592 unsigned char defined
;
594 struct neon_type_el eltype
;
597 /* ARM register categories. This includes coprocessor numbers and various
598 architecture extensions' registers. Each entry should have an error message
599 in reg_expected_msgs below. */
627 /* Structure for a hash table entry for a register.
628 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
629 information which states whether a vector type or index is specified (for a
630 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
636 unsigned char builtin
;
637 struct neon_typed_alias
* neon
;
640 /* Diagnostics used when we don't get a register of the expected type. */
641 const char * const reg_expected_msgs
[] =
643 [REG_TYPE_RN
] = N_("ARM register expected"),
644 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
645 [REG_TYPE_CN
] = N_("co-processor register expected"),
646 [REG_TYPE_FN
] = N_("FPA register expected"),
647 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
648 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
649 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
650 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
651 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
652 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
653 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
655 [REG_TYPE_VFC
] = N_("VFP system register expected"),
656 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
657 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
658 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
659 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
660 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
661 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
662 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
663 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
664 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
665 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
666 [REG_TYPE_RNB
] = N_("")
669 /* Some well known registers that we refer to directly elsewhere. */
675 /* ARM instructions take 4bytes in the object file, Thumb instructions
681 /* Basic string to match. */
682 const char * template_name
;
684 /* Parameters to instruction. */
685 unsigned int operands
[8];
687 /* Conditional tag - see opcode_lookup. */
688 unsigned int tag
: 4;
690 /* Basic instruction code. */
691 unsigned int avalue
: 28;
693 /* Thumb-format instruction code. */
696 /* Which architecture variant provides this instruction. */
697 const arm_feature_set
* avariant
;
698 const arm_feature_set
* tvariant
;
700 /* Function to call to encode instruction in ARM format. */
701 void (* aencode
) (void);
703 /* Function to call to encode instruction in Thumb format. */
704 void (* tencode
) (void);
707 /* Defines for various bits that we will want to toggle. */
708 #define INST_IMMEDIATE 0x02000000
709 #define OFFSET_REG 0x02000000
710 #define HWOFFSET_IMM 0x00400000
711 #define SHIFT_BY_REG 0x00000010
712 #define PRE_INDEX 0x01000000
713 #define INDEX_UP 0x00800000
714 #define WRITE_BACK 0x00200000
715 #define LDM_TYPE_2_OR_3 0x00400000
716 #define CPSI_MMOD 0x00020000
718 #define LITERAL_MASK 0xf000f000
719 #define OPCODE_MASK 0xfe1fffff
720 #define V4_STR_BIT 0x00000020
721 #define VLDR_VMOV_SAME 0x0040f000
723 #define T2_SUBS_PC_LR 0xf3de8f00
725 #define DATA_OP_SHIFT 21
726 #define SBIT_SHIFT 20
728 #define T2_OPCODE_MASK 0xfe1fffff
729 #define T2_DATA_OP_SHIFT 21
730 #define T2_SBIT_SHIFT 20
732 #define A_COND_MASK 0xf0000000
733 #define A_PUSH_POP_OP_MASK 0x0fff0000
735 /* Opcodes for pushing/poping registers to/from the stack. */
736 #define A1_OPCODE_PUSH 0x092d0000
737 #define A2_OPCODE_PUSH 0x052d0004
738 #define A2_OPCODE_POP 0x049d0004
740 /* Codes to distinguish the arithmetic instructions. */
751 #define OPCODE_CMP 10
752 #define OPCODE_CMN 11
753 #define OPCODE_ORR 12
754 #define OPCODE_MOV 13
755 #define OPCODE_BIC 14
756 #define OPCODE_MVN 15
758 #define T2_OPCODE_AND 0
759 #define T2_OPCODE_BIC 1
760 #define T2_OPCODE_ORR 2
761 #define T2_OPCODE_ORN 3
762 #define T2_OPCODE_EOR 4
763 #define T2_OPCODE_ADD 8
764 #define T2_OPCODE_ADC 10
765 #define T2_OPCODE_SBC 11
766 #define T2_OPCODE_SUB 13
767 #define T2_OPCODE_RSB 14
769 #define T_OPCODE_MUL 0x4340
770 #define T_OPCODE_TST 0x4200
771 #define T_OPCODE_CMN 0x42c0
772 #define T_OPCODE_NEG 0x4240
773 #define T_OPCODE_MVN 0x43c0
775 #define T_OPCODE_ADD_R3 0x1800
776 #define T_OPCODE_SUB_R3 0x1a00
777 #define T_OPCODE_ADD_HI 0x4400
778 #define T_OPCODE_ADD_ST 0xb000
779 #define T_OPCODE_SUB_ST 0xb080
780 #define T_OPCODE_ADD_SP 0xa800
781 #define T_OPCODE_ADD_PC 0xa000
782 #define T_OPCODE_ADD_I8 0x3000
783 #define T_OPCODE_SUB_I8 0x3800
784 #define T_OPCODE_ADD_I3 0x1c00
785 #define T_OPCODE_SUB_I3 0x1e00
787 #define T_OPCODE_ASR_R 0x4100
788 #define T_OPCODE_LSL_R 0x4080
789 #define T_OPCODE_LSR_R 0x40c0
790 #define T_OPCODE_ROR_R 0x41c0
791 #define T_OPCODE_ASR_I 0x1000
792 #define T_OPCODE_LSL_I 0x0000
793 #define T_OPCODE_LSR_I 0x0800
795 #define T_OPCODE_MOV_I8 0x2000
796 #define T_OPCODE_CMP_I8 0x2800
797 #define T_OPCODE_CMP_LR 0x4280
798 #define T_OPCODE_MOV_HR 0x4600
799 #define T_OPCODE_CMP_HR 0x4500
801 #define T_OPCODE_LDR_PC 0x4800
802 #define T_OPCODE_LDR_SP 0x9800
803 #define T_OPCODE_STR_SP 0x9000
804 #define T_OPCODE_LDR_IW 0x6800
805 #define T_OPCODE_STR_IW 0x6000
806 #define T_OPCODE_LDR_IH 0x8800
807 #define T_OPCODE_STR_IH 0x8000
808 #define T_OPCODE_LDR_IB 0x7800
809 #define T_OPCODE_STR_IB 0x7000
810 #define T_OPCODE_LDR_RW 0x5800
811 #define T_OPCODE_STR_RW 0x5000
812 #define T_OPCODE_LDR_RH 0x5a00
813 #define T_OPCODE_STR_RH 0x5200
814 #define T_OPCODE_LDR_RB 0x5c00
815 #define T_OPCODE_STR_RB 0x5400
817 #define T_OPCODE_PUSH 0xb400
818 #define T_OPCODE_POP 0xbc00
820 #define T_OPCODE_BRANCH 0xe000
822 #define THUMB_SIZE 2 /* Size of thumb instruction. */
823 #define THUMB_PP_PC_LR 0x0100
824 #define THUMB_LOAD_BIT 0x0800
825 #define THUMB2_LOAD_BIT 0x00100000
827 #define BAD_ARGS _("bad arguments to instruction")
828 #define BAD_SP _("r13 not allowed here")
829 #define BAD_PC _("r15 not allowed here")
830 #define BAD_COND _("instruction cannot be conditional")
831 #define BAD_OVERLAP _("registers may not be the same")
832 #define BAD_HIREG _("lo register required")
833 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
834 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode");
835 #define BAD_BRANCH _("branch must be last instruction in IT block")
836 #define BAD_NOT_IT _("instruction not allowed in IT block")
837 #define BAD_FPU _("selected FPU does not support instruction")
838 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
839 #define BAD_IT_COND _("incorrect condition in IT block")
840 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
841 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
842 #define BAD_PC_ADDRESSING \
843 _("cannot use register index with PC-relative addressing")
844 #define BAD_PC_WRITEBACK \
845 _("cannot use writeback with PC-relative addressing")
846 #define BAD_RANGE _("branch out of range")
847 #define BAD_FP16 _("selected processor does not support fp16 instruction")
848 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
849 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
851 static struct hash_control
* arm_ops_hsh
;
852 static struct hash_control
* arm_cond_hsh
;
853 static struct hash_control
* arm_shift_hsh
;
854 static struct hash_control
* arm_psr_hsh
;
855 static struct hash_control
* arm_v7m_psr_hsh
;
856 static struct hash_control
* arm_reg_hsh
;
857 static struct hash_control
* arm_reloc_hsh
;
858 static struct hash_control
* arm_barrier_opt_hsh
;
860 /* Stuff needed to resolve the label ambiguity
869 symbolS
* last_label_seen
;
870 static int label_is_thumb_function_name
= FALSE
;
872 /* Literal pool structure. Held on a per-section
873 and per-sub-section basis. */
875 #define MAX_LITERAL_POOL_SIZE 1024
876 typedef struct literal_pool
878 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
879 unsigned int next_free_entry
;
885 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
887 struct literal_pool
* next
;
888 unsigned int alignment
;
891 /* Pointer to a linked list of literal pools. */
892 literal_pool
* list_of_pools
= NULL
;
894 typedef enum asmfunc_states
897 WAITING_ASMFUNC_NAME
,
901 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
904 # define now_it seg_info (now_seg)->tc_segment_info_data.current_it
906 static struct current_it now_it
;
910 now_it_compatible (int cond
)
912 return (cond
& ~1) == (now_it
.cc
& ~1);
916 conditional_insn (void)
918 return inst
.cond
!= COND_ALWAYS
;
921 static int in_it_block (void);
923 static int handle_it_state (void);
925 static void force_automatic_it_block_close (void);
927 static void it_fsm_post_encode (void);
929 #define set_it_insn_type(type) \
932 inst.it_insn_type = type; \
933 if (handle_it_state () == FAIL) \
938 #define set_it_insn_type_nonvoid(type, failret) \
941 inst.it_insn_type = type; \
942 if (handle_it_state () == FAIL) \
947 #define set_it_insn_type_last() \
950 if (inst.cond == COND_ALWAYS) \
951 set_it_insn_type (IF_INSIDE_IT_LAST_INSN); \
953 set_it_insn_type (INSIDE_IT_LAST_INSN); \
959 /* This array holds the chars that always start a comment. If the
960 pre-processor is disabled, these aren't very useful. */
961 char arm_comment_chars
[] = "@";
963 /* This array holds the chars that only start a comment at the beginning of
964 a line. If the line seems to have the form '# 123 filename'
965 .line and .file directives will appear in the pre-processed output. */
966 /* Note that input_file.c hand checks for '#' at the beginning of the
967 first line of the input file. This is because the compiler outputs
968 #NO_APP at the beginning of its output. */
969 /* Also note that comments like this one will always work. */
970 const char line_comment_chars
[] = "#";
972 char arm_line_separator_chars
[] = ";";
974 /* Chars that can be used to separate mant
975 from exp in floating point numbers. */
976 const char EXP_CHARS
[] = "eE";
978 /* Chars that mean this number is a floating point constant. */
982 const char FLT_CHARS
[] = "rRsSfFdDxXeEpP";
984 /* Prefix characters that indicate the start of an immediate
986 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
988 /* Separator character handling. */
990 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
993 skip_past_char (char ** str
, char c
)
995 /* PR gas/14987: Allow for whitespace before the expected character. */
996 skip_whitespace (*str
);
1007 #define skip_past_comma(str) skip_past_char (str, ',')
1009 /* Arithmetic expressions (possibly involving symbols). */
1011 /* Return TRUE if anything in the expression is a bignum. */
1014 walk_no_bignums (symbolS
* sp
)
1016 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1019 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1021 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1022 || (symbol_get_value_expression (sp
)->X_op_symbol
1023 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1029 static bfd_boolean in_my_get_expression
= FALSE
;
1031 /* Third argument to my_get_expression. */
1032 #define GE_NO_PREFIX 0
1033 #define GE_IMM_PREFIX 1
1034 #define GE_OPT_PREFIX 2
1035 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1036 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1037 #define GE_OPT_PREFIX_BIG 3
1040 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1045 /* In unified syntax, all prefixes are optional. */
1047 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1050 switch (prefix_mode
)
1052 case GE_NO_PREFIX
: break;
1054 if (!is_immediate_prefix (**str
))
1056 inst
.error
= _("immediate expression requires a # prefix");
1062 case GE_OPT_PREFIX_BIG
:
1063 if (is_immediate_prefix (**str
))
1070 memset (ep
, 0, sizeof (expressionS
));
1072 save_in
= input_line_pointer
;
1073 input_line_pointer
= *str
;
1074 in_my_get_expression
= TRUE
;
1075 seg
= expression (ep
);
1076 in_my_get_expression
= FALSE
;
1078 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1080 /* We found a bad or missing expression in md_operand(). */
1081 *str
= input_line_pointer
;
1082 input_line_pointer
= save_in
;
1083 if (inst
.error
== NULL
)
1084 inst
.error
= (ep
->X_op
== O_absent
1085 ? _("missing expression") :_("bad expression"));
1090 if (seg
!= absolute_section
1091 && seg
!= text_section
1092 && seg
!= data_section
1093 && seg
!= bss_section
1094 && seg
!= undefined_section
)
1096 inst
.error
= _("bad segment");
1097 *str
= input_line_pointer
;
1098 input_line_pointer
= save_in
;
1105 /* Get rid of any bignums now, so that we don't generate an error for which
1106 we can't establish a line number later on. Big numbers are never valid
1107 in instructions, which is where this routine is always called. */
1108 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1109 && (ep
->X_op
== O_big
1110 || (ep
->X_add_symbol
1111 && (walk_no_bignums (ep
->X_add_symbol
)
1113 && walk_no_bignums (ep
->X_op_symbol
))))))
1115 inst
.error
= _("invalid constant");
1116 *str
= input_line_pointer
;
1117 input_line_pointer
= save_in
;
1121 *str
= input_line_pointer
;
1122 input_line_pointer
= save_in
;
1126 /* Turn a string in input_line_pointer into a floating point constant
1127 of type TYPE, and store the appropriate bytes in *LITP. The number
1128 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1129 returned, or NULL on OK.
1131 Note that fp constants aren't represent in the normal way on the ARM.
1132 In big endian mode, things are as expected. However, in little endian
1133 mode fp constants are big-endian word-wise, and little-endian byte-wise
1134 within the words. For example, (double) 1.1 in big endian mode is
1135 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1136 the byte sequence 99 99 f1 3f 9a 99 99 99.
1138 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1141 md_atof (int type
, char * litP
, int * sizeP
)
1144 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1176 return _("Unrecognized or unsupported floating point constant");
1179 t
= atof_ieee (input_line_pointer
, type
, words
);
1181 input_line_pointer
= t
;
1182 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1184 if (target_big_endian
)
1186 for (i
= 0; i
< prec
; i
++)
1188 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1189 litP
+= sizeof (LITTLENUM_TYPE
);
1194 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1195 for (i
= prec
- 1; i
>= 0; i
--)
1197 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1198 litP
+= sizeof (LITTLENUM_TYPE
);
1201 /* For a 4 byte float the order of elements in `words' is 1 0.
1202 For an 8 byte float the order is 1 0 3 2. */
1203 for (i
= 0; i
< prec
; i
+= 2)
1205 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1206 sizeof (LITTLENUM_TYPE
));
1207 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1208 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1209 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1216 /* We handle all bad expressions here, so that we can report the faulty
1217 instruction in the error message. */
1220 md_operand (expressionS
* exp
)
1222 if (in_my_get_expression
)
1223 exp
->X_op
= O_illegal
;
1226 /* Immediate values. */
1229 /* Generic immediate-value read function for use in directives.
1230 Accepts anything that 'expression' can fold to a constant.
1231 *val receives the number. */
1234 immediate_for_directive (int *val
)
1237 exp
.X_op
= O_illegal
;
1239 if (is_immediate_prefix (*input_line_pointer
))
1241 input_line_pointer
++;
1245 if (exp
.X_op
!= O_constant
)
1247 as_bad (_("expected #constant"));
1248 ignore_rest_of_line ();
1251 *val
= exp
.X_add_number
;
1256 /* Register parsing. */
1258 /* Generic register parser. CCP points to what should be the
1259 beginning of a register name. If it is indeed a valid register
1260 name, advance CCP over it and return the reg_entry structure;
1261 otherwise return NULL. Does not issue diagnostics. */
1263 static struct reg_entry
*
1264 arm_reg_parse_multi (char **ccp
)
1268 struct reg_entry
*reg
;
1270 skip_whitespace (start
);
1272 #ifdef REGISTER_PREFIX
1273 if (*start
!= REGISTER_PREFIX
)
1277 #ifdef OPTIONAL_REGISTER_PREFIX
1278 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1283 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1288 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1290 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1300 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1301 enum arm_reg_type type
)
1303 /* Alternative syntaxes are accepted for a few register classes. */
1310 /* Generic coprocessor register names are allowed for these. */
1311 if (reg
&& reg
->type
== REG_TYPE_CN
)
1316 /* For backward compatibility, a bare number is valid here. */
1318 unsigned long processor
= strtoul (start
, ccp
, 10);
1319 if (*ccp
!= start
&& processor
<= 15)
1324 case REG_TYPE_MMXWC
:
1325 /* WC includes WCG. ??? I'm not sure this is true for all
1326 instructions that take WC registers. */
1327 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1338 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1339 return value is the register number or FAIL. */
1342 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1345 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1348 /* Do not allow a scalar (reg+index) to parse as a register. */
1349 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1352 if (reg
&& reg
->type
== type
)
1355 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1362 /* Parse a Neon type specifier. *STR should point at the leading '.'
1363 character. Does no verification at this stage that the type fits the opcode
1370 Can all be legally parsed by this function.
1372 Fills in neon_type struct pointer with parsed information, and updates STR
1373 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1374 type, FAIL if not. */
1377 parse_neon_type (struct neon_type
*type
, char **str
)
1384 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1386 enum neon_el_type thistype
= NT_untyped
;
1387 unsigned thissize
= -1u;
1394 /* Just a size without an explicit type. */
1398 switch (TOLOWER (*ptr
))
1400 case 'i': thistype
= NT_integer
; break;
1401 case 'f': thistype
= NT_float
; break;
1402 case 'p': thistype
= NT_poly
; break;
1403 case 's': thistype
= NT_signed
; break;
1404 case 'u': thistype
= NT_unsigned
; break;
1406 thistype
= NT_float
;
1411 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1417 /* .f is an abbreviation for .f32. */
1418 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1423 thissize
= strtoul (ptr
, &ptr
, 10);
1425 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1428 as_bad (_("bad size %d in type specifier"), thissize
);
1436 type
->el
[type
->elems
].type
= thistype
;
1437 type
->el
[type
->elems
].size
= thissize
;
1442 /* Empty/missing type is not a successful parse. */
1443 if (type
->elems
== 0)
1451 /* Errors may be set multiple times during parsing or bit encoding
1452 (particularly in the Neon bits), but usually the earliest error which is set
1453 will be the most meaningful. Avoid overwriting it with later (cascading)
1454 errors by calling this function. */
1457 first_error (const char *err
)
1463 /* Parse a single type, e.g. ".s32", leading period included. */
1465 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1468 struct neon_type optype
;
1472 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1474 if (optype
.elems
== 1)
1475 *vectype
= optype
.el
[0];
1478 first_error (_("only one type should be specified for operand"));
1484 first_error (_("vector type expected"));
1496 /* Special meanings for indices (which have a range of 0-7), which will fit into
1499 #define NEON_ALL_LANES 15
1500 #define NEON_INTERLEAVE_LANES 14
1502 /* Parse either a register or a scalar, with an optional type. Return the
1503 register number, and optionally fill in the actual type of the register
1504 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1505 type/index information in *TYPEINFO. */
1508 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1509 enum arm_reg_type
*rtype
,
1510 struct neon_typed_alias
*typeinfo
)
1513 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1514 struct neon_typed_alias atype
;
1515 struct neon_type_el parsetype
;
1519 atype
.eltype
.type
= NT_invtype
;
1520 atype
.eltype
.size
= -1;
1522 /* Try alternate syntax for some types of register. Note these are mutually
1523 exclusive with the Neon syntax extensions. */
1526 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1534 /* Undo polymorphism when a set of register types may be accepted. */
1535 if ((type
== REG_TYPE_NDQ
1536 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1537 || (type
== REG_TYPE_VFSD
1538 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1539 || (type
== REG_TYPE_NSDQ
1540 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1541 || reg
->type
== REG_TYPE_NQ
))
1542 || (type
== REG_TYPE_NSD
1543 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1544 || (type
== REG_TYPE_MMXWC
1545 && (reg
->type
== REG_TYPE_MMXWCG
)))
1546 type
= (enum arm_reg_type
) reg
->type
;
1548 if (type
!= reg
->type
)
1554 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1556 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1558 first_error (_("can't redefine type for operand"));
1561 atype
.defined
|= NTA_HASTYPE
;
1562 atype
.eltype
= parsetype
;
1565 if (skip_past_char (&str
, '[') == SUCCESS
)
1567 if (type
!= REG_TYPE_VFD
1568 && !(type
== REG_TYPE_VFS
1569 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
)))
1571 first_error (_("only D registers may be indexed"));
1575 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1577 first_error (_("can't change index for operand"));
1581 atype
.defined
|= NTA_HASINDEX
;
1583 if (skip_past_char (&str
, ']') == SUCCESS
)
1584 atype
.index
= NEON_ALL_LANES
;
1589 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1591 if (exp
.X_op
!= O_constant
)
1593 first_error (_("constant expression required"));
1597 if (skip_past_char (&str
, ']') == FAIL
)
1600 atype
.index
= exp
.X_add_number
;
1615 /* Like arm_reg_parse, but allow allow the following extra features:
1616 - If RTYPE is non-zero, return the (possibly restricted) type of the
1617 register (e.g. Neon double or quad reg when either has been requested).
1618 - If this is a Neon vector type with additional type information, fill
1619 in the struct pointed to by VECTYPE (if non-NULL).
1620 This function will fault on encountering a scalar. */
1623 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1624 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1626 struct neon_typed_alias atype
;
1628 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1633 /* Do not allow regname(... to parse as a register. */
1637 /* Do not allow a scalar (reg+index) to parse as a register. */
1638 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1640 first_error (_("register operand expected, but got scalar"));
1645 *vectype
= atype
.eltype
;
1652 #define NEON_SCALAR_REG(X) ((X) >> 4)
1653 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1655 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1656 have enough information to be able to do a good job bounds-checking. So, we
1657 just do easy checks here, and do further checks later. */
1660 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
)
1664 struct neon_typed_alias atype
;
1665 enum arm_reg_type reg_type
= REG_TYPE_VFD
;
1668 reg_type
= REG_TYPE_VFS
;
1670 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1672 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1675 if (atype
.index
== NEON_ALL_LANES
)
1677 first_error (_("scalar must have an index"));
1680 else if (atype
.index
>= 64 / elsize
)
1682 first_error (_("scalar index out of range"));
1687 *type
= atype
.eltype
;
1691 return reg
* 16 + atype
.index
;
1694 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1697 parse_reg_list (char ** strp
)
1699 char * str
= * strp
;
1703 /* We come back here if we get ranges concatenated by '+' or '|'. */
1706 skip_whitespace (str
);
1720 if ((reg
= arm_reg_parse (&str
, REG_TYPE_RN
)) == FAIL
)
1722 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
1732 first_error (_("bad range in register list"));
1736 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1738 if (range
& (1 << i
))
1740 (_("Warning: duplicated register (r%d) in register list"),
1748 if (range
& (1 << reg
))
1749 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1751 else if (reg
<= cur_reg
)
1752 as_tsktsk (_("Warning: register range not in ascending order"));
1757 while (skip_past_comma (&str
) != FAIL
1758 || (in_range
= 1, *str
++ == '-'));
1761 if (skip_past_char (&str
, '}') == FAIL
)
1763 first_error (_("missing `}'"));
1771 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1774 if (exp
.X_op
== O_constant
)
1776 if (exp
.X_add_number
1777 != (exp
.X_add_number
& 0x0000ffff))
1779 inst
.error
= _("invalid register mask");
1783 if ((range
& exp
.X_add_number
) != 0)
1785 int regno
= range
& exp
.X_add_number
;
1788 regno
= (1 << regno
) - 1;
1790 (_("Warning: duplicated register (r%d) in register list"),
1794 range
|= exp
.X_add_number
;
1798 if (inst
.reloc
.type
!= 0)
1800 inst
.error
= _("expression too complex");
1804 memcpy (&inst
.reloc
.exp
, &exp
, sizeof (expressionS
));
1805 inst
.reloc
.type
= BFD_RELOC_ARM_MULTI
;
1806 inst
.reloc
.pc_rel
= 0;
1810 if (*str
== '|' || *str
== '+')
1816 while (another_range
);
1822 /* Types of registers in a list. */
1831 /* Parse a VFP register list. If the string is invalid return FAIL.
1832 Otherwise return the number of registers, and set PBASE to the first
1833 register. Parses registers of type ETYPE.
1834 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1835 - Q registers can be used to specify pairs of D registers
1836 - { } can be omitted from around a singleton register list
1837 FIXME: This is not implemented, as it would require backtracking in
1840 This could be done (the meaning isn't really ambiguous), but doesn't
1841 fit in well with the current parsing framework.
1842 - 32 D registers may be used (also true for VFPv3).
1843 FIXME: Types are ignored in these register lists, which is probably a
1847 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
)
1852 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
1856 unsigned long mask
= 0;
1859 if (skip_past_char (&str
, '{') == FAIL
)
1861 inst
.error
= _("expecting {");
1868 regtype
= REG_TYPE_VFS
;
1873 regtype
= REG_TYPE_VFD
;
1876 case REGLIST_NEON_D
:
1877 regtype
= REG_TYPE_NDQ
;
1881 if (etype
!= REGLIST_VFP_S
)
1883 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
1884 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
1888 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
1891 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
1898 base_reg
= max_regs
;
1902 int setmask
= 1, addregs
= 1;
1904 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
1906 if (new_base
== FAIL
)
1908 first_error (_(reg_expected_msgs
[regtype
]));
1912 if (new_base
>= max_regs
)
1914 first_error (_("register out of range in list"));
1918 /* Note: a value of 2 * n is returned for the register Q<n>. */
1919 if (regtype
== REG_TYPE_NQ
)
1925 if (new_base
< base_reg
)
1926 base_reg
= new_base
;
1928 if (mask
& (setmask
<< new_base
))
1930 first_error (_("invalid register list"));
1934 if ((mask
>> new_base
) != 0 && ! warned
)
1936 as_tsktsk (_("register list not in ascending order"));
1940 mask
|= setmask
<< new_base
;
1943 if (*str
== '-') /* We have the start of a range expression */
1949 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
1952 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
1956 if (high_range
>= max_regs
)
1958 first_error (_("register out of range in list"));
1962 if (regtype
== REG_TYPE_NQ
)
1963 high_range
= high_range
+ 1;
1965 if (high_range
<= new_base
)
1967 inst
.error
= _("register range not in ascending order");
1971 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
1973 if (mask
& (setmask
<< new_base
))
1975 inst
.error
= _("invalid register list");
1979 mask
|= setmask
<< new_base
;
1984 while (skip_past_comma (&str
) != FAIL
);
1988 /* Sanity check -- should have raised a parse error above. */
1989 if (count
== 0 || count
> max_regs
)
1994 /* Final test -- the registers must be consecutive. */
1996 for (i
= 0; i
< count
; i
++)
1998 if ((mask
& (1u << i
)) == 0)
2000 inst
.error
= _("non-contiguous register range");
2010 /* True if two alias types are the same. */
2013 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2021 if (a
->defined
!= b
->defined
)
2024 if ((a
->defined
& NTA_HASTYPE
) != 0
2025 && (a
->eltype
.type
!= b
->eltype
.type
2026 || a
->eltype
.size
!= b
->eltype
.size
))
2029 if ((a
->defined
& NTA_HASINDEX
) != 0
2030 && (a
->index
!= b
->index
))
2036 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2037 The base register is put in *PBASE.
2038 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2040 The register stride (minus one) is put in bit 4 of the return value.
2041 Bits [6:5] encode the list length (minus one).
2042 The type of the list elements is put in *ELTYPE, if non-NULL. */
2044 #define NEON_LANE(X) ((X) & 0xf)
2045 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2046 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2049 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2050 struct neon_type_el
*eltype
)
2057 int leading_brace
= 0;
2058 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2059 const char *const incr_error
= _("register stride must be 1 or 2");
2060 const char *const type_error
= _("mismatched element/structure types in list");
2061 struct neon_typed_alias firsttype
;
2062 firsttype
.defined
= 0;
2063 firsttype
.eltype
.type
= NT_invtype
;
2064 firsttype
.eltype
.size
= -1;
2065 firsttype
.index
= -1;
2067 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2072 struct neon_typed_alias atype
;
2073 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2077 first_error (_(reg_expected_msgs
[rtype
]));
2084 if (rtype
== REG_TYPE_NQ
)
2090 else if (reg_incr
== -1)
2092 reg_incr
= getreg
- base_reg
;
2093 if (reg_incr
< 1 || reg_incr
> 2)
2095 first_error (_(incr_error
));
2099 else if (getreg
!= base_reg
+ reg_incr
* count
)
2101 first_error (_(incr_error
));
2105 if (! neon_alias_types_same (&atype
, &firsttype
))
2107 first_error (_(type_error
));
2111 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2115 struct neon_typed_alias htype
;
2116 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2118 lane
= NEON_INTERLEAVE_LANES
;
2119 else if (lane
!= NEON_INTERLEAVE_LANES
)
2121 first_error (_(type_error
));
2126 else if (reg_incr
!= 1)
2128 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2132 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2135 first_error (_(reg_expected_msgs
[rtype
]));
2138 if (! neon_alias_types_same (&htype
, &firsttype
))
2140 first_error (_(type_error
));
2143 count
+= hireg
+ dregs
- getreg
;
2147 /* If we're using Q registers, we can't use [] or [n] syntax. */
2148 if (rtype
== REG_TYPE_NQ
)
2154 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2158 else if (lane
!= atype
.index
)
2160 first_error (_(type_error
));
2164 else if (lane
== -1)
2165 lane
= NEON_INTERLEAVE_LANES
;
2166 else if (lane
!= NEON_INTERLEAVE_LANES
)
2168 first_error (_(type_error
));
2173 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2175 /* No lane set by [x]. We must be interleaving structures. */
2177 lane
= NEON_INTERLEAVE_LANES
;
2180 if (lane
== -1 || base_reg
== -1 || count
< 1 || count
> 4
2181 || (count
> 1 && reg_incr
== -1))
2183 first_error (_("error parsing element/structure list"));
2187 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2189 first_error (_("expected }"));
2197 *eltype
= firsttype
.eltype
;
2202 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2205 /* Parse an explicit relocation suffix on an expression. This is
2206 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2207 arm_reloc_hsh contains no entries, so this function can only
2208 succeed if there is no () after the word. Returns -1 on error,
2209 BFD_RELOC_UNUSED if there wasn't any suffix. */
2212 parse_reloc (char **str
)
2214 struct reloc_entry
*r
;
2218 return BFD_RELOC_UNUSED
;
2223 while (*q
&& *q
!= ')' && *q
!= ',')
2228 if ((r
= (struct reloc_entry
*)
2229 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2236 /* Directives: register aliases. */
2238 static struct reg_entry
*
2239 insert_reg_alias (char *str
, unsigned number
, int type
)
2241 struct reg_entry
*new_reg
;
2244 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2246 if (new_reg
->builtin
)
2247 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2249 /* Only warn about a redefinition if it's not defined as the
2251 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2252 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2257 name
= xstrdup (str
);
2258 new_reg
= XNEW (struct reg_entry
);
2260 new_reg
->name
= name
;
2261 new_reg
->number
= number
;
2262 new_reg
->type
= type
;
2263 new_reg
->builtin
= FALSE
;
2264 new_reg
->neon
= NULL
;
2266 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2273 insert_neon_reg_alias (char *str
, int number
, int type
,
2274 struct neon_typed_alias
*atype
)
2276 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2280 first_error (_("attempt to redefine typed alias"));
2286 reg
->neon
= XNEW (struct neon_typed_alias
);
2287 *reg
->neon
= *atype
;
2291 /* Look for the .req directive. This is of the form:
2293 new_register_name .req existing_register_name
2295 If we find one, or if it looks sufficiently like one that we want to
2296 handle any error here, return TRUE. Otherwise return FALSE. */
2299 create_register_alias (char * newname
, char *p
)
2301 struct reg_entry
*old
;
2302 char *oldname
, *nbuf
;
2305 /* The input scrubber ensures that whitespace after the mnemonic is
2306 collapsed to single spaces. */
2308 if (strncmp (oldname
, " .req ", 6) != 0)
2312 if (*oldname
== '\0')
2315 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2318 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2322 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2323 the desired alias name, and p points to its end. If not, then
2324 the desired alias name is in the global original_case_string. */
2325 #ifdef TC_CASE_SENSITIVE
2328 newname
= original_case_string
;
2329 nlen
= strlen (newname
);
2332 nbuf
= xmemdup0 (newname
, nlen
);
2334 /* Create aliases under the new name as stated; an all-lowercase
2335 version of the new name; and an all-uppercase version of the new
2337 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2339 for (p
= nbuf
; *p
; p
++)
2342 if (strncmp (nbuf
, newname
, nlen
))
2344 /* If this attempt to create an additional alias fails, do not bother
2345 trying to create the all-lower case alias. We will fail and issue
2346 a second, duplicate error message. This situation arises when the
2347 programmer does something like:
2350 The second .req creates the "Foo" alias but then fails to create
2351 the artificial FOO alias because it has already been created by the
2353 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2360 for (p
= nbuf
; *p
; p
++)
2363 if (strncmp (nbuf
, newname
, nlen
))
2364 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2371 /* Create a Neon typed/indexed register alias using directives, e.g.:
2376 These typed registers can be used instead of the types specified after the
2377 Neon mnemonic, so long as all operands given have types. Types can also be
2378 specified directly, e.g.:
2379 vadd d0.s32, d1.s32, d2.s32 */
2382 create_neon_reg_alias (char *newname
, char *p
)
2384 enum arm_reg_type basetype
;
2385 struct reg_entry
*basereg
;
2386 struct reg_entry mybasereg
;
2387 struct neon_type ntype
;
2388 struct neon_typed_alias typeinfo
;
2389 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2392 typeinfo
.defined
= 0;
2393 typeinfo
.eltype
.type
= NT_invtype
;
2394 typeinfo
.eltype
.size
= -1;
2395 typeinfo
.index
= -1;
2399 if (strncmp (p
, " .dn ", 5) == 0)
2400 basetype
= REG_TYPE_VFD
;
2401 else if (strncmp (p
, " .qn ", 5) == 0)
2402 basetype
= REG_TYPE_NQ
;
2411 basereg
= arm_reg_parse_multi (&p
);
2413 if (basereg
&& basereg
->type
!= basetype
)
2415 as_bad (_("bad type for register"));
2419 if (basereg
== NULL
)
2422 /* Try parsing as an integer. */
2423 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2424 if (exp
.X_op
!= O_constant
)
2426 as_bad (_("expression must be constant"));
2429 basereg
= &mybasereg
;
2430 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2436 typeinfo
= *basereg
->neon
;
2438 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2440 /* We got a type. */
2441 if (typeinfo
.defined
& NTA_HASTYPE
)
2443 as_bad (_("can't redefine the type of a register alias"));
2447 typeinfo
.defined
|= NTA_HASTYPE
;
2448 if (ntype
.elems
!= 1)
2450 as_bad (_("you must specify a single type only"));
2453 typeinfo
.eltype
= ntype
.el
[0];
2456 if (skip_past_char (&p
, '[') == SUCCESS
)
2459 /* We got a scalar index. */
2461 if (typeinfo
.defined
& NTA_HASINDEX
)
2463 as_bad (_("can't redefine the index of a scalar alias"));
2467 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2469 if (exp
.X_op
!= O_constant
)
2471 as_bad (_("scalar index must be constant"));
2475 typeinfo
.defined
|= NTA_HASINDEX
;
2476 typeinfo
.index
= exp
.X_add_number
;
2478 if (skip_past_char (&p
, ']') == FAIL
)
2480 as_bad (_("expecting ]"));
2485 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2486 the desired alias name, and p points to its end. If not, then
2487 the desired alias name is in the global original_case_string. */
2488 #ifdef TC_CASE_SENSITIVE
2489 namelen
= nameend
- newname
;
2491 newname
= original_case_string
;
2492 namelen
= strlen (newname
);
2495 namebuf
= xmemdup0 (newname
, namelen
);
2497 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2498 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2500 /* Insert name in all uppercase. */
2501 for (p
= namebuf
; *p
; p
++)
2504 if (strncmp (namebuf
, newname
, namelen
))
2505 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2506 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2508 /* Insert name in all lowercase. */
2509 for (p
= namebuf
; *p
; p
++)
2512 if (strncmp (namebuf
, newname
, namelen
))
2513 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2514 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2520 /* Should never be called, as .req goes between the alias and the
2521 register name, not at the beginning of the line. */
2524 s_req (int a ATTRIBUTE_UNUSED
)
2526 as_bad (_("invalid syntax for .req directive"));
2530 s_dn (int a ATTRIBUTE_UNUSED
)
2532 as_bad (_("invalid syntax for .dn directive"));
2536 s_qn (int a ATTRIBUTE_UNUSED
)
2538 as_bad (_("invalid syntax for .qn directive"));
2541 /* The .unreq directive deletes an alias which was previously defined
2542 by .req. For example:
2548 s_unreq (int a ATTRIBUTE_UNUSED
)
2553 name
= input_line_pointer
;
2555 while (*input_line_pointer
!= 0
2556 && *input_line_pointer
!= ' '
2557 && *input_line_pointer
!= '\n')
2558 ++input_line_pointer
;
2560 saved_char
= *input_line_pointer
;
2561 *input_line_pointer
= 0;
2564 as_bad (_("invalid syntax for .unreq directive"));
2567 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2571 as_bad (_("unknown register alias '%s'"), name
);
2572 else if (reg
->builtin
)
2573 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2580 hash_delete (arm_reg_hsh
, name
, FALSE
);
2581 free ((char *) reg
->name
);
2586 /* Also locate the all upper case and all lower case versions.
2587 Do not complain if we cannot find one or the other as it
2588 was probably deleted above. */
2590 nbuf
= strdup (name
);
2591 for (p
= nbuf
; *p
; p
++)
2593 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2596 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2597 free ((char *) reg
->name
);
2603 for (p
= nbuf
; *p
; p
++)
2605 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2608 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2609 free ((char *) reg
->name
);
2619 *input_line_pointer
= saved_char
;
2620 demand_empty_rest_of_line ();
2623 /* Directives: Instruction set selection. */
2626 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2627 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2628 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2629 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2631 /* Create a new mapping symbol for the transition to STATE. */
2634 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2637 const char * symname
;
2644 type
= BSF_NO_FLAGS
;
2648 type
= BSF_NO_FLAGS
;
2652 type
= BSF_NO_FLAGS
;
2658 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2659 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2664 THUMB_SET_FUNC (symbolP
, 0);
2665 ARM_SET_THUMB (symbolP
, 0);
2666 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2670 THUMB_SET_FUNC (symbolP
, 1);
2671 ARM_SET_THUMB (symbolP
, 1);
2672 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2680 /* Save the mapping symbols for future reference. Also check that
2681 we do not place two mapping symbols at the same offset within a
2682 frag. We'll handle overlap between frags in
2683 check_mapping_symbols.
2685 If .fill or other data filling directive generates zero sized data,
2686 the mapping symbol for the following code will have the same value
2687 as the one generated for the data filling directive. In this case,
2688 we replace the old symbol with the new one at the same address. */
2691 if (frag
->tc_frag_data
.first_map
!= NULL
)
2693 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2694 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2696 frag
->tc_frag_data
.first_map
= symbolP
;
2698 if (frag
->tc_frag_data
.last_map
!= NULL
)
2700 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2701 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2702 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2704 frag
->tc_frag_data
.last_map
= symbolP
;
2707 /* We must sometimes convert a region marked as code to data during
2708 code alignment, if an odd number of bytes have to be padded. The
2709 code mapping symbol is pushed to an aligned address. */
2712 insert_data_mapping_symbol (enum mstate state
,
2713 valueT value
, fragS
*frag
, offsetT bytes
)
2715 /* If there was already a mapping symbol, remove it. */
2716 if (frag
->tc_frag_data
.last_map
!= NULL
2717 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2719 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2723 know (frag
->tc_frag_data
.first_map
== symp
);
2724 frag
->tc_frag_data
.first_map
= NULL
;
2726 frag
->tc_frag_data
.last_map
= NULL
;
2727 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2730 make_mapping_symbol (MAP_DATA
, value
, frag
);
2731 make_mapping_symbol (state
, value
+ bytes
, frag
);
2734 static void mapping_state_2 (enum mstate state
, int max_chars
);
2736 /* Set the mapping state to STATE. Only call this when about to
2737 emit some STATE bytes to the file. */
2739 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2741 mapping_state (enum mstate state
)
2743 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2745 if (mapstate
== state
)
2746 /* The mapping symbol has already been emitted.
2747 There is nothing else to do. */
2750 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2752 All ARM instructions require 4-byte alignment.
2753 (Almost) all Thumb instructions require 2-byte alignment.
2755 When emitting instructions into any section, mark the section
2758 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2759 but themselves require 2-byte alignment; this applies to some
2760 PC- relative forms. However, these cases will involve implicit
2761 literal pool generation or an explicit .align >=2, both of
2762 which will cause the section to me marked with sufficient
2763 alignment. Thus, we don't handle those cases here. */
2764 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2766 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2767 /* This case will be evaluated later. */
2770 mapping_state_2 (state
, 0);
2773 /* Same as mapping_state, but MAX_CHARS bytes have already been
2774 allocated. Put the mapping symbol that far back. */
2777 mapping_state_2 (enum mstate state
, int max_chars
)
2779 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2781 if (!SEG_NORMAL (now_seg
))
2784 if (mapstate
== state
)
2785 /* The mapping symbol has already been emitted.
2786 There is nothing else to do. */
2789 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
2790 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
2792 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
2793 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
2796 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
2799 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
2800 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
2804 #define mapping_state(x) ((void)0)
2805 #define mapping_state_2(x, y) ((void)0)
2808 /* Find the real, Thumb encoded start of a Thumb function. */
2812 find_real_start (symbolS
* symbolP
)
2815 const char * name
= S_GET_NAME (symbolP
);
2816 symbolS
* new_target
;
2818 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
2819 #define STUB_NAME ".real_start_of"
2824 /* The compiler may generate BL instructions to local labels because
2825 it needs to perform a branch to a far away location. These labels
2826 do not have a corresponding ".real_start_of" label. We check
2827 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
2828 the ".real_start_of" convention for nonlocal branches. */
2829 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
2832 real_start
= concat (STUB_NAME
, name
, NULL
);
2833 new_target
= symbol_find (real_start
);
2836 if (new_target
== NULL
)
2838 as_warn (_("Failed to find real start of function: %s\n"), name
);
2839 new_target
= symbolP
;
2847 opcode_select (int width
)
2854 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
2855 as_bad (_("selected processor does not support THUMB opcodes"));
2858 /* No need to force the alignment, since we will have been
2859 coming from ARM mode, which is word-aligned. */
2860 record_alignment (now_seg
, 1);
2867 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
2868 as_bad (_("selected processor does not support ARM opcodes"));
2873 frag_align (2, 0, 0);
2875 record_alignment (now_seg
, 1);
2880 as_bad (_("invalid instruction size selected (%d)"), width
);
2885 s_arm (int ignore ATTRIBUTE_UNUSED
)
2888 demand_empty_rest_of_line ();
2892 s_thumb (int ignore ATTRIBUTE_UNUSED
)
2895 demand_empty_rest_of_line ();
2899 s_code (int unused ATTRIBUTE_UNUSED
)
2903 temp
= get_absolute_expression ();
2908 opcode_select (temp
);
2912 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
2917 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
2919 /* If we are not already in thumb mode go into it, EVEN if
2920 the target processor does not support thumb instructions.
2921 This is used by gcc/config/arm/lib1funcs.asm for example
2922 to compile interworking support functions even if the
2923 target processor should not support interworking. */
2927 record_alignment (now_seg
, 1);
2930 demand_empty_rest_of_line ();
2934 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
2938 /* The following label is the name/address of the start of a Thumb function.
2939 We need to know this for the interworking support. */
2940 label_is_thumb_function_name
= TRUE
;
2943 /* Perform a .set directive, but also mark the alias as
2944 being a thumb function. */
2947 s_thumb_set (int equiv
)
2949 /* XXX the following is a duplicate of the code for s_set() in read.c
2950 We cannot just call that code as we need to get at the symbol that
2957 /* Especial apologies for the random logic:
2958 This just grew, and could be parsed much more simply!
2960 delim
= get_symbol_name (& name
);
2961 end_name
= input_line_pointer
;
2962 (void) restore_line_pointer (delim
);
2964 if (*input_line_pointer
!= ',')
2967 as_bad (_("expected comma after name \"%s\""), name
);
2969 ignore_rest_of_line ();
2973 input_line_pointer
++;
2976 if (name
[0] == '.' && name
[1] == '\0')
2978 /* XXX - this should not happen to .thumb_set. */
2982 if ((symbolP
= symbol_find (name
)) == NULL
2983 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
2986 /* When doing symbol listings, play games with dummy fragments living
2987 outside the normal fragment chain to record the file and line info
2989 if (listing
& LISTING_SYMBOLS
)
2991 extern struct list_info_struct
* listing_tail
;
2992 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
2994 memset (dummy_frag
, 0, sizeof (fragS
));
2995 dummy_frag
->fr_type
= rs_fill
;
2996 dummy_frag
->line
= listing_tail
;
2997 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
2998 dummy_frag
->fr_symbol
= symbolP
;
3002 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3005 /* "set" symbols are local unless otherwise specified. */
3006 SF_SET_LOCAL (symbolP
);
3007 #endif /* OBJ_COFF */
3008 } /* Make a new symbol. */
3010 symbol_table_insert (symbolP
);
3015 && S_IS_DEFINED (symbolP
)
3016 && S_GET_SEGMENT (symbolP
) != reg_section
)
3017 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3019 pseudo_set (symbolP
);
3021 demand_empty_rest_of_line ();
3023 /* XXX Now we come to the Thumb specific bit of code. */
3025 THUMB_SET_FUNC (symbolP
, 1);
3026 ARM_SET_THUMB (symbolP
, 1);
3027 #if defined OBJ_ELF || defined OBJ_COFF
3028 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3032 /* Directives: Mode selection. */
3034 /* .syntax [unified|divided] - choose the new unified syntax
3035 (same for Arm and Thumb encoding, modulo slight differences in what
3036 can be represented) or the old divergent syntax for each mode. */
3038 s_syntax (int unused ATTRIBUTE_UNUSED
)
3042 delim
= get_symbol_name (& name
);
3044 if (!strcasecmp (name
, "unified"))
3045 unified_syntax
= TRUE
;
3046 else if (!strcasecmp (name
, "divided"))
3047 unified_syntax
= FALSE
;
3050 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3053 (void) restore_line_pointer (delim
);
3054 demand_empty_rest_of_line ();
3057 /* Directives: sectioning and alignment. */
3060 s_bss (int ignore ATTRIBUTE_UNUSED
)
3062 /* We don't support putting frags in the BSS segment, we fake it by
3063 marking in_bss, then looking at s_skip for clues. */
3064 subseg_set (bss_section
, 0);
3065 demand_empty_rest_of_line ();
3067 #ifdef md_elf_section_change_hook
3068 md_elf_section_change_hook ();
3073 s_even (int ignore ATTRIBUTE_UNUSED
)
3075 /* Never make frag if expect extra pass. */
3077 frag_align (1, 0, 0);
3079 record_alignment (now_seg
, 1);
3081 demand_empty_rest_of_line ();
3084 /* Directives: CodeComposer Studio. */
3086 /* .ref (for CodeComposer Studio syntax only). */
3088 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3090 if (codecomposer_syntax
)
3091 ignore_rest_of_line ();
3093 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3096 /* If name is not NULL, then it is used for marking the beginning of a
3097 function, whereas if it is NULL then it means the function end. */
3099 asmfunc_debug (const char * name
)
3101 static const char * last_name
= NULL
;
3105 gas_assert (last_name
== NULL
);
3108 if (debug_type
== DEBUG_STABS
)
3109 stabs_generate_asm_func (name
, name
);
3113 gas_assert (last_name
!= NULL
);
3115 if (debug_type
== DEBUG_STABS
)
3116 stabs_generate_asm_endfunc (last_name
, last_name
);
3123 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3125 if (codecomposer_syntax
)
3127 switch (asmfunc_state
)
3129 case OUTSIDE_ASMFUNC
:
3130 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3133 case WAITING_ASMFUNC_NAME
:
3134 as_bad (_(".asmfunc repeated."));
3137 case WAITING_ENDASMFUNC
:
3138 as_bad (_(".asmfunc without function."));
3141 demand_empty_rest_of_line ();
3144 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3148 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3150 if (codecomposer_syntax
)
3152 switch (asmfunc_state
)
3154 case OUTSIDE_ASMFUNC
:
3155 as_bad (_(".endasmfunc without a .asmfunc."));
3158 case WAITING_ASMFUNC_NAME
:
3159 as_bad (_(".endasmfunc without function."));
3162 case WAITING_ENDASMFUNC
:
3163 asmfunc_state
= OUTSIDE_ASMFUNC
;
3164 asmfunc_debug (NULL
);
3167 demand_empty_rest_of_line ();
3170 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3174 s_ccs_def (int name
)
3176 if (codecomposer_syntax
)
3179 as_bad (_(".def pseudo-op only available with -mccs flag."));
3182 /* Directives: Literal pools. */
3184 static literal_pool
*
3185 find_literal_pool (void)
3187 literal_pool
* pool
;
3189 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3191 if (pool
->section
== now_seg
3192 && pool
->sub_section
== now_subseg
)
3199 static literal_pool
*
3200 find_or_make_literal_pool (void)
3202 /* Next literal pool ID number. */
3203 static unsigned int latest_pool_num
= 1;
3204 literal_pool
* pool
;
3206 pool
= find_literal_pool ();
3210 /* Create a new pool. */
3211 pool
= XNEW (literal_pool
);
3215 pool
->next_free_entry
= 0;
3216 pool
->section
= now_seg
;
3217 pool
->sub_section
= now_subseg
;
3218 pool
->next
= list_of_pools
;
3219 pool
->symbol
= NULL
;
3220 pool
->alignment
= 2;
3222 /* Add it to the list. */
3223 list_of_pools
= pool
;
3226 /* New pools, and emptied pools, will have a NULL symbol. */
3227 if (pool
->symbol
== NULL
)
3229 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3230 (valueT
) 0, &zero_address_frag
);
3231 pool
->id
= latest_pool_num
++;
3238 /* Add the literal in the global 'inst'
3239 structure to the relevant literal pool. */
3242 add_to_lit_pool (unsigned int nbytes
)
3244 #define PADDING_SLOT 0x1
3245 #define LIT_ENTRY_SIZE_MASK 0xFF
3246 literal_pool
* pool
;
3247 unsigned int entry
, pool_size
= 0;
3248 bfd_boolean padding_slot_p
= FALSE
;
3254 imm1
= inst
.operands
[1].imm
;
3255 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3256 : inst
.reloc
.exp
.X_unsigned
? 0
3257 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3258 if (target_big_endian
)
3261 imm2
= inst
.operands
[1].imm
;
3265 pool
= find_or_make_literal_pool ();
3267 /* Check if this literal value is already in the pool. */
3268 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3272 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3273 && (inst
.reloc
.exp
.X_op
== O_constant
)
3274 && (pool
->literals
[entry
].X_add_number
3275 == inst
.reloc
.exp
.X_add_number
)
3276 && (pool
->literals
[entry
].X_md
== nbytes
)
3277 && (pool
->literals
[entry
].X_unsigned
3278 == inst
.reloc
.exp
.X_unsigned
))
3281 if ((pool
->literals
[entry
].X_op
== inst
.reloc
.exp
.X_op
)
3282 && (inst
.reloc
.exp
.X_op
== O_symbol
)
3283 && (pool
->literals
[entry
].X_add_number
3284 == inst
.reloc
.exp
.X_add_number
)
3285 && (pool
->literals
[entry
].X_add_symbol
3286 == inst
.reloc
.exp
.X_add_symbol
)
3287 && (pool
->literals
[entry
].X_op_symbol
3288 == inst
.reloc
.exp
.X_op_symbol
)
3289 && (pool
->literals
[entry
].X_md
== nbytes
))
3292 else if ((nbytes
== 8)
3293 && !(pool_size
& 0x7)
3294 && ((entry
+ 1) != pool
->next_free_entry
)
3295 && (pool
->literals
[entry
].X_op
== O_constant
)
3296 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3297 && (pool
->literals
[entry
].X_unsigned
3298 == inst
.reloc
.exp
.X_unsigned
)
3299 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3300 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3301 && (pool
->literals
[entry
+ 1].X_unsigned
3302 == inst
.reloc
.exp
.X_unsigned
))
3305 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3306 if (padding_slot_p
&& (nbytes
== 4))
3312 /* Do we need to create a new entry? */
3313 if (entry
== pool
->next_free_entry
)
3315 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3317 inst
.error
= _("literal pool overflow");
3323 /* For 8-byte entries, we align to an 8-byte boundary,
3324 and split it into two 4-byte entries, because on 32-bit
3325 host, 8-byte constants are treated as big num, thus
3326 saved in "generic_bignum" which will be overwritten
3327 by later assignments.
3329 We also need to make sure there is enough space for
3332 We also check to make sure the literal operand is a
3334 if (!(inst
.reloc
.exp
.X_op
== O_constant
3335 || inst
.reloc
.exp
.X_op
== O_big
))
3337 inst
.error
= _("invalid type for literal pool");
3340 else if (pool_size
& 0x7)
3342 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3344 inst
.error
= _("literal pool overflow");
3348 pool
->literals
[entry
] = inst
.reloc
.exp
;
3349 pool
->literals
[entry
].X_op
= O_constant
;
3350 pool
->literals
[entry
].X_add_number
= 0;
3351 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3352 pool
->next_free_entry
+= 1;
3355 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3357 inst
.error
= _("literal pool overflow");
3361 pool
->literals
[entry
] = inst
.reloc
.exp
;
3362 pool
->literals
[entry
].X_op
= O_constant
;
3363 pool
->literals
[entry
].X_add_number
= imm1
;
3364 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3365 pool
->literals
[entry
++].X_md
= 4;
3366 pool
->literals
[entry
] = inst
.reloc
.exp
;
3367 pool
->literals
[entry
].X_op
= O_constant
;
3368 pool
->literals
[entry
].X_add_number
= imm2
;
3369 pool
->literals
[entry
].X_unsigned
= inst
.reloc
.exp
.X_unsigned
;
3370 pool
->literals
[entry
].X_md
= 4;
3371 pool
->alignment
= 3;
3372 pool
->next_free_entry
+= 1;
3376 pool
->literals
[entry
] = inst
.reloc
.exp
;
3377 pool
->literals
[entry
].X_md
= 4;
3381 /* PR ld/12974: Record the location of the first source line to reference
3382 this entry in the literal pool. If it turns out during linking that the
3383 symbol does not exist we will be able to give an accurate line number for
3384 the (first use of the) missing reference. */
3385 if (debug_type
== DEBUG_DWARF2
)
3386 dwarf2_where (pool
->locs
+ entry
);
3388 pool
->next_free_entry
+= 1;
3390 else if (padding_slot_p
)
3392 pool
->literals
[entry
] = inst
.reloc
.exp
;
3393 pool
->literals
[entry
].X_md
= nbytes
;
3396 inst
.reloc
.exp
.X_op
= O_symbol
;
3397 inst
.reloc
.exp
.X_add_number
= pool_size
;
3398 inst
.reloc
.exp
.X_add_symbol
= pool
->symbol
;
3404 tc_start_label_without_colon (void)
3406 bfd_boolean ret
= TRUE
;
3408 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3410 const char *label
= input_line_pointer
;
3412 while (!is_end_of_line
[(int) label
[-1]])
3417 as_bad (_("Invalid label '%s'"), label
);
3421 asmfunc_debug (label
);
3423 asmfunc_state
= WAITING_ENDASMFUNC
;
3429 /* Can't use symbol_new here, so have to create a symbol and then at
3430 a later date assign it a value. That's what these functions do. */
3433 symbol_locate (symbolS
* symbolP
,
3434 const char * name
, /* It is copied, the caller can modify. */
3435 segT segment
, /* Segment identifier (SEG_<something>). */
3436 valueT valu
, /* Symbol value. */
3437 fragS
* frag
) /* Associated fragment. */
3440 char * preserved_copy_of_name
;
3442 name_length
= strlen (name
) + 1; /* +1 for \0. */
3443 obstack_grow (¬es
, name
, name_length
);
3444 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3446 #ifdef tc_canonicalize_symbol_name
3447 preserved_copy_of_name
=
3448 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3451 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3453 S_SET_SEGMENT (symbolP
, segment
);
3454 S_SET_VALUE (symbolP
, valu
);
3455 symbol_clear_list_pointers (symbolP
);
3457 symbol_set_frag (symbolP
, frag
);
3459 /* Link to end of symbol chain. */
3461 extern int symbol_table_frozen
;
3463 if (symbol_table_frozen
)
3467 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3469 obj_symbol_new_hook (symbolP
);
3471 #ifdef tc_symbol_new_hook
3472 tc_symbol_new_hook (symbolP
);
3476 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3477 #endif /* DEBUG_SYMS */
3481 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3484 literal_pool
* pool
;
3487 pool
= find_literal_pool ();
3489 || pool
->symbol
== NULL
3490 || pool
->next_free_entry
== 0)
3493 /* Align pool as you have word accesses.
3494 Only make a frag if we have to. */
3496 frag_align (pool
->alignment
, 0, 0);
3498 record_alignment (now_seg
, 2);
3501 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3502 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3504 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3506 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3507 (valueT
) frag_now_fix (), frag_now
);
3508 symbol_table_insert (pool
->symbol
);
3510 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3512 #if defined OBJ_COFF || defined OBJ_ELF
3513 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3516 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3519 if (debug_type
== DEBUG_DWARF2
)
3520 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3522 /* First output the expression in the instruction to the pool. */
3523 emit_expr (&(pool
->literals
[entry
]),
3524 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3527 /* Mark the pool as empty. */
3528 pool
->next_free_entry
= 0;
3529 pool
->symbol
= NULL
;
3533 /* Forward declarations for functions below, in the MD interface
3535 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3536 static valueT
create_unwind_entry (int);
3537 static void start_unwind_section (const segT
, int);
3538 static void add_unwind_opcode (valueT
, int);
3539 static void flush_pending_unwind (void);
3541 /* Directives: Data. */
3544 s_arm_elf_cons (int nbytes
)
3548 #ifdef md_flush_pending_output
3549 md_flush_pending_output ();
3552 if (is_it_end_of_statement ())
3554 demand_empty_rest_of_line ();
3558 #ifdef md_cons_align
3559 md_cons_align (nbytes
);
3562 mapping_state (MAP_DATA
);
3566 char *base
= input_line_pointer
;
3570 if (exp
.X_op
!= O_symbol
)
3571 emit_expr (&exp
, (unsigned int) nbytes
);
3574 char *before_reloc
= input_line_pointer
;
3575 reloc
= parse_reloc (&input_line_pointer
);
3578 as_bad (_("unrecognized relocation suffix"));
3579 ignore_rest_of_line ();
3582 else if (reloc
== BFD_RELOC_UNUSED
)
3583 emit_expr (&exp
, (unsigned int) nbytes
);
3586 reloc_howto_type
*howto
= (reloc_howto_type
*)
3587 bfd_reloc_type_lookup (stdoutput
,
3588 (bfd_reloc_code_real_type
) reloc
);
3589 int size
= bfd_get_reloc_size (howto
);
3591 if (reloc
== BFD_RELOC_ARM_PLT32
)
3593 as_bad (_("(plt) is only valid on branch targets"));
3594 reloc
= BFD_RELOC_UNUSED
;
3599 as_bad (ngettext ("%s relocations do not fit in %d byte",
3600 "%s relocations do not fit in %d bytes",
3602 howto
->name
, nbytes
);
3605 /* We've parsed an expression stopping at O_symbol.
3606 But there may be more expression left now that we
3607 have parsed the relocation marker. Parse it again.
3608 XXX Surely there is a cleaner way to do this. */
3609 char *p
= input_line_pointer
;
3611 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3613 memcpy (save_buf
, base
, input_line_pointer
- base
);
3614 memmove (base
+ (input_line_pointer
- before_reloc
),
3615 base
, before_reloc
- base
);
3617 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3619 memcpy (base
, save_buf
, p
- base
);
3621 offset
= nbytes
- size
;
3622 p
= frag_more (nbytes
);
3623 memset (p
, 0, nbytes
);
3624 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3625 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3631 while (*input_line_pointer
++ == ',');
3633 /* Put terminator back into stream. */
3634 input_line_pointer
--;
3635 demand_empty_rest_of_line ();
3638 /* Emit an expression containing a 32-bit thumb instruction.
3639 Implementation based on put_thumb32_insn. */
3642 emit_thumb32_expr (expressionS
* exp
)
3644 expressionS exp_high
= *exp
;
3646 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3647 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3648 exp
->X_add_number
&= 0xffff;
3649 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3652 /* Guess the instruction size based on the opcode. */
3655 thumb_insn_size (int opcode
)
3657 if ((unsigned int) opcode
< 0xe800u
)
3659 else if ((unsigned int) opcode
>= 0xe8000000u
)
3666 emit_insn (expressionS
*exp
, int nbytes
)
3670 if (exp
->X_op
== O_constant
)
3675 size
= thumb_insn_size (exp
->X_add_number
);
3679 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3681 as_bad (_(".inst.n operand too big. "\
3682 "Use .inst.w instead"));
3687 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
3688 set_it_insn_type_nonvoid (OUTSIDE_IT_INSN
, 0);
3690 set_it_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3692 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3693 emit_thumb32_expr (exp
);
3695 emit_expr (exp
, (unsigned int) size
);
3697 it_fsm_post_encode ();
3701 as_bad (_("cannot determine Thumb instruction size. " \
3702 "Use .inst.n/.inst.w instead"));
3705 as_bad (_("constant expression required"));
3710 /* Like s_arm_elf_cons but do not use md_cons_align and
3711 set the mapping state to MAP_ARM/MAP_THUMB. */
3714 s_arm_elf_inst (int nbytes
)
3716 if (is_it_end_of_statement ())
3718 demand_empty_rest_of_line ();
3722 /* Calling mapping_state () here will not change ARM/THUMB,
3723 but will ensure not to be in DATA state. */
3726 mapping_state (MAP_THUMB
);
3731 as_bad (_("width suffixes are invalid in ARM mode"));
3732 ignore_rest_of_line ();
3738 mapping_state (MAP_ARM
);
3747 if (! emit_insn (& exp
, nbytes
))
3749 ignore_rest_of_line ();
3753 while (*input_line_pointer
++ == ',');
3755 /* Put terminator back into stream. */
3756 input_line_pointer
--;
3757 demand_empty_rest_of_line ();
3760 /* Parse a .rel31 directive. */
3763 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3770 if (*input_line_pointer
== '1')
3771 highbit
= 0x80000000;
3772 else if (*input_line_pointer
!= '0')
3773 as_bad (_("expected 0 or 1"));
3775 input_line_pointer
++;
3776 if (*input_line_pointer
!= ',')
3777 as_bad (_("missing comma"));
3778 input_line_pointer
++;
3780 #ifdef md_flush_pending_output
3781 md_flush_pending_output ();
3784 #ifdef md_cons_align
3788 mapping_state (MAP_DATA
);
3793 md_number_to_chars (p
, highbit
, 4);
3794 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
3795 BFD_RELOC_ARM_PREL31
);
3797 demand_empty_rest_of_line ();
3800 /* Directives: AEABI stack-unwind tables. */
3802 /* Parse an unwind_fnstart directive. Simply records the current location. */
3805 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
3807 demand_empty_rest_of_line ();
3808 if (unwind
.proc_start
)
3810 as_bad (_("duplicate .fnstart directive"));
3814 /* Mark the start of the function. */
3815 unwind
.proc_start
= expr_build_dot ();
3817 /* Reset the rest of the unwind info. */
3818 unwind
.opcode_count
= 0;
3819 unwind
.table_entry
= NULL
;
3820 unwind
.personality_routine
= NULL
;
3821 unwind
.personality_index
= -1;
3822 unwind
.frame_size
= 0;
3823 unwind
.fp_offset
= 0;
3824 unwind
.fp_reg
= REG_SP
;
3826 unwind
.sp_restored
= 0;
3830 /* Parse a handlerdata directive. Creates the exception handling table entry
3831 for the function. */
3834 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
3836 demand_empty_rest_of_line ();
3837 if (!unwind
.proc_start
)
3838 as_bad (MISSING_FNSTART
);
3840 if (unwind
.table_entry
)
3841 as_bad (_("duplicate .handlerdata directive"));
3843 create_unwind_entry (1);
3846 /* Parse an unwind_fnend directive. Generates the index table entry. */
3849 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
3854 unsigned int marked_pr_dependency
;
3856 demand_empty_rest_of_line ();
3858 if (!unwind
.proc_start
)
3860 as_bad (_(".fnend directive without .fnstart"));
3864 /* Add eh table entry. */
3865 if (unwind
.table_entry
== NULL
)
3866 val
= create_unwind_entry (0);
3870 /* Add index table entry. This is two words. */
3871 start_unwind_section (unwind
.saved_seg
, 1);
3872 frag_align (2, 0, 0);
3873 record_alignment (now_seg
, 2);
3875 ptr
= frag_more (8);
3877 where
= frag_now_fix () - 8;
3879 /* Self relative offset of the function start. */
3880 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
3881 BFD_RELOC_ARM_PREL31
);
3883 /* Indicate dependency on EHABI-defined personality routines to the
3884 linker, if it hasn't been done already. */
3885 marked_pr_dependency
3886 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
3887 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
3888 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
3890 static const char *const name
[] =
3892 "__aeabi_unwind_cpp_pr0",
3893 "__aeabi_unwind_cpp_pr1",
3894 "__aeabi_unwind_cpp_pr2"
3896 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
3897 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
3898 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
3899 |= 1 << unwind
.personality_index
;
3903 /* Inline exception table entry. */
3904 md_number_to_chars (ptr
+ 4, val
, 4);
3906 /* Self relative offset of the table entry. */
3907 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
3908 BFD_RELOC_ARM_PREL31
);
3910 /* Restore the original section. */
3911 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
3913 unwind
.proc_start
= NULL
;
3917 /* Parse an unwind_cantunwind directive. */
3920 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
3922 demand_empty_rest_of_line ();
3923 if (!unwind
.proc_start
)
3924 as_bad (MISSING_FNSTART
);
3926 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3927 as_bad (_("personality routine specified for cantunwind frame"));
3929 unwind
.personality_index
= -2;
3933 /* Parse a personalityindex directive. */
3936 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
3940 if (!unwind
.proc_start
)
3941 as_bad (MISSING_FNSTART
);
3943 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3944 as_bad (_("duplicate .personalityindex directive"));
3948 if (exp
.X_op
!= O_constant
3949 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
3951 as_bad (_("bad personality routine number"));
3952 ignore_rest_of_line ();
3956 unwind
.personality_index
= exp
.X_add_number
;
3958 demand_empty_rest_of_line ();
3962 /* Parse a personality directive. */
3965 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
3969 if (!unwind
.proc_start
)
3970 as_bad (MISSING_FNSTART
);
3972 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
3973 as_bad (_("duplicate .personality directive"));
3975 c
= get_symbol_name (& name
);
3976 p
= input_line_pointer
;
3978 ++ input_line_pointer
;
3979 unwind
.personality_routine
= symbol_find_or_make (name
);
3981 demand_empty_rest_of_line ();
3985 /* Parse a directive saving core registers. */
3988 s_arm_unwind_save_core (void)
3994 range
= parse_reg_list (&input_line_pointer
);
3997 as_bad (_("expected register list"));
3998 ignore_rest_of_line ();
4002 demand_empty_rest_of_line ();
4004 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4005 into .unwind_save {..., sp...}. We aren't bothered about the value of
4006 ip because it is clobbered by calls. */
4007 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4008 && (range
& 0x3000) == 0x1000)
4010 unwind
.opcode_count
--;
4011 unwind
.sp_restored
= 0;
4012 range
= (range
| 0x2000) & ~0x1000;
4013 unwind
.pending_offset
= 0;
4019 /* See if we can use the short opcodes. These pop a block of up to 8
4020 registers starting with r4, plus maybe r14. */
4021 for (n
= 0; n
< 8; n
++)
4023 /* Break at the first non-saved register. */
4024 if ((range
& (1 << (n
+ 4))) == 0)
4027 /* See if there are any other bits set. */
4028 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4030 /* Use the long form. */
4031 op
= 0x8000 | ((range
>> 4) & 0xfff);
4032 add_unwind_opcode (op
, 2);
4036 /* Use the short form. */
4038 op
= 0xa8; /* Pop r14. */
4040 op
= 0xa0; /* Do not pop r14. */
4042 add_unwind_opcode (op
, 1);
4049 op
= 0xb100 | (range
& 0xf);
4050 add_unwind_opcode (op
, 2);
4053 /* Record the number of bytes pushed. */
4054 for (n
= 0; n
< 16; n
++)
4056 if (range
& (1 << n
))
4057 unwind
.frame_size
+= 4;
4062 /* Parse a directive saving FPA registers. */
4065 s_arm_unwind_save_fpa (int reg
)
4071 /* Get Number of registers to transfer. */
4072 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4075 exp
.X_op
= O_illegal
;
4077 if (exp
.X_op
!= O_constant
)
4079 as_bad (_("expected , <constant>"));
4080 ignore_rest_of_line ();
4084 num_regs
= exp
.X_add_number
;
4086 if (num_regs
< 1 || num_regs
> 4)
4088 as_bad (_("number of registers must be in the range [1:4]"));
4089 ignore_rest_of_line ();
4093 demand_empty_rest_of_line ();
4098 op
= 0xb4 | (num_regs
- 1);
4099 add_unwind_opcode (op
, 1);
4104 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4105 add_unwind_opcode (op
, 2);
4107 unwind
.frame_size
+= num_regs
* 12;
4111 /* Parse a directive saving VFP registers for ARMv6 and above. */
4114 s_arm_unwind_save_vfp_armv6 (void)
4119 int num_vfpv3_regs
= 0;
4120 int num_regs_below_16
;
4122 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
);
4125 as_bad (_("expected register list"));
4126 ignore_rest_of_line ();
4130 demand_empty_rest_of_line ();
4132 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4133 than FSTMX/FLDMX-style ones). */
4135 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4137 num_vfpv3_regs
= count
;
4138 else if (start
+ count
> 16)
4139 num_vfpv3_regs
= start
+ count
- 16;
4141 if (num_vfpv3_regs
> 0)
4143 int start_offset
= start
> 16 ? start
- 16 : 0;
4144 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4145 add_unwind_opcode (op
, 2);
4148 /* Generate opcode for registers numbered in the range 0 .. 15. */
4149 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4150 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4151 if (num_regs_below_16
> 0)
4153 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4154 add_unwind_opcode (op
, 2);
4157 unwind
.frame_size
+= count
* 8;
4161 /* Parse a directive saving VFP registers for pre-ARMv6. */
4164 s_arm_unwind_save_vfp (void)
4170 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
);
4173 as_bad (_("expected register list"));
4174 ignore_rest_of_line ();
4178 demand_empty_rest_of_line ();
4183 op
= 0xb8 | (count
- 1);
4184 add_unwind_opcode (op
, 1);
4189 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4190 add_unwind_opcode (op
, 2);
4192 unwind
.frame_size
+= count
* 8 + 4;
4196 /* Parse a directive saving iWMMXt data registers. */
4199 s_arm_unwind_save_mmxwr (void)
4207 if (*input_line_pointer
== '{')
4208 input_line_pointer
++;
4212 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4216 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4221 as_tsktsk (_("register list not in ascending order"));
4224 if (*input_line_pointer
== '-')
4226 input_line_pointer
++;
4227 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4230 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4233 else if (reg
>= hi_reg
)
4235 as_bad (_("bad register range"));
4238 for (; reg
< hi_reg
; reg
++)
4242 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4244 skip_past_char (&input_line_pointer
, '}');
4246 demand_empty_rest_of_line ();
4248 /* Generate any deferred opcodes because we're going to be looking at
4250 flush_pending_unwind ();
4252 for (i
= 0; i
< 16; i
++)
4254 if (mask
& (1 << i
))
4255 unwind
.frame_size
+= 8;
4258 /* Attempt to combine with a previous opcode. We do this because gcc
4259 likes to output separate unwind directives for a single block of
4261 if (unwind
.opcode_count
> 0)
4263 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4264 if ((i
& 0xf8) == 0xc0)
4267 /* Only merge if the blocks are contiguous. */
4270 if ((mask
& 0xfe00) == (1 << 9))
4272 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4273 unwind
.opcode_count
--;
4276 else if (i
== 6 && unwind
.opcode_count
>= 2)
4278 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4282 op
= 0xffff << (reg
- 1);
4284 && ((mask
& op
) == (1u << (reg
- 1))))
4286 op
= (1 << (reg
+ i
+ 1)) - 1;
4287 op
&= ~((1 << reg
) - 1);
4289 unwind
.opcode_count
-= 2;
4296 /* We want to generate opcodes in the order the registers have been
4297 saved, ie. descending order. */
4298 for (reg
= 15; reg
>= -1; reg
--)
4300 /* Save registers in blocks. */
4302 || !(mask
& (1 << reg
)))
4304 /* We found an unsaved reg. Generate opcodes to save the
4311 op
= 0xc0 | (hi_reg
- 10);
4312 add_unwind_opcode (op
, 1);
4317 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4318 add_unwind_opcode (op
, 2);
4327 ignore_rest_of_line ();
4331 s_arm_unwind_save_mmxwcg (void)
4338 if (*input_line_pointer
== '{')
4339 input_line_pointer
++;
4341 skip_whitespace (input_line_pointer
);
4345 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4349 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4355 as_tsktsk (_("register list not in ascending order"));
4358 if (*input_line_pointer
== '-')
4360 input_line_pointer
++;
4361 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4364 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4367 else if (reg
>= hi_reg
)
4369 as_bad (_("bad register range"));
4372 for (; reg
< hi_reg
; reg
++)
4376 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4378 skip_past_char (&input_line_pointer
, '}');
4380 demand_empty_rest_of_line ();
4382 /* Generate any deferred opcodes because we're going to be looking at
4384 flush_pending_unwind ();
4386 for (reg
= 0; reg
< 16; reg
++)
4388 if (mask
& (1 << reg
))
4389 unwind
.frame_size
+= 4;
4392 add_unwind_opcode (op
, 2);
4395 ignore_rest_of_line ();
4399 /* Parse an unwind_save directive.
4400 If the argument is non-zero, this is a .vsave directive. */
4403 s_arm_unwind_save (int arch_v6
)
4406 struct reg_entry
*reg
;
4407 bfd_boolean had_brace
= FALSE
;
4409 if (!unwind
.proc_start
)
4410 as_bad (MISSING_FNSTART
);
4412 /* Figure out what sort of save we have. */
4413 peek
= input_line_pointer
;
4421 reg
= arm_reg_parse_multi (&peek
);
4425 as_bad (_("register expected"));
4426 ignore_rest_of_line ();
4435 as_bad (_("FPA .unwind_save does not take a register list"));
4436 ignore_rest_of_line ();
4439 input_line_pointer
= peek
;
4440 s_arm_unwind_save_fpa (reg
->number
);
4444 s_arm_unwind_save_core ();
4449 s_arm_unwind_save_vfp_armv6 ();
4451 s_arm_unwind_save_vfp ();
4454 case REG_TYPE_MMXWR
:
4455 s_arm_unwind_save_mmxwr ();
4458 case REG_TYPE_MMXWCG
:
4459 s_arm_unwind_save_mmxwcg ();
4463 as_bad (_(".unwind_save does not support this kind of register"));
4464 ignore_rest_of_line ();
4469 /* Parse an unwind_movsp directive. */
4472 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4478 if (!unwind
.proc_start
)
4479 as_bad (MISSING_FNSTART
);
4481 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4484 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4485 ignore_rest_of_line ();
4489 /* Optional constant. */
4490 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4492 if (immediate_for_directive (&offset
) == FAIL
)
4498 demand_empty_rest_of_line ();
4500 if (reg
== REG_SP
|| reg
== REG_PC
)
4502 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4506 if (unwind
.fp_reg
!= REG_SP
)
4507 as_bad (_("unexpected .unwind_movsp directive"));
4509 /* Generate opcode to restore the value. */
4511 add_unwind_opcode (op
, 1);
4513 /* Record the information for later. */
4514 unwind
.fp_reg
= reg
;
4515 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4516 unwind
.sp_restored
= 1;
4519 /* Parse an unwind_pad directive. */
4522 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4526 if (!unwind
.proc_start
)
4527 as_bad (MISSING_FNSTART
);
4529 if (immediate_for_directive (&offset
) == FAIL
)
4534 as_bad (_("stack increment must be multiple of 4"));
4535 ignore_rest_of_line ();
4539 /* Don't generate any opcodes, just record the details for later. */
4540 unwind
.frame_size
+= offset
;
4541 unwind
.pending_offset
+= offset
;
4543 demand_empty_rest_of_line ();
4546 /* Parse an unwind_setfp directive. */
4549 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4555 if (!unwind
.proc_start
)
4556 as_bad (MISSING_FNSTART
);
4558 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4559 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4562 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4564 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4566 as_bad (_("expected <reg>, <reg>"));
4567 ignore_rest_of_line ();
4571 /* Optional constant. */
4572 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4574 if (immediate_for_directive (&offset
) == FAIL
)
4580 demand_empty_rest_of_line ();
4582 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4584 as_bad (_("register must be either sp or set by a previous"
4585 "unwind_movsp directive"));
4589 /* Don't generate any opcodes, just record the information for later. */
4590 unwind
.fp_reg
= fp_reg
;
4592 if (sp_reg
== REG_SP
)
4593 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4595 unwind
.fp_offset
-= offset
;
4598 /* Parse an unwind_raw directive. */
4601 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4604 /* This is an arbitrary limit. */
4605 unsigned char op
[16];
4608 if (!unwind
.proc_start
)
4609 as_bad (MISSING_FNSTART
);
4612 if (exp
.X_op
== O_constant
4613 && skip_past_comma (&input_line_pointer
) != FAIL
)
4615 unwind
.frame_size
+= exp
.X_add_number
;
4619 exp
.X_op
= O_illegal
;
4621 if (exp
.X_op
!= O_constant
)
4623 as_bad (_("expected <offset>, <opcode>"));
4624 ignore_rest_of_line ();
4630 /* Parse the opcode. */
4635 as_bad (_("unwind opcode too long"));
4636 ignore_rest_of_line ();
4638 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4640 as_bad (_("invalid unwind opcode"));
4641 ignore_rest_of_line ();
4644 op
[count
++] = exp
.X_add_number
;
4646 /* Parse the next byte. */
4647 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4653 /* Add the opcode bytes in reverse order. */
4655 add_unwind_opcode (op
[count
], 1);
4657 demand_empty_rest_of_line ();
4661 /* Parse a .eabi_attribute directive. */
4664 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4666 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4668 if (tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4669 attributes_set_explicitly
[tag
] = 1;
4672 /* Emit a tls fix for the symbol. */
4675 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4679 #ifdef md_flush_pending_output
4680 md_flush_pending_output ();
4683 #ifdef md_cons_align
4687 /* Since we're just labelling the code, there's no need to define a
4690 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4691 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4692 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4693 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4695 #endif /* OBJ_ELF */
4697 static void s_arm_arch (int);
4698 static void s_arm_object_arch (int);
4699 static void s_arm_cpu (int);
4700 static void s_arm_fpu (int);
4701 static void s_arm_arch_extension (int);
4706 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4713 if (exp
.X_op
== O_symbol
)
4714 exp
.X_op
= O_secrel
;
4716 emit_expr (&exp
, 4);
4718 while (*input_line_pointer
++ == ',');
4720 input_line_pointer
--;
4721 demand_empty_rest_of_line ();
4725 /* This table describes all the machine specific pseudo-ops the assembler
4726 has to support. The fields are:
4727 pseudo-op name without dot
4728 function to call to execute this pseudo-op
4729 Integer arg to pass to the function. */
4731 const pseudo_typeS md_pseudo_table
[] =
4733 /* Never called because '.req' does not start a line. */
4734 { "req", s_req
, 0 },
4735 /* Following two are likewise never called. */
4738 { "unreq", s_unreq
, 0 },
4739 { "bss", s_bss
, 0 },
4740 { "align", s_align_ptwo
, 2 },
4741 { "arm", s_arm
, 0 },
4742 { "thumb", s_thumb
, 0 },
4743 { "code", s_code
, 0 },
4744 { "force_thumb", s_force_thumb
, 0 },
4745 { "thumb_func", s_thumb_func
, 0 },
4746 { "thumb_set", s_thumb_set
, 0 },
4747 { "even", s_even
, 0 },
4748 { "ltorg", s_ltorg
, 0 },
4749 { "pool", s_ltorg
, 0 },
4750 { "syntax", s_syntax
, 0 },
4751 { "cpu", s_arm_cpu
, 0 },
4752 { "arch", s_arm_arch
, 0 },
4753 { "object_arch", s_arm_object_arch
, 0 },
4754 { "fpu", s_arm_fpu
, 0 },
4755 { "arch_extension", s_arm_arch_extension
, 0 },
4757 { "word", s_arm_elf_cons
, 4 },
4758 { "long", s_arm_elf_cons
, 4 },
4759 { "inst.n", s_arm_elf_inst
, 2 },
4760 { "inst.w", s_arm_elf_inst
, 4 },
4761 { "inst", s_arm_elf_inst
, 0 },
4762 { "rel31", s_arm_rel31
, 0 },
4763 { "fnstart", s_arm_unwind_fnstart
, 0 },
4764 { "fnend", s_arm_unwind_fnend
, 0 },
4765 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
4766 { "personality", s_arm_unwind_personality
, 0 },
4767 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
4768 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
4769 { "save", s_arm_unwind_save
, 0 },
4770 { "vsave", s_arm_unwind_save
, 1 },
4771 { "movsp", s_arm_unwind_movsp
, 0 },
4772 { "pad", s_arm_unwind_pad
, 0 },
4773 { "setfp", s_arm_unwind_setfp
, 0 },
4774 { "unwind_raw", s_arm_unwind_raw
, 0 },
4775 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
4776 { "tlsdescseq", s_arm_tls_descseq
, 0 },
4780 /* These are used for dwarf. */
4784 /* These are used for dwarf2. */
4785 { "file", dwarf2_directive_file
, 0 },
4786 { "loc", dwarf2_directive_loc
, 0 },
4787 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
4789 { "extend", float_cons
, 'x' },
4790 { "ldouble", float_cons
, 'x' },
4791 { "packed", float_cons
, 'p' },
4793 {"secrel32", pe_directive_secrel
, 0},
4796 /* These are for compatibility with CodeComposer Studio. */
4797 {"ref", s_ccs_ref
, 0},
4798 {"def", s_ccs_def
, 0},
4799 {"asmfunc", s_ccs_asmfunc
, 0},
4800 {"endasmfunc", s_ccs_endasmfunc
, 0},
4805 /* Parser functions used exclusively in instruction operands. */
4807 /* Generic immediate-value read function for use in insn parsing.
4808 STR points to the beginning of the immediate (the leading #);
4809 VAL receives the value; if the value is outside [MIN, MAX]
4810 issue an error. PREFIX_OPT is true if the immediate prefix is
4814 parse_immediate (char **str
, int *val
, int min
, int max
,
4815 bfd_boolean prefix_opt
)
4819 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
4820 if (exp
.X_op
!= O_constant
)
4822 inst
.error
= _("constant expression required");
4826 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
4828 inst
.error
= _("immediate value out of range");
4832 *val
= exp
.X_add_number
;
4836 /* Less-generic immediate-value read function with the possibility of loading a
4837 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
4838 instructions. Puts the result directly in inst.operands[i]. */
4841 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
4842 bfd_boolean allow_symbol_p
)
4845 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
4848 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
4850 if (exp_p
->X_op
== O_constant
)
4852 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
4853 /* If we're on a 64-bit host, then a 64-bit number can be returned using
4854 O_constant. We have to be careful not to break compilation for
4855 32-bit X_add_number, though. */
4856 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
4858 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
4859 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
4861 inst
.operands
[i
].regisimm
= 1;
4864 else if (exp_p
->X_op
== O_big
4865 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
4867 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
4869 /* Bignums have their least significant bits in
4870 generic_bignum[0]. Make sure we put 32 bits in imm and
4871 32 bits in reg, in a (hopefully) portable way. */
4872 gas_assert (parts
!= 0);
4874 /* Make sure that the number is not too big.
4875 PR 11972: Bignums can now be sign-extended to the
4876 size of a .octa so check that the out of range bits
4877 are all zero or all one. */
4878 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
4880 LITTLENUM_TYPE m
= -1;
4882 if (generic_bignum
[parts
* 2] != 0
4883 && generic_bignum
[parts
* 2] != m
)
4886 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
4887 if (generic_bignum
[j
] != generic_bignum
[j
-1])
4891 inst
.operands
[i
].imm
= 0;
4892 for (j
= 0; j
< parts
; j
++, idx
++)
4893 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
4894 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4895 inst
.operands
[i
].reg
= 0;
4896 for (j
= 0; j
< parts
; j
++, idx
++)
4897 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
4898 << (LITTLENUM_NUMBER_OF_BITS
* j
);
4899 inst
.operands
[i
].regisimm
= 1;
4901 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
4909 /* Returns the pseudo-register number of an FPA immediate constant,
4910 or FAIL if there isn't a valid constant here. */
4913 parse_fpa_immediate (char ** str
)
4915 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
4921 /* First try and match exact strings, this is to guarantee
4922 that some formats will work even for cross assembly. */
4924 for (i
= 0; fp_const
[i
]; i
++)
4926 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
4930 *str
+= strlen (fp_const
[i
]);
4931 if (is_end_of_line
[(unsigned char) **str
])
4937 /* Just because we didn't get a match doesn't mean that the constant
4938 isn't valid, just that it is in a format that we don't
4939 automatically recognize. Try parsing it with the standard
4940 expression routines. */
4942 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
4944 /* Look for a raw floating point number. */
4945 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
4946 && is_end_of_line
[(unsigned char) *save_in
])
4948 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4950 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4952 if (words
[j
] != fp_values
[i
][j
])
4956 if (j
== MAX_LITTLENUMS
)
4964 /* Try and parse a more complex expression, this will probably fail
4965 unless the code uses a floating point prefix (eg "0f"). */
4966 save_in
= input_line_pointer
;
4967 input_line_pointer
= *str
;
4968 if (expression (&exp
) == absolute_section
4969 && exp
.X_op
== O_big
4970 && exp
.X_add_number
< 0)
4972 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
4974 #define X_PRECISION 5
4975 #define E_PRECISION 15L
4976 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
4978 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
4980 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
4982 if (words
[j
] != fp_values
[i
][j
])
4986 if (j
== MAX_LITTLENUMS
)
4988 *str
= input_line_pointer
;
4989 input_line_pointer
= save_in
;
4996 *str
= input_line_pointer
;
4997 input_line_pointer
= save_in
;
4998 inst
.error
= _("invalid FPA immediate expression");
5002 /* Returns 1 if a number has "quarter-precision" float format
5003 0baBbbbbbc defgh000 00000000 00000000. */
5006 is_quarter_float (unsigned imm
)
5008 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5009 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5013 /* Detect the presence of a floating point or integer zero constant,
5017 parse_ifimm_zero (char **in
)
5021 if (!is_immediate_prefix (**in
))
5023 /* In unified syntax, all prefixes are optional. */
5024 if (!unified_syntax
)
5030 /* Accept #0x0 as a synonym for #0. */
5031 if (strncmp (*in
, "0x", 2) == 0)
5034 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5039 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5040 &generic_floating_point_number
);
5043 && generic_floating_point_number
.sign
== '+'
5044 && (generic_floating_point_number
.low
5045 > generic_floating_point_number
.leader
))
5051 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5052 0baBbbbbbc defgh000 00000000 00000000.
5053 The zero and minus-zero cases need special handling, since they can't be
5054 encoded in the "quarter-precision" float format, but can nonetheless be
5055 loaded as integer constants. */
5058 parse_qfloat_immediate (char **ccp
, int *immed
)
5062 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5063 int found_fpchar
= 0;
5065 skip_past_char (&str
, '#');
5067 /* We must not accidentally parse an integer as a floating-point number. Make
5068 sure that the value we parse is not an integer by checking for special
5069 characters '.' or 'e'.
5070 FIXME: This is a horrible hack, but doing better is tricky because type
5071 information isn't in a very usable state at parse time. */
5073 skip_whitespace (fpnum
);
5075 if (strncmp (fpnum
, "0x", 2) == 0)
5079 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5080 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5090 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5092 unsigned fpword
= 0;
5095 /* Our FP word must be 32 bits (single-precision FP). */
5096 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5098 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5102 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5115 /* Shift operands. */
5118 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
5121 struct asm_shift_name
5124 enum shift_kind kind
;
5127 /* Third argument to parse_shift. */
5128 enum parse_shift_mode
5130 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5131 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5132 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5133 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5134 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5137 /* Parse a <shift> specifier on an ARM data processing instruction.
5138 This has three forms:
5140 (LSL|LSR|ASL|ASR|ROR) Rs
5141 (LSL|LSR|ASL|ASR|ROR) #imm
5144 Note that ASL is assimilated to LSL in the instruction encoding, and
5145 RRX to ROR #0 (which cannot be written as such). */
5148 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5150 const struct asm_shift_name
*shift_name
;
5151 enum shift_kind shift
;
5156 for (p
= *str
; ISALPHA (*p
); p
++)
5161 inst
.error
= _("shift expression expected");
5165 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5168 if (shift_name
== NULL
)
5170 inst
.error
= _("shift expression expected");
5174 shift
= shift_name
->kind
;
5178 case NO_SHIFT_RESTRICT
:
5179 case SHIFT_IMMEDIATE
: break;
5181 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5182 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5184 inst
.error
= _("'LSL' or 'ASR' required");
5189 case SHIFT_LSL_IMMEDIATE
:
5190 if (shift
!= SHIFT_LSL
)
5192 inst
.error
= _("'LSL' required");
5197 case SHIFT_ASR_IMMEDIATE
:
5198 if (shift
!= SHIFT_ASR
)
5200 inst
.error
= _("'ASR' required");
5208 if (shift
!= SHIFT_RRX
)
5210 /* Whitespace can appear here if the next thing is a bare digit. */
5211 skip_whitespace (p
);
5213 if (mode
== NO_SHIFT_RESTRICT
5214 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5216 inst
.operands
[i
].imm
= reg
;
5217 inst
.operands
[i
].immisreg
= 1;
5219 else if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5222 inst
.operands
[i
].shift_kind
= shift
;
5223 inst
.operands
[i
].shifted
= 1;
5228 /* Parse a <shifter_operand> for an ARM data processing instruction:
5231 #<immediate>, <rotate>
5235 where <shift> is defined by parse_shift above, and <rotate> is a
5236 multiple of 2 between 0 and 30. Validation of immediate operands
5237 is deferred to md_apply_fix. */
5240 parse_shifter_operand (char **str
, int i
)
5245 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5247 inst
.operands
[i
].reg
= value
;
5248 inst
.operands
[i
].isreg
= 1;
5250 /* parse_shift will override this if appropriate */
5251 inst
.reloc
.exp
.X_op
= O_constant
;
5252 inst
.reloc
.exp
.X_add_number
= 0;
5254 if (skip_past_comma (str
) == FAIL
)
5257 /* Shift operation on register. */
5258 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5261 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_IMM_PREFIX
))
5264 if (skip_past_comma (str
) == SUCCESS
)
5266 /* #x, y -- ie explicit rotation by Y. */
5267 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5270 if (exp
.X_op
!= O_constant
|| inst
.reloc
.exp
.X_op
!= O_constant
)
5272 inst
.error
= _("constant expression expected");
5276 value
= exp
.X_add_number
;
5277 if (value
< 0 || value
> 30 || value
% 2 != 0)
5279 inst
.error
= _("invalid rotation");
5282 if (inst
.reloc
.exp
.X_add_number
< 0 || inst
.reloc
.exp
.X_add_number
> 255)
5284 inst
.error
= _("invalid constant");
5288 /* Encode as specified. */
5289 inst
.operands
[i
].imm
= inst
.reloc
.exp
.X_add_number
| value
<< 7;
5293 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
5294 inst
.reloc
.pc_rel
= 0;
5298 /* Group relocation information. Each entry in the table contains the
5299 textual name of the relocation as may appear in assembler source
5300 and must end with a colon.
5301 Along with this textual name are the relocation codes to be used if
5302 the corresponding instruction is an ALU instruction (ADD or SUB only),
5303 an LDR, an LDRS, or an LDC. */
5305 struct group_reloc_table_entry
5316 /* Varieties of non-ALU group relocation. */
5323 static struct group_reloc_table_entry group_reloc_table
[] =
5324 { /* Program counter relative: */
5326 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5331 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5332 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5333 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5334 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5336 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5341 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5342 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5343 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5344 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5346 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5347 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5348 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5349 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5350 /* Section base relative */
5352 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5357 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5358 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5359 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5360 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5362 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5367 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5368 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5369 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5370 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5372 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5373 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5374 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5375 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5376 /* Absolute thumb alu relocations. */
5378 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5383 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5388 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5393 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5398 /* Given the address of a pointer pointing to the textual name of a group
5399 relocation as may appear in assembler source, attempt to find its details
5400 in group_reloc_table. The pointer will be updated to the character after
5401 the trailing colon. On failure, FAIL will be returned; SUCCESS
5402 otherwise. On success, *entry will be updated to point at the relevant
5403 group_reloc_table entry. */
5406 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5409 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5411 int length
= strlen (group_reloc_table
[i
].name
);
5413 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5414 && (*str
)[length
] == ':')
5416 *out
= &group_reloc_table
[i
];
5417 *str
+= (length
+ 1);
5425 /* Parse a <shifter_operand> for an ARM data processing instruction
5426 (as for parse_shifter_operand) where group relocations are allowed:
5429 #<immediate>, <rotate>
5430 #:<group_reloc>:<expression>
5434 where <group_reloc> is one of the strings defined in group_reloc_table.
5435 The hashes are optional.
5437 Everything else is as for parse_shifter_operand. */
5439 static parse_operand_result
5440 parse_shifter_operand_group_reloc (char **str
, int i
)
5442 /* Determine if we have the sequence of characters #: or just :
5443 coming next. If we do, then we check for a group relocation.
5444 If we don't, punt the whole lot to parse_shifter_operand. */
5446 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5447 || (*str
)[0] == ':')
5449 struct group_reloc_table_entry
*entry
;
5451 if ((*str
)[0] == '#')
5456 /* Try to parse a group relocation. Anything else is an error. */
5457 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5459 inst
.error
= _("unknown group relocation");
5460 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5463 /* We now have the group relocation table entry corresponding to
5464 the name in the assembler source. Next, we parse the expression. */
5465 if (my_get_expression (&inst
.reloc
.exp
, str
, GE_NO_PREFIX
))
5466 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5468 /* Record the relocation type (always the ALU variant here). */
5469 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5470 gas_assert (inst
.reloc
.type
!= 0);
5472 return PARSE_OPERAND_SUCCESS
;
5475 return parse_shifter_operand (str
, i
) == SUCCESS
5476 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5478 /* Never reached. */
5481 /* Parse a Neon alignment expression. Information is written to
5482 inst.operands[i]. We assume the initial ':' has been skipped.
5484 align .imm = align << 8, .immisalign=1, .preind=0 */
5485 static parse_operand_result
5486 parse_neon_alignment (char **str
, int i
)
5491 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5493 if (exp
.X_op
!= O_constant
)
5495 inst
.error
= _("alignment must be constant");
5496 return PARSE_OPERAND_FAIL
;
5499 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5500 inst
.operands
[i
].immisalign
= 1;
5501 /* Alignments are not pre-indexes. */
5502 inst
.operands
[i
].preind
= 0;
5505 return PARSE_OPERAND_SUCCESS
;
5508 /* Parse all forms of an ARM address expression. Information is written
5509 to inst.operands[i] and/or inst.reloc.
5511 Preindexed addressing (.preind=1):
5513 [Rn, #offset] .reg=Rn .reloc.exp=offset
5514 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5515 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5516 .shift_kind=shift .reloc.exp=shift_imm
5518 These three may have a trailing ! which causes .writeback to be set also.
5520 Postindexed addressing (.postind=1, .writeback=1):
5522 [Rn], #offset .reg=Rn .reloc.exp=offset
5523 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5524 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5525 .shift_kind=shift .reloc.exp=shift_imm
5527 Unindexed addressing (.preind=0, .postind=0):
5529 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5533 [Rn]{!} shorthand for [Rn,#0]{!}
5534 =immediate .isreg=0 .reloc.exp=immediate
5535 label .reg=PC .reloc.pc_rel=1 .reloc.exp=label
5537 It is the caller's responsibility to check for addressing modes not
5538 supported by the instruction, and to set inst.reloc.type. */
5540 static parse_operand_result
5541 parse_address_main (char **str
, int i
, int group_relocations
,
5542 group_reloc_type group_type
)
5547 if (skip_past_char (&p
, '[') == FAIL
)
5549 if (skip_past_char (&p
, '=') == FAIL
)
5551 /* Bare address - translate to PC-relative offset. */
5552 inst
.reloc
.pc_rel
= 1;
5553 inst
.operands
[i
].reg
= REG_PC
;
5554 inst
.operands
[i
].isreg
= 1;
5555 inst
.operands
[i
].preind
= 1;
5557 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_OPT_PREFIX_BIG
))
5558 return PARSE_OPERAND_FAIL
;
5560 else if (parse_big_immediate (&p
, i
, &inst
.reloc
.exp
,
5561 /*allow_symbol_p=*/TRUE
))
5562 return PARSE_OPERAND_FAIL
;
5565 return PARSE_OPERAND_SUCCESS
;
5568 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5569 skip_whitespace (p
);
5571 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5573 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5574 return PARSE_OPERAND_FAIL
;
5576 inst
.operands
[i
].reg
= reg
;
5577 inst
.operands
[i
].isreg
= 1;
5579 if (skip_past_comma (&p
) == SUCCESS
)
5581 inst
.operands
[i
].preind
= 1;
5584 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5586 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5588 inst
.operands
[i
].imm
= reg
;
5589 inst
.operands
[i
].immisreg
= 1;
5591 if (skip_past_comma (&p
) == SUCCESS
)
5592 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5593 return PARSE_OPERAND_FAIL
;
5595 else if (skip_past_char (&p
, ':') == SUCCESS
)
5597 /* FIXME: '@' should be used here, but it's filtered out by generic
5598 code before we get to see it here. This may be subject to
5600 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5602 if (result
!= PARSE_OPERAND_SUCCESS
)
5607 if (inst
.operands
[i
].negative
)
5609 inst
.operands
[i
].negative
= 0;
5613 if (group_relocations
5614 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5616 struct group_reloc_table_entry
*entry
;
5618 /* Skip over the #: or : sequence. */
5624 /* Try to parse a group relocation. Anything else is an
5626 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5628 inst
.error
= _("unknown group relocation");
5629 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5632 /* We now have the group relocation table entry corresponding to
5633 the name in the assembler source. Next, we parse the
5635 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5636 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5638 /* Record the relocation type. */
5642 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldr_code
;
5646 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5650 inst
.reloc
.type
= (bfd_reloc_code_real_type
) entry
->ldc_code
;
5657 if (inst
.reloc
.type
== 0)
5659 inst
.error
= _("this group relocation is not allowed on this instruction");
5660 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5667 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5668 return PARSE_OPERAND_FAIL
;
5669 /* If the offset is 0, find out if it's a +0 or -0. */
5670 if (inst
.reloc
.exp
.X_op
== O_constant
5671 && inst
.reloc
.exp
.X_add_number
== 0)
5673 skip_whitespace (q
);
5677 skip_whitespace (q
);
5680 inst
.operands
[i
].negative
= 1;
5685 else if (skip_past_char (&p
, ':') == SUCCESS
)
5687 /* FIXME: '@' should be used here, but it's filtered out by generic code
5688 before we get to see it here. This may be subject to change. */
5689 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5691 if (result
!= PARSE_OPERAND_SUCCESS
)
5695 if (skip_past_char (&p
, ']') == FAIL
)
5697 inst
.error
= _("']' expected");
5698 return PARSE_OPERAND_FAIL
;
5701 if (skip_past_char (&p
, '!') == SUCCESS
)
5702 inst
.operands
[i
].writeback
= 1;
5704 else if (skip_past_comma (&p
) == SUCCESS
)
5706 if (skip_past_char (&p
, '{') == SUCCESS
)
5708 /* [Rn], {expr} - unindexed, with option */
5709 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
5710 0, 255, TRUE
) == FAIL
)
5711 return PARSE_OPERAND_FAIL
;
5713 if (skip_past_char (&p
, '}') == FAIL
)
5715 inst
.error
= _("'}' expected at end of 'option' field");
5716 return PARSE_OPERAND_FAIL
;
5718 if (inst
.operands
[i
].preind
)
5720 inst
.error
= _("cannot combine index with option");
5721 return PARSE_OPERAND_FAIL
;
5724 return PARSE_OPERAND_SUCCESS
;
5728 inst
.operands
[i
].postind
= 1;
5729 inst
.operands
[i
].writeback
= 1;
5731 if (inst
.operands
[i
].preind
)
5733 inst
.error
= _("cannot combine pre- and post-indexing");
5734 return PARSE_OPERAND_FAIL
;
5738 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5740 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5742 /* We might be using the immediate for alignment already. If we
5743 are, OR the register number into the low-order bits. */
5744 if (inst
.operands
[i
].immisalign
)
5745 inst
.operands
[i
].imm
|= reg
;
5747 inst
.operands
[i
].imm
= reg
;
5748 inst
.operands
[i
].immisreg
= 1;
5750 if (skip_past_comma (&p
) == SUCCESS
)
5751 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5752 return PARSE_OPERAND_FAIL
;
5758 if (inst
.operands
[i
].negative
)
5760 inst
.operands
[i
].negative
= 0;
5763 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_IMM_PREFIX
))
5764 return PARSE_OPERAND_FAIL
;
5765 /* If the offset is 0, find out if it's a +0 or -0. */
5766 if (inst
.reloc
.exp
.X_op
== O_constant
5767 && inst
.reloc
.exp
.X_add_number
== 0)
5769 skip_whitespace (q
);
5773 skip_whitespace (q
);
5776 inst
.operands
[i
].negative
= 1;
5782 /* If at this point neither .preind nor .postind is set, we have a
5783 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
5784 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
5786 inst
.operands
[i
].preind
= 1;
5787 inst
.reloc
.exp
.X_op
= O_constant
;
5788 inst
.reloc
.exp
.X_add_number
= 0;
5791 return PARSE_OPERAND_SUCCESS
;
5795 parse_address (char **str
, int i
)
5797 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
5801 static parse_operand_result
5802 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
5804 return parse_address_main (str
, i
, 1, type
);
5807 /* Parse an operand for a MOVW or MOVT instruction. */
5809 parse_half (char **str
)
5814 skip_past_char (&p
, '#');
5815 if (strncasecmp (p
, ":lower16:", 9) == 0)
5816 inst
.reloc
.type
= BFD_RELOC_ARM_MOVW
;
5817 else if (strncasecmp (p
, ":upper16:", 9) == 0)
5818 inst
.reloc
.type
= BFD_RELOC_ARM_MOVT
;
5820 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
5823 skip_whitespace (p
);
5826 if (my_get_expression (&inst
.reloc
.exp
, &p
, GE_NO_PREFIX
))
5829 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
5831 if (inst
.reloc
.exp
.X_op
!= O_constant
)
5833 inst
.error
= _("constant expression expected");
5836 if (inst
.reloc
.exp
.X_add_number
< 0
5837 || inst
.reloc
.exp
.X_add_number
> 0xffff)
5839 inst
.error
= _("immediate value out of range");
5847 /* Miscellaneous. */
5849 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
5850 or a bitmask suitable to be or-ed into the ARM msr instruction. */
5852 parse_psr (char **str
, bfd_boolean lhs
)
5855 unsigned long psr_field
;
5856 const struct asm_psr
*psr
;
5858 bfd_boolean is_apsr
= FALSE
;
5859 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
5861 /* PR gas/12698: If the user has specified -march=all then m_profile will
5862 be TRUE, but we want to ignore it in this case as we are building for any
5863 CPU type, including non-m variants. */
5864 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
5867 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
5868 feature for ease of use and backwards compatibility. */
5870 if (strncasecmp (p
, "SPSR", 4) == 0)
5873 goto unsupported_psr
;
5875 psr_field
= SPSR_BIT
;
5877 else if (strncasecmp (p
, "CPSR", 4) == 0)
5880 goto unsupported_psr
;
5884 else if (strncasecmp (p
, "APSR", 4) == 0)
5886 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
5887 and ARMv7-R architecture CPUs. */
5896 while (ISALNUM (*p
) || *p
== '_');
5898 if (strncasecmp (start
, "iapsr", 5) == 0
5899 || strncasecmp (start
, "eapsr", 5) == 0
5900 || strncasecmp (start
, "xpsr", 4) == 0
5901 || strncasecmp (start
, "psr", 3) == 0)
5902 p
= start
+ strcspn (start
, "rR") + 1;
5904 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
5910 /* If APSR is being written, a bitfield may be specified. Note that
5911 APSR itself is handled above. */
5912 if (psr
->field
<= 3)
5914 psr_field
= psr
->field
;
5920 /* M-profile MSR instructions have the mask field set to "10", except
5921 *PSR variants which modify APSR, which may use a different mask (and
5922 have been handled already). Do that by setting the PSR_f field
5924 return psr
->field
| (lhs
? PSR_f
: 0);
5927 goto unsupported_psr
;
5933 /* A suffix follows. */
5939 while (ISALNUM (*p
) || *p
== '_');
5943 /* APSR uses a notation for bits, rather than fields. */
5944 unsigned int nzcvq_bits
= 0;
5945 unsigned int g_bit
= 0;
5948 for (bit
= start
; bit
!= p
; bit
++)
5950 switch (TOLOWER (*bit
))
5953 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
5957 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
5961 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
5965 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
5969 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
5973 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
5977 inst
.error
= _("unexpected bit specified after APSR");
5982 if (nzcvq_bits
== 0x1f)
5987 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
5989 inst
.error
= _("selected processor does not "
5990 "support DSP extension");
5997 if ((nzcvq_bits
& 0x20) != 0
5998 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
5999 || (g_bit
& 0x2) != 0)
6001 inst
.error
= _("bad bitmask specified after APSR");
6007 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6012 psr_field
|= psr
->field
;
6018 goto error
; /* Garbage after "[CS]PSR". */
6020 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6021 is deprecated, but allow it anyway. */
6025 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6028 else if (!m_profile
)
6029 /* These bits are never right for M-profile devices: don't set them
6030 (only code paths which read/write APSR reach here). */
6031 psr_field
|= (PSR_c
| PSR_f
);
6037 inst
.error
= _("selected processor does not support requested special "
6038 "purpose register");
6042 inst
.error
= _("flag for {c}psr instruction expected");
6046 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6047 value suitable for splatting into the AIF field of the instruction. */
6050 parse_cps_flags (char **str
)
6059 case '\0': case ',':
6062 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6063 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6064 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6067 inst
.error
= _("unrecognized CPS flag");
6072 if (saw_a_flag
== 0)
6074 inst
.error
= _("missing CPS flags");
6082 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6083 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6086 parse_endian_specifier (char **str
)
6091 if (strncasecmp (s
, "BE", 2))
6093 else if (strncasecmp (s
, "LE", 2))
6097 inst
.error
= _("valid endian specifiers are be or le");
6101 if (ISALNUM (s
[2]) || s
[2] == '_')
6103 inst
.error
= _("valid endian specifiers are be or le");
6108 return little_endian
;
6111 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6112 value suitable for poking into the rotate field of an sxt or sxta
6113 instruction, or FAIL on error. */
6116 parse_ror (char **str
)
6121 if (strncasecmp (s
, "ROR", 3) == 0)
6125 inst
.error
= _("missing rotation field after comma");
6129 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6134 case 0: *str
= s
; return 0x0;
6135 case 8: *str
= s
; return 0x1;
6136 case 16: *str
= s
; return 0x2;
6137 case 24: *str
= s
; return 0x3;
6140 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6145 /* Parse a conditional code (from conds[] below). The value returned is in the
6146 range 0 .. 14, or FAIL. */
6148 parse_cond (char **str
)
6151 const struct asm_cond
*c
;
6153 /* Condition codes are always 2 characters, so matching up to
6154 3 characters is sufficient. */
6159 while (ISALPHA (*q
) && n
< 3)
6161 cond
[n
] = TOLOWER (*q
);
6166 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6169 inst
.error
= _("condition required");
6177 /* Record a use of the given feature. */
6179 record_feature_use (const arm_feature_set
*feature
)
6182 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
6184 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
6187 /* If the given feature is currently allowed, mark it as used and return TRUE.
6188 Return FALSE otherwise. */
6190 mark_feature_used (const arm_feature_set
*feature
)
6192 /* Ensure the option is currently allowed. */
6193 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
6196 /* Add the appropriate architecture feature for the barrier option used. */
6197 record_feature_use (feature
);
6202 /* Parse an option for a barrier instruction. Returns the encoding for the
6205 parse_barrier (char **str
)
6208 const struct asm_barrier_opt
*o
;
6211 while (ISALPHA (*q
))
6214 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6219 if (!mark_feature_used (&o
->arch
))
6226 /* Parse the operands of a table branch instruction. Similar to a memory
6229 parse_tb (char **str
)
6234 if (skip_past_char (&p
, '[') == FAIL
)
6236 inst
.error
= _("'[' expected");
6240 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6242 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6245 inst
.operands
[0].reg
= reg
;
6247 if (skip_past_comma (&p
) == FAIL
)
6249 inst
.error
= _("',' expected");
6253 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6255 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6258 inst
.operands
[0].imm
= reg
;
6260 if (skip_past_comma (&p
) == SUCCESS
)
6262 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6264 if (inst
.reloc
.exp
.X_add_number
!= 1)
6266 inst
.error
= _("invalid shift");
6269 inst
.operands
[0].shifted
= 1;
6272 if (skip_past_char (&p
, ']') == FAIL
)
6274 inst
.error
= _("']' expected");
6281 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6282 information on the types the operands can take and how they are encoded.
6283 Up to four operands may be read; this function handles setting the
6284 ".present" field for each read operand itself.
6285 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6286 else returns FAIL. */
6289 parse_neon_mov (char **str
, int *which_operand
)
6291 int i
= *which_operand
, val
;
6292 enum arm_reg_type rtype
;
6294 struct neon_type_el optype
;
6296 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6298 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6299 inst
.operands
[i
].reg
= val
;
6300 inst
.operands
[i
].isscalar
= 1;
6301 inst
.operands
[i
].vectype
= optype
;
6302 inst
.operands
[i
++].present
= 1;
6304 if (skip_past_comma (&ptr
) == FAIL
)
6307 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6310 inst
.operands
[i
].reg
= val
;
6311 inst
.operands
[i
].isreg
= 1;
6312 inst
.operands
[i
].present
= 1;
6314 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6317 /* Cases 0, 1, 2, 3, 5 (D only). */
6318 if (skip_past_comma (&ptr
) == FAIL
)
6321 inst
.operands
[i
].reg
= val
;
6322 inst
.operands
[i
].isreg
= 1;
6323 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6324 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6325 inst
.operands
[i
].isvec
= 1;
6326 inst
.operands
[i
].vectype
= optype
;
6327 inst
.operands
[i
++].present
= 1;
6329 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6331 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6332 Case 13: VMOV <Sd>, <Rm> */
6333 inst
.operands
[i
].reg
= val
;
6334 inst
.operands
[i
].isreg
= 1;
6335 inst
.operands
[i
].present
= 1;
6337 if (rtype
== REG_TYPE_NQ
)
6339 first_error (_("can't use Neon quad register here"));
6342 else if (rtype
!= REG_TYPE_VFS
)
6345 if (skip_past_comma (&ptr
) == FAIL
)
6347 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6349 inst
.operands
[i
].reg
= val
;
6350 inst
.operands
[i
].isreg
= 1;
6351 inst
.operands
[i
].present
= 1;
6354 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6357 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6358 Case 1: VMOV<c><q> <Dd>, <Dm>
6359 Case 8: VMOV.F32 <Sd>, <Sm>
6360 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6362 inst
.operands
[i
].reg
= val
;
6363 inst
.operands
[i
].isreg
= 1;
6364 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6365 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6366 inst
.operands
[i
].isvec
= 1;
6367 inst
.operands
[i
].vectype
= optype
;
6368 inst
.operands
[i
].present
= 1;
6370 if (skip_past_comma (&ptr
) == SUCCESS
)
6375 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6378 inst
.operands
[i
].reg
= val
;
6379 inst
.operands
[i
].isreg
= 1;
6380 inst
.operands
[i
++].present
= 1;
6382 if (skip_past_comma (&ptr
) == FAIL
)
6385 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6388 inst
.operands
[i
].reg
= val
;
6389 inst
.operands
[i
].isreg
= 1;
6390 inst
.operands
[i
].present
= 1;
6393 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6394 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6395 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6396 Case 10: VMOV.F32 <Sd>, #<imm>
6397 Case 11: VMOV.F64 <Dd>, #<imm> */
6398 inst
.operands
[i
].immisfloat
= 1;
6399 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6401 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6402 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6406 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6410 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6413 inst
.operands
[i
].reg
= val
;
6414 inst
.operands
[i
].isreg
= 1;
6415 inst
.operands
[i
++].present
= 1;
6417 if (skip_past_comma (&ptr
) == FAIL
)
6420 if ((val
= parse_scalar (&ptr
, 8, &optype
)) != FAIL
)
6422 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6423 inst
.operands
[i
].reg
= val
;
6424 inst
.operands
[i
].isscalar
= 1;
6425 inst
.operands
[i
].present
= 1;
6426 inst
.operands
[i
].vectype
= optype
;
6428 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6430 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6431 inst
.operands
[i
].reg
= val
;
6432 inst
.operands
[i
].isreg
= 1;
6433 inst
.operands
[i
++].present
= 1;
6435 if (skip_past_comma (&ptr
) == FAIL
)
6438 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6441 first_error (_(reg_expected_msgs
[REG_TYPE_VFSD
]));
6445 inst
.operands
[i
].reg
= val
;
6446 inst
.operands
[i
].isreg
= 1;
6447 inst
.operands
[i
].isvec
= 1;
6448 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6449 inst
.operands
[i
].vectype
= optype
;
6450 inst
.operands
[i
].present
= 1;
6452 if (rtype
== REG_TYPE_VFS
)
6456 if (skip_past_comma (&ptr
) == FAIL
)
6458 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6461 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6464 inst
.operands
[i
].reg
= val
;
6465 inst
.operands
[i
].isreg
= 1;
6466 inst
.operands
[i
].isvec
= 1;
6467 inst
.operands
[i
].issingle
= 1;
6468 inst
.operands
[i
].vectype
= optype
;
6469 inst
.operands
[i
].present
= 1;
6472 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6476 inst
.operands
[i
].reg
= val
;
6477 inst
.operands
[i
].isreg
= 1;
6478 inst
.operands
[i
].isvec
= 1;
6479 inst
.operands
[i
].issingle
= 1;
6480 inst
.operands
[i
].vectype
= optype
;
6481 inst
.operands
[i
].present
= 1;
6486 first_error (_("parse error"));
6490 /* Successfully parsed the operands. Update args. */
6496 first_error (_("expected comma"));
6500 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6504 /* Use this macro when the operand constraints are different
6505 for ARM and THUMB (e.g. ldrd). */
6506 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6507 ((arm_operand) | ((thumb_operand) << 16))
6509 /* Matcher codes for parse_operands. */
6510 enum operand_parse_code
6512 OP_stop
, /* end of line */
6514 OP_RR
, /* ARM register */
6515 OP_RRnpc
, /* ARM register, not r15 */
6516 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6517 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6518 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6519 optional trailing ! */
6520 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6521 OP_RCP
, /* Coprocessor number */
6522 OP_RCN
, /* Coprocessor register */
6523 OP_RF
, /* FPA register */
6524 OP_RVS
, /* VFP single precision register */
6525 OP_RVD
, /* VFP double precision register (0..15) */
6526 OP_RND
, /* Neon double precision register (0..31) */
6527 OP_RNQ
, /* Neon quad precision register */
6528 OP_RVSD
, /* VFP single or double precision register */
6529 OP_RNSD
, /* Neon single or double precision register */
6530 OP_RNDQ
, /* Neon double or quad precision register */
6531 OP_RNSDQ
, /* Neon single, double or quad precision register */
6532 OP_RNSC
, /* Neon scalar D[X] */
6533 OP_RVC
, /* VFP control register */
6534 OP_RMF
, /* Maverick F register */
6535 OP_RMD
, /* Maverick D register */
6536 OP_RMFX
, /* Maverick FX register */
6537 OP_RMDX
, /* Maverick DX register */
6538 OP_RMAX
, /* Maverick AX register */
6539 OP_RMDS
, /* Maverick DSPSC register */
6540 OP_RIWR
, /* iWMMXt wR register */
6541 OP_RIWC
, /* iWMMXt wC register */
6542 OP_RIWG
, /* iWMMXt wCG register */
6543 OP_RXA
, /* XScale accumulator register */
6545 OP_REGLST
, /* ARM register list */
6546 OP_VRSLST
, /* VFP single-precision register list */
6547 OP_VRDLST
, /* VFP double-precision register list */
6548 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
6549 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
6550 OP_NSTRLST
, /* Neon element/structure list */
6552 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
6553 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
6554 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
6555 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
6556 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
6557 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
6558 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
6559 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
6560 OP_VMOV
, /* Neon VMOV operands. */
6561 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
6562 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
6563 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
6565 OP_I0
, /* immediate zero */
6566 OP_I7
, /* immediate value 0 .. 7 */
6567 OP_I15
, /* 0 .. 15 */
6568 OP_I16
, /* 1 .. 16 */
6569 OP_I16z
, /* 0 .. 16 */
6570 OP_I31
, /* 0 .. 31 */
6571 OP_I31w
, /* 0 .. 31, optional trailing ! */
6572 OP_I32
, /* 1 .. 32 */
6573 OP_I32z
, /* 0 .. 32 */
6574 OP_I63
, /* 0 .. 63 */
6575 OP_I63s
, /* -64 .. 63 */
6576 OP_I64
, /* 1 .. 64 */
6577 OP_I64z
, /* 0 .. 64 */
6578 OP_I255
, /* 0 .. 255 */
6580 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
6581 OP_I7b
, /* 0 .. 7 */
6582 OP_I15b
, /* 0 .. 15 */
6583 OP_I31b
, /* 0 .. 31 */
6585 OP_SH
, /* shifter operand */
6586 OP_SHG
, /* shifter operand with possible group relocation */
6587 OP_ADDR
, /* Memory address expression (any mode) */
6588 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
6589 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
6590 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
6591 OP_EXP
, /* arbitrary expression */
6592 OP_EXPi
, /* same, with optional immediate prefix */
6593 OP_EXPr
, /* same, with optional relocation suffix */
6594 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
6595 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
6596 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
6598 OP_CPSF
, /* CPS flags */
6599 OP_ENDI
, /* Endianness specifier */
6600 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
6601 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
6602 OP_COND
, /* conditional code */
6603 OP_TB
, /* Table branch. */
6605 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
6607 OP_RRnpc_I0
, /* ARM register or literal 0 */
6608 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
6609 OP_RR_EXi
, /* ARM register or expression with imm prefix */
6610 OP_RF_IF
, /* FPA register or immediate */
6611 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
6612 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
6614 /* Optional operands. */
6615 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
6616 OP_oI31b
, /* 0 .. 31 */
6617 OP_oI32b
, /* 1 .. 32 */
6618 OP_oI32z
, /* 0 .. 32 */
6619 OP_oIffffb
, /* 0 .. 65535 */
6620 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
6622 OP_oRR
, /* ARM register */
6623 OP_oRRnpc
, /* ARM register, not the PC */
6624 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
6625 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
6626 OP_oRND
, /* Optional Neon double precision register */
6627 OP_oRNQ
, /* Optional Neon quad precision register */
6628 OP_oRNDQ
, /* Optional Neon double or quad precision register */
6629 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
6630 OP_oSHll
, /* LSL immediate */
6631 OP_oSHar
, /* ASR immediate */
6632 OP_oSHllar
, /* LSL or ASR immediate */
6633 OP_oROR
, /* ROR 0/8/16/24 */
6634 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
6636 /* Some pre-defined mixed (ARM/THUMB) operands. */
6637 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
6638 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
6639 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
6641 OP_FIRST_OPTIONAL
= OP_oI7b
6644 /* Generic instruction operand parser. This does no encoding and no
6645 semantic validation; it merely squirrels values away in the inst
6646 structure. Returns SUCCESS or FAIL depending on whether the
6647 specified grammar matched. */
6649 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
6651 unsigned const int *upat
= pattern
;
6652 char *backtrack_pos
= 0;
6653 const char *backtrack_error
= 0;
6654 int i
, val
= 0, backtrack_index
= 0;
6655 enum arm_reg_type rtype
;
6656 parse_operand_result result
;
6657 unsigned int op_parse_code
;
6659 #define po_char_or_fail(chr) \
6662 if (skip_past_char (&str, chr) == FAIL) \
6667 #define po_reg_or_fail(regtype) \
6670 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6671 & inst.operands[i].vectype); \
6674 first_error (_(reg_expected_msgs[regtype])); \
6677 inst.operands[i].reg = val; \
6678 inst.operands[i].isreg = 1; \
6679 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6680 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6681 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6682 || rtype == REG_TYPE_VFD \
6683 || rtype == REG_TYPE_NQ); \
6687 #define po_reg_or_goto(regtype, label) \
6690 val = arm_typed_reg_parse (& str, regtype, & rtype, \
6691 & inst.operands[i].vectype); \
6695 inst.operands[i].reg = val; \
6696 inst.operands[i].isreg = 1; \
6697 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
6698 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
6699 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
6700 || rtype == REG_TYPE_VFD \
6701 || rtype == REG_TYPE_NQ); \
6705 #define po_imm_or_fail(min, max, popt) \
6708 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
6710 inst.operands[i].imm = val; \
6714 #define po_scalar_or_goto(elsz, label) \
6717 val = parse_scalar (& str, elsz, & inst.operands[i].vectype); \
6720 inst.operands[i].reg = val; \
6721 inst.operands[i].isscalar = 1; \
6725 #define po_misc_or_fail(expr) \
6733 #define po_misc_or_fail_no_backtrack(expr) \
6737 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
6738 backtrack_pos = 0; \
6739 if (result != PARSE_OPERAND_SUCCESS) \
6744 #define po_barrier_or_imm(str) \
6747 val = parse_barrier (&str); \
6748 if (val == FAIL && ! ISALPHA (*str)) \
6751 /* ISB can only take SY as an option. */ \
6752 || ((inst.instruction & 0xf0) == 0x60 \
6755 inst.error = _("invalid barrier type"); \
6756 backtrack_pos = 0; \
6762 skip_whitespace (str
);
6764 for (i
= 0; upat
[i
] != OP_stop
; i
++)
6766 op_parse_code
= upat
[i
];
6767 if (op_parse_code
>= 1<<16)
6768 op_parse_code
= thumb
? (op_parse_code
>> 16)
6769 : (op_parse_code
& ((1<<16)-1));
6771 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
6773 /* Remember where we are in case we need to backtrack. */
6774 gas_assert (!backtrack_pos
);
6775 backtrack_pos
= str
;
6776 backtrack_error
= inst
.error
;
6777 backtrack_index
= i
;
6780 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
6781 po_char_or_fail (',');
6783 switch (op_parse_code
)
6791 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
6792 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
6793 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
6794 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
6795 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
6796 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
6798 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
6800 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
6802 /* Also accept generic coprocessor regs for unknown registers. */
6804 po_reg_or_fail (REG_TYPE_CN
);
6806 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
6807 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
6808 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
6809 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
6810 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
6811 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
6812 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
6813 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
6814 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
6815 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
6817 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
6818 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
6820 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
6821 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
6823 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
6825 /* Neon scalar. Using an element size of 8 means that some invalid
6826 scalars are accepted here, so deal with those in later code. */
6827 case OP_RNSC
: po_scalar_or_goto (8, failure
); break;
6831 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
6834 po_imm_or_fail (0, 0, TRUE
);
6839 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
6844 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
6847 if (parse_ifimm_zero (&str
))
6848 inst
.operands
[i
].imm
= 0;
6852 = _("only floating point zero is allowed as immediate value");
6860 po_scalar_or_goto (8, try_rr
);
6863 po_reg_or_fail (REG_TYPE_RN
);
6869 po_scalar_or_goto (8, try_nsdq
);
6872 po_reg_or_fail (REG_TYPE_NSDQ
);
6878 po_scalar_or_goto (8, try_s_scalar
);
6881 po_scalar_or_goto (4, try_nsd
);
6884 po_reg_or_fail (REG_TYPE_NSD
);
6890 po_scalar_or_goto (8, try_ndq
);
6893 po_reg_or_fail (REG_TYPE_NDQ
);
6899 po_scalar_or_goto (8, try_vfd
);
6902 po_reg_or_fail (REG_TYPE_VFD
);
6907 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
6908 not careful then bad things might happen. */
6909 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
6914 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
6917 /* There's a possibility of getting a 64-bit immediate here, so
6918 we need special handling. */
6919 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6922 inst
.error
= _("immediate value is out of range");
6930 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
6933 po_imm_or_fail (0, 63, TRUE
);
6938 po_char_or_fail ('[');
6939 po_reg_or_fail (REG_TYPE_RN
);
6940 po_char_or_fail (']');
6946 po_reg_or_fail (REG_TYPE_RN
);
6947 if (skip_past_char (&str
, '!') == SUCCESS
)
6948 inst
.operands
[i
].writeback
= 1;
6952 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
6953 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
6954 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
6955 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
6956 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
6957 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
6958 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
6959 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
6960 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
6961 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
6962 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
6963 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
6965 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
6967 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
6968 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
6970 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
6971 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
6972 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
6973 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
6975 /* Immediate variants */
6977 po_char_or_fail ('{');
6978 po_imm_or_fail (0, 255, TRUE
);
6979 po_char_or_fail ('}');
6983 /* The expression parser chokes on a trailing !, so we have
6984 to find it first and zap it. */
6987 while (*s
&& *s
!= ',')
6992 inst
.operands
[i
].writeback
= 1;
6994 po_imm_or_fail (0, 31, TRUE
);
7002 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7007 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7012 po_misc_or_fail (my_get_expression (&inst
.reloc
.exp
, &str
,
7014 if (inst
.reloc
.exp
.X_op
== O_symbol
)
7016 val
= parse_reloc (&str
);
7019 inst
.error
= _("unrecognized relocation suffix");
7022 else if (val
!= BFD_RELOC_UNUSED
)
7024 inst
.operands
[i
].imm
= val
;
7025 inst
.operands
[i
].hasreloc
= 1;
7030 /* Operand for MOVW or MOVT. */
7032 po_misc_or_fail (parse_half (&str
));
7035 /* Register or expression. */
7036 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7037 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7039 /* Register or immediate. */
7040 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7041 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7043 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7045 if (!is_immediate_prefix (*str
))
7048 val
= parse_fpa_immediate (&str
);
7051 /* FPA immediates are encoded as registers 8-15.
7052 parse_fpa_immediate has already applied the offset. */
7053 inst
.operands
[i
].reg
= val
;
7054 inst
.operands
[i
].isreg
= 1;
7057 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7058 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7060 /* Two kinds of register. */
7063 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7065 || (rege
->type
!= REG_TYPE_MMXWR
7066 && rege
->type
!= REG_TYPE_MMXWC
7067 && rege
->type
!= REG_TYPE_MMXWCG
))
7069 inst
.error
= _("iWMMXt data or control register expected");
7072 inst
.operands
[i
].reg
= rege
->number
;
7073 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7079 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7081 || (rege
->type
!= REG_TYPE_MMXWC
7082 && rege
->type
!= REG_TYPE_MMXWCG
))
7084 inst
.error
= _("iWMMXt control register expected");
7087 inst
.operands
[i
].reg
= rege
->number
;
7088 inst
.operands
[i
].isreg
= 1;
7093 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7094 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7095 case OP_oROR
: val
= parse_ror (&str
); break;
7096 case OP_COND
: val
= parse_cond (&str
); break;
7097 case OP_oBARRIER_I15
:
7098 po_barrier_or_imm (str
); break;
7100 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7106 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7107 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7109 inst
.error
= _("Banked registers are not available with this "
7115 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7119 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7122 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7124 if (strncasecmp (str
, "APSR_", 5) == 0)
7131 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7132 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7133 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7134 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7135 default: found
= 16;
7139 inst
.operands
[i
].isvec
= 1;
7140 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7141 inst
.operands
[i
].reg
= REG_PC
;
7148 po_misc_or_fail (parse_tb (&str
));
7151 /* Register lists. */
7153 val
= parse_reg_list (&str
);
7156 inst
.operands
[i
].writeback
= 1;
7162 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
);
7166 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
);
7170 /* Allow Q registers too. */
7171 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7176 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7178 inst
.operands
[i
].issingle
= 1;
7183 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7188 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7189 &inst
.operands
[i
].vectype
);
7192 /* Addressing modes */
7194 po_misc_or_fail (parse_address (&str
, i
));
7198 po_misc_or_fail_no_backtrack (
7199 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7203 po_misc_or_fail_no_backtrack (
7204 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7208 po_misc_or_fail_no_backtrack (
7209 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7213 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7217 po_misc_or_fail_no_backtrack (
7218 parse_shifter_operand_group_reloc (&str
, i
));
7222 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7226 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7230 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7234 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7237 /* Various value-based sanity checks and shared operations. We
7238 do not signal immediate failures for the register constraints;
7239 this allows a syntax error to take precedence. */
7240 switch (op_parse_code
)
7248 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7249 inst
.error
= BAD_PC
;
7254 if (inst
.operands
[i
].isreg
)
7256 if (inst
.operands
[i
].reg
== REG_PC
)
7257 inst
.error
= BAD_PC
;
7258 else if (inst
.operands
[i
].reg
== REG_SP
7259 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7260 relaxed since ARMv8-A. */
7261 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7264 inst
.error
= BAD_SP
;
7270 if (inst
.operands
[i
].isreg
7271 && inst
.operands
[i
].reg
== REG_PC
7272 && (inst
.operands
[i
].writeback
|| thumb
))
7273 inst
.error
= BAD_PC
;
7282 case OP_oBARRIER_I15
:
7291 inst
.operands
[i
].imm
= val
;
7298 /* If we get here, this operand was successfully parsed. */
7299 inst
.operands
[i
].present
= 1;
7303 inst
.error
= BAD_ARGS
;
7308 /* The parse routine should already have set inst.error, but set a
7309 default here just in case. */
7311 inst
.error
= _("syntax error");
7315 /* Do not backtrack over a trailing optional argument that
7316 absorbed some text. We will only fail again, with the
7317 'garbage following instruction' error message, which is
7318 probably less helpful than the current one. */
7319 if (backtrack_index
== i
&& backtrack_pos
!= str
7320 && upat
[i
+1] == OP_stop
)
7323 inst
.error
= _("syntax error");
7327 /* Try again, skipping the optional argument at backtrack_pos. */
7328 str
= backtrack_pos
;
7329 inst
.error
= backtrack_error
;
7330 inst
.operands
[backtrack_index
].present
= 0;
7331 i
= backtrack_index
;
7335 /* Check that we have parsed all the arguments. */
7336 if (*str
!= '\0' && !inst
.error
)
7337 inst
.error
= _("garbage following instruction");
7339 return inst
.error
? FAIL
: SUCCESS
;
7342 #undef po_char_or_fail
7343 #undef po_reg_or_fail
7344 #undef po_reg_or_goto
7345 #undef po_imm_or_fail
7346 #undef po_scalar_or_fail
7347 #undef po_barrier_or_imm
7349 /* Shorthand macro for instruction encoding functions issuing errors. */
7350 #define constraint(expr, err) \
7361 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
7362 instructions are unpredictable if these registers are used. This
7363 is the BadReg predicate in ARM's Thumb-2 documentation.
7365 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
7366 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
7367 #define reject_bad_reg(reg) \
7369 if (reg == REG_PC) \
7371 inst.error = BAD_PC; \
7374 else if (reg == REG_SP \
7375 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
7377 inst.error = BAD_SP; \
7382 /* If REG is R13 (the stack pointer), warn that its use is
7384 #define warn_deprecated_sp(reg) \
7386 if (warn_on_deprecated && reg == REG_SP) \
7387 as_tsktsk (_("use of r13 is deprecated")); \
7390 /* Functions for operand encoding. ARM, then Thumb. */
7392 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
7394 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
7396 The only binary encoding difference is the Coprocessor number. Coprocessor
7397 9 is used for half-precision calculations or conversions. The format of the
7398 instruction is the same as the equivalent Coprocessor 10 instruction that
7399 exists for Single-Precision operation. */
7402 do_scalar_fp16_v82_encode (void)
7404 if (inst
.cond
!= COND_ALWAYS
)
7405 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
7406 " the behaviour is UNPREDICTABLE"));
7407 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
7410 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
7411 mark_feature_used (&arm_ext_fp16
);
7414 /* If VAL can be encoded in the immediate field of an ARM instruction,
7415 return the encoded form. Otherwise, return FAIL. */
7418 encode_arm_immediate (unsigned int val
)
7425 for (i
= 2; i
< 32; i
+= 2)
7426 if ((a
= rotate_left (val
, i
)) <= 0xff)
7427 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
7432 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
7433 return the encoded form. Otherwise, return FAIL. */
7435 encode_thumb32_immediate (unsigned int val
)
7442 for (i
= 1; i
<= 24; i
++)
7445 if ((val
& ~(0xff << i
)) == 0)
7446 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
7450 if (val
== ((a
<< 16) | a
))
7452 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
7456 if (val
== ((a
<< 16) | a
))
7457 return 0x200 | (a
>> 8);
7461 /* Encode a VFP SP or DP register number into inst.instruction. */
7464 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
7466 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
7469 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
7472 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
7475 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
7480 first_error (_("D register out of range for selected VFP version"));
7488 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
7492 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
7496 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
7500 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
7504 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
7508 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
7516 /* Encode a <shift> in an ARM-format instruction. The immediate,
7517 if any, is handled by md_apply_fix. */
7519 encode_arm_shift (int i
)
7521 /* register-shifted register. */
7522 if (inst
.operands
[i
].immisreg
)
7525 for (op_index
= 0; op_index
<= i
; ++op_index
)
7527 /* Check the operand only when it's presented. In pre-UAL syntax,
7528 if the destination register is the same as the first operand, two
7529 register form of the instruction can be used. */
7530 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
7531 && inst
.operands
[op_index
].reg
== REG_PC
)
7532 as_warn (UNPRED_REG ("r15"));
7535 if (inst
.operands
[i
].imm
== REG_PC
)
7536 as_warn (UNPRED_REG ("r15"));
7539 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7540 inst
.instruction
|= SHIFT_ROR
<< 5;
7543 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7544 if (inst
.operands
[i
].immisreg
)
7546 inst
.instruction
|= SHIFT_BY_REG
;
7547 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
7550 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7555 encode_arm_shifter_operand (int i
)
7557 if (inst
.operands
[i
].isreg
)
7559 inst
.instruction
|= inst
.operands
[i
].reg
;
7560 encode_arm_shift (i
);
7564 inst
.instruction
|= INST_IMMEDIATE
;
7565 if (inst
.reloc
.type
!= BFD_RELOC_ARM_IMMEDIATE
)
7566 inst
.instruction
|= inst
.operands
[i
].imm
;
7570 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
7572 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
7575 Generate an error if the operand is not a register. */
7576 constraint (!inst
.operands
[i
].isreg
,
7577 _("Instruction does not support =N addresses"));
7579 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
7581 if (inst
.operands
[i
].preind
)
7585 inst
.error
= _("instruction does not accept preindexed addressing");
7588 inst
.instruction
|= PRE_INDEX
;
7589 if (inst
.operands
[i
].writeback
)
7590 inst
.instruction
|= WRITE_BACK
;
7593 else if (inst
.operands
[i
].postind
)
7595 gas_assert (inst
.operands
[i
].writeback
);
7597 inst
.instruction
|= WRITE_BACK
;
7599 else /* unindexed - only for coprocessor */
7601 inst
.error
= _("instruction does not accept unindexed addressing");
7605 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
7606 && (((inst
.instruction
& 0x000f0000) >> 16)
7607 == ((inst
.instruction
& 0x0000f000) >> 12)))
7608 as_warn ((inst
.instruction
& LOAD_BIT
)
7609 ? _("destination register same as write-back base")
7610 : _("source register same as write-back base"));
7613 /* inst.operands[i] was set up by parse_address. Encode it into an
7614 ARM-format mode 2 load or store instruction. If is_t is true,
7615 reject forms that cannot be used with a T instruction (i.e. not
7618 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
7620 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
7622 encode_arm_addr_mode_common (i
, is_t
);
7624 if (inst
.operands
[i
].immisreg
)
7626 constraint ((inst
.operands
[i
].imm
== REG_PC
7627 || (is_pc
&& inst
.operands
[i
].writeback
)),
7629 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
7630 inst
.instruction
|= inst
.operands
[i
].imm
;
7631 if (!inst
.operands
[i
].negative
)
7632 inst
.instruction
|= INDEX_UP
;
7633 if (inst
.operands
[i
].shifted
)
7635 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
7636 inst
.instruction
|= SHIFT_ROR
<< 5;
7639 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
7640 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
7644 else /* immediate offset in inst.reloc */
7646 if (is_pc
&& !inst
.reloc
.pc_rel
)
7648 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
7650 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
7651 cannot use PC in addressing.
7652 PC cannot be used in writeback addressing, either. */
7653 constraint ((is_t
|| inst
.operands
[i
].writeback
),
7656 /* Use of PC in str is deprecated for ARMv7. */
7657 if (warn_on_deprecated
7659 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
7660 as_tsktsk (_("use of PC in this instruction is deprecated"));
7663 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7665 /* Prefer + for zero encoded value. */
7666 if (!inst
.operands
[i
].negative
)
7667 inst
.instruction
|= INDEX_UP
;
7668 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM
;
7673 /* inst.operands[i] was set up by parse_address. Encode it into an
7674 ARM-format mode 3 load or store instruction. Reject forms that
7675 cannot be used with such instructions. If is_t is true, reject
7676 forms that cannot be used with a T instruction (i.e. not
7679 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
7681 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
7683 inst
.error
= _("instruction does not accept scaled register index");
7687 encode_arm_addr_mode_common (i
, is_t
);
7689 if (inst
.operands
[i
].immisreg
)
7691 constraint ((inst
.operands
[i
].imm
== REG_PC
7692 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
7694 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
7696 inst
.instruction
|= inst
.operands
[i
].imm
;
7697 if (!inst
.operands
[i
].negative
)
7698 inst
.instruction
|= INDEX_UP
;
7700 else /* immediate offset in inst.reloc */
7702 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.reloc
.pc_rel
7703 && inst
.operands
[i
].writeback
),
7705 inst
.instruction
|= HWOFFSET_IMM
;
7706 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
7708 /* Prefer + for zero encoded value. */
7709 if (!inst
.operands
[i
].negative
)
7710 inst
.instruction
|= INDEX_UP
;
7712 inst
.reloc
.type
= BFD_RELOC_ARM_OFFSET_IMM8
;
7717 /* Write immediate bits [7:0] to the following locations:
7719 |28/24|23 19|18 16|15 4|3 0|
7720 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
7722 This function is used by VMOV/VMVN/VORR/VBIC. */
7725 neon_write_immbits (unsigned immbits
)
7727 inst
.instruction
|= immbits
& 0xf;
7728 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
7729 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
7732 /* Invert low-order SIZE bits of XHI:XLO. */
7735 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
7737 unsigned immlo
= xlo
? *xlo
: 0;
7738 unsigned immhi
= xhi
? *xhi
: 0;
7743 immlo
= (~immlo
) & 0xff;
7747 immlo
= (~immlo
) & 0xffff;
7751 immhi
= (~immhi
) & 0xffffffff;
7755 immlo
= (~immlo
) & 0xffffffff;
7769 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
7773 neon_bits_same_in_bytes (unsigned imm
)
7775 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
7776 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
7777 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
7778 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
7781 /* For immediate of above form, return 0bABCD. */
7784 neon_squash_bits (unsigned imm
)
7786 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
7787 | ((imm
& 0x01000000) >> 21);
7790 /* Compress quarter-float representation to 0b...000 abcdefgh. */
7793 neon_qfloat_bits (unsigned imm
)
7795 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
7798 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
7799 the instruction. *OP is passed as the initial value of the op field, and
7800 may be set to a different value depending on the constant (i.e.
7801 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
7802 MVN). If the immediate looks like a repeated pattern then also
7803 try smaller element sizes. */
7806 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
7807 unsigned *immbits
, int *op
, int size
,
7808 enum neon_el_type type
)
7810 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
7812 if (type
== NT_float
&& !float_p
)
7815 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
7817 if (size
!= 32 || *op
== 1)
7819 *immbits
= neon_qfloat_bits (immlo
);
7825 if (neon_bits_same_in_bytes (immhi
)
7826 && neon_bits_same_in_bytes (immlo
))
7830 *immbits
= (neon_squash_bits (immhi
) << 4)
7831 | neon_squash_bits (immlo
);
7842 if (immlo
== (immlo
& 0x000000ff))
7847 else if (immlo
== (immlo
& 0x0000ff00))
7849 *immbits
= immlo
>> 8;
7852 else if (immlo
== (immlo
& 0x00ff0000))
7854 *immbits
= immlo
>> 16;
7857 else if (immlo
== (immlo
& 0xff000000))
7859 *immbits
= immlo
>> 24;
7862 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
7864 *immbits
= (immlo
>> 8) & 0xff;
7867 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
7869 *immbits
= (immlo
>> 16) & 0xff;
7873 if ((immlo
& 0xffff) != (immlo
>> 16))
7880 if (immlo
== (immlo
& 0x000000ff))
7885 else if (immlo
== (immlo
& 0x0000ff00))
7887 *immbits
= immlo
>> 8;
7891 if ((immlo
& 0xff) != (immlo
>> 8))
7896 if (immlo
== (immlo
& 0x000000ff))
7898 /* Don't allow MVN with 8-bit immediate. */
7908 #if defined BFD_HOST_64_BIT
7909 /* Returns TRUE if double precision value V may be cast
7910 to single precision without loss of accuracy. */
7913 is_double_a_single (bfd_int64_t v
)
7915 int exp
= (int)((v
>> 52) & 0x7FF);
7916 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7918 return (exp
== 0 || exp
== 0x7FF
7919 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
7920 && (mantissa
& 0x1FFFFFFFl
) == 0;
7923 /* Returns a double precision value casted to single precision
7924 (ignoring the least significant bits in exponent and mantissa). */
7927 double_to_single (bfd_int64_t v
)
7929 int sign
= (int) ((v
>> 63) & 1l);
7930 int exp
= (int) ((v
>> 52) & 0x7FF);
7931 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
7937 exp
= exp
- 1023 + 127;
7946 /* No denormalized numbers. */
7952 return (sign
<< 31) | (exp
<< 23) | mantissa
;
7954 #endif /* BFD_HOST_64_BIT */
7963 static void do_vfp_nsyn_opcode (const char *);
7965 /* inst.reloc.exp describes an "=expr" load pseudo-operation.
7966 Determine whether it can be performed with a move instruction; if
7967 it can, convert inst.instruction to that move instruction and
7968 return TRUE; if it can't, convert inst.instruction to a literal-pool
7969 load and return FALSE. If this is not a valid thing to do in the
7970 current context, set inst.error and return TRUE.
7972 inst.operands[i] describes the destination register. */
7975 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
7978 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
7979 bfd_boolean arm_p
= (t
== CONST_ARM
);
7982 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
7986 if ((inst
.instruction
& tbit
) == 0)
7988 inst
.error
= _("invalid pseudo operation");
7992 if (inst
.reloc
.exp
.X_op
!= O_constant
7993 && inst
.reloc
.exp
.X_op
!= O_symbol
7994 && inst
.reloc
.exp
.X_op
!= O_big
)
7996 inst
.error
= _("constant expression expected");
8000 if (inst
.reloc
.exp
.X_op
== O_constant
8001 || inst
.reloc
.exp
.X_op
== O_big
)
8003 #if defined BFD_HOST_64_BIT
8008 if (inst
.reloc
.exp
.X_op
== O_big
)
8010 LITTLENUM_TYPE w
[X_PRECISION
];
8013 if (inst
.reloc
.exp
.X_add_number
== -1)
8015 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8017 /* FIXME: Should we check words w[2..5] ? */
8022 #if defined BFD_HOST_64_BIT
8024 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8025 << LITTLENUM_NUMBER_OF_BITS
)
8026 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8027 << LITTLENUM_NUMBER_OF_BITS
)
8028 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8029 << LITTLENUM_NUMBER_OF_BITS
)
8030 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8032 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8033 | (l
[0] & LITTLENUM_MASK
);
8037 v
= inst
.reloc
.exp
.X_add_number
;
8039 if (!inst
.operands
[i
].issingle
)
8043 /* LDR should not use lead in a flag-setting instruction being
8044 chosen so we do not check whether movs can be used. */
8046 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8047 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8048 && inst
.operands
[i
].reg
!= 13
8049 && inst
.operands
[i
].reg
!= 15)
8051 /* Check if on thumb2 it can be done with a mov.w, mvn or
8052 movw instruction. */
8053 unsigned int newimm
;
8054 bfd_boolean isNegated
;
8056 newimm
= encode_thumb32_immediate (v
);
8057 if (newimm
!= (unsigned int) FAIL
)
8061 newimm
= encode_thumb32_immediate (~v
);
8062 if (newimm
!= (unsigned int) FAIL
)
8066 /* The number can be loaded with a mov.w or mvn
8068 if (newimm
!= (unsigned int) FAIL
8069 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8071 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8072 | (inst
.operands
[i
].reg
<< 8));
8073 /* Change to MOVN. */
8074 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8075 inst
.instruction
|= (newimm
& 0x800) << 15;
8076 inst
.instruction
|= (newimm
& 0x700) << 4;
8077 inst
.instruction
|= (newimm
& 0x0ff);
8080 /* The number can be loaded with a movw instruction. */
8081 else if ((v
& ~0xFFFF) == 0
8082 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8084 int imm
= v
& 0xFFFF;
8086 inst
.instruction
= 0xf2400000; /* MOVW. */
8087 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8088 inst
.instruction
|= (imm
& 0xf000) << 4;
8089 inst
.instruction
|= (imm
& 0x0800) << 15;
8090 inst
.instruction
|= (imm
& 0x0700) << 4;
8091 inst
.instruction
|= (imm
& 0x00ff);
8098 int value
= encode_arm_immediate (v
);
8102 /* This can be done with a mov instruction. */
8103 inst
.instruction
&= LITERAL_MASK
;
8104 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8105 inst
.instruction
|= value
& 0xfff;
8109 value
= encode_arm_immediate (~ v
);
8112 /* This can be done with a mvn instruction. */
8113 inst
.instruction
&= LITERAL_MASK
;
8114 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8115 inst
.instruction
|= value
& 0xfff;
8119 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8122 unsigned immbits
= 0;
8123 unsigned immlo
= inst
.operands
[1].imm
;
8124 unsigned immhi
= inst
.operands
[1].regisimm
8125 ? inst
.operands
[1].reg
8126 : inst
.reloc
.exp
.X_unsigned
8128 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8129 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8130 &op
, 64, NT_invtype
);
8134 neon_invert_size (&immlo
, &immhi
, 64);
8136 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8137 &op
, 64, NT_invtype
);
8142 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8148 /* Fill other bits in vmov encoding for both thumb and arm. */
8150 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8152 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8153 neon_write_immbits (immbits
);
8161 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8162 if (inst
.operands
[i
].issingle
8163 && is_quarter_float (inst
.operands
[1].imm
)
8164 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8166 inst
.operands
[1].imm
=
8167 neon_qfloat_bits (v
);
8168 do_vfp_nsyn_opcode ("fconsts");
8172 /* If our host does not support a 64-bit type then we cannot perform
8173 the following optimization. This mean that there will be a
8174 discrepancy between the output produced by an assembler built for
8175 a 32-bit-only host and the output produced from a 64-bit host, but
8176 this cannot be helped. */
8177 #if defined BFD_HOST_64_BIT
8178 else if (!inst
.operands
[1].issingle
8179 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8181 if (is_double_a_single (v
)
8182 && is_quarter_float (double_to_single (v
)))
8184 inst
.operands
[1].imm
=
8185 neon_qfloat_bits (double_to_single (v
));
8186 do_vfp_nsyn_opcode ("fconstd");
8194 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8195 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8198 inst
.operands
[1].reg
= REG_PC
;
8199 inst
.operands
[1].isreg
= 1;
8200 inst
.operands
[1].preind
= 1;
8201 inst
.reloc
.pc_rel
= 1;
8202 inst
.reloc
.type
= (thumb_p
8203 ? BFD_RELOC_ARM_THUMB_OFFSET
8205 ? BFD_RELOC_ARM_HWLITERAL
8206 : BFD_RELOC_ARM_LITERAL
));
8210 /* inst.operands[i] was set up by parse_address. Encode it into an
8211 ARM-format instruction. Reject all forms which cannot be encoded
8212 into a coprocessor load/store instruction. If wb_ok is false,
8213 reject use of writeback; if unind_ok is false, reject use of
8214 unindexed addressing. If reloc_override is not 0, use it instead
8215 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8216 (in which case it is preserved). */
8219 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8221 if (!inst
.operands
[i
].isreg
)
8224 if (! inst
.operands
[0].isvec
)
8226 inst
.error
= _("invalid co-processor operand");
8229 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8233 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8235 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8237 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8239 gas_assert (!inst
.operands
[i
].writeback
);
8242 inst
.error
= _("instruction does not support unindexed addressing");
8245 inst
.instruction
|= inst
.operands
[i
].imm
;
8246 inst
.instruction
|= INDEX_UP
;
8250 if (inst
.operands
[i
].preind
)
8251 inst
.instruction
|= PRE_INDEX
;
8253 if (inst
.operands
[i
].writeback
)
8255 if (inst
.operands
[i
].reg
== REG_PC
)
8257 inst
.error
= _("pc may not be used with write-back");
8262 inst
.error
= _("instruction does not support writeback");
8265 inst
.instruction
|= WRITE_BACK
;
8269 inst
.reloc
.type
= (bfd_reloc_code_real_type
) reloc_override
;
8270 else if ((inst
.reloc
.type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8271 || inst
.reloc
.type
> BFD_RELOC_ARM_LDC_SB_G2
)
8272 && inst
.reloc
.type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8275 inst
.reloc
.type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8277 inst
.reloc
.type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8280 /* Prefer + for zero encoded value. */
8281 if (!inst
.operands
[i
].negative
)
8282 inst
.instruction
|= INDEX_UP
;
8287 /* Functions for instruction encoding, sorted by sub-architecture.
8288 First some generics; their names are taken from the conventional
8289 bit positions for register arguments in ARM format instructions. */
8299 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8305 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8311 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8312 inst
.instruction
|= inst
.operands
[1].reg
;
8318 inst
.instruction
|= inst
.operands
[0].reg
;
8319 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8325 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8326 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8332 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8333 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8339 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8340 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8344 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
8346 if (ARM_CPU_IS_ANY (cpu_variant
))
8348 as_tsktsk ("%s", msg
);
8351 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
8363 unsigned Rn
= inst
.operands
[2].reg
;
8364 /* Enforce restrictions on SWP instruction. */
8365 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
8367 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
8368 _("Rn must not overlap other operands"));
8370 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
8372 if (!check_obsolete (&arm_ext_v8
,
8373 _("swp{b} use is obsoleted for ARMv8 and later"))
8374 && warn_on_deprecated
8375 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
8376 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
8379 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8380 inst
.instruction
|= inst
.operands
[1].reg
;
8381 inst
.instruction
|= Rn
<< 16;
8387 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8388 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8389 inst
.instruction
|= inst
.operands
[2].reg
;
8395 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
8396 constraint (((inst
.reloc
.exp
.X_op
!= O_constant
8397 && inst
.reloc
.exp
.X_op
!= O_illegal
)
8398 || inst
.reloc
.exp
.X_add_number
!= 0),
8400 inst
.instruction
|= inst
.operands
[0].reg
;
8401 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
8402 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
8408 inst
.instruction
|= inst
.operands
[0].imm
;
8414 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8415 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
8418 /* ARM instructions, in alphabetical order by function name (except
8419 that wrapper functions appear immediately after the function they
8422 /* This is a pseudo-op of the form "adr rd, label" to be converted
8423 into a relative address of the form "add rd, pc, #label-.-8". */
8428 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8430 /* Frag hacking will turn this into a sub instruction if the offset turns
8431 out to be negative. */
8432 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
8433 inst
.reloc
.pc_rel
= 1;
8434 inst
.reloc
.exp
.X_add_number
-= 8;
8436 if (inst
.reloc
.exp
.X_op
== O_symbol
8437 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8438 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8439 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8440 inst
.reloc
.exp
.X_add_number
+= 1;
8443 /* This is a pseudo-op of the form "adrl rd, label" to be converted
8444 into a relative address of the form:
8445 add rd, pc, #low(label-.-8)"
8446 add rd, rd, #high(label-.-8)" */
8451 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
8453 /* Frag hacking will turn this into a sub instruction if the offset turns
8454 out to be negative. */
8455 inst
.reloc
.type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
8456 inst
.reloc
.pc_rel
= 1;
8457 inst
.size
= INSN_SIZE
* 2;
8458 inst
.reloc
.exp
.X_add_number
-= 8;
8460 if (inst
.reloc
.exp
.X_op
== O_symbol
8461 && inst
.reloc
.exp
.X_add_symbol
!= NULL
8462 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
8463 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
8464 inst
.reloc
.exp
.X_add_number
+= 1;
8470 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
8471 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
8473 if (!inst
.operands
[1].present
)
8474 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
8475 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8476 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
8477 encode_arm_shifter_operand (2);
8483 if (inst
.operands
[0].present
)
8484 inst
.instruction
|= inst
.operands
[0].imm
;
8486 inst
.instruction
|= 0xf;
8492 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
8493 constraint (msb
> 32, _("bit-field extends past end of register"));
8494 /* The instruction encoding stores the LSB and MSB,
8495 not the LSB and width. */
8496 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8497 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
8498 inst
.instruction
|= (msb
- 1) << 16;
8506 /* #0 in second position is alternative syntax for bfc, which is
8507 the same instruction but with REG_PC in the Rm field. */
8508 if (!inst
.operands
[1].isreg
)
8509 inst
.operands
[1].reg
= REG_PC
;
8511 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
8512 constraint (msb
> 32, _("bit-field extends past end of register"));
8513 /* The instruction encoding stores the LSB and MSB,
8514 not the LSB and width. */
8515 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8516 inst
.instruction
|= inst
.operands
[1].reg
;
8517 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8518 inst
.instruction
|= (msb
- 1) << 16;
8524 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
8525 _("bit-field extends past end of register"));
8526 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8527 inst
.instruction
|= inst
.operands
[1].reg
;
8528 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
8529 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
8532 /* ARM V5 breakpoint instruction (argument parse)
8533 BKPT <16 bit unsigned immediate>
8534 Instruction is not conditional.
8535 The bit pattern given in insns[] has the COND_ALWAYS condition,
8536 and it is an error if the caller tried to override that. */
8541 /* Top 12 of 16 bits to bits 19:8. */
8542 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
8544 /* Bottom 4 of 16 bits to bits 3:0. */
8545 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
8549 encode_branch (int default_reloc
)
8551 if (inst
.operands
[0].hasreloc
)
8553 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
8554 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
8555 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
8556 inst
.reloc
.type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
8557 ? BFD_RELOC_ARM_PLT32
8558 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
8561 inst
.reloc
.type
= (bfd_reloc_code_real_type
) default_reloc
;
8562 inst
.reloc
.pc_rel
= 1;
8569 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8570 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8573 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8580 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
8582 if (inst
.cond
== COND_ALWAYS
)
8583 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
8585 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
8589 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
8592 /* ARM V5 branch-link-exchange instruction (argument parse)
8593 BLX <target_addr> ie BLX(1)
8594 BLX{<condition>} <Rm> ie BLX(2)
8595 Unfortunately, there are two different opcodes for this mnemonic.
8596 So, the insns[].value is not used, and the code here zaps values
8597 into inst.instruction.
8598 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
8603 if (inst
.operands
[0].isreg
)
8605 /* Arg is a register; the opcode provided by insns[] is correct.
8606 It is not illegal to do "blx pc", just useless. */
8607 if (inst
.operands
[0].reg
== REG_PC
)
8608 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
8610 inst
.instruction
|= inst
.operands
[0].reg
;
8614 /* Arg is an address; this instruction cannot be executed
8615 conditionally, and the opcode must be adjusted.
8616 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
8617 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
8618 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
8619 inst
.instruction
= 0xfa000000;
8620 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
8627 bfd_boolean want_reloc
;
8629 if (inst
.operands
[0].reg
== REG_PC
)
8630 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
8632 inst
.instruction
|= inst
.operands
[0].reg
;
8633 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
8634 it is for ARMv4t or earlier. */
8635 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
8636 if (!ARM_FEATURE_ZERO (selected_object_arch
)
8637 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
8641 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
8646 inst
.reloc
.type
= BFD_RELOC_ARM_V4BX
;
8650 /* ARM v5TEJ. Jump to Jazelle code. */
8655 if (inst
.operands
[0].reg
== REG_PC
)
8656 as_tsktsk (_("use of r15 in bxj is not really useful"));
8658 inst
.instruction
|= inst
.operands
[0].reg
;
8661 /* Co-processor data operation:
8662 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
8663 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
8667 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8668 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
8669 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
8670 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8671 inst
.instruction
|= inst
.operands
[4].reg
;
8672 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8678 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
8679 encode_arm_shifter_operand (1);
8682 /* Transfer between coprocessor and ARM registers.
8683 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
8688 No special properties. */
8690 struct deprecated_coproc_regs_s
8697 arm_feature_set deprecated
;
8698 arm_feature_set obsoleted
;
8699 const char *dep_msg
;
8700 const char *obs_msg
;
8703 #define DEPR_ACCESS_V8 \
8704 N_("This coprocessor register access is deprecated in ARMv8")
8706 /* Table of all deprecated coprocessor registers. */
8707 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
8709 {15, 0, 7, 10, 5, /* CP15DMB. */
8710 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8711 DEPR_ACCESS_V8
, NULL
},
8712 {15, 0, 7, 10, 4, /* CP15DSB. */
8713 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8714 DEPR_ACCESS_V8
, NULL
},
8715 {15, 0, 7, 5, 4, /* CP15ISB. */
8716 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8717 DEPR_ACCESS_V8
, NULL
},
8718 {14, 6, 1, 0, 0, /* TEEHBR. */
8719 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8720 DEPR_ACCESS_V8
, NULL
},
8721 {14, 6, 0, 0, 0, /* TEECR. */
8722 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
8723 DEPR_ACCESS_V8
, NULL
},
8726 #undef DEPR_ACCESS_V8
8728 static const size_t deprecated_coproc_reg_count
=
8729 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
8737 Rd
= inst
.operands
[2].reg
;
8740 if (inst
.instruction
== 0xee000010
8741 || inst
.instruction
== 0xfe000010)
8743 reject_bad_reg (Rd
);
8744 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
8746 constraint (Rd
== REG_SP
, BAD_SP
);
8751 if (inst
.instruction
== 0xe000010)
8752 constraint (Rd
== REG_PC
, BAD_PC
);
8755 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
8757 const struct deprecated_coproc_regs_s
*r
=
8758 deprecated_coproc_regs
+ i
;
8760 if (inst
.operands
[0].reg
== r
->cp
8761 && inst
.operands
[1].imm
== r
->opc1
8762 && inst
.operands
[3].reg
== r
->crn
8763 && inst
.operands
[4].reg
== r
->crm
8764 && inst
.operands
[5].imm
== r
->opc2
)
8766 if (! ARM_CPU_IS_ANY (cpu_variant
)
8767 && warn_on_deprecated
8768 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
8769 as_tsktsk ("%s", r
->dep_msg
);
8773 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8774 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
8775 inst
.instruction
|= Rd
<< 12;
8776 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
8777 inst
.instruction
|= inst
.operands
[4].reg
;
8778 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
8781 /* Transfer between coprocessor register and pair of ARM registers.
8782 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
8787 Two XScale instructions are special cases of these:
8789 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
8790 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
8792 Result unpredictable if Rd or Rn is R15. */
8799 Rd
= inst
.operands
[2].reg
;
8800 Rn
= inst
.operands
[3].reg
;
8804 reject_bad_reg (Rd
);
8805 reject_bad_reg (Rn
);
8809 constraint (Rd
== REG_PC
, BAD_PC
);
8810 constraint (Rn
== REG_PC
, BAD_PC
);
8813 /* Only check the MRRC{2} variants. */
8814 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
8816 /* If Rd == Rn, error that the operation is
8817 unpredictable (example MRRC p3,#1,r1,r1,c4). */
8818 constraint (Rd
== Rn
, BAD_OVERLAP
);
8821 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
8822 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
8823 inst
.instruction
|= Rd
<< 12;
8824 inst
.instruction
|= Rn
<< 16;
8825 inst
.instruction
|= inst
.operands
[4].reg
;
8831 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
8832 if (inst
.operands
[1].present
)
8834 inst
.instruction
|= CPSI_MMOD
;
8835 inst
.instruction
|= inst
.operands
[1].imm
;
8842 inst
.instruction
|= inst
.operands
[0].imm
;
8848 unsigned Rd
, Rn
, Rm
;
8850 Rd
= inst
.operands
[0].reg
;
8851 Rn
= (inst
.operands
[1].present
8852 ? inst
.operands
[1].reg
: Rd
);
8853 Rm
= inst
.operands
[2].reg
;
8855 constraint ((Rd
== REG_PC
), BAD_PC
);
8856 constraint ((Rn
== REG_PC
), BAD_PC
);
8857 constraint ((Rm
== REG_PC
), BAD_PC
);
8859 inst
.instruction
|= Rd
<< 16;
8860 inst
.instruction
|= Rn
<< 0;
8861 inst
.instruction
|= Rm
<< 8;
8867 /* There is no IT instruction in ARM mode. We
8868 process it to do the validation as if in
8869 thumb mode, just in case the code gets
8870 assembled for thumb using the unified syntax. */
8875 set_it_insn_type (IT_INSN
);
8876 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
8877 now_it
.cc
= inst
.operands
[0].imm
;
8881 /* If there is only one register in the register list,
8882 then return its register number. Otherwise return -1. */
8884 only_one_reg_in_list (int range
)
8886 int i
= ffs (range
) - 1;
8887 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
8891 encode_ldmstm(int from_push_pop_mnem
)
8893 int base_reg
= inst
.operands
[0].reg
;
8894 int range
= inst
.operands
[1].imm
;
8897 inst
.instruction
|= base_reg
<< 16;
8898 inst
.instruction
|= range
;
8900 if (inst
.operands
[1].writeback
)
8901 inst
.instruction
|= LDM_TYPE_2_OR_3
;
8903 if (inst
.operands
[0].writeback
)
8905 inst
.instruction
|= WRITE_BACK
;
8906 /* Check for unpredictable uses of writeback. */
8907 if (inst
.instruction
& LOAD_BIT
)
8909 /* Not allowed in LDM type 2. */
8910 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
8911 && ((range
& (1 << REG_PC
)) == 0))
8912 as_warn (_("writeback of base register is UNPREDICTABLE"));
8913 /* Only allowed if base reg not in list for other types. */
8914 else if (range
& (1 << base_reg
))
8915 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
8919 /* Not allowed for type 2. */
8920 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
8921 as_warn (_("writeback of base register is UNPREDICTABLE"));
8922 /* Only allowed if base reg not in list, or first in list. */
8923 else if ((range
& (1 << base_reg
))
8924 && (range
& ((1 << base_reg
) - 1)))
8925 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
8929 /* If PUSH/POP has only one register, then use the A2 encoding. */
8930 one_reg
= only_one_reg_in_list (range
);
8931 if (from_push_pop_mnem
&& one_reg
>= 0)
8933 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
8935 if (is_push
&& one_reg
== 13 /* SP */)
8936 /* PR 22483: The A2 encoding cannot be used when
8937 pushing the stack pointer as this is UNPREDICTABLE. */
8940 inst
.instruction
&= A_COND_MASK
;
8941 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
8942 inst
.instruction
|= one_reg
<< 12;
8949 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
8952 /* ARMv5TE load-consecutive (argument parse)
8961 constraint (inst
.operands
[0].reg
% 2 != 0,
8962 _("first transfer register must be even"));
8963 constraint (inst
.operands
[1].present
8964 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
8965 _("can only transfer two consecutive registers"));
8966 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
8967 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
8969 if (!inst
.operands
[1].present
)
8970 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
8972 /* encode_arm_addr_mode_3 will diagnose overlap between the base
8973 register and the first register written; we have to diagnose
8974 overlap between the base and the second register written here. */
8976 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
8977 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
8978 as_warn (_("base register written back, and overlaps "
8979 "second transfer register"));
8981 if (!(inst
.instruction
& V4_STR_BIT
))
8983 /* For an index-register load, the index register must not overlap the
8984 destination (even if not write-back). */
8985 if (inst
.operands
[2].immisreg
8986 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
8987 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
8988 as_warn (_("index register overlaps transfer register"));
8990 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
8991 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
8997 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
8998 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
8999 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9000 || inst
.operands
[1].negative
9001 /* This can arise if the programmer has written
9003 or if they have mistakenly used a register name as the last
9006 It is very difficult to distinguish between these two cases
9007 because "rX" might actually be a label. ie the register
9008 name has been occluded by a symbol of the same name. So we
9009 just generate a general 'bad addressing mode' type error
9010 message and leave it up to the programmer to discover the
9011 true cause and fix their mistake. */
9012 || (inst
.operands
[1].reg
== REG_PC
),
9015 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9016 || inst
.reloc
.exp
.X_add_number
!= 0,
9017 _("offset must be zero in ARM encoding"));
9019 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9021 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9023 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9029 constraint (inst
.operands
[0].reg
% 2 != 0,
9030 _("even register required"));
9031 constraint (inst
.operands
[1].present
9032 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9033 _("can only load two consecutive registers"));
9034 /* If op 1 were present and equal to PC, this function wouldn't
9035 have been called in the first place. */
9036 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9038 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9039 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9042 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9043 which is not a multiple of four is UNPREDICTABLE. */
9045 check_ldr_r15_aligned (void)
9047 constraint (!(inst
.operands
[1].immisreg
)
9048 && (inst
.operands
[0].reg
== REG_PC
9049 && inst
.operands
[1].reg
== REG_PC
9050 && (inst
.reloc
.exp
.X_add_number
& 0x3)),
9051 _("ldr to register 15 must be 4-byte aligned"));
9057 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9058 if (!inst
.operands
[1].isreg
)
9059 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9061 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9062 check_ldr_r15_aligned ();
9068 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9070 if (inst
.operands
[1].preind
)
9072 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9073 || inst
.reloc
.exp
.X_add_number
!= 0,
9074 _("this instruction requires a post-indexed address"));
9076 inst
.operands
[1].preind
= 0;
9077 inst
.operands
[1].postind
= 1;
9078 inst
.operands
[1].writeback
= 1;
9080 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9081 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9084 /* Halfword and signed-byte load/store operations. */
9089 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9091 if (!inst
.operands
[1].isreg
)
9092 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9094 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9100 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9102 if (inst
.operands
[1].preind
)
9104 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9105 || inst
.reloc
.exp
.X_add_number
!= 0,
9106 _("this instruction requires a post-indexed address"));
9108 inst
.operands
[1].preind
= 0;
9109 inst
.operands
[1].postind
= 1;
9110 inst
.operands
[1].writeback
= 1;
9112 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9113 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9116 /* Co-processor register load/store.
9117 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9121 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9122 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9123 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9129 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9130 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9131 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9132 && !(inst
.instruction
& 0x00400000))
9133 as_tsktsk (_("Rd and Rm should be different in mla"));
9135 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9136 inst
.instruction
|= inst
.operands
[1].reg
;
9137 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9138 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9144 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9145 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9147 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9148 encode_arm_shifter_operand (1);
9151 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9158 top
= (inst
.instruction
& 0x00400000) != 0;
9159 constraint (top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
,
9160 _(":lower16: not allowed in this instruction"));
9161 constraint (!top
&& inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
,
9162 _(":upper16: not allowed in this instruction"));
9163 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9164 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
9166 imm
= inst
.reloc
.exp
.X_add_number
;
9167 /* The value is in two pieces: 0:11, 16:19. */
9168 inst
.instruction
|= (imm
& 0x00000fff);
9169 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9174 do_vfp_nsyn_mrs (void)
9176 if (inst
.operands
[0].isvec
)
9178 if (inst
.operands
[1].reg
!= 1)
9179 first_error (_("operand 1 must be FPSCR"));
9180 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9181 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9182 do_vfp_nsyn_opcode ("fmstat");
9184 else if (inst
.operands
[1].isvec
)
9185 do_vfp_nsyn_opcode ("fmrx");
9193 do_vfp_nsyn_msr (void)
9195 if (inst
.operands
[0].isvec
)
9196 do_vfp_nsyn_opcode ("fmxr");
9206 unsigned Rt
= inst
.operands
[0].reg
;
9208 if (thumb_mode
&& Rt
== REG_SP
)
9210 inst
.error
= BAD_SP
;
9214 /* MVFR2 is only valid at ARMv8-A. */
9215 if (inst
.operands
[1].reg
== 5)
9216 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9219 /* APSR_ sets isvec. All other refs to PC are illegal. */
9220 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9222 inst
.error
= BAD_PC
;
9226 /* If we get through parsing the register name, we just insert the number
9227 generated into the instruction without further validation. */
9228 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9229 inst
.instruction
|= (Rt
<< 12);
9235 unsigned Rt
= inst
.operands
[1].reg
;
9238 reject_bad_reg (Rt
);
9239 else if (Rt
== REG_PC
)
9241 inst
.error
= BAD_PC
;
9245 /* MVFR2 is only valid for ARMv8-A. */
9246 if (inst
.operands
[0].reg
== 5)
9247 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9250 /* If we get through parsing the register name, we just insert the number
9251 generated into the instruction without further validation. */
9252 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
9253 inst
.instruction
|= (Rt
<< 12);
9261 if (do_vfp_nsyn_mrs () == SUCCESS
)
9264 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9265 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9267 if (inst
.operands
[1].isreg
)
9269 br
= inst
.operands
[1].reg
;
9270 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
9271 as_bad (_("bad register for mrs"));
9275 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
9276 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
9278 _("'APSR', 'CPSR' or 'SPSR' expected"));
9279 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
9282 inst
.instruction
|= br
;
9285 /* Two possible forms:
9286 "{C|S}PSR_<field>, Rm",
9287 "{C|S}PSR_f, #expression". */
9292 if (do_vfp_nsyn_msr () == SUCCESS
)
9295 inst
.instruction
|= inst
.operands
[0].imm
;
9296 if (inst
.operands
[1].isreg
)
9297 inst
.instruction
|= inst
.operands
[1].reg
;
9300 inst
.instruction
|= INST_IMMEDIATE
;
9301 inst
.reloc
.type
= BFD_RELOC_ARM_IMMEDIATE
;
9302 inst
.reloc
.pc_rel
= 0;
9309 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
9311 if (!inst
.operands
[2].present
)
9312 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
9313 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9314 inst
.instruction
|= inst
.operands
[1].reg
;
9315 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9317 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9318 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9319 as_tsktsk (_("Rd and Rm should be different in mul"));
9322 /* Long Multiply Parser
9323 UMULL RdLo, RdHi, Rm, Rs
9324 SMULL RdLo, RdHi, Rm, Rs
9325 UMLAL RdLo, RdHi, Rm, Rs
9326 SMLAL RdLo, RdHi, Rm, Rs. */
9331 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9332 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9333 inst
.instruction
|= inst
.operands
[2].reg
;
9334 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9336 /* rdhi and rdlo must be different. */
9337 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9338 as_tsktsk (_("rdhi and rdlo must be different"));
9340 /* rdhi, rdlo and rm must all be different before armv6. */
9341 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
9342 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
9343 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
9344 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
9350 if (inst
.operands
[0].present
9351 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
9353 /* Architectural NOP hints are CPSR sets with no bits selected. */
9354 inst
.instruction
&= 0xf0000000;
9355 inst
.instruction
|= 0x0320f000;
9356 if (inst
.operands
[0].present
)
9357 inst
.instruction
|= inst
.operands
[0].imm
;
9361 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
9362 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
9363 Condition defaults to COND_ALWAYS.
9364 Error if Rd, Rn or Rm are R15. */
9369 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9370 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9371 inst
.instruction
|= inst
.operands
[2].reg
;
9372 if (inst
.operands
[3].present
)
9373 encode_arm_shift (3);
9376 /* ARM V6 PKHTB (Argument Parse). */
9381 if (!inst
.operands
[3].present
)
9383 /* If the shift specifier is omitted, turn the instruction
9384 into pkhbt rd, rm, rn. */
9385 inst
.instruction
&= 0xfff00010;
9386 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9387 inst
.instruction
|= inst
.operands
[1].reg
;
9388 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9392 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9393 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9394 inst
.instruction
|= inst
.operands
[2].reg
;
9395 encode_arm_shift (3);
9399 /* ARMv5TE: Preload-Cache
9400 MP Extensions: Preload for write
9404 Syntactically, like LDR with B=1, W=0, L=1. */
9409 constraint (!inst
.operands
[0].isreg
,
9410 _("'[' expected after PLD mnemonic"));
9411 constraint (inst
.operands
[0].postind
,
9412 _("post-indexed expression used in preload instruction"));
9413 constraint (inst
.operands
[0].writeback
,
9414 _("writeback used in preload instruction"));
9415 constraint (!inst
.operands
[0].preind
,
9416 _("unindexed addressing used in preload instruction"));
9417 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9420 /* ARMv7: PLI <addr_mode> */
9424 constraint (!inst
.operands
[0].isreg
,
9425 _("'[' expected after PLI mnemonic"));
9426 constraint (inst
.operands
[0].postind
,
9427 _("post-indexed expression used in preload instruction"));
9428 constraint (inst
.operands
[0].writeback
,
9429 _("writeback used in preload instruction"));
9430 constraint (!inst
.operands
[0].preind
,
9431 _("unindexed addressing used in preload instruction"));
9432 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
9433 inst
.instruction
&= ~PRE_INDEX
;
9439 constraint (inst
.operands
[0].writeback
,
9440 _("push/pop do not support {reglist}^"));
9441 inst
.operands
[1] = inst
.operands
[0];
9442 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
9443 inst
.operands
[0].isreg
= 1;
9444 inst
.operands
[0].writeback
= 1;
9445 inst
.operands
[0].reg
= REG_SP
;
9446 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
9449 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
9450 word at the specified address and the following word
9452 Unconditionally executed.
9453 Error if Rn is R15. */
9458 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9459 if (inst
.operands
[0].writeback
)
9460 inst
.instruction
|= WRITE_BACK
;
9463 /* ARM V6 ssat (argument parse). */
9468 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9469 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
9470 inst
.instruction
|= inst
.operands
[2].reg
;
9472 if (inst
.operands
[3].present
)
9473 encode_arm_shift (3);
9476 /* ARM V6 usat (argument parse). */
9481 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9482 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9483 inst
.instruction
|= inst
.operands
[2].reg
;
9485 if (inst
.operands
[3].present
)
9486 encode_arm_shift (3);
9489 /* ARM V6 ssat16 (argument parse). */
9494 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9495 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
9496 inst
.instruction
|= inst
.operands
[2].reg
;
9502 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9503 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
9504 inst
.instruction
|= inst
.operands
[2].reg
;
9507 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
9508 preserving the other bits.
9510 setend <endian_specifier>, where <endian_specifier> is either
9516 if (warn_on_deprecated
9517 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9518 as_tsktsk (_("setend use is deprecated for ARMv8"));
9520 if (inst
.operands
[0].imm
)
9521 inst
.instruction
|= 0x200;
9527 unsigned int Rm
= (inst
.operands
[1].present
9528 ? inst
.operands
[1].reg
9529 : inst
.operands
[0].reg
);
9531 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9532 inst
.instruction
|= Rm
;
9533 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
9535 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9536 inst
.instruction
|= SHIFT_BY_REG
;
9537 /* PR 12854: Error on extraneous shifts. */
9538 constraint (inst
.operands
[2].shifted
,
9539 _("extraneous shift as part of operand to shift insn"));
9542 inst
.reloc
.type
= BFD_RELOC_ARM_SHIFT_IMM
;
9548 inst
.reloc
.type
= BFD_RELOC_ARM_SMC
;
9549 inst
.reloc
.pc_rel
= 0;
9555 inst
.reloc
.type
= BFD_RELOC_ARM_HVC
;
9556 inst
.reloc
.pc_rel
= 0;
9562 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
9563 inst
.reloc
.pc_rel
= 0;
9569 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9570 _("selected processor does not support SETPAN instruction"));
9572 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
9578 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
9579 _("selected processor does not support SETPAN instruction"));
9581 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
9584 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
9585 SMLAxy{cond} Rd,Rm,Rs,Rn
9586 SMLAWy{cond} Rd,Rm,Rs,Rn
9587 Error if any register is R15. */
9592 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9593 inst
.instruction
|= inst
.operands
[1].reg
;
9594 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9595 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9598 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
9599 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
9600 Error if any register is R15.
9601 Warning if Rdlo == Rdhi. */
9606 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9607 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9608 inst
.instruction
|= inst
.operands
[2].reg
;
9609 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
9611 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
9612 as_tsktsk (_("rdhi and rdlo must be different"));
9615 /* ARM V5E (El Segundo) signed-multiply (argument parse)
9616 SMULxy{cond} Rd,Rm,Rs
9617 Error if any register is R15. */
9622 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9623 inst
.instruction
|= inst
.operands
[1].reg
;
9624 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9627 /* ARM V6 srs (argument parse). The variable fields in the encoding are
9628 the same for both ARM and Thumb-2. */
9635 if (inst
.operands
[0].present
)
9637 reg
= inst
.operands
[0].reg
;
9638 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
9643 inst
.instruction
|= reg
<< 16;
9644 inst
.instruction
|= inst
.operands
[1].imm
;
9645 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
9646 inst
.instruction
|= WRITE_BACK
;
9649 /* ARM V6 strex (argument parse). */
9654 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9655 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9656 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9657 || inst
.operands
[2].negative
9658 /* See comment in do_ldrex(). */
9659 || (inst
.operands
[2].reg
== REG_PC
),
9662 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9663 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9665 constraint (inst
.reloc
.exp
.X_op
!= O_constant
9666 || inst
.reloc
.exp
.X_add_number
!= 0,
9667 _("offset must be zero in ARM encoding"));
9669 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9670 inst
.instruction
|= inst
.operands
[1].reg
;
9671 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9672 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
9678 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
9679 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
9680 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
9681 || inst
.operands
[2].negative
,
9684 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9685 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9693 constraint (inst
.operands
[1].reg
% 2 != 0,
9694 _("even register required"));
9695 constraint (inst
.operands
[2].present
9696 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
9697 _("can only store two consecutive registers"));
9698 /* If op 2 were present and equal to PC, this function wouldn't
9699 have been called in the first place. */
9700 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
9702 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9703 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
9704 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
9707 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9708 inst
.instruction
|= inst
.operands
[1].reg
;
9709 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9716 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9717 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9725 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
9726 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
9731 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
9732 extends it to 32-bits, and adds the result to a value in another
9733 register. You can specify a rotation by 0, 8, 16, or 24 bits
9734 before extracting the 16-bit value.
9735 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
9736 Condition defaults to COND_ALWAYS.
9737 Error if any register uses R15. */
9742 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9743 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9744 inst
.instruction
|= inst
.operands
[2].reg
;
9745 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
9750 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
9751 Condition defaults to COND_ALWAYS.
9752 Error if any register uses R15. */
9757 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9758 inst
.instruction
|= inst
.operands
[1].reg
;
9759 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
9762 /* VFP instructions. In a logical order: SP variant first, monad
9763 before dyad, arithmetic then move then load/store. */
9766 do_vfp_sp_monadic (void)
9768 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9769 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9773 do_vfp_sp_dyadic (void)
9775 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9776 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9777 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9781 do_vfp_sp_compare_z (void)
9783 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9787 do_vfp_dp_sp_cvt (void)
9789 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9790 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
9794 do_vfp_sp_dp_cvt (void)
9796 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9797 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9801 do_vfp_reg_from_sp (void)
9803 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9804 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
9808 do_vfp_reg2_from_sp2 (void)
9810 constraint (inst
.operands
[2].imm
!= 2,
9811 _("only two consecutive VFP SP registers allowed here"));
9812 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9813 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9814 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
9818 do_vfp_sp_from_reg (void)
9820 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
9821 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9825 do_vfp_sp2_from_reg2 (void)
9827 constraint (inst
.operands
[0].imm
!= 2,
9828 _("only two consecutive VFP SP registers allowed here"));
9829 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
9830 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9831 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9835 do_vfp_sp_ldst (void)
9837 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9838 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9842 do_vfp_dp_ldst (void)
9844 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9845 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
9850 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
9852 if (inst
.operands
[0].writeback
)
9853 inst
.instruction
|= WRITE_BACK
;
9855 constraint (ldstm_type
!= VFP_LDSTMIA
,
9856 _("this addressing mode requires base-register writeback"));
9857 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9858 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
9859 inst
.instruction
|= inst
.operands
[1].imm
;
9863 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
9867 if (inst
.operands
[0].writeback
)
9868 inst
.instruction
|= WRITE_BACK
;
9870 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
9871 _("this addressing mode requires base-register writeback"));
9873 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9874 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9876 count
= inst
.operands
[1].imm
<< 1;
9877 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
9880 inst
.instruction
|= count
;
9884 do_vfp_sp_ldstmia (void)
9886 vfp_sp_ldstm (VFP_LDSTMIA
);
9890 do_vfp_sp_ldstmdb (void)
9892 vfp_sp_ldstm (VFP_LDSTMDB
);
9896 do_vfp_dp_ldstmia (void)
9898 vfp_dp_ldstm (VFP_LDSTMIA
);
9902 do_vfp_dp_ldstmdb (void)
9904 vfp_dp_ldstm (VFP_LDSTMDB
);
9908 do_vfp_xp_ldstmia (void)
9910 vfp_dp_ldstm (VFP_LDSTMIAX
);
9914 do_vfp_xp_ldstmdb (void)
9916 vfp_dp_ldstm (VFP_LDSTMDBX
);
9920 do_vfp_dp_rd_rm (void)
9922 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9923 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
9927 do_vfp_dp_rn_rd (void)
9929 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
9930 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9934 do_vfp_dp_rd_rn (void)
9936 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9937 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9941 do_vfp_dp_rd_rn_rm (void)
9943 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9944 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
9945 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
9951 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9955 do_vfp_dp_rm_rd_rn (void)
9957 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
9958 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
9959 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
9962 /* VFPv3 instructions. */
9964 do_vfp_sp_const (void)
9966 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
9967 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9968 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9972 do_vfp_dp_const (void)
9974 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
9975 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
9976 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
9980 vfp_conv (int srcsize
)
9982 int immbits
= srcsize
- inst
.operands
[1].imm
;
9984 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
9986 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
9987 i.e. immbits must be in range 0 - 16. */
9988 inst
.error
= _("immediate value out of range, expected range [0, 16]");
9991 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
9993 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
9994 i.e. immbits must be in range 0 - 31. */
9995 inst
.error
= _("immediate value out of range, expected range [1, 32]");
9999 inst
.instruction
|= (immbits
& 1) << 5;
10000 inst
.instruction
|= (immbits
>> 1);
10004 do_vfp_sp_conv_16 (void)
10006 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10011 do_vfp_dp_conv_16 (void)
10013 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10018 do_vfp_sp_conv_32 (void)
10020 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10025 do_vfp_dp_conv_32 (void)
10027 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10031 /* FPA instructions. Also in a logical order. */
10036 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10037 inst
.instruction
|= inst
.operands
[1].reg
;
10041 do_fpa_ldmstm (void)
10043 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10044 switch (inst
.operands
[1].imm
)
10046 case 1: inst
.instruction
|= CP_T_X
; break;
10047 case 2: inst
.instruction
|= CP_T_Y
; break;
10048 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10053 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10055 /* The instruction specified "ea" or "fd", so we can only accept
10056 [Rn]{!}. The instruction does not really support stacking or
10057 unstacking, so we have to emulate these by setting appropriate
10058 bits and offsets. */
10059 constraint (inst
.reloc
.exp
.X_op
!= O_constant
10060 || inst
.reloc
.exp
.X_add_number
!= 0,
10061 _("this instruction does not support indexing"));
10063 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10064 inst
.reloc
.exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10066 if (!(inst
.instruction
& INDEX_UP
))
10067 inst
.reloc
.exp
.X_add_number
= -inst
.reloc
.exp
.X_add_number
;
10069 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10071 inst
.operands
[2].preind
= 0;
10072 inst
.operands
[2].postind
= 1;
10076 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10079 /* iWMMXt instructions: strictly in alphabetical order. */
10082 do_iwmmxt_tandorc (void)
10084 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10088 do_iwmmxt_textrc (void)
10090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10091 inst
.instruction
|= inst
.operands
[1].imm
;
10095 do_iwmmxt_textrm (void)
10097 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10098 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10099 inst
.instruction
|= inst
.operands
[2].imm
;
10103 do_iwmmxt_tinsr (void)
10105 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10106 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10107 inst
.instruction
|= inst
.operands
[2].imm
;
10111 do_iwmmxt_tmia (void)
10113 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10114 inst
.instruction
|= inst
.operands
[1].reg
;
10115 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10119 do_iwmmxt_waligni (void)
10121 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10122 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10123 inst
.instruction
|= inst
.operands
[2].reg
;
10124 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10128 do_iwmmxt_wmerge (void)
10130 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10131 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10132 inst
.instruction
|= inst
.operands
[2].reg
;
10133 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10137 do_iwmmxt_wmov (void)
10139 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10140 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10141 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10142 inst
.instruction
|= inst
.operands
[1].reg
;
10146 do_iwmmxt_wldstbh (void)
10149 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10151 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10153 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10154 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10158 do_iwmmxt_wldstw (void)
10160 /* RIWR_RIWC clears .isreg for a control register. */
10161 if (!inst
.operands
[0].isreg
)
10163 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10164 inst
.instruction
|= 0xf0000000;
10167 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10168 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10172 do_iwmmxt_wldstd (void)
10174 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10175 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10176 && inst
.operands
[1].immisreg
)
10178 inst
.instruction
&= ~0x1a000ff;
10179 inst
.instruction
|= (0xfU
<< 28);
10180 if (inst
.operands
[1].preind
)
10181 inst
.instruction
|= PRE_INDEX
;
10182 if (!inst
.operands
[1].negative
)
10183 inst
.instruction
|= INDEX_UP
;
10184 if (inst
.operands
[1].writeback
)
10185 inst
.instruction
|= WRITE_BACK
;
10186 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10187 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10188 inst
.instruction
|= inst
.operands
[1].imm
;
10191 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10195 do_iwmmxt_wshufh (void)
10197 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10198 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10199 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10200 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
10204 do_iwmmxt_wzero (void)
10206 /* WZERO reg is an alias for WANDN reg, reg, reg. */
10207 inst
.instruction
|= inst
.operands
[0].reg
;
10208 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10209 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10213 do_iwmmxt_wrwrwr_or_imm5 (void)
10215 if (inst
.operands
[2].isreg
)
10218 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
10219 _("immediate operand requires iWMMXt2"));
10221 if (inst
.operands
[2].imm
== 0)
10223 switch ((inst
.instruction
>> 20) & 0xf)
10229 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
10230 inst
.operands
[2].imm
= 16;
10231 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
10237 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
10238 inst
.operands
[2].imm
= 32;
10239 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
10246 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
10248 wrn
= (inst
.instruction
>> 16) & 0xf;
10249 inst
.instruction
&= 0xff0fff0f;
10250 inst
.instruction
|= wrn
;
10251 /* Bail out here; the instruction is now assembled. */
10256 /* Map 32 -> 0, etc. */
10257 inst
.operands
[2].imm
&= 0x1f;
10258 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
10262 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
10263 operations first, then control, shift, and load/store. */
10265 /* Insns like "foo X,Y,Z". */
10268 do_mav_triple (void)
10270 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10271 inst
.instruction
|= inst
.operands
[1].reg
;
10272 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10275 /* Insns like "foo W,X,Y,Z".
10276 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
10281 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10282 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10283 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10284 inst
.instruction
|= inst
.operands
[3].reg
;
10287 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
10289 do_mav_dspsc (void)
10291 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10294 /* Maverick shift immediate instructions.
10295 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
10296 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
10299 do_mav_shift (void)
10301 int imm
= inst
.operands
[2].imm
;
10303 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10304 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10306 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
10307 Bits 5-7 of the insn should have bits 4-6 of the immediate.
10308 Bit 4 should be 0. */
10309 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
10311 inst
.instruction
|= imm
;
10314 /* XScale instructions. Also sorted arithmetic before move. */
10316 /* Xscale multiply-accumulate (argument parse)
10319 MIAxycc acc0,Rm,Rs. */
10324 inst
.instruction
|= inst
.operands
[1].reg
;
10325 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10328 /* Xscale move-accumulator-register (argument parse)
10330 MARcc acc0,RdLo,RdHi. */
10335 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10336 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10339 /* Xscale move-register-accumulator (argument parse)
10341 MRAcc RdLo,RdHi,acc0. */
10346 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
10347 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10348 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10351 /* Encoding functions relevant only to Thumb. */
10353 /* inst.operands[i] is a shifted-register operand; encode
10354 it into inst.instruction in the format used by Thumb32. */
10357 encode_thumb32_shifted_operand (int i
)
10359 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10360 unsigned int shift
= inst
.operands
[i
].shift_kind
;
10362 constraint (inst
.operands
[i
].immisreg
,
10363 _("shift by register not allowed in thumb mode"));
10364 inst
.instruction
|= inst
.operands
[i
].reg
;
10365 if (shift
== SHIFT_RRX
)
10366 inst
.instruction
|= SHIFT_ROR
<< 4;
10369 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10370 _("expression too complex"));
10372 constraint (value
> 32
10373 || (value
== 32 && (shift
== SHIFT_LSL
10374 || shift
== SHIFT_ROR
)),
10375 _("shift expression is too large"));
10379 else if (value
== 32)
10382 inst
.instruction
|= shift
<< 4;
10383 inst
.instruction
|= (value
& 0x1c) << 10;
10384 inst
.instruction
|= (value
& 0x03) << 6;
10389 /* inst.operands[i] was set up by parse_address. Encode it into a
10390 Thumb32 format load or store instruction. Reject forms that cannot
10391 be used with such instructions. If is_t is true, reject forms that
10392 cannot be used with a T instruction; if is_d is true, reject forms
10393 that cannot be used with a D instruction. If it is a store insn,
10394 reject PC in Rn. */
10397 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
10399 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
10401 constraint (!inst
.operands
[i
].isreg
,
10402 _("Instruction does not support =N addresses"));
10404 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
10405 if (inst
.operands
[i
].immisreg
)
10407 constraint (is_pc
, BAD_PC_ADDRESSING
);
10408 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
10409 constraint (inst
.operands
[i
].negative
,
10410 _("Thumb does not support negative register indexing"));
10411 constraint (inst
.operands
[i
].postind
,
10412 _("Thumb does not support register post-indexing"));
10413 constraint (inst
.operands
[i
].writeback
,
10414 _("Thumb does not support register indexing with writeback"));
10415 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
10416 _("Thumb supports only LSL in shifted register indexing"));
10418 inst
.instruction
|= inst
.operands
[i
].imm
;
10419 if (inst
.operands
[i
].shifted
)
10421 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10422 _("expression too complex"));
10423 constraint (inst
.reloc
.exp
.X_add_number
< 0
10424 || inst
.reloc
.exp
.X_add_number
> 3,
10425 _("shift out of range"));
10426 inst
.instruction
|= inst
.reloc
.exp
.X_add_number
<< 4;
10428 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10430 else if (inst
.operands
[i
].preind
)
10432 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
10433 constraint (is_t
&& inst
.operands
[i
].writeback
,
10434 _("cannot use writeback with this instruction"));
10435 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
10436 BAD_PC_ADDRESSING
);
10440 inst
.instruction
|= 0x01000000;
10441 if (inst
.operands
[i
].writeback
)
10442 inst
.instruction
|= 0x00200000;
10446 inst
.instruction
|= 0x00000c00;
10447 if (inst
.operands
[i
].writeback
)
10448 inst
.instruction
|= 0x00000100;
10450 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10452 else if (inst
.operands
[i
].postind
)
10454 gas_assert (inst
.operands
[i
].writeback
);
10455 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
10456 constraint (is_t
, _("cannot use post-indexing with this instruction"));
10459 inst
.instruction
|= 0x00200000;
10461 inst
.instruction
|= 0x00000900;
10462 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
10464 else /* unindexed - only for coprocessor */
10465 inst
.error
= _("instruction does not accept unindexed addressing");
10468 /* Table of Thumb instructions which exist in both 16- and 32-bit
10469 encodings (the latter only in post-V6T2 cores). The index is the
10470 value used in the insns table below. When there is more than one
10471 possible 16-bit encoding for the instruction, this table always
10473 Also contains several pseudo-instructions used during relaxation. */
10474 #define T16_32_TAB \
10475 X(_adc, 4140, eb400000), \
10476 X(_adcs, 4140, eb500000), \
10477 X(_add, 1c00, eb000000), \
10478 X(_adds, 1c00, eb100000), \
10479 X(_addi, 0000, f1000000), \
10480 X(_addis, 0000, f1100000), \
10481 X(_add_pc,000f, f20f0000), \
10482 X(_add_sp,000d, f10d0000), \
10483 X(_adr, 000f, f20f0000), \
10484 X(_and, 4000, ea000000), \
10485 X(_ands, 4000, ea100000), \
10486 X(_asr, 1000, fa40f000), \
10487 X(_asrs, 1000, fa50f000), \
10488 X(_b, e000, f000b000), \
10489 X(_bcond, d000, f0008000), \
10490 X(_bic, 4380, ea200000), \
10491 X(_bics, 4380, ea300000), \
10492 X(_cmn, 42c0, eb100f00), \
10493 X(_cmp, 2800, ebb00f00), \
10494 X(_cpsie, b660, f3af8400), \
10495 X(_cpsid, b670, f3af8600), \
10496 X(_cpy, 4600, ea4f0000), \
10497 X(_dec_sp,80dd, f1ad0d00), \
10498 X(_eor, 4040, ea800000), \
10499 X(_eors, 4040, ea900000), \
10500 X(_inc_sp,00dd, f10d0d00), \
10501 X(_ldmia, c800, e8900000), \
10502 X(_ldr, 6800, f8500000), \
10503 X(_ldrb, 7800, f8100000), \
10504 X(_ldrh, 8800, f8300000), \
10505 X(_ldrsb, 5600, f9100000), \
10506 X(_ldrsh, 5e00, f9300000), \
10507 X(_ldr_pc,4800, f85f0000), \
10508 X(_ldr_pc2,4800, f85f0000), \
10509 X(_ldr_sp,9800, f85d0000), \
10510 X(_lsl, 0000, fa00f000), \
10511 X(_lsls, 0000, fa10f000), \
10512 X(_lsr, 0800, fa20f000), \
10513 X(_lsrs, 0800, fa30f000), \
10514 X(_mov, 2000, ea4f0000), \
10515 X(_movs, 2000, ea5f0000), \
10516 X(_mul, 4340, fb00f000), \
10517 X(_muls, 4340, ffffffff), /* no 32b muls */ \
10518 X(_mvn, 43c0, ea6f0000), \
10519 X(_mvns, 43c0, ea7f0000), \
10520 X(_neg, 4240, f1c00000), /* rsb #0 */ \
10521 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
10522 X(_orr, 4300, ea400000), \
10523 X(_orrs, 4300, ea500000), \
10524 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
10525 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
10526 X(_rev, ba00, fa90f080), \
10527 X(_rev16, ba40, fa90f090), \
10528 X(_revsh, bac0, fa90f0b0), \
10529 X(_ror, 41c0, fa60f000), \
10530 X(_rors, 41c0, fa70f000), \
10531 X(_sbc, 4180, eb600000), \
10532 X(_sbcs, 4180, eb700000), \
10533 X(_stmia, c000, e8800000), \
10534 X(_str, 6000, f8400000), \
10535 X(_strb, 7000, f8000000), \
10536 X(_strh, 8000, f8200000), \
10537 X(_str_sp,9000, f84d0000), \
10538 X(_sub, 1e00, eba00000), \
10539 X(_subs, 1e00, ebb00000), \
10540 X(_subi, 8000, f1a00000), \
10541 X(_subis, 8000, f1b00000), \
10542 X(_sxtb, b240, fa4ff080), \
10543 X(_sxth, b200, fa0ff080), \
10544 X(_tst, 4200, ea100f00), \
10545 X(_uxtb, b2c0, fa5ff080), \
10546 X(_uxth, b280, fa1ff080), \
10547 X(_nop, bf00, f3af8000), \
10548 X(_yield, bf10, f3af8001), \
10549 X(_wfe, bf20, f3af8002), \
10550 X(_wfi, bf30, f3af8003), \
10551 X(_sev, bf40, f3af8004), \
10552 X(_sevl, bf50, f3af8005), \
10553 X(_udf, de00, f7f0a000)
10555 /* To catch errors in encoding functions, the codes are all offset by
10556 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
10557 as 16-bit instructions. */
10558 #define X(a,b,c) T_MNEM##a
10559 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
10562 #define X(a,b,c) 0x##b
10563 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
10564 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
10567 #define X(a,b,c) 0x##c
10568 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
10569 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
10570 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
10574 /* Thumb instruction encoders, in alphabetical order. */
10576 /* ADDW or SUBW. */
10579 do_t_add_sub_w (void)
10583 Rd
= inst
.operands
[0].reg
;
10584 Rn
= inst
.operands
[1].reg
;
10586 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
10587 is the SP-{plus,minus}-immediate form of the instruction. */
10589 constraint (Rd
== REG_PC
, BAD_PC
);
10591 reject_bad_reg (Rd
);
10593 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
10594 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10597 /* Parse an add or subtract instruction. We get here with inst.instruction
10598 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
10601 do_t_add_sub (void)
10605 Rd
= inst
.operands
[0].reg
;
10606 Rs
= (inst
.operands
[1].present
10607 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10608 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10611 set_it_insn_type_last ();
10613 if (unified_syntax
)
10616 bfd_boolean narrow
;
10619 flags
= (inst
.instruction
== T_MNEM_adds
10620 || inst
.instruction
== T_MNEM_subs
);
10622 narrow
= !in_it_block ();
10624 narrow
= in_it_block ();
10625 if (!inst
.operands
[2].isreg
)
10629 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10630 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10632 add
= (inst
.instruction
== T_MNEM_add
10633 || inst
.instruction
== T_MNEM_adds
);
10635 if (inst
.size_req
!= 4)
10637 /* Attempt to use a narrow opcode, with relaxation if
10639 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
10640 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
10641 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
10642 opcode
= T_MNEM_add_sp
;
10643 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
10644 opcode
= T_MNEM_add_pc
;
10645 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
10648 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
10650 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
10654 inst
.instruction
= THUMB_OP16(opcode
);
10655 inst
.instruction
|= (Rd
<< 4) | Rs
;
10656 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10657 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
10659 if (inst
.size_req
== 2)
10660 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10662 inst
.relax
= opcode
;
10666 constraint (inst
.size_req
== 2, BAD_HIREG
);
10668 if (inst
.size_req
== 4
10669 || (inst
.size_req
!= 2 && !opcode
))
10671 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
10672 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
10673 THUMB1_RELOC_ONLY
);
10676 constraint (add
, BAD_PC
);
10677 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
10678 _("only SUBS PC, LR, #const allowed"));
10679 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
10680 _("expression too complex"));
10681 constraint (inst
.reloc
.exp
.X_add_number
< 0
10682 || inst
.reloc
.exp
.X_add_number
> 0xff,
10683 _("immediate value out of range"));
10684 inst
.instruction
= T2_SUBS_PC_LR
10685 | inst
.reloc
.exp
.X_add_number
;
10686 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
10689 else if (Rs
== REG_PC
)
10691 /* Always use addw/subw. */
10692 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
10693 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMM12
;
10697 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10698 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
10701 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10703 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_IMM
;
10705 inst
.instruction
|= Rd
<< 8;
10706 inst
.instruction
|= Rs
<< 16;
10711 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
10712 unsigned int shift
= inst
.operands
[2].shift_kind
;
10714 Rn
= inst
.operands
[2].reg
;
10715 /* See if we can do this with a 16-bit instruction. */
10716 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
10718 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10723 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
10724 || inst
.instruction
== T_MNEM_add
)
10726 : T_OPCODE_SUB_R3
);
10727 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10731 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
10733 /* Thumb-1 cores (except v6-M) require at least one high
10734 register in a narrow non flag setting add. */
10735 if (Rd
> 7 || Rn
> 7
10736 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
10737 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
10744 inst
.instruction
= T_OPCODE_ADD_HI
;
10745 inst
.instruction
|= (Rd
& 8) << 4;
10746 inst
.instruction
|= (Rd
& 7);
10747 inst
.instruction
|= Rn
<< 3;
10753 constraint (Rd
== REG_PC
, BAD_PC
);
10754 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10755 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
10756 constraint (Rs
== REG_PC
, BAD_PC
);
10757 reject_bad_reg (Rn
);
10759 /* If we get here, it can't be done in 16 bits. */
10760 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
10761 _("shift must be constant"));
10762 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10763 inst
.instruction
|= Rd
<< 8;
10764 inst
.instruction
|= Rs
<< 16;
10765 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
10766 _("shift value over 3 not allowed in thumb mode"));
10767 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
10768 _("only LSL shift allowed in thumb mode"));
10769 encode_thumb32_shifted_operand (2);
10774 constraint (inst
.instruction
== T_MNEM_adds
10775 || inst
.instruction
== T_MNEM_subs
,
10778 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
10780 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
10781 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
10784 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10785 ? 0x0000 : 0x8000);
10786 inst
.instruction
|= (Rd
<< 4) | Rs
;
10787 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10791 Rn
= inst
.operands
[2].reg
;
10792 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
10794 /* We now have Rd, Rs, and Rn set to registers. */
10795 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
10797 /* Can't do this for SUB. */
10798 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
10799 inst
.instruction
= T_OPCODE_ADD_HI
;
10800 inst
.instruction
|= (Rd
& 8) << 4;
10801 inst
.instruction
|= (Rd
& 7);
10803 inst
.instruction
|= Rn
<< 3;
10805 inst
.instruction
|= Rs
<< 3;
10807 constraint (1, _("dest must overlap one source register"));
10811 inst
.instruction
= (inst
.instruction
== T_MNEM_add
10812 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
10813 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
10823 Rd
= inst
.operands
[0].reg
;
10824 reject_bad_reg (Rd
);
10826 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
10828 /* Defer to section relaxation. */
10829 inst
.relax
= inst
.instruction
;
10830 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10831 inst
.instruction
|= Rd
<< 4;
10833 else if (unified_syntax
&& inst
.size_req
!= 2)
10835 /* Generate a 32-bit opcode. */
10836 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10837 inst
.instruction
|= Rd
<< 8;
10838 inst
.reloc
.type
= BFD_RELOC_ARM_T32_ADD_PC12
;
10839 inst
.reloc
.pc_rel
= 1;
10843 /* Generate a 16-bit opcode. */
10844 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10845 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_ADD
;
10846 inst
.reloc
.exp
.X_add_number
-= 4; /* PC relative adjust. */
10847 inst
.reloc
.pc_rel
= 1;
10848 inst
.instruction
|= Rd
<< 4;
10851 if (inst
.reloc
.exp
.X_op
== O_symbol
10852 && inst
.reloc
.exp
.X_add_symbol
!= NULL
10853 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
10854 && THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
10855 inst
.reloc
.exp
.X_add_number
+= 1;
10858 /* Arithmetic instructions for which there is just one 16-bit
10859 instruction encoding, and it allows only two low registers.
10860 For maximal compatibility with ARM syntax, we allow three register
10861 operands even when Thumb-32 instructions are not available, as long
10862 as the first two are identical. For instance, both "sbc r0,r1" and
10863 "sbc r0,r0,r1" are allowed. */
10869 Rd
= inst
.operands
[0].reg
;
10870 Rs
= (inst
.operands
[1].present
10871 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10872 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10873 Rn
= inst
.operands
[2].reg
;
10875 reject_bad_reg (Rd
);
10876 reject_bad_reg (Rs
);
10877 if (inst
.operands
[2].isreg
)
10878 reject_bad_reg (Rn
);
10880 if (unified_syntax
)
10882 if (!inst
.operands
[2].isreg
)
10884 /* For an immediate, we always generate a 32-bit opcode;
10885 section relaxation will shrink it later if possible. */
10886 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10887 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10888 inst
.instruction
|= Rd
<< 8;
10889 inst
.instruction
|= Rs
<< 16;
10890 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10894 bfd_boolean narrow
;
10896 /* See if we can do this with a 16-bit instruction. */
10897 if (THUMB_SETS_FLAGS (inst
.instruction
))
10898 narrow
= !in_it_block ();
10900 narrow
= in_it_block ();
10902 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10904 if (inst
.operands
[2].shifted
)
10906 if (inst
.size_req
== 4)
10912 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10913 inst
.instruction
|= Rd
;
10914 inst
.instruction
|= Rn
<< 3;
10918 /* If we get here, it can't be done in 16 bits. */
10919 constraint (inst
.operands
[2].shifted
10920 && inst
.operands
[2].immisreg
,
10921 _("shift must be constant"));
10922 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10923 inst
.instruction
|= Rd
<< 8;
10924 inst
.instruction
|= Rs
<< 16;
10925 encode_thumb32_shifted_operand (2);
10930 /* On its face this is a lie - the instruction does set the
10931 flags. However, the only supported mnemonic in this mode
10932 says it doesn't. */
10933 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
10935 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
10936 _("unshifted register required"));
10937 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
10938 constraint (Rd
!= Rs
,
10939 _("dest and source1 must be the same register"));
10941 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
10942 inst
.instruction
|= Rd
;
10943 inst
.instruction
|= Rn
<< 3;
10947 /* Similarly, but for instructions where the arithmetic operation is
10948 commutative, so we can allow either of them to be different from
10949 the destination operand in a 16-bit instruction. For instance, all
10950 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
10957 Rd
= inst
.operands
[0].reg
;
10958 Rs
= (inst
.operands
[1].present
10959 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
10960 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
10961 Rn
= inst
.operands
[2].reg
;
10963 reject_bad_reg (Rd
);
10964 reject_bad_reg (Rs
);
10965 if (inst
.operands
[2].isreg
)
10966 reject_bad_reg (Rn
);
10968 if (unified_syntax
)
10970 if (!inst
.operands
[2].isreg
)
10972 /* For an immediate, we always generate a 32-bit opcode;
10973 section relaxation will shrink it later if possible. */
10974 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
10975 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
10976 inst
.instruction
|= Rd
<< 8;
10977 inst
.instruction
|= Rs
<< 16;
10978 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
10982 bfd_boolean narrow
;
10984 /* See if we can do this with a 16-bit instruction. */
10985 if (THUMB_SETS_FLAGS (inst
.instruction
))
10986 narrow
= !in_it_block ();
10988 narrow
= in_it_block ();
10990 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
10992 if (inst
.operands
[2].shifted
)
10994 if (inst
.size_req
== 4)
11001 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11002 inst
.instruction
|= Rd
;
11003 inst
.instruction
|= Rn
<< 3;
11008 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11009 inst
.instruction
|= Rd
;
11010 inst
.instruction
|= Rs
<< 3;
11015 /* If we get here, it can't be done in 16 bits. */
11016 constraint (inst
.operands
[2].shifted
11017 && inst
.operands
[2].immisreg
,
11018 _("shift must be constant"));
11019 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11020 inst
.instruction
|= Rd
<< 8;
11021 inst
.instruction
|= Rs
<< 16;
11022 encode_thumb32_shifted_operand (2);
11027 /* On its face this is a lie - the instruction does set the
11028 flags. However, the only supported mnemonic in this mode
11029 says it doesn't. */
11030 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11032 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11033 _("unshifted register required"));
11034 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11036 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11037 inst
.instruction
|= Rd
;
11040 inst
.instruction
|= Rn
<< 3;
11042 inst
.instruction
|= Rs
<< 3;
11044 constraint (1, _("dest must overlap one source register"));
11052 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11053 constraint (msb
> 32, _("bit-field extends past end of register"));
11054 /* The instruction encoding stores the LSB and MSB,
11055 not the LSB and width. */
11056 Rd
= inst
.operands
[0].reg
;
11057 reject_bad_reg (Rd
);
11058 inst
.instruction
|= Rd
<< 8;
11059 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11060 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11061 inst
.instruction
|= msb
- 1;
11070 Rd
= inst
.operands
[0].reg
;
11071 reject_bad_reg (Rd
);
11073 /* #0 in second position is alternative syntax for bfc, which is
11074 the same instruction but with REG_PC in the Rm field. */
11075 if (!inst
.operands
[1].isreg
)
11079 Rn
= inst
.operands
[1].reg
;
11080 reject_bad_reg (Rn
);
11083 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11084 constraint (msb
> 32, _("bit-field extends past end of register"));
11085 /* The instruction encoding stores the LSB and MSB,
11086 not the LSB and width. */
11087 inst
.instruction
|= Rd
<< 8;
11088 inst
.instruction
|= Rn
<< 16;
11089 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11090 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11091 inst
.instruction
|= msb
- 1;
11099 Rd
= inst
.operands
[0].reg
;
11100 Rn
= inst
.operands
[1].reg
;
11102 reject_bad_reg (Rd
);
11103 reject_bad_reg (Rn
);
11105 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11106 _("bit-field extends past end of register"));
11107 inst
.instruction
|= Rd
<< 8;
11108 inst
.instruction
|= Rn
<< 16;
11109 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11110 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11111 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11114 /* ARM V5 Thumb BLX (argument parse)
11115 BLX <target_addr> which is BLX(1)
11116 BLX <Rm> which is BLX(2)
11117 Unfortunately, there are two different opcodes for this mnemonic.
11118 So, the insns[].value is not used, and the code here zaps values
11119 into inst.instruction.
11121 ??? How to take advantage of the additional two bits of displacement
11122 available in Thumb32 mode? Need new relocation? */
11127 set_it_insn_type_last ();
11129 if (inst
.operands
[0].isreg
)
11131 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11132 /* We have a register, so this is BLX(2). */
11133 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11137 /* No register. This must be BLX(1). */
11138 inst
.instruction
= 0xf000e800;
11139 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11148 bfd_reloc_code_real_type reloc
;
11151 set_it_insn_type (IF_INSIDE_IT_LAST_INSN
);
11153 if (in_it_block ())
11155 /* Conditional branches inside IT blocks are encoded as unconditional
11157 cond
= COND_ALWAYS
;
11162 if (cond
!= COND_ALWAYS
)
11163 opcode
= T_MNEM_bcond
;
11165 opcode
= inst
.instruction
;
11168 && (inst
.size_req
== 4
11169 || (inst
.size_req
!= 2
11170 && (inst
.operands
[0].hasreloc
11171 || inst
.reloc
.exp
.X_op
== O_constant
))))
11173 inst
.instruction
= THUMB_OP32(opcode
);
11174 if (cond
== COND_ALWAYS
)
11175 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11178 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11179 _("selected architecture does not support "
11180 "wide conditional branch instruction"));
11182 gas_assert (cond
!= 0xF);
11183 inst
.instruction
|= cond
<< 22;
11184 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
11189 inst
.instruction
= THUMB_OP16(opcode
);
11190 if (cond
== COND_ALWAYS
)
11191 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
11194 inst
.instruction
|= cond
<< 8;
11195 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
11197 /* Allow section relaxation. */
11198 if (unified_syntax
&& inst
.size_req
!= 2)
11199 inst
.relax
= opcode
;
11201 inst
.reloc
.type
= reloc
;
11202 inst
.reloc
.pc_rel
= 1;
11205 /* Actually do the work for Thumb state bkpt and hlt. The only difference
11206 between the two is the maximum immediate allowed - which is passed in
11209 do_t_bkpt_hlt1 (int range
)
11211 constraint (inst
.cond
!= COND_ALWAYS
,
11212 _("instruction is always unconditional"));
11213 if (inst
.operands
[0].present
)
11215 constraint (inst
.operands
[0].imm
> range
,
11216 _("immediate value out of range"));
11217 inst
.instruction
|= inst
.operands
[0].imm
;
11220 set_it_insn_type (NEUTRAL_IT_INSN
);
11226 do_t_bkpt_hlt1 (63);
11232 do_t_bkpt_hlt1 (255);
11236 do_t_branch23 (void)
11238 set_it_insn_type_last ();
11239 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
11241 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
11242 this file. We used to simply ignore the PLT reloc type here --
11243 the branch encoding is now needed to deal with TLSCALL relocs.
11244 So if we see a PLT reloc now, put it back to how it used to be to
11245 keep the preexisting behaviour. */
11246 if (inst
.reloc
.type
== BFD_RELOC_ARM_PLT32
)
11247 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
11249 #if defined(OBJ_COFF)
11250 /* If the destination of the branch is a defined symbol which does not have
11251 the THUMB_FUNC attribute, then we must be calling a function which has
11252 the (interfacearm) attribute. We look for the Thumb entry point to that
11253 function and change the branch to refer to that function instead. */
11254 if ( inst
.reloc
.exp
.X_op
== O_symbol
11255 && inst
.reloc
.exp
.X_add_symbol
!= NULL
11256 && S_IS_DEFINED (inst
.reloc
.exp
.X_add_symbol
)
11257 && ! THUMB_IS_FUNC (inst
.reloc
.exp
.X_add_symbol
))
11258 inst
.reloc
.exp
.X_add_symbol
=
11259 find_real_start (inst
.reloc
.exp
.X_add_symbol
);
11266 set_it_insn_type_last ();
11267 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11268 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
11269 should cause the alignment to be checked once it is known. This is
11270 because BX PC only works if the instruction is word aligned. */
11278 set_it_insn_type_last ();
11279 Rm
= inst
.operands
[0].reg
;
11280 reject_bad_reg (Rm
);
11281 inst
.instruction
|= Rm
<< 16;
11290 Rd
= inst
.operands
[0].reg
;
11291 Rm
= inst
.operands
[1].reg
;
11293 reject_bad_reg (Rd
);
11294 reject_bad_reg (Rm
);
11296 inst
.instruction
|= Rd
<< 8;
11297 inst
.instruction
|= Rm
<< 16;
11298 inst
.instruction
|= Rm
;
11304 set_it_insn_type (OUTSIDE_IT_INSN
);
11310 set_it_insn_type (OUTSIDE_IT_INSN
);
11311 inst
.instruction
|= inst
.operands
[0].imm
;
11317 set_it_insn_type (OUTSIDE_IT_INSN
);
11319 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
11320 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
11322 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
11323 inst
.instruction
= 0xf3af8000;
11324 inst
.instruction
|= imod
<< 9;
11325 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
11326 if (inst
.operands
[1].present
)
11327 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
11331 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
11332 && (inst
.operands
[0].imm
& 4),
11333 _("selected processor does not support 'A' form "
11334 "of this instruction"));
11335 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
11336 _("Thumb does not support the 2-argument "
11337 "form of this instruction"));
11338 inst
.instruction
|= inst
.operands
[0].imm
;
11342 /* THUMB CPY instruction (argument parse). */
11347 if (inst
.size_req
== 4)
11349 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
11350 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11351 inst
.instruction
|= inst
.operands
[1].reg
;
11355 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
11356 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
11357 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11364 set_it_insn_type (OUTSIDE_IT_INSN
);
11365 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11366 inst
.instruction
|= inst
.operands
[0].reg
;
11367 inst
.reloc
.pc_rel
= 1;
11368 inst
.reloc
.type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
11374 inst
.instruction
|= inst
.operands
[0].imm
;
11380 unsigned Rd
, Rn
, Rm
;
11382 Rd
= inst
.operands
[0].reg
;
11383 Rn
= (inst
.operands
[1].present
11384 ? inst
.operands
[1].reg
: Rd
);
11385 Rm
= inst
.operands
[2].reg
;
11387 reject_bad_reg (Rd
);
11388 reject_bad_reg (Rn
);
11389 reject_bad_reg (Rm
);
11391 inst
.instruction
|= Rd
<< 8;
11392 inst
.instruction
|= Rn
<< 16;
11393 inst
.instruction
|= Rm
;
11399 if (unified_syntax
&& inst
.size_req
== 4)
11400 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11402 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11408 unsigned int cond
= inst
.operands
[0].imm
;
11410 set_it_insn_type (IT_INSN
);
11411 now_it
.mask
= (inst
.instruction
& 0xf) | 0x10;
11413 now_it
.warn_deprecated
= FALSE
;
11415 /* If the condition is a negative condition, invert the mask. */
11416 if ((cond
& 0x1) == 0x0)
11418 unsigned int mask
= inst
.instruction
& 0x000f;
11420 if ((mask
& 0x7) == 0)
11422 /* No conversion needed. */
11423 now_it
.block_length
= 1;
11425 else if ((mask
& 0x3) == 0)
11428 now_it
.block_length
= 2;
11430 else if ((mask
& 0x1) == 0)
11433 now_it
.block_length
= 3;
11438 now_it
.block_length
= 4;
11441 inst
.instruction
&= 0xfff0;
11442 inst
.instruction
|= mask
;
11445 inst
.instruction
|= cond
<< 4;
11448 /* Helper function used for both push/pop and ldm/stm. */
11450 encode_thumb2_ldmstm (int base
, unsigned mask
, bfd_boolean writeback
)
11454 load
= (inst
.instruction
& (1 << 20)) != 0;
11456 if (mask
& (1 << 13))
11457 inst
.error
= _("SP not allowed in register list");
11459 if ((mask
& (1 << base
)) != 0
11461 inst
.error
= _("having the base register in the register list when "
11462 "using write back is UNPREDICTABLE");
11466 if (mask
& (1 << 15))
11468 if (mask
& (1 << 14))
11469 inst
.error
= _("LR and PC should not both be in register list");
11471 set_it_insn_type_last ();
11476 if (mask
& (1 << 15))
11477 inst
.error
= _("PC not allowed in register list");
11480 if ((mask
& (mask
- 1)) == 0)
11482 /* Single register transfers implemented as str/ldr. */
11485 if (inst
.instruction
& (1 << 23))
11486 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
11488 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
11492 if (inst
.instruction
& (1 << 23))
11493 inst
.instruction
= 0x00800000; /* ia -> [base] */
11495 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
11498 inst
.instruction
|= 0xf8400000;
11500 inst
.instruction
|= 0x00100000;
11502 mask
= ffs (mask
) - 1;
11505 else if (writeback
)
11506 inst
.instruction
|= WRITE_BACK
;
11508 inst
.instruction
|= mask
;
11509 inst
.instruction
|= base
<< 16;
11515 /* This really doesn't seem worth it. */
11516 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
11517 _("expression too complex"));
11518 constraint (inst
.operands
[1].writeback
,
11519 _("Thumb load/store multiple does not support {reglist}^"));
11521 if (unified_syntax
)
11523 bfd_boolean narrow
;
11527 /* See if we can use a 16-bit instruction. */
11528 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
11529 && inst
.size_req
!= 4
11530 && !(inst
.operands
[1].imm
& ~0xff))
11532 mask
= 1 << inst
.operands
[0].reg
;
11534 if (inst
.operands
[0].reg
<= 7)
11536 if (inst
.instruction
== T_MNEM_stmia
11537 ? inst
.operands
[0].writeback
11538 : (inst
.operands
[0].writeback
11539 == !(inst
.operands
[1].imm
& mask
)))
11541 if (inst
.instruction
== T_MNEM_stmia
11542 && (inst
.operands
[1].imm
& mask
)
11543 && (inst
.operands
[1].imm
& (mask
- 1)))
11544 as_warn (_("value stored for r%d is UNKNOWN"),
11545 inst
.operands
[0].reg
);
11547 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11548 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11549 inst
.instruction
|= inst
.operands
[1].imm
;
11552 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11554 /* This means 1 register in reg list one of 3 situations:
11555 1. Instruction is stmia, but without writeback.
11556 2. lmdia without writeback, but with Rn not in
11558 3. ldmia with writeback, but with Rn in reglist.
11559 Case 3 is UNPREDICTABLE behaviour, so we handle
11560 case 1 and 2 which can be converted into a 16-bit
11561 str or ldr. The SP cases are handled below. */
11562 unsigned long opcode
;
11563 /* First, record an error for Case 3. */
11564 if (inst
.operands
[1].imm
& mask
11565 && inst
.operands
[0].writeback
)
11567 _("having the base register in the register list when "
11568 "using write back is UNPREDICTABLE");
11570 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
11572 inst
.instruction
= THUMB_OP16 (opcode
);
11573 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11574 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
11578 else if (inst
.operands
[0] .reg
== REG_SP
)
11580 if (inst
.operands
[0].writeback
)
11583 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11584 ? T_MNEM_push
: T_MNEM_pop
);
11585 inst
.instruction
|= inst
.operands
[1].imm
;
11588 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
11591 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
11592 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
11593 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
11601 if (inst
.instruction
< 0xffff)
11602 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11604 encode_thumb2_ldmstm (inst
.operands
[0].reg
, inst
.operands
[1].imm
,
11605 inst
.operands
[0].writeback
);
11610 constraint (inst
.operands
[0].reg
> 7
11611 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
11612 constraint (inst
.instruction
!= T_MNEM_ldmia
11613 && inst
.instruction
!= T_MNEM_stmia
,
11614 _("Thumb-2 instruction only valid in unified syntax"));
11615 if (inst
.instruction
== T_MNEM_stmia
)
11617 if (!inst
.operands
[0].writeback
)
11618 as_warn (_("this instruction will write back the base register"));
11619 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
11620 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
11621 as_warn (_("value stored for r%d is UNKNOWN"),
11622 inst
.operands
[0].reg
);
11626 if (!inst
.operands
[0].writeback
11627 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11628 as_warn (_("this instruction will write back the base register"));
11629 else if (inst
.operands
[0].writeback
11630 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
11631 as_warn (_("this instruction will not write back the base register"));
11634 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11635 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11636 inst
.instruction
|= inst
.operands
[1].imm
;
11643 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
11644 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
11645 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
11646 || inst
.operands
[1].negative
,
11649 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
11651 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11652 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11653 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
11659 if (!inst
.operands
[1].present
)
11661 constraint (inst
.operands
[0].reg
== REG_LR
,
11662 _("r14 not allowed as first register "
11663 "when second register is omitted"));
11664 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11666 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11669 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11670 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11671 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11677 unsigned long opcode
;
11680 if (inst
.operands
[0].isreg
11681 && !inst
.operands
[0].preind
11682 && inst
.operands
[0].reg
== REG_PC
)
11683 set_it_insn_type_last ();
11685 opcode
= inst
.instruction
;
11686 if (unified_syntax
)
11688 if (!inst
.operands
[1].isreg
)
11690 if (opcode
<= 0xffff)
11691 inst
.instruction
= THUMB_OP32 (opcode
);
11692 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11695 if (inst
.operands
[1].isreg
11696 && !inst
.operands
[1].writeback
11697 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
11698 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
11699 && opcode
<= 0xffff
11700 && inst
.size_req
!= 4)
11702 /* Insn may have a 16-bit form. */
11703 Rn
= inst
.operands
[1].reg
;
11704 if (inst
.operands
[1].immisreg
)
11706 inst
.instruction
= THUMB_OP16 (opcode
);
11708 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
11710 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
11711 reject_bad_reg (inst
.operands
[1].imm
);
11713 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
11714 && opcode
!= T_MNEM_ldrsb
)
11715 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
11716 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
11723 if (inst
.reloc
.pc_rel
)
11724 opcode
= T_MNEM_ldr_pc2
;
11726 opcode
= T_MNEM_ldr_pc
;
11730 if (opcode
== T_MNEM_ldr
)
11731 opcode
= T_MNEM_ldr_sp
;
11733 opcode
= T_MNEM_str_sp
;
11735 inst
.instruction
= inst
.operands
[0].reg
<< 8;
11739 inst
.instruction
= inst
.operands
[0].reg
;
11740 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11742 inst
.instruction
|= THUMB_OP16 (opcode
);
11743 if (inst
.size_req
== 2)
11744 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11746 inst
.relax
= opcode
;
11750 /* Definitely a 32-bit variant. */
11752 /* Warning for Erratum 752419. */
11753 if (opcode
== T_MNEM_ldr
11754 && inst
.operands
[0].reg
== REG_SP
11755 && inst
.operands
[1].writeback
== 1
11756 && !inst
.operands
[1].immisreg
)
11758 if (no_cpu_selected ()
11759 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
11760 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
11761 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
11762 as_warn (_("This instruction may be unpredictable "
11763 "if executed on M-profile cores "
11764 "with interrupts enabled."));
11767 /* Do some validations regarding addressing modes. */
11768 if (inst
.operands
[1].immisreg
)
11769 reject_bad_reg (inst
.operands
[1].imm
);
11771 constraint (inst
.operands
[1].writeback
== 1
11772 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
11775 inst
.instruction
= THUMB_OP32 (opcode
);
11776 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11777 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
11778 check_ldr_r15_aligned ();
11782 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
11784 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
11786 /* Only [Rn,Rm] is acceptable. */
11787 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
11788 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
11789 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
11790 || inst
.operands
[1].negative
,
11791 _("Thumb does not support this addressing mode"));
11792 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11796 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11797 if (!inst
.operands
[1].isreg
)
11798 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
11801 constraint (!inst
.operands
[1].preind
11802 || inst
.operands
[1].shifted
11803 || inst
.operands
[1].writeback
,
11804 _("Thumb does not support this addressing mode"));
11805 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
11807 constraint (inst
.instruction
& 0x0600,
11808 _("byte or halfword not valid for base register"));
11809 constraint (inst
.operands
[1].reg
== REG_PC
11810 && !(inst
.instruction
& THUMB_LOAD_BIT
),
11811 _("r15 based store not allowed"));
11812 constraint (inst
.operands
[1].immisreg
,
11813 _("invalid base register for register offset"));
11815 if (inst
.operands
[1].reg
== REG_PC
)
11816 inst
.instruction
= T_OPCODE_LDR_PC
;
11817 else if (inst
.instruction
& THUMB_LOAD_BIT
)
11818 inst
.instruction
= T_OPCODE_LDR_SP
;
11820 inst
.instruction
= T_OPCODE_STR_SP
;
11822 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
11823 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11827 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
11828 if (!inst
.operands
[1].immisreg
)
11830 /* Immediate offset. */
11831 inst
.instruction
|= inst
.operands
[0].reg
;
11832 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11833 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_OFFSET
;
11837 /* Register offset. */
11838 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
11839 constraint (inst
.operands
[1].negative
,
11840 _("Thumb does not support this addressing mode"));
11843 switch (inst
.instruction
)
11845 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
11846 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
11847 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
11848 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
11849 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
11850 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
11851 case 0x5600 /* ldrsb */:
11852 case 0x5e00 /* ldrsh */: break;
11856 inst
.instruction
|= inst
.operands
[0].reg
;
11857 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
11858 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
11864 if (!inst
.operands
[1].present
)
11866 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
11867 constraint (inst
.operands
[0].reg
== REG_LR
,
11868 _("r14 not allowed here"));
11869 constraint (inst
.operands
[0].reg
== REG_R12
,
11870 _("r12 not allowed here"));
11873 if (inst
.operands
[2].writeback
11874 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
11875 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
11876 as_warn (_("base register written back, and overlaps "
11877 "one of transfer registers"));
11879 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11880 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
11881 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
11887 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11888 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
11894 unsigned Rd
, Rn
, Rm
, Ra
;
11896 Rd
= inst
.operands
[0].reg
;
11897 Rn
= inst
.operands
[1].reg
;
11898 Rm
= inst
.operands
[2].reg
;
11899 Ra
= inst
.operands
[3].reg
;
11901 reject_bad_reg (Rd
);
11902 reject_bad_reg (Rn
);
11903 reject_bad_reg (Rm
);
11904 reject_bad_reg (Ra
);
11906 inst
.instruction
|= Rd
<< 8;
11907 inst
.instruction
|= Rn
<< 16;
11908 inst
.instruction
|= Rm
;
11909 inst
.instruction
|= Ra
<< 12;
11915 unsigned RdLo
, RdHi
, Rn
, Rm
;
11917 RdLo
= inst
.operands
[0].reg
;
11918 RdHi
= inst
.operands
[1].reg
;
11919 Rn
= inst
.operands
[2].reg
;
11920 Rm
= inst
.operands
[3].reg
;
11922 reject_bad_reg (RdLo
);
11923 reject_bad_reg (RdHi
);
11924 reject_bad_reg (Rn
);
11925 reject_bad_reg (Rm
);
11927 inst
.instruction
|= RdLo
<< 12;
11928 inst
.instruction
|= RdHi
<< 8;
11929 inst
.instruction
|= Rn
<< 16;
11930 inst
.instruction
|= Rm
;
11934 do_t_mov_cmp (void)
11938 Rn
= inst
.operands
[0].reg
;
11939 Rm
= inst
.operands
[1].reg
;
11942 set_it_insn_type_last ();
11944 if (unified_syntax
)
11946 int r0off
= (inst
.instruction
== T_MNEM_mov
11947 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
11948 unsigned long opcode
;
11949 bfd_boolean narrow
;
11950 bfd_boolean low_regs
;
11952 low_regs
= (Rn
<= 7 && Rm
<= 7);
11953 opcode
= inst
.instruction
;
11954 if (in_it_block ())
11955 narrow
= opcode
!= T_MNEM_movs
;
11957 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
11958 if (inst
.size_req
== 4
11959 || inst
.operands
[1].shifted
)
11962 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
11963 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
11964 && !inst
.operands
[1].shifted
11968 inst
.instruction
= T2_SUBS_PC_LR
;
11972 if (opcode
== T_MNEM_cmp
)
11974 constraint (Rn
== REG_PC
, BAD_PC
);
11977 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
11979 warn_deprecated_sp (Rm
);
11980 /* R15 was documented as a valid choice for Rm in ARMv6,
11981 but as UNPREDICTABLE in ARMv7. ARM's proprietary
11982 tools reject R15, so we do too. */
11983 constraint (Rm
== REG_PC
, BAD_PC
);
11986 reject_bad_reg (Rm
);
11988 else if (opcode
== T_MNEM_mov
11989 || opcode
== T_MNEM_movs
)
11991 if (inst
.operands
[1].isreg
)
11993 if (opcode
== T_MNEM_movs
)
11995 reject_bad_reg (Rn
);
11996 reject_bad_reg (Rm
);
12000 /* This is mov.n. */
12001 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12002 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12004 as_tsktsk (_("Use of r%u as a source register is "
12005 "deprecated when r%u is the destination "
12006 "register."), Rm
, Rn
);
12011 /* This is mov.w. */
12012 constraint (Rn
== REG_PC
, BAD_PC
);
12013 constraint (Rm
== REG_PC
, BAD_PC
);
12014 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12015 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12019 reject_bad_reg (Rn
);
12022 if (!inst
.operands
[1].isreg
)
12024 /* Immediate operand. */
12025 if (!in_it_block () && opcode
== T_MNEM_mov
)
12027 if (low_regs
&& narrow
)
12029 inst
.instruction
= THUMB_OP16 (opcode
);
12030 inst
.instruction
|= Rn
<< 8;
12031 if (inst
.reloc
.type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12032 || inst
.reloc
.type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12034 if (inst
.size_req
== 2)
12035 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12037 inst
.relax
= opcode
;
12042 constraint (inst
.reloc
.type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12043 && inst
.reloc
.type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
12044 THUMB1_RELOC_ONLY
);
12046 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12047 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12048 inst
.instruction
|= Rn
<< r0off
;
12049 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12052 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12053 && (inst
.instruction
== T_MNEM_mov
12054 || inst
.instruction
== T_MNEM_movs
))
12056 /* Register shifts are encoded as separate shift instructions. */
12057 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12059 if (in_it_block ())
12064 if (inst
.size_req
== 4)
12067 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12073 switch (inst
.operands
[1].shift_kind
)
12076 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12079 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12082 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12085 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12091 inst
.instruction
= opcode
;
12094 inst
.instruction
|= Rn
;
12095 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12100 inst
.instruction
|= CONDS_BIT
;
12102 inst
.instruction
|= Rn
<< 8;
12103 inst
.instruction
|= Rm
<< 16;
12104 inst
.instruction
|= inst
.operands
[1].imm
;
12109 /* Some mov with immediate shift have narrow variants.
12110 Register shifts are handled above. */
12111 if (low_regs
&& inst
.operands
[1].shifted
12112 && (inst
.instruction
== T_MNEM_mov
12113 || inst
.instruction
== T_MNEM_movs
))
12115 if (in_it_block ())
12116 narrow
= (inst
.instruction
== T_MNEM_mov
);
12118 narrow
= (inst
.instruction
== T_MNEM_movs
);
12123 switch (inst
.operands
[1].shift_kind
)
12125 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12126 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12127 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12128 default: narrow
= FALSE
; break;
12134 inst
.instruction
|= Rn
;
12135 inst
.instruction
|= Rm
<< 3;
12136 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12140 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12141 inst
.instruction
|= Rn
<< r0off
;
12142 encode_thumb32_shifted_operand (1);
12146 switch (inst
.instruction
)
12149 /* In v4t or v5t a move of two lowregs produces unpredictable
12150 results. Don't allow this. */
12153 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
12154 "MOV Rd, Rs with two low registers is not "
12155 "permitted on this architecture");
12156 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
12160 inst
.instruction
= T_OPCODE_MOV_HR
;
12161 inst
.instruction
|= (Rn
& 0x8) << 4;
12162 inst
.instruction
|= (Rn
& 0x7);
12163 inst
.instruction
|= Rm
<< 3;
12167 /* We know we have low registers at this point.
12168 Generate LSLS Rd, Rs, #0. */
12169 inst
.instruction
= T_OPCODE_LSL_I
;
12170 inst
.instruction
|= Rn
;
12171 inst
.instruction
|= Rm
<< 3;
12177 inst
.instruction
= T_OPCODE_CMP_LR
;
12178 inst
.instruction
|= Rn
;
12179 inst
.instruction
|= Rm
<< 3;
12183 inst
.instruction
= T_OPCODE_CMP_HR
;
12184 inst
.instruction
|= (Rn
& 0x8) << 4;
12185 inst
.instruction
|= (Rn
& 0x7);
12186 inst
.instruction
|= Rm
<< 3;
12193 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12195 /* PR 10443: Do not silently ignore shifted operands. */
12196 constraint (inst
.operands
[1].shifted
,
12197 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
12199 if (inst
.operands
[1].isreg
)
12201 if (Rn
< 8 && Rm
< 8)
12203 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
12204 since a MOV instruction produces unpredictable results. */
12205 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12206 inst
.instruction
= T_OPCODE_ADD_I3
;
12208 inst
.instruction
= T_OPCODE_CMP_LR
;
12210 inst
.instruction
|= Rn
;
12211 inst
.instruction
|= Rm
<< 3;
12215 if (inst
.instruction
== T_OPCODE_MOV_I8
)
12216 inst
.instruction
= T_OPCODE_MOV_HR
;
12218 inst
.instruction
= T_OPCODE_CMP_HR
;
12224 constraint (Rn
> 7,
12225 _("only lo regs allowed with immediate"));
12226 inst
.instruction
|= Rn
<< 8;
12227 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_IMM
;
12238 top
= (inst
.instruction
& 0x00800000) != 0;
12239 if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVW
)
12241 constraint (top
, _(":lower16: not allowed in this instruction"));
12242 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVW
;
12244 else if (inst
.reloc
.type
== BFD_RELOC_ARM_MOVT
)
12246 constraint (!top
, _(":upper16: not allowed in this instruction"));
12247 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_MOVT
;
12250 Rd
= inst
.operands
[0].reg
;
12251 reject_bad_reg (Rd
);
12253 inst
.instruction
|= Rd
<< 8;
12254 if (inst
.reloc
.type
== BFD_RELOC_UNUSED
)
12256 imm
= inst
.reloc
.exp
.X_add_number
;
12257 inst
.instruction
|= (imm
& 0xf000) << 4;
12258 inst
.instruction
|= (imm
& 0x0800) << 15;
12259 inst
.instruction
|= (imm
& 0x0700) << 4;
12260 inst
.instruction
|= (imm
& 0x00ff);
12265 do_t_mvn_tst (void)
12269 Rn
= inst
.operands
[0].reg
;
12270 Rm
= inst
.operands
[1].reg
;
12272 if (inst
.instruction
== T_MNEM_cmp
12273 || inst
.instruction
== T_MNEM_cmn
)
12274 constraint (Rn
== REG_PC
, BAD_PC
);
12276 reject_bad_reg (Rn
);
12277 reject_bad_reg (Rm
);
12279 if (unified_syntax
)
12281 int r0off
= (inst
.instruction
== T_MNEM_mvn
12282 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
12283 bfd_boolean narrow
;
12285 if (inst
.size_req
== 4
12286 || inst
.instruction
> 0xffff
12287 || inst
.operands
[1].shifted
12288 || Rn
> 7 || Rm
> 7)
12290 else if (inst
.instruction
== T_MNEM_cmn
12291 || inst
.instruction
== T_MNEM_tst
)
12293 else if (THUMB_SETS_FLAGS (inst
.instruction
))
12294 narrow
= !in_it_block ();
12296 narrow
= in_it_block ();
12298 if (!inst
.operands
[1].isreg
)
12300 /* For an immediate, we always generate a 32-bit opcode;
12301 section relaxation will shrink it later if possible. */
12302 if (inst
.instruction
< 0xffff)
12303 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12304 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12305 inst
.instruction
|= Rn
<< r0off
;
12306 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12310 /* See if we can do this with a 16-bit instruction. */
12313 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12314 inst
.instruction
|= Rn
;
12315 inst
.instruction
|= Rm
<< 3;
12319 constraint (inst
.operands
[1].shifted
12320 && inst
.operands
[1].immisreg
,
12321 _("shift must be constant"));
12322 if (inst
.instruction
< 0xffff)
12323 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12324 inst
.instruction
|= Rn
<< r0off
;
12325 encode_thumb32_shifted_operand (1);
12331 constraint (inst
.instruction
> 0xffff
12332 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
12333 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
12334 _("unshifted register required"));
12335 constraint (Rn
> 7 || Rm
> 7,
12338 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12339 inst
.instruction
|= Rn
;
12340 inst
.instruction
|= Rm
<< 3;
12349 if (do_vfp_nsyn_mrs () == SUCCESS
)
12352 Rd
= inst
.operands
[0].reg
;
12353 reject_bad_reg (Rd
);
12354 inst
.instruction
|= Rd
<< 8;
12356 if (inst
.operands
[1].isreg
)
12358 unsigned br
= inst
.operands
[1].reg
;
12359 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
12360 as_bad (_("bad register for mrs"));
12362 inst
.instruction
|= br
& (0xf << 16);
12363 inst
.instruction
|= (br
& 0x300) >> 4;
12364 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
12368 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12370 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12372 /* PR gas/12698: The constraint is only applied for m_profile.
12373 If the user has specified -march=all, we want to ignore it as
12374 we are building for any CPU type, including non-m variants. */
12375 bfd_boolean m_profile
=
12376 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12377 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
12378 "not support requested special purpose register"));
12381 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
12383 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
12384 _("'APSR', 'CPSR' or 'SPSR' expected"));
12386 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12387 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
12388 inst
.instruction
|= 0xf0000;
12398 if (do_vfp_nsyn_msr () == SUCCESS
)
12401 constraint (!inst
.operands
[1].isreg
,
12402 _("Thumb encoding does not support an immediate here"));
12404 if (inst
.operands
[0].isreg
)
12405 flags
= (int)(inst
.operands
[0].reg
);
12407 flags
= inst
.operands
[0].imm
;
12409 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
12411 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
12413 /* PR gas/12698: The constraint is only applied for m_profile.
12414 If the user has specified -march=all, we want to ignore it as
12415 we are building for any CPU type, including non-m variants. */
12416 bfd_boolean m_profile
=
12417 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
12418 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12419 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
12420 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
12421 && bits
!= PSR_f
)) && m_profile
,
12422 _("selected processor does not support requested special "
12423 "purpose register"));
12426 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
12427 "requested special purpose register"));
12429 Rn
= inst
.operands
[1].reg
;
12430 reject_bad_reg (Rn
);
12432 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
12433 inst
.instruction
|= (flags
& 0xf0000) >> 8;
12434 inst
.instruction
|= (flags
& 0x300) >> 4;
12435 inst
.instruction
|= (flags
& 0xff);
12436 inst
.instruction
|= Rn
<< 16;
12442 bfd_boolean narrow
;
12443 unsigned Rd
, Rn
, Rm
;
12445 if (!inst
.operands
[2].present
)
12446 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
12448 Rd
= inst
.operands
[0].reg
;
12449 Rn
= inst
.operands
[1].reg
;
12450 Rm
= inst
.operands
[2].reg
;
12452 if (unified_syntax
)
12454 if (inst
.size_req
== 4
12460 else if (inst
.instruction
== T_MNEM_muls
)
12461 narrow
= !in_it_block ();
12463 narrow
= in_it_block ();
12467 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
12468 constraint (Rn
> 7 || Rm
> 7,
12475 /* 16-bit MULS/Conditional MUL. */
12476 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12477 inst
.instruction
|= Rd
;
12480 inst
.instruction
|= Rm
<< 3;
12482 inst
.instruction
|= Rn
<< 3;
12484 constraint (1, _("dest must overlap one source register"));
12488 constraint (inst
.instruction
!= T_MNEM_mul
,
12489 _("Thumb-2 MUL must not set flags"));
12491 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12492 inst
.instruction
|= Rd
<< 8;
12493 inst
.instruction
|= Rn
<< 16;
12494 inst
.instruction
|= Rm
<< 0;
12496 reject_bad_reg (Rd
);
12497 reject_bad_reg (Rn
);
12498 reject_bad_reg (Rm
);
12505 unsigned RdLo
, RdHi
, Rn
, Rm
;
12507 RdLo
= inst
.operands
[0].reg
;
12508 RdHi
= inst
.operands
[1].reg
;
12509 Rn
= inst
.operands
[2].reg
;
12510 Rm
= inst
.operands
[3].reg
;
12512 reject_bad_reg (RdLo
);
12513 reject_bad_reg (RdHi
);
12514 reject_bad_reg (Rn
);
12515 reject_bad_reg (Rm
);
12517 inst
.instruction
|= RdLo
<< 12;
12518 inst
.instruction
|= RdHi
<< 8;
12519 inst
.instruction
|= Rn
<< 16;
12520 inst
.instruction
|= Rm
;
12523 as_tsktsk (_("rdhi and rdlo must be different"));
12529 set_it_insn_type (NEUTRAL_IT_INSN
);
12531 if (unified_syntax
)
12533 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
12535 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12536 inst
.instruction
|= inst
.operands
[0].imm
;
12540 /* PR9722: Check for Thumb2 availability before
12541 generating a thumb2 nop instruction. */
12542 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
12544 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12545 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
12548 inst
.instruction
= 0x46c0;
12553 constraint (inst
.operands
[0].present
,
12554 _("Thumb does not support NOP with hints"));
12555 inst
.instruction
= 0x46c0;
12562 if (unified_syntax
)
12564 bfd_boolean narrow
;
12566 if (THUMB_SETS_FLAGS (inst
.instruction
))
12567 narrow
= !in_it_block ();
12569 narrow
= in_it_block ();
12570 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12572 if (inst
.size_req
== 4)
12577 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12578 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12579 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12583 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12584 inst
.instruction
|= inst
.operands
[0].reg
;
12585 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12590 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
12592 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12594 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12595 inst
.instruction
|= inst
.operands
[0].reg
;
12596 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12605 Rd
= inst
.operands
[0].reg
;
12606 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
12608 reject_bad_reg (Rd
);
12609 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
12610 reject_bad_reg (Rn
);
12612 inst
.instruction
|= Rd
<< 8;
12613 inst
.instruction
|= Rn
<< 16;
12615 if (!inst
.operands
[2].isreg
)
12617 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12618 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12624 Rm
= inst
.operands
[2].reg
;
12625 reject_bad_reg (Rm
);
12627 constraint (inst
.operands
[2].shifted
12628 && inst
.operands
[2].immisreg
,
12629 _("shift must be constant"));
12630 encode_thumb32_shifted_operand (2);
12637 unsigned Rd
, Rn
, Rm
;
12639 Rd
= inst
.operands
[0].reg
;
12640 Rn
= inst
.operands
[1].reg
;
12641 Rm
= inst
.operands
[2].reg
;
12643 reject_bad_reg (Rd
);
12644 reject_bad_reg (Rn
);
12645 reject_bad_reg (Rm
);
12647 inst
.instruction
|= Rd
<< 8;
12648 inst
.instruction
|= Rn
<< 16;
12649 inst
.instruction
|= Rm
;
12650 if (inst
.operands
[3].present
)
12652 unsigned int val
= inst
.reloc
.exp
.X_add_number
;
12653 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
12654 _("expression too complex"));
12655 inst
.instruction
|= (val
& 0x1c) << 10;
12656 inst
.instruction
|= (val
& 0x03) << 6;
12663 if (!inst
.operands
[3].present
)
12667 inst
.instruction
&= ~0x00000020;
12669 /* PR 10168. Swap the Rm and Rn registers. */
12670 Rtmp
= inst
.operands
[1].reg
;
12671 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
12672 inst
.operands
[2].reg
= Rtmp
;
12680 if (inst
.operands
[0].immisreg
)
12681 reject_bad_reg (inst
.operands
[0].imm
);
12683 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12687 do_t_push_pop (void)
12691 constraint (inst
.operands
[0].writeback
,
12692 _("push/pop do not support {reglist}^"));
12693 constraint (inst
.reloc
.type
!= BFD_RELOC_UNUSED
,
12694 _("expression too complex"));
12696 mask
= inst
.operands
[0].imm
;
12697 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
12698 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
12699 else if (inst
.size_req
!= 4
12700 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
12701 ? REG_LR
: REG_PC
)))
12703 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12704 inst
.instruction
|= THUMB_PP_PC_LR
;
12705 inst
.instruction
|= mask
& 0xff;
12707 else if (unified_syntax
)
12709 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12710 encode_thumb2_ldmstm (13, mask
, TRUE
);
12714 inst
.error
= _("invalid register list to push/pop instruction");
12724 Rd
= inst
.operands
[0].reg
;
12725 Rm
= inst
.operands
[1].reg
;
12727 reject_bad_reg (Rd
);
12728 reject_bad_reg (Rm
);
12730 inst
.instruction
|= Rd
<< 8;
12731 inst
.instruction
|= Rm
<< 16;
12732 inst
.instruction
|= Rm
;
12740 Rd
= inst
.operands
[0].reg
;
12741 Rm
= inst
.operands
[1].reg
;
12743 reject_bad_reg (Rd
);
12744 reject_bad_reg (Rm
);
12746 if (Rd
<= 7 && Rm
<= 7
12747 && inst
.size_req
!= 4)
12749 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12750 inst
.instruction
|= Rd
;
12751 inst
.instruction
|= Rm
<< 3;
12753 else if (unified_syntax
)
12755 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12756 inst
.instruction
|= Rd
<< 8;
12757 inst
.instruction
|= Rm
<< 16;
12758 inst
.instruction
|= Rm
;
12761 inst
.error
= BAD_HIREG
;
12769 Rd
= inst
.operands
[0].reg
;
12770 Rm
= inst
.operands
[1].reg
;
12772 reject_bad_reg (Rd
);
12773 reject_bad_reg (Rm
);
12775 inst
.instruction
|= Rd
<< 8;
12776 inst
.instruction
|= Rm
;
12784 Rd
= inst
.operands
[0].reg
;
12785 Rs
= (inst
.operands
[1].present
12786 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
12787 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
12789 reject_bad_reg (Rd
);
12790 reject_bad_reg (Rs
);
12791 if (inst
.operands
[2].isreg
)
12792 reject_bad_reg (inst
.operands
[2].reg
);
12794 inst
.instruction
|= Rd
<< 8;
12795 inst
.instruction
|= Rs
<< 16;
12796 if (!inst
.operands
[2].isreg
)
12798 bfd_boolean narrow
;
12800 if ((inst
.instruction
& 0x00100000) != 0)
12801 narrow
= !in_it_block ();
12803 narrow
= in_it_block ();
12805 if (Rd
> 7 || Rs
> 7)
12808 if (inst
.size_req
== 4 || !unified_syntax
)
12811 if (inst
.reloc
.exp
.X_op
!= O_constant
12812 || inst
.reloc
.exp
.X_add_number
!= 0)
12815 /* Turn rsb #0 into 16-bit neg. We should probably do this via
12816 relaxation, but it doesn't seem worth the hassle. */
12819 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12820 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
12821 inst
.instruction
|= Rs
<< 3;
12822 inst
.instruction
|= Rd
;
12826 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12827 inst
.reloc
.type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12831 encode_thumb32_shifted_operand (2);
12837 if (warn_on_deprecated
12838 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12839 as_tsktsk (_("setend use is deprecated for ARMv8"));
12841 set_it_insn_type (OUTSIDE_IT_INSN
);
12842 if (inst
.operands
[0].imm
)
12843 inst
.instruction
|= 0x8;
12849 if (!inst
.operands
[1].present
)
12850 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
12852 if (unified_syntax
)
12854 bfd_boolean narrow
;
12857 switch (inst
.instruction
)
12860 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
12862 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
12864 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
12866 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
12870 if (THUMB_SETS_FLAGS (inst
.instruction
))
12871 narrow
= !in_it_block ();
12873 narrow
= in_it_block ();
12874 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
12876 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
12878 if (inst
.operands
[2].isreg
12879 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
12880 || inst
.operands
[2].reg
> 7))
12882 if (inst
.size_req
== 4)
12885 reject_bad_reg (inst
.operands
[0].reg
);
12886 reject_bad_reg (inst
.operands
[1].reg
);
12890 if (inst
.operands
[2].isreg
)
12892 reject_bad_reg (inst
.operands
[2].reg
);
12893 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12894 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12895 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12896 inst
.instruction
|= inst
.operands
[2].reg
;
12898 /* PR 12854: Error on extraneous shifts. */
12899 constraint (inst
.operands
[2].shifted
,
12900 _("extraneous shift as part of operand to shift insn"));
12904 inst
.operands
[1].shifted
= 1;
12905 inst
.operands
[1].shift_kind
= shift_kind
;
12906 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
12907 ? T_MNEM_movs
: T_MNEM_mov
);
12908 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12909 encode_thumb32_shifted_operand (1);
12910 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
12911 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
12916 if (inst
.operands
[2].isreg
)
12918 switch (shift_kind
)
12920 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12921 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12922 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12923 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12927 inst
.instruction
|= inst
.operands
[0].reg
;
12928 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12930 /* PR 12854: Error on extraneous shifts. */
12931 constraint (inst
.operands
[2].shifted
,
12932 _("extraneous shift as part of operand to shift insn"));
12936 switch (shift_kind
)
12938 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12939 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12940 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12943 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12944 inst
.instruction
|= inst
.operands
[0].reg
;
12945 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12951 constraint (inst
.operands
[0].reg
> 7
12952 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
12953 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
12955 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
12957 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
12958 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
12959 _("source1 and dest must be same register"));
12961 switch (inst
.instruction
)
12963 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
12964 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
12965 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
12966 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
12970 inst
.instruction
|= inst
.operands
[0].reg
;
12971 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
12973 /* PR 12854: Error on extraneous shifts. */
12974 constraint (inst
.operands
[2].shifted
,
12975 _("extraneous shift as part of operand to shift insn"));
12979 switch (inst
.instruction
)
12981 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
12982 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
12983 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
12984 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
12987 inst
.reloc
.type
= BFD_RELOC_ARM_THUMB_SHIFT
;
12988 inst
.instruction
|= inst
.operands
[0].reg
;
12989 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12997 unsigned Rd
, Rn
, Rm
;
12999 Rd
= inst
.operands
[0].reg
;
13000 Rn
= inst
.operands
[1].reg
;
13001 Rm
= inst
.operands
[2].reg
;
13003 reject_bad_reg (Rd
);
13004 reject_bad_reg (Rn
);
13005 reject_bad_reg (Rm
);
13007 inst
.instruction
|= Rd
<< 8;
13008 inst
.instruction
|= Rn
<< 16;
13009 inst
.instruction
|= Rm
;
13015 unsigned Rd
, Rn
, Rm
;
13017 Rd
= inst
.operands
[0].reg
;
13018 Rm
= inst
.operands
[1].reg
;
13019 Rn
= inst
.operands
[2].reg
;
13021 reject_bad_reg (Rd
);
13022 reject_bad_reg (Rn
);
13023 reject_bad_reg (Rm
);
13025 inst
.instruction
|= Rd
<< 8;
13026 inst
.instruction
|= Rn
<< 16;
13027 inst
.instruction
|= Rm
;
13033 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13034 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13035 _("SMC is not permitted on this architecture"));
13036 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13037 _("expression too complex"));
13038 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13039 inst
.instruction
|= (value
& 0xf000) >> 12;
13040 inst
.instruction
|= (value
& 0x0ff0);
13041 inst
.instruction
|= (value
& 0x000f) << 16;
13042 /* PR gas/15623: SMC instructions must be last in an IT block. */
13043 set_it_insn_type_last ();
13049 unsigned int value
= inst
.reloc
.exp
.X_add_number
;
13051 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13052 inst
.instruction
|= (value
& 0x0fff);
13053 inst
.instruction
|= (value
& 0xf000) << 4;
13057 do_t_ssat_usat (int bias
)
13061 Rd
= inst
.operands
[0].reg
;
13062 Rn
= inst
.operands
[2].reg
;
13064 reject_bad_reg (Rd
);
13065 reject_bad_reg (Rn
);
13067 inst
.instruction
|= Rd
<< 8;
13068 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13069 inst
.instruction
|= Rn
<< 16;
13071 if (inst
.operands
[3].present
)
13073 offsetT shift_amount
= inst
.reloc
.exp
.X_add_number
;
13075 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
13077 constraint (inst
.reloc
.exp
.X_op
!= O_constant
,
13078 _("expression too complex"));
13080 if (shift_amount
!= 0)
13082 constraint (shift_amount
> 31,
13083 _("shift expression is too large"));
13085 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13086 inst
.instruction
|= 0x00200000; /* sh bit. */
13088 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
13089 inst
.instruction
|= (shift_amount
& 0x03) << 6;
13097 do_t_ssat_usat (1);
13105 Rd
= inst
.operands
[0].reg
;
13106 Rn
= inst
.operands
[2].reg
;
13108 reject_bad_reg (Rd
);
13109 reject_bad_reg (Rn
);
13111 inst
.instruction
|= Rd
<< 8;
13112 inst
.instruction
|= inst
.operands
[1].imm
- 1;
13113 inst
.instruction
|= Rn
<< 16;
13119 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
13120 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
13121 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
13122 || inst
.operands
[2].negative
,
13125 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
13127 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13128 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13129 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
13130 inst
.reloc
.type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
13136 if (!inst
.operands
[2].present
)
13137 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
13139 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
13140 || inst
.operands
[0].reg
== inst
.operands
[2].reg
13141 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
13144 inst
.instruction
|= inst
.operands
[0].reg
;
13145 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
13146 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
13147 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
13153 unsigned Rd
, Rn
, Rm
;
13155 Rd
= inst
.operands
[0].reg
;
13156 Rn
= inst
.operands
[1].reg
;
13157 Rm
= inst
.operands
[2].reg
;
13159 reject_bad_reg (Rd
);
13160 reject_bad_reg (Rn
);
13161 reject_bad_reg (Rm
);
13163 inst
.instruction
|= Rd
<< 8;
13164 inst
.instruction
|= Rn
<< 16;
13165 inst
.instruction
|= Rm
;
13166 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
13174 Rd
= inst
.operands
[0].reg
;
13175 Rm
= inst
.operands
[1].reg
;
13177 reject_bad_reg (Rd
);
13178 reject_bad_reg (Rm
);
13180 if (inst
.instruction
<= 0xffff
13181 && inst
.size_req
!= 4
13182 && Rd
<= 7 && Rm
<= 7
13183 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
13185 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13186 inst
.instruction
|= Rd
;
13187 inst
.instruction
|= Rm
<< 3;
13189 else if (unified_syntax
)
13191 if (inst
.instruction
<= 0xffff)
13192 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13193 inst
.instruction
|= Rd
<< 8;
13194 inst
.instruction
|= Rm
;
13195 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
13199 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
13200 _("Thumb encoding does not support rotation"));
13201 constraint (1, BAD_HIREG
);
13208 inst
.reloc
.type
= BFD_RELOC_ARM_SWI
;
13217 half
= (inst
.instruction
& 0x10) != 0;
13218 set_it_insn_type_last ();
13219 constraint (inst
.operands
[0].immisreg
,
13220 _("instruction requires register index"));
13222 Rn
= inst
.operands
[0].reg
;
13223 Rm
= inst
.operands
[0].imm
;
13225 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13226 constraint (Rn
== REG_SP
, BAD_SP
);
13227 reject_bad_reg (Rm
);
13229 constraint (!half
&& inst
.operands
[0].shifted
,
13230 _("instruction does not allow shifted index"));
13231 inst
.instruction
|= (Rn
<< 16) | Rm
;
13237 if (!inst
.operands
[0].present
)
13238 inst
.operands
[0].imm
= 0;
13240 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
13242 constraint (inst
.size_req
== 2,
13243 _("immediate value out of range"));
13244 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13245 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
13246 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
13250 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13251 inst
.instruction
|= inst
.operands
[0].imm
;
13254 set_it_insn_type (NEUTRAL_IT_INSN
);
13261 do_t_ssat_usat (0);
13269 Rd
= inst
.operands
[0].reg
;
13270 Rn
= inst
.operands
[2].reg
;
13272 reject_bad_reg (Rd
);
13273 reject_bad_reg (Rn
);
13275 inst
.instruction
|= Rd
<< 8;
13276 inst
.instruction
|= inst
.operands
[1].imm
;
13277 inst
.instruction
|= Rn
<< 16;
13280 /* Neon instruction encoder helpers. */
13282 /* Encodings for the different types for various Neon opcodes. */
13284 /* An "invalid" code for the following tables. */
13287 struct neon_tab_entry
13290 unsigned float_or_poly
;
13291 unsigned scalar_or_imm
;
13294 /* Map overloaded Neon opcodes to their respective encodings. */
13295 #define NEON_ENC_TAB \
13296 X(vabd, 0x0000700, 0x1200d00, N_INV), \
13297 X(vmax, 0x0000600, 0x0000f00, N_INV), \
13298 X(vmin, 0x0000610, 0x0200f00, N_INV), \
13299 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
13300 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
13301 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
13302 X(vadd, 0x0000800, 0x0000d00, N_INV), \
13303 X(vsub, 0x1000800, 0x0200d00, N_INV), \
13304 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
13305 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
13306 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
13307 /* Register variants of the following two instructions are encoded as
13308 vcge / vcgt with the operands reversed. */ \
13309 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
13310 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
13311 X(vfma, N_INV, 0x0000c10, N_INV), \
13312 X(vfms, N_INV, 0x0200c10, N_INV), \
13313 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
13314 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
13315 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
13316 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
13317 X(vmlal, 0x0800800, N_INV, 0x0800240), \
13318 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
13319 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
13320 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
13321 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
13322 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
13323 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
13324 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
13325 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
13326 X(vshl, 0x0000400, N_INV, 0x0800510), \
13327 X(vqshl, 0x0000410, N_INV, 0x0800710), \
13328 X(vand, 0x0000110, N_INV, 0x0800030), \
13329 X(vbic, 0x0100110, N_INV, 0x0800030), \
13330 X(veor, 0x1000110, N_INV, N_INV), \
13331 X(vorn, 0x0300110, N_INV, 0x0800010), \
13332 X(vorr, 0x0200110, N_INV, 0x0800010), \
13333 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
13334 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
13335 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
13336 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
13337 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
13338 X(vst1, 0x0000000, 0x0800000, N_INV), \
13339 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
13340 X(vst2, 0x0000100, 0x0800100, N_INV), \
13341 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
13342 X(vst3, 0x0000200, 0x0800200, N_INV), \
13343 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
13344 X(vst4, 0x0000300, 0x0800300, N_INV), \
13345 X(vmovn, 0x1b20200, N_INV, N_INV), \
13346 X(vtrn, 0x1b20080, N_INV, N_INV), \
13347 X(vqmovn, 0x1b20200, N_INV, N_INV), \
13348 X(vqmovun, 0x1b20240, N_INV, N_INV), \
13349 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
13350 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
13351 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
13352 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
13353 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
13354 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
13355 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
13356 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
13357 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
13358 X(vseleq, 0xe000a00, N_INV, N_INV), \
13359 X(vselvs, 0xe100a00, N_INV, N_INV), \
13360 X(vselge, 0xe200a00, N_INV, N_INV), \
13361 X(vselgt, 0xe300a00, N_INV, N_INV), \
13362 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
13363 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
13364 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
13365 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
13366 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
13367 X(aes, 0x3b00300, N_INV, N_INV), \
13368 X(sha3op, 0x2000c00, N_INV, N_INV), \
13369 X(sha1h, 0x3b902c0, N_INV, N_INV), \
13370 X(sha2op, 0x3ba0380, N_INV, N_INV)
13374 #define X(OPC,I,F,S) N_MNEM_##OPC
13379 static const struct neon_tab_entry neon_enc_tab
[] =
13381 #define X(OPC,I,F,S) { (I), (F), (S) }
13386 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
13387 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13388 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13389 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13390 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13391 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13392 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13393 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
13394 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
13395 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
13396 #define NEON_ENC_SINGLE_(X) \
13397 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
13398 #define NEON_ENC_DOUBLE_(X) \
13399 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
13400 #define NEON_ENC_FPV8_(X) \
13401 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
13403 #define NEON_ENCODE(type, inst) \
13406 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
13407 inst.is_neon = 1; \
13411 #define check_neon_suffixes \
13414 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
13416 as_bad (_("invalid neon suffix for non neon instruction")); \
13422 /* Define shapes for instruction operands. The following mnemonic characters
13423 are used in this table:
13425 F - VFP S<n> register
13426 D - Neon D<n> register
13427 Q - Neon Q<n> register
13431 L - D<n> register list
13433 This table is used to generate various data:
13434 - enumerations of the form NS_DDR to be used as arguments to
13436 - a table classifying shapes into single, double, quad, mixed.
13437 - a table used to drive neon_select_shape. */
13439 #define NEON_SHAPE_DEF \
13440 X(3, (D, D, D), DOUBLE), \
13441 X(3, (Q, Q, Q), QUAD), \
13442 X(3, (D, D, I), DOUBLE), \
13443 X(3, (Q, Q, I), QUAD), \
13444 X(3, (D, D, S), DOUBLE), \
13445 X(3, (Q, Q, S), QUAD), \
13446 X(2, (D, D), DOUBLE), \
13447 X(2, (Q, Q), QUAD), \
13448 X(2, (D, S), DOUBLE), \
13449 X(2, (Q, S), QUAD), \
13450 X(2, (D, R), DOUBLE), \
13451 X(2, (Q, R), QUAD), \
13452 X(2, (D, I), DOUBLE), \
13453 X(2, (Q, I), QUAD), \
13454 X(3, (D, L, D), DOUBLE), \
13455 X(2, (D, Q), MIXED), \
13456 X(2, (Q, D), MIXED), \
13457 X(3, (D, Q, I), MIXED), \
13458 X(3, (Q, D, I), MIXED), \
13459 X(3, (Q, D, D), MIXED), \
13460 X(3, (D, Q, Q), MIXED), \
13461 X(3, (Q, Q, D), MIXED), \
13462 X(3, (Q, D, S), MIXED), \
13463 X(3, (D, Q, S), MIXED), \
13464 X(4, (D, D, D, I), DOUBLE), \
13465 X(4, (Q, Q, Q, I), QUAD), \
13466 X(4, (D, D, S, I), DOUBLE), \
13467 X(4, (Q, Q, S, I), QUAD), \
13468 X(2, (F, F), SINGLE), \
13469 X(3, (F, F, F), SINGLE), \
13470 X(2, (F, I), SINGLE), \
13471 X(2, (F, D), MIXED), \
13472 X(2, (D, F), MIXED), \
13473 X(3, (F, F, I), MIXED), \
13474 X(4, (R, R, F, F), SINGLE), \
13475 X(4, (F, F, R, R), SINGLE), \
13476 X(3, (D, R, R), DOUBLE), \
13477 X(3, (R, R, D), DOUBLE), \
13478 X(2, (S, R), SINGLE), \
13479 X(2, (R, S), SINGLE), \
13480 X(2, (F, R), SINGLE), \
13481 X(2, (R, F), SINGLE), \
13482 /* Half float shape supported so far. */\
13483 X (2, (H, D), MIXED), \
13484 X (2, (D, H), MIXED), \
13485 X (2, (H, F), MIXED), \
13486 X (2, (F, H), MIXED), \
13487 X (2, (H, H), HALF), \
13488 X (2, (H, R), HALF), \
13489 X (2, (R, H), HALF), \
13490 X (2, (H, I), HALF), \
13491 X (3, (H, H, H), HALF), \
13492 X (3, (H, F, I), MIXED), \
13493 X (3, (F, H, I), MIXED), \
13494 X (3, (D, H, H), MIXED), \
13495 X (3, (D, H, S), MIXED)
13497 #define S2(A,B) NS_##A##B
13498 #define S3(A,B,C) NS_##A##B##C
13499 #define S4(A,B,C,D) NS_##A##B##C##D
13501 #define X(N, L, C) S##N L
13514 enum neon_shape_class
13523 #define X(N, L, C) SC_##C
13525 static enum neon_shape_class neon_shape_class
[] =
13544 /* Register widths of above. */
13545 static unsigned neon_shape_el_size
[] =
13557 struct neon_shape_info
13560 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
13563 #define S2(A,B) { SE_##A, SE_##B }
13564 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
13565 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
13567 #define X(N, L, C) { N, S##N L }
13569 static struct neon_shape_info neon_shape_tab
[] =
13579 /* Bit masks used in type checking given instructions.
13580 'N_EQK' means the type must be the same as (or based on in some way) the key
13581 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
13582 set, various other bits can be set as well in order to modify the meaning of
13583 the type constraint. */
13585 enum neon_type_mask
13609 N_KEY
= 0x1000000, /* Key element (main type specifier). */
13610 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
13611 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
13612 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
13613 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
13614 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
13615 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
13616 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
13617 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
13618 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
13619 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
13621 N_MAX_NONSPECIAL
= N_P64
13624 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
13626 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
13627 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
13628 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
13629 #define N_S_32 (N_S8 | N_S16 | N_S32)
13630 #define N_F_16_32 (N_F16 | N_F32)
13631 #define N_SUF_32 (N_SU_32 | N_F_16_32)
13632 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
13633 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
13634 #define N_F_ALL (N_F16 | N_F32 | N_F64)
13636 /* Pass this as the first type argument to neon_check_type to ignore types
13638 #define N_IGNORE_TYPE (N_KEY | N_EQK)
13640 /* Select a "shape" for the current instruction (describing register types or
13641 sizes) from a list of alternatives. Return NS_NULL if the current instruction
13642 doesn't fit. For non-polymorphic shapes, checking is usually done as a
13643 function of operand parsing, so this function doesn't need to be called.
13644 Shapes should be listed in order of decreasing length. */
13646 static enum neon_shape
13647 neon_select_shape (enum neon_shape shape
, ...)
13650 enum neon_shape first_shape
= shape
;
13652 /* Fix missing optional operands. FIXME: we don't know at this point how
13653 many arguments we should have, so this makes the assumption that we have
13654 > 1. This is true of all current Neon opcodes, I think, but may not be
13655 true in the future. */
13656 if (!inst
.operands
[1].present
)
13657 inst
.operands
[1] = inst
.operands
[0];
13659 va_start (ap
, shape
);
13661 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
13666 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
13668 if (!inst
.operands
[j
].present
)
13674 switch (neon_shape_tab
[shape
].el
[j
])
13676 /* If a .f16, .16, .u16, .s16 type specifier is given over
13677 a VFP single precision register operand, it's essentially
13678 means only half of the register is used.
13680 If the type specifier is given after the mnemonics, the
13681 information is stored in inst.vectype. If the type specifier
13682 is given after register operand, the information is stored
13683 in inst.operands[].vectype.
13685 When there is only one type specifier, and all the register
13686 operands are the same type of hardware register, the type
13687 specifier applies to all register operands.
13689 If no type specifier is given, the shape is inferred from
13690 operand information.
13693 vadd.f16 s0, s1, s2: NS_HHH
13694 vabs.f16 s0, s1: NS_HH
13695 vmov.f16 s0, r1: NS_HR
13696 vmov.f16 r0, s1: NS_RH
13697 vcvt.f16 r0, s1: NS_RH
13698 vcvt.f16.s32 s2, s2, #29: NS_HFI
13699 vcvt.f16.s32 s2, s2: NS_HF
13702 if (!(inst
.operands
[j
].isreg
13703 && inst
.operands
[j
].isvec
13704 && inst
.operands
[j
].issingle
13705 && !inst
.operands
[j
].isquad
13706 && ((inst
.vectype
.elems
== 1
13707 && inst
.vectype
.el
[0].size
== 16)
13708 || (inst
.vectype
.elems
> 1
13709 && inst
.vectype
.el
[j
].size
== 16)
13710 || (inst
.vectype
.elems
== 0
13711 && inst
.operands
[j
].vectype
.type
!= NT_invtype
13712 && inst
.operands
[j
].vectype
.size
== 16))))
13717 if (!(inst
.operands
[j
].isreg
13718 && inst
.operands
[j
].isvec
13719 && inst
.operands
[j
].issingle
13720 && !inst
.operands
[j
].isquad
13721 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
13722 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
13723 || (inst
.vectype
.elems
== 0
13724 && (inst
.operands
[j
].vectype
.size
== 32
13725 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
13730 if (!(inst
.operands
[j
].isreg
13731 && inst
.operands
[j
].isvec
13732 && !inst
.operands
[j
].isquad
13733 && !inst
.operands
[j
].issingle
))
13738 if (!(inst
.operands
[j
].isreg
13739 && !inst
.operands
[j
].isvec
))
13744 if (!(inst
.operands
[j
].isreg
13745 && inst
.operands
[j
].isvec
13746 && inst
.operands
[j
].isquad
13747 && !inst
.operands
[j
].issingle
))
13752 if (!(!inst
.operands
[j
].isreg
13753 && !inst
.operands
[j
].isscalar
))
13758 if (!(!inst
.operands
[j
].isreg
13759 && inst
.operands
[j
].isscalar
))
13769 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
13770 /* We've matched all the entries in the shape table, and we don't
13771 have any left over operands which have not been matched. */
13777 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
13778 first_error (_("invalid instruction shape"));
13783 /* True if SHAPE is predominantly a quadword operation (most of the time, this
13784 means the Q bit should be set). */
13787 neon_quad (enum neon_shape shape
)
13789 return neon_shape_class
[shape
] == SC_QUAD
;
13793 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
13796 /* Allow modification to be made to types which are constrained to be
13797 based on the key element, based on bits set alongside N_EQK. */
13798 if ((typebits
& N_EQK
) != 0)
13800 if ((typebits
& N_HLF
) != 0)
13802 else if ((typebits
& N_DBL
) != 0)
13804 if ((typebits
& N_SGN
) != 0)
13805 *g_type
= NT_signed
;
13806 else if ((typebits
& N_UNS
) != 0)
13807 *g_type
= NT_unsigned
;
13808 else if ((typebits
& N_INT
) != 0)
13809 *g_type
= NT_integer
;
13810 else if ((typebits
& N_FLT
) != 0)
13811 *g_type
= NT_float
;
13812 else if ((typebits
& N_SIZ
) != 0)
13813 *g_type
= NT_untyped
;
13817 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
13818 operand type, i.e. the single type specified in a Neon instruction when it
13819 is the only one given. */
13821 static struct neon_type_el
13822 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
13824 struct neon_type_el dest
= *key
;
13826 gas_assert ((thisarg
& N_EQK
) != 0);
13828 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
13833 /* Convert Neon type and size into compact bitmask representation. */
13835 static enum neon_type_mask
13836 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
13843 case 8: return N_8
;
13844 case 16: return N_16
;
13845 case 32: return N_32
;
13846 case 64: return N_64
;
13854 case 8: return N_I8
;
13855 case 16: return N_I16
;
13856 case 32: return N_I32
;
13857 case 64: return N_I64
;
13865 case 16: return N_F16
;
13866 case 32: return N_F32
;
13867 case 64: return N_F64
;
13875 case 8: return N_P8
;
13876 case 16: return N_P16
;
13877 case 64: return N_P64
;
13885 case 8: return N_S8
;
13886 case 16: return N_S16
;
13887 case 32: return N_S32
;
13888 case 64: return N_S64
;
13896 case 8: return N_U8
;
13897 case 16: return N_U16
;
13898 case 32: return N_U32
;
13899 case 64: return N_U64
;
13910 /* Convert compact Neon bitmask type representation to a type and size. Only
13911 handles the case where a single bit is set in the mask. */
13914 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
13915 enum neon_type_mask mask
)
13917 if ((mask
& N_EQK
) != 0)
13920 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
13922 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
13924 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
13926 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
13931 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
13933 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
13934 *type
= NT_unsigned
;
13935 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
13936 *type
= NT_integer
;
13937 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
13938 *type
= NT_untyped
;
13939 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
13941 else if ((mask
& (N_F_ALL
)) != 0)
13949 /* Modify a bitmask of allowed types. This is only needed for type
13953 modify_types_allowed (unsigned allowed
, unsigned mods
)
13956 enum neon_el_type type
;
13962 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
13964 if (el_type_of_type_chk (&type
, &size
,
13965 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
13967 neon_modify_type_size (mods
, &type
, &size
);
13968 destmask
|= type_chk_of_el_type (type
, size
);
13975 /* Check type and return type classification.
13976 The manual states (paraphrase): If one datatype is given, it indicates the
13978 - the second operand, if there is one
13979 - the operand, if there is no second operand
13980 - the result, if there are no operands.
13981 This isn't quite good enough though, so we use a concept of a "key" datatype
13982 which is set on a per-instruction basis, which is the one which matters when
13983 only one data type is written.
13984 Note: this function has side-effects (e.g. filling in missing operands). All
13985 Neon instructions should call it before performing bit encoding. */
13987 static struct neon_type_el
13988 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
13991 unsigned i
, pass
, key_el
= 0;
13992 unsigned types
[NEON_MAX_TYPE_ELS
];
13993 enum neon_el_type k_type
= NT_invtype
;
13994 unsigned k_size
= -1u;
13995 struct neon_type_el badtype
= {NT_invtype
, -1};
13996 unsigned key_allowed
= 0;
13998 /* Optional registers in Neon instructions are always (not) in operand 1.
13999 Fill in the missing operand here, if it was omitted. */
14000 if (els
> 1 && !inst
.operands
[1].present
)
14001 inst
.operands
[1] = inst
.operands
[0];
14003 /* Suck up all the varargs. */
14005 for (i
= 0; i
< els
; i
++)
14007 unsigned thisarg
= va_arg (ap
, unsigned);
14008 if (thisarg
== N_IGNORE_TYPE
)
14013 types
[i
] = thisarg
;
14014 if ((thisarg
& N_KEY
) != 0)
14019 if (inst
.vectype
.elems
> 0)
14020 for (i
= 0; i
< els
; i
++)
14021 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
14023 first_error (_("types specified in both the mnemonic and operands"));
14027 /* Duplicate inst.vectype elements here as necessary.
14028 FIXME: No idea if this is exactly the same as the ARM assembler,
14029 particularly when an insn takes one register and one non-register
14031 if (inst
.vectype
.elems
== 1 && els
> 1)
14034 inst
.vectype
.elems
= els
;
14035 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
14036 for (j
= 0; j
< els
; j
++)
14038 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14041 else if (inst
.vectype
.elems
== 0 && els
> 0)
14044 /* No types were given after the mnemonic, so look for types specified
14045 after each operand. We allow some flexibility here; as long as the
14046 "key" operand has a type, we can infer the others. */
14047 for (j
= 0; j
< els
; j
++)
14048 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
14049 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
14051 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
14053 for (j
= 0; j
< els
; j
++)
14054 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
14055 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
14060 first_error (_("operand types can't be inferred"));
14064 else if (inst
.vectype
.elems
!= els
)
14066 first_error (_("type specifier has the wrong number of parts"));
14070 for (pass
= 0; pass
< 2; pass
++)
14072 for (i
= 0; i
< els
; i
++)
14074 unsigned thisarg
= types
[i
];
14075 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
14076 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
14077 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
14078 unsigned g_size
= inst
.vectype
.el
[i
].size
;
14080 /* Decay more-specific signed & unsigned types to sign-insensitive
14081 integer types if sign-specific variants are unavailable. */
14082 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
14083 && (types_allowed
& N_SU_ALL
) == 0)
14084 g_type
= NT_integer
;
14086 /* If only untyped args are allowed, decay any more specific types to
14087 them. Some instructions only care about signs for some element
14088 sizes, so handle that properly. */
14089 if (((types_allowed
& N_UNT
) == 0)
14090 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
14091 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
14092 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
14093 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
14094 g_type
= NT_untyped
;
14098 if ((thisarg
& N_KEY
) != 0)
14102 key_allowed
= thisarg
& ~N_KEY
;
14104 /* Check architecture constraint on FP16 extension. */
14106 && k_type
== NT_float
14107 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14109 inst
.error
= _(BAD_FP16
);
14116 if ((thisarg
& N_VFP
) != 0)
14118 enum neon_shape_el regshape
;
14119 unsigned regwidth
, match
;
14121 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
14124 first_error (_("invalid instruction shape"));
14127 regshape
= neon_shape_tab
[ns
].el
[i
];
14128 regwidth
= neon_shape_el_size
[regshape
];
14130 /* In VFP mode, operands must match register widths. If we
14131 have a key operand, use its width, else use the width of
14132 the current operand. */
14138 /* FP16 will use a single precision register. */
14139 if (regwidth
== 32 && match
== 16)
14141 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
14145 inst
.error
= _(BAD_FP16
);
14150 if (regwidth
!= match
)
14152 first_error (_("operand size must match register width"));
14157 if ((thisarg
& N_EQK
) == 0)
14159 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
14161 if ((given_type
& types_allowed
) == 0)
14163 first_error (_("bad type in Neon instruction"));
14169 enum neon_el_type mod_k_type
= k_type
;
14170 unsigned mod_k_size
= k_size
;
14171 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
14172 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
14174 first_error (_("inconsistent types in Neon instruction"));
14182 return inst
.vectype
.el
[key_el
];
14185 /* Neon-style VFP instruction forwarding. */
14187 /* Thumb VFP instructions have 0xE in the condition field. */
14190 do_vfp_cond_or_thumb (void)
14195 inst
.instruction
|= 0xe0000000;
14197 inst
.instruction
|= inst
.cond
<< 28;
14200 /* Look up and encode a simple mnemonic, for use as a helper function for the
14201 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
14202 etc. It is assumed that operand parsing has already been done, and that the
14203 operands are in the form expected by the given opcode (this isn't necessarily
14204 the same as the form in which they were parsed, hence some massaging must
14205 take place before this function is called).
14206 Checks current arch version against that in the looked-up opcode. */
14209 do_vfp_nsyn_opcode (const char *opname
)
14211 const struct asm_opcode
*opcode
;
14213 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
14218 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
14219 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
14226 inst
.instruction
= opcode
->tvalue
;
14227 opcode
->tencode ();
14231 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
14232 opcode
->aencode ();
14237 do_vfp_nsyn_add_sub (enum neon_shape rs
)
14239 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
14241 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14244 do_vfp_nsyn_opcode ("fadds");
14246 do_vfp_nsyn_opcode ("fsubs");
14248 /* ARMv8.2 fp16 instruction. */
14250 do_scalar_fp16_v82_encode ();
14255 do_vfp_nsyn_opcode ("faddd");
14257 do_vfp_nsyn_opcode ("fsubd");
14261 /* Check operand types to see if this is a VFP instruction, and if so call
14265 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
14267 enum neon_shape rs
;
14268 struct neon_type_el et
;
14273 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14274 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14278 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14279 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14280 N_F_ALL
| N_KEY
| N_VFP
);
14287 if (et
.type
!= NT_invtype
)
14298 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
14300 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
14302 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14305 do_vfp_nsyn_opcode ("fmacs");
14307 do_vfp_nsyn_opcode ("fnmacs");
14309 /* ARMv8.2 fp16 instruction. */
14311 do_scalar_fp16_v82_encode ();
14316 do_vfp_nsyn_opcode ("fmacd");
14318 do_vfp_nsyn_opcode ("fnmacd");
14323 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
14325 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
14327 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14330 do_vfp_nsyn_opcode ("ffmas");
14332 do_vfp_nsyn_opcode ("ffnmas");
14334 /* ARMv8.2 fp16 instruction. */
14336 do_scalar_fp16_v82_encode ();
14341 do_vfp_nsyn_opcode ("ffmad");
14343 do_vfp_nsyn_opcode ("ffnmad");
14348 do_vfp_nsyn_mul (enum neon_shape rs
)
14350 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14352 do_vfp_nsyn_opcode ("fmuls");
14354 /* ARMv8.2 fp16 instruction. */
14356 do_scalar_fp16_v82_encode ();
14359 do_vfp_nsyn_opcode ("fmuld");
14363 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
14365 int is_neg
= (inst
.instruction
& 0x80) != 0;
14366 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
14368 if (rs
== NS_FF
|| rs
== NS_HH
)
14371 do_vfp_nsyn_opcode ("fnegs");
14373 do_vfp_nsyn_opcode ("fabss");
14375 /* ARMv8.2 fp16 instruction. */
14377 do_scalar_fp16_v82_encode ();
14382 do_vfp_nsyn_opcode ("fnegd");
14384 do_vfp_nsyn_opcode ("fabsd");
14388 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
14389 insns belong to Neon, and are handled elsewhere. */
14392 do_vfp_nsyn_ldm_stm (int is_dbmode
)
14394 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
14398 do_vfp_nsyn_opcode ("fldmdbs");
14400 do_vfp_nsyn_opcode ("fldmias");
14405 do_vfp_nsyn_opcode ("fstmdbs");
14407 do_vfp_nsyn_opcode ("fstmias");
14412 do_vfp_nsyn_sqrt (void)
14414 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14415 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14417 if (rs
== NS_FF
|| rs
== NS_HH
)
14419 do_vfp_nsyn_opcode ("fsqrts");
14421 /* ARMv8.2 fp16 instruction. */
14423 do_scalar_fp16_v82_encode ();
14426 do_vfp_nsyn_opcode ("fsqrtd");
14430 do_vfp_nsyn_div (void)
14432 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14433 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14434 N_F_ALL
| N_KEY
| N_VFP
);
14436 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14438 do_vfp_nsyn_opcode ("fdivs");
14440 /* ARMv8.2 fp16 instruction. */
14442 do_scalar_fp16_v82_encode ();
14445 do_vfp_nsyn_opcode ("fdivd");
14449 do_vfp_nsyn_nmul (void)
14451 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
14452 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
14453 N_F_ALL
| N_KEY
| N_VFP
);
14455 if (rs
== NS_FFF
|| rs
== NS_HHH
)
14457 NEON_ENCODE (SINGLE
, inst
);
14458 do_vfp_sp_dyadic ();
14460 /* ARMv8.2 fp16 instruction. */
14462 do_scalar_fp16_v82_encode ();
14466 NEON_ENCODE (DOUBLE
, inst
);
14467 do_vfp_dp_rd_rn_rm ();
14469 do_vfp_cond_or_thumb ();
14474 do_vfp_nsyn_cmp (void)
14476 enum neon_shape rs
;
14477 if (inst
.operands
[1].isreg
)
14479 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
14480 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
14482 if (rs
== NS_FF
|| rs
== NS_HH
)
14484 NEON_ENCODE (SINGLE
, inst
);
14485 do_vfp_sp_monadic ();
14489 NEON_ENCODE (DOUBLE
, inst
);
14490 do_vfp_dp_rd_rm ();
14495 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
14496 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
14498 switch (inst
.instruction
& 0x0fffffff)
14501 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
14504 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
14510 if (rs
== NS_FI
|| rs
== NS_HI
)
14512 NEON_ENCODE (SINGLE
, inst
);
14513 do_vfp_sp_compare_z ();
14517 NEON_ENCODE (DOUBLE
, inst
);
14521 do_vfp_cond_or_thumb ();
14523 /* ARMv8.2 fp16 instruction. */
14524 if (rs
== NS_HI
|| rs
== NS_HH
)
14525 do_scalar_fp16_v82_encode ();
14529 nsyn_insert_sp (void)
14531 inst
.operands
[1] = inst
.operands
[0];
14532 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
14533 inst
.operands
[0].reg
= REG_SP
;
14534 inst
.operands
[0].isreg
= 1;
14535 inst
.operands
[0].writeback
= 1;
14536 inst
.operands
[0].present
= 1;
14540 do_vfp_nsyn_push (void)
14544 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14545 _("register list must contain at least 1 and at most 16 "
14548 if (inst
.operands
[1].issingle
)
14549 do_vfp_nsyn_opcode ("fstmdbs");
14551 do_vfp_nsyn_opcode ("fstmdbd");
14555 do_vfp_nsyn_pop (void)
14559 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
14560 _("register list must contain at least 1 and at most 16 "
14563 if (inst
.operands
[1].issingle
)
14564 do_vfp_nsyn_opcode ("fldmias");
14566 do_vfp_nsyn_opcode ("fldmiad");
14569 /* Fix up Neon data-processing instructions, ORing in the correct bits for
14570 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
14573 neon_dp_fixup (struct arm_it
* insn
)
14575 unsigned int i
= insn
->instruction
;
14580 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
14591 insn
->instruction
= i
;
14594 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
14598 neon_logbits (unsigned x
)
14600 return ffs (x
) - 4;
14603 #define LOW4(R) ((R) & 0xf)
14604 #define HI1(R) (((R) >> 4) & 1)
14606 /* Encode insns with bit pattern:
14608 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
14609 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
14611 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
14612 different meaning for some instruction. */
14615 neon_three_same (int isquad
, int ubit
, int size
)
14617 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14618 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14619 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
14620 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
14621 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
14622 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
14623 inst
.instruction
|= (isquad
!= 0) << 6;
14624 inst
.instruction
|= (ubit
!= 0) << 24;
14626 inst
.instruction
|= neon_logbits (size
) << 20;
14628 neon_dp_fixup (&inst
);
14631 /* Encode instructions of the form:
14633 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
14634 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
14636 Don't write size if SIZE == -1. */
14639 neon_two_same (int qbit
, int ubit
, int size
)
14641 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14642 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14643 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14644 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14645 inst
.instruction
|= (qbit
!= 0) << 6;
14646 inst
.instruction
|= (ubit
!= 0) << 24;
14649 inst
.instruction
|= neon_logbits (size
) << 18;
14651 neon_dp_fixup (&inst
);
14654 /* Neon instruction encoders, in approximate order of appearance. */
14657 do_neon_dyadic_i_su (void)
14659 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14660 struct neon_type_el et
= neon_check_type (3, rs
,
14661 N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
14662 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14666 do_neon_dyadic_i64_su (void)
14668 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14669 struct neon_type_el et
= neon_check_type (3, rs
,
14670 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14671 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14675 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
14678 unsigned size
= et
.size
>> 3;
14679 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14680 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14681 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
14682 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
14683 inst
.instruction
|= (isquad
!= 0) << 6;
14684 inst
.instruction
|= immbits
<< 16;
14685 inst
.instruction
|= (size
>> 3) << 7;
14686 inst
.instruction
|= (size
& 0x7) << 19;
14688 inst
.instruction
|= (uval
!= 0) << 24;
14690 neon_dp_fixup (&inst
);
14694 do_neon_shl_imm (void)
14696 if (!inst
.operands
[2].isreg
)
14698 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14699 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
14700 int imm
= inst
.operands
[2].imm
;
14702 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14703 _("immediate out of range for shift"));
14704 NEON_ENCODE (IMMED
, inst
);
14705 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
14709 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14710 struct neon_type_el et
= neon_check_type (3, rs
,
14711 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14714 /* VSHL/VQSHL 3-register variants have syntax such as:
14716 whereas other 3-register operations encoded by neon_three_same have
14719 (i.e. with Dn & Dm reversed). Swap operands[1].reg and operands[2].reg
14721 tmp
= inst
.operands
[2].reg
;
14722 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14723 inst
.operands
[1].reg
= tmp
;
14724 NEON_ENCODE (INTEGER
, inst
);
14725 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14730 do_neon_qshl_imm (void)
14732 if (!inst
.operands
[2].isreg
)
14734 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
14735 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
14736 int imm
= inst
.operands
[2].imm
;
14738 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
14739 _("immediate out of range for shift"));
14740 NEON_ENCODE (IMMED
, inst
);
14741 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
14745 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14746 struct neon_type_el et
= neon_check_type (3, rs
,
14747 N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
14750 /* See note in do_neon_shl_imm. */
14751 tmp
= inst
.operands
[2].reg
;
14752 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14753 inst
.operands
[1].reg
= tmp
;
14754 NEON_ENCODE (INTEGER
, inst
);
14755 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14760 do_neon_rshl (void)
14762 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14763 struct neon_type_el et
= neon_check_type (3, rs
,
14764 N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
14767 tmp
= inst
.operands
[2].reg
;
14768 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
14769 inst
.operands
[1].reg
= tmp
;
14770 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
14774 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
14776 /* Handle .I8 pseudo-instructions. */
14779 /* Unfortunately, this will make everything apart from zero out-of-range.
14780 FIXME is this the intended semantics? There doesn't seem much point in
14781 accepting .I8 if so. */
14782 immediate
|= immediate
<< 8;
14788 if (immediate
== (immediate
& 0x000000ff))
14790 *immbits
= immediate
;
14793 else if (immediate
== (immediate
& 0x0000ff00))
14795 *immbits
= immediate
>> 8;
14798 else if (immediate
== (immediate
& 0x00ff0000))
14800 *immbits
= immediate
>> 16;
14803 else if (immediate
== (immediate
& 0xff000000))
14805 *immbits
= immediate
>> 24;
14808 if ((immediate
& 0xffff) != (immediate
>> 16))
14809 goto bad_immediate
;
14810 immediate
&= 0xffff;
14813 if (immediate
== (immediate
& 0x000000ff))
14815 *immbits
= immediate
;
14818 else if (immediate
== (immediate
& 0x0000ff00))
14820 *immbits
= immediate
>> 8;
14825 first_error (_("immediate value out of range"));
14830 do_neon_logic (void)
14832 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
14834 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14835 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14836 /* U bit and size field were set as part of the bitmask. */
14837 NEON_ENCODE (INTEGER
, inst
);
14838 neon_three_same (neon_quad (rs
), 0, -1);
14842 const int three_ops_form
= (inst
.operands
[2].present
14843 && !inst
.operands
[2].isreg
);
14844 const int immoperand
= (three_ops_form
? 2 : 1);
14845 enum neon_shape rs
= (three_ops_form
14846 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
14847 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
14848 struct neon_type_el et
= neon_check_type (2, rs
,
14849 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
14850 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
14854 if (et
.type
== NT_invtype
)
14857 if (three_ops_form
)
14858 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
14859 _("first and second operands shall be the same register"));
14861 NEON_ENCODE (IMMED
, inst
);
14863 immbits
= inst
.operands
[immoperand
].imm
;
14866 /* .i64 is a pseudo-op, so the immediate must be a repeating
14868 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
14869 inst
.operands
[immoperand
].reg
: 0))
14871 /* Set immbits to an invalid constant. */
14872 immbits
= 0xdeadbeef;
14879 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14883 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14887 /* Pseudo-instruction for VBIC. */
14888 neon_invert_size (&immbits
, 0, et
.size
);
14889 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14893 /* Pseudo-instruction for VORR. */
14894 neon_invert_size (&immbits
, 0, et
.size
);
14895 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
14905 inst
.instruction
|= neon_quad (rs
) << 6;
14906 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
14907 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
14908 inst
.instruction
|= cmode
<< 8;
14909 neon_write_immbits (immbits
);
14911 neon_dp_fixup (&inst
);
14916 do_neon_bitfield (void)
14918 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14919 neon_check_type (3, rs
, N_IGNORE_TYPE
);
14920 neon_three_same (neon_quad (rs
), 0, -1);
14924 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
14927 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
14928 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
14930 if (et
.type
== NT_float
)
14932 NEON_ENCODE (FLOAT
, inst
);
14933 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
14937 NEON_ENCODE (INTEGER
, inst
);
14938 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
14943 do_neon_dyadic_if_su (void)
14945 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14949 do_neon_dyadic_if_su_d (void)
14951 /* This version only allow D registers, but that constraint is enforced during
14952 operand parsing so we don't need to do anything extra here. */
14953 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
14957 do_neon_dyadic_if_i_d (void)
14959 /* The "untyped" case can't happen. Do this to stop the "U" bit being
14960 affected if we specify unsigned args. */
14961 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
14964 enum vfp_or_neon_is_neon_bits
14967 NEON_CHECK_ARCH
= 2,
14968 NEON_CHECK_ARCH8
= 4
14971 /* Call this function if an instruction which may have belonged to the VFP or
14972 Neon instruction sets, but turned out to be a Neon instruction (due to the
14973 operand types involved, etc.). We have to check and/or fix-up a couple of
14976 - Make sure the user hasn't attempted to make a Neon instruction
14978 - Alter the value in the condition code field if necessary.
14979 - Make sure that the arch supports Neon instructions.
14981 Which of these operations take place depends on bits from enum
14982 vfp_or_neon_is_neon_bits.
14984 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
14985 current instruction's condition is COND_ALWAYS, the condition field is
14986 changed to inst.uncond_value. This is necessary because instructions shared
14987 between VFP and Neon may be conditional for the VFP variants only, and the
14988 unconditional Neon version must have, e.g., 0xF in the condition field. */
14991 vfp_or_neon_is_neon (unsigned check
)
14993 /* Conditions are always legal in Thumb mode (IT blocks). */
14994 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
14996 if (inst
.cond
!= COND_ALWAYS
)
14998 first_error (_(BAD_COND
));
15001 if (inst
.uncond_value
!= -1)
15002 inst
.instruction
|= inst
.uncond_value
<< 28;
15005 if ((check
& NEON_CHECK_ARCH
)
15006 && !mark_feature_used (&fpu_neon_ext_v1
))
15008 first_error (_(BAD_FPU
));
15012 if ((check
& NEON_CHECK_ARCH8
)
15013 && !mark_feature_used (&fpu_neon_ext_armv8
))
15015 first_error (_(BAD_FPU
));
15023 do_neon_addsub_if_i (void)
15025 if (try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
15028 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15031 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15032 affected if we specify unsigned args. */
15033 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
15036 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
15038 V<op> A,B (A is operand 0, B is operand 2)
15043 so handle that case specially. */
15046 neon_exchange_operands (void)
15048 if (inst
.operands
[1].present
)
15050 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
15052 /* Swap operands[1] and operands[2]. */
15053 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
15054 inst
.operands
[1] = inst
.operands
[2];
15055 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
15060 inst
.operands
[1] = inst
.operands
[2];
15061 inst
.operands
[2] = inst
.operands
[0];
15066 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
15068 if (inst
.operands
[2].isreg
)
15071 neon_exchange_operands ();
15072 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
15076 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15077 struct neon_type_el et
= neon_check_type (2, rs
,
15078 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
15080 NEON_ENCODE (IMMED
, inst
);
15081 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15082 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15083 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15084 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15085 inst
.instruction
|= neon_quad (rs
) << 6;
15086 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15087 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15089 neon_dp_fixup (&inst
);
15096 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
15100 do_neon_cmp_inv (void)
15102 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
15108 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
15111 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
15112 scalars, which are encoded in 5 bits, M : Rm.
15113 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
15114 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
15117 Dot Product instructions are similar to multiply instructions except elsize
15118 should always be 32.
15120 This function translates SCALAR, which is GAS's internal encoding of indexed
15121 scalar register, to raw encoding. There is also register and index range
15122 check based on ELSIZE. */
15125 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
15127 unsigned regno
= NEON_SCALAR_REG (scalar
);
15128 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
15133 if (regno
> 7 || elno
> 3)
15135 return regno
| (elno
<< 3);
15138 if (regno
> 15 || elno
> 1)
15140 return regno
| (elno
<< 4);
15144 first_error (_("scalar out of range for multiply instruction"));
15150 /* Encode multiply / multiply-accumulate scalar instructions. */
15153 neon_mul_mac (struct neon_type_el et
, int ubit
)
15157 /* Give a more helpful error message if we have an invalid type. */
15158 if (et
.type
== NT_invtype
)
15161 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
15162 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15163 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15164 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15165 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15166 inst
.instruction
|= LOW4 (scalar
);
15167 inst
.instruction
|= HI1 (scalar
) << 5;
15168 inst
.instruction
|= (et
.type
== NT_float
) << 8;
15169 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15170 inst
.instruction
|= (ubit
!= 0) << 24;
15172 neon_dp_fixup (&inst
);
15176 do_neon_mac_maybe_scalar (void)
15178 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
15181 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15184 if (inst
.operands
[2].isscalar
)
15186 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15187 struct neon_type_el et
= neon_check_type (3, rs
,
15188 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
15189 NEON_ENCODE (SCALAR
, inst
);
15190 neon_mul_mac (et
, neon_quad (rs
));
15194 /* The "untyped" case can't happen. Do this to stop the "U" bit being
15195 affected if we specify unsigned args. */
15196 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15201 do_neon_fmac (void)
15203 if (try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
15206 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15209 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
15215 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15216 struct neon_type_el et
= neon_check_type (3, rs
,
15217 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
15218 neon_three_same (neon_quad (rs
), 0, et
.size
);
15221 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
15222 same types as the MAC equivalents. The polynomial type for this instruction
15223 is encoded the same as the integer type. */
15228 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
15231 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15234 if (inst
.operands
[2].isscalar
)
15235 do_neon_mac_maybe_scalar ();
15237 neon_dyadic_misc (NT_poly
, N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
15241 do_neon_qdmulh (void)
15243 if (inst
.operands
[2].isscalar
)
15245 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15246 struct neon_type_el et
= neon_check_type (3, rs
,
15247 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15248 NEON_ENCODE (SCALAR
, inst
);
15249 neon_mul_mac (et
, neon_quad (rs
));
15253 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15254 struct neon_type_el et
= neon_check_type (3, rs
,
15255 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15256 NEON_ENCODE (INTEGER
, inst
);
15257 /* The U bit (rounding) comes from bit mask. */
15258 neon_three_same (neon_quad (rs
), 0, et
.size
);
15263 do_neon_qrdmlah (void)
15265 /* Check we're on the correct architecture. */
15266 if (!mark_feature_used (&fpu_neon_ext_armv8
))
15268 _("instruction form not available on this architecture.");
15269 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
15271 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
15272 record_feature_use (&fpu_neon_ext_v8_1
);
15275 if (inst
.operands
[2].isscalar
)
15277 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
15278 struct neon_type_el et
= neon_check_type (3, rs
,
15279 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15280 NEON_ENCODE (SCALAR
, inst
);
15281 neon_mul_mac (et
, neon_quad (rs
));
15285 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15286 struct neon_type_el et
= neon_check_type (3, rs
,
15287 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
15288 NEON_ENCODE (INTEGER
, inst
);
15289 /* The U bit (rounding) comes from bit mask. */
15290 neon_three_same (neon_quad (rs
), 0, et
.size
);
15295 do_neon_fcmp_absolute (void)
15297 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15298 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15299 N_F_16_32
| N_KEY
);
15300 /* Size field comes from bit mask. */
15301 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
15305 do_neon_fcmp_absolute_inv (void)
15307 neon_exchange_operands ();
15308 do_neon_fcmp_absolute ();
15312 do_neon_step (void)
15314 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
15315 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
15316 N_F_16_32
| N_KEY
);
15317 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
15321 do_neon_abs_neg (void)
15323 enum neon_shape rs
;
15324 struct neon_type_el et
;
15326 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
15329 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15332 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
15333 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
15335 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15336 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15337 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15338 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15339 inst
.instruction
|= neon_quad (rs
) << 6;
15340 inst
.instruction
|= (et
.type
== NT_float
) << 10;
15341 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15343 neon_dp_fixup (&inst
);
15349 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15350 struct neon_type_el et
= neon_check_type (2, rs
,
15351 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15352 int imm
= inst
.operands
[2].imm
;
15353 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15354 _("immediate out of range for insert"));
15355 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15361 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15362 struct neon_type_el et
= neon_check_type (2, rs
,
15363 N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
15364 int imm
= inst
.operands
[2].imm
;
15365 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15366 _("immediate out of range for insert"));
15367 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
15371 do_neon_qshlu_imm (void)
15373 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
15374 struct neon_type_el et
= neon_check_type (2, rs
,
15375 N_EQK
| N_UNS
, N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
15376 int imm
= inst
.operands
[2].imm
;
15377 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
15378 _("immediate out of range for shift"));
15379 /* Only encodes the 'U present' variant of the instruction.
15380 In this case, signed types have OP (bit 8) set to 0.
15381 Unsigned types have OP set to 1. */
15382 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
15383 /* The rest of the bits are the same as other immediate shifts. */
15384 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
15388 do_neon_qmovn (void)
15390 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15391 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15392 /* Saturating move where operands can be signed or unsigned, and the
15393 destination has the same signedness. */
15394 NEON_ENCODE (INTEGER
, inst
);
15395 if (et
.type
== NT_unsigned
)
15396 inst
.instruction
|= 0xc0;
15398 inst
.instruction
|= 0x80;
15399 neon_two_same (0, 1, et
.size
/ 2);
15403 do_neon_qmovun (void)
15405 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15406 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15407 /* Saturating move with unsigned results. Operands must be signed. */
15408 NEON_ENCODE (INTEGER
, inst
);
15409 neon_two_same (0, 1, et
.size
/ 2);
15413 do_neon_rshift_sat_narrow (void)
15415 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15416 or unsigned. If operands are unsigned, results must also be unsigned. */
15417 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15418 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
15419 int imm
= inst
.operands
[2].imm
;
15420 /* This gets the bounds check, size encoding and immediate bits calculation
15424 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
15425 VQMOVN.I<size> <Dd>, <Qm>. */
15428 inst
.operands
[2].present
= 0;
15429 inst
.instruction
= N_MNEM_vqmovn
;
15434 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15435 _("immediate out of range"));
15436 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
15440 do_neon_rshift_sat_narrow_u (void)
15442 /* FIXME: Types for narrowing. If operands are signed, results can be signed
15443 or unsigned. If operands are unsigned, results must also be unsigned. */
15444 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15445 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
15446 int imm
= inst
.operands
[2].imm
;
15447 /* This gets the bounds check, size encoding and immediate bits calculation
15451 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
15452 VQMOVUN.I<size> <Dd>, <Qm>. */
15455 inst
.operands
[2].present
= 0;
15456 inst
.instruction
= N_MNEM_vqmovun
;
15461 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15462 _("immediate out of range"));
15463 /* FIXME: The manual is kind of unclear about what value U should have in
15464 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
15466 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
15470 do_neon_movn (void)
15472 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
15473 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15474 NEON_ENCODE (INTEGER
, inst
);
15475 neon_two_same (0, 1, et
.size
/ 2);
15479 do_neon_rshift_narrow (void)
15481 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
15482 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
15483 int imm
= inst
.operands
[2].imm
;
15484 /* This gets the bounds check, size encoding and immediate bits calculation
15488 /* If immediate is zero then we are a pseudo-instruction for
15489 VMOVN.I<size> <Dd>, <Qm> */
15492 inst
.operands
[2].present
= 0;
15493 inst
.instruction
= N_MNEM_vmovn
;
15498 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
15499 _("immediate out of range for narrowing operation"));
15500 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
15504 do_neon_shll (void)
15506 /* FIXME: Type checking when lengthening. */
15507 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
15508 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
15509 unsigned imm
= inst
.operands
[2].imm
;
15511 if (imm
== et
.size
)
15513 /* Maximum shift variant. */
15514 NEON_ENCODE (INTEGER
, inst
);
15515 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15516 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15517 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15518 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15519 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15521 neon_dp_fixup (&inst
);
15525 /* A more-specific type check for non-max versions. */
15526 et
= neon_check_type (2, NS_QDI
,
15527 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
15528 NEON_ENCODE (IMMED
, inst
);
15529 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
15533 /* Check the various types for the VCVT instruction, and return which version
15534 the current instruction is. */
15536 #define CVT_FLAVOUR_VAR \
15537 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
15538 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
15539 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
15540 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
15541 /* Half-precision conversions. */ \
15542 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15543 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
15544 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
15545 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
15546 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
15547 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
15548 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
15549 Compared with single/double precision variants, only the co-processor \
15550 field is different, so the encoding flow is reused here. */ \
15551 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
15552 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
15553 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
15554 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
15555 /* VFP instructions. */ \
15556 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
15557 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
15558 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
15559 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
15560 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
15561 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
15562 /* VFP instructions with bitshift. */ \
15563 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
15564 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
15565 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
15566 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
15567 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
15568 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
15569 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
15570 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
15572 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
15573 neon_cvt_flavour_##C,
15575 /* The different types of conversions we can do. */
15576 enum neon_cvt_flavour
15579 neon_cvt_flavour_invalid
,
15580 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
15585 static enum neon_cvt_flavour
15586 get_neon_cvt_flavour (enum neon_shape rs
)
15588 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
15589 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
15590 if (et.type != NT_invtype) \
15592 inst.error = NULL; \
15593 return (neon_cvt_flavour_##C); \
15596 struct neon_type_el et
;
15597 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
15598 || rs
== NS_FF
) ? N_VFP
: 0;
15599 /* The instruction versions which take an immediate take one register
15600 argument, which is extended to the width of the full register. Thus the
15601 "source" and "destination" registers must have the same width. Hack that
15602 here by making the size equal to the key (wider, in this case) operand. */
15603 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
15607 return neon_cvt_flavour_invalid
;
15622 /* Neon-syntax VFP conversions. */
15625 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
15627 const char *opname
= 0;
15629 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
15630 || rs
== NS_FHI
|| rs
== NS_HFI
)
15632 /* Conversions with immediate bitshift. */
15633 const char *enc
[] =
15635 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
15641 if (flavour
< (int) ARRAY_SIZE (enc
))
15643 opname
= enc
[flavour
];
15644 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
15645 _("operands 0 and 1 must be the same register"));
15646 inst
.operands
[1] = inst
.operands
[2];
15647 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
15652 /* Conversions without bitshift. */
15653 const char *enc
[] =
15655 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
15661 if (flavour
< (int) ARRAY_SIZE (enc
))
15662 opname
= enc
[flavour
];
15666 do_vfp_nsyn_opcode (opname
);
15668 /* ARMv8.2 fp16 VCVT instruction. */
15669 if (flavour
== neon_cvt_flavour_s32_f16
15670 || flavour
== neon_cvt_flavour_u32_f16
15671 || flavour
== neon_cvt_flavour_f16_u32
15672 || flavour
== neon_cvt_flavour_f16_s32
)
15673 do_scalar_fp16_v82_encode ();
15677 do_vfp_nsyn_cvtz (void)
15679 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
15680 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15681 const char *enc
[] =
15683 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
15689 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
15690 do_vfp_nsyn_opcode (enc
[flavour
]);
15694 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
15695 enum neon_cvt_mode mode
)
15700 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
15701 D register operands. */
15702 if (flavour
== neon_cvt_flavour_s32_f64
15703 || flavour
== neon_cvt_flavour_u32_f64
)
15704 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
15707 if (flavour
== neon_cvt_flavour_s32_f16
15708 || flavour
== neon_cvt_flavour_u32_f16
)
15709 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
15712 set_it_insn_type (OUTSIDE_IT_INSN
);
15716 case neon_cvt_flavour_s32_f64
:
15720 case neon_cvt_flavour_s32_f32
:
15724 case neon_cvt_flavour_s32_f16
:
15728 case neon_cvt_flavour_u32_f64
:
15732 case neon_cvt_flavour_u32_f32
:
15736 case neon_cvt_flavour_u32_f16
:
15741 first_error (_("invalid instruction shape"));
15747 case neon_cvt_mode_a
: rm
= 0; break;
15748 case neon_cvt_mode_n
: rm
= 1; break;
15749 case neon_cvt_mode_p
: rm
= 2; break;
15750 case neon_cvt_mode_m
: rm
= 3; break;
15751 default: first_error (_("invalid rounding mode")); return;
15754 NEON_ENCODE (FPV8
, inst
);
15755 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
15756 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
15757 inst
.instruction
|= sz
<< 8;
15759 /* ARMv8.2 fp16 VCVT instruction. */
15760 if (flavour
== neon_cvt_flavour_s32_f16
15761 ||flavour
== neon_cvt_flavour_u32_f16
)
15762 do_scalar_fp16_v82_encode ();
15763 inst
.instruction
|= op
<< 7;
15764 inst
.instruction
|= rm
<< 16;
15765 inst
.instruction
|= 0xf0000000;
15766 inst
.is_neon
= TRUE
;
15770 do_neon_cvt_1 (enum neon_cvt_mode mode
)
15772 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
15773 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
15774 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
15776 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
15778 if (flavour
== neon_cvt_flavour_invalid
)
15781 /* PR11109: Handle round-to-zero for VCVT conversions. */
15782 if (mode
== neon_cvt_mode_z
15783 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
15784 && (flavour
== neon_cvt_flavour_s16_f16
15785 || flavour
== neon_cvt_flavour_u16_f16
15786 || flavour
== neon_cvt_flavour_s32_f32
15787 || flavour
== neon_cvt_flavour_u32_f32
15788 || flavour
== neon_cvt_flavour_s32_f64
15789 || flavour
== neon_cvt_flavour_u32_f64
)
15790 && (rs
== NS_FD
|| rs
== NS_FF
))
15792 do_vfp_nsyn_cvtz ();
15796 /* ARMv8.2 fp16 VCVT conversions. */
15797 if (mode
== neon_cvt_mode_z
15798 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
15799 && (flavour
== neon_cvt_flavour_s32_f16
15800 || flavour
== neon_cvt_flavour_u32_f16
)
15803 do_vfp_nsyn_cvtz ();
15804 do_scalar_fp16_v82_encode ();
15808 /* VFP rather than Neon conversions. */
15809 if (flavour
>= neon_cvt_flavour_first_fp
)
15811 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15812 do_vfp_nsyn_cvt (rs
, flavour
);
15814 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15825 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
15826 0x0000100, 0x1000100, 0x0, 0x1000000};
15828 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15831 /* Fixed-point conversion with #0 immediate is encoded as an
15832 integer conversion. */
15833 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
15835 NEON_ENCODE (IMMED
, inst
);
15836 if (flavour
!= neon_cvt_flavour_invalid
)
15837 inst
.instruction
|= enctab
[flavour
];
15838 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15839 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15840 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15841 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15842 inst
.instruction
|= neon_quad (rs
) << 6;
15843 inst
.instruction
|= 1 << 21;
15844 if (flavour
< neon_cvt_flavour_s16_f16
)
15846 inst
.instruction
|= 1 << 21;
15847 immbits
= 32 - inst
.operands
[2].imm
;
15848 inst
.instruction
|= immbits
<< 16;
15852 inst
.instruction
|= 3 << 20;
15853 immbits
= 16 - inst
.operands
[2].imm
;
15854 inst
.instruction
|= immbits
<< 16;
15855 inst
.instruction
&= ~(1 << 9);
15858 neon_dp_fixup (&inst
);
15864 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
15866 NEON_ENCODE (FLOAT
, inst
);
15867 set_it_insn_type (OUTSIDE_IT_INSN
);
15869 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
15872 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15873 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15874 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15875 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15876 inst
.instruction
|= neon_quad (rs
) << 6;
15877 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
15878 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
15879 inst
.instruction
|= mode
<< 8;
15880 if (flavour
== neon_cvt_flavour_u16_f16
15881 || flavour
== neon_cvt_flavour_s16_f16
)
15882 /* Mask off the original size bits and reencode them. */
15883 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
15886 inst
.instruction
|= 0xfc000000;
15888 inst
.instruction
|= 0xf0000000;
15894 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
15895 0x100, 0x180, 0x0, 0x080};
15897 NEON_ENCODE (INTEGER
, inst
);
15899 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
15902 if (flavour
!= neon_cvt_flavour_invalid
)
15903 inst
.instruction
|= enctab
[flavour
];
15905 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15906 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15907 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15908 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15909 inst
.instruction
|= neon_quad (rs
) << 6;
15910 if (flavour
>= neon_cvt_flavour_s16_f16
15911 && flavour
<= neon_cvt_flavour_f16_u16
)
15912 /* Half precision. */
15913 inst
.instruction
|= 1 << 18;
15915 inst
.instruction
|= 2 << 18;
15917 neon_dp_fixup (&inst
);
15922 /* Half-precision conversions for Advanced SIMD -- neon. */
15927 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
15929 as_bad (_("operand size must match register width"));
15934 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
15936 as_bad (_("operand size must match register width"));
15941 inst
.instruction
= 0x3b60600;
15943 inst
.instruction
= 0x3b60700;
15945 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15946 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15947 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15948 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15949 neon_dp_fixup (&inst
);
15953 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
15954 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
15955 do_vfp_nsyn_cvt (rs
, flavour
);
15957 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
15962 do_neon_cvtr (void)
15964 do_neon_cvt_1 (neon_cvt_mode_x
);
15970 do_neon_cvt_1 (neon_cvt_mode_z
);
15974 do_neon_cvta (void)
15976 do_neon_cvt_1 (neon_cvt_mode_a
);
15980 do_neon_cvtn (void)
15982 do_neon_cvt_1 (neon_cvt_mode_n
);
15986 do_neon_cvtp (void)
15988 do_neon_cvt_1 (neon_cvt_mode_p
);
15992 do_neon_cvtm (void)
15994 do_neon_cvt_1 (neon_cvt_mode_m
);
15998 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
16001 mark_feature_used (&fpu_vfp_ext_armv8
);
16003 encode_arm_vfp_reg (inst
.operands
[0].reg
,
16004 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
16005 encode_arm_vfp_reg (inst
.operands
[1].reg
,
16006 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
16007 inst
.instruction
|= to
? 0x10000 : 0;
16008 inst
.instruction
|= t
? 0x80 : 0;
16009 inst
.instruction
|= is_double
? 0x100 : 0;
16010 do_vfp_cond_or_thumb ();
16014 do_neon_cvttb_1 (bfd_boolean t
)
16016 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
16017 NS_DF
, NS_DH
, NS_NULL
);
16021 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
16024 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
16026 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
16029 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
16031 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
16033 /* The VCVTB and VCVTT instructions with D-register operands
16034 don't work for SP only targets. */
16035 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16039 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
16041 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
16043 /* The VCVTB and VCVTT instructions with D-register operands
16044 don't work for SP only targets. */
16045 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16049 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
16056 do_neon_cvtb (void)
16058 do_neon_cvttb_1 (FALSE
);
16063 do_neon_cvtt (void)
16065 do_neon_cvttb_1 (TRUE
);
16069 neon_move_immediate (void)
16071 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
16072 struct neon_type_el et
= neon_check_type (2, rs
,
16073 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
16074 unsigned immlo
, immhi
= 0, immbits
;
16075 int op
, cmode
, float_p
;
16077 constraint (et
.type
== NT_invtype
,
16078 _("operand size must be specified for immediate VMOV"));
16080 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
16081 op
= (inst
.instruction
& (1 << 5)) != 0;
16083 immlo
= inst
.operands
[1].imm
;
16084 if (inst
.operands
[1].regisimm
)
16085 immhi
= inst
.operands
[1].reg
;
16087 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
16088 _("immediate has bits set outside the operand size"));
16090 float_p
= inst
.operands
[1].immisfloat
;
16092 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
16093 et
.size
, et
.type
)) == FAIL
)
16095 /* Invert relevant bits only. */
16096 neon_invert_size (&immlo
, &immhi
, et
.size
);
16097 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
16098 with one or the other; those cases are caught by
16099 neon_cmode_for_move_imm. */
16101 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
16102 &op
, et
.size
, et
.type
)) == FAIL
)
16104 first_error (_("immediate out of range"));
16109 inst
.instruction
&= ~(1 << 5);
16110 inst
.instruction
|= op
<< 5;
16112 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16113 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16114 inst
.instruction
|= neon_quad (rs
) << 6;
16115 inst
.instruction
|= cmode
<< 8;
16117 neon_write_immbits (immbits
);
16123 if (inst
.operands
[1].isreg
)
16125 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16127 NEON_ENCODE (INTEGER
, inst
);
16128 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16129 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16130 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16131 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16132 inst
.instruction
|= neon_quad (rs
) << 6;
16136 NEON_ENCODE (IMMED
, inst
);
16137 neon_move_immediate ();
16140 neon_dp_fixup (&inst
);
16143 /* Encode instructions of form:
16145 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16146 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
16149 neon_mixed_length (struct neon_type_el et
, unsigned size
)
16151 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16152 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16153 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16154 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16155 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16156 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16157 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
16158 inst
.instruction
|= neon_logbits (size
) << 20;
16160 neon_dp_fixup (&inst
);
16164 do_neon_dyadic_long (void)
16166 /* FIXME: Type checking for lengthening op. */
16167 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16168 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16169 neon_mixed_length (et
, et
.size
);
16173 do_neon_abal (void)
16175 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16176 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
16177 neon_mixed_length (et
, et
.size
);
16181 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
16183 if (inst
.operands
[2].isscalar
)
16185 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
16186 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
16187 NEON_ENCODE (SCALAR
, inst
);
16188 neon_mul_mac (et
, et
.type
== NT_unsigned
);
16192 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16193 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
16194 NEON_ENCODE (INTEGER
, inst
);
16195 neon_mixed_length (et
, et
.size
);
16200 do_neon_mac_maybe_scalar_long (void)
16202 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
16205 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
16206 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
16209 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
16211 unsigned regno
= NEON_SCALAR_REG (scalar
);
16212 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
16216 if (regno
> 7 || elno
> 3)
16219 return ((regno
& 0x7)
16220 | ((elno
& 0x1) << 3)
16221 | (((elno
>> 1) & 0x1) << 5));
16225 if (regno
> 15 || elno
> 1)
16228 return (((regno
& 0x1) << 5)
16229 | ((regno
>> 1) & 0x7)
16230 | ((elno
& 0x1) << 3));
16234 first_error (_("scalar out of range for multiply instruction"));
16239 do_neon_fmac_maybe_scalar_long (int subtype
)
16241 enum neon_shape rs
;
16243 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
16244 field (bits[21:20]) has different meaning. For scalar index variant, it's
16245 used to differentiate add and subtract, otherwise it's with fixed value
16249 if (inst
.cond
!= COND_ALWAYS
)
16250 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
16251 "behaviour is UNPREDICTABLE"));
16253 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
16256 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
16259 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
16260 be a scalar index register. */
16261 if (inst
.operands
[2].isscalar
)
16263 high8
= 0xfe000000;
16266 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
16270 high8
= 0xfc000000;
16273 inst
.instruction
|= (0x1 << 23);
16274 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
16277 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
16279 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
16280 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
16281 so we simply pass -1 as size. */
16282 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
16283 neon_three_same (quad_p
, 0, size
);
16285 /* Undo neon_dp_fixup. Redo the high eight bits. */
16286 inst
.instruction
&= 0x00ffffff;
16287 inst
.instruction
|= high8
;
16289 #define LOW1(R) ((R) & 0x1)
16290 #define HI4(R) (((R) >> 1) & 0xf)
16291 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
16292 whether the instruction is in Q form and whether Vm is a scalar indexed
16294 if (inst
.operands
[2].isscalar
)
16297 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
16298 inst
.instruction
&= 0xffffffd0;
16299 inst
.instruction
|= rm
;
16303 /* Redo Rn as well. */
16304 inst
.instruction
&= 0xfff0ff7f;
16305 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16306 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16311 /* Redo Rn and Rm. */
16312 inst
.instruction
&= 0xfff0ff50;
16313 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
16314 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
16315 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
16316 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
16321 do_neon_vfmal (void)
16323 return do_neon_fmac_maybe_scalar_long (0);
16327 do_neon_vfmsl (void)
16329 return do_neon_fmac_maybe_scalar_long (1);
16333 do_neon_dyadic_wide (void)
16335 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
16336 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16337 neon_mixed_length (et
, et
.size
);
16341 do_neon_dyadic_narrow (void)
16343 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16344 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
16345 /* Operand sign is unimportant, and the U bit is part of the opcode,
16346 so force the operand type to integer. */
16347 et
.type
= NT_integer
;
16348 neon_mixed_length (et
, et
.size
/ 2);
16352 do_neon_mul_sat_scalar_long (void)
16354 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
16358 do_neon_vmull (void)
16360 if (inst
.operands
[2].isscalar
)
16361 do_neon_mac_maybe_scalar_long ();
16364 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
16365 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
16367 if (et
.type
== NT_poly
)
16368 NEON_ENCODE (POLY
, inst
);
16370 NEON_ENCODE (INTEGER
, inst
);
16372 /* For polynomial encoding the U bit must be zero, and the size must
16373 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
16374 obviously, as 0b10). */
16377 /* Check we're on the correct architecture. */
16378 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
16380 _("Instruction form not available on this architecture.");
16385 neon_mixed_length (et
, et
.size
);
16392 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
16393 struct neon_type_el et
= neon_check_type (3, rs
,
16394 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16395 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
16397 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
16398 _("shift out of range"));
16399 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16400 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16401 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16402 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16403 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16404 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16405 inst
.instruction
|= neon_quad (rs
) << 6;
16406 inst
.instruction
|= imm
<< 8;
16408 neon_dp_fixup (&inst
);
16414 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16415 struct neon_type_el et
= neon_check_type (2, rs
,
16416 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16417 unsigned op
= (inst
.instruction
>> 7) & 3;
16418 /* N (width of reversed regions) is encoded as part of the bitmask. We
16419 extract it here to check the elements to be reversed are smaller.
16420 Otherwise we'd get a reserved instruction. */
16421 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
16422 gas_assert (elsize
!= 0);
16423 constraint (et
.size
>= elsize
,
16424 _("elements must be smaller than reversal region"));
16425 neon_two_same (neon_quad (rs
), 1, et
.size
);
16431 if (inst
.operands
[1].isscalar
)
16433 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
16434 struct neon_type_el et
= neon_check_type (2, rs
,
16435 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16436 unsigned sizebits
= et
.size
>> 3;
16437 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16438 int logsize
= neon_logbits (et
.size
);
16439 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
16441 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
16444 NEON_ENCODE (SCALAR
, inst
);
16445 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16446 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16447 inst
.instruction
|= LOW4 (dm
);
16448 inst
.instruction
|= HI1 (dm
) << 5;
16449 inst
.instruction
|= neon_quad (rs
) << 6;
16450 inst
.instruction
|= x
<< 17;
16451 inst
.instruction
|= sizebits
<< 16;
16453 neon_dp_fixup (&inst
);
16457 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
16458 struct neon_type_el et
= neon_check_type (2, rs
,
16459 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16460 /* Duplicate ARM register to lanes of vector. */
16461 NEON_ENCODE (ARMREG
, inst
);
16464 case 8: inst
.instruction
|= 0x400000; break;
16465 case 16: inst
.instruction
|= 0x000020; break;
16466 case 32: inst
.instruction
|= 0x000000; break;
16469 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16470 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
16471 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
16472 inst
.instruction
|= neon_quad (rs
) << 21;
16473 /* The encoding for this instruction is identical for the ARM and Thumb
16474 variants, except for the condition field. */
16475 do_vfp_cond_or_thumb ();
16479 /* VMOV has particularly many variations. It can be one of:
16480 0. VMOV<c><q> <Qd>, <Qm>
16481 1. VMOV<c><q> <Dd>, <Dm>
16482 (Register operations, which are VORR with Rm = Rn.)
16483 2. VMOV<c><q>.<dt> <Qd>, #<imm>
16484 3. VMOV<c><q>.<dt> <Dd>, #<imm>
16486 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
16487 (ARM register to scalar.)
16488 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
16489 (Two ARM registers to vector.)
16490 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
16491 (Scalar to ARM register.)
16492 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
16493 (Vector to two ARM registers.)
16494 8. VMOV.F32 <Sd>, <Sm>
16495 9. VMOV.F64 <Dd>, <Dm>
16496 (VFP register moves.)
16497 10. VMOV.F32 <Sd>, #imm
16498 11. VMOV.F64 <Dd>, #imm
16499 (VFP float immediate load.)
16500 12. VMOV <Rd>, <Sm>
16501 (VFP single to ARM reg.)
16502 13. VMOV <Sd>, <Rm>
16503 (ARM reg to VFP single.)
16504 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
16505 (Two ARM regs to two VFP singles.)
16506 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
16507 (Two VFP singles to two ARM regs.)
16509 These cases can be disambiguated using neon_select_shape, except cases 1/9
16510 and 3/11 which depend on the operand type too.
16512 All the encoded bits are hardcoded by this function.
16514 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
16515 Cases 5, 7 may be used with VFPv2 and above.
16517 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
16518 can specify a type where it doesn't make sense to, and is ignored). */
16523 enum neon_shape rs
= neon_select_shape (NS_RRFF
, NS_FFRR
, NS_DRR
, NS_RRD
,
16524 NS_QQ
, NS_DD
, NS_QI
, NS_DI
, NS_SR
,
16525 NS_RS
, NS_FF
, NS_FI
, NS_RF
, NS_FR
,
16526 NS_HR
, NS_RH
, NS_HI
, NS_NULL
);
16527 struct neon_type_el et
;
16528 const char *ldconst
= 0;
16532 case NS_DD
: /* case 1/9. */
16533 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16534 /* It is not an error here if no type is given. */
16536 if (et
.type
== NT_float
&& et
.size
== 64)
16538 do_vfp_nsyn_opcode ("fcpyd");
16541 /* fall through. */
16543 case NS_QQ
: /* case 0/1. */
16545 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16547 /* The architecture manual I have doesn't explicitly state which
16548 value the U bit should have for register->register moves, but
16549 the equivalent VORR instruction has U = 0, so do that. */
16550 inst
.instruction
= 0x0200110;
16551 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16552 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16553 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16554 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16555 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16556 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16557 inst
.instruction
|= neon_quad (rs
) << 6;
16559 neon_dp_fixup (&inst
);
16563 case NS_DI
: /* case 3/11. */
16564 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
16566 if (et
.type
== NT_float
&& et
.size
== 64)
16568 /* case 11 (fconstd). */
16569 ldconst
= "fconstd";
16570 goto encode_fconstd
;
16572 /* fall through. */
16574 case NS_QI
: /* case 2/3. */
16575 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
16577 inst
.instruction
= 0x0800010;
16578 neon_move_immediate ();
16579 neon_dp_fixup (&inst
);
16582 case NS_SR
: /* case 4. */
16584 unsigned bcdebits
= 0;
16586 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
16587 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
16589 /* .<size> is optional here, defaulting to .32. */
16590 if (inst
.vectype
.elems
== 0
16591 && inst
.operands
[0].vectype
.type
== NT_invtype
16592 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16594 inst
.vectype
.el
[0].type
= NT_untyped
;
16595 inst
.vectype
.el
[0].size
= 32;
16596 inst
.vectype
.elems
= 1;
16599 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
16600 logsize
= neon_logbits (et
.size
);
16602 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16604 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16605 && et
.size
!= 32, _(BAD_FPU
));
16606 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16607 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16611 case 8: bcdebits
= 0x8; break;
16612 case 16: bcdebits
= 0x1; break;
16613 case 32: bcdebits
= 0x0; break;
16617 bcdebits
|= x
<< logsize
;
16619 inst
.instruction
= 0xe000b10;
16620 do_vfp_cond_or_thumb ();
16621 inst
.instruction
|= LOW4 (dn
) << 16;
16622 inst
.instruction
|= HI1 (dn
) << 7;
16623 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16624 inst
.instruction
|= (bcdebits
& 3) << 5;
16625 inst
.instruction
|= (bcdebits
>> 2) << 21;
16629 case NS_DRR
: /* case 5 (fmdrr). */
16630 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16633 inst
.instruction
= 0xc400b10;
16634 do_vfp_cond_or_thumb ();
16635 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
16636 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
16637 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
16638 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
16641 case NS_RS
: /* case 6. */
16644 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
16645 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
16646 unsigned abcdebits
= 0;
16648 /* .<dt> is optional here, defaulting to .32. */
16649 if (inst
.vectype
.elems
== 0
16650 && inst
.operands
[0].vectype
.type
== NT_invtype
16651 && inst
.operands
[1].vectype
.type
== NT_invtype
)
16653 inst
.vectype
.el
[0].type
= NT_untyped
;
16654 inst
.vectype
.el
[0].size
= 32;
16655 inst
.vectype
.elems
= 1;
16658 et
= neon_check_type (2, NS_NULL
,
16659 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
16660 logsize
= neon_logbits (et
.size
);
16662 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
),
16664 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
)
16665 && et
.size
!= 32, _(BAD_FPU
));
16666 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
16667 constraint (x
>= 64 / et
.size
, _("scalar index out of range"));
16671 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
16672 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
16673 case 32: abcdebits
= 0x00; break;
16677 abcdebits
|= x
<< logsize
;
16678 inst
.instruction
= 0xe100b10;
16679 do_vfp_cond_or_thumb ();
16680 inst
.instruction
|= LOW4 (dn
) << 16;
16681 inst
.instruction
|= HI1 (dn
) << 7;
16682 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16683 inst
.instruction
|= (abcdebits
& 3) << 5;
16684 inst
.instruction
|= (abcdebits
>> 2) << 21;
16688 case NS_RRD
: /* case 7 (fmrrd). */
16689 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
),
16692 inst
.instruction
= 0xc500b10;
16693 do_vfp_cond_or_thumb ();
16694 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16695 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
16696 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16697 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16700 case NS_FF
: /* case 8 (fcpys). */
16701 do_vfp_nsyn_opcode ("fcpys");
16705 case NS_FI
: /* case 10 (fconsts). */
16706 ldconst
= "fconsts";
16708 if (is_quarter_float (inst
.operands
[1].imm
))
16710 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
16711 do_vfp_nsyn_opcode (ldconst
);
16713 /* ARMv8.2 fp16 vmov.f16 instruction. */
16715 do_scalar_fp16_v82_encode ();
16718 first_error (_("immediate out of range"));
16722 case NS_RF
: /* case 12 (fmrs). */
16723 do_vfp_nsyn_opcode ("fmrs");
16724 /* ARMv8.2 fp16 vmov.f16 instruction. */
16726 do_scalar_fp16_v82_encode ();
16730 case NS_FR
: /* case 13 (fmsr). */
16731 do_vfp_nsyn_opcode ("fmsr");
16732 /* ARMv8.2 fp16 vmov.f16 instruction. */
16734 do_scalar_fp16_v82_encode ();
16737 /* The encoders for the fmrrs and fmsrr instructions expect three operands
16738 (one of which is a list), but we have parsed four. Do some fiddling to
16739 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
16741 case NS_RRFF
: /* case 14 (fmrrs). */
16742 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
16743 _("VFP registers must be adjacent"));
16744 inst
.operands
[2].imm
= 2;
16745 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16746 do_vfp_nsyn_opcode ("fmrrs");
16749 case NS_FFRR
: /* case 15 (fmsrr). */
16750 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
16751 _("VFP registers must be adjacent"));
16752 inst
.operands
[1] = inst
.operands
[2];
16753 inst
.operands
[2] = inst
.operands
[3];
16754 inst
.operands
[0].imm
= 2;
16755 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
16756 do_vfp_nsyn_opcode ("fmsrr");
16760 /* neon_select_shape has determined that the instruction
16761 shape is wrong and has already set the error message. */
16770 do_neon_rshift_round_imm (void)
16772 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16773 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16774 int imm
= inst
.operands
[2].imm
;
16776 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
16779 inst
.operands
[2].present
= 0;
16784 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16785 _("immediate out of range for shift"));
16786 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
16791 do_neon_movhf (void)
16793 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
16794 constraint (rs
!= NS_HH
, _("invalid suffix"));
16796 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
16799 if (inst
.cond
!= COND_ALWAYS
)
16803 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
16804 " the behaviour is UNPREDICTABLE"));
16808 inst
.error
= BAD_COND
;
16813 do_vfp_sp_monadic ();
16816 inst
.instruction
|= 0xf0000000;
16820 do_neon_movl (void)
16822 struct neon_type_el et
= neon_check_type (2, NS_QD
,
16823 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
16824 unsigned sizebits
= et
.size
>> 3;
16825 inst
.instruction
|= sizebits
<< 19;
16826 neon_two_same (0, et
.type
== NT_unsigned
, -1);
16832 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16833 struct neon_type_el et
= neon_check_type (2, rs
,
16834 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16835 NEON_ENCODE (INTEGER
, inst
);
16836 neon_two_same (neon_quad (rs
), 1, et
.size
);
16840 do_neon_zip_uzp (void)
16842 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16843 struct neon_type_el et
= neon_check_type (2, rs
,
16844 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
16845 if (rs
== NS_DD
&& et
.size
== 32)
16847 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
16848 inst
.instruction
= N_MNEM_vtrn
;
16852 neon_two_same (neon_quad (rs
), 1, et
.size
);
16856 do_neon_sat_abs_neg (void)
16858 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16859 struct neon_type_el et
= neon_check_type (2, rs
,
16860 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16861 neon_two_same (neon_quad (rs
), 1, et
.size
);
16865 do_neon_pair_long (void)
16867 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16868 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
16869 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
16870 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
16871 neon_two_same (neon_quad (rs
), 1, et
.size
);
16875 do_neon_recip_est (void)
16877 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16878 struct neon_type_el et
= neon_check_type (2, rs
,
16879 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
16880 inst
.instruction
|= (et
.type
== NT_float
) << 8;
16881 neon_two_same (neon_quad (rs
), 1, et
.size
);
16887 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16888 struct neon_type_el et
= neon_check_type (2, rs
,
16889 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
16890 neon_two_same (neon_quad (rs
), 1, et
.size
);
16896 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16897 struct neon_type_el et
= neon_check_type (2, rs
,
16898 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
16899 neon_two_same (neon_quad (rs
), 1, et
.size
);
16905 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16906 struct neon_type_el et
= neon_check_type (2, rs
,
16907 N_EQK
| N_INT
, N_8
| N_KEY
);
16908 neon_two_same (neon_quad (rs
), 1, et
.size
);
16914 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
16915 neon_two_same (neon_quad (rs
), 1, -1);
16919 do_neon_tbl_tbx (void)
16921 unsigned listlenbits
;
16922 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
16924 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
16926 first_error (_("bad list length for table lookup"));
16930 listlenbits
= inst
.operands
[1].imm
- 1;
16931 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16932 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16933 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16934 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16935 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16936 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16937 inst
.instruction
|= listlenbits
<< 8;
16939 neon_dp_fixup (&inst
);
16943 do_neon_ldm_stm (void)
16945 /* P, U and L bits are part of bitmask. */
16946 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
16947 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
16949 if (inst
.operands
[1].issingle
)
16951 do_vfp_nsyn_ldm_stm (is_dbmode
);
16955 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
16956 _("writeback (!) must be used for VLDMDB and VSTMDB"));
16958 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16959 _("register list must contain at least 1 and at most 16 "
16962 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
16963 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
16964 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
16965 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
16967 inst
.instruction
|= offsetbits
;
16969 do_vfp_cond_or_thumb ();
16973 do_neon_ldr_str (void)
16975 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
16977 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
16978 And is UNPREDICTABLE in thumb mode. */
16980 && inst
.operands
[1].reg
== REG_PC
16981 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
16984 inst
.error
= _("Use of PC here is UNPREDICTABLE");
16985 else if (warn_on_deprecated
)
16986 as_tsktsk (_("Use of PC here is deprecated"));
16989 if (inst
.operands
[0].issingle
)
16992 do_vfp_nsyn_opcode ("flds");
16994 do_vfp_nsyn_opcode ("fsts");
16996 /* ARMv8.2 vldr.16/vstr.16 instruction. */
16997 if (inst
.vectype
.el
[0].size
== 16)
16998 do_scalar_fp16_v82_encode ();
17003 do_vfp_nsyn_opcode ("fldd");
17005 do_vfp_nsyn_opcode ("fstd");
17009 /* "interleave" version also handles non-interleaving register VLD1/VST1
17013 do_neon_ld_st_interleave (void)
17015 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
17016 N_8
| N_16
| N_32
| N_64
);
17017 unsigned alignbits
= 0;
17019 /* The bits in this table go:
17020 0: register stride of one (0) or two (1)
17021 1,2: register list length, minus one (1, 2, 3, 4).
17022 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
17023 We use -1 for invalid entries. */
17024 const int typetable
[] =
17026 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
17027 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
17028 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
17029 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
17033 if (et
.type
== NT_invtype
)
17036 if (inst
.operands
[1].immisalign
)
17037 switch (inst
.operands
[1].imm
>> 8)
17039 case 64: alignbits
= 1; break;
17041 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
17042 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17043 goto bad_alignment
;
17047 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
17048 goto bad_alignment
;
17053 first_error (_("bad alignment"));
17057 inst
.instruction
|= alignbits
<< 4;
17058 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17060 /* Bits [4:6] of the immediate in a list specifier encode register stride
17061 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
17062 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
17063 up the right value for "type" in a table based on this value and the given
17064 list style, then stick it back. */
17065 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
17066 | (((inst
.instruction
>> 8) & 3) << 3);
17068 typebits
= typetable
[idx
];
17070 constraint (typebits
== -1, _("bad list type for instruction"));
17071 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
17072 _("bad element type for instruction"));
17074 inst
.instruction
&= ~0xf00;
17075 inst
.instruction
|= typebits
<< 8;
17078 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
17079 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
17080 otherwise. The variable arguments are a list of pairs of legal (size, align)
17081 values, terminated with -1. */
17084 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
17087 int result
= FAIL
, thissize
, thisalign
;
17089 if (!inst
.operands
[1].immisalign
)
17095 va_start (ap
, do_alignment
);
17099 thissize
= va_arg (ap
, int);
17100 if (thissize
== -1)
17102 thisalign
= va_arg (ap
, int);
17104 if (size
== thissize
&& align
== thisalign
)
17107 while (result
!= SUCCESS
);
17111 if (result
== SUCCESS
)
17114 first_error (_("unsupported alignment for instruction"));
17120 do_neon_ld_st_lane (void)
17122 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17123 int align_good
, do_alignment
= 0;
17124 int logsize
= neon_logbits (et
.size
);
17125 int align
= inst
.operands
[1].imm
>> 8;
17126 int n
= (inst
.instruction
>> 8) & 3;
17127 int max_el
= 64 / et
.size
;
17129 if (et
.type
== NT_invtype
)
17132 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
17133 _("bad list length"));
17134 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
17135 _("scalar index out of range"));
17136 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
17138 _("stride of 2 unavailable when element size is 8"));
17142 case 0: /* VLD1 / VST1. */
17143 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
17145 if (align_good
== FAIL
)
17149 unsigned alignbits
= 0;
17152 case 16: alignbits
= 0x1; break;
17153 case 32: alignbits
= 0x3; break;
17156 inst
.instruction
|= alignbits
<< 4;
17160 case 1: /* VLD2 / VST2. */
17161 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
17162 16, 32, 32, 64, -1);
17163 if (align_good
== FAIL
)
17166 inst
.instruction
|= 1 << 4;
17169 case 2: /* VLD3 / VST3. */
17170 constraint (inst
.operands
[1].immisalign
,
17171 _("can't use alignment with this instruction"));
17174 case 3: /* VLD4 / VST4. */
17175 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17176 16, 64, 32, 64, 32, 128, -1);
17177 if (align_good
== FAIL
)
17181 unsigned alignbits
= 0;
17184 case 8: alignbits
= 0x1; break;
17185 case 16: alignbits
= 0x1; break;
17186 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
17189 inst
.instruction
|= alignbits
<< 4;
17196 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
17197 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17198 inst
.instruction
|= 1 << (4 + logsize
);
17200 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
17201 inst
.instruction
|= logsize
<< 10;
17204 /* Encode single n-element structure to all lanes VLD<n> instructions. */
17207 do_neon_ld_dup (void)
17209 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
17210 int align_good
, do_alignment
= 0;
17212 if (et
.type
== NT_invtype
)
17215 switch ((inst
.instruction
>> 8) & 3)
17217 case 0: /* VLD1. */
17218 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
17219 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17220 &do_alignment
, 16, 16, 32, 32, -1);
17221 if (align_good
== FAIL
)
17223 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
17226 case 2: inst
.instruction
|= 1 << 5; break;
17227 default: first_error (_("bad list length")); return;
17229 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17232 case 1: /* VLD2. */
17233 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
17234 &do_alignment
, 8, 16, 16, 32, 32, 64,
17236 if (align_good
== FAIL
)
17238 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
17239 _("bad list length"));
17240 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17241 inst
.instruction
|= 1 << 5;
17242 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17245 case 2: /* VLD3. */
17246 constraint (inst
.operands
[1].immisalign
,
17247 _("can't use alignment with this instruction"));
17248 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
17249 _("bad list length"));
17250 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17251 inst
.instruction
|= 1 << 5;
17252 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17255 case 3: /* VLD4. */
17257 int align
= inst
.operands
[1].imm
>> 8;
17258 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
17259 16, 64, 32, 64, 32, 128, -1);
17260 if (align_good
== FAIL
)
17262 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
17263 _("bad list length"));
17264 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
17265 inst
.instruction
|= 1 << 5;
17266 if (et
.size
== 32 && align
== 128)
17267 inst
.instruction
|= 0x3 << 6;
17269 inst
.instruction
|= neon_logbits (et
.size
) << 6;
17276 inst
.instruction
|= do_alignment
<< 4;
17279 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
17280 apart from bits [11:4]. */
17283 do_neon_ldx_stx (void)
17285 if (inst
.operands
[1].isreg
)
17286 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
17288 switch (NEON_LANE (inst
.operands
[0].imm
))
17290 case NEON_INTERLEAVE_LANES
:
17291 NEON_ENCODE (INTERLV
, inst
);
17292 do_neon_ld_st_interleave ();
17295 case NEON_ALL_LANES
:
17296 NEON_ENCODE (DUP
, inst
);
17297 if (inst
.instruction
== N_INV
)
17299 first_error ("only loads support such operands");
17306 NEON_ENCODE (LANE
, inst
);
17307 do_neon_ld_st_lane ();
17310 /* L bit comes from bit mask. */
17311 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17312 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17313 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17315 if (inst
.operands
[1].postind
)
17317 int postreg
= inst
.operands
[1].imm
& 0xf;
17318 constraint (!inst
.operands
[1].immisreg
,
17319 _("post-index must be a register"));
17320 constraint (postreg
== 0xd || postreg
== 0xf,
17321 _("bad register for post-index"));
17322 inst
.instruction
|= postreg
;
17326 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17327 constraint (inst
.reloc
.exp
.X_op
!= O_constant
17328 || inst
.reloc
.exp
.X_add_number
!= 0,
17331 if (inst
.operands
[1].writeback
)
17333 inst
.instruction
|= 0xd;
17336 inst
.instruction
|= 0xf;
17340 inst
.instruction
|= 0xf9000000;
17342 inst
.instruction
|= 0xf4000000;
17347 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
17349 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17350 D register operands. */
17351 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17352 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17355 NEON_ENCODE (FPV8
, inst
);
17357 if (rs
== NS_FFF
|| rs
== NS_HHH
)
17359 do_vfp_sp_dyadic ();
17361 /* ARMv8.2 fp16 instruction. */
17363 do_scalar_fp16_v82_encode ();
17366 do_vfp_dp_rd_rn_rm ();
17369 inst
.instruction
|= 0x100;
17371 inst
.instruction
|= 0xf0000000;
17377 set_it_insn_type (OUTSIDE_IT_INSN
);
17379 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
17380 first_error (_("invalid instruction shape"));
17386 set_it_insn_type (OUTSIDE_IT_INSN
);
17388 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
17391 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17394 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
17398 do_vrint_1 (enum neon_cvt_mode mode
)
17400 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
17401 struct neon_type_el et
;
17406 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
17407 D register operands. */
17408 if (neon_shape_class
[rs
] == SC_DOUBLE
)
17409 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17412 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
17414 if (et
.type
!= NT_invtype
)
17416 /* VFP encodings. */
17417 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
17418 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
17419 set_it_insn_type (OUTSIDE_IT_INSN
);
17421 NEON_ENCODE (FPV8
, inst
);
17422 if (rs
== NS_FF
|| rs
== NS_HH
)
17423 do_vfp_sp_monadic ();
17425 do_vfp_dp_rd_rm ();
17429 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
17430 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
17431 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
17432 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
17433 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
17434 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
17435 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
17439 inst
.instruction
|= (rs
== NS_DD
) << 8;
17440 do_vfp_cond_or_thumb ();
17442 /* ARMv8.2 fp16 vrint instruction. */
17444 do_scalar_fp16_v82_encode ();
17448 /* Neon encodings (or something broken...). */
17450 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
17452 if (et
.type
== NT_invtype
)
17455 set_it_insn_type (OUTSIDE_IT_INSN
);
17456 NEON_ENCODE (FLOAT
, inst
);
17458 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH8
) == FAIL
)
17461 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17462 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17463 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17464 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17465 inst
.instruction
|= neon_quad (rs
) << 6;
17466 /* Mask off the original size bits and reencode them. */
17467 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
17468 | neon_logbits (et
.size
) << 18);
17472 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
17473 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
17474 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
17475 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
17476 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
17477 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
17478 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
17483 inst
.instruction
|= 0xfc000000;
17485 inst
.instruction
|= 0xf0000000;
17492 do_vrint_1 (neon_cvt_mode_x
);
17498 do_vrint_1 (neon_cvt_mode_z
);
17504 do_vrint_1 (neon_cvt_mode_r
);
17510 do_vrint_1 (neon_cvt_mode_a
);
17516 do_vrint_1 (neon_cvt_mode_n
);
17522 do_vrint_1 (neon_cvt_mode_p
);
17528 do_vrint_1 (neon_cvt_mode_m
);
17532 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
17534 unsigned regno
= NEON_SCALAR_REG (opnd
);
17535 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
17537 if (elsize
== 16 && elno
< 2 && regno
< 16)
17538 return regno
| (elno
<< 4);
17539 else if (elsize
== 32 && elno
== 0)
17542 first_error (_("scalar out of range"));
17549 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17551 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17552 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17553 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
17554 _("immediate out of range"));
17556 if (inst
.operands
[2].isscalar
)
17558 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
17559 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17560 N_KEY
| N_F16
| N_F32
).size
;
17561 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
17563 inst
.instruction
= 0xfe000800;
17564 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17565 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17566 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17567 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17568 inst
.instruction
|= LOW4 (m
);
17569 inst
.instruction
|= HI1 (m
) << 5;
17570 inst
.instruction
|= neon_quad (rs
) << 6;
17571 inst
.instruction
|= rot
<< 20;
17572 inst
.instruction
|= (size
== 32) << 23;
17576 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17577 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17578 N_KEY
| N_F16
| N_F32
).size
;
17579 neon_three_same (neon_quad (rs
), 0, -1);
17580 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17581 inst
.instruction
|= 0xfc200800;
17582 inst
.instruction
|= rot
<< 23;
17583 inst
.instruction
|= (size
== 32) << 20;
17590 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17592 constraint (inst
.reloc
.exp
.X_op
!= O_constant
, _("expression too complex"));
17593 unsigned rot
= inst
.reloc
.exp
.X_add_number
;
17594 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17595 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
17596 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17597 N_KEY
| N_F16
| N_F32
).size
;
17598 neon_three_same (neon_quad (rs
), 0, -1);
17599 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
17600 inst
.instruction
|= 0xfc800800;
17601 inst
.instruction
|= (rot
== 270) << 24;
17602 inst
.instruction
|= (size
== 32) << 20;
17605 /* Dot Product instructions encoding support. */
17608 do_neon_dotproduct (int unsigned_p
)
17610 enum neon_shape rs
;
17611 unsigned scalar_oprd2
= 0;
17614 if (inst
.cond
!= COND_ALWAYS
)
17615 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
17616 "is UNPREDICTABLE"));
17618 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
17621 /* Dot Product instructions are in three-same D/Q register format or the third
17622 operand can be a scalar index register. */
17623 if (inst
.operands
[2].isscalar
)
17625 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
17626 high8
= 0xfe000000;
17627 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17631 high8
= 0xfc000000;
17632 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17636 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
17638 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
17640 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
17641 Product instruction, so we pass 0 as the "ubit" parameter. And the
17642 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
17643 neon_three_same (neon_quad (rs
), 0, 32);
17645 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
17646 different NEON three-same encoding. */
17647 inst
.instruction
&= 0x00ffffff;
17648 inst
.instruction
|= high8
;
17649 /* Encode 'U' bit which indicates signedness. */
17650 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
17651 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
17652 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
17653 the instruction encoding. */
17654 if (inst
.operands
[2].isscalar
)
17656 inst
.instruction
&= 0xffffffd0;
17657 inst
.instruction
|= LOW4 (scalar_oprd2
);
17658 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
17662 /* Dot Product instructions for signed integer. */
17665 do_neon_dotproduct_s (void)
17667 return do_neon_dotproduct (0);
17670 /* Dot Product instructions for unsigned integer. */
17673 do_neon_dotproduct_u (void)
17675 return do_neon_dotproduct (1);
17678 /* Crypto v1 instructions. */
17680 do_crypto_2op_1 (unsigned elttype
, int op
)
17682 set_it_insn_type (OUTSIDE_IT_INSN
);
17684 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
17690 NEON_ENCODE (INTEGER
, inst
);
17691 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17692 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17693 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17694 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17696 inst
.instruction
|= op
<< 6;
17699 inst
.instruction
|= 0xfc000000;
17701 inst
.instruction
|= 0xf0000000;
17705 do_crypto_3op_1 (int u
, int op
)
17707 set_it_insn_type (OUTSIDE_IT_INSN
);
17709 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
17710 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
17715 NEON_ENCODE (INTEGER
, inst
);
17716 neon_three_same (1, u
, 8 << op
);
17722 do_crypto_2op_1 (N_8
, 0);
17728 do_crypto_2op_1 (N_8
, 1);
17734 do_crypto_2op_1 (N_8
, 2);
17740 do_crypto_2op_1 (N_8
, 3);
17746 do_crypto_3op_1 (0, 0);
17752 do_crypto_3op_1 (0, 1);
17758 do_crypto_3op_1 (0, 2);
17764 do_crypto_3op_1 (0, 3);
17770 do_crypto_3op_1 (1, 0);
17776 do_crypto_3op_1 (1, 1);
17780 do_sha256su1 (void)
17782 do_crypto_3op_1 (1, 2);
17788 do_crypto_2op_1 (N_32
, -1);
17794 do_crypto_2op_1 (N_32
, 0);
17798 do_sha256su0 (void)
17800 do_crypto_2op_1 (N_32
, 1);
17804 do_crc32_1 (unsigned int poly
, unsigned int sz
)
17806 unsigned int Rd
= inst
.operands
[0].reg
;
17807 unsigned int Rn
= inst
.operands
[1].reg
;
17808 unsigned int Rm
= inst
.operands
[2].reg
;
17810 set_it_insn_type (OUTSIDE_IT_INSN
);
17811 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
17812 inst
.instruction
|= LOW4 (Rn
) << 16;
17813 inst
.instruction
|= LOW4 (Rm
);
17814 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
17815 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
17817 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
17818 as_warn (UNPRED_REG ("r15"));
17860 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
17862 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
17863 do_vfp_sp_dp_cvt ();
17864 do_vfp_cond_or_thumb ();
17868 /* Overall per-instruction processing. */
17870 /* We need to be able to fix up arbitrary expressions in some statements.
17871 This is so that we can handle symbols that are an arbitrary distance from
17872 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
17873 which returns part of an address in a form which will be valid for
17874 a data instruction. We do this by pushing the expression into a symbol
17875 in the expr_section, and creating a fix for that. */
17878 fix_new_arm (fragS
* frag
,
17892 /* Create an absolute valued symbol, so we have something to
17893 refer to in the object file. Unfortunately for us, gas's
17894 generic expression parsing will already have folded out
17895 any use of .set foo/.type foo %function that may have
17896 been used to set type information of the target location,
17897 that's being specified symbolically. We have to presume
17898 the user knows what they are doing. */
17902 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
17904 symbol
= symbol_find_or_make (name
);
17905 S_SET_SEGMENT (symbol
, absolute_section
);
17906 symbol_set_frag (symbol
, &zero_address_frag
);
17907 S_SET_VALUE (symbol
, exp
->X_add_number
);
17908 exp
->X_op
= O_symbol
;
17909 exp
->X_add_symbol
= symbol
;
17910 exp
->X_add_number
= 0;
17916 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
17917 (enum bfd_reloc_code_real
) reloc
);
17921 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
17922 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
17926 /* Mark whether the fix is to a THUMB instruction, or an ARM
17928 new_fix
->tc_fix_data
= thumb_mode
;
17931 /* Create a frg for an instruction requiring relaxation. */
17933 output_relax_insn (void)
17939 /* The size of the instruction is unknown, so tie the debug info to the
17940 start of the instruction. */
17941 dwarf2_emit_insn (0);
17943 switch (inst
.reloc
.exp
.X_op
)
17946 sym
= inst
.reloc
.exp
.X_add_symbol
;
17947 offset
= inst
.reloc
.exp
.X_add_number
;
17951 offset
= inst
.reloc
.exp
.X_add_number
;
17954 sym
= make_expr_symbol (&inst
.reloc
.exp
);
17958 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
17959 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
17960 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
17963 /* Write a 32-bit thumb instruction to buf. */
17965 put_thumb32_insn (char * buf
, unsigned long insn
)
17967 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
17968 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
17972 output_inst (const char * str
)
17978 as_bad ("%s -- `%s'", inst
.error
, str
);
17983 output_relax_insn ();
17986 if (inst
.size
== 0)
17989 to
= frag_more (inst
.size
);
17990 /* PR 9814: Record the thumb mode into the current frag so that we know
17991 what type of NOP padding to use, if necessary. We override any previous
17992 setting so that if the mode has changed then the NOPS that we use will
17993 match the encoding of the last instruction in the frag. */
17994 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
17996 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
17998 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
17999 put_thumb32_insn (to
, inst
.instruction
);
18001 else if (inst
.size
> INSN_SIZE
)
18003 gas_assert (inst
.size
== (2 * INSN_SIZE
));
18004 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
18005 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
18008 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
18010 if (inst
.reloc
.type
!= BFD_RELOC_UNUSED
)
18011 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
18012 inst
.size
, & inst
.reloc
.exp
, inst
.reloc
.pc_rel
,
18015 dwarf2_emit_insn (inst
.size
);
18019 output_it_inst (int cond
, int mask
, char * to
)
18021 unsigned long instruction
= 0xbf00;
18024 instruction
|= mask
;
18025 instruction
|= cond
<< 4;
18029 to
= frag_more (2);
18031 dwarf2_emit_insn (2);
18035 md_number_to_chars (to
, instruction
, 2);
18040 /* Tag values used in struct asm_opcode's tag field. */
18043 OT_unconditional
, /* Instruction cannot be conditionalized.
18044 The ARM condition field is still 0xE. */
18045 OT_unconditionalF
, /* Instruction cannot be conditionalized
18046 and carries 0xF in its ARM condition field. */
18047 OT_csuffix
, /* Instruction takes a conditional suffix. */
18048 OT_csuffixF
, /* Some forms of the instruction take a conditional
18049 suffix, others place 0xF where the condition field
18051 OT_cinfix3
, /* Instruction takes a conditional infix,
18052 beginning at character index 3. (In
18053 unified mode, it becomes a suffix.) */
18054 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
18055 tsts, cmps, cmns, and teqs. */
18056 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
18057 character index 3, even in unified mode. Used for
18058 legacy instructions where suffix and infix forms
18059 may be ambiguous. */
18060 OT_csuf_or_in3
, /* Instruction takes either a conditional
18061 suffix or an infix at character index 3. */
18062 OT_odd_infix_unc
, /* This is the unconditional variant of an
18063 instruction that takes a conditional infix
18064 at an unusual position. In unified mode,
18065 this variant will accept a suffix. */
18066 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
18067 are the conditional variants of instructions that
18068 take conditional infixes in unusual positions.
18069 The infix appears at character index
18070 (tag - OT_odd_infix_0). These are not accepted
18071 in unified mode. */
18074 /* Subroutine of md_assemble, responsible for looking up the primary
18075 opcode from the mnemonic the user wrote. STR points to the
18076 beginning of the mnemonic.
18078 This is not simply a hash table lookup, because of conditional
18079 variants. Most instructions have conditional variants, which are
18080 expressed with a _conditional affix_ to the mnemonic. If we were
18081 to encode each conditional variant as a literal string in the opcode
18082 table, it would have approximately 20,000 entries.
18084 Most mnemonics take this affix as a suffix, and in unified syntax,
18085 'most' is upgraded to 'all'. However, in the divided syntax, some
18086 instructions take the affix as an infix, notably the s-variants of
18087 the arithmetic instructions. Of those instructions, all but six
18088 have the infix appear after the third character of the mnemonic.
18090 Accordingly, the algorithm for looking up primary opcodes given
18093 1. Look up the identifier in the opcode table.
18094 If we find a match, go to step U.
18096 2. Look up the last two characters of the identifier in the
18097 conditions table. If we find a match, look up the first N-2
18098 characters of the identifier in the opcode table. If we
18099 find a match, go to step CE.
18101 3. Look up the fourth and fifth characters of the identifier in
18102 the conditions table. If we find a match, extract those
18103 characters from the identifier, and look up the remaining
18104 characters in the opcode table. If we find a match, go
18109 U. Examine the tag field of the opcode structure, in case this is
18110 one of the six instructions with its conditional infix in an
18111 unusual place. If it is, the tag tells us where to find the
18112 infix; look it up in the conditions table and set inst.cond
18113 accordingly. Otherwise, this is an unconditional instruction.
18114 Again set inst.cond accordingly. Return the opcode structure.
18116 CE. Examine the tag field to make sure this is an instruction that
18117 should receive a conditional suffix. If it is not, fail.
18118 Otherwise, set inst.cond from the suffix we already looked up,
18119 and return the opcode structure.
18121 CM. Examine the tag field to make sure this is an instruction that
18122 should receive a conditional infix after the third character.
18123 If it is not, fail. Otherwise, undo the edits to the current
18124 line of input and proceed as for case CE. */
18126 static const struct asm_opcode
*
18127 opcode_lookup (char **str
)
18131 const struct asm_opcode
*opcode
;
18132 const struct asm_cond
*cond
;
18135 /* Scan up to the end of the mnemonic, which must end in white space,
18136 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
18137 for (base
= end
= *str
; *end
!= '\0'; end
++)
18138 if (*end
== ' ' || *end
== '.')
18144 /* Handle a possible width suffix and/or Neon type suffix. */
18149 /* The .w and .n suffixes are only valid if the unified syntax is in
18151 if (unified_syntax
&& end
[1] == 'w')
18153 else if (unified_syntax
&& end
[1] == 'n')
18158 inst
.vectype
.elems
= 0;
18160 *str
= end
+ offset
;
18162 if (end
[offset
] == '.')
18164 /* See if we have a Neon type suffix (possible in either unified or
18165 non-unified ARM syntax mode). */
18166 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
18169 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
18175 /* Look for unaffixed or special-case affixed mnemonic. */
18176 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18181 if (opcode
->tag
< OT_odd_infix_0
)
18183 inst
.cond
= COND_ALWAYS
;
18187 if (warn_on_deprecated
&& unified_syntax
)
18188 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18189 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
18190 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18193 inst
.cond
= cond
->value
;
18197 /* Cannot have a conditional suffix on a mnemonic of less than two
18199 if (end
- base
< 3)
18202 /* Look for suffixed mnemonic. */
18204 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18205 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18207 if (opcode
&& cond
)
18210 switch (opcode
->tag
)
18212 case OT_cinfix3_legacy
:
18213 /* Ignore conditional suffixes matched on infix only mnemonics. */
18217 case OT_cinfix3_deprecated
:
18218 case OT_odd_infix_unc
:
18219 if (!unified_syntax
)
18221 /* Fall through. */
18225 case OT_csuf_or_in3
:
18226 inst
.cond
= cond
->value
;
18229 case OT_unconditional
:
18230 case OT_unconditionalF
:
18232 inst
.cond
= cond
->value
;
18235 /* Delayed diagnostic. */
18236 inst
.error
= BAD_COND
;
18237 inst
.cond
= COND_ALWAYS
;
18246 /* Cannot have a usual-position infix on a mnemonic of less than
18247 six characters (five would be a suffix). */
18248 if (end
- base
< 6)
18251 /* Look for infixed mnemonic in the usual position. */
18253 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
18257 memcpy (save
, affix
, 2);
18258 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
18259 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
18261 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
18262 memcpy (affix
, save
, 2);
18265 && (opcode
->tag
== OT_cinfix3
18266 || opcode
->tag
== OT_cinfix3_deprecated
18267 || opcode
->tag
== OT_csuf_or_in3
18268 || opcode
->tag
== OT_cinfix3_legacy
))
18271 if (warn_on_deprecated
&& unified_syntax
18272 && (opcode
->tag
== OT_cinfix3
18273 || opcode
->tag
== OT_cinfix3_deprecated
))
18274 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
18276 inst
.cond
= cond
->value
;
18283 /* This function generates an initial IT instruction, leaving its block
18284 virtually open for the new instructions. Eventually,
18285 the mask will be updated by now_it_add_mask () each time
18286 a new instruction needs to be included in the IT block.
18287 Finally, the block is closed with close_automatic_it_block ().
18288 The block closure can be requested either from md_assemble (),
18289 a tencode (), or due to a label hook. */
18292 new_automatic_it_block (int cond
)
18294 now_it
.state
= AUTOMATIC_IT_BLOCK
;
18295 now_it
.mask
= 0x18;
18297 now_it
.block_length
= 1;
18298 mapping_state (MAP_THUMB
);
18299 now_it
.insn
= output_it_inst (cond
, now_it
.mask
, NULL
);
18300 now_it
.warn_deprecated
= FALSE
;
18301 now_it
.insn_cond
= TRUE
;
18304 /* Close an automatic IT block.
18305 See comments in new_automatic_it_block (). */
18308 close_automatic_it_block (void)
18310 now_it
.mask
= 0x10;
18311 now_it
.block_length
= 0;
18314 /* Update the mask of the current automatically-generated IT
18315 instruction. See comments in new_automatic_it_block (). */
18318 now_it_add_mask (int cond
)
18320 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
18321 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
18322 | ((bitvalue) << (nbit)))
18323 const int resulting_bit
= (cond
& 1);
18325 now_it
.mask
&= 0xf;
18326 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18328 (5 - now_it
.block_length
));
18329 now_it
.mask
= SET_BIT_VALUE (now_it
.mask
,
18331 ((5 - now_it
.block_length
) - 1) );
18332 output_it_inst (now_it
.cc
, now_it
.mask
, now_it
.insn
);
18335 #undef SET_BIT_VALUE
18338 /* The IT blocks handling machinery is accessed through the these functions:
18339 it_fsm_pre_encode () from md_assemble ()
18340 set_it_insn_type () optional, from the tencode functions
18341 set_it_insn_type_last () ditto
18342 in_it_block () ditto
18343 it_fsm_post_encode () from md_assemble ()
18344 force_automatic_it_block_close () from label handling functions
18347 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
18348 initializing the IT insn type with a generic initial value depending
18349 on the inst.condition.
18350 2) During the tencode function, two things may happen:
18351 a) The tencode function overrides the IT insn type by
18352 calling either set_it_insn_type (type) or set_it_insn_type_last ().
18353 b) The tencode function queries the IT block state by
18354 calling in_it_block () (i.e. to determine narrow/not narrow mode).
18356 Both set_it_insn_type and in_it_block run the internal FSM state
18357 handling function (handle_it_state), because: a) setting the IT insn
18358 type may incur in an invalid state (exiting the function),
18359 and b) querying the state requires the FSM to be updated.
18360 Specifically we want to avoid creating an IT block for conditional
18361 branches, so it_fsm_pre_encode is actually a guess and we can't
18362 determine whether an IT block is required until the tencode () routine
18363 has decided what type of instruction this actually it.
18364 Because of this, if set_it_insn_type and in_it_block have to be used,
18365 set_it_insn_type has to be called first.
18367 set_it_insn_type_last () is a wrapper of set_it_insn_type (type), that
18368 determines the insn IT type depending on the inst.cond code.
18369 When a tencode () routine encodes an instruction that can be
18370 either outside an IT block, or, in the case of being inside, has to be
18371 the last one, set_it_insn_type_last () will determine the proper
18372 IT instruction type based on the inst.cond code. Otherwise,
18373 set_it_insn_type can be called for overriding that logic or
18374 for covering other cases.
18376 Calling handle_it_state () may not transition the IT block state to
18377 OUTSIDE_IT_BLOCK immediately, since the (current) state could be
18378 still queried. Instead, if the FSM determines that the state should
18379 be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
18380 after the tencode () function: that's what it_fsm_post_encode () does.
18382 Since in_it_block () calls the state handling function to get an
18383 updated state, an error may occur (due to invalid insns combination).
18384 In that case, inst.error is set.
18385 Therefore, inst.error has to be checked after the execution of
18386 the tencode () routine.
18388 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
18389 any pending state change (if any) that didn't take place in
18390 handle_it_state () as explained above. */
18393 it_fsm_pre_encode (void)
18395 if (inst
.cond
!= COND_ALWAYS
)
18396 inst
.it_insn_type
= INSIDE_IT_INSN
;
18398 inst
.it_insn_type
= OUTSIDE_IT_INSN
;
18400 now_it
.state_handled
= 0;
18403 /* IT state FSM handling function. */
18406 handle_it_state (void)
18408 now_it
.state_handled
= 1;
18409 now_it
.insn_cond
= FALSE
;
18411 switch (now_it
.state
)
18413 case OUTSIDE_IT_BLOCK
:
18414 switch (inst
.it_insn_type
)
18416 case OUTSIDE_IT_INSN
:
18419 case INSIDE_IT_INSN
:
18420 case INSIDE_IT_LAST_INSN
:
18421 if (thumb_mode
== 0)
18424 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
18425 as_tsktsk (_("Warning: conditional outside an IT block"\
18430 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
18431 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
18433 /* Automatically generate the IT instruction. */
18434 new_automatic_it_block (inst
.cond
);
18435 if (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
)
18436 close_automatic_it_block ();
18440 inst
.error
= BAD_OUT_IT
;
18446 case IF_INSIDE_IT_LAST_INSN
:
18447 case NEUTRAL_IT_INSN
:
18451 now_it
.state
= MANUAL_IT_BLOCK
;
18452 now_it
.block_length
= 0;
18457 case AUTOMATIC_IT_BLOCK
:
18458 /* Three things may happen now:
18459 a) We should increment current it block size;
18460 b) We should close current it block (closing insn or 4 insns);
18461 c) We should close current it block and start a new one (due
18462 to incompatible conditions or
18463 4 insns-length block reached). */
18465 switch (inst
.it_insn_type
)
18467 case OUTSIDE_IT_INSN
:
18468 /* The closure of the block shall happen immediately,
18469 so any in_it_block () call reports the block as closed. */
18470 force_automatic_it_block_close ();
18473 case INSIDE_IT_INSN
:
18474 case INSIDE_IT_LAST_INSN
:
18475 case IF_INSIDE_IT_LAST_INSN
:
18476 now_it
.block_length
++;
18478 if (now_it
.block_length
> 4
18479 || !now_it_compatible (inst
.cond
))
18481 force_automatic_it_block_close ();
18482 if (inst
.it_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
18483 new_automatic_it_block (inst
.cond
);
18487 now_it
.insn_cond
= TRUE
;
18488 now_it_add_mask (inst
.cond
);
18491 if (now_it
.state
== AUTOMATIC_IT_BLOCK
18492 && (inst
.it_insn_type
== INSIDE_IT_LAST_INSN
18493 || inst
.it_insn_type
== IF_INSIDE_IT_LAST_INSN
))
18494 close_automatic_it_block ();
18497 case NEUTRAL_IT_INSN
:
18498 now_it
.block_length
++;
18499 now_it
.insn_cond
= TRUE
;
18501 if (now_it
.block_length
> 4)
18502 force_automatic_it_block_close ();
18504 now_it_add_mask (now_it
.cc
& 1);
18508 close_automatic_it_block ();
18509 now_it
.state
= MANUAL_IT_BLOCK
;
18514 case MANUAL_IT_BLOCK
:
18516 /* Check conditional suffixes. */
18517 const int cond
= now_it
.cc
^ ((now_it
.mask
>> 4) & 1) ^ 1;
18520 now_it
.mask
&= 0x1f;
18521 is_last
= (now_it
.mask
== 0x10);
18522 now_it
.insn_cond
= TRUE
;
18524 switch (inst
.it_insn_type
)
18526 case OUTSIDE_IT_INSN
:
18527 inst
.error
= BAD_NOT_IT
;
18530 case INSIDE_IT_INSN
:
18531 if (cond
!= inst
.cond
)
18533 inst
.error
= BAD_IT_COND
;
18538 case INSIDE_IT_LAST_INSN
:
18539 case IF_INSIDE_IT_LAST_INSN
:
18540 if (cond
!= inst
.cond
)
18542 inst
.error
= BAD_IT_COND
;
18547 inst
.error
= BAD_BRANCH
;
18552 case NEUTRAL_IT_INSN
:
18553 /* The BKPT instruction is unconditional even in an IT block. */
18557 inst
.error
= BAD_IT_IT
;
18567 struct depr_insn_mask
18569 unsigned long pattern
;
18570 unsigned long mask
;
18571 const char* description
;
18574 /* List of 16-bit instruction patterns deprecated in an IT block in
18576 static const struct depr_insn_mask depr_it_insns
[] = {
18577 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
18578 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
18579 { 0xa000, 0xb800, N_("ADR") },
18580 { 0x4800, 0xf800, N_("Literal loads") },
18581 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
18582 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
18583 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
18584 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
18585 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
18590 it_fsm_post_encode (void)
18594 if (!now_it
.state_handled
)
18595 handle_it_state ();
18597 if (now_it
.insn_cond
18598 && !now_it
.warn_deprecated
18599 && warn_on_deprecated
18600 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
18601 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
18603 if (inst
.instruction
>= 0x10000)
18605 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
18606 "performance deprecated in ARMv8-A and ARMv8-R"));
18607 now_it
.warn_deprecated
= TRUE
;
18611 const struct depr_insn_mask
*p
= depr_it_insns
;
18613 while (p
->mask
!= 0)
18615 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
18617 as_tsktsk (_("IT blocks containing 16-bit Thumb "
18618 "instructions of the following class are "
18619 "performance deprecated in ARMv8-A and "
18620 "ARMv8-R: %s"), p
->description
);
18621 now_it
.warn_deprecated
= TRUE
;
18629 if (now_it
.block_length
> 1)
18631 as_tsktsk (_("IT blocks containing more than one conditional "
18632 "instruction are performance deprecated in ARMv8-A and "
18634 now_it
.warn_deprecated
= TRUE
;
18638 is_last
= (now_it
.mask
== 0x10);
18641 now_it
.state
= OUTSIDE_IT_BLOCK
;
18647 force_automatic_it_block_close (void)
18649 if (now_it
.state
== AUTOMATIC_IT_BLOCK
)
18651 close_automatic_it_block ();
18652 now_it
.state
= OUTSIDE_IT_BLOCK
;
18660 if (!now_it
.state_handled
)
18661 handle_it_state ();
18663 return now_it
.state
!= OUTSIDE_IT_BLOCK
;
18666 /* Whether OPCODE only has T32 encoding. Since this function is only used by
18667 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
18668 here, hence the "known" in the function name. */
18671 known_t32_only_insn (const struct asm_opcode
*opcode
)
18673 /* Original Thumb-1 wide instruction. */
18674 if (opcode
->tencode
== do_t_blx
18675 || opcode
->tencode
== do_t_branch23
18676 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
18677 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
18680 /* Wide-only instruction added to ARMv8-M Baseline. */
18681 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
18682 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
18683 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
18684 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
18690 /* Whether wide instruction variant can be used if available for a valid OPCODE
18694 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
18696 if (known_t32_only_insn (opcode
))
18699 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
18700 of variant T3 of B.W is checked in do_t_branch. */
18701 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18702 && opcode
->tencode
== do_t_branch
)
18705 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
18706 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
18707 && opcode
->tencode
== do_t_mov_cmp
18708 /* Make sure CMP instruction is not affected. */
18709 && opcode
->aencode
== do_mov
)
18712 /* Wide instruction variants of all instructions with narrow *and* wide
18713 variants become available with ARMv6t2. Other opcodes are either
18714 narrow-only or wide-only and are thus available if OPCODE is valid. */
18715 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
18718 /* OPCODE with narrow only instruction variant or wide variant not
18724 md_assemble (char *str
)
18727 const struct asm_opcode
* opcode
;
18729 /* Align the previous label if needed. */
18730 if (last_label_seen
!= NULL
)
18732 symbol_set_frag (last_label_seen
, frag_now
);
18733 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
18734 S_SET_SEGMENT (last_label_seen
, now_seg
);
18737 memset (&inst
, '\0', sizeof (inst
));
18738 inst
.reloc
.type
= BFD_RELOC_UNUSED
;
18740 opcode
= opcode_lookup (&p
);
18743 /* It wasn't an instruction, but it might be a register alias of
18744 the form alias .req reg, or a Neon .dn/.qn directive. */
18745 if (! create_register_alias (str
, p
)
18746 && ! create_neon_reg_alias (str
, p
))
18747 as_bad (_("bad instruction `%s'"), str
);
18752 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
18753 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
18755 /* The value which unconditional instructions should have in place of the
18756 condition field. */
18757 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
18761 arm_feature_set variant
;
18763 variant
= cpu_variant
;
18764 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
18765 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
18766 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
18767 /* Check that this instruction is supported for this CPU. */
18768 if (!opcode
->tvariant
18769 || (thumb_mode
== 1
18770 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
18772 if (opcode
->tencode
== do_t_swi
)
18773 as_bad (_("SVC is not permitted on this architecture"));
18775 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
18778 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
18779 && opcode
->tencode
!= do_t_branch
)
18781 as_bad (_("Thumb does not support conditional execution"));
18785 /* Two things are addressed here:
18786 1) Implicit require narrow instructions on Thumb-1.
18787 This avoids relaxation accidentally introducing Thumb-2
18789 2) Reject wide instructions in non Thumb-2 cores.
18791 Only instructions with narrow and wide variants need to be handled
18792 but selecting all non wide-only instructions is easier. */
18793 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
18794 && !t32_insn_ok (variant
, opcode
))
18796 if (inst
.size_req
== 0)
18798 else if (inst
.size_req
== 4)
18800 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
18801 as_bad (_("selected processor does not support 32bit wide "
18802 "variant of instruction `%s'"), str
);
18804 as_bad (_("selected processor does not support `%s' in "
18805 "Thumb-2 mode"), str
);
18810 inst
.instruction
= opcode
->tvalue
;
18812 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
18814 /* Prepare the it_insn_type for those encodings that don't set
18816 it_fsm_pre_encode ();
18818 opcode
->tencode ();
18820 it_fsm_post_encode ();
18823 if (!(inst
.error
|| inst
.relax
))
18825 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
18826 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
18827 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
18829 as_bad (_("cannot honor width suffix -- `%s'"), str
);
18834 /* Something has gone badly wrong if we try to relax a fixed size
18836 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
18838 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18839 *opcode
->tvariant
);
18840 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
18841 set those bits when Thumb-2 32-bit instructions are seen. The impact
18842 of relaxable instructions will be considered later after we finish all
18844 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
18845 variant
= arm_arch_none
;
18847 variant
= cpu_variant
;
18848 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
18849 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
18852 check_neon_suffixes
;
18856 mapping_state (MAP_THUMB
);
18859 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
18863 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
18864 is_bx
= (opcode
->aencode
== do_bx
);
18866 /* Check that this instruction is supported for this CPU. */
18867 if (!(is_bx
&& fix_v4bx
)
18868 && !(opcode
->avariant
&&
18869 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
18871 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
18876 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
18880 inst
.instruction
= opcode
->avalue
;
18881 if (opcode
->tag
== OT_unconditionalF
)
18882 inst
.instruction
|= 0xFU
<< 28;
18884 inst
.instruction
|= inst
.cond
<< 28;
18885 inst
.size
= INSN_SIZE
;
18886 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
18888 it_fsm_pre_encode ();
18889 opcode
->aencode ();
18890 it_fsm_post_encode ();
18892 /* Arm mode bx is marked as both v4T and v5 because it's still required
18893 on a hypothetical non-thumb v5 core. */
18895 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
18897 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
18898 *opcode
->avariant
);
18900 check_neon_suffixes
;
18904 mapping_state (MAP_ARM
);
18909 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
18917 check_it_blocks_finished (void)
18922 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
18923 if (seg_info (sect
)->tc_segment_info_data
.current_it
.state
18924 == MANUAL_IT_BLOCK
)
18926 as_warn (_("section '%s' finished with an open IT block."),
18930 if (now_it
.state
== MANUAL_IT_BLOCK
)
18931 as_warn (_("file finished with an open IT block."));
18935 /* Various frobbings of labels and their addresses. */
18938 arm_start_line_hook (void)
18940 last_label_seen
= NULL
;
18944 arm_frob_label (symbolS
* sym
)
18946 last_label_seen
= sym
;
18948 ARM_SET_THUMB (sym
, thumb_mode
);
18950 #if defined OBJ_COFF || defined OBJ_ELF
18951 ARM_SET_INTERWORK (sym
, support_interwork
);
18954 force_automatic_it_block_close ();
18956 /* Note - do not allow local symbols (.Lxxx) to be labelled
18957 as Thumb functions. This is because these labels, whilst
18958 they exist inside Thumb code, are not the entry points for
18959 possible ARM->Thumb calls. Also, these labels can be used
18960 as part of a computed goto or switch statement. eg gcc
18961 can generate code that looks like this:
18963 ldr r2, [pc, .Laaa]
18973 The first instruction loads the address of the jump table.
18974 The second instruction converts a table index into a byte offset.
18975 The third instruction gets the jump address out of the table.
18976 The fourth instruction performs the jump.
18978 If the address stored at .Laaa is that of a symbol which has the
18979 Thumb_Func bit set, then the linker will arrange for this address
18980 to have the bottom bit set, which in turn would mean that the
18981 address computation performed by the third instruction would end
18982 up with the bottom bit set. Since the ARM is capable of unaligned
18983 word loads, the instruction would then load the incorrect address
18984 out of the jump table, and chaos would ensue. */
18985 if (label_is_thumb_function_name
18986 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
18987 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
18989 /* When the address of a Thumb function is taken the bottom
18990 bit of that address should be set. This will allow
18991 interworking between Arm and Thumb functions to work
18994 THUMB_SET_FUNC (sym
, 1);
18996 label_is_thumb_function_name
= FALSE
;
18999 dwarf2_emit_label (sym
);
19003 arm_data_in_code (void)
19005 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
19007 *input_line_pointer
= '/';
19008 input_line_pointer
+= 5;
19009 *input_line_pointer
= 0;
19017 arm_canonicalize_symbol_name (char * name
)
19021 if (thumb_mode
&& (len
= strlen (name
)) > 5
19022 && streq (name
+ len
- 5, "/data"))
19023 *(name
+ len
- 5) = 0;
19028 /* Table of all register names defined by default. The user can
19029 define additional names with .req. Note that all register names
19030 should appear in both upper and lowercase variants. Some registers
19031 also have mixed-case names. */
19033 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
19034 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
19035 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
19036 #define REGSET(p,t) \
19037 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
19038 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
19039 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
19040 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
19041 #define REGSETH(p,t) \
19042 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
19043 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
19044 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
19045 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
19046 #define REGSET2(p,t) \
19047 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
19048 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
19049 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
19050 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
19051 #define SPLRBANK(base,bank,t) \
19052 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
19053 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
19054 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
19055 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
19056 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
19057 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
19059 static const struct reg_entry reg_names
[] =
19061 /* ARM integer registers. */
19062 REGSET(r
, RN
), REGSET(R
, RN
),
19064 /* ATPCS synonyms. */
19065 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
19066 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
19067 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
19069 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
19070 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
19071 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
19073 /* Well-known aliases. */
19074 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
19075 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
19077 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
19078 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
19080 /* Coprocessor numbers. */
19081 REGSET(p
, CP
), REGSET(P
, CP
),
19083 /* Coprocessor register numbers. The "cr" variants are for backward
19085 REGSET(c
, CN
), REGSET(C
, CN
),
19086 REGSET(cr
, CN
), REGSET(CR
, CN
),
19088 /* ARM banked registers. */
19089 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
19090 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
19091 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
19092 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
19093 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
19094 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
19095 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
19097 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
19098 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
19099 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
19100 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
19101 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
19102 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
19103 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
19104 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
19106 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
19107 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
19108 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
19109 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
19110 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
19111 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
19112 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
19113 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19114 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
19116 /* FPA registers. */
19117 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
19118 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
19120 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
19121 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
19123 /* VFP SP registers. */
19124 REGSET(s
,VFS
), REGSET(S
,VFS
),
19125 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
19127 /* VFP DP Registers. */
19128 REGSET(d
,VFD
), REGSET(D
,VFD
),
19129 /* Extra Neon DP registers. */
19130 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
19132 /* Neon QP registers. */
19133 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
19135 /* VFP control registers. */
19136 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
19137 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
19138 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
19139 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
19140 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
19141 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
19142 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
19144 /* Maverick DSP coprocessor registers. */
19145 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
19146 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
19148 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
19149 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
19150 REGDEF(dspsc
,0,DSPSC
),
19152 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
19153 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
19154 REGDEF(DSPSC
,0,DSPSC
),
19156 /* iWMMXt data registers - p0, c0-15. */
19157 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
19159 /* iWMMXt control registers - p1, c0-3. */
19160 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
19161 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
19162 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
19163 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
19165 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
19166 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
19167 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
19168 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
19169 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
19171 /* XScale accumulator registers. */
19172 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
19178 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
19179 within psr_required_here. */
19180 static const struct asm_psr psrs
[] =
19182 /* Backward compatibility notation. Note that "all" is no longer
19183 truly all possible PSR bits. */
19184 {"all", PSR_c
| PSR_f
},
19188 /* Individual flags. */
19194 /* Combinations of flags. */
19195 {"fs", PSR_f
| PSR_s
},
19196 {"fx", PSR_f
| PSR_x
},
19197 {"fc", PSR_f
| PSR_c
},
19198 {"sf", PSR_s
| PSR_f
},
19199 {"sx", PSR_s
| PSR_x
},
19200 {"sc", PSR_s
| PSR_c
},
19201 {"xf", PSR_x
| PSR_f
},
19202 {"xs", PSR_x
| PSR_s
},
19203 {"xc", PSR_x
| PSR_c
},
19204 {"cf", PSR_c
| PSR_f
},
19205 {"cs", PSR_c
| PSR_s
},
19206 {"cx", PSR_c
| PSR_x
},
19207 {"fsx", PSR_f
| PSR_s
| PSR_x
},
19208 {"fsc", PSR_f
| PSR_s
| PSR_c
},
19209 {"fxs", PSR_f
| PSR_x
| PSR_s
},
19210 {"fxc", PSR_f
| PSR_x
| PSR_c
},
19211 {"fcs", PSR_f
| PSR_c
| PSR_s
},
19212 {"fcx", PSR_f
| PSR_c
| PSR_x
},
19213 {"sfx", PSR_s
| PSR_f
| PSR_x
},
19214 {"sfc", PSR_s
| PSR_f
| PSR_c
},
19215 {"sxf", PSR_s
| PSR_x
| PSR_f
},
19216 {"sxc", PSR_s
| PSR_x
| PSR_c
},
19217 {"scf", PSR_s
| PSR_c
| PSR_f
},
19218 {"scx", PSR_s
| PSR_c
| PSR_x
},
19219 {"xfs", PSR_x
| PSR_f
| PSR_s
},
19220 {"xfc", PSR_x
| PSR_f
| PSR_c
},
19221 {"xsf", PSR_x
| PSR_s
| PSR_f
},
19222 {"xsc", PSR_x
| PSR_s
| PSR_c
},
19223 {"xcf", PSR_x
| PSR_c
| PSR_f
},
19224 {"xcs", PSR_x
| PSR_c
| PSR_s
},
19225 {"cfs", PSR_c
| PSR_f
| PSR_s
},
19226 {"cfx", PSR_c
| PSR_f
| PSR_x
},
19227 {"csf", PSR_c
| PSR_s
| PSR_f
},
19228 {"csx", PSR_c
| PSR_s
| PSR_x
},
19229 {"cxf", PSR_c
| PSR_x
| PSR_f
},
19230 {"cxs", PSR_c
| PSR_x
| PSR_s
},
19231 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
19232 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
19233 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
19234 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
19235 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
19236 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
19237 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
19238 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
19239 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
19240 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
19241 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
19242 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
19243 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
19244 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
19245 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
19246 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
19247 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
19248 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
19249 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
19250 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
19251 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
19252 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
19253 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
19254 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
19257 /* Table of V7M psr names. */
19258 static const struct asm_psr v7m_psrs
[] =
19260 {"apsr", 0x0 }, {"APSR", 0x0 },
19261 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
19262 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
19263 {"psr", 0x3 }, {"PSR", 0x3 },
19264 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
19265 {"ipsr", 0x5 }, {"IPSR", 0x5 },
19266 {"epsr", 0x6 }, {"EPSR", 0x6 },
19267 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
19268 {"msp", 0x8 }, {"MSP", 0x8 },
19269 {"psp", 0x9 }, {"PSP", 0x9 },
19270 {"msplim", 0xa }, {"MSPLIM", 0xa },
19271 {"psplim", 0xb }, {"PSPLIM", 0xb },
19272 {"primask", 0x10}, {"PRIMASK", 0x10},
19273 {"basepri", 0x11}, {"BASEPRI", 0x11},
19274 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
19275 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
19276 {"control", 0x14}, {"CONTROL", 0x14},
19277 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
19278 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
19279 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
19280 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
19281 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
19282 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
19283 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
19284 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
19285 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
19288 /* Table of all shift-in-operand names. */
19289 static const struct asm_shift_name shift_names
[] =
19291 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
19292 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
19293 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
19294 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
19295 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
19296 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
}
19299 /* Table of all explicit relocation names. */
19301 static struct reloc_entry reloc_names
[] =
19303 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
19304 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
19305 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
19306 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
19307 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
19308 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
19309 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
19310 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
19311 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
19312 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
19313 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
19314 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
19315 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
19316 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
19317 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
19318 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
19319 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
19320 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
}
19324 /* Table of all conditional affixes. 0xF is not defined as a condition code. */
19325 static const struct asm_cond conds
[] =
19329 {"cs", 0x2}, {"hs", 0x2},
19330 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
19344 #define UL_BARRIER(L,U,CODE,FEAT) \
19345 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
19346 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
19348 static struct asm_barrier_opt barrier_opt_names
[] =
19350 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
19351 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
19352 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
19353 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
19354 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
19355 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
19356 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
19357 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
19358 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
19359 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
19360 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
19361 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
19362 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
19363 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
19364 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
19365 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
19370 /* Table of ARM-format instructions. */
19372 /* Macros for gluing together operand strings. N.B. In all cases
19373 other than OPS0, the trailing OP_stop comes from default
19374 zero-initialization of the unspecified elements of the array. */
19375 #define OPS0() { OP_stop, }
19376 #define OPS1(a) { OP_##a, }
19377 #define OPS2(a,b) { OP_##a,OP_##b, }
19378 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
19379 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
19380 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
19381 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
19383 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
19384 This is useful when mixing operands for ARM and THUMB, i.e. using the
19385 MIX_ARM_THUMB_OPERANDS macro.
19386 In order to use these macros, prefix the number of operands with _
19388 #define OPS_1(a) { a, }
19389 #define OPS_2(a,b) { a,b, }
19390 #define OPS_3(a,b,c) { a,b,c, }
19391 #define OPS_4(a,b,c,d) { a,b,c,d, }
19392 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
19393 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
19395 /* These macros abstract out the exact format of the mnemonic table and
19396 save some repeated characters. */
19398 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
19399 #define TxCE(mnem, op, top, nops, ops, ae, te) \
19400 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
19401 THUMB_VARIANT, do_##ae, do_##te }
19403 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
19404 a T_MNEM_xyz enumerator. */
19405 #define TCE(mnem, aop, top, nops, ops, ae, te) \
19406 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
19407 #define tCE(mnem, aop, top, nops, ops, ae, te) \
19408 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19410 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
19411 infix after the third character. */
19412 #define TxC3(mnem, op, top, nops, ops, ae, te) \
19413 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
19414 THUMB_VARIANT, do_##ae, do_##te }
19415 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
19416 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
19417 THUMB_VARIANT, do_##ae, do_##te }
19418 #define TC3(mnem, aop, top, nops, ops, ae, te) \
19419 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
19420 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
19421 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
19422 #define tC3(mnem, aop, top, nops, ops, ae, te) \
19423 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19424 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
19425 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
19427 /* Mnemonic that cannot be conditionalized. The ARM condition-code
19428 field is still 0xE. Many of the Thumb variants can be executed
19429 conditionally, so this is checked separately. */
19430 #define TUE(mnem, op, top, nops, ops, ae, te) \
19431 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19432 THUMB_VARIANT, do_##ae, do_##te }
19434 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
19435 Used by mnemonics that have very minimal differences in the encoding for
19436 ARM and Thumb variants and can be handled in a common function. */
19437 #define TUEc(mnem, op, top, nops, ops, en) \
19438 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
19439 THUMB_VARIANT, do_##en, do_##en }
19441 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
19442 condition code field. */
19443 #define TUF(mnem, op, top, nops, ops, ae, te) \
19444 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
19445 THUMB_VARIANT, do_##ae, do_##te }
19447 /* ARM-only variants of all the above. */
19448 #define CE(mnem, op, nops, ops, ae) \
19449 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19451 #define C3(mnem, op, nops, ops, ae) \
19452 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19454 /* Thumb-only variants of TCE and TUE. */
19455 #define ToC(mnem, top, nops, ops, te) \
19456 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
19459 #define ToU(mnem, top, nops, ops, te) \
19460 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
19463 /* Legacy mnemonics that always have conditional infix after the third
19465 #define CL(mnem, op, nops, ops, ae) \
19466 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19467 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19469 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
19470 #define cCE(mnem, op, nops, ops, ae) \
19471 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19473 /* Legacy coprocessor instructions where conditional infix and conditional
19474 suffix are ambiguous. For consistency this includes all FPA instructions,
19475 not just the potentially ambiguous ones. */
19476 #define cCL(mnem, op, nops, ops, ae) \
19477 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
19478 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19480 /* Coprocessor, takes either a suffix or a position-3 infix
19481 (for an FPA corner case). */
19482 #define C3E(mnem, op, nops, ops, ae) \
19483 { mnem, OPS##nops ops, OT_csuf_or_in3, \
19484 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae }
19486 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
19487 { m1 #m2 m3, OPS##nops ops, \
19488 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
19489 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL }
19491 #define CM(m1, m2, op, nops, ops, ae) \
19492 xCM_ (m1, , m2, op, nops, ops, ae), \
19493 xCM_ (m1, eq, m2, op, nops, ops, ae), \
19494 xCM_ (m1, ne, m2, op, nops, ops, ae), \
19495 xCM_ (m1, cs, m2, op, nops, ops, ae), \
19496 xCM_ (m1, hs, m2, op, nops, ops, ae), \
19497 xCM_ (m1, cc, m2, op, nops, ops, ae), \
19498 xCM_ (m1, ul, m2, op, nops, ops, ae), \
19499 xCM_ (m1, lo, m2, op, nops, ops, ae), \
19500 xCM_ (m1, mi, m2, op, nops, ops, ae), \
19501 xCM_ (m1, pl, m2, op, nops, ops, ae), \
19502 xCM_ (m1, vs, m2, op, nops, ops, ae), \
19503 xCM_ (m1, vc, m2, op, nops, ops, ae), \
19504 xCM_ (m1, hi, m2, op, nops, ops, ae), \
19505 xCM_ (m1, ls, m2, op, nops, ops, ae), \
19506 xCM_ (m1, ge, m2, op, nops, ops, ae), \
19507 xCM_ (m1, lt, m2, op, nops, ops, ae), \
19508 xCM_ (m1, gt, m2, op, nops, ops, ae), \
19509 xCM_ (m1, le, m2, op, nops, ops, ae), \
19510 xCM_ (m1, al, m2, op, nops, ops, ae)
19512 #define UE(mnem, op, nops, ops, ae) \
19513 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19515 #define UF(mnem, op, nops, ops, ae) \
19516 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL }
19518 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
19519 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
19520 use the same encoding function for each. */
19521 #define NUF(mnem, op, nops, ops, enc) \
19522 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
19523 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19525 /* Neon data processing, version which indirects through neon_enc_tab for
19526 the various overloaded versions of opcodes. */
19527 #define nUF(mnem, op, nops, ops, enc) \
19528 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
19529 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19531 /* Neon insn with conditional suffix for the ARM version, non-overloaded
19533 #define NCE_tag(mnem, op, nops, ops, enc, tag) \
19534 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
19535 THUMB_VARIANT, do_##enc, do_##enc }
19537 #define NCE(mnem, op, nops, ops, enc) \
19538 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19540 #define NCEF(mnem, op, nops, ops, enc) \
19541 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19543 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
19544 #define nCE_tag(mnem, op, nops, ops, enc, tag) \
19545 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
19546 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc }
19548 #define nCE(mnem, op, nops, ops, enc) \
19549 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix)
19551 #define nCEF(mnem, op, nops, ops, enc) \
19552 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF)
19556 static const struct asm_opcode insns
[] =
19558 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
19559 #define THUMB_VARIANT & arm_ext_v4t
19560 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19561 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19562 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19563 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19564 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19565 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
19566 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19567 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
19568 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19569 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19570 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19571 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19572 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19573 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
19574 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19575 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
19577 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
19578 for setting PSR flag bits. They are obsolete in V6 and do not
19579 have Thumb equivalents. */
19580 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19581 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19582 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
19583 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19584 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
19585 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
19586 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19587 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19588 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
19590 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
19591 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
19592 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19593 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
19595 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
19596 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19597 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
19599 OP_ADDRGLDR
),ldst
, t_ldst
),
19600 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
19602 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19603 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19604 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19605 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19606 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19607 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19609 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
19610 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
19613 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
19614 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
19615 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
19616 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
19618 /* Thumb-compatibility pseudo ops. */
19619 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19620 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19621 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19622 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19623 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19624 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19625 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19626 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
19627 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
19628 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
19629 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
19630 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
19632 /* These may simplify to neg. */
19633 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19634 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
19636 #undef THUMB_VARIANT
19637 #define THUMB_VARIANT & arm_ext_os
19639 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19640 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
19642 #undef THUMB_VARIANT
19643 #define THUMB_VARIANT & arm_ext_v6
19645 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
19647 /* V1 instructions with no Thumb analogue prior to V6T2. */
19648 #undef THUMB_VARIANT
19649 #define THUMB_VARIANT & arm_ext_v6t2
19651 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19652 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
19653 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
19655 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19656 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19657 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
19658 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
19660 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19661 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19663 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19664 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
19666 /* V1 instructions with no Thumb analogue at all. */
19667 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
19668 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
19670 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19671 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
19672 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19673 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
19674 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19675 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
19676 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19677 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
19680 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
19681 #undef THUMB_VARIANT
19682 #define THUMB_VARIANT & arm_ext_v4t
19684 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19685 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
19687 #undef THUMB_VARIANT
19688 #define THUMB_VARIANT & arm_ext_v6t2
19690 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
19691 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
19693 /* Generic coprocessor instructions. */
19694 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19695 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19696 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19697 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19698 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19699 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19700 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19703 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
19705 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19706 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
19709 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
19710 #undef THUMB_VARIANT
19711 #define THUMB_VARIANT & arm_ext_msr
19713 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
19714 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
19717 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
19718 #undef THUMB_VARIANT
19719 #define THUMB_VARIANT & arm_ext_v6t2
19721 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19722 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19723 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19724 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19725 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19726 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19727 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
19728 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
19731 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
19732 #undef THUMB_VARIANT
19733 #define THUMB_VARIANT & arm_ext_v4t
19735 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19736 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19737 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19738 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19739 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19740 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
19743 #define ARM_VARIANT & arm_ext_v4t_5
19745 /* ARM Architecture 4T. */
19746 /* Note: bx (and blx) are required on V5, even if the processor does
19747 not support Thumb. */
19748 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
19751 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
19752 #undef THUMB_VARIANT
19753 #define THUMB_VARIANT & arm_ext_v5t
19755 /* Note: blx has 2 variants; the .value coded here is for
19756 BLX(2). Only this variant has conditional execution. */
19757 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
19758 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
19760 #undef THUMB_VARIANT
19761 #define THUMB_VARIANT & arm_ext_v6t2
19763 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
19764 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19765 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19766 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19767 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
19768 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
19769 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19770 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
19773 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
19774 #undef THUMB_VARIANT
19775 #define THUMB_VARIANT & arm_ext_v5exp
19777 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19778 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19779 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19780 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19782 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19783 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
19785 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19786 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19787 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19788 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
19790 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19791 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19792 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19793 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19795 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19796 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19798 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19799 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19800 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19801 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
19804 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
19805 #undef THUMB_VARIANT
19806 #define THUMB_VARIANT & arm_ext_v6t2
19808 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
19809 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
19811 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
19812 ADDRGLDRS
), ldrd
, t_ldstd
),
19814 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19815 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19818 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
19820 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
19823 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
19824 #undef THUMB_VARIANT
19825 #define THUMB_VARIANT & arm_ext_v6
19827 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19828 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
19829 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19830 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19831 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
19832 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19833 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19834 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19835 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19836 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
19838 #undef THUMB_VARIANT
19839 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19841 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
19842 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19844 #undef THUMB_VARIANT
19845 #define THUMB_VARIANT & arm_ext_v6t2
19847 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19848 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
19850 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
19851 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
19853 /* ARM V6 not included in V7M. */
19854 #undef THUMB_VARIANT
19855 #define THUMB_VARIANT & arm_ext_v6_notm
19856 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19857 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19858 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
19859 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
19860 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19861 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
19862 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
19863 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
19864 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
19865 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19866 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19867 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
19868 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19869 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
19870 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
19871 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
19872 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19873 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
19874 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
19876 /* ARM V6 not included in V7M (eg. integer SIMD). */
19877 #undef THUMB_VARIANT
19878 #define THUMB_VARIANT & arm_ext_v6_dsp
19879 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
19880 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
19881 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19882 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19883 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19884 /* Old name for QASX. */
19885 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19886 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19887 /* Old name for QSAX. */
19888 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19889 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19890 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19891 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19892 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19893 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19894 /* Old name for SASX. */
19895 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19896 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19897 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19898 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19899 /* Old name for SHASX. */
19900 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19901 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19902 /* Old name for SHSAX. */
19903 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19904 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19905 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19906 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19907 /* Old name for SSAX. */
19908 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19909 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19910 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19911 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19912 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19913 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19914 /* Old name for UASX. */
19915 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19916 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19917 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19918 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19919 /* Old name for UHASX. */
19920 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19921 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19922 /* Old name for UHSAX. */
19923 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19924 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19925 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19926 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19927 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19928 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19929 /* Old name for UQASX. */
19930 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19931 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19932 /* Old name for UQSAX. */
19933 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19934 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19935 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19936 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19937 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19938 /* Old name for USAX. */
19939 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19940 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19941 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19942 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19943 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19944 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19945 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19946 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19947 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
19948 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
19949 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
19950 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19951 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19952 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19953 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19954 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19955 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19956 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19957 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
19958 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19959 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19960 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19961 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19962 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19963 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19964 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19965 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19966 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19967 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19968 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
19969 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
19970 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
19971 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
19972 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
19975 #define ARM_VARIANT & arm_ext_v6k
19976 #undef THUMB_VARIANT
19977 #define THUMB_VARIANT & arm_ext_v6k
19979 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
19980 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
19981 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
19982 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
19984 #undef THUMB_VARIANT
19985 #define THUMB_VARIANT & arm_ext_v6_notm
19986 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
19988 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
19989 RRnpcb
), strexd
, t_strexd
),
19991 #undef THUMB_VARIANT
19992 #define THUMB_VARIANT & arm_ext_v6t2_v8m
19993 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
19995 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
19997 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
19999 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
20001 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
20004 #define ARM_VARIANT & arm_ext_sec
20005 #undef THUMB_VARIANT
20006 #define THUMB_VARIANT & arm_ext_sec
20008 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
20011 #define ARM_VARIANT & arm_ext_virt
20012 #undef THUMB_VARIANT
20013 #define THUMB_VARIANT & arm_ext_virt
20015 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
20016 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
20019 #define ARM_VARIANT & arm_ext_pan
20020 #undef THUMB_VARIANT
20021 #define THUMB_VARIANT & arm_ext_pan
20023 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
20026 #define ARM_VARIANT & arm_ext_v6t2
20027 #undef THUMB_VARIANT
20028 #define THUMB_VARIANT & arm_ext_v6t2
20030 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
20031 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
20032 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20033 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
20035 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
20036 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
20038 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20039 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20040 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20041 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
20044 #define ARM_VARIANT & arm_ext_v3
20045 #undef THUMB_VARIANT
20046 #define THUMB_VARIANT & arm_ext_v6t2
20048 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
20051 #define ARM_VARIANT & arm_ext_v6t2
20052 #undef THUMB_VARIANT
20053 #define THUMB_VARIANT & arm_ext_v6t2_v8m
20054 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20055 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
20057 /* Thumb-only instructions. */
20059 #define ARM_VARIANT NULL
20060 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
20061 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
20063 /* ARM does not really have an IT instruction, so always allow it.
20064 The opcode is copied from Thumb in order to allow warnings in
20065 -mimplicit-it=[never | arm] modes. */
20067 #define ARM_VARIANT & arm_ext_v1
20068 #undef THUMB_VARIANT
20069 #define THUMB_VARIANT & arm_ext_v6t2
20071 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
20072 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
20073 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
20074 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
20075 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
20076 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
20077 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
20078 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
20079 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
20080 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
20081 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
20082 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
20083 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
20084 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
20085 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
20086 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
20087 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20088 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
20090 /* Thumb2 only instructions. */
20092 #define ARM_VARIANT NULL
20094 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20095 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
20096 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20097 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
20098 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
20099 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
20101 /* Hardware division instructions. */
20103 #define ARM_VARIANT & arm_ext_adiv
20104 #undef THUMB_VARIANT
20105 #define THUMB_VARIANT & arm_ext_div
20107 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20108 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
20110 /* ARM V6M/V7 instructions. */
20112 #define ARM_VARIANT & arm_ext_barrier
20113 #undef THUMB_VARIANT
20114 #define THUMB_VARIANT & arm_ext_barrier
20116 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
20117 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
20118 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
20120 /* ARM V7 instructions. */
20122 #define ARM_VARIANT & arm_ext_v7
20123 #undef THUMB_VARIANT
20124 #define THUMB_VARIANT & arm_ext_v7
20126 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
20127 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
20130 #define ARM_VARIANT & arm_ext_mp
20131 #undef THUMB_VARIANT
20132 #define THUMB_VARIANT & arm_ext_mp
20134 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
20136 /* AArchv8 instructions. */
20138 #define ARM_VARIANT & arm_ext_v8
20140 /* Instructions shared between armv8-a and armv8-m. */
20141 #undef THUMB_VARIANT
20142 #define THUMB_VARIANT & arm_ext_atomics
20144 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20145 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20146 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20147 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20148 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20149 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
20150 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20151 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
20152 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
20153 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20155 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20157 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
20159 #undef THUMB_VARIANT
20160 #define THUMB_VARIANT & arm_ext_v8
20162 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
20163 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
20164 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
20166 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
20168 /* ARMv8 T32 only. */
20170 #define ARM_VARIANT NULL
20171 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
20172 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
20173 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
20175 /* FP for ARMv8. */
20177 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
20178 #undef THUMB_VARIANT
20179 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
20181 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20182 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20183 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20184 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
20185 nUF(vmaxnm
, _vmaxnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20186 nUF(vminnm
, _vminnm
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), vmaxnm
),
20187 nUF(vcvta
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvta
),
20188 nUF(vcvtn
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtn
),
20189 nUF(vcvtp
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtp
),
20190 nUF(vcvtm
, _vcvta
, 2, (RNSDQ
, oRNSDQ
), neon_cvtm
),
20191 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
20192 nCE(vrintz
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintz
),
20193 nCE(vrintx
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintx
),
20194 nUF(vrinta
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrinta
),
20195 nUF(vrintn
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintn
),
20196 nUF(vrintp
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintp
),
20197 nUF(vrintm
, _vrinta
, 2, (RNSDQ
, oRNSDQ
), vrintm
),
20199 /* Crypto v1 extensions. */
20201 #define ARM_VARIANT & fpu_crypto_ext_armv8
20202 #undef THUMB_VARIANT
20203 #define THUMB_VARIANT & fpu_crypto_ext_armv8
20205 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
20206 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
20207 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
20208 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
20209 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
20210 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
20211 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
20212 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
20213 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
20214 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
20215 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
20216 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
20217 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
20218 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
20221 #define ARM_VARIANT & crc_ext_armv8
20222 #undef THUMB_VARIANT
20223 #define THUMB_VARIANT & crc_ext_armv8
20224 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
20225 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
20226 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
20227 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
20228 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
20229 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
20231 /* ARMv8.2 RAS extension. */
20233 #define ARM_VARIANT & arm_ext_ras
20234 #undef THUMB_VARIANT
20235 #define THUMB_VARIANT & arm_ext_ras
20236 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
20239 #define ARM_VARIANT & arm_ext_v8_3
20240 #undef THUMB_VARIANT
20241 #define THUMB_VARIANT & arm_ext_v8_3
20242 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
20243 NUF (vcmla
, 0, 4, (RNDQ
, RNDQ
, RNDQ_RNSC
, EXPi
), vcmla
),
20244 NUF (vcadd
, 0, 4, (RNDQ
, RNDQ
, RNDQ
, EXPi
), vcadd
),
20247 #define ARM_VARIANT & fpu_neon_ext_dotprod
20248 #undef THUMB_VARIANT
20249 #define THUMB_VARIANT & fpu_neon_ext_dotprod
20250 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
20251 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
20254 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
20255 #undef THUMB_VARIANT
20256 #define THUMB_VARIANT NULL
20258 cCE("wfs", e200110
, 1, (RR
), rd
),
20259 cCE("rfs", e300110
, 1, (RR
), rd
),
20260 cCE("wfc", e400110
, 1, (RR
), rd
),
20261 cCE("rfc", e500110
, 1, (RR
), rd
),
20263 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20264 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20265 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20266 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20268 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20269 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20270 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20271 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
20273 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
20274 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
20275 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
20276 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
20277 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
20278 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
20279 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
20280 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
20281 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
20282 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
20283 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
20284 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
20286 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
20287 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
20288 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
20289 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
20290 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
20291 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
20292 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
20293 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
20294 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
20295 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
20296 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
20297 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
20299 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
20300 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
20301 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
20302 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
20303 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
20304 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
20305 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
20306 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
20307 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
20308 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
20309 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
20310 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
20312 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
20313 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
20314 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
20315 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
20316 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
20317 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
20318 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
20319 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
20320 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
20321 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
20322 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
20323 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
20325 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
20326 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
20327 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
20328 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
20329 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
20330 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
20331 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
20332 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
20333 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
20334 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
20335 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
20336 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
20338 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
20339 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
20340 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
20341 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
20342 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
20343 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
20344 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
20345 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
20346 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
20347 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
20348 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
20349 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
20351 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
20352 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
20353 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
20354 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
20355 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
20356 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
20357 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
20358 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
20359 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
20360 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
20361 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
20362 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
20364 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
20365 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
20366 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
20367 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
20368 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
20369 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
20370 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
20371 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
20372 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
20373 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
20374 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
20375 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
20377 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
20378 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
20379 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
20380 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
20381 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
20382 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
20383 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
20384 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
20385 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
20386 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
20387 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
20388 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
20390 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
20391 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
20392 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
20393 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
20394 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
20395 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
20396 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
20397 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
20398 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
20399 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
20400 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
20401 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
20403 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
20404 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
20405 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
20406 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
20407 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
20408 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
20409 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
20410 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
20411 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
20412 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
20413 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
20414 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
20416 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
20417 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
20418 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
20419 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
20420 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
20421 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
20422 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
20423 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
20424 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
20425 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
20426 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
20427 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
20429 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
20430 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
20431 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
20432 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
20433 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
20434 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
20435 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
20436 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
20437 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
20438 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
20439 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
20440 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
20442 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
20443 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
20444 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
20445 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
20446 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
20447 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
20448 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
20449 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
20450 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
20451 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
20452 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
20453 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
20455 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
20456 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
20457 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
20458 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
20459 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
20460 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
20461 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
20462 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
20463 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
20464 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
20465 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
20466 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
20468 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
20469 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
20470 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
20471 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
20472 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
20473 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
20474 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
20475 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
20476 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
20477 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
20478 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
20479 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
20481 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20482 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20483 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20484 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20485 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20486 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20487 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20488 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20489 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20490 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20491 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20492 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20494 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20495 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20496 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20497 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20498 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20499 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20500 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20501 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20502 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20503 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20504 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20505 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20507 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20508 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20509 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20510 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20511 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20512 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20513 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20514 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20515 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20516 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20517 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20518 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20520 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20521 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20522 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20523 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20524 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20525 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20526 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20527 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20528 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20529 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20530 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20531 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20533 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20534 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20535 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20536 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20537 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20538 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20539 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20540 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20541 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20542 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20543 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20544 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20546 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20547 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20548 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20549 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20550 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20551 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20552 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20553 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20554 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20555 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20556 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20557 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20559 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20560 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20561 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20562 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20563 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20564 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20565 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20566 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20567 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20568 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20569 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20570 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20572 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20573 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20574 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20575 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20576 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20577 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20578 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20579 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20580 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20581 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20582 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20583 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20585 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20586 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20587 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20588 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20589 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20590 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20591 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20592 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20593 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20594 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20595 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20596 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20598 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20599 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20600 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20601 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20602 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20603 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20604 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20605 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20606 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20607 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20608 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20609 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20611 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20612 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20613 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20614 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20615 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20616 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20617 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20618 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20619 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20620 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20621 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20622 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20624 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20625 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20626 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20627 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20628 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20629 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20630 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20631 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20632 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20633 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20634 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20635 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20637 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20638 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20639 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20640 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20641 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20642 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20643 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20644 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20645 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20646 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20647 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20648 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
20650 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20651 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20652 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20653 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
20655 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
20656 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
20657 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
20658 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
20659 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
20660 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
20661 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
20662 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
20663 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
20664 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
20665 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
20666 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
20668 /* The implementation of the FIX instruction is broken on some
20669 assemblers, in that it accepts a precision specifier as well as a
20670 rounding specifier, despite the fact that this is meaningless.
20671 To be more compatible, we accept it as well, though of course it
20672 does not set any bits. */
20673 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
20674 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
20675 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
20676 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
20677 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
20678 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
20679 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
20680 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
20681 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
20682 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
20683 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
20684 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
20685 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
20687 /* Instructions that were new with the real FPA, call them V2. */
20689 #define ARM_VARIANT & fpu_fpa_ext_v2
20691 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20692 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20693 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20694 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20695 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20696 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
20699 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
20701 /* Moves and type conversions. */
20702 cCE("fcpys", eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20703 cCE("fmrs", e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
20704 cCE("fmsr", e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
20705 cCE("fmstat", ef1fa10
, 0, (), noargs
),
20706 cCE("vmrs", ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
20707 cCE("vmsr", ee00a10
, 2, (RVC
, RR
), vmsr
),
20708 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20709 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20710 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20711 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20712 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20713 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20714 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
20715 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
20717 /* Memory operations. */
20718 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20719 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
20720 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20721 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20722 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20723 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20724 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20725 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20726 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20727 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20728 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20729 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
20730 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20731 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
20732 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20733 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
20734 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20735 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
20737 /* Monadic operations. */
20738 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20739 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20740 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20742 /* Dyadic operations. */
20743 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20744 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20745 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20746 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20747 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20748 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20749 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20750 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20751 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
20754 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20755 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
20756 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
20757 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
20759 /* Double precision load/store are still present on single precision
20760 implementations. */
20761 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20762 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
20763 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20764 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20765 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20766 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20767 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20768 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
20769 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20770 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
20773 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
20775 /* Moves and type conversions. */
20776 cCE("fcpyd", eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20777 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20778 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20779 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20780 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
20781 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20782 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
20783 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20784 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
20785 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20786 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20787 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20788 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
20790 /* Monadic operations. */
20791 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20792 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20793 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20795 /* Dyadic operations. */
20796 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20797 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20798 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20799 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20800 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20801 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20802 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20803 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20804 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
20807 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20808 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
20809 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
20810 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
20813 #define ARM_VARIANT & fpu_vfp_ext_v2
20815 cCE("fmsrr", c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
20816 cCE("fmrrs", c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
20817 cCE("fmdrr", c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
20818 cCE("fmrrd", c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
20820 /* Instructions which may belong to either the Neon or VFP instruction sets.
20821 Individual encoder functions perform additional architecture checks. */
20823 #define ARM_VARIANT & fpu_vfp_ext_v1xd
20824 #undef THUMB_VARIANT
20825 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
20827 /* These mnemonics are unique to VFP. */
20828 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
20829 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
20830 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20831 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20832 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
20833 nCE(vcmp
, _vcmp
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20834 nCE(vcmpe
, _vcmpe
, 2, (RVSD
, RSVD_FI0
), vfp_nsyn_cmp
),
20835 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
20836 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
20837 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
20839 /* Mnemonics shared by Neon and VFP. */
20840 nCEF(vmul
, _vmul
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mul
),
20841 nCEF(vmla
, _vmla
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20842 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
20844 nCEF(vadd
, _vadd
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20845 nCEF(vsub
, _vsub
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_addsub_if_i
),
20847 NCEF(vabs
, 1b10300
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20848 NCEF(vneg
, 1b10380
, 2, (RNSDQ
, RNSDQ
), neon_abs_neg
),
20850 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20851 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20852 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20853 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20854 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20855 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
20856 NCE(vldr
, d100b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20857 NCE(vstr
, d000b00
, 2, (RVSD
, ADDRGLDC
), neon_ldr_str
),
20859 nCEF(vcvt
, _vcvt
, 3, (RNSDQ
, RNSDQ
, oI32z
), neon_cvt
),
20860 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
20861 NCEF(vcvtb
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtb
),
20862 NCEF(vcvtt
, eb20a40
, 2, (RVSD
, RVSD
), neon_cvtt
),
20865 /* NOTE: All VMOV encoding is special-cased! */
20866 NCE(vmov
, 0, 1, (VMOV
), neon_mov
),
20867 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
20870 #define ARM_VARIANT & arm_ext_fp16
20871 #undef THUMB_VARIANT
20872 #define THUMB_VARIANT & arm_ext_fp16
20873 /* New instructions added from v8.2, allowing the extraction and insertion of
20874 the upper 16 bits of a 32-bit vector register. */
20875 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
20876 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
20878 /* New backported fma/fms instructions optional in v8.2. */
20879 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
20880 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
20882 #undef THUMB_VARIANT
20883 #define THUMB_VARIANT & fpu_neon_ext_v1
20885 #define ARM_VARIANT & fpu_neon_ext_v1
20887 /* Data processing with three registers of the same length. */
20888 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
20889 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
20890 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
20891 NUF(vhadd
, 0000000, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20892 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20893 NUF(vrhadd
, 0000100, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20894 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20895 NUF(vhsub
, 0000200, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i_su
),
20896 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
20897 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
20898 NUF(vqadd
, 0000010, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20899 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20900 NUF(vqsub
, 0000210, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_i64_su
),
20901 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
20902 NUF(vrshl
, 0000500, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20903 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20904 NUF(vqrshl
, 0000510, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_rshl
),
20905 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
20906 /* If not immediate, fall back to neon_dyadic_i64_su.
20907 shl_imm should accept I8 I16 I32 I64,
20908 qshl_imm should accept S8 S16 S32 S64 U8 U16 U32 U64. */
20909 nUF(vshl
, _vshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_shl_imm
),
20910 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl_imm
),
20911 nUF(vqshl
, _vqshl
, 3, (RNDQ
, oRNDQ
, RNDQ_I63b
), neon_qshl_imm
),
20912 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl_imm
),
20913 /* Logic ops, types optional & ignored. */
20914 nUF(vand
, _vand
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20915 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20916 nUF(vbic
, _vbic
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20917 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20918 nUF(vorr
, _vorr
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20919 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20920 nUF(vorn
, _vorn
, 3, (RNDQ
, oRNDQ
, RNDQ_Ibig
), neon_logic
),
20921 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
20922 nUF(veor
, _veor
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_logic
),
20923 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
20924 /* Bitfield ops, untyped. */
20925 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20926 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20927 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20928 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20929 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
20930 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
20931 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
20932 nUF(vabd
, _vabd
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20933 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20934 nUF(vmax
, _vmax
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20935 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20936 nUF(vmin
, _vmin
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_dyadic_if_su
),
20937 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
20938 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
20939 back to neon_dyadic_if_su. */
20940 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20941 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20942 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
20943 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
20944 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20945 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20946 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
20947 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
20948 /* Comparison. Type I8 I16 I32 F32. */
20949 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
20950 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
20951 /* As above, D registers only. */
20952 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20953 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
20954 /* Int and float variants, signedness unimportant. */
20955 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20956 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
20957 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
20958 /* Add/sub take types I8 I16 I32 I64 F32. */
20959 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20960 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
20961 /* vtst takes sizes 8, 16, 32. */
20962 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
20963 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
20964 /* VMUL takes I8 I16 I32 F32 P8. */
20965 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
20966 /* VQD{R}MULH takes S16 S32. */
20967 nUF(vqdmulh
, _vqdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20968 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20969 nUF(vqrdmulh
, _vqrdmulh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qdmulh
),
20970 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
20971 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20972 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20973 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
20974 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
20975 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20976 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20977 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
20978 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
20979 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20980 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20981 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
20982 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
20983 /* ARM v8.1 extension. */
20984 nUF (vqrdmlah
, _vqrdmlah
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20985 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20986 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
20987 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
20989 /* Two address, int/float. Types S8 S16 S32 F32. */
20990 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20991 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
20993 /* Data processing with two registers and a shift amount. */
20994 /* Right shifts, and variants with rounding.
20995 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
20996 NUF(vshr
, 0800010, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20997 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
20998 NUF(vrshr
, 0800210, 3, (RNDQ
, oRNDQ
, I64z
), neon_rshift_round_imm
),
20999 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
21000 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21001 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21002 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
21003 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
21004 /* Shift and insert. Sizes accepted 8 16 32 64. */
21005 NUF(vsli
, 1800510, 3, (RNDQ
, oRNDQ
, I63
), neon_sli
),
21006 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
21007 NUF(vsri
, 1800410, 3, (RNDQ
, oRNDQ
, I64
), neon_sri
),
21008 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
21009 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
21010 NUF(vqshlu
, 1800610, 3, (RNDQ
, oRNDQ
, I63
), neon_qshlu_imm
),
21011 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
21012 /* Right shift immediate, saturating & narrowing, with rounding variants.
21013 Types accepted S16 S32 S64 U16 U32 U64. */
21014 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21015 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
21016 /* As above, unsigned. Types accepted S16 S32 S64. */
21017 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21018 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
21019 /* Right shift narrowing. Types accepted I16 I32 I64. */
21020 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21021 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
21022 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
21023 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
21024 /* CVT with optional immediate for fixed-point variant. */
21025 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
21027 nUF(vmvn
, _vmvn
, 2, (RNDQ
, RNDQ_Ibig
), neon_mvn
),
21028 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
21030 /* Data processing, three registers of different lengths. */
21031 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
21032 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
21033 NUF(vabdl
, 0800700, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21034 NUF(vaddl
, 0800000, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21035 NUF(vsubl
, 0800200, 3, (RNQ
, RND
, RND
), neon_dyadic_long
),
21036 /* If not scalar, fall back to neon_dyadic_long.
21037 Vector types as above, scalar types S16 S32 U16 U32. */
21038 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21039 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
21040 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
21041 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21042 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
21043 /* Dyadic, narrowing insns. Types I16 I32 I64. */
21044 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21045 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21046 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21047 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
21048 /* Saturating doubling multiplies. Types S16 S32. */
21049 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21050 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21051 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
21052 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
21053 S16 S32 U16 U32. */
21054 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
21056 /* Extract. Size 8. */
21057 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
21058 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
21060 /* Two registers, miscellaneous. */
21061 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
21062 NUF(vrev64
, 1b00000
, 2, (RNDQ
, RNDQ
), neon_rev
),
21063 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
21064 NUF(vrev32
, 1b00080
, 2, (RNDQ
, RNDQ
), neon_rev
),
21065 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
21066 NUF(vrev16
, 1b00100
, 2, (RNDQ
, RNDQ
), neon_rev
),
21067 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
21068 /* Vector replicate. Sizes 8 16 32. */
21069 nCE(vdup
, _vdup
, 2, (RNDQ
, RR_RNSC
), neon_dup
),
21070 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
21071 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
21072 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
21073 /* VMOVN. Types I16 I32 I64. */
21074 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
21075 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
21076 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
21077 /* VQMOVUN. Types S16 S32 S64. */
21078 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
21079 /* VZIP / VUZP. Sizes 8 16 32. */
21080 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21081 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21082 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
21083 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
21084 /* VQABS / VQNEG. Types S8 S16 S32. */
21085 NUF(vqabs
, 1b00700
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21086 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21087 NUF(vqneg
, 1b00780
, 2, (RNDQ
, RNDQ
), neon_sat_abs_neg
),
21088 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
21089 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
21090 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21091 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
21092 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
21093 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
21094 /* Reciprocal estimates. Types U32 F16 F32. */
21095 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21096 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
21097 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
21098 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
21099 /* VCLS. Types S8 S16 S32. */
21100 NUF(vcls
, 1b00400
, 2, (RNDQ
, RNDQ
), neon_cls
),
21101 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
21102 /* VCLZ. Types I8 I16 I32. */
21103 NUF(vclz
, 1b00480
, 2, (RNDQ
, RNDQ
), neon_clz
),
21104 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
21105 /* VCNT. Size 8. */
21106 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
21107 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
21108 /* Two address, untyped. */
21109 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
21110 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
21111 /* VTRN. Sizes 8 16 32. */
21112 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
21113 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
21115 /* Table lookup. Size 8. */
21116 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21117 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
21119 #undef THUMB_VARIANT
21120 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
21122 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
21124 /* Neon element/structure load/store. */
21125 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21126 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21127 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21128 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21129 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21130 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21131 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21132 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
21134 #undef THUMB_VARIANT
21135 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
21137 #define ARM_VARIANT & fpu_vfp_ext_v3xd
21138 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
21139 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21140 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21141 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21142 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21143 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21144 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21145 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
21146 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
21148 #undef THUMB_VARIANT
21149 #define THUMB_VARIANT & fpu_vfp_ext_v3
21151 #define ARM_VARIANT & fpu_vfp_ext_v3
21153 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
21154 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21155 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21156 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21157 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21158 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21159 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21160 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
21161 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
21164 #define ARM_VARIANT & fpu_vfp_ext_fma
21165 #undef THUMB_VARIANT
21166 #define THUMB_VARIANT & fpu_vfp_ext_fma
21167 /* Mnemonics shared by Neon and VFP. These are included in the
21168 VFP FMA variant; NEON and VFP FMA always includes the NEON
21169 FMA instructions. */
21170 nCEF(vfma
, _vfma
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21171 nCEF(vfms
, _vfms
, 3, (RNSDQ
, oRNSDQ
, RNSDQ
), neon_fmac
),
21172 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
21173 the v form should always be used. */
21174 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21175 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
21176 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21177 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
21178 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21179 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
21181 #undef THUMB_VARIANT
21183 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
21185 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21186 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21187 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21188 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21189 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21190 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
21191 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
21192 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
21195 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
21197 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
21198 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
21199 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
21200 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
21201 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
21202 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
21203 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
21204 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
21205 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
21206 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21207 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21208 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21209 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21210 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21211 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
21212 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21213 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21214 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
21215 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
21216 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
21217 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21218 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21219 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21220 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21221 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21222 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
21223 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
21224 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
21225 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
21226 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
21227 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
21228 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
21229 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
21230 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
21231 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21232 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21233 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21234 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21235 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21236 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21237 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21238 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21239 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21240 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21241 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21242 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21243 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
21244 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21245 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21246 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21247 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21248 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21249 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21250 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21251 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21252 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21253 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21254 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21255 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21256 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21257 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21258 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21259 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21260 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21261 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21262 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21263 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21264 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21265 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21266 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21267 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21268 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21269 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21270 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21271 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21272 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21273 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21274 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21275 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21276 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21277 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21278 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21279 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21280 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21281 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21282 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21283 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21284 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21285 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
21286 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21287 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21288 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21289 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21290 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21291 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21292 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21293 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21294 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21295 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21296 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21297 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21298 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21299 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21300 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21301 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21302 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21303 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21304 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21305 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21306 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21307 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
21308 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21309 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21310 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21311 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21312 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21313 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21314 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21315 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21316 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21317 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21318 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21319 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21320 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21321 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21322 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21323 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21324 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
21325 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
21326 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21327 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
21328 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
21329 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
21330 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21331 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21332 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21333 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21334 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21335 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21336 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21337 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21338 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21339 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21340 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21341 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21342 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21343 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21344 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
21345 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21346 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21347 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21348 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21349 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21350 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21351 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21352 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21353 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
21354 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21355 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21356 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21357 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21358 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
21361 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
21363 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
21364 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
21365 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
21366 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21367 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21368 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
21369 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21370 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21371 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21372 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21373 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21374 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21375 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21376 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21377 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21378 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21379 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21380 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21381 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21382 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21383 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
21384 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21385 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21386 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21387 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21388 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21389 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21390 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21391 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21392 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21393 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21394 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21395 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21396 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21397 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21398 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21399 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21400 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21401 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21402 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21403 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21404 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21405 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21406 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21407 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21408 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21409 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21410 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21411 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21412 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21413 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21414 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21415 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21416 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21417 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21418 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21419 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
21422 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
21424 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21425 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21426 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21427 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21428 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
21429 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
21430 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
21431 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
21432 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
21433 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
21434 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
21435 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
21436 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
21437 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
21438 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
21439 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
21440 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
21441 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
21442 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
21443 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
21444 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
21445 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
21446 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
21447 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
21448 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
21449 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
21450 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
21451 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
21452 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
21453 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
21454 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
21455 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
21456 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
21457 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
21458 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
21459 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
21460 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
21461 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
21462 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
21463 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
21464 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
21465 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
21466 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
21467 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
21468 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
21469 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
21470 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
21471 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
21472 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
21473 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
21474 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
21475 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
21476 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
21477 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
21478 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21479 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21480 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21481 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21482 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
21483 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
21484 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
21485 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
21486 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
21487 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
21488 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21489 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21490 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21491 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21492 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21493 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
21494 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21495 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
21496 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21497 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
21498 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21499 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
21501 /* ARMv8-M instructions. */
21503 #define ARM_VARIANT NULL
21504 #undef THUMB_VARIANT
21505 #define THUMB_VARIANT & arm_ext_v8m
21506 ToU("sg", e97fe97f
, 0, (), noargs
),
21507 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
21508 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
21509 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
21510 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
21511 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
21512 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
21514 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
21515 instructions behave as nop if no VFP is present. */
21516 #undef THUMB_VARIANT
21517 #define THUMB_VARIANT & arm_ext_v8m_main
21518 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
21519 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
21522 #undef THUMB_VARIANT
21548 /* MD interface: bits in the object file. */
21550 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
21551 for use in the a.out file, and stores them in the array pointed to by buf.
21552 This knows about the endian-ness of the target machine and does
21553 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
21554 2 (short) and 4 (long) Floating numbers are put out as a series of
21555 LITTLENUMS (shorts, here at least). */
21558 md_number_to_chars (char * buf
, valueT val
, int n
)
21560 if (target_big_endian
)
21561 number_to_chars_bigendian (buf
, val
, n
);
21563 number_to_chars_littleendian (buf
, val
, n
);
21567 md_chars_to_number (char * buf
, int n
)
21570 unsigned char * where
= (unsigned char *) buf
;
21572 if (target_big_endian
)
21577 result
|= (*where
++ & 255);
21585 result
|= (where
[n
] & 255);
21592 /* MD interface: Sections. */
21594 /* Calculate the maximum variable size (i.e., excluding fr_fix)
21595 that an rs_machine_dependent frag may reach. */
21598 arm_frag_max_var (fragS
*fragp
)
21600 /* We only use rs_machine_dependent for variable-size Thumb instructions,
21601 which are either THUMB_SIZE (2) or INSN_SIZE (4).
21603 Note that we generate relaxable instructions even for cases that don't
21604 really need it, like an immediate that's a trivial constant. So we're
21605 overestimating the instruction size for some of those cases. Rather
21606 than putting more intelligence here, it would probably be better to
21607 avoid generating a relaxation frag in the first place when it can be
21608 determined up front that a short instruction will suffice. */
21610 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
21614 /* Estimate the size of a frag before relaxing. Assume everything fits in
21618 md_estimate_size_before_relax (fragS
* fragp
,
21619 segT segtype ATTRIBUTE_UNUSED
)
21625 /* Convert a machine dependent frag. */
21628 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
21630 unsigned long insn
;
21631 unsigned long old_op
;
21639 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21641 old_op
= bfd_get_16(abfd
, buf
);
21642 if (fragp
->fr_symbol
)
21644 exp
.X_op
= O_symbol
;
21645 exp
.X_add_symbol
= fragp
->fr_symbol
;
21649 exp
.X_op
= O_constant
;
21651 exp
.X_add_number
= fragp
->fr_offset
;
21652 opcode
= fragp
->fr_subtype
;
21655 case T_MNEM_ldr_pc
:
21656 case T_MNEM_ldr_pc2
:
21657 case T_MNEM_ldr_sp
:
21658 case T_MNEM_str_sp
:
21665 if (fragp
->fr_var
== 4)
21667 insn
= THUMB_OP32 (opcode
);
21668 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
21670 insn
|= (old_op
& 0x700) << 4;
21674 insn
|= (old_op
& 7) << 12;
21675 insn
|= (old_op
& 0x38) << 13;
21677 insn
|= 0x00000c00;
21678 put_thumb32_insn (buf
, insn
);
21679 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
21683 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
21685 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
21688 if (fragp
->fr_var
== 4)
21690 insn
= THUMB_OP32 (opcode
);
21691 insn
|= (old_op
& 0xf0) << 4;
21692 put_thumb32_insn (buf
, insn
);
21693 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
21697 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21698 exp
.X_add_number
-= 4;
21706 if (fragp
->fr_var
== 4)
21708 int r0off
= (opcode
== T_MNEM_mov
21709 || opcode
== T_MNEM_movs
) ? 0 : 8;
21710 insn
= THUMB_OP32 (opcode
);
21711 insn
= (insn
& 0xe1ffffff) | 0x10000000;
21712 insn
|= (old_op
& 0x700) << r0off
;
21713 put_thumb32_insn (buf
, insn
);
21714 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21718 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
21723 if (fragp
->fr_var
== 4)
21725 insn
= THUMB_OP32(opcode
);
21726 put_thumb32_insn (buf
, insn
);
21727 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
21730 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
21734 if (fragp
->fr_var
== 4)
21736 insn
= THUMB_OP32(opcode
);
21737 insn
|= (old_op
& 0xf00) << 14;
21738 put_thumb32_insn (buf
, insn
);
21739 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
21742 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
21745 case T_MNEM_add_sp
:
21746 case T_MNEM_add_pc
:
21747 case T_MNEM_inc_sp
:
21748 case T_MNEM_dec_sp
:
21749 if (fragp
->fr_var
== 4)
21751 /* ??? Choose between add and addw. */
21752 insn
= THUMB_OP32 (opcode
);
21753 insn
|= (old_op
& 0xf0) << 4;
21754 put_thumb32_insn (buf
, insn
);
21755 if (opcode
== T_MNEM_add_pc
)
21756 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
21758 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21761 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21769 if (fragp
->fr_var
== 4)
21771 insn
= THUMB_OP32 (opcode
);
21772 insn
|= (old_op
& 0xf0) << 4;
21773 insn
|= (old_op
& 0xf) << 16;
21774 put_thumb32_insn (buf
, insn
);
21775 if (insn
& (1 << 20))
21776 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
21778 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
21781 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
21787 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
21788 (enum bfd_reloc_code_real
) reloc_type
);
21789 fixp
->fx_file
= fragp
->fr_file
;
21790 fixp
->fx_line
= fragp
->fr_line
;
21791 fragp
->fr_fix
+= fragp
->fr_var
;
21793 /* Set whether we use thumb-2 ISA based on final relaxation results. */
21794 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
21795 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
21796 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
21799 /* Return the size of a relaxable immediate operand instruction.
21800 SHIFT and SIZE specify the form of the allowable immediate. */
21802 relax_immediate (fragS
*fragp
, int size
, int shift
)
21808 /* ??? Should be able to do better than this. */
21809 if (fragp
->fr_symbol
)
21812 low
= (1 << shift
) - 1;
21813 mask
= (1 << (shift
+ size
)) - (1 << shift
);
21814 offset
= fragp
->fr_offset
;
21815 /* Force misaligned offsets to 32-bit variant. */
21818 if (offset
& ~mask
)
21823 /* Get the address of a symbol during relaxation. */
21825 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
21831 sym
= fragp
->fr_symbol
;
21832 sym_frag
= symbol_get_frag (sym
);
21833 know (S_GET_SEGMENT (sym
) != absolute_section
21834 || sym_frag
== &zero_address_frag
);
21835 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
21837 /* If frag has yet to be reached on this pass, assume it will
21838 move by STRETCH just as we did. If this is not so, it will
21839 be because some frag between grows, and that will force
21843 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
21847 /* Adjust stretch for any alignment frag. Note that if have
21848 been expanding the earlier code, the symbol may be
21849 defined in what appears to be an earlier frag. FIXME:
21850 This doesn't handle the fr_subtype field, which specifies
21851 a maximum number of bytes to skip when doing an
21853 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
21855 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
21858 stretch
= - ((- stretch
)
21859 & ~ ((1 << (int) f
->fr_offset
) - 1));
21861 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
21873 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
21876 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
21881 /* Assume worst case for symbols not known to be in the same section. */
21882 if (fragp
->fr_symbol
== NULL
21883 || !S_IS_DEFINED (fragp
->fr_symbol
)
21884 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21885 || S_IS_WEAK (fragp
->fr_symbol
))
21888 val
= relaxed_symbol_addr (fragp
, stretch
);
21889 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
21890 addr
= (addr
+ 4) & ~3;
21891 /* Force misaligned targets to 32-bit variant. */
21895 if (val
< 0 || val
> 1020)
21900 /* Return the size of a relaxable add/sub immediate instruction. */
21902 relax_addsub (fragS
*fragp
, asection
*sec
)
21907 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
21908 op
= bfd_get_16(sec
->owner
, buf
);
21909 if ((op
& 0xf) == ((op
>> 4) & 0xf))
21910 return relax_immediate (fragp
, 8, 0);
21912 return relax_immediate (fragp
, 3, 0);
21915 /* Return TRUE iff the definition of symbol S could be pre-empted
21916 (overridden) at link or load time. */
21918 symbol_preemptible (symbolS
*s
)
21920 /* Weak symbols can always be pre-empted. */
21924 /* Non-global symbols cannot be pre-empted. */
21925 if (! S_IS_EXTERNAL (s
))
21929 /* In ELF, a global symbol can be marked protected, or private. In that
21930 case it can't be pre-empted (other definitions in the same link unit
21931 would violate the ODR). */
21932 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
21936 /* Other global symbols might be pre-empted. */
21940 /* Return the size of a relaxable branch instruction. BITS is the
21941 size of the offset field in the narrow instruction. */
21944 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
21950 /* Assume worst case for symbols not known to be in the same section. */
21951 if (!S_IS_DEFINED (fragp
->fr_symbol
)
21952 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
21953 || S_IS_WEAK (fragp
->fr_symbol
))
21957 /* A branch to a function in ARM state will require interworking. */
21958 if (S_IS_DEFINED (fragp
->fr_symbol
)
21959 && ARM_IS_FUNC (fragp
->fr_symbol
))
21963 if (symbol_preemptible (fragp
->fr_symbol
))
21966 val
= relaxed_symbol_addr (fragp
, stretch
);
21967 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
21970 /* Offset is a signed value *2 */
21972 if (val
>= limit
|| val
< -limit
)
21978 /* Relax a machine dependent frag. This returns the amount by which
21979 the current size of the frag should change. */
21982 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
21987 oldsize
= fragp
->fr_var
;
21988 switch (fragp
->fr_subtype
)
21990 case T_MNEM_ldr_pc2
:
21991 newsize
= relax_adr (fragp
, sec
, stretch
);
21993 case T_MNEM_ldr_pc
:
21994 case T_MNEM_ldr_sp
:
21995 case T_MNEM_str_sp
:
21996 newsize
= relax_immediate (fragp
, 8, 2);
22000 newsize
= relax_immediate (fragp
, 5, 2);
22004 newsize
= relax_immediate (fragp
, 5, 1);
22008 newsize
= relax_immediate (fragp
, 5, 0);
22011 newsize
= relax_adr (fragp
, sec
, stretch
);
22017 newsize
= relax_immediate (fragp
, 8, 0);
22020 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
22023 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
22025 case T_MNEM_add_sp
:
22026 case T_MNEM_add_pc
:
22027 newsize
= relax_immediate (fragp
, 8, 2);
22029 case T_MNEM_inc_sp
:
22030 case T_MNEM_dec_sp
:
22031 newsize
= relax_immediate (fragp
, 7, 2);
22037 newsize
= relax_addsub (fragp
, sec
);
22043 fragp
->fr_var
= newsize
;
22044 /* Freeze wide instructions that are at or before the same location as
22045 in the previous pass. This avoids infinite loops.
22046 Don't freeze them unconditionally because targets may be artificially
22047 misaligned by the expansion of preceding frags. */
22048 if (stretch
<= 0 && newsize
> 2)
22050 md_convert_frag (sec
->owner
, sec
, fragp
);
22054 return newsize
- oldsize
;
22057 /* Round up a section size to the appropriate boundary. */
22060 md_section_align (segT segment ATTRIBUTE_UNUSED
,
22063 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
22064 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
22066 /* For a.out, force the section size to be aligned. If we don't do
22067 this, BFD will align it for us, but it will not write out the
22068 final bytes of the section. This may be a bug in BFD, but it is
22069 easier to fix it here since that is how the other a.out targets
22073 align
= bfd_get_section_alignment (stdoutput
, segment
);
22074 size
= ((size
+ (1 << align
) - 1) & (-((valueT
) 1 << align
)));
22081 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
22082 of an rs_align_code fragment. */
22085 arm_handle_align (fragS
* fragP
)
22087 static unsigned char const arm_noop
[2][2][4] =
22090 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
22091 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
22094 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
22095 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
22098 static unsigned char const thumb_noop
[2][2][2] =
22101 {0xc0, 0x46}, /* LE */
22102 {0x46, 0xc0}, /* BE */
22105 {0x00, 0xbf}, /* LE */
22106 {0xbf, 0x00} /* BE */
22109 static unsigned char const wide_thumb_noop
[2][4] =
22110 { /* Wide Thumb-2 */
22111 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
22112 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
22115 unsigned bytes
, fix
, noop_size
;
22117 const unsigned char * noop
;
22118 const unsigned char *narrow_noop
= NULL
;
22123 if (fragP
->fr_type
!= rs_align_code
)
22126 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
22127 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
22130 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22131 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
22133 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
22135 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
22137 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22138 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
22140 narrow_noop
= thumb_noop
[1][target_big_endian
];
22141 noop
= wide_thumb_noop
[target_big_endian
];
22144 noop
= thumb_noop
[0][target_big_endian
];
22152 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
22153 ? selected_cpu
: arm_arch_none
,
22155 [target_big_endian
];
22162 fragP
->fr_var
= noop_size
;
22164 if (bytes
& (noop_size
- 1))
22166 fix
= bytes
& (noop_size
- 1);
22168 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
22170 memset (p
, 0, fix
);
22177 if (bytes
& noop_size
)
22179 /* Insert a narrow noop. */
22180 memcpy (p
, narrow_noop
, noop_size
);
22182 bytes
-= noop_size
;
22186 /* Use wide noops for the remainder */
22190 while (bytes
>= noop_size
)
22192 memcpy (p
, noop
, noop_size
);
22194 bytes
-= noop_size
;
22198 fragP
->fr_fix
+= fix
;
22201 /* Called from md_do_align. Used to create an alignment
22202 frag in a code section. */
22205 arm_frag_align_code (int n
, int max
)
22209 /* We assume that there will never be a requirement
22210 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
22211 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
22216 _("alignments greater than %d bytes not supported in .text sections."),
22217 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
22218 as_fatal ("%s", err_msg
);
22221 p
= frag_var (rs_align_code
,
22222 MAX_MEM_FOR_RS_ALIGN_CODE
,
22224 (relax_substateT
) max
,
22231 /* Perform target specific initialisation of a frag.
22232 Note - despite the name this initialisation is not done when the frag
22233 is created, but only when its type is assigned. A frag can be created
22234 and used a long time before its type is set, so beware of assuming that
22235 this initialisation is performed first. */
22239 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
22241 /* Record whether this frag is in an ARM or a THUMB area. */
22242 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22245 #else /* OBJ_ELF is defined. */
22247 arm_init_frag (fragS
* fragP
, int max_chars
)
22249 bfd_boolean frag_thumb_mode
;
22251 /* If the current ARM vs THUMB mode has not already
22252 been recorded into this frag then do so now. */
22253 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
22254 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
22256 /* PR 21809: Do not set a mapping state for debug sections
22257 - it just confuses other tools. */
22258 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
22261 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
22263 /* Record a mapping symbol for alignment frags. We will delete this
22264 later if the alignment ends up empty. */
22265 switch (fragP
->fr_type
)
22268 case rs_align_test
:
22270 mapping_state_2 (MAP_DATA
, max_chars
);
22272 case rs_align_code
:
22273 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
22280 /* When we change sections we need to issue a new mapping symbol. */
22283 arm_elf_change_section (void)
22285 /* Link an unlinked unwind index table section to the .text section. */
22286 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
22287 && elf_linked_to_section (now_seg
) == NULL
)
22288 elf_linked_to_section (now_seg
) = text_section
;
22292 arm_elf_section_type (const char * str
, size_t len
)
22294 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
22295 return SHT_ARM_EXIDX
;
22300 /* Code to deal with unwinding tables. */
22302 static void add_unwind_adjustsp (offsetT
);
22304 /* Generate any deferred unwind frame offset. */
22307 flush_pending_unwind (void)
22311 offset
= unwind
.pending_offset
;
22312 unwind
.pending_offset
= 0;
22314 add_unwind_adjustsp (offset
);
22317 /* Add an opcode to this list for this function. Two-byte opcodes should
22318 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
22322 add_unwind_opcode (valueT op
, int length
)
22324 /* Add any deferred stack adjustment. */
22325 if (unwind
.pending_offset
)
22326 flush_pending_unwind ();
22328 unwind
.sp_restored
= 0;
22330 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
22332 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
22333 if (unwind
.opcodes
)
22334 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
22335 unwind
.opcode_alloc
);
22337 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
22342 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
22344 unwind
.opcode_count
++;
22348 /* Add unwind opcodes to adjust the stack pointer. */
22351 add_unwind_adjustsp (offsetT offset
)
22355 if (offset
> 0x200)
22357 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
22362 /* Long form: 0xb2, uleb128. */
22363 /* This might not fit in a word so add the individual bytes,
22364 remembering the list is built in reverse order. */
22365 o
= (valueT
) ((offset
- 0x204) >> 2);
22367 add_unwind_opcode (0, 1);
22369 /* Calculate the uleb128 encoding of the offset. */
22373 bytes
[n
] = o
& 0x7f;
22379 /* Add the insn. */
22381 add_unwind_opcode (bytes
[n
- 1], 1);
22382 add_unwind_opcode (0xb2, 1);
22384 else if (offset
> 0x100)
22386 /* Two short opcodes. */
22387 add_unwind_opcode (0x3f, 1);
22388 op
= (offset
- 0x104) >> 2;
22389 add_unwind_opcode (op
, 1);
22391 else if (offset
> 0)
22393 /* Short opcode. */
22394 op
= (offset
- 4) >> 2;
22395 add_unwind_opcode (op
, 1);
22397 else if (offset
< 0)
22400 while (offset
> 0x100)
22402 add_unwind_opcode (0x7f, 1);
22405 op
= ((offset
- 4) >> 2) | 0x40;
22406 add_unwind_opcode (op
, 1);
22410 /* Finish the list of unwind opcodes for this function. */
22413 finish_unwind_opcodes (void)
22417 if (unwind
.fp_used
)
22419 /* Adjust sp as necessary. */
22420 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
22421 flush_pending_unwind ();
22423 /* After restoring sp from the frame pointer. */
22424 op
= 0x90 | unwind
.fp_reg
;
22425 add_unwind_opcode (op
, 1);
22428 flush_pending_unwind ();
22432 /* Start an exception table entry. If idx is nonzero this is an index table
22436 start_unwind_section (const segT text_seg
, int idx
)
22438 const char * text_name
;
22439 const char * prefix
;
22440 const char * prefix_once
;
22441 const char * group_name
;
22449 prefix
= ELF_STRING_ARM_unwind
;
22450 prefix_once
= ELF_STRING_ARM_unwind_once
;
22451 type
= SHT_ARM_EXIDX
;
22455 prefix
= ELF_STRING_ARM_unwind_info
;
22456 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
22457 type
= SHT_PROGBITS
;
22460 text_name
= segment_name (text_seg
);
22461 if (streq (text_name
, ".text"))
22464 if (strncmp (text_name
, ".gnu.linkonce.t.",
22465 strlen (".gnu.linkonce.t.")) == 0)
22467 prefix
= prefix_once
;
22468 text_name
+= strlen (".gnu.linkonce.t.");
22471 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
22477 /* Handle COMDAT group. */
22478 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
22480 group_name
= elf_group_name (text_seg
);
22481 if (group_name
== NULL
)
22483 as_bad (_("Group section `%s' has no group signature"),
22484 segment_name (text_seg
));
22485 ignore_rest_of_line ();
22488 flags
|= SHF_GROUP
;
22492 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
22495 /* Set the section link for index tables. */
22497 elf_linked_to_section (now_seg
) = text_seg
;
22501 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
22502 personality routine data. Returns zero, or the index table value for
22503 an inline entry. */
22506 create_unwind_entry (int have_data
)
22511 /* The current word of data. */
22513 /* The number of bytes left in this word. */
22516 finish_unwind_opcodes ();
22518 /* Remember the current text section. */
22519 unwind
.saved_seg
= now_seg
;
22520 unwind
.saved_subseg
= now_subseg
;
22522 start_unwind_section (now_seg
, 0);
22524 if (unwind
.personality_routine
== NULL
)
22526 if (unwind
.personality_index
== -2)
22529 as_bad (_("handlerdata in cantunwind frame"));
22530 return 1; /* EXIDX_CANTUNWIND. */
22533 /* Use a default personality routine if none is specified. */
22534 if (unwind
.personality_index
== -1)
22536 if (unwind
.opcode_count
> 3)
22537 unwind
.personality_index
= 1;
22539 unwind
.personality_index
= 0;
22542 /* Space for the personality routine entry. */
22543 if (unwind
.personality_index
== 0)
22545 if (unwind
.opcode_count
> 3)
22546 as_bad (_("too many unwind opcodes for personality routine 0"));
22550 /* All the data is inline in the index table. */
22553 while (unwind
.opcode_count
> 0)
22555 unwind
.opcode_count
--;
22556 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22560 /* Pad with "finish" opcodes. */
22562 data
= (data
<< 8) | 0xb0;
22569 /* We get two opcodes "free" in the first word. */
22570 size
= unwind
.opcode_count
- 2;
22574 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
22575 if (unwind
.personality_index
!= -1)
22577 as_bad (_("attempt to recreate an unwind entry"));
22581 /* An extra byte is required for the opcode count. */
22582 size
= unwind
.opcode_count
+ 1;
22585 size
= (size
+ 3) >> 2;
22587 as_bad (_("too many unwind opcodes"));
22589 frag_align (2, 0, 0);
22590 record_alignment (now_seg
, 2);
22591 unwind
.table_entry
= expr_build_dot ();
22593 /* Allocate the table entry. */
22594 ptr
= frag_more ((size
<< 2) + 4);
22595 /* PR 13449: Zero the table entries in case some of them are not used. */
22596 memset (ptr
, 0, (size
<< 2) + 4);
22597 where
= frag_now_fix () - ((size
<< 2) + 4);
22599 switch (unwind
.personality_index
)
22602 /* ??? Should this be a PLT generating relocation? */
22603 /* Custom personality routine. */
22604 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
22605 BFD_RELOC_ARM_PREL31
);
22610 /* Set the first byte to the number of additional words. */
22611 data
= size
> 0 ? size
- 1 : 0;
22615 /* ABI defined personality routines. */
22617 /* Three opcodes bytes are packed into the first word. */
22624 /* The size and first two opcode bytes go in the first word. */
22625 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
22630 /* Should never happen. */
22634 /* Pack the opcodes into words (MSB first), reversing the list at the same
22636 while (unwind
.opcode_count
> 0)
22640 md_number_to_chars (ptr
, data
, 4);
22645 unwind
.opcode_count
--;
22647 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
22650 /* Finish off the last word. */
22653 /* Pad with "finish" opcodes. */
22655 data
= (data
<< 8) | 0xb0;
22657 md_number_to_chars (ptr
, data
, 4);
22662 /* Add an empty descriptor if there is no user-specified data. */
22663 ptr
= frag_more (4);
22664 md_number_to_chars (ptr
, 0, 4);
22671 /* Initialize the DWARF-2 unwind information for this procedure. */
22674 tc_arm_frame_initial_instructions (void)
22676 cfi_add_CFA_def_cfa (REG_SP
, 0);
22678 #endif /* OBJ_ELF */
22680 /* Convert REGNAME to a DWARF-2 register number. */
22683 tc_arm_regname_to_dw2regnum (char *regname
)
22685 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
22689 /* PR 16694: Allow VFP registers as well. */
22690 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
22694 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
22703 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
22707 exp
.X_op
= O_secrel
;
22708 exp
.X_add_symbol
= symbol
;
22709 exp
.X_add_number
= 0;
22710 emit_expr (&exp
, size
);
22714 /* MD interface: Symbol and relocation handling. */
22716 /* Return the address within the segment that a PC-relative fixup is
22717 relative to. For ARM, PC-relative fixups applied to instructions
22718 are generally relative to the location of the fixup plus 8 bytes.
22719 Thumb branches are offset by 4, and Thumb loads relative to PC
22720 require special handling. */
22723 md_pcrel_from_section (fixS
* fixP
, segT seg
)
22725 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22727 /* If this is pc-relative and we are going to emit a relocation
22728 then we just want to put out any pipeline compensation that the linker
22729 will need. Otherwise we want to use the calculated base.
22730 For WinCE we skip the bias for externals as well, since this
22731 is how the MS ARM-CE assembler behaves and we want to be compatible. */
22733 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
22734 || (arm_force_relocation (fixP
)
22736 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
22742 switch (fixP
->fx_r_type
)
22744 /* PC relative addressing on the Thumb is slightly odd as the
22745 bottom two bits of the PC are forced to zero for the
22746 calculation. This happens *after* application of the
22747 pipeline offset. However, Thumb adrl already adjusts for
22748 this, so we need not do it again. */
22749 case BFD_RELOC_ARM_THUMB_ADD
:
22752 case BFD_RELOC_ARM_THUMB_OFFSET
:
22753 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
22754 case BFD_RELOC_ARM_T32_ADD_PC12
:
22755 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
22756 return (base
+ 4) & ~3;
22758 /* Thumb branches are simply offset by +4. */
22759 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
22760 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
22761 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
22762 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
22763 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
22766 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
22768 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22769 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22770 && ARM_IS_FUNC (fixP
->fx_addsy
)
22771 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22772 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22775 /* BLX is like branches above, but forces the low two bits of PC to
22777 case BFD_RELOC_THUMB_PCREL_BLX
:
22779 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22780 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22781 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22782 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22783 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22784 return (base
+ 4) & ~3;
22786 /* ARM mode branches are offset by +8. However, the Windows CE
22787 loader expects the relocation not to take this into account. */
22788 case BFD_RELOC_ARM_PCREL_BLX
:
22790 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22791 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22792 && ARM_IS_FUNC (fixP
->fx_addsy
)
22793 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22794 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22797 case BFD_RELOC_ARM_PCREL_CALL
:
22799 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22800 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
22801 && THUMB_IS_FUNC (fixP
->fx_addsy
)
22802 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
22803 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
22806 case BFD_RELOC_ARM_PCREL_BRANCH
:
22807 case BFD_RELOC_ARM_PCREL_JUMP
:
22808 case BFD_RELOC_ARM_PLT32
:
22810 /* When handling fixups immediately, because we have already
22811 discovered the value of a symbol, or the address of the frag involved
22812 we must account for the offset by +8, as the OS loader will never see the reloc.
22813 see fixup_segment() in write.c
22814 The S_IS_EXTERNAL test handles the case of global symbols.
22815 Those need the calculated base, not just the pipe compensation the linker will need. */
22817 && fixP
->fx_addsy
!= NULL
22818 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
22819 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
22827 /* ARM mode loads relative to PC are also offset by +8. Unlike
22828 branches, the Windows CE loader *does* expect the relocation
22829 to take this into account. */
22830 case BFD_RELOC_ARM_OFFSET_IMM
:
22831 case BFD_RELOC_ARM_OFFSET_IMM8
:
22832 case BFD_RELOC_ARM_HWLITERAL
:
22833 case BFD_RELOC_ARM_LITERAL
:
22834 case BFD_RELOC_ARM_CP_OFF_IMM
:
22838 /* Other PC-relative relocations are un-offset. */
22844 static bfd_boolean flag_warn_syms
= TRUE
;
22847 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
22849 /* PR 18347 - Warn if the user attempts to create a symbol with the same
22850 name as an ARM instruction. Whilst strictly speaking it is allowed, it
22851 does mean that the resulting code might be very confusing to the reader.
22852 Also this warning can be triggered if the user omits an operand before
22853 an immediate address, eg:
22857 GAS treats this as an assignment of the value of the symbol foo to a
22858 symbol LDR, and so (without this code) it will not issue any kind of
22859 warning or error message.
22861 Note - ARM instructions are case-insensitive but the strings in the hash
22862 table are all stored in lower case, so we must first ensure that name is
22864 if (flag_warn_syms
&& arm_ops_hsh
)
22866 char * nbuf
= strdup (name
);
22869 for (p
= nbuf
; *p
; p
++)
22871 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
22873 static struct hash_control
* already_warned
= NULL
;
22875 if (already_warned
== NULL
)
22876 already_warned
= hash_new ();
22877 /* Only warn about the symbol once. To keep the code
22878 simple we let hash_insert do the lookup for us. */
22879 if (hash_insert (already_warned
, name
, NULL
) == NULL
)
22880 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
22889 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
22890 Otherwise we have no need to default values of symbols. */
22893 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
22896 if (name
[0] == '_' && name
[1] == 'G'
22897 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
22901 if (symbol_find (name
))
22902 as_bad (_("GOT already in the symbol table"));
22904 GOT_symbol
= symbol_new (name
, undefined_section
,
22905 (valueT
) 0, & zero_address_frag
);
22915 /* Subroutine of md_apply_fix. Check to see if an immediate can be
22916 computed as two separate immediate values, added together. We
22917 already know that this value cannot be computed by just one ARM
22920 static unsigned int
22921 validate_immediate_twopart (unsigned int val
,
22922 unsigned int * highpart
)
22927 for (i
= 0; i
< 32; i
+= 2)
22928 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
22934 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
22936 else if (a
& 0xff0000)
22938 if (a
& 0xff000000)
22940 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
22944 gas_assert (a
& 0xff000000);
22945 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
22948 return (a
& 0xff) | (i
<< 7);
22955 validate_offset_imm (unsigned int val
, int hwse
)
22957 if ((hwse
&& val
> 255) || val
> 4095)
22962 /* Subroutine of md_apply_fix. Do those data_ops which can take a
22963 negative immediate constant by altering the instruction. A bit of
22968 by inverting the second operand, and
22971 by negating the second operand. */
22974 negate_data_op (unsigned long * instruction
,
22975 unsigned long value
)
22978 unsigned long negated
, inverted
;
22980 negated
= encode_arm_immediate (-value
);
22981 inverted
= encode_arm_immediate (~value
);
22983 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
22986 /* First negates. */
22987 case OPCODE_SUB
: /* ADD <-> SUB */
22988 new_inst
= OPCODE_ADD
;
22993 new_inst
= OPCODE_SUB
;
22997 case OPCODE_CMP
: /* CMP <-> CMN */
22998 new_inst
= OPCODE_CMN
;
23003 new_inst
= OPCODE_CMP
;
23007 /* Now Inverted ops. */
23008 case OPCODE_MOV
: /* MOV <-> MVN */
23009 new_inst
= OPCODE_MVN
;
23014 new_inst
= OPCODE_MOV
;
23018 case OPCODE_AND
: /* AND <-> BIC */
23019 new_inst
= OPCODE_BIC
;
23024 new_inst
= OPCODE_AND
;
23028 case OPCODE_ADC
: /* ADC <-> SBC */
23029 new_inst
= OPCODE_SBC
;
23034 new_inst
= OPCODE_ADC
;
23038 /* We cannot do anything. */
23043 if (value
== (unsigned) FAIL
)
23046 *instruction
&= OPCODE_MASK
;
23047 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
23051 /* Like negate_data_op, but for Thumb-2. */
23053 static unsigned int
23054 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
23058 unsigned int negated
, inverted
;
23060 negated
= encode_thumb32_immediate (-value
);
23061 inverted
= encode_thumb32_immediate (~value
);
23063 rd
= (*instruction
>> 8) & 0xf;
23064 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
23067 /* ADD <-> SUB. Includes CMP <-> CMN. */
23068 case T2_OPCODE_SUB
:
23069 new_inst
= T2_OPCODE_ADD
;
23073 case T2_OPCODE_ADD
:
23074 new_inst
= T2_OPCODE_SUB
;
23078 /* ORR <-> ORN. Includes MOV <-> MVN. */
23079 case T2_OPCODE_ORR
:
23080 new_inst
= T2_OPCODE_ORN
;
23084 case T2_OPCODE_ORN
:
23085 new_inst
= T2_OPCODE_ORR
;
23089 /* AND <-> BIC. TST has no inverted equivalent. */
23090 case T2_OPCODE_AND
:
23091 new_inst
= T2_OPCODE_BIC
;
23098 case T2_OPCODE_BIC
:
23099 new_inst
= T2_OPCODE_AND
;
23104 case T2_OPCODE_ADC
:
23105 new_inst
= T2_OPCODE_SBC
;
23109 case T2_OPCODE_SBC
:
23110 new_inst
= T2_OPCODE_ADC
;
23114 /* We cannot do anything. */
23119 if (value
== (unsigned int)FAIL
)
23122 *instruction
&= T2_OPCODE_MASK
;
23123 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
23127 /* Read a 32-bit thumb instruction from buf. */
23129 static unsigned long
23130 get_thumb32_insn (char * buf
)
23132 unsigned long insn
;
23133 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
23134 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23139 /* We usually want to set the low bit on the address of thumb function
23140 symbols. In particular .word foo - . should have the low bit set.
23141 Generic code tries to fold the difference of two symbols to
23142 a constant. Prevent this and force a relocation when the first symbols
23143 is a thumb function. */
23146 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
23148 if (op
== O_subtract
23149 && l
->X_op
== O_symbol
23150 && r
->X_op
== O_symbol
23151 && THUMB_IS_FUNC (l
->X_add_symbol
))
23153 l
->X_op
= O_subtract
;
23154 l
->X_op_symbol
= r
->X_add_symbol
;
23155 l
->X_add_number
-= r
->X_add_number
;
23159 /* Process as normal. */
23163 /* Encode Thumb2 unconditional branches and calls. The encoding
23164 for the 2 are identical for the immediate values. */
23167 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
23169 #define T2I1I2MASK ((1 << 13) | (1 << 11))
23172 addressT S
, I1
, I2
, lo
, hi
;
23174 S
= (value
>> 24) & 0x01;
23175 I1
= (value
>> 23) & 0x01;
23176 I2
= (value
>> 22) & 0x01;
23177 hi
= (value
>> 12) & 0x3ff;
23178 lo
= (value
>> 1) & 0x7ff;
23179 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23180 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23181 newval
|= (S
<< 10) | hi
;
23182 newval2
&= ~T2I1I2MASK
;
23183 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
23184 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23185 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23189 md_apply_fix (fixS
* fixP
,
23193 offsetT value
= * valP
;
23195 unsigned int newimm
;
23196 unsigned long temp
;
23198 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
23200 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
23202 /* Note whether this will delete the relocation. */
23204 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
23207 /* On a 64-bit host, silently truncate 'value' to 32 bits for
23208 consistency with the behaviour on 32-bit hosts. Remember value
23210 value
&= 0xffffffff;
23211 value
^= 0x80000000;
23212 value
-= 0x80000000;
23215 fixP
->fx_addnumber
= value
;
23217 /* Same treatment for fixP->fx_offset. */
23218 fixP
->fx_offset
&= 0xffffffff;
23219 fixP
->fx_offset
^= 0x80000000;
23220 fixP
->fx_offset
-= 0x80000000;
23222 switch (fixP
->fx_r_type
)
23224 case BFD_RELOC_NONE
:
23225 /* This will need to go in the object file. */
23229 case BFD_RELOC_ARM_IMMEDIATE
:
23230 /* We claim that this fixup has been processed here,
23231 even if in fact we generate an error because we do
23232 not have a reloc for it, so tc_gen_reloc will reject it. */
23235 if (fixP
->fx_addsy
)
23237 const char *msg
= 0;
23239 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23240 msg
= _("undefined symbol %s used as an immediate value");
23241 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23242 msg
= _("symbol %s is in a different section");
23243 else if (S_IS_WEAK (fixP
->fx_addsy
))
23244 msg
= _("symbol %s is weak and may be overridden later");
23248 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23249 msg
, S_GET_NAME (fixP
->fx_addsy
));
23254 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23256 /* If the offset is negative, we should use encoding A2 for ADR. */
23257 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
23258 newimm
= negate_data_op (&temp
, value
);
23261 newimm
= encode_arm_immediate (value
);
23263 /* If the instruction will fail, see if we can fix things up by
23264 changing the opcode. */
23265 if (newimm
== (unsigned int) FAIL
)
23266 newimm
= negate_data_op (&temp
, value
);
23267 /* MOV accepts both ARM modified immediate (A1 encoding) and
23268 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
23269 When disassembling, MOV is preferred when there is no encoding
23271 if (newimm
== (unsigned int) FAIL
23272 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
23273 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
23274 && !((temp
>> SBIT_SHIFT
) & 0x1)
23275 && value
>= 0 && value
<= 0xffff)
23277 /* Clear bits[23:20] to change encoding from A1 to A2. */
23278 temp
&= 0xff0fffff;
23279 /* Encoding high 4bits imm. Code below will encode the remaining
23281 temp
|= (value
& 0x0000f000) << 4;
23282 newimm
= value
& 0x00000fff;
23286 if (newimm
== (unsigned int) FAIL
)
23288 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23289 _("invalid constant (%lx) after fixup"),
23290 (unsigned long) value
);
23294 newimm
|= (temp
& 0xfffff000);
23295 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23298 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
23300 unsigned int highpart
= 0;
23301 unsigned int newinsn
= 0xe1a00000; /* nop. */
23303 if (fixP
->fx_addsy
)
23305 const char *msg
= 0;
23307 if (! S_IS_DEFINED (fixP
->fx_addsy
))
23308 msg
= _("undefined symbol %s used as an immediate value");
23309 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
23310 msg
= _("symbol %s is in a different section");
23311 else if (S_IS_WEAK (fixP
->fx_addsy
))
23312 msg
= _("symbol %s is weak and may be overridden later");
23316 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23317 msg
, S_GET_NAME (fixP
->fx_addsy
));
23322 newimm
= encode_arm_immediate (value
);
23323 temp
= md_chars_to_number (buf
, INSN_SIZE
);
23325 /* If the instruction will fail, see if we can fix things up by
23326 changing the opcode. */
23327 if (newimm
== (unsigned int) FAIL
23328 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
23330 /* No ? OK - try using two ADD instructions to generate
23332 newimm
= validate_immediate_twopart (value
, & highpart
);
23334 /* Yes - then make sure that the second instruction is
23336 if (newimm
!= (unsigned int) FAIL
)
23338 /* Still No ? Try using a negated value. */
23339 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
23340 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
23341 /* Otherwise - give up. */
23344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23345 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
23350 /* Replace the first operand in the 2nd instruction (which
23351 is the PC) with the destination register. We have
23352 already added in the PC in the first instruction and we
23353 do not want to do it again. */
23354 newinsn
&= ~ 0xf0000;
23355 newinsn
|= ((newinsn
& 0x0f000) << 4);
23358 newimm
|= (temp
& 0xfffff000);
23359 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
23361 highpart
|= (newinsn
& 0xfffff000);
23362 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
23366 case BFD_RELOC_ARM_OFFSET_IMM
:
23367 if (!fixP
->fx_done
&& seg
->use_rela_p
)
23369 /* Fall through. */
23371 case BFD_RELOC_ARM_LITERAL
:
23377 if (validate_offset_imm (value
, 0) == FAIL
)
23379 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
23380 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23381 _("invalid literal constant: pool needs to be closer"));
23383 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23384 _("bad immediate value for offset (%ld)"),
23389 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23391 newval
&= 0xfffff000;
23394 newval
&= 0xff7ff000;
23395 newval
|= value
| (sign
? INDEX_UP
: 0);
23397 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23400 case BFD_RELOC_ARM_OFFSET_IMM8
:
23401 case BFD_RELOC_ARM_HWLITERAL
:
23407 if (validate_offset_imm (value
, 1) == FAIL
)
23409 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
23410 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23411 _("invalid literal constant: pool needs to be closer"));
23413 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23414 _("bad immediate value for 8-bit offset (%ld)"),
23419 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23421 newval
&= 0xfffff0f0;
23424 newval
&= 0xff7ff0f0;
23425 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
23427 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23430 case BFD_RELOC_ARM_T32_OFFSET_U8
:
23431 if (value
< 0 || value
> 1020 || value
% 4 != 0)
23432 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23433 _("bad immediate value for offset (%ld)"), (long) value
);
23436 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
23438 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
23441 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
23442 /* This is a complicated relocation used for all varieties of Thumb32
23443 load/store instruction with immediate offset:
23445 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
23446 *4, optional writeback(W)
23447 (doubleword load/store)
23449 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
23450 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
23451 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
23452 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
23453 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
23455 Uppercase letters indicate bits that are already encoded at
23456 this point. Lowercase letters are our problem. For the
23457 second block of instructions, the secondary opcode nybble
23458 (bits 8..11) is present, and bit 23 is zero, even if this is
23459 a PC-relative operation. */
23460 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23462 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
23464 if ((newval
& 0xf0000000) == 0xe0000000)
23466 /* Doubleword load/store: 8-bit offset, scaled by 4. */
23468 newval
|= (1 << 23);
23471 if (value
% 4 != 0)
23473 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23474 _("offset not a multiple of 4"));
23480 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23481 _("offset out of range"));
23486 else if ((newval
& 0x000f0000) == 0x000f0000)
23488 /* PC-relative, 12-bit offset. */
23490 newval
|= (1 << 23);
23495 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23496 _("offset out of range"));
23501 else if ((newval
& 0x00000100) == 0x00000100)
23503 /* Writeback: 8-bit, +/- offset. */
23505 newval
|= (1 << 9);
23510 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23511 _("offset out of range"));
23516 else if ((newval
& 0x00000f00) == 0x00000e00)
23518 /* T-instruction: positive 8-bit offset. */
23519 if (value
< 0 || value
> 0xff)
23521 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23522 _("offset out of range"));
23530 /* Positive 12-bit or negative 8-bit offset. */
23534 newval
|= (1 << 23);
23544 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23545 _("offset out of range"));
23552 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
23553 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
23556 case BFD_RELOC_ARM_SHIFT_IMM
:
23557 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23558 if (((unsigned long) value
) > 32
23560 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
23562 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23563 _("shift expression is too large"));
23568 /* Shifts of zero must be done as lsl. */
23570 else if (value
== 32)
23572 newval
&= 0xfffff07f;
23573 newval
|= (value
& 0x1f) << 7;
23574 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23577 case BFD_RELOC_ARM_T32_IMMEDIATE
:
23578 case BFD_RELOC_ARM_T32_ADD_IMM
:
23579 case BFD_RELOC_ARM_T32_IMM12
:
23580 case BFD_RELOC_ARM_T32_ADD_PC12
:
23581 /* We claim that this fixup has been processed here,
23582 even if in fact we generate an error because we do
23583 not have a reloc for it, so tc_gen_reloc will reject it. */
23587 && ! S_IS_DEFINED (fixP
->fx_addsy
))
23589 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23590 _("undefined symbol %s used as an immediate value"),
23591 S_GET_NAME (fixP
->fx_addsy
));
23595 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23597 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
23600 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
23601 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
23602 Thumb2 modified immediate encoding (T2). */
23603 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
23604 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23606 newimm
= encode_thumb32_immediate (value
);
23607 if (newimm
== (unsigned int) FAIL
)
23608 newimm
= thumb32_negate_data_op (&newval
, value
);
23610 if (newimm
== (unsigned int) FAIL
)
23612 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
23614 /* Turn add/sum into addw/subw. */
23615 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
23616 newval
= (newval
& 0xfeffffff) | 0x02000000;
23617 /* No flat 12-bit imm encoding for addsw/subsw. */
23618 if ((newval
& 0x00100000) == 0)
23620 /* 12 bit immediate for addw/subw. */
23624 newval
^= 0x00a00000;
23627 newimm
= (unsigned int) FAIL
;
23634 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
23635 UINT16 (T3 encoding), MOVW only accepts UINT16. When
23636 disassembling, MOV is preferred when there is no encoding
23638 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
23639 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
23640 but with the Rn field [19:16] set to 1111. */
23641 && (((newval
>> 16) & 0xf) == 0xf)
23642 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
23643 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
23644 && value
>= 0 && value
<= 0xffff)
23646 /* Toggle bit[25] to change encoding from T2 to T3. */
23648 /* Clear bits[19:16]. */
23649 newval
&= 0xfff0ffff;
23650 /* Encoding high 4bits imm. Code below will encode the
23651 remaining low 12bits. */
23652 newval
|= (value
& 0x0000f000) << 4;
23653 newimm
= value
& 0x00000fff;
23658 if (newimm
== (unsigned int)FAIL
)
23660 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23661 _("invalid constant (%lx) after fixup"),
23662 (unsigned long) value
);
23666 newval
|= (newimm
& 0x800) << 15;
23667 newval
|= (newimm
& 0x700) << 4;
23668 newval
|= (newimm
& 0x0ff);
23670 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
23671 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
23674 case BFD_RELOC_ARM_SMC
:
23675 if (((unsigned long) value
) > 0xffff)
23676 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23677 _("invalid smc expression"));
23678 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23679 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23680 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23683 case BFD_RELOC_ARM_HVC
:
23684 if (((unsigned long) value
) > 0xffff)
23685 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23686 _("invalid hvc expression"));
23687 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23688 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
23689 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23692 case BFD_RELOC_ARM_SWI
:
23693 if (fixP
->tc_fix_data
!= 0)
23695 if (((unsigned long) value
) > 0xff)
23696 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23697 _("invalid swi expression"));
23698 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23700 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23704 if (((unsigned long) value
) > 0x00ffffff)
23705 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23706 _("invalid swi expression"));
23707 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23709 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23713 case BFD_RELOC_ARM_MULTI
:
23714 if (((unsigned long) value
) > 0xffff)
23715 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23716 _("invalid expression in load/store multiple"));
23717 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
23718 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23722 case BFD_RELOC_ARM_PCREL_CALL
:
23724 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23726 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23727 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23728 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23729 /* Flip the bl to blx. This is a simple flip
23730 bit here because we generate PCREL_CALL for
23731 unconditional bls. */
23733 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23734 newval
= newval
| 0x10000000;
23735 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23741 goto arm_branch_common
;
23743 case BFD_RELOC_ARM_PCREL_JUMP
:
23744 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23746 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23747 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23748 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23750 /* This would map to a bl<cond>, b<cond>,
23751 b<always> to a Thumb function. We
23752 need to force a relocation for this particular
23754 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23757 /* Fall through. */
23759 case BFD_RELOC_ARM_PLT32
:
23761 case BFD_RELOC_ARM_PCREL_BRANCH
:
23763 goto arm_branch_common
;
23765 case BFD_RELOC_ARM_PCREL_BLX
:
23768 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
23770 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23771 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23772 && ARM_IS_FUNC (fixP
->fx_addsy
))
23774 /* Flip the blx to a bl and warn. */
23775 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23776 newval
= 0xeb000000;
23777 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23778 _("blx to '%s' an ARM ISA state function changed to bl"),
23780 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23786 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
23787 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
23791 /* We are going to store value (shifted right by two) in the
23792 instruction, in a 24 bit, signed field. Bits 26 through 32 either
23793 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
23796 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23797 _("misaligned branch destination"));
23798 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
23799 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
23800 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23802 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23804 newval
= md_chars_to_number (buf
, INSN_SIZE
);
23805 newval
|= (value
>> 2) & 0x00ffffff;
23806 /* Set the H bit on BLX instructions. */
23810 newval
|= 0x01000000;
23812 newval
&= ~0x01000000;
23814 md_number_to_chars (buf
, newval
, INSN_SIZE
);
23818 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
23819 /* CBZ can only branch forward. */
23821 /* Attempts to use CBZ to branch to the next instruction
23822 (which, strictly speaking, are prohibited) will be turned into
23825 FIXME: It may be better to remove the instruction completely and
23826 perform relaxation. */
23829 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23830 newval
= 0xbf00; /* NOP encoding T1 */
23831 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23836 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23838 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23840 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23841 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
23842 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23847 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
23848 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
23849 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23851 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23853 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23854 newval
|= (value
& 0x1ff) >> 1;
23855 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23859 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
23860 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
23861 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23863 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23865 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23866 newval
|= (value
& 0xfff) >> 1;
23867 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23871 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
23873 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23874 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23875 && ARM_IS_FUNC (fixP
->fx_addsy
)
23876 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23878 /* Force a relocation for a branch 20 bits wide. */
23881 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
23882 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23883 _("conditional branch out of range"));
23885 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23888 addressT S
, J1
, J2
, lo
, hi
;
23890 S
= (value
& 0x00100000) >> 20;
23891 J2
= (value
& 0x00080000) >> 19;
23892 J1
= (value
& 0x00040000) >> 18;
23893 hi
= (value
& 0x0003f000) >> 12;
23894 lo
= (value
& 0x00000ffe) >> 1;
23896 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
23897 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23898 newval
|= (S
<< 10) | hi
;
23899 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
23900 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
23901 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
23905 case BFD_RELOC_THUMB_PCREL_BLX
:
23906 /* If there is a blx from a thumb state function to
23907 another thumb function flip this to a bl and warn
23911 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23912 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23913 && THUMB_IS_FUNC (fixP
->fx_addsy
))
23915 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
23916 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
23917 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
23919 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23920 newval
= newval
| 0x1000;
23921 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23922 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23927 goto thumb_bl_common
;
23929 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
23930 /* A bl from Thumb state ISA to an internal ARM state function
23931 is converted to a blx. */
23933 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
23934 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
23935 && ARM_IS_FUNC (fixP
->fx_addsy
)
23936 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
23938 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
23939 newval
= newval
& ~0x1000;
23940 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
23941 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
23947 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23948 /* For a BLX instruction, make sure that the relocation is rounded up
23949 to a word boundary. This follows the semantics of the instruction
23950 which specifies that bit 1 of the target address will come from bit
23951 1 of the base address. */
23952 value
= (value
+ 3) & ~ 3;
23955 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
23956 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
23957 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
23960 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
23962 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
23963 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23964 else if ((value
& ~0x1ffffff)
23965 && ((value
& ~0x1ffffff) != ~0x1ffffff))
23966 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
23967 _("Thumb2 branch out of range"));
23970 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23971 encode_thumb2_b_bl_offset (buf
, value
);
23975 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
23976 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
23977 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
23979 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23980 encode_thumb2_b_bl_offset (buf
, value
);
23985 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23990 if (fixP
->fx_done
|| !seg
->use_rela_p
)
23991 md_number_to_chars (buf
, value
, 2);
23995 case BFD_RELOC_ARM_TLS_CALL
:
23996 case BFD_RELOC_ARM_THM_TLS_CALL
:
23997 case BFD_RELOC_ARM_TLS_DESCSEQ
:
23998 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
23999 case BFD_RELOC_ARM_TLS_GOTDESC
:
24000 case BFD_RELOC_ARM_TLS_GD32
:
24001 case BFD_RELOC_ARM_TLS_LE32
:
24002 case BFD_RELOC_ARM_TLS_IE32
:
24003 case BFD_RELOC_ARM_TLS_LDM32
:
24004 case BFD_RELOC_ARM_TLS_LDO32
:
24005 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
24008 case BFD_RELOC_ARM_GOT32
:
24009 case BFD_RELOC_ARM_GOTOFF
:
24012 case BFD_RELOC_ARM_GOT_PREL
:
24013 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24014 md_number_to_chars (buf
, value
, 4);
24017 case BFD_RELOC_ARM_TARGET2
:
24018 /* TARGET2 is not partial-inplace, so we need to write the
24019 addend here for REL targets, because it won't be written out
24020 during reloc processing later. */
24021 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24022 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
24026 case BFD_RELOC_RVA
:
24028 case BFD_RELOC_ARM_TARGET1
:
24029 case BFD_RELOC_ARM_ROSEGREL32
:
24030 case BFD_RELOC_ARM_SBREL32
:
24031 case BFD_RELOC_32_PCREL
:
24033 case BFD_RELOC_32_SECREL
:
24035 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24037 /* For WinCE we only do this for pcrel fixups. */
24038 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
24040 md_number_to_chars (buf
, value
, 4);
24044 case BFD_RELOC_ARM_PREL31
:
24045 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24047 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
24048 if ((value
^ (value
>> 1)) & 0x40000000)
24050 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24051 _("rel31 relocation overflow"));
24053 newval
|= value
& 0x7fffffff;
24054 md_number_to_chars (buf
, newval
, 4);
24059 case BFD_RELOC_ARM_CP_OFF_IMM
:
24060 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
24061 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
24062 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24064 newval
= get_thumb32_insn (buf
);
24065 if ((newval
& 0x0f200f00) == 0x0d000900)
24067 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
24068 has permitted values that are multiples of 2, in the range 0
24070 if (value
< -510 || value
> 510 || (value
& 1))
24071 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24072 _("co-processor offset out of range"));
24074 else if (value
< -1023 || value
> 1023 || (value
& 3))
24075 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24076 _("co-processor offset out of range"));
24081 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24082 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24083 newval
= md_chars_to_number (buf
, INSN_SIZE
);
24085 newval
= get_thumb32_insn (buf
);
24087 newval
&= 0xffffff00;
24090 newval
&= 0xff7fff00;
24091 if ((newval
& 0x0f200f00) == 0x0d000900)
24093 /* This is a fp16 vstr/vldr.
24095 It requires the immediate offset in the instruction is shifted
24096 left by 1 to be a half-word offset.
24098 Here, left shift by 1 first, and later right shift by 2
24099 should get the right offset. */
24102 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
24104 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24105 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
24106 md_number_to_chars (buf
, newval
, INSN_SIZE
);
24108 put_thumb32_insn (buf
, newval
);
24111 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
24112 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
24113 if (value
< -255 || value
> 255)
24114 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24115 _("co-processor offset out of range"));
24117 goto cp_off_common
;
24119 case BFD_RELOC_ARM_THUMB_OFFSET
:
24120 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24121 /* Exactly what ranges, and where the offset is inserted depends
24122 on the type of instruction, we can establish this from the
24124 switch (newval
>> 12)
24126 case 4: /* PC load. */
24127 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
24128 forced to zero for these loads; md_pcrel_from has already
24129 compensated for this. */
24131 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24132 _("invalid offset, target not word aligned (0x%08lX)"),
24133 (((unsigned long) fixP
->fx_frag
->fr_address
24134 + (unsigned long) fixP
->fx_where
) & ~3)
24135 + (unsigned long) value
);
24137 if (value
& ~0x3fc)
24138 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24139 _("invalid offset, value too big (0x%08lX)"),
24142 newval
|= value
>> 2;
24145 case 9: /* SP load/store. */
24146 if (value
& ~0x3fc)
24147 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24148 _("invalid offset, value too big (0x%08lX)"),
24150 newval
|= value
>> 2;
24153 case 6: /* Word load/store. */
24155 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24156 _("invalid offset, value too big (0x%08lX)"),
24158 newval
|= value
<< 4; /* 6 - 2. */
24161 case 7: /* Byte load/store. */
24163 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24164 _("invalid offset, value too big (0x%08lX)"),
24166 newval
|= value
<< 6;
24169 case 8: /* Halfword load/store. */
24171 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24172 _("invalid offset, value too big (0x%08lX)"),
24174 newval
|= value
<< 5; /* 6 - 1. */
24178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24179 "Unable to process relocation for thumb opcode: %lx",
24180 (unsigned long) newval
);
24183 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24186 case BFD_RELOC_ARM_THUMB_ADD
:
24187 /* This is a complicated relocation, since we use it for all of
24188 the following immediate relocations:
24192 9bit ADD/SUB SP word-aligned
24193 10bit ADD PC/SP word-aligned
24195 The type of instruction being processed is encoded in the
24202 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24204 int rd
= (newval
>> 4) & 0xf;
24205 int rs
= newval
& 0xf;
24206 int subtract
= !!(newval
& 0x8000);
24208 /* Check for HI regs, only very restricted cases allowed:
24209 Adjusting SP, and using PC or SP to get an address. */
24210 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
24211 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
24212 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24213 _("invalid Hi register with immediate"));
24215 /* If value is negative, choose the opposite instruction. */
24219 subtract
= !subtract
;
24221 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24222 _("immediate value out of range"));
24227 if (value
& ~0x1fc)
24228 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24229 _("invalid immediate for stack address calculation"));
24230 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
24231 newval
|= value
>> 2;
24233 else if (rs
== REG_PC
|| rs
== REG_SP
)
24235 /* PR gas/18541. If the addition is for a defined symbol
24236 within range of an ADR instruction then accept it. */
24239 && fixP
->fx_addsy
!= NULL
)
24243 if (! S_IS_DEFINED (fixP
->fx_addsy
)
24244 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
24245 || S_IS_WEAK (fixP
->fx_addsy
))
24247 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24248 _("address calculation needs a strongly defined nearby symbol"));
24252 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
24254 /* Round up to the next 4-byte boundary. */
24259 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
24263 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24264 _("symbol too far away"));
24274 if (subtract
|| value
& ~0x3fc)
24275 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24276 _("invalid immediate for address calculation (value = 0x%08lX)"),
24277 (unsigned long) (subtract
? - value
: value
));
24278 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
24280 newval
|= value
>> 2;
24285 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24286 _("immediate value out of range"));
24287 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
24288 newval
|= (rd
<< 8) | value
;
24293 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24294 _("immediate value out of range"));
24295 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
24296 newval
|= rd
| (rs
<< 3) | (value
<< 6);
24299 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24302 case BFD_RELOC_ARM_THUMB_IMM
:
24303 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
24304 if (value
< 0 || value
> 255)
24305 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24306 _("invalid immediate: %ld is out of range"),
24309 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24312 case BFD_RELOC_ARM_THUMB_SHIFT
:
24313 /* 5bit shift value (0..32). LSL cannot take 32. */
24314 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
24315 temp
= newval
& 0xf800;
24316 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
24317 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24318 _("invalid shift value: %ld"), (long) value
);
24319 /* Shifts of zero must be encoded as LSL. */
24321 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
24322 /* Shifts of 32 are encoded as zero. */
24323 else if (value
== 32)
24325 newval
|= value
<< 6;
24326 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
24329 case BFD_RELOC_VTABLE_INHERIT
:
24330 case BFD_RELOC_VTABLE_ENTRY
:
24334 case BFD_RELOC_ARM_MOVW
:
24335 case BFD_RELOC_ARM_MOVT
:
24336 case BFD_RELOC_ARM_THUMB_MOVW
:
24337 case BFD_RELOC_ARM_THUMB_MOVT
:
24338 if (fixP
->fx_done
|| !seg
->use_rela_p
)
24340 /* REL format relocations are limited to a 16-bit addend. */
24341 if (!fixP
->fx_done
)
24343 if (value
< -0x8000 || value
> 0x7fff)
24344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24345 _("offset out of range"));
24347 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
24348 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24353 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
24354 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
24356 newval
= get_thumb32_insn (buf
);
24357 newval
&= 0xfbf08f00;
24358 newval
|= (value
& 0xf000) << 4;
24359 newval
|= (value
& 0x0800) << 15;
24360 newval
|= (value
& 0x0700) << 4;
24361 newval
|= (value
& 0x00ff);
24362 put_thumb32_insn (buf
, newval
);
24366 newval
= md_chars_to_number (buf
, 4);
24367 newval
&= 0xfff0f000;
24368 newval
|= value
& 0x0fff;
24369 newval
|= (value
& 0xf000) << 4;
24370 md_number_to_chars (buf
, newval
, 4);
24375 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24376 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24377 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24378 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24379 gas_assert (!fixP
->fx_done
);
24382 bfd_boolean is_mov
;
24383 bfd_vma encoded_addend
= value
;
24385 /* Check that addend can be encoded in instruction. */
24386 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
24387 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24388 _("the offset 0x%08lX is not representable"),
24389 (unsigned long) encoded_addend
);
24391 /* Extract the instruction. */
24392 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
24393 is_mov
= (insn
& 0xf800) == 0x2000;
24398 if (!seg
->use_rela_p
)
24399 insn
|= encoded_addend
;
24405 /* Extract the instruction. */
24406 /* Encoding is the following
24411 /* The following conditions must be true :
24416 rd
= (insn
>> 4) & 0xf;
24418 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
24419 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24420 _("Unable to process relocation for thumb opcode: %lx"),
24421 (unsigned long) insn
);
24423 /* Encode as ADD immediate8 thumb 1 code. */
24424 insn
= 0x3000 | (rd
<< 8);
24426 /* Place the encoded addend into the first 8 bits of the
24428 if (!seg
->use_rela_p
)
24429 insn
|= encoded_addend
;
24432 /* Update the instruction. */
24433 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
24437 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24438 case BFD_RELOC_ARM_ALU_PC_G0
:
24439 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24440 case BFD_RELOC_ARM_ALU_PC_G1
:
24441 case BFD_RELOC_ARM_ALU_PC_G2
:
24442 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24443 case BFD_RELOC_ARM_ALU_SB_G0
:
24444 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24445 case BFD_RELOC_ARM_ALU_SB_G1
:
24446 case BFD_RELOC_ARM_ALU_SB_G2
:
24447 gas_assert (!fixP
->fx_done
);
24448 if (!seg
->use_rela_p
)
24451 bfd_vma encoded_addend
;
24452 bfd_vma addend_abs
= abs (value
);
24454 /* Check that the absolute value of the addend can be
24455 expressed as an 8-bit constant plus a rotation. */
24456 encoded_addend
= encode_arm_immediate (addend_abs
);
24457 if (encoded_addend
== (unsigned int) FAIL
)
24458 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24459 _("the offset 0x%08lX is not representable"),
24460 (unsigned long) addend_abs
);
24462 /* Extract the instruction. */
24463 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24465 /* If the addend is positive, use an ADD instruction.
24466 Otherwise use a SUB. Take care not to destroy the S bit. */
24467 insn
&= 0xff1fffff;
24473 /* Place the encoded addend into the first 12 bits of the
24475 insn
&= 0xfffff000;
24476 insn
|= encoded_addend
;
24478 /* Update the instruction. */
24479 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24483 case BFD_RELOC_ARM_LDR_PC_G0
:
24484 case BFD_RELOC_ARM_LDR_PC_G1
:
24485 case BFD_RELOC_ARM_LDR_PC_G2
:
24486 case BFD_RELOC_ARM_LDR_SB_G0
:
24487 case BFD_RELOC_ARM_LDR_SB_G1
:
24488 case BFD_RELOC_ARM_LDR_SB_G2
:
24489 gas_assert (!fixP
->fx_done
);
24490 if (!seg
->use_rela_p
)
24493 bfd_vma addend_abs
= abs (value
);
24495 /* Check that the absolute value of the addend can be
24496 encoded in 12 bits. */
24497 if (addend_abs
>= 0x1000)
24498 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24499 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
24500 (unsigned long) addend_abs
);
24502 /* Extract the instruction. */
24503 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24505 /* If the addend is negative, clear bit 23 of the instruction.
24506 Otherwise set it. */
24508 insn
&= ~(1 << 23);
24512 /* Place the absolute value of the addend into the first 12 bits
24513 of the instruction. */
24514 insn
&= 0xfffff000;
24515 insn
|= addend_abs
;
24517 /* Update the instruction. */
24518 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24522 case BFD_RELOC_ARM_LDRS_PC_G0
:
24523 case BFD_RELOC_ARM_LDRS_PC_G1
:
24524 case BFD_RELOC_ARM_LDRS_PC_G2
:
24525 case BFD_RELOC_ARM_LDRS_SB_G0
:
24526 case BFD_RELOC_ARM_LDRS_SB_G1
:
24527 case BFD_RELOC_ARM_LDRS_SB_G2
:
24528 gas_assert (!fixP
->fx_done
);
24529 if (!seg
->use_rela_p
)
24532 bfd_vma addend_abs
= abs (value
);
24534 /* Check that the absolute value of the addend can be
24535 encoded in 8 bits. */
24536 if (addend_abs
>= 0x100)
24537 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24538 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
24539 (unsigned long) addend_abs
);
24541 /* Extract the instruction. */
24542 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24544 /* If the addend is negative, clear bit 23 of the instruction.
24545 Otherwise set it. */
24547 insn
&= ~(1 << 23);
24551 /* Place the first four bits of the absolute value of the addend
24552 into the first 4 bits of the instruction, and the remaining
24553 four into bits 8 .. 11. */
24554 insn
&= 0xfffff0f0;
24555 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
24557 /* Update the instruction. */
24558 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24562 case BFD_RELOC_ARM_LDC_PC_G0
:
24563 case BFD_RELOC_ARM_LDC_PC_G1
:
24564 case BFD_RELOC_ARM_LDC_PC_G2
:
24565 case BFD_RELOC_ARM_LDC_SB_G0
:
24566 case BFD_RELOC_ARM_LDC_SB_G1
:
24567 case BFD_RELOC_ARM_LDC_SB_G2
:
24568 gas_assert (!fixP
->fx_done
);
24569 if (!seg
->use_rela_p
)
24572 bfd_vma addend_abs
= abs (value
);
24574 /* Check that the absolute value of the addend is a multiple of
24575 four and, when divided by four, fits in 8 bits. */
24576 if (addend_abs
& 0x3)
24577 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24578 _("bad offset 0x%08lX (must be word-aligned)"),
24579 (unsigned long) addend_abs
);
24581 if ((addend_abs
>> 2) > 0xff)
24582 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24583 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
24584 (unsigned long) addend_abs
);
24586 /* Extract the instruction. */
24587 insn
= md_chars_to_number (buf
, INSN_SIZE
);
24589 /* If the addend is negative, clear bit 23 of the instruction.
24590 Otherwise set it. */
24592 insn
&= ~(1 << 23);
24596 /* Place the addend (divided by four) into the first eight
24597 bits of the instruction. */
24598 insn
&= 0xfffffff0;
24599 insn
|= addend_abs
>> 2;
24601 /* Update the instruction. */
24602 md_number_to_chars (buf
, insn
, INSN_SIZE
);
24606 case BFD_RELOC_ARM_V4BX
:
24607 /* This will need to go in the object file. */
24611 case BFD_RELOC_UNUSED
:
24613 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
24614 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
24618 /* Translate internal representation of relocation info to BFD target
24622 tc_gen_reloc (asection
*section
, fixS
*fixp
)
24625 bfd_reloc_code_real_type code
;
24627 reloc
= XNEW (arelent
);
24629 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
24630 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
24631 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
24633 if (fixp
->fx_pcrel
)
24635 if (section
->use_rela_p
)
24636 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
24638 fixp
->fx_offset
= reloc
->address
;
24640 reloc
->addend
= fixp
->fx_offset
;
24642 switch (fixp
->fx_r_type
)
24645 if (fixp
->fx_pcrel
)
24647 code
= BFD_RELOC_8_PCREL
;
24650 /* Fall through. */
24653 if (fixp
->fx_pcrel
)
24655 code
= BFD_RELOC_16_PCREL
;
24658 /* Fall through. */
24661 if (fixp
->fx_pcrel
)
24663 code
= BFD_RELOC_32_PCREL
;
24666 /* Fall through. */
24668 case BFD_RELOC_ARM_MOVW
:
24669 if (fixp
->fx_pcrel
)
24671 code
= BFD_RELOC_ARM_MOVW_PCREL
;
24674 /* Fall through. */
24676 case BFD_RELOC_ARM_MOVT
:
24677 if (fixp
->fx_pcrel
)
24679 code
= BFD_RELOC_ARM_MOVT_PCREL
;
24682 /* Fall through. */
24684 case BFD_RELOC_ARM_THUMB_MOVW
:
24685 if (fixp
->fx_pcrel
)
24687 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
24690 /* Fall through. */
24692 case BFD_RELOC_ARM_THUMB_MOVT
:
24693 if (fixp
->fx_pcrel
)
24695 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
24698 /* Fall through. */
24700 case BFD_RELOC_NONE
:
24701 case BFD_RELOC_ARM_PCREL_BRANCH
:
24702 case BFD_RELOC_ARM_PCREL_BLX
:
24703 case BFD_RELOC_RVA
:
24704 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
24705 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
24706 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
24707 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24708 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24709 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24710 case BFD_RELOC_VTABLE_ENTRY
:
24711 case BFD_RELOC_VTABLE_INHERIT
:
24713 case BFD_RELOC_32_SECREL
:
24715 code
= fixp
->fx_r_type
;
24718 case BFD_RELOC_THUMB_PCREL_BLX
:
24720 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
24721 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
24724 code
= BFD_RELOC_THUMB_PCREL_BLX
;
24727 case BFD_RELOC_ARM_LITERAL
:
24728 case BFD_RELOC_ARM_HWLITERAL
:
24729 /* If this is called then the a literal has
24730 been referenced across a section boundary. */
24731 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24732 _("literal referenced across section boundary"));
24736 case BFD_RELOC_ARM_TLS_CALL
:
24737 case BFD_RELOC_ARM_THM_TLS_CALL
:
24738 case BFD_RELOC_ARM_TLS_DESCSEQ
:
24739 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
24740 case BFD_RELOC_ARM_GOT32
:
24741 case BFD_RELOC_ARM_GOTOFF
:
24742 case BFD_RELOC_ARM_GOT_PREL
:
24743 case BFD_RELOC_ARM_PLT32
:
24744 case BFD_RELOC_ARM_TARGET1
:
24745 case BFD_RELOC_ARM_ROSEGREL32
:
24746 case BFD_RELOC_ARM_SBREL32
:
24747 case BFD_RELOC_ARM_PREL31
:
24748 case BFD_RELOC_ARM_TARGET2
:
24749 case BFD_RELOC_ARM_TLS_LDO32
:
24750 case BFD_RELOC_ARM_PCREL_CALL
:
24751 case BFD_RELOC_ARM_PCREL_JUMP
:
24752 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
24753 case BFD_RELOC_ARM_ALU_PC_G0
:
24754 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
24755 case BFD_RELOC_ARM_ALU_PC_G1
:
24756 case BFD_RELOC_ARM_ALU_PC_G2
:
24757 case BFD_RELOC_ARM_LDR_PC_G0
:
24758 case BFD_RELOC_ARM_LDR_PC_G1
:
24759 case BFD_RELOC_ARM_LDR_PC_G2
:
24760 case BFD_RELOC_ARM_LDRS_PC_G0
:
24761 case BFD_RELOC_ARM_LDRS_PC_G1
:
24762 case BFD_RELOC_ARM_LDRS_PC_G2
:
24763 case BFD_RELOC_ARM_LDC_PC_G0
:
24764 case BFD_RELOC_ARM_LDC_PC_G1
:
24765 case BFD_RELOC_ARM_LDC_PC_G2
:
24766 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
24767 case BFD_RELOC_ARM_ALU_SB_G0
:
24768 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
24769 case BFD_RELOC_ARM_ALU_SB_G1
:
24770 case BFD_RELOC_ARM_ALU_SB_G2
:
24771 case BFD_RELOC_ARM_LDR_SB_G0
:
24772 case BFD_RELOC_ARM_LDR_SB_G1
:
24773 case BFD_RELOC_ARM_LDR_SB_G2
:
24774 case BFD_RELOC_ARM_LDRS_SB_G0
:
24775 case BFD_RELOC_ARM_LDRS_SB_G1
:
24776 case BFD_RELOC_ARM_LDRS_SB_G2
:
24777 case BFD_RELOC_ARM_LDC_SB_G0
:
24778 case BFD_RELOC_ARM_LDC_SB_G1
:
24779 case BFD_RELOC_ARM_LDC_SB_G2
:
24780 case BFD_RELOC_ARM_V4BX
:
24781 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
24782 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
24783 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
24784 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
24785 code
= fixp
->fx_r_type
;
24788 case BFD_RELOC_ARM_TLS_GOTDESC
:
24789 case BFD_RELOC_ARM_TLS_GD32
:
24790 case BFD_RELOC_ARM_TLS_LE32
:
24791 case BFD_RELOC_ARM_TLS_IE32
:
24792 case BFD_RELOC_ARM_TLS_LDM32
:
24793 /* BFD will include the symbol's address in the addend.
24794 But we don't want that, so subtract it out again here. */
24795 if (!S_IS_COMMON (fixp
->fx_addsy
))
24796 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
24797 code
= fixp
->fx_r_type
;
24801 case BFD_RELOC_ARM_IMMEDIATE
:
24802 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24803 _("internal relocation (type: IMMEDIATE) not fixed up"));
24806 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
24807 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24808 _("ADRL used for a symbol not defined in the same file"));
24811 case BFD_RELOC_ARM_OFFSET_IMM
:
24812 if (section
->use_rela_p
)
24814 code
= fixp
->fx_r_type
;
24818 if (fixp
->fx_addsy
!= NULL
24819 && !S_IS_DEFINED (fixp
->fx_addsy
)
24820 && S_IS_LOCAL (fixp
->fx_addsy
))
24822 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24823 _("undefined local label `%s'"),
24824 S_GET_NAME (fixp
->fx_addsy
));
24828 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24829 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
24836 switch (fixp
->fx_r_type
)
24838 case BFD_RELOC_NONE
: type
= "NONE"; break;
24839 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
24840 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
24841 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
24842 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
24843 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
24844 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
24845 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
24846 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
24847 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
24848 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
24849 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
24850 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
24851 default: type
= _("<unknown>"); break;
24853 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24854 _("cannot represent %s relocation in this object file format"),
24861 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
24863 && fixp
->fx_addsy
== GOT_symbol
)
24865 code
= BFD_RELOC_ARM_GOTPC
;
24866 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
24870 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
24872 if (reloc
->howto
== NULL
)
24874 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
24875 _("cannot represent %s relocation in this object file format"),
24876 bfd_get_reloc_code_name (code
));
24880 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
24881 vtable entry to be used in the relocation's section offset. */
24882 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
24883 reloc
->address
= fixp
->fx_offset
;
24888 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
24891 cons_fix_new_arm (fragS
* frag
,
24895 bfd_reloc_code_real_type reloc
)
24900 FIXME: @@ Should look at CPU word size. */
24904 reloc
= BFD_RELOC_8
;
24907 reloc
= BFD_RELOC_16
;
24911 reloc
= BFD_RELOC_32
;
24914 reloc
= BFD_RELOC_64
;
24919 if (exp
->X_op
== O_secrel
)
24921 exp
->X_op
= O_symbol
;
24922 reloc
= BFD_RELOC_32_SECREL
;
24926 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
24929 #if defined (OBJ_COFF)
24931 arm_validate_fix (fixS
* fixP
)
24933 /* If the destination of the branch is a defined symbol which does not have
24934 the THUMB_FUNC attribute, then we must be calling a function which has
24935 the (interfacearm) attribute. We look for the Thumb entry point to that
24936 function and change the branch to refer to that function instead. */
24937 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
24938 && fixP
->fx_addsy
!= NULL
24939 && S_IS_DEFINED (fixP
->fx_addsy
)
24940 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
24942 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
24949 arm_force_relocation (struct fix
* fixp
)
24951 #if defined (OBJ_COFF) && defined (TE_PE)
24952 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
24956 /* In case we have a call or a branch to a function in ARM ISA mode from
24957 a thumb function or vice-versa force the relocation. These relocations
24958 are cleared off for some cores that might have blx and simple transformations
24962 switch (fixp
->fx_r_type
)
24964 case BFD_RELOC_ARM_PCREL_JUMP
:
24965 case BFD_RELOC_ARM_PCREL_CALL
:
24966 case BFD_RELOC_THUMB_PCREL_BLX
:
24967 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
24971 case BFD_RELOC_ARM_PCREL_BLX
:
24972 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
24973 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
24974 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
24975 if (ARM_IS_FUNC (fixp
->fx_addsy
))
24984 /* Resolve these relocations even if the symbol is extern or weak.
24985 Technically this is probably wrong due to symbol preemption.
24986 In practice these relocations do not have enough range to be useful
24987 at dynamic link time, and some code (e.g. in the Linux kernel)
24988 expects these references to be resolved. */
24989 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
24990 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
24991 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
24992 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
24993 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
24994 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
24995 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
24996 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
24997 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
24998 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
24999 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
25000 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
25001 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
25002 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
25005 /* Always leave these relocations for the linker. */
25006 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25007 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25008 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25011 /* Always generate relocations against function symbols. */
25012 if (fixp
->fx_r_type
== BFD_RELOC_32
25014 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
25017 return generic_force_reloc (fixp
);
25020 #if defined (OBJ_ELF) || defined (OBJ_COFF)
25021 /* Relocations against function names must be left unadjusted,
25022 so that the linker can use this information to generate interworking
25023 stubs. The MIPS version of this function
25024 also prevents relocations that are mips-16 specific, but I do not
25025 know why it does this.
25028 There is one other problem that ought to be addressed here, but
25029 which currently is not: Taking the address of a label (rather
25030 than a function) and then later jumping to that address. Such
25031 addresses also ought to have their bottom bit set (assuming that
25032 they reside in Thumb code), but at the moment they will not. */
25035 arm_fix_adjustable (fixS
* fixP
)
25037 if (fixP
->fx_addsy
== NULL
)
25040 /* Preserve relocations against symbols with function type. */
25041 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
25044 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
25045 && fixP
->fx_subsy
== NULL
)
25048 /* We need the symbol name for the VTABLE entries. */
25049 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
25050 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
25053 /* Don't allow symbols to be discarded on GOT related relocs. */
25054 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
25055 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
25056 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
25057 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
25058 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
25059 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
25060 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
25061 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
25062 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
25063 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
25064 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
25065 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
25066 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
25067 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
25070 /* Similarly for group relocations. */
25071 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
25072 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
25073 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
25076 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
25077 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
25078 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
25079 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
25080 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
25081 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
25082 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
25083 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
25084 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
25087 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
25088 offsets, so keep these symbols. */
25089 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
25090 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
25095 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
25099 elf32_arm_target_format (void)
25102 return (target_big_endian
25103 ? "elf32-bigarm-symbian"
25104 : "elf32-littlearm-symbian");
25105 #elif defined (TE_VXWORKS)
25106 return (target_big_endian
25107 ? "elf32-bigarm-vxworks"
25108 : "elf32-littlearm-vxworks");
25109 #elif defined (TE_NACL)
25110 return (target_big_endian
25111 ? "elf32-bigarm-nacl"
25112 : "elf32-littlearm-nacl");
25114 if (target_big_endian
)
25115 return "elf32-bigarm";
25117 return "elf32-littlearm";
25122 armelf_frob_symbol (symbolS
* symp
,
25125 elf_frob_symbol (symp
, puntp
);
25129 /* MD interface: Finalization. */
25134 literal_pool
* pool
;
25136 /* Ensure that all the IT blocks are properly closed. */
25137 check_it_blocks_finished ();
25139 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
25141 /* Put it at the end of the relevant section. */
25142 subseg_set (pool
->section
, pool
->sub_section
);
25144 arm_elf_change_section ();
25151 /* Remove any excess mapping symbols generated for alignment frags in
25152 SEC. We may have created a mapping symbol before a zero byte
25153 alignment; remove it if there's a mapping symbol after the
25156 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
25157 void *dummy ATTRIBUTE_UNUSED
)
25159 segment_info_type
*seginfo
= seg_info (sec
);
25162 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
25165 for (fragp
= seginfo
->frchainP
->frch_root
;
25167 fragp
= fragp
->fr_next
)
25169 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
25170 fragS
*next
= fragp
->fr_next
;
25172 /* Variable-sized frags have been converted to fixed size by
25173 this point. But if this was variable-sized to start with,
25174 there will be a fixed-size frag after it. So don't handle
25176 if (sym
== NULL
|| next
== NULL
)
25179 if (S_GET_VALUE (sym
) < next
->fr_address
)
25180 /* Not at the end of this frag. */
25182 know (S_GET_VALUE (sym
) == next
->fr_address
);
25186 if (next
->tc_frag_data
.first_map
!= NULL
)
25188 /* Next frag starts with a mapping symbol. Discard this
25190 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25194 if (next
->fr_next
== NULL
)
25196 /* This mapping symbol is at the end of the section. Discard
25198 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
25199 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
25203 /* As long as we have empty frags without any mapping symbols,
25205 /* If the next frag is non-empty and does not start with a
25206 mapping symbol, then this mapping symbol is required. */
25207 if (next
->fr_address
!= next
->fr_next
->fr_address
)
25210 next
= next
->fr_next
;
25212 while (next
!= NULL
);
25217 /* Adjust the symbol table. This marks Thumb symbols as distinct from
25221 arm_adjust_symtab (void)
25226 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25228 if (ARM_IS_THUMB (sym
))
25230 if (THUMB_IS_FUNC (sym
))
25232 /* Mark the symbol as a Thumb function. */
25233 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
25234 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
25235 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
25237 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
25238 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
25240 as_bad (_("%s: unexpected function type: %d"),
25241 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
25243 else switch (S_GET_STORAGE_CLASS (sym
))
25246 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
25249 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
25252 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
25260 if (ARM_IS_INTERWORK (sym
))
25261 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
25268 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
25270 if (ARM_IS_THUMB (sym
))
25272 elf_symbol_type
* elf_sym
;
25274 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
25275 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
25277 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
25278 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
25280 /* If it's a .thumb_func, declare it as so,
25281 otherwise tag label as .code 16. */
25282 if (THUMB_IS_FUNC (sym
))
25283 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
25284 ST_BRANCH_TO_THUMB
);
25285 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
25286 elf_sym
->internal_elf_sym
.st_info
=
25287 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
25292 /* Remove any overlapping mapping symbols generated by alignment frags. */
25293 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
25294 /* Now do generic ELF adjustments. */
25295 elf_adjust_symtab ();
25299 /* MD interface: Initialization. */
25302 set_constant_flonums (void)
25306 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
25307 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
25311 /* Auto-select Thumb mode if it's the only available instruction set for the
25312 given architecture. */
25315 autoselect_thumb_from_cpu_variant (void)
25317 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
25318 opcode_select (16);
25327 if ( (arm_ops_hsh
= hash_new ()) == NULL
25328 || (arm_cond_hsh
= hash_new ()) == NULL
25329 || (arm_shift_hsh
= hash_new ()) == NULL
25330 || (arm_psr_hsh
= hash_new ()) == NULL
25331 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
25332 || (arm_reg_hsh
= hash_new ()) == NULL
25333 || (arm_reloc_hsh
= hash_new ()) == NULL
25334 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
25335 as_fatal (_("virtual memory exhausted"));
25337 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
25338 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
25339 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
25340 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
25341 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
25342 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
25343 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
25344 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
25345 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
25346 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
25347 (void *) (v7m_psrs
+ i
));
25348 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
25349 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
25351 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
25353 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
25354 (void *) (barrier_opt_names
+ i
));
25356 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
25358 struct reloc_entry
* entry
= reloc_names
+ i
;
25360 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
25361 /* This makes encode_branch() use the EABI versions of this relocation. */
25362 entry
->reloc
= BFD_RELOC_UNUSED
;
25364 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
25368 set_constant_flonums ();
25370 /* Set the cpu variant based on the command-line options. We prefer
25371 -mcpu= over -march= if both are set (as for GCC); and we prefer
25372 -mfpu= over any other way of setting the floating point unit.
25373 Use of legacy options with new options are faulted. */
25376 if (mcpu_cpu_opt
|| march_cpu_opt
)
25377 as_bad (_("use of old and new-style options to set CPU type"));
25379 selected_arch
= *legacy_cpu
;
25381 else if (mcpu_cpu_opt
)
25383 selected_arch
= *mcpu_cpu_opt
;
25384 selected_ext
= *mcpu_ext_opt
;
25386 else if (march_cpu_opt
)
25388 selected_arch
= *march_cpu_opt
;
25389 selected_ext
= *march_ext_opt
;
25391 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
25396 as_bad (_("use of old and new-style options to set FPU type"));
25398 selected_fpu
= *legacy_fpu
;
25401 selected_fpu
= *mfpu_opt
;
25404 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
25405 || defined (TE_NetBSD) || defined (TE_VXWORKS))
25406 /* Some environments specify a default FPU. If they don't, infer it
25407 from the processor. */
25409 selected_fpu
= *mcpu_fpu_opt
;
25411 selected_fpu
= *march_fpu_opt
;
25413 selected_fpu
= fpu_default
;
25417 if (ARM_FEATURE_ZERO (selected_fpu
))
25419 if (!no_cpu_selected ())
25420 selected_fpu
= fpu_default
;
25422 selected_fpu
= fpu_arch_fpa
;
25426 if (ARM_FEATURE_ZERO (selected_arch
))
25428 selected_arch
= cpu_default
;
25429 selected_cpu
= selected_arch
;
25431 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25433 /* Autodection of feature mode: allow all features in cpu_variant but leave
25434 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
25435 after all instruction have been processed and we can decide what CPU
25436 should be selected. */
25437 if (ARM_FEATURE_ZERO (selected_arch
))
25438 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
25440 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
25443 autoselect_thumb_from_cpu_variant ();
25445 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
25447 #if defined OBJ_COFF || defined OBJ_ELF
25449 unsigned int flags
= 0;
25451 #if defined OBJ_ELF
25452 flags
= meabi_flags
;
25454 switch (meabi_flags
)
25456 case EF_ARM_EABI_UNKNOWN
:
25458 /* Set the flags in the private structure. */
25459 if (uses_apcs_26
) flags
|= F_APCS26
;
25460 if (support_interwork
) flags
|= F_INTERWORK
;
25461 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
25462 if (pic_code
) flags
|= F_PIC
;
25463 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
25464 flags
|= F_SOFT_FLOAT
;
25466 switch (mfloat_abi_opt
)
25468 case ARM_FLOAT_ABI_SOFT
:
25469 case ARM_FLOAT_ABI_SOFTFP
:
25470 flags
|= F_SOFT_FLOAT
;
25473 case ARM_FLOAT_ABI_HARD
:
25474 if (flags
& F_SOFT_FLOAT
)
25475 as_bad (_("hard-float conflicts with specified fpu"));
25479 /* Using pure-endian doubles (even if soft-float). */
25480 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
25481 flags
|= F_VFP_FLOAT
;
25483 #if defined OBJ_ELF
25484 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
25485 flags
|= EF_ARM_MAVERICK_FLOAT
;
25488 case EF_ARM_EABI_VER4
:
25489 case EF_ARM_EABI_VER5
:
25490 /* No additional flags to set. */
25497 bfd_set_private_flags (stdoutput
, flags
);
25499 /* We have run out flags in the COFF header to encode the
25500 status of ATPCS support, so instead we create a dummy,
25501 empty, debug section called .arm.atpcs. */
25506 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
25510 bfd_set_section_flags
25511 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
25512 bfd_set_section_size (stdoutput
, sec
, 0);
25513 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
25519 /* Record the CPU type as well. */
25520 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
25521 mach
= bfd_mach_arm_iWMMXt2
;
25522 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
25523 mach
= bfd_mach_arm_iWMMXt
;
25524 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
25525 mach
= bfd_mach_arm_XScale
;
25526 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
25527 mach
= bfd_mach_arm_ep9312
;
25528 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
25529 mach
= bfd_mach_arm_5TE
;
25530 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
25532 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25533 mach
= bfd_mach_arm_5T
;
25535 mach
= bfd_mach_arm_5
;
25537 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
25539 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
25540 mach
= bfd_mach_arm_4T
;
25542 mach
= bfd_mach_arm_4
;
25544 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
25545 mach
= bfd_mach_arm_3M
;
25546 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
25547 mach
= bfd_mach_arm_3
;
25548 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
25549 mach
= bfd_mach_arm_2a
;
25550 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
25551 mach
= bfd_mach_arm_2
;
25553 mach
= bfd_mach_arm_unknown
;
25555 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
25558 /* Command line processing. */
25561 Invocation line includes a switch not recognized by the base assembler.
25562 See if it's a processor-specific option.
25564 This routine is somewhat complicated by the need for backwards
25565 compatibility (since older releases of gcc can't be changed).
25566 The new options try to make the interface as compatible as
25569 New options (supported) are:
25571 -mcpu=<cpu name> Assemble for selected processor
25572 -march=<architecture name> Assemble for selected architecture
25573 -mfpu=<fpu architecture> Assemble for selected FPU.
25574 -EB/-mbig-endian Big-endian
25575 -EL/-mlittle-endian Little-endian
25576 -k Generate PIC code
25577 -mthumb Start in Thumb mode
25578 -mthumb-interwork Code supports ARM/Thumb interworking
25580 -m[no-]warn-deprecated Warn about deprecated features
25581 -m[no-]warn-syms Warn when symbols match instructions
25583 For now we will also provide support for:
25585 -mapcs-32 32-bit Program counter
25586 -mapcs-26 26-bit Program counter
25587 -macps-float Floats passed in FP registers
25588 -mapcs-reentrant Reentrant code
25590 (sometime these will probably be replaced with -mapcs=<list of options>
25591 and -matpcs=<list of options>)
25593 The remaining options are only supported for back-wards compatibility.
25594 Cpu variants, the arm part is optional:
25595 -m[arm]1 Currently not supported.
25596 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
25597 -m[arm]3 Arm 3 processor
25598 -m[arm]6[xx], Arm 6 processors
25599 -m[arm]7[xx][t][[d]m] Arm 7 processors
25600 -m[arm]8[10] Arm 8 processors
25601 -m[arm]9[20][tdmi] Arm 9 processors
25602 -mstrongarm[110[0]] StrongARM processors
25603 -mxscale XScale processors
25604 -m[arm]v[2345[t[e]]] Arm architectures
25605 -mall All (except the ARM1)
25607 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
25608 -mfpe-old (No float load/store multiples)
25609 -mvfpxd VFP Single precision
25611 -mno-fpu Disable all floating point instructions
25613 The following CPU names are recognized:
25614 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
25615 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
25616 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
25617 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
25618 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
25619 arm10t arm10e, arm1020t, arm1020e, arm10200e,
25620 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
25624 const char * md_shortopts
= "m:k";
25626 #ifdef ARM_BI_ENDIAN
25627 #define OPTION_EB (OPTION_MD_BASE + 0)
25628 #define OPTION_EL (OPTION_MD_BASE + 1)
25630 #if TARGET_BYTES_BIG_ENDIAN
25631 #define OPTION_EB (OPTION_MD_BASE + 0)
25633 #define OPTION_EL (OPTION_MD_BASE + 1)
25636 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
25638 struct option md_longopts
[] =
25641 {"EB", no_argument
, NULL
, OPTION_EB
},
25644 {"EL", no_argument
, NULL
, OPTION_EL
},
25646 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
25647 {NULL
, no_argument
, NULL
, 0}
25650 size_t md_longopts_size
= sizeof (md_longopts
);
25652 struct arm_option_table
25654 const char * option
; /* Option name to match. */
25655 const char * help
; /* Help information. */
25656 int * var
; /* Variable to change. */
25657 int value
; /* What to change it to. */
25658 const char * deprecated
; /* If non-null, print this message. */
25661 struct arm_option_table arm_opts
[] =
25663 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
25664 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
25665 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
25666 &support_interwork
, 1, NULL
},
25667 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
25668 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
25669 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
25671 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
25672 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
25673 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
25674 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
25677 /* These are recognized by the assembler, but have no affect on code. */
25678 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
25679 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
25681 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
25682 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
25683 &warn_on_deprecated
, 0, NULL
},
25684 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
25685 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
25686 {NULL
, NULL
, NULL
, 0, NULL
}
25689 struct arm_legacy_option_table
25691 const char * option
; /* Option name to match. */
25692 const arm_feature_set
** var
; /* Variable to change. */
25693 const arm_feature_set value
; /* What to change it to. */
25694 const char * deprecated
; /* If non-null, print this message. */
25697 const struct arm_legacy_option_table arm_legacy_opts
[] =
25699 /* DON'T add any new processors to this list -- we want the whole list
25700 to go away... Add them to the processors table instead. */
25701 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25702 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
25703 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25704 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
25705 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25706 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
25707 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25708 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
25709 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25710 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
25711 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25712 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
25713 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25714 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
25715 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25716 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
25717 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25718 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
25719 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25720 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
25721 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25722 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
25723 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25724 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
25725 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25726 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
25727 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25728 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
25729 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25730 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
25731 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25732 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
25733 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25734 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
25735 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25736 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
25737 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25738 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
25739 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25740 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
25741 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25742 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
25743 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25744 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
25745 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25746 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
25747 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25748 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25749 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25750 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
25751 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25752 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
25753 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25754 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
25755 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25756 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
25757 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25758 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
25759 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25760 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
25761 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25762 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
25763 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25764 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
25765 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25766 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
25767 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25768 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
25769 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
25770 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
25771 N_("use -mcpu=strongarm110")},
25772 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
25773 N_("use -mcpu=strongarm1100")},
25774 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
25775 N_("use -mcpu=strongarm1110")},
25776 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
25777 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
25778 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
25780 /* Architecture variants -- don't add any more to this list either. */
25781 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25782 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
25783 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25784 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
25785 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25786 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
25787 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25788 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
25789 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25790 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
25791 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25792 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
25793 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25794 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
25795 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25796 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
25797 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25798 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
25800 /* Floating point variants -- don't add any more to this list either. */
25801 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
25802 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
25803 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
25804 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
25805 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
25807 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
25810 struct arm_cpu_option_table
25814 const arm_feature_set value
;
25815 const arm_feature_set ext
;
25816 /* For some CPUs we assume an FPU unless the user explicitly sets
25818 const arm_feature_set default_fpu
;
25819 /* The canonical name of the CPU, or NULL to use NAME converted to upper
25821 const char * canonical_name
;
25824 /* This list should, at a minimum, contain all the cpu names
25825 recognized by GCC. */
25826 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
25828 static const struct arm_cpu_option_table arm_cpus
[] =
25830 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
25833 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
25836 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
25839 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
25842 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
25845 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
25848 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
25851 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
25854 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
25857 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
25860 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
25863 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
25866 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
25869 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
25872 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
25875 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
25878 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
25881 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
25884 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
25887 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
25890 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
25893 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
25896 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
25899 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
25902 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
25905 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
25908 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
25911 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
25914 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
25917 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
25920 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
25923 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
25926 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
25929 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
25932 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
25935 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
25938 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
25941 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
25944 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
25947 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
25950 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
25953 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
25956 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
25959 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
25962 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
25965 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
25969 /* For V5 or later processors we default to using VFP; but the user
25970 should really set the FPU type explicitly. */
25971 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
25974 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
25977 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25980 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
25983 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
25986 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
25989 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
25992 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
25995 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
25998 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
26001 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
26004 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
26007 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
26010 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
26013 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
26016 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
26019 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
26022 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
26025 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
26028 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
26031 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
26034 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
26037 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
26040 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
26043 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
26046 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
26049 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
26052 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
26055 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
26058 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
26061 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
26064 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
26067 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
26070 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
26073 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
26076 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
26079 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
26080 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26082 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
26084 FPU_ARCH_NEON_VFP_V4
),
26085 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
26086 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26087 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26088 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
26089 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26090 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
26091 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
26093 FPU_ARCH_NEON_VFP_V4
),
26094 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
26096 FPU_ARCH_NEON_VFP_V4
),
26097 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
26099 FPU_ARCH_NEON_VFP_V4
),
26100 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
26101 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26102 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26103 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
26104 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26105 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26106 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
26107 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26108 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26109 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
26110 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26111 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26112 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
26113 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26114 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26115 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
26116 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26117 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26118 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
26119 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26120 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26121 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
26122 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26123 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
26124 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
26127 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
26129 FPU_ARCH_VFP_V3D16
),
26130 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
26131 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26133 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
26134 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26135 FPU_ARCH_VFP_V3D16
),
26136 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
26137 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
26138 FPU_ARCH_VFP_V3D16
),
26139 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
26140 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26141 FPU_ARCH_NEON_VFP_ARMV8
),
26142 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
26143 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26145 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
26148 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
26151 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
26154 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
26157 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
26160 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
26163 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
26166 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
26167 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26168 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26170 /* ??? XSCALE is really an architecture. */
26171 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
26175 /* ??? iwmmxt is not a processor. */
26176 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
26179 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
26182 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
26187 ARM_CPU_OPT ("ep9312", "ARM920T",
26188 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
26189 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
26191 /* Marvell processors. */
26192 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
26193 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26194 FPU_ARCH_VFP_V3D16
),
26195 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
26196 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
26197 FPU_ARCH_NEON_VFP_V4
),
26199 /* APM X-Gene family. */
26200 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
26202 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26203 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
26204 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26205 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
26207 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
26211 struct arm_arch_option_table
26215 const arm_feature_set value
;
26216 const arm_feature_set default_fpu
;
26219 /* This list should, at a minimum, contain all the architecture names
26220 recognized by GCC. */
26221 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF }
26223 static const struct arm_arch_option_table arm_archs
[] =
26225 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
26226 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
26227 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
26228 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26229 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
26230 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
26231 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
26232 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
26233 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
26234 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
26235 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
26236 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
26237 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
26238 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
26239 ARM_ARCH_OPT ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
),
26240 ARM_ARCH_OPT ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
),
26241 ARM_ARCH_OPT ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
),
26242 ARM_ARCH_OPT ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26243 ARM_ARCH_OPT ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
),
26244 ARM_ARCH_OPT ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
),
26245 ARM_ARCH_OPT ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
),
26246 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
26247 kept to preserve existing behaviour. */
26248 ARM_ARCH_OPT ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26249 ARM_ARCH_OPT ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
),
26250 ARM_ARCH_OPT ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
),
26251 ARM_ARCH_OPT ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
),
26252 ARM_ARCH_OPT ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
),
26253 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
26254 kept to preserve existing behaviour. */
26255 ARM_ARCH_OPT ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26256 ARM_ARCH_OPT ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
),
26257 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
26258 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
26259 ARM_ARCH_OPT ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
),
26260 /* The official spelling of the ARMv7 profile variants is the dashed form.
26261 Accept the non-dashed form for compatibility with old toolchains. */
26262 ARM_ARCH_OPT ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26263 ARM_ARCH_OPT ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
),
26264 ARM_ARCH_OPT ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26265 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26266 ARM_ARCH_OPT ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
),
26267 ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
),
26268 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
26269 ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
),
26270 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
26271 ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
),
26272 ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
),
26273 ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
),
26274 ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
),
26275 ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
),
26276 ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
),
26277 ARM_ARCH_OPT ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
),
26278 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
26279 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
26280 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
,FPU_ARCH_VFP
),
26281 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
26283 #undef ARM_ARCH_OPT
26285 /* ISA extensions in the co-processor and main instruction set space. */
26287 struct arm_option_extension_value_table
26291 const arm_feature_set merge_value
;
26292 const arm_feature_set clear_value
;
26293 /* List of architectures for which an extension is available. ARM_ARCH_NONE
26294 indicates that an extension is available for all architectures while
26295 ARM_ANY marks an empty entry. */
26296 const arm_feature_set allowed_archs
[2];
26299 /* The following table must be in alphabetical order with a NULL last entry. */
26301 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
26302 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
26304 static const struct arm_option_extension_value_table arm_extensions
[] =
26306 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
26307 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26308 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
26309 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
26310 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26311 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
26312 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
26314 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26315 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
26316 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
26317 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
26318 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26319 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26320 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
26322 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26323 | ARM_EXT2_FP16_FML
),
26324 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
26325 | ARM_EXT2_FP16_FML
),
26327 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26328 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
26329 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26330 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26331 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
26332 Thumb divide instruction. Due to this having the same name as the
26333 previous entry, this will be ignored when doing command-line parsing and
26334 only considered by build attribute selection code. */
26335 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26336 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
26337 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
26338 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
26339 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
26340 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
26341 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
26342 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
26343 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
26344 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26345 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
26346 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
26347 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
26348 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26349 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
26350 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
26351 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
26352 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
26353 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26354 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
26355 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
26356 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26357 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
26358 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
26359 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
26360 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26361 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
26362 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
26363 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26364 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
26365 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
26366 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
26367 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
26369 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
26370 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
26371 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
26372 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
26373 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
26377 /* ISA floating-point and Advanced SIMD extensions. */
26378 struct arm_option_fpu_value_table
26381 const arm_feature_set value
;
26384 /* This list should, at a minimum, contain all the fpu names
26385 recognized by GCC. */
26386 static const struct arm_option_fpu_value_table arm_fpus
[] =
26388 {"softfpa", FPU_NONE
},
26389 {"fpe", FPU_ARCH_FPE
},
26390 {"fpe2", FPU_ARCH_FPE
},
26391 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
26392 {"fpa", FPU_ARCH_FPA
},
26393 {"fpa10", FPU_ARCH_FPA
},
26394 {"fpa11", FPU_ARCH_FPA
},
26395 {"arm7500fe", FPU_ARCH_FPA
},
26396 {"softvfp", FPU_ARCH_VFP
},
26397 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
26398 {"vfp", FPU_ARCH_VFP_V2
},
26399 {"vfp9", FPU_ARCH_VFP_V2
},
26400 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
26401 {"vfp10", FPU_ARCH_VFP_V2
},
26402 {"vfp10-r0", FPU_ARCH_VFP_V1
},
26403 {"vfpxd", FPU_ARCH_VFP_V1xD
},
26404 {"vfpv2", FPU_ARCH_VFP_V2
},
26405 {"vfpv3", FPU_ARCH_VFP_V3
},
26406 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
26407 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
26408 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
26409 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
26410 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
26411 {"arm1020t", FPU_ARCH_VFP_V1
},
26412 {"arm1020e", FPU_ARCH_VFP_V2
},
26413 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
26414 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
26415 {"maverick", FPU_ARCH_MAVERICK
},
26416 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26417 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
26418 {"neon-fp16", FPU_ARCH_NEON_FP16
},
26419 {"vfpv4", FPU_ARCH_VFP_V4
},
26420 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
26421 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
26422 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
26423 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
26424 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
26425 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
26426 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
26427 {"crypto-neon-fp-armv8",
26428 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
26429 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
26430 {"crypto-neon-fp-armv8.1",
26431 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
26432 {NULL
, ARM_ARCH_NONE
}
26435 struct arm_option_value_table
26441 static const struct arm_option_value_table arm_float_abis
[] =
26443 {"hard", ARM_FLOAT_ABI_HARD
},
26444 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
26445 {"soft", ARM_FLOAT_ABI_SOFT
},
26450 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
26451 static const struct arm_option_value_table arm_eabis
[] =
26453 {"gnu", EF_ARM_EABI_UNKNOWN
},
26454 {"4", EF_ARM_EABI_VER4
},
26455 {"5", EF_ARM_EABI_VER5
},
26460 struct arm_long_option_table
26462 const char * option
; /* Substring to match. */
26463 const char * help
; /* Help information. */
26464 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
26465 const char * deprecated
; /* If non-null, print this message. */
26469 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
26470 arm_feature_set
*ext_set
)
26472 /* We insist on extensions being specified in alphabetical order, and with
26473 extensions being added before being removed. We achieve this by having
26474 the global ARM_EXTENSIONS table in alphabetical order, and using the
26475 ADDING_VALUE variable to indicate whether we are adding an extension (1)
26476 or removing it (0) and only allowing it to change in the order
26478 const struct arm_option_extension_value_table
* opt
= NULL
;
26479 const arm_feature_set arm_any
= ARM_ANY
;
26480 int adding_value
= -1;
26482 while (str
!= NULL
&& *str
!= 0)
26489 as_bad (_("invalid architectural extension"));
26494 ext
= strchr (str
, '+');
26499 len
= strlen (str
);
26501 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
26503 if (adding_value
!= 0)
26506 opt
= arm_extensions
;
26514 if (adding_value
== -1)
26517 opt
= arm_extensions
;
26519 else if (adding_value
!= 1)
26521 as_bad (_("must specify extensions to add before specifying "
26522 "those to remove"));
26529 as_bad (_("missing architectural extension"));
26533 gas_assert (adding_value
!= -1);
26534 gas_assert (opt
!= NULL
);
26536 /* Scan over the options table trying to find an exact match. */
26537 for (; opt
->name
!= NULL
; opt
++)
26538 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26540 int i
, nb_allowed_archs
=
26541 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
26542 /* Check we can apply the extension to this architecture. */
26543 for (i
= 0; i
< nb_allowed_archs
; i
++)
26546 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
26548 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
26551 if (i
== nb_allowed_archs
)
26553 as_bad (_("extension does not apply to the base architecture"));
26557 /* Add or remove the extension. */
26559 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
26561 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
26563 /* Allowing Thumb division instructions for ARMv7 in autodetection
26564 rely on this break so that duplicate extensions (extensions
26565 with the same name as a previous extension in the list) are not
26566 considered for command-line parsing. */
26570 if (opt
->name
== NULL
)
26572 /* Did we fail to find an extension because it wasn't specified in
26573 alphabetical order, or because it does not exist? */
26575 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
26576 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26579 if (opt
->name
== NULL
)
26580 as_bad (_("unknown architectural extension `%s'"), str
);
26582 as_bad (_("architectural extensions must be specified in "
26583 "alphabetical order"));
26589 /* We should skip the extension we've just matched the next time
26601 arm_parse_cpu (const char *str
)
26603 const struct arm_cpu_option_table
*opt
;
26604 const char *ext
= strchr (str
, '+');
26610 len
= strlen (str
);
26614 as_bad (_("missing cpu name `%s'"), str
);
26618 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
26619 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26621 mcpu_cpu_opt
= &opt
->value
;
26622 if (mcpu_ext_opt
== NULL
)
26623 mcpu_ext_opt
= XNEW (arm_feature_set
);
26624 *mcpu_ext_opt
= opt
->ext
;
26625 mcpu_fpu_opt
= &opt
->default_fpu
;
26626 if (opt
->canonical_name
)
26628 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
26629 strcpy (selected_cpu_name
, opt
->canonical_name
);
26635 if (len
>= sizeof selected_cpu_name
)
26636 len
= (sizeof selected_cpu_name
) - 1;
26638 for (i
= 0; i
< len
; i
++)
26639 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
26640 selected_cpu_name
[i
] = 0;
26644 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
);
26649 as_bad (_("unknown cpu `%s'"), str
);
26654 arm_parse_arch (const char *str
)
26656 const struct arm_arch_option_table
*opt
;
26657 const char *ext
= strchr (str
, '+');
26663 len
= strlen (str
);
26667 as_bad (_("missing architecture name `%s'"), str
);
26671 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
26672 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
26674 march_cpu_opt
= &opt
->value
;
26675 if (march_ext_opt
== NULL
)
26676 march_ext_opt
= XNEW (arm_feature_set
);
26677 *march_ext_opt
= arm_arch_none
;
26678 march_fpu_opt
= &opt
->default_fpu
;
26679 strcpy (selected_cpu_name
, opt
->name
);
26682 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
);
26687 as_bad (_("unknown architecture `%s'\n"), str
);
26692 arm_parse_fpu (const char * str
)
26694 const struct arm_option_fpu_value_table
* opt
;
26696 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
26697 if (streq (opt
->name
, str
))
26699 mfpu_opt
= &opt
->value
;
26703 as_bad (_("unknown floating point format `%s'\n"), str
);
26708 arm_parse_float_abi (const char * str
)
26710 const struct arm_option_value_table
* opt
;
26712 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
26713 if (streq (opt
->name
, str
))
26715 mfloat_abi_opt
= opt
->value
;
26719 as_bad (_("unknown floating point abi `%s'\n"), str
);
26725 arm_parse_eabi (const char * str
)
26727 const struct arm_option_value_table
*opt
;
26729 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
26730 if (streq (opt
->name
, str
))
26732 meabi_flags
= opt
->value
;
26735 as_bad (_("unknown EABI `%s'\n"), str
);
26741 arm_parse_it_mode (const char * str
)
26743 bfd_boolean ret
= TRUE
;
26745 if (streq ("arm", str
))
26746 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
26747 else if (streq ("thumb", str
))
26748 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
26749 else if (streq ("always", str
))
26750 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
26751 else if (streq ("never", str
))
26752 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
26755 as_bad (_("unknown implicit IT mode `%s', should be "\
26756 "arm, thumb, always, or never."), str
);
26764 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
26766 codecomposer_syntax
= TRUE
;
26767 arm_comment_chars
[0] = ';';
26768 arm_line_separator_chars
[0] = 0;
26772 struct arm_long_option_table arm_long_opts
[] =
26774 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
26775 arm_parse_cpu
, NULL
},
26776 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
26777 arm_parse_arch
, NULL
},
26778 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
26779 arm_parse_fpu
, NULL
},
26780 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
26781 arm_parse_float_abi
, NULL
},
26783 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
26784 arm_parse_eabi
, NULL
},
26786 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
26787 arm_parse_it_mode
, NULL
},
26788 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
26789 arm_ccs_mode
, NULL
},
26790 {NULL
, NULL
, 0, NULL
}
26794 md_parse_option (int c
, const char * arg
)
26796 struct arm_option_table
*opt
;
26797 const struct arm_legacy_option_table
*fopt
;
26798 struct arm_long_option_table
*lopt
;
26804 target_big_endian
= 1;
26810 target_big_endian
= 0;
26814 case OPTION_FIX_V4BX
:
26819 /* Listing option. Just ignore these, we don't support additional
26824 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26826 if (c
== opt
->option
[0]
26827 && ((arg
== NULL
&& opt
->option
[1] == 0)
26828 || streq (arg
, opt
->option
+ 1)))
26830 /* If the option is deprecated, tell the user. */
26831 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
26832 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26833 arg
? arg
: "", _(opt
->deprecated
));
26835 if (opt
->var
!= NULL
)
26836 *opt
->var
= opt
->value
;
26842 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
26844 if (c
== fopt
->option
[0]
26845 && ((arg
== NULL
&& fopt
->option
[1] == 0)
26846 || streq (arg
, fopt
->option
+ 1)))
26848 /* If the option is deprecated, tell the user. */
26849 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
26850 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
26851 arg
? arg
: "", _(fopt
->deprecated
));
26853 if (fopt
->var
!= NULL
)
26854 *fopt
->var
= &fopt
->value
;
26860 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26862 /* These options are expected to have an argument. */
26863 if (c
== lopt
->option
[0]
26865 && strncmp (arg
, lopt
->option
+ 1,
26866 strlen (lopt
->option
+ 1)) == 0)
26868 /* If the option is deprecated, tell the user. */
26869 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
26870 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
26871 _(lopt
->deprecated
));
26873 /* Call the sup-option parser. */
26874 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
26885 md_show_usage (FILE * fp
)
26887 struct arm_option_table
*opt
;
26888 struct arm_long_option_table
*lopt
;
26890 fprintf (fp
, _(" ARM-specific assembler options:\n"));
26892 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
26893 if (opt
->help
!= NULL
)
26894 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
26896 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
26897 if (lopt
->help
!= NULL
)
26898 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
26902 -EB assemble code for a big-endian cpu\n"));
26907 -EL assemble code for a little-endian cpu\n"));
26911 --fix-v4bx Allow BX in ARMv4 code\n"));
26919 arm_feature_set flags
;
26920 } cpu_arch_ver_table
;
26922 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
26923 chronologically for architectures, with an exception for ARMv6-M and
26924 ARMv6S-M due to legacy reasons. No new architecture should have a
26925 special case. This allows for build attribute selection results to be
26926 stable when new architectures are added. */
26927 static const cpu_arch_ver_table cpu_arch_ver
[] =
26934 {1, ARM_ARCH_V4xM
},
26936 {2, ARM_ARCH_V4TxM
},
26938 {3, ARM_ARCH_V5xM
},
26940 {3, ARM_ARCH_V5TxM
},
26942 {4, ARM_ARCH_V5TExP
},
26943 {4, ARM_ARCH_V5TE
},
26944 {5, ARM_ARCH_V5TEJ
},
26947 {7, ARM_ARCH_V6KZ
},
26949 {8, ARM_ARCH_V6T2
},
26950 {8, ARM_ARCH_V6KT2
},
26951 {8, ARM_ARCH_V6ZT2
},
26952 {8, ARM_ARCH_V6KZT2
},
26954 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
26955 always selected build attributes to match those of ARMv6-M
26956 (resp. ARMv6S-M). However, due to these architectures being a strict
26957 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
26958 would be selected when fully respecting chronology of architectures.
26959 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
26960 move them before ARMv7 architectures. */
26961 {11, ARM_ARCH_V6M
},
26962 {12, ARM_ARCH_V6SM
},
26965 {10, ARM_ARCH_V7A
},
26966 {10, ARM_ARCH_V7R
},
26967 {10, ARM_ARCH_V7M
},
26968 {10, ARM_ARCH_V7VE
},
26969 {13, ARM_ARCH_V7EM
},
26970 {14, ARM_ARCH_V8A
},
26971 {14, ARM_ARCH_V8_1A
},
26972 {14, ARM_ARCH_V8_2A
},
26973 {14, ARM_ARCH_V8_3A
},
26974 {16, ARM_ARCH_V8M_BASE
},
26975 {17, ARM_ARCH_V8M_MAIN
},
26976 {15, ARM_ARCH_V8R
},
26977 {14, ARM_ARCH_V8_4A
},
26978 {-1, ARM_ARCH_NONE
}
26981 /* Set an attribute if it has not already been set by the user. */
26984 aeabi_set_attribute_int (int tag
, int value
)
26987 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26988 || !attributes_set_explicitly
[tag
])
26989 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
26993 aeabi_set_attribute_string (int tag
, const char *value
)
26996 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
26997 || !attributes_set_explicitly
[tag
])
26998 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
27001 /* Return whether features in the *NEEDED feature set are available via
27002 extensions for the architecture whose feature set is *ARCH_FSET. */
27005 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
27006 const arm_feature_set
*needed
)
27008 int i
, nb_allowed_archs
;
27009 arm_feature_set ext_fset
;
27010 const struct arm_option_extension_value_table
*opt
;
27012 ext_fset
= arm_arch_none
;
27013 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27015 /* Extension does not provide any feature we need. */
27016 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
27020 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
27021 for (i
= 0; i
< nb_allowed_archs
; i
++)
27024 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
27027 /* Extension is available, add it. */
27028 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
27029 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
27033 /* Can we enable all features in *needed? */
27034 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
27037 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
27038 a given architecture feature set *ARCH_EXT_FSET including extension feature
27039 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
27040 - if true, check for an exact match of the architecture modulo extensions;
27041 - otherwise, select build attribute value of the first superset
27042 architecture released so that results remains stable when new architectures
27044 For -march/-mcpu=all the build attribute value of the most featureful
27045 architecture is returned. Tag_CPU_arch_profile result is returned in
27049 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
27050 const arm_feature_set
*ext_fset
,
27051 char *profile
, int exact_match
)
27053 arm_feature_set arch_fset
;
27054 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
27056 /* Select most featureful architecture with all its extensions if building
27057 for -march=all as the feature sets used to set build attributes. */
27058 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
27060 /* Force revisiting of decision for each new architecture. */
27061 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8M_MAIN
);
27063 return TAG_CPU_ARCH_V8
;
27066 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
27068 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
27070 arm_feature_set known_arch_fset
;
27072 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
27075 /* Base architecture match user-specified architecture and
27076 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
27077 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
27082 /* Base architecture match user-specified architecture only
27083 (eg. ARMv6-M in the same case as above). Record it in case we
27084 find a match with above condition. */
27085 else if (p_ver_ret
== NULL
27086 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
27092 /* Architecture has all features wanted. */
27093 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
27095 arm_feature_set added_fset
;
27097 /* Compute features added by this architecture over the one
27098 recorded in p_ver_ret. */
27099 if (p_ver_ret
!= NULL
)
27100 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
27102 /* First architecture that match incl. with extensions, or the
27103 only difference in features over the recorded match is
27104 features that were optional and are now mandatory. */
27105 if (p_ver_ret
== NULL
27106 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
27112 else if (p_ver_ret
== NULL
)
27114 arm_feature_set needed_ext_fset
;
27116 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
27118 /* Architecture has all features needed when using some
27119 extensions. Record it and continue searching in case there
27120 exist an architecture providing all needed features without
27121 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
27123 if (have_ext_for_needed_feat_p (&known_arch_fset
,
27130 if (p_ver_ret
== NULL
)
27134 /* Tag_CPU_arch_profile. */
27135 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
27136 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
27137 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
27138 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
27140 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
27142 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
27146 return p_ver_ret
->val
;
27149 /* Set the public EABI object attributes. */
27152 aeabi_set_public_attributes (void)
27154 char profile
= '\0';
27157 int fp16_optional
= 0;
27158 int skip_exact_match
= 0;
27159 arm_feature_set flags
, flags_arch
, flags_ext
;
27161 /* Autodetection mode, choose the architecture based the instructions
27163 if (no_cpu_selected ())
27165 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
27167 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
27168 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
27170 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
27171 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
27173 /* Code run during relaxation relies on selected_cpu being set. */
27174 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27175 flags_ext
= arm_arch_none
;
27176 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
27177 selected_ext
= flags_ext
;
27178 selected_cpu
= flags
;
27180 /* Otherwise, choose the architecture based on the capabilities of the
27184 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
27185 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
27186 flags_ext
= selected_ext
;
27187 flags
= selected_cpu
;
27189 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
27191 /* Allow the user to override the reported architecture. */
27192 if (!ARM_FEATURE_ZERO (selected_object_arch
))
27194 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
27195 flags_ext
= arm_arch_none
;
27198 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
27200 /* When this function is run again after relaxation has happened there is no
27201 way to determine whether an architecture or CPU was specified by the user:
27202 - selected_cpu is set above for relaxation to work;
27203 - march_cpu_opt is not set if only -mcpu or .cpu is used;
27204 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
27205 Therefore, if not in -march=all case we first try an exact match and fall
27206 back to autodetection. */
27207 if (!skip_exact_match
)
27208 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
27210 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
27212 as_bad (_("no architecture contains all the instructions used\n"));
27214 /* Tag_CPU_name. */
27215 if (selected_cpu_name
[0])
27219 q
= selected_cpu_name
;
27220 if (strncmp (q
, "armv", 4) == 0)
27225 for (i
= 0; q
[i
]; i
++)
27226 q
[i
] = TOUPPER (q
[i
]);
27228 aeabi_set_attribute_string (Tag_CPU_name
, q
);
27231 /* Tag_CPU_arch. */
27232 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
27234 /* Tag_CPU_arch_profile. */
27235 if (profile
!= '\0')
27236 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
27238 /* Tag_DSP_extension. */
27239 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
27240 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
27242 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
27243 /* Tag_ARM_ISA_use. */
27244 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
27245 || ARM_FEATURE_ZERO (flags_arch
))
27246 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
27248 /* Tag_THUMB_ISA_use. */
27249 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
27250 || ARM_FEATURE_ZERO (flags_arch
))
27254 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27255 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
27257 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
27261 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
27264 /* Tag_VFP_arch. */
27265 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
27266 aeabi_set_attribute_int (Tag_VFP_arch
,
27267 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27269 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
27270 aeabi_set_attribute_int (Tag_VFP_arch
,
27271 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
27273 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
27276 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
27278 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
27280 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
27283 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
27284 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
27285 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
27286 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
27287 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
27289 /* Tag_ABI_HardFP_use. */
27290 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
27291 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
27292 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
27294 /* Tag_WMMX_arch. */
27295 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
27296 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
27297 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
27298 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
27300 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
27301 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
27302 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
27303 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
27304 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
27305 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
27307 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
27309 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
27313 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
27318 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
27319 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
27320 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
27324 We set Tag_DIV_use to two when integer divide instructions have been used
27325 in ARM state, or when Thumb integer divide instructions have been used,
27326 but we have no architecture profile set, nor have we any ARM instructions.
27328 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
27329 by the base architecture.
27331 For new architectures we will have to check these tests. */
27332 gas_assert (arch
<= TAG_CPU_ARCH_V8M_MAIN
);
27333 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
27334 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
27335 aeabi_set_attribute_int (Tag_DIV_use
, 0);
27336 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
27337 || (profile
== '\0'
27338 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
27339 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
27340 aeabi_set_attribute_int (Tag_DIV_use
, 2);
27342 /* Tag_MP_extension_use. */
27343 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
27344 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
27346 /* Tag Virtualization_use. */
27347 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
27349 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
27352 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
27355 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
27356 finished and free extension feature bits which will not be used anymore. */
27359 arm_md_post_relax (void)
27361 aeabi_set_public_attributes ();
27362 XDELETE (mcpu_ext_opt
);
27363 mcpu_ext_opt
= NULL
;
27364 XDELETE (march_ext_opt
);
27365 march_ext_opt
= NULL
;
27368 /* Add the default contents for the .ARM.attributes section. */
27373 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
27376 aeabi_set_public_attributes ();
27378 #endif /* OBJ_ELF */
27380 /* Parse a .cpu directive. */
27383 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
27385 const struct arm_cpu_option_table
*opt
;
27389 name
= input_line_pointer
;
27390 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27391 input_line_pointer
++;
27392 saved_char
= *input_line_pointer
;
27393 *input_line_pointer
= 0;
27395 /* Skip the first "all" entry. */
27396 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
27397 if (streq (opt
->name
, name
))
27399 selected_arch
= opt
->value
;
27400 selected_ext
= opt
->ext
;
27401 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27402 if (opt
->canonical_name
)
27403 strcpy (selected_cpu_name
, opt
->canonical_name
);
27407 for (i
= 0; opt
->name
[i
]; i
++)
27408 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
27410 selected_cpu_name
[i
] = 0;
27412 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27414 *input_line_pointer
= saved_char
;
27415 demand_empty_rest_of_line ();
27418 as_bad (_("unknown cpu `%s'"), name
);
27419 *input_line_pointer
= saved_char
;
27420 ignore_rest_of_line ();
27423 /* Parse a .arch directive. */
27426 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
27428 const struct arm_arch_option_table
*opt
;
27432 name
= input_line_pointer
;
27433 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27434 input_line_pointer
++;
27435 saved_char
= *input_line_pointer
;
27436 *input_line_pointer
= 0;
27438 /* Skip the first "all" entry. */
27439 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27440 if (streq (opt
->name
, name
))
27442 selected_arch
= opt
->value
;
27443 selected_ext
= arm_arch_none
;
27444 selected_cpu
= selected_arch
;
27445 strcpy (selected_cpu_name
, opt
->name
);
27446 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27447 *input_line_pointer
= saved_char
;
27448 demand_empty_rest_of_line ();
27452 as_bad (_("unknown architecture `%s'\n"), name
);
27453 *input_line_pointer
= saved_char
;
27454 ignore_rest_of_line ();
27457 /* Parse a .object_arch directive. */
27460 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
27462 const struct arm_arch_option_table
*opt
;
27466 name
= input_line_pointer
;
27467 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27468 input_line_pointer
++;
27469 saved_char
= *input_line_pointer
;
27470 *input_line_pointer
= 0;
27472 /* Skip the first "all" entry. */
27473 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
27474 if (streq (opt
->name
, name
))
27476 selected_object_arch
= opt
->value
;
27477 *input_line_pointer
= saved_char
;
27478 demand_empty_rest_of_line ();
27482 as_bad (_("unknown architecture `%s'\n"), name
);
27483 *input_line_pointer
= saved_char
;
27484 ignore_rest_of_line ();
27487 /* Parse a .arch_extension directive. */
27490 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
27492 const struct arm_option_extension_value_table
*opt
;
27495 int adding_value
= 1;
27497 name
= input_line_pointer
;
27498 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27499 input_line_pointer
++;
27500 saved_char
= *input_line_pointer
;
27501 *input_line_pointer
= 0;
27503 if (strlen (name
) >= 2
27504 && strncmp (name
, "no", 2) == 0)
27510 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
27511 if (streq (opt
->name
, name
))
27513 int i
, nb_allowed_archs
=
27514 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
27515 for (i
= 0; i
< nb_allowed_archs
; i
++)
27518 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
27520 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
27524 if (i
== nb_allowed_archs
)
27526 as_bad (_("architectural extension `%s' is not allowed for the "
27527 "current base architecture"), name
);
27532 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
27535 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
27537 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
27538 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27539 *input_line_pointer
= saved_char
;
27540 demand_empty_rest_of_line ();
27541 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
27542 on this return so that duplicate extensions (extensions with the
27543 same name as a previous extension in the list) are not considered
27544 for command-line parsing. */
27548 if (opt
->name
== NULL
)
27549 as_bad (_("unknown architecture extension `%s'\n"), name
);
27551 *input_line_pointer
= saved_char
;
27552 ignore_rest_of_line ();
27555 /* Parse a .fpu directive. */
27558 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
27560 const struct arm_option_fpu_value_table
*opt
;
27564 name
= input_line_pointer
;
27565 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
27566 input_line_pointer
++;
27567 saved_char
= *input_line_pointer
;
27568 *input_line_pointer
= 0;
27570 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
27571 if (streq (opt
->name
, name
))
27573 selected_fpu
= opt
->value
;
27574 #ifndef CPU_DEFAULT
27575 if (no_cpu_selected ())
27576 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
27579 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
27580 *input_line_pointer
= saved_char
;
27581 demand_empty_rest_of_line ();
27585 as_bad (_("unknown floating point format `%s'\n"), name
);
27586 *input_line_pointer
= saved_char
;
27587 ignore_rest_of_line ();
27590 /* Copy symbol information. */
27593 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
27595 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
27599 /* Given a symbolic attribute NAME, return the proper integer value.
27600 Returns -1 if the attribute is not known. */
27603 arm_convert_symbolic_attribute (const char *name
)
27605 static const struct
27610 attribute_table
[] =
27612 /* When you modify this table you should
27613 also modify the list in doc/c-arm.texi. */
27614 #define T(tag) {#tag, tag}
27615 T (Tag_CPU_raw_name
),
27618 T (Tag_CPU_arch_profile
),
27619 T (Tag_ARM_ISA_use
),
27620 T (Tag_THUMB_ISA_use
),
27624 T (Tag_Advanced_SIMD_arch
),
27625 T (Tag_PCS_config
),
27626 T (Tag_ABI_PCS_R9_use
),
27627 T (Tag_ABI_PCS_RW_data
),
27628 T (Tag_ABI_PCS_RO_data
),
27629 T (Tag_ABI_PCS_GOT_use
),
27630 T (Tag_ABI_PCS_wchar_t
),
27631 T (Tag_ABI_FP_rounding
),
27632 T (Tag_ABI_FP_denormal
),
27633 T (Tag_ABI_FP_exceptions
),
27634 T (Tag_ABI_FP_user_exceptions
),
27635 T (Tag_ABI_FP_number_model
),
27636 T (Tag_ABI_align_needed
),
27637 T (Tag_ABI_align8_needed
),
27638 T (Tag_ABI_align_preserved
),
27639 T (Tag_ABI_align8_preserved
),
27640 T (Tag_ABI_enum_size
),
27641 T (Tag_ABI_HardFP_use
),
27642 T (Tag_ABI_VFP_args
),
27643 T (Tag_ABI_WMMX_args
),
27644 T (Tag_ABI_optimization_goals
),
27645 T (Tag_ABI_FP_optimization_goals
),
27646 T (Tag_compatibility
),
27647 T (Tag_CPU_unaligned_access
),
27648 T (Tag_FP_HP_extension
),
27649 T (Tag_VFP_HP_extension
),
27650 T (Tag_ABI_FP_16bit_format
),
27651 T (Tag_MPextension_use
),
27653 T (Tag_nodefaults
),
27654 T (Tag_also_compatible_with
),
27655 T (Tag_conformance
),
27657 T (Tag_Virtualization_use
),
27658 T (Tag_DSP_extension
),
27659 /* We deliberately do not include Tag_MPextension_use_legacy. */
27667 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
27668 if (streq (name
, attribute_table
[i
].name
))
27669 return attribute_table
[i
].tag
;
27674 /* Apply sym value for relocations only in the case that they are for
27675 local symbols in the same segment as the fixup and you have the
27676 respective architectural feature for blx and simple switches. */
27679 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
27682 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27683 /* PR 17444: If the local symbol is in a different section then a reloc
27684 will always be generated for it, so applying the symbol value now
27685 will result in a double offset being stored in the relocation. */
27686 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
27687 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
27689 switch (fixP
->fx_r_type
)
27691 case BFD_RELOC_ARM_PCREL_BLX
:
27692 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
27693 if (ARM_IS_FUNC (fixP
->fx_addsy
))
27697 case BFD_RELOC_ARM_PCREL_CALL
:
27698 case BFD_RELOC_THUMB_PCREL_BLX
:
27699 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
27710 #endif /* OBJ_ELF */