1 /* tc-arm.c -- Assemble for the ARM
2 Copyright (C) 1994-2019 Free Software Foundation, Inc.
3 Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
4 Modified by David Taylor (dtaylor@armltd.co.uk)
5 Cirrus coprocessor mods by Aldy Hernandez (aldyh@redhat.com)
6 Cirrus coprocessor fixes by Petko Manolov (petkan@nucleusys.com)
7 Cirrus coprocessor fixes by Vladimir Ivanov (vladitx@nucleusys.com)
9 This file is part of GAS, the GNU Assembler.
11 GAS is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 3, or (at your option)
16 GAS is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GAS; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
30 #include "safe-ctype.h"
33 #include "libiberty.h"
34 #include "opcode/arm.h"
38 #include "dw2gencfi.h"
41 #include "dwarf2dbg.h"
44 /* Must be at least the size of the largest unwind opcode (currently two). */
45 #define ARM_OPCODE_CHUNK_SIZE 8
47 /* This structure holds the unwinding state. */
52 symbolS
* table_entry
;
53 symbolS
* personality_routine
;
54 int personality_index
;
55 /* The segment containing the function. */
58 /* Opcodes generated from this function. */
59 unsigned char * opcodes
;
62 /* The number of bytes pushed to the stack. */
64 /* We don't add stack adjustment opcodes immediately so that we can merge
65 multiple adjustments. We can also omit the final adjustment
66 when using a frame pointer. */
67 offsetT pending_offset
;
68 /* These two fields are set by both unwind_movsp and unwind_setfp. They
69 hold the reg+offset to use when restoring sp from a frame pointer. */
72 /* Nonzero if an unwind_setfp directive has been seen. */
74 /* Nonzero if the last opcode restores sp from fp_reg. */
75 unsigned sp_restored
:1;
78 /* Whether --fdpic was given. */
83 /* Results from operand parsing worker functions. */
87 PARSE_OPERAND_SUCCESS
,
89 PARSE_OPERAND_FAIL_NO_BACKTRACK
90 } parse_operand_result
;
99 /* Types of processor to assemble for. */
101 /* The code that was here used to select a default CPU depending on compiler
102 pre-defines which were only present when doing native builds, thus
103 changing gas' default behaviour depending upon the build host.
105 If you have a target that requires a default CPU option then the you
106 should define CPU_DEFAULT here. */
111 # define FPU_DEFAULT FPU_ARCH_FPA
112 # elif defined (TE_NetBSD)
114 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, but VFP order. */
116 /* Legacy a.out format. */
117 # define FPU_DEFAULT FPU_ARCH_FPA /* Soft-float, but FPA order. */
119 # elif defined (TE_VXWORKS)
120 # define FPU_DEFAULT FPU_ARCH_VFP /* Soft-float, VFP order. */
122 /* For backwards compatibility, default to FPA. */
123 # define FPU_DEFAULT FPU_ARCH_FPA
125 #endif /* ifndef FPU_DEFAULT */
127 #define streq(a, b) (strcmp (a, b) == 0)
129 /* Current set of feature bits available (CPU+FPU). Different from
130 selected_cpu + selected_fpu in case of autodetection since the CPU
131 feature bits are then all set. */
132 static arm_feature_set cpu_variant
;
133 /* Feature bits used in each execution state. Used to set build attribute
134 (in particular Tag_*_ISA_use) in CPU autodetection mode. */
135 static arm_feature_set arm_arch_used
;
136 static arm_feature_set thumb_arch_used
;
138 /* Flags stored in private area of BFD structure. */
139 static int uses_apcs_26
= FALSE
;
140 static int atpcs
= FALSE
;
141 static int support_interwork
= FALSE
;
142 static int uses_apcs_float
= FALSE
;
143 static int pic_code
= FALSE
;
144 static int fix_v4bx
= FALSE
;
145 /* Warn on using deprecated features. */
146 static int warn_on_deprecated
= TRUE
;
148 /* Understand CodeComposer Studio assembly syntax. */
149 bfd_boolean codecomposer_syntax
= FALSE
;
151 /* Variables that we set while parsing command-line options. Once all
152 options have been read we re-process these values to set the real
155 /* CPU and FPU feature bits set for legacy CPU and FPU options (eg. -marm1
156 instead of -mcpu=arm1). */
157 static const arm_feature_set
*legacy_cpu
= NULL
;
158 static const arm_feature_set
*legacy_fpu
= NULL
;
160 /* CPU, extension and FPU feature bits selected by -mcpu. */
161 static const arm_feature_set
*mcpu_cpu_opt
= NULL
;
162 static arm_feature_set
*mcpu_ext_opt
= NULL
;
163 static const arm_feature_set
*mcpu_fpu_opt
= NULL
;
165 /* CPU, extension and FPU feature bits selected by -march. */
166 static const arm_feature_set
*march_cpu_opt
= NULL
;
167 static arm_feature_set
*march_ext_opt
= NULL
;
168 static const arm_feature_set
*march_fpu_opt
= NULL
;
170 /* Feature bits selected by -mfpu. */
171 static const arm_feature_set
*mfpu_opt
= NULL
;
173 /* Constants for known architecture features. */
174 static const arm_feature_set fpu_default
= FPU_DEFAULT
;
175 static const arm_feature_set fpu_arch_vfp_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V1
;
176 static const arm_feature_set fpu_arch_vfp_v2
= FPU_ARCH_VFP_V2
;
177 static const arm_feature_set fpu_arch_vfp_v3 ATTRIBUTE_UNUSED
= FPU_ARCH_VFP_V3
;
178 static const arm_feature_set fpu_arch_neon_v1 ATTRIBUTE_UNUSED
= FPU_ARCH_NEON_V1
;
179 static const arm_feature_set fpu_arch_fpa
= FPU_ARCH_FPA
;
180 static const arm_feature_set fpu_any_hard
= FPU_ANY_HARD
;
182 static const arm_feature_set fpu_arch_maverick
= FPU_ARCH_MAVERICK
;
184 static const arm_feature_set fpu_endian_pure
= FPU_ARCH_ENDIAN_PURE
;
187 static const arm_feature_set cpu_default
= CPU_DEFAULT
;
190 static const arm_feature_set arm_ext_v1
= ARM_FEATURE_CORE_LOW (ARM_EXT_V1
);
191 static const arm_feature_set arm_ext_v2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2
);
192 static const arm_feature_set arm_ext_v2s
= ARM_FEATURE_CORE_LOW (ARM_EXT_V2S
);
193 static const arm_feature_set arm_ext_v3
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3
);
194 static const arm_feature_set arm_ext_v3m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V3M
);
195 static const arm_feature_set arm_ext_v4
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4
);
196 static const arm_feature_set arm_ext_v4t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
);
197 static const arm_feature_set arm_ext_v5
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5
);
198 static const arm_feature_set arm_ext_v4t_5
=
199 ARM_FEATURE_CORE_LOW (ARM_EXT_V4T
| ARM_EXT_V5
);
200 static const arm_feature_set arm_ext_v5t
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5T
);
201 static const arm_feature_set arm_ext_v5e
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
);
202 static const arm_feature_set arm_ext_v5exp
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
);
203 static const arm_feature_set arm_ext_v5j
= ARM_FEATURE_CORE_LOW (ARM_EXT_V5J
);
204 static const arm_feature_set arm_ext_v6
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6
);
205 static const arm_feature_set arm_ext_v6k
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
);
206 static const arm_feature_set arm_ext_v6t2
= ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2
);
207 /* Only for compatability of hint instructions. */
208 static const arm_feature_set arm_ext_v6k_v6t2
=
209 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
| ARM_EXT_V6T2
);
210 static const arm_feature_set arm_ext_v6_notm
=
211 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM
);
212 static const arm_feature_set arm_ext_v6_dsp
=
213 ARM_FEATURE_CORE_LOW (ARM_EXT_V6_DSP
);
214 static const arm_feature_set arm_ext_barrier
=
215 ARM_FEATURE_CORE_LOW (ARM_EXT_BARRIER
);
216 static const arm_feature_set arm_ext_msr
=
217 ARM_FEATURE_CORE_LOW (ARM_EXT_THUMB_MSR
);
218 static const arm_feature_set arm_ext_div
= ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
);
219 static const arm_feature_set arm_ext_v7
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7
);
220 static const arm_feature_set arm_ext_v7a
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
);
221 static const arm_feature_set arm_ext_v7r
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
);
223 static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m
= ARM_FEATURE_CORE_LOW (ARM_EXT_V7M
);
225 static const arm_feature_set arm_ext_v8
= ARM_FEATURE_CORE_LOW (ARM_EXT_V8
);
226 static const arm_feature_set arm_ext_m
=
227 ARM_FEATURE_CORE (ARM_EXT_V6M
| ARM_EXT_V7M
,
228 ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
229 static const arm_feature_set arm_ext_mp
= ARM_FEATURE_CORE_LOW (ARM_EXT_MP
);
230 static const arm_feature_set arm_ext_sec
= ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
);
231 static const arm_feature_set arm_ext_os
= ARM_FEATURE_CORE_LOW (ARM_EXT_OS
);
232 static const arm_feature_set arm_ext_adiv
= ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
);
233 static const arm_feature_set arm_ext_virt
= ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
);
234 static const arm_feature_set arm_ext_pan
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
);
235 static const arm_feature_set arm_ext_v8m
= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
);
236 static const arm_feature_set arm_ext_v8m_main
=
237 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M_MAIN
);
238 static const arm_feature_set arm_ext_v8_1m_main
=
239 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN
);
240 /* Instructions in ARMv8-M only found in M profile architectures. */
241 static const arm_feature_set arm_ext_v8m_m_only
=
242 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M
| ARM_EXT2_V8M_MAIN
);
243 static const arm_feature_set arm_ext_v6t2_v8m
=
244 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M
);
245 /* Instructions shared between ARMv8-A and ARMv8-M. */
246 static const arm_feature_set arm_ext_atomics
=
247 ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS
);
249 /* DSP instructions Tag_DSP_extension refers to. */
250 static const arm_feature_set arm_ext_dsp
=
251 ARM_FEATURE_CORE_LOW (ARM_EXT_V5E
| ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
);
253 static const arm_feature_set arm_ext_ras
=
254 ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
);
255 /* FP16 instructions. */
256 static const arm_feature_set arm_ext_fp16
=
257 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
);
258 static const arm_feature_set arm_ext_fp16_fml
=
259 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_FML
);
260 static const arm_feature_set arm_ext_v8_2
=
261 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_2A
);
262 static const arm_feature_set arm_ext_v8_3
=
263 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A
);
264 static const arm_feature_set arm_ext_sb
=
265 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
);
266 static const arm_feature_set arm_ext_predres
=
267 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
);
269 static const arm_feature_set arm_arch_any
= ARM_ANY
;
271 static const arm_feature_set fpu_any
= FPU_ANY
;
273 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED
= ARM_FEATURE (-1, -1, -1);
274 static const arm_feature_set arm_arch_t2
= ARM_ARCH_THUMB2
;
275 static const arm_feature_set arm_arch_none
= ARM_ARCH_NONE
;
277 static const arm_feature_set arm_cext_iwmmxt2
=
278 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
);
279 static const arm_feature_set arm_cext_iwmmxt
=
280 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
);
281 static const arm_feature_set arm_cext_xscale
=
282 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
);
283 static const arm_feature_set arm_cext_maverick
=
284 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
);
285 static const arm_feature_set fpu_fpa_ext_v1
=
286 ARM_FEATURE_COPROC (FPU_FPA_EXT_V1
);
287 static const arm_feature_set fpu_fpa_ext_v2
=
288 ARM_FEATURE_COPROC (FPU_FPA_EXT_V2
);
289 static const arm_feature_set fpu_vfp_ext_v1xd
=
290 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD
);
291 static const arm_feature_set fpu_vfp_ext_v1
=
292 ARM_FEATURE_COPROC (FPU_VFP_EXT_V1
);
293 static const arm_feature_set fpu_vfp_ext_v2
=
294 ARM_FEATURE_COPROC (FPU_VFP_EXT_V2
);
295 static const arm_feature_set fpu_vfp_ext_v3xd
=
296 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3xD
);
297 static const arm_feature_set fpu_vfp_ext_v3
=
298 ARM_FEATURE_COPROC (FPU_VFP_EXT_V3
);
299 static const arm_feature_set fpu_vfp_ext_d32
=
300 ARM_FEATURE_COPROC (FPU_VFP_EXT_D32
);
301 static const arm_feature_set fpu_neon_ext_v1
=
302 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
);
303 static const arm_feature_set fpu_vfp_v3_or_neon_ext
=
304 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_VFP_EXT_V3
);
305 static const arm_feature_set mve_ext
=
306 ARM_FEATURE_COPROC (FPU_MVE
);
307 static const arm_feature_set mve_fp_ext
=
308 ARM_FEATURE_COPROC (FPU_MVE_FP
);
310 static const arm_feature_set fpu_vfp_fp16
=
311 ARM_FEATURE_COPROC (FPU_VFP_EXT_FP16
);
312 static const arm_feature_set fpu_neon_ext_fma
=
313 ARM_FEATURE_COPROC (FPU_NEON_EXT_FMA
);
315 static const arm_feature_set fpu_vfp_ext_fma
=
316 ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA
);
317 static const arm_feature_set fpu_vfp_ext_armv8
=
318 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8
);
319 static const arm_feature_set fpu_vfp_ext_armv8xd
=
320 ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8xD
);
321 static const arm_feature_set fpu_neon_ext_armv8
=
322 ARM_FEATURE_COPROC (FPU_NEON_EXT_ARMV8
);
323 static const arm_feature_set fpu_crypto_ext_armv8
=
324 ARM_FEATURE_COPROC (FPU_CRYPTO_EXT_ARMV8
);
325 static const arm_feature_set crc_ext_armv8
=
326 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
);
327 static const arm_feature_set fpu_neon_ext_v8_1
=
328 ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA
);
329 static const arm_feature_set fpu_neon_ext_dotprod
=
330 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
);
332 static int mfloat_abi_opt
= -1;
333 /* Architecture feature bits selected by the last -mcpu/-march or .cpu/.arch
335 static arm_feature_set selected_arch
= ARM_ARCH_NONE
;
336 /* Extension feature bits selected by the last -mcpu/-march or .arch_extension
338 static arm_feature_set selected_ext
= ARM_ARCH_NONE
;
339 /* Feature bits selected by the last -mcpu/-march or by the combination of the
340 last .cpu/.arch directive .arch_extension directives since that
342 static arm_feature_set selected_cpu
= ARM_ARCH_NONE
;
343 /* FPU feature bits selected by the last -mfpu or .fpu directive. */
344 static arm_feature_set selected_fpu
= FPU_NONE
;
345 /* Feature bits selected by the last .object_arch directive. */
346 static arm_feature_set selected_object_arch
= ARM_ARCH_NONE
;
347 /* Must be long enough to hold any of the names in arm_cpus. */
348 static char selected_cpu_name
[20];
350 extern FLONUM_TYPE generic_floating_point_number
;
352 /* Return if no cpu was selected on command-line. */
354 no_cpu_selected (void)
356 return ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_none
);
361 static int meabi_flags
= EABI_DEFAULT
;
363 static int meabi_flags
= EF_ARM_EABI_UNKNOWN
;
366 static int attributes_set_explicitly
[NUM_KNOWN_OBJ_ATTRIBUTES
];
371 return (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
);
376 /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
377 symbolS
* GOT_symbol
;
380 /* 0: assemble for ARM,
381 1: assemble for Thumb,
382 2: assemble for Thumb even though target CPU does not support thumb
384 static int thumb_mode
= 0;
385 /* A value distinct from the possible values for thumb_mode that we
386 can use to record whether thumb_mode has been copied into the
387 tc_frag_data field of a frag. */
388 #define MODE_RECORDED (1 << 4)
390 /* Specifies the intrinsic IT insn behavior mode. */
391 enum implicit_it_mode
393 IMPLICIT_IT_MODE_NEVER
= 0x00,
394 IMPLICIT_IT_MODE_ARM
= 0x01,
395 IMPLICIT_IT_MODE_THUMB
= 0x02,
396 IMPLICIT_IT_MODE_ALWAYS
= (IMPLICIT_IT_MODE_ARM
| IMPLICIT_IT_MODE_THUMB
)
398 static int implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
400 /* If unified_syntax is true, we are processing the new unified
401 ARM/Thumb syntax. Important differences from the old ARM mode:
403 - Immediate operands do not require a # prefix.
404 - Conditional affixes always appear at the end of the
405 instruction. (For backward compatibility, those instructions
406 that formerly had them in the middle, continue to accept them
408 - The IT instruction may appear, and if it does is validated
409 against subsequent conditional affixes. It does not generate
412 Important differences from the old Thumb mode:
414 - Immediate operands do not require a # prefix.
415 - Most of the V6T2 instructions are only available in unified mode.
416 - The .N and .W suffixes are recognized and honored (it is an error
417 if they cannot be honored).
418 - All instructions set the flags if and only if they have an 's' affix.
419 - Conditional affixes may be used. They are validated against
420 preceding IT instructions. Unlike ARM mode, you cannot use a
421 conditional affix except in the scope of an IT instruction. */
423 static bfd_boolean unified_syntax
= FALSE
;
425 /* An immediate operand can start with #, and ld*, st*, pld operands
426 can contain [ and ]. We need to tell APP not to elide whitespace
427 before a [, which can appear as the first operand for pld.
428 Likewise, a { can appear as the first operand for push, pop, vld*, etc. */
429 const char arm_symbol_chars
[] = "#[]{}";
444 enum neon_el_type type
;
448 #define NEON_MAX_TYPE_ELS 4
452 struct neon_type_el el
[NEON_MAX_TYPE_ELS
];
456 enum pred_instruction_type
462 IF_INSIDE_IT_LAST_INSN
, /* Either outside or inside;
463 if inside, should be the last one. */
464 NEUTRAL_IT_INSN
, /* This could be either inside or outside,
465 i.e. BKPT and NOP. */
466 IT_INSN
, /* The IT insn has been parsed. */
467 VPT_INSN
, /* The VPT/VPST insn has been parsed. */
468 MVE_OUTSIDE_PRED_INSN
, /* Instruction to indicate a MVE instruction without
469 a predication code. */
470 MVE_UNPREDICABLE_INSN
/* MVE instruction that is non-predicable. */
473 /* The maximum number of operands we need. */
474 #define ARM_IT_MAX_OPERANDS 6
475 #define ARM_IT_MAX_RELOCS 3
480 unsigned long instruction
;
484 /* "uncond_value" is set to the value in place of the conditional field in
485 unconditional versions of the instruction, or -1 if nothing is
488 struct neon_type vectype
;
489 /* This does not indicate an actual NEON instruction, only that
490 the mnemonic accepts neon-style type suffixes. */
492 /* Set to the opcode if the instruction needs relaxation.
493 Zero if the instruction is not relaxed. */
497 bfd_reloc_code_real_type type
;
500 } relocs
[ARM_IT_MAX_RELOCS
];
502 enum pred_instruction_type pred_insn_type
;
508 struct neon_type_el vectype
;
509 unsigned present
: 1; /* Operand present. */
510 unsigned isreg
: 1; /* Operand was a register. */
511 unsigned immisreg
: 2; /* .imm field is a second register.
512 0: imm, 1: gpr, 2: MVE Q-register. */
513 unsigned isscalar
: 2; /* Operand is a (SIMD) scalar:
517 unsigned immisalign
: 1; /* Immediate is an alignment specifier. */
518 unsigned immisfloat
: 1; /* Immediate was parsed as a float. */
519 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
520 instructions. This allows us to disambiguate ARM <-> vector insns. */
521 unsigned regisimm
: 1; /* 64-bit immediate, reg forms high 32 bits. */
522 unsigned isvec
: 1; /* Is a single, double or quad VFP/Neon reg. */
523 unsigned isquad
: 1; /* Operand is SIMD quad register. */
524 unsigned issingle
: 1; /* Operand is VFP single-precision register. */
525 unsigned iszr
: 1; /* Operand is ZR register. */
526 unsigned hasreloc
: 1; /* Operand has relocation suffix. */
527 unsigned writeback
: 1; /* Operand has trailing ! */
528 unsigned preind
: 1; /* Preindexed address. */
529 unsigned postind
: 1; /* Postindexed address. */
530 unsigned negative
: 1; /* Index register was negated. */
531 unsigned shifted
: 1; /* Shift applied to operation. */
532 unsigned shift_kind
: 3; /* Shift operation (enum shift_kind). */
533 } operands
[ARM_IT_MAX_OPERANDS
];
536 static struct arm_it inst
;
538 #define NUM_FLOAT_VALS 8
540 const char * fp_const
[] =
542 "0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0", 0
545 LITTLENUM_TYPE fp_values
[NUM_FLOAT_VALS
][MAX_LITTLENUMS
];
555 #define CP_T_X 0x00008000
556 #define CP_T_Y 0x00400000
558 #define CONDS_BIT 0x00100000
559 #define LOAD_BIT 0x00100000
561 #define DOUBLE_LOAD_FLAG 0x00000001
565 const char * template_name
;
569 #define COND_ALWAYS 0xE
573 const char * template_name
;
577 struct asm_barrier_opt
579 const char * template_name
;
581 const arm_feature_set arch
;
584 /* The bit that distinguishes CPSR and SPSR. */
585 #define SPSR_BIT (1 << 22)
587 /* The individual PSR flag bits. */
588 #define PSR_c (1 << 16)
589 #define PSR_x (1 << 17)
590 #define PSR_s (1 << 18)
591 #define PSR_f (1 << 19)
596 bfd_reloc_code_real_type reloc
;
601 VFP_REG_Sd
, VFP_REG_Sm
, VFP_REG_Sn
,
602 VFP_REG_Dd
, VFP_REG_Dm
, VFP_REG_Dn
607 VFP_LDSTMIA
, VFP_LDSTMDB
, VFP_LDSTMIAX
, VFP_LDSTMDBX
610 /* Bits for DEFINED field in neon_typed_alias. */
611 #define NTA_HASTYPE 1
612 #define NTA_HASINDEX 2
614 struct neon_typed_alias
616 unsigned char defined
;
618 struct neon_type_el eltype
;
621 /* ARM register categories. This includes coprocessor numbers and various
622 architecture extensions' registers. Each entry should have an error message
623 in reg_expected_msgs below. */
653 /* Structure for a hash table entry for a register.
654 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
655 information which states whether a vector type or index is specified (for a
656 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
662 unsigned char builtin
;
663 struct neon_typed_alias
* neon
;
666 /* Diagnostics used when we don't get a register of the expected type. */
667 const char * const reg_expected_msgs
[] =
669 [REG_TYPE_RN
] = N_("ARM register expected"),
670 [REG_TYPE_CP
] = N_("bad or missing co-processor number"),
671 [REG_TYPE_CN
] = N_("co-processor register expected"),
672 [REG_TYPE_FN
] = N_("FPA register expected"),
673 [REG_TYPE_VFS
] = N_("VFP single precision register expected"),
674 [REG_TYPE_VFD
] = N_("VFP/Neon double precision register expected"),
675 [REG_TYPE_NQ
] = N_("Neon quad precision register expected"),
676 [REG_TYPE_VFSD
] = N_("VFP single or double precision register expected"),
677 [REG_TYPE_NDQ
] = N_("Neon double or quad precision register expected"),
678 [REG_TYPE_NSD
] = N_("Neon single or double precision register expected"),
679 [REG_TYPE_NSDQ
] = N_("VFP single, double or Neon quad precision register"
681 [REG_TYPE_VFC
] = N_("VFP system register expected"),
682 [REG_TYPE_MVF
] = N_("Maverick MVF register expected"),
683 [REG_TYPE_MVD
] = N_("Maverick MVD register expected"),
684 [REG_TYPE_MVFX
] = N_("Maverick MVFX register expected"),
685 [REG_TYPE_MVDX
] = N_("Maverick MVDX register expected"),
686 [REG_TYPE_MVAX
] = N_("Maverick MVAX register expected"),
687 [REG_TYPE_DSPSC
] = N_("Maverick DSPSC register expected"),
688 [REG_TYPE_MMXWR
] = N_("iWMMXt data register expected"),
689 [REG_TYPE_MMXWC
] = N_("iWMMXt control register expected"),
690 [REG_TYPE_MMXWCG
] = N_("iWMMXt scalar register expected"),
691 [REG_TYPE_XSCALE
] = N_("XScale accumulator register expected"),
692 [REG_TYPE_MQ
] = N_("MVE vector register expected"),
693 [REG_TYPE_RNB
] = N_("")
696 /* Some well known registers that we refer to directly elsewhere. */
702 /* ARM instructions take 4bytes in the object file, Thumb instructions
708 /* Basic string to match. */
709 const char * template_name
;
711 /* Parameters to instruction. */
712 unsigned int operands
[8];
714 /* Conditional tag - see opcode_lookup. */
715 unsigned int tag
: 4;
717 /* Basic instruction code. */
720 /* Thumb-format instruction code. */
723 /* Which architecture variant provides this instruction. */
724 const arm_feature_set
* avariant
;
725 const arm_feature_set
* tvariant
;
727 /* Function to call to encode instruction in ARM format. */
728 void (* aencode
) (void);
730 /* Function to call to encode instruction in Thumb format. */
731 void (* tencode
) (void);
733 /* Indicates whether this instruction may be vector predicated. */
734 unsigned int mayBeVecPred
: 1;
737 /* Defines for various bits that we will want to toggle. */
738 #define INST_IMMEDIATE 0x02000000
739 #define OFFSET_REG 0x02000000
740 #define HWOFFSET_IMM 0x00400000
741 #define SHIFT_BY_REG 0x00000010
742 #define PRE_INDEX 0x01000000
743 #define INDEX_UP 0x00800000
744 #define WRITE_BACK 0x00200000
745 #define LDM_TYPE_2_OR_3 0x00400000
746 #define CPSI_MMOD 0x00020000
748 #define LITERAL_MASK 0xf000f000
749 #define OPCODE_MASK 0xfe1fffff
750 #define V4_STR_BIT 0x00000020
751 #define VLDR_VMOV_SAME 0x0040f000
753 #define T2_SUBS_PC_LR 0xf3de8f00
755 #define DATA_OP_SHIFT 21
756 #define SBIT_SHIFT 20
758 #define T2_OPCODE_MASK 0xfe1fffff
759 #define T2_DATA_OP_SHIFT 21
760 #define T2_SBIT_SHIFT 20
762 #define A_COND_MASK 0xf0000000
763 #define A_PUSH_POP_OP_MASK 0x0fff0000
765 /* Opcodes for pushing/poping registers to/from the stack. */
766 #define A1_OPCODE_PUSH 0x092d0000
767 #define A2_OPCODE_PUSH 0x052d0004
768 #define A2_OPCODE_POP 0x049d0004
770 /* Codes to distinguish the arithmetic instructions. */
781 #define OPCODE_CMP 10
782 #define OPCODE_CMN 11
783 #define OPCODE_ORR 12
784 #define OPCODE_MOV 13
785 #define OPCODE_BIC 14
786 #define OPCODE_MVN 15
788 #define T2_OPCODE_AND 0
789 #define T2_OPCODE_BIC 1
790 #define T2_OPCODE_ORR 2
791 #define T2_OPCODE_ORN 3
792 #define T2_OPCODE_EOR 4
793 #define T2_OPCODE_ADD 8
794 #define T2_OPCODE_ADC 10
795 #define T2_OPCODE_SBC 11
796 #define T2_OPCODE_SUB 13
797 #define T2_OPCODE_RSB 14
799 #define T_OPCODE_MUL 0x4340
800 #define T_OPCODE_TST 0x4200
801 #define T_OPCODE_CMN 0x42c0
802 #define T_OPCODE_NEG 0x4240
803 #define T_OPCODE_MVN 0x43c0
805 #define T_OPCODE_ADD_R3 0x1800
806 #define T_OPCODE_SUB_R3 0x1a00
807 #define T_OPCODE_ADD_HI 0x4400
808 #define T_OPCODE_ADD_ST 0xb000
809 #define T_OPCODE_SUB_ST 0xb080
810 #define T_OPCODE_ADD_SP 0xa800
811 #define T_OPCODE_ADD_PC 0xa000
812 #define T_OPCODE_ADD_I8 0x3000
813 #define T_OPCODE_SUB_I8 0x3800
814 #define T_OPCODE_ADD_I3 0x1c00
815 #define T_OPCODE_SUB_I3 0x1e00
817 #define T_OPCODE_ASR_R 0x4100
818 #define T_OPCODE_LSL_R 0x4080
819 #define T_OPCODE_LSR_R 0x40c0
820 #define T_OPCODE_ROR_R 0x41c0
821 #define T_OPCODE_ASR_I 0x1000
822 #define T_OPCODE_LSL_I 0x0000
823 #define T_OPCODE_LSR_I 0x0800
825 #define T_OPCODE_MOV_I8 0x2000
826 #define T_OPCODE_CMP_I8 0x2800
827 #define T_OPCODE_CMP_LR 0x4280
828 #define T_OPCODE_MOV_HR 0x4600
829 #define T_OPCODE_CMP_HR 0x4500
831 #define T_OPCODE_LDR_PC 0x4800
832 #define T_OPCODE_LDR_SP 0x9800
833 #define T_OPCODE_STR_SP 0x9000
834 #define T_OPCODE_LDR_IW 0x6800
835 #define T_OPCODE_STR_IW 0x6000
836 #define T_OPCODE_LDR_IH 0x8800
837 #define T_OPCODE_STR_IH 0x8000
838 #define T_OPCODE_LDR_IB 0x7800
839 #define T_OPCODE_STR_IB 0x7000
840 #define T_OPCODE_LDR_RW 0x5800
841 #define T_OPCODE_STR_RW 0x5000
842 #define T_OPCODE_LDR_RH 0x5a00
843 #define T_OPCODE_STR_RH 0x5200
844 #define T_OPCODE_LDR_RB 0x5c00
845 #define T_OPCODE_STR_RB 0x5400
847 #define T_OPCODE_PUSH 0xb400
848 #define T_OPCODE_POP 0xbc00
850 #define T_OPCODE_BRANCH 0xe000
852 #define THUMB_SIZE 2 /* Size of thumb instruction. */
853 #define THUMB_PP_PC_LR 0x0100
854 #define THUMB_LOAD_BIT 0x0800
855 #define THUMB2_LOAD_BIT 0x00100000
857 #define BAD_SYNTAX _("syntax error")
858 #define BAD_ARGS _("bad arguments to instruction")
859 #define BAD_SP _("r13 not allowed here")
860 #define BAD_PC _("r15 not allowed here")
861 #define BAD_ODD _("Odd register not allowed here")
862 #define BAD_EVEN _("Even register not allowed here")
863 #define BAD_COND _("instruction cannot be conditional")
864 #define BAD_OVERLAP _("registers may not be the same")
865 #define BAD_HIREG _("lo register required")
866 #define BAD_THUMB32 _("instruction not supported in Thumb16 mode")
867 #define BAD_ADDR_MODE _("instruction does not accept this addressing mode")
868 #define BAD_BRANCH _("branch must be last instruction in IT block")
869 #define BAD_BRANCH_OFF _("branch out of range or not a multiple of 2")
870 #define BAD_NOT_IT _("instruction not allowed in IT block")
871 #define BAD_NOT_VPT _("instruction missing MVE vector predication code")
872 #define BAD_FPU _("selected FPU does not support instruction")
873 #define BAD_OUT_IT _("thumb conditional instruction should be in IT block")
874 #define BAD_OUT_VPT \
875 _("vector predicated instruction should be in VPT/VPST block")
876 #define BAD_IT_COND _("incorrect condition in IT block")
877 #define BAD_VPT_COND _("incorrect condition in VPT/VPST block")
878 #define BAD_IT_IT _("IT falling in the range of a previous IT block")
879 #define MISSING_FNSTART _("missing .fnstart before unwinding directive")
880 #define BAD_PC_ADDRESSING \
881 _("cannot use register index with PC-relative addressing")
882 #define BAD_PC_WRITEBACK \
883 _("cannot use writeback with PC-relative addressing")
884 #define BAD_RANGE _("branch out of range")
885 #define BAD_FP16 _("selected processor does not support fp16 instruction")
886 #define UNPRED_REG(R) _("using " R " results in unpredictable behaviour")
887 #define THUMB1_RELOC_ONLY _("relocation valid in thumb1 code only")
888 #define MVE_NOT_IT _("Warning: instruction is UNPREDICTABLE in an IT " \
890 #define MVE_NOT_VPT _("Warning: instruction is UNPREDICTABLE in a VPT " \
892 #define MVE_BAD_PC _("Warning: instruction is UNPREDICTABLE with PC" \
894 #define MVE_BAD_SP _("Warning: instruction is UNPREDICTABLE with SP" \
896 #define BAD_SIMD_TYPE _("bad type in SIMD instruction")
897 #define BAD_MVE_AUTO \
898 _("GAS auto-detection mode and -march=all is deprecated for MVE, please" \
899 " use a valid -march or -mcpu option.")
900 #define BAD_MVE_SRCDEST _("Warning: 32-bit element size and same destination "\
901 "and source operands makes instruction UNPREDICTABLE")
902 #define BAD_EL_TYPE _("bad element type for instruction")
903 #define MVE_BAD_QREG _("MVE vector register Q[0..7] expected")
905 static struct hash_control
* arm_ops_hsh
;
906 static struct hash_control
* arm_cond_hsh
;
907 static struct hash_control
* arm_vcond_hsh
;
908 static struct hash_control
* arm_shift_hsh
;
909 static struct hash_control
* arm_psr_hsh
;
910 static struct hash_control
* arm_v7m_psr_hsh
;
911 static struct hash_control
* arm_reg_hsh
;
912 static struct hash_control
* arm_reloc_hsh
;
913 static struct hash_control
* arm_barrier_opt_hsh
;
915 /* Stuff needed to resolve the label ambiguity
924 symbolS
* last_label_seen
;
925 static int label_is_thumb_function_name
= FALSE
;
927 /* Literal pool structure. Held on a per-section
928 and per-sub-section basis. */
930 #define MAX_LITERAL_POOL_SIZE 1024
931 typedef struct literal_pool
933 expressionS literals
[MAX_LITERAL_POOL_SIZE
];
934 unsigned int next_free_entry
;
940 struct dwarf2_line_info locs
[MAX_LITERAL_POOL_SIZE
];
942 struct literal_pool
* next
;
943 unsigned int alignment
;
946 /* Pointer to a linked list of literal pools. */
947 literal_pool
* list_of_pools
= NULL
;
949 typedef enum asmfunc_states
952 WAITING_ASMFUNC_NAME
,
956 static asmfunc_states asmfunc_state
= OUTSIDE_ASMFUNC
;
959 # define now_pred seg_info (now_seg)->tc_segment_info_data.current_pred
961 static struct current_pred now_pred
;
965 now_pred_compatible (int cond
)
967 return (cond
& ~1) == (now_pred
.cc
& ~1);
971 conditional_insn (void)
973 return inst
.cond
!= COND_ALWAYS
;
976 static int in_pred_block (void);
978 static int handle_pred_state (void);
980 static void force_automatic_it_block_close (void);
982 static void it_fsm_post_encode (void);
984 #define set_pred_insn_type(type) \
987 inst.pred_insn_type = type; \
988 if (handle_pred_state () == FAIL) \
993 #define set_pred_insn_type_nonvoid(type, failret) \
996 inst.pred_insn_type = type; \
997 if (handle_pred_state () == FAIL) \
1002 #define set_pred_insn_type_last() \
1005 if (inst.cond == COND_ALWAYS) \
1006 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN); \
1008 set_pred_insn_type (INSIDE_IT_LAST_INSN); \
1012 /* Toggle value[pos]. */
1013 #define TOGGLE_BIT(value, pos) (value ^ (1 << pos))
1017 /* This array holds the chars that always start a comment. If the
1018 pre-processor is disabled, these aren't very useful. */
1019 char arm_comment_chars
[] = "@";
1021 /* This array holds the chars that only start a comment at the beginning of
1022 a line. If the line seems to have the form '# 123 filename'
1023 .line and .file directives will appear in the pre-processed output. */
1024 /* Note that input_file.c hand checks for '#' at the beginning of the
1025 first line of the input file. This is because the compiler outputs
1026 #NO_APP at the beginning of its output. */
1027 /* Also note that comments like this one will always work. */
1028 const char line_comment_chars
[] = "#";
1030 char arm_line_separator_chars
[] = ";";
1032 /* Chars that can be used to separate mant
1033 from exp in floating point numbers. */
1034 const char EXP_CHARS
[] = "eE";
1036 /* Chars that mean this number is a floating point constant. */
1037 /* As in 0f12.456 */
1038 /* or 0d1.2345e12 */
1040 const char FLT_CHARS
[] = "rRsSfFdDxXeEpPHh";
1042 /* Prefix characters that indicate the start of an immediate
1044 #define is_immediate_prefix(C) ((C) == '#' || (C) == '$')
1046 /* Separator character handling. */
1048 #define skip_whitespace(str) do { if (*(str) == ' ') ++(str); } while (0)
1050 enum fp_16bit_format
1052 ARM_FP16_FORMAT_IEEE
= 0x1,
1053 ARM_FP16_FORMAT_ALTERNATIVE
= 0x2,
1054 ARM_FP16_FORMAT_DEFAULT
= 0x3
1057 static enum fp_16bit_format fp16_format
= ARM_FP16_FORMAT_DEFAULT
;
1061 skip_past_char (char ** str
, char c
)
1063 /* PR gas/14987: Allow for whitespace before the expected character. */
1064 skip_whitespace (*str
);
1075 #define skip_past_comma(str) skip_past_char (str, ',')
1077 /* Arithmetic expressions (possibly involving symbols). */
1079 /* Return TRUE if anything in the expression is a bignum. */
1082 walk_no_bignums (symbolS
* sp
)
1084 if (symbol_get_value_expression (sp
)->X_op
== O_big
)
1087 if (symbol_get_value_expression (sp
)->X_add_symbol
)
1089 return (walk_no_bignums (symbol_get_value_expression (sp
)->X_add_symbol
)
1090 || (symbol_get_value_expression (sp
)->X_op_symbol
1091 && walk_no_bignums (symbol_get_value_expression (sp
)->X_op_symbol
)));
1097 static bfd_boolean in_my_get_expression
= FALSE
;
1099 /* Third argument to my_get_expression. */
1100 #define GE_NO_PREFIX 0
1101 #define GE_IMM_PREFIX 1
1102 #define GE_OPT_PREFIX 2
1103 /* This is a bit of a hack. Use an optional prefix, and also allow big (64-bit)
1104 immediates, as can be used in Neon VMVN and VMOV immediate instructions. */
1105 #define GE_OPT_PREFIX_BIG 3
1108 my_get_expression (expressionS
* ep
, char ** str
, int prefix_mode
)
1112 /* In unified syntax, all prefixes are optional. */
1114 prefix_mode
= (prefix_mode
== GE_OPT_PREFIX_BIG
) ? prefix_mode
1117 switch (prefix_mode
)
1119 case GE_NO_PREFIX
: break;
1121 if (!is_immediate_prefix (**str
))
1123 inst
.error
= _("immediate expression requires a # prefix");
1129 case GE_OPT_PREFIX_BIG
:
1130 if (is_immediate_prefix (**str
))
1137 memset (ep
, 0, sizeof (expressionS
));
1139 save_in
= input_line_pointer
;
1140 input_line_pointer
= *str
;
1141 in_my_get_expression
= TRUE
;
1143 in_my_get_expression
= FALSE
;
1145 if (ep
->X_op
== O_illegal
|| ep
->X_op
== O_absent
)
1147 /* We found a bad or missing expression in md_operand(). */
1148 *str
= input_line_pointer
;
1149 input_line_pointer
= save_in
;
1150 if (inst
.error
== NULL
)
1151 inst
.error
= (ep
->X_op
== O_absent
1152 ? _("missing expression") :_("bad expression"));
1156 /* Get rid of any bignums now, so that we don't generate an error for which
1157 we can't establish a line number later on. Big numbers are never valid
1158 in instructions, which is where this routine is always called. */
1159 if (prefix_mode
!= GE_OPT_PREFIX_BIG
1160 && (ep
->X_op
== O_big
1161 || (ep
->X_add_symbol
1162 && (walk_no_bignums (ep
->X_add_symbol
)
1164 && walk_no_bignums (ep
->X_op_symbol
))))))
1166 inst
.error
= _("invalid constant");
1167 *str
= input_line_pointer
;
1168 input_line_pointer
= save_in
;
1172 *str
= input_line_pointer
;
1173 input_line_pointer
= save_in
;
1177 /* Turn a string in input_line_pointer into a floating point constant
1178 of type TYPE, and store the appropriate bytes in *LITP. The number
1179 of LITTLENUMS emitted is stored in *SIZEP. An error message is
1180 returned, or NULL on OK.
1182 Note that fp constants aren't represent in the normal way on the ARM.
1183 In big endian mode, things are as expected. However, in little endian
1184 mode fp constants are big-endian word-wise, and little-endian byte-wise
1185 within the words. For example, (double) 1.1 in big endian mode is
1186 the byte sequence 3f f1 99 99 99 99 99 9a, and in little endian mode is
1187 the byte sequence 99 99 f1 3f 9a 99 99 99.
1189 ??? The format of 12 byte floats is uncertain according to gcc's arm.h. */
1192 md_atof (int type
, char * litP
, int * sizeP
)
1195 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
1232 return _("Unrecognized or unsupported floating point constant");
1235 t
= atof_ieee (input_line_pointer
, type
, words
);
1237 input_line_pointer
= t
;
1238 *sizeP
= prec
* sizeof (LITTLENUM_TYPE
);
1240 if (target_big_endian
)
1242 for (i
= 0; i
< prec
; i
++)
1244 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1245 litP
+= sizeof (LITTLENUM_TYPE
);
1250 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
1251 for (i
= prec
- 1; i
>= 0; i
--)
1253 md_number_to_chars (litP
, (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1254 litP
+= sizeof (LITTLENUM_TYPE
);
1257 /* For a 4 byte float the order of elements in `words' is 1 0.
1258 For an 8 byte float the order is 1 0 3 2. */
1259 for (i
= 0; i
< prec
; i
+= 2)
1261 md_number_to_chars (litP
, (valueT
) words
[i
+ 1],
1262 sizeof (LITTLENUM_TYPE
));
1263 md_number_to_chars (litP
+ sizeof (LITTLENUM_TYPE
),
1264 (valueT
) words
[i
], sizeof (LITTLENUM_TYPE
));
1265 litP
+= 2 * sizeof (LITTLENUM_TYPE
);
1272 /* We handle all bad expressions here, so that we can report the faulty
1273 instruction in the error message. */
1276 md_operand (expressionS
* exp
)
1278 if (in_my_get_expression
)
1279 exp
->X_op
= O_illegal
;
1282 /* Immediate values. */
1285 /* Generic immediate-value read function for use in directives.
1286 Accepts anything that 'expression' can fold to a constant.
1287 *val receives the number. */
1290 immediate_for_directive (int *val
)
1293 exp
.X_op
= O_illegal
;
1295 if (is_immediate_prefix (*input_line_pointer
))
1297 input_line_pointer
++;
1301 if (exp
.X_op
!= O_constant
)
1303 as_bad (_("expected #constant"));
1304 ignore_rest_of_line ();
1307 *val
= exp
.X_add_number
;
1312 /* Register parsing. */
1314 /* Generic register parser. CCP points to what should be the
1315 beginning of a register name. If it is indeed a valid register
1316 name, advance CCP over it and return the reg_entry structure;
1317 otherwise return NULL. Does not issue diagnostics. */
1319 static struct reg_entry
*
1320 arm_reg_parse_multi (char **ccp
)
1324 struct reg_entry
*reg
;
1326 skip_whitespace (start
);
1328 #ifdef REGISTER_PREFIX
1329 if (*start
!= REGISTER_PREFIX
)
1333 #ifdef OPTIONAL_REGISTER_PREFIX
1334 if (*start
== OPTIONAL_REGISTER_PREFIX
)
1339 if (!ISALPHA (*p
) || !is_name_beginner (*p
))
1344 while (ISALPHA (*p
) || ISDIGIT (*p
) || *p
== '_');
1346 reg
= (struct reg_entry
*) hash_find_n (arm_reg_hsh
, start
, p
- start
);
1356 arm_reg_alt_syntax (char **ccp
, char *start
, struct reg_entry
*reg
,
1357 enum arm_reg_type type
)
1359 /* Alternative syntaxes are accepted for a few register classes. */
1366 /* Generic coprocessor register names are allowed for these. */
1367 if (reg
&& reg
->type
== REG_TYPE_CN
)
1372 /* For backward compatibility, a bare number is valid here. */
1374 unsigned long processor
= strtoul (start
, ccp
, 10);
1375 if (*ccp
!= start
&& processor
<= 15)
1380 case REG_TYPE_MMXWC
:
1381 /* WC includes WCG. ??? I'm not sure this is true for all
1382 instructions that take WC registers. */
1383 if (reg
&& reg
->type
== REG_TYPE_MMXWCG
)
1394 /* As arm_reg_parse_multi, but the register must be of type TYPE, and the
1395 return value is the register number or FAIL. */
1398 arm_reg_parse (char **ccp
, enum arm_reg_type type
)
1401 struct reg_entry
*reg
= arm_reg_parse_multi (ccp
);
1404 /* Do not allow a scalar (reg+index) to parse as a register. */
1405 if (reg
&& reg
->neon
&& (reg
->neon
->defined
& NTA_HASINDEX
))
1408 if (reg
&& reg
->type
== type
)
1411 if ((ret
= arm_reg_alt_syntax (ccp
, start
, reg
, type
)) != FAIL
)
1418 /* Parse a Neon type specifier. *STR should point at the leading '.'
1419 character. Does no verification at this stage that the type fits the opcode
1426 Can all be legally parsed by this function.
1428 Fills in neon_type struct pointer with parsed information, and updates STR
1429 to point after the parsed type specifier. Returns SUCCESS if this was a legal
1430 type, FAIL if not. */
1433 parse_neon_type (struct neon_type
*type
, char **str
)
1440 while (type
->elems
< NEON_MAX_TYPE_ELS
)
1442 enum neon_el_type thistype
= NT_untyped
;
1443 unsigned thissize
= -1u;
1450 /* Just a size without an explicit type. */
1454 switch (TOLOWER (*ptr
))
1456 case 'i': thistype
= NT_integer
; break;
1457 case 'f': thistype
= NT_float
; break;
1458 case 'p': thistype
= NT_poly
; break;
1459 case 's': thistype
= NT_signed
; break;
1460 case 'u': thistype
= NT_unsigned
; break;
1462 thistype
= NT_float
;
1467 as_bad (_("unexpected character `%c' in type specifier"), *ptr
);
1473 /* .f is an abbreviation for .f32. */
1474 if (thistype
== NT_float
&& !ISDIGIT (*ptr
))
1479 thissize
= strtoul (ptr
, &ptr
, 10);
1481 if (thissize
!= 8 && thissize
!= 16 && thissize
!= 32
1484 as_bad (_("bad size %d in type specifier"), thissize
);
1492 type
->el
[type
->elems
].type
= thistype
;
1493 type
->el
[type
->elems
].size
= thissize
;
1498 /* Empty/missing type is not a successful parse. */
1499 if (type
->elems
== 0)
1507 /* Errors may be set multiple times during parsing or bit encoding
1508 (particularly in the Neon bits), but usually the earliest error which is set
1509 will be the most meaningful. Avoid overwriting it with later (cascading)
1510 errors by calling this function. */
1513 first_error (const char *err
)
1519 /* Parse a single type, e.g. ".s32", leading period included. */
1521 parse_neon_operand_type (struct neon_type_el
*vectype
, char **ccp
)
1524 struct neon_type optype
;
1528 if (parse_neon_type (&optype
, &str
) == SUCCESS
)
1530 if (optype
.elems
== 1)
1531 *vectype
= optype
.el
[0];
1534 first_error (_("only one type should be specified for operand"));
1540 first_error (_("vector type expected"));
1552 /* Special meanings for indices (which have a range of 0-7), which will fit into
1555 #define NEON_ALL_LANES 15
1556 #define NEON_INTERLEAVE_LANES 14
1558 /* Record a use of the given feature. */
1560 record_feature_use (const arm_feature_set
*feature
)
1563 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
, *feature
);
1565 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, *feature
);
1568 /* If the given feature available in the selected CPU, mark it as used.
1569 Returns TRUE iff feature is available. */
1571 mark_feature_used (const arm_feature_set
*feature
)
1574 /* Do not support the use of MVE only instructions when in auto-detection or
1576 if (((feature
== &mve_ext
) || (feature
== &mve_fp_ext
))
1577 && ARM_CPU_IS_ANY (cpu_variant
))
1579 first_error (BAD_MVE_AUTO
);
1582 /* Ensure the option is valid on the current architecture. */
1583 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
1586 /* Add the appropriate architecture feature for the barrier option used.
1588 record_feature_use (feature
);
1593 /* Parse either a register or a scalar, with an optional type. Return the
1594 register number, and optionally fill in the actual type of the register
1595 when multiple alternatives were given (NEON_TYPE_NDQ) in *RTYPE, and
1596 type/index information in *TYPEINFO. */
1599 parse_typed_reg_or_scalar (char **ccp
, enum arm_reg_type type
,
1600 enum arm_reg_type
*rtype
,
1601 struct neon_typed_alias
*typeinfo
)
1604 struct reg_entry
*reg
= arm_reg_parse_multi (&str
);
1605 struct neon_typed_alias atype
;
1606 struct neon_type_el parsetype
;
1610 atype
.eltype
.type
= NT_invtype
;
1611 atype
.eltype
.size
= -1;
1613 /* Try alternate syntax for some types of register. Note these are mutually
1614 exclusive with the Neon syntax extensions. */
1617 int altreg
= arm_reg_alt_syntax (&str
, *ccp
, reg
, type
);
1625 /* Undo polymorphism when a set of register types may be accepted. */
1626 if ((type
== REG_TYPE_NDQ
1627 && (reg
->type
== REG_TYPE_NQ
|| reg
->type
== REG_TYPE_VFD
))
1628 || (type
== REG_TYPE_VFSD
1629 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1630 || (type
== REG_TYPE_NSDQ
1631 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
1632 || reg
->type
== REG_TYPE_NQ
))
1633 || (type
== REG_TYPE_NSD
1634 && (reg
->type
== REG_TYPE_VFS
|| reg
->type
== REG_TYPE_VFD
))
1635 || (type
== REG_TYPE_MMXWC
1636 && (reg
->type
== REG_TYPE_MMXWCG
)))
1637 type
= (enum arm_reg_type
) reg
->type
;
1639 if (type
== REG_TYPE_MQ
)
1641 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1644 if (!reg
|| reg
->type
!= REG_TYPE_NQ
)
1647 if (reg
->number
> 14 && !mark_feature_used (&fpu_vfp_ext_d32
))
1649 first_error (_("expected MVE register [q0..q7]"));
1654 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
1655 && (type
== REG_TYPE_NQ
))
1659 if (type
!= reg
->type
)
1665 if (parse_neon_operand_type (&parsetype
, &str
) == SUCCESS
)
1667 if ((atype
.defined
& NTA_HASTYPE
) != 0)
1669 first_error (_("can't redefine type for operand"));
1672 atype
.defined
|= NTA_HASTYPE
;
1673 atype
.eltype
= parsetype
;
1676 if (skip_past_char (&str
, '[') == SUCCESS
)
1678 if (type
!= REG_TYPE_VFD
1679 && !(type
== REG_TYPE_VFS
1680 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_2
))
1681 && !(type
== REG_TYPE_NQ
1682 && ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)))
1684 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
1685 first_error (_("only D and Q registers may be indexed"));
1687 first_error (_("only D registers may be indexed"));
1691 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1693 first_error (_("can't change index for operand"));
1697 atype
.defined
|= NTA_HASINDEX
;
1699 if (skip_past_char (&str
, ']') == SUCCESS
)
1700 atype
.index
= NEON_ALL_LANES
;
1705 my_get_expression (&exp
, &str
, GE_NO_PREFIX
);
1707 if (exp
.X_op
!= O_constant
)
1709 first_error (_("constant expression required"));
1713 if (skip_past_char (&str
, ']') == FAIL
)
1716 atype
.index
= exp
.X_add_number
;
1731 /* Like arm_reg_parse, but also allow the following extra features:
1732 - If RTYPE is non-zero, return the (possibly restricted) type of the
1733 register (e.g. Neon double or quad reg when either has been requested).
1734 - If this is a Neon vector type with additional type information, fill
1735 in the struct pointed to by VECTYPE (if non-NULL).
1736 This function will fault on encountering a scalar. */
1739 arm_typed_reg_parse (char **ccp
, enum arm_reg_type type
,
1740 enum arm_reg_type
*rtype
, struct neon_type_el
*vectype
)
1742 struct neon_typed_alias atype
;
1744 int reg
= parse_typed_reg_or_scalar (&str
, type
, rtype
, &atype
);
1749 /* Do not allow regname(... to parse as a register. */
1753 /* Do not allow a scalar (reg+index) to parse as a register. */
1754 if ((atype
.defined
& NTA_HASINDEX
) != 0)
1756 first_error (_("register operand expected, but got scalar"));
1761 *vectype
= atype
.eltype
;
1768 #define NEON_SCALAR_REG(X) ((X) >> 4)
1769 #define NEON_SCALAR_INDEX(X) ((X) & 15)
1771 /* Parse a Neon scalar. Most of the time when we're parsing a scalar, we don't
1772 have enough information to be able to do a good job bounds-checking. So, we
1773 just do easy checks here, and do further checks later. */
1776 parse_scalar (char **ccp
, int elsize
, struct neon_type_el
*type
, enum
1777 arm_reg_type reg_type
)
1781 struct neon_typed_alias atype
;
1784 reg
= parse_typed_reg_or_scalar (&str
, reg_type
, NULL
, &atype
);
1802 if (reg
== FAIL
|| (atype
.defined
& NTA_HASINDEX
) == 0)
1805 if (reg_type
!= REG_TYPE_MQ
&& atype
.index
== NEON_ALL_LANES
)
1807 first_error (_("scalar must have an index"));
1810 else if (atype
.index
>= reg_size
/ elsize
)
1812 first_error (_("scalar index out of range"));
1817 *type
= atype
.eltype
;
1821 return reg
* 16 + atype
.index
;
1824 /* Types of registers in a list. */
1837 /* Parse an ARM register list. Returns the bitmask, or FAIL. */
1840 parse_reg_list (char ** strp
, enum reg_list_els etype
)
1846 gas_assert (etype
== REGLIST_RN
|| etype
== REGLIST_CLRM
);
1848 /* We come back here if we get ranges concatenated by '+' or '|'. */
1851 skip_whitespace (str
);
1864 const char apsr_str
[] = "apsr";
1865 int apsr_str_len
= strlen (apsr_str
);
1867 reg
= arm_reg_parse (&str
, REGLIST_RN
);
1868 if (etype
== REGLIST_CLRM
)
1870 if (reg
== REG_SP
|| reg
== REG_PC
)
1872 else if (reg
== FAIL
1873 && !strncasecmp (str
, apsr_str
, apsr_str_len
)
1874 && !ISALPHA (*(str
+ apsr_str_len
)))
1877 str
+= apsr_str_len
;
1882 first_error (_("r0-r12, lr or APSR expected"));
1886 else /* etype == REGLIST_RN. */
1890 first_error (_(reg_expected_msgs
[REGLIST_RN
]));
1901 first_error (_("bad range in register list"));
1905 for (i
= cur_reg
+ 1; i
< reg
; i
++)
1907 if (range
& (1 << i
))
1909 (_("Warning: duplicated register (r%d) in register list"),
1917 if (range
& (1 << reg
))
1918 as_tsktsk (_("Warning: duplicated register (r%d) in register list"),
1920 else if (reg
<= cur_reg
)
1921 as_tsktsk (_("Warning: register range not in ascending order"));
1926 while (skip_past_comma (&str
) != FAIL
1927 || (in_range
= 1, *str
++ == '-'));
1930 if (skip_past_char (&str
, '}') == FAIL
)
1932 first_error (_("missing `}'"));
1936 else if (etype
== REGLIST_RN
)
1940 if (my_get_expression (&exp
, &str
, GE_NO_PREFIX
))
1943 if (exp
.X_op
== O_constant
)
1945 if (exp
.X_add_number
1946 != (exp
.X_add_number
& 0x0000ffff))
1948 inst
.error
= _("invalid register mask");
1952 if ((range
& exp
.X_add_number
) != 0)
1954 int regno
= range
& exp
.X_add_number
;
1957 regno
= (1 << regno
) - 1;
1959 (_("Warning: duplicated register (r%d) in register list"),
1963 range
|= exp
.X_add_number
;
1967 if (inst
.relocs
[0].type
!= 0)
1969 inst
.error
= _("expression too complex");
1973 memcpy (&inst
.relocs
[0].exp
, &exp
, sizeof (expressionS
));
1974 inst
.relocs
[0].type
= BFD_RELOC_ARM_MULTI
;
1975 inst
.relocs
[0].pc_rel
= 0;
1979 if (*str
== '|' || *str
== '+')
1985 while (another_range
);
1991 /* Parse a VFP register list. If the string is invalid return FAIL.
1992 Otherwise return the number of registers, and set PBASE to the first
1993 register. Parses registers of type ETYPE.
1994 If REGLIST_NEON_D is used, several syntax enhancements are enabled:
1995 - Q registers can be used to specify pairs of D registers
1996 - { } can be omitted from around a singleton register list
1997 FIXME: This is not implemented, as it would require backtracking in
2000 This could be done (the meaning isn't really ambiguous), but doesn't
2001 fit in well with the current parsing framework.
2002 - 32 D registers may be used (also true for VFPv3).
2003 FIXME: Types are ignored in these register lists, which is probably a
2007 parse_vfp_reg_list (char **ccp
, unsigned int *pbase
, enum reg_list_els etype
,
2008 bfd_boolean
*partial_match
)
2013 enum arm_reg_type regtype
= (enum arm_reg_type
) 0;
2017 unsigned long mask
= 0;
2019 bfd_boolean vpr_seen
= FALSE
;
2020 bfd_boolean expect_vpr
=
2021 (etype
== REGLIST_VFP_S_VPR
) || (etype
== REGLIST_VFP_D_VPR
);
2023 if (skip_past_char (&str
, '{') == FAIL
)
2025 inst
.error
= _("expecting {");
2032 case REGLIST_VFP_S_VPR
:
2033 regtype
= REG_TYPE_VFS
;
2038 case REGLIST_VFP_D_VPR
:
2039 regtype
= REG_TYPE_VFD
;
2042 case REGLIST_NEON_D
:
2043 regtype
= REG_TYPE_NDQ
;
2050 if (etype
!= REGLIST_VFP_S
&& etype
!= REGLIST_VFP_S_VPR
)
2052 /* VFPv3 allows 32 D registers, except for the VFPv3-D16 variant. */
2053 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
2057 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
2060 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
2067 base_reg
= max_regs
;
2068 *partial_match
= FALSE
;
2072 int setmask
= 1, addregs
= 1;
2073 const char vpr_str
[] = "vpr";
2074 int vpr_str_len
= strlen (vpr_str
);
2076 new_base
= arm_typed_reg_parse (&str
, regtype
, ®type
, NULL
);
2080 if (new_base
== FAIL
2081 && !strncasecmp (str
, vpr_str
, vpr_str_len
)
2082 && !ISALPHA (*(str
+ vpr_str_len
))
2088 base_reg
= 0; /* Canonicalize VPR only on d0 with 0 regs. */
2092 first_error (_("VPR expected last"));
2095 else if (new_base
== FAIL
)
2097 if (regtype
== REG_TYPE_VFS
)
2098 first_error (_("VFP single precision register or VPR "
2100 else /* regtype == REG_TYPE_VFD. */
2101 first_error (_("VFP/Neon double precision register or VPR "
2106 else if (new_base
== FAIL
)
2108 first_error (_(reg_expected_msgs
[regtype
]));
2112 *partial_match
= TRUE
;
2116 if (new_base
>= max_regs
)
2118 first_error (_("register out of range in list"));
2122 /* Note: a value of 2 * n is returned for the register Q<n>. */
2123 if (regtype
== REG_TYPE_NQ
)
2129 if (new_base
< base_reg
)
2130 base_reg
= new_base
;
2132 if (mask
& (setmask
<< new_base
))
2134 first_error (_("invalid register list"));
2138 if ((mask
>> new_base
) != 0 && ! warned
&& !vpr_seen
)
2140 as_tsktsk (_("register list not in ascending order"));
2144 mask
|= setmask
<< new_base
;
2147 if (*str
== '-') /* We have the start of a range expression */
2153 if ((high_range
= arm_typed_reg_parse (&str
, regtype
, NULL
, NULL
))
2156 inst
.error
= gettext (reg_expected_msgs
[regtype
]);
2160 if (high_range
>= max_regs
)
2162 first_error (_("register out of range in list"));
2166 if (regtype
== REG_TYPE_NQ
)
2167 high_range
= high_range
+ 1;
2169 if (high_range
<= new_base
)
2171 inst
.error
= _("register range not in ascending order");
2175 for (new_base
+= addregs
; new_base
<= high_range
; new_base
+= addregs
)
2177 if (mask
& (setmask
<< new_base
))
2179 inst
.error
= _("invalid register list");
2183 mask
|= setmask
<< new_base
;
2188 while (skip_past_comma (&str
) != FAIL
);
2192 /* Sanity check -- should have raised a parse error above. */
2193 if ((!vpr_seen
&& count
== 0) || count
> max_regs
)
2198 if (expect_vpr
&& !vpr_seen
)
2200 first_error (_("VPR expected last"));
2204 /* Final test -- the registers must be consecutive. */
2206 for (i
= 0; i
< count
; i
++)
2208 if ((mask
& (1u << i
)) == 0)
2210 inst
.error
= _("non-contiguous register range");
2220 /* True if two alias types are the same. */
2223 neon_alias_types_same (struct neon_typed_alias
*a
, struct neon_typed_alias
*b
)
2231 if (a
->defined
!= b
->defined
)
2234 if ((a
->defined
& NTA_HASTYPE
) != 0
2235 && (a
->eltype
.type
!= b
->eltype
.type
2236 || a
->eltype
.size
!= b
->eltype
.size
))
2239 if ((a
->defined
& NTA_HASINDEX
) != 0
2240 && (a
->index
!= b
->index
))
2246 /* Parse element/structure lists for Neon VLD<n> and VST<n> instructions.
2247 The base register is put in *PBASE.
2248 The lane (or one of the NEON_*_LANES constants) is placed in bits [3:0] of
2250 The register stride (minus one) is put in bit 4 of the return value.
2251 Bits [6:5] encode the list length (minus one).
2252 The type of the list elements is put in *ELTYPE, if non-NULL. */
2254 #define NEON_LANE(X) ((X) & 0xf)
2255 #define NEON_REG_STRIDE(X) ((((X) >> 4) & 1) + 1)
2256 #define NEON_REGLIST_LENGTH(X) ((((X) >> 5) & 3) + 1)
2259 parse_neon_el_struct_list (char **str
, unsigned *pbase
,
2261 struct neon_type_el
*eltype
)
2268 int leading_brace
= 0;
2269 enum arm_reg_type rtype
= REG_TYPE_NDQ
;
2270 const char *const incr_error
= mve
? _("register stride must be 1") :
2271 _("register stride must be 1 or 2");
2272 const char *const type_error
= _("mismatched element/structure types in list");
2273 struct neon_typed_alias firsttype
;
2274 firsttype
.defined
= 0;
2275 firsttype
.eltype
.type
= NT_invtype
;
2276 firsttype
.eltype
.size
= -1;
2277 firsttype
.index
= -1;
2279 if (skip_past_char (&ptr
, '{') == SUCCESS
)
2284 struct neon_typed_alias atype
;
2286 rtype
= REG_TYPE_MQ
;
2287 int getreg
= parse_typed_reg_or_scalar (&ptr
, rtype
, &rtype
, &atype
);
2291 first_error (_(reg_expected_msgs
[rtype
]));
2298 if (rtype
== REG_TYPE_NQ
)
2304 else if (reg_incr
== -1)
2306 reg_incr
= getreg
- base_reg
;
2307 if (reg_incr
< 1 || reg_incr
> 2)
2309 first_error (_(incr_error
));
2313 else if (getreg
!= base_reg
+ reg_incr
* count
)
2315 first_error (_(incr_error
));
2319 if (! neon_alias_types_same (&atype
, &firsttype
))
2321 first_error (_(type_error
));
2325 /* Handle Dn-Dm or Qn-Qm syntax. Can only be used with non-indexed list
2329 struct neon_typed_alias htype
;
2330 int hireg
, dregs
= (rtype
== REG_TYPE_NQ
) ? 2 : 1;
2332 lane
= NEON_INTERLEAVE_LANES
;
2333 else if (lane
!= NEON_INTERLEAVE_LANES
)
2335 first_error (_(type_error
));
2340 else if (reg_incr
!= 1)
2342 first_error (_("don't use Rn-Rm syntax with non-unit stride"));
2346 hireg
= parse_typed_reg_or_scalar (&ptr
, rtype
, NULL
, &htype
);
2349 first_error (_(reg_expected_msgs
[rtype
]));
2352 if (! neon_alias_types_same (&htype
, &firsttype
))
2354 first_error (_(type_error
));
2357 count
+= hireg
+ dregs
- getreg
;
2361 /* If we're using Q registers, we can't use [] or [n] syntax. */
2362 if (rtype
== REG_TYPE_NQ
)
2368 if ((atype
.defined
& NTA_HASINDEX
) != 0)
2372 else if (lane
!= atype
.index
)
2374 first_error (_(type_error
));
2378 else if (lane
== -1)
2379 lane
= NEON_INTERLEAVE_LANES
;
2380 else if (lane
!= NEON_INTERLEAVE_LANES
)
2382 first_error (_(type_error
));
2387 while ((count
!= 1 || leading_brace
) && skip_past_comma (&ptr
) != FAIL
);
2389 /* No lane set by [x]. We must be interleaving structures. */
2391 lane
= NEON_INTERLEAVE_LANES
;
2394 if (lane
== -1 || base_reg
== -1 || count
< 1 || (!mve
&& count
> 4)
2395 || (count
> 1 && reg_incr
== -1))
2397 first_error (_("error parsing element/structure list"));
2401 if ((count
> 1 || leading_brace
) && skip_past_char (&ptr
, '}') == FAIL
)
2403 first_error (_("expected }"));
2411 *eltype
= firsttype
.eltype
;
2416 return lane
| ((reg_incr
- 1) << 4) | ((count
- 1) << 5);
2419 /* Parse an explicit relocation suffix on an expression. This is
2420 either nothing, or a word in parentheses. Note that if !OBJ_ELF,
2421 arm_reloc_hsh contains no entries, so this function can only
2422 succeed if there is no () after the word. Returns -1 on error,
2423 BFD_RELOC_UNUSED if there wasn't any suffix. */
2426 parse_reloc (char **str
)
2428 struct reloc_entry
*r
;
2432 return BFD_RELOC_UNUSED
;
2437 while (*q
&& *q
!= ')' && *q
!= ',')
2442 if ((r
= (struct reloc_entry
*)
2443 hash_find_n (arm_reloc_hsh
, p
, q
- p
)) == NULL
)
2450 /* Directives: register aliases. */
2452 static struct reg_entry
*
2453 insert_reg_alias (char *str
, unsigned number
, int type
)
2455 struct reg_entry
*new_reg
;
2458 if ((new_reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, str
)) != 0)
2460 if (new_reg
->builtin
)
2461 as_warn (_("ignoring attempt to redefine built-in register '%s'"), str
);
2463 /* Only warn about a redefinition if it's not defined as the
2465 else if (new_reg
->number
!= number
|| new_reg
->type
!= type
)
2466 as_warn (_("ignoring redefinition of register alias '%s'"), str
);
2471 name
= xstrdup (str
);
2472 new_reg
= XNEW (struct reg_entry
);
2474 new_reg
->name
= name
;
2475 new_reg
->number
= number
;
2476 new_reg
->type
= type
;
2477 new_reg
->builtin
= FALSE
;
2478 new_reg
->neon
= NULL
;
2480 if (hash_insert (arm_reg_hsh
, name
, (void *) new_reg
))
2487 insert_neon_reg_alias (char *str
, int number
, int type
,
2488 struct neon_typed_alias
*atype
)
2490 struct reg_entry
*reg
= insert_reg_alias (str
, number
, type
);
2494 first_error (_("attempt to redefine typed alias"));
2500 reg
->neon
= XNEW (struct neon_typed_alias
);
2501 *reg
->neon
= *atype
;
2505 /* Look for the .req directive. This is of the form:
2507 new_register_name .req existing_register_name
2509 If we find one, or if it looks sufficiently like one that we want to
2510 handle any error here, return TRUE. Otherwise return FALSE. */
2513 create_register_alias (char * newname
, char *p
)
2515 struct reg_entry
*old
;
2516 char *oldname
, *nbuf
;
2519 /* The input scrubber ensures that whitespace after the mnemonic is
2520 collapsed to single spaces. */
2522 if (strncmp (oldname
, " .req ", 6) != 0)
2526 if (*oldname
== '\0')
2529 old
= (struct reg_entry
*) hash_find (arm_reg_hsh
, oldname
);
2532 as_warn (_("unknown register '%s' -- .req ignored"), oldname
);
2536 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2537 the desired alias name, and p points to its end. If not, then
2538 the desired alias name is in the global original_case_string. */
2539 #ifdef TC_CASE_SENSITIVE
2542 newname
= original_case_string
;
2543 nlen
= strlen (newname
);
2546 nbuf
= xmemdup0 (newname
, nlen
);
2548 /* Create aliases under the new name as stated; an all-lowercase
2549 version of the new name; and an all-uppercase version of the new
2551 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) != NULL
)
2553 for (p
= nbuf
; *p
; p
++)
2556 if (strncmp (nbuf
, newname
, nlen
))
2558 /* If this attempt to create an additional alias fails, do not bother
2559 trying to create the all-lower case alias. We will fail and issue
2560 a second, duplicate error message. This situation arises when the
2561 programmer does something like:
2564 The second .req creates the "Foo" alias but then fails to create
2565 the artificial FOO alias because it has already been created by the
2567 if (insert_reg_alias (nbuf
, old
->number
, old
->type
) == NULL
)
2574 for (p
= nbuf
; *p
; p
++)
2577 if (strncmp (nbuf
, newname
, nlen
))
2578 insert_reg_alias (nbuf
, old
->number
, old
->type
);
2585 /* Create a Neon typed/indexed register alias using directives, e.g.:
2590 These typed registers can be used instead of the types specified after the
2591 Neon mnemonic, so long as all operands given have types. Types can also be
2592 specified directly, e.g.:
2593 vadd d0.s32, d1.s32, d2.s32 */
2596 create_neon_reg_alias (char *newname
, char *p
)
2598 enum arm_reg_type basetype
;
2599 struct reg_entry
*basereg
;
2600 struct reg_entry mybasereg
;
2601 struct neon_type ntype
;
2602 struct neon_typed_alias typeinfo
;
2603 char *namebuf
, *nameend ATTRIBUTE_UNUSED
;
2606 typeinfo
.defined
= 0;
2607 typeinfo
.eltype
.type
= NT_invtype
;
2608 typeinfo
.eltype
.size
= -1;
2609 typeinfo
.index
= -1;
2613 if (strncmp (p
, " .dn ", 5) == 0)
2614 basetype
= REG_TYPE_VFD
;
2615 else if (strncmp (p
, " .qn ", 5) == 0)
2616 basetype
= REG_TYPE_NQ
;
2625 basereg
= arm_reg_parse_multi (&p
);
2627 if (basereg
&& basereg
->type
!= basetype
)
2629 as_bad (_("bad type for register"));
2633 if (basereg
== NULL
)
2636 /* Try parsing as an integer. */
2637 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2638 if (exp
.X_op
!= O_constant
)
2640 as_bad (_("expression must be constant"));
2643 basereg
= &mybasereg
;
2644 basereg
->number
= (basetype
== REG_TYPE_NQ
) ? exp
.X_add_number
* 2
2650 typeinfo
= *basereg
->neon
;
2652 if (parse_neon_type (&ntype
, &p
) == SUCCESS
)
2654 /* We got a type. */
2655 if (typeinfo
.defined
& NTA_HASTYPE
)
2657 as_bad (_("can't redefine the type of a register alias"));
2661 typeinfo
.defined
|= NTA_HASTYPE
;
2662 if (ntype
.elems
!= 1)
2664 as_bad (_("you must specify a single type only"));
2667 typeinfo
.eltype
= ntype
.el
[0];
2670 if (skip_past_char (&p
, '[') == SUCCESS
)
2673 /* We got a scalar index. */
2675 if (typeinfo
.defined
& NTA_HASINDEX
)
2677 as_bad (_("can't redefine the index of a scalar alias"));
2681 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
2683 if (exp
.X_op
!= O_constant
)
2685 as_bad (_("scalar index must be constant"));
2689 typeinfo
.defined
|= NTA_HASINDEX
;
2690 typeinfo
.index
= exp
.X_add_number
;
2692 if (skip_past_char (&p
, ']') == FAIL
)
2694 as_bad (_("expecting ]"));
2699 /* If TC_CASE_SENSITIVE is defined, then newname already points to
2700 the desired alias name, and p points to its end. If not, then
2701 the desired alias name is in the global original_case_string. */
2702 #ifdef TC_CASE_SENSITIVE
2703 namelen
= nameend
- newname
;
2705 newname
= original_case_string
;
2706 namelen
= strlen (newname
);
2709 namebuf
= xmemdup0 (newname
, namelen
);
2711 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2712 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2714 /* Insert name in all uppercase. */
2715 for (p
= namebuf
; *p
; p
++)
2718 if (strncmp (namebuf
, newname
, namelen
))
2719 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2720 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2722 /* Insert name in all lowercase. */
2723 for (p
= namebuf
; *p
; p
++)
2726 if (strncmp (namebuf
, newname
, namelen
))
2727 insert_neon_reg_alias (namebuf
, basereg
->number
, basetype
,
2728 typeinfo
.defined
!= 0 ? &typeinfo
: NULL
);
2734 /* Should never be called, as .req goes between the alias and the
2735 register name, not at the beginning of the line. */
2738 s_req (int a ATTRIBUTE_UNUSED
)
2740 as_bad (_("invalid syntax for .req directive"));
2744 s_dn (int a ATTRIBUTE_UNUSED
)
2746 as_bad (_("invalid syntax for .dn directive"));
2750 s_qn (int a ATTRIBUTE_UNUSED
)
2752 as_bad (_("invalid syntax for .qn directive"));
2755 /* The .unreq directive deletes an alias which was previously defined
2756 by .req. For example:
2762 s_unreq (int a ATTRIBUTE_UNUSED
)
2767 name
= input_line_pointer
;
2769 while (*input_line_pointer
!= 0
2770 && *input_line_pointer
!= ' '
2771 && *input_line_pointer
!= '\n')
2772 ++input_line_pointer
;
2774 saved_char
= *input_line_pointer
;
2775 *input_line_pointer
= 0;
2778 as_bad (_("invalid syntax for .unreq directive"));
2781 struct reg_entry
*reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
,
2785 as_bad (_("unknown register alias '%s'"), name
);
2786 else if (reg
->builtin
)
2787 as_warn (_("ignoring attempt to use .unreq on fixed register name: '%s'"),
2794 hash_delete (arm_reg_hsh
, name
, FALSE
);
2795 free ((char *) reg
->name
);
2800 /* Also locate the all upper case and all lower case versions.
2801 Do not complain if we cannot find one or the other as it
2802 was probably deleted above. */
2804 nbuf
= strdup (name
);
2805 for (p
= nbuf
; *p
; p
++)
2807 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2810 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2811 free ((char *) reg
->name
);
2817 for (p
= nbuf
; *p
; p
++)
2819 reg
= (struct reg_entry
*) hash_find (arm_reg_hsh
, nbuf
);
2822 hash_delete (arm_reg_hsh
, nbuf
, FALSE
);
2823 free ((char *) reg
->name
);
2833 *input_line_pointer
= saved_char
;
2834 demand_empty_rest_of_line ();
2837 /* Directives: Instruction set selection. */
2840 /* This code is to handle mapping symbols as defined in the ARM ELF spec.
2841 (See "Mapping symbols", section 4.5.5, ARM AAELF version 1.0).
2842 Note that previously, $a and $t has type STT_FUNC (BSF_OBJECT flag),
2843 and $d has type STT_OBJECT (BSF_OBJECT flag). Now all three are untyped. */
2845 /* Create a new mapping symbol for the transition to STATE. */
2848 make_mapping_symbol (enum mstate state
, valueT value
, fragS
*frag
)
2851 const char * symname
;
2858 type
= BSF_NO_FLAGS
;
2862 type
= BSF_NO_FLAGS
;
2866 type
= BSF_NO_FLAGS
;
2872 symbolP
= symbol_new (symname
, now_seg
, value
, frag
);
2873 symbol_get_bfdsym (symbolP
)->flags
|= type
| BSF_LOCAL
;
2878 THUMB_SET_FUNC (symbolP
, 0);
2879 ARM_SET_THUMB (symbolP
, 0);
2880 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2884 THUMB_SET_FUNC (symbolP
, 1);
2885 ARM_SET_THUMB (symbolP
, 1);
2886 ARM_SET_INTERWORK (symbolP
, support_interwork
);
2894 /* Save the mapping symbols for future reference. Also check that
2895 we do not place two mapping symbols at the same offset within a
2896 frag. We'll handle overlap between frags in
2897 check_mapping_symbols.
2899 If .fill or other data filling directive generates zero sized data,
2900 the mapping symbol for the following code will have the same value
2901 as the one generated for the data filling directive. In this case,
2902 we replace the old symbol with the new one at the same address. */
2905 if (frag
->tc_frag_data
.first_map
!= NULL
)
2907 know (S_GET_VALUE (frag
->tc_frag_data
.first_map
) == 0);
2908 symbol_remove (frag
->tc_frag_data
.first_map
, &symbol_rootP
, &symbol_lastP
);
2910 frag
->tc_frag_data
.first_map
= symbolP
;
2912 if (frag
->tc_frag_data
.last_map
!= NULL
)
2914 know (S_GET_VALUE (frag
->tc_frag_data
.last_map
) <= S_GET_VALUE (symbolP
));
2915 if (S_GET_VALUE (frag
->tc_frag_data
.last_map
) == S_GET_VALUE (symbolP
))
2916 symbol_remove (frag
->tc_frag_data
.last_map
, &symbol_rootP
, &symbol_lastP
);
2918 frag
->tc_frag_data
.last_map
= symbolP
;
2921 /* We must sometimes convert a region marked as code to data during
2922 code alignment, if an odd number of bytes have to be padded. The
2923 code mapping symbol is pushed to an aligned address. */
2926 insert_data_mapping_symbol (enum mstate state
,
2927 valueT value
, fragS
*frag
, offsetT bytes
)
2929 /* If there was already a mapping symbol, remove it. */
2930 if (frag
->tc_frag_data
.last_map
!= NULL
2931 && S_GET_VALUE (frag
->tc_frag_data
.last_map
) == frag
->fr_address
+ value
)
2933 symbolS
*symp
= frag
->tc_frag_data
.last_map
;
2937 know (frag
->tc_frag_data
.first_map
== symp
);
2938 frag
->tc_frag_data
.first_map
= NULL
;
2940 frag
->tc_frag_data
.last_map
= NULL
;
2941 symbol_remove (symp
, &symbol_rootP
, &symbol_lastP
);
2944 make_mapping_symbol (MAP_DATA
, value
, frag
);
2945 make_mapping_symbol (state
, value
+ bytes
, frag
);
2948 static void mapping_state_2 (enum mstate state
, int max_chars
);
2950 /* Set the mapping state to STATE. Only call this when about to
2951 emit some STATE bytes to the file. */
2953 #define TRANSITION(from, to) (mapstate == (from) && state == (to))
2955 mapping_state (enum mstate state
)
2957 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2959 if (mapstate
== state
)
2960 /* The mapping symbol has already been emitted.
2961 There is nothing else to do. */
2964 if (state
== MAP_ARM
|| state
== MAP_THUMB
)
2966 All ARM instructions require 4-byte alignment.
2967 (Almost) all Thumb instructions require 2-byte alignment.
2969 When emitting instructions into any section, mark the section
2972 Some Thumb instructions are alignment-sensitive modulo 4 bytes,
2973 but themselves require 2-byte alignment; this applies to some
2974 PC- relative forms. However, these cases will involve implicit
2975 literal pool generation or an explicit .align >=2, both of
2976 which will cause the section to me marked with sufficient
2977 alignment. Thus, we don't handle those cases here. */
2978 record_alignment (now_seg
, state
== MAP_ARM
? 2 : 1);
2980 if (TRANSITION (MAP_UNDEFINED
, MAP_DATA
))
2981 /* This case will be evaluated later. */
2984 mapping_state_2 (state
, 0);
2987 /* Same as mapping_state, but MAX_CHARS bytes have already been
2988 allocated. Put the mapping symbol that far back. */
2991 mapping_state_2 (enum mstate state
, int max_chars
)
2993 enum mstate mapstate
= seg_info (now_seg
)->tc_segment_info_data
.mapstate
;
2995 if (!SEG_NORMAL (now_seg
))
2998 if (mapstate
== state
)
2999 /* The mapping symbol has already been emitted.
3000 There is nothing else to do. */
3003 if (TRANSITION (MAP_UNDEFINED
, MAP_ARM
)
3004 || TRANSITION (MAP_UNDEFINED
, MAP_THUMB
))
3006 struct frag
* const frag_first
= seg_info (now_seg
)->frchainP
->frch_root
;
3007 const int add_symbol
= (frag_now
!= frag_first
) || (frag_now_fix () > 0);
3010 make_mapping_symbol (MAP_DATA
, (valueT
) 0, frag_first
);
3013 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= state
;
3014 make_mapping_symbol (state
, (valueT
) frag_now_fix () - max_chars
, frag_now
);
3018 #define mapping_state(x) ((void)0)
3019 #define mapping_state_2(x, y) ((void)0)
3022 /* Find the real, Thumb encoded start of a Thumb function. */
3026 find_real_start (symbolS
* symbolP
)
3029 const char * name
= S_GET_NAME (symbolP
);
3030 symbolS
* new_target
;
3032 /* This definition must agree with the one in gcc/config/arm/thumb.c. */
3033 #define STUB_NAME ".real_start_of"
3038 /* The compiler may generate BL instructions to local labels because
3039 it needs to perform a branch to a far away location. These labels
3040 do not have a corresponding ".real_start_of" label. We check
3041 both for S_IS_LOCAL and for a leading dot, to give a way to bypass
3042 the ".real_start_of" convention for nonlocal branches. */
3043 if (S_IS_LOCAL (symbolP
) || name
[0] == '.')
3046 real_start
= concat (STUB_NAME
, name
, NULL
);
3047 new_target
= symbol_find (real_start
);
3050 if (new_target
== NULL
)
3052 as_warn (_("Failed to find real start of function: %s\n"), name
);
3053 new_target
= symbolP
;
3061 opcode_select (int width
)
3068 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
3069 as_bad (_("selected processor does not support THUMB opcodes"));
3072 /* No need to force the alignment, since we will have been
3073 coming from ARM mode, which is word-aligned. */
3074 record_alignment (now_seg
, 1);
3081 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
3082 as_bad (_("selected processor does not support ARM opcodes"));
3087 frag_align (2, 0, 0);
3089 record_alignment (now_seg
, 1);
3094 as_bad (_("invalid instruction size selected (%d)"), width
);
3099 s_arm (int ignore ATTRIBUTE_UNUSED
)
3102 demand_empty_rest_of_line ();
3106 s_thumb (int ignore ATTRIBUTE_UNUSED
)
3109 demand_empty_rest_of_line ();
3113 s_code (int unused ATTRIBUTE_UNUSED
)
3117 temp
= get_absolute_expression ();
3122 opcode_select (temp
);
3126 as_bad (_("invalid operand to .code directive (%d) (expecting 16 or 32)"), temp
);
3131 s_force_thumb (int ignore ATTRIBUTE_UNUSED
)
3133 /* If we are not already in thumb mode go into it, EVEN if
3134 the target processor does not support thumb instructions.
3135 This is used by gcc/config/arm/lib1funcs.asm for example
3136 to compile interworking support functions even if the
3137 target processor should not support interworking. */
3141 record_alignment (now_seg
, 1);
3144 demand_empty_rest_of_line ();
3148 s_thumb_func (int ignore ATTRIBUTE_UNUSED
)
3152 /* The following label is the name/address of the start of a Thumb function.
3153 We need to know this for the interworking support. */
3154 label_is_thumb_function_name
= TRUE
;
3157 /* Perform a .set directive, but also mark the alias as
3158 being a thumb function. */
3161 s_thumb_set (int equiv
)
3163 /* XXX the following is a duplicate of the code for s_set() in read.c
3164 We cannot just call that code as we need to get at the symbol that
3171 /* Especial apologies for the random logic:
3172 This just grew, and could be parsed much more simply!
3174 delim
= get_symbol_name (& name
);
3175 end_name
= input_line_pointer
;
3176 (void) restore_line_pointer (delim
);
3178 if (*input_line_pointer
!= ',')
3181 as_bad (_("expected comma after name \"%s\""), name
);
3183 ignore_rest_of_line ();
3187 input_line_pointer
++;
3190 if (name
[0] == '.' && name
[1] == '\0')
3192 /* XXX - this should not happen to .thumb_set. */
3196 if ((symbolP
= symbol_find (name
)) == NULL
3197 && (symbolP
= md_undefined_symbol (name
)) == NULL
)
3200 /* When doing symbol listings, play games with dummy fragments living
3201 outside the normal fragment chain to record the file and line info
3203 if (listing
& LISTING_SYMBOLS
)
3205 extern struct list_info_struct
* listing_tail
;
3206 fragS
* dummy_frag
= (fragS
* ) xmalloc (sizeof (fragS
));
3208 memset (dummy_frag
, 0, sizeof (fragS
));
3209 dummy_frag
->fr_type
= rs_fill
;
3210 dummy_frag
->line
= listing_tail
;
3211 symbolP
= symbol_new (name
, undefined_section
, 0, dummy_frag
);
3212 dummy_frag
->fr_symbol
= symbolP
;
3216 symbolP
= symbol_new (name
, undefined_section
, 0, &zero_address_frag
);
3219 /* "set" symbols are local unless otherwise specified. */
3220 SF_SET_LOCAL (symbolP
);
3221 #endif /* OBJ_COFF */
3222 } /* Make a new symbol. */
3224 symbol_table_insert (symbolP
);
3229 && S_IS_DEFINED (symbolP
)
3230 && S_GET_SEGMENT (symbolP
) != reg_section
)
3231 as_bad (_("symbol `%s' already defined"), S_GET_NAME (symbolP
));
3233 pseudo_set (symbolP
);
3235 demand_empty_rest_of_line ();
3237 /* XXX Now we come to the Thumb specific bit of code. */
3239 THUMB_SET_FUNC (symbolP
, 1);
3240 ARM_SET_THUMB (symbolP
, 1);
3241 #if defined OBJ_ELF || defined OBJ_COFF
3242 ARM_SET_INTERWORK (symbolP
, support_interwork
);
3246 /* Directives: Mode selection. */
3248 /* .syntax [unified|divided] - choose the new unified syntax
3249 (same for Arm and Thumb encoding, modulo slight differences in what
3250 can be represented) or the old divergent syntax for each mode. */
3252 s_syntax (int unused ATTRIBUTE_UNUSED
)
3256 delim
= get_symbol_name (& name
);
3258 if (!strcasecmp (name
, "unified"))
3259 unified_syntax
= TRUE
;
3260 else if (!strcasecmp (name
, "divided"))
3261 unified_syntax
= FALSE
;
3264 as_bad (_("unrecognized syntax mode \"%s\""), name
);
3267 (void) restore_line_pointer (delim
);
3268 demand_empty_rest_of_line ();
3271 /* Directives: sectioning and alignment. */
3274 s_bss (int ignore ATTRIBUTE_UNUSED
)
3276 /* We don't support putting frags in the BSS segment, we fake it by
3277 marking in_bss, then looking at s_skip for clues. */
3278 subseg_set (bss_section
, 0);
3279 demand_empty_rest_of_line ();
3281 #ifdef md_elf_section_change_hook
3282 md_elf_section_change_hook ();
3287 s_even (int ignore ATTRIBUTE_UNUSED
)
3289 /* Never make frag if expect extra pass. */
3291 frag_align (1, 0, 0);
3293 record_alignment (now_seg
, 1);
3295 demand_empty_rest_of_line ();
3298 /* Directives: CodeComposer Studio. */
3300 /* .ref (for CodeComposer Studio syntax only). */
3302 s_ccs_ref (int unused ATTRIBUTE_UNUSED
)
3304 if (codecomposer_syntax
)
3305 ignore_rest_of_line ();
3307 as_bad (_(".ref pseudo-op only available with -mccs flag."));
3310 /* If name is not NULL, then it is used for marking the beginning of a
3311 function, whereas if it is NULL then it means the function end. */
3313 asmfunc_debug (const char * name
)
3315 static const char * last_name
= NULL
;
3319 gas_assert (last_name
== NULL
);
3322 if (debug_type
== DEBUG_STABS
)
3323 stabs_generate_asm_func (name
, name
);
3327 gas_assert (last_name
!= NULL
);
3329 if (debug_type
== DEBUG_STABS
)
3330 stabs_generate_asm_endfunc (last_name
, last_name
);
3337 s_ccs_asmfunc (int unused ATTRIBUTE_UNUSED
)
3339 if (codecomposer_syntax
)
3341 switch (asmfunc_state
)
3343 case OUTSIDE_ASMFUNC
:
3344 asmfunc_state
= WAITING_ASMFUNC_NAME
;
3347 case WAITING_ASMFUNC_NAME
:
3348 as_bad (_(".asmfunc repeated."));
3351 case WAITING_ENDASMFUNC
:
3352 as_bad (_(".asmfunc without function."));
3355 demand_empty_rest_of_line ();
3358 as_bad (_(".asmfunc pseudo-op only available with -mccs flag."));
3362 s_ccs_endasmfunc (int unused ATTRIBUTE_UNUSED
)
3364 if (codecomposer_syntax
)
3366 switch (asmfunc_state
)
3368 case OUTSIDE_ASMFUNC
:
3369 as_bad (_(".endasmfunc without a .asmfunc."));
3372 case WAITING_ASMFUNC_NAME
:
3373 as_bad (_(".endasmfunc without function."));
3376 case WAITING_ENDASMFUNC
:
3377 asmfunc_state
= OUTSIDE_ASMFUNC
;
3378 asmfunc_debug (NULL
);
3381 demand_empty_rest_of_line ();
3384 as_bad (_(".endasmfunc pseudo-op only available with -mccs flag."));
3388 s_ccs_def (int name
)
3390 if (codecomposer_syntax
)
3393 as_bad (_(".def pseudo-op only available with -mccs flag."));
3396 /* Directives: Literal pools. */
3398 static literal_pool
*
3399 find_literal_pool (void)
3401 literal_pool
* pool
;
3403 for (pool
= list_of_pools
; pool
!= NULL
; pool
= pool
->next
)
3405 if (pool
->section
== now_seg
3406 && pool
->sub_section
== now_subseg
)
3413 static literal_pool
*
3414 find_or_make_literal_pool (void)
3416 /* Next literal pool ID number. */
3417 static unsigned int latest_pool_num
= 1;
3418 literal_pool
* pool
;
3420 pool
= find_literal_pool ();
3424 /* Create a new pool. */
3425 pool
= XNEW (literal_pool
);
3429 pool
->next_free_entry
= 0;
3430 pool
->section
= now_seg
;
3431 pool
->sub_section
= now_subseg
;
3432 pool
->next
= list_of_pools
;
3433 pool
->symbol
= NULL
;
3434 pool
->alignment
= 2;
3436 /* Add it to the list. */
3437 list_of_pools
= pool
;
3440 /* New pools, and emptied pools, will have a NULL symbol. */
3441 if (pool
->symbol
== NULL
)
3443 pool
->symbol
= symbol_create (FAKE_LABEL_NAME
, undefined_section
,
3444 (valueT
) 0, &zero_address_frag
);
3445 pool
->id
= latest_pool_num
++;
3452 /* Add the literal in the global 'inst'
3453 structure to the relevant literal pool. */
3456 add_to_lit_pool (unsigned int nbytes
)
3458 #define PADDING_SLOT 0x1
3459 #define LIT_ENTRY_SIZE_MASK 0xFF
3460 literal_pool
* pool
;
3461 unsigned int entry
, pool_size
= 0;
3462 bfd_boolean padding_slot_p
= FALSE
;
3468 imm1
= inst
.operands
[1].imm
;
3469 imm2
= (inst
.operands
[1].regisimm
? inst
.operands
[1].reg
3470 : inst
.relocs
[0].exp
.X_unsigned
? 0
3471 : ((bfd_int64_t
) inst
.operands
[1].imm
) >> 32);
3472 if (target_big_endian
)
3475 imm2
= inst
.operands
[1].imm
;
3479 pool
= find_or_make_literal_pool ();
3481 /* Check if this literal value is already in the pool. */
3482 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3486 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3487 && (inst
.relocs
[0].exp
.X_op
== O_constant
)
3488 && (pool
->literals
[entry
].X_add_number
3489 == inst
.relocs
[0].exp
.X_add_number
)
3490 && (pool
->literals
[entry
].X_md
== nbytes
)
3491 && (pool
->literals
[entry
].X_unsigned
3492 == inst
.relocs
[0].exp
.X_unsigned
))
3495 if ((pool
->literals
[entry
].X_op
== inst
.relocs
[0].exp
.X_op
)
3496 && (inst
.relocs
[0].exp
.X_op
== O_symbol
)
3497 && (pool
->literals
[entry
].X_add_number
3498 == inst
.relocs
[0].exp
.X_add_number
)
3499 && (pool
->literals
[entry
].X_add_symbol
3500 == inst
.relocs
[0].exp
.X_add_symbol
)
3501 && (pool
->literals
[entry
].X_op_symbol
3502 == inst
.relocs
[0].exp
.X_op_symbol
)
3503 && (pool
->literals
[entry
].X_md
== nbytes
))
3506 else if ((nbytes
== 8)
3507 && !(pool_size
& 0x7)
3508 && ((entry
+ 1) != pool
->next_free_entry
)
3509 && (pool
->literals
[entry
].X_op
== O_constant
)
3510 && (pool
->literals
[entry
].X_add_number
== (offsetT
) imm1
)
3511 && (pool
->literals
[entry
].X_unsigned
3512 == inst
.relocs
[0].exp
.X_unsigned
)
3513 && (pool
->literals
[entry
+ 1].X_op
== O_constant
)
3514 && (pool
->literals
[entry
+ 1].X_add_number
== (offsetT
) imm2
)
3515 && (pool
->literals
[entry
+ 1].X_unsigned
3516 == inst
.relocs
[0].exp
.X_unsigned
))
3519 padding_slot_p
= ((pool
->literals
[entry
].X_md
>> 8) == PADDING_SLOT
);
3520 if (padding_slot_p
&& (nbytes
== 4))
3526 /* Do we need to create a new entry? */
3527 if (entry
== pool
->next_free_entry
)
3529 if (entry
>= MAX_LITERAL_POOL_SIZE
)
3531 inst
.error
= _("literal pool overflow");
3537 /* For 8-byte entries, we align to an 8-byte boundary,
3538 and split it into two 4-byte entries, because on 32-bit
3539 host, 8-byte constants are treated as big num, thus
3540 saved in "generic_bignum" which will be overwritten
3541 by later assignments.
3543 We also need to make sure there is enough space for
3546 We also check to make sure the literal operand is a
3548 if (!(inst
.relocs
[0].exp
.X_op
== O_constant
3549 || inst
.relocs
[0].exp
.X_op
== O_big
))
3551 inst
.error
= _("invalid type for literal pool");
3554 else if (pool_size
& 0x7)
3556 if ((entry
+ 2) >= MAX_LITERAL_POOL_SIZE
)
3558 inst
.error
= _("literal pool overflow");
3562 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3563 pool
->literals
[entry
].X_op
= O_constant
;
3564 pool
->literals
[entry
].X_add_number
= 0;
3565 pool
->literals
[entry
++].X_md
= (PADDING_SLOT
<< 8) | 4;
3566 pool
->next_free_entry
+= 1;
3569 else if ((entry
+ 1) >= MAX_LITERAL_POOL_SIZE
)
3571 inst
.error
= _("literal pool overflow");
3575 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3576 pool
->literals
[entry
].X_op
= O_constant
;
3577 pool
->literals
[entry
].X_add_number
= imm1
;
3578 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3579 pool
->literals
[entry
++].X_md
= 4;
3580 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3581 pool
->literals
[entry
].X_op
= O_constant
;
3582 pool
->literals
[entry
].X_add_number
= imm2
;
3583 pool
->literals
[entry
].X_unsigned
= inst
.relocs
[0].exp
.X_unsigned
;
3584 pool
->literals
[entry
].X_md
= 4;
3585 pool
->alignment
= 3;
3586 pool
->next_free_entry
+= 1;
3590 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3591 pool
->literals
[entry
].X_md
= 4;
3595 /* PR ld/12974: Record the location of the first source line to reference
3596 this entry in the literal pool. If it turns out during linking that the
3597 symbol does not exist we will be able to give an accurate line number for
3598 the (first use of the) missing reference. */
3599 if (debug_type
== DEBUG_DWARF2
)
3600 dwarf2_where (pool
->locs
+ entry
);
3602 pool
->next_free_entry
+= 1;
3604 else if (padding_slot_p
)
3606 pool
->literals
[entry
] = inst
.relocs
[0].exp
;
3607 pool
->literals
[entry
].X_md
= nbytes
;
3610 inst
.relocs
[0].exp
.X_op
= O_symbol
;
3611 inst
.relocs
[0].exp
.X_add_number
= pool_size
;
3612 inst
.relocs
[0].exp
.X_add_symbol
= pool
->symbol
;
3618 tc_start_label_without_colon (void)
3620 bfd_boolean ret
= TRUE
;
3622 if (codecomposer_syntax
&& asmfunc_state
== WAITING_ASMFUNC_NAME
)
3624 const char *label
= input_line_pointer
;
3626 while (!is_end_of_line
[(int) label
[-1]])
3631 as_bad (_("Invalid label '%s'"), label
);
3635 asmfunc_debug (label
);
3637 asmfunc_state
= WAITING_ENDASMFUNC
;
3643 /* Can't use symbol_new here, so have to create a symbol and then at
3644 a later date assign it a value. That's what these functions do. */
3647 symbol_locate (symbolS
* symbolP
,
3648 const char * name
, /* It is copied, the caller can modify. */
3649 segT segment
, /* Segment identifier (SEG_<something>). */
3650 valueT valu
, /* Symbol value. */
3651 fragS
* frag
) /* Associated fragment. */
3654 char * preserved_copy_of_name
;
3656 name_length
= strlen (name
) + 1; /* +1 for \0. */
3657 obstack_grow (¬es
, name
, name_length
);
3658 preserved_copy_of_name
= (char *) obstack_finish (¬es
);
3660 #ifdef tc_canonicalize_symbol_name
3661 preserved_copy_of_name
=
3662 tc_canonicalize_symbol_name (preserved_copy_of_name
);
3665 S_SET_NAME (symbolP
, preserved_copy_of_name
);
3667 S_SET_SEGMENT (symbolP
, segment
);
3668 S_SET_VALUE (symbolP
, valu
);
3669 symbol_clear_list_pointers (symbolP
);
3671 symbol_set_frag (symbolP
, frag
);
3673 /* Link to end of symbol chain. */
3675 extern int symbol_table_frozen
;
3677 if (symbol_table_frozen
)
3681 symbol_append (symbolP
, symbol_lastP
, & symbol_rootP
, & symbol_lastP
);
3683 obj_symbol_new_hook (symbolP
);
3685 #ifdef tc_symbol_new_hook
3686 tc_symbol_new_hook (symbolP
);
3690 verify_symbol_chain (symbol_rootP
, symbol_lastP
);
3691 #endif /* DEBUG_SYMS */
3695 s_ltorg (int ignored ATTRIBUTE_UNUSED
)
3698 literal_pool
* pool
;
3701 pool
= find_literal_pool ();
3703 || pool
->symbol
== NULL
3704 || pool
->next_free_entry
== 0)
3707 /* Align pool as you have word accesses.
3708 Only make a frag if we have to. */
3710 frag_align (pool
->alignment
, 0, 0);
3712 record_alignment (now_seg
, 2);
3715 seg_info (now_seg
)->tc_segment_info_data
.mapstate
= MAP_DATA
;
3716 make_mapping_symbol (MAP_DATA
, (valueT
) frag_now_fix (), frag_now
);
3718 sprintf (sym_name
, "$$lit_\002%x", pool
->id
);
3720 symbol_locate (pool
->symbol
, sym_name
, now_seg
,
3721 (valueT
) frag_now_fix (), frag_now
);
3722 symbol_table_insert (pool
->symbol
);
3724 ARM_SET_THUMB (pool
->symbol
, thumb_mode
);
3726 #if defined OBJ_COFF || defined OBJ_ELF
3727 ARM_SET_INTERWORK (pool
->symbol
, support_interwork
);
3730 for (entry
= 0; entry
< pool
->next_free_entry
; entry
++)
3733 if (debug_type
== DEBUG_DWARF2
)
3734 dwarf2_gen_line_info (frag_now_fix (), pool
->locs
+ entry
);
3736 /* First output the expression in the instruction to the pool. */
3737 emit_expr (&(pool
->literals
[entry
]),
3738 pool
->literals
[entry
].X_md
& LIT_ENTRY_SIZE_MASK
);
3741 /* Mark the pool as empty. */
3742 pool
->next_free_entry
= 0;
3743 pool
->symbol
= NULL
;
3747 /* Forward declarations for functions below, in the MD interface
3749 static void fix_new_arm (fragS
*, int, short, expressionS
*, int, int);
3750 static valueT
create_unwind_entry (int);
3751 static void start_unwind_section (const segT
, int);
3752 static void add_unwind_opcode (valueT
, int);
3753 static void flush_pending_unwind (void);
3755 /* Directives: Data. */
3758 s_arm_elf_cons (int nbytes
)
3762 #ifdef md_flush_pending_output
3763 md_flush_pending_output ();
3766 if (is_it_end_of_statement ())
3768 demand_empty_rest_of_line ();
3772 #ifdef md_cons_align
3773 md_cons_align (nbytes
);
3776 mapping_state (MAP_DATA
);
3780 char *base
= input_line_pointer
;
3784 if (exp
.X_op
!= O_symbol
)
3785 emit_expr (&exp
, (unsigned int) nbytes
);
3788 char *before_reloc
= input_line_pointer
;
3789 reloc
= parse_reloc (&input_line_pointer
);
3792 as_bad (_("unrecognized relocation suffix"));
3793 ignore_rest_of_line ();
3796 else if (reloc
== BFD_RELOC_UNUSED
)
3797 emit_expr (&exp
, (unsigned int) nbytes
);
3800 reloc_howto_type
*howto
= (reloc_howto_type
*)
3801 bfd_reloc_type_lookup (stdoutput
,
3802 (bfd_reloc_code_real_type
) reloc
);
3803 int size
= bfd_get_reloc_size (howto
);
3805 if (reloc
== BFD_RELOC_ARM_PLT32
)
3807 as_bad (_("(plt) is only valid on branch targets"));
3808 reloc
= BFD_RELOC_UNUSED
;
3813 as_bad (ngettext ("%s relocations do not fit in %d byte",
3814 "%s relocations do not fit in %d bytes",
3816 howto
->name
, nbytes
);
3819 /* We've parsed an expression stopping at O_symbol.
3820 But there may be more expression left now that we
3821 have parsed the relocation marker. Parse it again.
3822 XXX Surely there is a cleaner way to do this. */
3823 char *p
= input_line_pointer
;
3825 char *save_buf
= XNEWVEC (char, input_line_pointer
- base
);
3827 memcpy (save_buf
, base
, input_line_pointer
- base
);
3828 memmove (base
+ (input_line_pointer
- before_reloc
),
3829 base
, before_reloc
- base
);
3831 input_line_pointer
= base
+ (input_line_pointer
-before_reloc
);
3833 memcpy (base
, save_buf
, p
- base
);
3835 offset
= nbytes
- size
;
3836 p
= frag_more (nbytes
);
3837 memset (p
, 0, nbytes
);
3838 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
+ offset
,
3839 size
, &exp
, 0, (enum bfd_reloc_code_real
) reloc
);
3845 while (*input_line_pointer
++ == ',');
3847 /* Put terminator back into stream. */
3848 input_line_pointer
--;
3849 demand_empty_rest_of_line ();
3852 /* Emit an expression containing a 32-bit thumb instruction.
3853 Implementation based on put_thumb32_insn. */
3856 emit_thumb32_expr (expressionS
* exp
)
3858 expressionS exp_high
= *exp
;
3860 exp_high
.X_add_number
= (unsigned long)exp_high
.X_add_number
>> 16;
3861 emit_expr (& exp_high
, (unsigned int) THUMB_SIZE
);
3862 exp
->X_add_number
&= 0xffff;
3863 emit_expr (exp
, (unsigned int) THUMB_SIZE
);
3866 /* Guess the instruction size based on the opcode. */
3869 thumb_insn_size (int opcode
)
3871 if ((unsigned int) opcode
< 0xe800u
)
3873 else if ((unsigned int) opcode
>= 0xe8000000u
)
3880 emit_insn (expressionS
*exp
, int nbytes
)
3884 if (exp
->X_op
== O_constant
)
3889 size
= thumb_insn_size (exp
->X_add_number
);
3893 if (size
== 2 && (unsigned int)exp
->X_add_number
> 0xffffu
)
3895 as_bad (_(".inst.n operand too big. "\
3896 "Use .inst.w instead"));
3901 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
3902 set_pred_insn_type_nonvoid (OUTSIDE_PRED_INSN
, 0);
3904 set_pred_insn_type_nonvoid (NEUTRAL_IT_INSN
, 0);
3906 if (thumb_mode
&& (size
> THUMB_SIZE
) && !target_big_endian
)
3907 emit_thumb32_expr (exp
);
3909 emit_expr (exp
, (unsigned int) size
);
3911 it_fsm_post_encode ();
3915 as_bad (_("cannot determine Thumb instruction size. " \
3916 "Use .inst.n/.inst.w instead"));
3919 as_bad (_("constant expression required"));
3924 /* Like s_arm_elf_cons but do not use md_cons_align and
3925 set the mapping state to MAP_ARM/MAP_THUMB. */
3928 s_arm_elf_inst (int nbytes
)
3930 if (is_it_end_of_statement ())
3932 demand_empty_rest_of_line ();
3936 /* Calling mapping_state () here will not change ARM/THUMB,
3937 but will ensure not to be in DATA state. */
3940 mapping_state (MAP_THUMB
);
3945 as_bad (_("width suffixes are invalid in ARM mode"));
3946 ignore_rest_of_line ();
3952 mapping_state (MAP_ARM
);
3961 if (! emit_insn (& exp
, nbytes
))
3963 ignore_rest_of_line ();
3967 while (*input_line_pointer
++ == ',');
3969 /* Put terminator back into stream. */
3970 input_line_pointer
--;
3971 demand_empty_rest_of_line ();
3974 /* Parse a .rel31 directive. */
3977 s_arm_rel31 (int ignored ATTRIBUTE_UNUSED
)
3984 if (*input_line_pointer
== '1')
3985 highbit
= 0x80000000;
3986 else if (*input_line_pointer
!= '0')
3987 as_bad (_("expected 0 or 1"));
3989 input_line_pointer
++;
3990 if (*input_line_pointer
!= ',')
3991 as_bad (_("missing comma"));
3992 input_line_pointer
++;
3994 #ifdef md_flush_pending_output
3995 md_flush_pending_output ();
3998 #ifdef md_cons_align
4002 mapping_state (MAP_DATA
);
4007 md_number_to_chars (p
, highbit
, 4);
4008 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 1,
4009 BFD_RELOC_ARM_PREL31
);
4011 demand_empty_rest_of_line ();
4014 /* Directives: AEABI stack-unwind tables. */
4016 /* Parse an unwind_fnstart directive. Simply records the current location. */
4019 s_arm_unwind_fnstart (int ignored ATTRIBUTE_UNUSED
)
4021 demand_empty_rest_of_line ();
4022 if (unwind
.proc_start
)
4024 as_bad (_("duplicate .fnstart directive"));
4028 /* Mark the start of the function. */
4029 unwind
.proc_start
= expr_build_dot ();
4031 /* Reset the rest of the unwind info. */
4032 unwind
.opcode_count
= 0;
4033 unwind
.table_entry
= NULL
;
4034 unwind
.personality_routine
= NULL
;
4035 unwind
.personality_index
= -1;
4036 unwind
.frame_size
= 0;
4037 unwind
.fp_offset
= 0;
4038 unwind
.fp_reg
= REG_SP
;
4040 unwind
.sp_restored
= 0;
4044 /* Parse a handlerdata directive. Creates the exception handling table entry
4045 for the function. */
4048 s_arm_unwind_handlerdata (int ignored ATTRIBUTE_UNUSED
)
4050 demand_empty_rest_of_line ();
4051 if (!unwind
.proc_start
)
4052 as_bad (MISSING_FNSTART
);
4054 if (unwind
.table_entry
)
4055 as_bad (_("duplicate .handlerdata directive"));
4057 create_unwind_entry (1);
4060 /* Parse an unwind_fnend directive. Generates the index table entry. */
4063 s_arm_unwind_fnend (int ignored ATTRIBUTE_UNUSED
)
4068 unsigned int marked_pr_dependency
;
4070 demand_empty_rest_of_line ();
4072 if (!unwind
.proc_start
)
4074 as_bad (_(".fnend directive without .fnstart"));
4078 /* Add eh table entry. */
4079 if (unwind
.table_entry
== NULL
)
4080 val
= create_unwind_entry (0);
4084 /* Add index table entry. This is two words. */
4085 start_unwind_section (unwind
.saved_seg
, 1);
4086 frag_align (2, 0, 0);
4087 record_alignment (now_seg
, 2);
4089 ptr
= frag_more (8);
4091 where
= frag_now_fix () - 8;
4093 /* Self relative offset of the function start. */
4094 fix_new (frag_now
, where
, 4, unwind
.proc_start
, 0, 1,
4095 BFD_RELOC_ARM_PREL31
);
4097 /* Indicate dependency on EHABI-defined personality routines to the
4098 linker, if it hasn't been done already. */
4099 marked_pr_dependency
4100 = seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
;
4101 if (unwind
.personality_index
>= 0 && unwind
.personality_index
< 3
4102 && !(marked_pr_dependency
& (1 << unwind
.personality_index
)))
4104 static const char *const name
[] =
4106 "__aeabi_unwind_cpp_pr0",
4107 "__aeabi_unwind_cpp_pr1",
4108 "__aeabi_unwind_cpp_pr2"
4110 symbolS
*pr
= symbol_find_or_make (name
[unwind
.personality_index
]);
4111 fix_new (frag_now
, where
, 0, pr
, 0, 1, BFD_RELOC_NONE
);
4112 seg_info (now_seg
)->tc_segment_info_data
.marked_pr_dependency
4113 |= 1 << unwind
.personality_index
;
4117 /* Inline exception table entry. */
4118 md_number_to_chars (ptr
+ 4, val
, 4);
4120 /* Self relative offset of the table entry. */
4121 fix_new (frag_now
, where
+ 4, 4, unwind
.table_entry
, 0, 1,
4122 BFD_RELOC_ARM_PREL31
);
4124 /* Restore the original section. */
4125 subseg_set (unwind
.saved_seg
, unwind
.saved_subseg
);
4127 unwind
.proc_start
= NULL
;
4131 /* Parse an unwind_cantunwind directive. */
4134 s_arm_unwind_cantunwind (int ignored ATTRIBUTE_UNUSED
)
4136 demand_empty_rest_of_line ();
4137 if (!unwind
.proc_start
)
4138 as_bad (MISSING_FNSTART
);
4140 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4141 as_bad (_("personality routine specified for cantunwind frame"));
4143 unwind
.personality_index
= -2;
4147 /* Parse a personalityindex directive. */
4150 s_arm_unwind_personalityindex (int ignored ATTRIBUTE_UNUSED
)
4154 if (!unwind
.proc_start
)
4155 as_bad (MISSING_FNSTART
);
4157 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4158 as_bad (_("duplicate .personalityindex directive"));
4162 if (exp
.X_op
!= O_constant
4163 || exp
.X_add_number
< 0 || exp
.X_add_number
> 15)
4165 as_bad (_("bad personality routine number"));
4166 ignore_rest_of_line ();
4170 unwind
.personality_index
= exp
.X_add_number
;
4172 demand_empty_rest_of_line ();
4176 /* Parse a personality directive. */
4179 s_arm_unwind_personality (int ignored ATTRIBUTE_UNUSED
)
4183 if (!unwind
.proc_start
)
4184 as_bad (MISSING_FNSTART
);
4186 if (unwind
.personality_routine
|| unwind
.personality_index
!= -1)
4187 as_bad (_("duplicate .personality directive"));
4189 c
= get_symbol_name (& name
);
4190 p
= input_line_pointer
;
4192 ++ input_line_pointer
;
4193 unwind
.personality_routine
= symbol_find_or_make (name
);
4195 demand_empty_rest_of_line ();
4199 /* Parse a directive saving core registers. */
4202 s_arm_unwind_save_core (void)
4208 range
= parse_reg_list (&input_line_pointer
, REGLIST_RN
);
4211 as_bad (_("expected register list"));
4212 ignore_rest_of_line ();
4216 demand_empty_rest_of_line ();
4218 /* Turn .unwind_movsp ip followed by .unwind_save {..., ip, ...}
4219 into .unwind_save {..., sp...}. We aren't bothered about the value of
4220 ip because it is clobbered by calls. */
4221 if (unwind
.sp_restored
&& unwind
.fp_reg
== 12
4222 && (range
& 0x3000) == 0x1000)
4224 unwind
.opcode_count
--;
4225 unwind
.sp_restored
= 0;
4226 range
= (range
| 0x2000) & ~0x1000;
4227 unwind
.pending_offset
= 0;
4233 /* See if we can use the short opcodes. These pop a block of up to 8
4234 registers starting with r4, plus maybe r14. */
4235 for (n
= 0; n
< 8; n
++)
4237 /* Break at the first non-saved register. */
4238 if ((range
& (1 << (n
+ 4))) == 0)
4241 /* See if there are any other bits set. */
4242 if (n
== 0 || (range
& (0xfff0 << n
) & 0xbff0) != 0)
4244 /* Use the long form. */
4245 op
= 0x8000 | ((range
>> 4) & 0xfff);
4246 add_unwind_opcode (op
, 2);
4250 /* Use the short form. */
4252 op
= 0xa8; /* Pop r14. */
4254 op
= 0xa0; /* Do not pop r14. */
4256 add_unwind_opcode (op
, 1);
4263 op
= 0xb100 | (range
& 0xf);
4264 add_unwind_opcode (op
, 2);
4267 /* Record the number of bytes pushed. */
4268 for (n
= 0; n
< 16; n
++)
4270 if (range
& (1 << n
))
4271 unwind
.frame_size
+= 4;
4276 /* Parse a directive saving FPA registers. */
4279 s_arm_unwind_save_fpa (int reg
)
4285 /* Get Number of registers to transfer. */
4286 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4289 exp
.X_op
= O_illegal
;
4291 if (exp
.X_op
!= O_constant
)
4293 as_bad (_("expected , <constant>"));
4294 ignore_rest_of_line ();
4298 num_regs
= exp
.X_add_number
;
4300 if (num_regs
< 1 || num_regs
> 4)
4302 as_bad (_("number of registers must be in the range [1:4]"));
4303 ignore_rest_of_line ();
4307 demand_empty_rest_of_line ();
4312 op
= 0xb4 | (num_regs
- 1);
4313 add_unwind_opcode (op
, 1);
4318 op
= 0xc800 | (reg
<< 4) | (num_regs
- 1);
4319 add_unwind_opcode (op
, 2);
4321 unwind
.frame_size
+= num_regs
* 12;
4325 /* Parse a directive saving VFP registers for ARMv6 and above. */
4328 s_arm_unwind_save_vfp_armv6 (void)
4333 int num_vfpv3_regs
= 0;
4334 int num_regs_below_16
;
4335 bfd_boolean partial_match
;
4337 count
= parse_vfp_reg_list (&input_line_pointer
, &start
, REGLIST_VFP_D
,
4341 as_bad (_("expected register list"));
4342 ignore_rest_of_line ();
4346 demand_empty_rest_of_line ();
4348 /* We always generate FSTMD/FLDMD-style unwinding opcodes (rather
4349 than FSTMX/FLDMX-style ones). */
4351 /* Generate opcode for (VFPv3) registers numbered in the range 16 .. 31. */
4353 num_vfpv3_regs
= count
;
4354 else if (start
+ count
> 16)
4355 num_vfpv3_regs
= start
+ count
- 16;
4357 if (num_vfpv3_regs
> 0)
4359 int start_offset
= start
> 16 ? start
- 16 : 0;
4360 op
= 0xc800 | (start_offset
<< 4) | (num_vfpv3_regs
- 1);
4361 add_unwind_opcode (op
, 2);
4364 /* Generate opcode for registers numbered in the range 0 .. 15. */
4365 num_regs_below_16
= num_vfpv3_regs
> 0 ? 16 - (int) start
: count
;
4366 gas_assert (num_regs_below_16
+ num_vfpv3_regs
== count
);
4367 if (num_regs_below_16
> 0)
4369 op
= 0xc900 | (start
<< 4) | (num_regs_below_16
- 1);
4370 add_unwind_opcode (op
, 2);
4373 unwind
.frame_size
+= count
* 8;
4377 /* Parse a directive saving VFP registers for pre-ARMv6. */
4380 s_arm_unwind_save_vfp (void)
4385 bfd_boolean partial_match
;
4387 count
= parse_vfp_reg_list (&input_line_pointer
, ®
, REGLIST_VFP_D
,
4391 as_bad (_("expected register list"));
4392 ignore_rest_of_line ();
4396 demand_empty_rest_of_line ();
4401 op
= 0xb8 | (count
- 1);
4402 add_unwind_opcode (op
, 1);
4407 op
= 0xb300 | (reg
<< 4) | (count
- 1);
4408 add_unwind_opcode (op
, 2);
4410 unwind
.frame_size
+= count
* 8 + 4;
4414 /* Parse a directive saving iWMMXt data registers. */
4417 s_arm_unwind_save_mmxwr (void)
4425 if (*input_line_pointer
== '{')
4426 input_line_pointer
++;
4430 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4434 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4439 as_tsktsk (_("register list not in ascending order"));
4442 if (*input_line_pointer
== '-')
4444 input_line_pointer
++;
4445 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWR
);
4448 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWR
]));
4451 else if (reg
>= hi_reg
)
4453 as_bad (_("bad register range"));
4456 for (; reg
< hi_reg
; reg
++)
4460 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4462 skip_past_char (&input_line_pointer
, '}');
4464 demand_empty_rest_of_line ();
4466 /* Generate any deferred opcodes because we're going to be looking at
4468 flush_pending_unwind ();
4470 for (i
= 0; i
< 16; i
++)
4472 if (mask
& (1 << i
))
4473 unwind
.frame_size
+= 8;
4476 /* Attempt to combine with a previous opcode. We do this because gcc
4477 likes to output separate unwind directives for a single block of
4479 if (unwind
.opcode_count
> 0)
4481 i
= unwind
.opcodes
[unwind
.opcode_count
- 1];
4482 if ((i
& 0xf8) == 0xc0)
4485 /* Only merge if the blocks are contiguous. */
4488 if ((mask
& 0xfe00) == (1 << 9))
4490 mask
|= ((1 << (i
+ 11)) - 1) & 0xfc00;
4491 unwind
.opcode_count
--;
4494 else if (i
== 6 && unwind
.opcode_count
>= 2)
4496 i
= unwind
.opcodes
[unwind
.opcode_count
- 2];
4500 op
= 0xffff << (reg
- 1);
4502 && ((mask
& op
) == (1u << (reg
- 1))))
4504 op
= (1 << (reg
+ i
+ 1)) - 1;
4505 op
&= ~((1 << reg
) - 1);
4507 unwind
.opcode_count
-= 2;
4514 /* We want to generate opcodes in the order the registers have been
4515 saved, ie. descending order. */
4516 for (reg
= 15; reg
>= -1; reg
--)
4518 /* Save registers in blocks. */
4520 || !(mask
& (1 << reg
)))
4522 /* We found an unsaved reg. Generate opcodes to save the
4529 op
= 0xc0 | (hi_reg
- 10);
4530 add_unwind_opcode (op
, 1);
4535 op
= 0xc600 | ((reg
+ 1) << 4) | ((hi_reg
- reg
) - 1);
4536 add_unwind_opcode (op
, 2);
4545 ignore_rest_of_line ();
4549 s_arm_unwind_save_mmxwcg (void)
4556 if (*input_line_pointer
== '{')
4557 input_line_pointer
++;
4559 skip_whitespace (input_line_pointer
);
4563 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4567 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4573 as_tsktsk (_("register list not in ascending order"));
4576 if (*input_line_pointer
== '-')
4578 input_line_pointer
++;
4579 hi_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_MMXWCG
);
4582 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_MMXWCG
]));
4585 else if (reg
>= hi_reg
)
4587 as_bad (_("bad register range"));
4590 for (; reg
< hi_reg
; reg
++)
4594 while (skip_past_comma (&input_line_pointer
) != FAIL
);
4596 skip_past_char (&input_line_pointer
, '}');
4598 demand_empty_rest_of_line ();
4600 /* Generate any deferred opcodes because we're going to be looking at
4602 flush_pending_unwind ();
4604 for (reg
= 0; reg
< 16; reg
++)
4606 if (mask
& (1 << reg
))
4607 unwind
.frame_size
+= 4;
4610 add_unwind_opcode (op
, 2);
4613 ignore_rest_of_line ();
4617 /* Parse an unwind_save directive.
4618 If the argument is non-zero, this is a .vsave directive. */
4621 s_arm_unwind_save (int arch_v6
)
4624 struct reg_entry
*reg
;
4625 bfd_boolean had_brace
= FALSE
;
4627 if (!unwind
.proc_start
)
4628 as_bad (MISSING_FNSTART
);
4630 /* Figure out what sort of save we have. */
4631 peek
= input_line_pointer
;
4639 reg
= arm_reg_parse_multi (&peek
);
4643 as_bad (_("register expected"));
4644 ignore_rest_of_line ();
4653 as_bad (_("FPA .unwind_save does not take a register list"));
4654 ignore_rest_of_line ();
4657 input_line_pointer
= peek
;
4658 s_arm_unwind_save_fpa (reg
->number
);
4662 s_arm_unwind_save_core ();
4667 s_arm_unwind_save_vfp_armv6 ();
4669 s_arm_unwind_save_vfp ();
4672 case REG_TYPE_MMXWR
:
4673 s_arm_unwind_save_mmxwr ();
4676 case REG_TYPE_MMXWCG
:
4677 s_arm_unwind_save_mmxwcg ();
4681 as_bad (_(".unwind_save does not support this kind of register"));
4682 ignore_rest_of_line ();
4687 /* Parse an unwind_movsp directive. */
4690 s_arm_unwind_movsp (int ignored ATTRIBUTE_UNUSED
)
4696 if (!unwind
.proc_start
)
4697 as_bad (MISSING_FNSTART
);
4699 reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4702 as_bad ("%s", _(reg_expected_msgs
[REG_TYPE_RN
]));
4703 ignore_rest_of_line ();
4707 /* Optional constant. */
4708 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4710 if (immediate_for_directive (&offset
) == FAIL
)
4716 demand_empty_rest_of_line ();
4718 if (reg
== REG_SP
|| reg
== REG_PC
)
4720 as_bad (_("SP and PC not permitted in .unwind_movsp directive"));
4724 if (unwind
.fp_reg
!= REG_SP
)
4725 as_bad (_("unexpected .unwind_movsp directive"));
4727 /* Generate opcode to restore the value. */
4729 add_unwind_opcode (op
, 1);
4731 /* Record the information for later. */
4732 unwind
.fp_reg
= reg
;
4733 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4734 unwind
.sp_restored
= 1;
4737 /* Parse an unwind_pad directive. */
4740 s_arm_unwind_pad (int ignored ATTRIBUTE_UNUSED
)
4744 if (!unwind
.proc_start
)
4745 as_bad (MISSING_FNSTART
);
4747 if (immediate_for_directive (&offset
) == FAIL
)
4752 as_bad (_("stack increment must be multiple of 4"));
4753 ignore_rest_of_line ();
4757 /* Don't generate any opcodes, just record the details for later. */
4758 unwind
.frame_size
+= offset
;
4759 unwind
.pending_offset
+= offset
;
4761 demand_empty_rest_of_line ();
4764 /* Parse an unwind_setfp directive. */
4767 s_arm_unwind_setfp (int ignored ATTRIBUTE_UNUSED
)
4773 if (!unwind
.proc_start
)
4774 as_bad (MISSING_FNSTART
);
4776 fp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4777 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4780 sp_reg
= arm_reg_parse (&input_line_pointer
, REG_TYPE_RN
);
4782 if (fp_reg
== FAIL
|| sp_reg
== FAIL
)
4784 as_bad (_("expected <reg>, <reg>"));
4785 ignore_rest_of_line ();
4789 /* Optional constant. */
4790 if (skip_past_comma (&input_line_pointer
) != FAIL
)
4792 if (immediate_for_directive (&offset
) == FAIL
)
4798 demand_empty_rest_of_line ();
4800 if (sp_reg
!= REG_SP
&& sp_reg
!= unwind
.fp_reg
)
4802 as_bad (_("register must be either sp or set by a previous"
4803 "unwind_movsp directive"));
4807 /* Don't generate any opcodes, just record the information for later. */
4808 unwind
.fp_reg
= fp_reg
;
4810 if (sp_reg
== REG_SP
)
4811 unwind
.fp_offset
= unwind
.frame_size
- offset
;
4813 unwind
.fp_offset
-= offset
;
4816 /* Parse an unwind_raw directive. */
4819 s_arm_unwind_raw (int ignored ATTRIBUTE_UNUSED
)
4822 /* This is an arbitrary limit. */
4823 unsigned char op
[16];
4826 if (!unwind
.proc_start
)
4827 as_bad (MISSING_FNSTART
);
4830 if (exp
.X_op
== O_constant
4831 && skip_past_comma (&input_line_pointer
) != FAIL
)
4833 unwind
.frame_size
+= exp
.X_add_number
;
4837 exp
.X_op
= O_illegal
;
4839 if (exp
.X_op
!= O_constant
)
4841 as_bad (_("expected <offset>, <opcode>"));
4842 ignore_rest_of_line ();
4848 /* Parse the opcode. */
4853 as_bad (_("unwind opcode too long"));
4854 ignore_rest_of_line ();
4856 if (exp
.X_op
!= O_constant
|| exp
.X_add_number
& ~0xff)
4858 as_bad (_("invalid unwind opcode"));
4859 ignore_rest_of_line ();
4862 op
[count
++] = exp
.X_add_number
;
4864 /* Parse the next byte. */
4865 if (skip_past_comma (&input_line_pointer
) == FAIL
)
4871 /* Add the opcode bytes in reverse order. */
4873 add_unwind_opcode (op
[count
], 1);
4875 demand_empty_rest_of_line ();
4879 /* Parse a .eabi_attribute directive. */
4882 s_arm_eabi_attribute (int ignored ATTRIBUTE_UNUSED
)
4884 int tag
= obj_elf_vendor_attribute (OBJ_ATTR_PROC
);
4886 if (tag
>= 0 && tag
< NUM_KNOWN_OBJ_ATTRIBUTES
)
4887 attributes_set_explicitly
[tag
] = 1;
4890 /* Emit a tls fix for the symbol. */
4893 s_arm_tls_descseq (int ignored ATTRIBUTE_UNUSED
)
4897 #ifdef md_flush_pending_output
4898 md_flush_pending_output ();
4901 #ifdef md_cons_align
4905 /* Since we're just labelling the code, there's no need to define a
4908 p
= obstack_next_free (&frchain_now
->frch_obstack
);
4909 fix_new_arm (frag_now
, p
- frag_now
->fr_literal
, 4, &exp
, 0,
4910 thumb_mode
? BFD_RELOC_ARM_THM_TLS_DESCSEQ
4911 : BFD_RELOC_ARM_TLS_DESCSEQ
);
4913 #endif /* OBJ_ELF */
4915 static void s_arm_arch (int);
4916 static void s_arm_object_arch (int);
4917 static void s_arm_cpu (int);
4918 static void s_arm_fpu (int);
4919 static void s_arm_arch_extension (int);
4924 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED
)
4931 if (exp
.X_op
== O_symbol
)
4932 exp
.X_op
= O_secrel
;
4934 emit_expr (&exp
, 4);
4936 while (*input_line_pointer
++ == ',');
4938 input_line_pointer
--;
4939 demand_empty_rest_of_line ();
4944 arm_is_largest_exponent_ok (int precision
)
4946 /* precision == 1 ensures that this will only return
4947 true for 16 bit floats. */
4948 return (precision
== 1) && (fp16_format
== ARM_FP16_FORMAT_ALTERNATIVE
);
4952 set_fp16_format (int dummy ATTRIBUTE_UNUSED
)
4956 enum fp_16bit_format new_format
;
4958 new_format
= ARM_FP16_FORMAT_DEFAULT
;
4960 name
= input_line_pointer
;
4961 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
4962 input_line_pointer
++;
4964 saved_char
= *input_line_pointer
;
4965 *input_line_pointer
= 0;
4967 if (strcasecmp (name
, "ieee") == 0)
4968 new_format
= ARM_FP16_FORMAT_IEEE
;
4969 else if (strcasecmp (name
, "alternative") == 0)
4970 new_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
4973 as_bad (_("unrecognised float16 format \"%s\""), name
);
4977 /* Only set fp16_format if it is still the default (aka not already
4979 if (fp16_format
== ARM_FP16_FORMAT_DEFAULT
)
4980 fp16_format
= new_format
;
4983 if (new_format
!= fp16_format
)
4984 as_warn (_("float16 format cannot be set more than once, ignoring."));
4988 *input_line_pointer
= saved_char
;
4989 ignore_rest_of_line ();
4992 /* This table describes all the machine specific pseudo-ops the assembler
4993 has to support. The fields are:
4994 pseudo-op name without dot
4995 function to call to execute this pseudo-op
4996 Integer arg to pass to the function. */
4998 const pseudo_typeS md_pseudo_table
[] =
5000 /* Never called because '.req' does not start a line. */
5001 { "req", s_req
, 0 },
5002 /* Following two are likewise never called. */
5005 { "unreq", s_unreq
, 0 },
5006 { "bss", s_bss
, 0 },
5007 { "align", s_align_ptwo
, 2 },
5008 { "arm", s_arm
, 0 },
5009 { "thumb", s_thumb
, 0 },
5010 { "code", s_code
, 0 },
5011 { "force_thumb", s_force_thumb
, 0 },
5012 { "thumb_func", s_thumb_func
, 0 },
5013 { "thumb_set", s_thumb_set
, 0 },
5014 { "even", s_even
, 0 },
5015 { "ltorg", s_ltorg
, 0 },
5016 { "pool", s_ltorg
, 0 },
5017 { "syntax", s_syntax
, 0 },
5018 { "cpu", s_arm_cpu
, 0 },
5019 { "arch", s_arm_arch
, 0 },
5020 { "object_arch", s_arm_object_arch
, 0 },
5021 { "fpu", s_arm_fpu
, 0 },
5022 { "arch_extension", s_arm_arch_extension
, 0 },
5024 { "word", s_arm_elf_cons
, 4 },
5025 { "long", s_arm_elf_cons
, 4 },
5026 { "inst.n", s_arm_elf_inst
, 2 },
5027 { "inst.w", s_arm_elf_inst
, 4 },
5028 { "inst", s_arm_elf_inst
, 0 },
5029 { "rel31", s_arm_rel31
, 0 },
5030 { "fnstart", s_arm_unwind_fnstart
, 0 },
5031 { "fnend", s_arm_unwind_fnend
, 0 },
5032 { "cantunwind", s_arm_unwind_cantunwind
, 0 },
5033 { "personality", s_arm_unwind_personality
, 0 },
5034 { "personalityindex", s_arm_unwind_personalityindex
, 0 },
5035 { "handlerdata", s_arm_unwind_handlerdata
, 0 },
5036 { "save", s_arm_unwind_save
, 0 },
5037 { "vsave", s_arm_unwind_save
, 1 },
5038 { "movsp", s_arm_unwind_movsp
, 0 },
5039 { "pad", s_arm_unwind_pad
, 0 },
5040 { "setfp", s_arm_unwind_setfp
, 0 },
5041 { "unwind_raw", s_arm_unwind_raw
, 0 },
5042 { "eabi_attribute", s_arm_eabi_attribute
, 0 },
5043 { "tlsdescseq", s_arm_tls_descseq
, 0 },
5047 /* These are used for dwarf. */
5051 /* These are used for dwarf2. */
5052 { "file", dwarf2_directive_file
, 0 },
5053 { "loc", dwarf2_directive_loc
, 0 },
5054 { "loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0 },
5056 { "extend", float_cons
, 'x' },
5057 { "ldouble", float_cons
, 'x' },
5058 { "packed", float_cons
, 'p' },
5060 {"secrel32", pe_directive_secrel
, 0},
5063 /* These are for compatibility with CodeComposer Studio. */
5064 {"ref", s_ccs_ref
, 0},
5065 {"def", s_ccs_def
, 0},
5066 {"asmfunc", s_ccs_asmfunc
, 0},
5067 {"endasmfunc", s_ccs_endasmfunc
, 0},
5069 {"float16", float_cons
, 'h' },
5070 {"float16_format", set_fp16_format
, 0 },
5075 /* Parser functions used exclusively in instruction operands. */
5077 /* Generic immediate-value read function for use in insn parsing.
5078 STR points to the beginning of the immediate (the leading #);
5079 VAL receives the value; if the value is outside [MIN, MAX]
5080 issue an error. PREFIX_OPT is true if the immediate prefix is
5084 parse_immediate (char **str
, int *val
, int min
, int max
,
5085 bfd_boolean prefix_opt
)
5089 my_get_expression (&exp
, str
, prefix_opt
? GE_OPT_PREFIX
: GE_IMM_PREFIX
);
5090 if (exp
.X_op
!= O_constant
)
5092 inst
.error
= _("constant expression required");
5096 if (exp
.X_add_number
< min
|| exp
.X_add_number
> max
)
5098 inst
.error
= _("immediate value out of range");
5102 *val
= exp
.X_add_number
;
5106 /* Less-generic immediate-value read function with the possibility of loading a
5107 big (64-bit) immediate, as required by Neon VMOV, VMVN and logic immediate
5108 instructions. Puts the result directly in inst.operands[i]. */
5111 parse_big_immediate (char **str
, int i
, expressionS
*in_exp
,
5112 bfd_boolean allow_symbol_p
)
5115 expressionS
*exp_p
= in_exp
? in_exp
: &exp
;
5118 my_get_expression (exp_p
, &ptr
, GE_OPT_PREFIX_BIG
);
5120 if (exp_p
->X_op
== O_constant
)
5122 inst
.operands
[i
].imm
= exp_p
->X_add_number
& 0xffffffff;
5123 /* If we're on a 64-bit host, then a 64-bit number can be returned using
5124 O_constant. We have to be careful not to break compilation for
5125 32-bit X_add_number, though. */
5126 if ((exp_p
->X_add_number
& ~(offsetT
)(0xffffffffU
)) != 0)
5128 /* X >> 32 is illegal if sizeof (exp_p->X_add_number) == 4. */
5129 inst
.operands
[i
].reg
= (((exp_p
->X_add_number
>> 16) >> 16)
5131 inst
.operands
[i
].regisimm
= 1;
5134 else if (exp_p
->X_op
== O_big
5135 && LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 32)
5137 unsigned parts
= 32 / LITTLENUM_NUMBER_OF_BITS
, j
, idx
= 0;
5139 /* Bignums have their least significant bits in
5140 generic_bignum[0]. Make sure we put 32 bits in imm and
5141 32 bits in reg, in a (hopefully) portable way. */
5142 gas_assert (parts
!= 0);
5144 /* Make sure that the number is not too big.
5145 PR 11972: Bignums can now be sign-extended to the
5146 size of a .octa so check that the out of range bits
5147 are all zero or all one. */
5148 if (LITTLENUM_NUMBER_OF_BITS
* exp_p
->X_add_number
> 64)
5150 LITTLENUM_TYPE m
= -1;
5152 if (generic_bignum
[parts
* 2] != 0
5153 && generic_bignum
[parts
* 2] != m
)
5156 for (j
= parts
* 2 + 1; j
< (unsigned) exp_p
->X_add_number
; j
++)
5157 if (generic_bignum
[j
] != generic_bignum
[j
-1])
5161 inst
.operands
[i
].imm
= 0;
5162 for (j
= 0; j
< parts
; j
++, idx
++)
5163 inst
.operands
[i
].imm
|= generic_bignum
[idx
]
5164 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5165 inst
.operands
[i
].reg
= 0;
5166 for (j
= 0; j
< parts
; j
++, idx
++)
5167 inst
.operands
[i
].reg
|= generic_bignum
[idx
]
5168 << (LITTLENUM_NUMBER_OF_BITS
* j
);
5169 inst
.operands
[i
].regisimm
= 1;
5171 else if (!(exp_p
->X_op
== O_symbol
&& allow_symbol_p
))
5179 /* Returns the pseudo-register number of an FPA immediate constant,
5180 or FAIL if there isn't a valid constant here. */
5183 parse_fpa_immediate (char ** str
)
5185 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5191 /* First try and match exact strings, this is to guarantee
5192 that some formats will work even for cross assembly. */
5194 for (i
= 0; fp_const
[i
]; i
++)
5196 if (strncmp (*str
, fp_const
[i
], strlen (fp_const
[i
])) == 0)
5200 *str
+= strlen (fp_const
[i
]);
5201 if (is_end_of_line
[(unsigned char) **str
])
5207 /* Just because we didn't get a match doesn't mean that the constant
5208 isn't valid, just that it is in a format that we don't
5209 automatically recognize. Try parsing it with the standard
5210 expression routines. */
5212 memset (words
, 0, MAX_LITTLENUMS
* sizeof (LITTLENUM_TYPE
));
5214 /* Look for a raw floating point number. */
5215 if ((save_in
= atof_ieee (*str
, 'x', words
)) != NULL
5216 && is_end_of_line
[(unsigned char) *save_in
])
5218 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5220 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5222 if (words
[j
] != fp_values
[i
][j
])
5226 if (j
== MAX_LITTLENUMS
)
5234 /* Try and parse a more complex expression, this will probably fail
5235 unless the code uses a floating point prefix (eg "0f"). */
5236 save_in
= input_line_pointer
;
5237 input_line_pointer
= *str
;
5238 if (expression (&exp
) == absolute_section
5239 && exp
.X_op
== O_big
5240 && exp
.X_add_number
< 0)
5242 /* FIXME: 5 = X_PRECISION, should be #define'd where we can use it.
5244 #define X_PRECISION 5
5245 #define E_PRECISION 15L
5246 if (gen_to_words (words
, X_PRECISION
, E_PRECISION
) == 0)
5248 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
5250 for (j
= 0; j
< MAX_LITTLENUMS
; j
++)
5252 if (words
[j
] != fp_values
[i
][j
])
5256 if (j
== MAX_LITTLENUMS
)
5258 *str
= input_line_pointer
;
5259 input_line_pointer
= save_in
;
5266 *str
= input_line_pointer
;
5267 input_line_pointer
= save_in
;
5268 inst
.error
= _("invalid FPA immediate expression");
5272 /* Returns 1 if a number has "quarter-precision" float format
5273 0baBbbbbbc defgh000 00000000 00000000. */
5276 is_quarter_float (unsigned imm
)
5278 int bs
= (imm
& 0x20000000) ? 0x3e000000 : 0x40000000;
5279 return (imm
& 0x7ffff) == 0 && ((imm
& 0x7e000000) ^ bs
) == 0;
5283 /* Detect the presence of a floating point or integer zero constant,
5287 parse_ifimm_zero (char **in
)
5291 if (!is_immediate_prefix (**in
))
5293 /* In unified syntax, all prefixes are optional. */
5294 if (!unified_syntax
)
5300 /* Accept #0x0 as a synonym for #0. */
5301 if (strncmp (*in
, "0x", 2) == 0)
5304 if (parse_immediate (in
, &val
, 0, 0, TRUE
) == FAIL
)
5309 error_code
= atof_generic (in
, ".", EXP_CHARS
,
5310 &generic_floating_point_number
);
5313 && generic_floating_point_number
.sign
== '+'
5314 && (generic_floating_point_number
.low
5315 > generic_floating_point_number
.leader
))
5321 /* Parse an 8-bit "quarter-precision" floating point number of the form:
5322 0baBbbbbbc defgh000 00000000 00000000.
5323 The zero and minus-zero cases need special handling, since they can't be
5324 encoded in the "quarter-precision" float format, but can nonetheless be
5325 loaded as integer constants. */
5328 parse_qfloat_immediate (char **ccp
, int *immed
)
5332 LITTLENUM_TYPE words
[MAX_LITTLENUMS
];
5333 int found_fpchar
= 0;
5335 skip_past_char (&str
, '#');
5337 /* We must not accidentally parse an integer as a floating-point number. Make
5338 sure that the value we parse is not an integer by checking for special
5339 characters '.' or 'e'.
5340 FIXME: This is a horrible hack, but doing better is tricky because type
5341 information isn't in a very usable state at parse time. */
5343 skip_whitespace (fpnum
);
5345 if (strncmp (fpnum
, "0x", 2) == 0)
5349 for (; *fpnum
!= '\0' && *fpnum
!= ' ' && *fpnum
!= '\n'; fpnum
++)
5350 if (*fpnum
== '.' || *fpnum
== 'e' || *fpnum
== 'E')
5360 if ((str
= atof_ieee (str
, 's', words
)) != NULL
)
5362 unsigned fpword
= 0;
5365 /* Our FP word must be 32 bits (single-precision FP). */
5366 for (i
= 0; i
< 32 / LITTLENUM_NUMBER_OF_BITS
; i
++)
5368 fpword
<<= LITTLENUM_NUMBER_OF_BITS
;
5372 if (is_quarter_float (fpword
) || (fpword
& 0x7fffffff) == 0)
5385 /* Shift operands. */
5388 SHIFT_LSL
, SHIFT_LSR
, SHIFT_ASR
, SHIFT_ROR
, SHIFT_RRX
, SHIFT_UXTW
5391 struct asm_shift_name
5394 enum shift_kind kind
;
5397 /* Third argument to parse_shift. */
5398 enum parse_shift_mode
5400 NO_SHIFT_RESTRICT
, /* Any kind of shift is accepted. */
5401 SHIFT_IMMEDIATE
, /* Shift operand must be an immediate. */
5402 SHIFT_LSL_OR_ASR_IMMEDIATE
, /* Shift must be LSL or ASR immediate. */
5403 SHIFT_ASR_IMMEDIATE
, /* Shift must be ASR immediate. */
5404 SHIFT_LSL_IMMEDIATE
, /* Shift must be LSL immediate. */
5405 SHIFT_UXTW_IMMEDIATE
/* Shift must be UXTW immediate. */
5408 /* Parse a <shift> specifier on an ARM data processing instruction.
5409 This has three forms:
5411 (LSL|LSR|ASL|ASR|ROR) Rs
5412 (LSL|LSR|ASL|ASR|ROR) #imm
5415 Note that ASL is assimilated to LSL in the instruction encoding, and
5416 RRX to ROR #0 (which cannot be written as such). */
5419 parse_shift (char **str
, int i
, enum parse_shift_mode mode
)
5421 const struct asm_shift_name
*shift_name
;
5422 enum shift_kind shift
;
5427 for (p
= *str
; ISALPHA (*p
); p
++)
5432 inst
.error
= _("shift expression expected");
5436 shift_name
= (const struct asm_shift_name
*) hash_find_n (arm_shift_hsh
, *str
,
5439 if (shift_name
== NULL
)
5441 inst
.error
= _("shift expression expected");
5445 shift
= shift_name
->kind
;
5449 case NO_SHIFT_RESTRICT
:
5450 case SHIFT_IMMEDIATE
:
5451 if (shift
== SHIFT_UXTW
)
5453 inst
.error
= _("'UXTW' not allowed here");
5458 case SHIFT_LSL_OR_ASR_IMMEDIATE
:
5459 if (shift
!= SHIFT_LSL
&& shift
!= SHIFT_ASR
)
5461 inst
.error
= _("'LSL' or 'ASR' required");
5466 case SHIFT_LSL_IMMEDIATE
:
5467 if (shift
!= SHIFT_LSL
)
5469 inst
.error
= _("'LSL' required");
5474 case SHIFT_ASR_IMMEDIATE
:
5475 if (shift
!= SHIFT_ASR
)
5477 inst
.error
= _("'ASR' required");
5481 case SHIFT_UXTW_IMMEDIATE
:
5482 if (shift
!= SHIFT_UXTW
)
5484 inst
.error
= _("'UXTW' required");
5492 if (shift
!= SHIFT_RRX
)
5494 /* Whitespace can appear here if the next thing is a bare digit. */
5495 skip_whitespace (p
);
5497 if (mode
== NO_SHIFT_RESTRICT
5498 && (reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5500 inst
.operands
[i
].imm
= reg
;
5501 inst
.operands
[i
].immisreg
= 1;
5503 else if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5506 inst
.operands
[i
].shift_kind
= shift
;
5507 inst
.operands
[i
].shifted
= 1;
5512 /* Parse a <shifter_operand> for an ARM data processing instruction:
5515 #<immediate>, <rotate>
5519 where <shift> is defined by parse_shift above, and <rotate> is a
5520 multiple of 2 between 0 and 30. Validation of immediate operands
5521 is deferred to md_apply_fix. */
5524 parse_shifter_operand (char **str
, int i
)
5529 if ((value
= arm_reg_parse (str
, REG_TYPE_RN
)) != FAIL
)
5531 inst
.operands
[i
].reg
= value
;
5532 inst
.operands
[i
].isreg
= 1;
5534 /* parse_shift will override this if appropriate */
5535 inst
.relocs
[0].exp
.X_op
= O_constant
;
5536 inst
.relocs
[0].exp
.X_add_number
= 0;
5538 if (skip_past_comma (str
) == FAIL
)
5541 /* Shift operation on register. */
5542 return parse_shift (str
, i
, NO_SHIFT_RESTRICT
);
5545 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_IMM_PREFIX
))
5548 if (skip_past_comma (str
) == SUCCESS
)
5550 /* #x, y -- ie explicit rotation by Y. */
5551 if (my_get_expression (&exp
, str
, GE_NO_PREFIX
))
5554 if (exp
.X_op
!= O_constant
|| inst
.relocs
[0].exp
.X_op
!= O_constant
)
5556 inst
.error
= _("constant expression expected");
5560 value
= exp
.X_add_number
;
5561 if (value
< 0 || value
> 30 || value
% 2 != 0)
5563 inst
.error
= _("invalid rotation");
5566 if (inst
.relocs
[0].exp
.X_add_number
< 0
5567 || inst
.relocs
[0].exp
.X_add_number
> 255)
5569 inst
.error
= _("invalid constant");
5573 /* Encode as specified. */
5574 inst
.operands
[i
].imm
= inst
.relocs
[0].exp
.X_add_number
| value
<< 7;
5578 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
5579 inst
.relocs
[0].pc_rel
= 0;
5583 /* Group relocation information. Each entry in the table contains the
5584 textual name of the relocation as may appear in assembler source
5585 and must end with a colon.
5586 Along with this textual name are the relocation codes to be used if
5587 the corresponding instruction is an ALU instruction (ADD or SUB only),
5588 an LDR, an LDRS, or an LDC. */
5590 struct group_reloc_table_entry
5601 /* Varieties of non-ALU group relocation. */
5609 static struct group_reloc_table_entry group_reloc_table
[] =
5610 { /* Program counter relative: */
5612 BFD_RELOC_ARM_ALU_PC_G0_NC
, /* ALU */
5617 BFD_RELOC_ARM_ALU_PC_G0
, /* ALU */
5618 BFD_RELOC_ARM_LDR_PC_G0
, /* LDR */
5619 BFD_RELOC_ARM_LDRS_PC_G0
, /* LDRS */
5620 BFD_RELOC_ARM_LDC_PC_G0
}, /* LDC */
5622 BFD_RELOC_ARM_ALU_PC_G1_NC
, /* ALU */
5627 BFD_RELOC_ARM_ALU_PC_G1
, /* ALU */
5628 BFD_RELOC_ARM_LDR_PC_G1
, /* LDR */
5629 BFD_RELOC_ARM_LDRS_PC_G1
, /* LDRS */
5630 BFD_RELOC_ARM_LDC_PC_G1
}, /* LDC */
5632 BFD_RELOC_ARM_ALU_PC_G2
, /* ALU */
5633 BFD_RELOC_ARM_LDR_PC_G2
, /* LDR */
5634 BFD_RELOC_ARM_LDRS_PC_G2
, /* LDRS */
5635 BFD_RELOC_ARM_LDC_PC_G2
}, /* LDC */
5636 /* Section base relative */
5638 BFD_RELOC_ARM_ALU_SB_G0_NC
, /* ALU */
5643 BFD_RELOC_ARM_ALU_SB_G0
, /* ALU */
5644 BFD_RELOC_ARM_LDR_SB_G0
, /* LDR */
5645 BFD_RELOC_ARM_LDRS_SB_G0
, /* LDRS */
5646 BFD_RELOC_ARM_LDC_SB_G0
}, /* LDC */
5648 BFD_RELOC_ARM_ALU_SB_G1_NC
, /* ALU */
5653 BFD_RELOC_ARM_ALU_SB_G1
, /* ALU */
5654 BFD_RELOC_ARM_LDR_SB_G1
, /* LDR */
5655 BFD_RELOC_ARM_LDRS_SB_G1
, /* LDRS */
5656 BFD_RELOC_ARM_LDC_SB_G1
}, /* LDC */
5658 BFD_RELOC_ARM_ALU_SB_G2
, /* ALU */
5659 BFD_RELOC_ARM_LDR_SB_G2
, /* LDR */
5660 BFD_RELOC_ARM_LDRS_SB_G2
, /* LDRS */
5661 BFD_RELOC_ARM_LDC_SB_G2
}, /* LDC */
5662 /* Absolute thumb alu relocations. */
5664 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
,/* ALU. */
5669 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
,/* ALU. */
5674 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
,/* ALU. */
5679 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,/* ALU. */
5684 /* Given the address of a pointer pointing to the textual name of a group
5685 relocation as may appear in assembler source, attempt to find its details
5686 in group_reloc_table. The pointer will be updated to the character after
5687 the trailing colon. On failure, FAIL will be returned; SUCCESS
5688 otherwise. On success, *entry will be updated to point at the relevant
5689 group_reloc_table entry. */
5692 find_group_reloc_table_entry (char **str
, struct group_reloc_table_entry
**out
)
5695 for (i
= 0; i
< ARRAY_SIZE (group_reloc_table
); i
++)
5697 int length
= strlen (group_reloc_table
[i
].name
);
5699 if (strncasecmp (group_reloc_table
[i
].name
, *str
, length
) == 0
5700 && (*str
)[length
] == ':')
5702 *out
= &group_reloc_table
[i
];
5703 *str
+= (length
+ 1);
5711 /* Parse a <shifter_operand> for an ARM data processing instruction
5712 (as for parse_shifter_operand) where group relocations are allowed:
5715 #<immediate>, <rotate>
5716 #:<group_reloc>:<expression>
5720 where <group_reloc> is one of the strings defined in group_reloc_table.
5721 The hashes are optional.
5723 Everything else is as for parse_shifter_operand. */
5725 static parse_operand_result
5726 parse_shifter_operand_group_reloc (char **str
, int i
)
5728 /* Determine if we have the sequence of characters #: or just :
5729 coming next. If we do, then we check for a group relocation.
5730 If we don't, punt the whole lot to parse_shifter_operand. */
5732 if (((*str
)[0] == '#' && (*str
)[1] == ':')
5733 || (*str
)[0] == ':')
5735 struct group_reloc_table_entry
*entry
;
5737 if ((*str
)[0] == '#')
5742 /* Try to parse a group relocation. Anything else is an error. */
5743 if (find_group_reloc_table_entry (str
, &entry
) == FAIL
)
5745 inst
.error
= _("unknown group relocation");
5746 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5749 /* We now have the group relocation table entry corresponding to
5750 the name in the assembler source. Next, we parse the expression. */
5751 if (my_get_expression (&inst
.relocs
[0].exp
, str
, GE_NO_PREFIX
))
5752 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5754 /* Record the relocation type (always the ALU variant here). */
5755 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) entry
->alu_code
;
5756 gas_assert (inst
.relocs
[0].type
!= 0);
5758 return PARSE_OPERAND_SUCCESS
;
5761 return parse_shifter_operand (str
, i
) == SUCCESS
5762 ? PARSE_OPERAND_SUCCESS
: PARSE_OPERAND_FAIL
;
5764 /* Never reached. */
5767 /* Parse a Neon alignment expression. Information is written to
5768 inst.operands[i]. We assume the initial ':' has been skipped.
5770 align .imm = align << 8, .immisalign=1, .preind=0 */
5771 static parse_operand_result
5772 parse_neon_alignment (char **str
, int i
)
5777 my_get_expression (&exp
, &p
, GE_NO_PREFIX
);
5779 if (exp
.X_op
!= O_constant
)
5781 inst
.error
= _("alignment must be constant");
5782 return PARSE_OPERAND_FAIL
;
5785 inst
.operands
[i
].imm
= exp
.X_add_number
<< 8;
5786 inst
.operands
[i
].immisalign
= 1;
5787 /* Alignments are not pre-indexes. */
5788 inst
.operands
[i
].preind
= 0;
5791 return PARSE_OPERAND_SUCCESS
;
5794 /* Parse all forms of an ARM address expression. Information is written
5795 to inst.operands[i] and/or inst.relocs[0].
5797 Preindexed addressing (.preind=1):
5799 [Rn, #offset] .reg=Rn .relocs[0].exp=offset
5800 [Rn, +/-Rm] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5801 [Rn, +/-Rm, shift] .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5802 .shift_kind=shift .relocs[0].exp=shift_imm
5804 These three may have a trailing ! which causes .writeback to be set also.
5806 Postindexed addressing (.postind=1, .writeback=1):
5808 [Rn], #offset .reg=Rn .relocs[0].exp=offset
5809 [Rn], +/-Rm .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5810 [Rn], +/-Rm, shift .reg=Rn .imm=Rm .immisreg=1 .negative=0/1
5811 .shift_kind=shift .relocs[0].exp=shift_imm
5813 Unindexed addressing (.preind=0, .postind=0):
5815 [Rn], {option} .reg=Rn .imm=option .immisreg=0
5819 [Rn]{!} shorthand for [Rn,#0]{!}
5820 =immediate .isreg=0 .relocs[0].exp=immediate
5821 label .reg=PC .relocs[0].pc_rel=1 .relocs[0].exp=label
5823 It is the caller's responsibility to check for addressing modes not
5824 supported by the instruction, and to set inst.relocs[0].type. */
5826 static parse_operand_result
5827 parse_address_main (char **str
, int i
, int group_relocations
,
5828 group_reloc_type group_type
)
5833 if (skip_past_char (&p
, '[') == FAIL
)
5835 if (skip_past_char (&p
, '=') == FAIL
)
5837 /* Bare address - translate to PC-relative offset. */
5838 inst
.relocs
[0].pc_rel
= 1;
5839 inst
.operands
[i
].reg
= REG_PC
;
5840 inst
.operands
[i
].isreg
= 1;
5841 inst
.operands
[i
].preind
= 1;
5843 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_OPT_PREFIX_BIG
))
5844 return PARSE_OPERAND_FAIL
;
5846 else if (parse_big_immediate (&p
, i
, &inst
.relocs
[0].exp
,
5847 /*allow_symbol_p=*/TRUE
))
5848 return PARSE_OPERAND_FAIL
;
5851 return PARSE_OPERAND_SUCCESS
;
5854 /* PR gas/14887: Allow for whitespace after the opening bracket. */
5855 skip_whitespace (p
);
5857 if (group_type
== GROUP_MVE
)
5859 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5860 struct neon_type_el et
;
5861 if ((reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5863 inst
.operands
[i
].isquad
= 1;
5865 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5867 inst
.error
= BAD_ADDR_MODE
;
5868 return PARSE_OPERAND_FAIL
;
5871 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
5873 if (group_type
== GROUP_MVE
)
5874 inst
.error
= BAD_ADDR_MODE
;
5876 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
5877 return PARSE_OPERAND_FAIL
;
5879 inst
.operands
[i
].reg
= reg
;
5880 inst
.operands
[i
].isreg
= 1;
5882 if (skip_past_comma (&p
) == SUCCESS
)
5884 inst
.operands
[i
].preind
= 1;
5887 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
5889 enum arm_reg_type rtype
= REG_TYPE_MQ
;
5890 struct neon_type_el et
;
5891 if (group_type
== GROUP_MVE
5892 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
5894 inst
.operands
[i
].immisreg
= 2;
5895 inst
.operands
[i
].imm
= reg
;
5897 if (skip_past_comma (&p
) == SUCCESS
)
5899 if (parse_shift (&p
, i
, SHIFT_UXTW_IMMEDIATE
) == SUCCESS
)
5901 inst
.operands
[i
].imm
|= inst
.relocs
[0].exp
.X_add_number
<< 5;
5902 inst
.relocs
[0].exp
.X_add_number
= 0;
5905 return PARSE_OPERAND_FAIL
;
5908 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
5910 inst
.operands
[i
].imm
= reg
;
5911 inst
.operands
[i
].immisreg
= 1;
5913 if (skip_past_comma (&p
) == SUCCESS
)
5914 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
5915 return PARSE_OPERAND_FAIL
;
5917 else if (skip_past_char (&p
, ':') == SUCCESS
)
5919 /* FIXME: '@' should be used here, but it's filtered out by generic
5920 code before we get to see it here. This may be subject to
5922 parse_operand_result result
= parse_neon_alignment (&p
, i
);
5924 if (result
!= PARSE_OPERAND_SUCCESS
)
5929 if (inst
.operands
[i
].negative
)
5931 inst
.operands
[i
].negative
= 0;
5935 if (group_relocations
5936 && ((*p
== '#' && *(p
+ 1) == ':') || *p
== ':'))
5938 struct group_reloc_table_entry
*entry
;
5940 /* Skip over the #: or : sequence. */
5946 /* Try to parse a group relocation. Anything else is an
5948 if (find_group_reloc_table_entry (&p
, &entry
) == FAIL
)
5950 inst
.error
= _("unknown group relocation");
5951 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5954 /* We now have the group relocation table entry corresponding to
5955 the name in the assembler source. Next, we parse the
5957 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
5958 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5960 /* Record the relocation type. */
5965 = (bfd_reloc_code_real_type
) entry
->ldr_code
;
5970 = (bfd_reloc_code_real_type
) entry
->ldrs_code
;
5975 = (bfd_reloc_code_real_type
) entry
->ldc_code
;
5982 if (inst
.relocs
[0].type
== 0)
5984 inst
.error
= _("this group relocation is not allowed on this instruction");
5985 return PARSE_OPERAND_FAIL_NO_BACKTRACK
;
5992 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
5993 return PARSE_OPERAND_FAIL
;
5994 /* If the offset is 0, find out if it's a +0 or -0. */
5995 if (inst
.relocs
[0].exp
.X_op
== O_constant
5996 && inst
.relocs
[0].exp
.X_add_number
== 0)
5998 skip_whitespace (q
);
6002 skip_whitespace (q
);
6005 inst
.operands
[i
].negative
= 1;
6010 else if (skip_past_char (&p
, ':') == SUCCESS
)
6012 /* FIXME: '@' should be used here, but it's filtered out by generic code
6013 before we get to see it here. This may be subject to change. */
6014 parse_operand_result result
= parse_neon_alignment (&p
, i
);
6016 if (result
!= PARSE_OPERAND_SUCCESS
)
6020 if (skip_past_char (&p
, ']') == FAIL
)
6022 inst
.error
= _("']' expected");
6023 return PARSE_OPERAND_FAIL
;
6026 if (skip_past_char (&p
, '!') == SUCCESS
)
6027 inst
.operands
[i
].writeback
= 1;
6029 else if (skip_past_comma (&p
) == SUCCESS
)
6031 if (skip_past_char (&p
, '{') == SUCCESS
)
6033 /* [Rn], {expr} - unindexed, with option */
6034 if (parse_immediate (&p
, &inst
.operands
[i
].imm
,
6035 0, 255, TRUE
) == FAIL
)
6036 return PARSE_OPERAND_FAIL
;
6038 if (skip_past_char (&p
, '}') == FAIL
)
6040 inst
.error
= _("'}' expected at end of 'option' field");
6041 return PARSE_OPERAND_FAIL
;
6043 if (inst
.operands
[i
].preind
)
6045 inst
.error
= _("cannot combine index with option");
6046 return PARSE_OPERAND_FAIL
;
6049 return PARSE_OPERAND_SUCCESS
;
6053 inst
.operands
[i
].postind
= 1;
6054 inst
.operands
[i
].writeback
= 1;
6056 if (inst
.operands
[i
].preind
)
6058 inst
.error
= _("cannot combine pre- and post-indexing");
6059 return PARSE_OPERAND_FAIL
;
6063 else if (*p
== '-') p
++, inst
.operands
[i
].negative
= 1;
6065 enum arm_reg_type rtype
= REG_TYPE_MQ
;
6066 struct neon_type_el et
;
6067 if (group_type
== GROUP_MVE
6068 && (reg
= arm_typed_reg_parse (&p
, rtype
, &rtype
, &et
)) != FAIL
)
6070 inst
.operands
[i
].immisreg
= 2;
6071 inst
.operands
[i
].imm
= reg
;
6073 else if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) != FAIL
)
6075 /* We might be using the immediate for alignment already. If we
6076 are, OR the register number into the low-order bits. */
6077 if (inst
.operands
[i
].immisalign
)
6078 inst
.operands
[i
].imm
|= reg
;
6080 inst
.operands
[i
].imm
= reg
;
6081 inst
.operands
[i
].immisreg
= 1;
6083 if (skip_past_comma (&p
) == SUCCESS
)
6084 if (parse_shift (&p
, i
, SHIFT_IMMEDIATE
) == FAIL
)
6085 return PARSE_OPERAND_FAIL
;
6091 if (inst
.operands
[i
].negative
)
6093 inst
.operands
[i
].negative
= 0;
6096 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_IMM_PREFIX
))
6097 return PARSE_OPERAND_FAIL
;
6098 /* If the offset is 0, find out if it's a +0 or -0. */
6099 if (inst
.relocs
[0].exp
.X_op
== O_constant
6100 && inst
.relocs
[0].exp
.X_add_number
== 0)
6102 skip_whitespace (q
);
6106 skip_whitespace (q
);
6109 inst
.operands
[i
].negative
= 1;
6115 /* If at this point neither .preind nor .postind is set, we have a
6116 bare [Rn]{!}, which is shorthand for [Rn,#0]{!}. */
6117 if (inst
.operands
[i
].preind
== 0 && inst
.operands
[i
].postind
== 0)
6119 inst
.operands
[i
].preind
= 1;
6120 inst
.relocs
[0].exp
.X_op
= O_constant
;
6121 inst
.relocs
[0].exp
.X_add_number
= 0;
6124 return PARSE_OPERAND_SUCCESS
;
6128 parse_address (char **str
, int i
)
6130 return parse_address_main (str
, i
, 0, GROUP_LDR
) == PARSE_OPERAND_SUCCESS
6134 static parse_operand_result
6135 parse_address_group_reloc (char **str
, int i
, group_reloc_type type
)
6137 return parse_address_main (str
, i
, 1, type
);
6140 /* Parse an operand for a MOVW or MOVT instruction. */
6142 parse_half (char **str
)
6147 skip_past_char (&p
, '#');
6148 if (strncasecmp (p
, ":lower16:", 9) == 0)
6149 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVW
;
6150 else if (strncasecmp (p
, ":upper16:", 9) == 0)
6151 inst
.relocs
[0].type
= BFD_RELOC_ARM_MOVT
;
6153 if (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
)
6156 skip_whitespace (p
);
6159 if (my_get_expression (&inst
.relocs
[0].exp
, &p
, GE_NO_PREFIX
))
6162 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
6164 if (inst
.relocs
[0].exp
.X_op
!= O_constant
)
6166 inst
.error
= _("constant expression expected");
6169 if (inst
.relocs
[0].exp
.X_add_number
< 0
6170 || inst
.relocs
[0].exp
.X_add_number
> 0xffff)
6172 inst
.error
= _("immediate value out of range");
6180 /* Miscellaneous. */
6182 /* Parse a PSR flag operand. The value returned is FAIL on syntax error,
6183 or a bitmask suitable to be or-ed into the ARM msr instruction. */
6185 parse_psr (char **str
, bfd_boolean lhs
)
6188 unsigned long psr_field
;
6189 const struct asm_psr
*psr
;
6191 bfd_boolean is_apsr
= FALSE
;
6192 bfd_boolean m_profile
= ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
);
6194 /* PR gas/12698: If the user has specified -march=all then m_profile will
6195 be TRUE, but we want to ignore it in this case as we are building for any
6196 CPU type, including non-m variants. */
6197 if (ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
))
6200 /* CPSR's and SPSR's can now be lowercase. This is just a convenience
6201 feature for ease of use and backwards compatibility. */
6203 if (strncasecmp (p
, "SPSR", 4) == 0)
6206 goto unsupported_psr
;
6208 psr_field
= SPSR_BIT
;
6210 else if (strncasecmp (p
, "CPSR", 4) == 0)
6213 goto unsupported_psr
;
6217 else if (strncasecmp (p
, "APSR", 4) == 0)
6219 /* APSR[_<bits>] can be used as a synonym for CPSR[_<flags>] on ARMv7-A
6220 and ARMv7-R architecture CPUs. */
6229 while (ISALNUM (*p
) || *p
== '_');
6231 if (strncasecmp (start
, "iapsr", 5) == 0
6232 || strncasecmp (start
, "eapsr", 5) == 0
6233 || strncasecmp (start
, "xpsr", 4) == 0
6234 || strncasecmp (start
, "psr", 3) == 0)
6235 p
= start
+ strcspn (start
, "rR") + 1;
6237 psr
= (const struct asm_psr
*) hash_find_n (arm_v7m_psr_hsh
, start
,
6243 /* If APSR is being written, a bitfield may be specified. Note that
6244 APSR itself is handled above. */
6245 if (psr
->field
<= 3)
6247 psr_field
= psr
->field
;
6253 /* M-profile MSR instructions have the mask field set to "10", except
6254 *PSR variants which modify APSR, which may use a different mask (and
6255 have been handled already). Do that by setting the PSR_f field
6257 return psr
->field
| (lhs
? PSR_f
: 0);
6260 goto unsupported_psr
;
6266 /* A suffix follows. */
6272 while (ISALNUM (*p
) || *p
== '_');
6276 /* APSR uses a notation for bits, rather than fields. */
6277 unsigned int nzcvq_bits
= 0;
6278 unsigned int g_bit
= 0;
6281 for (bit
= start
; bit
!= p
; bit
++)
6283 switch (TOLOWER (*bit
))
6286 nzcvq_bits
|= (nzcvq_bits
& 0x01) ? 0x20 : 0x01;
6290 nzcvq_bits
|= (nzcvq_bits
& 0x02) ? 0x20 : 0x02;
6294 nzcvq_bits
|= (nzcvq_bits
& 0x04) ? 0x20 : 0x04;
6298 nzcvq_bits
|= (nzcvq_bits
& 0x08) ? 0x20 : 0x08;
6302 nzcvq_bits
|= (nzcvq_bits
& 0x10) ? 0x20 : 0x10;
6306 g_bit
|= (g_bit
& 0x1) ? 0x2 : 0x1;
6310 inst
.error
= _("unexpected bit specified after APSR");
6315 if (nzcvq_bits
== 0x1f)
6320 if (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
))
6322 inst
.error
= _("selected processor does not "
6323 "support DSP extension");
6330 if ((nzcvq_bits
& 0x20) != 0
6331 || (nzcvq_bits
!= 0x1f && nzcvq_bits
!= 0)
6332 || (g_bit
& 0x2) != 0)
6334 inst
.error
= _("bad bitmask specified after APSR");
6340 psr
= (const struct asm_psr
*) hash_find_n (arm_psr_hsh
, start
,
6345 psr_field
|= psr
->field
;
6351 goto error
; /* Garbage after "[CS]PSR". */
6353 /* Unadorned APSR is equivalent to APSR_nzcvq/CPSR_f (for writes). This
6354 is deprecated, but allow it anyway. */
6358 as_tsktsk (_("writing to APSR without specifying a bitmask is "
6361 else if (!m_profile
)
6362 /* These bits are never right for M-profile devices: don't set them
6363 (only code paths which read/write APSR reach here). */
6364 psr_field
|= (PSR_c
| PSR_f
);
6370 inst
.error
= _("selected processor does not support requested special "
6371 "purpose register");
6375 inst
.error
= _("flag for {c}psr instruction expected");
6380 parse_sys_vldr_vstr (char **str
)
6389 {"FPSCR", 0x1, 0x0},
6390 {"FPSCR_nzcvqc", 0x2, 0x0},
6393 {"FPCXTNS", 0x6, 0x1},
6394 {"FPCXTS", 0x7, 0x1}
6396 char *op_end
= strchr (*str
, ',');
6397 size_t op_strlen
= op_end
- *str
;
6399 for (i
= 0; i
< sizeof (sysregs
) / sizeof (sysregs
[0]); i
++)
6401 if (!strncmp (*str
, sysregs
[i
].name
, op_strlen
))
6403 val
= sysregs
[i
].regl
| (sysregs
[i
].regh
<< 3);
6412 /* Parse the flags argument to CPSI[ED]. Returns FAIL on error, or a
6413 value suitable for splatting into the AIF field of the instruction. */
6416 parse_cps_flags (char **str
)
6425 case '\0': case ',':
6428 case 'a': case 'A': saw_a_flag
= 1; val
|= 0x4; break;
6429 case 'i': case 'I': saw_a_flag
= 1; val
|= 0x2; break;
6430 case 'f': case 'F': saw_a_flag
= 1; val
|= 0x1; break;
6433 inst
.error
= _("unrecognized CPS flag");
6438 if (saw_a_flag
== 0)
6440 inst
.error
= _("missing CPS flags");
6448 /* Parse an endian specifier ("BE" or "LE", case insensitive);
6449 returns 0 for big-endian, 1 for little-endian, FAIL for an error. */
6452 parse_endian_specifier (char **str
)
6457 if (strncasecmp (s
, "BE", 2))
6459 else if (strncasecmp (s
, "LE", 2))
6463 inst
.error
= _("valid endian specifiers are be or le");
6467 if (ISALNUM (s
[2]) || s
[2] == '_')
6469 inst
.error
= _("valid endian specifiers are be or le");
6474 return little_endian
;
6477 /* Parse a rotation specifier: ROR #0, #8, #16, #24. *val receives a
6478 value suitable for poking into the rotate field of an sxt or sxta
6479 instruction, or FAIL on error. */
6482 parse_ror (char **str
)
6487 if (strncasecmp (s
, "ROR", 3) == 0)
6491 inst
.error
= _("missing rotation field after comma");
6495 if (parse_immediate (&s
, &rot
, 0, 24, FALSE
) == FAIL
)
6500 case 0: *str
= s
; return 0x0;
6501 case 8: *str
= s
; return 0x1;
6502 case 16: *str
= s
; return 0x2;
6503 case 24: *str
= s
; return 0x3;
6506 inst
.error
= _("rotation can only be 0, 8, 16, or 24");
6511 /* Parse a conditional code (from conds[] below). The value returned is in the
6512 range 0 .. 14, or FAIL. */
6514 parse_cond (char **str
)
6517 const struct asm_cond
*c
;
6519 /* Condition codes are always 2 characters, so matching up to
6520 3 characters is sufficient. */
6525 while (ISALPHA (*q
) && n
< 3)
6527 cond
[n
] = TOLOWER (*q
);
6532 c
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, cond
, n
);
6535 inst
.error
= _("condition required");
6543 /* Parse an option for a barrier instruction. Returns the encoding for the
6546 parse_barrier (char **str
)
6549 const struct asm_barrier_opt
*o
;
6552 while (ISALPHA (*q
))
6555 o
= (const struct asm_barrier_opt
*) hash_find_n (arm_barrier_opt_hsh
, p
,
6560 if (!mark_feature_used (&o
->arch
))
6567 /* Parse the operands of a table branch instruction. Similar to a memory
6570 parse_tb (char **str
)
6575 if (skip_past_char (&p
, '[') == FAIL
)
6577 inst
.error
= _("'[' expected");
6581 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6583 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6586 inst
.operands
[0].reg
= reg
;
6588 if (skip_past_comma (&p
) == FAIL
)
6590 inst
.error
= _("',' expected");
6594 if ((reg
= arm_reg_parse (&p
, REG_TYPE_RN
)) == FAIL
)
6596 inst
.error
= _(reg_expected_msgs
[REG_TYPE_RN
]);
6599 inst
.operands
[0].imm
= reg
;
6601 if (skip_past_comma (&p
) == SUCCESS
)
6603 if (parse_shift (&p
, 0, SHIFT_LSL_IMMEDIATE
) == FAIL
)
6605 if (inst
.relocs
[0].exp
.X_add_number
!= 1)
6607 inst
.error
= _("invalid shift");
6610 inst
.operands
[0].shifted
= 1;
6613 if (skip_past_char (&p
, ']') == FAIL
)
6615 inst
.error
= _("']' expected");
6622 /* Parse the operands of a Neon VMOV instruction. See do_neon_mov for more
6623 information on the types the operands can take and how they are encoded.
6624 Up to four operands may be read; this function handles setting the
6625 ".present" field for each read operand itself.
6626 Updates STR and WHICH_OPERAND if parsing is successful and returns SUCCESS,
6627 else returns FAIL. */
6630 parse_neon_mov (char **str
, int *which_operand
)
6632 int i
= *which_operand
, val
;
6633 enum arm_reg_type rtype
;
6635 struct neon_type_el optype
;
6637 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6639 /* Cases 17 or 19. */
6640 inst
.operands
[i
].reg
= val
;
6641 inst
.operands
[i
].isvec
= 1;
6642 inst
.operands
[i
].isscalar
= 2;
6643 inst
.operands
[i
].vectype
= optype
;
6644 inst
.operands
[i
++].present
= 1;
6646 if (skip_past_comma (&ptr
) == FAIL
)
6649 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6651 /* Case 17: VMOV<c>.<dt> <Qd[idx]>, <Rt> */
6652 inst
.operands
[i
].reg
= val
;
6653 inst
.operands
[i
].isreg
= 1;
6654 inst
.operands
[i
].present
= 1;
6656 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6658 /* Case 19: VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2> */
6659 inst
.operands
[i
].reg
= val
;
6660 inst
.operands
[i
].isvec
= 1;
6661 inst
.operands
[i
].isscalar
= 2;
6662 inst
.operands
[i
].vectype
= optype
;
6663 inst
.operands
[i
++].present
= 1;
6665 if (skip_past_comma (&ptr
) == FAIL
)
6668 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6671 inst
.operands
[i
].reg
= val
;
6672 inst
.operands
[i
].isreg
= 1;
6673 inst
.operands
[i
++].present
= 1;
6675 if (skip_past_comma (&ptr
) == FAIL
)
6678 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6681 inst
.operands
[i
].reg
= val
;
6682 inst
.operands
[i
].isreg
= 1;
6683 inst
.operands
[i
].present
= 1;
6687 first_error (_("expected ARM or MVE vector register"));
6691 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6693 /* Case 4: VMOV<c><q>.<size> <Dn[x]>, <Rd>. */
6694 inst
.operands
[i
].reg
= val
;
6695 inst
.operands
[i
].isscalar
= 1;
6696 inst
.operands
[i
].vectype
= optype
;
6697 inst
.operands
[i
++].present
= 1;
6699 if (skip_past_comma (&ptr
) == FAIL
)
6702 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6705 inst
.operands
[i
].reg
= val
;
6706 inst
.operands
[i
].isreg
= 1;
6707 inst
.operands
[i
].present
= 1;
6709 else if (((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
, &optype
))
6711 || ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_MQ
, &rtype
, &optype
))
6714 /* Cases 0, 1, 2, 3, 5 (D only). */
6715 if (skip_past_comma (&ptr
) == FAIL
)
6718 inst
.operands
[i
].reg
= val
;
6719 inst
.operands
[i
].isreg
= 1;
6720 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6721 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6722 inst
.operands
[i
].isvec
= 1;
6723 inst
.operands
[i
].vectype
= optype
;
6724 inst
.operands
[i
++].present
= 1;
6726 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6728 /* Case 5: VMOV<c><q> <Dm>, <Rd>, <Rn>.
6729 Case 13: VMOV <Sd>, <Rm> */
6730 inst
.operands
[i
].reg
= val
;
6731 inst
.operands
[i
].isreg
= 1;
6732 inst
.operands
[i
].present
= 1;
6734 if (rtype
== REG_TYPE_NQ
)
6736 first_error (_("can't use Neon quad register here"));
6739 else if (rtype
!= REG_TYPE_VFS
)
6742 if (skip_past_comma (&ptr
) == FAIL
)
6744 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6746 inst
.operands
[i
].reg
= val
;
6747 inst
.operands
[i
].isreg
= 1;
6748 inst
.operands
[i
].present
= 1;
6751 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_NSDQ
, &rtype
,
6754 /* Case 0: VMOV<c><q> <Qd>, <Qm>
6755 Case 1: VMOV<c><q> <Dd>, <Dm>
6756 Case 8: VMOV.F32 <Sd>, <Sm>
6757 Case 15: VMOV <Sd>, <Se>, <Rn>, <Rm> */
6759 inst
.operands
[i
].reg
= val
;
6760 inst
.operands
[i
].isreg
= 1;
6761 inst
.operands
[i
].isquad
= (rtype
== REG_TYPE_NQ
);
6762 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6763 inst
.operands
[i
].isvec
= 1;
6764 inst
.operands
[i
].vectype
= optype
;
6765 inst
.operands
[i
].present
= 1;
6767 if (skip_past_comma (&ptr
) == SUCCESS
)
6772 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6775 inst
.operands
[i
].reg
= val
;
6776 inst
.operands
[i
].isreg
= 1;
6777 inst
.operands
[i
++].present
= 1;
6779 if (skip_past_comma (&ptr
) == FAIL
)
6782 if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) == FAIL
)
6785 inst
.operands
[i
].reg
= val
;
6786 inst
.operands
[i
].isreg
= 1;
6787 inst
.operands
[i
].present
= 1;
6790 else if (parse_qfloat_immediate (&ptr
, &inst
.operands
[i
].imm
) == SUCCESS
)
6791 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<float-imm>
6792 Case 3: VMOV<c><q>.<dt> <Dd>, #<float-imm>
6793 Case 10: VMOV.F32 <Sd>, #<imm>
6794 Case 11: VMOV.F64 <Dd>, #<imm> */
6795 inst
.operands
[i
].immisfloat
= 1;
6796 else if (parse_big_immediate (&ptr
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
6798 /* Case 2: VMOV<c><q>.<dt> <Qd>, #<imm>
6799 Case 3: VMOV<c><q>.<dt> <Dd>, #<imm> */
6803 first_error (_("expected <Rm> or <Dm> or <Qm> operand"));
6807 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6809 /* Cases 6, 7, 16, 18. */
6810 inst
.operands
[i
].reg
= val
;
6811 inst
.operands
[i
].isreg
= 1;
6812 inst
.operands
[i
++].present
= 1;
6814 if (skip_past_comma (&ptr
) == FAIL
)
6817 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
)) != FAIL
)
6819 /* Case 18: VMOV<c>.<dt> <Rt>, <Qn[idx]> */
6820 inst
.operands
[i
].reg
= val
;
6821 inst
.operands
[i
].isscalar
= 2;
6822 inst
.operands
[i
].present
= 1;
6823 inst
.operands
[i
].vectype
= optype
;
6825 else if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_VFD
)) != FAIL
)
6827 /* Case 6: VMOV<c><q>.<dt> <Rd>, <Dn[x]> */
6828 inst
.operands
[i
].reg
= val
;
6829 inst
.operands
[i
].isscalar
= 1;
6830 inst
.operands
[i
].present
= 1;
6831 inst
.operands
[i
].vectype
= optype
;
6833 else if ((val
= arm_reg_parse (&ptr
, REG_TYPE_RN
)) != FAIL
)
6835 inst
.operands
[i
].reg
= val
;
6836 inst
.operands
[i
].isreg
= 1;
6837 inst
.operands
[i
++].present
= 1;
6839 if (skip_past_comma (&ptr
) == FAIL
)
6842 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFSD
, &rtype
, &optype
))
6845 /* Case 7: VMOV<c><q> <Rd>, <Rn>, <Dm> */
6847 inst
.operands
[i
].reg
= val
;
6848 inst
.operands
[i
].isreg
= 1;
6849 inst
.operands
[i
].isvec
= 1;
6850 inst
.operands
[i
].issingle
= (rtype
== REG_TYPE_VFS
);
6851 inst
.operands
[i
].vectype
= optype
;
6852 inst
.operands
[i
].present
= 1;
6854 if (rtype
== REG_TYPE_VFS
)
6858 if (skip_past_comma (&ptr
) == FAIL
)
6860 if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
,
6863 first_error (_(reg_expected_msgs
[REG_TYPE_VFS
]));
6866 inst
.operands
[i
].reg
= val
;
6867 inst
.operands
[i
].isreg
= 1;
6868 inst
.operands
[i
].isvec
= 1;
6869 inst
.operands
[i
].issingle
= 1;
6870 inst
.operands
[i
].vectype
= optype
;
6871 inst
.operands
[i
].present
= 1;
6876 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6879 /* Case 16: VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]> */
6880 inst
.operands
[i
].reg
= val
;
6881 inst
.operands
[i
].isvec
= 1;
6882 inst
.operands
[i
].isscalar
= 2;
6883 inst
.operands
[i
].vectype
= optype
;
6884 inst
.operands
[i
++].present
= 1;
6886 if (skip_past_comma (&ptr
) == FAIL
)
6889 if ((val
= parse_scalar (&ptr
, 8, &optype
, REG_TYPE_MQ
))
6892 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
6895 inst
.operands
[i
].reg
= val
;
6896 inst
.operands
[i
].isvec
= 1;
6897 inst
.operands
[i
].isscalar
= 2;
6898 inst
.operands
[i
].vectype
= optype
;
6899 inst
.operands
[i
].present
= 1;
6903 first_error (_("VFP single, double or MVE vector register"
6909 else if ((val
= arm_typed_reg_parse (&ptr
, REG_TYPE_VFS
, NULL
, &optype
))
6913 inst
.operands
[i
].reg
= val
;
6914 inst
.operands
[i
].isreg
= 1;
6915 inst
.operands
[i
].isvec
= 1;
6916 inst
.operands
[i
].issingle
= 1;
6917 inst
.operands
[i
].vectype
= optype
;
6918 inst
.operands
[i
].present
= 1;
6923 first_error (_("parse error"));
6927 /* Successfully parsed the operands. Update args. */
6933 first_error (_("expected comma"));
6937 first_error (_(reg_expected_msgs
[REG_TYPE_RN
]));
6941 /* Use this macro when the operand constraints are different
6942 for ARM and THUMB (e.g. ldrd). */
6943 #define MIX_ARM_THUMB_OPERANDS(arm_operand, thumb_operand) \
6944 ((arm_operand) | ((thumb_operand) << 16))
6946 /* Matcher codes for parse_operands. */
6947 enum operand_parse_code
6949 OP_stop
, /* end of line */
6951 OP_RR
, /* ARM register */
6952 OP_RRnpc
, /* ARM register, not r15 */
6953 OP_RRnpcsp
, /* ARM register, neither r15 nor r13 (a.k.a. 'BadReg') */
6954 OP_RRnpcb
, /* ARM register, not r15, in square brackets */
6955 OP_RRnpctw
, /* ARM register, not r15 in Thumb-state or with writeback,
6956 optional trailing ! */
6957 OP_RRw
, /* ARM register, not r15, optional trailing ! */
6958 OP_RCP
, /* Coprocessor number */
6959 OP_RCN
, /* Coprocessor register */
6960 OP_RF
, /* FPA register */
6961 OP_RVS
, /* VFP single precision register */
6962 OP_RVD
, /* VFP double precision register (0..15) */
6963 OP_RND
, /* Neon double precision register (0..31) */
6964 OP_RNDMQ
, /* Neon double precision (0..31) or MVE vector register. */
6965 OP_RNDMQR
, /* Neon double precision (0..31), MVE vector or ARM register.
6967 OP_RNQ
, /* Neon quad precision register */
6968 OP_RNQMQ
, /* Neon quad or MVE vector register. */
6969 OP_RVSD
, /* VFP single or double precision register */
6970 OP_RVSD_COND
, /* VFP single, double precision register or condition code. */
6971 OP_RVSDMQ
, /* VFP single, double precision or MVE vector register. */
6972 OP_RNSD
, /* Neon single or double precision register */
6973 OP_RNDQ
, /* Neon double or quad precision register */
6974 OP_RNDQMQ
, /* Neon double, quad or MVE vector register. */
6975 OP_RNDQMQR
, /* Neon double, quad, MVE vector or ARM register. */
6976 OP_RNSDQ
, /* Neon single, double or quad precision register */
6977 OP_RNSC
, /* Neon scalar D[X] */
6978 OP_RVC
, /* VFP control register */
6979 OP_RMF
, /* Maverick F register */
6980 OP_RMD
, /* Maverick D register */
6981 OP_RMFX
, /* Maverick FX register */
6982 OP_RMDX
, /* Maverick DX register */
6983 OP_RMAX
, /* Maverick AX register */
6984 OP_RMDS
, /* Maverick DSPSC register */
6985 OP_RIWR
, /* iWMMXt wR register */
6986 OP_RIWC
, /* iWMMXt wC register */
6987 OP_RIWG
, /* iWMMXt wCG register */
6988 OP_RXA
, /* XScale accumulator register */
6990 OP_RNSDQMQ
, /* Neon single, double or quad register or MVE vector register
6992 OP_RNSDQMQR
, /* Neon single, double or quad register, MVE vector register or
6994 OP_RMQ
, /* MVE vector register. */
6995 OP_RMQRZ
, /* MVE vector or ARM register including ZR. */
6996 OP_RMQRR
, /* MVE vector or ARM register. */
6998 /* New operands for Armv8.1-M Mainline. */
6999 OP_LR
, /* ARM LR register */
7000 OP_RRe
, /* ARM register, only even numbered. */
7001 OP_RRo
, /* ARM register, only odd numbered, not r13 or r15. */
7002 OP_RRnpcsp_I32
, /* ARM register (no BadReg) or literal 1 .. 32 */
7003 OP_RR_ZR
, /* ARM register or ZR but no PC */
7005 OP_REGLST
, /* ARM register list */
7006 OP_CLRMLST
, /* CLRM register list */
7007 OP_VRSLST
, /* VFP single-precision register list */
7008 OP_VRDLST
, /* VFP double-precision register list */
7009 OP_VRSDLST
, /* VFP single or double-precision register list (& quad) */
7010 OP_NRDLST
, /* Neon double-precision register list (d0-d31, qN aliases) */
7011 OP_NSTRLST
, /* Neon element/structure list */
7012 OP_VRSDVLST
, /* VFP single or double-precision register list and VPR */
7013 OP_MSTRLST2
, /* MVE vector list with two elements. */
7014 OP_MSTRLST4
, /* MVE vector list with four elements. */
7016 OP_RNDQ_I0
, /* Neon D or Q reg, or immediate zero. */
7017 OP_RVSD_I0
, /* VFP S or D reg, or immediate zero. */
7018 OP_RSVD_FI0
, /* VFP S or D reg, or floating point immediate zero. */
7019 OP_RSVDMQ_FI0
, /* VFP S, D, MVE vector register or floating point immediate
7021 OP_RR_RNSC
, /* ARM reg or Neon scalar. */
7022 OP_RNSD_RNSC
, /* Neon S or D reg, or Neon scalar. */
7023 OP_RNSDQ_RNSC
, /* Vector S, D or Q reg, or Neon scalar. */
7024 OP_RNSDQ_RNSC_MQ
, /* Vector S, D or Q reg, Neon scalar or MVE vector register.
7026 OP_RNSDQ_RNSC_MQ_RR
, /* Vector S, D or Q reg, or MVE vector reg , or Neon
7027 scalar, or ARM register. */
7028 OP_RNDQ_RNSC
, /* Neon D or Q reg, or Neon scalar. */
7029 OP_RNDQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, or ARM register. */
7030 OP_RNDQMQ_RNSC_RR
, /* Neon D or Q reg, Neon scalar, MVE vector or ARM
7032 OP_RNDQMQ_RNSC
, /* Neon D, Q or MVE vector reg, or Neon scalar. */
7033 OP_RND_RNSC
, /* Neon D reg, or Neon scalar. */
7034 OP_VMOV
, /* Neon VMOV operands. */
7035 OP_RNDQ_Ibig
, /* Neon D or Q reg, or big immediate for logic and VMVN. */
7036 /* Neon D, Q or MVE vector register, or big immediate for logic and VMVN. */
7038 OP_RNDQ_I63b
, /* Neon D or Q reg, or immediate for shift. */
7039 OP_RNDQMQ_I63b_RR
, /* Neon D or Q reg, immediate for shift, MVE vector or
7041 OP_RIWR_I32z
, /* iWMMXt wR register, or immediate 0 .. 32 for iWMMXt2. */
7042 OP_VLDR
, /* VLDR operand. */
7044 OP_I0
, /* immediate zero */
7045 OP_I7
, /* immediate value 0 .. 7 */
7046 OP_I15
, /* 0 .. 15 */
7047 OP_I16
, /* 1 .. 16 */
7048 OP_I16z
, /* 0 .. 16 */
7049 OP_I31
, /* 0 .. 31 */
7050 OP_I31w
, /* 0 .. 31, optional trailing ! */
7051 OP_I32
, /* 1 .. 32 */
7052 OP_I32z
, /* 0 .. 32 */
7053 OP_I63
, /* 0 .. 63 */
7054 OP_I63s
, /* -64 .. 63 */
7055 OP_I64
, /* 1 .. 64 */
7056 OP_I64z
, /* 0 .. 64 */
7057 OP_I255
, /* 0 .. 255 */
7059 OP_I4b
, /* immediate, prefix optional, 1 .. 4 */
7060 OP_I7b
, /* 0 .. 7 */
7061 OP_I15b
, /* 0 .. 15 */
7062 OP_I31b
, /* 0 .. 31 */
7064 OP_SH
, /* shifter operand */
7065 OP_SHG
, /* shifter operand with possible group relocation */
7066 OP_ADDR
, /* Memory address expression (any mode) */
7067 OP_ADDRMVE
, /* Memory address expression for MVE's VSTR/VLDR. */
7068 OP_ADDRGLDR
, /* Mem addr expr (any mode) with possible LDR group reloc */
7069 OP_ADDRGLDRS
, /* Mem addr expr (any mode) with possible LDRS group reloc */
7070 OP_ADDRGLDC
, /* Mem addr expr (any mode) with possible LDC group reloc */
7071 OP_EXP
, /* arbitrary expression */
7072 OP_EXPi
, /* same, with optional immediate prefix */
7073 OP_EXPr
, /* same, with optional relocation suffix */
7074 OP_EXPs
, /* same, with optional non-first operand relocation suffix */
7075 OP_HALF
, /* 0 .. 65535 or low/high reloc. */
7076 OP_IROT1
, /* VCADD rotate immediate: 90, 270. */
7077 OP_IROT2
, /* VCMLA rotate immediate: 0, 90, 180, 270. */
7079 OP_CPSF
, /* CPS flags */
7080 OP_ENDI
, /* Endianness specifier */
7081 OP_wPSR
, /* CPSR/SPSR/APSR mask for msr (writing). */
7082 OP_rPSR
, /* CPSR/SPSR/APSR mask for msr (reading). */
7083 OP_COND
, /* conditional code */
7084 OP_TB
, /* Table branch. */
7086 OP_APSR_RR
, /* ARM register or "APSR_nzcv". */
7088 OP_RRnpc_I0
, /* ARM register or literal 0 */
7089 OP_RR_EXr
, /* ARM register or expression with opt. reloc stuff. */
7090 OP_RR_EXi
, /* ARM register or expression with imm prefix */
7091 OP_RF_IF
, /* FPA register or immediate */
7092 OP_RIWR_RIWC
, /* iWMMXt R or C reg */
7093 OP_RIWC_RIWG
, /* iWMMXt wC or wCG reg */
7095 /* Optional operands. */
7096 OP_oI7b
, /* immediate, prefix optional, 0 .. 7 */
7097 OP_oI31b
, /* 0 .. 31 */
7098 OP_oI32b
, /* 1 .. 32 */
7099 OP_oI32z
, /* 0 .. 32 */
7100 OP_oIffffb
, /* 0 .. 65535 */
7101 OP_oI255c
, /* curly-brace enclosed, 0 .. 255 */
7103 OP_oRR
, /* ARM register */
7104 OP_oLR
, /* ARM LR register */
7105 OP_oRRnpc
, /* ARM register, not the PC */
7106 OP_oRRnpcsp
, /* ARM register, neither the PC nor the SP (a.k.a. BadReg) */
7107 OP_oRRw
, /* ARM register, not r15, optional trailing ! */
7108 OP_oRND
, /* Optional Neon double precision register */
7109 OP_oRNQ
, /* Optional Neon quad precision register */
7110 OP_oRNDQMQ
, /* Optional Neon double, quad or MVE vector register. */
7111 OP_oRNDQ
, /* Optional Neon double or quad precision register */
7112 OP_oRNSDQ
, /* Optional single, double or quad precision vector register */
7113 OP_oRNSDQMQ
, /* Optional single, double or quad register or MVE vector
7115 OP_oSHll
, /* LSL immediate */
7116 OP_oSHar
, /* ASR immediate */
7117 OP_oSHllar
, /* LSL or ASR immediate */
7118 OP_oROR
, /* ROR 0/8/16/24 */
7119 OP_oBARRIER_I15
, /* Option argument for a barrier instruction. */
7121 OP_oRMQRZ
, /* optional MVE vector or ARM register including ZR. */
7123 /* Some pre-defined mixed (ARM/THUMB) operands. */
7124 OP_RR_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RR
, OP_RRnpcsp
),
7125 OP_RRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_RRnpc
, OP_RRnpcsp
),
7126 OP_oRRnpc_npcsp
= MIX_ARM_THUMB_OPERANDS (OP_oRRnpc
, OP_oRRnpcsp
),
7128 OP_FIRST_OPTIONAL
= OP_oI7b
7131 /* Generic instruction operand parser. This does no encoding and no
7132 semantic validation; it merely squirrels values away in the inst
7133 structure. Returns SUCCESS or FAIL depending on whether the
7134 specified grammar matched. */
7136 parse_operands (char *str
, const unsigned int *pattern
, bfd_boolean thumb
)
7138 unsigned const int *upat
= pattern
;
7139 char *backtrack_pos
= 0;
7140 const char *backtrack_error
= 0;
7141 int i
, val
= 0, backtrack_index
= 0;
7142 enum arm_reg_type rtype
;
7143 parse_operand_result result
;
7144 unsigned int op_parse_code
;
7145 bfd_boolean partial_match
;
7147 #define po_char_or_fail(chr) \
7150 if (skip_past_char (&str, chr) == FAIL) \
7155 #define po_reg_or_fail(regtype) \
7158 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7159 & inst.operands[i].vectype); \
7162 first_error (_(reg_expected_msgs[regtype])); \
7165 inst.operands[i].reg = val; \
7166 inst.operands[i].isreg = 1; \
7167 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7168 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7169 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7170 || rtype == REG_TYPE_VFD \
7171 || rtype == REG_TYPE_NQ); \
7172 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7176 #define po_reg_or_goto(regtype, label) \
7179 val = arm_typed_reg_parse (& str, regtype, & rtype, \
7180 & inst.operands[i].vectype); \
7184 inst.operands[i].reg = val; \
7185 inst.operands[i].isreg = 1; \
7186 inst.operands[i].isquad = (rtype == REG_TYPE_NQ); \
7187 inst.operands[i].issingle = (rtype == REG_TYPE_VFS); \
7188 inst.operands[i].isvec = (rtype == REG_TYPE_VFS \
7189 || rtype == REG_TYPE_VFD \
7190 || rtype == REG_TYPE_NQ); \
7191 inst.operands[i].iszr = (rtype == REG_TYPE_ZR); \
7195 #define po_imm_or_fail(min, max, popt) \
7198 if (parse_immediate (&str, &val, min, max, popt) == FAIL) \
7200 inst.operands[i].imm = val; \
7204 #define po_scalar_or_goto(elsz, label, reg_type) \
7207 val = parse_scalar (& str, elsz, & inst.operands[i].vectype, \
7211 inst.operands[i].reg = val; \
7212 inst.operands[i].isscalar = 1; \
7216 #define po_misc_or_fail(expr) \
7224 #define po_misc_or_fail_no_backtrack(expr) \
7228 if (result == PARSE_OPERAND_FAIL_NO_BACKTRACK) \
7229 backtrack_pos = 0; \
7230 if (result != PARSE_OPERAND_SUCCESS) \
7235 #define po_barrier_or_imm(str) \
7238 val = parse_barrier (&str); \
7239 if (val == FAIL && ! ISALPHA (*str)) \
7242 /* ISB can only take SY as an option. */ \
7243 || ((inst.instruction & 0xf0) == 0x60 \
7246 inst.error = _("invalid barrier type"); \
7247 backtrack_pos = 0; \
7253 skip_whitespace (str
);
7255 for (i
= 0; upat
[i
] != OP_stop
; i
++)
7257 op_parse_code
= upat
[i
];
7258 if (op_parse_code
>= 1<<16)
7259 op_parse_code
= thumb
? (op_parse_code
>> 16)
7260 : (op_parse_code
& ((1<<16)-1));
7262 if (op_parse_code
>= OP_FIRST_OPTIONAL
)
7264 /* Remember where we are in case we need to backtrack. */
7265 backtrack_pos
= str
;
7266 backtrack_error
= inst
.error
;
7267 backtrack_index
= i
;
7270 if (i
> 0 && (i
> 1 || inst
.operands
[0].present
))
7271 po_char_or_fail (',');
7273 switch (op_parse_code
)
7285 case OP_RR
: po_reg_or_fail (REG_TYPE_RN
); break;
7286 case OP_RCP
: po_reg_or_fail (REG_TYPE_CP
); break;
7287 case OP_RCN
: po_reg_or_fail (REG_TYPE_CN
); break;
7288 case OP_RF
: po_reg_or_fail (REG_TYPE_FN
); break;
7289 case OP_RVS
: po_reg_or_fail (REG_TYPE_VFS
); break;
7290 case OP_RVD
: po_reg_or_fail (REG_TYPE_VFD
); break;
7293 po_reg_or_goto (REG_TYPE_RN
, try_rndmq
);
7297 po_reg_or_goto (REG_TYPE_MQ
, try_rnd
);
7300 case OP_RND
: po_reg_or_fail (REG_TYPE_VFD
); break;
7302 po_reg_or_goto (REG_TYPE_VFC
, coproc_reg
);
7304 /* Also accept generic coprocessor regs for unknown registers. */
7306 po_reg_or_goto (REG_TYPE_CN
, vpr_po
);
7308 /* Also accept P0 or p0 for VPR.P0. Since P0 is already an
7309 existing register with a value of 0, this seems like the
7310 best way to parse P0. */
7312 if (strncasecmp (str
, "P0", 2) == 0)
7315 inst
.operands
[i
].isreg
= 1;
7316 inst
.operands
[i
].reg
= 13;
7321 case OP_RMF
: po_reg_or_fail (REG_TYPE_MVF
); break;
7322 case OP_RMD
: po_reg_or_fail (REG_TYPE_MVD
); break;
7323 case OP_RMFX
: po_reg_or_fail (REG_TYPE_MVFX
); break;
7324 case OP_RMDX
: po_reg_or_fail (REG_TYPE_MVDX
); break;
7325 case OP_RMAX
: po_reg_or_fail (REG_TYPE_MVAX
); break;
7326 case OP_RMDS
: po_reg_or_fail (REG_TYPE_DSPSC
); break;
7327 case OP_RIWR
: po_reg_or_fail (REG_TYPE_MMXWR
); break;
7328 case OP_RIWC
: po_reg_or_fail (REG_TYPE_MMXWC
); break;
7329 case OP_RIWG
: po_reg_or_fail (REG_TYPE_MMXWCG
); break;
7330 case OP_RXA
: po_reg_or_fail (REG_TYPE_XSCALE
); break;
7333 po_reg_or_goto (REG_TYPE_MQ
, try_nq
);
7336 case OP_RNQ
: po_reg_or_fail (REG_TYPE_NQ
); break;
7337 case OP_RNSD
: po_reg_or_fail (REG_TYPE_NSD
); break;
7339 po_reg_or_goto (REG_TYPE_RN
, try_rndqmq
);
7344 po_reg_or_goto (REG_TYPE_MQ
, try_rndq
);
7348 case OP_RNDQ
: po_reg_or_fail (REG_TYPE_NDQ
); break;
7350 po_reg_or_goto (REG_TYPE_MQ
, try_rvsd
);
7353 case OP_RVSD
: po_reg_or_fail (REG_TYPE_VFSD
); break;
7355 po_reg_or_goto (REG_TYPE_VFSD
, try_cond
);
7358 case OP_RNSDQ
: po_reg_or_fail (REG_TYPE_NSDQ
); break;
7360 po_reg_or_goto (REG_TYPE_RN
, try_mq
);
7365 po_reg_or_goto (REG_TYPE_MQ
, try_nsdq2
);
7368 po_reg_or_fail (REG_TYPE_NSDQ
);
7372 po_reg_or_goto (REG_TYPE_RN
, try_rmq
);
7376 po_reg_or_fail (REG_TYPE_MQ
);
7378 /* Neon scalar. Using an element size of 8 means that some invalid
7379 scalars are accepted here, so deal with those in later code. */
7380 case OP_RNSC
: po_scalar_or_goto (8, failure
, REG_TYPE_VFD
); break;
7384 po_reg_or_goto (REG_TYPE_NDQ
, try_imm0
);
7387 po_imm_or_fail (0, 0, TRUE
);
7392 po_reg_or_goto (REG_TYPE_VFSD
, try_imm0
);
7396 po_reg_or_goto (REG_TYPE_MQ
, try_rsvd_fi0
);
7401 po_reg_or_goto (REG_TYPE_VFSD
, try_ifimm0
);
7404 if (parse_ifimm_zero (&str
))
7405 inst
.operands
[i
].imm
= 0;
7409 = _("only floating point zero is allowed as immediate value");
7417 po_scalar_or_goto (8, try_rr
, REG_TYPE_VFD
);
7420 po_reg_or_fail (REG_TYPE_RN
);
7424 case OP_RNSDQ_RNSC_MQ_RR
:
7425 po_reg_or_goto (REG_TYPE_RN
, try_rnsdq_rnsc_mq
);
7428 case OP_RNSDQ_RNSC_MQ
:
7429 po_reg_or_goto (REG_TYPE_MQ
, try_rnsdq_rnsc
);
7434 po_scalar_or_goto (8, try_nsdq
, REG_TYPE_VFD
);
7438 po_reg_or_fail (REG_TYPE_NSDQ
);
7445 po_scalar_or_goto (8, try_s_scalar
, REG_TYPE_VFD
);
7448 po_scalar_or_goto (4, try_nsd
, REG_TYPE_VFS
);
7451 po_reg_or_fail (REG_TYPE_NSD
);
7455 case OP_RNDQMQ_RNSC_RR
:
7456 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc_rr
);
7459 case OP_RNDQ_RNSC_RR
:
7460 po_reg_or_goto (REG_TYPE_RN
, try_rndq_rnsc
);
7462 case OP_RNDQMQ_RNSC
:
7463 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_rnsc
);
7468 po_scalar_or_goto (8, try_ndq
, REG_TYPE_VFD
);
7471 po_reg_or_fail (REG_TYPE_NDQ
);
7477 po_scalar_or_goto (8, try_vfd
, REG_TYPE_VFD
);
7480 po_reg_or_fail (REG_TYPE_VFD
);
7485 /* WARNING: parse_neon_mov can move the operand counter, i. If we're
7486 not careful then bad things might happen. */
7487 po_misc_or_fail (parse_neon_mov (&str
, &i
) == FAIL
);
7490 case OP_RNDQMQ_Ibig
:
7491 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_ibig
);
7496 po_reg_or_goto (REG_TYPE_NDQ
, try_immbig
);
7499 /* There's a possibility of getting a 64-bit immediate here, so
7500 we need special handling. */
7501 if (parse_big_immediate (&str
, i
, NULL
, /*allow_symbol_p=*/FALSE
)
7504 inst
.error
= _("immediate value is out of range");
7510 case OP_RNDQMQ_I63b_RR
:
7511 po_reg_or_goto (REG_TYPE_MQ
, try_rndq_i63b_rr
);
7514 po_reg_or_goto (REG_TYPE_RN
, try_rndq_i63b
);
7519 po_reg_or_goto (REG_TYPE_NDQ
, try_shimm
);
7522 po_imm_or_fail (0, 63, TRUE
);
7527 po_char_or_fail ('[');
7528 po_reg_or_fail (REG_TYPE_RN
);
7529 po_char_or_fail (']');
7535 po_reg_or_fail (REG_TYPE_RN
);
7536 if (skip_past_char (&str
, '!') == SUCCESS
)
7537 inst
.operands
[i
].writeback
= 1;
7541 case OP_I7
: po_imm_or_fail ( 0, 7, FALSE
); break;
7542 case OP_I15
: po_imm_or_fail ( 0, 15, FALSE
); break;
7543 case OP_I16
: po_imm_or_fail ( 1, 16, FALSE
); break;
7544 case OP_I16z
: po_imm_or_fail ( 0, 16, FALSE
); break;
7545 case OP_I31
: po_imm_or_fail ( 0, 31, FALSE
); break;
7546 case OP_I32
: po_imm_or_fail ( 1, 32, FALSE
); break;
7547 case OP_I32z
: po_imm_or_fail ( 0, 32, FALSE
); break;
7548 case OP_I63s
: po_imm_or_fail (-64, 63, FALSE
); break;
7549 case OP_I63
: po_imm_or_fail ( 0, 63, FALSE
); break;
7550 case OP_I64
: po_imm_or_fail ( 1, 64, FALSE
); break;
7551 case OP_I64z
: po_imm_or_fail ( 0, 64, FALSE
); break;
7552 case OP_I255
: po_imm_or_fail ( 0, 255, FALSE
); break;
7554 case OP_I4b
: po_imm_or_fail ( 1, 4, TRUE
); break;
7556 case OP_I7b
: po_imm_or_fail ( 0, 7, TRUE
); break;
7557 case OP_I15b
: po_imm_or_fail ( 0, 15, TRUE
); break;
7559 case OP_I31b
: po_imm_or_fail ( 0, 31, TRUE
); break;
7560 case OP_oI32b
: po_imm_or_fail ( 1, 32, TRUE
); break;
7561 case OP_oI32z
: po_imm_or_fail ( 0, 32, TRUE
); break;
7562 case OP_oIffffb
: po_imm_or_fail ( 0, 0xffff, TRUE
); break;
7564 /* Immediate variants */
7566 po_char_or_fail ('{');
7567 po_imm_or_fail (0, 255, TRUE
);
7568 po_char_or_fail ('}');
7572 /* The expression parser chokes on a trailing !, so we have
7573 to find it first and zap it. */
7576 while (*s
&& *s
!= ',')
7581 inst
.operands
[i
].writeback
= 1;
7583 po_imm_or_fail (0, 31, TRUE
);
7591 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7596 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7601 po_misc_or_fail (my_get_expression (&inst
.relocs
[0].exp
, &str
,
7603 if (inst
.relocs
[0].exp
.X_op
== O_symbol
)
7605 val
= parse_reloc (&str
);
7608 inst
.error
= _("unrecognized relocation suffix");
7611 else if (val
!= BFD_RELOC_UNUSED
)
7613 inst
.operands
[i
].imm
= val
;
7614 inst
.operands
[i
].hasreloc
= 1;
7620 po_misc_or_fail (my_get_expression (&inst
.relocs
[i
].exp
, &str
,
7622 if (inst
.relocs
[i
].exp
.X_op
== O_symbol
)
7624 inst
.operands
[i
].hasreloc
= 1;
7626 else if (inst
.relocs
[i
].exp
.X_op
== O_constant
)
7628 inst
.operands
[i
].imm
= inst
.relocs
[i
].exp
.X_add_number
;
7629 inst
.operands
[i
].hasreloc
= 0;
7633 /* Operand for MOVW or MOVT. */
7635 po_misc_or_fail (parse_half (&str
));
7638 /* Register or expression. */
7639 case OP_RR_EXr
: po_reg_or_goto (REG_TYPE_RN
, EXPr
); break;
7640 case OP_RR_EXi
: po_reg_or_goto (REG_TYPE_RN
, EXPi
); break;
7642 /* Register or immediate. */
7643 case OP_RRnpc_I0
: po_reg_or_goto (REG_TYPE_RN
, I0
); break;
7644 I0
: po_imm_or_fail (0, 0, FALSE
); break;
7646 case OP_RRnpcsp_I32
: po_reg_or_goto (REG_TYPE_RN
, I32
); break;
7647 I32
: po_imm_or_fail (1, 32, FALSE
); break;
7649 case OP_RF_IF
: po_reg_or_goto (REG_TYPE_FN
, IF
); break;
7651 if (!is_immediate_prefix (*str
))
7654 val
= parse_fpa_immediate (&str
);
7657 /* FPA immediates are encoded as registers 8-15.
7658 parse_fpa_immediate has already applied the offset. */
7659 inst
.operands
[i
].reg
= val
;
7660 inst
.operands
[i
].isreg
= 1;
7663 case OP_RIWR_I32z
: po_reg_or_goto (REG_TYPE_MMXWR
, I32z
); break;
7664 I32z
: po_imm_or_fail (0, 32, FALSE
); break;
7666 /* Two kinds of register. */
7669 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7671 || (rege
->type
!= REG_TYPE_MMXWR
7672 && rege
->type
!= REG_TYPE_MMXWC
7673 && rege
->type
!= REG_TYPE_MMXWCG
))
7675 inst
.error
= _("iWMMXt data or control register expected");
7678 inst
.operands
[i
].reg
= rege
->number
;
7679 inst
.operands
[i
].isreg
= (rege
->type
== REG_TYPE_MMXWR
);
7685 struct reg_entry
*rege
= arm_reg_parse_multi (&str
);
7687 || (rege
->type
!= REG_TYPE_MMXWC
7688 && rege
->type
!= REG_TYPE_MMXWCG
))
7690 inst
.error
= _("iWMMXt control register expected");
7693 inst
.operands
[i
].reg
= rege
->number
;
7694 inst
.operands
[i
].isreg
= 1;
7699 case OP_CPSF
: val
= parse_cps_flags (&str
); break;
7700 case OP_ENDI
: val
= parse_endian_specifier (&str
); break;
7701 case OP_oROR
: val
= parse_ror (&str
); break;
7703 case OP_COND
: val
= parse_cond (&str
); break;
7704 case OP_oBARRIER_I15
:
7705 po_barrier_or_imm (str
); break;
7707 if (parse_immediate (&str
, &val
, 0, 15, TRUE
) == FAIL
)
7713 po_reg_or_goto (REG_TYPE_RNB
, try_psr
);
7714 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_virt
))
7716 inst
.error
= _("Banked registers are not available with this "
7722 val
= parse_psr (&str
, op_parse_code
== OP_wPSR
);
7726 po_reg_or_goto (REG_TYPE_VFSD
, try_sysreg
);
7729 val
= parse_sys_vldr_vstr (&str
);
7733 po_reg_or_goto (REG_TYPE_RN
, try_apsr
);
7736 /* Parse "APSR_nvzc" operand (for FMSTAT-equivalent MRS
7738 if (strncasecmp (str
, "APSR_", 5) == 0)
7745 case 'c': found
= (found
& 1) ? 16 : found
| 1; break;
7746 case 'n': found
= (found
& 2) ? 16 : found
| 2; break;
7747 case 'z': found
= (found
& 4) ? 16 : found
| 4; break;
7748 case 'v': found
= (found
& 8) ? 16 : found
| 8; break;
7749 default: found
= 16;
7753 inst
.operands
[i
].isvec
= 1;
7754 /* APSR_nzcv is encoded in instructions as if it were the REG_PC. */
7755 inst
.operands
[i
].reg
= REG_PC
;
7762 po_misc_or_fail (parse_tb (&str
));
7765 /* Register lists. */
7767 val
= parse_reg_list (&str
, REGLIST_RN
);
7770 inst
.operands
[i
].writeback
= 1;
7776 val
= parse_reg_list (&str
, REGLIST_CLRM
);
7780 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_S
,
7785 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
, REGLIST_VFP_D
,
7790 /* Allow Q registers too. */
7791 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7792 REGLIST_NEON_D
, &partial_match
);
7796 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7797 REGLIST_VFP_S
, &partial_match
);
7798 inst
.operands
[i
].issingle
= 1;
7803 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7804 REGLIST_VFP_D_VPR
, &partial_match
);
7805 if (val
== FAIL
&& !partial_match
)
7808 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7809 REGLIST_VFP_S_VPR
, &partial_match
);
7810 inst
.operands
[i
].issingle
= 1;
7815 val
= parse_vfp_reg_list (&str
, &inst
.operands
[i
].reg
,
7816 REGLIST_NEON_D
, &partial_match
);
7821 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7822 1, &inst
.operands
[i
].vectype
);
7823 if (val
!= (((op_parse_code
== OP_MSTRLST2
) ? 3 : 7) << 5 | 0xe))
7827 val
= parse_neon_el_struct_list (&str
, &inst
.operands
[i
].reg
,
7828 0, &inst
.operands
[i
].vectype
);
7831 /* Addressing modes */
7833 po_misc_or_fail (parse_address_group_reloc (&str
, i
, GROUP_MVE
));
7837 po_misc_or_fail (parse_address (&str
, i
));
7841 po_misc_or_fail_no_backtrack (
7842 parse_address_group_reloc (&str
, i
, GROUP_LDR
));
7846 po_misc_or_fail_no_backtrack (
7847 parse_address_group_reloc (&str
, i
, GROUP_LDRS
));
7851 po_misc_or_fail_no_backtrack (
7852 parse_address_group_reloc (&str
, i
, GROUP_LDC
));
7856 po_misc_or_fail (parse_shifter_operand (&str
, i
));
7860 po_misc_or_fail_no_backtrack (
7861 parse_shifter_operand_group_reloc (&str
, i
));
7865 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_IMMEDIATE
));
7869 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_ASR_IMMEDIATE
));
7873 po_misc_or_fail (parse_shift (&str
, i
, SHIFT_LSL_OR_ASR_IMMEDIATE
));
7878 po_reg_or_goto (REG_TYPE_MQ
, try_rr_zr
);
7883 po_reg_or_goto (REG_TYPE_RN
, ZR
);
7886 po_reg_or_fail (REG_TYPE_ZR
);
7890 as_fatal (_("unhandled operand code %d"), op_parse_code
);
7893 /* Various value-based sanity checks and shared operations. We
7894 do not signal immediate failures for the register constraints;
7895 this allows a syntax error to take precedence. */
7896 switch (op_parse_code
)
7904 if (inst
.operands
[i
].isreg
&& inst
.operands
[i
].reg
== REG_PC
)
7905 inst
.error
= BAD_PC
;
7910 case OP_RRnpcsp_I32
:
7911 if (inst
.operands
[i
].isreg
)
7913 if (inst
.operands
[i
].reg
== REG_PC
)
7914 inst
.error
= BAD_PC
;
7915 else if (inst
.operands
[i
].reg
== REG_SP
7916 /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
7917 relaxed since ARMv8-A. */
7918 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
7921 inst
.error
= BAD_SP
;
7927 if (inst
.operands
[i
].isreg
7928 && inst
.operands
[i
].reg
== REG_PC
7929 && (inst
.operands
[i
].writeback
|| thumb
))
7930 inst
.error
= BAD_PC
;
7935 if (inst
.operands
[i
].isreg
)
7945 case OP_oBARRIER_I15
:
7958 inst
.operands
[i
].imm
= val
;
7963 if (inst
.operands
[i
].reg
!= REG_LR
)
7964 inst
.error
= _("operand must be LR register");
7970 if (!inst
.operands
[i
].iszr
&& inst
.operands
[i
].reg
== REG_PC
)
7971 inst
.error
= BAD_PC
;
7975 if (inst
.operands
[i
].isreg
7976 && (inst
.operands
[i
].reg
& 0x00000001) != 0)
7977 inst
.error
= BAD_ODD
;
7981 if (inst
.operands
[i
].isreg
)
7983 if ((inst
.operands
[i
].reg
& 0x00000001) != 1)
7984 inst
.error
= BAD_EVEN
;
7985 else if (inst
.operands
[i
].reg
== REG_SP
)
7986 as_tsktsk (MVE_BAD_SP
);
7987 else if (inst
.operands
[i
].reg
== REG_PC
)
7988 inst
.error
= BAD_PC
;
7996 /* If we get here, this operand was successfully parsed. */
7997 inst
.operands
[i
].present
= 1;
8001 inst
.error
= BAD_ARGS
;
8006 /* The parse routine should already have set inst.error, but set a
8007 default here just in case. */
8009 inst
.error
= BAD_SYNTAX
;
8013 /* Do not backtrack over a trailing optional argument that
8014 absorbed some text. We will only fail again, with the
8015 'garbage following instruction' error message, which is
8016 probably less helpful than the current one. */
8017 if (backtrack_index
== i
&& backtrack_pos
!= str
8018 && upat
[i
+1] == OP_stop
)
8021 inst
.error
= BAD_SYNTAX
;
8025 /* Try again, skipping the optional argument at backtrack_pos. */
8026 str
= backtrack_pos
;
8027 inst
.error
= backtrack_error
;
8028 inst
.operands
[backtrack_index
].present
= 0;
8029 i
= backtrack_index
;
8033 /* Check that we have parsed all the arguments. */
8034 if (*str
!= '\0' && !inst
.error
)
8035 inst
.error
= _("garbage following instruction");
8037 return inst
.error
? FAIL
: SUCCESS
;
8040 #undef po_char_or_fail
8041 #undef po_reg_or_fail
8042 #undef po_reg_or_goto
8043 #undef po_imm_or_fail
8044 #undef po_scalar_or_fail
8045 #undef po_barrier_or_imm
8047 /* Shorthand macro for instruction encoding functions issuing errors. */
8048 #define constraint(expr, err) \
8059 /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
8060 instructions are unpredictable if these registers are used. This
8061 is the BadReg predicate in ARM's Thumb-2 documentation.
8063 Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
8064 places, while the restriction on REG_SP was relaxed since ARMv8-A. */
8065 #define reject_bad_reg(reg) \
8067 if (reg == REG_PC) \
8069 inst.error = BAD_PC; \
8072 else if (reg == REG_SP \
8073 && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
8075 inst.error = BAD_SP; \
8080 /* If REG is R13 (the stack pointer), warn that its use is
8082 #define warn_deprecated_sp(reg) \
8084 if (warn_on_deprecated && reg == REG_SP) \
8085 as_tsktsk (_("use of r13 is deprecated")); \
8088 /* Functions for operand encoding. ARM, then Thumb. */
8090 #define rotate_left(v, n) (v << (n & 31) | v >> ((32 - n) & 31))
8092 /* If the current inst is scalar ARMv8.2 fp16 instruction, do special encoding.
8094 The only binary encoding difference is the Coprocessor number. Coprocessor
8095 9 is used for half-precision calculations or conversions. The format of the
8096 instruction is the same as the equivalent Coprocessor 10 instruction that
8097 exists for Single-Precision operation. */
8100 do_scalar_fp16_v82_encode (void)
8102 if (inst
.cond
< COND_ALWAYS
)
8103 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
8104 " the behaviour is UNPREDICTABLE"));
8105 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
8108 inst
.instruction
= (inst
.instruction
& 0xfffff0ff) | 0x900;
8109 mark_feature_used (&arm_ext_fp16
);
8112 /* If VAL can be encoded in the immediate field of an ARM instruction,
8113 return the encoded form. Otherwise, return FAIL. */
8116 encode_arm_immediate (unsigned int val
)
8123 for (i
= 2; i
< 32; i
+= 2)
8124 if ((a
= rotate_left (val
, i
)) <= 0xff)
8125 return a
| (i
<< 7); /* 12-bit pack: [shift-cnt,const]. */
8130 /* If VAL can be encoded in the immediate field of a Thumb32 instruction,
8131 return the encoded form. Otherwise, return FAIL. */
8133 encode_thumb32_immediate (unsigned int val
)
8140 for (i
= 1; i
<= 24; i
++)
8143 if ((val
& ~(0xff << i
)) == 0)
8144 return ((val
>> i
) & 0x7f) | ((32 - i
) << 7);
8148 if (val
== ((a
<< 16) | a
))
8150 if (val
== ((a
<< 24) | (a
<< 16) | (a
<< 8) | a
))
8154 if (val
== ((a
<< 16) | a
))
8155 return 0x200 | (a
>> 8);
8159 /* Encode a VFP SP or DP register number into inst.instruction. */
8162 encode_arm_vfp_reg (int reg
, enum vfp_reg_pos pos
)
8164 if ((pos
== VFP_REG_Dd
|| pos
== VFP_REG_Dn
|| pos
== VFP_REG_Dm
)
8167 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_d32
))
8170 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
8173 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
8178 first_error (_("D register out of range for selected VFP version"));
8186 inst
.instruction
|= ((reg
>> 1) << 12) | ((reg
& 1) << 22);
8190 inst
.instruction
|= ((reg
>> 1) << 16) | ((reg
& 1) << 7);
8194 inst
.instruction
|= ((reg
>> 1) << 0) | ((reg
& 1) << 5);
8198 inst
.instruction
|= ((reg
& 15) << 12) | ((reg
>> 4) << 22);
8202 inst
.instruction
|= ((reg
& 15) << 16) | ((reg
>> 4) << 7);
8206 inst
.instruction
|= (reg
& 15) | ((reg
>> 4) << 5);
8214 /* Encode a <shift> in an ARM-format instruction. The immediate,
8215 if any, is handled by md_apply_fix. */
8217 encode_arm_shift (int i
)
8219 /* register-shifted register. */
8220 if (inst
.operands
[i
].immisreg
)
8223 for (op_index
= 0; op_index
<= i
; ++op_index
)
8225 /* Check the operand only when it's presented. In pre-UAL syntax,
8226 if the destination register is the same as the first operand, two
8227 register form of the instruction can be used. */
8228 if (inst
.operands
[op_index
].present
&& inst
.operands
[op_index
].isreg
8229 && inst
.operands
[op_index
].reg
== REG_PC
)
8230 as_warn (UNPRED_REG ("r15"));
8233 if (inst
.operands
[i
].imm
== REG_PC
)
8234 as_warn (UNPRED_REG ("r15"));
8237 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8238 inst
.instruction
|= SHIFT_ROR
<< 5;
8241 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8242 if (inst
.operands
[i
].immisreg
)
8244 inst
.instruction
|= SHIFT_BY_REG
;
8245 inst
.instruction
|= inst
.operands
[i
].imm
<< 8;
8248 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8253 encode_arm_shifter_operand (int i
)
8255 if (inst
.operands
[i
].isreg
)
8257 inst
.instruction
|= inst
.operands
[i
].reg
;
8258 encode_arm_shift (i
);
8262 inst
.instruction
|= INST_IMMEDIATE
;
8263 if (inst
.relocs
[0].type
!= BFD_RELOC_ARM_IMMEDIATE
)
8264 inst
.instruction
|= inst
.operands
[i
].imm
;
8268 /* Subroutine of encode_arm_addr_mode_2 and encode_arm_addr_mode_3. */
8270 encode_arm_addr_mode_common (int i
, bfd_boolean is_t
)
8273 Generate an error if the operand is not a register. */
8274 constraint (!inst
.operands
[i
].isreg
,
8275 _("Instruction does not support =N addresses"));
8277 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8279 if (inst
.operands
[i
].preind
)
8283 inst
.error
= _("instruction does not accept preindexed addressing");
8286 inst
.instruction
|= PRE_INDEX
;
8287 if (inst
.operands
[i
].writeback
)
8288 inst
.instruction
|= WRITE_BACK
;
8291 else if (inst
.operands
[i
].postind
)
8293 gas_assert (inst
.operands
[i
].writeback
);
8295 inst
.instruction
|= WRITE_BACK
;
8297 else /* unindexed - only for coprocessor */
8299 inst
.error
= _("instruction does not accept unindexed addressing");
8303 if (((inst
.instruction
& WRITE_BACK
) || !(inst
.instruction
& PRE_INDEX
))
8304 && (((inst
.instruction
& 0x000f0000) >> 16)
8305 == ((inst
.instruction
& 0x0000f000) >> 12)))
8306 as_warn ((inst
.instruction
& LOAD_BIT
)
8307 ? _("destination register same as write-back base")
8308 : _("source register same as write-back base"));
8311 /* inst.operands[i] was set up by parse_address. Encode it into an
8312 ARM-format mode 2 load or store instruction. If is_t is true,
8313 reject forms that cannot be used with a T instruction (i.e. not
8316 encode_arm_addr_mode_2 (int i
, bfd_boolean is_t
)
8318 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
8320 encode_arm_addr_mode_common (i
, is_t
);
8322 if (inst
.operands
[i
].immisreg
)
8324 constraint ((inst
.operands
[i
].imm
== REG_PC
8325 || (is_pc
&& inst
.operands
[i
].writeback
)),
8327 inst
.instruction
|= INST_IMMEDIATE
; /* yes, this is backwards */
8328 inst
.instruction
|= inst
.operands
[i
].imm
;
8329 if (!inst
.operands
[i
].negative
)
8330 inst
.instruction
|= INDEX_UP
;
8331 if (inst
.operands
[i
].shifted
)
8333 if (inst
.operands
[i
].shift_kind
== SHIFT_RRX
)
8334 inst
.instruction
|= SHIFT_ROR
<< 5;
8337 inst
.instruction
|= inst
.operands
[i
].shift_kind
<< 5;
8338 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
8342 else /* immediate offset in inst.relocs[0] */
8344 if (is_pc
&& !inst
.relocs
[0].pc_rel
)
8346 const bfd_boolean is_load
= ((inst
.instruction
& LOAD_BIT
) != 0);
8348 /* If is_t is TRUE, it's called from do_ldstt. ldrt/strt
8349 cannot use PC in addressing.
8350 PC cannot be used in writeback addressing, either. */
8351 constraint ((is_t
|| inst
.operands
[i
].writeback
),
8354 /* Use of PC in str is deprecated for ARMv7. */
8355 if (warn_on_deprecated
8357 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
))
8358 as_tsktsk (_("use of PC in this instruction is deprecated"));
8361 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8363 /* Prefer + for zero encoded value. */
8364 if (!inst
.operands
[i
].negative
)
8365 inst
.instruction
|= INDEX_UP
;
8366 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM
;
8371 /* inst.operands[i] was set up by parse_address. Encode it into an
8372 ARM-format mode 3 load or store instruction. Reject forms that
8373 cannot be used with such instructions. If is_t is true, reject
8374 forms that cannot be used with a T instruction (i.e. not
8377 encode_arm_addr_mode_3 (int i
, bfd_boolean is_t
)
8379 if (inst
.operands
[i
].immisreg
&& inst
.operands
[i
].shifted
)
8381 inst
.error
= _("instruction does not accept scaled register index");
8385 encode_arm_addr_mode_common (i
, is_t
);
8387 if (inst
.operands
[i
].immisreg
)
8389 constraint ((inst
.operands
[i
].imm
== REG_PC
8390 || (is_t
&& inst
.operands
[i
].reg
== REG_PC
)),
8392 constraint (inst
.operands
[i
].reg
== REG_PC
&& inst
.operands
[i
].writeback
,
8394 inst
.instruction
|= inst
.operands
[i
].imm
;
8395 if (!inst
.operands
[i
].negative
)
8396 inst
.instruction
|= INDEX_UP
;
8398 else /* immediate offset in inst.relocs[0] */
8400 constraint ((inst
.operands
[i
].reg
== REG_PC
&& !inst
.relocs
[0].pc_rel
8401 && inst
.operands
[i
].writeback
),
8403 inst
.instruction
|= HWOFFSET_IMM
;
8404 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
8406 /* Prefer + for zero encoded value. */
8407 if (!inst
.operands
[i
].negative
)
8408 inst
.instruction
|= INDEX_UP
;
8410 inst
.relocs
[0].type
= BFD_RELOC_ARM_OFFSET_IMM8
;
8415 /* Write immediate bits [7:0] to the following locations:
8417 |28/24|23 19|18 16|15 4|3 0|
8418 | a |x x x x x|b c d|x x x x x x x x x x x x|e f g h|
8420 This function is used by VMOV/VMVN/VORR/VBIC. */
8423 neon_write_immbits (unsigned immbits
)
8425 inst
.instruction
|= immbits
& 0xf;
8426 inst
.instruction
|= ((immbits
>> 4) & 0x7) << 16;
8427 inst
.instruction
|= ((immbits
>> 7) & 0x1) << (thumb_mode
? 28 : 24);
8430 /* Invert low-order SIZE bits of XHI:XLO. */
8433 neon_invert_size (unsigned *xlo
, unsigned *xhi
, int size
)
8435 unsigned immlo
= xlo
? *xlo
: 0;
8436 unsigned immhi
= xhi
? *xhi
: 0;
8441 immlo
= (~immlo
) & 0xff;
8445 immlo
= (~immlo
) & 0xffff;
8449 immhi
= (~immhi
) & 0xffffffff;
8453 immlo
= (~immlo
) & 0xffffffff;
8467 /* True if IMM has form 0bAAAAAAAABBBBBBBBCCCCCCCCDDDDDDDD for bits
8471 neon_bits_same_in_bytes (unsigned imm
)
8473 return ((imm
& 0x000000ff) == 0 || (imm
& 0x000000ff) == 0x000000ff)
8474 && ((imm
& 0x0000ff00) == 0 || (imm
& 0x0000ff00) == 0x0000ff00)
8475 && ((imm
& 0x00ff0000) == 0 || (imm
& 0x00ff0000) == 0x00ff0000)
8476 && ((imm
& 0xff000000) == 0 || (imm
& 0xff000000) == 0xff000000);
8479 /* For immediate of above form, return 0bABCD. */
8482 neon_squash_bits (unsigned imm
)
8484 return (imm
& 0x01) | ((imm
& 0x0100) >> 7) | ((imm
& 0x010000) >> 14)
8485 | ((imm
& 0x01000000) >> 21);
8488 /* Compress quarter-float representation to 0b...000 abcdefgh. */
8491 neon_qfloat_bits (unsigned imm
)
8493 return ((imm
>> 19) & 0x7f) | ((imm
>> 24) & 0x80);
8496 /* Returns CMODE. IMMBITS [7:0] is set to bits suitable for inserting into
8497 the instruction. *OP is passed as the initial value of the op field, and
8498 may be set to a different value depending on the constant (i.e.
8499 "MOV I64, 0bAAAAAAAABBBB..." which uses OP = 1 despite being MOV not
8500 MVN). If the immediate looks like a repeated pattern then also
8501 try smaller element sizes. */
8504 neon_cmode_for_move_imm (unsigned immlo
, unsigned immhi
, int float_p
,
8505 unsigned *immbits
, int *op
, int size
,
8506 enum neon_el_type type
)
8508 /* Only permit float immediates (including 0.0/-0.0) if the operand type is
8510 if (type
== NT_float
&& !float_p
)
8513 if (type
== NT_float
&& is_quarter_float (immlo
) && immhi
== 0)
8515 if (size
!= 32 || *op
== 1)
8517 *immbits
= neon_qfloat_bits (immlo
);
8523 if (neon_bits_same_in_bytes (immhi
)
8524 && neon_bits_same_in_bytes (immlo
))
8528 *immbits
= (neon_squash_bits (immhi
) << 4)
8529 | neon_squash_bits (immlo
);
8540 if (immlo
== (immlo
& 0x000000ff))
8545 else if (immlo
== (immlo
& 0x0000ff00))
8547 *immbits
= immlo
>> 8;
8550 else if (immlo
== (immlo
& 0x00ff0000))
8552 *immbits
= immlo
>> 16;
8555 else if (immlo
== (immlo
& 0xff000000))
8557 *immbits
= immlo
>> 24;
8560 else if (immlo
== ((immlo
& 0x0000ff00) | 0x000000ff))
8562 *immbits
= (immlo
>> 8) & 0xff;
8565 else if (immlo
== ((immlo
& 0x00ff0000) | 0x0000ffff))
8567 *immbits
= (immlo
>> 16) & 0xff;
8571 if ((immlo
& 0xffff) != (immlo
>> 16))
8578 if (immlo
== (immlo
& 0x000000ff))
8583 else if (immlo
== (immlo
& 0x0000ff00))
8585 *immbits
= immlo
>> 8;
8589 if ((immlo
& 0xff) != (immlo
>> 8))
8594 if (immlo
== (immlo
& 0x000000ff))
8596 /* Don't allow MVN with 8-bit immediate. */
8606 #if defined BFD_HOST_64_BIT
8607 /* Returns TRUE if double precision value V may be cast
8608 to single precision without loss of accuracy. */
8611 is_double_a_single (bfd_int64_t v
)
8613 int exp
= (int)((v
>> 52) & 0x7FF);
8614 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8616 return (exp
== 0 || exp
== 0x7FF
8617 || (exp
>= 1023 - 126 && exp
<= 1023 + 127))
8618 && (mantissa
& 0x1FFFFFFFl
) == 0;
8621 /* Returns a double precision value casted to single precision
8622 (ignoring the least significant bits in exponent and mantissa). */
8625 double_to_single (bfd_int64_t v
)
8627 int sign
= (int) ((v
>> 63) & 1l);
8628 int exp
= (int) ((v
>> 52) & 0x7FF);
8629 bfd_int64_t mantissa
= (v
& (bfd_int64_t
)0xFFFFFFFFFFFFFULL
);
8635 exp
= exp
- 1023 + 127;
8644 /* No denormalized numbers. */
8650 return (sign
<< 31) | (exp
<< 23) | mantissa
;
8652 #endif /* BFD_HOST_64_BIT */
8661 static void do_vfp_nsyn_opcode (const char *);
8663 /* inst.relocs[0].exp describes an "=expr" load pseudo-operation.
8664 Determine whether it can be performed with a move instruction; if
8665 it can, convert inst.instruction to that move instruction and
8666 return TRUE; if it can't, convert inst.instruction to a literal-pool
8667 load and return FALSE. If this is not a valid thing to do in the
8668 current context, set inst.error and return TRUE.
8670 inst.operands[i] describes the destination register. */
8673 move_or_literal_pool (int i
, enum lit_type t
, bfd_boolean mode_3
)
8676 bfd_boolean thumb_p
= (t
== CONST_THUMB
);
8677 bfd_boolean arm_p
= (t
== CONST_ARM
);
8680 tbit
= (inst
.instruction
> 0xffff) ? THUMB2_LOAD_BIT
: THUMB_LOAD_BIT
;
8684 if ((inst
.instruction
& tbit
) == 0)
8686 inst
.error
= _("invalid pseudo operation");
8690 if (inst
.relocs
[0].exp
.X_op
!= O_constant
8691 && inst
.relocs
[0].exp
.X_op
!= O_symbol
8692 && inst
.relocs
[0].exp
.X_op
!= O_big
)
8694 inst
.error
= _("constant expression expected");
8698 if (inst
.relocs
[0].exp
.X_op
== O_constant
8699 || inst
.relocs
[0].exp
.X_op
== O_big
)
8701 #if defined BFD_HOST_64_BIT
8706 if (inst
.relocs
[0].exp
.X_op
== O_big
)
8708 LITTLENUM_TYPE w
[X_PRECISION
];
8711 if (inst
.relocs
[0].exp
.X_add_number
== -1)
8713 gen_to_words (w
, X_PRECISION
, E_PRECISION
);
8715 /* FIXME: Should we check words w[2..5] ? */
8720 #if defined BFD_HOST_64_BIT
8722 ((((((((bfd_int64_t
) l
[3] & LITTLENUM_MASK
)
8723 << LITTLENUM_NUMBER_OF_BITS
)
8724 | ((bfd_int64_t
) l
[2] & LITTLENUM_MASK
))
8725 << LITTLENUM_NUMBER_OF_BITS
)
8726 | ((bfd_int64_t
) l
[1] & LITTLENUM_MASK
))
8727 << LITTLENUM_NUMBER_OF_BITS
)
8728 | ((bfd_int64_t
) l
[0] & LITTLENUM_MASK
));
8730 v
= ((l
[1] & LITTLENUM_MASK
) << LITTLENUM_NUMBER_OF_BITS
)
8731 | (l
[0] & LITTLENUM_MASK
);
8735 v
= inst
.relocs
[0].exp
.X_add_number
;
8737 if (!inst
.operands
[i
].issingle
)
8741 /* LDR should not use lead in a flag-setting instruction being
8742 chosen so we do not check whether movs can be used. */
8744 if ((ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
8745 || ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8746 && inst
.operands
[i
].reg
!= 13
8747 && inst
.operands
[i
].reg
!= 15)
8749 /* Check if on thumb2 it can be done with a mov.w, mvn or
8750 movw instruction. */
8751 unsigned int newimm
;
8752 bfd_boolean isNegated
;
8754 newimm
= encode_thumb32_immediate (v
);
8755 if (newimm
!= (unsigned int) FAIL
)
8759 newimm
= encode_thumb32_immediate (~v
);
8760 if (newimm
!= (unsigned int) FAIL
)
8764 /* The number can be loaded with a mov.w or mvn
8766 if (newimm
!= (unsigned int) FAIL
8767 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
8769 inst
.instruction
= (0xf04f0000 /* MOV.W. */
8770 | (inst
.operands
[i
].reg
<< 8));
8771 /* Change to MOVN. */
8772 inst
.instruction
|= (isNegated
? 0x200000 : 0);
8773 inst
.instruction
|= (newimm
& 0x800) << 15;
8774 inst
.instruction
|= (newimm
& 0x700) << 4;
8775 inst
.instruction
|= (newimm
& 0x0ff);
8778 /* The number can be loaded with a movw instruction. */
8779 else if ((v
& ~0xFFFF) == 0
8780 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
))
8782 int imm
= v
& 0xFFFF;
8784 inst
.instruction
= 0xf2400000; /* MOVW. */
8785 inst
.instruction
|= (inst
.operands
[i
].reg
<< 8);
8786 inst
.instruction
|= (imm
& 0xf000) << 4;
8787 inst
.instruction
|= (imm
& 0x0800) << 15;
8788 inst
.instruction
|= (imm
& 0x0700) << 4;
8789 inst
.instruction
|= (imm
& 0x00ff);
8790 /* In case this replacement is being done on Armv8-M
8791 Baseline we need to make sure to disable the
8792 instruction size check, as otherwise GAS will reject
8793 the use of this T32 instruction. */
8801 int value
= encode_arm_immediate (v
);
8805 /* This can be done with a mov instruction. */
8806 inst
.instruction
&= LITERAL_MASK
;
8807 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MOV
<< DATA_OP_SHIFT
);
8808 inst
.instruction
|= value
& 0xfff;
8812 value
= encode_arm_immediate (~ v
);
8815 /* This can be done with a mvn instruction. */
8816 inst
.instruction
&= LITERAL_MASK
;
8817 inst
.instruction
|= INST_IMMEDIATE
| (OPCODE_MVN
<< DATA_OP_SHIFT
);
8818 inst
.instruction
|= value
& 0xfff;
8822 else if (t
== CONST_VEC
&& ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
8825 unsigned immbits
= 0;
8826 unsigned immlo
= inst
.operands
[1].imm
;
8827 unsigned immhi
= inst
.operands
[1].regisimm
8828 ? inst
.operands
[1].reg
8829 : inst
.relocs
[0].exp
.X_unsigned
8831 : ((bfd_int64_t
)((int) immlo
)) >> 32;
8832 int cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8833 &op
, 64, NT_invtype
);
8837 neon_invert_size (&immlo
, &immhi
, 64);
8839 cmode
= neon_cmode_for_move_imm (immlo
, immhi
, FALSE
, &immbits
,
8840 &op
, 64, NT_invtype
);
8845 inst
.instruction
= (inst
.instruction
& VLDR_VMOV_SAME
)
8851 /* Fill other bits in vmov encoding for both thumb and arm. */
8853 inst
.instruction
|= (0x7U
<< 29) | (0xF << 24);
8855 inst
.instruction
|= (0xFU
<< 28) | (0x1 << 25);
8856 neon_write_immbits (immbits
);
8864 /* Check if vldr Rx, =constant could be optimized to vmov Rx, #constant. */
8865 if (inst
.operands
[i
].issingle
8866 && is_quarter_float (inst
.operands
[1].imm
)
8867 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3xd
))
8869 inst
.operands
[1].imm
=
8870 neon_qfloat_bits (v
);
8871 do_vfp_nsyn_opcode ("fconsts");
8875 /* If our host does not support a 64-bit type then we cannot perform
8876 the following optimization. This mean that there will be a
8877 discrepancy between the output produced by an assembler built for
8878 a 32-bit-only host and the output produced from a 64-bit host, but
8879 this cannot be helped. */
8880 #if defined BFD_HOST_64_BIT
8881 else if (!inst
.operands
[1].issingle
8882 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v3
))
8884 if (is_double_a_single (v
)
8885 && is_quarter_float (double_to_single (v
)))
8887 inst
.operands
[1].imm
=
8888 neon_qfloat_bits (double_to_single (v
));
8889 do_vfp_nsyn_opcode ("fconstd");
8897 if (add_to_lit_pool ((!inst
.operands
[i
].isvec
8898 || inst
.operands
[i
].issingle
) ? 4 : 8) == FAIL
)
8901 inst
.operands
[1].reg
= REG_PC
;
8902 inst
.operands
[1].isreg
= 1;
8903 inst
.operands
[1].preind
= 1;
8904 inst
.relocs
[0].pc_rel
= 1;
8905 inst
.relocs
[0].type
= (thumb_p
8906 ? BFD_RELOC_ARM_THUMB_OFFSET
8908 ? BFD_RELOC_ARM_HWLITERAL
8909 : BFD_RELOC_ARM_LITERAL
));
8913 /* inst.operands[i] was set up by parse_address. Encode it into an
8914 ARM-format instruction. Reject all forms which cannot be encoded
8915 into a coprocessor load/store instruction. If wb_ok is false,
8916 reject use of writeback; if unind_ok is false, reject use of
8917 unindexed addressing. If reloc_override is not 0, use it instead
8918 of BFD_ARM_CP_OFF_IMM, unless the initial relocation is a group one
8919 (in which case it is preserved). */
8922 encode_arm_cp_address (int i
, int wb_ok
, int unind_ok
, int reloc_override
)
8924 if (!inst
.operands
[i
].isreg
)
8927 if (! inst
.operands
[0].isvec
)
8929 inst
.error
= _("invalid co-processor operand");
8932 if (move_or_literal_pool (0, CONST_VEC
, /*mode_3=*/FALSE
))
8936 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
8938 gas_assert (!(inst
.operands
[i
].preind
&& inst
.operands
[i
].postind
));
8940 if (!inst
.operands
[i
].preind
&& !inst
.operands
[i
].postind
) /* unindexed */
8942 gas_assert (!inst
.operands
[i
].writeback
);
8945 inst
.error
= _("instruction does not support unindexed addressing");
8948 inst
.instruction
|= inst
.operands
[i
].imm
;
8949 inst
.instruction
|= INDEX_UP
;
8953 if (inst
.operands
[i
].preind
)
8954 inst
.instruction
|= PRE_INDEX
;
8956 if (inst
.operands
[i
].writeback
)
8958 if (inst
.operands
[i
].reg
== REG_PC
)
8960 inst
.error
= _("pc may not be used with write-back");
8965 inst
.error
= _("instruction does not support writeback");
8968 inst
.instruction
|= WRITE_BACK
;
8972 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) reloc_override
;
8973 else if ((inst
.relocs
[0].type
< BFD_RELOC_ARM_ALU_PC_G0_NC
8974 || inst
.relocs
[0].type
> BFD_RELOC_ARM_LDC_SB_G2
)
8975 && inst
.relocs
[0].type
!= BFD_RELOC_ARM_LDR_PC_G0
)
8978 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_CP_OFF_IMM
;
8980 inst
.relocs
[0].type
= BFD_RELOC_ARM_CP_OFF_IMM
;
8983 /* Prefer + for zero encoded value. */
8984 if (!inst
.operands
[i
].negative
)
8985 inst
.instruction
|= INDEX_UP
;
8990 /* Functions for instruction encoding, sorted by sub-architecture.
8991 First some generics; their names are taken from the conventional
8992 bit positions for register arguments in ARM format instructions. */
9002 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9008 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9014 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9015 inst
.instruction
|= inst
.operands
[1].reg
;
9021 inst
.instruction
|= inst
.operands
[0].reg
;
9022 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9028 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9029 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9035 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9036 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9042 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9043 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9047 check_obsolete (const arm_feature_set
*feature
, const char *msg
)
9049 if (ARM_CPU_IS_ANY (cpu_variant
))
9051 as_tsktsk ("%s", msg
);
9054 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, *feature
))
9066 unsigned Rn
= inst
.operands
[2].reg
;
9067 /* Enforce restrictions on SWP instruction. */
9068 if ((inst
.instruction
& 0x0fbfffff) == 0x01000090)
9070 constraint (Rn
== inst
.operands
[0].reg
|| Rn
== inst
.operands
[1].reg
,
9071 _("Rn must not overlap other operands"));
9073 /* SWP{b} is obsolete for ARMv8-A, and deprecated for ARMv6* and ARMv7.
9075 if (!check_obsolete (&arm_ext_v8
,
9076 _("swp{b} use is obsoleted for ARMv8 and later"))
9077 && warn_on_deprecated
9078 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
))
9079 as_tsktsk (_("swp{b} use is deprecated for ARMv6 and ARMv7"));
9082 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9083 inst
.instruction
|= inst
.operands
[1].reg
;
9084 inst
.instruction
|= Rn
<< 16;
9090 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9091 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9092 inst
.instruction
|= inst
.operands
[2].reg
;
9098 constraint ((inst
.operands
[2].reg
== REG_PC
), BAD_PC
);
9099 constraint (((inst
.relocs
[0].exp
.X_op
!= O_constant
9100 && inst
.relocs
[0].exp
.X_op
!= O_illegal
)
9101 || inst
.relocs
[0].exp
.X_add_number
!= 0),
9103 inst
.instruction
|= inst
.operands
[0].reg
;
9104 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9105 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9111 inst
.instruction
|= inst
.operands
[0].imm
;
9117 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9118 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
9121 /* ARM instructions, in alphabetical order by function name (except
9122 that wrapper functions appear immediately after the function they
9125 /* This is a pseudo-op of the form "adr rd, label" to be converted
9126 into a relative address of the form "add rd, pc, #label-.-8". */
9131 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9133 /* Frag hacking will turn this into a sub instruction if the offset turns
9134 out to be negative. */
9135 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
9136 inst
.relocs
[0].pc_rel
= 1;
9137 inst
.relocs
[0].exp
.X_add_number
-= 8;
9139 if (support_interwork
9140 && inst
.relocs
[0].exp
.X_op
== O_symbol
9141 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9142 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9143 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9144 inst
.relocs
[0].exp
.X_add_number
|= 1;
9147 /* This is a pseudo-op of the form "adrl rd, label" to be converted
9148 into a relative address of the form:
9149 add rd, pc, #low(label-.-8)"
9150 add rd, rd, #high(label-.-8)" */
9155 inst
.instruction
|= (inst
.operands
[0].reg
<< 12); /* Rd */
9157 /* Frag hacking will turn this into a sub instruction if the offset turns
9158 out to be negative. */
9159 inst
.relocs
[0].type
= BFD_RELOC_ARM_ADRL_IMMEDIATE
;
9160 inst
.relocs
[0].pc_rel
= 1;
9161 inst
.size
= INSN_SIZE
* 2;
9162 inst
.relocs
[0].exp
.X_add_number
-= 8;
9164 if (support_interwork
9165 && inst
.relocs
[0].exp
.X_op
== O_symbol
9166 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
9167 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
9168 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
9169 inst
.relocs
[0].exp
.X_add_number
|= 1;
9175 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9176 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9178 if (!inst
.operands
[1].present
)
9179 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
9180 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9181 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9182 encode_arm_shifter_operand (2);
9188 if (inst
.operands
[0].present
)
9189 inst
.instruction
|= inst
.operands
[0].imm
;
9191 inst
.instruction
|= 0xf;
9197 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
9198 constraint (msb
> 32, _("bit-field extends past end of register"));
9199 /* The instruction encoding stores the LSB and MSB,
9200 not the LSB and width. */
9201 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9202 inst
.instruction
|= inst
.operands
[1].imm
<< 7;
9203 inst
.instruction
|= (msb
- 1) << 16;
9211 /* #0 in second position is alternative syntax for bfc, which is
9212 the same instruction but with REG_PC in the Rm field. */
9213 if (!inst
.operands
[1].isreg
)
9214 inst
.operands
[1].reg
= REG_PC
;
9216 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
9217 constraint (msb
> 32, _("bit-field extends past end of register"));
9218 /* The instruction encoding stores the LSB and MSB,
9219 not the LSB and width. */
9220 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9221 inst
.instruction
|= inst
.operands
[1].reg
;
9222 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9223 inst
.instruction
|= (msb
- 1) << 16;
9229 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
9230 _("bit-field extends past end of register"));
9231 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9232 inst
.instruction
|= inst
.operands
[1].reg
;
9233 inst
.instruction
|= inst
.operands
[2].imm
<< 7;
9234 inst
.instruction
|= (inst
.operands
[3].imm
- 1) << 16;
9237 /* ARM V5 breakpoint instruction (argument parse)
9238 BKPT <16 bit unsigned immediate>
9239 Instruction is not conditional.
9240 The bit pattern given in insns[] has the COND_ALWAYS condition,
9241 and it is an error if the caller tried to override that. */
9246 /* Top 12 of 16 bits to bits 19:8. */
9247 inst
.instruction
|= (inst
.operands
[0].imm
& 0xfff0) << 4;
9249 /* Bottom 4 of 16 bits to bits 3:0. */
9250 inst
.instruction
|= inst
.operands
[0].imm
& 0xf;
9254 encode_branch (int default_reloc
)
9256 if (inst
.operands
[0].hasreloc
)
9258 constraint (inst
.operands
[0].imm
!= BFD_RELOC_ARM_PLT32
9259 && inst
.operands
[0].imm
!= BFD_RELOC_ARM_TLS_CALL
,
9260 _("the only valid suffixes here are '(plt)' and '(tlscall)'"));
9261 inst
.relocs
[0].type
= inst
.operands
[0].imm
== BFD_RELOC_ARM_PLT32
9262 ? BFD_RELOC_ARM_PLT32
9263 : thumb_mode
? BFD_RELOC_ARM_THM_TLS_CALL
: BFD_RELOC_ARM_TLS_CALL
;
9266 inst
.relocs
[0].type
= (bfd_reloc_code_real_type
) default_reloc
;
9267 inst
.relocs
[0].pc_rel
= 1;
9274 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9275 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9278 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9285 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
9287 if (inst
.cond
== COND_ALWAYS
)
9288 encode_branch (BFD_RELOC_ARM_PCREL_CALL
);
9290 encode_branch (BFD_RELOC_ARM_PCREL_JUMP
);
9294 encode_branch (BFD_RELOC_ARM_PCREL_BRANCH
);
9297 /* ARM V5 branch-link-exchange instruction (argument parse)
9298 BLX <target_addr> ie BLX(1)
9299 BLX{<condition>} <Rm> ie BLX(2)
9300 Unfortunately, there are two different opcodes for this mnemonic.
9301 So, the insns[].value is not used, and the code here zaps values
9302 into inst.instruction.
9303 Also, the <target_addr> can be 25 bits, hence has its own reloc. */
9308 if (inst
.operands
[0].isreg
)
9310 /* Arg is a register; the opcode provided by insns[] is correct.
9311 It is not illegal to do "blx pc", just useless. */
9312 if (inst
.operands
[0].reg
== REG_PC
)
9313 as_tsktsk (_("use of r15 in blx in ARM mode is not really useful"));
9315 inst
.instruction
|= inst
.operands
[0].reg
;
9319 /* Arg is an address; this instruction cannot be executed
9320 conditionally, and the opcode must be adjusted.
9321 We retain the BFD_RELOC_ARM_PCREL_BLX till the very end
9322 where we generate out a BFD_RELOC_ARM_PCREL_CALL instead. */
9323 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
9324 inst
.instruction
= 0xfa000000;
9325 encode_branch (BFD_RELOC_ARM_PCREL_BLX
);
9332 bfd_boolean want_reloc
;
9334 if (inst
.operands
[0].reg
== REG_PC
)
9335 as_tsktsk (_("use of r15 in bx in ARM mode is not really useful"));
9337 inst
.instruction
|= inst
.operands
[0].reg
;
9338 /* Output R_ARM_V4BX relocations if is an EABI object that looks like
9339 it is for ARMv4t or earlier. */
9340 want_reloc
= !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5
);
9341 if (!ARM_FEATURE_ZERO (selected_object_arch
)
9342 && !ARM_CPU_HAS_FEATURE (selected_object_arch
, arm_ext_v5
))
9346 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
9351 inst
.relocs
[0].type
= BFD_RELOC_ARM_V4BX
;
9355 /* ARM v5TEJ. Jump to Jazelle code. */
9360 if (inst
.operands
[0].reg
== REG_PC
)
9361 as_tsktsk (_("use of r15 in bxj is not really useful"));
9363 inst
.instruction
|= inst
.operands
[0].reg
;
9366 /* Co-processor data operation:
9367 CDP{cond} <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>}
9368 CDP2 <coproc>, <opcode_1>, <CRd>, <CRn>, <CRm>{, <opcode_2>} */
9372 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9373 inst
.instruction
|= inst
.operands
[1].imm
<< 20;
9374 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
9375 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9376 inst
.instruction
|= inst
.operands
[4].reg
;
9377 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9383 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9384 encode_arm_shifter_operand (1);
9387 /* Transfer between coprocessor and ARM registers.
9388 MRC{cond} <coproc>, <opcode_1>, <Rd>, <CRn>, <CRm>{, <opcode_2>}
9393 No special properties. */
9395 struct deprecated_coproc_regs_s
9402 arm_feature_set deprecated
;
9403 arm_feature_set obsoleted
;
9404 const char *dep_msg
;
9405 const char *obs_msg
;
9408 #define DEPR_ACCESS_V8 \
9409 N_("This coprocessor register access is deprecated in ARMv8")
9411 /* Table of all deprecated coprocessor registers. */
9412 static struct deprecated_coproc_regs_s deprecated_coproc_regs
[] =
9414 {15, 0, 7, 10, 5, /* CP15DMB. */
9415 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9416 DEPR_ACCESS_V8
, NULL
},
9417 {15, 0, 7, 10, 4, /* CP15DSB. */
9418 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9419 DEPR_ACCESS_V8
, NULL
},
9420 {15, 0, 7, 5, 4, /* CP15ISB. */
9421 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9422 DEPR_ACCESS_V8
, NULL
},
9423 {14, 6, 1, 0, 0, /* TEEHBR. */
9424 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9425 DEPR_ACCESS_V8
, NULL
},
9426 {14, 6, 0, 0, 0, /* TEECR. */
9427 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
), ARM_ARCH_NONE
,
9428 DEPR_ACCESS_V8
, NULL
},
9431 #undef DEPR_ACCESS_V8
9433 static const size_t deprecated_coproc_reg_count
=
9434 sizeof (deprecated_coproc_regs
) / sizeof (deprecated_coproc_regs
[0]);
9442 Rd
= inst
.operands
[2].reg
;
9445 if (inst
.instruction
== 0xee000010
9446 || inst
.instruction
== 0xfe000010)
9448 reject_bad_reg (Rd
);
9449 else if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
9451 constraint (Rd
== REG_SP
, BAD_SP
);
9456 if (inst
.instruction
== 0xe000010)
9457 constraint (Rd
== REG_PC
, BAD_PC
);
9460 for (i
= 0; i
< deprecated_coproc_reg_count
; ++i
)
9462 const struct deprecated_coproc_regs_s
*r
=
9463 deprecated_coproc_regs
+ i
;
9465 if (inst
.operands
[0].reg
== r
->cp
9466 && inst
.operands
[1].imm
== r
->opc1
9467 && inst
.operands
[3].reg
== r
->crn
9468 && inst
.operands
[4].reg
== r
->crm
9469 && inst
.operands
[5].imm
== r
->opc2
)
9471 if (! ARM_CPU_IS_ANY (cpu_variant
)
9472 && warn_on_deprecated
9473 && ARM_CPU_HAS_FEATURE (cpu_variant
, r
->deprecated
))
9474 as_tsktsk ("%s", r
->dep_msg
);
9478 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9479 inst
.instruction
|= inst
.operands
[1].imm
<< 21;
9480 inst
.instruction
|= Rd
<< 12;
9481 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
9482 inst
.instruction
|= inst
.operands
[4].reg
;
9483 inst
.instruction
|= inst
.operands
[5].imm
<< 5;
9486 /* Transfer between coprocessor register and pair of ARM registers.
9487 MCRR{cond} <coproc>, <opcode>, <Rd>, <Rn>, <CRm>.
9492 Two XScale instructions are special cases of these:
9494 MAR{cond} acc0, <RdLo>, <RdHi> == MCRR{cond} p0, #0, <RdLo>, <RdHi>, c0
9495 MRA{cond} acc0, <RdLo>, <RdHi> == MRRC{cond} p0, #0, <RdLo>, <RdHi>, c0
9497 Result unpredictable if Rd or Rn is R15. */
9504 Rd
= inst
.operands
[2].reg
;
9505 Rn
= inst
.operands
[3].reg
;
9509 reject_bad_reg (Rd
);
9510 reject_bad_reg (Rn
);
9514 constraint (Rd
== REG_PC
, BAD_PC
);
9515 constraint (Rn
== REG_PC
, BAD_PC
);
9518 /* Only check the MRRC{2} variants. */
9519 if ((inst
.instruction
& 0x0FF00000) == 0x0C500000)
9521 /* If Rd == Rn, error that the operation is
9522 unpredictable (example MRRC p3,#1,r1,r1,c4). */
9523 constraint (Rd
== Rn
, BAD_OVERLAP
);
9526 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9527 inst
.instruction
|= inst
.operands
[1].imm
<< 4;
9528 inst
.instruction
|= Rd
<< 12;
9529 inst
.instruction
|= Rn
<< 16;
9530 inst
.instruction
|= inst
.operands
[4].reg
;
9536 inst
.instruction
|= inst
.operands
[0].imm
<< 6;
9537 if (inst
.operands
[1].present
)
9539 inst
.instruction
|= CPSI_MMOD
;
9540 inst
.instruction
|= inst
.operands
[1].imm
;
9547 inst
.instruction
|= inst
.operands
[0].imm
;
9553 unsigned Rd
, Rn
, Rm
;
9555 Rd
= inst
.operands
[0].reg
;
9556 Rn
= (inst
.operands
[1].present
9557 ? inst
.operands
[1].reg
: Rd
);
9558 Rm
= inst
.operands
[2].reg
;
9560 constraint ((Rd
== REG_PC
), BAD_PC
);
9561 constraint ((Rn
== REG_PC
), BAD_PC
);
9562 constraint ((Rm
== REG_PC
), BAD_PC
);
9564 inst
.instruction
|= Rd
<< 16;
9565 inst
.instruction
|= Rn
<< 0;
9566 inst
.instruction
|= Rm
<< 8;
9572 /* There is no IT instruction in ARM mode. We
9573 process it to do the validation as if in
9574 thumb mode, just in case the code gets
9575 assembled for thumb using the unified syntax. */
9580 set_pred_insn_type (IT_INSN
);
9581 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
9582 now_pred
.cc
= inst
.operands
[0].imm
;
9586 /* If there is only one register in the register list,
9587 then return its register number. Otherwise return -1. */
9589 only_one_reg_in_list (int range
)
9591 int i
= ffs (range
) - 1;
9592 return (i
> 15 || range
!= (1 << i
)) ? -1 : i
;
9596 encode_ldmstm(int from_push_pop_mnem
)
9598 int base_reg
= inst
.operands
[0].reg
;
9599 int range
= inst
.operands
[1].imm
;
9602 inst
.instruction
|= base_reg
<< 16;
9603 inst
.instruction
|= range
;
9605 if (inst
.operands
[1].writeback
)
9606 inst
.instruction
|= LDM_TYPE_2_OR_3
;
9608 if (inst
.operands
[0].writeback
)
9610 inst
.instruction
|= WRITE_BACK
;
9611 /* Check for unpredictable uses of writeback. */
9612 if (inst
.instruction
& LOAD_BIT
)
9614 /* Not allowed in LDM type 2. */
9615 if ((inst
.instruction
& LDM_TYPE_2_OR_3
)
9616 && ((range
& (1 << REG_PC
)) == 0))
9617 as_warn (_("writeback of base register is UNPREDICTABLE"));
9618 /* Only allowed if base reg not in list for other types. */
9619 else if (range
& (1 << base_reg
))
9620 as_warn (_("writeback of base register when in register list is UNPREDICTABLE"));
9624 /* Not allowed for type 2. */
9625 if (inst
.instruction
& LDM_TYPE_2_OR_3
)
9626 as_warn (_("writeback of base register is UNPREDICTABLE"));
9627 /* Only allowed if base reg not in list, or first in list. */
9628 else if ((range
& (1 << base_reg
))
9629 && (range
& ((1 << base_reg
) - 1)))
9630 as_warn (_("if writeback register is in list, it must be the lowest reg in the list"));
9634 /* If PUSH/POP has only one register, then use the A2 encoding. */
9635 one_reg
= only_one_reg_in_list (range
);
9636 if (from_push_pop_mnem
&& one_reg
>= 0)
9638 int is_push
= (inst
.instruction
& A_PUSH_POP_OP_MASK
) == A1_OPCODE_PUSH
;
9640 if (is_push
&& one_reg
== 13 /* SP */)
9641 /* PR 22483: The A2 encoding cannot be used when
9642 pushing the stack pointer as this is UNPREDICTABLE. */
9645 inst
.instruction
&= A_COND_MASK
;
9646 inst
.instruction
|= is_push
? A2_OPCODE_PUSH
: A2_OPCODE_POP
;
9647 inst
.instruction
|= one_reg
<< 12;
9654 encode_ldmstm (/*from_push_pop_mnem=*/FALSE
);
9657 /* ARMv5TE load-consecutive (argument parse)
9666 constraint (inst
.operands
[0].reg
% 2 != 0,
9667 _("first transfer register must be even"));
9668 constraint (inst
.operands
[1].present
9669 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9670 _("can only transfer two consecutive registers"));
9671 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9672 constraint (!inst
.operands
[2].isreg
, _("'[' expected"));
9674 if (!inst
.operands
[1].present
)
9675 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
9677 /* encode_arm_addr_mode_3 will diagnose overlap between the base
9678 register and the first register written; we have to diagnose
9679 overlap between the base and the second register written here. */
9681 if (inst
.operands
[2].reg
== inst
.operands
[1].reg
9682 && (inst
.operands
[2].writeback
|| inst
.operands
[2].postind
))
9683 as_warn (_("base register written back, and overlaps "
9684 "second transfer register"));
9686 if (!(inst
.instruction
& V4_STR_BIT
))
9688 /* For an index-register load, the index register must not overlap the
9689 destination (even if not write-back). */
9690 if (inst
.operands
[2].immisreg
9691 && ((unsigned) inst
.operands
[2].imm
== inst
.operands
[0].reg
9692 || (unsigned) inst
.operands
[2].imm
== inst
.operands
[1].reg
))
9693 as_warn (_("index register overlaps transfer register"));
9695 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9696 encode_arm_addr_mode_3 (2, /*is_t=*/FALSE
);
9702 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
9703 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
9704 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
9705 || inst
.operands
[1].negative
9706 /* This can arise if the programmer has written
9708 or if they have mistakenly used a register name as the last
9711 It is very difficult to distinguish between these two cases
9712 because "rX" might actually be a label. ie the register
9713 name has been occluded by a symbol of the same name. So we
9714 just generate a general 'bad addressing mode' type error
9715 message and leave it up to the programmer to discover the
9716 true cause and fix their mistake. */
9717 || (inst
.operands
[1].reg
== REG_PC
),
9720 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9721 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9722 _("offset must be zero in ARM encoding"));
9724 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
9726 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9727 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
9728 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
9734 constraint (inst
.operands
[0].reg
% 2 != 0,
9735 _("even register required"));
9736 constraint (inst
.operands
[1].present
9737 && inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
9738 _("can only load two consecutive registers"));
9739 /* If op 1 were present and equal to PC, this function wouldn't
9740 have been called in the first place. */
9741 constraint (inst
.operands
[0].reg
== REG_LR
, _("r14 not allowed here"));
9743 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9744 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
9747 /* In both ARM and thumb state 'ldr pc, #imm' with an immediate
9748 which is not a multiple of four is UNPREDICTABLE. */
9750 check_ldr_r15_aligned (void)
9752 constraint (!(inst
.operands
[1].immisreg
)
9753 && (inst
.operands
[0].reg
== REG_PC
9754 && inst
.operands
[1].reg
== REG_PC
9755 && (inst
.relocs
[0].exp
.X_add_number
& 0x3)),
9756 _("ldr to register 15 must be 4-byte aligned"));
9762 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9763 if (!inst
.operands
[1].isreg
)
9764 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/FALSE
))
9766 encode_arm_addr_mode_2 (1, /*is_t=*/FALSE
);
9767 check_ldr_r15_aligned ();
9773 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9775 if (inst
.operands
[1].preind
)
9777 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9778 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9779 _("this instruction requires a post-indexed address"));
9781 inst
.operands
[1].preind
= 0;
9782 inst
.operands
[1].postind
= 1;
9783 inst
.operands
[1].writeback
= 1;
9785 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9786 encode_arm_addr_mode_2 (1, /*is_t=*/TRUE
);
9789 /* Halfword and signed-byte load/store operations. */
9794 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
9795 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9796 if (!inst
.operands
[1].isreg
)
9797 if (move_or_literal_pool (0, CONST_ARM
, /*mode_3=*/TRUE
))
9799 encode_arm_addr_mode_3 (1, /*is_t=*/FALSE
);
9805 /* ldrt/strt always use post-indexed addressing. Turn [Rn] into [Rn]! and
9807 if (inst
.operands
[1].preind
)
9809 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
9810 || inst
.relocs
[0].exp
.X_add_number
!= 0,
9811 _("this instruction requires a post-indexed address"));
9813 inst
.operands
[1].preind
= 0;
9814 inst
.operands
[1].postind
= 1;
9815 inst
.operands
[1].writeback
= 1;
9817 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9818 encode_arm_addr_mode_3 (1, /*is_t=*/TRUE
);
9821 /* Co-processor register load/store.
9822 Format: <LDC|STC>{cond}[L] CP#,CRd,<address> */
9826 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
9827 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
9828 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
9834 /* This restriction does not apply to mls (nor to mla in v6 or later). */
9835 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
9836 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
)
9837 && !(inst
.instruction
& 0x00400000))
9838 as_tsktsk (_("Rd and Rm should be different in mla"));
9840 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
9841 inst
.instruction
|= inst
.operands
[1].reg
;
9842 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
9843 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
9849 constraint (inst
.relocs
[0].type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
9850 && inst
.relocs
[0].type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
,
9852 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9853 encode_arm_shifter_operand (1);
9856 /* ARM V6T2 16-bit immediate register load: MOV[WT]{cond} Rd, #<imm16>. */
9863 top
= (inst
.instruction
& 0x00400000) != 0;
9864 constraint (top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
,
9865 _(":lower16: not allowed in this instruction"));
9866 constraint (!top
&& inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
,
9867 _(":upper16: not allowed in this instruction"));
9868 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
9869 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
9871 imm
= inst
.relocs
[0].exp
.X_add_number
;
9872 /* The value is in two pieces: 0:11, 16:19. */
9873 inst
.instruction
|= (imm
& 0x00000fff);
9874 inst
.instruction
|= (imm
& 0x0000f000) << 4;
9879 do_vfp_nsyn_mrs (void)
9881 if (inst
.operands
[0].isvec
)
9883 if (inst
.operands
[1].reg
!= 1)
9884 first_error (_("operand 1 must be FPSCR"));
9885 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
9886 memset (&inst
.operands
[1], '\0', sizeof (inst
.operands
[1]));
9887 do_vfp_nsyn_opcode ("fmstat");
9889 else if (inst
.operands
[1].isvec
)
9890 do_vfp_nsyn_opcode ("fmrx");
9898 do_vfp_nsyn_msr (void)
9900 if (inst
.operands
[0].isvec
)
9901 do_vfp_nsyn_opcode ("fmxr");
9911 unsigned Rt
= inst
.operands
[0].reg
;
9913 if (thumb_mode
&& Rt
== REG_SP
)
9915 inst
.error
= BAD_SP
;
9919 switch (inst
.operands
[1].reg
)
9921 /* MVFR2 is only valid for Armv8-A. */
9923 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9927 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9928 case 1: /* fpscr. */
9929 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9930 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9934 case 14: /* fpcxt_ns. */
9935 case 15: /* fpcxt_s. */
9936 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
9937 _("selected processor does not support instruction"));
9940 case 2: /* fpscr_nzcvqc. */
9943 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
9944 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9945 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9946 _("selected processor does not support instruction"));
9947 if (inst
.operands
[0].reg
!= 2
9948 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
9949 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
9956 /* APSR_ sets isvec. All other refs to PC are illegal. */
9957 if (!inst
.operands
[0].isvec
&& Rt
== REG_PC
)
9959 inst
.error
= BAD_PC
;
9963 /* If we get through parsing the register name, we just insert the number
9964 generated into the instruction without further validation. */
9965 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
9966 inst
.instruction
|= (Rt
<< 12);
9972 unsigned Rt
= inst
.operands
[1].reg
;
9975 reject_bad_reg (Rt
);
9976 else if (Rt
== REG_PC
)
9978 inst
.error
= BAD_PC
;
9982 switch (inst
.operands
[0].reg
)
9984 /* MVFR2 is only valid for Armv8-A. */
9986 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
9990 /* Check for new Armv8.1-M Mainline changes to <spec_reg>. */
9992 constraint (!(ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
9993 || ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
9997 case 14: /* fpcxt_ns. */
9998 case 15: /* fpcxt_s. */
9999 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
),
10000 _("selected processor does not support instruction"));
10003 case 2: /* fpscr_nzcvqc. */
10004 case 12: /* vpr. */
10006 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8_1m_main
)
10007 || (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
10008 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)),
10009 _("selected processor does not support instruction"));
10010 if (inst
.operands
[0].reg
!= 2
10011 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
10012 as_warn (_("accessing MVE system register without MVE is UNPREDICTABLE"));
10019 /* If we get through parsing the register name, we just insert the number
10020 generated into the instruction without further validation. */
10021 inst
.instruction
|= (inst
.operands
[0].reg
<< 16);
10022 inst
.instruction
|= (Rt
<< 12);
10030 if (do_vfp_nsyn_mrs () == SUCCESS
)
10033 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
10034 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10036 if (inst
.operands
[1].isreg
)
10038 br
= inst
.operands
[1].reg
;
10039 if (((br
& 0x200) == 0) && ((br
& 0xf0000) != 0xf0000))
10040 as_bad (_("bad register for mrs"));
10044 /* mrs only accepts CPSR/SPSR/CPSR_all/SPSR_all. */
10045 constraint ((inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
))
10047 _("'APSR', 'CPSR' or 'SPSR' expected"));
10048 br
= (15<<16) | (inst
.operands
[1].imm
& SPSR_BIT
);
10051 inst
.instruction
|= br
;
10054 /* Two possible forms:
10055 "{C|S}PSR_<field>, Rm",
10056 "{C|S}PSR_f, #expression". */
10061 if (do_vfp_nsyn_msr () == SUCCESS
)
10064 inst
.instruction
|= inst
.operands
[0].imm
;
10065 if (inst
.operands
[1].isreg
)
10066 inst
.instruction
|= inst
.operands
[1].reg
;
10069 inst
.instruction
|= INST_IMMEDIATE
;
10070 inst
.relocs
[0].type
= BFD_RELOC_ARM_IMMEDIATE
;
10071 inst
.relocs
[0].pc_rel
= 0;
10078 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
10080 if (!inst
.operands
[2].present
)
10081 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
10082 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10083 inst
.instruction
|= inst
.operands
[1].reg
;
10084 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10086 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
10087 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10088 as_tsktsk (_("Rd and Rm should be different in mul"));
10091 /* Long Multiply Parser
10092 UMULL RdLo, RdHi, Rm, Rs
10093 SMULL RdLo, RdHi, Rm, Rs
10094 UMLAL RdLo, RdHi, Rm, Rs
10095 SMLAL RdLo, RdHi, Rm, Rs. */
10100 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10101 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10102 inst
.instruction
|= inst
.operands
[2].reg
;
10103 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10105 /* rdhi and rdlo must be different. */
10106 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10107 as_tsktsk (_("rdhi and rdlo must be different"));
10109 /* rdhi, rdlo and rm must all be different before armv6. */
10110 if ((inst
.operands
[0].reg
== inst
.operands
[2].reg
10111 || inst
.operands
[1].reg
== inst
.operands
[2].reg
)
10112 && !ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6
))
10113 as_tsktsk (_("rdhi, rdlo and rm must all be different"));
10119 if (inst
.operands
[0].present
10120 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6k
))
10122 /* Architectural NOP hints are CPSR sets with no bits selected. */
10123 inst
.instruction
&= 0xf0000000;
10124 inst
.instruction
|= 0x0320f000;
10125 if (inst
.operands
[0].present
)
10126 inst
.instruction
|= inst
.operands
[0].imm
;
10130 /* ARM V6 Pack Halfword Bottom Top instruction (argument parse).
10131 PKHBT {<cond>} <Rd>, <Rn>, <Rm> {, LSL #<shift_imm>}
10132 Condition defaults to COND_ALWAYS.
10133 Error if Rd, Rn or Rm are R15. */
10138 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10139 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10140 inst
.instruction
|= inst
.operands
[2].reg
;
10141 if (inst
.operands
[3].present
)
10142 encode_arm_shift (3);
10145 /* ARM V6 PKHTB (Argument Parse). */
10150 if (!inst
.operands
[3].present
)
10152 /* If the shift specifier is omitted, turn the instruction
10153 into pkhbt rd, rm, rn. */
10154 inst
.instruction
&= 0xfff00010;
10155 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10156 inst
.instruction
|= inst
.operands
[1].reg
;
10157 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10161 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10162 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10163 inst
.instruction
|= inst
.operands
[2].reg
;
10164 encode_arm_shift (3);
10168 /* ARMv5TE: Preload-Cache
10169 MP Extensions: Preload for write
10173 Syntactically, like LDR with B=1, W=0, L=1. */
10178 constraint (!inst
.operands
[0].isreg
,
10179 _("'[' expected after PLD mnemonic"));
10180 constraint (inst
.operands
[0].postind
,
10181 _("post-indexed expression used in preload instruction"));
10182 constraint (inst
.operands
[0].writeback
,
10183 _("writeback used in preload instruction"));
10184 constraint (!inst
.operands
[0].preind
,
10185 _("unindexed addressing used in preload instruction"));
10186 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10189 /* ARMv7: PLI <addr_mode> */
10193 constraint (!inst
.operands
[0].isreg
,
10194 _("'[' expected after PLI mnemonic"));
10195 constraint (inst
.operands
[0].postind
,
10196 _("post-indexed expression used in preload instruction"));
10197 constraint (inst
.operands
[0].writeback
,
10198 _("writeback used in preload instruction"));
10199 constraint (!inst
.operands
[0].preind
,
10200 _("unindexed addressing used in preload instruction"));
10201 encode_arm_addr_mode_2 (0, /*is_t=*/FALSE
);
10202 inst
.instruction
&= ~PRE_INDEX
;
10208 constraint (inst
.operands
[0].writeback
,
10209 _("push/pop do not support {reglist}^"));
10210 inst
.operands
[1] = inst
.operands
[0];
10211 memset (&inst
.operands
[0], 0, sizeof inst
.operands
[0]);
10212 inst
.operands
[0].isreg
= 1;
10213 inst
.operands
[0].writeback
= 1;
10214 inst
.operands
[0].reg
= REG_SP
;
10215 encode_ldmstm (/*from_push_pop_mnem=*/TRUE
);
10218 /* ARM V6 RFE (Return from Exception) loads the PC and CPSR from the
10219 word at the specified address and the following word
10221 Unconditionally executed.
10222 Error if Rn is R15. */
10227 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10228 if (inst
.operands
[0].writeback
)
10229 inst
.instruction
|= WRITE_BACK
;
10232 /* ARM V6 ssat (argument parse). */
10237 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10238 inst
.instruction
|= (inst
.operands
[1].imm
- 1) << 16;
10239 inst
.instruction
|= inst
.operands
[2].reg
;
10241 if (inst
.operands
[3].present
)
10242 encode_arm_shift (3);
10245 /* ARM V6 usat (argument parse). */
10250 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10251 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10252 inst
.instruction
|= inst
.operands
[2].reg
;
10254 if (inst
.operands
[3].present
)
10255 encode_arm_shift (3);
10258 /* ARM V6 ssat16 (argument parse). */
10263 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10264 inst
.instruction
|= ((inst
.operands
[1].imm
- 1) << 16);
10265 inst
.instruction
|= inst
.operands
[2].reg
;
10271 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10272 inst
.instruction
|= inst
.operands
[1].imm
<< 16;
10273 inst
.instruction
|= inst
.operands
[2].reg
;
10276 /* ARM V6 SETEND (argument parse). Sets the E bit in the CPSR while
10277 preserving the other bits.
10279 setend <endian_specifier>, where <endian_specifier> is either
10285 if (warn_on_deprecated
10286 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
10287 as_tsktsk (_("setend use is deprecated for ARMv8"));
10289 if (inst
.operands
[0].imm
)
10290 inst
.instruction
|= 0x200;
10296 unsigned int Rm
= (inst
.operands
[1].present
10297 ? inst
.operands
[1].reg
10298 : inst
.operands
[0].reg
);
10300 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10301 inst
.instruction
|= Rm
;
10302 if (inst
.operands
[2].isreg
) /* Rd, {Rm,} Rs */
10304 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10305 inst
.instruction
|= SHIFT_BY_REG
;
10306 /* PR 12854: Error on extraneous shifts. */
10307 constraint (inst
.operands
[2].shifted
,
10308 _("extraneous shift as part of operand to shift insn"));
10311 inst
.relocs
[0].type
= BFD_RELOC_ARM_SHIFT_IMM
;
10317 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
10318 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
10320 inst
.relocs
[0].type
= BFD_RELOC_ARM_SMC
;
10321 inst
.relocs
[0].pc_rel
= 0;
10327 inst
.relocs
[0].type
= BFD_RELOC_ARM_HVC
;
10328 inst
.relocs
[0].pc_rel
= 0;
10334 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
10335 inst
.relocs
[0].pc_rel
= 0;
10341 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10342 _("selected processor does not support SETPAN instruction"));
10344 inst
.instruction
|= ((inst
.operands
[0].imm
& 1) << 9);
10350 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_pan
),
10351 _("selected processor does not support SETPAN instruction"));
10353 inst
.instruction
|= (inst
.operands
[0].imm
<< 3);
10356 /* ARM V5E (El Segundo) signed-multiply-accumulate (argument parse)
10357 SMLAxy{cond} Rd,Rm,Rs,Rn
10358 SMLAWy{cond} Rd,Rm,Rs,Rn
10359 Error if any register is R15. */
10364 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10365 inst
.instruction
|= inst
.operands
[1].reg
;
10366 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10367 inst
.instruction
|= inst
.operands
[3].reg
<< 12;
10370 /* ARM V5E (El Segundo) signed-multiply-accumulate-long (argument parse)
10371 SMLALxy{cond} Rdlo,Rdhi,Rm,Rs
10372 Error if any register is R15.
10373 Warning if Rdlo == Rdhi. */
10378 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10379 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10380 inst
.instruction
|= inst
.operands
[2].reg
;
10381 inst
.instruction
|= inst
.operands
[3].reg
<< 8;
10383 if (inst
.operands
[0].reg
== inst
.operands
[1].reg
)
10384 as_tsktsk (_("rdhi and rdlo must be different"));
10387 /* ARM V5E (El Segundo) signed-multiply (argument parse)
10388 SMULxy{cond} Rd,Rm,Rs
10389 Error if any register is R15. */
10394 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10395 inst
.instruction
|= inst
.operands
[1].reg
;
10396 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
10399 /* ARM V6 srs (argument parse). The variable fields in the encoding are
10400 the same for both ARM and Thumb-2. */
10407 if (inst
.operands
[0].present
)
10409 reg
= inst
.operands
[0].reg
;
10410 constraint (reg
!= REG_SP
, _("SRS base register must be r13"));
10415 inst
.instruction
|= reg
<< 16;
10416 inst
.instruction
|= inst
.operands
[1].imm
;
10417 if (inst
.operands
[0].writeback
|| inst
.operands
[1].writeback
)
10418 inst
.instruction
|= WRITE_BACK
;
10421 /* ARM V6 strex (argument parse). */
10426 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10427 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10428 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10429 || inst
.operands
[2].negative
10430 /* See comment in do_ldrex(). */
10431 || (inst
.operands
[2].reg
== REG_PC
),
10434 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10435 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10437 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10438 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10439 _("offset must be zero in ARM encoding"));
10441 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10442 inst
.instruction
|= inst
.operands
[1].reg
;
10443 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10444 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
10448 do_t_strexbh (void)
10450 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
10451 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
10452 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
10453 || inst
.operands
[2].negative
,
10456 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10457 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10465 constraint (inst
.operands
[1].reg
% 2 != 0,
10466 _("even register required"));
10467 constraint (inst
.operands
[2].present
10468 && inst
.operands
[2].reg
!= inst
.operands
[1].reg
+ 1,
10469 _("can only store two consecutive registers"));
10470 /* If op 2 were present and equal to PC, this function wouldn't
10471 have been called in the first place. */
10472 constraint (inst
.operands
[1].reg
== REG_LR
, _("r14 not allowed here"));
10474 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10475 || inst
.operands
[0].reg
== inst
.operands
[1].reg
+ 1
10476 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
10479 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10480 inst
.instruction
|= inst
.operands
[1].reg
;
10481 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
10488 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10489 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10497 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
10498 || inst
.operands
[0].reg
== inst
.operands
[2].reg
, BAD_OVERLAP
);
10503 /* ARM V6 SXTAH extracts a 16-bit value from a register, sign
10504 extends it to 32-bits, and adds the result to a value in another
10505 register. You can specify a rotation by 0, 8, 16, or 24 bits
10506 before extracting the 16-bit value.
10507 SXTAH{<cond>} <Rd>, <Rn>, <Rm>{, <rotation>}
10508 Condition defaults to COND_ALWAYS.
10509 Error if any register uses R15. */
10514 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10515 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10516 inst
.instruction
|= inst
.operands
[2].reg
;
10517 inst
.instruction
|= inst
.operands
[3].imm
<< 10;
10522 SXTH {<cond>} <Rd>, <Rm>{, <rotation>}
10523 Condition defaults to COND_ALWAYS.
10524 Error if any register uses R15. */
10529 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10530 inst
.instruction
|= inst
.operands
[1].reg
;
10531 inst
.instruction
|= inst
.operands
[2].imm
<< 10;
10534 /* VFP instructions. In a logical order: SP variant first, monad
10535 before dyad, arithmetic then move then load/store. */
10538 do_vfp_sp_monadic (void)
10540 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10541 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10544 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10545 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10549 do_vfp_sp_dyadic (void)
10551 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10552 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10553 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10557 do_vfp_sp_compare_z (void)
10559 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10563 do_vfp_dp_sp_cvt (void)
10565 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10566 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sm
);
10570 do_vfp_sp_dp_cvt (void)
10572 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10573 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10577 do_vfp_reg_from_sp (void)
10579 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10580 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10583 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10584 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sn
);
10588 do_vfp_reg2_from_sp2 (void)
10590 constraint (inst
.operands
[2].imm
!= 2,
10591 _("only two consecutive VFP SP registers allowed here"));
10592 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10593 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10594 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Sm
);
10598 do_vfp_sp_from_reg (void)
10600 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
10601 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10604 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sn
);
10605 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10609 do_vfp_sp2_from_reg2 (void)
10611 constraint (inst
.operands
[0].imm
!= 2,
10612 _("only two consecutive VFP SP registers allowed here"));
10613 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sm
);
10614 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10615 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
10619 do_vfp_sp_ldst (void)
10621 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10622 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10626 do_vfp_dp_ldst (void)
10628 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10629 encode_arm_cp_address (1, FALSE
, TRUE
, 0);
10634 vfp_sp_ldstm (enum vfp_ldstm_type ldstm_type
)
10636 if (inst
.operands
[0].writeback
)
10637 inst
.instruction
|= WRITE_BACK
;
10639 constraint (ldstm_type
!= VFP_LDSTMIA
,
10640 _("this addressing mode requires base-register writeback"));
10641 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10642 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Sd
);
10643 inst
.instruction
|= inst
.operands
[1].imm
;
10647 vfp_dp_ldstm (enum vfp_ldstm_type ldstm_type
)
10651 if (inst
.operands
[0].writeback
)
10652 inst
.instruction
|= WRITE_BACK
;
10654 constraint (ldstm_type
!= VFP_LDSTMIA
&& ldstm_type
!= VFP_LDSTMIAX
,
10655 _("this addressing mode requires base-register writeback"));
10657 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10658 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10660 count
= inst
.operands
[1].imm
<< 1;
10661 if (ldstm_type
== VFP_LDSTMIAX
|| ldstm_type
== VFP_LDSTMDBX
)
10664 inst
.instruction
|= count
;
10668 do_vfp_sp_ldstmia (void)
10670 vfp_sp_ldstm (VFP_LDSTMIA
);
10674 do_vfp_sp_ldstmdb (void)
10676 vfp_sp_ldstm (VFP_LDSTMDB
);
10680 do_vfp_dp_ldstmia (void)
10682 vfp_dp_ldstm (VFP_LDSTMIA
);
10686 do_vfp_dp_ldstmdb (void)
10688 vfp_dp_ldstm (VFP_LDSTMDB
);
10692 do_vfp_xp_ldstmia (void)
10694 vfp_dp_ldstm (VFP_LDSTMIAX
);
10698 do_vfp_xp_ldstmdb (void)
10700 vfp_dp_ldstm (VFP_LDSTMDBX
);
10704 do_vfp_dp_rd_rm (void)
10706 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
10707 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10710 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10711 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dm
);
10715 do_vfp_dp_rn_rd (void)
10717 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dn
);
10718 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10722 do_vfp_dp_rd_rn (void)
10724 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10725 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10729 do_vfp_dp_rd_rn_rm (void)
10731 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10732 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10735 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10736 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dn
);
10737 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dm
);
10741 do_vfp_dp_rd (void)
10743 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10747 do_vfp_dp_rm_rd_rn (void)
10749 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
10750 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
10753 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dm
);
10754 encode_arm_vfp_reg (inst
.operands
[1].reg
, VFP_REG_Dd
);
10755 encode_arm_vfp_reg (inst
.operands
[2].reg
, VFP_REG_Dn
);
10758 /* VFPv3 instructions. */
10760 do_vfp_sp_const (void)
10762 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10763 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10764 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10768 do_vfp_dp_const (void)
10770 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10771 inst
.instruction
|= (inst
.operands
[1].imm
& 0xf0) << 12;
10772 inst
.instruction
|= (inst
.operands
[1].imm
& 0x0f);
10776 vfp_conv (int srcsize
)
10778 int immbits
= srcsize
- inst
.operands
[1].imm
;
10780 if (srcsize
== 16 && !(immbits
>= 0 && immbits
<= srcsize
))
10782 /* If srcsize is 16, inst.operands[1].imm must be in the range 0-16.
10783 i.e. immbits must be in range 0 - 16. */
10784 inst
.error
= _("immediate value out of range, expected range [0, 16]");
10787 else if (srcsize
== 32 && !(immbits
>= 0 && immbits
< srcsize
))
10789 /* If srcsize is 32, inst.operands[1].imm must be in the range 1-32.
10790 i.e. immbits must be in range 0 - 31. */
10791 inst
.error
= _("immediate value out of range, expected range [1, 32]");
10795 inst
.instruction
|= (immbits
& 1) << 5;
10796 inst
.instruction
|= (immbits
>> 1);
10800 do_vfp_sp_conv_16 (void)
10802 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10807 do_vfp_dp_conv_16 (void)
10809 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10814 do_vfp_sp_conv_32 (void)
10816 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
10821 do_vfp_dp_conv_32 (void)
10823 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Dd
);
10827 /* FPA instructions. Also in a logical order. */
10832 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10833 inst
.instruction
|= inst
.operands
[1].reg
;
10837 do_fpa_ldmstm (void)
10839 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10840 switch (inst
.operands
[1].imm
)
10842 case 1: inst
.instruction
|= CP_T_X
; break;
10843 case 2: inst
.instruction
|= CP_T_Y
; break;
10844 case 3: inst
.instruction
|= CP_T_Y
| CP_T_X
; break;
10849 if (inst
.instruction
& (PRE_INDEX
| INDEX_UP
))
10851 /* The instruction specified "ea" or "fd", so we can only accept
10852 [Rn]{!}. The instruction does not really support stacking or
10853 unstacking, so we have to emulate these by setting appropriate
10854 bits and offsets. */
10855 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
10856 || inst
.relocs
[0].exp
.X_add_number
!= 0,
10857 _("this instruction does not support indexing"));
10859 if ((inst
.instruction
& PRE_INDEX
) || inst
.operands
[2].writeback
)
10860 inst
.relocs
[0].exp
.X_add_number
= 12 * inst
.operands
[1].imm
;
10862 if (!(inst
.instruction
& INDEX_UP
))
10863 inst
.relocs
[0].exp
.X_add_number
= -inst
.relocs
[0].exp
.X_add_number
;
10865 if (!(inst
.instruction
& PRE_INDEX
) && inst
.operands
[2].writeback
)
10867 inst
.operands
[2].preind
= 0;
10868 inst
.operands
[2].postind
= 1;
10872 encode_arm_cp_address (2, TRUE
, TRUE
, 0);
10875 /* iWMMXt instructions: strictly in alphabetical order. */
10878 do_iwmmxt_tandorc (void)
10880 constraint (inst
.operands
[0].reg
!= REG_PC
, _("only r15 allowed here"));
10884 do_iwmmxt_textrc (void)
10886 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10887 inst
.instruction
|= inst
.operands
[1].imm
;
10891 do_iwmmxt_textrm (void)
10893 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10894 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10895 inst
.instruction
|= inst
.operands
[2].imm
;
10899 do_iwmmxt_tinsr (void)
10901 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
10902 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
10903 inst
.instruction
|= inst
.operands
[2].imm
;
10907 do_iwmmxt_tmia (void)
10909 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
10910 inst
.instruction
|= inst
.operands
[1].reg
;
10911 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
10915 do_iwmmxt_waligni (void)
10917 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10918 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10919 inst
.instruction
|= inst
.operands
[2].reg
;
10920 inst
.instruction
|= inst
.operands
[3].imm
<< 20;
10924 do_iwmmxt_wmerge (void)
10926 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10927 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10928 inst
.instruction
|= inst
.operands
[2].reg
;
10929 inst
.instruction
|= inst
.operands
[3].imm
<< 21;
10933 do_iwmmxt_wmov (void)
10935 /* WMOV rD, rN is an alias for WOR rD, rN, rN. */
10936 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10937 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10938 inst
.instruction
|= inst
.operands
[1].reg
;
10942 do_iwmmxt_wldstbh (void)
10945 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10947 reloc
= BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
;
10949 reloc
= BFD_RELOC_ARM_CP_OFF_IMM_S2
;
10950 encode_arm_cp_address (1, TRUE
, FALSE
, reloc
);
10954 do_iwmmxt_wldstw (void)
10956 /* RIWR_RIWC clears .isreg for a control register. */
10957 if (!inst
.operands
[0].isreg
)
10959 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
10960 inst
.instruction
|= 0xf0000000;
10963 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10964 encode_arm_cp_address (1, TRUE
, TRUE
, 0);
10968 do_iwmmxt_wldstd (void)
10970 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10971 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
)
10972 && inst
.operands
[1].immisreg
)
10974 inst
.instruction
&= ~0x1a000ff;
10975 inst
.instruction
|= (0xfU
<< 28);
10976 if (inst
.operands
[1].preind
)
10977 inst
.instruction
|= PRE_INDEX
;
10978 if (!inst
.operands
[1].negative
)
10979 inst
.instruction
|= INDEX_UP
;
10980 if (inst
.operands
[1].writeback
)
10981 inst
.instruction
|= WRITE_BACK
;
10982 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10983 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
10984 inst
.instruction
|= inst
.operands
[1].imm
;
10987 encode_arm_cp_address (1, TRUE
, FALSE
, 0);
10991 do_iwmmxt_wshufh (void)
10993 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
10994 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
10995 inst
.instruction
|= ((inst
.operands
[2].imm
& 0xf0) << 16);
10996 inst
.instruction
|= (inst
.operands
[2].imm
& 0x0f);
11000 do_iwmmxt_wzero (void)
11002 /* WZERO reg is an alias for WANDN reg, reg, reg. */
11003 inst
.instruction
|= inst
.operands
[0].reg
;
11004 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11005 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11009 do_iwmmxt_wrwrwr_or_imm5 (void)
11011 if (inst
.operands
[2].isreg
)
11014 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
),
11015 _("immediate operand requires iWMMXt2"));
11017 if (inst
.operands
[2].imm
== 0)
11019 switch ((inst
.instruction
>> 20) & 0xf)
11025 /* w...h wrd, wrn, #0 -> wrorh wrd, wrn, #16. */
11026 inst
.operands
[2].imm
= 16;
11027 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0x7 << 20);
11033 /* w...w wrd, wrn, #0 -> wrorw wrd, wrn, #32. */
11034 inst
.operands
[2].imm
= 32;
11035 inst
.instruction
= (inst
.instruction
& 0xff0fffff) | (0xb << 20);
11042 /* w...d wrd, wrn, #0 -> wor wrd, wrn, wrn. */
11044 wrn
= (inst
.instruction
>> 16) & 0xf;
11045 inst
.instruction
&= 0xff0fff0f;
11046 inst
.instruction
|= wrn
;
11047 /* Bail out here; the instruction is now assembled. */
11052 /* Map 32 -> 0, etc. */
11053 inst
.operands
[2].imm
&= 0x1f;
11054 inst
.instruction
|= (0xfU
<< 28) | ((inst
.operands
[2].imm
& 0x10) << 4) | (inst
.operands
[2].imm
& 0xf);
11058 /* Cirrus Maverick instructions. Simple 2-, 3-, and 4-register
11059 operations first, then control, shift, and load/store. */
11061 /* Insns like "foo X,Y,Z". */
11064 do_mav_triple (void)
11066 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
11067 inst
.instruction
|= inst
.operands
[1].reg
;
11068 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11071 /* Insns like "foo W,X,Y,Z".
11072 where W=MVAX[0:3] and X,Y,Z=MVFX[0:15]. */
11077 inst
.instruction
|= inst
.operands
[0].reg
<< 5;
11078 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11079 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11080 inst
.instruction
|= inst
.operands
[3].reg
;
11083 /* cfmvsc32<cond> DSPSC,MVDX[15:0]. */
11085 do_mav_dspsc (void)
11087 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11090 /* Maverick shift immediate instructions.
11091 cfsh32<cond> MVFX[15:0],MVFX[15:0],Shift[6:0].
11092 cfsh64<cond> MVDX[15:0],MVDX[15:0],Shift[6:0]. */
11095 do_mav_shift (void)
11097 int imm
= inst
.operands
[2].imm
;
11099 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11100 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11102 /* Bits 0-3 of the insn should have bits 0-3 of the immediate.
11103 Bits 5-7 of the insn should have bits 4-6 of the immediate.
11104 Bit 4 should be 0. */
11105 imm
= (imm
& 0xf) | ((imm
& 0x70) << 1);
11107 inst
.instruction
|= imm
;
11110 /* XScale instructions. Also sorted arithmetic before move. */
11112 /* Xscale multiply-accumulate (argument parse)
11115 MIAxycc acc0,Rm,Rs. */
11120 inst
.instruction
|= inst
.operands
[1].reg
;
11121 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
11124 /* Xscale move-accumulator-register (argument parse)
11126 MARcc acc0,RdLo,RdHi. */
11131 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
11132 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
11135 /* Xscale move-register-accumulator (argument parse)
11137 MRAcc RdLo,RdHi,acc0. */
11142 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
11143 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
11144 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
11147 /* Encoding functions relevant only to Thumb. */
11149 /* inst.operands[i] is a shifted-register operand; encode
11150 it into inst.instruction in the format used by Thumb32. */
11153 encode_thumb32_shifted_operand (int i
)
11155 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11156 unsigned int shift
= inst
.operands
[i
].shift_kind
;
11158 constraint (inst
.operands
[i
].immisreg
,
11159 _("shift by register not allowed in thumb mode"));
11160 inst
.instruction
|= inst
.operands
[i
].reg
;
11161 if (shift
== SHIFT_RRX
)
11162 inst
.instruction
|= SHIFT_ROR
<< 4;
11165 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11166 _("expression too complex"));
11168 constraint (value
> 32
11169 || (value
== 32 && (shift
== SHIFT_LSL
11170 || shift
== SHIFT_ROR
)),
11171 _("shift expression is too large"));
11175 else if (value
== 32)
11178 inst
.instruction
|= shift
<< 4;
11179 inst
.instruction
|= (value
& 0x1c) << 10;
11180 inst
.instruction
|= (value
& 0x03) << 6;
11185 /* inst.operands[i] was set up by parse_address. Encode it into a
11186 Thumb32 format load or store instruction. Reject forms that cannot
11187 be used with such instructions. If is_t is true, reject forms that
11188 cannot be used with a T instruction; if is_d is true, reject forms
11189 that cannot be used with a D instruction. If it is a store insn,
11190 reject PC in Rn. */
11193 encode_thumb32_addr_mode (int i
, bfd_boolean is_t
, bfd_boolean is_d
)
11195 const bfd_boolean is_pc
= (inst
.operands
[i
].reg
== REG_PC
);
11197 constraint (!inst
.operands
[i
].isreg
,
11198 _("Instruction does not support =N addresses"));
11200 inst
.instruction
|= inst
.operands
[i
].reg
<< 16;
11201 if (inst
.operands
[i
].immisreg
)
11203 constraint (is_pc
, BAD_PC_ADDRESSING
);
11204 constraint (is_t
|| is_d
, _("cannot use register index with this instruction"));
11205 constraint (inst
.operands
[i
].negative
,
11206 _("Thumb does not support negative register indexing"));
11207 constraint (inst
.operands
[i
].postind
,
11208 _("Thumb does not support register post-indexing"));
11209 constraint (inst
.operands
[i
].writeback
,
11210 _("Thumb does not support register indexing with writeback"));
11211 constraint (inst
.operands
[i
].shifted
&& inst
.operands
[i
].shift_kind
!= SHIFT_LSL
,
11212 _("Thumb supports only LSL in shifted register indexing"));
11214 inst
.instruction
|= inst
.operands
[i
].imm
;
11215 if (inst
.operands
[i
].shifted
)
11217 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11218 _("expression too complex"));
11219 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11220 || inst
.relocs
[0].exp
.X_add_number
> 3,
11221 _("shift out of range"));
11222 inst
.instruction
|= inst
.relocs
[0].exp
.X_add_number
<< 4;
11224 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11226 else if (inst
.operands
[i
].preind
)
11228 constraint (is_pc
&& inst
.operands
[i
].writeback
, BAD_PC_WRITEBACK
);
11229 constraint (is_t
&& inst
.operands
[i
].writeback
,
11230 _("cannot use writeback with this instruction"));
11231 constraint (is_pc
&& ((inst
.instruction
& THUMB2_LOAD_BIT
) == 0),
11232 BAD_PC_ADDRESSING
);
11236 inst
.instruction
|= 0x01000000;
11237 if (inst
.operands
[i
].writeback
)
11238 inst
.instruction
|= 0x00200000;
11242 inst
.instruction
|= 0x00000c00;
11243 if (inst
.operands
[i
].writeback
)
11244 inst
.instruction
|= 0x00000100;
11246 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11248 else if (inst
.operands
[i
].postind
)
11250 gas_assert (inst
.operands
[i
].writeback
);
11251 constraint (is_pc
, _("cannot use post-indexing with PC-relative addressing"));
11252 constraint (is_t
, _("cannot use post-indexing with this instruction"));
11255 inst
.instruction
|= 0x00200000;
11257 inst
.instruction
|= 0x00000900;
11258 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
11260 else /* unindexed - only for coprocessor */
11261 inst
.error
= _("instruction does not accept unindexed addressing");
11264 /* Table of Thumb instructions which exist in 16- and/or 32-bit
11265 encodings (the latter only in post-V6T2 cores). The index is the
11266 value used in the insns table below. When there is more than one
11267 possible 16-bit encoding for the instruction, this table always
11269 Also contains several pseudo-instructions used during relaxation. */
11270 #define T16_32_TAB \
11271 X(_adc, 4140, eb400000), \
11272 X(_adcs, 4140, eb500000), \
11273 X(_add, 1c00, eb000000), \
11274 X(_adds, 1c00, eb100000), \
11275 X(_addi, 0000, f1000000), \
11276 X(_addis, 0000, f1100000), \
11277 X(_add_pc,000f, f20f0000), \
11278 X(_add_sp,000d, f10d0000), \
11279 X(_adr, 000f, f20f0000), \
11280 X(_and, 4000, ea000000), \
11281 X(_ands, 4000, ea100000), \
11282 X(_asr, 1000, fa40f000), \
11283 X(_asrs, 1000, fa50f000), \
11284 X(_b, e000, f000b000), \
11285 X(_bcond, d000, f0008000), \
11286 X(_bf, 0000, f040e001), \
11287 X(_bfcsel,0000, f000e001), \
11288 X(_bfx, 0000, f060e001), \
11289 X(_bfl, 0000, f000c001), \
11290 X(_bflx, 0000, f070e001), \
11291 X(_bic, 4380, ea200000), \
11292 X(_bics, 4380, ea300000), \
11293 X(_cinc, 0000, ea509000), \
11294 X(_cinv, 0000, ea50a000), \
11295 X(_cmn, 42c0, eb100f00), \
11296 X(_cmp, 2800, ebb00f00), \
11297 X(_cneg, 0000, ea50b000), \
11298 X(_cpsie, b660, f3af8400), \
11299 X(_cpsid, b670, f3af8600), \
11300 X(_cpy, 4600, ea4f0000), \
11301 X(_csel, 0000, ea508000), \
11302 X(_cset, 0000, ea5f900f), \
11303 X(_csetm, 0000, ea5fa00f), \
11304 X(_csinc, 0000, ea509000), \
11305 X(_csinv, 0000, ea50a000), \
11306 X(_csneg, 0000, ea50b000), \
11307 X(_dec_sp,80dd, f1ad0d00), \
11308 X(_dls, 0000, f040e001), \
11309 X(_dlstp, 0000, f000e001), \
11310 X(_eor, 4040, ea800000), \
11311 X(_eors, 4040, ea900000), \
11312 X(_inc_sp,00dd, f10d0d00), \
11313 X(_lctp, 0000, f00fe001), \
11314 X(_ldmia, c800, e8900000), \
11315 X(_ldr, 6800, f8500000), \
11316 X(_ldrb, 7800, f8100000), \
11317 X(_ldrh, 8800, f8300000), \
11318 X(_ldrsb, 5600, f9100000), \
11319 X(_ldrsh, 5e00, f9300000), \
11320 X(_ldr_pc,4800, f85f0000), \
11321 X(_ldr_pc2,4800, f85f0000), \
11322 X(_ldr_sp,9800, f85d0000), \
11323 X(_le, 0000, f00fc001), \
11324 X(_letp, 0000, f01fc001), \
11325 X(_lsl, 0000, fa00f000), \
11326 X(_lsls, 0000, fa10f000), \
11327 X(_lsr, 0800, fa20f000), \
11328 X(_lsrs, 0800, fa30f000), \
11329 X(_mov, 2000, ea4f0000), \
11330 X(_movs, 2000, ea5f0000), \
11331 X(_mul, 4340, fb00f000), \
11332 X(_muls, 4340, ffffffff), /* no 32b muls */ \
11333 X(_mvn, 43c0, ea6f0000), \
11334 X(_mvns, 43c0, ea7f0000), \
11335 X(_neg, 4240, f1c00000), /* rsb #0 */ \
11336 X(_negs, 4240, f1d00000), /* rsbs #0 */ \
11337 X(_orr, 4300, ea400000), \
11338 X(_orrs, 4300, ea500000), \
11339 X(_pop, bc00, e8bd0000), /* ldmia sp!,... */ \
11340 X(_push, b400, e92d0000), /* stmdb sp!,... */ \
11341 X(_rev, ba00, fa90f080), \
11342 X(_rev16, ba40, fa90f090), \
11343 X(_revsh, bac0, fa90f0b0), \
11344 X(_ror, 41c0, fa60f000), \
11345 X(_rors, 41c0, fa70f000), \
11346 X(_sbc, 4180, eb600000), \
11347 X(_sbcs, 4180, eb700000), \
11348 X(_stmia, c000, e8800000), \
11349 X(_str, 6000, f8400000), \
11350 X(_strb, 7000, f8000000), \
11351 X(_strh, 8000, f8200000), \
11352 X(_str_sp,9000, f84d0000), \
11353 X(_sub, 1e00, eba00000), \
11354 X(_subs, 1e00, ebb00000), \
11355 X(_subi, 8000, f1a00000), \
11356 X(_subis, 8000, f1b00000), \
11357 X(_sxtb, b240, fa4ff080), \
11358 X(_sxth, b200, fa0ff080), \
11359 X(_tst, 4200, ea100f00), \
11360 X(_uxtb, b2c0, fa5ff080), \
11361 X(_uxth, b280, fa1ff080), \
11362 X(_nop, bf00, f3af8000), \
11363 X(_yield, bf10, f3af8001), \
11364 X(_wfe, bf20, f3af8002), \
11365 X(_wfi, bf30, f3af8003), \
11366 X(_wls, 0000, f040c001), \
11367 X(_wlstp, 0000, f000c001), \
11368 X(_sev, bf40, f3af8004), \
11369 X(_sevl, bf50, f3af8005), \
11370 X(_udf, de00, f7f0a000)
11372 /* To catch errors in encoding functions, the codes are all offset by
11373 0xF800, putting them in one of the 32-bit prefix ranges, ergo undefined
11374 as 16-bit instructions. */
11375 #define X(a,b,c) T_MNEM##a
11376 enum t16_32_codes
{ T16_32_OFFSET
= 0xF7FF, T16_32_TAB
};
11379 #define X(a,b,c) 0x##b
11380 static const unsigned short thumb_op16
[] = { T16_32_TAB
};
11381 #define THUMB_OP16(n) (thumb_op16[(n) - (T16_32_OFFSET + 1)])
11384 #define X(a,b,c) 0x##c
11385 static const unsigned int thumb_op32
[] = { T16_32_TAB
};
11386 #define THUMB_OP32(n) (thumb_op32[(n) - (T16_32_OFFSET + 1)])
11387 #define THUMB_SETS_FLAGS(n) (THUMB_OP32 (n) & 0x00100000)
11391 /* Thumb instruction encoders, in alphabetical order. */
11393 /* ADDW or SUBW. */
11396 do_t_add_sub_w (void)
11400 Rd
= inst
.operands
[0].reg
;
11401 Rn
= inst
.operands
[1].reg
;
11403 /* If Rn is REG_PC, this is ADR; if Rn is REG_SP, then this
11404 is the SP-{plus,minus}-immediate form of the instruction. */
11406 constraint (Rd
== REG_PC
, BAD_PC
);
11408 reject_bad_reg (Rd
);
11410 inst
.instruction
|= (Rn
<< 16) | (Rd
<< 8);
11411 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11414 /* Parse an add or subtract instruction. We get here with inst.instruction
11415 equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
11418 do_t_add_sub (void)
11422 Rd
= inst
.operands
[0].reg
;
11423 Rs
= (inst
.operands
[1].present
11424 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11425 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11428 set_pred_insn_type_last ();
11430 if (unified_syntax
)
11433 bfd_boolean narrow
;
11436 flags
= (inst
.instruction
== T_MNEM_adds
11437 || inst
.instruction
== T_MNEM_subs
);
11439 narrow
= !in_pred_block ();
11441 narrow
= in_pred_block ();
11442 if (!inst
.operands
[2].isreg
)
11446 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11447 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11449 add
= (inst
.instruction
== T_MNEM_add
11450 || inst
.instruction
== T_MNEM_adds
);
11452 if (inst
.size_req
!= 4)
11454 /* Attempt to use a narrow opcode, with relaxation if
11456 if (Rd
== REG_SP
&& Rs
== REG_SP
&& !flags
)
11457 opcode
= add
? T_MNEM_inc_sp
: T_MNEM_dec_sp
;
11458 else if (Rd
<= 7 && Rs
== REG_SP
&& add
&& !flags
)
11459 opcode
= T_MNEM_add_sp
;
11460 else if (Rd
<= 7 && Rs
== REG_PC
&& add
&& !flags
)
11461 opcode
= T_MNEM_add_pc
;
11462 else if (Rd
<= 7 && Rs
<= 7 && narrow
)
11465 opcode
= add
? T_MNEM_addis
: T_MNEM_subis
;
11467 opcode
= add
? T_MNEM_addi
: T_MNEM_subi
;
11471 inst
.instruction
= THUMB_OP16(opcode
);
11472 inst
.instruction
|= (Rd
<< 4) | Rs
;
11473 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
11474 || (inst
.relocs
[0].type
11475 > BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
))
11477 if (inst
.size_req
== 2)
11478 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11480 inst
.relax
= opcode
;
11484 constraint (inst
.size_req
== 2, BAD_HIREG
);
11486 if (inst
.size_req
== 4
11487 || (inst
.size_req
!= 2 && !opcode
))
11489 constraint ((inst
.relocs
[0].type
11490 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
11491 && (inst
.relocs
[0].type
11492 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
11493 THUMB1_RELOC_ONLY
);
11496 constraint (add
, BAD_PC
);
11497 constraint (Rs
!= REG_LR
|| inst
.instruction
!= T_MNEM_subs
,
11498 _("only SUBS PC, LR, #const allowed"));
11499 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
11500 _("expression too complex"));
11501 constraint (inst
.relocs
[0].exp
.X_add_number
< 0
11502 || inst
.relocs
[0].exp
.X_add_number
> 0xff,
11503 _("immediate value out of range"));
11504 inst
.instruction
= T2_SUBS_PC_LR
11505 | inst
.relocs
[0].exp
.X_add_number
;
11506 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
11509 else if (Rs
== REG_PC
)
11511 /* Always use addw/subw. */
11512 inst
.instruction
= add
? 0xf20f0000 : 0xf2af0000;
11513 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMM12
;
11517 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11518 inst
.instruction
= (inst
.instruction
& 0xe1ffffff)
11521 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11523 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_IMM
;
11525 inst
.instruction
|= Rd
<< 8;
11526 inst
.instruction
|= Rs
<< 16;
11531 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
11532 unsigned int shift
= inst
.operands
[2].shift_kind
;
11534 Rn
= inst
.operands
[2].reg
;
11535 /* See if we can do this with a 16-bit instruction. */
11536 if (!inst
.operands
[2].shifted
&& inst
.size_req
!= 4)
11538 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11543 inst
.instruction
= ((inst
.instruction
== T_MNEM_adds
11544 || inst
.instruction
== T_MNEM_add
)
11546 : T_OPCODE_SUB_R3
);
11547 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11551 if (inst
.instruction
== T_MNEM_add
&& (Rd
== Rs
|| Rd
== Rn
))
11553 /* Thumb-1 cores (except v6-M) require at least one high
11554 register in a narrow non flag setting add. */
11555 if (Rd
> 7 || Rn
> 7
11556 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
)
11557 || ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_msr
))
11564 inst
.instruction
= T_OPCODE_ADD_HI
;
11565 inst
.instruction
|= (Rd
& 8) << 4;
11566 inst
.instruction
|= (Rd
& 7);
11567 inst
.instruction
|= Rn
<< 3;
11573 constraint (Rd
== REG_PC
, BAD_PC
);
11574 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
11575 constraint (Rd
== REG_SP
&& Rs
!= REG_SP
, BAD_SP
);
11576 constraint (Rs
== REG_PC
, BAD_PC
);
11577 reject_bad_reg (Rn
);
11579 /* If we get here, it can't be done in 16 bits. */
11580 constraint (inst
.operands
[2].shifted
&& inst
.operands
[2].immisreg
,
11581 _("shift must be constant"));
11582 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11583 inst
.instruction
|= Rd
<< 8;
11584 inst
.instruction
|= Rs
<< 16;
11585 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& value
> 3,
11586 _("shift value over 3 not allowed in thumb mode"));
11587 constraint (Rd
== REG_SP
&& Rs
== REG_SP
&& shift
!= SHIFT_LSL
,
11588 _("only LSL shift allowed in thumb mode"));
11589 encode_thumb32_shifted_operand (2);
11594 constraint (inst
.instruction
== T_MNEM_adds
11595 || inst
.instruction
== T_MNEM_subs
,
11598 if (!inst
.operands
[2].isreg
) /* Rd, Rs, #imm */
11600 constraint ((Rd
> 7 && (Rd
!= REG_SP
|| Rs
!= REG_SP
))
11601 || (Rs
> 7 && Rs
!= REG_SP
&& Rs
!= REG_PC
),
11604 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11605 ? 0x0000 : 0x8000);
11606 inst
.instruction
|= (Rd
<< 4) | Rs
;
11607 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11611 Rn
= inst
.operands
[2].reg
;
11612 constraint (inst
.operands
[2].shifted
, _("unshifted register required"));
11614 /* We now have Rd, Rs, and Rn set to registers. */
11615 if (Rd
> 7 || Rs
> 7 || Rn
> 7)
11617 /* Can't do this for SUB. */
11618 constraint (inst
.instruction
== T_MNEM_sub
, BAD_HIREG
);
11619 inst
.instruction
= T_OPCODE_ADD_HI
;
11620 inst
.instruction
|= (Rd
& 8) << 4;
11621 inst
.instruction
|= (Rd
& 7);
11623 inst
.instruction
|= Rn
<< 3;
11625 inst
.instruction
|= Rs
<< 3;
11627 constraint (1, _("dest must overlap one source register"));
11631 inst
.instruction
= (inst
.instruction
== T_MNEM_add
11632 ? T_OPCODE_ADD_R3
: T_OPCODE_SUB_R3
);
11633 inst
.instruction
|= Rd
| (Rs
<< 3) | (Rn
<< 6);
11643 Rd
= inst
.operands
[0].reg
;
11644 reject_bad_reg (Rd
);
11646 if (unified_syntax
&& inst
.size_req
== 0 && Rd
<= 7)
11648 /* Defer to section relaxation. */
11649 inst
.relax
= inst
.instruction
;
11650 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11651 inst
.instruction
|= Rd
<< 4;
11653 else if (unified_syntax
&& inst
.size_req
!= 2)
11655 /* Generate a 32-bit opcode. */
11656 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11657 inst
.instruction
|= Rd
<< 8;
11658 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_ADD_PC12
;
11659 inst
.relocs
[0].pc_rel
= 1;
11663 /* Generate a 16-bit opcode. */
11664 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11665 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_ADD
;
11666 inst
.relocs
[0].exp
.X_add_number
-= 4; /* PC relative adjust. */
11667 inst
.relocs
[0].pc_rel
= 1;
11668 inst
.instruction
|= Rd
<< 4;
11671 if (inst
.relocs
[0].exp
.X_op
== O_symbol
11672 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
11673 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
11674 && THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
11675 inst
.relocs
[0].exp
.X_add_number
+= 1;
11678 /* Arithmetic instructions for which there is just one 16-bit
11679 instruction encoding, and it allows only two low registers.
11680 For maximal compatibility with ARM syntax, we allow three register
11681 operands even when Thumb-32 instructions are not available, as long
11682 as the first two are identical. For instance, both "sbc r0,r1" and
11683 "sbc r0,r0,r1" are allowed. */
11689 Rd
= inst
.operands
[0].reg
;
11690 Rs
= (inst
.operands
[1].present
11691 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11692 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11693 Rn
= inst
.operands
[2].reg
;
11695 reject_bad_reg (Rd
);
11696 reject_bad_reg (Rs
);
11697 if (inst
.operands
[2].isreg
)
11698 reject_bad_reg (Rn
);
11700 if (unified_syntax
)
11702 if (!inst
.operands
[2].isreg
)
11704 /* For an immediate, we always generate a 32-bit opcode;
11705 section relaxation will shrink it later if possible. */
11706 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11707 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11708 inst
.instruction
|= Rd
<< 8;
11709 inst
.instruction
|= Rs
<< 16;
11710 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11714 bfd_boolean narrow
;
11716 /* See if we can do this with a 16-bit instruction. */
11717 if (THUMB_SETS_FLAGS (inst
.instruction
))
11718 narrow
= !in_pred_block ();
11720 narrow
= in_pred_block ();
11722 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11724 if (inst
.operands
[2].shifted
)
11726 if (inst
.size_req
== 4)
11732 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11733 inst
.instruction
|= Rd
;
11734 inst
.instruction
|= Rn
<< 3;
11738 /* If we get here, it can't be done in 16 bits. */
11739 constraint (inst
.operands
[2].shifted
11740 && inst
.operands
[2].immisreg
,
11741 _("shift must be constant"));
11742 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11743 inst
.instruction
|= Rd
<< 8;
11744 inst
.instruction
|= Rs
<< 16;
11745 encode_thumb32_shifted_operand (2);
11750 /* On its face this is a lie - the instruction does set the
11751 flags. However, the only supported mnemonic in this mode
11752 says it doesn't. */
11753 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11755 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11756 _("unshifted register required"));
11757 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11758 constraint (Rd
!= Rs
,
11759 _("dest and source1 must be the same register"));
11761 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11762 inst
.instruction
|= Rd
;
11763 inst
.instruction
|= Rn
<< 3;
11767 /* Similarly, but for instructions where the arithmetic operation is
11768 commutative, so we can allow either of them to be different from
11769 the destination operand in a 16-bit instruction. For instance, all
11770 three of "adc r0,r1", "adc r0,r0,r1", and "adc r0,r1,r0" are
11777 Rd
= inst
.operands
[0].reg
;
11778 Rs
= (inst
.operands
[1].present
11779 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
11780 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
11781 Rn
= inst
.operands
[2].reg
;
11783 reject_bad_reg (Rd
);
11784 reject_bad_reg (Rs
);
11785 if (inst
.operands
[2].isreg
)
11786 reject_bad_reg (Rn
);
11788 if (unified_syntax
)
11790 if (!inst
.operands
[2].isreg
)
11792 /* For an immediate, we always generate a 32-bit opcode;
11793 section relaxation will shrink it later if possible. */
11794 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11795 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
11796 inst
.instruction
|= Rd
<< 8;
11797 inst
.instruction
|= Rs
<< 16;
11798 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
11802 bfd_boolean narrow
;
11804 /* See if we can do this with a 16-bit instruction. */
11805 if (THUMB_SETS_FLAGS (inst
.instruction
))
11806 narrow
= !in_pred_block ();
11808 narrow
= in_pred_block ();
11810 if (Rd
> 7 || Rn
> 7 || Rs
> 7)
11812 if (inst
.operands
[2].shifted
)
11814 if (inst
.size_req
== 4)
11821 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11822 inst
.instruction
|= Rd
;
11823 inst
.instruction
|= Rn
<< 3;
11828 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11829 inst
.instruction
|= Rd
;
11830 inst
.instruction
|= Rs
<< 3;
11835 /* If we get here, it can't be done in 16 bits. */
11836 constraint (inst
.operands
[2].shifted
11837 && inst
.operands
[2].immisreg
,
11838 _("shift must be constant"));
11839 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
11840 inst
.instruction
|= Rd
<< 8;
11841 inst
.instruction
|= Rs
<< 16;
11842 encode_thumb32_shifted_operand (2);
11847 /* On its face this is a lie - the instruction does set the
11848 flags. However, the only supported mnemonic in this mode
11849 says it doesn't. */
11850 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
11852 constraint (!inst
.operands
[2].isreg
|| inst
.operands
[2].shifted
,
11853 _("unshifted register required"));
11854 constraint (Rd
> 7 || Rs
> 7 || Rn
> 7, BAD_HIREG
);
11856 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
11857 inst
.instruction
|= Rd
;
11860 inst
.instruction
|= Rn
<< 3;
11862 inst
.instruction
|= Rs
<< 3;
11864 constraint (1, _("dest must overlap one source register"));
11872 unsigned int msb
= inst
.operands
[1].imm
+ inst
.operands
[2].imm
;
11873 constraint (msb
> 32, _("bit-field extends past end of register"));
11874 /* The instruction encoding stores the LSB and MSB,
11875 not the LSB and width. */
11876 Rd
= inst
.operands
[0].reg
;
11877 reject_bad_reg (Rd
);
11878 inst
.instruction
|= Rd
<< 8;
11879 inst
.instruction
|= (inst
.operands
[1].imm
& 0x1c) << 10;
11880 inst
.instruction
|= (inst
.operands
[1].imm
& 0x03) << 6;
11881 inst
.instruction
|= msb
- 1;
11890 Rd
= inst
.operands
[0].reg
;
11891 reject_bad_reg (Rd
);
11893 /* #0 in second position is alternative syntax for bfc, which is
11894 the same instruction but with REG_PC in the Rm field. */
11895 if (!inst
.operands
[1].isreg
)
11899 Rn
= inst
.operands
[1].reg
;
11900 reject_bad_reg (Rn
);
11903 msb
= inst
.operands
[2].imm
+ inst
.operands
[3].imm
;
11904 constraint (msb
> 32, _("bit-field extends past end of register"));
11905 /* The instruction encoding stores the LSB and MSB,
11906 not the LSB and width. */
11907 inst
.instruction
|= Rd
<< 8;
11908 inst
.instruction
|= Rn
<< 16;
11909 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11910 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11911 inst
.instruction
|= msb
- 1;
11919 Rd
= inst
.operands
[0].reg
;
11920 Rn
= inst
.operands
[1].reg
;
11922 reject_bad_reg (Rd
);
11923 reject_bad_reg (Rn
);
11925 constraint (inst
.operands
[2].imm
+ inst
.operands
[3].imm
> 32,
11926 _("bit-field extends past end of register"));
11927 inst
.instruction
|= Rd
<< 8;
11928 inst
.instruction
|= Rn
<< 16;
11929 inst
.instruction
|= (inst
.operands
[2].imm
& 0x1c) << 10;
11930 inst
.instruction
|= (inst
.operands
[2].imm
& 0x03) << 6;
11931 inst
.instruction
|= inst
.operands
[3].imm
- 1;
11934 /* ARM V5 Thumb BLX (argument parse)
11935 BLX <target_addr> which is BLX(1)
11936 BLX <Rm> which is BLX(2)
11937 Unfortunately, there are two different opcodes for this mnemonic.
11938 So, the insns[].value is not used, and the code here zaps values
11939 into inst.instruction.
11941 ??? How to take advantage of the additional two bits of displacement
11942 available in Thumb32 mode? Need new relocation? */
11947 set_pred_insn_type_last ();
11949 if (inst
.operands
[0].isreg
)
11951 constraint (inst
.operands
[0].reg
== REG_PC
, BAD_PC
);
11952 /* We have a register, so this is BLX(2). */
11953 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
11957 /* No register. This must be BLX(1). */
11958 inst
.instruction
= 0xf000e800;
11959 encode_branch (BFD_RELOC_THUMB_PCREL_BLX
);
11968 bfd_reloc_code_real_type reloc
;
11971 set_pred_insn_type (IF_INSIDE_IT_LAST_INSN
);
11973 if (in_pred_block ())
11975 /* Conditional branches inside IT blocks are encoded as unconditional
11977 cond
= COND_ALWAYS
;
11982 if (cond
!= COND_ALWAYS
)
11983 opcode
= T_MNEM_bcond
;
11985 opcode
= inst
.instruction
;
11988 && (inst
.size_req
== 4
11989 || (inst
.size_req
!= 2
11990 && (inst
.operands
[0].hasreloc
11991 || inst
.relocs
[0].exp
.X_op
== O_constant
))))
11993 inst
.instruction
= THUMB_OP32(opcode
);
11994 if (cond
== COND_ALWAYS
)
11995 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
11998 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
),
11999 _("selected architecture does not support "
12000 "wide conditional branch instruction"));
12002 gas_assert (cond
!= 0xF);
12003 inst
.instruction
|= cond
<< 22;
12004 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
12009 inst
.instruction
= THUMB_OP16(opcode
);
12010 if (cond
== COND_ALWAYS
)
12011 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
12014 inst
.instruction
|= cond
<< 8;
12015 reloc
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
12017 /* Allow section relaxation. */
12018 if (unified_syntax
&& inst
.size_req
!= 2)
12019 inst
.relax
= opcode
;
12021 inst
.relocs
[0].type
= reloc
;
12022 inst
.relocs
[0].pc_rel
= 1;
12025 /* Actually do the work for Thumb state bkpt and hlt. The only difference
12026 between the two is the maximum immediate allowed - which is passed in
12029 do_t_bkpt_hlt1 (int range
)
12031 constraint (inst
.cond
!= COND_ALWAYS
,
12032 _("instruction is always unconditional"));
12033 if (inst
.operands
[0].present
)
12035 constraint (inst
.operands
[0].imm
> range
,
12036 _("immediate value out of range"));
12037 inst
.instruction
|= inst
.operands
[0].imm
;
12040 set_pred_insn_type (NEUTRAL_IT_INSN
);
12046 do_t_bkpt_hlt1 (63);
12052 do_t_bkpt_hlt1 (255);
12056 do_t_branch23 (void)
12058 set_pred_insn_type_last ();
12059 encode_branch (BFD_RELOC_THUMB_PCREL_BRANCH23
);
12061 /* md_apply_fix blows up with 'bl foo(PLT)' where foo is defined in
12062 this file. We used to simply ignore the PLT reloc type here --
12063 the branch encoding is now needed to deal with TLSCALL relocs.
12064 So if we see a PLT reloc now, put it back to how it used to be to
12065 keep the preexisting behaviour. */
12066 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_PLT32
)
12067 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
12069 #if defined(OBJ_COFF)
12070 /* If the destination of the branch is a defined symbol which does not have
12071 the THUMB_FUNC attribute, then we must be calling a function which has
12072 the (interfacearm) attribute. We look for the Thumb entry point to that
12073 function and change the branch to refer to that function instead. */
12074 if ( inst
.relocs
[0].exp
.X_op
== O_symbol
12075 && inst
.relocs
[0].exp
.X_add_symbol
!= NULL
12076 && S_IS_DEFINED (inst
.relocs
[0].exp
.X_add_symbol
)
12077 && ! THUMB_IS_FUNC (inst
.relocs
[0].exp
.X_add_symbol
))
12078 inst
.relocs
[0].exp
.X_add_symbol
12079 = find_real_start (inst
.relocs
[0].exp
.X_add_symbol
);
12086 set_pred_insn_type_last ();
12087 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12088 /* ??? FIXME: Should add a hacky reloc here if reg is REG_PC. The reloc
12089 should cause the alignment to be checked once it is known. This is
12090 because BX PC only works if the instruction is word aligned. */
12098 set_pred_insn_type_last ();
12099 Rm
= inst
.operands
[0].reg
;
12100 reject_bad_reg (Rm
);
12101 inst
.instruction
|= Rm
<< 16;
12110 Rd
= inst
.operands
[0].reg
;
12111 Rm
= inst
.operands
[1].reg
;
12113 reject_bad_reg (Rd
);
12114 reject_bad_reg (Rm
);
12116 inst
.instruction
|= Rd
<< 8;
12117 inst
.instruction
|= Rm
<< 16;
12118 inst
.instruction
|= Rm
;
12121 /* For the Armv8.1-M conditional instructions. */
12125 unsigned Rd
, Rn
, Rm
;
12128 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
12130 Rd
= inst
.operands
[0].reg
;
12131 switch (inst
.instruction
)
12137 Rn
= inst
.operands
[1].reg
;
12138 Rm
= inst
.operands
[2].reg
;
12139 cond
= inst
.operands
[3].imm
;
12140 constraint (Rn
== REG_SP
, BAD_SP
);
12141 constraint (Rm
== REG_SP
, BAD_SP
);
12147 Rn
= inst
.operands
[1].reg
;
12148 cond
= inst
.operands
[2].imm
;
12149 /* Invert the last bit to invert the cond. */
12150 cond
= TOGGLE_BIT (cond
, 0);
12151 constraint (Rn
== REG_SP
, BAD_SP
);
12157 cond
= inst
.operands
[1].imm
;
12158 /* Invert the last bit to invert the cond. */
12159 cond
= TOGGLE_BIT (cond
, 0);
12167 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12168 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12169 inst
.instruction
|= Rd
<< 8;
12170 inst
.instruction
|= Rn
<< 16;
12171 inst
.instruction
|= Rm
;
12172 inst
.instruction
|= cond
<< 4;
12178 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12184 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12185 inst
.instruction
|= inst
.operands
[0].imm
;
12191 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12193 && (inst
.operands
[1].present
|| inst
.size_req
== 4)
12194 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6_notm
))
12196 unsigned int imod
= (inst
.instruction
& 0x0030) >> 4;
12197 inst
.instruction
= 0xf3af8000;
12198 inst
.instruction
|= imod
<< 9;
12199 inst
.instruction
|= inst
.operands
[0].imm
<< 5;
12200 if (inst
.operands
[1].present
)
12201 inst
.instruction
|= 0x100 | inst
.operands
[1].imm
;
12205 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
)
12206 && (inst
.operands
[0].imm
& 4),
12207 _("selected processor does not support 'A' form "
12208 "of this instruction"));
12209 constraint (inst
.operands
[1].present
|| inst
.size_req
== 4,
12210 _("Thumb does not support the 2-argument "
12211 "form of this instruction"));
12212 inst
.instruction
|= inst
.operands
[0].imm
;
12216 /* THUMB CPY instruction (argument parse). */
12221 if (inst
.size_req
== 4)
12223 inst
.instruction
= THUMB_OP32 (T_MNEM_mov
);
12224 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12225 inst
.instruction
|= inst
.operands
[1].reg
;
12229 inst
.instruction
|= (inst
.operands
[0].reg
& 0x8) << 4;
12230 inst
.instruction
|= (inst
.operands
[0].reg
& 0x7);
12231 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12238 set_pred_insn_type (OUTSIDE_PRED_INSN
);
12239 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12240 inst
.instruction
|= inst
.operands
[0].reg
;
12241 inst
.relocs
[0].pc_rel
= 1;
12242 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH7
;
12248 inst
.instruction
|= inst
.operands
[0].imm
;
12254 unsigned Rd
, Rn
, Rm
;
12256 Rd
= inst
.operands
[0].reg
;
12257 Rn
= (inst
.operands
[1].present
12258 ? inst
.operands
[1].reg
: Rd
);
12259 Rm
= inst
.operands
[2].reg
;
12261 reject_bad_reg (Rd
);
12262 reject_bad_reg (Rn
);
12263 reject_bad_reg (Rm
);
12265 inst
.instruction
|= Rd
<< 8;
12266 inst
.instruction
|= Rn
<< 16;
12267 inst
.instruction
|= Rm
;
12273 if (unified_syntax
&& inst
.size_req
== 4)
12274 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12276 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12282 unsigned int cond
= inst
.operands
[0].imm
;
12284 set_pred_insn_type (IT_INSN
);
12285 now_pred
.mask
= (inst
.instruction
& 0xf) | 0x10;
12286 now_pred
.cc
= cond
;
12287 now_pred
.warn_deprecated
= FALSE
;
12288 now_pred
.type
= SCALAR_PRED
;
12290 /* If the condition is a negative condition, invert the mask. */
12291 if ((cond
& 0x1) == 0x0)
12293 unsigned int mask
= inst
.instruction
& 0x000f;
12295 if ((mask
& 0x7) == 0)
12297 /* No conversion needed. */
12298 now_pred
.block_length
= 1;
12300 else if ((mask
& 0x3) == 0)
12303 now_pred
.block_length
= 2;
12305 else if ((mask
& 0x1) == 0)
12308 now_pred
.block_length
= 3;
12313 now_pred
.block_length
= 4;
12316 inst
.instruction
&= 0xfff0;
12317 inst
.instruction
|= mask
;
12320 inst
.instruction
|= cond
<< 4;
12323 /* Helper function used for both push/pop and ldm/stm. */
12325 encode_thumb2_multi (bfd_boolean do_io
, int base
, unsigned mask
,
12326 bfd_boolean writeback
)
12328 bfd_boolean load
, store
;
12330 gas_assert (base
!= -1 || !do_io
);
12331 load
= do_io
&& ((inst
.instruction
& (1 << 20)) != 0);
12332 store
= do_io
&& !load
;
12334 if (mask
& (1 << 13))
12335 inst
.error
= _("SP not allowed in register list");
12337 if (do_io
&& (mask
& (1 << base
)) != 0
12339 inst
.error
= _("having the base register in the register list when "
12340 "using write back is UNPREDICTABLE");
12344 if (mask
& (1 << 15))
12346 if (mask
& (1 << 14))
12347 inst
.error
= _("LR and PC should not both be in register list");
12349 set_pred_insn_type_last ();
12354 if (mask
& (1 << 15))
12355 inst
.error
= _("PC not allowed in register list");
12358 if (do_io
&& ((mask
& (mask
- 1)) == 0))
12360 /* Single register transfers implemented as str/ldr. */
12363 if (inst
.instruction
& (1 << 23))
12364 inst
.instruction
= 0x00000b04; /* ia! -> [base], #4 */
12366 inst
.instruction
= 0x00000d04; /* db! -> [base, #-4]! */
12370 if (inst
.instruction
& (1 << 23))
12371 inst
.instruction
= 0x00800000; /* ia -> [base] */
12373 inst
.instruction
= 0x00000c04; /* db -> [base, #-4] */
12376 inst
.instruction
|= 0xf8400000;
12378 inst
.instruction
|= 0x00100000;
12380 mask
= ffs (mask
) - 1;
12383 else if (writeback
)
12384 inst
.instruction
|= WRITE_BACK
;
12386 inst
.instruction
|= mask
;
12388 inst
.instruction
|= base
<< 16;
12394 /* This really doesn't seem worth it. */
12395 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
12396 _("expression too complex"));
12397 constraint (inst
.operands
[1].writeback
,
12398 _("Thumb load/store multiple does not support {reglist}^"));
12400 if (unified_syntax
)
12402 bfd_boolean narrow
;
12406 /* See if we can use a 16-bit instruction. */
12407 if (inst
.instruction
< 0xffff /* not ldmdb/stmdb */
12408 && inst
.size_req
!= 4
12409 && !(inst
.operands
[1].imm
& ~0xff))
12411 mask
= 1 << inst
.operands
[0].reg
;
12413 if (inst
.operands
[0].reg
<= 7)
12415 if (inst
.instruction
== T_MNEM_stmia
12416 ? inst
.operands
[0].writeback
12417 : (inst
.operands
[0].writeback
12418 == !(inst
.operands
[1].imm
& mask
)))
12420 if (inst
.instruction
== T_MNEM_stmia
12421 && (inst
.operands
[1].imm
& mask
)
12422 && (inst
.operands
[1].imm
& (mask
- 1)))
12423 as_warn (_("value stored for r%d is UNKNOWN"),
12424 inst
.operands
[0].reg
);
12426 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12427 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12428 inst
.instruction
|= inst
.operands
[1].imm
;
12431 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12433 /* This means 1 register in reg list one of 3 situations:
12434 1. Instruction is stmia, but without writeback.
12435 2. lmdia without writeback, but with Rn not in
12437 3. ldmia with writeback, but with Rn in reglist.
12438 Case 3 is UNPREDICTABLE behaviour, so we handle
12439 case 1 and 2 which can be converted into a 16-bit
12440 str or ldr. The SP cases are handled below. */
12441 unsigned long opcode
;
12442 /* First, record an error for Case 3. */
12443 if (inst
.operands
[1].imm
& mask
12444 && inst
.operands
[0].writeback
)
12446 _("having the base register in the register list when "
12447 "using write back is UNPREDICTABLE");
12449 opcode
= (inst
.instruction
== T_MNEM_stmia
? T_MNEM_str
12451 inst
.instruction
= THUMB_OP16 (opcode
);
12452 inst
.instruction
|= inst
.operands
[0].reg
<< 3;
12453 inst
.instruction
|= (ffs (inst
.operands
[1].imm
)-1);
12457 else if (inst
.operands
[0] .reg
== REG_SP
)
12459 if (inst
.operands
[0].writeback
)
12462 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12463 ? T_MNEM_push
: T_MNEM_pop
);
12464 inst
.instruction
|= inst
.operands
[1].imm
;
12467 else if ((inst
.operands
[1].imm
& (inst
.operands
[1].imm
-1)) == 0)
12470 THUMB_OP16 (inst
.instruction
== T_MNEM_stmia
12471 ? T_MNEM_str_sp
: T_MNEM_ldr_sp
);
12472 inst
.instruction
|= ((ffs (inst
.operands
[1].imm
)-1) << 8);
12480 if (inst
.instruction
< 0xffff)
12481 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12483 encode_thumb2_multi (TRUE
/* do_io */, inst
.operands
[0].reg
,
12484 inst
.operands
[1].imm
,
12485 inst
.operands
[0].writeback
);
12490 constraint (inst
.operands
[0].reg
> 7
12491 || (inst
.operands
[1].imm
& ~0xff), BAD_HIREG
);
12492 constraint (inst
.instruction
!= T_MNEM_ldmia
12493 && inst
.instruction
!= T_MNEM_stmia
,
12494 _("Thumb-2 instruction only valid in unified syntax"));
12495 if (inst
.instruction
== T_MNEM_stmia
)
12497 if (!inst
.operands
[0].writeback
)
12498 as_warn (_("this instruction will write back the base register"));
12499 if ((inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
))
12500 && (inst
.operands
[1].imm
& ((1 << inst
.operands
[0].reg
) - 1)))
12501 as_warn (_("value stored for r%d is UNKNOWN"),
12502 inst
.operands
[0].reg
);
12506 if (!inst
.operands
[0].writeback
12507 && !(inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12508 as_warn (_("this instruction will write back the base register"));
12509 else if (inst
.operands
[0].writeback
12510 && (inst
.operands
[1].imm
& (1 << inst
.operands
[0].reg
)))
12511 as_warn (_("this instruction will not write back the base register"));
12514 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12515 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12516 inst
.instruction
|= inst
.operands
[1].imm
;
12523 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].preind
12524 || inst
.operands
[1].postind
|| inst
.operands
[1].writeback
12525 || inst
.operands
[1].immisreg
|| inst
.operands
[1].shifted
12526 || inst
.operands
[1].negative
,
12529 constraint ((inst
.operands
[1].reg
== REG_PC
), BAD_PC
);
12531 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12532 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
12533 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
12539 if (!inst
.operands
[1].present
)
12541 constraint (inst
.operands
[0].reg
== REG_LR
,
12542 _("r14 not allowed as first register "
12543 "when second register is omitted"));
12544 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12546 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12549 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12550 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12551 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
12557 unsigned long opcode
;
12560 if (inst
.operands
[0].isreg
12561 && !inst
.operands
[0].preind
12562 && inst
.operands
[0].reg
== REG_PC
)
12563 set_pred_insn_type_last ();
12565 opcode
= inst
.instruction
;
12566 if (unified_syntax
)
12568 if (!inst
.operands
[1].isreg
)
12570 if (opcode
<= 0xffff)
12571 inst
.instruction
= THUMB_OP32 (opcode
);
12572 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12575 if (inst
.operands
[1].isreg
12576 && !inst
.operands
[1].writeback
12577 && !inst
.operands
[1].shifted
&& !inst
.operands
[1].postind
12578 && !inst
.operands
[1].negative
&& inst
.operands
[0].reg
<= 7
12579 && opcode
<= 0xffff
12580 && inst
.size_req
!= 4)
12582 /* Insn may have a 16-bit form. */
12583 Rn
= inst
.operands
[1].reg
;
12584 if (inst
.operands
[1].immisreg
)
12586 inst
.instruction
= THUMB_OP16 (opcode
);
12588 if (Rn
<= 7 && inst
.operands
[1].imm
<= 7)
12590 else if (opcode
!= T_MNEM_ldr
&& opcode
!= T_MNEM_str
)
12591 reject_bad_reg (inst
.operands
[1].imm
);
12593 else if ((Rn
<= 7 && opcode
!= T_MNEM_ldrsh
12594 && opcode
!= T_MNEM_ldrsb
)
12595 || ((Rn
== REG_PC
|| Rn
== REG_SP
) && opcode
== T_MNEM_ldr
)
12596 || (Rn
== REG_SP
&& opcode
== T_MNEM_str
))
12603 if (inst
.relocs
[0].pc_rel
)
12604 opcode
= T_MNEM_ldr_pc2
;
12606 opcode
= T_MNEM_ldr_pc
;
12610 if (opcode
== T_MNEM_ldr
)
12611 opcode
= T_MNEM_ldr_sp
;
12613 opcode
= T_MNEM_str_sp
;
12615 inst
.instruction
= inst
.operands
[0].reg
<< 8;
12619 inst
.instruction
= inst
.operands
[0].reg
;
12620 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12622 inst
.instruction
|= THUMB_OP16 (opcode
);
12623 if (inst
.size_req
== 2)
12624 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12626 inst
.relax
= opcode
;
12630 /* Definitely a 32-bit variant. */
12632 /* Warning for Erratum 752419. */
12633 if (opcode
== T_MNEM_ldr
12634 && inst
.operands
[0].reg
== REG_SP
12635 && inst
.operands
[1].writeback
== 1
12636 && !inst
.operands
[1].immisreg
)
12638 if (no_cpu_selected ()
12639 || (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7
)
12640 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
)
12641 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7r
)))
12642 as_warn (_("This instruction may be unpredictable "
12643 "if executed on M-profile cores "
12644 "with interrupts enabled."));
12647 /* Do some validations regarding addressing modes. */
12648 if (inst
.operands
[1].immisreg
)
12649 reject_bad_reg (inst
.operands
[1].imm
);
12651 constraint (inst
.operands
[1].writeback
== 1
12652 && inst
.operands
[0].reg
== inst
.operands
[1].reg
,
12655 inst
.instruction
= THUMB_OP32 (opcode
);
12656 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12657 encode_thumb32_addr_mode (1, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
12658 check_ldr_r15_aligned ();
12662 constraint (inst
.operands
[0].reg
> 7, BAD_HIREG
);
12664 if (inst
.instruction
== T_MNEM_ldrsh
|| inst
.instruction
== T_MNEM_ldrsb
)
12666 /* Only [Rn,Rm] is acceptable. */
12667 constraint (inst
.operands
[1].reg
> 7 || inst
.operands
[1].imm
> 7, BAD_HIREG
);
12668 constraint (!inst
.operands
[1].isreg
|| !inst
.operands
[1].immisreg
12669 || inst
.operands
[1].postind
|| inst
.operands
[1].shifted
12670 || inst
.operands
[1].negative
,
12671 _("Thumb does not support this addressing mode"));
12672 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12676 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
12677 if (!inst
.operands
[1].isreg
)
12678 if (move_or_literal_pool (0, CONST_THUMB
, /*mode_3=*/FALSE
))
12681 constraint (!inst
.operands
[1].preind
12682 || inst
.operands
[1].shifted
12683 || inst
.operands
[1].writeback
,
12684 _("Thumb does not support this addressing mode"));
12685 if (inst
.operands
[1].reg
== REG_PC
|| inst
.operands
[1].reg
== REG_SP
)
12687 constraint (inst
.instruction
& 0x0600,
12688 _("byte or halfword not valid for base register"));
12689 constraint (inst
.operands
[1].reg
== REG_PC
12690 && !(inst
.instruction
& THUMB_LOAD_BIT
),
12691 _("r15 based store not allowed"));
12692 constraint (inst
.operands
[1].immisreg
,
12693 _("invalid base register for register offset"));
12695 if (inst
.operands
[1].reg
== REG_PC
)
12696 inst
.instruction
= T_OPCODE_LDR_PC
;
12697 else if (inst
.instruction
& THUMB_LOAD_BIT
)
12698 inst
.instruction
= T_OPCODE_LDR_SP
;
12700 inst
.instruction
= T_OPCODE_STR_SP
;
12702 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
12703 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12707 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
12708 if (!inst
.operands
[1].immisreg
)
12710 /* Immediate offset. */
12711 inst
.instruction
|= inst
.operands
[0].reg
;
12712 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12713 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_OFFSET
;
12717 /* Register offset. */
12718 constraint (inst
.operands
[1].imm
> 7, BAD_HIREG
);
12719 constraint (inst
.operands
[1].negative
,
12720 _("Thumb does not support this addressing mode"));
12723 switch (inst
.instruction
)
12725 case T_OPCODE_STR_IW
: inst
.instruction
= T_OPCODE_STR_RW
; break;
12726 case T_OPCODE_STR_IH
: inst
.instruction
= T_OPCODE_STR_RH
; break;
12727 case T_OPCODE_STR_IB
: inst
.instruction
= T_OPCODE_STR_RB
; break;
12728 case T_OPCODE_LDR_IW
: inst
.instruction
= T_OPCODE_LDR_RW
; break;
12729 case T_OPCODE_LDR_IH
: inst
.instruction
= T_OPCODE_LDR_RH
; break;
12730 case T_OPCODE_LDR_IB
: inst
.instruction
= T_OPCODE_LDR_RB
; break;
12731 case 0x5600 /* ldrsb */:
12732 case 0x5e00 /* ldrsh */: break;
12736 inst
.instruction
|= inst
.operands
[0].reg
;
12737 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
12738 inst
.instruction
|= inst
.operands
[1].imm
<< 6;
12744 if (!inst
.operands
[1].present
)
12746 inst
.operands
[1].reg
= inst
.operands
[0].reg
+ 1;
12747 constraint (inst
.operands
[0].reg
== REG_LR
,
12748 _("r14 not allowed here"));
12749 constraint (inst
.operands
[0].reg
== REG_R12
,
12750 _("r12 not allowed here"));
12753 if (inst
.operands
[2].writeback
12754 && (inst
.operands
[0].reg
== inst
.operands
[2].reg
12755 || inst
.operands
[1].reg
== inst
.operands
[2].reg
))
12756 as_warn (_("base register written back, and overlaps "
12757 "one of transfer registers"));
12759 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12760 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
12761 encode_thumb32_addr_mode (2, /*is_t=*/FALSE
, /*is_d=*/TRUE
);
12767 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
12768 encode_thumb32_addr_mode (1, /*is_t=*/TRUE
, /*is_d=*/FALSE
);
12774 unsigned Rd
, Rn
, Rm
, Ra
;
12776 Rd
= inst
.operands
[0].reg
;
12777 Rn
= inst
.operands
[1].reg
;
12778 Rm
= inst
.operands
[2].reg
;
12779 Ra
= inst
.operands
[3].reg
;
12781 reject_bad_reg (Rd
);
12782 reject_bad_reg (Rn
);
12783 reject_bad_reg (Rm
);
12784 reject_bad_reg (Ra
);
12786 inst
.instruction
|= Rd
<< 8;
12787 inst
.instruction
|= Rn
<< 16;
12788 inst
.instruction
|= Rm
;
12789 inst
.instruction
|= Ra
<< 12;
12795 unsigned RdLo
, RdHi
, Rn
, Rm
;
12797 RdLo
= inst
.operands
[0].reg
;
12798 RdHi
= inst
.operands
[1].reg
;
12799 Rn
= inst
.operands
[2].reg
;
12800 Rm
= inst
.operands
[3].reg
;
12802 reject_bad_reg (RdLo
);
12803 reject_bad_reg (RdHi
);
12804 reject_bad_reg (Rn
);
12805 reject_bad_reg (Rm
);
12807 inst
.instruction
|= RdLo
<< 12;
12808 inst
.instruction
|= RdHi
<< 8;
12809 inst
.instruction
|= Rn
<< 16;
12810 inst
.instruction
|= Rm
;
12814 do_t_mov_cmp (void)
12818 Rn
= inst
.operands
[0].reg
;
12819 Rm
= inst
.operands
[1].reg
;
12822 set_pred_insn_type_last ();
12824 if (unified_syntax
)
12826 int r0off
= (inst
.instruction
== T_MNEM_mov
12827 || inst
.instruction
== T_MNEM_movs
) ? 8 : 16;
12828 unsigned long opcode
;
12829 bfd_boolean narrow
;
12830 bfd_boolean low_regs
;
12832 low_regs
= (Rn
<= 7 && Rm
<= 7);
12833 opcode
= inst
.instruction
;
12834 if (in_pred_block ())
12835 narrow
= opcode
!= T_MNEM_movs
;
12837 narrow
= opcode
!= T_MNEM_movs
|| low_regs
;
12838 if (inst
.size_req
== 4
12839 || inst
.operands
[1].shifted
)
12842 /* MOVS PC, LR is encoded as SUBS PC, LR, #0. */
12843 if (opcode
== T_MNEM_movs
&& inst
.operands
[1].isreg
12844 && !inst
.operands
[1].shifted
12848 inst
.instruction
= T2_SUBS_PC_LR
;
12852 if (opcode
== T_MNEM_cmp
)
12854 constraint (Rn
== REG_PC
, BAD_PC
);
12857 /* In the Thumb-2 ISA, use of R13 as Rm is deprecated,
12859 warn_deprecated_sp (Rm
);
12860 /* R15 was documented as a valid choice for Rm in ARMv6,
12861 but as UNPREDICTABLE in ARMv7. ARM's proprietary
12862 tools reject R15, so we do too. */
12863 constraint (Rm
== REG_PC
, BAD_PC
);
12866 reject_bad_reg (Rm
);
12868 else if (opcode
== T_MNEM_mov
12869 || opcode
== T_MNEM_movs
)
12871 if (inst
.operands
[1].isreg
)
12873 if (opcode
== T_MNEM_movs
)
12875 reject_bad_reg (Rn
);
12876 reject_bad_reg (Rm
);
12880 /* This is mov.n. */
12881 if ((Rn
== REG_SP
|| Rn
== REG_PC
)
12882 && (Rm
== REG_SP
|| Rm
== REG_PC
))
12884 as_tsktsk (_("Use of r%u as a source register is "
12885 "deprecated when r%u is the destination "
12886 "register."), Rm
, Rn
);
12891 /* This is mov.w. */
12892 constraint (Rn
== REG_PC
, BAD_PC
);
12893 constraint (Rm
== REG_PC
, BAD_PC
);
12894 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
12895 constraint (Rn
== REG_SP
&& Rm
== REG_SP
, BAD_SP
);
12899 reject_bad_reg (Rn
);
12902 if (!inst
.operands
[1].isreg
)
12904 /* Immediate operand. */
12905 if (!in_pred_block () && opcode
== T_MNEM_mov
)
12907 if (low_regs
&& narrow
)
12909 inst
.instruction
= THUMB_OP16 (opcode
);
12910 inst
.instruction
|= Rn
<< 8;
12911 if (inst
.relocs
[0].type
< BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
12912 || inst
.relocs
[0].type
> BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
12914 if (inst
.size_req
== 2)
12915 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
12917 inst
.relax
= opcode
;
12922 constraint ((inst
.relocs
[0].type
12923 >= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
)
12924 && (inst
.relocs
[0].type
12925 <= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
) ,
12926 THUMB1_RELOC_ONLY
);
12928 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
12929 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
12930 inst
.instruction
|= Rn
<< r0off
;
12931 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
12934 else if (inst
.operands
[1].shifted
&& inst
.operands
[1].immisreg
12935 && (inst
.instruction
== T_MNEM_mov
12936 || inst
.instruction
== T_MNEM_movs
))
12938 /* Register shifts are encoded as separate shift instructions. */
12939 bfd_boolean flags
= (inst
.instruction
== T_MNEM_movs
);
12941 if (in_pred_block ())
12946 if (inst
.size_req
== 4)
12949 if (!low_regs
|| inst
.operands
[1].imm
> 7)
12955 switch (inst
.operands
[1].shift_kind
)
12958 opcode
= narrow
? T_OPCODE_LSL_R
: THUMB_OP32 (T_MNEM_lsl
);
12961 opcode
= narrow
? T_OPCODE_ASR_R
: THUMB_OP32 (T_MNEM_asr
);
12964 opcode
= narrow
? T_OPCODE_LSR_R
: THUMB_OP32 (T_MNEM_lsr
);
12967 opcode
= narrow
? T_OPCODE_ROR_R
: THUMB_OP32 (T_MNEM_ror
);
12973 inst
.instruction
= opcode
;
12976 inst
.instruction
|= Rn
;
12977 inst
.instruction
|= inst
.operands
[1].imm
<< 3;
12982 inst
.instruction
|= CONDS_BIT
;
12984 inst
.instruction
|= Rn
<< 8;
12985 inst
.instruction
|= Rm
<< 16;
12986 inst
.instruction
|= inst
.operands
[1].imm
;
12991 /* Some mov with immediate shift have narrow variants.
12992 Register shifts are handled above. */
12993 if (low_regs
&& inst
.operands
[1].shifted
12994 && (inst
.instruction
== T_MNEM_mov
12995 || inst
.instruction
== T_MNEM_movs
))
12997 if (in_pred_block ())
12998 narrow
= (inst
.instruction
== T_MNEM_mov
);
13000 narrow
= (inst
.instruction
== T_MNEM_movs
);
13005 switch (inst
.operands
[1].shift_kind
)
13007 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13008 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13009 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13010 default: narrow
= FALSE
; break;
13016 inst
.instruction
|= Rn
;
13017 inst
.instruction
|= Rm
<< 3;
13018 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13022 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13023 inst
.instruction
|= Rn
<< r0off
;
13024 encode_thumb32_shifted_operand (1);
13028 switch (inst
.instruction
)
13031 /* In v4t or v5t a move of two lowregs produces unpredictable
13032 results. Don't allow this. */
13035 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6
),
13036 "MOV Rd, Rs with two low registers is not "
13037 "permitted on this architecture");
13038 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
13042 inst
.instruction
= T_OPCODE_MOV_HR
;
13043 inst
.instruction
|= (Rn
& 0x8) << 4;
13044 inst
.instruction
|= (Rn
& 0x7);
13045 inst
.instruction
|= Rm
<< 3;
13049 /* We know we have low registers at this point.
13050 Generate LSLS Rd, Rs, #0. */
13051 inst
.instruction
= T_OPCODE_LSL_I
;
13052 inst
.instruction
|= Rn
;
13053 inst
.instruction
|= Rm
<< 3;
13059 inst
.instruction
= T_OPCODE_CMP_LR
;
13060 inst
.instruction
|= Rn
;
13061 inst
.instruction
|= Rm
<< 3;
13065 inst
.instruction
= T_OPCODE_CMP_HR
;
13066 inst
.instruction
|= (Rn
& 0x8) << 4;
13067 inst
.instruction
|= (Rn
& 0x7);
13068 inst
.instruction
|= Rm
<< 3;
13075 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13077 /* PR 10443: Do not silently ignore shifted operands. */
13078 constraint (inst
.operands
[1].shifted
,
13079 _("shifts in CMP/MOV instructions are only supported in unified syntax"));
13081 if (inst
.operands
[1].isreg
)
13083 if (Rn
< 8 && Rm
< 8)
13085 /* A move of two lowregs is encoded as ADD Rd, Rs, #0
13086 since a MOV instruction produces unpredictable results. */
13087 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13088 inst
.instruction
= T_OPCODE_ADD_I3
;
13090 inst
.instruction
= T_OPCODE_CMP_LR
;
13092 inst
.instruction
|= Rn
;
13093 inst
.instruction
|= Rm
<< 3;
13097 if (inst
.instruction
== T_OPCODE_MOV_I8
)
13098 inst
.instruction
= T_OPCODE_MOV_HR
;
13100 inst
.instruction
= T_OPCODE_CMP_HR
;
13106 constraint (Rn
> 7,
13107 _("only lo regs allowed with immediate"));
13108 inst
.instruction
|= Rn
<< 8;
13109 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_IMM
;
13120 top
= (inst
.instruction
& 0x00800000) != 0;
13121 if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVW
)
13123 constraint (top
, _(":lower16: not allowed in this instruction"));
13124 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVW
;
13126 else if (inst
.relocs
[0].type
== BFD_RELOC_ARM_MOVT
)
13128 constraint (!top
, _(":upper16: not allowed in this instruction"));
13129 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_MOVT
;
13132 Rd
= inst
.operands
[0].reg
;
13133 reject_bad_reg (Rd
);
13135 inst
.instruction
|= Rd
<< 8;
13136 if (inst
.relocs
[0].type
== BFD_RELOC_UNUSED
)
13138 imm
= inst
.relocs
[0].exp
.X_add_number
;
13139 inst
.instruction
|= (imm
& 0xf000) << 4;
13140 inst
.instruction
|= (imm
& 0x0800) << 15;
13141 inst
.instruction
|= (imm
& 0x0700) << 4;
13142 inst
.instruction
|= (imm
& 0x00ff);
13147 do_t_mvn_tst (void)
13151 Rn
= inst
.operands
[0].reg
;
13152 Rm
= inst
.operands
[1].reg
;
13154 if (inst
.instruction
== T_MNEM_cmp
13155 || inst
.instruction
== T_MNEM_cmn
)
13156 constraint (Rn
== REG_PC
, BAD_PC
);
13158 reject_bad_reg (Rn
);
13159 reject_bad_reg (Rm
);
13161 if (unified_syntax
)
13163 int r0off
= (inst
.instruction
== T_MNEM_mvn
13164 || inst
.instruction
== T_MNEM_mvns
) ? 8 : 16;
13165 bfd_boolean narrow
;
13167 if (inst
.size_req
== 4
13168 || inst
.instruction
> 0xffff
13169 || inst
.operands
[1].shifted
13170 || Rn
> 7 || Rm
> 7)
13172 else if (inst
.instruction
== T_MNEM_cmn
13173 || inst
.instruction
== T_MNEM_tst
)
13175 else if (THUMB_SETS_FLAGS (inst
.instruction
))
13176 narrow
= !in_pred_block ();
13178 narrow
= in_pred_block ();
13180 if (!inst
.operands
[1].isreg
)
13182 /* For an immediate, we always generate a 32-bit opcode;
13183 section relaxation will shrink it later if possible. */
13184 if (inst
.instruction
< 0xffff)
13185 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13186 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13187 inst
.instruction
|= Rn
<< r0off
;
13188 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13192 /* See if we can do this with a 16-bit instruction. */
13195 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13196 inst
.instruction
|= Rn
;
13197 inst
.instruction
|= Rm
<< 3;
13201 constraint (inst
.operands
[1].shifted
13202 && inst
.operands
[1].immisreg
,
13203 _("shift must be constant"));
13204 if (inst
.instruction
< 0xffff)
13205 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13206 inst
.instruction
|= Rn
<< r0off
;
13207 encode_thumb32_shifted_operand (1);
13213 constraint (inst
.instruction
> 0xffff
13214 || inst
.instruction
== T_MNEM_mvns
, BAD_THUMB32
);
13215 constraint (!inst
.operands
[1].isreg
|| inst
.operands
[1].shifted
,
13216 _("unshifted register required"));
13217 constraint (Rn
> 7 || Rm
> 7,
13220 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13221 inst
.instruction
|= Rn
;
13222 inst
.instruction
|= Rm
<< 3;
13231 if (do_vfp_nsyn_mrs () == SUCCESS
)
13234 Rd
= inst
.operands
[0].reg
;
13235 reject_bad_reg (Rd
);
13236 inst
.instruction
|= Rd
<< 8;
13238 if (inst
.operands
[1].isreg
)
13240 unsigned br
= inst
.operands
[1].reg
;
13241 if (((br
& 0x200) == 0) && ((br
& 0xf000) != 0xf000))
13242 as_bad (_("bad register for mrs"));
13244 inst
.instruction
|= br
& (0xf << 16);
13245 inst
.instruction
|= (br
& 0x300) >> 4;
13246 inst
.instruction
|= (br
& SPSR_BIT
) >> 2;
13250 int flags
= inst
.operands
[1].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13252 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13254 /* PR gas/12698: The constraint is only applied for m_profile.
13255 If the user has specified -march=all, we want to ignore it as
13256 we are building for any CPU type, including non-m variants. */
13257 bfd_boolean m_profile
=
13258 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13259 constraint ((flags
!= 0) && m_profile
, _("selected processor does "
13260 "not support requested special purpose register"));
13263 /* mrs only accepts APSR/CPSR/SPSR/CPSR_all/SPSR_all (for non-M profile
13265 constraint ((flags
& ~SPSR_BIT
) != (PSR_c
|PSR_f
),
13266 _("'APSR', 'CPSR' or 'SPSR' expected"));
13268 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13269 inst
.instruction
|= inst
.operands
[1].imm
& 0xff;
13270 inst
.instruction
|= 0xf0000;
13280 if (do_vfp_nsyn_msr () == SUCCESS
)
13283 constraint (!inst
.operands
[1].isreg
,
13284 _("Thumb encoding does not support an immediate here"));
13286 if (inst
.operands
[0].isreg
)
13287 flags
= (int)(inst
.operands
[0].reg
);
13289 flags
= inst
.operands
[0].imm
;
13291 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_m
))
13293 int bits
= inst
.operands
[0].imm
& (PSR_c
|PSR_x
|PSR_s
|PSR_f
|SPSR_BIT
);
13295 /* PR gas/12698: The constraint is only applied for m_profile.
13296 If the user has specified -march=all, we want to ignore it as
13297 we are building for any CPU type, including non-m variants. */
13298 bfd_boolean m_profile
=
13299 !ARM_FEATURE_CORE_EQUAL (selected_cpu
, arm_arch_any
);
13300 constraint (((ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13301 && (bits
& ~(PSR_s
| PSR_f
)) != 0)
13302 || (!ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6_dsp
)
13303 && bits
!= PSR_f
)) && m_profile
,
13304 _("selected processor does not support requested special "
13305 "purpose register"));
13308 constraint ((flags
& 0xff) != 0, _("selected processor does not support "
13309 "requested special purpose register"));
13311 Rn
= inst
.operands
[1].reg
;
13312 reject_bad_reg (Rn
);
13314 inst
.instruction
|= (flags
& SPSR_BIT
) >> 2;
13315 inst
.instruction
|= (flags
& 0xf0000) >> 8;
13316 inst
.instruction
|= (flags
& 0x300) >> 4;
13317 inst
.instruction
|= (flags
& 0xff);
13318 inst
.instruction
|= Rn
<< 16;
13324 bfd_boolean narrow
;
13325 unsigned Rd
, Rn
, Rm
;
13327 if (!inst
.operands
[2].present
)
13328 inst
.operands
[2].reg
= inst
.operands
[0].reg
;
13330 Rd
= inst
.operands
[0].reg
;
13331 Rn
= inst
.operands
[1].reg
;
13332 Rm
= inst
.operands
[2].reg
;
13334 if (unified_syntax
)
13336 if (inst
.size_req
== 4
13342 else if (inst
.instruction
== T_MNEM_muls
)
13343 narrow
= !in_pred_block ();
13345 narrow
= in_pred_block ();
13349 constraint (inst
.instruction
== T_MNEM_muls
, BAD_THUMB32
);
13350 constraint (Rn
> 7 || Rm
> 7,
13357 /* 16-bit MULS/Conditional MUL. */
13358 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13359 inst
.instruction
|= Rd
;
13362 inst
.instruction
|= Rm
<< 3;
13364 inst
.instruction
|= Rn
<< 3;
13366 constraint (1, _("dest must overlap one source register"));
13370 constraint (inst
.instruction
!= T_MNEM_mul
,
13371 _("Thumb-2 MUL must not set flags"));
13373 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13374 inst
.instruction
|= Rd
<< 8;
13375 inst
.instruction
|= Rn
<< 16;
13376 inst
.instruction
|= Rm
<< 0;
13378 reject_bad_reg (Rd
);
13379 reject_bad_reg (Rn
);
13380 reject_bad_reg (Rm
);
13387 unsigned RdLo
, RdHi
, Rn
, Rm
;
13389 RdLo
= inst
.operands
[0].reg
;
13390 RdHi
= inst
.operands
[1].reg
;
13391 Rn
= inst
.operands
[2].reg
;
13392 Rm
= inst
.operands
[3].reg
;
13394 reject_bad_reg (RdLo
);
13395 reject_bad_reg (RdHi
);
13396 reject_bad_reg (Rn
);
13397 reject_bad_reg (Rm
);
13399 inst
.instruction
|= RdLo
<< 12;
13400 inst
.instruction
|= RdHi
<< 8;
13401 inst
.instruction
|= Rn
<< 16;
13402 inst
.instruction
|= Rm
;
13405 as_tsktsk (_("rdhi and rdlo must be different"));
13411 set_pred_insn_type (NEUTRAL_IT_INSN
);
13413 if (unified_syntax
)
13415 if (inst
.size_req
== 4 || inst
.operands
[0].imm
> 15)
13417 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13418 inst
.instruction
|= inst
.operands
[0].imm
;
13422 /* PR9722: Check for Thumb2 availability before
13423 generating a thumb2 nop instruction. */
13424 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v6t2
))
13426 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13427 inst
.instruction
|= inst
.operands
[0].imm
<< 4;
13430 inst
.instruction
= 0x46c0;
13435 constraint (inst
.operands
[0].present
,
13436 _("Thumb does not support NOP with hints"));
13437 inst
.instruction
= 0x46c0;
13444 if (unified_syntax
)
13446 bfd_boolean narrow
;
13448 if (THUMB_SETS_FLAGS (inst
.instruction
))
13449 narrow
= !in_pred_block ();
13451 narrow
= in_pred_block ();
13452 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13454 if (inst
.size_req
== 4)
13459 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13460 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13461 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13465 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13466 inst
.instruction
|= inst
.operands
[0].reg
;
13467 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13472 constraint (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7,
13474 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13476 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13477 inst
.instruction
|= inst
.operands
[0].reg
;
13478 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13487 Rd
= inst
.operands
[0].reg
;
13488 Rn
= inst
.operands
[1].present
? inst
.operands
[1].reg
: Rd
;
13490 reject_bad_reg (Rd
);
13491 /* Rn == REG_SP is unpredictable; Rn == REG_PC is MVN. */
13492 reject_bad_reg (Rn
);
13494 inst
.instruction
|= Rd
<< 8;
13495 inst
.instruction
|= Rn
<< 16;
13497 if (!inst
.operands
[2].isreg
)
13499 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13500 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13506 Rm
= inst
.operands
[2].reg
;
13507 reject_bad_reg (Rm
);
13509 constraint (inst
.operands
[2].shifted
13510 && inst
.operands
[2].immisreg
,
13511 _("shift must be constant"));
13512 encode_thumb32_shifted_operand (2);
13519 unsigned Rd
, Rn
, Rm
;
13521 Rd
= inst
.operands
[0].reg
;
13522 Rn
= inst
.operands
[1].reg
;
13523 Rm
= inst
.operands
[2].reg
;
13525 reject_bad_reg (Rd
);
13526 reject_bad_reg (Rn
);
13527 reject_bad_reg (Rm
);
13529 inst
.instruction
|= Rd
<< 8;
13530 inst
.instruction
|= Rn
<< 16;
13531 inst
.instruction
|= Rm
;
13532 if (inst
.operands
[3].present
)
13534 unsigned int val
= inst
.relocs
[0].exp
.X_add_number
;
13535 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13536 _("expression too complex"));
13537 inst
.instruction
|= (val
& 0x1c) << 10;
13538 inst
.instruction
|= (val
& 0x03) << 6;
13545 if (!inst
.operands
[3].present
)
13549 inst
.instruction
&= ~0x00000020;
13551 /* PR 10168. Swap the Rm and Rn registers. */
13552 Rtmp
= inst
.operands
[1].reg
;
13553 inst
.operands
[1].reg
= inst
.operands
[2].reg
;
13554 inst
.operands
[2].reg
= Rtmp
;
13562 if (inst
.operands
[0].immisreg
)
13563 reject_bad_reg (inst
.operands
[0].imm
);
13565 encode_thumb32_addr_mode (0, /*is_t=*/FALSE
, /*is_d=*/FALSE
);
13569 do_t_push_pop (void)
13573 constraint (inst
.operands
[0].writeback
,
13574 _("push/pop do not support {reglist}^"));
13575 constraint (inst
.relocs
[0].type
!= BFD_RELOC_UNUSED
,
13576 _("expression too complex"));
13578 mask
= inst
.operands
[0].imm
;
13579 if (inst
.size_req
!= 4 && (mask
& ~0xff) == 0)
13580 inst
.instruction
= THUMB_OP16 (inst
.instruction
) | mask
;
13581 else if (inst
.size_req
!= 4
13582 && (mask
& ~0xff) == (1U << (inst
.instruction
== T_MNEM_push
13583 ? REG_LR
: REG_PC
)))
13585 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13586 inst
.instruction
|= THUMB_PP_PC_LR
;
13587 inst
.instruction
|= mask
& 0xff;
13589 else if (unified_syntax
)
13591 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13592 encode_thumb2_multi (TRUE
/* do_io */, 13, mask
, TRUE
);
13596 inst
.error
= _("invalid register list to push/pop instruction");
13604 if (unified_syntax
)
13605 encode_thumb2_multi (FALSE
/* do_io */, -1, inst
.operands
[0].imm
, FALSE
);
13608 inst
.error
= _("invalid register list to push/pop instruction");
13614 do_t_vscclrm (void)
13616 if (inst
.operands
[0].issingle
)
13618 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1) << 22;
13619 inst
.instruction
|= (inst
.operands
[0].reg
& 0x1e) << 11;
13620 inst
.instruction
|= inst
.operands
[0].imm
;
13624 inst
.instruction
|= (inst
.operands
[0].reg
& 0x10) << 18;
13625 inst
.instruction
|= (inst
.operands
[0].reg
& 0xf) << 12;
13626 inst
.instruction
|= 1 << 8;
13627 inst
.instruction
|= inst
.operands
[0].imm
<< 1;
13636 Rd
= inst
.operands
[0].reg
;
13637 Rm
= inst
.operands
[1].reg
;
13639 reject_bad_reg (Rd
);
13640 reject_bad_reg (Rm
);
13642 inst
.instruction
|= Rd
<< 8;
13643 inst
.instruction
|= Rm
<< 16;
13644 inst
.instruction
|= Rm
;
13652 Rd
= inst
.operands
[0].reg
;
13653 Rm
= inst
.operands
[1].reg
;
13655 reject_bad_reg (Rd
);
13656 reject_bad_reg (Rm
);
13658 if (Rd
<= 7 && Rm
<= 7
13659 && inst
.size_req
!= 4)
13661 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
13662 inst
.instruction
|= Rd
;
13663 inst
.instruction
|= Rm
<< 3;
13665 else if (unified_syntax
)
13667 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13668 inst
.instruction
|= Rd
<< 8;
13669 inst
.instruction
|= Rm
<< 16;
13670 inst
.instruction
|= Rm
;
13673 inst
.error
= BAD_HIREG
;
13681 Rd
= inst
.operands
[0].reg
;
13682 Rm
= inst
.operands
[1].reg
;
13684 reject_bad_reg (Rd
);
13685 reject_bad_reg (Rm
);
13687 inst
.instruction
|= Rd
<< 8;
13688 inst
.instruction
|= Rm
;
13696 Rd
= inst
.operands
[0].reg
;
13697 Rs
= (inst
.operands
[1].present
13698 ? inst
.operands
[1].reg
/* Rd, Rs, foo */
13699 : inst
.operands
[0].reg
); /* Rd, foo -> Rd, Rd, foo */
13701 reject_bad_reg (Rd
);
13702 reject_bad_reg (Rs
);
13703 if (inst
.operands
[2].isreg
)
13704 reject_bad_reg (inst
.operands
[2].reg
);
13706 inst
.instruction
|= Rd
<< 8;
13707 inst
.instruction
|= Rs
<< 16;
13708 if (!inst
.operands
[2].isreg
)
13710 bfd_boolean narrow
;
13712 if ((inst
.instruction
& 0x00100000) != 0)
13713 narrow
= !in_pred_block ();
13715 narrow
= in_pred_block ();
13717 if (Rd
> 7 || Rs
> 7)
13720 if (inst
.size_req
== 4 || !unified_syntax
)
13723 if (inst
.relocs
[0].exp
.X_op
!= O_constant
13724 || inst
.relocs
[0].exp
.X_add_number
!= 0)
13727 /* Turn rsb #0 into 16-bit neg. We should probably do this via
13728 relaxation, but it doesn't seem worth the hassle. */
13731 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13732 inst
.instruction
= THUMB_OP16 (T_MNEM_negs
);
13733 inst
.instruction
|= Rs
<< 3;
13734 inst
.instruction
|= Rd
;
13738 inst
.instruction
= (inst
.instruction
& 0xe1ffffff) | 0x10000000;
13739 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
13743 encode_thumb32_shifted_operand (2);
13749 if (warn_on_deprecated
13750 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
13751 as_tsktsk (_("setend use is deprecated for ARMv8"));
13753 set_pred_insn_type (OUTSIDE_PRED_INSN
);
13754 if (inst
.operands
[0].imm
)
13755 inst
.instruction
|= 0x8;
13761 if (!inst
.operands
[1].present
)
13762 inst
.operands
[1].reg
= inst
.operands
[0].reg
;
13764 if (unified_syntax
)
13766 bfd_boolean narrow
;
13769 switch (inst
.instruction
)
13772 case T_MNEM_asrs
: shift_kind
= SHIFT_ASR
; break;
13774 case T_MNEM_lsls
: shift_kind
= SHIFT_LSL
; break;
13776 case T_MNEM_lsrs
: shift_kind
= SHIFT_LSR
; break;
13778 case T_MNEM_rors
: shift_kind
= SHIFT_ROR
; break;
13782 if (THUMB_SETS_FLAGS (inst
.instruction
))
13783 narrow
= !in_pred_block ();
13785 narrow
= in_pred_block ();
13786 if (inst
.operands
[0].reg
> 7 || inst
.operands
[1].reg
> 7)
13788 if (!inst
.operands
[2].isreg
&& shift_kind
== SHIFT_ROR
)
13790 if (inst
.operands
[2].isreg
13791 && (inst
.operands
[1].reg
!= inst
.operands
[0].reg
13792 || inst
.operands
[2].reg
> 7))
13794 if (inst
.size_req
== 4)
13797 reject_bad_reg (inst
.operands
[0].reg
);
13798 reject_bad_reg (inst
.operands
[1].reg
);
13802 if (inst
.operands
[2].isreg
)
13804 reject_bad_reg (inst
.operands
[2].reg
);
13805 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
13806 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13807 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
13808 inst
.instruction
|= inst
.operands
[2].reg
;
13810 /* PR 12854: Error on extraneous shifts. */
13811 constraint (inst
.operands
[2].shifted
,
13812 _("extraneous shift as part of operand to shift insn"));
13816 inst
.operands
[1].shifted
= 1;
13817 inst
.operands
[1].shift_kind
= shift_kind
;
13818 inst
.instruction
= THUMB_OP32 (THUMB_SETS_FLAGS (inst
.instruction
)
13819 ? T_MNEM_movs
: T_MNEM_mov
);
13820 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
13821 encode_thumb32_shifted_operand (1);
13822 /* Prevent the incorrect generation of an ARM_IMMEDIATE fixup. */
13823 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13828 if (inst
.operands
[2].isreg
)
13830 switch (shift_kind
)
13832 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13833 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13834 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13835 case SHIFT_ROR
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13839 inst
.instruction
|= inst
.operands
[0].reg
;
13840 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13842 /* PR 12854: Error on extraneous shifts. */
13843 constraint (inst
.operands
[2].shifted
,
13844 _("extraneous shift as part of operand to shift insn"));
13848 switch (shift_kind
)
13850 case SHIFT_ASR
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13851 case SHIFT_LSL
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13852 case SHIFT_LSR
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13855 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13856 inst
.instruction
|= inst
.operands
[0].reg
;
13857 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13863 constraint (inst
.operands
[0].reg
> 7
13864 || inst
.operands
[1].reg
> 7, BAD_HIREG
);
13865 constraint (THUMB_SETS_FLAGS (inst
.instruction
), BAD_THUMB32
);
13867 if (inst
.operands
[2].isreg
) /* Rd, {Rs,} Rn */
13869 constraint (inst
.operands
[2].reg
> 7, BAD_HIREG
);
13870 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
13871 _("source1 and dest must be same register"));
13873 switch (inst
.instruction
)
13875 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_R
; break;
13876 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_R
; break;
13877 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_R
; break;
13878 case T_MNEM_ror
: inst
.instruction
= T_OPCODE_ROR_R
; break;
13882 inst
.instruction
|= inst
.operands
[0].reg
;
13883 inst
.instruction
|= inst
.operands
[2].reg
<< 3;
13885 /* PR 12854: Error on extraneous shifts. */
13886 constraint (inst
.operands
[2].shifted
,
13887 _("extraneous shift as part of operand to shift insn"));
13891 switch (inst
.instruction
)
13893 case T_MNEM_asr
: inst
.instruction
= T_OPCODE_ASR_I
; break;
13894 case T_MNEM_lsl
: inst
.instruction
= T_OPCODE_LSL_I
; break;
13895 case T_MNEM_lsr
: inst
.instruction
= T_OPCODE_LSR_I
; break;
13896 case T_MNEM_ror
: inst
.error
= _("ror #imm not supported"); return;
13899 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_SHIFT
;
13900 inst
.instruction
|= inst
.operands
[0].reg
;
13901 inst
.instruction
|= inst
.operands
[1].reg
<< 3;
13909 unsigned Rd
, Rn
, Rm
;
13911 Rd
= inst
.operands
[0].reg
;
13912 Rn
= inst
.operands
[1].reg
;
13913 Rm
= inst
.operands
[2].reg
;
13915 reject_bad_reg (Rd
);
13916 reject_bad_reg (Rn
);
13917 reject_bad_reg (Rm
);
13919 inst
.instruction
|= Rd
<< 8;
13920 inst
.instruction
|= Rn
<< 16;
13921 inst
.instruction
|= Rm
;
13927 unsigned Rd
, Rn
, Rm
;
13929 Rd
= inst
.operands
[0].reg
;
13930 Rm
= inst
.operands
[1].reg
;
13931 Rn
= inst
.operands
[2].reg
;
13933 reject_bad_reg (Rd
);
13934 reject_bad_reg (Rn
);
13935 reject_bad_reg (Rm
);
13937 inst
.instruction
|= Rd
<< 8;
13938 inst
.instruction
|= Rn
<< 16;
13939 inst
.instruction
|= Rm
;
13945 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13946 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v7a
),
13947 _("SMC is not permitted on this architecture"));
13948 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13949 _("expression too complex"));
13950 constraint (value
> 0xf, _("immediate too large (bigger than 0xF)"));
13952 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13953 inst
.instruction
|= (value
& 0x000f) << 16;
13955 /* PR gas/15623: SMC instructions must be last in an IT block. */
13956 set_pred_insn_type_last ();
13962 unsigned int value
= inst
.relocs
[0].exp
.X_add_number
;
13964 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13965 inst
.instruction
|= (value
& 0x0fff);
13966 inst
.instruction
|= (value
& 0xf000) << 4;
13970 do_t_ssat_usat (int bias
)
13974 Rd
= inst
.operands
[0].reg
;
13975 Rn
= inst
.operands
[2].reg
;
13977 reject_bad_reg (Rd
);
13978 reject_bad_reg (Rn
);
13980 inst
.instruction
|= Rd
<< 8;
13981 inst
.instruction
|= inst
.operands
[1].imm
- bias
;
13982 inst
.instruction
|= Rn
<< 16;
13984 if (inst
.operands
[3].present
)
13986 offsetT shift_amount
= inst
.relocs
[0].exp
.X_add_number
;
13988 inst
.relocs
[0].type
= BFD_RELOC_UNUSED
;
13990 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
13991 _("expression too complex"));
13993 if (shift_amount
!= 0)
13995 constraint (shift_amount
> 31,
13996 _("shift expression is too large"));
13998 if (inst
.operands
[3].shift_kind
== SHIFT_ASR
)
13999 inst
.instruction
|= 0x00200000; /* sh bit. */
14001 inst
.instruction
|= (shift_amount
& 0x1c) << 10;
14002 inst
.instruction
|= (shift_amount
& 0x03) << 6;
14010 do_t_ssat_usat (1);
14018 Rd
= inst
.operands
[0].reg
;
14019 Rn
= inst
.operands
[2].reg
;
14021 reject_bad_reg (Rd
);
14022 reject_bad_reg (Rn
);
14024 inst
.instruction
|= Rd
<< 8;
14025 inst
.instruction
|= inst
.operands
[1].imm
- 1;
14026 inst
.instruction
|= Rn
<< 16;
14032 constraint (!inst
.operands
[2].isreg
|| !inst
.operands
[2].preind
14033 || inst
.operands
[2].postind
|| inst
.operands
[2].writeback
14034 || inst
.operands
[2].immisreg
|| inst
.operands
[2].shifted
14035 || inst
.operands
[2].negative
,
14038 constraint (inst
.operands
[2].reg
== REG_PC
, BAD_PC
);
14040 inst
.instruction
|= inst
.operands
[0].reg
<< 8;
14041 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14042 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
14043 inst
.relocs
[0].type
= BFD_RELOC_ARM_T32_OFFSET_U8
;
14049 if (!inst
.operands
[2].present
)
14050 inst
.operands
[2].reg
= inst
.operands
[1].reg
+ 1;
14052 constraint (inst
.operands
[0].reg
== inst
.operands
[1].reg
14053 || inst
.operands
[0].reg
== inst
.operands
[2].reg
14054 || inst
.operands
[0].reg
== inst
.operands
[3].reg
,
14057 inst
.instruction
|= inst
.operands
[0].reg
;
14058 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
14059 inst
.instruction
|= inst
.operands
[2].reg
<< 8;
14060 inst
.instruction
|= inst
.operands
[3].reg
<< 16;
14066 unsigned Rd
, Rn
, Rm
;
14068 Rd
= inst
.operands
[0].reg
;
14069 Rn
= inst
.operands
[1].reg
;
14070 Rm
= inst
.operands
[2].reg
;
14072 reject_bad_reg (Rd
);
14073 reject_bad_reg (Rn
);
14074 reject_bad_reg (Rm
);
14076 inst
.instruction
|= Rd
<< 8;
14077 inst
.instruction
|= Rn
<< 16;
14078 inst
.instruction
|= Rm
;
14079 inst
.instruction
|= inst
.operands
[3].imm
<< 4;
14087 Rd
= inst
.operands
[0].reg
;
14088 Rm
= inst
.operands
[1].reg
;
14090 reject_bad_reg (Rd
);
14091 reject_bad_reg (Rm
);
14093 if (inst
.instruction
<= 0xffff
14094 && inst
.size_req
!= 4
14095 && Rd
<= 7 && Rm
<= 7
14096 && (!inst
.operands
[2].present
|| inst
.operands
[2].imm
== 0))
14098 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14099 inst
.instruction
|= Rd
;
14100 inst
.instruction
|= Rm
<< 3;
14102 else if (unified_syntax
)
14104 if (inst
.instruction
<= 0xffff)
14105 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14106 inst
.instruction
|= Rd
<< 8;
14107 inst
.instruction
|= Rm
;
14108 inst
.instruction
|= inst
.operands
[2].imm
<< 4;
14112 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
!= 0,
14113 _("Thumb encoding does not support rotation"));
14114 constraint (1, BAD_HIREG
);
14121 inst
.relocs
[0].type
= BFD_RELOC_ARM_SWI
;
14130 half
= (inst
.instruction
& 0x10) != 0;
14131 set_pred_insn_type_last ();
14132 constraint (inst
.operands
[0].immisreg
,
14133 _("instruction requires register index"));
14135 Rn
= inst
.operands
[0].reg
;
14136 Rm
= inst
.operands
[0].imm
;
14138 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
))
14139 constraint (Rn
== REG_SP
, BAD_SP
);
14140 reject_bad_reg (Rm
);
14142 constraint (!half
&& inst
.operands
[0].shifted
,
14143 _("instruction does not allow shifted index"));
14144 inst
.instruction
|= (Rn
<< 16) | Rm
;
14150 if (!inst
.operands
[0].present
)
14151 inst
.operands
[0].imm
= 0;
14153 if ((unsigned int) inst
.operands
[0].imm
> 255 || inst
.size_req
== 4)
14155 constraint (inst
.size_req
== 2,
14156 _("immediate value out of range"));
14157 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14158 inst
.instruction
|= (inst
.operands
[0].imm
& 0xf000u
) << 4;
14159 inst
.instruction
|= (inst
.operands
[0].imm
& 0x0fffu
) << 0;
14163 inst
.instruction
= THUMB_OP16 (inst
.instruction
);
14164 inst
.instruction
|= inst
.operands
[0].imm
;
14167 set_pred_insn_type (NEUTRAL_IT_INSN
);
14174 do_t_ssat_usat (0);
14182 Rd
= inst
.operands
[0].reg
;
14183 Rn
= inst
.operands
[2].reg
;
14185 reject_bad_reg (Rd
);
14186 reject_bad_reg (Rn
);
14188 inst
.instruction
|= Rd
<< 8;
14189 inst
.instruction
|= inst
.operands
[1].imm
;
14190 inst
.instruction
|= Rn
<< 16;
14193 /* Checking the range of the branch offset (VAL) with NBITS bits
14194 and IS_SIGNED signedness. Also checks the LSB to be 0. */
14196 v8_1_branch_value_check (int val
, int nbits
, int is_signed
)
14198 gas_assert (nbits
> 0 && nbits
<= 32);
14201 int cmp
= (1 << (nbits
- 1));
14202 if ((val
< -cmp
) || (val
>= cmp
) || (val
& 0x01))
14207 if ((val
<= 0) || (val
>= (1 << nbits
)) || (val
& 0x1))
14213 /* For branches in Armv8.1-M Mainline. */
14215 do_t_branch_future (void)
14217 unsigned long insn
= inst
.instruction
;
14219 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
14220 if (inst
.operands
[0].hasreloc
== 0)
14222 if (v8_1_branch_value_check (inst
.operands
[0].imm
, 5, FALSE
) == FAIL
)
14223 as_bad (BAD_BRANCH_OFF
);
14225 inst
.instruction
|= ((inst
.operands
[0].imm
& 0x1f) >> 1) << 23;
14229 inst
.relocs
[0].type
= BFD_RELOC_THUMB_PCREL_BRANCH5
;
14230 inst
.relocs
[0].pc_rel
= 1;
14236 if (inst
.operands
[1].hasreloc
== 0)
14238 int val
= inst
.operands
[1].imm
;
14239 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 17, TRUE
) == FAIL
)
14240 as_bad (BAD_BRANCH_OFF
);
14242 int immA
= (val
& 0x0001f000) >> 12;
14243 int immB
= (val
& 0x00000ffc) >> 2;
14244 int immC
= (val
& 0x00000002) >> 1;
14245 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14249 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF17
;
14250 inst
.relocs
[1].pc_rel
= 1;
14255 if (inst
.operands
[1].hasreloc
== 0)
14257 int val
= inst
.operands
[1].imm
;
14258 if (v8_1_branch_value_check (inst
.operands
[1].imm
, 19, TRUE
) == FAIL
)
14259 as_bad (BAD_BRANCH_OFF
);
14261 int immA
= (val
& 0x0007f000) >> 12;
14262 int immB
= (val
& 0x00000ffc) >> 2;
14263 int immC
= (val
& 0x00000002) >> 1;
14264 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14268 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF19
;
14269 inst
.relocs
[1].pc_rel
= 1;
14273 case T_MNEM_bfcsel
:
14275 if (inst
.operands
[1].hasreloc
== 0)
14277 int val
= inst
.operands
[1].imm
;
14278 int immA
= (val
& 0x00001000) >> 12;
14279 int immB
= (val
& 0x00000ffc) >> 2;
14280 int immC
= (val
& 0x00000002) >> 1;
14281 inst
.instruction
|= (immA
<< 16) | (immB
<< 1) | (immC
<< 11);
14285 inst
.relocs
[1].type
= BFD_RELOC_ARM_THUMB_BF13
;
14286 inst
.relocs
[1].pc_rel
= 1;
14290 if (inst
.operands
[2].hasreloc
== 0)
14292 constraint ((inst
.operands
[0].hasreloc
!= 0), BAD_ARGS
);
14293 int val2
= inst
.operands
[2].imm
;
14294 int val0
= inst
.operands
[0].imm
& 0x1f;
14295 int diff
= val2
- val0
;
14297 inst
.instruction
|= 1 << 17; /* T bit. */
14298 else if (diff
!= 2)
14299 as_bad (_("out of range label-relative fixup value"));
14303 constraint ((inst
.operands
[0].hasreloc
== 0), BAD_ARGS
);
14304 inst
.relocs
[2].type
= BFD_RELOC_THUMB_PCREL_BFCSEL
;
14305 inst
.relocs
[2].pc_rel
= 1;
14309 constraint (inst
.cond
!= COND_ALWAYS
, BAD_COND
);
14310 inst
.instruction
|= (inst
.operands
[3].imm
& 0xf) << 18;
14315 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
14322 /* Helper function for do_t_loloop to handle relocations. */
14324 v8_1_loop_reloc (int is_le
)
14326 if (inst
.relocs
[0].exp
.X_op
== O_constant
)
14328 int value
= inst
.relocs
[0].exp
.X_add_number
;
14329 value
= (is_le
) ? -value
: value
;
14331 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
14332 as_bad (BAD_BRANCH_OFF
);
14336 immh
= (value
& 0x00000ffc) >> 2;
14337 imml
= (value
& 0x00000002) >> 1;
14339 inst
.instruction
|= (imml
<< 11) | (immh
<< 1);
14343 inst
.relocs
[0].type
= BFD_RELOC_ARM_THUMB_LOOP12
;
14344 inst
.relocs
[0].pc_rel
= 1;
14348 /* For shifts in MVE. */
14350 do_mve_scalar_shift (void)
14352 if (!inst
.operands
[2].present
)
14354 inst
.operands
[2] = inst
.operands
[1];
14355 inst
.operands
[1].reg
= 0xf;
14358 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
14359 inst
.instruction
|= inst
.operands
[1].reg
<< 8;
14361 if (inst
.operands
[2].isreg
)
14363 /* Assuming Rm is already checked not to be 11x1. */
14364 constraint (inst
.operands
[2].reg
== inst
.operands
[0].reg
, BAD_OVERLAP
);
14365 constraint (inst
.operands
[2].reg
== inst
.operands
[1].reg
, BAD_OVERLAP
);
14366 inst
.instruction
|= inst
.operands
[2].reg
<< 12;
14370 /* Assuming imm is already checked as [1,32]. */
14371 unsigned int value
= inst
.operands
[2].imm
;
14372 inst
.instruction
|= (value
& 0x1c) << 10;
14373 inst
.instruction
|= (value
& 0x03) << 6;
14374 /* Change last 4 bits from 0xd to 0xf. */
14375 inst
.instruction
|= 0x2;
14379 /* MVE instruction encoder helpers. */
14380 #define M_MNEM_vabav 0xee800f01
14381 #define M_MNEM_vmladav 0xeef00e00
14382 #define M_MNEM_vmladava 0xeef00e20
14383 #define M_MNEM_vmladavx 0xeef01e00
14384 #define M_MNEM_vmladavax 0xeef01e20
14385 #define M_MNEM_vmlsdav 0xeef00e01
14386 #define M_MNEM_vmlsdava 0xeef00e21
14387 #define M_MNEM_vmlsdavx 0xeef01e01
14388 #define M_MNEM_vmlsdavax 0xeef01e21
14389 #define M_MNEM_vmullt 0xee011e00
14390 #define M_MNEM_vmullb 0xee010e00
14391 #define M_MNEM_vst20 0xfc801e00
14392 #define M_MNEM_vst21 0xfc801e20
14393 #define M_MNEM_vst40 0xfc801e01
14394 #define M_MNEM_vst41 0xfc801e21
14395 #define M_MNEM_vst42 0xfc801e41
14396 #define M_MNEM_vst43 0xfc801e61
14397 #define M_MNEM_vld20 0xfc901e00
14398 #define M_MNEM_vld21 0xfc901e20
14399 #define M_MNEM_vld40 0xfc901e01
14400 #define M_MNEM_vld41 0xfc901e21
14401 #define M_MNEM_vld42 0xfc901e41
14402 #define M_MNEM_vld43 0xfc901e61
14403 #define M_MNEM_vstrb 0xec000e00
14404 #define M_MNEM_vstrh 0xec000e10
14405 #define M_MNEM_vstrw 0xec000e40
14406 #define M_MNEM_vstrd 0xec000e50
14407 #define M_MNEM_vldrb 0xec100e00
14408 #define M_MNEM_vldrh 0xec100e10
14409 #define M_MNEM_vldrw 0xec100e40
14410 #define M_MNEM_vldrd 0xec100e50
14411 #define M_MNEM_vmovlt 0xeea01f40
14412 #define M_MNEM_vmovlb 0xeea00f40
14413 #define M_MNEM_vmovnt 0xfe311e81
14414 #define M_MNEM_vmovnb 0xfe310e81
14415 #define M_MNEM_vadc 0xee300f00
14416 #define M_MNEM_vadci 0xee301f00
14417 #define M_MNEM_vbrsr 0xfe011e60
14418 #define M_MNEM_vaddlv 0xee890f00
14419 #define M_MNEM_vaddlva 0xee890f20
14420 #define M_MNEM_vaddv 0xeef10f00
14421 #define M_MNEM_vaddva 0xeef10f20
14422 #define M_MNEM_vddup 0xee011f6e
14423 #define M_MNEM_vdwdup 0xee011f60
14424 #define M_MNEM_vidup 0xee010f6e
14425 #define M_MNEM_viwdup 0xee010f60
14426 #define M_MNEM_vmaxv 0xeee20f00
14427 #define M_MNEM_vmaxav 0xeee00f00
14428 #define M_MNEM_vminv 0xeee20f80
14429 #define M_MNEM_vminav 0xeee00f80
14430 #define M_MNEM_vmlaldav 0xee800e00
14431 #define M_MNEM_vmlaldava 0xee800e20
14432 #define M_MNEM_vmlaldavx 0xee801e00
14433 #define M_MNEM_vmlaldavax 0xee801e20
14434 #define M_MNEM_vmlsldav 0xee800e01
14435 #define M_MNEM_vmlsldava 0xee800e21
14436 #define M_MNEM_vmlsldavx 0xee801e01
14437 #define M_MNEM_vmlsldavax 0xee801e21
14438 #define M_MNEM_vrmlaldavhx 0xee801f00
14439 #define M_MNEM_vrmlaldavhax 0xee801f20
14440 #define M_MNEM_vrmlsldavh 0xfe800e01
14441 #define M_MNEM_vrmlsldavha 0xfe800e21
14442 #define M_MNEM_vrmlsldavhx 0xfe801e01
14443 #define M_MNEM_vrmlsldavhax 0xfe801e21
14444 #define M_MNEM_vqmovnt 0xee331e01
14445 #define M_MNEM_vqmovnb 0xee330e01
14446 #define M_MNEM_vqmovunt 0xee311e81
14447 #define M_MNEM_vqmovunb 0xee310e81
14448 #define M_MNEM_vshrnt 0xee801fc1
14449 #define M_MNEM_vshrnb 0xee800fc1
14450 #define M_MNEM_vrshrnt 0xfe801fc1
14451 #define M_MNEM_vqshrnt 0xee801f40
14452 #define M_MNEM_vqshrnb 0xee800f40
14453 #define M_MNEM_vqshrunt 0xee801fc0
14454 #define M_MNEM_vqshrunb 0xee800fc0
14455 #define M_MNEM_vrshrnb 0xfe800fc1
14456 #define M_MNEM_vqrshrnt 0xee801f41
14457 #define M_MNEM_vqrshrnb 0xee800f41
14458 #define M_MNEM_vqrshrunt 0xfe801fc0
14459 #define M_MNEM_vqrshrunb 0xfe800fc0
14461 /* Neon instruction encoder helpers. */
14463 /* Encodings for the different types for various Neon opcodes. */
14465 /* An "invalid" code for the following tables. */
14468 struct neon_tab_entry
14471 unsigned float_or_poly
;
14472 unsigned scalar_or_imm
;
14475 /* Map overloaded Neon opcodes to their respective encodings. */
14476 #define NEON_ENC_TAB \
14477 X(vabd, 0x0000700, 0x1200d00, N_INV), \
14478 X(vabdl, 0x0800700, N_INV, N_INV), \
14479 X(vmax, 0x0000600, 0x0000f00, N_INV), \
14480 X(vmin, 0x0000610, 0x0200f00, N_INV), \
14481 X(vpadd, 0x0000b10, 0x1000d00, N_INV), \
14482 X(vpmax, 0x0000a00, 0x1000f00, N_INV), \
14483 X(vpmin, 0x0000a10, 0x1200f00, N_INV), \
14484 X(vadd, 0x0000800, 0x0000d00, N_INV), \
14485 X(vaddl, 0x0800000, N_INV, N_INV), \
14486 X(vsub, 0x1000800, 0x0200d00, N_INV), \
14487 X(vsubl, 0x0800200, N_INV, N_INV), \
14488 X(vceq, 0x1000810, 0x0000e00, 0x1b10100), \
14489 X(vcge, 0x0000310, 0x1000e00, 0x1b10080), \
14490 X(vcgt, 0x0000300, 0x1200e00, 0x1b10000), \
14491 /* Register variants of the following two instructions are encoded as
14492 vcge / vcgt with the operands reversed. */ \
14493 X(vclt, 0x0000300, 0x1200e00, 0x1b10200), \
14494 X(vcle, 0x0000310, 0x1000e00, 0x1b10180), \
14495 X(vfma, N_INV, 0x0000c10, N_INV), \
14496 X(vfms, N_INV, 0x0200c10, N_INV), \
14497 X(vmla, 0x0000900, 0x0000d10, 0x0800040), \
14498 X(vmls, 0x1000900, 0x0200d10, 0x0800440), \
14499 X(vmul, 0x0000910, 0x1000d10, 0x0800840), \
14500 X(vmull, 0x0800c00, 0x0800e00, 0x0800a40), /* polynomial not float. */ \
14501 X(vmlal, 0x0800800, N_INV, 0x0800240), \
14502 X(vmlsl, 0x0800a00, N_INV, 0x0800640), \
14503 X(vqdmlal, 0x0800900, N_INV, 0x0800340), \
14504 X(vqdmlsl, 0x0800b00, N_INV, 0x0800740), \
14505 X(vqdmull, 0x0800d00, N_INV, 0x0800b40), \
14506 X(vqdmulh, 0x0000b00, N_INV, 0x0800c40), \
14507 X(vqrdmulh, 0x1000b00, N_INV, 0x0800d40), \
14508 X(vqrdmlah, 0x3000b10, N_INV, 0x0800e40), \
14509 X(vqrdmlsh, 0x3000c10, N_INV, 0x0800f40), \
14510 X(vshl, 0x0000400, N_INV, 0x0800510), \
14511 X(vqshl, 0x0000410, N_INV, 0x0800710), \
14512 X(vand, 0x0000110, N_INV, 0x0800030), \
14513 X(vbic, 0x0100110, N_INV, 0x0800030), \
14514 X(veor, 0x1000110, N_INV, N_INV), \
14515 X(vorn, 0x0300110, N_INV, 0x0800010), \
14516 X(vorr, 0x0200110, N_INV, 0x0800010), \
14517 X(vmvn, 0x1b00580, N_INV, 0x0800030), \
14518 X(vshll, 0x1b20300, N_INV, 0x0800a10), /* max shift, immediate. */ \
14519 X(vcvt, 0x1b30600, N_INV, 0x0800e10), /* integer, fixed-point. */ \
14520 X(vdup, 0xe800b10, N_INV, 0x1b00c00), /* arm, scalar. */ \
14521 X(vld1, 0x0200000, 0x0a00000, 0x0a00c00), /* interlv, lane, dup. */ \
14522 X(vst1, 0x0000000, 0x0800000, N_INV), \
14523 X(vld2, 0x0200100, 0x0a00100, 0x0a00d00), \
14524 X(vst2, 0x0000100, 0x0800100, N_INV), \
14525 X(vld3, 0x0200200, 0x0a00200, 0x0a00e00), \
14526 X(vst3, 0x0000200, 0x0800200, N_INV), \
14527 X(vld4, 0x0200300, 0x0a00300, 0x0a00f00), \
14528 X(vst4, 0x0000300, 0x0800300, N_INV), \
14529 X(vmovn, 0x1b20200, N_INV, N_INV), \
14530 X(vtrn, 0x1b20080, N_INV, N_INV), \
14531 X(vqmovn, 0x1b20200, N_INV, N_INV), \
14532 X(vqmovun, 0x1b20240, N_INV, N_INV), \
14533 X(vnmul, 0xe200a40, 0xe200b40, N_INV), \
14534 X(vnmla, 0xe100a40, 0xe100b40, N_INV), \
14535 X(vnmls, 0xe100a00, 0xe100b00, N_INV), \
14536 X(vfnma, 0xe900a40, 0xe900b40, N_INV), \
14537 X(vfnms, 0xe900a00, 0xe900b00, N_INV), \
14538 X(vcmp, 0xeb40a40, 0xeb40b40, N_INV), \
14539 X(vcmpz, 0xeb50a40, 0xeb50b40, N_INV), \
14540 X(vcmpe, 0xeb40ac0, 0xeb40bc0, N_INV), \
14541 X(vcmpez, 0xeb50ac0, 0xeb50bc0, N_INV), \
14542 X(vseleq, 0xe000a00, N_INV, N_INV), \
14543 X(vselvs, 0xe100a00, N_INV, N_INV), \
14544 X(vselge, 0xe200a00, N_INV, N_INV), \
14545 X(vselgt, 0xe300a00, N_INV, N_INV), \
14546 X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
14547 X(vminnm, 0xe800a40, 0x3200f10, N_INV), \
14548 X(vcvta, 0xebc0a40, 0x3bb0000, N_INV), \
14549 X(vrintr, 0xeb60a40, 0x3ba0400, N_INV), \
14550 X(vrinta, 0xeb80a40, 0x3ba0400, N_INV), \
14551 X(aes, 0x3b00300, N_INV, N_INV), \
14552 X(sha3op, 0x2000c00, N_INV, N_INV), \
14553 X(sha1h, 0x3b902c0, N_INV, N_INV), \
14554 X(sha2op, 0x3ba0380, N_INV, N_INV)
14558 #define X(OPC,I,F,S) N_MNEM_##OPC
14563 static const struct neon_tab_entry neon_enc_tab
[] =
14565 #define X(OPC,I,F,S) { (I), (F), (S) }
14570 /* Do not use these macros; instead, use NEON_ENCODE defined below. */
14571 #define NEON_ENC_INTEGER_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14572 #define NEON_ENC_ARMREG_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14573 #define NEON_ENC_POLY_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14574 #define NEON_ENC_FLOAT_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14575 #define NEON_ENC_SCALAR_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14576 #define NEON_ENC_IMMED_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14577 #define NEON_ENC_INTERLV_(X) (neon_enc_tab[(X) & 0x0fffffff].integer)
14578 #define NEON_ENC_LANE_(X) (neon_enc_tab[(X) & 0x0fffffff].float_or_poly)
14579 #define NEON_ENC_DUP_(X) (neon_enc_tab[(X) & 0x0fffffff].scalar_or_imm)
14580 #define NEON_ENC_SINGLE_(X) \
14581 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf0000000))
14582 #define NEON_ENC_DOUBLE_(X) \
14583 ((neon_enc_tab[(X) & 0x0fffffff].float_or_poly) | ((X) & 0xf0000000))
14584 #define NEON_ENC_FPV8_(X) \
14585 ((neon_enc_tab[(X) & 0x0fffffff].integer) | ((X) & 0xf000000))
14587 #define NEON_ENCODE(type, inst) \
14590 inst.instruction = NEON_ENC_##type##_ (inst.instruction); \
14591 inst.is_neon = 1; \
14595 #define check_neon_suffixes \
14598 if (!inst.error && inst.vectype.elems > 0 && !inst.is_neon) \
14600 as_bad (_("invalid neon suffix for non neon instruction")); \
14606 /* Define shapes for instruction operands. The following mnemonic characters
14607 are used in this table:
14609 F - VFP S<n> register
14610 D - Neon D<n> register
14611 Q - Neon Q<n> register
14615 L - D<n> register list
14617 This table is used to generate various data:
14618 - enumerations of the form NS_DDR to be used as arguments to
14620 - a table classifying shapes into single, double, quad, mixed.
14621 - a table used to drive neon_select_shape. */
14623 #define NEON_SHAPE_DEF \
14624 X(4, (R, R, Q, Q), QUAD), \
14625 X(4, (Q, R, R, I), QUAD), \
14626 X(4, (R, R, S, S), QUAD), \
14627 X(4, (S, S, R, R), QUAD), \
14628 X(3, (Q, R, I), QUAD), \
14629 X(3, (I, Q, Q), QUAD), \
14630 X(3, (I, Q, R), QUAD), \
14631 X(3, (R, Q, Q), QUAD), \
14632 X(3, (D, D, D), DOUBLE), \
14633 X(3, (Q, Q, Q), QUAD), \
14634 X(3, (D, D, I), DOUBLE), \
14635 X(3, (Q, Q, I), QUAD), \
14636 X(3, (D, D, S), DOUBLE), \
14637 X(3, (Q, Q, S), QUAD), \
14638 X(3, (Q, Q, R), QUAD), \
14639 X(3, (R, R, Q), QUAD), \
14640 X(2, (R, Q), QUAD), \
14641 X(2, (D, D), DOUBLE), \
14642 X(2, (Q, Q), QUAD), \
14643 X(2, (D, S), DOUBLE), \
14644 X(2, (Q, S), QUAD), \
14645 X(2, (D, R), DOUBLE), \
14646 X(2, (Q, R), QUAD), \
14647 X(2, (D, I), DOUBLE), \
14648 X(2, (Q, I), QUAD), \
14649 X(3, (D, L, D), DOUBLE), \
14650 X(2, (D, Q), MIXED), \
14651 X(2, (Q, D), MIXED), \
14652 X(3, (D, Q, I), MIXED), \
14653 X(3, (Q, D, I), MIXED), \
14654 X(3, (Q, D, D), MIXED), \
14655 X(3, (D, Q, Q), MIXED), \
14656 X(3, (Q, Q, D), MIXED), \
14657 X(3, (Q, D, S), MIXED), \
14658 X(3, (D, Q, S), MIXED), \
14659 X(4, (D, D, D, I), DOUBLE), \
14660 X(4, (Q, Q, Q, I), QUAD), \
14661 X(4, (D, D, S, I), DOUBLE), \
14662 X(4, (Q, Q, S, I), QUAD), \
14663 X(2, (F, F), SINGLE), \
14664 X(3, (F, F, F), SINGLE), \
14665 X(2, (F, I), SINGLE), \
14666 X(2, (F, D), MIXED), \
14667 X(2, (D, F), MIXED), \
14668 X(3, (F, F, I), MIXED), \
14669 X(4, (R, R, F, F), SINGLE), \
14670 X(4, (F, F, R, R), SINGLE), \
14671 X(3, (D, R, R), DOUBLE), \
14672 X(3, (R, R, D), DOUBLE), \
14673 X(2, (S, R), SINGLE), \
14674 X(2, (R, S), SINGLE), \
14675 X(2, (F, R), SINGLE), \
14676 X(2, (R, F), SINGLE), \
14677 /* Used for MVE tail predicated loop instructions. */\
14678 X(2, (R, R), QUAD), \
14679 /* Half float shape supported so far. */\
14680 X (2, (H, D), MIXED), \
14681 X (2, (D, H), MIXED), \
14682 X (2, (H, F), MIXED), \
14683 X (2, (F, H), MIXED), \
14684 X (2, (H, H), HALF), \
14685 X (2, (H, R), HALF), \
14686 X (2, (R, H), HALF), \
14687 X (2, (H, I), HALF), \
14688 X (3, (H, H, H), HALF), \
14689 X (3, (H, F, I), MIXED), \
14690 X (3, (F, H, I), MIXED), \
14691 X (3, (D, H, H), MIXED), \
14692 X (3, (D, H, S), MIXED)
14694 #define S2(A,B) NS_##A##B
14695 #define S3(A,B,C) NS_##A##B##C
14696 #define S4(A,B,C,D) NS_##A##B##C##D
14698 #define X(N, L, C) S##N L
14711 enum neon_shape_class
14720 #define X(N, L, C) SC_##C
14722 static enum neon_shape_class neon_shape_class
[] =
14741 /* Register widths of above. */
14742 static unsigned neon_shape_el_size
[] =
14754 struct neon_shape_info
14757 enum neon_shape_el el
[NEON_MAX_TYPE_ELS
];
14760 #define S2(A,B) { SE_##A, SE_##B }
14761 #define S3(A,B,C) { SE_##A, SE_##B, SE_##C }
14762 #define S4(A,B,C,D) { SE_##A, SE_##B, SE_##C, SE_##D }
14764 #define X(N, L, C) { N, S##N L }
14766 static struct neon_shape_info neon_shape_tab
[] =
14776 /* Bit masks used in type checking given instructions.
14777 'N_EQK' means the type must be the same as (or based on in some way) the key
14778 type, which itself is marked with the 'N_KEY' bit. If the 'N_EQK' bit is
14779 set, various other bits can be set as well in order to modify the meaning of
14780 the type constraint. */
14782 enum neon_type_mask
14806 N_KEY
= 0x1000000, /* Key element (main type specifier). */
14807 N_EQK
= 0x2000000, /* Given operand has the same type & size as the key. */
14808 N_VFP
= 0x4000000, /* VFP mode: operand size must match register width. */
14809 N_UNT
= 0x8000000, /* Must be explicitly untyped. */
14810 N_DBL
= 0x0000001, /* If N_EQK, this operand is twice the size. */
14811 N_HLF
= 0x0000002, /* If N_EQK, this operand is half the size. */
14812 N_SGN
= 0x0000004, /* If N_EQK, this operand is forced to be signed. */
14813 N_UNS
= 0x0000008, /* If N_EQK, this operand is forced to be unsigned. */
14814 N_INT
= 0x0000010, /* If N_EQK, this operand is forced to be integer. */
14815 N_FLT
= 0x0000020, /* If N_EQK, this operand is forced to be float. */
14816 N_SIZ
= 0x0000040, /* If N_EQK, this operand is forced to be size-only. */
14818 N_MAX_NONSPECIAL
= N_P64
14821 #define N_ALLMODS (N_DBL | N_HLF | N_SGN | N_UNS | N_INT | N_FLT | N_SIZ)
14823 #define N_SU_ALL (N_S8 | N_S16 | N_S32 | N_S64 | N_U8 | N_U16 | N_U32 | N_U64)
14824 #define N_SU_32 (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14825 #define N_SU_16_64 (N_S16 | N_S32 | N_S64 | N_U16 | N_U32 | N_U64)
14826 #define N_S_32 (N_S8 | N_S16 | N_S32)
14827 #define N_F_16_32 (N_F16 | N_F32)
14828 #define N_SUF_32 (N_SU_32 | N_F_16_32)
14829 #define N_I_ALL (N_I8 | N_I16 | N_I32 | N_I64)
14830 #define N_IF_32 (N_I8 | N_I16 | N_I32 | N_F16 | N_F32)
14831 #define N_F_ALL (N_F16 | N_F32 | N_F64)
14832 #define N_I_MVE (N_I8 | N_I16 | N_I32)
14833 #define N_F_MVE (N_F16 | N_F32)
14834 #define N_SU_MVE (N_S8 | N_S16 | N_S32 | N_U8 | N_U16 | N_U32)
14836 /* Pass this as the first type argument to neon_check_type to ignore types
14838 #define N_IGNORE_TYPE (N_KEY | N_EQK)
14840 /* Select a "shape" for the current instruction (describing register types or
14841 sizes) from a list of alternatives. Return NS_NULL if the current instruction
14842 doesn't fit. For non-polymorphic shapes, checking is usually done as a
14843 function of operand parsing, so this function doesn't need to be called.
14844 Shapes should be listed in order of decreasing length. */
14846 static enum neon_shape
14847 neon_select_shape (enum neon_shape shape
, ...)
14850 enum neon_shape first_shape
= shape
;
14852 /* Fix missing optional operands. FIXME: we don't know at this point how
14853 many arguments we should have, so this makes the assumption that we have
14854 > 1. This is true of all current Neon opcodes, I think, but may not be
14855 true in the future. */
14856 if (!inst
.operands
[1].present
)
14857 inst
.operands
[1] = inst
.operands
[0];
14859 va_start (ap
, shape
);
14861 for (; shape
!= NS_NULL
; shape
= (enum neon_shape
) va_arg (ap
, int))
14866 for (j
= 0; j
< neon_shape_tab
[shape
].els
; j
++)
14868 if (!inst
.operands
[j
].present
)
14874 switch (neon_shape_tab
[shape
].el
[j
])
14876 /* If a .f16, .16, .u16, .s16 type specifier is given over
14877 a VFP single precision register operand, it's essentially
14878 means only half of the register is used.
14880 If the type specifier is given after the mnemonics, the
14881 information is stored in inst.vectype. If the type specifier
14882 is given after register operand, the information is stored
14883 in inst.operands[].vectype.
14885 When there is only one type specifier, and all the register
14886 operands are the same type of hardware register, the type
14887 specifier applies to all register operands.
14889 If no type specifier is given, the shape is inferred from
14890 operand information.
14893 vadd.f16 s0, s1, s2: NS_HHH
14894 vabs.f16 s0, s1: NS_HH
14895 vmov.f16 s0, r1: NS_HR
14896 vmov.f16 r0, s1: NS_RH
14897 vcvt.f16 r0, s1: NS_RH
14898 vcvt.f16.s32 s2, s2, #29: NS_HFI
14899 vcvt.f16.s32 s2, s2: NS_HF
14902 if (!(inst
.operands
[j
].isreg
14903 && inst
.operands
[j
].isvec
14904 && inst
.operands
[j
].issingle
14905 && !inst
.operands
[j
].isquad
14906 && ((inst
.vectype
.elems
== 1
14907 && inst
.vectype
.el
[0].size
== 16)
14908 || (inst
.vectype
.elems
> 1
14909 && inst
.vectype
.el
[j
].size
== 16)
14910 || (inst
.vectype
.elems
== 0
14911 && inst
.operands
[j
].vectype
.type
!= NT_invtype
14912 && inst
.operands
[j
].vectype
.size
== 16))))
14917 if (!(inst
.operands
[j
].isreg
14918 && inst
.operands
[j
].isvec
14919 && inst
.operands
[j
].issingle
14920 && !inst
.operands
[j
].isquad
14921 && ((inst
.vectype
.elems
== 1 && inst
.vectype
.el
[0].size
== 32)
14922 || (inst
.vectype
.elems
> 1 && inst
.vectype
.el
[j
].size
== 32)
14923 || (inst
.vectype
.elems
== 0
14924 && (inst
.operands
[j
].vectype
.size
== 32
14925 || inst
.operands
[j
].vectype
.type
== NT_invtype
)))))
14930 if (!(inst
.operands
[j
].isreg
14931 && inst
.operands
[j
].isvec
14932 && !inst
.operands
[j
].isquad
14933 && !inst
.operands
[j
].issingle
))
14938 if (!(inst
.operands
[j
].isreg
14939 && !inst
.operands
[j
].isvec
))
14944 if (!(inst
.operands
[j
].isreg
14945 && inst
.operands
[j
].isvec
14946 && inst
.operands
[j
].isquad
14947 && !inst
.operands
[j
].issingle
))
14952 if (!(!inst
.operands
[j
].isreg
14953 && !inst
.operands
[j
].isscalar
))
14958 if (!(!inst
.operands
[j
].isreg
14959 && inst
.operands
[j
].isscalar
))
14969 if (matches
&& (j
>= ARM_IT_MAX_OPERANDS
|| !inst
.operands
[j
].present
))
14970 /* We've matched all the entries in the shape table, and we don't
14971 have any left over operands which have not been matched. */
14977 if (shape
== NS_NULL
&& first_shape
!= NS_NULL
)
14978 first_error (_("invalid instruction shape"));
14983 /* True if SHAPE is predominantly a quadword operation (most of the time, this
14984 means the Q bit should be set). */
14987 neon_quad (enum neon_shape shape
)
14989 return neon_shape_class
[shape
] == SC_QUAD
;
14993 neon_modify_type_size (unsigned typebits
, enum neon_el_type
*g_type
,
14996 /* Allow modification to be made to types which are constrained to be
14997 based on the key element, based on bits set alongside N_EQK. */
14998 if ((typebits
& N_EQK
) != 0)
15000 if ((typebits
& N_HLF
) != 0)
15002 else if ((typebits
& N_DBL
) != 0)
15004 if ((typebits
& N_SGN
) != 0)
15005 *g_type
= NT_signed
;
15006 else if ((typebits
& N_UNS
) != 0)
15007 *g_type
= NT_unsigned
;
15008 else if ((typebits
& N_INT
) != 0)
15009 *g_type
= NT_integer
;
15010 else if ((typebits
& N_FLT
) != 0)
15011 *g_type
= NT_float
;
15012 else if ((typebits
& N_SIZ
) != 0)
15013 *g_type
= NT_untyped
;
15017 /* Return operand OPNO promoted by bits set in THISARG. KEY should be the "key"
15018 operand type, i.e. the single type specified in a Neon instruction when it
15019 is the only one given. */
15021 static struct neon_type_el
15022 neon_type_promote (struct neon_type_el
*key
, unsigned thisarg
)
15024 struct neon_type_el dest
= *key
;
15026 gas_assert ((thisarg
& N_EQK
) != 0);
15028 neon_modify_type_size (thisarg
, &dest
.type
, &dest
.size
);
15033 /* Convert Neon type and size into compact bitmask representation. */
15035 static enum neon_type_mask
15036 type_chk_of_el_type (enum neon_el_type type
, unsigned size
)
15043 case 8: return N_8
;
15044 case 16: return N_16
;
15045 case 32: return N_32
;
15046 case 64: return N_64
;
15054 case 8: return N_I8
;
15055 case 16: return N_I16
;
15056 case 32: return N_I32
;
15057 case 64: return N_I64
;
15065 case 16: return N_F16
;
15066 case 32: return N_F32
;
15067 case 64: return N_F64
;
15075 case 8: return N_P8
;
15076 case 16: return N_P16
;
15077 case 64: return N_P64
;
15085 case 8: return N_S8
;
15086 case 16: return N_S16
;
15087 case 32: return N_S32
;
15088 case 64: return N_S64
;
15096 case 8: return N_U8
;
15097 case 16: return N_U16
;
15098 case 32: return N_U32
;
15099 case 64: return N_U64
;
15110 /* Convert compact Neon bitmask type representation to a type and size. Only
15111 handles the case where a single bit is set in the mask. */
15114 el_type_of_type_chk (enum neon_el_type
*type
, unsigned *size
,
15115 enum neon_type_mask mask
)
15117 if ((mask
& N_EQK
) != 0)
15120 if ((mask
& (N_S8
| N_U8
| N_I8
| N_8
| N_P8
)) != 0)
15122 else if ((mask
& (N_S16
| N_U16
| N_I16
| N_16
| N_F16
| N_P16
)) != 0)
15124 else if ((mask
& (N_S32
| N_U32
| N_I32
| N_32
| N_F32
)) != 0)
15126 else if ((mask
& (N_S64
| N_U64
| N_I64
| N_64
| N_F64
| N_P64
)) != 0)
15131 if ((mask
& (N_S8
| N_S16
| N_S32
| N_S64
)) != 0)
15133 else if ((mask
& (N_U8
| N_U16
| N_U32
| N_U64
)) != 0)
15134 *type
= NT_unsigned
;
15135 else if ((mask
& (N_I8
| N_I16
| N_I32
| N_I64
)) != 0)
15136 *type
= NT_integer
;
15137 else if ((mask
& (N_8
| N_16
| N_32
| N_64
)) != 0)
15138 *type
= NT_untyped
;
15139 else if ((mask
& (N_P8
| N_P16
| N_P64
)) != 0)
15141 else if ((mask
& (N_F_ALL
)) != 0)
15149 /* Modify a bitmask of allowed types. This is only needed for type
15153 modify_types_allowed (unsigned allowed
, unsigned mods
)
15156 enum neon_el_type type
;
15162 for (i
= 1; i
<= N_MAX_NONSPECIAL
; i
<<= 1)
15164 if (el_type_of_type_chk (&type
, &size
,
15165 (enum neon_type_mask
) (allowed
& i
)) == SUCCESS
)
15167 neon_modify_type_size (mods
, &type
, &size
);
15168 destmask
|= type_chk_of_el_type (type
, size
);
15175 /* Check type and return type classification.
15176 The manual states (paraphrase): If one datatype is given, it indicates the
15178 - the second operand, if there is one
15179 - the operand, if there is no second operand
15180 - the result, if there are no operands.
15181 This isn't quite good enough though, so we use a concept of a "key" datatype
15182 which is set on a per-instruction basis, which is the one which matters when
15183 only one data type is written.
15184 Note: this function has side-effects (e.g. filling in missing operands). All
15185 Neon instructions should call it before performing bit encoding. */
15187 static struct neon_type_el
15188 neon_check_type (unsigned els
, enum neon_shape ns
, ...)
15191 unsigned i
, pass
, key_el
= 0;
15192 unsigned types
[NEON_MAX_TYPE_ELS
];
15193 enum neon_el_type k_type
= NT_invtype
;
15194 unsigned k_size
= -1u;
15195 struct neon_type_el badtype
= {NT_invtype
, -1};
15196 unsigned key_allowed
= 0;
15198 /* Optional registers in Neon instructions are always (not) in operand 1.
15199 Fill in the missing operand here, if it was omitted. */
15200 if (els
> 1 && !inst
.operands
[1].present
)
15201 inst
.operands
[1] = inst
.operands
[0];
15203 /* Suck up all the varargs. */
15205 for (i
= 0; i
< els
; i
++)
15207 unsigned thisarg
= va_arg (ap
, unsigned);
15208 if (thisarg
== N_IGNORE_TYPE
)
15213 types
[i
] = thisarg
;
15214 if ((thisarg
& N_KEY
) != 0)
15219 if (inst
.vectype
.elems
> 0)
15220 for (i
= 0; i
< els
; i
++)
15221 if (inst
.operands
[i
].vectype
.type
!= NT_invtype
)
15223 first_error (_("types specified in both the mnemonic and operands"));
15227 /* Duplicate inst.vectype elements here as necessary.
15228 FIXME: No idea if this is exactly the same as the ARM assembler,
15229 particularly when an insn takes one register and one non-register
15231 if (inst
.vectype
.elems
== 1 && els
> 1)
15234 inst
.vectype
.elems
= els
;
15235 inst
.vectype
.el
[key_el
] = inst
.vectype
.el
[0];
15236 for (j
= 0; j
< els
; j
++)
15238 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15241 else if (inst
.vectype
.elems
== 0 && els
> 0)
15244 /* No types were given after the mnemonic, so look for types specified
15245 after each operand. We allow some flexibility here; as long as the
15246 "key" operand has a type, we can infer the others. */
15247 for (j
= 0; j
< els
; j
++)
15248 if (inst
.operands
[j
].vectype
.type
!= NT_invtype
)
15249 inst
.vectype
.el
[j
] = inst
.operands
[j
].vectype
;
15251 if (inst
.operands
[key_el
].vectype
.type
!= NT_invtype
)
15253 for (j
= 0; j
< els
; j
++)
15254 if (inst
.operands
[j
].vectype
.type
== NT_invtype
)
15255 inst
.vectype
.el
[j
] = neon_type_promote (&inst
.vectype
.el
[key_el
],
15260 first_error (_("operand types can't be inferred"));
15264 else if (inst
.vectype
.elems
!= els
)
15266 first_error (_("type specifier has the wrong number of parts"));
15270 for (pass
= 0; pass
< 2; pass
++)
15272 for (i
= 0; i
< els
; i
++)
15274 unsigned thisarg
= types
[i
];
15275 unsigned types_allowed
= ((thisarg
& N_EQK
) != 0 && pass
!= 0)
15276 ? modify_types_allowed (key_allowed
, thisarg
) : thisarg
;
15277 enum neon_el_type g_type
= inst
.vectype
.el
[i
].type
;
15278 unsigned g_size
= inst
.vectype
.el
[i
].size
;
15280 /* Decay more-specific signed & unsigned types to sign-insensitive
15281 integer types if sign-specific variants are unavailable. */
15282 if ((g_type
== NT_signed
|| g_type
== NT_unsigned
)
15283 && (types_allowed
& N_SU_ALL
) == 0)
15284 g_type
= NT_integer
;
15286 /* If only untyped args are allowed, decay any more specific types to
15287 them. Some instructions only care about signs for some element
15288 sizes, so handle that properly. */
15289 if (((types_allowed
& N_UNT
) == 0)
15290 && ((g_size
== 8 && (types_allowed
& N_8
) != 0)
15291 || (g_size
== 16 && (types_allowed
& N_16
) != 0)
15292 || (g_size
== 32 && (types_allowed
& N_32
) != 0)
15293 || (g_size
== 64 && (types_allowed
& N_64
) != 0)))
15294 g_type
= NT_untyped
;
15298 if ((thisarg
& N_KEY
) != 0)
15302 key_allowed
= thisarg
& ~N_KEY
;
15304 /* Check architecture constraint on FP16 extension. */
15306 && k_type
== NT_float
15307 && ! ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15309 inst
.error
= _(BAD_FP16
);
15316 if ((thisarg
& N_VFP
) != 0)
15318 enum neon_shape_el regshape
;
15319 unsigned regwidth
, match
;
15321 /* PR 11136: Catch the case where we are passed a shape of NS_NULL. */
15324 first_error (_("invalid instruction shape"));
15327 regshape
= neon_shape_tab
[ns
].el
[i
];
15328 regwidth
= neon_shape_el_size
[regshape
];
15330 /* In VFP mode, operands must match register widths. If we
15331 have a key operand, use its width, else use the width of
15332 the current operand. */
15338 /* FP16 will use a single precision register. */
15339 if (regwidth
== 32 && match
== 16)
15341 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
))
15345 inst
.error
= _(BAD_FP16
);
15350 if (regwidth
!= match
)
15352 first_error (_("operand size must match register width"));
15357 if ((thisarg
& N_EQK
) == 0)
15359 unsigned given_type
= type_chk_of_el_type (g_type
, g_size
);
15361 if ((given_type
& types_allowed
) == 0)
15363 first_error (BAD_SIMD_TYPE
);
15369 enum neon_el_type mod_k_type
= k_type
;
15370 unsigned mod_k_size
= k_size
;
15371 neon_modify_type_size (thisarg
, &mod_k_type
, &mod_k_size
);
15372 if (g_type
!= mod_k_type
|| g_size
!= mod_k_size
)
15374 first_error (_("inconsistent types in Neon instruction"));
15382 return inst
.vectype
.el
[key_el
];
15385 /* Neon-style VFP instruction forwarding. */
15387 /* Thumb VFP instructions have 0xE in the condition field. */
15390 do_vfp_cond_or_thumb (void)
15395 inst
.instruction
|= 0xe0000000;
15397 inst
.instruction
|= inst
.cond
<< 28;
15400 /* Look up and encode a simple mnemonic, for use as a helper function for the
15401 Neon-style VFP syntax. This avoids duplication of bits of the insns table,
15402 etc. It is assumed that operand parsing has already been done, and that the
15403 operands are in the form expected by the given opcode (this isn't necessarily
15404 the same as the form in which they were parsed, hence some massaging must
15405 take place before this function is called).
15406 Checks current arch version against that in the looked-up opcode. */
15409 do_vfp_nsyn_opcode (const char *opname
)
15411 const struct asm_opcode
*opcode
;
15413 opcode
= (const struct asm_opcode
*) hash_find (arm_ops_hsh
, opname
);
15418 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
,
15419 thumb_mode
? *opcode
->tvariant
: *opcode
->avariant
),
15426 inst
.instruction
= opcode
->tvalue
;
15427 opcode
->tencode ();
15431 inst
.instruction
= (inst
.cond
<< 28) | opcode
->avalue
;
15432 opcode
->aencode ();
15437 do_vfp_nsyn_add_sub (enum neon_shape rs
)
15439 int is_add
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vadd
;
15441 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15444 do_vfp_nsyn_opcode ("fadds");
15446 do_vfp_nsyn_opcode ("fsubs");
15448 /* ARMv8.2 fp16 instruction. */
15450 do_scalar_fp16_v82_encode ();
15455 do_vfp_nsyn_opcode ("faddd");
15457 do_vfp_nsyn_opcode ("fsubd");
15461 /* Check operand types to see if this is a VFP instruction, and if so call
15465 try_vfp_nsyn (int args
, void (*pfn
) (enum neon_shape
))
15467 enum neon_shape rs
;
15468 struct neon_type_el et
;
15473 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15474 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15478 rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15479 et
= neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15480 N_F_ALL
| N_KEY
| N_VFP
);
15487 if (et
.type
!= NT_invtype
)
15498 do_vfp_nsyn_mla_mls (enum neon_shape rs
)
15500 int is_mla
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vmla
;
15502 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15505 do_vfp_nsyn_opcode ("fmacs");
15507 do_vfp_nsyn_opcode ("fnmacs");
15509 /* ARMv8.2 fp16 instruction. */
15511 do_scalar_fp16_v82_encode ();
15516 do_vfp_nsyn_opcode ("fmacd");
15518 do_vfp_nsyn_opcode ("fnmacd");
15523 do_vfp_nsyn_fma_fms (enum neon_shape rs
)
15525 int is_fma
= (inst
.instruction
& 0x0fffffff) == N_MNEM_vfma
;
15527 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15530 do_vfp_nsyn_opcode ("ffmas");
15532 do_vfp_nsyn_opcode ("ffnmas");
15534 /* ARMv8.2 fp16 instruction. */
15536 do_scalar_fp16_v82_encode ();
15541 do_vfp_nsyn_opcode ("ffmad");
15543 do_vfp_nsyn_opcode ("ffnmad");
15548 do_vfp_nsyn_mul (enum neon_shape rs
)
15550 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15552 do_vfp_nsyn_opcode ("fmuls");
15554 /* ARMv8.2 fp16 instruction. */
15556 do_scalar_fp16_v82_encode ();
15559 do_vfp_nsyn_opcode ("fmuld");
15563 do_vfp_nsyn_abs_neg (enum neon_shape rs
)
15565 int is_neg
= (inst
.instruction
& 0x80) != 0;
15566 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_VFP
| N_KEY
);
15568 if (rs
== NS_FF
|| rs
== NS_HH
)
15571 do_vfp_nsyn_opcode ("fnegs");
15573 do_vfp_nsyn_opcode ("fabss");
15575 /* ARMv8.2 fp16 instruction. */
15577 do_scalar_fp16_v82_encode ();
15582 do_vfp_nsyn_opcode ("fnegd");
15584 do_vfp_nsyn_opcode ("fabsd");
15588 /* Encode single-precision (only!) VFP fldm/fstm instructions. Double precision
15589 insns belong to Neon, and are handled elsewhere. */
15592 do_vfp_nsyn_ldm_stm (int is_dbmode
)
15594 int is_ldm
= (inst
.instruction
& (1 << 20)) != 0;
15598 do_vfp_nsyn_opcode ("fldmdbs");
15600 do_vfp_nsyn_opcode ("fldmias");
15605 do_vfp_nsyn_opcode ("fstmdbs");
15607 do_vfp_nsyn_opcode ("fstmias");
15612 do_vfp_nsyn_sqrt (void)
15614 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
15615 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
15617 if (rs
== NS_FF
|| rs
== NS_HH
)
15619 do_vfp_nsyn_opcode ("fsqrts");
15621 /* ARMv8.2 fp16 instruction. */
15623 do_scalar_fp16_v82_encode ();
15626 do_vfp_nsyn_opcode ("fsqrtd");
15630 do_vfp_nsyn_div (void)
15632 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15633 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15634 N_F_ALL
| N_KEY
| N_VFP
);
15636 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15638 do_vfp_nsyn_opcode ("fdivs");
15640 /* ARMv8.2 fp16 instruction. */
15642 do_scalar_fp16_v82_encode ();
15645 do_vfp_nsyn_opcode ("fdivd");
15649 do_vfp_nsyn_nmul (void)
15651 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_NULL
);
15652 neon_check_type (3, rs
, N_EQK
| N_VFP
, N_EQK
| N_VFP
,
15653 N_F_ALL
| N_KEY
| N_VFP
);
15655 if (rs
== NS_FFF
|| rs
== NS_HHH
)
15657 NEON_ENCODE (SINGLE
, inst
);
15658 do_vfp_sp_dyadic ();
15660 /* ARMv8.2 fp16 instruction. */
15662 do_scalar_fp16_v82_encode ();
15666 NEON_ENCODE (DOUBLE
, inst
);
15667 do_vfp_dp_rd_rn_rm ();
15669 do_vfp_cond_or_thumb ();
15673 /* Turn a size (8, 16, 32, 64) into the respective bit number minus 3
15677 neon_logbits (unsigned x
)
15679 return ffs (x
) - 4;
15682 #define LOW4(R) ((R) & 0xf)
15683 #define HI1(R) (((R) >> 4) & 1)
15686 mve_get_vcmp_vpt_cond (struct neon_type_el et
)
15691 first_error (BAD_EL_TYPE
);
15694 switch (inst
.operands
[0].imm
)
15697 first_error (_("invalid condition"));
15719 /* only accept eq and ne. */
15720 if (inst
.operands
[0].imm
> 1)
15722 first_error (_("invalid condition"));
15725 return inst
.operands
[0].imm
;
15727 if (inst
.operands
[0].imm
== 0x2)
15729 else if (inst
.operands
[0].imm
== 0x8)
15733 first_error (_("invalid condition"));
15737 switch (inst
.operands
[0].imm
)
15740 first_error (_("invalid condition"));
15756 /* Should be unreachable. */
15763 /* We are dealing with a vector predicated block. */
15764 if (inst
.operands
[0].present
)
15766 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15767 struct neon_type_el et
15768 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15771 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15773 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15775 if (et
.type
== NT_invtype
)
15778 if (et
.type
== NT_float
)
15780 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15782 constraint (et
.size
!= 16 && et
.size
!= 32, BAD_EL_TYPE
);
15783 inst
.instruction
|= (et
.size
== 16) << 28;
15784 inst
.instruction
|= 0x3 << 20;
15788 constraint (et
.size
!= 8 && et
.size
!= 16 && et
.size
!= 32,
15790 inst
.instruction
|= 1 << 28;
15791 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15794 if (inst
.operands
[2].isquad
)
15796 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15797 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15798 inst
.instruction
|= (fcond
& 0x2) >> 1;
15802 if (inst
.operands
[2].reg
== REG_SP
)
15803 as_tsktsk (MVE_BAD_SP
);
15804 inst
.instruction
|= 1 << 6;
15805 inst
.instruction
|= (fcond
& 0x2) << 4;
15806 inst
.instruction
|= inst
.operands
[2].reg
;
15808 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15809 inst
.instruction
|= (fcond
& 0x4) << 10;
15810 inst
.instruction
|= (fcond
& 0x1) << 7;
15813 set_pred_insn_type (VPT_INSN
);
15815 now_pred
.mask
= ((inst
.instruction
& 0x00400000) >> 19)
15816 | ((inst
.instruction
& 0xe000) >> 13);
15817 now_pred
.warn_deprecated
= FALSE
;
15818 now_pred
.type
= VECTOR_PRED
;
15825 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
15826 if (!inst
.operands
[1].isreg
|| !inst
.operands
[1].isquad
)
15827 first_error (_(reg_expected_msgs
[REG_TYPE_MQ
]));
15828 if (!inst
.operands
[2].present
)
15829 first_error (_("MVE vector or ARM register expected"));
15830 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
15832 /* Deal with 'else' conditional MVE's vcmp, it will be parsed as vcmpe. */
15833 if ((inst
.instruction
& 0xffffffff) == N_MNEM_vcmpe
15834 && inst
.operands
[1].isquad
)
15836 inst
.instruction
= N_MNEM_vcmp
;
15840 if (inst
.cond
> COND_ALWAYS
)
15841 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15843 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15845 enum neon_shape rs
= neon_select_shape (NS_IQQ
, NS_IQR
, NS_NULL
);
15846 struct neon_type_el et
15847 = neon_check_type (3, rs
, N_EQK
, N_KEY
| N_F_MVE
| N_I_MVE
| N_SU_32
,
15850 constraint (rs
== NS_IQR
&& inst
.operands
[2].reg
== REG_PC
15851 && !inst
.operands
[2].iszr
, BAD_PC
);
15853 unsigned fcond
= mve_get_vcmp_vpt_cond (et
);
15855 inst
.instruction
= 0xee010f00;
15856 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15857 inst
.instruction
|= (fcond
& 0x4) << 10;
15858 inst
.instruction
|= (fcond
& 0x1) << 7;
15859 if (et
.type
== NT_float
)
15861 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
15863 inst
.instruction
|= (et
.size
== 16) << 28;
15864 inst
.instruction
|= 0x3 << 20;
15868 inst
.instruction
|= 1 << 28;
15869 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15871 if (inst
.operands
[2].isquad
)
15873 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
15874 inst
.instruction
|= (fcond
& 0x2) >> 1;
15875 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
15879 if (inst
.operands
[2].reg
== REG_SP
)
15880 as_tsktsk (MVE_BAD_SP
);
15881 inst
.instruction
|= 1 << 6;
15882 inst
.instruction
|= (fcond
& 0x2) << 4;
15883 inst
.instruction
|= inst
.operands
[2].reg
;
15891 do_mve_vmaxa_vmina (void)
15893 if (inst
.cond
> COND_ALWAYS
)
15894 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15896 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15898 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
15899 struct neon_type_el et
15900 = neon_check_type (2, rs
, N_EQK
, N_KEY
| N_S8
| N_S16
| N_S32
);
15902 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15903 inst
.instruction
|= neon_logbits (et
.size
) << 18;
15904 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15905 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
15906 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
15911 do_mve_vfmas (void)
15913 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15914 struct neon_type_el et
15915 = neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
, N_EQK
);
15917 if (inst
.cond
> COND_ALWAYS
)
15918 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15920 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15922 if (inst
.operands
[2].reg
== REG_SP
)
15923 as_tsktsk (MVE_BAD_SP
);
15924 else if (inst
.operands
[2].reg
== REG_PC
)
15925 as_tsktsk (MVE_BAD_PC
);
15927 inst
.instruction
|= (et
.size
== 16) << 28;
15928 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15929 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
15930 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15931 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
15932 inst
.instruction
|= inst
.operands
[2].reg
;
15937 do_mve_viddup (void)
15939 if (inst
.cond
> COND_ALWAYS
)
15940 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15942 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15944 unsigned imm
= inst
.relocs
[0].exp
.X_add_number
;
15945 constraint (imm
!= 1 && imm
!= 2 && imm
!= 4 && imm
!= 8,
15946 _("immediate must be either 1, 2, 4 or 8"));
15948 enum neon_shape rs
;
15949 struct neon_type_el et
;
15951 if (inst
.instruction
== M_MNEM_vddup
|| inst
.instruction
== M_MNEM_vidup
)
15953 rs
= neon_select_shape (NS_QRI
, NS_NULL
);
15954 et
= neon_check_type (2, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
);
15959 constraint ((inst
.operands
[2].reg
% 2) != 1, BAD_EVEN
);
15960 if (inst
.operands
[2].reg
== REG_SP
)
15961 as_tsktsk (MVE_BAD_SP
);
15962 else if (inst
.operands
[2].reg
== REG_PC
)
15963 first_error (BAD_PC
);
15965 rs
= neon_select_shape (NS_QRRI
, NS_NULL
);
15966 et
= neon_check_type (3, rs
, N_KEY
| N_U8
| N_U16
| N_U32
, N_EQK
, N_EQK
);
15967 Rm
= inst
.operands
[2].reg
>> 1;
15969 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15970 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15971 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
15972 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
15973 inst
.instruction
|= (imm
> 2) << 7;
15974 inst
.instruction
|= Rm
<< 1;
15975 inst
.instruction
|= (imm
== 2 || imm
== 8);
15980 do_mve_vmlas (void)
15982 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
15983 struct neon_type_el et
15984 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
15986 if (inst
.operands
[2].reg
== REG_PC
)
15987 as_tsktsk (MVE_BAD_PC
);
15988 else if (inst
.operands
[2].reg
== REG_SP
)
15989 as_tsktsk (MVE_BAD_SP
);
15991 if (inst
.cond
> COND_ALWAYS
)
15992 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
15994 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
15996 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
15997 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
15998 inst
.instruction
|= neon_logbits (et
.size
) << 20;
15999 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16000 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16001 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16002 inst
.instruction
|= inst
.operands
[2].reg
;
16007 do_mve_vshll (void)
16009 struct neon_type_el et
16010 = neon_check_type (2, NS_QQI
, N_EQK
, N_S8
| N_U8
| N_S16
| N_U16
| N_KEY
);
16012 if (inst
.cond
> COND_ALWAYS
)
16013 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16015 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16017 int imm
= inst
.operands
[2].imm
;
16018 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
16019 _("immediate value out of range"));
16021 if ((unsigned)imm
== et
.size
)
16023 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16024 inst
.instruction
|= 0x110001;
16028 inst
.instruction
|= (et
.size
+ imm
) << 16;
16029 inst
.instruction
|= 0x800140;
16032 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16033 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16034 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16035 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16036 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16041 do_mve_vshlc (void)
16043 if (inst
.cond
> COND_ALWAYS
)
16044 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16046 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16048 if (inst
.operands
[1].reg
== REG_PC
)
16049 as_tsktsk (MVE_BAD_PC
);
16050 else if (inst
.operands
[1].reg
== REG_SP
)
16051 as_tsktsk (MVE_BAD_SP
);
16053 int imm
= inst
.operands
[2].imm
;
16054 constraint (imm
< 1 || imm
> 32, _("immediate value out of range"));
16056 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16057 inst
.instruction
|= (imm
& 0x1f) << 16;
16058 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16059 inst
.instruction
|= inst
.operands
[1].reg
;
16064 do_mve_vshrn (void)
16067 switch (inst
.instruction
)
16069 case M_MNEM_vshrnt
:
16070 case M_MNEM_vshrnb
:
16071 case M_MNEM_vrshrnt
:
16072 case M_MNEM_vrshrnb
:
16073 types
= N_I16
| N_I32
;
16075 case M_MNEM_vqshrnt
:
16076 case M_MNEM_vqshrnb
:
16077 case M_MNEM_vqrshrnt
:
16078 case M_MNEM_vqrshrnb
:
16079 types
= N_U16
| N_U32
| N_S16
| N_S32
;
16081 case M_MNEM_vqshrunt
:
16082 case M_MNEM_vqshrunb
:
16083 case M_MNEM_vqrshrunt
:
16084 case M_MNEM_vqrshrunb
:
16085 types
= N_S16
| N_S32
;
16091 struct neon_type_el et
= neon_check_type (2, NS_QQI
, N_EQK
, types
| N_KEY
);
16093 if (inst
.cond
> COND_ALWAYS
)
16094 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16096 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16098 unsigned Qd
= inst
.operands
[0].reg
;
16099 unsigned Qm
= inst
.operands
[1].reg
;
16100 unsigned imm
= inst
.operands
[2].imm
;
16101 constraint (imm
< 1 || ((unsigned) imm
) > (et
.size
/ 2),
16103 ? _("immediate operand expected in the range [1,8]")
16104 : _("immediate operand expected in the range [1,16]"));
16106 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16107 inst
.instruction
|= HI1 (Qd
) << 22;
16108 inst
.instruction
|= (et
.size
- imm
) << 16;
16109 inst
.instruction
|= LOW4 (Qd
) << 12;
16110 inst
.instruction
|= HI1 (Qm
) << 5;
16111 inst
.instruction
|= LOW4 (Qm
);
16116 do_mve_vqmovn (void)
16118 struct neon_type_el et
;
16119 if (inst
.instruction
== M_MNEM_vqmovnt
16120 || inst
.instruction
== M_MNEM_vqmovnb
)
16121 et
= neon_check_type (2, NS_QQ
, N_EQK
,
16122 N_U16
| N_U32
| N_S16
| N_S32
| N_KEY
);
16124 et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S16
| N_S32
| N_KEY
);
16126 if (inst
.cond
> COND_ALWAYS
)
16127 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16129 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16131 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16132 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16133 inst
.instruction
|= (et
.size
== 32) << 18;
16134 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16135 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16136 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16141 do_mve_vpsel (void)
16143 neon_select_shape (NS_QQQ
, NS_NULL
);
16145 if (inst
.cond
> COND_ALWAYS
)
16146 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16148 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16150 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16151 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16152 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16153 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16154 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16155 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16160 do_mve_vpnot (void)
16162 if (inst
.cond
> COND_ALWAYS
)
16163 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16165 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16169 do_mve_vmaxnma_vminnma (void)
16171 enum neon_shape rs
= neon_select_shape (NS_QQ
, NS_NULL
);
16172 struct neon_type_el et
16173 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
16175 if (inst
.cond
> COND_ALWAYS
)
16176 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16178 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16180 inst
.instruction
|= (et
.size
== 16) << 28;
16181 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16182 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16183 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16184 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16189 do_mve_vcmul (void)
16191 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
16192 struct neon_type_el et
16193 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_F_MVE
| N_KEY
);
16195 if (inst
.cond
> COND_ALWAYS
)
16196 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16198 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16200 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
16201 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
16202 _("immediate out of range"));
16204 if (et
.size
== 32 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
16205 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
16206 as_tsktsk (BAD_MVE_SRCDEST
);
16208 inst
.instruction
|= (et
.size
== 32) << 28;
16209 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16210 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16211 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16212 inst
.instruction
|= (rot
> 90) << 12;
16213 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16214 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16215 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16216 inst
.instruction
|= (rot
== 90 || rot
== 270);
16220 /* To handle the Low Overhead Loop instructions
16221 in Armv8.1-M Mainline and MVE. */
16225 unsigned long insn
= inst
.instruction
;
16227 inst
.instruction
= THUMB_OP32 (inst
.instruction
);
16229 if (insn
== T_MNEM_lctp
)
16232 set_pred_insn_type (MVE_OUTSIDE_PRED_INSN
);
16234 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16236 struct neon_type_el et
16237 = neon_check_type (2, NS_RR
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
16238 inst
.instruction
|= neon_logbits (et
.size
) << 20;
16245 constraint (!inst
.operands
[0].present
,
16247 /* fall through. */
16250 if (!inst
.operands
[0].present
)
16251 inst
.instruction
|= 1 << 21;
16253 v8_1_loop_reloc (TRUE
);
16258 v8_1_loop_reloc (FALSE
);
16259 /* fall through. */
16262 constraint (inst
.operands
[1].isreg
!= 1, BAD_ARGS
);
16264 if (insn
== T_MNEM_wlstp
|| insn
== T_MNEM_dlstp
)
16265 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
16266 else if (inst
.operands
[1].reg
== REG_PC
)
16267 as_tsktsk (MVE_BAD_PC
);
16268 if (inst
.operands
[1].reg
== REG_SP
)
16269 as_tsktsk (MVE_BAD_SP
);
16271 inst
.instruction
|= (inst
.operands
[1].reg
<< 16);
16281 do_vfp_nsyn_cmp (void)
16283 enum neon_shape rs
;
16284 if (!inst
.operands
[0].isreg
)
16291 constraint (inst
.operands
[2].present
, BAD_SYNTAX
);
16292 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
),
16296 if (inst
.operands
[1].isreg
)
16298 rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_NULL
);
16299 neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
| N_VFP
);
16301 if (rs
== NS_FF
|| rs
== NS_HH
)
16303 NEON_ENCODE (SINGLE
, inst
);
16304 do_vfp_sp_monadic ();
16308 NEON_ENCODE (DOUBLE
, inst
);
16309 do_vfp_dp_rd_rm ();
16314 rs
= neon_select_shape (NS_HI
, NS_FI
, NS_DI
, NS_NULL
);
16315 neon_check_type (2, rs
, N_F_ALL
| N_KEY
| N_VFP
, N_EQK
);
16317 switch (inst
.instruction
& 0x0fffffff)
16320 inst
.instruction
+= N_MNEM_vcmpz
- N_MNEM_vcmp
;
16323 inst
.instruction
+= N_MNEM_vcmpez
- N_MNEM_vcmpe
;
16329 if (rs
== NS_FI
|| rs
== NS_HI
)
16331 NEON_ENCODE (SINGLE
, inst
);
16332 do_vfp_sp_compare_z ();
16336 NEON_ENCODE (DOUBLE
, inst
);
16340 do_vfp_cond_or_thumb ();
16342 /* ARMv8.2 fp16 instruction. */
16343 if (rs
== NS_HI
|| rs
== NS_HH
)
16344 do_scalar_fp16_v82_encode ();
16348 nsyn_insert_sp (void)
16350 inst
.operands
[1] = inst
.operands
[0];
16351 memset (&inst
.operands
[0], '\0', sizeof (inst
.operands
[0]));
16352 inst
.operands
[0].reg
= REG_SP
;
16353 inst
.operands
[0].isreg
= 1;
16354 inst
.operands
[0].writeback
= 1;
16355 inst
.operands
[0].present
= 1;
16359 do_vfp_nsyn_push (void)
16363 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16364 _("register list must contain at least 1 and at most 16 "
16367 if (inst
.operands
[1].issingle
)
16368 do_vfp_nsyn_opcode ("fstmdbs");
16370 do_vfp_nsyn_opcode ("fstmdbd");
16374 do_vfp_nsyn_pop (void)
16378 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
16379 _("register list must contain at least 1 and at most 16 "
16382 if (inst
.operands
[1].issingle
)
16383 do_vfp_nsyn_opcode ("fldmias");
16385 do_vfp_nsyn_opcode ("fldmiad");
16388 /* Fix up Neon data-processing instructions, ORing in the correct bits for
16389 ARM mode or Thumb mode and moving the encoded bit 24 to bit 28. */
16392 neon_dp_fixup (struct arm_it
* insn
)
16394 unsigned int i
= insn
->instruction
;
16399 /* The U bit is at bit 24 by default. Move to bit 28 in Thumb mode. */
16410 insn
->instruction
= i
;
16414 mve_encode_qqr (int size
, int U
, int fp
)
16416 if (inst
.operands
[2].reg
== REG_SP
)
16417 as_tsktsk (MVE_BAD_SP
);
16418 else if (inst
.operands
[2].reg
== REG_PC
)
16419 as_tsktsk (MVE_BAD_PC
);
16424 if (((unsigned)inst
.instruction
) == 0xd00)
16425 inst
.instruction
= 0xee300f40;
16427 else if (((unsigned)inst
.instruction
) == 0x200d00)
16428 inst
.instruction
= 0xee301f40;
16430 else if (((unsigned)inst
.instruction
) == 0x1000d10)
16431 inst
.instruction
= 0xee310e60;
16433 /* Setting size which is 1 for F16 and 0 for F32. */
16434 inst
.instruction
|= (size
== 16) << 28;
16439 if (((unsigned)inst
.instruction
) == 0x800)
16440 inst
.instruction
= 0xee010f40;
16442 else if (((unsigned)inst
.instruction
) == 0x1000800)
16443 inst
.instruction
= 0xee011f40;
16445 else if (((unsigned)inst
.instruction
) == 0)
16446 inst
.instruction
= 0xee000f40;
16448 else if (((unsigned)inst
.instruction
) == 0x200)
16449 inst
.instruction
= 0xee001f40;
16451 else if (((unsigned)inst
.instruction
) == 0x900)
16452 inst
.instruction
= 0xee010e40;
16454 else if (((unsigned)inst
.instruction
) == 0x910)
16455 inst
.instruction
= 0xee011e60;
16457 else if (((unsigned)inst
.instruction
) == 0x10)
16458 inst
.instruction
= 0xee000f60;
16460 else if (((unsigned)inst
.instruction
) == 0x210)
16461 inst
.instruction
= 0xee001f60;
16463 else if (((unsigned)inst
.instruction
) == 0x3000b10)
16464 inst
.instruction
= 0xee000e40;
16466 else if (((unsigned)inst
.instruction
) == 0x0000b00)
16467 inst
.instruction
= 0xee010e60;
16469 else if (((unsigned)inst
.instruction
) == 0x1000b00)
16470 inst
.instruction
= 0xfe010e60;
16473 inst
.instruction
|= U
<< 28;
16475 /* Setting bits for size. */
16476 inst
.instruction
|= neon_logbits (size
) << 20;
16478 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16479 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16480 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16481 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16482 inst
.instruction
|= inst
.operands
[2].reg
;
16487 mve_encode_rqq (unsigned bit28
, unsigned size
)
16489 inst
.instruction
|= bit28
<< 28;
16490 inst
.instruction
|= neon_logbits (size
) << 20;
16491 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16492 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16493 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16494 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16495 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16500 mve_encode_qqq (int ubit
, int size
)
16503 inst
.instruction
|= (ubit
!= 0) << 28;
16504 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16505 inst
.instruction
|= neon_logbits (size
) << 20;
16506 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16507 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16508 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16509 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16510 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16516 mve_encode_rq (unsigned bit28
, unsigned size
)
16518 inst
.instruction
|= bit28
<< 28;
16519 inst
.instruction
|= neon_logbits (size
) << 18;
16520 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16521 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16526 mve_encode_rrqq (unsigned U
, unsigned size
)
16528 constraint (inst
.operands
[3].reg
> 14, MVE_BAD_QREG
);
16530 inst
.instruction
|= U
<< 28;
16531 inst
.instruction
|= (inst
.operands
[1].reg
>> 1) << 20;
16532 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
) << 16;
16533 inst
.instruction
|= (size
== 32) << 16;
16534 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
16535 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 7;
16536 inst
.instruction
|= inst
.operands
[3].reg
;
16540 /* Encode insns with bit pattern:
16542 |28/24|23|22 |21 20|19 16|15 12|11 8|7|6|5|4|3 0|
16543 | U |x |D |size | Rn | Rd |x x x x|N|Q|M|x| Rm |
16545 SIZE is passed in bits. -1 means size field isn't changed, in case it has a
16546 different meaning for some instruction. */
16549 neon_three_same (int isquad
, int ubit
, int size
)
16551 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16552 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16553 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
16554 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
16555 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
16556 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
16557 inst
.instruction
|= (isquad
!= 0) << 6;
16558 inst
.instruction
|= (ubit
!= 0) << 24;
16560 inst
.instruction
|= neon_logbits (size
) << 20;
16562 neon_dp_fixup (&inst
);
16565 /* Encode instructions of the form:
16567 |28/24|23|22|21 20|19 18|17 16|15 12|11 7|6|5|4|3 0|
16568 | U |x |D |x x |size |x x | Rd |x x x x x|Q|M|x| Rm |
16570 Don't write size if SIZE == -1. */
16573 neon_two_same (int qbit
, int ubit
, int size
)
16575 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16576 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16577 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16578 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16579 inst
.instruction
|= (qbit
!= 0) << 6;
16580 inst
.instruction
|= (ubit
!= 0) << 24;
16583 inst
.instruction
|= neon_logbits (size
) << 18;
16585 neon_dp_fixup (&inst
);
16588 enum vfp_or_neon_is_neon_bits
16591 NEON_CHECK_ARCH
= 2,
16592 NEON_CHECK_ARCH8
= 4
16595 /* Call this function if an instruction which may have belonged to the VFP or
16596 Neon instruction sets, but turned out to be a Neon instruction (due to the
16597 operand types involved, etc.). We have to check and/or fix-up a couple of
16600 - Make sure the user hasn't attempted to make a Neon instruction
16602 - Alter the value in the condition code field if necessary.
16603 - Make sure that the arch supports Neon instructions.
16605 Which of these operations take place depends on bits from enum
16606 vfp_or_neon_is_neon_bits.
16608 WARNING: This function has side effects! If NEON_CHECK_CC is used and the
16609 current instruction's condition is COND_ALWAYS, the condition field is
16610 changed to inst.uncond_value. This is necessary because instructions shared
16611 between VFP and Neon may be conditional for the VFP variants only, and the
16612 unconditional Neon version must have, e.g., 0xF in the condition field. */
16615 vfp_or_neon_is_neon (unsigned check
)
16617 /* Conditions are always legal in Thumb mode (IT blocks). */
16618 if (!thumb_mode
&& (check
& NEON_CHECK_CC
))
16620 if (inst
.cond
!= COND_ALWAYS
)
16622 first_error (_(BAD_COND
));
16625 if (inst
.uncond_value
!= -1)
16626 inst
.instruction
|= inst
.uncond_value
<< 28;
16630 if (((check
& NEON_CHECK_ARCH
) && !mark_feature_used (&fpu_neon_ext_v1
))
16631 || ((check
& NEON_CHECK_ARCH8
)
16632 && !mark_feature_used (&fpu_neon_ext_armv8
)))
16634 first_error (_(BAD_FPU
));
16642 /* Return TRUE if the SIMD instruction is available for the current
16643 cpu_variant. FP is set to TRUE if this is a SIMD floating-point
16644 instruction. CHECK contains th. CHECK contains the set of bits to pass to
16645 vfp_or_neon_is_neon for the NEON specific checks. */
16648 check_simd_pred_availability (int fp
, unsigned check
)
16650 if (inst
.cond
> COND_ALWAYS
)
16652 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16654 inst
.error
= BAD_FPU
;
16657 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
16659 else if (inst
.cond
< COND_ALWAYS
)
16661 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16662 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16663 else if (vfp_or_neon_is_neon (check
) == FAIL
)
16668 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fp
? mve_fp_ext
: mve_ext
)
16669 && vfp_or_neon_is_neon (check
) == FAIL
)
16672 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16673 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
16678 /* Neon instruction encoders, in approximate order of appearance. */
16681 do_neon_dyadic_i_su (void)
16683 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16686 enum neon_shape rs
;
16687 struct neon_type_el et
;
16688 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16689 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16691 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16693 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_32
| N_KEY
);
16697 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16699 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16703 do_neon_dyadic_i64_su (void)
16705 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
16707 enum neon_shape rs
;
16708 struct neon_type_el et
;
16709 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16711 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16712 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16716 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16717 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16720 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
16722 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16726 neon_imm_shift (int write_ubit
, int uval
, int isquad
, struct neon_type_el et
,
16729 unsigned size
= et
.size
>> 3;
16730 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16731 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16732 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
16733 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
16734 inst
.instruction
|= (isquad
!= 0) << 6;
16735 inst
.instruction
|= immbits
<< 16;
16736 inst
.instruction
|= (size
>> 3) << 7;
16737 inst
.instruction
|= (size
& 0x7) << 19;
16739 inst
.instruction
|= (uval
!= 0) << 24;
16741 neon_dp_fixup (&inst
);
16747 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16750 if (!inst
.operands
[2].isreg
)
16752 enum neon_shape rs
;
16753 struct neon_type_el et
;
16754 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16756 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16757 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_MVE
);
16761 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16762 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_I_ALL
);
16764 int imm
= inst
.operands
[2].imm
;
16766 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16767 _("immediate out of range for shift"));
16768 NEON_ENCODE (IMMED
, inst
);
16769 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
16773 enum neon_shape rs
;
16774 struct neon_type_el et
;
16775 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16777 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16778 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16782 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16783 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16789 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16790 _("invalid instruction shape"));
16791 if (inst
.operands
[2].reg
== REG_SP
)
16792 as_tsktsk (MVE_BAD_SP
);
16793 else if (inst
.operands
[2].reg
== REG_PC
)
16794 as_tsktsk (MVE_BAD_PC
);
16796 inst
.instruction
= 0xee311e60;
16797 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16798 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16799 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16800 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16801 inst
.instruction
|= inst
.operands
[2].reg
;
16808 /* VSHL/VQSHL 3-register variants have syntax such as:
16810 whereas other 3-register operations encoded by neon_three_same have
16813 (i.e. with Dn & Dm reversed). Swap operands[1].reg and
16814 operands[2].reg here. */
16815 tmp
= inst
.operands
[2].reg
;
16816 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16817 inst
.operands
[1].reg
= tmp
;
16818 NEON_ENCODE (INTEGER
, inst
);
16819 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16825 do_neon_qshl (void)
16827 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16830 if (!inst
.operands
[2].isreg
)
16832 enum neon_shape rs
;
16833 struct neon_type_el et
;
16834 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16836 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
16837 et
= neon_check_type (2, rs
, N_EQK
, N_KEY
| N_SU_MVE
);
16841 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
16842 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
16844 int imm
= inst
.operands
[2].imm
;
16846 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
16847 _("immediate out of range for shift"));
16848 NEON_ENCODE (IMMED
, inst
);
16849 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
, imm
);
16853 enum neon_shape rs
;
16854 struct neon_type_el et
;
16856 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16858 rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
16859 et
= neon_check_type (3, rs
, N_EQK
, N_SU_MVE
| N_KEY
, N_EQK
| N_EQK
);
16863 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16864 et
= neon_check_type (3, rs
, N_EQK
, N_SU_ALL
| N_KEY
, N_EQK
| N_SGN
);
16869 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16870 _("invalid instruction shape"));
16871 if (inst
.operands
[2].reg
== REG_SP
)
16872 as_tsktsk (MVE_BAD_SP
);
16873 else if (inst
.operands
[2].reg
== REG_PC
)
16874 as_tsktsk (MVE_BAD_PC
);
16876 inst
.instruction
= 0xee311ee0;
16877 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16878 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16879 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16880 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16881 inst
.instruction
|= inst
.operands
[2].reg
;
16888 /* See note in do_neon_shl. */
16889 tmp
= inst
.operands
[2].reg
;
16890 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16891 inst
.operands
[1].reg
= tmp
;
16892 NEON_ENCODE (INTEGER
, inst
);
16893 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16899 do_neon_rshl (void)
16901 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
16904 enum neon_shape rs
;
16905 struct neon_type_el et
;
16906 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
16908 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
16909 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
16913 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
16914 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_ALL
| N_KEY
);
16921 if (inst
.operands
[2].reg
== REG_PC
)
16922 as_tsktsk (MVE_BAD_PC
);
16923 else if (inst
.operands
[2].reg
== REG_SP
)
16924 as_tsktsk (MVE_BAD_SP
);
16926 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
16927 _("invalid instruction shape"));
16929 if (inst
.instruction
== 0x0000510)
16930 /* We are dealing with vqrshl. */
16931 inst
.instruction
= 0xee331ee0;
16933 /* We are dealing with vrshl. */
16934 inst
.instruction
= 0xee331e60;
16936 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
16937 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
16938 inst
.instruction
|= neon_logbits (et
.size
) << 18;
16939 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
16940 inst
.instruction
|= inst
.operands
[2].reg
;
16945 tmp
= inst
.operands
[2].reg
;
16946 inst
.operands
[2].reg
= inst
.operands
[1].reg
;
16947 inst
.operands
[1].reg
= tmp
;
16948 neon_three_same (neon_quad (rs
), et
.type
== NT_unsigned
, et
.size
);
16953 neon_cmode_for_logic_imm (unsigned immediate
, unsigned *immbits
, int size
)
16955 /* Handle .I8 pseudo-instructions. */
16958 /* Unfortunately, this will make everything apart from zero out-of-range.
16959 FIXME is this the intended semantics? There doesn't seem much point in
16960 accepting .I8 if so. */
16961 immediate
|= immediate
<< 8;
16967 if (immediate
== (immediate
& 0x000000ff))
16969 *immbits
= immediate
;
16972 else if (immediate
== (immediate
& 0x0000ff00))
16974 *immbits
= immediate
>> 8;
16977 else if (immediate
== (immediate
& 0x00ff0000))
16979 *immbits
= immediate
>> 16;
16982 else if (immediate
== (immediate
& 0xff000000))
16984 *immbits
= immediate
>> 24;
16987 if ((immediate
& 0xffff) != (immediate
>> 16))
16988 goto bad_immediate
;
16989 immediate
&= 0xffff;
16992 if (immediate
== (immediate
& 0x000000ff))
16994 *immbits
= immediate
;
16997 else if (immediate
== (immediate
& 0x0000ff00))
16999 *immbits
= immediate
>> 8;
17004 first_error (_("immediate value out of range"));
17009 do_neon_logic (void)
17011 if (inst
.operands
[2].present
&& inst
.operands
[2].isreg
)
17013 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17015 && !check_simd_pred_availability (FALSE
,
17016 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17018 else if (rs
!= NS_QQQ
17019 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17020 first_error (BAD_FPU
);
17022 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17023 /* U bit and size field were set as part of the bitmask. */
17024 NEON_ENCODE (INTEGER
, inst
);
17025 neon_three_same (neon_quad (rs
), 0, -1);
17029 const int three_ops_form
= (inst
.operands
[2].present
17030 && !inst
.operands
[2].isreg
);
17031 const int immoperand
= (three_ops_form
? 2 : 1);
17032 enum neon_shape rs
= (three_ops_form
17033 ? neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
)
17034 : neon_select_shape (NS_DI
, NS_QI
, NS_NULL
));
17035 /* Because neon_select_shape makes the second operand a copy of the first
17036 if the second operand is not present. */
17038 && !check_simd_pred_availability (FALSE
,
17039 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17041 else if (rs
!= NS_QQI
17042 && !ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
))
17043 first_error (BAD_FPU
);
17045 struct neon_type_el et
;
17046 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17047 et
= neon_check_type (2, rs
, N_I32
| N_I16
| N_KEY
, N_EQK
);
17049 et
= neon_check_type (2, rs
, N_I8
| N_I16
| N_I32
| N_I64
| N_F32
17052 if (et
.type
== NT_invtype
)
17054 enum neon_opc opcode
= (enum neon_opc
) inst
.instruction
& 0x0fffffff;
17059 if (three_ops_form
)
17060 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
17061 _("first and second operands shall be the same register"));
17063 NEON_ENCODE (IMMED
, inst
);
17065 immbits
= inst
.operands
[immoperand
].imm
;
17068 /* .i64 is a pseudo-op, so the immediate must be a repeating
17070 if (immbits
!= (inst
.operands
[immoperand
].regisimm
?
17071 inst
.operands
[immoperand
].reg
: 0))
17073 /* Set immbits to an invalid constant. */
17074 immbits
= 0xdeadbeef;
17081 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17085 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17089 /* Pseudo-instruction for VBIC. */
17090 neon_invert_size (&immbits
, 0, et
.size
);
17091 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17095 /* Pseudo-instruction for VORR. */
17096 neon_invert_size (&immbits
, 0, et
.size
);
17097 cmode
= neon_cmode_for_logic_imm (immbits
, &immbits
, et
.size
);
17107 inst
.instruction
|= neon_quad (rs
) << 6;
17108 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17109 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17110 inst
.instruction
|= cmode
<< 8;
17111 neon_write_immbits (immbits
);
17113 neon_dp_fixup (&inst
);
17118 do_neon_bitfield (void)
17120 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17121 neon_check_type (3, rs
, N_IGNORE_TYPE
);
17122 neon_three_same (neon_quad (rs
), 0, -1);
17126 neon_dyadic_misc (enum neon_el_type ubit_meaning
, unsigned types
,
17129 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17130 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
| destbits
, N_EQK
,
17132 if (et
.type
== NT_float
)
17134 NEON_ENCODE (FLOAT
, inst
);
17136 mve_encode_qqr (et
.size
, 0, 1);
17138 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
17142 NEON_ENCODE (INTEGER
, inst
);
17144 mve_encode_qqr (et
.size
, et
.type
== ubit_meaning
, 0);
17146 neon_three_same (neon_quad (rs
), et
.type
== ubit_meaning
, et
.size
);
17152 do_neon_dyadic_if_su_d (void)
17154 /* This version only allow D registers, but that constraint is enforced during
17155 operand parsing so we don't need to do anything extra here. */
17156 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17160 do_neon_dyadic_if_i_d (void)
17162 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17163 affected if we specify unsigned args. */
17164 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17168 do_mve_vstr_vldr_QI (int size
, int elsize
, int load
)
17170 constraint (size
< 32, BAD_ADDR_MODE
);
17171 constraint (size
!= elsize
, BAD_EL_TYPE
);
17172 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
17173 constraint (!inst
.operands
[1].preind
, BAD_ADDR_MODE
);
17174 constraint (load
&& inst
.operands
[0].reg
== inst
.operands
[1].reg
,
17175 _("destination register and offset register may not be the"
17178 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17185 constraint ((imm
% (size
/ 8) != 0)
17186 || imm
> (0x7f << neon_logbits (size
)),
17187 (size
== 32) ? _("immediate must be a multiple of 4 in the"
17188 " range of +/-[0,508]")
17189 : _("immediate must be a multiple of 8 in the"
17190 " range of +/-[0,1016]"));
17191 inst
.instruction
|= 0x11 << 24;
17192 inst
.instruction
|= add
<< 23;
17193 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17194 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17195 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17196 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17197 inst
.instruction
|= 1 << 12;
17198 inst
.instruction
|= (size
== 64) << 8;
17199 inst
.instruction
&= 0xffffff00;
17200 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17201 inst
.instruction
|= imm
>> neon_logbits (size
);
17205 do_mve_vstr_vldr_RQ (int size
, int elsize
, int load
)
17207 unsigned os
= inst
.operands
[1].imm
>> 5;
17208 constraint (os
!= 0 && size
== 8,
17209 _("can not shift offsets when accessing less than half-word"));
17210 constraint (os
&& os
!= neon_logbits (size
),
17211 _("shift immediate must be 1, 2 or 3 for half-word, word"
17212 " or double-word accesses respectively"));
17213 if (inst
.operands
[1].reg
== REG_PC
)
17214 as_tsktsk (MVE_BAD_PC
);
17219 constraint (elsize
>= 64, BAD_EL_TYPE
);
17222 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17226 constraint (elsize
!= size
, BAD_EL_TYPE
);
17231 constraint (inst
.operands
[1].writeback
|| !inst
.operands
[1].preind
,
17235 constraint (inst
.operands
[0].reg
== (inst
.operands
[1].imm
& 0x1f),
17236 _("destination register and offset register may not be"
17238 constraint (size
== elsize
&& inst
.vectype
.el
[0].type
!= NT_unsigned
,
17240 constraint (inst
.vectype
.el
[0].type
!= NT_unsigned
17241 && inst
.vectype
.el
[0].type
!= NT_signed
, BAD_EL_TYPE
);
17242 inst
.instruction
|= (inst
.vectype
.el
[0].type
== NT_unsigned
) << 28;
17246 constraint (inst
.vectype
.el
[0].type
!= NT_untyped
, BAD_EL_TYPE
);
17249 inst
.instruction
|= 1 << 23;
17250 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17251 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17252 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17253 inst
.instruction
|= neon_logbits (elsize
) << 7;
17254 inst
.instruction
|= HI1 (inst
.operands
[1].imm
) << 5;
17255 inst
.instruction
|= LOW4 (inst
.operands
[1].imm
);
17256 inst
.instruction
|= !!os
;
17260 do_mve_vstr_vldr_RI (int size
, int elsize
, int load
)
17262 enum neon_el_type type
= inst
.vectype
.el
[0].type
;
17264 constraint (size
>= 64, BAD_ADDR_MODE
);
17268 constraint (elsize
< 16 || elsize
>= 64, BAD_EL_TYPE
);
17271 constraint (elsize
!= size
, BAD_EL_TYPE
);
17278 constraint (elsize
!= size
&& type
!= NT_unsigned
17279 && type
!= NT_signed
, BAD_EL_TYPE
);
17283 constraint (elsize
!= size
&& type
!= NT_untyped
, BAD_EL_TYPE
);
17286 int imm
= inst
.relocs
[0].exp
.X_add_number
;
17294 if ((imm
% (size
/ 8) != 0) || imm
> (0x7f << neon_logbits (size
)))
17299 constraint (1, _("immediate must be in the range of +/-[0,127]"));
17302 constraint (1, _("immediate must be a multiple of 2 in the"
17303 " range of +/-[0,254]"));
17306 constraint (1, _("immediate must be a multiple of 4 in the"
17307 " range of +/-[0,508]"));
17312 if (size
!= elsize
)
17314 constraint (inst
.operands
[1].reg
> 7, BAD_HIREG
);
17315 constraint (inst
.operands
[0].reg
> 14,
17316 _("MVE vector register in the range [Q0..Q7] expected"));
17317 inst
.instruction
|= (load
&& type
== NT_unsigned
) << 28;
17318 inst
.instruction
|= (size
== 16) << 19;
17319 inst
.instruction
|= neon_logbits (elsize
) << 7;
17323 if (inst
.operands
[1].reg
== REG_PC
)
17324 as_tsktsk (MVE_BAD_PC
);
17325 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17326 as_tsktsk (MVE_BAD_SP
);
17327 inst
.instruction
|= 1 << 12;
17328 inst
.instruction
|= neon_logbits (size
) << 7;
17330 inst
.instruction
|= inst
.operands
[1].preind
<< 24;
17331 inst
.instruction
|= add
<< 23;
17332 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17333 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17334 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17335 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17336 inst
.instruction
&= 0xffffff80;
17337 inst
.instruction
|= imm
>> neon_logbits (size
);
17342 do_mve_vstr_vldr (void)
17347 if (inst
.cond
> COND_ALWAYS
)
17348 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17350 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17352 switch (inst
.instruction
)
17359 /* fall through. */
17365 /* fall through. */
17371 /* fall through. */
17377 /* fall through. */
17382 unsigned elsize
= inst
.vectype
.el
[0].size
;
17384 if (inst
.operands
[1].isquad
)
17386 /* We are dealing with [Q, imm]{!} cases. */
17387 do_mve_vstr_vldr_QI (size
, elsize
, load
);
17391 if (inst
.operands
[1].immisreg
== 2)
17393 /* We are dealing with [R, Q, {UXTW #os}] cases. */
17394 do_mve_vstr_vldr_RQ (size
, elsize
, load
);
17396 else if (!inst
.operands
[1].immisreg
)
17398 /* We are dealing with [R, Imm]{!}/[R], Imm cases. */
17399 do_mve_vstr_vldr_RI (size
, elsize
, load
);
17402 constraint (1, BAD_ADDR_MODE
);
17409 do_mve_vst_vld (void)
17411 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17414 constraint (!inst
.operands
[1].preind
|| inst
.relocs
[0].exp
.X_add_symbol
!= 0
17415 || inst
.relocs
[0].exp
.X_add_number
!= 0
17416 || inst
.operands
[1].immisreg
!= 0,
17418 constraint (inst
.vectype
.el
[0].size
> 32, BAD_EL_TYPE
);
17419 if (inst
.operands
[1].reg
== REG_PC
)
17420 as_tsktsk (MVE_BAD_PC
);
17421 else if (inst
.operands
[1].reg
== REG_SP
&& inst
.operands
[1].writeback
)
17422 as_tsktsk (MVE_BAD_SP
);
17425 /* These instructions are one of the "exceptions" mentioned in
17426 handle_pred_state. They are MVE instructions that are not VPT compatible
17427 and do not accept a VPT code, thus appending such a code is a syntax
17429 if (inst
.cond
> COND_ALWAYS
)
17430 first_error (BAD_SYNTAX
);
17431 /* If we append a scalar condition code we can set this to
17432 MVE_OUTSIDE_PRED_INSN as it will also lead to a syntax error. */
17433 else if (inst
.cond
< COND_ALWAYS
)
17434 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17436 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
17438 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17439 inst
.instruction
|= inst
.operands
[1].writeback
<< 21;
17440 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
17441 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17442 inst
.instruction
|= neon_logbits (inst
.vectype
.el
[0].size
) << 7;
17447 do_mve_vaddlv (void)
17449 enum neon_shape rs
= neon_select_shape (NS_RRQ
, NS_NULL
);
17450 struct neon_type_el et
17451 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S32
| N_U32
| N_KEY
);
17453 if (et
.type
== NT_invtype
)
17454 first_error (BAD_EL_TYPE
);
17456 if (inst
.cond
> COND_ALWAYS
)
17457 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17459 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17461 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17463 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
17464 inst
.instruction
|= inst
.operands
[1].reg
<< 19;
17465 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
17466 inst
.instruction
|= inst
.operands
[2].reg
;
17471 do_neon_dyadic_if_su (void)
17473 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17474 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
17477 constraint ((inst
.instruction
== ((unsigned) N_MNEM_vmax
)
17478 || inst
.instruction
== ((unsigned) N_MNEM_vmin
))
17479 && et
.type
== NT_float
17480 && !ARM_CPU_HAS_FEATURE (cpu_variant
,fpu_neon_ext_v1
), BAD_FPU
);
17482 if (!check_simd_pred_availability (et
.type
== NT_float
,
17483 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17486 neon_dyadic_misc (NT_unsigned
, N_SUF_32
, 0);
17490 do_neon_addsub_if_i (void)
17492 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1xd
)
17493 && try_vfp_nsyn (3, do_vfp_nsyn_add_sub
) == SUCCESS
)
17496 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
17497 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
,
17498 N_EQK
, N_IF_32
| N_I64
| N_KEY
);
17500 constraint (rs
== NS_QQR
&& et
.size
== 64, BAD_FPU
);
17501 /* If we are parsing Q registers and the element types match MVE, which NEON
17502 also supports, then we must check whether this is an instruction that can
17503 be used by both MVE/NEON. This distinction can be made based on whether
17504 they are predicated or not. */
17505 if ((rs
== NS_QQQ
|| rs
== NS_QQR
) && et
.size
!= 64)
17507 if (!check_simd_pred_availability (et
.type
== NT_float
,
17508 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17513 /* If they are either in a D register or are using an unsupported. */
17515 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
17519 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17520 affected if we specify unsigned args. */
17521 neon_dyadic_misc (NT_untyped
, N_IF_32
| N_I64
, 0);
17524 /* Swaps operands 1 and 2. If operand 1 (optional arg) was omitted, we want the
17526 V<op> A,B (A is operand 0, B is operand 2)
17531 so handle that case specially. */
17534 neon_exchange_operands (void)
17536 if (inst
.operands
[1].present
)
17538 void *scratch
= xmalloc (sizeof (inst
.operands
[0]));
17540 /* Swap operands[1] and operands[2]. */
17541 memcpy (scratch
, &inst
.operands
[1], sizeof (inst
.operands
[0]));
17542 inst
.operands
[1] = inst
.operands
[2];
17543 memcpy (&inst
.operands
[2], scratch
, sizeof (inst
.operands
[0]));
17548 inst
.operands
[1] = inst
.operands
[2];
17549 inst
.operands
[2] = inst
.operands
[0];
17554 neon_compare (unsigned regtypes
, unsigned immtypes
, int invert
)
17556 if (inst
.operands
[2].isreg
)
17559 neon_exchange_operands ();
17560 neon_dyadic_misc (NT_unsigned
, regtypes
, N_SIZ
);
17564 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
17565 struct neon_type_el et
= neon_check_type (2, rs
,
17566 N_EQK
| N_SIZ
, immtypes
| N_KEY
);
17568 NEON_ENCODE (IMMED
, inst
);
17569 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17570 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17571 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
17572 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
17573 inst
.instruction
|= neon_quad (rs
) << 6;
17574 inst
.instruction
|= (et
.type
== NT_float
) << 10;
17575 inst
.instruction
|= neon_logbits (et
.size
) << 18;
17577 neon_dp_fixup (&inst
);
17584 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, FALSE
);
17588 do_neon_cmp_inv (void)
17590 neon_compare (N_SUF_32
, N_S_32
| N_F_16_32
, TRUE
);
17596 neon_compare (N_IF_32
, N_IF_32
, FALSE
);
17599 /* For multiply instructions, we have the possibility of 16-bit or 32-bit
17600 scalars, which are encoded in 5 bits, M : Rm.
17601 For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
17602 M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
17605 Dot Product instructions are similar to multiply instructions except elsize
17606 should always be 32.
17608 This function translates SCALAR, which is GAS's internal encoding of indexed
17609 scalar register, to raw encoding. There is also register and index range
17610 check based on ELSIZE. */
17613 neon_scalar_for_mul (unsigned scalar
, unsigned elsize
)
17615 unsigned regno
= NEON_SCALAR_REG (scalar
);
17616 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
17621 if (regno
> 7 || elno
> 3)
17623 return regno
| (elno
<< 3);
17626 if (regno
> 15 || elno
> 1)
17628 return regno
| (elno
<< 4);
17632 first_error (_("scalar out of range for multiply instruction"));
17638 /* Encode multiply / multiply-accumulate scalar instructions. */
17641 neon_mul_mac (struct neon_type_el et
, int ubit
)
17645 /* Give a more helpful error message if we have an invalid type. */
17646 if (et
.type
== NT_invtype
)
17649 scalar
= neon_scalar_for_mul (inst
.operands
[2].reg
, et
.size
);
17650 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17651 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17652 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17653 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
17654 inst
.instruction
|= LOW4 (scalar
);
17655 inst
.instruction
|= HI1 (scalar
) << 5;
17656 inst
.instruction
|= (et
.type
== NT_float
) << 8;
17657 inst
.instruction
|= neon_logbits (et
.size
) << 20;
17658 inst
.instruction
|= (ubit
!= 0) << 24;
17660 neon_dp_fixup (&inst
);
17664 do_neon_mac_maybe_scalar (void)
17666 if (try_vfp_nsyn (3, do_vfp_nsyn_mla_mls
) == SUCCESS
)
17669 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17672 if (inst
.operands
[2].isscalar
)
17674 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17675 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17676 struct neon_type_el et
= neon_check_type (3, rs
,
17677 N_EQK
, N_EQK
, N_I16
| N_I32
| N_F_16_32
| N_KEY
);
17678 NEON_ENCODE (SCALAR
, inst
);
17679 neon_mul_mac (et
, neon_quad (rs
));
17681 else if (!inst
.operands
[2].isvec
)
17683 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17685 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17686 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17688 neon_dyadic_misc (NT_unsigned
, N_SU_MVE
, 0);
17692 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17693 /* The "untyped" case can't happen. Do this to stop the "U" bit being
17694 affected if we specify unsigned args. */
17695 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17700 do_neon_fmac (void)
17702 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_fma
)
17703 && try_vfp_nsyn (3, do_vfp_nsyn_fma_fms
) == SUCCESS
)
17706 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17709 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
17711 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17712 struct neon_type_el et
= neon_check_type (3, rs
, N_F_MVE
| N_KEY
, N_EQK
,
17717 if (inst
.operands
[2].reg
== REG_SP
)
17718 as_tsktsk (MVE_BAD_SP
);
17719 else if (inst
.operands
[2].reg
== REG_PC
)
17720 as_tsktsk (MVE_BAD_PC
);
17722 inst
.instruction
= 0xee310e40;
17723 inst
.instruction
|= (et
.size
== 16) << 28;
17724 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
17725 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
17726 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
17727 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 6;
17728 inst
.instruction
|= inst
.operands
[2].reg
;
17735 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17738 neon_dyadic_misc (NT_untyped
, N_IF_32
, 0);
17744 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17745 struct neon_type_el et
= neon_check_type (3, rs
,
17746 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17747 neon_three_same (neon_quad (rs
), 0, et
.size
);
17750 /* VMUL with 3 registers allows the P8 type. The scalar version supports the
17751 same types as the MAC equivalents. The polynomial type for this instruction
17752 is encoded the same as the integer type. */
17757 if (try_vfp_nsyn (3, do_vfp_nsyn_mul
) == SUCCESS
)
17760 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
17763 if (inst
.operands
[2].isscalar
)
17765 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17766 do_neon_mac_maybe_scalar ();
17770 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17772 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17773 struct neon_type_el et
17774 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_I_MVE
| N_F_MVE
| N_KEY
);
17775 if (et
.type
== NT_float
)
17776 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
),
17779 neon_dyadic_misc (NT_float
, N_I_MVE
| N_F_MVE
, 0);
17783 constraint (!inst
.operands
[2].isvec
, BAD_FPU
);
17784 neon_dyadic_misc (NT_poly
,
17785 N_I8
| N_I16
| N_I32
| N_F16
| N_F32
| N_P8
, 0);
17791 do_neon_qdmulh (void)
17793 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
17796 if (inst
.operands
[2].isscalar
)
17798 constraint (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
17799 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
17800 struct neon_type_el et
= neon_check_type (3, rs
,
17801 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17802 NEON_ENCODE (SCALAR
, inst
);
17803 neon_mul_mac (et
, neon_quad (rs
));
17807 enum neon_shape rs
;
17808 struct neon_type_el et
;
17809 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
17811 rs
= neon_select_shape (NS_QQR
, NS_QQQ
, NS_NULL
);
17812 et
= neon_check_type (3, rs
,
17813 N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17817 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
17818 et
= neon_check_type (3, rs
,
17819 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17822 NEON_ENCODE (INTEGER
, inst
);
17824 mve_encode_qqr (et
.size
, 0, 0);
17826 /* The U bit (rounding) comes from bit mask. */
17827 neon_three_same (neon_quad (rs
), 0, et
.size
);
17832 do_mve_vaddv (void)
17834 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
17835 struct neon_type_el et
17836 = neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
17838 if (et
.type
== NT_invtype
)
17839 first_error (BAD_EL_TYPE
);
17841 if (inst
.cond
> COND_ALWAYS
)
17842 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17844 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17846 constraint (inst
.operands
[1].reg
> 14, MVE_BAD_QREG
);
17848 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
17852 do_mve_vhcadd (void)
17854 enum neon_shape rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
17855 struct neon_type_el et
17856 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17858 if (inst
.cond
> COND_ALWAYS
)
17859 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17861 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17863 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
17864 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
17866 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
17867 as_tsktsk (_("Warning: 32-bit element size and same first and third "
17868 "operand makes instruction UNPREDICTABLE"));
17870 mve_encode_qqq (0, et
.size
);
17871 inst
.instruction
|= (rot
== 270) << 12;
17876 do_mve_vqdmull (void)
17878 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_QQR
, NS_NULL
);
17879 struct neon_type_el et
17880 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
17883 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
17884 || (rs
== NS_QQQ
&& inst
.operands
[0].reg
== inst
.operands
[2].reg
)))
17885 as_tsktsk (BAD_MVE_SRCDEST
);
17887 if (inst
.cond
> COND_ALWAYS
)
17888 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17890 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17894 mve_encode_qqq (et
.size
== 32, 64);
17895 inst
.instruction
|= 1;
17899 mve_encode_qqr (64, et
.size
== 32, 0);
17900 inst
.instruction
|= 0x3 << 5;
17907 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17908 struct neon_type_el et
17909 = neon_check_type (3, rs
, N_KEY
| N_I32
, N_EQK
, N_EQK
);
17911 if (et
.type
== NT_invtype
)
17912 first_error (BAD_EL_TYPE
);
17914 if (inst
.cond
> COND_ALWAYS
)
17915 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17917 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17919 mve_encode_qqq (0, 64);
17923 do_mve_vbrsr (void)
17925 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17926 struct neon_type_el et
17927 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
17929 if (inst
.cond
> COND_ALWAYS
)
17930 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17932 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17934 mve_encode_qqr (et
.size
, 0, 0);
17940 neon_check_type (3, NS_QQQ
, N_EQK
, N_EQK
, N_I32
| N_KEY
);
17942 if (inst
.cond
> COND_ALWAYS
)
17943 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17945 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17947 mve_encode_qqq (1, 64);
17951 do_mve_vmulh (void)
17953 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17954 struct neon_type_el et
17955 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
17957 if (inst
.cond
> COND_ALWAYS
)
17958 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17960 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17962 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
17966 do_mve_vqdmlah (void)
17968 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
17969 struct neon_type_el et
17970 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
17972 if (inst
.cond
> COND_ALWAYS
)
17973 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17975 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17977 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
17981 do_mve_vqdmladh (void)
17983 enum neon_shape rs
= neon_select_shape (NS_QQQ
, NS_NULL
);
17984 struct neon_type_el et
17985 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
17987 if (inst
.cond
> COND_ALWAYS
)
17988 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
17990 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
17992 mve_encode_qqq (0, et
.size
);
17997 do_mve_vmull (void)
18000 enum neon_shape rs
= neon_select_shape (NS_HHH
, NS_FFF
, NS_DDD
, NS_DDS
,
18001 NS_QQS
, NS_QQQ
, NS_QQR
, NS_NULL
);
18002 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
18003 && inst
.cond
== COND_ALWAYS
18004 && ((unsigned)inst
.instruction
) == M_MNEM_vmullt
)
18009 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18010 N_SUF_32
| N_F64
| N_P8
18011 | N_P16
| N_I_MVE
| N_KEY
);
18012 if (((et
.type
== NT_poly
) && et
.size
== 8
18013 && ARM_CPU_IS_ANY (cpu_variant
))
18014 || (et
.type
== NT_integer
) || (et
.type
== NT_float
))
18021 constraint (rs
!= NS_QQQ
, BAD_FPU
);
18022 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18023 N_SU_32
| N_P8
| N_P16
| N_KEY
);
18025 /* We are dealing with MVE's vmullt. */
18027 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
18028 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
18029 as_tsktsk (BAD_MVE_SRCDEST
);
18031 if (inst
.cond
> COND_ALWAYS
)
18032 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18034 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18036 if (et
.type
== NT_poly
)
18037 mve_encode_qqq (neon_logbits (et
.size
), 64);
18039 mve_encode_qqq (et
.type
== NT_unsigned
, et
.size
);
18044 inst
.instruction
= N_MNEM_vmul
;
18047 inst
.pred_insn_type
= INSIDE_IT_INSN
;
18052 do_mve_vabav (void)
18054 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18059 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18062 struct neon_type_el et
= neon_check_type (2, NS_NULL
, N_EQK
, N_KEY
| N_S8
18063 | N_S16
| N_S32
| N_U8
| N_U16
18066 if (inst
.cond
> COND_ALWAYS
)
18067 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18069 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18071 mve_encode_rqq (et
.type
== NT_unsigned
, et
.size
);
18075 do_mve_vmladav (void)
18077 enum neon_shape rs
= neon_select_shape (NS_RQQ
, NS_NULL
);
18078 struct neon_type_el et
= neon_check_type (3, rs
,
18079 N_EQK
, N_EQK
, N_SU_MVE
| N_KEY
);
18081 if (et
.type
== NT_unsigned
18082 && (inst
.instruction
== M_MNEM_vmladavx
18083 || inst
.instruction
== M_MNEM_vmladavax
18084 || inst
.instruction
== M_MNEM_vmlsdav
18085 || inst
.instruction
== M_MNEM_vmlsdava
18086 || inst
.instruction
== M_MNEM_vmlsdavx
18087 || inst
.instruction
== M_MNEM_vmlsdavax
))
18088 first_error (BAD_SIMD_TYPE
);
18090 constraint (inst
.operands
[2].reg
> 14,
18091 _("MVE vector register in the range [Q0..Q7] expected"));
18093 if (inst
.cond
> COND_ALWAYS
)
18094 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18096 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18098 if (inst
.instruction
== M_MNEM_vmlsdav
18099 || inst
.instruction
== M_MNEM_vmlsdava
18100 || inst
.instruction
== M_MNEM_vmlsdavx
18101 || inst
.instruction
== M_MNEM_vmlsdavax
)
18102 inst
.instruction
|= (et
.size
== 8) << 28;
18104 inst
.instruction
|= (et
.size
== 8) << 8;
18106 mve_encode_rqq (et
.type
== NT_unsigned
, 64);
18107 inst
.instruction
|= (et
.size
== 32) << 16;
18111 do_mve_vmlaldav (void)
18113 enum neon_shape rs
= neon_select_shape (NS_RRQQ
, NS_NULL
);
18114 struct neon_type_el et
18115 = neon_check_type (4, rs
, N_EQK
, N_EQK
, N_EQK
,
18116 N_S16
| N_S32
| N_U16
| N_U32
| N_KEY
);
18118 if (et
.type
== NT_unsigned
18119 && (inst
.instruction
== M_MNEM_vmlsldav
18120 || inst
.instruction
== M_MNEM_vmlsldava
18121 || inst
.instruction
== M_MNEM_vmlsldavx
18122 || inst
.instruction
== M_MNEM_vmlsldavax
))
18123 first_error (BAD_SIMD_TYPE
);
18125 if (inst
.cond
> COND_ALWAYS
)
18126 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18128 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18130 mve_encode_rrqq (et
.type
== NT_unsigned
, et
.size
);
18134 do_mve_vrmlaldavh (void)
18136 struct neon_type_el et
;
18137 if (inst
.instruction
== M_MNEM_vrmlsldavh
18138 || inst
.instruction
== M_MNEM_vrmlsldavha
18139 || inst
.instruction
== M_MNEM_vrmlsldavhx
18140 || inst
.instruction
== M_MNEM_vrmlsldavhax
)
18142 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18143 if (inst
.operands
[1].reg
== REG_SP
)
18144 as_tsktsk (MVE_BAD_SP
);
18148 if (inst
.instruction
== M_MNEM_vrmlaldavhx
18149 || inst
.instruction
== M_MNEM_vrmlaldavhax
)
18150 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
, N_S32
| N_KEY
);
18152 et
= neon_check_type (4, NS_RRQQ
, N_EQK
, N_EQK
, N_EQK
,
18153 N_U32
| N_S32
| N_KEY
);
18154 /* vrmlaldavh's encoding with SP as the second, odd, GPR operand may alias
18155 with vmax/min instructions, making the use of SP in assembly really
18156 nonsensical, so instead of issuing a warning like we do for other uses
18157 of SP for the odd register operand we error out. */
18158 constraint (inst
.operands
[1].reg
== REG_SP
, BAD_SP
);
18161 /* Make sure we still check the second operand is an odd one and that PC is
18162 disallowed. This because we are parsing for any GPR operand, to be able
18163 to distinguish between giving a warning or an error for SP as described
18165 constraint ((inst
.operands
[1].reg
% 2) != 1, BAD_EVEN
);
18166 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
18168 if (inst
.cond
> COND_ALWAYS
)
18169 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18171 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18173 mve_encode_rrqq (et
.type
== NT_unsigned
, 0);
18178 do_mve_vmaxnmv (void)
18180 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18181 struct neon_type_el et
18182 = neon_check_type (2, rs
, N_EQK
, N_F_MVE
| N_KEY
);
18184 if (inst
.cond
> COND_ALWAYS
)
18185 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18187 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18189 if (inst
.operands
[0].reg
== REG_SP
)
18190 as_tsktsk (MVE_BAD_SP
);
18191 else if (inst
.operands
[0].reg
== REG_PC
)
18192 as_tsktsk (MVE_BAD_PC
);
18194 mve_encode_rq (et
.size
== 16, 64);
18198 do_mve_vmaxv (void)
18200 enum neon_shape rs
= neon_select_shape (NS_RQ
, NS_NULL
);
18201 struct neon_type_el et
;
18203 if (inst
.instruction
== M_MNEM_vmaxv
|| inst
.instruction
== M_MNEM_vminv
)
18204 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
18206 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18208 if (inst
.cond
> COND_ALWAYS
)
18209 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
18211 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
18213 if (inst
.operands
[0].reg
== REG_SP
)
18214 as_tsktsk (MVE_BAD_SP
);
18215 else if (inst
.operands
[0].reg
== REG_PC
)
18216 as_tsktsk (MVE_BAD_PC
);
18218 mve_encode_rq (et
.type
== NT_unsigned
, et
.size
);
18223 do_neon_qrdmlah (void)
18225 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18227 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18229 /* Check we're on the correct architecture. */
18230 if (!mark_feature_used (&fpu_neon_ext_armv8
))
18232 = _("instruction form not available on this architecture.");
18233 else if (!mark_feature_used (&fpu_neon_ext_v8_1
))
18235 as_warn (_("this instruction implies use of ARMv8.1 AdvSIMD."));
18236 record_feature_use (&fpu_neon_ext_v8_1
);
18238 if (inst
.operands
[2].isscalar
)
18240 enum neon_shape rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
18241 struct neon_type_el et
= neon_check_type (3, rs
,
18242 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18243 NEON_ENCODE (SCALAR
, inst
);
18244 neon_mul_mac (et
, neon_quad (rs
));
18248 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18249 struct neon_type_el et
= neon_check_type (3, rs
,
18250 N_EQK
, N_EQK
, N_S16
| N_S32
| N_KEY
);
18251 NEON_ENCODE (INTEGER
, inst
);
18252 /* The U bit (rounding) comes from bit mask. */
18253 neon_three_same (neon_quad (rs
), 0, et
.size
);
18258 enum neon_shape rs
= neon_select_shape (NS_QQR
, NS_NULL
);
18259 struct neon_type_el et
18260 = neon_check_type (3, rs
, N_EQK
, N_EQK
, N_S_32
| N_KEY
);
18262 NEON_ENCODE (INTEGER
, inst
);
18263 mve_encode_qqr (et
.size
, et
.type
== NT_unsigned
, 0);
18268 do_neon_fcmp_absolute (void)
18270 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18271 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18272 N_F_16_32
| N_KEY
);
18273 /* Size field comes from bit mask. */
18274 neon_three_same (neon_quad (rs
), 1, et
.size
== 16 ? (int) et
.size
: -1);
18278 do_neon_fcmp_absolute_inv (void)
18280 neon_exchange_operands ();
18281 do_neon_fcmp_absolute ();
18285 do_neon_step (void)
18287 enum neon_shape rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
18288 struct neon_type_el et
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
18289 N_F_16_32
| N_KEY
);
18290 neon_three_same (neon_quad (rs
), 0, et
.size
== 16 ? (int) et
.size
: -1);
18294 do_neon_abs_neg (void)
18296 enum neon_shape rs
;
18297 struct neon_type_el et
;
18299 if (try_vfp_nsyn (2, do_vfp_nsyn_abs_neg
) == SUCCESS
)
18302 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
18303 et
= neon_check_type (2, rs
, N_EQK
, N_S_32
| N_F_16_32
| N_KEY
);
18305 if (!check_simd_pred_availability (et
.type
== NT_float
,
18306 NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18309 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18310 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18311 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18312 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18313 inst
.instruction
|= neon_quad (rs
) << 6;
18314 inst
.instruction
|= (et
.type
== NT_float
) << 10;
18315 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18317 neon_dp_fixup (&inst
);
18323 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18326 enum neon_shape rs
;
18327 struct neon_type_el et
;
18328 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18330 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18331 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18335 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18336 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18340 int imm
= inst
.operands
[2].imm
;
18341 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18342 _("immediate out of range for insert"));
18343 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18349 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18352 enum neon_shape rs
;
18353 struct neon_type_el et
;
18354 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18356 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18357 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
18361 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18362 et
= neon_check_type (2, rs
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
18365 int imm
= inst
.operands
[2].imm
;
18366 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18367 _("immediate out of range for insert"));
18368 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, et
.size
- imm
);
18372 do_neon_qshlu_imm (void)
18374 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
18377 enum neon_shape rs
;
18378 struct neon_type_el et
;
18379 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
18381 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
18382 et
= neon_check_type (2, rs
, N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
18386 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
18387 et
= neon_check_type (2, rs
, N_EQK
| N_UNS
,
18388 N_S8
| N_S16
| N_S32
| N_S64
| N_KEY
);
18391 int imm
= inst
.operands
[2].imm
;
18392 constraint (imm
< 0 || (unsigned)imm
>= et
.size
,
18393 _("immediate out of range for shift"));
18394 /* Only encodes the 'U present' variant of the instruction.
18395 In this case, signed types have OP (bit 8) set to 0.
18396 Unsigned types have OP set to 1. */
18397 inst
.instruction
|= (et
.type
== NT_unsigned
) << 8;
18398 /* The rest of the bits are the same as other immediate shifts. */
18399 neon_imm_shift (FALSE
, 0, neon_quad (rs
), et
, imm
);
18403 do_neon_qmovn (void)
18405 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18406 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18407 /* Saturating move where operands can be signed or unsigned, and the
18408 destination has the same signedness. */
18409 NEON_ENCODE (INTEGER
, inst
);
18410 if (et
.type
== NT_unsigned
)
18411 inst
.instruction
|= 0xc0;
18413 inst
.instruction
|= 0x80;
18414 neon_two_same (0, 1, et
.size
/ 2);
18418 do_neon_qmovun (void)
18420 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18421 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18422 /* Saturating move with unsigned results. Operands must be signed. */
18423 NEON_ENCODE (INTEGER
, inst
);
18424 neon_two_same (0, 1, et
.size
/ 2);
18428 do_neon_rshift_sat_narrow (void)
18430 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18431 or unsigned. If operands are unsigned, results must also be unsigned. */
18432 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18433 N_EQK
| N_HLF
, N_SU_16_64
| N_KEY
);
18434 int imm
= inst
.operands
[2].imm
;
18435 /* This gets the bounds check, size encoding and immediate bits calculation
18439 /* VQ{R}SHRN.I<size> <Dd>, <Qm>, #0 is a synonym for
18440 VQMOVN.I<size> <Dd>, <Qm>. */
18443 inst
.operands
[2].present
= 0;
18444 inst
.instruction
= N_MNEM_vqmovn
;
18449 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18450 _("immediate out of range"));
18451 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, et
.size
- imm
);
18455 do_neon_rshift_sat_narrow_u (void)
18457 /* FIXME: Types for narrowing. If operands are signed, results can be signed
18458 or unsigned. If operands are unsigned, results must also be unsigned. */
18459 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18460 N_EQK
| N_HLF
| N_UNS
, N_S16
| N_S32
| N_S64
| N_KEY
);
18461 int imm
= inst
.operands
[2].imm
;
18462 /* This gets the bounds check, size encoding and immediate bits calculation
18466 /* VQSHRUN.I<size> <Dd>, <Qm>, #0 is a synonym for
18467 VQMOVUN.I<size> <Dd>, <Qm>. */
18470 inst
.operands
[2].present
= 0;
18471 inst
.instruction
= N_MNEM_vqmovun
;
18476 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18477 _("immediate out of range"));
18478 /* FIXME: The manual is kind of unclear about what value U should have in
18479 VQ{R}SHRUN instructions, but U=0, op=0 definitely encodes VRSHR, so it
18481 neon_imm_shift (TRUE
, 1, 0, et
, et
.size
- imm
);
18485 do_neon_movn (void)
18487 struct neon_type_el et
= neon_check_type (2, NS_DQ
,
18488 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18489 NEON_ENCODE (INTEGER
, inst
);
18490 neon_two_same (0, 1, et
.size
/ 2);
18494 do_neon_rshift_narrow (void)
18496 struct neon_type_el et
= neon_check_type (2, NS_DQI
,
18497 N_EQK
| N_HLF
, N_I16
| N_I32
| N_I64
| N_KEY
);
18498 int imm
= inst
.operands
[2].imm
;
18499 /* This gets the bounds check, size encoding and immediate bits calculation
18503 /* If immediate is zero then we are a pseudo-instruction for
18504 VMOVN.I<size> <Dd>, <Qm> */
18507 inst
.operands
[2].present
= 0;
18508 inst
.instruction
= N_MNEM_vmovn
;
18513 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
18514 _("immediate out of range for narrowing operation"));
18515 neon_imm_shift (FALSE
, 0, 0, et
, et
.size
- imm
);
18519 do_neon_shll (void)
18521 /* FIXME: Type checking when lengthening. */
18522 struct neon_type_el et
= neon_check_type (2, NS_QDI
,
18523 N_EQK
| N_DBL
, N_I8
| N_I16
| N_I32
| N_KEY
);
18524 unsigned imm
= inst
.operands
[2].imm
;
18526 if (imm
== et
.size
)
18528 /* Maximum shift variant. */
18529 NEON_ENCODE (INTEGER
, inst
);
18530 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18531 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18532 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18533 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18534 inst
.instruction
|= neon_logbits (et
.size
) << 18;
18536 neon_dp_fixup (&inst
);
18540 /* A more-specific type check for non-max versions. */
18541 et
= neon_check_type (2, NS_QDI
,
18542 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
18543 NEON_ENCODE (IMMED
, inst
);
18544 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, 0, et
, imm
);
18548 /* Check the various types for the VCVT instruction, and return which version
18549 the current instruction is. */
18551 #define CVT_FLAVOUR_VAR \
18552 CVT_VAR (s32_f32, N_S32, N_F32, whole_reg, "ftosls", "ftosis", "ftosizs") \
18553 CVT_VAR (u32_f32, N_U32, N_F32, whole_reg, "ftouls", "ftouis", "ftouizs") \
18554 CVT_VAR (f32_s32, N_F32, N_S32, whole_reg, "fsltos", "fsitos", NULL) \
18555 CVT_VAR (f32_u32, N_F32, N_U32, whole_reg, "fultos", "fuitos", NULL) \
18556 /* Half-precision conversions. */ \
18557 CVT_VAR (s16_f16, N_S16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18558 CVT_VAR (u16_f16, N_U16, N_F16 | N_KEY, whole_reg, NULL, NULL, NULL) \
18559 CVT_VAR (f16_s16, N_F16 | N_KEY, N_S16, whole_reg, NULL, NULL, NULL) \
18560 CVT_VAR (f16_u16, N_F16 | N_KEY, N_U16, whole_reg, NULL, NULL, NULL) \
18561 CVT_VAR (f32_f16, N_F32, N_F16, whole_reg, NULL, NULL, NULL) \
18562 CVT_VAR (f16_f32, N_F16, N_F32, whole_reg, NULL, NULL, NULL) \
18563 /* New VCVT instructions introduced by ARMv8.2 fp16 extension. \
18564 Compared with single/double precision variants, only the co-processor \
18565 field is different, so the encoding flow is reused here. */ \
18566 CVT_VAR (f16_s32, N_F16 | N_KEY, N_S32, N_VFP, "fsltos", "fsitos", NULL) \
18567 CVT_VAR (f16_u32, N_F16 | N_KEY, N_U32, N_VFP, "fultos", "fuitos", NULL) \
18568 CVT_VAR (u32_f16, N_U32, N_F16 | N_KEY, N_VFP, "ftouls", "ftouis", "ftouizs")\
18569 CVT_VAR (s32_f16, N_S32, N_F16 | N_KEY, N_VFP, "ftosls", "ftosis", "ftosizs")\
18570 /* VFP instructions. */ \
18571 CVT_VAR (f32_f64, N_F32, N_F64, N_VFP, NULL, "fcvtsd", NULL) \
18572 CVT_VAR (f64_f32, N_F64, N_F32, N_VFP, NULL, "fcvtds", NULL) \
18573 CVT_VAR (s32_f64, N_S32, N_F64 | key, N_VFP, "ftosld", "ftosid", "ftosizd") \
18574 CVT_VAR (u32_f64, N_U32, N_F64 | key, N_VFP, "ftould", "ftouid", "ftouizd") \
18575 CVT_VAR (f64_s32, N_F64 | key, N_S32, N_VFP, "fsltod", "fsitod", NULL) \
18576 CVT_VAR (f64_u32, N_F64 | key, N_U32, N_VFP, "fultod", "fuitod", NULL) \
18577 /* VFP instructions with bitshift. */ \
18578 CVT_VAR (f32_s16, N_F32 | key, N_S16, N_VFP, "fshtos", NULL, NULL) \
18579 CVT_VAR (f32_u16, N_F32 | key, N_U16, N_VFP, "fuhtos", NULL, NULL) \
18580 CVT_VAR (f64_s16, N_F64 | key, N_S16, N_VFP, "fshtod", NULL, NULL) \
18581 CVT_VAR (f64_u16, N_F64 | key, N_U16, N_VFP, "fuhtod", NULL, NULL) \
18582 CVT_VAR (s16_f32, N_S16, N_F32 | key, N_VFP, "ftoshs", NULL, NULL) \
18583 CVT_VAR (u16_f32, N_U16, N_F32 | key, N_VFP, "ftouhs", NULL, NULL) \
18584 CVT_VAR (s16_f64, N_S16, N_F64 | key, N_VFP, "ftoshd", NULL, NULL) \
18585 CVT_VAR (u16_f64, N_U16, N_F64 | key, N_VFP, "ftouhd", NULL, NULL)
18587 #define CVT_VAR(C, X, Y, R, BSN, CN, ZN) \
18588 neon_cvt_flavour_##C,
18590 /* The different types of conversions we can do. */
18591 enum neon_cvt_flavour
18594 neon_cvt_flavour_invalid
,
18595 neon_cvt_flavour_first_fp
= neon_cvt_flavour_f32_f64
18600 static enum neon_cvt_flavour
18601 get_neon_cvt_flavour (enum neon_shape rs
)
18603 #define CVT_VAR(C,X,Y,R,BSN,CN,ZN) \
18604 et = neon_check_type (2, rs, (R) | (X), (R) | (Y)); \
18605 if (et.type != NT_invtype) \
18607 inst.error = NULL; \
18608 return (neon_cvt_flavour_##C); \
18611 struct neon_type_el et
;
18612 unsigned whole_reg
= (rs
== NS_FFI
|| rs
== NS_FD
|| rs
== NS_DF
18613 || rs
== NS_FF
) ? N_VFP
: 0;
18614 /* The instruction versions which take an immediate take one register
18615 argument, which is extended to the width of the full register. Thus the
18616 "source" and "destination" registers must have the same width. Hack that
18617 here by making the size equal to the key (wider, in this case) operand. */
18618 unsigned key
= (rs
== NS_QQI
|| rs
== NS_DDI
|| rs
== NS_FFI
) ? N_KEY
: 0;
18622 return neon_cvt_flavour_invalid
;
18637 /* Neon-syntax VFP conversions. */
18640 do_vfp_nsyn_cvt (enum neon_shape rs
, enum neon_cvt_flavour flavour
)
18642 const char *opname
= 0;
18644 if (rs
== NS_DDI
|| rs
== NS_QQI
|| rs
== NS_FFI
18645 || rs
== NS_FHI
|| rs
== NS_HFI
)
18647 /* Conversions with immediate bitshift. */
18648 const char *enc
[] =
18650 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) BSN,
18656 if (flavour
< (int) ARRAY_SIZE (enc
))
18658 opname
= enc
[flavour
];
18659 constraint (inst
.operands
[0].reg
!= inst
.operands
[1].reg
,
18660 _("operands 0 and 1 must be the same register"));
18661 inst
.operands
[1] = inst
.operands
[2];
18662 memset (&inst
.operands
[2], '\0', sizeof (inst
.operands
[2]));
18667 /* Conversions without bitshift. */
18668 const char *enc
[] =
18670 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) CN,
18676 if (flavour
< (int) ARRAY_SIZE (enc
))
18677 opname
= enc
[flavour
];
18681 do_vfp_nsyn_opcode (opname
);
18683 /* ARMv8.2 fp16 VCVT instruction. */
18684 if (flavour
== neon_cvt_flavour_s32_f16
18685 || flavour
== neon_cvt_flavour_u32_f16
18686 || flavour
== neon_cvt_flavour_f16_u32
18687 || flavour
== neon_cvt_flavour_f16_s32
)
18688 do_scalar_fp16_v82_encode ();
18692 do_vfp_nsyn_cvtz (void)
18694 enum neon_shape rs
= neon_select_shape (NS_FH
, NS_FF
, NS_FD
, NS_NULL
);
18695 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18696 const char *enc
[] =
18698 #define CVT_VAR(C,A,B,R,BSN,CN,ZN) ZN,
18704 if (flavour
< (int) ARRAY_SIZE (enc
) && enc
[flavour
])
18705 do_vfp_nsyn_opcode (enc
[flavour
]);
18709 do_vfp_nsyn_cvt_fpv8 (enum neon_cvt_flavour flavour
,
18710 enum neon_cvt_mode mode
)
18715 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
18716 D register operands. */
18717 if (flavour
== neon_cvt_flavour_s32_f64
18718 || flavour
== neon_cvt_flavour_u32_f64
)
18719 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
18722 if (flavour
== neon_cvt_flavour_s32_f16
18723 || flavour
== neon_cvt_flavour_u32_f16
)
18724 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
),
18727 set_pred_insn_type (OUTSIDE_PRED_INSN
);
18731 case neon_cvt_flavour_s32_f64
:
18735 case neon_cvt_flavour_s32_f32
:
18739 case neon_cvt_flavour_s32_f16
:
18743 case neon_cvt_flavour_u32_f64
:
18747 case neon_cvt_flavour_u32_f32
:
18751 case neon_cvt_flavour_u32_f16
:
18756 first_error (_("invalid instruction shape"));
18762 case neon_cvt_mode_a
: rm
= 0; break;
18763 case neon_cvt_mode_n
: rm
= 1; break;
18764 case neon_cvt_mode_p
: rm
= 2; break;
18765 case neon_cvt_mode_m
: rm
= 3; break;
18766 default: first_error (_("invalid rounding mode")); return;
18769 NEON_ENCODE (FPV8
, inst
);
18770 encode_arm_vfp_reg (inst
.operands
[0].reg
, VFP_REG_Sd
);
18771 encode_arm_vfp_reg (inst
.operands
[1].reg
, sz
== 1 ? VFP_REG_Dm
: VFP_REG_Sm
);
18772 inst
.instruction
|= sz
<< 8;
18774 /* ARMv8.2 fp16 VCVT instruction. */
18775 if (flavour
== neon_cvt_flavour_s32_f16
18776 ||flavour
== neon_cvt_flavour_u32_f16
)
18777 do_scalar_fp16_v82_encode ();
18778 inst
.instruction
|= op
<< 7;
18779 inst
.instruction
|= rm
<< 16;
18780 inst
.instruction
|= 0xf0000000;
18781 inst
.is_neon
= TRUE
;
18785 do_neon_cvt_1 (enum neon_cvt_mode mode
)
18787 enum neon_shape rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_FFI
, NS_DD
, NS_QQ
,
18788 NS_FD
, NS_DF
, NS_FF
, NS_QD
, NS_DQ
,
18789 NS_FH
, NS_HF
, NS_FHI
, NS_HFI
,
18791 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
18793 if (flavour
== neon_cvt_flavour_invalid
)
18796 /* PR11109: Handle round-to-zero for VCVT conversions. */
18797 if (mode
== neon_cvt_mode_z
18798 && ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_vfp_v2
)
18799 && (flavour
== neon_cvt_flavour_s16_f16
18800 || flavour
== neon_cvt_flavour_u16_f16
18801 || flavour
== neon_cvt_flavour_s32_f32
18802 || flavour
== neon_cvt_flavour_u32_f32
18803 || flavour
== neon_cvt_flavour_s32_f64
18804 || flavour
== neon_cvt_flavour_u32_f64
)
18805 && (rs
== NS_FD
|| rs
== NS_FF
))
18807 do_vfp_nsyn_cvtz ();
18811 /* ARMv8.2 fp16 VCVT conversions. */
18812 if (mode
== neon_cvt_mode_z
18813 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16
)
18814 && (flavour
== neon_cvt_flavour_s32_f16
18815 || flavour
== neon_cvt_flavour_u32_f16
)
18818 do_vfp_nsyn_cvtz ();
18819 do_scalar_fp16_v82_encode ();
18823 /* VFP rather than Neon conversions. */
18824 if (flavour
>= neon_cvt_flavour_first_fp
)
18826 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
18827 do_vfp_nsyn_cvt (rs
, flavour
);
18829 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
18837 if (mode
== neon_cvt_mode_z
18838 && (flavour
== neon_cvt_flavour_f16_s16
18839 || flavour
== neon_cvt_flavour_f16_u16
18840 || flavour
== neon_cvt_flavour_s16_f16
18841 || flavour
== neon_cvt_flavour_u16_f16
18842 || flavour
== neon_cvt_flavour_f32_u32
18843 || flavour
== neon_cvt_flavour_f32_s32
18844 || flavour
== neon_cvt_flavour_s32_f32
18845 || flavour
== neon_cvt_flavour_u32_f32
))
18847 if (!check_simd_pred_availability (TRUE
,
18848 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18851 else if (mode
== neon_cvt_mode_n
)
18853 /* We are dealing with vcvt with the 'ne' condition. */
18855 inst
.instruction
= N_MNEM_vcvt
;
18856 do_neon_cvt_1 (neon_cvt_mode_z
);
18859 /* fall through. */
18863 unsigned enctab
[] = {0x0000100, 0x1000100, 0x0, 0x1000000,
18864 0x0000100, 0x1000100, 0x0, 0x1000000};
18866 if ((rs
!= NS_QQI
|| !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18867 && vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18870 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18872 constraint (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0,
18873 _("immediate value out of range"));
18876 case neon_cvt_flavour_f16_s16
:
18877 case neon_cvt_flavour_f16_u16
:
18878 case neon_cvt_flavour_s16_f16
:
18879 case neon_cvt_flavour_u16_f16
:
18880 constraint (inst
.operands
[2].imm
> 16,
18881 _("immediate value out of range"));
18883 case neon_cvt_flavour_f32_u32
:
18884 case neon_cvt_flavour_f32_s32
:
18885 case neon_cvt_flavour_s32_f32
:
18886 case neon_cvt_flavour_u32_f32
:
18887 constraint (inst
.operands
[2].imm
> 32,
18888 _("immediate value out of range"));
18891 inst
.error
= BAD_FPU
;
18896 /* Fixed-point conversion with #0 immediate is encoded as an
18897 integer conversion. */
18898 if (inst
.operands
[2].present
&& inst
.operands
[2].imm
== 0)
18900 NEON_ENCODE (IMMED
, inst
);
18901 if (flavour
!= neon_cvt_flavour_invalid
)
18902 inst
.instruction
|= enctab
[flavour
];
18903 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18904 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18905 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18906 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18907 inst
.instruction
|= neon_quad (rs
) << 6;
18908 inst
.instruction
|= 1 << 21;
18909 if (flavour
< neon_cvt_flavour_s16_f16
)
18911 inst
.instruction
|= 1 << 21;
18912 immbits
= 32 - inst
.operands
[2].imm
;
18913 inst
.instruction
|= immbits
<< 16;
18917 inst
.instruction
|= 3 << 20;
18918 immbits
= 16 - inst
.operands
[2].imm
;
18919 inst
.instruction
|= immbits
<< 16;
18920 inst
.instruction
&= ~(1 << 9);
18923 neon_dp_fixup (&inst
);
18928 if ((mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
18929 || mode
== neon_cvt_mode_m
|| mode
== neon_cvt_mode_p
)
18930 && (flavour
== neon_cvt_flavour_s16_f16
18931 || flavour
== neon_cvt_flavour_u16_f16
18932 || flavour
== neon_cvt_flavour_s32_f32
18933 || flavour
== neon_cvt_flavour_u32_f32
))
18935 if (!check_simd_pred_availability (TRUE
,
18936 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18939 else if (mode
== neon_cvt_mode_z
18940 && (flavour
== neon_cvt_flavour_f16_s16
18941 || flavour
== neon_cvt_flavour_f16_u16
18942 || flavour
== neon_cvt_flavour_s16_f16
18943 || flavour
== neon_cvt_flavour_u16_f16
18944 || flavour
== neon_cvt_flavour_f32_u32
18945 || flavour
== neon_cvt_flavour_f32_s32
18946 || flavour
== neon_cvt_flavour_s32_f32
18947 || flavour
== neon_cvt_flavour_u32_f32
))
18949 if (!check_simd_pred_availability (TRUE
,
18950 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
18953 /* fall through. */
18955 if (mode
!= neon_cvt_mode_x
&& mode
!= neon_cvt_mode_z
)
18958 NEON_ENCODE (FLOAT
, inst
);
18959 if (!check_simd_pred_availability (TRUE
,
18960 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
18963 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
18964 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
18965 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
18966 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
18967 inst
.instruction
|= neon_quad (rs
) << 6;
18968 inst
.instruction
|= (flavour
== neon_cvt_flavour_u16_f16
18969 || flavour
== neon_cvt_flavour_u32_f32
) << 7;
18970 inst
.instruction
|= mode
<< 8;
18971 if (flavour
== neon_cvt_flavour_u16_f16
18972 || flavour
== neon_cvt_flavour_s16_f16
)
18973 /* Mask off the original size bits and reencode them. */
18974 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff) | (1 << 18));
18977 inst
.instruction
|= 0xfc000000;
18979 inst
.instruction
|= 0xf0000000;
18985 unsigned enctab
[] = { 0x100, 0x180, 0x0, 0x080,
18986 0x100, 0x180, 0x0, 0x080};
18988 NEON_ENCODE (INTEGER
, inst
);
18990 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
18992 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
18996 if (flavour
!= neon_cvt_flavour_invalid
)
18997 inst
.instruction
|= enctab
[flavour
];
18999 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19000 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19001 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19002 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19003 inst
.instruction
|= neon_quad (rs
) << 6;
19004 if (flavour
>= neon_cvt_flavour_s16_f16
19005 && flavour
<= neon_cvt_flavour_f16_u16
)
19006 /* Half precision. */
19007 inst
.instruction
|= 1 << 18;
19009 inst
.instruction
|= 2 << 18;
19011 neon_dp_fixup (&inst
);
19016 /* Half-precision conversions for Advanced SIMD -- neon. */
19019 if (vfp_or_neon_is_neon (NEON_CHECK_CC
| NEON_CHECK_ARCH
) == FAIL
)
19023 && (inst
.vectype
.el
[0].size
!= 16 || inst
.vectype
.el
[1].size
!= 32))
19025 as_bad (_("operand size must match register width"));
19030 && ((inst
.vectype
.el
[0].size
!= 32 || inst
.vectype
.el
[1].size
!= 16)))
19032 as_bad (_("operand size must match register width"));
19037 inst
.instruction
= 0x3b60600;
19039 inst
.instruction
= 0x3b60700;
19041 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19042 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19043 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19044 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19045 neon_dp_fixup (&inst
);
19049 /* Some VFP conversions go here (s32 <-> f32, u32 <-> f32). */
19050 if (mode
== neon_cvt_mode_x
|| mode
== neon_cvt_mode_z
)
19051 do_vfp_nsyn_cvt (rs
, flavour
);
19053 do_vfp_nsyn_cvt_fpv8 (flavour
, mode
);
19058 do_neon_cvtr (void)
19060 do_neon_cvt_1 (neon_cvt_mode_x
);
19066 do_neon_cvt_1 (neon_cvt_mode_z
);
19070 do_neon_cvta (void)
19072 do_neon_cvt_1 (neon_cvt_mode_a
);
19076 do_neon_cvtn (void)
19078 do_neon_cvt_1 (neon_cvt_mode_n
);
19082 do_neon_cvtp (void)
19084 do_neon_cvt_1 (neon_cvt_mode_p
);
19088 do_neon_cvtm (void)
19090 do_neon_cvt_1 (neon_cvt_mode_m
);
19094 do_neon_cvttb_2 (bfd_boolean t
, bfd_boolean to
, bfd_boolean is_double
)
19097 mark_feature_used (&fpu_vfp_ext_armv8
);
19099 encode_arm_vfp_reg (inst
.operands
[0].reg
,
19100 (is_double
&& !to
) ? VFP_REG_Dd
: VFP_REG_Sd
);
19101 encode_arm_vfp_reg (inst
.operands
[1].reg
,
19102 (is_double
&& to
) ? VFP_REG_Dm
: VFP_REG_Sm
);
19103 inst
.instruction
|= to
? 0x10000 : 0;
19104 inst
.instruction
|= t
? 0x80 : 0;
19105 inst
.instruction
|= is_double
? 0x100 : 0;
19106 do_vfp_cond_or_thumb ();
19110 do_neon_cvttb_1 (bfd_boolean t
)
19112 enum neon_shape rs
= neon_select_shape (NS_HF
, NS_HD
, NS_FH
, NS_FF
, NS_FD
,
19113 NS_DF
, NS_DH
, NS_QQ
, NS_QQI
, NS_NULL
);
19117 else if (rs
== NS_QQ
|| rs
== NS_QQI
)
19119 int single_to_half
= 0;
19120 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_ARCH
))
19123 enum neon_cvt_flavour flavour
= get_neon_cvt_flavour (rs
);
19125 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19126 && (flavour
== neon_cvt_flavour_u16_f16
19127 || flavour
== neon_cvt_flavour_s16_f16
19128 || flavour
== neon_cvt_flavour_f16_s16
19129 || flavour
== neon_cvt_flavour_f16_u16
19130 || flavour
== neon_cvt_flavour_u32_f32
19131 || flavour
== neon_cvt_flavour_s32_f32
19132 || flavour
== neon_cvt_flavour_f32_s32
19133 || flavour
== neon_cvt_flavour_f32_u32
))
19136 inst
.instruction
= N_MNEM_vcvt
;
19137 set_pred_insn_type (INSIDE_VPT_INSN
);
19138 do_neon_cvt_1 (neon_cvt_mode_z
);
19141 else if (rs
== NS_QQ
&& flavour
== neon_cvt_flavour_f32_f16
)
19142 single_to_half
= 1;
19143 else if (rs
== NS_QQ
&& flavour
!= neon_cvt_flavour_f16_f32
)
19145 first_error (BAD_FPU
);
19149 inst
.instruction
= 0xee3f0e01;
19150 inst
.instruction
|= single_to_half
<< 28;
19151 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19152 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 13;
19153 inst
.instruction
|= t
<< 12;
19154 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19155 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 1;
19158 else if (neon_check_type (2, rs
, N_F16
, N_F32
| N_VFP
).type
!= NT_invtype
)
19161 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/FALSE
);
19163 else if (neon_check_type (2, rs
, N_F32
| N_VFP
, N_F16
).type
!= NT_invtype
)
19166 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/FALSE
);
19168 else if (neon_check_type (2, rs
, N_F16
, N_F64
| N_VFP
).type
!= NT_invtype
)
19170 /* The VCVTB and VCVTT instructions with D-register operands
19171 don't work for SP only targets. */
19172 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19176 do_neon_cvttb_2 (t
, /*to=*/TRUE
, /*is_double=*/TRUE
);
19178 else if (neon_check_type (2, rs
, N_F64
| N_VFP
, N_F16
).type
!= NT_invtype
)
19180 /* The VCVTB and VCVTT instructions with D-register operands
19181 don't work for SP only targets. */
19182 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
19186 do_neon_cvttb_2 (t
, /*to=*/FALSE
, /*is_double=*/TRUE
);
19193 do_neon_cvtb (void)
19195 do_neon_cvttb_1 (FALSE
);
19200 do_neon_cvtt (void)
19202 do_neon_cvttb_1 (TRUE
);
19206 neon_move_immediate (void)
19208 enum neon_shape rs
= neon_select_shape (NS_DI
, NS_QI
, NS_NULL
);
19209 struct neon_type_el et
= neon_check_type (2, rs
,
19210 N_I8
| N_I16
| N_I32
| N_I64
| N_F32
| N_KEY
, N_EQK
);
19211 unsigned immlo
, immhi
= 0, immbits
;
19212 int op
, cmode
, float_p
;
19214 constraint (et
.type
== NT_invtype
,
19215 _("operand size must be specified for immediate VMOV"));
19217 /* We start out as an MVN instruction if OP = 1, MOV otherwise. */
19218 op
= (inst
.instruction
& (1 << 5)) != 0;
19220 immlo
= inst
.operands
[1].imm
;
19221 if (inst
.operands
[1].regisimm
)
19222 immhi
= inst
.operands
[1].reg
;
19224 constraint (et
.size
< 32 && (immlo
& ~((1 << et
.size
) - 1)) != 0,
19225 _("immediate has bits set outside the operand size"));
19227 float_p
= inst
.operands
[1].immisfloat
;
19229 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
, &op
,
19230 et
.size
, et
.type
)) == FAIL
)
19232 /* Invert relevant bits only. */
19233 neon_invert_size (&immlo
, &immhi
, et
.size
);
19234 /* Flip from VMOV/VMVN to VMVN/VMOV. Some immediate types are unavailable
19235 with one or the other; those cases are caught by
19236 neon_cmode_for_move_imm. */
19238 if ((cmode
= neon_cmode_for_move_imm (immlo
, immhi
, float_p
, &immbits
,
19239 &op
, et
.size
, et
.type
)) == FAIL
)
19241 first_error (_("immediate out of range"));
19246 inst
.instruction
&= ~(1 << 5);
19247 inst
.instruction
|= op
<< 5;
19249 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19250 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19251 inst
.instruction
|= neon_quad (rs
) << 6;
19252 inst
.instruction
|= cmode
<< 8;
19254 neon_write_immbits (immbits
);
19260 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19263 if (inst
.operands
[1].isreg
)
19265 enum neon_shape rs
;
19266 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19267 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19269 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19271 NEON_ENCODE (INTEGER
, inst
);
19272 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19273 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19274 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19275 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19276 inst
.instruction
|= neon_quad (rs
) << 6;
19280 NEON_ENCODE (IMMED
, inst
);
19281 neon_move_immediate ();
19284 neon_dp_fixup (&inst
);
19286 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19288 constraint (!inst
.operands
[1].isreg
&& !inst
.operands
[0].isquad
, BAD_FPU
);
19289 constraint ((inst
.instruction
& 0xd00) == 0xd00,
19290 _("immediate value out of range"));
19294 /* Encode instructions of form:
19296 |28/24|23|22|21 20|19 16|15 12|11 8|7|6|5|4|3 0|
19297 | U |x |D |size | Rn | Rd |x x x x|N|x|M|x| Rm | */
19300 neon_mixed_length (struct neon_type_el et
, unsigned size
)
19302 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19303 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19304 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19305 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19306 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19307 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19308 inst
.instruction
|= (et
.type
== NT_unsigned
) << 24;
19309 inst
.instruction
|= neon_logbits (size
) << 20;
19311 neon_dp_fixup (&inst
);
19315 do_neon_dyadic_long (void)
19317 enum neon_shape rs
= neon_select_shape (NS_QDD
, NS_QQQ
, NS_QQR
, NS_NULL
);
19320 if (vfp_or_neon_is_neon (NEON_CHECK_ARCH
| NEON_CHECK_CC
) == FAIL
)
19323 NEON_ENCODE (INTEGER
, inst
);
19324 /* FIXME: Type checking for lengthening op. */
19325 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19326 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19327 neon_mixed_length (et
, et
.size
);
19329 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19330 && (inst
.cond
== 0xf || inst
.cond
== 0x10))
19332 /* If parsing for MVE, vaddl/vsubl/vabdl{e,t} can only be vadd/vsub/vabd
19333 in an IT block with le/lt conditions. */
19335 if (inst
.cond
== 0xf)
19337 else if (inst
.cond
== 0x10)
19340 inst
.pred_insn_type
= INSIDE_IT_INSN
;
19342 if (inst
.instruction
== N_MNEM_vaddl
)
19344 inst
.instruction
= N_MNEM_vadd
;
19345 do_neon_addsub_if_i ();
19347 else if (inst
.instruction
== N_MNEM_vsubl
)
19349 inst
.instruction
= N_MNEM_vsub
;
19350 do_neon_addsub_if_i ();
19352 else if (inst
.instruction
== N_MNEM_vabdl
)
19354 inst
.instruction
= N_MNEM_vabd
;
19355 do_neon_dyadic_if_su ();
19359 first_error (BAD_FPU
);
19363 do_neon_abal (void)
19365 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19366 N_EQK
| N_INT
| N_DBL
, N_EQK
, N_SU_32
| N_KEY
);
19367 neon_mixed_length (et
, et
.size
);
19371 neon_mac_reg_scalar_long (unsigned regtypes
, unsigned scalartypes
)
19373 if (inst
.operands
[2].isscalar
)
19375 struct neon_type_el et
= neon_check_type (3, NS_QDS
,
19376 N_EQK
| N_DBL
, N_EQK
, regtypes
| N_KEY
);
19377 NEON_ENCODE (SCALAR
, inst
);
19378 neon_mul_mac (et
, et
.type
== NT_unsigned
);
19382 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19383 N_EQK
| N_DBL
, N_EQK
, scalartypes
| N_KEY
);
19384 NEON_ENCODE (INTEGER
, inst
);
19385 neon_mixed_length (et
, et
.size
);
19390 do_neon_mac_maybe_scalar_long (void)
19392 neon_mac_reg_scalar_long (N_S16
| N_S32
| N_U16
| N_U32
, N_SU_32
);
19395 /* Like neon_scalar_for_mul, this function generate Rm encoding from GAS's
19396 internal SCALAR. QUAD_P is 1 if it's for Q format, otherwise it's 0. */
19399 neon_scalar_for_fmac_fp16_long (unsigned scalar
, unsigned quad_p
)
19401 unsigned regno
= NEON_SCALAR_REG (scalar
);
19402 unsigned elno
= NEON_SCALAR_INDEX (scalar
);
19406 if (regno
> 7 || elno
> 3)
19409 return ((regno
& 0x7)
19410 | ((elno
& 0x1) << 3)
19411 | (((elno
>> 1) & 0x1) << 5));
19415 if (regno
> 15 || elno
> 1)
19418 return (((regno
& 0x1) << 5)
19419 | ((regno
>> 1) & 0x7)
19420 | ((elno
& 0x1) << 3));
19424 first_error (_("scalar out of range for multiply instruction"));
19429 do_neon_fmac_maybe_scalar_long (int subtype
)
19431 enum neon_shape rs
;
19433 /* NOTE: vfmal/vfmsl use slightly different NEON three-same encoding. 'size"
19434 field (bits[21:20]) has different meaning. For scalar index variant, it's
19435 used to differentiate add and subtract, otherwise it's with fixed value
19439 if (inst
.cond
!= COND_ALWAYS
)
19440 as_warn (_("vfmal/vfmsl with FP16 type cannot be conditional, the "
19441 "behaviour is UNPREDICTABLE"));
19443 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_fp16_fml
),
19446 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
19449 /* vfmal/vfmsl are in three-same D/Q register format or the third operand can
19450 be a scalar index register. */
19451 if (inst
.operands
[2].isscalar
)
19453 high8
= 0xfe000000;
19456 rs
= neon_select_shape (NS_DHS
, NS_QDS
, NS_NULL
);
19460 high8
= 0xfc000000;
19463 inst
.instruction
|= (0x1 << 23);
19464 rs
= neon_select_shape (NS_DHH
, NS_QDD
, NS_NULL
);
19467 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
);
19469 /* "opcode" from template has included "ubit", so simply pass 0 here. Also,
19470 the "S" bit in size field has been reused to differentiate vfmal and vfmsl,
19471 so we simply pass -1 as size. */
19472 unsigned quad_p
= (rs
== NS_QDD
|| rs
== NS_QDS
);
19473 neon_three_same (quad_p
, 0, size
);
19475 /* Undo neon_dp_fixup. Redo the high eight bits. */
19476 inst
.instruction
&= 0x00ffffff;
19477 inst
.instruction
|= high8
;
19479 #define LOW1(R) ((R) & 0x1)
19480 #define HI4(R) (((R) >> 1) & 0xf)
19481 /* Unlike usually NEON three-same, encoding for Vn and Vm will depend on
19482 whether the instruction is in Q form and whether Vm is a scalar indexed
19484 if (inst
.operands
[2].isscalar
)
19487 = neon_scalar_for_fmac_fp16_long (inst
.operands
[2].reg
, quad_p
);
19488 inst
.instruction
&= 0xffffffd0;
19489 inst
.instruction
|= rm
;
19493 /* Redo Rn as well. */
19494 inst
.instruction
&= 0xfff0ff7f;
19495 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19496 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19501 /* Redo Rn and Rm. */
19502 inst
.instruction
&= 0xfff0ff50;
19503 inst
.instruction
|= HI4 (inst
.operands
[1].reg
) << 16;
19504 inst
.instruction
|= LOW1 (inst
.operands
[1].reg
) << 7;
19505 inst
.instruction
|= HI4 (inst
.operands
[2].reg
);
19506 inst
.instruction
|= LOW1 (inst
.operands
[2].reg
) << 5;
19511 do_neon_vfmal (void)
19513 return do_neon_fmac_maybe_scalar_long (0);
19517 do_neon_vfmsl (void)
19519 return do_neon_fmac_maybe_scalar_long (1);
19523 do_neon_dyadic_wide (void)
19525 struct neon_type_el et
= neon_check_type (3, NS_QQD
,
19526 N_EQK
| N_DBL
, N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
19527 neon_mixed_length (et
, et
.size
);
19531 do_neon_dyadic_narrow (void)
19533 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19534 N_EQK
| N_DBL
, N_EQK
, N_I16
| N_I32
| N_I64
| N_KEY
);
19535 /* Operand sign is unimportant, and the U bit is part of the opcode,
19536 so force the operand type to integer. */
19537 et
.type
= NT_integer
;
19538 neon_mixed_length (et
, et
.size
/ 2);
19542 do_neon_mul_sat_scalar_long (void)
19544 neon_mac_reg_scalar_long (N_S16
| N_S32
, N_S16
| N_S32
);
19548 do_neon_vmull (void)
19550 if (inst
.operands
[2].isscalar
)
19551 do_neon_mac_maybe_scalar_long ();
19554 struct neon_type_el et
= neon_check_type (3, NS_QDD
,
19555 N_EQK
| N_DBL
, N_EQK
, N_SU_32
| N_P8
| N_P64
| N_KEY
);
19557 if (et
.type
== NT_poly
)
19558 NEON_ENCODE (POLY
, inst
);
19560 NEON_ENCODE (INTEGER
, inst
);
19562 /* For polynomial encoding the U bit must be zero, and the size must
19563 be 8 (encoded as 0b00) or, on ARMv8 or later 64 (encoded, non
19564 obviously, as 0b10). */
19567 /* Check we're on the correct architecture. */
19568 if (!mark_feature_used (&fpu_crypto_ext_armv8
))
19570 _("Instruction form not available on this architecture.");
19575 neon_mixed_length (et
, et
.size
);
19582 enum neon_shape rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
19583 struct neon_type_el et
= neon_check_type (3, rs
,
19584 N_EQK
, N_EQK
, N_8
| N_16
| N_32
| N_64
| N_KEY
);
19585 unsigned imm
= (inst
.operands
[3].imm
* et
.size
) / 8;
19587 constraint (imm
>= (unsigned) (neon_quad (rs
) ? 16 : 8),
19588 _("shift out of range"));
19589 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19590 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19591 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19592 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19593 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
19594 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
19595 inst
.instruction
|= neon_quad (rs
) << 6;
19596 inst
.instruction
|= imm
<< 8;
19598 neon_dp_fixup (&inst
);
19604 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
19607 enum neon_shape rs
;
19608 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19609 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
19611 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
19613 struct neon_type_el et
= neon_check_type (2, rs
,
19614 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19616 unsigned op
= (inst
.instruction
>> 7) & 3;
19617 /* N (width of reversed regions) is encoded as part of the bitmask. We
19618 extract it here to check the elements to be reversed are smaller.
19619 Otherwise we'd get a reserved instruction. */
19620 unsigned elsize
= (op
== 2) ? 16 : (op
== 1) ? 32 : (op
== 0) ? 64 : 0;
19622 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
) && elsize
== 64
19623 && inst
.operands
[0].reg
== inst
.operands
[1].reg
)
19624 as_tsktsk (_("Warning: 64-bit element size and same destination and source"
19625 " operands makes instruction UNPREDICTABLE"));
19627 gas_assert (elsize
!= 0);
19628 constraint (et
.size
>= elsize
,
19629 _("elements must be smaller than reversal region"));
19630 neon_two_same (neon_quad (rs
), 1, et
.size
);
19636 if (inst
.operands
[1].isscalar
)
19638 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19640 enum neon_shape rs
= neon_select_shape (NS_DS
, NS_QS
, NS_NULL
);
19641 struct neon_type_el et
= neon_check_type (2, rs
,
19642 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
19643 unsigned sizebits
= et
.size
>> 3;
19644 unsigned dm
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19645 int logsize
= neon_logbits (et
.size
);
19646 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
) << logsize
;
19648 if (vfp_or_neon_is_neon (NEON_CHECK_CC
) == FAIL
)
19651 NEON_ENCODE (SCALAR
, inst
);
19652 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19653 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19654 inst
.instruction
|= LOW4 (dm
);
19655 inst
.instruction
|= HI1 (dm
) << 5;
19656 inst
.instruction
|= neon_quad (rs
) << 6;
19657 inst
.instruction
|= x
<< 17;
19658 inst
.instruction
|= sizebits
<< 16;
19660 neon_dp_fixup (&inst
);
19664 enum neon_shape rs
= neon_select_shape (NS_DR
, NS_QR
, NS_NULL
);
19665 struct neon_type_el et
= neon_check_type (2, rs
,
19666 N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19669 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
))
19673 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_v1
),
19676 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19678 if (inst
.operands
[1].reg
== REG_SP
)
19679 as_tsktsk (MVE_BAD_SP
);
19680 else if (inst
.operands
[1].reg
== REG_PC
)
19681 as_tsktsk (MVE_BAD_PC
);
19684 /* Duplicate ARM register to lanes of vector. */
19685 NEON_ENCODE (ARMREG
, inst
);
19688 case 8: inst
.instruction
|= 0x400000; break;
19689 case 16: inst
.instruction
|= 0x000020; break;
19690 case 32: inst
.instruction
|= 0x000000; break;
19693 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
19694 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 16;
19695 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 7;
19696 inst
.instruction
|= neon_quad (rs
) << 21;
19697 /* The encoding for this instruction is identical for the ARM and Thumb
19698 variants, except for the condition field. */
19699 do_vfp_cond_or_thumb ();
19704 do_mve_mov (int toQ
)
19706 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19708 if (inst
.cond
> COND_ALWAYS
)
19709 inst
.pred_insn_type
= MVE_UNPREDICABLE_INSN
;
19711 unsigned Rt
= 0, Rt2
= 1, Q0
= 2, Q1
= 3;
19720 constraint (inst
.operands
[Q0
].reg
!= inst
.operands
[Q1
].reg
+ 2,
19721 _("Index one must be [2,3] and index two must be two less than"
19723 constraint (inst
.operands
[Rt
].reg
== inst
.operands
[Rt2
].reg
,
19724 _("General purpose registers may not be the same"));
19725 constraint (inst
.operands
[Rt
].reg
== REG_SP
19726 || inst
.operands
[Rt2
].reg
== REG_SP
,
19728 constraint (inst
.operands
[Rt
].reg
== REG_PC
19729 || inst
.operands
[Rt2
].reg
== REG_PC
,
19732 inst
.instruction
= 0xec000f00;
19733 inst
.instruction
|= HI1 (inst
.operands
[Q1
].reg
/ 32) << 23;
19734 inst
.instruction
|= !!toQ
<< 20;
19735 inst
.instruction
|= inst
.operands
[Rt2
].reg
<< 16;
19736 inst
.instruction
|= LOW4 (inst
.operands
[Q1
].reg
/ 32) << 13;
19737 inst
.instruction
|= (inst
.operands
[Q1
].reg
% 4) << 4;
19738 inst
.instruction
|= inst
.operands
[Rt
].reg
;
19744 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19747 if (inst
.cond
> COND_ALWAYS
)
19748 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
19750 inst
.pred_insn_type
= MVE_OUTSIDE_PRED_INSN
;
19752 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_I16
| N_I32
19755 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19756 inst
.instruction
|= (neon_logbits (et
.size
) - 1) << 18;
19757 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19758 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19759 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19764 /* VMOV has particularly many variations. It can be one of:
19765 0. VMOV<c><q> <Qd>, <Qm>
19766 1. VMOV<c><q> <Dd>, <Dm>
19767 (Register operations, which are VORR with Rm = Rn.)
19768 2. VMOV<c><q>.<dt> <Qd>, #<imm>
19769 3. VMOV<c><q>.<dt> <Dd>, #<imm>
19771 4. VMOV<c><q>.<size> <Dn[x]>, <Rd>
19772 (ARM register to scalar.)
19773 5. VMOV<c><q> <Dm>, <Rd>, <Rn>
19774 (Two ARM registers to vector.)
19775 6. VMOV<c><q>.<dt> <Rd>, <Dn[x]>
19776 (Scalar to ARM register.)
19777 7. VMOV<c><q> <Rd>, <Rn>, <Dm>
19778 (Vector to two ARM registers.)
19779 8. VMOV.F32 <Sd>, <Sm>
19780 9. VMOV.F64 <Dd>, <Dm>
19781 (VFP register moves.)
19782 10. VMOV.F32 <Sd>, #imm
19783 11. VMOV.F64 <Dd>, #imm
19784 (VFP float immediate load.)
19785 12. VMOV <Rd>, <Sm>
19786 (VFP single to ARM reg.)
19787 13. VMOV <Sd>, <Rm>
19788 (ARM reg to VFP single.)
19789 14. VMOV <Rd>, <Re>, <Sn>, <Sm>
19790 (Two ARM regs to two VFP singles.)
19791 15. VMOV <Sd>, <Se>, <Rn>, <Rm>
19792 (Two VFP singles to two ARM regs.)
19793 16. VMOV<c> <Rt>, <Rt2>, <Qd[idx]>, <Qd[idx2]>
19794 17. VMOV<c> <Qd[idx]>, <Qd[idx2]>, <Rt>, <Rt2>
19795 18. VMOV<c>.<dt> <Rt>, <Qn[idx]>
19796 19. VMOV<c>.<dt> <Qd[idx]>, <Rt>
19798 These cases can be disambiguated using neon_select_shape, except cases 1/9
19799 and 3/11 which depend on the operand type too.
19801 All the encoded bits are hardcoded by this function.
19803 Cases 4, 6 may be used with VFPv1 and above (only 32-bit transfers!).
19804 Cases 5, 7 may be used with VFPv2 and above.
19806 FIXME: Some of the checking may be a bit sloppy (in a couple of cases you
19807 can specify a type where it doesn't make sense to, and is ignored). */
19812 enum neon_shape rs
= neon_select_shape (NS_RRSS
, NS_SSRR
, NS_RRFF
, NS_FFRR
,
19813 NS_DRR
, NS_RRD
, NS_QQ
, NS_DD
, NS_QI
,
19814 NS_DI
, NS_SR
, NS_RS
, NS_FF
, NS_FI
,
19815 NS_RF
, NS_FR
, NS_HR
, NS_RH
, NS_HI
,
19817 struct neon_type_el et
;
19818 const char *ldconst
= 0;
19822 case NS_DD
: /* case 1/9. */
19823 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19824 /* It is not an error here if no type is given. */
19826 if (et
.type
== NT_float
&& et
.size
== 64)
19828 do_vfp_nsyn_opcode ("fcpyd");
19831 /* fall through. */
19833 case NS_QQ
: /* case 0/1. */
19835 if (!check_simd_pred_availability (FALSE
,
19836 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19838 /* The architecture manual I have doesn't explicitly state which
19839 value the U bit should have for register->register moves, but
19840 the equivalent VORR instruction has U = 0, so do that. */
19841 inst
.instruction
= 0x0200110;
19842 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
19843 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
19844 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
19845 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
19846 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
19847 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
19848 inst
.instruction
|= neon_quad (rs
) << 6;
19850 neon_dp_fixup (&inst
);
19854 case NS_DI
: /* case 3/11. */
19855 et
= neon_check_type (2, rs
, N_EQK
, N_F64
| N_KEY
);
19857 if (et
.type
== NT_float
&& et
.size
== 64)
19859 /* case 11 (fconstd). */
19860 ldconst
= "fconstd";
19861 goto encode_fconstd
;
19863 /* fall through. */
19865 case NS_QI
: /* case 2/3. */
19866 if (!check_simd_pred_availability (FALSE
,
19867 NEON_CHECK_CC
| NEON_CHECK_ARCH
))
19869 inst
.instruction
= 0x0800010;
19870 neon_move_immediate ();
19871 neon_dp_fixup (&inst
);
19874 case NS_SR
: /* case 4. */
19876 unsigned bcdebits
= 0;
19878 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[0].reg
);
19879 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[0].reg
);
19881 /* .<size> is optional here, defaulting to .32. */
19882 if (inst
.vectype
.elems
== 0
19883 && inst
.operands
[0].vectype
.type
== NT_invtype
19884 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19886 inst
.vectype
.el
[0].type
= NT_untyped
;
19887 inst
.vectype
.el
[0].size
= 32;
19888 inst
.vectype
.elems
= 1;
19891 et
= neon_check_type (2, NS_NULL
, N_8
| N_16
| N_32
| N_KEY
, N_EQK
);
19892 logsize
= neon_logbits (et
.size
);
19896 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19897 && vfp_or_neon_is_neon (NEON_CHECK_ARCH
) == FAIL
)
19902 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19903 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19907 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19909 if (inst
.operands
[1].reg
== REG_SP
)
19910 as_tsktsk (MVE_BAD_SP
);
19911 else if (inst
.operands
[1].reg
== REG_PC
)
19912 as_tsktsk (MVE_BAD_PC
);
19914 unsigned size
= inst
.operands
[0].isscalar
== 1 ? 64 : 128;
19916 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
19917 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
19922 case 8: bcdebits
= 0x8; break;
19923 case 16: bcdebits
= 0x1; break;
19924 case 32: bcdebits
= 0x0; break;
19928 bcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
19930 inst
.instruction
= 0xe000b10;
19931 do_vfp_cond_or_thumb ();
19932 inst
.instruction
|= LOW4 (dn
) << 16;
19933 inst
.instruction
|= HI1 (dn
) << 7;
19934 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19935 inst
.instruction
|= (bcdebits
& 3) << 5;
19936 inst
.instruction
|= ((bcdebits
>> 2) & 3) << 21;
19937 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
19941 case NS_DRR
: /* case 5 (fmdrr). */
19942 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
19943 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19946 inst
.instruction
= 0xc400b10;
19947 do_vfp_cond_or_thumb ();
19948 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
);
19949 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 5;
19950 inst
.instruction
|= inst
.operands
[1].reg
<< 12;
19951 inst
.instruction
|= inst
.operands
[2].reg
<< 16;
19954 case NS_RS
: /* case 6. */
19957 unsigned dn
= NEON_SCALAR_REG (inst
.operands
[1].reg
);
19958 unsigned x
= NEON_SCALAR_INDEX (inst
.operands
[1].reg
);
19959 unsigned abcdebits
= 0;
19961 /* .<dt> is optional here, defaulting to .32. */
19962 if (inst
.vectype
.elems
== 0
19963 && inst
.operands
[0].vectype
.type
== NT_invtype
19964 && inst
.operands
[1].vectype
.type
== NT_invtype
)
19966 inst
.vectype
.el
[0].type
= NT_untyped
;
19967 inst
.vectype
.el
[0].size
= 32;
19968 inst
.vectype
.elems
= 1;
19971 et
= neon_check_type (2, NS_NULL
,
19972 N_EQK
, N_S8
| N_S16
| N_U8
| N_U16
| N_32
| N_KEY
);
19973 logsize
= neon_logbits (et
.size
);
19977 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
19978 && vfp_or_neon_is_neon (NEON_CHECK_CC
19979 | NEON_CHECK_ARCH
) == FAIL
)
19984 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v1
)
19985 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
19989 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
19991 if (inst
.operands
[0].reg
== REG_SP
)
19992 as_tsktsk (MVE_BAD_SP
);
19993 else if (inst
.operands
[0].reg
== REG_PC
)
19994 as_tsktsk (MVE_BAD_PC
);
19997 unsigned size
= inst
.operands
[1].isscalar
== 1 ? 64 : 128;
19999 constraint (et
.type
== NT_invtype
, _("bad type for scalar"));
20000 constraint (x
>= size
/ et
.size
, _("scalar index out of range"));
20004 case 8: abcdebits
= (et
.type
== NT_signed
) ? 0x08 : 0x18; break;
20005 case 16: abcdebits
= (et
.type
== NT_signed
) ? 0x01 : 0x11; break;
20006 case 32: abcdebits
= 0x00; break;
20010 abcdebits
|= (x
& ((1 << (3-logsize
)) - 1)) << logsize
;
20011 inst
.instruction
= 0xe100b10;
20012 do_vfp_cond_or_thumb ();
20013 inst
.instruction
|= LOW4 (dn
) << 16;
20014 inst
.instruction
|= HI1 (dn
) << 7;
20015 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20016 inst
.instruction
|= (abcdebits
& 3) << 5;
20017 inst
.instruction
|= (abcdebits
>> 2) << 21;
20018 inst
.instruction
|= (x
>> (3-logsize
)) << 16;
20022 case NS_RRD
: /* case 7 (fmrrd). */
20023 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20024 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20027 inst
.instruction
= 0xc500b10;
20028 do_vfp_cond_or_thumb ();
20029 inst
.instruction
|= inst
.operands
[0].reg
<< 12;
20030 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20031 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20032 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20035 case NS_FF
: /* case 8 (fcpys). */
20036 do_vfp_nsyn_opcode ("fcpys");
20040 case NS_FI
: /* case 10 (fconsts). */
20041 ldconst
= "fconsts";
20043 if (!inst
.operands
[1].immisfloat
)
20046 /* Immediate has to fit in 8 bits so float is enough. */
20047 float imm
= (float) inst
.operands
[1].imm
;
20048 memcpy (&new_imm
, &imm
, sizeof (float));
20049 /* But the assembly may have been written to provide an integer
20050 bit pattern that equates to a float, so check that the
20051 conversion has worked. */
20052 if (is_quarter_float (new_imm
))
20054 if (is_quarter_float (inst
.operands
[1].imm
))
20055 as_warn (_("immediate constant is valid both as a bit-pattern and a floating point value (using the fp value)"));
20057 inst
.operands
[1].imm
= new_imm
;
20058 inst
.operands
[1].immisfloat
= 1;
20062 if (is_quarter_float (inst
.operands
[1].imm
))
20064 inst
.operands
[1].imm
= neon_qfloat_bits (inst
.operands
[1].imm
);
20065 do_vfp_nsyn_opcode (ldconst
);
20067 /* ARMv8.2 fp16 vmov.f16 instruction. */
20069 do_scalar_fp16_v82_encode ();
20072 first_error (_("immediate out of range"));
20076 case NS_RF
: /* case 12 (fmrs). */
20077 do_vfp_nsyn_opcode ("fmrs");
20078 /* ARMv8.2 fp16 vmov.f16 instruction. */
20080 do_scalar_fp16_v82_encode ();
20084 case NS_FR
: /* case 13 (fmsr). */
20085 do_vfp_nsyn_opcode ("fmsr");
20086 /* ARMv8.2 fp16 vmov.f16 instruction. */
20088 do_scalar_fp16_v82_encode ();
20098 /* The encoders for the fmrrs and fmsrr instructions expect three operands
20099 (one of which is a list), but we have parsed four. Do some fiddling to
20100 make the operands what do_vfp_reg2_from_sp2 and do_vfp_sp2_from_reg2
20102 case NS_RRFF
: /* case 14 (fmrrs). */
20103 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20104 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20106 constraint (inst
.operands
[3].reg
!= inst
.operands
[2].reg
+ 1,
20107 _("VFP registers must be adjacent"));
20108 inst
.operands
[2].imm
= 2;
20109 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20110 do_vfp_nsyn_opcode ("fmrrs");
20113 case NS_FFRR
: /* case 15 (fmsrr). */
20114 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_v2
)
20115 && !ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
),
20117 constraint (inst
.operands
[1].reg
!= inst
.operands
[0].reg
+ 1,
20118 _("VFP registers must be adjacent"));
20119 inst
.operands
[1] = inst
.operands
[2];
20120 inst
.operands
[2] = inst
.operands
[3];
20121 inst
.operands
[0].imm
= 2;
20122 memset (&inst
.operands
[3], '\0', sizeof (inst
.operands
[3]));
20123 do_vfp_nsyn_opcode ("fmsrr");
20127 /* neon_select_shape has determined that the instruction
20128 shape is wrong and has already set the error message. */
20139 if (!(inst
.operands
[0].present
&& inst
.operands
[0].isquad
20140 && inst
.operands
[1].present
&& inst
.operands
[1].isquad
20141 && !inst
.operands
[2].present
))
20143 inst
.instruction
= 0;
20146 set_pred_insn_type (INSIDE_IT_INSN
);
20151 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20154 if (inst
.cond
!= COND_ALWAYS
)
20155 inst
.pred_insn_type
= INSIDE_VPT_INSN
;
20157 struct neon_type_el et
= neon_check_type (2, NS_QQ
, N_EQK
, N_S8
| N_U8
20158 | N_S16
| N_U16
| N_KEY
);
20160 inst
.instruction
|= (et
.type
== NT_unsigned
) << 28;
20161 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20162 inst
.instruction
|= (neon_logbits (et
.size
) + 1) << 19;
20163 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20164 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20165 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20170 do_neon_rshift_round_imm (void)
20172 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20175 enum neon_shape rs
;
20176 struct neon_type_el et
;
20178 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20180 rs
= neon_select_shape (NS_QQI
, NS_NULL
);
20181 et
= neon_check_type (2, rs
, N_EQK
, N_SU_MVE
| N_KEY
);
20185 rs
= neon_select_shape (NS_DDI
, NS_QQI
, NS_NULL
);
20186 et
= neon_check_type (2, rs
, N_EQK
, N_SU_ALL
| N_KEY
);
20188 int imm
= inst
.operands
[2].imm
;
20190 /* imm == 0 case is encoded as VMOV for V{R}SHR. */
20193 inst
.operands
[2].present
= 0;
20198 constraint (imm
< 1 || (unsigned)imm
> et
.size
,
20199 _("immediate out of range for shift"));
20200 neon_imm_shift (TRUE
, et
.type
== NT_unsigned
, neon_quad (rs
), et
,
20205 do_neon_movhf (void)
20207 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_NULL
);
20208 constraint (rs
!= NS_HH
, _("invalid suffix"));
20210 if (inst
.cond
!= COND_ALWAYS
)
20214 as_warn (_("ARMv8.2 scalar fp16 instruction cannot be conditional,"
20215 " the behaviour is UNPREDICTABLE"));
20219 inst
.error
= BAD_COND
;
20224 do_vfp_sp_monadic ();
20227 inst
.instruction
|= 0xf0000000;
20231 do_neon_movl (void)
20233 struct neon_type_el et
= neon_check_type (2, NS_QD
,
20234 N_EQK
| N_DBL
, N_SU_32
| N_KEY
);
20235 unsigned sizebits
= et
.size
>> 3;
20236 inst
.instruction
|= sizebits
<< 19;
20237 neon_two_same (0, et
.type
== NT_unsigned
, -1);
20243 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20244 struct neon_type_el et
= neon_check_type (2, rs
,
20245 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20246 NEON_ENCODE (INTEGER
, inst
);
20247 neon_two_same (neon_quad (rs
), 1, et
.size
);
20251 do_neon_zip_uzp (void)
20253 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20254 struct neon_type_el et
= neon_check_type (2, rs
,
20255 N_EQK
, N_8
| N_16
| N_32
| N_KEY
);
20256 if (rs
== NS_DD
&& et
.size
== 32)
20258 /* Special case: encode as VTRN.32 <Dd>, <Dm>. */
20259 inst
.instruction
= N_MNEM_vtrn
;
20263 neon_two_same (neon_quad (rs
), 1, et
.size
);
20267 do_neon_sat_abs_neg (void)
20269 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_CC
| NEON_CHECK_ARCH
))
20272 enum neon_shape rs
;
20273 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20274 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20276 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20277 struct neon_type_el et
= neon_check_type (2, rs
,
20278 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20279 neon_two_same (neon_quad (rs
), 1, et
.size
);
20283 do_neon_pair_long (void)
20285 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20286 struct neon_type_el et
= neon_check_type (2, rs
, N_EQK
, N_SU_32
| N_KEY
);
20287 /* Unsigned is encoded in OP field (bit 7) for these instruction. */
20288 inst
.instruction
|= (et
.type
== NT_unsigned
) << 7;
20289 neon_two_same (neon_quad (rs
), 1, et
.size
);
20293 do_neon_recip_est (void)
20295 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20296 struct neon_type_el et
= neon_check_type (2, rs
,
20297 N_EQK
| N_FLT
, N_F_16_32
| N_U32
| N_KEY
);
20298 inst
.instruction
|= (et
.type
== NT_float
) << 8;
20299 neon_two_same (neon_quad (rs
), 1, et
.size
);
20305 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20308 enum neon_shape rs
;
20309 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20310 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20312 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20314 struct neon_type_el et
= neon_check_type (2, rs
,
20315 N_EQK
, N_S8
| N_S16
| N_S32
| N_KEY
);
20316 neon_two_same (neon_quad (rs
), 1, et
.size
);
20322 if (!check_simd_pred_availability (FALSE
, NEON_CHECK_ARCH
| NEON_CHECK_CC
))
20325 enum neon_shape rs
;
20326 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20327 rs
= neon_select_shape (NS_QQ
, NS_NULL
);
20329 rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20331 struct neon_type_el et
= neon_check_type (2, rs
,
20332 N_EQK
, N_I8
| N_I16
| N_I32
| N_KEY
);
20333 neon_two_same (neon_quad (rs
), 1, et
.size
);
20339 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20340 struct neon_type_el et
= neon_check_type (2, rs
,
20341 N_EQK
| N_INT
, N_8
| N_KEY
);
20342 neon_two_same (neon_quad (rs
), 1, et
.size
);
20348 enum neon_shape rs
= neon_select_shape (NS_DD
, NS_QQ
, NS_NULL
);
20349 neon_two_same (neon_quad (rs
), 1, -1);
20353 do_neon_tbl_tbx (void)
20355 unsigned listlenbits
;
20356 neon_check_type (3, NS_DLD
, N_EQK
, N_EQK
, N_8
| N_KEY
);
20358 if (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 4)
20360 first_error (_("bad list length for table lookup"));
20364 listlenbits
= inst
.operands
[1].imm
- 1;
20365 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20366 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20367 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
20368 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
20369 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
20370 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
20371 inst
.instruction
|= listlenbits
<< 8;
20373 neon_dp_fixup (&inst
);
20377 do_neon_ldm_stm (void)
20379 /* P, U and L bits are part of bitmask. */
20380 int is_dbmode
= (inst
.instruction
& (1 << 24)) != 0;
20381 unsigned offsetbits
= inst
.operands
[1].imm
* 2;
20383 if (inst
.operands
[1].issingle
)
20385 do_vfp_nsyn_ldm_stm (is_dbmode
);
20389 constraint (is_dbmode
&& !inst
.operands
[0].writeback
,
20390 _("writeback (!) must be used for VLDMDB and VSTMDB"));
20392 constraint (inst
.operands
[1].imm
< 1 || inst
.operands
[1].imm
> 16,
20393 _("register list must contain at least 1 and at most 16 "
20396 inst
.instruction
|= inst
.operands
[0].reg
<< 16;
20397 inst
.instruction
|= inst
.operands
[0].writeback
<< 21;
20398 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 12;
20399 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 22;
20401 inst
.instruction
|= offsetbits
;
20403 do_vfp_cond_or_thumb ();
20407 do_neon_ldr_str (void)
20409 int is_ldr
= (inst
.instruction
& (1 << 20)) != 0;
20411 /* Use of PC in vstr in ARM mode is deprecated in ARMv7.
20412 And is UNPREDICTABLE in thumb mode. */
20414 && inst
.operands
[1].reg
== REG_PC
20415 && (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v7
) || thumb_mode
))
20418 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20419 else if (warn_on_deprecated
)
20420 as_tsktsk (_("Use of PC here is deprecated"));
20423 if (inst
.operands
[0].issingle
)
20426 do_vfp_nsyn_opcode ("flds");
20428 do_vfp_nsyn_opcode ("fsts");
20430 /* ARMv8.2 vldr.16/vstr.16 instruction. */
20431 if (inst
.vectype
.el
[0].size
== 16)
20432 do_scalar_fp16_v82_encode ();
20437 do_vfp_nsyn_opcode ("fldd");
20439 do_vfp_nsyn_opcode ("fstd");
20444 do_t_vldr_vstr_sysreg (void)
20446 int fp_vldr_bitno
= 20, sysreg_vldr_bitno
= 20;
20447 bfd_boolean is_vldr
= ((inst
.instruction
& (1 << fp_vldr_bitno
)) != 0);
20449 /* Use of PC is UNPREDICTABLE. */
20450 if (inst
.operands
[1].reg
== REG_PC
)
20451 inst
.error
= _("Use of PC here is UNPREDICTABLE");
20453 if (inst
.operands
[1].immisreg
)
20454 inst
.error
= _("instruction does not accept register index");
20456 if (!inst
.operands
[1].isreg
)
20457 inst
.error
= _("instruction does not accept PC-relative addressing");
20459 if (abs (inst
.operands
[1].imm
) >= (1 << 7))
20460 inst
.error
= _("immediate value out of range");
20462 inst
.instruction
= 0xec000f80;
20464 inst
.instruction
|= 1 << sysreg_vldr_bitno
;
20465 encode_arm_cp_address (1, TRUE
, FALSE
, BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
);
20466 inst
.instruction
|= (inst
.operands
[0].imm
& 0x7) << 13;
20467 inst
.instruction
|= (inst
.operands
[0].imm
& 0x8) << 19;
20471 do_vldr_vstr (void)
20473 bfd_boolean sysreg_op
= !inst
.operands
[0].isreg
;
20475 /* VLDR/VSTR (System Register). */
20478 if (!mark_feature_used (&arm_ext_v8_1m_main
))
20479 as_bad (_("Instruction not permitted on this architecture"));
20481 do_t_vldr_vstr_sysreg ();
20486 if (!mark_feature_used (&fpu_vfp_ext_v1xd
))
20487 as_bad (_("Instruction not permitted on this architecture"));
20488 do_neon_ldr_str ();
20492 /* "interleave" version also handles non-interleaving register VLD1/VST1
20496 do_neon_ld_st_interleave (void)
20498 struct neon_type_el et
= neon_check_type (1, NS_NULL
,
20499 N_8
| N_16
| N_32
| N_64
);
20500 unsigned alignbits
= 0;
20502 /* The bits in this table go:
20503 0: register stride of one (0) or two (1)
20504 1,2: register list length, minus one (1, 2, 3, 4).
20505 3,4: <n> in instruction type, minus one (VLD<n> / VST<n>).
20506 We use -1 for invalid entries. */
20507 const int typetable
[] =
20509 0x7, -1, 0xa, -1, 0x6, -1, 0x2, -1, /* VLD1 / VST1. */
20510 -1, -1, 0x8, 0x9, -1, -1, 0x3, -1, /* VLD2 / VST2. */
20511 -1, -1, -1, -1, 0x4, 0x5, -1, -1, /* VLD3 / VST3. */
20512 -1, -1, -1, -1, -1, -1, 0x0, 0x1 /* VLD4 / VST4. */
20516 if (et
.type
== NT_invtype
)
20519 if (inst
.operands
[1].immisalign
)
20520 switch (inst
.operands
[1].imm
>> 8)
20522 case 64: alignbits
= 1; break;
20524 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2
20525 && NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20526 goto bad_alignment
;
20530 if (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4)
20531 goto bad_alignment
;
20536 first_error (_("bad alignment"));
20540 inst
.instruction
|= alignbits
<< 4;
20541 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20543 /* Bits [4:6] of the immediate in a list specifier encode register stride
20544 (minus 1) in bit 4, and list length in bits [5:6]. We put the <n> of
20545 VLD<n>/VST<n> in bits [9:8] of the initial bitmask. Suck it out here, look
20546 up the right value for "type" in a table based on this value and the given
20547 list style, then stick it back. */
20548 idx
= ((inst
.operands
[0].imm
>> 4) & 7)
20549 | (((inst
.instruction
>> 8) & 3) << 3);
20551 typebits
= typetable
[idx
];
20553 constraint (typebits
== -1, _("bad list type for instruction"));
20554 constraint (((inst
.instruction
>> 8) & 3) && et
.size
== 64,
20557 inst
.instruction
&= ~0xf00;
20558 inst
.instruction
|= typebits
<< 8;
20561 /* Check alignment is valid for do_neon_ld_st_lane and do_neon_ld_dup.
20562 *DO_ALIGN is set to 1 if the relevant alignment bit should be set, 0
20563 otherwise. The variable arguments are a list of pairs of legal (size, align)
20564 values, terminated with -1. */
20567 neon_alignment_bit (int size
, int align
, int *do_alignment
, ...)
20570 int result
= FAIL
, thissize
, thisalign
;
20572 if (!inst
.operands
[1].immisalign
)
20578 va_start (ap
, do_alignment
);
20582 thissize
= va_arg (ap
, int);
20583 if (thissize
== -1)
20585 thisalign
= va_arg (ap
, int);
20587 if (size
== thissize
&& align
== thisalign
)
20590 while (result
!= SUCCESS
);
20594 if (result
== SUCCESS
)
20597 first_error (_("unsupported alignment for instruction"));
20603 do_neon_ld_st_lane (void)
20605 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20606 int align_good
, do_alignment
= 0;
20607 int logsize
= neon_logbits (et
.size
);
20608 int align
= inst
.operands
[1].imm
>> 8;
20609 int n
= (inst
.instruction
>> 8) & 3;
20610 int max_el
= 64 / et
.size
;
20612 if (et
.type
== NT_invtype
)
20615 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != n
+ 1,
20616 _("bad list length"));
20617 constraint (NEON_LANE (inst
.operands
[0].imm
) >= max_el
,
20618 _("scalar index out of range"));
20619 constraint (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2
20621 _("stride of 2 unavailable when element size is 8"));
20625 case 0: /* VLD1 / VST1. */
20626 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 16, 16,
20628 if (align_good
== FAIL
)
20632 unsigned alignbits
= 0;
20635 case 16: alignbits
= 0x1; break;
20636 case 32: alignbits
= 0x3; break;
20639 inst
.instruction
|= alignbits
<< 4;
20643 case 1: /* VLD2 / VST2. */
20644 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 16,
20645 16, 32, 32, 64, -1);
20646 if (align_good
== FAIL
)
20649 inst
.instruction
|= 1 << 4;
20652 case 2: /* VLD3 / VST3. */
20653 constraint (inst
.operands
[1].immisalign
,
20654 _("can't use alignment with this instruction"));
20657 case 3: /* VLD4 / VST4. */
20658 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20659 16, 64, 32, 64, 32, 128, -1);
20660 if (align_good
== FAIL
)
20664 unsigned alignbits
= 0;
20667 case 8: alignbits
= 0x1; break;
20668 case 16: alignbits
= 0x1; break;
20669 case 32: alignbits
= (align
== 64) ? 0x1 : 0x2; break;
20672 inst
.instruction
|= alignbits
<< 4;
20679 /* Reg stride of 2 is encoded in bit 5 when size==16, bit 6 when size==32. */
20680 if (n
!= 0 && NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20681 inst
.instruction
|= 1 << (4 + logsize
);
20683 inst
.instruction
|= NEON_LANE (inst
.operands
[0].imm
) << (logsize
+ 5);
20684 inst
.instruction
|= logsize
<< 10;
20687 /* Encode single n-element structure to all lanes VLD<n> instructions. */
20690 do_neon_ld_dup (void)
20692 struct neon_type_el et
= neon_check_type (1, NS_NULL
, N_8
| N_16
| N_32
);
20693 int align_good
, do_alignment
= 0;
20695 if (et
.type
== NT_invtype
)
20698 switch ((inst
.instruction
>> 8) & 3)
20700 case 0: /* VLD1. */
20701 gas_assert (NEON_REG_STRIDE (inst
.operands
[0].imm
) != 2);
20702 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20703 &do_alignment
, 16, 16, 32, 32, -1);
20704 if (align_good
== FAIL
)
20706 switch (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
))
20709 case 2: inst
.instruction
|= 1 << 5; break;
20710 default: first_error (_("bad list length")); return;
20712 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20715 case 1: /* VLD2. */
20716 align_good
= neon_alignment_bit (et
.size
, inst
.operands
[1].imm
>> 8,
20717 &do_alignment
, 8, 16, 16, 32, 32, 64,
20719 if (align_good
== FAIL
)
20721 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 2,
20722 _("bad list length"));
20723 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20724 inst
.instruction
|= 1 << 5;
20725 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20728 case 2: /* VLD3. */
20729 constraint (inst
.operands
[1].immisalign
,
20730 _("can't use alignment with this instruction"));
20731 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 3,
20732 _("bad list length"));
20733 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20734 inst
.instruction
|= 1 << 5;
20735 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20738 case 3: /* VLD4. */
20740 int align
= inst
.operands
[1].imm
>> 8;
20741 align_good
= neon_alignment_bit (et
.size
, align
, &do_alignment
, 8, 32,
20742 16, 64, 32, 64, 32, 128, -1);
20743 if (align_good
== FAIL
)
20745 constraint (NEON_REGLIST_LENGTH (inst
.operands
[0].imm
) != 4,
20746 _("bad list length"));
20747 if (NEON_REG_STRIDE (inst
.operands
[0].imm
) == 2)
20748 inst
.instruction
|= 1 << 5;
20749 if (et
.size
== 32 && align
== 128)
20750 inst
.instruction
|= 0x3 << 6;
20752 inst
.instruction
|= neon_logbits (et
.size
) << 6;
20759 inst
.instruction
|= do_alignment
<< 4;
20762 /* Disambiguate VLD<n> and VST<n> instructions, and fill in common bits (those
20763 apart from bits [11:4]. */
20766 do_neon_ldx_stx (void)
20768 if (inst
.operands
[1].isreg
)
20769 constraint (inst
.operands
[1].reg
== REG_PC
, BAD_PC
);
20771 switch (NEON_LANE (inst
.operands
[0].imm
))
20773 case NEON_INTERLEAVE_LANES
:
20774 NEON_ENCODE (INTERLV
, inst
);
20775 do_neon_ld_st_interleave ();
20778 case NEON_ALL_LANES
:
20779 NEON_ENCODE (DUP
, inst
);
20780 if (inst
.instruction
== N_INV
)
20782 first_error ("only loads support such operands");
20789 NEON_ENCODE (LANE
, inst
);
20790 do_neon_ld_st_lane ();
20793 /* L bit comes from bit mask. */
20794 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20795 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20796 inst
.instruction
|= inst
.operands
[1].reg
<< 16;
20798 if (inst
.operands
[1].postind
)
20800 int postreg
= inst
.operands
[1].imm
& 0xf;
20801 constraint (!inst
.operands
[1].immisreg
,
20802 _("post-index must be a register"));
20803 constraint (postreg
== 0xd || postreg
== 0xf,
20804 _("bad register for post-index"));
20805 inst
.instruction
|= postreg
;
20809 constraint (inst
.operands
[1].immisreg
, BAD_ADDR_MODE
);
20810 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
20811 || inst
.relocs
[0].exp
.X_add_number
!= 0,
20814 if (inst
.operands
[1].writeback
)
20816 inst
.instruction
|= 0xd;
20819 inst
.instruction
|= 0xf;
20823 inst
.instruction
|= 0xf9000000;
20825 inst
.instruction
|= 0xf4000000;
20830 do_vfp_nsyn_fpv8 (enum neon_shape rs
)
20832 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20833 D register operands. */
20834 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20835 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20838 NEON_ENCODE (FPV8
, inst
);
20840 if (rs
== NS_FFF
|| rs
== NS_HHH
)
20842 do_vfp_sp_dyadic ();
20844 /* ARMv8.2 fp16 instruction. */
20846 do_scalar_fp16_v82_encode ();
20849 do_vfp_dp_rd_rn_rm ();
20852 inst
.instruction
|= 0x100;
20854 inst
.instruction
|= 0xf0000000;
20860 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20862 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) != SUCCESS
)
20863 first_error (_("invalid instruction shape"));
20869 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
20870 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20872 if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8
) == SUCCESS
)
20875 if (!check_simd_pred_availability (TRUE
, NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20878 neon_dyadic_misc (NT_untyped
, N_F_16_32
, 0);
20882 do_vrint_1 (enum neon_cvt_mode mode
)
20884 enum neon_shape rs
= neon_select_shape (NS_HH
, NS_FF
, NS_DD
, NS_QQ
, NS_NULL
);
20885 struct neon_type_el et
;
20890 /* Targets like FPv5-SP-D16 don't support FP v8 instructions with
20891 D register operands. */
20892 if (neon_shape_class
[rs
] == SC_DOUBLE
)
20893 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
20896 et
= neon_check_type (2, rs
, N_EQK
| N_VFP
, N_F_ALL
| N_KEY
20898 if (et
.type
!= NT_invtype
)
20900 /* VFP encodings. */
20901 if (mode
== neon_cvt_mode_a
|| mode
== neon_cvt_mode_n
20902 || mode
== neon_cvt_mode_p
|| mode
== neon_cvt_mode_m
)
20903 set_pred_insn_type (OUTSIDE_PRED_INSN
);
20905 NEON_ENCODE (FPV8
, inst
);
20906 if (rs
== NS_FF
|| rs
== NS_HH
)
20907 do_vfp_sp_monadic ();
20909 do_vfp_dp_rd_rm ();
20913 case neon_cvt_mode_r
: inst
.instruction
|= 0x00000000; break;
20914 case neon_cvt_mode_z
: inst
.instruction
|= 0x00000080; break;
20915 case neon_cvt_mode_x
: inst
.instruction
|= 0x00010000; break;
20916 case neon_cvt_mode_a
: inst
.instruction
|= 0xf0000000; break;
20917 case neon_cvt_mode_n
: inst
.instruction
|= 0xf0010000; break;
20918 case neon_cvt_mode_p
: inst
.instruction
|= 0xf0020000; break;
20919 case neon_cvt_mode_m
: inst
.instruction
|= 0xf0030000; break;
20923 inst
.instruction
|= (rs
== NS_DD
) << 8;
20924 do_vfp_cond_or_thumb ();
20926 /* ARMv8.2 fp16 vrint instruction. */
20928 do_scalar_fp16_v82_encode ();
20932 /* Neon encodings (or something broken...). */
20934 et
= neon_check_type (2, rs
, N_EQK
, N_F_16_32
| N_KEY
);
20936 if (et
.type
== NT_invtype
)
20939 if (!check_simd_pred_availability (TRUE
,
20940 NEON_CHECK_CC
| NEON_CHECK_ARCH8
))
20943 NEON_ENCODE (FLOAT
, inst
);
20945 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
20946 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
20947 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
20948 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
20949 inst
.instruction
|= neon_quad (rs
) << 6;
20950 /* Mask off the original size bits and reencode them. */
20951 inst
.instruction
= ((inst
.instruction
& 0xfff3ffff)
20952 | neon_logbits (et
.size
) << 18);
20956 case neon_cvt_mode_z
: inst
.instruction
|= 3 << 7; break;
20957 case neon_cvt_mode_x
: inst
.instruction
|= 1 << 7; break;
20958 case neon_cvt_mode_a
: inst
.instruction
|= 2 << 7; break;
20959 case neon_cvt_mode_n
: inst
.instruction
|= 0 << 7; break;
20960 case neon_cvt_mode_p
: inst
.instruction
|= 7 << 7; break;
20961 case neon_cvt_mode_m
: inst
.instruction
|= 5 << 7; break;
20962 case neon_cvt_mode_r
: inst
.error
= _("invalid rounding mode"); break;
20967 inst
.instruction
|= 0xfc000000;
20969 inst
.instruction
|= 0xf0000000;
20976 do_vrint_1 (neon_cvt_mode_x
);
20982 do_vrint_1 (neon_cvt_mode_z
);
20988 do_vrint_1 (neon_cvt_mode_r
);
20994 do_vrint_1 (neon_cvt_mode_a
);
21000 do_vrint_1 (neon_cvt_mode_n
);
21006 do_vrint_1 (neon_cvt_mode_p
);
21012 do_vrint_1 (neon_cvt_mode_m
);
21016 neon_scalar_for_vcmla (unsigned opnd
, unsigned elsize
)
21018 unsigned regno
= NEON_SCALAR_REG (opnd
);
21019 unsigned elno
= NEON_SCALAR_INDEX (opnd
);
21021 if (elsize
== 16 && elno
< 2 && regno
< 16)
21022 return regno
| (elno
<< 4);
21023 else if (elsize
== 32 && elno
== 0)
21026 first_error (_("scalar out of range"));
21033 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
)
21034 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21035 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21036 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21037 _("expression too complex"));
21038 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21039 constraint (rot
!= 0 && rot
!= 90 && rot
!= 180 && rot
!= 270,
21040 _("immediate out of range"));
21043 if (!check_simd_pred_availability (TRUE
,
21044 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21047 if (inst
.operands
[2].isscalar
)
21049 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21050 first_error (_("invalid instruction shape"));
21051 enum neon_shape rs
= neon_select_shape (NS_DDSI
, NS_QQSI
, NS_NULL
);
21052 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21053 N_KEY
| N_F16
| N_F32
).size
;
21054 unsigned m
= neon_scalar_for_vcmla (inst
.operands
[2].reg
, size
);
21056 inst
.instruction
= 0xfe000800;
21057 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21058 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21059 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21060 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21061 inst
.instruction
|= LOW4 (m
);
21062 inst
.instruction
|= HI1 (m
) << 5;
21063 inst
.instruction
|= neon_quad (rs
) << 6;
21064 inst
.instruction
|= rot
<< 20;
21065 inst
.instruction
|= (size
== 32) << 23;
21069 enum neon_shape rs
;
21070 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
))
21071 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21073 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21075 unsigned size
= neon_check_type (3, rs
, N_EQK
, N_EQK
,
21076 N_KEY
| N_F16
| N_F32
).size
;
21077 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_fp_ext
) && size
== 32
21078 && (inst
.operands
[0].reg
== inst
.operands
[1].reg
21079 || inst
.operands
[0].reg
== inst
.operands
[2].reg
))
21080 as_tsktsk (BAD_MVE_SRCDEST
);
21082 neon_three_same (neon_quad (rs
), 0, -1);
21083 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21084 inst
.instruction
|= 0xfc200800;
21085 inst
.instruction
|= rot
<< 23;
21086 inst
.instruction
|= (size
== 32) << 20;
21093 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
)
21094 && (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
)
21095 || !mark_feature_used (&arm_ext_v8_3
)), (BAD_FPU
));
21096 constraint (inst
.relocs
[0].exp
.X_op
!= O_constant
,
21097 _("expression too complex"));
21099 unsigned rot
= inst
.relocs
[0].exp
.X_add_number
;
21100 constraint (rot
!= 90 && rot
!= 270, _("immediate out of range"));
21101 enum neon_shape rs
;
21102 struct neon_type_el et
;
21103 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21105 rs
= neon_select_shape (NS_DDDI
, NS_QQQI
, NS_NULL
);
21106 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
);
21110 rs
= neon_select_shape (NS_QQQI
, NS_NULL
);
21111 et
= neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_F16
| N_F32
| N_I8
21113 if (et
.size
== 32 && inst
.operands
[0].reg
== inst
.operands
[2].reg
)
21114 as_tsktsk (_("Warning: 32-bit element size and same first and third "
21115 "operand makes instruction UNPREDICTABLE"));
21118 if (et
.type
== NT_invtype
)
21121 if (!check_simd_pred_availability (et
.type
== NT_float
,
21122 NEON_CHECK_ARCH8
| NEON_CHECK_CC
))
21125 if (et
.type
== NT_float
)
21127 neon_three_same (neon_quad (rs
), 0, -1);
21128 inst
.instruction
&= 0x00ffffff; /* Undo neon_dp_fixup. */
21129 inst
.instruction
|= 0xfc800800;
21130 inst
.instruction
|= (rot
== 270) << 24;
21131 inst
.instruction
|= (et
.size
== 32) << 20;
21135 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
), BAD_FPU
);
21136 inst
.instruction
= 0xfe000f00;
21137 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21138 inst
.instruction
|= neon_logbits (et
.size
) << 20;
21139 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
) << 16;
21140 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21141 inst
.instruction
|= (rot
== 270) << 12;
21142 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 7;
21143 inst
.instruction
|= HI1 (inst
.operands
[2].reg
) << 5;
21144 inst
.instruction
|= LOW4 (inst
.operands
[2].reg
);
21149 /* Dot Product instructions encoding support. */
21152 do_neon_dotproduct (int unsigned_p
)
21154 enum neon_shape rs
;
21155 unsigned scalar_oprd2
= 0;
21158 if (inst
.cond
!= COND_ALWAYS
)
21159 as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
21160 "is UNPREDICTABLE"));
21162 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_neon_ext_armv8
),
21165 /* Dot Product instructions are in three-same D/Q register format or the third
21166 operand can be a scalar index register. */
21167 if (inst
.operands
[2].isscalar
)
21169 scalar_oprd2
= neon_scalar_for_mul (inst
.operands
[2].reg
, 32);
21170 high8
= 0xfe000000;
21171 rs
= neon_select_shape (NS_DDS
, NS_QQS
, NS_NULL
);
21175 high8
= 0xfc000000;
21176 rs
= neon_select_shape (NS_DDD
, NS_QQQ
, NS_NULL
);
21180 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_U8
);
21182 neon_check_type (3, rs
, N_EQK
, N_EQK
, N_KEY
| N_S8
);
21184 /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
21185 Product instruction, so we pass 0 as the "ubit" parameter. And the
21186 "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
21187 neon_three_same (neon_quad (rs
), 0, 32);
21189 /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
21190 different NEON three-same encoding. */
21191 inst
.instruction
&= 0x00ffffff;
21192 inst
.instruction
|= high8
;
21193 /* Encode 'U' bit which indicates signedness. */
21194 inst
.instruction
|= (unsigned_p
? 1 : 0) << 4;
21195 /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
21196 from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
21197 the instruction encoding. */
21198 if (inst
.operands
[2].isscalar
)
21200 inst
.instruction
&= 0xffffffd0;
21201 inst
.instruction
|= LOW4 (scalar_oprd2
);
21202 inst
.instruction
|= HI1 (scalar_oprd2
) << 5;
21206 /* Dot Product instructions for signed integer. */
21209 do_neon_dotproduct_s (void)
21211 return do_neon_dotproduct (0);
21214 /* Dot Product instructions for unsigned integer. */
21217 do_neon_dotproduct_u (void)
21219 return do_neon_dotproduct (1);
21222 /* Crypto v1 instructions. */
21224 do_crypto_2op_1 (unsigned elttype
, int op
)
21226 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21228 if (neon_check_type (2, NS_QQ
, N_EQK
| N_UNT
, elttype
| N_UNT
| N_KEY
).type
21234 NEON_ENCODE (INTEGER
, inst
);
21235 inst
.instruction
|= LOW4 (inst
.operands
[0].reg
) << 12;
21236 inst
.instruction
|= HI1 (inst
.operands
[0].reg
) << 22;
21237 inst
.instruction
|= LOW4 (inst
.operands
[1].reg
);
21238 inst
.instruction
|= HI1 (inst
.operands
[1].reg
) << 5;
21240 inst
.instruction
|= op
<< 6;
21243 inst
.instruction
|= 0xfc000000;
21245 inst
.instruction
|= 0xf0000000;
21249 do_crypto_3op_1 (int u
, int op
)
21251 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21253 if (neon_check_type (3, NS_QQQ
, N_EQK
| N_UNT
, N_EQK
| N_UNT
,
21254 N_32
| N_UNT
| N_KEY
).type
== NT_invtype
)
21259 NEON_ENCODE (INTEGER
, inst
);
21260 neon_three_same (1, u
, 8 << op
);
21266 do_crypto_2op_1 (N_8
, 0);
21272 do_crypto_2op_1 (N_8
, 1);
21278 do_crypto_2op_1 (N_8
, 2);
21284 do_crypto_2op_1 (N_8
, 3);
21290 do_crypto_3op_1 (0, 0);
21296 do_crypto_3op_1 (0, 1);
21302 do_crypto_3op_1 (0, 2);
21308 do_crypto_3op_1 (0, 3);
21314 do_crypto_3op_1 (1, 0);
21320 do_crypto_3op_1 (1, 1);
21324 do_sha256su1 (void)
21326 do_crypto_3op_1 (1, 2);
21332 do_crypto_2op_1 (N_32
, -1);
21338 do_crypto_2op_1 (N_32
, 0);
21342 do_sha256su0 (void)
21344 do_crypto_2op_1 (N_32
, 1);
21348 do_crc32_1 (unsigned int poly
, unsigned int sz
)
21350 unsigned int Rd
= inst
.operands
[0].reg
;
21351 unsigned int Rn
= inst
.operands
[1].reg
;
21352 unsigned int Rm
= inst
.operands
[2].reg
;
21354 set_pred_insn_type (OUTSIDE_PRED_INSN
);
21355 inst
.instruction
|= LOW4 (Rd
) << (thumb_mode
? 8 : 12);
21356 inst
.instruction
|= LOW4 (Rn
) << 16;
21357 inst
.instruction
|= LOW4 (Rm
);
21358 inst
.instruction
|= sz
<< (thumb_mode
? 4 : 21);
21359 inst
.instruction
|= poly
<< (thumb_mode
? 20 : 9);
21361 if (Rd
== REG_PC
|| Rn
== REG_PC
|| Rm
== REG_PC
)
21362 as_warn (UNPRED_REG ("r15"));
21404 constraint (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_vfp_ext_armv8
),
21406 neon_check_type (2, NS_FD
, N_S32
, N_F64
);
21407 do_vfp_sp_dp_cvt ();
21408 do_vfp_cond_or_thumb ();
21412 /* Overall per-instruction processing. */
21414 /* We need to be able to fix up arbitrary expressions in some statements.
21415 This is so that we can handle symbols that are an arbitrary distance from
21416 the pc. The most common cases are of the form ((+/-sym -/+ . - 8) & mask),
21417 which returns part of an address in a form which will be valid for
21418 a data instruction. We do this by pushing the expression into a symbol
21419 in the expr_section, and creating a fix for that. */
21422 fix_new_arm (fragS
* frag
,
21436 /* Create an absolute valued symbol, so we have something to
21437 refer to in the object file. Unfortunately for us, gas's
21438 generic expression parsing will already have folded out
21439 any use of .set foo/.type foo %function that may have
21440 been used to set type information of the target location,
21441 that's being specified symbolically. We have to presume
21442 the user knows what they are doing. */
21446 sprintf (name
, "*ABS*0x%lx", (unsigned long)exp
->X_add_number
);
21448 symbol
= symbol_find_or_make (name
);
21449 S_SET_SEGMENT (symbol
, absolute_section
);
21450 symbol_set_frag (symbol
, &zero_address_frag
);
21451 S_SET_VALUE (symbol
, exp
->X_add_number
);
21452 exp
->X_op
= O_symbol
;
21453 exp
->X_add_symbol
= symbol
;
21454 exp
->X_add_number
= 0;
21460 new_fix
= fix_new_exp (frag
, where
, size
, exp
, pc_rel
,
21461 (enum bfd_reloc_code_real
) reloc
);
21465 new_fix
= (fixS
*) fix_new (frag
, where
, size
, make_expr_symbol (exp
), 0,
21466 pc_rel
, (enum bfd_reloc_code_real
) reloc
);
21470 /* Mark whether the fix is to a THUMB instruction, or an ARM
21472 new_fix
->tc_fix_data
= thumb_mode
;
21475 /* Create a frg for an instruction requiring relaxation. */
21477 output_relax_insn (void)
21483 /* The size of the instruction is unknown, so tie the debug info to the
21484 start of the instruction. */
21485 dwarf2_emit_insn (0);
21487 switch (inst
.relocs
[0].exp
.X_op
)
21490 sym
= inst
.relocs
[0].exp
.X_add_symbol
;
21491 offset
= inst
.relocs
[0].exp
.X_add_number
;
21495 offset
= inst
.relocs
[0].exp
.X_add_number
;
21498 sym
= make_expr_symbol (&inst
.relocs
[0].exp
);
21502 to
= frag_var (rs_machine_dependent
, INSN_SIZE
, THUMB_SIZE
,
21503 inst
.relax
, sym
, offset
, NULL
/*offset, opcode*/);
21504 md_number_to_chars (to
, inst
.instruction
, THUMB_SIZE
);
21507 /* Write a 32-bit thumb instruction to buf. */
21509 put_thumb32_insn (char * buf
, unsigned long insn
)
21511 md_number_to_chars (buf
, insn
>> 16, THUMB_SIZE
);
21512 md_number_to_chars (buf
+ THUMB_SIZE
, insn
, THUMB_SIZE
);
21516 output_inst (const char * str
)
21522 as_bad ("%s -- `%s'", inst
.error
, str
);
21527 output_relax_insn ();
21530 if (inst
.size
== 0)
21533 to
= frag_more (inst
.size
);
21534 /* PR 9814: Record the thumb mode into the current frag so that we know
21535 what type of NOP padding to use, if necessary. We override any previous
21536 setting so that if the mode has changed then the NOPS that we use will
21537 match the encoding of the last instruction in the frag. */
21538 frag_now
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
21540 if (thumb_mode
&& (inst
.size
> THUMB_SIZE
))
21542 gas_assert (inst
.size
== (2 * THUMB_SIZE
));
21543 put_thumb32_insn (to
, inst
.instruction
);
21545 else if (inst
.size
> INSN_SIZE
)
21547 gas_assert (inst
.size
== (2 * INSN_SIZE
));
21548 md_number_to_chars (to
, inst
.instruction
, INSN_SIZE
);
21549 md_number_to_chars (to
+ INSN_SIZE
, inst
.instruction
, INSN_SIZE
);
21552 md_number_to_chars (to
, inst
.instruction
, inst
.size
);
21555 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
21557 if (inst
.relocs
[r
].type
!= BFD_RELOC_UNUSED
)
21558 fix_new_arm (frag_now
, to
- frag_now
->fr_literal
,
21559 inst
.size
, & inst
.relocs
[r
].exp
, inst
.relocs
[r
].pc_rel
,
21560 inst
.relocs
[r
].type
);
21563 dwarf2_emit_insn (inst
.size
);
21567 output_it_inst (int cond
, int mask
, char * to
)
21569 unsigned long instruction
= 0xbf00;
21572 instruction
|= mask
;
21573 instruction
|= cond
<< 4;
21577 to
= frag_more (2);
21579 dwarf2_emit_insn (2);
21583 md_number_to_chars (to
, instruction
, 2);
21588 /* Tag values used in struct asm_opcode's tag field. */
21591 OT_unconditional
, /* Instruction cannot be conditionalized.
21592 The ARM condition field is still 0xE. */
21593 OT_unconditionalF
, /* Instruction cannot be conditionalized
21594 and carries 0xF in its ARM condition field. */
21595 OT_csuffix
, /* Instruction takes a conditional suffix. */
21596 OT_csuffixF
, /* Some forms of the instruction take a scalar
21597 conditional suffix, others place 0xF where the
21598 condition field would be, others take a vector
21599 conditional suffix. */
21600 OT_cinfix3
, /* Instruction takes a conditional infix,
21601 beginning at character index 3. (In
21602 unified mode, it becomes a suffix.) */
21603 OT_cinfix3_deprecated
, /* The same as OT_cinfix3. This is used for
21604 tsts, cmps, cmns, and teqs. */
21605 OT_cinfix3_legacy
, /* Legacy instruction takes a conditional infix at
21606 character index 3, even in unified mode. Used for
21607 legacy instructions where suffix and infix forms
21608 may be ambiguous. */
21609 OT_csuf_or_in3
, /* Instruction takes either a conditional
21610 suffix or an infix at character index 3. */
21611 OT_odd_infix_unc
, /* This is the unconditional variant of an
21612 instruction that takes a conditional infix
21613 at an unusual position. In unified mode,
21614 this variant will accept a suffix. */
21615 OT_odd_infix_0
/* Values greater than or equal to OT_odd_infix_0
21616 are the conditional variants of instructions that
21617 take conditional infixes in unusual positions.
21618 The infix appears at character index
21619 (tag - OT_odd_infix_0). These are not accepted
21620 in unified mode. */
21623 /* Subroutine of md_assemble, responsible for looking up the primary
21624 opcode from the mnemonic the user wrote. STR points to the
21625 beginning of the mnemonic.
21627 This is not simply a hash table lookup, because of conditional
21628 variants. Most instructions have conditional variants, which are
21629 expressed with a _conditional affix_ to the mnemonic. If we were
21630 to encode each conditional variant as a literal string in the opcode
21631 table, it would have approximately 20,000 entries.
21633 Most mnemonics take this affix as a suffix, and in unified syntax,
21634 'most' is upgraded to 'all'. However, in the divided syntax, some
21635 instructions take the affix as an infix, notably the s-variants of
21636 the arithmetic instructions. Of those instructions, all but six
21637 have the infix appear after the third character of the mnemonic.
21639 Accordingly, the algorithm for looking up primary opcodes given
21642 1. Look up the identifier in the opcode table.
21643 If we find a match, go to step U.
21645 2. Look up the last two characters of the identifier in the
21646 conditions table. If we find a match, look up the first N-2
21647 characters of the identifier in the opcode table. If we
21648 find a match, go to step CE.
21650 3. Look up the fourth and fifth characters of the identifier in
21651 the conditions table. If we find a match, extract those
21652 characters from the identifier, and look up the remaining
21653 characters in the opcode table. If we find a match, go
21658 U. Examine the tag field of the opcode structure, in case this is
21659 one of the six instructions with its conditional infix in an
21660 unusual place. If it is, the tag tells us where to find the
21661 infix; look it up in the conditions table and set inst.cond
21662 accordingly. Otherwise, this is an unconditional instruction.
21663 Again set inst.cond accordingly. Return the opcode structure.
21665 CE. Examine the tag field to make sure this is an instruction that
21666 should receive a conditional suffix. If it is not, fail.
21667 Otherwise, set inst.cond from the suffix we already looked up,
21668 and return the opcode structure.
21670 CM. Examine the tag field to make sure this is an instruction that
21671 should receive a conditional infix after the third character.
21672 If it is not, fail. Otherwise, undo the edits to the current
21673 line of input and proceed as for case CE. */
21675 static const struct asm_opcode
*
21676 opcode_lookup (char **str
)
21680 const struct asm_opcode
*opcode
;
21681 const struct asm_cond
*cond
;
21684 /* Scan up to the end of the mnemonic, which must end in white space,
21685 '.' (in unified mode, or for Neon/VFP instructions), or end of string. */
21686 for (base
= end
= *str
; *end
!= '\0'; end
++)
21687 if (*end
== ' ' || *end
== '.')
21693 /* Handle a possible width suffix and/or Neon type suffix. */
21698 /* The .w and .n suffixes are only valid if the unified syntax is in
21700 if (unified_syntax
&& end
[1] == 'w')
21702 else if (unified_syntax
&& end
[1] == 'n')
21707 inst
.vectype
.elems
= 0;
21709 *str
= end
+ offset
;
21711 if (end
[offset
] == '.')
21713 /* See if we have a Neon type suffix (possible in either unified or
21714 non-unified ARM syntax mode). */
21715 if (parse_neon_type (&inst
.vectype
, str
) == FAIL
)
21718 else if (end
[offset
] != '\0' && end
[offset
] != ' ')
21724 /* Look for unaffixed or special-case affixed mnemonic. */
21725 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21730 if (opcode
->tag
< OT_odd_infix_0
)
21732 inst
.cond
= COND_ALWAYS
;
21736 if (warn_on_deprecated
&& unified_syntax
)
21737 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21738 affix
= base
+ (opcode
->tag
- OT_odd_infix_0
);
21739 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21742 inst
.cond
= cond
->value
;
21745 if (ARM_CPU_HAS_FEATURE (cpu_variant
, mve_ext
))
21747 /* Cannot have a conditional suffix on a mnemonic of less than a character.
21749 if (end
- base
< 2)
21752 cond
= (const struct asm_cond
*) hash_find_n (arm_vcond_hsh
, affix
, 1);
21753 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21755 /* If this opcode can not be vector predicated then don't accept it with a
21756 vector predication code. */
21757 if (opcode
&& !opcode
->mayBeVecPred
)
21760 if (!opcode
|| !cond
)
21762 /* Cannot have a conditional suffix on a mnemonic of less than two
21764 if (end
- base
< 3)
21767 /* Look for suffixed mnemonic. */
21769 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21770 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21774 if (opcode
&& cond
)
21777 switch (opcode
->tag
)
21779 case OT_cinfix3_legacy
:
21780 /* Ignore conditional suffixes matched on infix only mnemonics. */
21784 case OT_cinfix3_deprecated
:
21785 case OT_odd_infix_unc
:
21786 if (!unified_syntax
)
21788 /* Fall through. */
21792 case OT_csuf_or_in3
:
21793 inst
.cond
= cond
->value
;
21796 case OT_unconditional
:
21797 case OT_unconditionalF
:
21799 inst
.cond
= cond
->value
;
21802 /* Delayed diagnostic. */
21803 inst
.error
= BAD_COND
;
21804 inst
.cond
= COND_ALWAYS
;
21813 /* Cannot have a usual-position infix on a mnemonic of less than
21814 six characters (five would be a suffix). */
21815 if (end
- base
< 6)
21818 /* Look for infixed mnemonic in the usual position. */
21820 cond
= (const struct asm_cond
*) hash_find_n (arm_cond_hsh
, affix
, 2);
21824 memcpy (save
, affix
, 2);
21825 memmove (affix
, affix
+ 2, (end
- affix
) - 2);
21826 opcode
= (const struct asm_opcode
*) hash_find_n (arm_ops_hsh
, base
,
21828 memmove (affix
+ 2, affix
, (end
- affix
) - 2);
21829 memcpy (affix
, save
, 2);
21832 && (opcode
->tag
== OT_cinfix3
21833 || opcode
->tag
== OT_cinfix3_deprecated
21834 || opcode
->tag
== OT_csuf_or_in3
21835 || opcode
->tag
== OT_cinfix3_legacy
))
21838 if (warn_on_deprecated
&& unified_syntax
21839 && (opcode
->tag
== OT_cinfix3
21840 || opcode
->tag
== OT_cinfix3_deprecated
))
21841 as_tsktsk (_("conditional infixes are deprecated in unified syntax"));
21843 inst
.cond
= cond
->value
;
21850 /* This function generates an initial IT instruction, leaving its block
21851 virtually open for the new instructions. Eventually,
21852 the mask will be updated by now_pred_add_mask () each time
21853 a new instruction needs to be included in the IT block.
21854 Finally, the block is closed with close_automatic_it_block ().
21855 The block closure can be requested either from md_assemble (),
21856 a tencode (), or due to a label hook. */
21859 new_automatic_it_block (int cond
)
21861 now_pred
.state
= AUTOMATIC_PRED_BLOCK
;
21862 now_pred
.mask
= 0x18;
21863 now_pred
.cc
= cond
;
21864 now_pred
.block_length
= 1;
21865 mapping_state (MAP_THUMB
);
21866 now_pred
.insn
= output_it_inst (cond
, now_pred
.mask
, NULL
);
21867 now_pred
.warn_deprecated
= FALSE
;
21868 now_pred
.insn_cond
= TRUE
;
21871 /* Close an automatic IT block.
21872 See comments in new_automatic_it_block (). */
21875 close_automatic_it_block (void)
21877 now_pred
.mask
= 0x10;
21878 now_pred
.block_length
= 0;
21881 /* Update the mask of the current automatically-generated IT
21882 instruction. See comments in new_automatic_it_block (). */
21885 now_pred_add_mask (int cond
)
21887 #define CLEAR_BIT(value, nbit) ((value) & ~(1 << (nbit)))
21888 #define SET_BIT_VALUE(value, bitvalue, nbit) (CLEAR_BIT (value, nbit) \
21889 | ((bitvalue) << (nbit)))
21890 const int resulting_bit
= (cond
& 1);
21892 now_pred
.mask
&= 0xf;
21893 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21895 (5 - now_pred
.block_length
));
21896 now_pred
.mask
= SET_BIT_VALUE (now_pred
.mask
,
21898 ((5 - now_pred
.block_length
) - 1));
21899 output_it_inst (now_pred
.cc
, now_pred
.mask
, now_pred
.insn
);
21902 #undef SET_BIT_VALUE
21905 /* The IT blocks handling machinery is accessed through the these functions:
21906 it_fsm_pre_encode () from md_assemble ()
21907 set_pred_insn_type () optional, from the tencode functions
21908 set_pred_insn_type_last () ditto
21909 in_pred_block () ditto
21910 it_fsm_post_encode () from md_assemble ()
21911 force_automatic_it_block_close () from label handling functions
21914 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
21915 initializing the IT insn type with a generic initial value depending
21916 on the inst.condition.
21917 2) During the tencode function, two things may happen:
21918 a) The tencode function overrides the IT insn type by
21919 calling either set_pred_insn_type (type) or
21920 set_pred_insn_type_last ().
21921 b) The tencode function queries the IT block state by
21922 calling in_pred_block () (i.e. to determine narrow/not narrow mode).
21924 Both set_pred_insn_type and in_pred_block run the internal FSM state
21925 handling function (handle_pred_state), because: a) setting the IT insn
21926 type may incur in an invalid state (exiting the function),
21927 and b) querying the state requires the FSM to be updated.
21928 Specifically we want to avoid creating an IT block for conditional
21929 branches, so it_fsm_pre_encode is actually a guess and we can't
21930 determine whether an IT block is required until the tencode () routine
21931 has decided what type of instruction this actually it.
21932 Because of this, if set_pred_insn_type and in_pred_block have to be
21933 used, set_pred_insn_type has to be called first.
21935 set_pred_insn_type_last () is a wrapper of set_pred_insn_type (type),
21936 that determines the insn IT type depending on the inst.cond code.
21937 When a tencode () routine encodes an instruction that can be
21938 either outside an IT block, or, in the case of being inside, has to be
21939 the last one, set_pred_insn_type_last () will determine the proper
21940 IT instruction type based on the inst.cond code. Otherwise,
21941 set_pred_insn_type can be called for overriding that logic or
21942 for covering other cases.
21944 Calling handle_pred_state () may not transition the IT block state to
21945 OUTSIDE_PRED_BLOCK immediately, since the (current) state could be
21946 still queried. Instead, if the FSM determines that the state should
21947 be transitioned to OUTSIDE_PRED_BLOCK, a flag is marked to be closed
21948 after the tencode () function: that's what it_fsm_post_encode () does.
21950 Since in_pred_block () calls the state handling function to get an
21951 updated state, an error may occur (due to invalid insns combination).
21952 In that case, inst.error is set.
21953 Therefore, inst.error has to be checked after the execution of
21954 the tencode () routine.
21956 3) Back in md_assemble(), it_fsm_post_encode () is called to commit
21957 any pending state change (if any) that didn't take place in
21958 handle_pred_state () as explained above. */
21961 it_fsm_pre_encode (void)
21963 if (inst
.cond
!= COND_ALWAYS
)
21964 inst
.pred_insn_type
= INSIDE_IT_INSN
;
21966 inst
.pred_insn_type
= OUTSIDE_PRED_INSN
;
21968 now_pred
.state_handled
= 0;
21971 /* IT state FSM handling function. */
21972 /* MVE instructions and non-MVE instructions are handled differently because of
21973 the introduction of VPT blocks.
21974 Specifications say that any non-MVE instruction inside a VPT block is
21975 UNPREDICTABLE, with the exception of the BKPT instruction. Whereas most MVE
21976 instructions are deemed to be UNPREDICTABLE if inside an IT block. For the
21977 few exceptions we have MVE_UNPREDICABLE_INSN.
21978 The error messages provided depending on the different combinations possible
21979 are described in the cases below:
21980 For 'most' MVE instructions:
21981 1) In an IT block, with an IT code: syntax error
21982 2) In an IT block, with a VPT code: error: must be in a VPT block
21983 3) In an IT block, with no code: warning: UNPREDICTABLE
21984 4) In a VPT block, with an IT code: syntax error
21985 5) In a VPT block, with a VPT code: OK!
21986 6) In a VPT block, with no code: error: missing code
21987 7) Outside a pred block, with an IT code: error: syntax error
21988 8) Outside a pred block, with a VPT code: error: should be in a VPT block
21989 9) Outside a pred block, with no code: OK!
21990 For non-MVE instructions:
21991 10) In an IT block, with an IT code: OK!
21992 11) In an IT block, with a VPT code: syntax error
21993 12) In an IT block, with no code: error: missing code
21994 13) In a VPT block, with an IT code: error: should be in an IT block
21995 14) In a VPT block, with a VPT code: syntax error
21996 15) In a VPT block, with no code: UNPREDICTABLE
21997 16) Outside a pred block, with an IT code: error: should be in an IT block
21998 17) Outside a pred block, with a VPT code: syntax error
21999 18) Outside a pred block, with no code: OK!
22004 handle_pred_state (void)
22006 now_pred
.state_handled
= 1;
22007 now_pred
.insn_cond
= FALSE
;
22009 switch (now_pred
.state
)
22011 case OUTSIDE_PRED_BLOCK
:
22012 switch (inst
.pred_insn_type
)
22014 case MVE_UNPREDICABLE_INSN
:
22015 case MVE_OUTSIDE_PRED_INSN
:
22016 if (inst
.cond
< COND_ALWAYS
)
22018 /* Case 7: Outside a pred block, with an IT code: error: syntax
22020 inst
.error
= BAD_SYNTAX
;
22023 /* Case 9: Outside a pred block, with no code: OK! */
22025 case OUTSIDE_PRED_INSN
:
22026 if (inst
.cond
> COND_ALWAYS
)
22028 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22030 inst
.error
= BAD_SYNTAX
;
22033 /* Case 18: Outside a pred block, with no code: OK! */
22036 case INSIDE_VPT_INSN
:
22037 /* Case 8: Outside a pred block, with a VPT code: error: should be in
22039 inst
.error
= BAD_OUT_VPT
;
22042 case INSIDE_IT_INSN
:
22043 case INSIDE_IT_LAST_INSN
:
22044 if (inst
.cond
< COND_ALWAYS
)
22046 /* Case 16: Outside a pred block, with an IT code: error: should
22047 be in an IT block. */
22048 if (thumb_mode
== 0)
22051 && !(implicit_it_mode
& IMPLICIT_IT_MODE_ARM
))
22052 as_tsktsk (_("Warning: conditional outside an IT block"\
22057 if ((implicit_it_mode
& IMPLICIT_IT_MODE_THUMB
)
22058 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
22060 /* Automatically generate the IT instruction. */
22061 new_automatic_it_block (inst
.cond
);
22062 if (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
)
22063 close_automatic_it_block ();
22067 inst
.error
= BAD_OUT_IT
;
22073 else if (inst
.cond
> COND_ALWAYS
)
22075 /* Case 17: Outside a pred block, with a VPT code: syntax error.
22077 inst
.error
= BAD_SYNTAX
;
22082 case IF_INSIDE_IT_LAST_INSN
:
22083 case NEUTRAL_IT_INSN
:
22087 if (inst
.cond
!= COND_ALWAYS
)
22088 first_error (BAD_SYNTAX
);
22089 now_pred
.state
= MANUAL_PRED_BLOCK
;
22090 now_pred
.block_length
= 0;
22091 now_pred
.type
= VECTOR_PRED
;
22095 now_pred
.state
= MANUAL_PRED_BLOCK
;
22096 now_pred
.block_length
= 0;
22097 now_pred
.type
= SCALAR_PRED
;
22102 case AUTOMATIC_PRED_BLOCK
:
22103 /* Three things may happen now:
22104 a) We should increment current it block size;
22105 b) We should close current it block (closing insn or 4 insns);
22106 c) We should close current it block and start a new one (due
22107 to incompatible conditions or
22108 4 insns-length block reached). */
22110 switch (inst
.pred_insn_type
)
22112 case INSIDE_VPT_INSN
:
22114 case MVE_UNPREDICABLE_INSN
:
22115 case MVE_OUTSIDE_PRED_INSN
:
22117 case OUTSIDE_PRED_INSN
:
22118 /* The closure of the block shall happen immediately,
22119 so any in_pred_block () call reports the block as closed. */
22120 force_automatic_it_block_close ();
22123 case INSIDE_IT_INSN
:
22124 case INSIDE_IT_LAST_INSN
:
22125 case IF_INSIDE_IT_LAST_INSN
:
22126 now_pred
.block_length
++;
22128 if (now_pred
.block_length
> 4
22129 || !now_pred_compatible (inst
.cond
))
22131 force_automatic_it_block_close ();
22132 if (inst
.pred_insn_type
!= IF_INSIDE_IT_LAST_INSN
)
22133 new_automatic_it_block (inst
.cond
);
22137 now_pred
.insn_cond
= TRUE
;
22138 now_pred_add_mask (inst
.cond
);
22141 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
22142 && (inst
.pred_insn_type
== INSIDE_IT_LAST_INSN
22143 || inst
.pred_insn_type
== IF_INSIDE_IT_LAST_INSN
))
22144 close_automatic_it_block ();
22147 case NEUTRAL_IT_INSN
:
22148 now_pred
.block_length
++;
22149 now_pred
.insn_cond
= TRUE
;
22151 if (now_pred
.block_length
> 4)
22152 force_automatic_it_block_close ();
22154 now_pred_add_mask (now_pred
.cc
& 1);
22158 close_automatic_it_block ();
22159 now_pred
.state
= MANUAL_PRED_BLOCK
;
22164 case MANUAL_PRED_BLOCK
:
22167 if (now_pred
.type
== SCALAR_PRED
)
22169 /* Check conditional suffixes. */
22170 cond
= now_pred
.cc
^ ((now_pred
.mask
>> 4) & 1) ^ 1;
22171 now_pred
.mask
<<= 1;
22172 now_pred
.mask
&= 0x1f;
22173 is_last
= (now_pred
.mask
== 0x10);
22177 now_pred
.cc
^= (now_pred
.mask
>> 4);
22178 cond
= now_pred
.cc
+ 0xf;
22179 now_pred
.mask
<<= 1;
22180 now_pred
.mask
&= 0x1f;
22181 is_last
= now_pred
.mask
== 0x10;
22183 now_pred
.insn_cond
= TRUE
;
22185 switch (inst
.pred_insn_type
)
22187 case OUTSIDE_PRED_INSN
:
22188 if (now_pred
.type
== SCALAR_PRED
)
22190 if (inst
.cond
== COND_ALWAYS
)
22192 /* Case 12: In an IT block, with no code: error: missing
22194 inst
.error
= BAD_NOT_IT
;
22197 else if (inst
.cond
> COND_ALWAYS
)
22199 /* Case 11: In an IT block, with a VPT code: syntax error.
22201 inst
.error
= BAD_SYNTAX
;
22204 else if (thumb_mode
)
22206 /* This is for some special cases where a non-MVE
22207 instruction is not allowed in an IT block, such as cbz,
22208 but are put into one with a condition code.
22209 You could argue this should be a syntax error, but we
22210 gave the 'not allowed in IT block' diagnostic in the
22211 past so we will keep doing so. */
22212 inst
.error
= BAD_NOT_IT
;
22219 /* Case 15: In a VPT block, with no code: UNPREDICTABLE. */
22220 as_tsktsk (MVE_NOT_VPT
);
22223 case MVE_OUTSIDE_PRED_INSN
:
22224 if (now_pred
.type
== SCALAR_PRED
)
22226 if (inst
.cond
== COND_ALWAYS
)
22228 /* Case 3: In an IT block, with no code: warning:
22230 as_tsktsk (MVE_NOT_IT
);
22233 else if (inst
.cond
< COND_ALWAYS
)
22235 /* Case 1: In an IT block, with an IT code: syntax error.
22237 inst
.error
= BAD_SYNTAX
;
22245 if (inst
.cond
< COND_ALWAYS
)
22247 /* Case 4: In a VPT block, with an IT code: syntax error.
22249 inst
.error
= BAD_SYNTAX
;
22252 else if (inst
.cond
== COND_ALWAYS
)
22254 /* Case 6: In a VPT block, with no code: error: missing
22256 inst
.error
= BAD_NOT_VPT
;
22264 case MVE_UNPREDICABLE_INSN
:
22265 as_tsktsk (now_pred
.type
== SCALAR_PRED
? MVE_NOT_IT
: MVE_NOT_VPT
);
22267 case INSIDE_IT_INSN
:
22268 if (inst
.cond
> COND_ALWAYS
)
22270 /* Case 11: In an IT block, with a VPT code: syntax error. */
22271 /* Case 14: In a VPT block, with a VPT code: syntax error. */
22272 inst
.error
= BAD_SYNTAX
;
22275 else if (now_pred
.type
== SCALAR_PRED
)
22277 /* Case 10: In an IT block, with an IT code: OK! */
22278 if (cond
!= inst
.cond
)
22280 inst
.error
= now_pred
.type
== SCALAR_PRED
? BAD_IT_COND
:
22287 /* Case 13: In a VPT block, with an IT code: error: should be
22289 inst
.error
= BAD_OUT_IT
;
22294 case INSIDE_VPT_INSN
:
22295 if (now_pred
.type
== SCALAR_PRED
)
22297 /* Case 2: In an IT block, with a VPT code: error: must be in a
22299 inst
.error
= BAD_OUT_VPT
;
22302 /* Case 5: In a VPT block, with a VPT code: OK! */
22303 else if (cond
!= inst
.cond
)
22305 inst
.error
= BAD_VPT_COND
;
22309 case INSIDE_IT_LAST_INSN
:
22310 case IF_INSIDE_IT_LAST_INSN
:
22311 if (now_pred
.type
== VECTOR_PRED
|| inst
.cond
> COND_ALWAYS
)
22313 /* Case 4: In a VPT block, with an IT code: syntax error. */
22314 /* Case 11: In an IT block, with a VPT code: syntax error. */
22315 inst
.error
= BAD_SYNTAX
;
22318 else if (cond
!= inst
.cond
)
22320 inst
.error
= BAD_IT_COND
;
22325 inst
.error
= BAD_BRANCH
;
22330 case NEUTRAL_IT_INSN
:
22331 /* The BKPT instruction is unconditional even in a IT or VPT
22336 if (now_pred
.type
== SCALAR_PRED
)
22338 inst
.error
= BAD_IT_IT
;
22341 /* fall through. */
22343 if (inst
.cond
== COND_ALWAYS
)
22345 /* Executing a VPT/VPST instruction inside an IT block or a
22346 VPT/VPST/IT instruction inside a VPT block is UNPREDICTABLE.
22348 if (now_pred
.type
== SCALAR_PRED
)
22349 as_tsktsk (MVE_NOT_IT
);
22351 as_tsktsk (MVE_NOT_VPT
);
22356 /* VPT/VPST do not accept condition codes. */
22357 inst
.error
= BAD_SYNTAX
;
22368 struct depr_insn_mask
22370 unsigned long pattern
;
22371 unsigned long mask
;
22372 const char* description
;
22375 /* List of 16-bit instruction patterns deprecated in an IT block in
22377 static const struct depr_insn_mask depr_it_insns
[] = {
22378 { 0xc000, 0xc000, N_("Short branches, Undefined, SVC, LDM/STM") },
22379 { 0xb000, 0xb000, N_("Miscellaneous 16-bit instructions") },
22380 { 0xa000, 0xb800, N_("ADR") },
22381 { 0x4800, 0xf800, N_("Literal loads") },
22382 { 0x4478, 0xf478, N_("Hi-register ADD, MOV, CMP, BX, BLX using pc") },
22383 { 0x4487, 0xfc87, N_("Hi-register ADD, MOV, CMP using pc") },
22384 /* NOTE: 0x00dd is not the real encoding, instead, it is the 'tvalue'
22385 field in asm_opcode. 'tvalue' is used at the stage this check happen. */
22386 { 0x00dd, 0x7fff, N_("ADD/SUB sp, sp #imm") },
22391 it_fsm_post_encode (void)
22395 if (!now_pred
.state_handled
)
22396 handle_pred_state ();
22398 if (now_pred
.insn_cond
22399 && !now_pred
.warn_deprecated
22400 && warn_on_deprecated
22401 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v8
)
22402 && !ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_m
))
22404 if (inst
.instruction
>= 0x10000)
22406 as_tsktsk (_("IT blocks containing 32-bit Thumb instructions are "
22407 "performance deprecated in ARMv8-A and ARMv8-R"));
22408 now_pred
.warn_deprecated
= TRUE
;
22412 const struct depr_insn_mask
*p
= depr_it_insns
;
22414 while (p
->mask
!= 0)
22416 if ((inst
.instruction
& p
->mask
) == p
->pattern
)
22418 as_tsktsk (_("IT blocks containing 16-bit Thumb "
22419 "instructions of the following class are "
22420 "performance deprecated in ARMv8-A and "
22421 "ARMv8-R: %s"), p
->description
);
22422 now_pred
.warn_deprecated
= TRUE
;
22430 if (now_pred
.block_length
> 1)
22432 as_tsktsk (_("IT blocks containing more than one conditional "
22433 "instruction are performance deprecated in ARMv8-A and "
22435 now_pred
.warn_deprecated
= TRUE
;
22439 is_last
= (now_pred
.mask
== 0x10);
22442 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22448 force_automatic_it_block_close (void)
22450 if (now_pred
.state
== AUTOMATIC_PRED_BLOCK
)
22452 close_automatic_it_block ();
22453 now_pred
.state
= OUTSIDE_PRED_BLOCK
;
22459 in_pred_block (void)
22461 if (!now_pred
.state_handled
)
22462 handle_pred_state ();
22464 return now_pred
.state
!= OUTSIDE_PRED_BLOCK
;
22467 /* Whether OPCODE only has T32 encoding. Since this function is only used by
22468 t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed
22469 here, hence the "known" in the function name. */
22472 known_t32_only_insn (const struct asm_opcode
*opcode
)
22474 /* Original Thumb-1 wide instruction. */
22475 if (opcode
->tencode
== do_t_blx
22476 || opcode
->tencode
== do_t_branch23
22477 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_msr
)
22478 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_barrier
))
22481 /* Wide-only instruction added to ARMv8-M Baseline. */
22482 if (ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v8m_m_only
)
22483 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_atomics
)
22484 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_v6t2_v8m
)
22485 || ARM_CPU_HAS_FEATURE (*opcode
->tvariant
, arm_ext_div
))
22491 /* Whether wide instruction variant can be used if available for a valid OPCODE
22495 t32_insn_ok (arm_feature_set arch
, const struct asm_opcode
*opcode
)
22497 if (known_t32_only_insn (opcode
))
22500 /* Instruction with narrow and wide encoding added to ARMv8-M. Availability
22501 of variant T3 of B.W is checked in do_t_branch. */
22502 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22503 && opcode
->tencode
== do_t_branch
)
22506 /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
22507 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v8m
)
22508 && opcode
->tencode
== do_t_mov_cmp
22509 /* Make sure CMP instruction is not affected. */
22510 && opcode
->aencode
== do_mov
)
22513 /* Wide instruction variants of all instructions with narrow *and* wide
22514 variants become available with ARMv6t2. Other opcodes are either
22515 narrow-only or wide-only and are thus available if OPCODE is valid. */
22516 if (ARM_CPU_HAS_FEATURE (arch
, arm_ext_v6t2
))
22519 /* OPCODE with narrow only instruction variant or wide variant not
22525 md_assemble (char *str
)
22528 const struct asm_opcode
* opcode
;
22530 /* Align the previous label if needed. */
22531 if (last_label_seen
!= NULL
)
22533 symbol_set_frag (last_label_seen
, frag_now
);
22534 S_SET_VALUE (last_label_seen
, (valueT
) frag_now_fix ());
22535 S_SET_SEGMENT (last_label_seen
, now_seg
);
22538 memset (&inst
, '\0', sizeof (inst
));
22540 for (r
= 0; r
< ARM_IT_MAX_RELOCS
; r
++)
22541 inst
.relocs
[r
].type
= BFD_RELOC_UNUSED
;
22543 opcode
= opcode_lookup (&p
);
22546 /* It wasn't an instruction, but it might be a register alias of
22547 the form alias .req reg, or a Neon .dn/.qn directive. */
22548 if (! create_register_alias (str
, p
)
22549 && ! create_neon_reg_alias (str
, p
))
22550 as_bad (_("bad instruction `%s'"), str
);
22555 if (warn_on_deprecated
&& opcode
->tag
== OT_cinfix3_deprecated
)
22556 as_tsktsk (_("s suffix on comparison instruction is deprecated"));
22558 /* The value which unconditional instructions should have in place of the
22559 condition field. */
22560 inst
.uncond_value
= (opcode
->tag
== OT_csuffixF
) ? 0xf : -1;
22564 arm_feature_set variant
;
22566 variant
= cpu_variant
;
22567 /* Only allow coprocessor instructions on Thumb-2 capable devices. */
22568 if (!ARM_CPU_HAS_FEATURE (variant
, arm_arch_t2
))
22569 ARM_CLEAR_FEATURE (variant
, variant
, fpu_any_hard
);
22570 /* Check that this instruction is supported for this CPU. */
22571 if (!opcode
->tvariant
22572 || (thumb_mode
== 1
22573 && !ARM_CPU_HAS_FEATURE (variant
, *opcode
->tvariant
)))
22575 if (opcode
->tencode
== do_t_swi
)
22576 as_bad (_("SVC is not permitted on this architecture"));
22578 as_bad (_("selected processor does not support `%s' in Thumb mode"), str
);
22581 if (inst
.cond
!= COND_ALWAYS
&& !unified_syntax
22582 && opcode
->tencode
!= do_t_branch
)
22584 as_bad (_("Thumb does not support conditional execution"));
22588 /* Two things are addressed here:
22589 1) Implicit require narrow instructions on Thumb-1.
22590 This avoids relaxation accidentally introducing Thumb-2
22592 2) Reject wide instructions in non Thumb-2 cores.
22594 Only instructions with narrow and wide variants need to be handled
22595 but selecting all non wide-only instructions is easier. */
22596 if (!ARM_CPU_HAS_FEATURE (variant
, arm_ext_v6t2
)
22597 && !t32_insn_ok (variant
, opcode
))
22599 if (inst
.size_req
== 0)
22601 else if (inst
.size_req
== 4)
22603 if (ARM_CPU_HAS_FEATURE (variant
, arm_ext_v8m
))
22604 as_bad (_("selected processor does not support 32bit wide "
22605 "variant of instruction `%s'"), str
);
22607 as_bad (_("selected processor does not support `%s' in "
22608 "Thumb-2 mode"), str
);
22613 inst
.instruction
= opcode
->tvalue
;
22615 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/TRUE
))
22617 /* Prepare the pred_insn_type for those encodings that don't set
22619 it_fsm_pre_encode ();
22621 opcode
->tencode ();
22623 it_fsm_post_encode ();
22626 if (!(inst
.error
|| inst
.relax
))
22628 gas_assert (inst
.instruction
< 0xe800 || inst
.instruction
> 0xffff);
22629 inst
.size
= (inst
.instruction
> 0xffff ? 4 : 2);
22630 if (inst
.size_req
&& inst
.size_req
!= inst
.size
)
22632 as_bad (_("cannot honor width suffix -- `%s'"), str
);
22637 /* Something has gone badly wrong if we try to relax a fixed size
22639 gas_assert (inst
.size_req
== 0 || !inst
.relax
);
22641 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22642 *opcode
->tvariant
);
22643 /* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
22644 set those bits when Thumb-2 32-bit instructions are seen. The impact
22645 of relaxable instructions will be considered later after we finish all
22647 if (ARM_FEATURE_CORE_EQUAL (cpu_variant
, arm_arch_any
))
22648 variant
= arm_arch_none
;
22650 variant
= cpu_variant
;
22651 if (inst
.size
== 4 && !t32_insn_ok (variant
, opcode
))
22652 ARM_MERGE_FEATURE_SETS (thumb_arch_used
, thumb_arch_used
,
22655 check_neon_suffixes
;
22659 mapping_state (MAP_THUMB
);
22662 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
22666 /* bx is allowed on v5 cores, and sometimes on v4 cores. */
22667 is_bx
= (opcode
->aencode
== do_bx
);
22669 /* Check that this instruction is supported for this CPU. */
22670 if (!(is_bx
&& fix_v4bx
)
22671 && !(opcode
->avariant
&&
22672 ARM_CPU_HAS_FEATURE (cpu_variant
, *opcode
->avariant
)))
22674 as_bad (_("selected processor does not support `%s' in ARM mode"), str
);
22679 as_bad (_("width suffixes are invalid in ARM mode -- `%s'"), str
);
22683 inst
.instruction
= opcode
->avalue
;
22684 if (opcode
->tag
== OT_unconditionalF
)
22685 inst
.instruction
|= 0xFU
<< 28;
22687 inst
.instruction
|= inst
.cond
<< 28;
22688 inst
.size
= INSN_SIZE
;
22689 if (!parse_operands (p
, opcode
->operands
, /*thumb=*/FALSE
))
22691 it_fsm_pre_encode ();
22692 opcode
->aencode ();
22693 it_fsm_post_encode ();
22695 /* Arm mode bx is marked as both v4T and v5 because it's still required
22696 on a hypothetical non-thumb v5 core. */
22698 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
, arm_ext_v4t
);
22700 ARM_MERGE_FEATURE_SETS (arm_arch_used
, arm_arch_used
,
22701 *opcode
->avariant
);
22703 check_neon_suffixes
;
22707 mapping_state (MAP_ARM
);
22712 as_bad (_("attempt to use an ARM instruction on a Thumb-only processor "
22720 check_pred_blocks_finished (void)
22725 for (sect
= stdoutput
->sections
; sect
!= NULL
; sect
= sect
->next
)
22726 if (seg_info (sect
)->tc_segment_info_data
.current_pred
.state
22727 == MANUAL_PRED_BLOCK
)
22729 if (now_pred
.type
== SCALAR_PRED
)
22730 as_warn (_("section '%s' finished with an open IT block."),
22733 as_warn (_("section '%s' finished with an open VPT/VPST block."),
22737 if (now_pred
.state
== MANUAL_PRED_BLOCK
)
22739 if (now_pred
.type
== SCALAR_PRED
)
22740 as_warn (_("file finished with an open IT block."));
22742 as_warn (_("file finished with an open VPT/VPST block."));
22747 /* Various frobbings of labels and their addresses. */
22750 arm_start_line_hook (void)
22752 last_label_seen
= NULL
;
22756 arm_frob_label (symbolS
* sym
)
22758 last_label_seen
= sym
;
22760 ARM_SET_THUMB (sym
, thumb_mode
);
22762 #if defined OBJ_COFF || defined OBJ_ELF
22763 ARM_SET_INTERWORK (sym
, support_interwork
);
22766 force_automatic_it_block_close ();
22768 /* Note - do not allow local symbols (.Lxxx) to be labelled
22769 as Thumb functions. This is because these labels, whilst
22770 they exist inside Thumb code, are not the entry points for
22771 possible ARM->Thumb calls. Also, these labels can be used
22772 as part of a computed goto or switch statement. eg gcc
22773 can generate code that looks like this:
22775 ldr r2, [pc, .Laaa]
22785 The first instruction loads the address of the jump table.
22786 The second instruction converts a table index into a byte offset.
22787 The third instruction gets the jump address out of the table.
22788 The fourth instruction performs the jump.
22790 If the address stored at .Laaa is that of a symbol which has the
22791 Thumb_Func bit set, then the linker will arrange for this address
22792 to have the bottom bit set, which in turn would mean that the
22793 address computation performed by the third instruction would end
22794 up with the bottom bit set. Since the ARM is capable of unaligned
22795 word loads, the instruction would then load the incorrect address
22796 out of the jump table, and chaos would ensue. */
22797 if (label_is_thumb_function_name
22798 && (S_GET_NAME (sym
)[0] != '.' || S_GET_NAME (sym
)[1] != 'L')
22799 && (bfd_get_section_flags (stdoutput
, now_seg
) & SEC_CODE
) != 0)
22801 /* When the address of a Thumb function is taken the bottom
22802 bit of that address should be set. This will allow
22803 interworking between Arm and Thumb functions to work
22806 THUMB_SET_FUNC (sym
, 1);
22808 label_is_thumb_function_name
= FALSE
;
22811 dwarf2_emit_label (sym
);
22815 arm_data_in_code (void)
22817 if (thumb_mode
&& ! strncmp (input_line_pointer
+ 1, "data:", 5))
22819 *input_line_pointer
= '/';
22820 input_line_pointer
+= 5;
22821 *input_line_pointer
= 0;
22829 arm_canonicalize_symbol_name (char * name
)
22833 if (thumb_mode
&& (len
= strlen (name
)) > 5
22834 && streq (name
+ len
- 5, "/data"))
22835 *(name
+ len
- 5) = 0;
22840 /* Table of all register names defined by default. The user can
22841 define additional names with .req. Note that all register names
22842 should appear in both upper and lowercase variants. Some registers
22843 also have mixed-case names. */
22845 #define REGDEF(s,n,t) { #s, n, REG_TYPE_##t, TRUE, 0 }
22846 #define REGNUM(p,n,t) REGDEF(p##n, n, t)
22847 #define REGNUM2(p,n,t) REGDEF(p##n, 2 * n, t)
22848 #define REGSET(p,t) \
22849 REGNUM(p, 0,t), REGNUM(p, 1,t), REGNUM(p, 2,t), REGNUM(p, 3,t), \
22850 REGNUM(p, 4,t), REGNUM(p, 5,t), REGNUM(p, 6,t), REGNUM(p, 7,t), \
22851 REGNUM(p, 8,t), REGNUM(p, 9,t), REGNUM(p,10,t), REGNUM(p,11,t), \
22852 REGNUM(p,12,t), REGNUM(p,13,t), REGNUM(p,14,t), REGNUM(p,15,t)
22853 #define REGSETH(p,t) \
22854 REGNUM(p,16,t), REGNUM(p,17,t), REGNUM(p,18,t), REGNUM(p,19,t), \
22855 REGNUM(p,20,t), REGNUM(p,21,t), REGNUM(p,22,t), REGNUM(p,23,t), \
22856 REGNUM(p,24,t), REGNUM(p,25,t), REGNUM(p,26,t), REGNUM(p,27,t), \
22857 REGNUM(p,28,t), REGNUM(p,29,t), REGNUM(p,30,t), REGNUM(p,31,t)
22858 #define REGSET2(p,t) \
22859 REGNUM2(p, 0,t), REGNUM2(p, 1,t), REGNUM2(p, 2,t), REGNUM2(p, 3,t), \
22860 REGNUM2(p, 4,t), REGNUM2(p, 5,t), REGNUM2(p, 6,t), REGNUM2(p, 7,t), \
22861 REGNUM2(p, 8,t), REGNUM2(p, 9,t), REGNUM2(p,10,t), REGNUM2(p,11,t), \
22862 REGNUM2(p,12,t), REGNUM2(p,13,t), REGNUM2(p,14,t), REGNUM2(p,15,t)
22863 #define SPLRBANK(base,bank,t) \
22864 REGDEF(lr_##bank, 768|((base+0)<<16), t), \
22865 REGDEF(sp_##bank, 768|((base+1)<<16), t), \
22866 REGDEF(spsr_##bank, 768|(base<<16)|SPSR_BIT, t), \
22867 REGDEF(LR_##bank, 768|((base+0)<<16), t), \
22868 REGDEF(SP_##bank, 768|((base+1)<<16), t), \
22869 REGDEF(SPSR_##bank, 768|(base<<16)|SPSR_BIT, t)
22871 static const struct reg_entry reg_names
[] =
22873 /* ARM integer registers. */
22874 REGSET(r
, RN
), REGSET(R
, RN
),
22876 /* ATPCS synonyms. */
22877 REGDEF(a1
,0,RN
), REGDEF(a2
,1,RN
), REGDEF(a3
, 2,RN
), REGDEF(a4
, 3,RN
),
22878 REGDEF(v1
,4,RN
), REGDEF(v2
,5,RN
), REGDEF(v3
, 6,RN
), REGDEF(v4
, 7,RN
),
22879 REGDEF(v5
,8,RN
), REGDEF(v6
,9,RN
), REGDEF(v7
,10,RN
), REGDEF(v8
,11,RN
),
22881 REGDEF(A1
,0,RN
), REGDEF(A2
,1,RN
), REGDEF(A3
, 2,RN
), REGDEF(A4
, 3,RN
),
22882 REGDEF(V1
,4,RN
), REGDEF(V2
,5,RN
), REGDEF(V3
, 6,RN
), REGDEF(V4
, 7,RN
),
22883 REGDEF(V5
,8,RN
), REGDEF(V6
,9,RN
), REGDEF(V7
,10,RN
), REGDEF(V8
,11,RN
),
22885 /* Well-known aliases. */
22886 REGDEF(wr
, 7,RN
), REGDEF(sb
, 9,RN
), REGDEF(sl
,10,RN
), REGDEF(fp
,11,RN
),
22887 REGDEF(ip
,12,RN
), REGDEF(sp
,13,RN
), REGDEF(lr
,14,RN
), REGDEF(pc
,15,RN
),
22889 REGDEF(WR
, 7,RN
), REGDEF(SB
, 9,RN
), REGDEF(SL
,10,RN
), REGDEF(FP
,11,RN
),
22890 REGDEF(IP
,12,RN
), REGDEF(SP
,13,RN
), REGDEF(LR
,14,RN
), REGDEF(PC
,15,RN
),
22892 /* Defining the new Zero register from ARMv8.1-M. */
22896 /* Coprocessor numbers. */
22897 REGSET(p
, CP
), REGSET(P
, CP
),
22899 /* Coprocessor register numbers. The "cr" variants are for backward
22901 REGSET(c
, CN
), REGSET(C
, CN
),
22902 REGSET(cr
, CN
), REGSET(CR
, CN
),
22904 /* ARM banked registers. */
22905 REGDEF(R8_usr
,512|(0<<16),RNB
), REGDEF(r8_usr
,512|(0<<16),RNB
),
22906 REGDEF(R9_usr
,512|(1<<16),RNB
), REGDEF(r9_usr
,512|(1<<16),RNB
),
22907 REGDEF(R10_usr
,512|(2<<16),RNB
), REGDEF(r10_usr
,512|(2<<16),RNB
),
22908 REGDEF(R11_usr
,512|(3<<16),RNB
), REGDEF(r11_usr
,512|(3<<16),RNB
),
22909 REGDEF(R12_usr
,512|(4<<16),RNB
), REGDEF(r12_usr
,512|(4<<16),RNB
),
22910 REGDEF(SP_usr
,512|(5<<16),RNB
), REGDEF(sp_usr
,512|(5<<16),RNB
),
22911 REGDEF(LR_usr
,512|(6<<16),RNB
), REGDEF(lr_usr
,512|(6<<16),RNB
),
22913 REGDEF(R8_fiq
,512|(8<<16),RNB
), REGDEF(r8_fiq
,512|(8<<16),RNB
),
22914 REGDEF(R9_fiq
,512|(9<<16),RNB
), REGDEF(r9_fiq
,512|(9<<16),RNB
),
22915 REGDEF(R10_fiq
,512|(10<<16),RNB
), REGDEF(r10_fiq
,512|(10<<16),RNB
),
22916 REGDEF(R11_fiq
,512|(11<<16),RNB
), REGDEF(r11_fiq
,512|(11<<16),RNB
),
22917 REGDEF(R12_fiq
,512|(12<<16),RNB
), REGDEF(r12_fiq
,512|(12<<16),RNB
),
22918 REGDEF(SP_fiq
,512|(13<<16),RNB
), REGDEF(sp_fiq
,512|(13<<16),RNB
),
22919 REGDEF(LR_fiq
,512|(14<<16),RNB
), REGDEF(lr_fiq
,512|(14<<16),RNB
),
22920 REGDEF(SPSR_fiq
,512|(14<<16)|SPSR_BIT
,RNB
), REGDEF(spsr_fiq
,512|(14<<16)|SPSR_BIT
,RNB
),
22922 SPLRBANK(0,IRQ
,RNB
), SPLRBANK(0,irq
,RNB
),
22923 SPLRBANK(2,SVC
,RNB
), SPLRBANK(2,svc
,RNB
),
22924 SPLRBANK(4,ABT
,RNB
), SPLRBANK(4,abt
,RNB
),
22925 SPLRBANK(6,UND
,RNB
), SPLRBANK(6,und
,RNB
),
22926 SPLRBANK(12,MON
,RNB
), SPLRBANK(12,mon
,RNB
),
22927 REGDEF(elr_hyp
,768|(14<<16),RNB
), REGDEF(ELR_hyp
,768|(14<<16),RNB
),
22928 REGDEF(sp_hyp
,768|(15<<16),RNB
), REGDEF(SP_hyp
,768|(15<<16),RNB
),
22929 REGDEF(spsr_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22930 REGDEF(SPSR_hyp
,768|(14<<16)|SPSR_BIT
,RNB
),
22932 /* FPA registers. */
22933 REGNUM(f
,0,FN
), REGNUM(f
,1,FN
), REGNUM(f
,2,FN
), REGNUM(f
,3,FN
),
22934 REGNUM(f
,4,FN
), REGNUM(f
,5,FN
), REGNUM(f
,6,FN
), REGNUM(f
,7, FN
),
22936 REGNUM(F
,0,FN
), REGNUM(F
,1,FN
), REGNUM(F
,2,FN
), REGNUM(F
,3,FN
),
22937 REGNUM(F
,4,FN
), REGNUM(F
,5,FN
), REGNUM(F
,6,FN
), REGNUM(F
,7, FN
),
22939 /* VFP SP registers. */
22940 REGSET(s
,VFS
), REGSET(S
,VFS
),
22941 REGSETH(s
,VFS
), REGSETH(S
,VFS
),
22943 /* VFP DP Registers. */
22944 REGSET(d
,VFD
), REGSET(D
,VFD
),
22945 /* Extra Neon DP registers. */
22946 REGSETH(d
,VFD
), REGSETH(D
,VFD
),
22948 /* Neon QP registers. */
22949 REGSET2(q
,NQ
), REGSET2(Q
,NQ
),
22951 /* VFP control registers. */
22952 REGDEF(fpsid
,0,VFC
), REGDEF(fpscr
,1,VFC
), REGDEF(fpexc
,8,VFC
),
22953 REGDEF(FPSID
,0,VFC
), REGDEF(FPSCR
,1,VFC
), REGDEF(FPEXC
,8,VFC
),
22954 REGDEF(fpinst
,9,VFC
), REGDEF(fpinst2
,10,VFC
),
22955 REGDEF(FPINST
,9,VFC
), REGDEF(FPINST2
,10,VFC
),
22956 REGDEF(mvfr0
,7,VFC
), REGDEF(mvfr1
,6,VFC
),
22957 REGDEF(MVFR0
,7,VFC
), REGDEF(MVFR1
,6,VFC
),
22958 REGDEF(mvfr2
,5,VFC
), REGDEF(MVFR2
,5,VFC
),
22959 REGDEF(fpscr_nzcvqc
,2,VFC
), REGDEF(FPSCR_nzcvqc
,2,VFC
),
22960 REGDEF(vpr
,12,VFC
), REGDEF(VPR
,12,VFC
),
22961 REGDEF(fpcxt_ns
,14,VFC
), REGDEF(FPCXT_NS
,14,VFC
),
22962 REGDEF(fpcxt_s
,15,VFC
), REGDEF(FPCXT_S
,15,VFC
),
22964 /* Maverick DSP coprocessor registers. */
22965 REGSET(mvf
,MVF
), REGSET(mvd
,MVD
), REGSET(mvfx
,MVFX
), REGSET(mvdx
,MVDX
),
22966 REGSET(MVF
,MVF
), REGSET(MVD
,MVD
), REGSET(MVFX
,MVFX
), REGSET(MVDX
,MVDX
),
22968 REGNUM(mvax
,0,MVAX
), REGNUM(mvax
,1,MVAX
),
22969 REGNUM(mvax
,2,MVAX
), REGNUM(mvax
,3,MVAX
),
22970 REGDEF(dspsc
,0,DSPSC
),
22972 REGNUM(MVAX
,0,MVAX
), REGNUM(MVAX
,1,MVAX
),
22973 REGNUM(MVAX
,2,MVAX
), REGNUM(MVAX
,3,MVAX
),
22974 REGDEF(DSPSC
,0,DSPSC
),
22976 /* iWMMXt data registers - p0, c0-15. */
22977 REGSET(wr
,MMXWR
), REGSET(wR
,MMXWR
), REGSET(WR
, MMXWR
),
22979 /* iWMMXt control registers - p1, c0-3. */
22980 REGDEF(wcid
, 0,MMXWC
), REGDEF(wCID
, 0,MMXWC
), REGDEF(WCID
, 0,MMXWC
),
22981 REGDEF(wcon
, 1,MMXWC
), REGDEF(wCon
, 1,MMXWC
), REGDEF(WCON
, 1,MMXWC
),
22982 REGDEF(wcssf
, 2,MMXWC
), REGDEF(wCSSF
, 2,MMXWC
), REGDEF(WCSSF
, 2,MMXWC
),
22983 REGDEF(wcasf
, 3,MMXWC
), REGDEF(wCASF
, 3,MMXWC
), REGDEF(WCASF
, 3,MMXWC
),
22985 /* iWMMXt scalar (constant/offset) registers - p1, c8-11. */
22986 REGDEF(wcgr0
, 8,MMXWCG
), REGDEF(wCGR0
, 8,MMXWCG
), REGDEF(WCGR0
, 8,MMXWCG
),
22987 REGDEF(wcgr1
, 9,MMXWCG
), REGDEF(wCGR1
, 9,MMXWCG
), REGDEF(WCGR1
, 9,MMXWCG
),
22988 REGDEF(wcgr2
,10,MMXWCG
), REGDEF(wCGR2
,10,MMXWCG
), REGDEF(WCGR2
,10,MMXWCG
),
22989 REGDEF(wcgr3
,11,MMXWCG
), REGDEF(wCGR3
,11,MMXWCG
), REGDEF(WCGR3
,11,MMXWCG
),
22991 /* XScale accumulator registers. */
22992 REGNUM(acc
,0,XSCALE
), REGNUM(ACC
,0,XSCALE
),
22998 /* Table of all PSR suffixes. Bare "CPSR" and "SPSR" are handled
22999 within psr_required_here. */
23000 static const struct asm_psr psrs
[] =
23002 /* Backward compatibility notation. Note that "all" is no longer
23003 truly all possible PSR bits. */
23004 {"all", PSR_c
| PSR_f
},
23008 /* Individual flags. */
23014 /* Combinations of flags. */
23015 {"fs", PSR_f
| PSR_s
},
23016 {"fx", PSR_f
| PSR_x
},
23017 {"fc", PSR_f
| PSR_c
},
23018 {"sf", PSR_s
| PSR_f
},
23019 {"sx", PSR_s
| PSR_x
},
23020 {"sc", PSR_s
| PSR_c
},
23021 {"xf", PSR_x
| PSR_f
},
23022 {"xs", PSR_x
| PSR_s
},
23023 {"xc", PSR_x
| PSR_c
},
23024 {"cf", PSR_c
| PSR_f
},
23025 {"cs", PSR_c
| PSR_s
},
23026 {"cx", PSR_c
| PSR_x
},
23027 {"fsx", PSR_f
| PSR_s
| PSR_x
},
23028 {"fsc", PSR_f
| PSR_s
| PSR_c
},
23029 {"fxs", PSR_f
| PSR_x
| PSR_s
},
23030 {"fxc", PSR_f
| PSR_x
| PSR_c
},
23031 {"fcs", PSR_f
| PSR_c
| PSR_s
},
23032 {"fcx", PSR_f
| PSR_c
| PSR_x
},
23033 {"sfx", PSR_s
| PSR_f
| PSR_x
},
23034 {"sfc", PSR_s
| PSR_f
| PSR_c
},
23035 {"sxf", PSR_s
| PSR_x
| PSR_f
},
23036 {"sxc", PSR_s
| PSR_x
| PSR_c
},
23037 {"scf", PSR_s
| PSR_c
| PSR_f
},
23038 {"scx", PSR_s
| PSR_c
| PSR_x
},
23039 {"xfs", PSR_x
| PSR_f
| PSR_s
},
23040 {"xfc", PSR_x
| PSR_f
| PSR_c
},
23041 {"xsf", PSR_x
| PSR_s
| PSR_f
},
23042 {"xsc", PSR_x
| PSR_s
| PSR_c
},
23043 {"xcf", PSR_x
| PSR_c
| PSR_f
},
23044 {"xcs", PSR_x
| PSR_c
| PSR_s
},
23045 {"cfs", PSR_c
| PSR_f
| PSR_s
},
23046 {"cfx", PSR_c
| PSR_f
| PSR_x
},
23047 {"csf", PSR_c
| PSR_s
| PSR_f
},
23048 {"csx", PSR_c
| PSR_s
| PSR_x
},
23049 {"cxf", PSR_c
| PSR_x
| PSR_f
},
23050 {"cxs", PSR_c
| PSR_x
| PSR_s
},
23051 {"fsxc", PSR_f
| PSR_s
| PSR_x
| PSR_c
},
23052 {"fscx", PSR_f
| PSR_s
| PSR_c
| PSR_x
},
23053 {"fxsc", PSR_f
| PSR_x
| PSR_s
| PSR_c
},
23054 {"fxcs", PSR_f
| PSR_x
| PSR_c
| PSR_s
},
23055 {"fcsx", PSR_f
| PSR_c
| PSR_s
| PSR_x
},
23056 {"fcxs", PSR_f
| PSR_c
| PSR_x
| PSR_s
},
23057 {"sfxc", PSR_s
| PSR_f
| PSR_x
| PSR_c
},
23058 {"sfcx", PSR_s
| PSR_f
| PSR_c
| PSR_x
},
23059 {"sxfc", PSR_s
| PSR_x
| PSR_f
| PSR_c
},
23060 {"sxcf", PSR_s
| PSR_x
| PSR_c
| PSR_f
},
23061 {"scfx", PSR_s
| PSR_c
| PSR_f
| PSR_x
},
23062 {"scxf", PSR_s
| PSR_c
| PSR_x
| PSR_f
},
23063 {"xfsc", PSR_x
| PSR_f
| PSR_s
| PSR_c
},
23064 {"xfcs", PSR_x
| PSR_f
| PSR_c
| PSR_s
},
23065 {"xsfc", PSR_x
| PSR_s
| PSR_f
| PSR_c
},
23066 {"xscf", PSR_x
| PSR_s
| PSR_c
| PSR_f
},
23067 {"xcfs", PSR_x
| PSR_c
| PSR_f
| PSR_s
},
23068 {"xcsf", PSR_x
| PSR_c
| PSR_s
| PSR_f
},
23069 {"cfsx", PSR_c
| PSR_f
| PSR_s
| PSR_x
},
23070 {"cfxs", PSR_c
| PSR_f
| PSR_x
| PSR_s
},
23071 {"csfx", PSR_c
| PSR_s
| PSR_f
| PSR_x
},
23072 {"csxf", PSR_c
| PSR_s
| PSR_x
| PSR_f
},
23073 {"cxfs", PSR_c
| PSR_x
| PSR_f
| PSR_s
},
23074 {"cxsf", PSR_c
| PSR_x
| PSR_s
| PSR_f
},
23077 /* Table of V7M psr names. */
23078 static const struct asm_psr v7m_psrs
[] =
23080 {"apsr", 0x0 }, {"APSR", 0x0 },
23081 {"iapsr", 0x1 }, {"IAPSR", 0x1 },
23082 {"eapsr", 0x2 }, {"EAPSR", 0x2 },
23083 {"psr", 0x3 }, {"PSR", 0x3 },
23084 {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
23085 {"ipsr", 0x5 }, {"IPSR", 0x5 },
23086 {"epsr", 0x6 }, {"EPSR", 0x6 },
23087 {"iepsr", 0x7 }, {"IEPSR", 0x7 },
23088 {"msp", 0x8 }, {"MSP", 0x8 },
23089 {"psp", 0x9 }, {"PSP", 0x9 },
23090 {"msplim", 0xa }, {"MSPLIM", 0xa },
23091 {"psplim", 0xb }, {"PSPLIM", 0xb },
23092 {"primask", 0x10}, {"PRIMASK", 0x10},
23093 {"basepri", 0x11}, {"BASEPRI", 0x11},
23094 {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
23095 {"faultmask", 0x13}, {"FAULTMASK", 0x13},
23096 {"control", 0x14}, {"CONTROL", 0x14},
23097 {"msp_ns", 0x88}, {"MSP_NS", 0x88},
23098 {"psp_ns", 0x89}, {"PSP_NS", 0x89},
23099 {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
23100 {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
23101 {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
23102 {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
23103 {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
23104 {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
23105 {"sp_ns", 0x98}, {"SP_NS", 0x98 }
23108 /* Table of all shift-in-operand names. */
23109 static const struct asm_shift_name shift_names
[] =
23111 { "asl", SHIFT_LSL
}, { "ASL", SHIFT_LSL
},
23112 { "lsl", SHIFT_LSL
}, { "LSL", SHIFT_LSL
},
23113 { "lsr", SHIFT_LSR
}, { "LSR", SHIFT_LSR
},
23114 { "asr", SHIFT_ASR
}, { "ASR", SHIFT_ASR
},
23115 { "ror", SHIFT_ROR
}, { "ROR", SHIFT_ROR
},
23116 { "rrx", SHIFT_RRX
}, { "RRX", SHIFT_RRX
},
23117 { "uxtw", SHIFT_UXTW
}, { "UXTW", SHIFT_UXTW
}
23120 /* Table of all explicit relocation names. */
23122 static struct reloc_entry reloc_names
[] =
23124 { "got", BFD_RELOC_ARM_GOT32
}, { "GOT", BFD_RELOC_ARM_GOT32
},
23125 { "gotoff", BFD_RELOC_ARM_GOTOFF
}, { "GOTOFF", BFD_RELOC_ARM_GOTOFF
},
23126 { "plt", BFD_RELOC_ARM_PLT32
}, { "PLT", BFD_RELOC_ARM_PLT32
},
23127 { "target1", BFD_RELOC_ARM_TARGET1
}, { "TARGET1", BFD_RELOC_ARM_TARGET1
},
23128 { "target2", BFD_RELOC_ARM_TARGET2
}, { "TARGET2", BFD_RELOC_ARM_TARGET2
},
23129 { "sbrel", BFD_RELOC_ARM_SBREL32
}, { "SBREL", BFD_RELOC_ARM_SBREL32
},
23130 { "tlsgd", BFD_RELOC_ARM_TLS_GD32
}, { "TLSGD", BFD_RELOC_ARM_TLS_GD32
},
23131 { "tlsldm", BFD_RELOC_ARM_TLS_LDM32
}, { "TLSLDM", BFD_RELOC_ARM_TLS_LDM32
},
23132 { "tlsldo", BFD_RELOC_ARM_TLS_LDO32
}, { "TLSLDO", BFD_RELOC_ARM_TLS_LDO32
},
23133 { "gottpoff",BFD_RELOC_ARM_TLS_IE32
}, { "GOTTPOFF",BFD_RELOC_ARM_TLS_IE32
},
23134 { "tpoff", BFD_RELOC_ARM_TLS_LE32
}, { "TPOFF", BFD_RELOC_ARM_TLS_LE32
},
23135 { "got_prel", BFD_RELOC_ARM_GOT_PREL
}, { "GOT_PREL", BFD_RELOC_ARM_GOT_PREL
},
23136 { "tlsdesc", BFD_RELOC_ARM_TLS_GOTDESC
},
23137 { "TLSDESC", BFD_RELOC_ARM_TLS_GOTDESC
},
23138 { "tlscall", BFD_RELOC_ARM_TLS_CALL
},
23139 { "TLSCALL", BFD_RELOC_ARM_TLS_CALL
},
23140 { "tlsdescseq", BFD_RELOC_ARM_TLS_DESCSEQ
},
23141 { "TLSDESCSEQ", BFD_RELOC_ARM_TLS_DESCSEQ
},
23142 { "gotfuncdesc", BFD_RELOC_ARM_GOTFUNCDESC
},
23143 { "GOTFUNCDESC", BFD_RELOC_ARM_GOTFUNCDESC
},
23144 { "gotofffuncdesc", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23145 { "GOTOFFFUNCDESC", BFD_RELOC_ARM_GOTOFFFUNCDESC
},
23146 { "funcdesc", BFD_RELOC_ARM_FUNCDESC
},
23147 { "FUNCDESC", BFD_RELOC_ARM_FUNCDESC
},
23148 { "tlsgd_fdpic", BFD_RELOC_ARM_TLS_GD32_FDPIC
}, { "TLSGD_FDPIC", BFD_RELOC_ARM_TLS_GD32_FDPIC
},
23149 { "tlsldm_fdpic", BFD_RELOC_ARM_TLS_LDM32_FDPIC
}, { "TLSLDM_FDPIC", BFD_RELOC_ARM_TLS_LDM32_FDPIC
},
23150 { "gottpoff_fdpic", BFD_RELOC_ARM_TLS_IE32_FDPIC
}, { "GOTTPOFF_FDIC", BFD_RELOC_ARM_TLS_IE32_FDPIC
},
23154 /* Table of all conditional affixes. */
23155 static const struct asm_cond conds
[] =
23159 {"cs", 0x2}, {"hs", 0x2},
23160 {"cc", 0x3}, {"ul", 0x3}, {"lo", 0x3},
23173 static const struct asm_cond vconds
[] =
23179 #define UL_BARRIER(L,U,CODE,FEAT) \
23180 { L, CODE, ARM_FEATURE_CORE_LOW (FEAT) }, \
23181 { U, CODE, ARM_FEATURE_CORE_LOW (FEAT) }
23183 static struct asm_barrier_opt barrier_opt_names
[] =
23185 UL_BARRIER ("sy", "SY", 0xf, ARM_EXT_BARRIER
),
23186 UL_BARRIER ("st", "ST", 0xe, ARM_EXT_BARRIER
),
23187 UL_BARRIER ("ld", "LD", 0xd, ARM_EXT_V8
),
23188 UL_BARRIER ("ish", "ISH", 0xb, ARM_EXT_BARRIER
),
23189 UL_BARRIER ("sh", "SH", 0xb, ARM_EXT_BARRIER
),
23190 UL_BARRIER ("ishst", "ISHST", 0xa, ARM_EXT_BARRIER
),
23191 UL_BARRIER ("shst", "SHST", 0xa, ARM_EXT_BARRIER
),
23192 UL_BARRIER ("ishld", "ISHLD", 0x9, ARM_EXT_V8
),
23193 UL_BARRIER ("un", "UN", 0x7, ARM_EXT_BARRIER
),
23194 UL_BARRIER ("nsh", "NSH", 0x7, ARM_EXT_BARRIER
),
23195 UL_BARRIER ("unst", "UNST", 0x6, ARM_EXT_BARRIER
),
23196 UL_BARRIER ("nshst", "NSHST", 0x6, ARM_EXT_BARRIER
),
23197 UL_BARRIER ("nshld", "NSHLD", 0x5, ARM_EXT_V8
),
23198 UL_BARRIER ("osh", "OSH", 0x3, ARM_EXT_BARRIER
),
23199 UL_BARRIER ("oshst", "OSHST", 0x2, ARM_EXT_BARRIER
),
23200 UL_BARRIER ("oshld", "OSHLD", 0x1, ARM_EXT_V8
)
23205 /* Table of ARM-format instructions. */
23207 /* Macros for gluing together operand strings. N.B. In all cases
23208 other than OPS0, the trailing OP_stop comes from default
23209 zero-initialization of the unspecified elements of the array. */
23210 #define OPS0() { OP_stop, }
23211 #define OPS1(a) { OP_##a, }
23212 #define OPS2(a,b) { OP_##a,OP_##b, }
23213 #define OPS3(a,b,c) { OP_##a,OP_##b,OP_##c, }
23214 #define OPS4(a,b,c,d) { OP_##a,OP_##b,OP_##c,OP_##d, }
23215 #define OPS5(a,b,c,d,e) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e, }
23216 #define OPS6(a,b,c,d,e,f) { OP_##a,OP_##b,OP_##c,OP_##d,OP_##e,OP_##f, }
23218 /* These macros are similar to the OPSn, but do not prepend the OP_ prefix.
23219 This is useful when mixing operands for ARM and THUMB, i.e. using the
23220 MIX_ARM_THUMB_OPERANDS macro.
23221 In order to use these macros, prefix the number of operands with _
23223 #define OPS_1(a) { a, }
23224 #define OPS_2(a,b) { a,b, }
23225 #define OPS_3(a,b,c) { a,b,c, }
23226 #define OPS_4(a,b,c,d) { a,b,c,d, }
23227 #define OPS_5(a,b,c,d,e) { a,b,c,d,e, }
23228 #define OPS_6(a,b,c,d,e,f) { a,b,c,d,e,f, }
23230 /* These macros abstract out the exact format of the mnemonic table and
23231 save some repeated characters. */
23233 /* The normal sort of mnemonic; has a Thumb variant; takes a conditional suffix. */
23234 #define TxCE(mnem, op, top, nops, ops, ae, te) \
23235 { mnem, OPS##nops ops, OT_csuffix, 0x##op, top, ARM_VARIANT, \
23236 THUMB_VARIANT, do_##ae, do_##te, 0 }
23238 /* Two variants of the above - TCE for a numeric Thumb opcode, tCE for
23239 a T_MNEM_xyz enumerator. */
23240 #define TCE(mnem, aop, top, nops, ops, ae, te) \
23241 TxCE (mnem, aop, 0x##top, nops, ops, ae, te)
23242 #define tCE(mnem, aop, top, nops, ops, ae, te) \
23243 TxCE (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23245 /* Second most common sort of mnemonic: has a Thumb variant, takes a conditional
23246 infix after the third character. */
23247 #define TxC3(mnem, op, top, nops, ops, ae, te) \
23248 { mnem, OPS##nops ops, OT_cinfix3, 0x##op, top, ARM_VARIANT, \
23249 THUMB_VARIANT, do_##ae, do_##te, 0 }
23250 #define TxC3w(mnem, op, top, nops, ops, ae, te) \
23251 { mnem, OPS##nops ops, OT_cinfix3_deprecated, 0x##op, top, ARM_VARIANT, \
23252 THUMB_VARIANT, do_##ae, do_##te, 0 }
23253 #define TC3(mnem, aop, top, nops, ops, ae, te) \
23254 TxC3 (mnem, aop, 0x##top, nops, ops, ae, te)
23255 #define TC3w(mnem, aop, top, nops, ops, ae, te) \
23256 TxC3w (mnem, aop, 0x##top, nops, ops, ae, te)
23257 #define tC3(mnem, aop, top, nops, ops, ae, te) \
23258 TxC3 (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23259 #define tC3w(mnem, aop, top, nops, ops, ae, te) \
23260 TxC3w (mnem, aop, T_MNEM##top, nops, ops, ae, te)
23262 /* Mnemonic that cannot be conditionalized. The ARM condition-code
23263 field is still 0xE. Many of the Thumb variants can be executed
23264 conditionally, so this is checked separately. */
23265 #define TUE(mnem, op, top, nops, ops, ae, te) \
23266 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23267 THUMB_VARIANT, do_##ae, do_##te, 0 }
23269 /* Same as TUE but the encoding function for ARM and Thumb modes is the same.
23270 Used by mnemonics that have very minimal differences in the encoding for
23271 ARM and Thumb variants and can be handled in a common function. */
23272 #define TUEc(mnem, op, top, nops, ops, en) \
23273 { mnem, OPS##nops ops, OT_unconditional, 0x##op, 0x##top, ARM_VARIANT, \
23274 THUMB_VARIANT, do_##en, do_##en, 0 }
23276 /* Mnemonic that cannot be conditionalized, and bears 0xF in its ARM
23277 condition code field. */
23278 #define TUF(mnem, op, top, nops, ops, ae, te) \
23279 { mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##top, ARM_VARIANT, \
23280 THUMB_VARIANT, do_##ae, do_##te, 0 }
23282 /* ARM-only variants of all the above. */
23283 #define CE(mnem, op, nops, ops, ae) \
23284 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23286 #define C3(mnem, op, nops, ops, ae) \
23287 { #mnem, OPS##nops ops, OT_cinfix3, 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23289 /* Thumb-only variants of TCE and TUE. */
23290 #define ToC(mnem, top, nops, ops, te) \
23291 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23294 #define ToU(mnem, top, nops, ops, te) \
23295 { mnem, OPS##nops ops, OT_unconditional, 0x0, 0x##top, 0, THUMB_VARIANT, \
23298 /* T_MNEM_xyz enumerator variants of ToC. */
23299 #define toC(mnem, top, nops, ops, te) \
23300 { mnem, OPS##nops ops, OT_csuffix, 0x0, T_MNEM##top, 0, THUMB_VARIANT, NULL, \
23303 /* T_MNEM_xyz enumerator variants of ToU. */
23304 #define toU(mnem, top, nops, ops, te) \
23305 { mnem, OPS##nops ops, OT_unconditional, 0x0, T_MNEM##top, 0, THUMB_VARIANT, \
23308 /* Legacy mnemonics that always have conditional infix after the third
23310 #define CL(mnem, op, nops, ops, ae) \
23311 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23312 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23314 /* Coprocessor instructions. Isomorphic between Arm and Thumb-2. */
23315 #define cCE(mnem, op, nops, ops, ae) \
23316 { mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23318 /* mov instructions that are shared between coprocessor and MVE. */
23319 #define mcCE(mnem, op, nops, ops, ae) \
23320 { #mnem, OPS##nops ops, OT_csuffix, 0x##op, 0xe##op, ARM_VARIANT, THUMB_VARIANT, do_##ae, do_##ae, 0 }
23322 /* Legacy coprocessor instructions where conditional infix and conditional
23323 suffix are ambiguous. For consistency this includes all FPA instructions,
23324 not just the potentially ambiguous ones. */
23325 #define cCL(mnem, op, nops, ops, ae) \
23326 { mnem, OPS##nops ops, OT_cinfix3_legacy, \
23327 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23329 /* Coprocessor, takes either a suffix or a position-3 infix
23330 (for an FPA corner case). */
23331 #define C3E(mnem, op, nops, ops, ae) \
23332 { mnem, OPS##nops ops, OT_csuf_or_in3, \
23333 0x##op, 0xe##op, ARM_VARIANT, ARM_VARIANT, do_##ae, do_##ae, 0 }
23335 #define xCM_(m1, m2, m3, op, nops, ops, ae) \
23336 { m1 #m2 m3, OPS##nops ops, \
23337 sizeof (#m2) == 1 ? OT_odd_infix_unc : OT_odd_infix_0 + sizeof (m1) - 1, \
23338 0x##op, 0x0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23340 #define CM(m1, m2, op, nops, ops, ae) \
23341 xCM_ (m1, , m2, op, nops, ops, ae), \
23342 xCM_ (m1, eq, m2, op, nops, ops, ae), \
23343 xCM_ (m1, ne, m2, op, nops, ops, ae), \
23344 xCM_ (m1, cs, m2, op, nops, ops, ae), \
23345 xCM_ (m1, hs, m2, op, nops, ops, ae), \
23346 xCM_ (m1, cc, m2, op, nops, ops, ae), \
23347 xCM_ (m1, ul, m2, op, nops, ops, ae), \
23348 xCM_ (m1, lo, m2, op, nops, ops, ae), \
23349 xCM_ (m1, mi, m2, op, nops, ops, ae), \
23350 xCM_ (m1, pl, m2, op, nops, ops, ae), \
23351 xCM_ (m1, vs, m2, op, nops, ops, ae), \
23352 xCM_ (m1, vc, m2, op, nops, ops, ae), \
23353 xCM_ (m1, hi, m2, op, nops, ops, ae), \
23354 xCM_ (m1, ls, m2, op, nops, ops, ae), \
23355 xCM_ (m1, ge, m2, op, nops, ops, ae), \
23356 xCM_ (m1, lt, m2, op, nops, ops, ae), \
23357 xCM_ (m1, gt, m2, op, nops, ops, ae), \
23358 xCM_ (m1, le, m2, op, nops, ops, ae), \
23359 xCM_ (m1, al, m2, op, nops, ops, ae)
23361 #define UE(mnem, op, nops, ops, ae) \
23362 { #mnem, OPS##nops ops, OT_unconditional, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23364 #define UF(mnem, op, nops, ops, ae) \
23365 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0, ARM_VARIANT, 0, do_##ae, NULL, 0 }
23367 /* Neon data-processing. ARM versions are unconditional with cond=0xf.
23368 The Thumb and ARM variants are mostly the same (bits 0-23 and 24/28), so we
23369 use the same encoding function for each. */
23370 #define NUF(mnem, op, nops, ops, enc) \
23371 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23372 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23374 /* Neon data processing, version which indirects through neon_enc_tab for
23375 the various overloaded versions of opcodes. */
23376 #define nUF(mnem, op, nops, ops, enc) \
23377 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23378 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 0 }
23380 /* Neon insn with conditional suffix for the ARM version, non-overloaded
23382 #define NCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23383 { #mnem, OPS##nops ops, tag, 0x##op, 0x##op, ARM_VARIANT, \
23384 THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23386 #define NCE(mnem, op, nops, ops, enc) \
23387 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23389 #define NCEF(mnem, op, nops, ops, enc) \
23390 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23392 /* Neon insn with conditional suffix for the ARM version, overloaded types. */
23393 #define nCE_tag(mnem, op, nops, ops, enc, tag, mve_p) \
23394 { #mnem, OPS##nops ops, tag, N_MNEM##op, N_MNEM##op, \
23395 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, mve_p }
23397 #define nCE(mnem, op, nops, ops, enc) \
23398 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 0)
23400 #define nCEF(mnem, op, nops, ops, enc) \
23401 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 0)
23404 #define mCEF(mnem, op, nops, ops, enc) \
23405 { #mnem, OPS##nops ops, OT_csuffixF, M_MNEM##op, M_MNEM##op, \
23406 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23409 /* nCEF but for MVE predicated instructions. */
23410 #define mnCEF(mnem, op, nops, ops, enc) \
23411 nCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23413 /* nCE but for MVE predicated instructions. */
23414 #define mnCE(mnem, op, nops, ops, enc) \
23415 nCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23417 /* NUF but for potentially MVE predicated instructions. */
23418 #define MNUF(mnem, op, nops, ops, enc) \
23419 { #mnem, OPS##nops ops, OT_unconditionalF, 0x##op, 0x##op, \
23420 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23422 /* nUF but for potentially MVE predicated instructions. */
23423 #define mnUF(mnem, op, nops, ops, enc) \
23424 { #mnem, OPS##nops ops, OT_unconditionalF, N_MNEM##op, N_MNEM##op, \
23425 ARM_VARIANT, THUMB_VARIANT, do_##enc, do_##enc, 1 }
23427 /* ToC but for potentially MVE predicated instructions. */
23428 #define mToC(mnem, top, nops, ops, te) \
23429 { mnem, OPS##nops ops, OT_csuffix, 0x0, 0x##top, 0, THUMB_VARIANT, NULL, \
23432 /* NCE but for MVE predicated instructions. */
23433 #define MNCE(mnem, op, nops, ops, enc) \
23434 NCE_tag (mnem, op, nops, ops, enc, OT_csuffix, 1)
23436 /* NCEF but for MVE predicated instructions. */
23437 #define MNCEF(mnem, op, nops, ops, enc) \
23438 NCE_tag (mnem, op, nops, ops, enc, OT_csuffixF, 1)
23441 static const struct asm_opcode insns
[] =
23443 #define ARM_VARIANT & arm_ext_v1 /* Core ARM Instructions. */
23444 #define THUMB_VARIANT & arm_ext_v4t
23445 tCE("and", 0000000, _and
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23446 tC3("ands", 0100000, _ands
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23447 tCE("eor", 0200000, _eor
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23448 tC3("eors", 0300000, _eors
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23449 tCE("sub", 0400000, _sub
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23450 tC3("subs", 0500000, _subs
, 3, (RR
, oRR
, SH
), arit
, t_add_sub
),
23451 tCE("add", 0800000, _add
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23452 tC3("adds", 0900000, _adds
, 3, (RR
, oRR
, SHG
), arit
, t_add_sub
),
23453 tCE("adc", 0a00000
, _adc
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23454 tC3("adcs", 0b00000, _adcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23455 tCE("sbc", 0c00000
, _sbc
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23456 tC3("sbcs", 0d00000
, _sbcs
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23457 tCE("orr", 1800000, _orr
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23458 tC3("orrs", 1900000, _orrs
, 3, (RR
, oRR
, SH
), arit
, t_arit3c
),
23459 tCE("bic", 1c00000
, _bic
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23460 tC3("bics", 1d00000
, _bics
, 3, (RR
, oRR
, SH
), arit
, t_arit3
),
23462 /* The p-variants of tst/cmp/cmn/teq (below) are the pre-V6 mechanism
23463 for setting PSR flag bits. They are obsolete in V6 and do not
23464 have Thumb equivalents. */
23465 tCE("tst", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23466 tC3w("tsts", 1100000, _tst
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23467 CL("tstp", 110f000
, 2, (RR
, SH
), cmp
),
23468 tCE("cmp", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23469 tC3w("cmps", 1500000, _cmp
, 2, (RR
, SH
), cmp
, t_mov_cmp
),
23470 CL("cmpp", 150f000
, 2, (RR
, SH
), cmp
),
23471 tCE("cmn", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23472 tC3w("cmns", 1700000, _cmn
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23473 CL("cmnp", 170f000
, 2, (RR
, SH
), cmp
),
23475 tCE("mov", 1a00000
, _mov
, 2, (RR
, SH
), mov
, t_mov_cmp
),
23476 tC3("movs", 1b00000
, _movs
, 2, (RR
, SHG
), mov
, t_mov_cmp
),
23477 tCE("mvn", 1e00000
, _mvn
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23478 tC3("mvns", 1f00000
, _mvns
, 2, (RR
, SH
), mov
, t_mvn_tst
),
23480 tCE("ldr", 4100000, _ldr
, 2, (RR
, ADDRGLDR
),ldst
, t_ldst
),
23481 tC3("ldrb", 4500000, _ldrb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23482 tCE("str", 4000000, _str
, _2
, (MIX_ARM_THUMB_OPERANDS (OP_RR
,
23484 OP_ADDRGLDR
),ldst
, t_ldst
),
23485 tC3("strb", 4400000, _strb
, 2, (RRnpc_npcsp
, ADDRGLDR
),ldst
, t_ldst
),
23487 tCE("stm", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23488 tC3("stmia", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23489 tC3("stmea", 8800000, _stmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23490 tCE("ldm", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23491 tC3("ldmia", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23492 tC3("ldmfd", 8900000, _ldmia
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23494 tCE("b", a000000
, _b
, 1, (EXPr
), branch
, t_branch
),
23495 TCE("bl", b000000
, f000f800
, 1, (EXPr
), bl
, t_branch23
),
23498 tCE("adr", 28f0000
, _adr
, 2, (RR
, EXP
), adr
, t_adr
),
23499 C3(adrl
, 28f0000
, 2, (RR
, EXP
), adrl
),
23500 tCE("nop", 1a00000
, _nop
, 1, (oI255c
), nop
, t_nop
),
23501 tCE("udf", 7f000f0
, _udf
, 1, (oIffffb
), bkpt
, t_udf
),
23503 /* Thumb-compatibility pseudo ops. */
23504 tCE("lsl", 1a00000
, _lsl
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23505 tC3("lsls", 1b00000
, _lsls
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23506 tCE("lsr", 1a00020
, _lsr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23507 tC3("lsrs", 1b00020
, _lsrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23508 tCE("asr", 1a00040
, _asr
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23509 tC3("asrs", 1b00040
, _asrs
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23510 tCE("ror", 1a00060
, _ror
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23511 tC3("rors", 1b00060
, _rors
, 3, (RR
, oRR
, SH
), shift
, t_shift
),
23512 tCE("neg", 2600000, _neg
, 2, (RR
, RR
), rd_rn
, t_neg
),
23513 tC3("negs", 2700000, _negs
, 2, (RR
, RR
), rd_rn
, t_neg
),
23514 tCE("push", 92d0000
, _push
, 1, (REGLST
), push_pop
, t_push_pop
),
23515 tCE("pop", 8bd0000
, _pop
, 1, (REGLST
), push_pop
, t_push_pop
),
23517 /* These may simplify to neg. */
23518 TCE("rsb", 0600000, ebc00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23519 TC3("rsbs", 0700000, ebd00000
, 3, (RR
, oRR
, SH
), arit
, t_rsb
),
23521 #undef THUMB_VARIANT
23522 #define THUMB_VARIANT & arm_ext_os
23524 TCE("swi", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23525 TCE("svc", f000000
, df00
, 1, (EXPi
), swi
, t_swi
),
23527 #undef THUMB_VARIANT
23528 #define THUMB_VARIANT & arm_ext_v6
23530 TCE("cpy", 1a00000
, 4600, 2, (RR
, RR
), rd_rm
, t_cpy
),
23532 /* V1 instructions with no Thumb analogue prior to V6T2. */
23533 #undef THUMB_VARIANT
23534 #define THUMB_VARIANT & arm_ext_v6t2
23536 TCE("teq", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23537 TC3w("teqs", 1300000, ea900f00
, 2, (RR
, SH
), cmp
, t_mvn_tst
),
23538 CL("teqp", 130f000
, 2, (RR
, SH
), cmp
),
23540 TC3("ldrt", 4300000, f8500e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23541 TC3("ldrbt", 4700000, f8100e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23542 TC3("strt", 4200000, f8400e00
, 2, (RR_npcsp
, ADDR
), ldstt
, t_ldstt
),
23543 TC3("strbt", 4600000, f8000e00
, 2, (RRnpc_npcsp
, ADDR
),ldstt
, t_ldstt
),
23545 TC3("stmdb", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23546 TC3("stmfd", 9000000, e9000000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23548 TC3("ldmdb", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23549 TC3("ldmea", 9100000, e9100000
, 2, (RRw
, REGLST
), ldmstm
, t_ldmstm
),
23551 /* V1 instructions with no Thumb analogue at all. */
23552 CE("rsc", 0e00000
, 3, (RR
, oRR
, SH
), arit
),
23553 C3(rscs
, 0f00000
, 3, (RR
, oRR
, SH
), arit
),
23555 C3(stmib
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23556 C3(stmfa
, 9800000, 2, (RRw
, REGLST
), ldmstm
),
23557 C3(stmda
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23558 C3(stmed
, 8000000, 2, (RRw
, REGLST
), ldmstm
),
23559 C3(ldmib
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23560 C3(ldmed
, 9900000, 2, (RRw
, REGLST
), ldmstm
),
23561 C3(ldmda
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23562 C3(ldmfa
, 8100000, 2, (RRw
, REGLST
), ldmstm
),
23565 #define ARM_VARIANT & arm_ext_v2 /* ARM 2 - multiplies. */
23566 #undef THUMB_VARIANT
23567 #define THUMB_VARIANT & arm_ext_v4t
23569 tCE("mul", 0000090, _mul
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23570 tC3("muls", 0100090, _muls
, 3, (RRnpc
, RRnpc
, oRR
), mul
, t_mul
),
23572 #undef THUMB_VARIANT
23573 #define THUMB_VARIANT & arm_ext_v6t2
23575 TCE("mla", 0200090, fb000000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23576 C3(mlas
, 0300090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
),
23578 /* Generic coprocessor instructions. */
23579 TCE("cdp", e000000
, ee000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23580 TCE("ldc", c100000
, ec100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23581 TC3("ldcl", c500000
, ec500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23582 TCE("stc", c000000
, ec000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23583 TC3("stcl", c400000
, ec400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23584 TCE("mcr", e000010
, ee000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23585 TCE("mrc", e100010
, ee100010
, 6, (RCP
, I7b
, APSR_RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23588 #define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */
23590 CE("swp", 1000090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23591 C3(swpb
, 1400090, 3, (RRnpc
, RRnpc
, RRnpcb
), rd_rm_rn
),
23594 #define ARM_VARIANT & arm_ext_v3 /* ARM 6 Status register instructions. */
23595 #undef THUMB_VARIANT
23596 #define THUMB_VARIANT & arm_ext_msr
23598 TCE("mrs", 1000000, f3e08000
, 2, (RRnpc
, rPSR
), mrs
, t_mrs
),
23599 TCE("msr", 120f000
, f3808000
, 2, (wPSR
, RR_EXi
), msr
, t_msr
),
23602 #define ARM_VARIANT & arm_ext_v3m /* ARM 7M long multiplies. */
23603 #undef THUMB_VARIANT
23604 #define THUMB_VARIANT & arm_ext_v6t2
23606 TCE("smull", 0c00090
, fb800000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23607 CM("smull","s", 0d00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23608 TCE("umull", 0800090, fba00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23609 CM("umull","s", 0900090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23610 TCE("smlal", 0e00090
, fbc00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23611 CM("smlal","s", 0f00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23612 TCE("umlal", 0a00090
, fbe00000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
, t_mull
),
23613 CM("umlal","s", 0b00090, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mull
),
23616 #define ARM_VARIANT & arm_ext_v4 /* ARM Architecture 4. */
23617 #undef THUMB_VARIANT
23618 #define THUMB_VARIANT & arm_ext_v4t
23620 tC3("ldrh", 01000b0
, _ldrh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23621 tC3("strh", 00000b0
, _strh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23622 tC3("ldrsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23623 tC3("ldrsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23624 tC3("ldsh", 01000f0
, _ldrsh
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23625 tC3("ldsb", 01000d0
, _ldrsb
, 2, (RRnpc_npcsp
, ADDRGLDRS
), ldstv4
, t_ldst
),
23628 #define ARM_VARIANT & arm_ext_v4t_5
23630 /* ARM Architecture 4T. */
23631 /* Note: bx (and blx) are required on V5, even if the processor does
23632 not support Thumb. */
23633 TCE("bx", 12fff10
, 4700, 1, (RR
), bx
, t_bx
),
23636 #define ARM_VARIANT & arm_ext_v5 /* ARM Architecture 5T. */
23637 #undef THUMB_VARIANT
23638 #define THUMB_VARIANT & arm_ext_v5t
23640 /* Note: blx has 2 variants; the .value coded here is for
23641 BLX(2). Only this variant has conditional execution. */
23642 TCE("blx", 12fff30
, 4780, 1, (RR_EXr
), blx
, t_blx
),
23643 TUE("bkpt", 1200070, be00
, 1, (oIffffb
), bkpt
, t_bkpt
),
23645 #undef THUMB_VARIANT
23646 #define THUMB_VARIANT & arm_ext_v6t2
23648 TCE("clz", 16f0f10
, fab0f080
, 2, (RRnpc
, RRnpc
), rd_rm
, t_clz
),
23649 TUF("ldc2", c100000
, fc100000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23650 TUF("ldc2l", c500000
, fc500000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23651 TUF("stc2", c000000
, fc000000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23652 TUF("stc2l", c400000
, fc400000
, 3, (RCP
, RCN
, ADDRGLDC
), lstc
, lstc
),
23653 TUF("cdp2", e000000
, fe000000
, 6, (RCP
, I15b
, RCN
, RCN
, RCN
, oI7b
), cdp
, cdp
),
23654 TUF("mcr2", e000010
, fe000010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23655 TUF("mrc2", e100010
, fe100010
, 6, (RCP
, I7b
, RR
, RCN
, RCN
, oI7b
), co_reg
, co_reg
),
23658 #define ARM_VARIANT & arm_ext_v5exp /* ARM Architecture 5TExP. */
23659 #undef THUMB_VARIANT
23660 #define THUMB_VARIANT & arm_ext_v5exp
23662 TCE("smlabb", 1000080, fb100000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23663 TCE("smlatb", 10000a0
, fb100020
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23664 TCE("smlabt", 10000c0
, fb100010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23665 TCE("smlatt", 10000e0
, fb100030
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23667 TCE("smlawb", 1200080, fb300000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23668 TCE("smlawt", 12000c0
, fb300010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smla
, t_mla
),
23670 TCE("smlalbb", 1400080, fbc00080
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23671 TCE("smlaltb", 14000a0
, fbc000a0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23672 TCE("smlalbt", 14000c0
, fbc00090
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23673 TCE("smlaltt", 14000e0
, fbc000b0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), smlal
, t_mlal
),
23675 TCE("smulbb", 1600080, fb10f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23676 TCE("smultb", 16000a0
, fb10f020
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23677 TCE("smulbt", 16000c0
, fb10f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23678 TCE("smultt", 16000e0
, fb10f030
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23680 TCE("smulwb", 12000a0
, fb30f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23681 TCE("smulwt", 12000e0
, fb30f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23683 TCE("qadd", 1000050, fa80f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23684 TCE("qdadd", 1400050, fa80f090
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23685 TCE("qsub", 1200050, fa80f0a0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23686 TCE("qdsub", 1600050, fa80f0b0
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rm_rn
, t_simd2
),
23689 #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */
23690 #undef THUMB_VARIANT
23691 #define THUMB_VARIANT & arm_ext_v6t2
23693 TUF("pld", 450f000
, f810f000
, 1, (ADDR
), pld
, t_pld
),
23694 TC3("ldrd", 00000d0
, e8500000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, ADDRGLDRS
),
23696 TC3("strd", 00000f0
, e8400000
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
,
23697 ADDRGLDRS
), ldrd
, t_ldstd
),
23699 TCE("mcrr", c400000
, ec400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23700 TCE("mrrc", c500000
, ec500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23703 #define ARM_VARIANT & arm_ext_v5j /* ARM Architecture 5TEJ. */
23705 TCE("bxj", 12fff20
, f3c08f00
, 1, (RR
), bxj
, t_bxj
),
23708 #define ARM_VARIANT & arm_ext_v6 /* ARM V6. */
23709 #undef THUMB_VARIANT
23710 #define THUMB_VARIANT & arm_ext_v6
23712 TUF("cpsie", 1080000, b660
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23713 TUF("cpsid", 10c0000
, b670
, 2, (CPSF
, oI31b
), cpsi
, t_cpsi
),
23714 tCE("rev", 6bf0f30
, _rev
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23715 tCE("rev16", 6bf0fb0
, _rev16
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23716 tCE("revsh", 6ff0fb0
, _revsh
, 2, (RRnpc
, RRnpc
), rd_rm
, t_rev
),
23717 tCE("sxth", 6bf0070
, _sxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23718 tCE("uxth", 6ff0070
, _uxth
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23719 tCE("sxtb", 6af0070
, _sxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23720 tCE("uxtb", 6ef0070
, _uxtb
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23721 TUF("setend", 1010000, b650
, 1, (ENDI
), setend
, t_setend
),
23723 #undef THUMB_VARIANT
23724 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23726 TCE("ldrex", 1900f9f
, e8500f00
, 2, (RRnpc_npcsp
, ADDR
), ldrex
, t_ldrex
),
23727 TCE("strex", 1800f90
, e8400000
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23729 #undef THUMB_VARIANT
23730 #define THUMB_VARIANT & arm_ext_v6t2
23732 TUF("mcrr2", c400000
, fc400000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23733 TUF("mrrc2", c500000
, fc500000
, 5, (RCP
, I15b
, RRnpc
, RRnpc
, RCN
), co_reg2c
, co_reg2c
),
23735 TCE("ssat", 6a00010
, f3000000
, 4, (RRnpc
, I32
, RRnpc
, oSHllar
),ssat
, t_ssat
),
23736 TCE("usat", 6e00010
, f3800000
, 4, (RRnpc
, I31
, RRnpc
, oSHllar
),usat
, t_usat
),
23738 /* ARM V6 not included in V7M. */
23739 #undef THUMB_VARIANT
23740 #define THUMB_VARIANT & arm_ext_v6_notm
23741 TUF("rfeia", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23742 TUF("rfe", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23743 UF(rfeib
, 9900a00
, 1, (RRw
), rfe
),
23744 UF(rfeda
, 8100a00
, 1, (RRw
), rfe
),
23745 TUF("rfedb", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23746 TUF("rfefd", 8900a00
, e990c000
, 1, (RRw
), rfe
, rfe
),
23747 UF(rfefa
, 8100a00
, 1, (RRw
), rfe
),
23748 TUF("rfeea", 9100a00
, e810c000
, 1, (RRw
), rfe
, rfe
),
23749 UF(rfeed
, 9900a00
, 1, (RRw
), rfe
),
23750 TUF("srsia", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23751 TUF("srs", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23752 TUF("srsea", 8c00500
, e980c000
, 2, (oRRw
, I31w
), srs
, srs
),
23753 UF(srsib
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23754 UF(srsfa
, 9c00500
, 2, (oRRw
, I31w
), srs
),
23755 UF(srsda
, 8400500, 2, (oRRw
, I31w
), srs
),
23756 UF(srsed
, 8400500, 2, (oRRw
, I31w
), srs
),
23757 TUF("srsdb", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23758 TUF("srsfd", 9400500, e800c000
, 2, (oRRw
, I31w
), srs
, srs
),
23759 TUF("cps", 1020000, f3af8100
, 1, (I31b
), imm0
, t_cps
),
23761 /* ARM V6 not included in V7M (eg. integer SIMD). */
23762 #undef THUMB_VARIANT
23763 #define THUMB_VARIANT & arm_ext_v6_dsp
23764 TCE("pkhbt", 6800010, eac00000
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHll
), pkhbt
, t_pkhbt
),
23765 TCE("pkhtb", 6800050, eac00020
, 4, (RRnpc
, RRnpc
, RRnpc
, oSHar
), pkhtb
, t_pkhtb
),
23766 TCE("qadd16", 6200f10
, fa90f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23767 TCE("qadd8", 6200f90
, fa80f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23768 TCE("qasx", 6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23769 /* Old name for QASX. */
23770 TCE("qaddsubx",6200f30
, faa0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23771 TCE("qsax", 6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23772 /* Old name for QSAX. */
23773 TCE("qsubaddx",6200f50
, fae0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23774 TCE("qsub16", 6200f70
, fad0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23775 TCE("qsub8", 6200ff0
, fac0f010
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23776 TCE("sadd16", 6100f10
, fa90f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23777 TCE("sadd8", 6100f90
, fa80f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23778 TCE("sasx", 6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23779 /* Old name for SASX. */
23780 TCE("saddsubx",6100f30
, faa0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23781 TCE("shadd16", 6300f10
, fa90f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23782 TCE("shadd8", 6300f90
, fa80f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23783 TCE("shasx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23784 /* Old name for SHASX. */
23785 TCE("shaddsubx", 6300f30
, faa0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23786 TCE("shsax", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23787 /* Old name for SHSAX. */
23788 TCE("shsubaddx", 6300f50
, fae0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23789 TCE("shsub16", 6300f70
, fad0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23790 TCE("shsub8", 6300ff0
, fac0f020
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23791 TCE("ssax", 6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23792 /* Old name for SSAX. */
23793 TCE("ssubaddx",6100f50
, fae0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23794 TCE("ssub16", 6100f70
, fad0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23795 TCE("ssub8", 6100ff0
, fac0f000
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23796 TCE("uadd16", 6500f10
, fa90f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23797 TCE("uadd8", 6500f90
, fa80f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23798 TCE("uasx", 6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23799 /* Old name for UASX. */
23800 TCE("uaddsubx",6500f30
, faa0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23801 TCE("uhadd16", 6700f10
, fa90f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23802 TCE("uhadd8", 6700f90
, fa80f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23803 TCE("uhasx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23804 /* Old name for UHASX. */
23805 TCE("uhaddsubx", 6700f30
, faa0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23806 TCE("uhsax", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23807 /* Old name for UHSAX. */
23808 TCE("uhsubaddx", 6700f50
, fae0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23809 TCE("uhsub16", 6700f70
, fad0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23810 TCE("uhsub8", 6700ff0
, fac0f060
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23811 TCE("uqadd16", 6600f10
, fa90f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23812 TCE("uqadd8", 6600f90
, fa80f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23813 TCE("uqasx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23814 /* Old name for UQASX. */
23815 TCE("uqaddsubx", 6600f30
, faa0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23816 TCE("uqsax", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23817 /* Old name for UQSAX. */
23818 TCE("uqsubaddx", 6600f50
, fae0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23819 TCE("uqsub16", 6600f70
, fad0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23820 TCE("uqsub8", 6600ff0
, fac0f050
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23821 TCE("usub16", 6500f70
, fad0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23822 TCE("usax", 6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23823 /* Old name for USAX. */
23824 TCE("usubaddx",6500f50
, fae0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23825 TCE("usub8", 6500ff0
, fac0f040
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23826 TCE("sxtah", 6b00070
, fa00f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23827 TCE("sxtab16", 6800070, fa20f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23828 TCE("sxtab", 6a00070
, fa40f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23829 TCE("sxtb16", 68f0070
, fa2ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23830 TCE("uxtah", 6f00070
, fa10f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23831 TCE("uxtab16", 6c00070
, fa30f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23832 TCE("uxtab", 6e00070
, fa50f080
, 4, (RRnpc
, RRnpc
, RRnpc
, oROR
), sxtah
, t_sxtah
),
23833 TCE("uxtb16", 6cf0070
, fa3ff080
, 3, (RRnpc
, RRnpc
, oROR
), sxth
, t_sxth
),
23834 TCE("sel", 6800fb0
, faa0f080
, 3, (RRnpc
, RRnpc
, RRnpc
), rd_rn_rm
, t_simd
),
23835 TCE("smlad", 7000010, fb200000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23836 TCE("smladx", 7000030, fb200010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23837 TCE("smlald", 7400010, fbc000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23838 TCE("smlaldx", 7400030, fbc000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23839 TCE("smlsd", 7000050, fb400000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23840 TCE("smlsdx", 7000070, fb400010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23841 TCE("smlsld", 7400050, fbd000c0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23842 TCE("smlsldx", 7400070, fbd000d0
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
,t_mlal
),
23843 TCE("smmla", 7500010, fb500000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23844 TCE("smmlar", 7500030, fb500010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23845 TCE("smmls", 75000d0
, fb600000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23846 TCE("smmlsr", 75000f0
, fb600010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23847 TCE("smmul", 750f010
, fb50f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23848 TCE("smmulr", 750f030
, fb50f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23849 TCE("smuad", 700f010
, fb20f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23850 TCE("smuadx", 700f030
, fb20f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23851 TCE("smusd", 700f050
, fb40f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23852 TCE("smusdx", 700f070
, fb40f010
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23853 TCE("ssat16", 6a00f30
, f3200000
, 3, (RRnpc
, I16
, RRnpc
), ssat16
, t_ssat16
),
23854 TCE("umaal", 0400090, fbe00060
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smlal
, t_mlal
),
23855 TCE("usad8", 780f010
, fb70f000
, 3, (RRnpc
, RRnpc
, RRnpc
), smul
, t_simd
),
23856 TCE("usada8", 7800010, fb700000
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
),smla
, t_mla
),
23857 TCE("usat16", 6e00f30
, f3a00000
, 3, (RRnpc
, I15
, RRnpc
), usat16
, t_usat16
),
23860 #define ARM_VARIANT & arm_ext_v6k_v6t2
23861 #undef THUMB_VARIANT
23862 #define THUMB_VARIANT & arm_ext_v6k_v6t2
23864 tCE("yield", 320f001
, _yield
, 0, (), noargs
, t_hint
),
23865 tCE("wfe", 320f002
, _wfe
, 0, (), noargs
, t_hint
),
23866 tCE("wfi", 320f003
, _wfi
, 0, (), noargs
, t_hint
),
23867 tCE("sev", 320f004
, _sev
, 0, (), noargs
, t_hint
),
23869 #undef THUMB_VARIANT
23870 #define THUMB_VARIANT & arm_ext_v6_notm
23871 TCE("ldrexd", 1b00f9f
, e8d0007f
, 3, (RRnpc_npcsp
, oRRnpc_npcsp
, RRnpcb
),
23873 TCE("strexd", 1a00f90
, e8c00070
, 4, (RRnpc_npcsp
, RRnpc_npcsp
, oRRnpc_npcsp
,
23874 RRnpcb
), strexd
, t_strexd
),
23876 #undef THUMB_VARIANT
23877 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23878 TCE("ldrexb", 1d00f9f
, e8d00f4f
, 2, (RRnpc_npcsp
,RRnpcb
),
23880 TCE("ldrexh", 1f00f9f
, e8d00f5f
, 2, (RRnpc_npcsp
, RRnpcb
),
23882 TCE("strexb", 1c00f90
, e8c00f40
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23884 TCE("strexh", 1e00f90
, e8c00f50
, 3, (RRnpc_npcsp
, RRnpc_npcsp
, ADDR
),
23886 TUF("clrex", 57ff01f
, f3bf8f2f
, 0, (), noargs
, noargs
),
23889 #define ARM_VARIANT & arm_ext_sec
23890 #undef THUMB_VARIANT
23891 #define THUMB_VARIANT & arm_ext_sec
23893 TCE("smc", 1600070, f7f08000
, 1, (EXPi
), smc
, t_smc
),
23896 #define ARM_VARIANT & arm_ext_virt
23897 #undef THUMB_VARIANT
23898 #define THUMB_VARIANT & arm_ext_virt
23900 TCE("hvc", 1400070, f7e08000
, 1, (EXPi
), hvc
, t_hvc
),
23901 TCE("eret", 160006e
, f3de8f00
, 0, (), noargs
, noargs
),
23904 #define ARM_VARIANT & arm_ext_pan
23905 #undef THUMB_VARIANT
23906 #define THUMB_VARIANT & arm_ext_pan
23908 TUF("setpan", 1100000, b610
, 1, (I7
), setpan
, t_setpan
),
23911 #define ARM_VARIANT & arm_ext_v6t2
23912 #undef THUMB_VARIANT
23913 #define THUMB_VARIANT & arm_ext_v6t2
23915 TCE("bfc", 7c0001f
, f36f0000
, 3, (RRnpc
, I31
, I32
), bfc
, t_bfc
),
23916 TCE("bfi", 7c00010
, f3600000
, 4, (RRnpc
, RRnpc_I0
, I31
, I32
), bfi
, t_bfi
),
23917 TCE("sbfx", 7a00050
, f3400000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23918 TCE("ubfx", 7e00050
, f3c00000
, 4, (RR
, RR
, I31
, I32
), bfx
, t_bfx
),
23920 TCE("mls", 0600090, fb000010
, 4, (RRnpc
, RRnpc
, RRnpc
, RRnpc
), mlas
, t_mla
),
23921 TCE("rbit", 6ff0f30
, fa90f0a0
, 2, (RR
, RR
), rd_rm
, t_rbit
),
23923 TC3("ldrht", 03000b0
, f8300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23924 TC3("ldrsht", 03000f0
, f9300e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23925 TC3("ldrsbt", 03000d0
, f9100e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23926 TC3("strht", 02000b0
, f8200e00
, 2, (RRnpc_npcsp
, ADDR
), ldsttv4
, t_ldstt
),
23929 #define ARM_VARIANT & arm_ext_v3
23930 #undef THUMB_VARIANT
23931 #define THUMB_VARIANT & arm_ext_v6t2
23933 TUE("csdb", 320f014
, f3af8014
, 0, (), noargs
, t_csdb
),
23934 TUF("ssbb", 57ff040
, f3bf8f40
, 0, (), noargs
, t_csdb
),
23935 TUF("pssbb", 57ff044
, f3bf8f44
, 0, (), noargs
, t_csdb
),
23938 #define ARM_VARIANT & arm_ext_v6t2
23939 #undef THUMB_VARIANT
23940 #define THUMB_VARIANT & arm_ext_v6t2_v8m
23941 TCE("movw", 3000000, f2400000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23942 TCE("movt", 3400000, f2c00000
, 2, (RRnpc
, HALF
), mov16
, t_mov16
),
23944 /* Thumb-only instructions. */
23946 #define ARM_VARIANT NULL
23947 TUE("cbnz", 0, b900
, 2, (RR
, EXP
), 0, t_cbz
),
23948 TUE("cbz", 0, b100
, 2, (RR
, EXP
), 0, t_cbz
),
23950 /* ARM does not really have an IT instruction, so always allow it.
23951 The opcode is copied from Thumb in order to allow warnings in
23952 -mimplicit-it=[never | arm] modes. */
23954 #define ARM_VARIANT & arm_ext_v1
23955 #undef THUMB_VARIANT
23956 #define THUMB_VARIANT & arm_ext_v6t2
23958 TUE("it", bf08
, bf08
, 1, (COND
), it
, t_it
),
23959 TUE("itt", bf0c
, bf0c
, 1, (COND
), it
, t_it
),
23960 TUE("ite", bf04
, bf04
, 1, (COND
), it
, t_it
),
23961 TUE("ittt", bf0e
, bf0e
, 1, (COND
), it
, t_it
),
23962 TUE("itet", bf06
, bf06
, 1, (COND
), it
, t_it
),
23963 TUE("itte", bf0a
, bf0a
, 1, (COND
), it
, t_it
),
23964 TUE("itee", bf02
, bf02
, 1, (COND
), it
, t_it
),
23965 TUE("itttt", bf0f
, bf0f
, 1, (COND
), it
, t_it
),
23966 TUE("itett", bf07
, bf07
, 1, (COND
), it
, t_it
),
23967 TUE("ittet", bf0b
, bf0b
, 1, (COND
), it
, t_it
),
23968 TUE("iteet", bf03
, bf03
, 1, (COND
), it
, t_it
),
23969 TUE("ittte", bf0d
, bf0d
, 1, (COND
), it
, t_it
),
23970 TUE("itete", bf05
, bf05
, 1, (COND
), it
, t_it
),
23971 TUE("ittee", bf09
, bf09
, 1, (COND
), it
, t_it
),
23972 TUE("iteee", bf01
, bf01
, 1, (COND
), it
, t_it
),
23973 /* ARM/Thumb-2 instructions with no Thumb-1 equivalent. */
23974 TC3("rrx", 01a00060
, ea4f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23975 TC3("rrxs", 01b00060
, ea5f0030
, 2, (RR
, RR
), rd_rm
, t_rrx
),
23977 /* Thumb2 only instructions. */
23979 #define ARM_VARIANT NULL
23981 TCE("addw", 0, f2000000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23982 TCE("subw", 0, f2a00000
, 3, (RR
, RR
, EXPi
), 0, t_add_sub_w
),
23983 TCE("orn", 0, ea600000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23984 TCE("orns", 0, ea700000
, 3, (RR
, oRR
, SH
), 0, t_orn
),
23985 TCE("tbb", 0, e8d0f000
, 1, (TB
), 0, t_tb
),
23986 TCE("tbh", 0, e8d0f010
, 1, (TB
), 0, t_tb
),
23988 /* Hardware division instructions. */
23990 #define ARM_VARIANT & arm_ext_adiv
23991 #undef THUMB_VARIANT
23992 #define THUMB_VARIANT & arm_ext_div
23994 TCE("sdiv", 710f010
, fb90f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23995 TCE("udiv", 730f010
, fbb0f0f0
, 3, (RR
, oRR
, RR
), div
, t_div
),
23997 /* ARM V6M/V7 instructions. */
23999 #define ARM_VARIANT & arm_ext_barrier
24000 #undef THUMB_VARIANT
24001 #define THUMB_VARIANT & arm_ext_barrier
24003 TUF("dmb", 57ff050
, f3bf8f50
, 1, (oBARRIER_I15
), barrier
, barrier
),
24004 TUF("dsb", 57ff040
, f3bf8f40
, 1, (oBARRIER_I15
), barrier
, barrier
),
24005 TUF("isb", 57ff060
, f3bf8f60
, 1, (oBARRIER_I15
), barrier
, barrier
),
24007 /* ARM V7 instructions. */
24009 #define ARM_VARIANT & arm_ext_v7
24010 #undef THUMB_VARIANT
24011 #define THUMB_VARIANT & arm_ext_v7
24013 TUF("pli", 450f000
, f910f000
, 1, (ADDR
), pli
, t_pld
),
24014 TCE("dbg", 320f0f0
, f3af80f0
, 1, (I15
), dbg
, t_dbg
),
24017 #define ARM_VARIANT & arm_ext_mp
24018 #undef THUMB_VARIANT
24019 #define THUMB_VARIANT & arm_ext_mp
24021 TUF("pldw", 410f000
, f830f000
, 1, (ADDR
), pld
, t_pld
),
24023 /* AArchv8 instructions. */
24025 #define ARM_VARIANT & arm_ext_v8
24027 /* Instructions shared between armv8-a and armv8-m. */
24028 #undef THUMB_VARIANT
24029 #define THUMB_VARIANT & arm_ext_atomics
24031 TCE("lda", 1900c9f
, e8d00faf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24032 TCE("ldab", 1d00c9f
, e8d00f8f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24033 TCE("ldah", 1f00c9f
, e8d00f9f
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24034 TCE("stl", 180fc90
, e8c00faf
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24035 TCE("stlb", 1c0fc90
, e8c00f8f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24036 TCE("stlh", 1e0fc90
, e8c00f9f
, 2, (RRnpc
, RRnpcb
), rm_rn
, rd_rn
),
24037 TCE("ldaex", 1900e9f
, e8d00fef
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24038 TCE("ldaexb", 1d00e9f
, e8d00fcf
, 2, (RRnpc
,RRnpcb
), rd_rn
, rd_rn
),
24039 TCE("ldaexh", 1f00e9f
, e8d00fdf
, 2, (RRnpc
, RRnpcb
), rd_rn
, rd_rn
),
24040 TCE("stlex", 1800e90
, e8c00fe0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24042 TCE("stlexb", 1c00e90
, e8c00fc0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24044 TCE("stlexh", 1e00e90
, e8c00fd0
, 3, (RRnpc
, RRnpc
, RRnpcb
),
24046 #undef THUMB_VARIANT
24047 #define THUMB_VARIANT & arm_ext_v8
24049 tCE("sevl", 320f005
, _sevl
, 0, (), noargs
, t_hint
),
24050 TCE("ldaexd", 1b00e9f
, e8d000ff
, 3, (RRnpc
, oRRnpc
, RRnpcb
),
24052 TCE("stlexd", 1a00e90
, e8c000f0
, 4, (RRnpc
, RRnpc
, oRRnpc
, RRnpcb
),
24055 /* Defined in V8 but is in undefined encoding space for earlier
24056 architectures. However earlier architectures are required to treat
24057 this instuction as a semihosting trap as well. Hence while not explicitly
24058 defined as such, it is in fact correct to define the instruction for all
24060 #undef THUMB_VARIANT
24061 #define THUMB_VARIANT & arm_ext_v1
24063 #define ARM_VARIANT & arm_ext_v1
24064 TUE("hlt", 1000070, ba80
, 1, (oIffffb
), bkpt
, t_hlt
),
24066 /* ARMv8 T32 only. */
24068 #define ARM_VARIANT NULL
24069 TUF("dcps1", 0, f78f8001
, 0, (), noargs
, noargs
),
24070 TUF("dcps2", 0, f78f8002
, 0, (), noargs
, noargs
),
24071 TUF("dcps3", 0, f78f8003
, 0, (), noargs
, noargs
),
24073 /* FP for ARMv8. */
24075 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
24076 #undef THUMB_VARIANT
24077 #define THUMB_VARIANT & fpu_vfp_ext_armv8xd
24079 nUF(vseleq
, _vseleq
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24080 nUF(vselvs
, _vselvs
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24081 nUF(vselge
, _vselge
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24082 nUF(vselgt
, _vselgt
, 3, (RVSD
, RVSD
, RVSD
), vsel
),
24083 nCE(vrintr
, _vrintr
, 2, (RNSDQ
, oRNSDQ
), vrintr
),
24084 mnCE(vrintz
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintz
),
24085 mnCE(vrintx
, _vrintr
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintx
),
24086 mnUF(vrinta
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrinta
),
24087 mnUF(vrintn
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintn
),
24088 mnUF(vrintp
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintp
),
24089 mnUF(vrintm
, _vrinta
, 2, (RNSDQMQ
, oRNSDQMQ
), vrintm
),
24091 /* Crypto v1 extensions. */
24093 #define ARM_VARIANT & fpu_crypto_ext_armv8
24094 #undef THUMB_VARIANT
24095 #define THUMB_VARIANT & fpu_crypto_ext_armv8
24097 nUF(aese
, _aes
, 2, (RNQ
, RNQ
), aese
),
24098 nUF(aesd
, _aes
, 2, (RNQ
, RNQ
), aesd
),
24099 nUF(aesmc
, _aes
, 2, (RNQ
, RNQ
), aesmc
),
24100 nUF(aesimc
, _aes
, 2, (RNQ
, RNQ
), aesimc
),
24101 nUF(sha1c
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1c
),
24102 nUF(sha1p
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1p
),
24103 nUF(sha1m
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1m
),
24104 nUF(sha1su0
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha1su0
),
24105 nUF(sha256h
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h
),
24106 nUF(sha256h2
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256h2
),
24107 nUF(sha256su1
, _sha3op
, 3, (RNQ
, RNQ
, RNQ
), sha256su1
),
24108 nUF(sha1h
, _sha1h
, 2, (RNQ
, RNQ
), sha1h
),
24109 nUF(sha1su1
, _sha2op
, 2, (RNQ
, RNQ
), sha1su1
),
24110 nUF(sha256su0
, _sha2op
, 2, (RNQ
, RNQ
), sha256su0
),
24113 #define ARM_VARIANT & crc_ext_armv8
24114 #undef THUMB_VARIANT
24115 #define THUMB_VARIANT & crc_ext_armv8
24116 TUEc("crc32b", 1000040, fac0f080
, 3, (RR
, oRR
, RR
), crc32b
),
24117 TUEc("crc32h", 1200040, fac0f090
, 3, (RR
, oRR
, RR
), crc32h
),
24118 TUEc("crc32w", 1400040, fac0f0a0
, 3, (RR
, oRR
, RR
), crc32w
),
24119 TUEc("crc32cb",1000240, fad0f080
, 3, (RR
, oRR
, RR
), crc32cb
),
24120 TUEc("crc32ch",1200240, fad0f090
, 3, (RR
, oRR
, RR
), crc32ch
),
24121 TUEc("crc32cw",1400240, fad0f0a0
, 3, (RR
, oRR
, RR
), crc32cw
),
24123 /* ARMv8.2 RAS extension. */
24125 #define ARM_VARIANT & arm_ext_ras
24126 #undef THUMB_VARIANT
24127 #define THUMB_VARIANT & arm_ext_ras
24128 TUE ("esb", 320f010
, f3af8010
, 0, (), noargs
, noargs
),
24131 #define ARM_VARIANT & arm_ext_v8_3
24132 #undef THUMB_VARIANT
24133 #define THUMB_VARIANT & arm_ext_v8_3
24134 NCE (vjcvt
, eb90bc0
, 2, (RVS
, RVD
), vjcvt
),
24137 #define ARM_VARIANT & fpu_neon_ext_dotprod
24138 #undef THUMB_VARIANT
24139 #define THUMB_VARIANT & fpu_neon_ext_dotprod
24140 NUF (vsdot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_s
),
24141 NUF (vudot
, d00
, 3, (RNDQ
, RNDQ
, RNDQ_RNSC
), neon_dotproduct_u
),
24144 #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
24145 #undef THUMB_VARIANT
24146 #define THUMB_VARIANT NULL
24148 cCE("wfs", e200110
, 1, (RR
), rd
),
24149 cCE("rfs", e300110
, 1, (RR
), rd
),
24150 cCE("wfc", e400110
, 1, (RR
), rd
),
24151 cCE("rfc", e500110
, 1, (RR
), rd
),
24153 cCL("ldfs", c100100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24154 cCL("ldfd", c108100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24155 cCL("ldfe", c500100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24156 cCL("ldfp", c508100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24158 cCL("stfs", c000100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24159 cCL("stfd", c008100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24160 cCL("stfe", c400100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24161 cCL("stfp", c408100
, 2, (RF
, ADDRGLDC
), rd_cpaddr
),
24163 cCL("mvfs", e008100
, 2, (RF
, RF_IF
), rd_rm
),
24164 cCL("mvfsp", e008120
, 2, (RF
, RF_IF
), rd_rm
),
24165 cCL("mvfsm", e008140
, 2, (RF
, RF_IF
), rd_rm
),
24166 cCL("mvfsz", e008160
, 2, (RF
, RF_IF
), rd_rm
),
24167 cCL("mvfd", e008180
, 2, (RF
, RF_IF
), rd_rm
),
24168 cCL("mvfdp", e0081a0
, 2, (RF
, RF_IF
), rd_rm
),
24169 cCL("mvfdm", e0081c0
, 2, (RF
, RF_IF
), rd_rm
),
24170 cCL("mvfdz", e0081e0
, 2, (RF
, RF_IF
), rd_rm
),
24171 cCL("mvfe", e088100
, 2, (RF
, RF_IF
), rd_rm
),
24172 cCL("mvfep", e088120
, 2, (RF
, RF_IF
), rd_rm
),
24173 cCL("mvfem", e088140
, 2, (RF
, RF_IF
), rd_rm
),
24174 cCL("mvfez", e088160
, 2, (RF
, RF_IF
), rd_rm
),
24176 cCL("mnfs", e108100
, 2, (RF
, RF_IF
), rd_rm
),
24177 cCL("mnfsp", e108120
, 2, (RF
, RF_IF
), rd_rm
),
24178 cCL("mnfsm", e108140
, 2, (RF
, RF_IF
), rd_rm
),
24179 cCL("mnfsz", e108160
, 2, (RF
, RF_IF
), rd_rm
),
24180 cCL("mnfd", e108180
, 2, (RF
, RF_IF
), rd_rm
),
24181 cCL("mnfdp", e1081a0
, 2, (RF
, RF_IF
), rd_rm
),
24182 cCL("mnfdm", e1081c0
, 2, (RF
, RF_IF
), rd_rm
),
24183 cCL("mnfdz", e1081e0
, 2, (RF
, RF_IF
), rd_rm
),
24184 cCL("mnfe", e188100
, 2, (RF
, RF_IF
), rd_rm
),
24185 cCL("mnfep", e188120
, 2, (RF
, RF_IF
), rd_rm
),
24186 cCL("mnfem", e188140
, 2, (RF
, RF_IF
), rd_rm
),
24187 cCL("mnfez", e188160
, 2, (RF
, RF_IF
), rd_rm
),
24189 cCL("abss", e208100
, 2, (RF
, RF_IF
), rd_rm
),
24190 cCL("abssp", e208120
, 2, (RF
, RF_IF
), rd_rm
),
24191 cCL("abssm", e208140
, 2, (RF
, RF_IF
), rd_rm
),
24192 cCL("abssz", e208160
, 2, (RF
, RF_IF
), rd_rm
),
24193 cCL("absd", e208180
, 2, (RF
, RF_IF
), rd_rm
),
24194 cCL("absdp", e2081a0
, 2, (RF
, RF_IF
), rd_rm
),
24195 cCL("absdm", e2081c0
, 2, (RF
, RF_IF
), rd_rm
),
24196 cCL("absdz", e2081e0
, 2, (RF
, RF_IF
), rd_rm
),
24197 cCL("abse", e288100
, 2, (RF
, RF_IF
), rd_rm
),
24198 cCL("absep", e288120
, 2, (RF
, RF_IF
), rd_rm
),
24199 cCL("absem", e288140
, 2, (RF
, RF_IF
), rd_rm
),
24200 cCL("absez", e288160
, 2, (RF
, RF_IF
), rd_rm
),
24202 cCL("rnds", e308100
, 2, (RF
, RF_IF
), rd_rm
),
24203 cCL("rndsp", e308120
, 2, (RF
, RF_IF
), rd_rm
),
24204 cCL("rndsm", e308140
, 2, (RF
, RF_IF
), rd_rm
),
24205 cCL("rndsz", e308160
, 2, (RF
, RF_IF
), rd_rm
),
24206 cCL("rndd", e308180
, 2, (RF
, RF_IF
), rd_rm
),
24207 cCL("rnddp", e3081a0
, 2, (RF
, RF_IF
), rd_rm
),
24208 cCL("rnddm", e3081c0
, 2, (RF
, RF_IF
), rd_rm
),
24209 cCL("rnddz", e3081e0
, 2, (RF
, RF_IF
), rd_rm
),
24210 cCL("rnde", e388100
, 2, (RF
, RF_IF
), rd_rm
),
24211 cCL("rndep", e388120
, 2, (RF
, RF_IF
), rd_rm
),
24212 cCL("rndem", e388140
, 2, (RF
, RF_IF
), rd_rm
),
24213 cCL("rndez", e388160
, 2, (RF
, RF_IF
), rd_rm
),
24215 cCL("sqts", e408100
, 2, (RF
, RF_IF
), rd_rm
),
24216 cCL("sqtsp", e408120
, 2, (RF
, RF_IF
), rd_rm
),
24217 cCL("sqtsm", e408140
, 2, (RF
, RF_IF
), rd_rm
),
24218 cCL("sqtsz", e408160
, 2, (RF
, RF_IF
), rd_rm
),
24219 cCL("sqtd", e408180
, 2, (RF
, RF_IF
), rd_rm
),
24220 cCL("sqtdp", e4081a0
, 2, (RF
, RF_IF
), rd_rm
),
24221 cCL("sqtdm", e4081c0
, 2, (RF
, RF_IF
), rd_rm
),
24222 cCL("sqtdz", e4081e0
, 2, (RF
, RF_IF
), rd_rm
),
24223 cCL("sqte", e488100
, 2, (RF
, RF_IF
), rd_rm
),
24224 cCL("sqtep", e488120
, 2, (RF
, RF_IF
), rd_rm
),
24225 cCL("sqtem", e488140
, 2, (RF
, RF_IF
), rd_rm
),
24226 cCL("sqtez", e488160
, 2, (RF
, RF_IF
), rd_rm
),
24228 cCL("logs", e508100
, 2, (RF
, RF_IF
), rd_rm
),
24229 cCL("logsp", e508120
, 2, (RF
, RF_IF
), rd_rm
),
24230 cCL("logsm", e508140
, 2, (RF
, RF_IF
), rd_rm
),
24231 cCL("logsz", e508160
, 2, (RF
, RF_IF
), rd_rm
),
24232 cCL("logd", e508180
, 2, (RF
, RF_IF
), rd_rm
),
24233 cCL("logdp", e5081a0
, 2, (RF
, RF_IF
), rd_rm
),
24234 cCL("logdm", e5081c0
, 2, (RF
, RF_IF
), rd_rm
),
24235 cCL("logdz", e5081e0
, 2, (RF
, RF_IF
), rd_rm
),
24236 cCL("loge", e588100
, 2, (RF
, RF_IF
), rd_rm
),
24237 cCL("logep", e588120
, 2, (RF
, RF_IF
), rd_rm
),
24238 cCL("logem", e588140
, 2, (RF
, RF_IF
), rd_rm
),
24239 cCL("logez", e588160
, 2, (RF
, RF_IF
), rd_rm
),
24241 cCL("lgns", e608100
, 2, (RF
, RF_IF
), rd_rm
),
24242 cCL("lgnsp", e608120
, 2, (RF
, RF_IF
), rd_rm
),
24243 cCL("lgnsm", e608140
, 2, (RF
, RF_IF
), rd_rm
),
24244 cCL("lgnsz", e608160
, 2, (RF
, RF_IF
), rd_rm
),
24245 cCL("lgnd", e608180
, 2, (RF
, RF_IF
), rd_rm
),
24246 cCL("lgndp", e6081a0
, 2, (RF
, RF_IF
), rd_rm
),
24247 cCL("lgndm", e6081c0
, 2, (RF
, RF_IF
), rd_rm
),
24248 cCL("lgndz", e6081e0
, 2, (RF
, RF_IF
), rd_rm
),
24249 cCL("lgne", e688100
, 2, (RF
, RF_IF
), rd_rm
),
24250 cCL("lgnep", e688120
, 2, (RF
, RF_IF
), rd_rm
),
24251 cCL("lgnem", e688140
, 2, (RF
, RF_IF
), rd_rm
),
24252 cCL("lgnez", e688160
, 2, (RF
, RF_IF
), rd_rm
),
24254 cCL("exps", e708100
, 2, (RF
, RF_IF
), rd_rm
),
24255 cCL("expsp", e708120
, 2, (RF
, RF_IF
), rd_rm
),
24256 cCL("expsm", e708140
, 2, (RF
, RF_IF
), rd_rm
),
24257 cCL("expsz", e708160
, 2, (RF
, RF_IF
), rd_rm
),
24258 cCL("expd", e708180
, 2, (RF
, RF_IF
), rd_rm
),
24259 cCL("expdp", e7081a0
, 2, (RF
, RF_IF
), rd_rm
),
24260 cCL("expdm", e7081c0
, 2, (RF
, RF_IF
), rd_rm
),
24261 cCL("expdz", e7081e0
, 2, (RF
, RF_IF
), rd_rm
),
24262 cCL("expe", e788100
, 2, (RF
, RF_IF
), rd_rm
),
24263 cCL("expep", e788120
, 2, (RF
, RF_IF
), rd_rm
),
24264 cCL("expem", e788140
, 2, (RF
, RF_IF
), rd_rm
),
24265 cCL("expdz", e788160
, 2, (RF
, RF_IF
), rd_rm
),
24267 cCL("sins", e808100
, 2, (RF
, RF_IF
), rd_rm
),
24268 cCL("sinsp", e808120
, 2, (RF
, RF_IF
), rd_rm
),
24269 cCL("sinsm", e808140
, 2, (RF
, RF_IF
), rd_rm
),
24270 cCL("sinsz", e808160
, 2, (RF
, RF_IF
), rd_rm
),
24271 cCL("sind", e808180
, 2, (RF
, RF_IF
), rd_rm
),
24272 cCL("sindp", e8081a0
, 2, (RF
, RF_IF
), rd_rm
),
24273 cCL("sindm", e8081c0
, 2, (RF
, RF_IF
), rd_rm
),
24274 cCL("sindz", e8081e0
, 2, (RF
, RF_IF
), rd_rm
),
24275 cCL("sine", e888100
, 2, (RF
, RF_IF
), rd_rm
),
24276 cCL("sinep", e888120
, 2, (RF
, RF_IF
), rd_rm
),
24277 cCL("sinem", e888140
, 2, (RF
, RF_IF
), rd_rm
),
24278 cCL("sinez", e888160
, 2, (RF
, RF_IF
), rd_rm
),
24280 cCL("coss", e908100
, 2, (RF
, RF_IF
), rd_rm
),
24281 cCL("cossp", e908120
, 2, (RF
, RF_IF
), rd_rm
),
24282 cCL("cossm", e908140
, 2, (RF
, RF_IF
), rd_rm
),
24283 cCL("cossz", e908160
, 2, (RF
, RF_IF
), rd_rm
),
24284 cCL("cosd", e908180
, 2, (RF
, RF_IF
), rd_rm
),
24285 cCL("cosdp", e9081a0
, 2, (RF
, RF_IF
), rd_rm
),
24286 cCL("cosdm", e9081c0
, 2, (RF
, RF_IF
), rd_rm
),
24287 cCL("cosdz", e9081e0
, 2, (RF
, RF_IF
), rd_rm
),
24288 cCL("cose", e988100
, 2, (RF
, RF_IF
), rd_rm
),
24289 cCL("cosep", e988120
, 2, (RF
, RF_IF
), rd_rm
),
24290 cCL("cosem", e988140
, 2, (RF
, RF_IF
), rd_rm
),
24291 cCL("cosez", e988160
, 2, (RF
, RF_IF
), rd_rm
),
24293 cCL("tans", ea08100
, 2, (RF
, RF_IF
), rd_rm
),
24294 cCL("tansp", ea08120
, 2, (RF
, RF_IF
), rd_rm
),
24295 cCL("tansm", ea08140
, 2, (RF
, RF_IF
), rd_rm
),
24296 cCL("tansz", ea08160
, 2, (RF
, RF_IF
), rd_rm
),
24297 cCL("tand", ea08180
, 2, (RF
, RF_IF
), rd_rm
),
24298 cCL("tandp", ea081a0
, 2, (RF
, RF_IF
), rd_rm
),
24299 cCL("tandm", ea081c0
, 2, (RF
, RF_IF
), rd_rm
),
24300 cCL("tandz", ea081e0
, 2, (RF
, RF_IF
), rd_rm
),
24301 cCL("tane", ea88100
, 2, (RF
, RF_IF
), rd_rm
),
24302 cCL("tanep", ea88120
, 2, (RF
, RF_IF
), rd_rm
),
24303 cCL("tanem", ea88140
, 2, (RF
, RF_IF
), rd_rm
),
24304 cCL("tanez", ea88160
, 2, (RF
, RF_IF
), rd_rm
),
24306 cCL("asns", eb08100
, 2, (RF
, RF_IF
), rd_rm
),
24307 cCL("asnsp", eb08120
, 2, (RF
, RF_IF
), rd_rm
),
24308 cCL("asnsm", eb08140
, 2, (RF
, RF_IF
), rd_rm
),
24309 cCL("asnsz", eb08160
, 2, (RF
, RF_IF
), rd_rm
),
24310 cCL("asnd", eb08180
, 2, (RF
, RF_IF
), rd_rm
),
24311 cCL("asndp", eb081a0
, 2, (RF
, RF_IF
), rd_rm
),
24312 cCL("asndm", eb081c0
, 2, (RF
, RF_IF
), rd_rm
),
24313 cCL("asndz", eb081e0
, 2, (RF
, RF_IF
), rd_rm
),
24314 cCL("asne", eb88100
, 2, (RF
, RF_IF
), rd_rm
),
24315 cCL("asnep", eb88120
, 2, (RF
, RF_IF
), rd_rm
),
24316 cCL("asnem", eb88140
, 2, (RF
, RF_IF
), rd_rm
),
24317 cCL("asnez", eb88160
, 2, (RF
, RF_IF
), rd_rm
),
24319 cCL("acss", ec08100
, 2, (RF
, RF_IF
), rd_rm
),
24320 cCL("acssp", ec08120
, 2, (RF
, RF_IF
), rd_rm
),
24321 cCL("acssm", ec08140
, 2, (RF
, RF_IF
), rd_rm
),
24322 cCL("acssz", ec08160
, 2, (RF
, RF_IF
), rd_rm
),
24323 cCL("acsd", ec08180
, 2, (RF
, RF_IF
), rd_rm
),
24324 cCL("acsdp", ec081a0
, 2, (RF
, RF_IF
), rd_rm
),
24325 cCL("acsdm", ec081c0
, 2, (RF
, RF_IF
), rd_rm
),
24326 cCL("acsdz", ec081e0
, 2, (RF
, RF_IF
), rd_rm
),
24327 cCL("acse", ec88100
, 2, (RF
, RF_IF
), rd_rm
),
24328 cCL("acsep", ec88120
, 2, (RF
, RF_IF
), rd_rm
),
24329 cCL("acsem", ec88140
, 2, (RF
, RF_IF
), rd_rm
),
24330 cCL("acsez", ec88160
, 2, (RF
, RF_IF
), rd_rm
),
24332 cCL("atns", ed08100
, 2, (RF
, RF_IF
), rd_rm
),
24333 cCL("atnsp", ed08120
, 2, (RF
, RF_IF
), rd_rm
),
24334 cCL("atnsm", ed08140
, 2, (RF
, RF_IF
), rd_rm
),
24335 cCL("atnsz", ed08160
, 2, (RF
, RF_IF
), rd_rm
),
24336 cCL("atnd", ed08180
, 2, (RF
, RF_IF
), rd_rm
),
24337 cCL("atndp", ed081a0
, 2, (RF
, RF_IF
), rd_rm
),
24338 cCL("atndm", ed081c0
, 2, (RF
, RF_IF
), rd_rm
),
24339 cCL("atndz", ed081e0
, 2, (RF
, RF_IF
), rd_rm
),
24340 cCL("atne", ed88100
, 2, (RF
, RF_IF
), rd_rm
),
24341 cCL("atnep", ed88120
, 2, (RF
, RF_IF
), rd_rm
),
24342 cCL("atnem", ed88140
, 2, (RF
, RF_IF
), rd_rm
),
24343 cCL("atnez", ed88160
, 2, (RF
, RF_IF
), rd_rm
),
24345 cCL("urds", ee08100
, 2, (RF
, RF_IF
), rd_rm
),
24346 cCL("urdsp", ee08120
, 2, (RF
, RF_IF
), rd_rm
),
24347 cCL("urdsm", ee08140
, 2, (RF
, RF_IF
), rd_rm
),
24348 cCL("urdsz", ee08160
, 2, (RF
, RF_IF
), rd_rm
),
24349 cCL("urdd", ee08180
, 2, (RF
, RF_IF
), rd_rm
),
24350 cCL("urddp", ee081a0
, 2, (RF
, RF_IF
), rd_rm
),
24351 cCL("urddm", ee081c0
, 2, (RF
, RF_IF
), rd_rm
),
24352 cCL("urddz", ee081e0
, 2, (RF
, RF_IF
), rd_rm
),
24353 cCL("urde", ee88100
, 2, (RF
, RF_IF
), rd_rm
),
24354 cCL("urdep", ee88120
, 2, (RF
, RF_IF
), rd_rm
),
24355 cCL("urdem", ee88140
, 2, (RF
, RF_IF
), rd_rm
),
24356 cCL("urdez", ee88160
, 2, (RF
, RF_IF
), rd_rm
),
24358 cCL("nrms", ef08100
, 2, (RF
, RF_IF
), rd_rm
),
24359 cCL("nrmsp", ef08120
, 2, (RF
, RF_IF
), rd_rm
),
24360 cCL("nrmsm", ef08140
, 2, (RF
, RF_IF
), rd_rm
),
24361 cCL("nrmsz", ef08160
, 2, (RF
, RF_IF
), rd_rm
),
24362 cCL("nrmd", ef08180
, 2, (RF
, RF_IF
), rd_rm
),
24363 cCL("nrmdp", ef081a0
, 2, (RF
, RF_IF
), rd_rm
),
24364 cCL("nrmdm", ef081c0
, 2, (RF
, RF_IF
), rd_rm
),
24365 cCL("nrmdz", ef081e0
, 2, (RF
, RF_IF
), rd_rm
),
24366 cCL("nrme", ef88100
, 2, (RF
, RF_IF
), rd_rm
),
24367 cCL("nrmep", ef88120
, 2, (RF
, RF_IF
), rd_rm
),
24368 cCL("nrmem", ef88140
, 2, (RF
, RF_IF
), rd_rm
),
24369 cCL("nrmez", ef88160
, 2, (RF
, RF_IF
), rd_rm
),
24371 cCL("adfs", e000100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24372 cCL("adfsp", e000120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24373 cCL("adfsm", e000140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24374 cCL("adfsz", e000160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24375 cCL("adfd", e000180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24376 cCL("adfdp", e0001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24377 cCL("adfdm", e0001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24378 cCL("adfdz", e0001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24379 cCL("adfe", e080100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24380 cCL("adfep", e080120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24381 cCL("adfem", e080140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24382 cCL("adfez", e080160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24384 cCL("sufs", e200100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24385 cCL("sufsp", e200120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24386 cCL("sufsm", e200140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24387 cCL("sufsz", e200160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24388 cCL("sufd", e200180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24389 cCL("sufdp", e2001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24390 cCL("sufdm", e2001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24391 cCL("sufdz", e2001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24392 cCL("sufe", e280100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24393 cCL("sufep", e280120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24394 cCL("sufem", e280140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24395 cCL("sufez", e280160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24397 cCL("rsfs", e300100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24398 cCL("rsfsp", e300120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24399 cCL("rsfsm", e300140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24400 cCL("rsfsz", e300160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24401 cCL("rsfd", e300180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24402 cCL("rsfdp", e3001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24403 cCL("rsfdm", e3001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24404 cCL("rsfdz", e3001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24405 cCL("rsfe", e380100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24406 cCL("rsfep", e380120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24407 cCL("rsfem", e380140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24408 cCL("rsfez", e380160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24410 cCL("mufs", e100100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24411 cCL("mufsp", e100120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24412 cCL("mufsm", e100140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24413 cCL("mufsz", e100160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24414 cCL("mufd", e100180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24415 cCL("mufdp", e1001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24416 cCL("mufdm", e1001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24417 cCL("mufdz", e1001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24418 cCL("mufe", e180100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24419 cCL("mufep", e180120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24420 cCL("mufem", e180140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24421 cCL("mufez", e180160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24423 cCL("dvfs", e400100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24424 cCL("dvfsp", e400120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24425 cCL("dvfsm", e400140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24426 cCL("dvfsz", e400160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24427 cCL("dvfd", e400180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24428 cCL("dvfdp", e4001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24429 cCL("dvfdm", e4001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24430 cCL("dvfdz", e4001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24431 cCL("dvfe", e480100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24432 cCL("dvfep", e480120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24433 cCL("dvfem", e480140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24434 cCL("dvfez", e480160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24436 cCL("rdfs", e500100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24437 cCL("rdfsp", e500120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24438 cCL("rdfsm", e500140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24439 cCL("rdfsz", e500160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24440 cCL("rdfd", e500180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24441 cCL("rdfdp", e5001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24442 cCL("rdfdm", e5001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24443 cCL("rdfdz", e5001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24444 cCL("rdfe", e580100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24445 cCL("rdfep", e580120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24446 cCL("rdfem", e580140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24447 cCL("rdfez", e580160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24449 cCL("pows", e600100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24450 cCL("powsp", e600120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24451 cCL("powsm", e600140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24452 cCL("powsz", e600160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24453 cCL("powd", e600180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24454 cCL("powdp", e6001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24455 cCL("powdm", e6001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24456 cCL("powdz", e6001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24457 cCL("powe", e680100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24458 cCL("powep", e680120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24459 cCL("powem", e680140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24460 cCL("powez", e680160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24462 cCL("rpws", e700100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24463 cCL("rpwsp", e700120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24464 cCL("rpwsm", e700140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24465 cCL("rpwsz", e700160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24466 cCL("rpwd", e700180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24467 cCL("rpwdp", e7001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24468 cCL("rpwdm", e7001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24469 cCL("rpwdz", e7001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24470 cCL("rpwe", e780100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24471 cCL("rpwep", e780120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24472 cCL("rpwem", e780140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24473 cCL("rpwez", e780160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24475 cCL("rmfs", e800100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24476 cCL("rmfsp", e800120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24477 cCL("rmfsm", e800140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24478 cCL("rmfsz", e800160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24479 cCL("rmfd", e800180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24480 cCL("rmfdp", e8001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24481 cCL("rmfdm", e8001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24482 cCL("rmfdz", e8001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24483 cCL("rmfe", e880100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24484 cCL("rmfep", e880120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24485 cCL("rmfem", e880140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24486 cCL("rmfez", e880160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24488 cCL("fmls", e900100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24489 cCL("fmlsp", e900120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24490 cCL("fmlsm", e900140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24491 cCL("fmlsz", e900160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24492 cCL("fmld", e900180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24493 cCL("fmldp", e9001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24494 cCL("fmldm", e9001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24495 cCL("fmldz", e9001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24496 cCL("fmle", e980100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24497 cCL("fmlep", e980120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24498 cCL("fmlem", e980140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24499 cCL("fmlez", e980160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24501 cCL("fdvs", ea00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24502 cCL("fdvsp", ea00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24503 cCL("fdvsm", ea00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24504 cCL("fdvsz", ea00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24505 cCL("fdvd", ea00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24506 cCL("fdvdp", ea001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24507 cCL("fdvdm", ea001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24508 cCL("fdvdz", ea001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24509 cCL("fdve", ea80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24510 cCL("fdvep", ea80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24511 cCL("fdvem", ea80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24512 cCL("fdvez", ea80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24514 cCL("frds", eb00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24515 cCL("frdsp", eb00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24516 cCL("frdsm", eb00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24517 cCL("frdsz", eb00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24518 cCL("frdd", eb00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24519 cCL("frddp", eb001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24520 cCL("frddm", eb001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24521 cCL("frddz", eb001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24522 cCL("frde", eb80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24523 cCL("frdep", eb80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24524 cCL("frdem", eb80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24525 cCL("frdez", eb80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24527 cCL("pols", ec00100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24528 cCL("polsp", ec00120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24529 cCL("polsm", ec00140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24530 cCL("polsz", ec00160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24531 cCL("pold", ec00180
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24532 cCL("poldp", ec001a0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24533 cCL("poldm", ec001c0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24534 cCL("poldz", ec001e0
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24535 cCL("pole", ec80100
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24536 cCL("polep", ec80120
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24537 cCL("polem", ec80140
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24538 cCL("polez", ec80160
, 3, (RF
, RF
, RF_IF
), rd_rn_rm
),
24540 cCE("cmf", e90f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24541 C3E("cmfe", ed0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24542 cCE("cnf", eb0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24543 C3E("cnfe", ef0f110
, 2, (RF
, RF_IF
), fpa_cmp
),
24545 cCL("flts", e000110
, 2, (RF
, RR
), rn_rd
),
24546 cCL("fltsp", e000130
, 2, (RF
, RR
), rn_rd
),
24547 cCL("fltsm", e000150
, 2, (RF
, RR
), rn_rd
),
24548 cCL("fltsz", e000170
, 2, (RF
, RR
), rn_rd
),
24549 cCL("fltd", e000190
, 2, (RF
, RR
), rn_rd
),
24550 cCL("fltdp", e0001b0
, 2, (RF
, RR
), rn_rd
),
24551 cCL("fltdm", e0001d0
, 2, (RF
, RR
), rn_rd
),
24552 cCL("fltdz", e0001f0
, 2, (RF
, RR
), rn_rd
),
24553 cCL("flte", e080110
, 2, (RF
, RR
), rn_rd
),
24554 cCL("fltep", e080130
, 2, (RF
, RR
), rn_rd
),
24555 cCL("fltem", e080150
, 2, (RF
, RR
), rn_rd
),
24556 cCL("fltez", e080170
, 2, (RF
, RR
), rn_rd
),
24558 /* The implementation of the FIX instruction is broken on some
24559 assemblers, in that it accepts a precision specifier as well as a
24560 rounding specifier, despite the fact that this is meaningless.
24561 To be more compatible, we accept it as well, though of course it
24562 does not set any bits. */
24563 cCE("fix", e100110
, 2, (RR
, RF
), rd_rm
),
24564 cCL("fixp", e100130
, 2, (RR
, RF
), rd_rm
),
24565 cCL("fixm", e100150
, 2, (RR
, RF
), rd_rm
),
24566 cCL("fixz", e100170
, 2, (RR
, RF
), rd_rm
),
24567 cCL("fixsp", e100130
, 2, (RR
, RF
), rd_rm
),
24568 cCL("fixsm", e100150
, 2, (RR
, RF
), rd_rm
),
24569 cCL("fixsz", e100170
, 2, (RR
, RF
), rd_rm
),
24570 cCL("fixdp", e100130
, 2, (RR
, RF
), rd_rm
),
24571 cCL("fixdm", e100150
, 2, (RR
, RF
), rd_rm
),
24572 cCL("fixdz", e100170
, 2, (RR
, RF
), rd_rm
),
24573 cCL("fixep", e100130
, 2, (RR
, RF
), rd_rm
),
24574 cCL("fixem", e100150
, 2, (RR
, RF
), rd_rm
),
24575 cCL("fixez", e100170
, 2, (RR
, RF
), rd_rm
),
24577 /* Instructions that were new with the real FPA, call them V2. */
24579 #define ARM_VARIANT & fpu_fpa_ext_v2
24581 cCE("lfm", c100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24582 cCL("lfmfd", c900200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24583 cCL("lfmea", d100200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24584 cCE("sfm", c000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24585 cCL("sfmfd", d000200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24586 cCL("sfmea", c800200
, 3, (RF
, I4b
, ADDR
), fpa_ldmstm
),
24589 #define ARM_VARIANT & fpu_vfp_ext_v1xd /* VFP V1xD (single precision). */
24590 #undef THUMB_VARIANT
24591 #define THUMB_VARIANT & arm_ext_v6t2
24592 mcCE(vmrs
, ef00a10
, 2, (APSR_RR
, RVC
), vmrs
),
24593 mcCE(vmsr
, ee00a10
, 2, (RVC
, RR
), vmsr
),
24594 #undef THUMB_VARIANT
24596 /* Moves and type conversions. */
24597 cCE("fmstat", ef1fa10
, 0, (), noargs
),
24598 cCE("fsitos", eb80ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24599 cCE("fuitos", eb80a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24600 cCE("ftosis", ebd0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24601 cCE("ftosizs", ebd0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24602 cCE("ftouis", ebc0a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24603 cCE("ftouizs", ebc0ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24604 cCE("fmrx", ef00a10
, 2, (RR
, RVC
), rd_rn
),
24605 cCE("fmxr", ee00a10
, 2, (RVC
, RR
), rn_rd
),
24607 /* Memory operations. */
24608 cCE("flds", d100a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24609 cCE("fsts", d000a00
, 2, (RVS
, ADDRGLDC
), vfp_sp_ldst
),
24610 cCE("fldmias", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24611 cCE("fldmfds", c900a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24612 cCE("fldmdbs", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24613 cCE("fldmeas", d300a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24614 cCE("fldmiax", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24615 cCE("fldmfdx", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24616 cCE("fldmdbx", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24617 cCE("fldmeax", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24618 cCE("fstmias", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24619 cCE("fstmeas", c800a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmia
),
24620 cCE("fstmdbs", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24621 cCE("fstmfds", d200a00
, 2, (RRnpctw
, VRSLST
), vfp_sp_ldstmdb
),
24622 cCE("fstmiax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24623 cCE("fstmeax", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmia
),
24624 cCE("fstmdbx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24625 cCE("fstmfdx", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_xp_ldstmdb
),
24627 /* Monadic operations. */
24628 cCE("fabss", eb00ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24629 cCE("fnegs", eb10a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24630 cCE("fsqrts", eb10ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24632 /* Dyadic operations. */
24633 cCE("fadds", e300a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24634 cCE("fsubs", e300a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24635 cCE("fmuls", e200a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24636 cCE("fdivs", e800a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24637 cCE("fmacs", e000a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24638 cCE("fmscs", e100a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24639 cCE("fnmuls", e200a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24640 cCE("fnmacs", e000a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24641 cCE("fnmscs", e100a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
24644 cCE("fcmps", eb40a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24645 cCE("fcmpzs", eb50a40
, 1, (RVS
), vfp_sp_compare_z
),
24646 cCE("fcmpes", eb40ac0
, 2, (RVS
, RVS
), vfp_sp_monadic
),
24647 cCE("fcmpezs", eb50ac0
, 1, (RVS
), vfp_sp_compare_z
),
24649 /* Double precision load/store are still present on single precision
24650 implementations. */
24651 cCE("fldd", d100b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24652 cCE("fstd", d000b00
, 2, (RVD
, ADDRGLDC
), vfp_dp_ldst
),
24653 cCE("fldmiad", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24654 cCE("fldmfdd", c900b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24655 cCE("fldmdbd", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24656 cCE("fldmead", d300b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24657 cCE("fstmiad", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24658 cCE("fstmead", c800b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmia
),
24659 cCE("fstmdbd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24660 cCE("fstmfdd", d200b00
, 2, (RRnpctw
, VRDLST
), vfp_dp_ldstmdb
),
24663 #define ARM_VARIANT & fpu_vfp_ext_v1 /* VFP V1 (Double precision). */
24665 /* Moves and type conversions. */
24666 cCE("fcvtds", eb70ac0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24667 cCE("fcvtsd", eb70bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24668 cCE("fmdhr", e200b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24669 cCE("fmdlr", e000b10
, 2, (RVD
, RR
), vfp_dp_rn_rd
),
24670 cCE("fmrdh", e300b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24671 cCE("fmrdl", e100b10
, 2, (RR
, RVD
), vfp_dp_rd_rn
),
24672 cCE("fsitod", eb80bc0
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24673 cCE("fuitod", eb80b40
, 2, (RVD
, RVS
), vfp_dp_sp_cvt
),
24674 cCE("ftosid", ebd0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24675 cCE("ftosizd", ebd0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24676 cCE("ftouid", ebc0b40
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24677 cCE("ftouizd", ebc0bc0
, 2, (RVS
, RVD
), vfp_sp_dp_cvt
),
24679 /* Monadic operations. */
24680 cCE("fabsd", eb00bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24681 cCE("fnegd", eb10b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24682 cCE("fsqrtd", eb10bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24684 /* Dyadic operations. */
24685 cCE("faddd", e300b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24686 cCE("fsubd", e300b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24687 cCE("fmuld", e200b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24688 cCE("fdivd", e800b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24689 cCE("fmacd", e000b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24690 cCE("fmscd", e100b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24691 cCE("fnmuld", e200b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24692 cCE("fnmacd", e000b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24693 cCE("fnmscd", e100b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
24696 cCE("fcmpd", eb40b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24697 cCE("fcmpzd", eb50b40
, 1, (RVD
), vfp_dp_rd
),
24698 cCE("fcmped", eb40bc0
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
24699 cCE("fcmpezd", eb50bc0
, 1, (RVD
), vfp_dp_rd
),
24701 /* Instructions which may belong to either the Neon or VFP instruction sets.
24702 Individual encoder functions perform additional architecture checks. */
24704 #define ARM_VARIANT & fpu_vfp_ext_v1xd
24705 #undef THUMB_VARIANT
24706 #define THUMB_VARIANT & fpu_vfp_ext_v1xd
24708 /* These mnemonics are unique to VFP. */
24709 NCE(vsqrt
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_sqrt
),
24710 NCE(vdiv
, 0, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_div
),
24711 nCE(vnmul
, _vnmul
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24712 nCE(vnmla
, _vnmla
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24713 nCE(vnmls
, _vnmls
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
24714 NCE(vpush
, 0, 1, (VRSDLST
), vfp_nsyn_push
),
24715 NCE(vpop
, 0, 1, (VRSDLST
), vfp_nsyn_pop
),
24716 NCE(vcvtz
, 0, 2, (RVSD
, RVSD
), vfp_nsyn_cvtz
),
24718 /* Mnemonics shared by Neon and VFP. */
24719 nCEF(vmls
, _vmls
, 3, (RNSDQ
, oRNSDQ
, RNSDQ_RNSC
), neon_mac_maybe_scalar
),
24721 NCE(vldm
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24722 NCE(vldmia
, c900b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24723 NCE(vldmdb
, d100b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24724 NCE(vstm
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24725 NCE(vstmia
, c800b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24726 NCE(vstmdb
, d000b00
, 2, (RRnpctw
, VRSDLST
), neon_ldm_stm
),
24728 mnCEF(vcvt
, _vcvt
, 3, (RNSDQMQ
, RNSDQMQ
, oI32z
), neon_cvt
),
24729 nCEF(vcvtr
, _vcvt
, 2, (RNSDQ
, RNSDQ
), neon_cvtr
),
24730 MNCEF(vcvtb
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtb
),
24731 MNCEF(vcvtt
, eb20a40
, 3, (RVSDMQ
, RVSDMQ
, oI32b
), neon_cvtt
),
24734 /* NOTE: All VMOV encoding is special-cased! */
24735 NCE(vmovq
, 0, 1, (VMOV
), neon_mov
),
24737 #undef THUMB_VARIANT
24738 /* Could be either VLDR/VSTR or VLDR/VSTR (system register) which are guarded
24739 by different feature bits. Since we are setting the Thumb guard, we can
24740 require Thumb-1 which makes it a nop guard and set the right feature bit in
24741 do_vldr_vstr (). */
24742 #define THUMB_VARIANT & arm_ext_v4t
24743 NCE(vldr
, d100b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24744 NCE(vstr
, d000b00
, 2, (VLDR
, ADDRGLDC
), vldr_vstr
),
24747 #define ARM_VARIANT & arm_ext_fp16
24748 #undef THUMB_VARIANT
24749 #define THUMB_VARIANT & arm_ext_fp16
24750 /* New instructions added from v8.2, allowing the extraction and insertion of
24751 the upper 16 bits of a 32-bit vector register. */
24752 NCE (vmovx
, eb00a40
, 2, (RVS
, RVS
), neon_movhf
),
24753 NCE (vins
, eb00ac0
, 2, (RVS
, RVS
), neon_movhf
),
24755 /* New backported fma/fms instructions optional in v8.2. */
24756 NCE (vfmal
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmal
),
24757 NCE (vfmsl
, 810, 3, (RNDQ
, RNSD
, RNSD_RNSC
), neon_vfmsl
),
24759 #undef THUMB_VARIANT
24760 #define THUMB_VARIANT & fpu_neon_ext_v1
24762 #define ARM_VARIANT & fpu_neon_ext_v1
24764 /* Data processing with three registers of the same length. */
24765 /* integer ops, valid types S8 S16 S32 U8 U16 U32. */
24766 NUF(vaba
, 0000710, 3, (RNDQ
, RNDQ
, RNDQ
), neon_dyadic_i_su
),
24767 NUF(vabaq
, 0000710, 3, (RNQ
, RNQ
, RNQ
), neon_dyadic_i_su
),
24768 NUF(vhaddq
, 0000000, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24769 NUF(vrhaddq
, 0000100, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24770 NUF(vhsubq
, 0000200, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i_su
),
24771 /* integer ops, valid types S8 S16 S32 S64 U8 U16 U32 U64. */
24772 NUF(vqaddq
, 0000010, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24773 NUF(vqsubq
, 0000210, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_i64_su
),
24774 NUF(vrshlq
, 0000500, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24775 NUF(vqrshlq
, 0000510, 3, (RNQ
, oRNQ
, RNQ
), neon_rshl
),
24776 /* If not immediate, fall back to neon_dyadic_i64_su.
24777 shl should accept I8 I16 I32 I64,
24778 qshl should accept S8 S16 S32 S64 U8 U16 U32 U64. */
24779 nUF(vshlq
, _vshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_shl
),
24780 nUF(vqshlq
, _vqshl
, 3, (RNQ
, oRNQ
, RNDQ_I63b
), neon_qshl
),
24781 /* Logic ops, types optional & ignored. */
24782 nUF(vandq
, _vand
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24783 nUF(vbicq
, _vbic
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24784 nUF(vorrq
, _vorr
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24785 nUF(vornq
, _vorn
, 3, (RNQ
, oRNQ
, RNDQ_Ibig
), neon_logic
),
24786 nUF(veorq
, _veor
, 3, (RNQ
, oRNQ
, RNQ
), neon_logic
),
24787 /* Bitfield ops, untyped. */
24788 NUF(vbsl
, 1100110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24789 NUF(vbslq
, 1100110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24790 NUF(vbit
, 1200110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24791 NUF(vbitq
, 1200110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24792 NUF(vbif
, 1300110, 3, (RNDQ
, RNDQ
, RNDQ
), neon_bitfield
),
24793 NUF(vbifq
, 1300110, 3, (RNQ
, RNQ
, RNQ
), neon_bitfield
),
24794 /* Int and float variants, types S8 S16 S32 U8 U16 U32 F16 F32. */
24795 nUF(vabdq
, _vabd
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24796 nUF(vmaxq
, _vmax
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24797 nUF(vminq
, _vmin
, 3, (RNQ
, oRNQ
, RNQ
), neon_dyadic_if_su
),
24798 /* Comparisons. Types S8 S16 S32 U8 U16 U32 F32. Non-immediate versions fall
24799 back to neon_dyadic_if_su. */
24800 nUF(vcge
, _vcge
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24801 nUF(vcgeq
, _vcge
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24802 nUF(vcgt
, _vcgt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp
),
24803 nUF(vcgtq
, _vcgt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp
),
24804 nUF(vclt
, _vclt
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24805 nUF(vcltq
, _vclt
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24806 nUF(vcle
, _vcle
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_cmp_inv
),
24807 nUF(vcleq
, _vcle
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_cmp_inv
),
24808 /* Comparison. Type I8 I16 I32 F32. */
24809 nUF(vceq
, _vceq
, 3, (RNDQ
, oRNDQ
, RNDQ_I0
), neon_ceq
),
24810 nUF(vceqq
, _vceq
, 3, (RNQ
, oRNQ
, RNDQ_I0
), neon_ceq
),
24811 /* As above, D registers only. */
24812 nUF(vpmax
, _vpmax
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24813 nUF(vpmin
, _vpmin
, 3, (RND
, oRND
, RND
), neon_dyadic_if_su_d
),
24814 /* Int and float variants, signedness unimportant. */
24815 nUF(vmlaq
, _vmla
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24816 nUF(vmlsq
, _vmls
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mac_maybe_scalar
),
24817 nUF(vpadd
, _vpadd
, 3, (RND
, oRND
, RND
), neon_dyadic_if_i_d
),
24818 /* Add/sub take types I8 I16 I32 I64 F32. */
24819 nUF(vaddq
, _vadd
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24820 nUF(vsubq
, _vsub
, 3, (RNQ
, oRNQ
, RNQ
), neon_addsub_if_i
),
24821 /* vtst takes sizes 8, 16, 32. */
24822 NUF(vtst
, 0000810, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_tst
),
24823 NUF(vtstq
, 0000810, 3, (RNQ
, oRNQ
, RNQ
), neon_tst
),
24824 /* VMUL takes I8 I16 I32 F32 P8. */
24825 nUF(vmulq
, _vmul
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_mul
),
24826 /* VQD{R}MULH takes S16 S32. */
24827 nUF(vqdmulhq
, _vqdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24828 nUF(vqrdmulhq
, _vqrdmulh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qdmulh
),
24829 NUF(vacge
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24830 NUF(vacgeq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24831 NUF(vacgt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute
),
24832 NUF(vacgtq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute
),
24833 NUF(vaclt
, 0200e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24834 NUF(vacltq
, 0200e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24835 NUF(vacle
, 0000e10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_fcmp_absolute_inv
),
24836 NUF(vacleq
, 0000e10
, 3, (RNQ
, oRNQ
, RNQ
), neon_fcmp_absolute_inv
),
24837 NUF(vrecps
, 0000f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24838 NUF(vrecpsq
, 0000f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24839 NUF(vrsqrts
, 0200f10
, 3, (RNDQ
, oRNDQ
, RNDQ
), neon_step
),
24840 NUF(vrsqrtsq
, 0200f10
, 3, (RNQ
, oRNQ
, RNQ
), neon_step
),
24841 /* ARM v8.1 extension. */
24842 nUF (vqrdmlahq
, _vqrdmlah
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24843 nUF (vqrdmlsh
, _vqrdmlsh
, 3, (RNDQ
, oRNDQ
, RNDQ_RNSC
), neon_qrdmlah
),
24844 nUF (vqrdmlshq
, _vqrdmlsh
, 3, (RNQ
, oRNQ
, RNDQ_RNSC
), neon_qrdmlah
),
24846 /* Two address, int/float. Types S8 S16 S32 F32. */
24847 NUF(vabsq
, 1b10300
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24848 NUF(vnegq
, 1b10380
, 2, (RNQ
, RNQ
), neon_abs_neg
),
24850 /* Data processing with two registers and a shift amount. */
24851 /* Right shifts, and variants with rounding.
24852 Types accepted S8 S16 S32 S64 U8 U16 U32 U64. */
24853 NUF(vshrq
, 0800010, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24854 NUF(vrshrq
, 0800210, 3, (RNQ
, oRNQ
, I64z
), neon_rshift_round_imm
),
24855 NUF(vsra
, 0800110, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24856 NUF(vsraq
, 0800110, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24857 NUF(vrsra
, 0800310, 3, (RNDQ
, oRNDQ
, I64
), neon_rshift_round_imm
),
24858 NUF(vrsraq
, 0800310, 3, (RNQ
, oRNQ
, I64
), neon_rshift_round_imm
),
24859 /* Shift and insert. Sizes accepted 8 16 32 64. */
24860 NUF(vsliq
, 1800510, 3, (RNQ
, oRNQ
, I63
), neon_sli
),
24861 NUF(vsriq
, 1800410, 3, (RNQ
, oRNQ
, I64
), neon_sri
),
24862 /* QSHL{U} immediate accepts S8 S16 S32 S64 U8 U16 U32 U64. */
24863 NUF(vqshluq
, 1800610, 3, (RNQ
, oRNQ
, I63
), neon_qshlu_imm
),
24864 /* Right shift immediate, saturating & narrowing, with rounding variants.
24865 Types accepted S16 S32 S64 U16 U32 U64. */
24866 NUF(vqshrn
, 0800910, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24867 NUF(vqrshrn
, 0800950, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow
),
24868 /* As above, unsigned. Types accepted S16 S32 S64. */
24869 NUF(vqshrun
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24870 NUF(vqrshrun
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_sat_narrow_u
),
24871 /* Right shift narrowing. Types accepted I16 I32 I64. */
24872 NUF(vshrn
, 0800810, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24873 NUF(vrshrn
, 0800850, 3, (RND
, RNQ
, I32z
), neon_rshift_narrow
),
24874 /* Special case. Types S8 S16 S32 U8 U16 U32. Handles max shift variant. */
24875 nUF(vshll
, _vshll
, 3, (RNQ
, RND
, I32
), neon_shll
),
24876 /* CVT with optional immediate for fixed-point variant. */
24877 nUF(vcvtq
, _vcvt
, 3, (RNQ
, RNQ
, oI32b
), neon_cvt
),
24879 nUF(vmvnq
, _vmvn
, 2, (RNQ
, RNDQ_Ibig
), neon_mvn
),
24881 /* Data processing, three registers of different lengths. */
24882 /* Dyadic, long insns. Types S8 S16 S32 U8 U16 U32. */
24883 NUF(vabal
, 0800500, 3, (RNQ
, RND
, RND
), neon_abal
),
24884 /* If not scalar, fall back to neon_dyadic_long.
24885 Vector types as above, scalar types S16 S32 U16 U32. */
24886 nUF(vmlal
, _vmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24887 nUF(vmlsl
, _vmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mac_maybe_scalar_long
),
24888 /* Dyadic, widening insns. Types S8 S16 S32 U8 U16 U32. */
24889 NUF(vaddw
, 0800100, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24890 NUF(vsubw
, 0800300, 3, (RNQ
, oRNQ
, RND
), neon_dyadic_wide
),
24891 /* Dyadic, narrowing insns. Types I16 I32 I64. */
24892 NUF(vaddhn
, 0800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24893 NUF(vraddhn
, 1800400, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24894 NUF(vsubhn
, 0800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24895 NUF(vrsubhn
, 1800600, 3, (RND
, RNQ
, RNQ
), neon_dyadic_narrow
),
24896 /* Saturating doubling multiplies. Types S16 S32. */
24897 nUF(vqdmlal
, _vqdmlal
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24898 nUF(vqdmlsl
, _vqdmlsl
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24899 nUF(vqdmull
, _vqdmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_mul_sat_scalar_long
),
24900 /* VMULL. Vector types S8 S16 S32 U8 U16 U32 P8, scalar types
24901 S16 S32 U16 U32. */
24902 nUF(vmull
, _vmull
, 3, (RNQ
, RND
, RND_RNSC
), neon_vmull
),
24904 /* Extract. Size 8. */
24905 NUF(vext
, 0b00000, 4, (RNDQ
, oRNDQ
, RNDQ
, I15
), neon_ext
),
24906 NUF(vextq
, 0b00000, 4, (RNQ
, oRNQ
, RNQ
, I15
), neon_ext
),
24908 /* Two registers, miscellaneous. */
24909 /* Reverse. Sizes 8 16 32 (must be < size in opcode). */
24910 NUF(vrev64q
, 1b00000
, 2, (RNQ
, RNQ
), neon_rev
),
24911 NUF(vrev32q
, 1b00080
, 2, (RNQ
, RNQ
), neon_rev
),
24912 NUF(vrev16q
, 1b00100
, 2, (RNQ
, RNQ
), neon_rev
),
24913 /* Vector replicate. Sizes 8 16 32. */
24914 nCE(vdupq
, _vdup
, 2, (RNQ
, RR_RNSC
), neon_dup
),
24915 /* VMOVL. Types S8 S16 S32 U8 U16 U32. */
24916 NUF(vmovl
, 0800a10
, 2, (RNQ
, RND
), neon_movl
),
24917 /* VMOVN. Types I16 I32 I64. */
24918 nUF(vmovn
, _vmovn
, 2, (RND
, RNQ
), neon_movn
),
24919 /* VQMOVN. Types S16 S32 S64 U16 U32 U64. */
24920 nUF(vqmovn
, _vqmovn
, 2, (RND
, RNQ
), neon_qmovn
),
24921 /* VQMOVUN. Types S16 S32 S64. */
24922 nUF(vqmovun
, _vqmovun
, 2, (RND
, RNQ
), neon_qmovun
),
24923 /* VZIP / VUZP. Sizes 8 16 32. */
24924 NUF(vzip
, 1b20180
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24925 NUF(vzipq
, 1b20180
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24926 NUF(vuzp
, 1b20100
, 2, (RNDQ
, RNDQ
), neon_zip_uzp
),
24927 NUF(vuzpq
, 1b20100
, 2, (RNQ
, RNQ
), neon_zip_uzp
),
24928 /* VQABS / VQNEG. Types S8 S16 S32. */
24929 NUF(vqabsq
, 1b00700
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24930 NUF(vqnegq
, 1b00780
, 2, (RNQ
, RNQ
), neon_sat_abs_neg
),
24931 /* Pairwise, lengthening. Types S8 S16 S32 U8 U16 U32. */
24932 NUF(vpadal
, 1b00600
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24933 NUF(vpadalq
, 1b00600
, 2, (RNQ
, RNQ
), neon_pair_long
),
24934 NUF(vpaddl
, 1b00200
, 2, (RNDQ
, RNDQ
), neon_pair_long
),
24935 NUF(vpaddlq
, 1b00200
, 2, (RNQ
, RNQ
), neon_pair_long
),
24936 /* Reciprocal estimates. Types U32 F16 F32. */
24937 NUF(vrecpe
, 1b30400
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24938 NUF(vrecpeq
, 1b30400
, 2, (RNQ
, RNQ
), neon_recip_est
),
24939 NUF(vrsqrte
, 1b30480
, 2, (RNDQ
, RNDQ
), neon_recip_est
),
24940 NUF(vrsqrteq
, 1b30480
, 2, (RNQ
, RNQ
), neon_recip_est
),
24941 /* VCLS. Types S8 S16 S32. */
24942 NUF(vclsq
, 1b00400
, 2, (RNQ
, RNQ
), neon_cls
),
24943 /* VCLZ. Types I8 I16 I32. */
24944 NUF(vclzq
, 1b00480
, 2, (RNQ
, RNQ
), neon_clz
),
24945 /* VCNT. Size 8. */
24946 NUF(vcnt
, 1b00500
, 2, (RNDQ
, RNDQ
), neon_cnt
),
24947 NUF(vcntq
, 1b00500
, 2, (RNQ
, RNQ
), neon_cnt
),
24948 /* Two address, untyped. */
24949 NUF(vswp
, 1b20000
, 2, (RNDQ
, RNDQ
), neon_swp
),
24950 NUF(vswpq
, 1b20000
, 2, (RNQ
, RNQ
), neon_swp
),
24951 /* VTRN. Sizes 8 16 32. */
24952 nUF(vtrn
, _vtrn
, 2, (RNDQ
, RNDQ
), neon_trn
),
24953 nUF(vtrnq
, _vtrn
, 2, (RNQ
, RNQ
), neon_trn
),
24955 /* Table lookup. Size 8. */
24956 NUF(vtbl
, 1b00800
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24957 NUF(vtbx
, 1b00840
, 3, (RND
, NRDLST
, RND
), neon_tbl_tbx
),
24959 #undef THUMB_VARIANT
24960 #define THUMB_VARIANT & fpu_vfp_v3_or_neon_ext
24962 #define ARM_VARIANT & fpu_vfp_v3_or_neon_ext
24964 /* Neon element/structure load/store. */
24965 nUF(vld1
, _vld1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24966 nUF(vst1
, _vst1
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24967 nUF(vld2
, _vld2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24968 nUF(vst2
, _vst2
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24969 nUF(vld3
, _vld3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24970 nUF(vst3
, _vst3
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24971 nUF(vld4
, _vld4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24972 nUF(vst4
, _vst4
, 2, (NSTRLST
, ADDR
), neon_ldx_stx
),
24974 #undef THUMB_VARIANT
24975 #define THUMB_VARIANT & fpu_vfp_ext_v3xd
24977 #define ARM_VARIANT & fpu_vfp_ext_v3xd
24978 cCE("fconsts", eb00a00
, 2, (RVS
, I255
), vfp_sp_const
),
24979 cCE("fshtos", eba0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24980 cCE("fsltos", eba0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24981 cCE("fuhtos", ebb0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24982 cCE("fultos", ebb0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24983 cCE("ftoshs", ebe0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24984 cCE("ftosls", ebe0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24985 cCE("ftouhs", ebf0a40
, 2, (RVS
, I16z
), vfp_sp_conv_16
),
24986 cCE("ftouls", ebf0ac0
, 2, (RVS
, I32
), vfp_sp_conv_32
),
24988 #undef THUMB_VARIANT
24989 #define THUMB_VARIANT & fpu_vfp_ext_v3
24991 #define ARM_VARIANT & fpu_vfp_ext_v3
24993 cCE("fconstd", eb00b00
, 2, (RVD
, I255
), vfp_dp_const
),
24994 cCE("fshtod", eba0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24995 cCE("fsltod", eba0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24996 cCE("fuhtod", ebb0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24997 cCE("fultod", ebb0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
24998 cCE("ftoshd", ebe0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
24999 cCE("ftosld", ebe0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25000 cCE("ftouhd", ebf0b40
, 2, (RVD
, I16z
), vfp_dp_conv_16
),
25001 cCE("ftould", ebf0bc0
, 2, (RVD
, I32
), vfp_dp_conv_32
),
25004 #define ARM_VARIANT & fpu_vfp_ext_fma
25005 #undef THUMB_VARIANT
25006 #define THUMB_VARIANT & fpu_vfp_ext_fma
25007 /* Mnemonics shared by Neon, VFP and MVE. These are included in the
25008 VFP FMA variant; NEON and VFP FMA always includes the NEON
25009 FMA instructions. */
25010 mnCEF(vfma
, _vfma
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_fmac
),
25011 mnCEF(vfms
, _vfms
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), neon_fmac
),
25013 /* ffmas/ffmad/ffmss/ffmsd are dummy mnemonics to satisfy gas;
25014 the v form should always be used. */
25015 cCE("ffmas", ea00a00
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25016 cCE("ffnmas", ea00a40
, 3, (RVS
, RVS
, RVS
), vfp_sp_dyadic
),
25017 cCE("ffmad", ea00b00
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25018 cCE("ffnmad", ea00b40
, 3, (RVD
, RVD
, RVD
), vfp_dp_rd_rn_rm
),
25019 nCE(vfnma
, _vfnma
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25020 nCE(vfnms
, _vfnms
, 3, (RVSD
, RVSD
, RVSD
), vfp_nsyn_nmul
),
25022 #undef THUMB_VARIANT
25024 #define ARM_VARIANT & arm_cext_xscale /* Intel XScale extensions. */
25026 cCE("mia", e200010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25027 cCE("miaph", e280010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25028 cCE("miabb", e2c0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25029 cCE("miabt", e2d0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25030 cCE("miatb", e2e0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25031 cCE("miatt", e2f0010
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mia
),
25032 cCE("mar", c400000
, 3, (RXA
, RRnpc
, RRnpc
), xsc_mar
),
25033 cCE("mra", c500000
, 3, (RRnpc
, RRnpc
, RXA
), xsc_mra
),
25036 #define ARM_VARIANT & arm_cext_iwmmxt /* Intel Wireless MMX technology. */
25038 cCE("tandcb", e13f130
, 1, (RR
), iwmmxt_tandorc
),
25039 cCE("tandch", e53f130
, 1, (RR
), iwmmxt_tandorc
),
25040 cCE("tandcw", e93f130
, 1, (RR
), iwmmxt_tandorc
),
25041 cCE("tbcstb", e400010
, 2, (RIWR
, RR
), rn_rd
),
25042 cCE("tbcsth", e400050
, 2, (RIWR
, RR
), rn_rd
),
25043 cCE("tbcstw", e400090
, 2, (RIWR
, RR
), rn_rd
),
25044 cCE("textrcb", e130170
, 2, (RR
, I7
), iwmmxt_textrc
),
25045 cCE("textrch", e530170
, 2, (RR
, I7
), iwmmxt_textrc
),
25046 cCE("textrcw", e930170
, 2, (RR
, I7
), iwmmxt_textrc
),
25047 cCE("textrmub",e100070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25048 cCE("textrmuh",e500070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25049 cCE("textrmuw",e900070
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25050 cCE("textrmsb",e100078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25051 cCE("textrmsh",e500078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25052 cCE("textrmsw",e900078
, 3, (RR
, RIWR
, I7
), iwmmxt_textrm
),
25053 cCE("tinsrb", e600010
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25054 cCE("tinsrh", e600050
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25055 cCE("tinsrw", e600090
, 3, (RIWR
, RR
, I7
), iwmmxt_tinsr
),
25056 cCE("tmcr", e000110
, 2, (RIWC_RIWG
, RR
), rn_rd
),
25057 cCE("tmcrr", c400000
, 3, (RIWR
, RR
, RR
), rm_rd_rn
),
25058 cCE("tmia", e200010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25059 cCE("tmiaph", e280010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25060 cCE("tmiabb", e2c0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25061 cCE("tmiabt", e2d0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25062 cCE("tmiatb", e2e0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25063 cCE("tmiatt", e2f0010
, 3, (RIWR
, RR
, RR
), iwmmxt_tmia
),
25064 cCE("tmovmskb",e100030
, 2, (RR
, RIWR
), rd_rn
),
25065 cCE("tmovmskh",e500030
, 2, (RR
, RIWR
), rd_rn
),
25066 cCE("tmovmskw",e900030
, 2, (RR
, RIWR
), rd_rn
),
25067 cCE("tmrc", e100110
, 2, (RR
, RIWC_RIWG
), rd_rn
),
25068 cCE("tmrrc", c500000
, 3, (RR
, RR
, RIWR
), rd_rn_rm
),
25069 cCE("torcb", e13f150
, 1, (RR
), iwmmxt_tandorc
),
25070 cCE("torch", e53f150
, 1, (RR
), iwmmxt_tandorc
),
25071 cCE("torcw", e93f150
, 1, (RR
), iwmmxt_tandorc
),
25072 cCE("waccb", e0001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25073 cCE("wacch", e4001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25074 cCE("waccw", e8001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25075 cCE("waddbss", e300180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25076 cCE("waddb", e000180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25077 cCE("waddbus", e100180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25078 cCE("waddhss", e700180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25079 cCE("waddh", e400180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25080 cCE("waddhus", e500180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25081 cCE("waddwss", eb00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25082 cCE("waddw", e800180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25083 cCE("waddwus", e900180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25084 cCE("waligni", e000020
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_waligni
),
25085 cCE("walignr0",e800020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25086 cCE("walignr1",e900020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25087 cCE("walignr2",ea00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25088 cCE("walignr3",eb00020
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25089 cCE("wand", e200000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25090 cCE("wandn", e300000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25091 cCE("wavg2b", e800000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25092 cCE("wavg2br", e900000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25093 cCE("wavg2h", ec00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25094 cCE("wavg2hr", ed00000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25095 cCE("wcmpeqb", e000060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25096 cCE("wcmpeqh", e400060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25097 cCE("wcmpeqw", e800060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25098 cCE("wcmpgtub",e100060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25099 cCE("wcmpgtuh",e500060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25100 cCE("wcmpgtuw",e900060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25101 cCE("wcmpgtsb",e300060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25102 cCE("wcmpgtsh",e700060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25103 cCE("wcmpgtsw",eb00060
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25104 cCE("wldrb", c100000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25105 cCE("wldrh", c500000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25106 cCE("wldrw", c100100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25107 cCE("wldrd", c500100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25108 cCE("wmacs", e600100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25109 cCE("wmacsz", e700100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25110 cCE("wmacu", e400100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25111 cCE("wmacuz", e500100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25112 cCE("wmadds", ea00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25113 cCE("wmaddu", e800100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25114 cCE("wmaxsb", e200160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25115 cCE("wmaxsh", e600160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25116 cCE("wmaxsw", ea00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25117 cCE("wmaxub", e000160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25118 cCE("wmaxuh", e400160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25119 cCE("wmaxuw", e800160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25120 cCE("wminsb", e300160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25121 cCE("wminsh", e700160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25122 cCE("wminsw", eb00160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25123 cCE("wminub", e100160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25124 cCE("wminuh", e500160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25125 cCE("wminuw", e900160
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25126 cCE("wmov", e000000
, 2, (RIWR
, RIWR
), iwmmxt_wmov
),
25127 cCE("wmulsm", e300100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25128 cCE("wmulsl", e200100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25129 cCE("wmulum", e100100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25130 cCE("wmulul", e000100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25131 cCE("wor", e000000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25132 cCE("wpackhss",e700080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25133 cCE("wpackhus",e500080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25134 cCE("wpackwss",eb00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25135 cCE("wpackwus",e900080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25136 cCE("wpackdss",ef00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25137 cCE("wpackdus",ed00080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25138 cCE("wrorh", e700040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25139 cCE("wrorhg", e700148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25140 cCE("wrorw", eb00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25141 cCE("wrorwg", eb00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25142 cCE("wrord", ef00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25143 cCE("wrordg", ef00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25144 cCE("wsadb", e000120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25145 cCE("wsadbz", e100120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25146 cCE("wsadh", e400120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25147 cCE("wsadhz", e500120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25148 cCE("wshufh", e0001e0
, 3, (RIWR
, RIWR
, I255
), iwmmxt_wshufh
),
25149 cCE("wsllh", e500040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25150 cCE("wsllhg", e500148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25151 cCE("wsllw", e900040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25152 cCE("wsllwg", e900148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25153 cCE("wslld", ed00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25154 cCE("wslldg", ed00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25155 cCE("wsrah", e400040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25156 cCE("wsrahg", e400148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25157 cCE("wsraw", e800040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25158 cCE("wsrawg", e800148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25159 cCE("wsrad", ec00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25160 cCE("wsradg", ec00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25161 cCE("wsrlh", e600040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25162 cCE("wsrlhg", e600148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25163 cCE("wsrlw", ea00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25164 cCE("wsrlwg", ea00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25165 cCE("wsrld", ee00040
, 3, (RIWR
, RIWR
, RIWR_I32z
),iwmmxt_wrwrwr_or_imm5
),
25166 cCE("wsrldg", ee00148
, 3, (RIWR
, RIWR
, RIWG
), rd_rn_rm
),
25167 cCE("wstrb", c000000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25168 cCE("wstrh", c400000
, 2, (RIWR
, ADDR
), iwmmxt_wldstbh
),
25169 cCE("wstrw", c000100
, 2, (RIWR_RIWC
, ADDR
), iwmmxt_wldstw
),
25170 cCE("wstrd", c400100
, 2, (RIWR
, ADDR
), iwmmxt_wldstd
),
25171 cCE("wsubbss", e3001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25172 cCE("wsubb", e0001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25173 cCE("wsubbus", e1001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25174 cCE("wsubhss", e7001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25175 cCE("wsubh", e4001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25176 cCE("wsubhus", e5001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25177 cCE("wsubwss", eb001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25178 cCE("wsubw", e8001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25179 cCE("wsubwus", e9001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25180 cCE("wunpckehub",e0000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25181 cCE("wunpckehuh",e4000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25182 cCE("wunpckehuw",e8000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25183 cCE("wunpckehsb",e2000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25184 cCE("wunpckehsh",e6000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25185 cCE("wunpckehsw",ea000c0
, 2, (RIWR
, RIWR
), rd_rn
),
25186 cCE("wunpckihb", e1000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25187 cCE("wunpckihh", e5000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25188 cCE("wunpckihw", e9000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25189 cCE("wunpckelub",e0000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25190 cCE("wunpckeluh",e4000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25191 cCE("wunpckeluw",e8000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25192 cCE("wunpckelsb",e2000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25193 cCE("wunpckelsh",e6000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25194 cCE("wunpckelsw",ea000e0
, 2, (RIWR
, RIWR
), rd_rn
),
25195 cCE("wunpckilb", e1000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25196 cCE("wunpckilh", e5000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25197 cCE("wunpckilw", e9000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25198 cCE("wxor", e100000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25199 cCE("wzero", e300000
, 1, (RIWR
), iwmmxt_wzero
),
25202 #define ARM_VARIANT & arm_cext_iwmmxt2 /* Intel Wireless MMX technology, version 2. */
25204 cCE("torvscb", e12f190
, 1, (RR
), iwmmxt_tandorc
),
25205 cCE("torvsch", e52f190
, 1, (RR
), iwmmxt_tandorc
),
25206 cCE("torvscw", e92f190
, 1, (RR
), iwmmxt_tandorc
),
25207 cCE("wabsb", e2001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25208 cCE("wabsh", e6001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25209 cCE("wabsw", ea001c0
, 2, (RIWR
, RIWR
), rd_rn
),
25210 cCE("wabsdiffb", e1001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25211 cCE("wabsdiffh", e5001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25212 cCE("wabsdiffw", e9001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25213 cCE("waddbhusl", e2001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25214 cCE("waddbhusm", e6001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25215 cCE("waddhc", e600180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25216 cCE("waddwc", ea00180
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25217 cCE("waddsubhx", ea001a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25218 cCE("wavg4", e400000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25219 cCE("wavg4r", e500000
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25220 cCE("wmaddsn", ee00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25221 cCE("wmaddsx", eb00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25222 cCE("wmaddun", ec00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25223 cCE("wmaddux", e900100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25224 cCE("wmerge", e000080
, 4, (RIWR
, RIWR
, RIWR
, I7
), iwmmxt_wmerge
),
25225 cCE("wmiabb", e0000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25226 cCE("wmiabt", e1000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25227 cCE("wmiatb", e2000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25228 cCE("wmiatt", e3000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25229 cCE("wmiabbn", e4000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25230 cCE("wmiabtn", e5000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25231 cCE("wmiatbn", e6000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25232 cCE("wmiattn", e7000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25233 cCE("wmiawbb", e800120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25234 cCE("wmiawbt", e900120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25235 cCE("wmiawtb", ea00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25236 cCE("wmiawtt", eb00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25237 cCE("wmiawbbn", ec00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25238 cCE("wmiawbtn", ed00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25239 cCE("wmiawtbn", ee00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25240 cCE("wmiawttn", ef00120
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25241 cCE("wmulsmr", ef00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25242 cCE("wmulumr", ed00100
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25243 cCE("wmulwumr", ec000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25244 cCE("wmulwsmr", ee000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25245 cCE("wmulwum", ed000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25246 cCE("wmulwsm", ef000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25247 cCE("wmulwl", eb000c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25248 cCE("wqmiabb", e8000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25249 cCE("wqmiabt", e9000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25250 cCE("wqmiatb", ea000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25251 cCE("wqmiatt", eb000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25252 cCE("wqmiabbn", ec000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25253 cCE("wqmiabtn", ed000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25254 cCE("wqmiatbn", ee000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25255 cCE("wqmiattn", ef000a0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25256 cCE("wqmulm", e100080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25257 cCE("wqmulmr", e300080
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25258 cCE("wqmulwm", ec000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25259 cCE("wqmulwmr", ee000e0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25260 cCE("wsubaddhx", ed001c0
, 3, (RIWR
, RIWR
, RIWR
), rd_rn_rm
),
25263 #define ARM_VARIANT & arm_cext_maverick /* Cirrus Maverick instructions. */
25265 cCE("cfldrs", c100400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25266 cCE("cfldrd", c500400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25267 cCE("cfldr32", c100500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25268 cCE("cfldr64", c500500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25269 cCE("cfstrs", c000400
, 2, (RMF
, ADDRGLDC
), rd_cpaddr
),
25270 cCE("cfstrd", c400400
, 2, (RMD
, ADDRGLDC
), rd_cpaddr
),
25271 cCE("cfstr32", c000500
, 2, (RMFX
, ADDRGLDC
), rd_cpaddr
),
25272 cCE("cfstr64", c400500
, 2, (RMDX
, ADDRGLDC
), rd_cpaddr
),
25273 cCE("cfmvsr", e000450
, 2, (RMF
, RR
), rn_rd
),
25274 cCE("cfmvrs", e100450
, 2, (RR
, RMF
), rd_rn
),
25275 cCE("cfmvdlr", e000410
, 2, (RMD
, RR
), rn_rd
),
25276 cCE("cfmvrdl", e100410
, 2, (RR
, RMD
), rd_rn
),
25277 cCE("cfmvdhr", e000430
, 2, (RMD
, RR
), rn_rd
),
25278 cCE("cfmvrdh", e100430
, 2, (RR
, RMD
), rd_rn
),
25279 cCE("cfmv64lr",e000510
, 2, (RMDX
, RR
), rn_rd
),
25280 cCE("cfmvr64l",e100510
, 2, (RR
, RMDX
), rd_rn
),
25281 cCE("cfmv64hr",e000530
, 2, (RMDX
, RR
), rn_rd
),
25282 cCE("cfmvr64h",e100530
, 2, (RR
, RMDX
), rd_rn
),
25283 cCE("cfmval32",e200440
, 2, (RMAX
, RMFX
), rd_rn
),
25284 cCE("cfmv32al",e100440
, 2, (RMFX
, RMAX
), rd_rn
),
25285 cCE("cfmvam32",e200460
, 2, (RMAX
, RMFX
), rd_rn
),
25286 cCE("cfmv32am",e100460
, 2, (RMFX
, RMAX
), rd_rn
),
25287 cCE("cfmvah32",e200480
, 2, (RMAX
, RMFX
), rd_rn
),
25288 cCE("cfmv32ah",e100480
, 2, (RMFX
, RMAX
), rd_rn
),
25289 cCE("cfmva32", e2004a0
, 2, (RMAX
, RMFX
), rd_rn
),
25290 cCE("cfmv32a", e1004a0
, 2, (RMFX
, RMAX
), rd_rn
),
25291 cCE("cfmva64", e2004c0
, 2, (RMAX
, RMDX
), rd_rn
),
25292 cCE("cfmv64a", e1004c0
, 2, (RMDX
, RMAX
), rd_rn
),
25293 cCE("cfmvsc32",e2004e0
, 2, (RMDS
, RMDX
), mav_dspsc
),
25294 cCE("cfmv32sc",e1004e0
, 2, (RMDX
, RMDS
), rd
),
25295 cCE("cfcpys", e000400
, 2, (RMF
, RMF
), rd_rn
),
25296 cCE("cfcpyd", e000420
, 2, (RMD
, RMD
), rd_rn
),
25297 cCE("cfcvtsd", e000460
, 2, (RMD
, RMF
), rd_rn
),
25298 cCE("cfcvtds", e000440
, 2, (RMF
, RMD
), rd_rn
),
25299 cCE("cfcvt32s",e000480
, 2, (RMF
, RMFX
), rd_rn
),
25300 cCE("cfcvt32d",e0004a0
, 2, (RMD
, RMFX
), rd_rn
),
25301 cCE("cfcvt64s",e0004c0
, 2, (RMF
, RMDX
), rd_rn
),
25302 cCE("cfcvt64d",e0004e0
, 2, (RMD
, RMDX
), rd_rn
),
25303 cCE("cfcvts32",e100580
, 2, (RMFX
, RMF
), rd_rn
),
25304 cCE("cfcvtd32",e1005a0
, 2, (RMFX
, RMD
), rd_rn
),
25305 cCE("cftruncs32",e1005c0
, 2, (RMFX
, RMF
), rd_rn
),
25306 cCE("cftruncd32",e1005e0
, 2, (RMFX
, RMD
), rd_rn
),
25307 cCE("cfrshl32",e000550
, 3, (RMFX
, RMFX
, RR
), mav_triple
),
25308 cCE("cfrshl64",e000570
, 3, (RMDX
, RMDX
, RR
), mav_triple
),
25309 cCE("cfsh32", e000500
, 3, (RMFX
, RMFX
, I63s
), mav_shift
),
25310 cCE("cfsh64", e200500
, 3, (RMDX
, RMDX
, I63s
), mav_shift
),
25311 cCE("cfcmps", e100490
, 3, (RR
, RMF
, RMF
), rd_rn_rm
),
25312 cCE("cfcmpd", e1004b0
, 3, (RR
, RMD
, RMD
), rd_rn_rm
),
25313 cCE("cfcmp32", e100590
, 3, (RR
, RMFX
, RMFX
), rd_rn_rm
),
25314 cCE("cfcmp64", e1005b0
, 3, (RR
, RMDX
, RMDX
), rd_rn_rm
),
25315 cCE("cfabss", e300400
, 2, (RMF
, RMF
), rd_rn
),
25316 cCE("cfabsd", e300420
, 2, (RMD
, RMD
), rd_rn
),
25317 cCE("cfnegs", e300440
, 2, (RMF
, RMF
), rd_rn
),
25318 cCE("cfnegd", e300460
, 2, (RMD
, RMD
), rd_rn
),
25319 cCE("cfadds", e300480
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25320 cCE("cfaddd", e3004a0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25321 cCE("cfsubs", e3004c0
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25322 cCE("cfsubd", e3004e0
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25323 cCE("cfmuls", e100400
, 3, (RMF
, RMF
, RMF
), rd_rn_rm
),
25324 cCE("cfmuld", e100420
, 3, (RMD
, RMD
, RMD
), rd_rn_rm
),
25325 cCE("cfabs32", e300500
, 2, (RMFX
, RMFX
), rd_rn
),
25326 cCE("cfabs64", e300520
, 2, (RMDX
, RMDX
), rd_rn
),
25327 cCE("cfneg32", e300540
, 2, (RMFX
, RMFX
), rd_rn
),
25328 cCE("cfneg64", e300560
, 2, (RMDX
, RMDX
), rd_rn
),
25329 cCE("cfadd32", e300580
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25330 cCE("cfadd64", e3005a0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25331 cCE("cfsub32", e3005c0
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25332 cCE("cfsub64", e3005e0
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25333 cCE("cfmul32", e100500
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25334 cCE("cfmul64", e100520
, 3, (RMDX
, RMDX
, RMDX
), rd_rn_rm
),
25335 cCE("cfmac32", e100540
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25336 cCE("cfmsc32", e100560
, 3, (RMFX
, RMFX
, RMFX
), rd_rn_rm
),
25337 cCE("cfmadd32",e000600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25338 cCE("cfmsub32",e100600
, 4, (RMAX
, RMFX
, RMFX
, RMFX
), mav_quad
),
25339 cCE("cfmadda32", e200600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25340 cCE("cfmsuba32", e300600
, 4, (RMAX
, RMAX
, RMFX
, RMFX
), mav_quad
),
25342 /* ARMv8.5-A instructions. */
25344 #define ARM_VARIANT & arm_ext_sb
25345 #undef THUMB_VARIANT
25346 #define THUMB_VARIANT & arm_ext_sb
25347 TUF("sb", 57ff070
, f3bf8f70
, 0, (), noargs
, noargs
),
25350 #define ARM_VARIANT & arm_ext_predres
25351 #undef THUMB_VARIANT
25352 #define THUMB_VARIANT & arm_ext_predres
25353 CE("cfprctx", e070f93
, 1, (RRnpc
), rd
),
25354 CE("dvprctx", e070fb3
, 1, (RRnpc
), rd
),
25355 CE("cpprctx", e070ff3
, 1, (RRnpc
), rd
),
25357 /* ARMv8-M instructions. */
25359 #define ARM_VARIANT NULL
25360 #undef THUMB_VARIANT
25361 #define THUMB_VARIANT & arm_ext_v8m
25362 ToU("sg", e97fe97f
, 0, (), noargs
),
25363 ToC("blxns", 4784, 1, (RRnpc
), t_blx
),
25364 ToC("bxns", 4704, 1, (RRnpc
), t_bx
),
25365 ToC("tt", e840f000
, 2, (RRnpc
, RRnpc
), tt
),
25366 ToC("ttt", e840f040
, 2, (RRnpc
, RRnpc
), tt
),
25367 ToC("tta", e840f080
, 2, (RRnpc
, RRnpc
), tt
),
25368 ToC("ttat", e840f0c0
, 2, (RRnpc
, RRnpc
), tt
),
25370 /* FP for ARMv8-M Mainline. Enabled for ARMv8-M Mainline because the
25371 instructions behave as nop if no VFP is present. */
25372 #undef THUMB_VARIANT
25373 #define THUMB_VARIANT & arm_ext_v8m_main
25374 ToC("vlldm", ec300a00
, 1, (RRnpc
), rn
),
25375 ToC("vlstm", ec200a00
, 1, (RRnpc
), rn
),
25377 /* Armv8.1-M Mainline instructions. */
25378 #undef THUMB_VARIANT
25379 #define THUMB_VARIANT & arm_ext_v8_1m_main
25380 toU("cinc", _cinc
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25381 toU("cinv", _cinv
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25382 toU("cneg", _cneg
, 3, (RRnpcsp
, RR_ZR
, COND
), t_cond
),
25383 toU("csel", _csel
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25384 toU("csetm", _csetm
, 2, (RRnpcsp
, COND
), t_cond
),
25385 toU("cset", _cset
, 2, (RRnpcsp
, COND
), t_cond
),
25386 toU("csinc", _csinc
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25387 toU("csinv", _csinv
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25388 toU("csneg", _csneg
, 4, (RRnpcsp
, RR_ZR
, RR_ZR
, COND
), t_cond
),
25390 toC("bf", _bf
, 2, (EXPs
, EXPs
), t_branch_future
),
25391 toU("bfcsel", _bfcsel
, 4, (EXPs
, EXPs
, EXPs
, COND
), t_branch_future
),
25392 toC("bfx", _bfx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25393 toC("bfl", _bfl
, 2, (EXPs
, EXPs
), t_branch_future
),
25394 toC("bflx", _bflx
, 2, (EXPs
, RRnpcsp
), t_branch_future
),
25396 toU("dls", _dls
, 2, (LR
, RRnpcsp
), t_loloop
),
25397 toU("wls", _wls
, 3, (LR
, RRnpcsp
, EXP
), t_loloop
),
25398 toU("le", _le
, 2, (oLR
, EXP
), t_loloop
),
25400 ToC("clrm", e89f0000
, 1, (CLRMLST
), t_clrm
),
25401 ToC("vscclrm", ec9f0a00
, 1, (VRSDVLST
), t_vscclrm
),
25403 #undef THUMB_VARIANT
25404 #define THUMB_VARIANT & mve_ext
25405 ToC("lsll", ea50010d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25406 ToC("lsrl", ea50011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25407 ToC("asrl", ea50012d
, 3, (RRe
, RRo
, RRnpcsp_I32
), mve_scalar_shift
),
25408 ToC("uqrshll", ea51010d
, 3, (RRe
, RRo
, RRnpcsp
), mve_scalar_shift
),
25409 ToC("sqrshrl", ea51012d
, 3, (RRe
, RRo
, RRnpcsp
), mve_scalar_shift
),
25410 ToC("uqshll", ea51010f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25411 ToC("urshrl", ea51011f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25412 ToC("srshrl", ea51012f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25413 ToC("sqshll", ea51013f
, 3, (RRe
, RRo
, I32
), mve_scalar_shift
),
25414 ToC("uqrshl", ea500f0d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25415 ToC("sqrshr", ea500f2d
, 2, (RRnpcsp
, RRnpcsp
), mve_scalar_shift
),
25416 ToC("uqshl", ea500f0f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25417 ToC("urshr", ea500f1f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25418 ToC("srshr", ea500f2f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25419 ToC("sqshl", ea500f3f
, 2, (RRnpcsp
, I32
), mve_scalar_shift
),
25421 ToC("vpt", ee410f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25422 ToC("vptt", ee018f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25423 ToC("vpte", ee418f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25424 ToC("vpttt", ee014f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25425 ToC("vptte", ee01cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25426 ToC("vptet", ee41cf00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25427 ToC("vptee", ee414f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25428 ToC("vptttt", ee012f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25429 ToC("vpttte", ee016f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25430 ToC("vpttet", ee01ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25431 ToC("vpttee", ee01af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25432 ToC("vptett", ee41af00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25433 ToC("vptete", ee41ef00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25434 ToC("vpteet", ee416f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25435 ToC("vpteee", ee412f00
, 3, (COND
, RMQ
, RMQRZ
), mve_vpt
),
25437 ToC("vpst", fe710f4d
, 0, (), mve_vpt
),
25438 ToC("vpstt", fe318f4d
, 0, (), mve_vpt
),
25439 ToC("vpste", fe718f4d
, 0, (), mve_vpt
),
25440 ToC("vpsttt", fe314f4d
, 0, (), mve_vpt
),
25441 ToC("vpstte", fe31cf4d
, 0, (), mve_vpt
),
25442 ToC("vpstet", fe71cf4d
, 0, (), mve_vpt
),
25443 ToC("vpstee", fe714f4d
, 0, (), mve_vpt
),
25444 ToC("vpstttt", fe312f4d
, 0, (), mve_vpt
),
25445 ToC("vpsttte", fe316f4d
, 0, (), mve_vpt
),
25446 ToC("vpsttet", fe31ef4d
, 0, (), mve_vpt
),
25447 ToC("vpsttee", fe31af4d
, 0, (), mve_vpt
),
25448 ToC("vpstett", fe71af4d
, 0, (), mve_vpt
),
25449 ToC("vpstete", fe71ef4d
, 0, (), mve_vpt
),
25450 ToC("vpsteet", fe716f4d
, 0, (), mve_vpt
),
25451 ToC("vpsteee", fe712f4d
, 0, (), mve_vpt
),
25453 /* MVE and MVE FP only. */
25454 mToC("vhcadd", ee000f00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vhcadd
),
25455 mCEF(vadc
, _vadc
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25456 mCEF(vadci
, _vadci
, 3, (RMQ
, RMQ
, RMQ
), mve_vadc
),
25457 mToC("vsbc", fe300f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25458 mToC("vsbci", fe301f00
, 3, (RMQ
, RMQ
, RMQ
), mve_vsbc
),
25459 mCEF(vmullb
, _vmullb
, 3, (RMQ
, RMQ
, RMQ
), mve_vmull
),
25460 mCEF(vabav
, _vabav
, 3, (RRnpcsp
, RMQ
, RMQ
), mve_vabav
),
25461 mCEF(vmladav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25462 mCEF(vmladava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25463 mCEF(vmladavx
, _vmladavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25464 mCEF(vmladavax
, _vmladavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25465 mCEF(vmlav
, _vmladav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25466 mCEF(vmlava
, _vmladava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25467 mCEF(vmlsdav
, _vmlsdav
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25468 mCEF(vmlsdava
, _vmlsdava
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25469 mCEF(vmlsdavx
, _vmlsdavx
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25470 mCEF(vmlsdavax
, _vmlsdavax
, 3, (RRe
, RMQ
, RMQ
), mve_vmladav
),
25472 mCEF(vst20
, _vst20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25473 mCEF(vst21
, _vst21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25474 mCEF(vst40
, _vst40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25475 mCEF(vst41
, _vst41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25476 mCEF(vst42
, _vst42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25477 mCEF(vst43
, _vst43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25478 mCEF(vld20
, _vld20
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25479 mCEF(vld21
, _vld21
, 2, (MSTRLST2
, ADDRMVE
), mve_vst_vld
),
25480 mCEF(vld40
, _vld40
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25481 mCEF(vld41
, _vld41
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25482 mCEF(vld42
, _vld42
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25483 mCEF(vld43
, _vld43
, 2, (MSTRLST4
, ADDRMVE
), mve_vst_vld
),
25484 mCEF(vstrb
, _vstrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25485 mCEF(vstrh
, _vstrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25486 mCEF(vstrw
, _vstrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25487 mCEF(vstrd
, _vstrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25488 mCEF(vldrb
, _vldrb
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25489 mCEF(vldrh
, _vldrh
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25490 mCEF(vldrw
, _vldrw
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25491 mCEF(vldrd
, _vldrd
, 2, (RMQ
, ADDRMVE
), mve_vstr_vldr
),
25493 mCEF(vmovnt
, _vmovnt
, 2, (RMQ
, RMQ
), mve_movn
),
25494 mCEF(vmovnb
, _vmovnb
, 2, (RMQ
, RMQ
), mve_movn
),
25495 mCEF(vbrsr
, _vbrsr
, 3, (RMQ
, RMQ
, RR
), mve_vbrsr
),
25496 mCEF(vaddlv
, _vaddlv
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25497 mCEF(vaddlva
, _vaddlva
, 3, (RRe
, RRo
, RMQ
), mve_vaddlv
),
25498 mCEF(vaddv
, _vaddv
, 2, (RRe
, RMQ
), mve_vaddv
),
25499 mCEF(vaddva
, _vaddva
, 2, (RRe
, RMQ
), mve_vaddv
),
25500 mCEF(vddup
, _vddup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25501 mCEF(vdwdup
, _vdwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25502 mCEF(vidup
, _vidup
, 3, (RMQ
, RRe
, EXPi
), mve_viddup
),
25503 mCEF(viwdup
, _viwdup
, 4, (RMQ
, RRe
, RR
, EXPi
), mve_viddup
),
25504 mToC("vmaxa", ee330e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25505 mToC("vmina", ee331e81
, 2, (RMQ
, RMQ
), mve_vmaxa_vmina
),
25506 mCEF(vmaxv
, _vmaxv
, 2, (RR
, RMQ
), mve_vmaxv
),
25507 mCEF(vmaxav
, _vmaxav
, 2, (RR
, RMQ
), mve_vmaxv
),
25508 mCEF(vminv
, _vminv
, 2, (RR
, RMQ
), mve_vmaxv
),
25509 mCEF(vminav
, _vminav
, 2, (RR
, RMQ
), mve_vmaxv
),
25511 mCEF(vmlaldav
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25512 mCEF(vmlaldava
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25513 mCEF(vmlaldavx
, _vmlaldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25514 mCEF(vmlaldavax
, _vmlaldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25515 mCEF(vmlalv
, _vmlaldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25516 mCEF(vmlalva
, _vmlaldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25517 mCEF(vmlsldav
, _vmlsldav
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25518 mCEF(vmlsldava
, _vmlsldava
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25519 mCEF(vmlsldavx
, _vmlsldavx
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25520 mCEF(vmlsldavax
, _vmlsldavax
, 4, (RRe
, RRo
, RMQ
, RMQ
), mve_vmlaldav
),
25521 mToC("vrmlaldavh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25522 mToC("vrmlaldavha",ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25523 mCEF(vrmlaldavhx
, _vrmlaldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25524 mCEF(vrmlaldavhax
, _vrmlaldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25525 mToC("vrmlalvh", ee800f00
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25526 mToC("vrmlalvha", ee800f20
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25527 mCEF(vrmlsldavh
, _vrmlsldavh
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25528 mCEF(vrmlsldavha
, _vrmlsldavha
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25529 mCEF(vrmlsldavhx
, _vrmlsldavhx
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25530 mCEF(vrmlsldavhax
, _vrmlsldavhax
, 4, (RRe
, RR
, RMQ
, RMQ
), mve_vrmlaldavh
),
25532 mToC("vmlas", ee011e40
, 3, (RMQ
, RMQ
, RR
), mve_vmlas
),
25533 mToC("vmulh", ee010e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25534 mToC("vrmulh", ee011e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vmulh
),
25535 mToC("vpnot", fe310f4d
, 0, (), mve_vpnot
),
25536 mToC("vpsel", fe310f01
, 3, (RMQ
, RMQ
, RMQ
), mve_vpsel
),
25538 mToC("vqdmladh", ee000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25539 mToC("vqdmladhx", ee001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25540 mToC("vqrdmladh", ee000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25541 mToC("vqrdmladhx",ee001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25542 mToC("vqdmlsdh", fe000e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25543 mToC("vqdmlsdhx", fe001e00
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25544 mToC("vqrdmlsdh", fe000e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25545 mToC("vqrdmlsdhx",fe001e01
, 3, (RMQ
, RMQ
, RMQ
), mve_vqdmladh
),
25546 mToC("vqdmlah", ee000e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25547 mToC("vqdmlash", ee001e60
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25548 mToC("vqrdmlash", ee001e40
, 3, (RMQ
, RMQ
, RR
), mve_vqdmlah
),
25549 mToC("vqdmullt", ee301f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25550 mToC("vqdmullb", ee300f00
, 3, (RMQ
, RMQ
, RMQRR
), mve_vqdmull
),
25551 mCEF(vqmovnt
, _vqmovnt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25552 mCEF(vqmovnb
, _vqmovnb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25553 mCEF(vqmovunt
, _vqmovunt
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25554 mCEF(vqmovunb
, _vqmovunb
, 2, (RMQ
, RMQ
), mve_vqmovn
),
25556 mCEF(vshrnt
, _vshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25557 mCEF(vshrnb
, _vshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25558 mCEF(vrshrnt
, _vrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25559 mCEF(vrshrnb
, _vrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25560 mCEF(vqshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25561 mCEF(vqshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25562 mCEF(vqshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25563 mCEF(vqshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25564 mCEF(vqrshrnt
, _vqrshrnt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25565 mCEF(vqrshrnb
, _vqrshrnb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25566 mCEF(vqrshrunt
, _vqrshrunt
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25567 mCEF(vqrshrunb
, _vqrshrunb
, 3, (RMQ
, RMQ
, I32z
), mve_vshrn
),
25569 mToC("vshlc", eea00fc0
, 3, (RMQ
, RR
, I32z
), mve_vshlc
),
25570 mToC("vshllt", ee201e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25571 mToC("vshllb", ee200e00
, 3, (RMQ
, RMQ
, I32
), mve_vshll
),
25573 toU("dlstp", _dlstp
, 2, (LR
, RR
), t_loloop
),
25574 toU("wlstp", _wlstp
, 3, (LR
, RR
, EXP
), t_loloop
),
25575 toU("letp", _letp
, 2, (LR
, EXP
), t_loloop
),
25576 toU("lctp", _lctp
, 0, (), t_loloop
),
25578 #undef THUMB_VARIANT
25579 #define THUMB_VARIANT & mve_fp_ext
25580 mToC("vcmul", ee300e00
, 4, (RMQ
, RMQ
, RMQ
, EXPi
), mve_vcmul
),
25581 mToC("vfmas", ee311e40
, 3, (RMQ
, RMQ
, RR
), mve_vfmas
),
25582 mToC("vmaxnma", ee3f0e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25583 mToC("vminnma", ee3f1e81
, 2, (RMQ
, RMQ
), mve_vmaxnma_vminnma
),
25584 mToC("vmaxnmv", eeee0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25585 mToC("vmaxnmav",eeec0f00
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25586 mToC("vminnmv", eeee0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25587 mToC("vminnmav",eeec0f80
, 2, (RR
, RMQ
), mve_vmaxnmv
),
25590 #define ARM_VARIANT & fpu_vfp_ext_v1
25591 #undef THUMB_VARIANT
25592 #define THUMB_VARIANT & arm_ext_v6t2
25593 mnCEF(vmla
, _vmla
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mac_maybe_scalar
),
25594 mnCEF(vmul
, _vmul
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ_RR
), neon_mul
),
25596 mcCE(fcpyd
, eb00b40
, 2, (RVD
, RVD
), vfp_dp_rd_rm
),
25599 #define ARM_VARIANT & fpu_vfp_ext_v1xd
25601 MNCE(vmov
, 0, 1, (VMOV
), neon_mov
),
25602 mcCE(fmrs
, e100a10
, 2, (RR
, RVS
), vfp_reg_from_sp
),
25603 mcCE(fmsr
, e000a10
, 2, (RVS
, RR
), vfp_sp_from_reg
),
25604 mcCE(fcpys
, eb00a40
, 2, (RVS
, RVS
), vfp_sp_monadic
),
25606 mCEF(vmullt
, _vmullt
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQ_RNSC_MQ
), mve_vmull
),
25607 mnCEF(vadd
, _vadd
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25608 mnCEF(vsub
, _vsub
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQR
), neon_addsub_if_i
),
25610 MNCEF(vabs
, 1b10300
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25611 MNCEF(vneg
, 1b10380
, 2, (RNSDQMQ
, RNSDQMQ
), neon_abs_neg
),
25613 mCEF(vmovlt
, _vmovlt
, 1, (VMOV
), mve_movl
),
25614 mCEF(vmovlb
, _vmovlb
, 1, (VMOV
), mve_movl
),
25616 mnCE(vcmp
, _vcmp
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25617 mnCE(vcmpe
, _vcmpe
, 3, (RVSD_COND
, RSVDMQ_FI0
, oRMQRZ
), vfp_nsyn_cmp
),
25620 #define ARM_VARIANT & fpu_vfp_ext_v2
25622 mcCE(fmsrr
, c400a10
, 3, (VRSLST
, RR
, RR
), vfp_sp2_from_reg2
),
25623 mcCE(fmrrs
, c500a10
, 3, (RR
, RR
, VRSLST
), vfp_reg2_from_sp2
),
25624 mcCE(fmdrr
, c400b10
, 3, (RVD
, RR
, RR
), vfp_dp_rm_rd_rn
),
25625 mcCE(fmrrd
, c500b10
, 3, (RR
, RR
, RVD
), vfp_dp_rd_rn_rm
),
25628 #define ARM_VARIANT & fpu_vfp_ext_armv8xd
25629 mnUF(vcvta
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvta
),
25630 mnUF(vcvtp
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtp
),
25631 mnUF(vcvtn
, _vcvta
, 3, (RNSDQMQ
, oRNSDQMQ
, oI32z
), neon_cvtn
),
25632 mnUF(vcvtm
, _vcvta
, 2, (RNSDQMQ
, oRNSDQMQ
), neon_cvtm
),
25633 mnUF(vmaxnm
, _vmaxnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25634 mnUF(vminnm
, _vminnm
, 3, (RNSDQMQ
, oRNSDQMQ
, RNSDQMQ
), vmaxnm
),
25637 #define ARM_VARIANT & fpu_neon_ext_v1
25638 mnUF(vabd
, _vabd
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25639 mnUF(vabdl
, _vabdl
, 3, (RNQMQ
, RNDMQ
, RNDMQ
), neon_dyadic_long
),
25640 mnUF(vaddl
, _vaddl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25641 mnUF(vsubl
, _vsubl
, 3, (RNQMQ
, RNDMQ
, RNDMQR
), neon_dyadic_long
),
25642 mnUF(vand
, _vand
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25643 mnUF(vbic
, _vbic
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25644 mnUF(vorr
, _vorr
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25645 mnUF(vorn
, _vorn
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_Ibig
), neon_logic
),
25646 mnUF(veor
, _veor
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_logic
),
25647 MNUF(vcls
, 1b00400
, 2, (RNDQMQ
, RNDQMQ
), neon_cls
),
25648 MNUF(vclz
, 1b00480
, 2, (RNDQMQ
, RNDQMQ
), neon_clz
),
25649 mnCE(vdup
, _vdup
, 2, (RNDQMQ
, RR_RNSC
), neon_dup
),
25650 MNUF(vhadd
, 00000000, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25651 MNUF(vrhadd
, 00000100, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_i_su
),
25652 MNUF(vhsub
, 00000200, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i_su
),
25653 mnUF(vmin
, _vmin
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25654 mnUF(vmax
, _vmax
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ
), neon_dyadic_if_su
),
25655 MNUF(vqadd
, 0000010, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25656 MNUF(vqsub
, 0000210, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_dyadic_i64_su
),
25657 mnUF(vmvn
, _vmvn
, 2, (RNDQMQ
, RNDQMQ_Ibig
), neon_mvn
),
25658 MNUF(vqabs
, 1b00700
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25659 MNUF(vqneg
, 1b00780
, 2, (RNDQMQ
, RNDQMQ
), neon_sat_abs_neg
),
25660 mnUF(vqrdmlah
, _vqrdmlah
,3, (RNDQMQ
, oRNDQMQ
, RNDQ_RNSC_RR
), neon_qrdmlah
),
25661 mnUF(vqdmulh
, _vqdmulh
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25662 mnUF(vqrdmulh
, _vqrdmulh
,3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_RNSC_RR
), neon_qdmulh
),
25663 MNUF(vqrshl
, 0000510, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25664 MNUF(vrshl
, 0000500, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQR
), neon_rshl
),
25665 MNUF(vshr
, 0800010, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25666 MNUF(vrshr
, 0800210, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_rshift_round_imm
),
25667 MNUF(vsli
, 1800510, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_sli
),
25668 MNUF(vsri
, 1800410, 3, (RNDQMQ
, oRNDQMQ
, I64z
), neon_sri
),
25669 MNUF(vrev64
, 1b00000
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25670 MNUF(vrev32
, 1b00080
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25671 MNUF(vrev16
, 1b00100
, 2, (RNDQMQ
, RNDQMQ
), neon_rev
),
25672 mnUF(vshl
, _vshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_shl
),
25673 mnUF(vqshl
, _vqshl
, 3, (RNDQMQ
, oRNDQMQ
, RNDQMQ_I63b_RR
), neon_qshl
),
25674 MNUF(vqshlu
, 1800610, 3, (RNDQMQ
, oRNDQMQ
, I63
), neon_qshlu_imm
),
25677 #define ARM_VARIANT & arm_ext_v8_3
25678 #undef THUMB_VARIANT
25679 #define THUMB_VARIANT & arm_ext_v6t2_v8m
25680 MNUF (vcadd
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ
, EXPi
), vcadd
),
25681 MNUF (vcmla
, 0, 4, (RNDQMQ
, RNDQMQ
, RNDQMQ_RNSC
, EXPi
), vcmla
),
25684 #undef THUMB_VARIANT
25716 /* MD interface: bits in the object file. */
25718 /* Turn an integer of n bytes (in val) into a stream of bytes appropriate
25719 for use in the a.out file, and stores them in the array pointed to by buf.
25720 This knows about the endian-ness of the target machine and does
25721 THE RIGHT THING, whatever it is. Possible values for n are 1 (byte)
25722 2 (short) and 4 (long) Floating numbers are put out as a series of
25723 LITTLENUMS (shorts, here at least). */
25726 md_number_to_chars (char * buf
, valueT val
, int n
)
25728 if (target_big_endian
)
25729 number_to_chars_bigendian (buf
, val
, n
);
25731 number_to_chars_littleendian (buf
, val
, n
);
25735 md_chars_to_number (char * buf
, int n
)
25738 unsigned char * where
= (unsigned char *) buf
;
25740 if (target_big_endian
)
25745 result
|= (*where
++ & 255);
25753 result
|= (where
[n
] & 255);
25760 /* MD interface: Sections. */
25762 /* Calculate the maximum variable size (i.e., excluding fr_fix)
25763 that an rs_machine_dependent frag may reach. */
25766 arm_frag_max_var (fragS
*fragp
)
25768 /* We only use rs_machine_dependent for variable-size Thumb instructions,
25769 which are either THUMB_SIZE (2) or INSN_SIZE (4).
25771 Note that we generate relaxable instructions even for cases that don't
25772 really need it, like an immediate that's a trivial constant. So we're
25773 overestimating the instruction size for some of those cases. Rather
25774 than putting more intelligence here, it would probably be better to
25775 avoid generating a relaxation frag in the first place when it can be
25776 determined up front that a short instruction will suffice. */
25778 gas_assert (fragp
->fr_type
== rs_machine_dependent
);
25782 /* Estimate the size of a frag before relaxing. Assume everything fits in
25786 md_estimate_size_before_relax (fragS
* fragp
,
25787 segT segtype ATTRIBUTE_UNUSED
)
25793 /* Convert a machine dependent frag. */
25796 md_convert_frag (bfd
*abfd
, segT asec ATTRIBUTE_UNUSED
, fragS
*fragp
)
25798 unsigned long insn
;
25799 unsigned long old_op
;
25807 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
25809 old_op
= bfd_get_16(abfd
, buf
);
25810 if (fragp
->fr_symbol
)
25812 exp
.X_op
= O_symbol
;
25813 exp
.X_add_symbol
= fragp
->fr_symbol
;
25817 exp
.X_op
= O_constant
;
25819 exp
.X_add_number
= fragp
->fr_offset
;
25820 opcode
= fragp
->fr_subtype
;
25823 case T_MNEM_ldr_pc
:
25824 case T_MNEM_ldr_pc2
:
25825 case T_MNEM_ldr_sp
:
25826 case T_MNEM_str_sp
:
25833 if (fragp
->fr_var
== 4)
25835 insn
= THUMB_OP32 (opcode
);
25836 if ((old_op
>> 12) == 4 || (old_op
>> 12) == 9)
25838 insn
|= (old_op
& 0x700) << 4;
25842 insn
|= (old_op
& 7) << 12;
25843 insn
|= (old_op
& 0x38) << 13;
25845 insn
|= 0x00000c00;
25846 put_thumb32_insn (buf
, insn
);
25847 reloc_type
= BFD_RELOC_ARM_T32_OFFSET_IMM
;
25851 reloc_type
= BFD_RELOC_ARM_THUMB_OFFSET
;
25853 pc_rel
= (opcode
== T_MNEM_ldr_pc2
);
25856 if (fragp
->fr_var
== 4)
25858 insn
= THUMB_OP32 (opcode
);
25859 insn
|= (old_op
& 0xf0) << 4;
25860 put_thumb32_insn (buf
, insn
);
25861 reloc_type
= BFD_RELOC_ARM_T32_ADD_PC12
;
25865 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25866 exp
.X_add_number
-= 4;
25874 if (fragp
->fr_var
== 4)
25876 int r0off
= (opcode
== T_MNEM_mov
25877 || opcode
== T_MNEM_movs
) ? 0 : 8;
25878 insn
= THUMB_OP32 (opcode
);
25879 insn
= (insn
& 0xe1ffffff) | 0x10000000;
25880 insn
|= (old_op
& 0x700) << r0off
;
25881 put_thumb32_insn (buf
, insn
);
25882 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25886 reloc_type
= BFD_RELOC_ARM_THUMB_IMM
;
25891 if (fragp
->fr_var
== 4)
25893 insn
= THUMB_OP32(opcode
);
25894 put_thumb32_insn (buf
, insn
);
25895 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH25
;
25898 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH12
;
25902 if (fragp
->fr_var
== 4)
25904 insn
= THUMB_OP32(opcode
);
25905 insn
|= (old_op
& 0xf00) << 14;
25906 put_thumb32_insn (buf
, insn
);
25907 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH20
;
25910 reloc_type
= BFD_RELOC_THUMB_PCREL_BRANCH9
;
25913 case T_MNEM_add_sp
:
25914 case T_MNEM_add_pc
:
25915 case T_MNEM_inc_sp
:
25916 case T_MNEM_dec_sp
:
25917 if (fragp
->fr_var
== 4)
25919 /* ??? Choose between add and addw. */
25920 insn
= THUMB_OP32 (opcode
);
25921 insn
|= (old_op
& 0xf0) << 4;
25922 put_thumb32_insn (buf
, insn
);
25923 if (opcode
== T_MNEM_add_pc
)
25924 reloc_type
= BFD_RELOC_ARM_T32_IMM12
;
25926 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25929 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25937 if (fragp
->fr_var
== 4)
25939 insn
= THUMB_OP32 (opcode
);
25940 insn
|= (old_op
& 0xf0) << 4;
25941 insn
|= (old_op
& 0xf) << 16;
25942 put_thumb32_insn (buf
, insn
);
25943 if (insn
& (1 << 20))
25944 reloc_type
= BFD_RELOC_ARM_T32_ADD_IMM
;
25946 reloc_type
= BFD_RELOC_ARM_T32_IMMEDIATE
;
25949 reloc_type
= BFD_RELOC_ARM_THUMB_ADD
;
25955 fixp
= fix_new_exp (fragp
, fragp
->fr_fix
, fragp
->fr_var
, &exp
, pc_rel
,
25956 (enum bfd_reloc_code_real
) reloc_type
);
25957 fixp
->fx_file
= fragp
->fr_file
;
25958 fixp
->fx_line
= fragp
->fr_line
;
25959 fragp
->fr_fix
+= fragp
->fr_var
;
25961 /* Set whether we use thumb-2 ISA based on final relaxation results. */
25962 if (thumb_mode
&& fragp
->fr_var
== 4 && no_cpu_selected ()
25963 && !ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_t2
))
25964 ARM_MERGE_FEATURE_SETS (arm_arch_used
, thumb_arch_used
, arm_ext_v6t2
);
25967 /* Return the size of a relaxable immediate operand instruction.
25968 SHIFT and SIZE specify the form of the allowable immediate. */
25970 relax_immediate (fragS
*fragp
, int size
, int shift
)
25976 /* ??? Should be able to do better than this. */
25977 if (fragp
->fr_symbol
)
25980 low
= (1 << shift
) - 1;
25981 mask
= (1 << (shift
+ size
)) - (1 << shift
);
25982 offset
= fragp
->fr_offset
;
25983 /* Force misaligned offsets to 32-bit variant. */
25986 if (offset
& ~mask
)
25991 /* Get the address of a symbol during relaxation. */
25993 relaxed_symbol_addr (fragS
*fragp
, long stretch
)
25999 sym
= fragp
->fr_symbol
;
26000 sym_frag
= symbol_get_frag (sym
);
26001 know (S_GET_SEGMENT (sym
) != absolute_section
26002 || sym_frag
== &zero_address_frag
);
26003 addr
= S_GET_VALUE (sym
) + fragp
->fr_offset
;
26005 /* If frag has yet to be reached on this pass, assume it will
26006 move by STRETCH just as we did. If this is not so, it will
26007 be because some frag between grows, and that will force
26011 && sym_frag
->relax_marker
!= fragp
->relax_marker
)
26015 /* Adjust stretch for any alignment frag. Note that if have
26016 been expanding the earlier code, the symbol may be
26017 defined in what appears to be an earlier frag. FIXME:
26018 This doesn't handle the fr_subtype field, which specifies
26019 a maximum number of bytes to skip when doing an
26021 for (f
= fragp
; f
!= NULL
&& f
!= sym_frag
; f
= f
->fr_next
)
26023 if (f
->fr_type
== rs_align
|| f
->fr_type
== rs_align_code
)
26026 stretch
= - ((- stretch
)
26027 & ~ ((1 << (int) f
->fr_offset
) - 1));
26029 stretch
&= ~ ((1 << (int) f
->fr_offset
) - 1);
26041 /* Return the size of a relaxable adr pseudo-instruction or PC-relative
26044 relax_adr (fragS
*fragp
, asection
*sec
, long stretch
)
26049 /* Assume worst case for symbols not known to be in the same section. */
26050 if (fragp
->fr_symbol
== NULL
26051 || !S_IS_DEFINED (fragp
->fr_symbol
)
26052 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26053 || S_IS_WEAK (fragp
->fr_symbol
))
26056 val
= relaxed_symbol_addr (fragp
, stretch
);
26057 addr
= fragp
->fr_address
+ fragp
->fr_fix
;
26058 addr
= (addr
+ 4) & ~3;
26059 /* Force misaligned targets to 32-bit variant. */
26063 if (val
< 0 || val
> 1020)
26068 /* Return the size of a relaxable add/sub immediate instruction. */
26070 relax_addsub (fragS
*fragp
, asection
*sec
)
26075 buf
= fragp
->fr_literal
+ fragp
->fr_fix
;
26076 op
= bfd_get_16(sec
->owner
, buf
);
26077 if ((op
& 0xf) == ((op
>> 4) & 0xf))
26078 return relax_immediate (fragp
, 8, 0);
26080 return relax_immediate (fragp
, 3, 0);
26083 /* Return TRUE iff the definition of symbol S could be pre-empted
26084 (overridden) at link or load time. */
26086 symbol_preemptible (symbolS
*s
)
26088 /* Weak symbols can always be pre-empted. */
26092 /* Non-global symbols cannot be pre-empted. */
26093 if (! S_IS_EXTERNAL (s
))
26097 /* In ELF, a global symbol can be marked protected, or private. In that
26098 case it can't be pre-empted (other definitions in the same link unit
26099 would violate the ODR). */
26100 if (ELF_ST_VISIBILITY (S_GET_OTHER (s
)) > STV_DEFAULT
)
26104 /* Other global symbols might be pre-empted. */
26108 /* Return the size of a relaxable branch instruction. BITS is the
26109 size of the offset field in the narrow instruction. */
26112 relax_branch (fragS
*fragp
, asection
*sec
, int bits
, long stretch
)
26118 /* Assume worst case for symbols not known to be in the same section. */
26119 if (!S_IS_DEFINED (fragp
->fr_symbol
)
26120 || sec
!= S_GET_SEGMENT (fragp
->fr_symbol
)
26121 || S_IS_WEAK (fragp
->fr_symbol
))
26125 /* A branch to a function in ARM state will require interworking. */
26126 if (S_IS_DEFINED (fragp
->fr_symbol
)
26127 && ARM_IS_FUNC (fragp
->fr_symbol
))
26131 if (symbol_preemptible (fragp
->fr_symbol
))
26134 val
= relaxed_symbol_addr (fragp
, stretch
);
26135 addr
= fragp
->fr_address
+ fragp
->fr_fix
+ 4;
26138 /* Offset is a signed value *2 */
26140 if (val
>= limit
|| val
< -limit
)
26146 /* Relax a machine dependent frag. This returns the amount by which
26147 the current size of the frag should change. */
26150 arm_relax_frag (asection
*sec
, fragS
*fragp
, long stretch
)
26155 oldsize
= fragp
->fr_var
;
26156 switch (fragp
->fr_subtype
)
26158 case T_MNEM_ldr_pc2
:
26159 newsize
= relax_adr (fragp
, sec
, stretch
);
26161 case T_MNEM_ldr_pc
:
26162 case T_MNEM_ldr_sp
:
26163 case T_MNEM_str_sp
:
26164 newsize
= relax_immediate (fragp
, 8, 2);
26168 newsize
= relax_immediate (fragp
, 5, 2);
26172 newsize
= relax_immediate (fragp
, 5, 1);
26176 newsize
= relax_immediate (fragp
, 5, 0);
26179 newsize
= relax_adr (fragp
, sec
, stretch
);
26185 newsize
= relax_immediate (fragp
, 8, 0);
26188 newsize
= relax_branch (fragp
, sec
, 11, stretch
);
26191 newsize
= relax_branch (fragp
, sec
, 8, stretch
);
26193 case T_MNEM_add_sp
:
26194 case T_MNEM_add_pc
:
26195 newsize
= relax_immediate (fragp
, 8, 2);
26197 case T_MNEM_inc_sp
:
26198 case T_MNEM_dec_sp
:
26199 newsize
= relax_immediate (fragp
, 7, 2);
26205 newsize
= relax_addsub (fragp
, sec
);
26211 fragp
->fr_var
= newsize
;
26212 /* Freeze wide instructions that are at or before the same location as
26213 in the previous pass. This avoids infinite loops.
26214 Don't freeze them unconditionally because targets may be artificially
26215 misaligned by the expansion of preceding frags. */
26216 if (stretch
<= 0 && newsize
> 2)
26218 md_convert_frag (sec
->owner
, sec
, fragp
);
26222 return newsize
- oldsize
;
26225 /* Round up a section size to the appropriate boundary. */
26228 md_section_align (segT segment ATTRIBUTE_UNUSED
,
26234 /* This is called from HANDLE_ALIGN in write.c. Fill in the contents
26235 of an rs_align_code fragment. */
26238 arm_handle_align (fragS
* fragP
)
26240 static unsigned char const arm_noop
[2][2][4] =
26243 {0x00, 0x00, 0xa0, 0xe1}, /* LE */
26244 {0xe1, 0xa0, 0x00, 0x00}, /* BE */
26247 {0x00, 0xf0, 0x20, 0xe3}, /* LE */
26248 {0xe3, 0x20, 0xf0, 0x00}, /* BE */
26251 static unsigned char const thumb_noop
[2][2][2] =
26254 {0xc0, 0x46}, /* LE */
26255 {0x46, 0xc0}, /* BE */
26258 {0x00, 0xbf}, /* LE */
26259 {0xbf, 0x00} /* BE */
26262 static unsigned char const wide_thumb_noop
[2][4] =
26263 { /* Wide Thumb-2 */
26264 {0xaf, 0xf3, 0x00, 0x80}, /* LE */
26265 {0xf3, 0xaf, 0x80, 0x00}, /* BE */
26268 unsigned bytes
, fix
, noop_size
;
26270 const unsigned char * noop
;
26271 const unsigned char *narrow_noop
= NULL
;
26276 if (fragP
->fr_type
!= rs_align_code
)
26279 bytes
= fragP
->fr_next
->fr_address
- fragP
->fr_address
- fragP
->fr_fix
;
26280 p
= fragP
->fr_literal
+ fragP
->fr_fix
;
26283 if (bytes
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26284 bytes
&= MAX_MEM_FOR_RS_ALIGN_CODE
;
26286 gas_assert ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) != 0);
26288 if (fragP
->tc_frag_data
.thumb_mode
& (~ MODE_RECORDED
))
26290 if (ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26291 ? selected_cpu
: arm_arch_none
, arm_ext_v6t2
))
26293 narrow_noop
= thumb_noop
[1][target_big_endian
];
26294 noop
= wide_thumb_noop
[target_big_endian
];
26297 noop
= thumb_noop
[0][target_big_endian
];
26305 noop
= arm_noop
[ARM_CPU_HAS_FEATURE (selected_cpu_name
[0]
26306 ? selected_cpu
: arm_arch_none
,
26308 [target_big_endian
];
26315 fragP
->fr_var
= noop_size
;
26317 if (bytes
& (noop_size
- 1))
26319 fix
= bytes
& (noop_size
- 1);
26321 insert_data_mapping_symbol (state
, fragP
->fr_fix
, fragP
, fix
);
26323 memset (p
, 0, fix
);
26330 if (bytes
& noop_size
)
26332 /* Insert a narrow noop. */
26333 memcpy (p
, narrow_noop
, noop_size
);
26335 bytes
-= noop_size
;
26339 /* Use wide noops for the remainder */
26343 while (bytes
>= noop_size
)
26345 memcpy (p
, noop
, noop_size
);
26347 bytes
-= noop_size
;
26351 fragP
->fr_fix
+= fix
;
26354 /* Called from md_do_align. Used to create an alignment
26355 frag in a code section. */
26358 arm_frag_align_code (int n
, int max
)
26362 /* We assume that there will never be a requirement
26363 to support alignments greater than MAX_MEM_FOR_RS_ALIGN_CODE bytes. */
26364 if (max
> MAX_MEM_FOR_RS_ALIGN_CODE
)
26369 _("alignments greater than %d bytes not supported in .text sections."),
26370 MAX_MEM_FOR_RS_ALIGN_CODE
+ 1);
26371 as_fatal ("%s", err_msg
);
26374 p
= frag_var (rs_align_code
,
26375 MAX_MEM_FOR_RS_ALIGN_CODE
,
26377 (relax_substateT
) max
,
26384 /* Perform target specific initialisation of a frag.
26385 Note - despite the name this initialisation is not done when the frag
26386 is created, but only when its type is assigned. A frag can be created
26387 and used a long time before its type is set, so beware of assuming that
26388 this initialisation is performed first. */
26392 arm_init_frag (fragS
* fragP
, int max_chars ATTRIBUTE_UNUSED
)
26394 /* Record whether this frag is in an ARM or a THUMB area. */
26395 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26398 #else /* OBJ_ELF is defined. */
26400 arm_init_frag (fragS
* fragP
, int max_chars
)
26402 bfd_boolean frag_thumb_mode
;
26404 /* If the current ARM vs THUMB mode has not already
26405 been recorded into this frag then do so now. */
26406 if ((fragP
->tc_frag_data
.thumb_mode
& MODE_RECORDED
) == 0)
26407 fragP
->tc_frag_data
.thumb_mode
= thumb_mode
| MODE_RECORDED
;
26409 /* PR 21809: Do not set a mapping state for debug sections
26410 - it just confuses other tools. */
26411 if (bfd_get_section_flags (NULL
, now_seg
) & SEC_DEBUGGING
)
26414 frag_thumb_mode
= fragP
->tc_frag_data
.thumb_mode
^ MODE_RECORDED
;
26416 /* Record a mapping symbol for alignment frags. We will delete this
26417 later if the alignment ends up empty. */
26418 switch (fragP
->fr_type
)
26421 case rs_align_test
:
26423 mapping_state_2 (MAP_DATA
, max_chars
);
26425 case rs_align_code
:
26426 mapping_state_2 (frag_thumb_mode
? MAP_THUMB
: MAP_ARM
, max_chars
);
26433 /* When we change sections we need to issue a new mapping symbol. */
26436 arm_elf_change_section (void)
26438 /* Link an unlinked unwind index table section to the .text section. */
26439 if (elf_section_type (now_seg
) == SHT_ARM_EXIDX
26440 && elf_linked_to_section (now_seg
) == NULL
)
26441 elf_linked_to_section (now_seg
) = text_section
;
26445 arm_elf_section_type (const char * str
, size_t len
)
26447 if (len
== 5 && strncmp (str
, "exidx", 5) == 0)
26448 return SHT_ARM_EXIDX
;
26453 /* Code to deal with unwinding tables. */
26455 static void add_unwind_adjustsp (offsetT
);
26457 /* Generate any deferred unwind frame offset. */
26460 flush_pending_unwind (void)
26464 offset
= unwind
.pending_offset
;
26465 unwind
.pending_offset
= 0;
26467 add_unwind_adjustsp (offset
);
26470 /* Add an opcode to this list for this function. Two-byte opcodes should
26471 be passed as op[0] << 8 | op[1]. The list of opcodes is built in reverse
26475 add_unwind_opcode (valueT op
, int length
)
26477 /* Add any deferred stack adjustment. */
26478 if (unwind
.pending_offset
)
26479 flush_pending_unwind ();
26481 unwind
.sp_restored
= 0;
26483 if (unwind
.opcode_count
+ length
> unwind
.opcode_alloc
)
26485 unwind
.opcode_alloc
+= ARM_OPCODE_CHUNK_SIZE
;
26486 if (unwind
.opcodes
)
26487 unwind
.opcodes
= XRESIZEVEC (unsigned char, unwind
.opcodes
,
26488 unwind
.opcode_alloc
);
26490 unwind
.opcodes
= XNEWVEC (unsigned char, unwind
.opcode_alloc
);
26495 unwind
.opcodes
[unwind
.opcode_count
] = op
& 0xff;
26497 unwind
.opcode_count
++;
26501 /* Add unwind opcodes to adjust the stack pointer. */
26504 add_unwind_adjustsp (offsetT offset
)
26508 if (offset
> 0x200)
26510 /* We need at most 5 bytes to hold a 32-bit value in a uleb128. */
26515 /* Long form: 0xb2, uleb128. */
26516 /* This might not fit in a word so add the individual bytes,
26517 remembering the list is built in reverse order. */
26518 o
= (valueT
) ((offset
- 0x204) >> 2);
26520 add_unwind_opcode (0, 1);
26522 /* Calculate the uleb128 encoding of the offset. */
26526 bytes
[n
] = o
& 0x7f;
26532 /* Add the insn. */
26534 add_unwind_opcode (bytes
[n
- 1], 1);
26535 add_unwind_opcode (0xb2, 1);
26537 else if (offset
> 0x100)
26539 /* Two short opcodes. */
26540 add_unwind_opcode (0x3f, 1);
26541 op
= (offset
- 0x104) >> 2;
26542 add_unwind_opcode (op
, 1);
26544 else if (offset
> 0)
26546 /* Short opcode. */
26547 op
= (offset
- 4) >> 2;
26548 add_unwind_opcode (op
, 1);
26550 else if (offset
< 0)
26553 while (offset
> 0x100)
26555 add_unwind_opcode (0x7f, 1);
26558 op
= ((offset
- 4) >> 2) | 0x40;
26559 add_unwind_opcode (op
, 1);
26563 /* Finish the list of unwind opcodes for this function. */
26566 finish_unwind_opcodes (void)
26570 if (unwind
.fp_used
)
26572 /* Adjust sp as necessary. */
26573 unwind
.pending_offset
+= unwind
.fp_offset
- unwind
.frame_size
;
26574 flush_pending_unwind ();
26576 /* After restoring sp from the frame pointer. */
26577 op
= 0x90 | unwind
.fp_reg
;
26578 add_unwind_opcode (op
, 1);
26581 flush_pending_unwind ();
26585 /* Start an exception table entry. If idx is nonzero this is an index table
26589 start_unwind_section (const segT text_seg
, int idx
)
26591 const char * text_name
;
26592 const char * prefix
;
26593 const char * prefix_once
;
26594 const char * group_name
;
26602 prefix
= ELF_STRING_ARM_unwind
;
26603 prefix_once
= ELF_STRING_ARM_unwind_once
;
26604 type
= SHT_ARM_EXIDX
;
26608 prefix
= ELF_STRING_ARM_unwind_info
;
26609 prefix_once
= ELF_STRING_ARM_unwind_info_once
;
26610 type
= SHT_PROGBITS
;
26613 text_name
= segment_name (text_seg
);
26614 if (streq (text_name
, ".text"))
26617 if (strncmp (text_name
, ".gnu.linkonce.t.",
26618 strlen (".gnu.linkonce.t.")) == 0)
26620 prefix
= prefix_once
;
26621 text_name
+= strlen (".gnu.linkonce.t.");
26624 sec_name
= concat (prefix
, text_name
, (char *) NULL
);
26630 /* Handle COMDAT group. */
26631 if (prefix
!= prefix_once
&& (text_seg
->flags
& SEC_LINK_ONCE
) != 0)
26633 group_name
= elf_group_name (text_seg
);
26634 if (group_name
== NULL
)
26636 as_bad (_("Group section `%s' has no group signature"),
26637 segment_name (text_seg
));
26638 ignore_rest_of_line ();
26641 flags
|= SHF_GROUP
;
26645 obj_elf_change_section (sec_name
, type
, 0, flags
, 0, group_name
,
26648 /* Set the section link for index tables. */
26650 elf_linked_to_section (now_seg
) = text_seg
;
26654 /* Start an unwind table entry. HAVE_DATA is nonzero if we have additional
26655 personality routine data. Returns zero, or the index table value for
26656 an inline entry. */
26659 create_unwind_entry (int have_data
)
26664 /* The current word of data. */
26666 /* The number of bytes left in this word. */
26669 finish_unwind_opcodes ();
26671 /* Remember the current text section. */
26672 unwind
.saved_seg
= now_seg
;
26673 unwind
.saved_subseg
= now_subseg
;
26675 start_unwind_section (now_seg
, 0);
26677 if (unwind
.personality_routine
== NULL
)
26679 if (unwind
.personality_index
== -2)
26682 as_bad (_("handlerdata in cantunwind frame"));
26683 return 1; /* EXIDX_CANTUNWIND. */
26686 /* Use a default personality routine if none is specified. */
26687 if (unwind
.personality_index
== -1)
26689 if (unwind
.opcode_count
> 3)
26690 unwind
.personality_index
= 1;
26692 unwind
.personality_index
= 0;
26695 /* Space for the personality routine entry. */
26696 if (unwind
.personality_index
== 0)
26698 if (unwind
.opcode_count
> 3)
26699 as_bad (_("too many unwind opcodes for personality routine 0"));
26703 /* All the data is inline in the index table. */
26706 while (unwind
.opcode_count
> 0)
26708 unwind
.opcode_count
--;
26709 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26713 /* Pad with "finish" opcodes. */
26715 data
= (data
<< 8) | 0xb0;
26722 /* We get two opcodes "free" in the first word. */
26723 size
= unwind
.opcode_count
- 2;
26727 /* PR 16765: Missing or misplaced unwind directives can trigger this. */
26728 if (unwind
.personality_index
!= -1)
26730 as_bad (_("attempt to recreate an unwind entry"));
26734 /* An extra byte is required for the opcode count. */
26735 size
= unwind
.opcode_count
+ 1;
26738 size
= (size
+ 3) >> 2;
26740 as_bad (_("too many unwind opcodes"));
26742 frag_align (2, 0, 0);
26743 record_alignment (now_seg
, 2);
26744 unwind
.table_entry
= expr_build_dot ();
26746 /* Allocate the table entry. */
26747 ptr
= frag_more ((size
<< 2) + 4);
26748 /* PR 13449: Zero the table entries in case some of them are not used. */
26749 memset (ptr
, 0, (size
<< 2) + 4);
26750 where
= frag_now_fix () - ((size
<< 2) + 4);
26752 switch (unwind
.personality_index
)
26755 /* ??? Should this be a PLT generating relocation? */
26756 /* Custom personality routine. */
26757 fix_new (frag_now
, where
, 4, unwind
.personality_routine
, 0, 1,
26758 BFD_RELOC_ARM_PREL31
);
26763 /* Set the first byte to the number of additional words. */
26764 data
= size
> 0 ? size
- 1 : 0;
26768 /* ABI defined personality routines. */
26770 /* Three opcodes bytes are packed into the first word. */
26777 /* The size and first two opcode bytes go in the first word. */
26778 data
= ((0x80 + unwind
.personality_index
) << 8) | size
;
26783 /* Should never happen. */
26787 /* Pack the opcodes into words (MSB first), reversing the list at the same
26789 while (unwind
.opcode_count
> 0)
26793 md_number_to_chars (ptr
, data
, 4);
26798 unwind
.opcode_count
--;
26800 data
= (data
<< 8) | unwind
.opcodes
[unwind
.opcode_count
];
26803 /* Finish off the last word. */
26806 /* Pad with "finish" opcodes. */
26808 data
= (data
<< 8) | 0xb0;
26810 md_number_to_chars (ptr
, data
, 4);
26815 /* Add an empty descriptor if there is no user-specified data. */
26816 ptr
= frag_more (4);
26817 md_number_to_chars (ptr
, 0, 4);
26824 /* Initialize the DWARF-2 unwind information for this procedure. */
26827 tc_arm_frame_initial_instructions (void)
26829 cfi_add_CFA_def_cfa (REG_SP
, 0);
26831 #endif /* OBJ_ELF */
26833 /* Convert REGNAME to a DWARF-2 register number. */
26836 tc_arm_regname_to_dw2regnum (char *regname
)
26838 int reg
= arm_reg_parse (®name
, REG_TYPE_RN
);
26842 /* PR 16694: Allow VFP registers as well. */
26843 reg
= arm_reg_parse (®name
, REG_TYPE_VFS
);
26847 reg
= arm_reg_parse (®name
, REG_TYPE_VFD
);
26856 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
26860 exp
.X_op
= O_secrel
;
26861 exp
.X_add_symbol
= symbol
;
26862 exp
.X_add_number
= 0;
26863 emit_expr (&exp
, size
);
26867 /* MD interface: Symbol and relocation handling. */
26869 /* Return the address within the segment that a PC-relative fixup is
26870 relative to. For ARM, PC-relative fixups applied to instructions
26871 are generally relative to the location of the fixup plus 8 bytes.
26872 Thumb branches are offset by 4, and Thumb loads relative to PC
26873 require special handling. */
26876 md_pcrel_from_section (fixS
* fixP
, segT seg
)
26878 offsetT base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26880 /* If this is pc-relative and we are going to emit a relocation
26881 then we just want to put out any pipeline compensation that the linker
26882 will need. Otherwise we want to use the calculated base.
26883 For WinCE we skip the bias for externals as well, since this
26884 is how the MS ARM-CE assembler behaves and we want to be compatible. */
26886 && ((fixP
->fx_addsy
&& S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
26887 || (arm_force_relocation (fixP
)
26889 && !S_IS_EXTERNAL (fixP
->fx_addsy
)
26895 switch (fixP
->fx_r_type
)
26897 /* PC relative addressing on the Thumb is slightly odd as the
26898 bottom two bits of the PC are forced to zero for the
26899 calculation. This happens *after* application of the
26900 pipeline offset. However, Thumb adrl already adjusts for
26901 this, so we need not do it again. */
26902 case BFD_RELOC_ARM_THUMB_ADD
:
26905 case BFD_RELOC_ARM_THUMB_OFFSET
:
26906 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
26907 case BFD_RELOC_ARM_T32_ADD_PC12
:
26908 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
26909 return (base
+ 4) & ~3;
26911 /* Thumb branches are simply offset by +4. */
26912 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
26913 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
26914 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
26915 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
26916 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
26917 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
26918 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
26919 case BFD_RELOC_ARM_THUMB_BF17
:
26920 case BFD_RELOC_ARM_THUMB_BF19
:
26921 case BFD_RELOC_ARM_THUMB_BF13
:
26922 case BFD_RELOC_ARM_THUMB_LOOP12
:
26925 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
26927 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26928 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26929 && ARM_IS_FUNC (fixP
->fx_addsy
)
26930 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26931 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26934 /* BLX is like branches above, but forces the low two bits of PC to
26936 case BFD_RELOC_THUMB_PCREL_BLX
:
26938 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26939 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26940 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26941 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26942 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26943 return (base
+ 4) & ~3;
26945 /* ARM mode branches are offset by +8. However, the Windows CE
26946 loader expects the relocation not to take this into account. */
26947 case BFD_RELOC_ARM_PCREL_BLX
:
26949 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26950 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26951 && ARM_IS_FUNC (fixP
->fx_addsy
)
26952 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26953 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26956 case BFD_RELOC_ARM_PCREL_CALL
:
26958 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26959 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
26960 && THUMB_IS_FUNC (fixP
->fx_addsy
)
26961 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
26962 base
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
26965 case BFD_RELOC_ARM_PCREL_BRANCH
:
26966 case BFD_RELOC_ARM_PCREL_JUMP
:
26967 case BFD_RELOC_ARM_PLT32
:
26969 /* When handling fixups immediately, because we have already
26970 discovered the value of a symbol, or the address of the frag involved
26971 we must account for the offset by +8, as the OS loader will never see the reloc.
26972 see fixup_segment() in write.c
26973 The S_IS_EXTERNAL test handles the case of global symbols.
26974 Those need the calculated base, not just the pipe compensation the linker will need. */
26976 && fixP
->fx_addsy
!= NULL
26977 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
26978 && (S_IS_EXTERNAL (fixP
->fx_addsy
) || !arm_force_relocation (fixP
)))
26986 /* ARM mode loads relative to PC are also offset by +8. Unlike
26987 branches, the Windows CE loader *does* expect the relocation
26988 to take this into account. */
26989 case BFD_RELOC_ARM_OFFSET_IMM
:
26990 case BFD_RELOC_ARM_OFFSET_IMM8
:
26991 case BFD_RELOC_ARM_HWLITERAL
:
26992 case BFD_RELOC_ARM_LITERAL
:
26993 case BFD_RELOC_ARM_CP_OFF_IMM
:
26997 /* Other PC-relative relocations are un-offset. */
27003 static bfd_boolean flag_warn_syms
= TRUE
;
27006 arm_tc_equal_in_insn (int c ATTRIBUTE_UNUSED
, char * name
)
27008 /* PR 18347 - Warn if the user attempts to create a symbol with the same
27009 name as an ARM instruction. Whilst strictly speaking it is allowed, it
27010 does mean that the resulting code might be very confusing to the reader.
27011 Also this warning can be triggered if the user omits an operand before
27012 an immediate address, eg:
27016 GAS treats this as an assignment of the value of the symbol foo to a
27017 symbol LDR, and so (without this code) it will not issue any kind of
27018 warning or error message.
27020 Note - ARM instructions are case-insensitive but the strings in the hash
27021 table are all stored in lower case, so we must first ensure that name is
27023 if (flag_warn_syms
&& arm_ops_hsh
)
27025 char * nbuf
= strdup (name
);
27028 for (p
= nbuf
; *p
; p
++)
27030 if (hash_find (arm_ops_hsh
, nbuf
) != NULL
)
27032 static struct hash_control
* already_warned
= NULL
;
27034 if (already_warned
== NULL
)
27035 already_warned
= hash_new ();
27036 /* Only warn about the symbol once. To keep the code
27037 simple we let hash_insert do the lookup for us. */
27038 if (hash_insert (already_warned
, nbuf
, NULL
) == NULL
)
27039 as_warn (_("[-mwarn-syms]: Assignment makes a symbol match an ARM instruction: %s"), name
);
27048 /* Under ELF we need to default _GLOBAL_OFFSET_TABLE.
27049 Otherwise we have no need to default values of symbols. */
27052 md_undefined_symbol (char * name ATTRIBUTE_UNUSED
)
27055 if (name
[0] == '_' && name
[1] == 'G'
27056 && streq (name
, GLOBAL_OFFSET_TABLE_NAME
))
27060 if (symbol_find (name
))
27061 as_bad (_("GOT already in the symbol table"));
27063 GOT_symbol
= symbol_new (name
, undefined_section
,
27064 (valueT
) 0, & zero_address_frag
);
27074 /* Subroutine of md_apply_fix. Check to see if an immediate can be
27075 computed as two separate immediate values, added together. We
27076 already know that this value cannot be computed by just one ARM
27079 static unsigned int
27080 validate_immediate_twopart (unsigned int val
,
27081 unsigned int * highpart
)
27086 for (i
= 0; i
< 32; i
+= 2)
27087 if (((a
= rotate_left (val
, i
)) & 0xff) != 0)
27093 * highpart
= (a
>> 8) | ((i
+ 24) << 7);
27095 else if (a
& 0xff0000)
27097 if (a
& 0xff000000)
27099 * highpart
= (a
>> 16) | ((i
+ 16) << 7);
27103 gas_assert (a
& 0xff000000);
27104 * highpart
= (a
>> 24) | ((i
+ 8) << 7);
27107 return (a
& 0xff) | (i
<< 7);
27114 validate_offset_imm (unsigned int val
, int hwse
)
27116 if ((hwse
&& val
> 255) || val
> 4095)
27121 /* Subroutine of md_apply_fix. Do those data_ops which can take a
27122 negative immediate constant by altering the instruction. A bit of
27127 by inverting the second operand, and
27130 by negating the second operand. */
27133 negate_data_op (unsigned long * instruction
,
27134 unsigned long value
)
27137 unsigned long negated
, inverted
;
27139 negated
= encode_arm_immediate (-value
);
27140 inverted
= encode_arm_immediate (~value
);
27142 op
= (*instruction
>> DATA_OP_SHIFT
) & 0xf;
27145 /* First negates. */
27146 case OPCODE_SUB
: /* ADD <-> SUB */
27147 new_inst
= OPCODE_ADD
;
27152 new_inst
= OPCODE_SUB
;
27156 case OPCODE_CMP
: /* CMP <-> CMN */
27157 new_inst
= OPCODE_CMN
;
27162 new_inst
= OPCODE_CMP
;
27166 /* Now Inverted ops. */
27167 case OPCODE_MOV
: /* MOV <-> MVN */
27168 new_inst
= OPCODE_MVN
;
27173 new_inst
= OPCODE_MOV
;
27177 case OPCODE_AND
: /* AND <-> BIC */
27178 new_inst
= OPCODE_BIC
;
27183 new_inst
= OPCODE_AND
;
27187 case OPCODE_ADC
: /* ADC <-> SBC */
27188 new_inst
= OPCODE_SBC
;
27193 new_inst
= OPCODE_ADC
;
27197 /* We cannot do anything. */
27202 if (value
== (unsigned) FAIL
)
27205 *instruction
&= OPCODE_MASK
;
27206 *instruction
|= new_inst
<< DATA_OP_SHIFT
;
27210 /* Like negate_data_op, but for Thumb-2. */
27212 static unsigned int
27213 thumb32_negate_data_op (offsetT
*instruction
, unsigned int value
)
27217 unsigned int negated
, inverted
;
27219 negated
= encode_thumb32_immediate (-value
);
27220 inverted
= encode_thumb32_immediate (~value
);
27222 rd
= (*instruction
>> 8) & 0xf;
27223 op
= (*instruction
>> T2_DATA_OP_SHIFT
) & 0xf;
27226 /* ADD <-> SUB. Includes CMP <-> CMN. */
27227 case T2_OPCODE_SUB
:
27228 new_inst
= T2_OPCODE_ADD
;
27232 case T2_OPCODE_ADD
:
27233 new_inst
= T2_OPCODE_SUB
;
27237 /* ORR <-> ORN. Includes MOV <-> MVN. */
27238 case T2_OPCODE_ORR
:
27239 new_inst
= T2_OPCODE_ORN
;
27243 case T2_OPCODE_ORN
:
27244 new_inst
= T2_OPCODE_ORR
;
27248 /* AND <-> BIC. TST has no inverted equivalent. */
27249 case T2_OPCODE_AND
:
27250 new_inst
= T2_OPCODE_BIC
;
27257 case T2_OPCODE_BIC
:
27258 new_inst
= T2_OPCODE_AND
;
27263 case T2_OPCODE_ADC
:
27264 new_inst
= T2_OPCODE_SBC
;
27268 case T2_OPCODE_SBC
:
27269 new_inst
= T2_OPCODE_ADC
;
27273 /* We cannot do anything. */
27278 if (value
== (unsigned int)FAIL
)
27281 *instruction
&= T2_OPCODE_MASK
;
27282 *instruction
|= new_inst
<< T2_DATA_OP_SHIFT
;
27286 /* Read a 32-bit thumb instruction from buf. */
27288 static unsigned long
27289 get_thumb32_insn (char * buf
)
27291 unsigned long insn
;
27292 insn
= md_chars_to_number (buf
, THUMB_SIZE
) << 16;
27293 insn
|= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27298 /* We usually want to set the low bit on the address of thumb function
27299 symbols. In particular .word foo - . should have the low bit set.
27300 Generic code tries to fold the difference of two symbols to
27301 a constant. Prevent this and force a relocation when the first symbols
27302 is a thumb function. */
27305 arm_optimize_expr (expressionS
*l
, operatorT op
, expressionS
*r
)
27307 if (op
== O_subtract
27308 && l
->X_op
== O_symbol
27309 && r
->X_op
== O_symbol
27310 && THUMB_IS_FUNC (l
->X_add_symbol
))
27312 l
->X_op
= O_subtract
;
27313 l
->X_op_symbol
= r
->X_add_symbol
;
27314 l
->X_add_number
-= r
->X_add_number
;
27318 /* Process as normal. */
27322 /* Encode Thumb2 unconditional branches and calls. The encoding
27323 for the 2 are identical for the immediate values. */
27326 encode_thumb2_b_bl_offset (char * buf
, offsetT value
)
27328 #define T2I1I2MASK ((1 << 13) | (1 << 11))
27331 addressT S
, I1
, I2
, lo
, hi
;
27333 S
= (value
>> 24) & 0x01;
27334 I1
= (value
>> 23) & 0x01;
27335 I2
= (value
>> 22) & 0x01;
27336 hi
= (value
>> 12) & 0x3ff;
27337 lo
= (value
>> 1) & 0x7ff;
27338 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27339 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
27340 newval
|= (S
<< 10) | hi
;
27341 newval2
&= ~T2I1I2MASK
;
27342 newval2
|= (((I1
^ S
) << 13) | ((I2
^ S
) << 11) | lo
) ^ T2I1I2MASK
;
27343 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27344 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
27348 md_apply_fix (fixS
* fixP
,
27352 offsetT value
= * valP
;
27354 unsigned int newimm
;
27355 unsigned long temp
;
27357 char * buf
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
27359 gas_assert (fixP
->fx_r_type
<= BFD_RELOC_UNUSED
);
27361 /* Note whether this will delete the relocation. */
27363 if (fixP
->fx_addsy
== 0 && !fixP
->fx_pcrel
)
27366 /* On a 64-bit host, silently truncate 'value' to 32 bits for
27367 consistency with the behaviour on 32-bit hosts. Remember value
27369 value
&= 0xffffffff;
27370 value
^= 0x80000000;
27371 value
-= 0x80000000;
27374 fixP
->fx_addnumber
= value
;
27376 /* Same treatment for fixP->fx_offset. */
27377 fixP
->fx_offset
&= 0xffffffff;
27378 fixP
->fx_offset
^= 0x80000000;
27379 fixP
->fx_offset
-= 0x80000000;
27381 switch (fixP
->fx_r_type
)
27383 case BFD_RELOC_NONE
:
27384 /* This will need to go in the object file. */
27388 case BFD_RELOC_ARM_IMMEDIATE
:
27389 /* We claim that this fixup has been processed here,
27390 even if in fact we generate an error because we do
27391 not have a reloc for it, so tc_gen_reloc will reject it. */
27394 if (fixP
->fx_addsy
)
27396 const char *msg
= 0;
27398 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27399 msg
= _("undefined symbol %s used as an immediate value");
27400 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27401 msg
= _("symbol %s is in a different section");
27402 else if (S_IS_WEAK (fixP
->fx_addsy
))
27403 msg
= _("symbol %s is weak and may be overridden later");
27407 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27408 msg
, S_GET_NAME (fixP
->fx_addsy
));
27413 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27415 /* If the offset is negative, we should use encoding A2 for ADR. */
27416 if ((temp
& 0xfff0000) == 0x28f0000 && value
< 0)
27417 newimm
= negate_data_op (&temp
, value
);
27420 newimm
= encode_arm_immediate (value
);
27422 /* If the instruction will fail, see if we can fix things up by
27423 changing the opcode. */
27424 if (newimm
== (unsigned int) FAIL
)
27425 newimm
= negate_data_op (&temp
, value
);
27426 /* MOV accepts both ARM modified immediate (A1 encoding) and
27427 UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
27428 When disassembling, MOV is preferred when there is no encoding
27430 if (newimm
== (unsigned int) FAIL
27431 && ((temp
>> DATA_OP_SHIFT
) & 0xf) == OPCODE_MOV
27432 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)
27433 && !((temp
>> SBIT_SHIFT
) & 0x1)
27434 && value
>= 0 && value
<= 0xffff)
27436 /* Clear bits[23:20] to change encoding from A1 to A2. */
27437 temp
&= 0xff0fffff;
27438 /* Encoding high 4bits imm. Code below will encode the remaining
27440 temp
|= (value
& 0x0000f000) << 4;
27441 newimm
= value
& 0x00000fff;
27445 if (newimm
== (unsigned int) FAIL
)
27447 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27448 _("invalid constant (%lx) after fixup"),
27449 (unsigned long) value
);
27453 newimm
|= (temp
& 0xfffff000);
27454 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27457 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
27459 unsigned int highpart
= 0;
27460 unsigned int newinsn
= 0xe1a00000; /* nop. */
27462 if (fixP
->fx_addsy
)
27464 const char *msg
= 0;
27466 if (! S_IS_DEFINED (fixP
->fx_addsy
))
27467 msg
= _("undefined symbol %s used as an immediate value");
27468 else if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
)
27469 msg
= _("symbol %s is in a different section");
27470 else if (S_IS_WEAK (fixP
->fx_addsy
))
27471 msg
= _("symbol %s is weak and may be overridden later");
27475 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27476 msg
, S_GET_NAME (fixP
->fx_addsy
));
27481 newimm
= encode_arm_immediate (value
);
27482 temp
= md_chars_to_number (buf
, INSN_SIZE
);
27484 /* If the instruction will fail, see if we can fix things up by
27485 changing the opcode. */
27486 if (newimm
== (unsigned int) FAIL
27487 && (newimm
= negate_data_op (& temp
, value
)) == (unsigned int) FAIL
)
27489 /* No ? OK - try using two ADD instructions to generate
27491 newimm
= validate_immediate_twopart (value
, & highpart
);
27493 /* Yes - then make sure that the second instruction is
27495 if (newimm
!= (unsigned int) FAIL
)
27497 /* Still No ? Try using a negated value. */
27498 else if ((newimm
= validate_immediate_twopart (- value
, & highpart
)) != (unsigned int) FAIL
)
27499 temp
= newinsn
= (temp
& OPCODE_MASK
) | OPCODE_SUB
<< DATA_OP_SHIFT
;
27500 /* Otherwise - give up. */
27503 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27504 _("unable to compute ADRL instructions for PC offset of 0x%lx"),
27509 /* Replace the first operand in the 2nd instruction (which
27510 is the PC) with the destination register. We have
27511 already added in the PC in the first instruction and we
27512 do not want to do it again. */
27513 newinsn
&= ~ 0xf0000;
27514 newinsn
|= ((newinsn
& 0x0f000) << 4);
27517 newimm
|= (temp
& 0xfffff000);
27518 md_number_to_chars (buf
, (valueT
) newimm
, INSN_SIZE
);
27520 highpart
|= (newinsn
& 0xfffff000);
27521 md_number_to_chars (buf
+ INSN_SIZE
, (valueT
) highpart
, INSN_SIZE
);
27525 case BFD_RELOC_ARM_OFFSET_IMM
:
27526 if (!fixP
->fx_done
&& seg
->use_rela_p
)
27528 /* Fall through. */
27530 case BFD_RELOC_ARM_LITERAL
:
27536 if (validate_offset_imm (value
, 0) == FAIL
)
27538 if (fixP
->fx_r_type
== BFD_RELOC_ARM_LITERAL
)
27539 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27540 _("invalid literal constant: pool needs to be closer"));
27542 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27543 _("bad immediate value for offset (%ld)"),
27548 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27550 newval
&= 0xfffff000;
27553 newval
&= 0xff7ff000;
27554 newval
|= value
| (sign
? INDEX_UP
: 0);
27556 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27559 case BFD_RELOC_ARM_OFFSET_IMM8
:
27560 case BFD_RELOC_ARM_HWLITERAL
:
27566 if (validate_offset_imm (value
, 1) == FAIL
)
27568 if (fixP
->fx_r_type
== BFD_RELOC_ARM_HWLITERAL
)
27569 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27570 _("invalid literal constant: pool needs to be closer"));
27572 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27573 _("bad immediate value for 8-bit offset (%ld)"),
27578 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27580 newval
&= 0xfffff0f0;
27583 newval
&= 0xff7ff0f0;
27584 newval
|= ((value
>> 4) << 8) | (value
& 0xf) | (sign
? INDEX_UP
: 0);
27586 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27589 case BFD_RELOC_ARM_T32_OFFSET_U8
:
27590 if (value
< 0 || value
> 1020 || value
% 4 != 0)
27591 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27592 _("bad immediate value for offset (%ld)"), (long) value
);
27595 newval
= md_chars_to_number (buf
+2, THUMB_SIZE
);
27597 md_number_to_chars (buf
+2, newval
, THUMB_SIZE
);
27600 case BFD_RELOC_ARM_T32_OFFSET_IMM
:
27601 /* This is a complicated relocation used for all varieties of Thumb32
27602 load/store instruction with immediate offset:
27604 1110 100P u1WL NNNN XXXX YYYY iiii iiii - +/-(U) pre/post(P) 8-bit,
27605 *4, optional writeback(W)
27606 (doubleword load/store)
27608 1111 100S uTTL 1111 XXXX iiii iiii iiii - +/-(U) 12-bit PC-rel
27609 1111 100S 0TTL NNNN XXXX 1Pu1 iiii iiii - +/-(U) pre/post(P) 8-bit
27610 1111 100S 0TTL NNNN XXXX 1110 iiii iiii - positive 8-bit (T instruction)
27611 1111 100S 1TTL NNNN XXXX iiii iiii iiii - positive 12-bit
27612 1111 100S 0TTL NNNN XXXX 1100 iiii iiii - negative 8-bit
27614 Uppercase letters indicate bits that are already encoded at
27615 this point. Lowercase letters are our problem. For the
27616 second block of instructions, the secondary opcode nybble
27617 (bits 8..11) is present, and bit 23 is zero, even if this is
27618 a PC-relative operation. */
27619 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27621 newval
|= md_chars_to_number (buf
+THUMB_SIZE
, THUMB_SIZE
);
27623 if ((newval
& 0xf0000000) == 0xe0000000)
27625 /* Doubleword load/store: 8-bit offset, scaled by 4. */
27627 newval
|= (1 << 23);
27630 if (value
% 4 != 0)
27632 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27633 _("offset not a multiple of 4"));
27639 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27640 _("offset out of range"));
27645 else if ((newval
& 0x000f0000) == 0x000f0000)
27647 /* PC-relative, 12-bit offset. */
27649 newval
|= (1 << 23);
27654 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27655 _("offset out of range"));
27660 else if ((newval
& 0x00000100) == 0x00000100)
27662 /* Writeback: 8-bit, +/- offset. */
27664 newval
|= (1 << 9);
27669 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27670 _("offset out of range"));
27675 else if ((newval
& 0x00000f00) == 0x00000e00)
27677 /* T-instruction: positive 8-bit offset. */
27678 if (value
< 0 || value
> 0xff)
27680 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27681 _("offset out of range"));
27689 /* Positive 12-bit or negative 8-bit offset. */
27693 newval
|= (1 << 23);
27703 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27704 _("offset out of range"));
27711 md_number_to_chars (buf
, (newval
>> 16) & 0xffff, THUMB_SIZE
);
27712 md_number_to_chars (buf
+ THUMB_SIZE
, newval
& 0xffff, THUMB_SIZE
);
27715 case BFD_RELOC_ARM_SHIFT_IMM
:
27716 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27717 if (((unsigned long) value
) > 32
27719 && (((newval
& 0x60) == 0) || (newval
& 0x60) == 0x60)))
27721 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27722 _("shift expression is too large"));
27727 /* Shifts of zero must be done as lsl. */
27729 else if (value
== 32)
27731 newval
&= 0xfffff07f;
27732 newval
|= (value
& 0x1f) << 7;
27733 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27736 case BFD_RELOC_ARM_T32_IMMEDIATE
:
27737 case BFD_RELOC_ARM_T32_ADD_IMM
:
27738 case BFD_RELOC_ARM_T32_IMM12
:
27739 case BFD_RELOC_ARM_T32_ADD_PC12
:
27740 /* We claim that this fixup has been processed here,
27741 even if in fact we generate an error because we do
27742 not have a reloc for it, so tc_gen_reloc will reject it. */
27746 && ! S_IS_DEFINED (fixP
->fx_addsy
))
27748 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27749 _("undefined symbol %s used as an immediate value"),
27750 S_GET_NAME (fixP
->fx_addsy
));
27754 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27756 newval
|= md_chars_to_number (buf
+2, THUMB_SIZE
);
27759 if ((fixP
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
27760 /* ARMv8-M Baseline MOV will reach here, but it doesn't support
27761 Thumb2 modified immediate encoding (T2). */
27762 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
))
27763 || fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27765 newimm
= encode_thumb32_immediate (value
);
27766 if (newimm
== (unsigned int) FAIL
)
27767 newimm
= thumb32_negate_data_op (&newval
, value
);
27769 if (newimm
== (unsigned int) FAIL
)
27771 if (fixP
->fx_r_type
!= BFD_RELOC_ARM_T32_IMMEDIATE
)
27773 /* Turn add/sum into addw/subw. */
27774 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
)
27775 newval
= (newval
& 0xfeffffff) | 0x02000000;
27776 /* No flat 12-bit imm encoding for addsw/subsw. */
27777 if ((newval
& 0x00100000) == 0)
27779 /* 12 bit immediate for addw/subw. */
27783 newval
^= 0x00a00000;
27786 newimm
= (unsigned int) FAIL
;
27793 /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
27794 UINT16 (T3 encoding), MOVW only accepts UINT16. When
27795 disassembling, MOV is preferred when there is no encoding
27797 if (((newval
>> T2_DATA_OP_SHIFT
) & 0xf) == T2_OPCODE_ORR
27798 /* NOTE: MOV uses the ORR opcode in Thumb 2 mode
27799 but with the Rn field [19:16] set to 1111. */
27800 && (((newval
>> 16) & 0xf) == 0xf)
27801 && ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2_v8m
)
27802 && !((newval
>> T2_SBIT_SHIFT
) & 0x1)
27803 && value
>= 0 && value
<= 0xffff)
27805 /* Toggle bit[25] to change encoding from T2 to T3. */
27807 /* Clear bits[19:16]. */
27808 newval
&= 0xfff0ffff;
27809 /* Encoding high 4bits imm. Code below will encode the
27810 remaining low 12bits. */
27811 newval
|= (value
& 0x0000f000) << 4;
27812 newimm
= value
& 0x00000fff;
27817 if (newimm
== (unsigned int)FAIL
)
27819 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27820 _("invalid constant (%lx) after fixup"),
27821 (unsigned long) value
);
27825 newval
|= (newimm
& 0x800) << 15;
27826 newval
|= (newimm
& 0x700) << 4;
27827 newval
|= (newimm
& 0x0ff);
27829 md_number_to_chars (buf
, (valueT
) ((newval
>> 16) & 0xffff), THUMB_SIZE
);
27830 md_number_to_chars (buf
+2, (valueT
) (newval
& 0xffff), THUMB_SIZE
);
27833 case BFD_RELOC_ARM_SMC
:
27834 if (((unsigned long) value
) > 0xf)
27835 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27836 _("invalid smc expression"));
27838 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27839 newval
|= (value
& 0xf);
27840 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27843 case BFD_RELOC_ARM_HVC
:
27844 if (((unsigned long) value
) > 0xffff)
27845 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27846 _("invalid hvc expression"));
27847 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27848 newval
|= (value
& 0xf) | ((value
& 0xfff0) << 4);
27849 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27852 case BFD_RELOC_ARM_SWI
:
27853 if (fixP
->tc_fix_data
!= 0)
27855 if (((unsigned long) value
) > 0xff)
27856 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27857 _("invalid swi expression"));
27858 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27860 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27864 if (((unsigned long) value
) > 0x00ffffff)
27865 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27866 _("invalid swi expression"));
27867 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27869 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27873 case BFD_RELOC_ARM_MULTI
:
27874 if (((unsigned long) value
) > 0xffff)
27875 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27876 _("invalid expression in load/store multiple"));
27877 newval
= value
| md_chars_to_number (buf
, INSN_SIZE
);
27878 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27882 case BFD_RELOC_ARM_PCREL_CALL
:
27884 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27886 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27887 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27888 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27889 /* Flip the bl to blx. This is a simple flip
27890 bit here because we generate PCREL_CALL for
27891 unconditional bls. */
27893 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27894 newval
= newval
| 0x10000000;
27895 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27901 goto arm_branch_common
;
27903 case BFD_RELOC_ARM_PCREL_JUMP
:
27904 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27906 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27907 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27908 && THUMB_IS_FUNC (fixP
->fx_addsy
))
27910 /* This would map to a bl<cond>, b<cond>,
27911 b<always> to a Thumb function. We
27912 need to force a relocation for this particular
27914 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27917 /* Fall through. */
27919 case BFD_RELOC_ARM_PLT32
:
27921 case BFD_RELOC_ARM_PCREL_BRANCH
:
27923 goto arm_branch_common
;
27925 case BFD_RELOC_ARM_PCREL_BLX
:
27928 if (ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
27930 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
27931 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
27932 && ARM_IS_FUNC (fixP
->fx_addsy
))
27934 /* Flip the blx to a bl and warn. */
27935 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
27936 newval
= 0xeb000000;
27937 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
27938 _("blx to '%s' an ARM ISA state function changed to bl"),
27940 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27946 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
27947 fixP
->fx_r_type
= BFD_RELOC_ARM_PCREL_CALL
;
27951 /* We are going to store value (shifted right by two) in the
27952 instruction, in a 24 bit, signed field. Bits 26 through 32 either
27953 all clear or all set and bit 0 must be clear. For B/BL bit 1 must
27956 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
27957 _("misaligned branch destination"));
27958 if ((value
& (offsetT
)0xfe000000) != (offsetT
)0
27959 && (value
& (offsetT
)0xfe000000) != (offsetT
)0xfe000000)
27960 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27962 if (fixP
->fx_done
|| !seg
->use_rela_p
)
27964 newval
= md_chars_to_number (buf
, INSN_SIZE
);
27965 newval
|= (value
>> 2) & 0x00ffffff;
27966 /* Set the H bit on BLX instructions. */
27970 newval
|= 0x01000000;
27972 newval
&= ~0x01000000;
27974 md_number_to_chars (buf
, newval
, INSN_SIZE
);
27978 case BFD_RELOC_THUMB_PCREL_BRANCH7
: /* CBZ */
27979 /* CBZ can only branch forward. */
27981 /* Attempts to use CBZ to branch to the next instruction
27982 (which, strictly speaking, are prohibited) will be turned into
27985 FIXME: It may be better to remove the instruction completely and
27986 perform relaxation. */
27989 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
27990 newval
= 0xbf00; /* NOP encoding T1 */
27991 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
27996 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
27998 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28000 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28001 newval
|= ((value
& 0x3e) << 2) | ((value
& 0x40) << 3);
28002 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28007 case BFD_RELOC_THUMB_PCREL_BRANCH9
: /* Conditional branch. */
28008 if ((value
& ~0xff) && ((value
& ~0xff) != ~0xff))
28009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28011 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28013 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28014 newval
|= (value
& 0x1ff) >> 1;
28015 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28019 case BFD_RELOC_THUMB_PCREL_BRANCH12
: /* Unconditional branch. */
28020 if ((value
& ~0x7ff) && ((value
& ~0x7ff) != ~0x7ff))
28021 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28023 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28025 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28026 newval
|= (value
& 0xfff) >> 1;
28027 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28031 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
28033 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28034 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28035 && ARM_IS_FUNC (fixP
->fx_addsy
)
28036 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28038 /* Force a relocation for a branch 20 bits wide. */
28041 if ((value
& ~0x1fffff) && ((value
& ~0x0fffff) != ~0x0fffff))
28042 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28043 _("conditional branch out of range"));
28045 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28048 addressT S
, J1
, J2
, lo
, hi
;
28050 S
= (value
& 0x00100000) >> 20;
28051 J2
= (value
& 0x00080000) >> 19;
28052 J1
= (value
& 0x00040000) >> 18;
28053 hi
= (value
& 0x0003f000) >> 12;
28054 lo
= (value
& 0x00000ffe) >> 1;
28056 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28057 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28058 newval
|= (S
<< 10) | hi
;
28059 newval2
|= (J1
<< 13) | (J2
<< 11) | lo
;
28060 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28061 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28065 case BFD_RELOC_THUMB_PCREL_BLX
:
28066 /* If there is a blx from a thumb state function to
28067 another thumb function flip this to a bl and warn
28071 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28072 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28073 && THUMB_IS_FUNC (fixP
->fx_addsy
))
28075 const char *name
= S_GET_NAME (fixP
->fx_addsy
);
28076 as_warn_where (fixP
->fx_file
, fixP
->fx_line
,
28077 _("blx to Thumb func '%s' from Thumb ISA state changed to bl"),
28079 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28080 newval
= newval
| 0x1000;
28081 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28082 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28087 goto thumb_bl_common
;
28089 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
28090 /* A bl from Thumb state ISA to an internal ARM state function
28091 is converted to a blx. */
28093 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28094 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28095 && ARM_IS_FUNC (fixP
->fx_addsy
)
28096 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
))
28098 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28099 newval
= newval
& ~0x1000;
28100 md_number_to_chars (buf
+THUMB_SIZE
, newval
, THUMB_SIZE
);
28101 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BLX
;
28107 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28108 /* For a BLX instruction, make sure that the relocation is rounded up
28109 to a word boundary. This follows the semantics of the instruction
28110 which specifies that bit 1 of the target address will come from bit
28111 1 of the base address. */
28112 value
= (value
+ 3) & ~ 3;
28115 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
28116 && fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BLX
)
28117 fixP
->fx_r_type
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
28120 if ((value
& ~0x3fffff) && ((value
& ~0x3fffff) != ~0x3fffff))
28122 if (!(ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v6t2
)))
28123 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28124 else if ((value
& ~0x1ffffff)
28125 && ((value
& ~0x1ffffff) != ~0x1ffffff))
28126 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28127 _("Thumb2 branch out of range"));
28130 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28131 encode_thumb2_b_bl_offset (buf
, value
);
28135 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
28136 if ((value
& ~0x0ffffff) && ((value
& ~0x0ffffff) != ~0x0ffffff))
28137 as_bad_where (fixP
->fx_file
, fixP
->fx_line
, BAD_RANGE
);
28139 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28140 encode_thumb2_b_bl_offset (buf
, value
);
28145 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28150 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28151 md_number_to_chars (buf
, value
, 2);
28155 case BFD_RELOC_ARM_TLS_CALL
:
28156 case BFD_RELOC_ARM_THM_TLS_CALL
:
28157 case BFD_RELOC_ARM_TLS_DESCSEQ
:
28158 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
28159 case BFD_RELOC_ARM_TLS_GOTDESC
:
28160 case BFD_RELOC_ARM_TLS_GD32
:
28161 case BFD_RELOC_ARM_TLS_LE32
:
28162 case BFD_RELOC_ARM_TLS_IE32
:
28163 case BFD_RELOC_ARM_TLS_LDM32
:
28164 case BFD_RELOC_ARM_TLS_LDO32
:
28165 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28168 /* Same handling as above, but with the arm_fdpic guard. */
28169 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
28170 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
28171 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
28174 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
28178 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28179 _("Relocation supported only in FDPIC mode"));
28183 case BFD_RELOC_ARM_GOT32
:
28184 case BFD_RELOC_ARM_GOTOFF
:
28187 case BFD_RELOC_ARM_GOT_PREL
:
28188 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28189 md_number_to_chars (buf
, value
, 4);
28192 case BFD_RELOC_ARM_TARGET2
:
28193 /* TARGET2 is not partial-inplace, so we need to write the
28194 addend here for REL targets, because it won't be written out
28195 during reloc processing later. */
28196 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28197 md_number_to_chars (buf
, fixP
->fx_offset
, 4);
28200 /* Relocations for FDPIC. */
28201 case BFD_RELOC_ARM_GOTFUNCDESC
:
28202 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
28203 case BFD_RELOC_ARM_FUNCDESC
:
28206 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28207 md_number_to_chars (buf
, 0, 4);
28211 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28212 _("Relocation supported only in FDPIC mode"));
28217 case BFD_RELOC_RVA
:
28219 case BFD_RELOC_ARM_TARGET1
:
28220 case BFD_RELOC_ARM_ROSEGREL32
:
28221 case BFD_RELOC_ARM_SBREL32
:
28222 case BFD_RELOC_32_PCREL
:
28224 case BFD_RELOC_32_SECREL
:
28226 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28228 /* For WinCE we only do this for pcrel fixups. */
28229 if (fixP
->fx_done
|| fixP
->fx_pcrel
)
28231 md_number_to_chars (buf
, value
, 4);
28235 case BFD_RELOC_ARM_PREL31
:
28236 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28238 newval
= md_chars_to_number (buf
, 4) & 0x80000000;
28239 if ((value
^ (value
>> 1)) & 0x40000000)
28241 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28242 _("rel31 relocation overflow"));
28244 newval
|= value
& 0x7fffffff;
28245 md_number_to_chars (buf
, newval
, 4);
28250 case BFD_RELOC_ARM_CP_OFF_IMM
:
28251 case BFD_RELOC_ARM_T32_CP_OFF_IMM
:
28252 case BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
:
28253 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
)
28254 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28256 newval
= get_thumb32_insn (buf
);
28257 if ((newval
& 0x0f200f00) == 0x0d000900)
28259 /* This is a fp16 vstr/vldr. The immediate offset in the mnemonic
28260 has permitted values that are multiples of 2, in the range 0
28262 if (value
< -510 || value
> 510 || (value
& 1))
28263 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28264 _("co-processor offset out of range"));
28266 else if ((newval
& 0xfe001f80) == 0xec000f80)
28268 if (value
< -511 || value
> 512 || (value
& 3))
28269 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28270 _("co-processor offset out of range"));
28272 else if (value
< -1023 || value
> 1023 || (value
& 3))
28273 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28274 _("co-processor offset out of range"));
28279 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28280 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28281 newval
= md_chars_to_number (buf
, INSN_SIZE
);
28283 newval
= get_thumb32_insn (buf
);
28286 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28287 newval
&= 0xffffff80;
28289 newval
&= 0xffffff00;
28293 if (fixP
->fx_r_type
== BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
)
28294 newval
&= 0xff7fff80;
28296 newval
&= 0xff7fff00;
28297 if ((newval
& 0x0f200f00) == 0x0d000900)
28299 /* This is a fp16 vstr/vldr.
28301 It requires the immediate offset in the instruction is shifted
28302 left by 1 to be a half-word offset.
28304 Here, left shift by 1 first, and later right shift by 2
28305 should get the right offset. */
28308 newval
|= (value
>> 2) | (sign
? INDEX_UP
: 0);
28310 if (fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
28311 || fixP
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
)
28312 md_number_to_chars (buf
, newval
, INSN_SIZE
);
28314 put_thumb32_insn (buf
, newval
);
28317 case BFD_RELOC_ARM_CP_OFF_IMM_S2
:
28318 case BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
:
28319 if (value
< -255 || value
> 255)
28320 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28321 _("co-processor offset out of range"));
28323 goto cp_off_common
;
28325 case BFD_RELOC_ARM_THUMB_OFFSET
:
28326 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28327 /* Exactly what ranges, and where the offset is inserted depends
28328 on the type of instruction, we can establish this from the
28330 switch (newval
>> 12)
28332 case 4: /* PC load. */
28333 /* Thumb PC loads are somewhat odd, bit 1 of the PC is
28334 forced to zero for these loads; md_pcrel_from has already
28335 compensated for this. */
28337 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28338 _("invalid offset, target not word aligned (0x%08lX)"),
28339 (((unsigned long) fixP
->fx_frag
->fr_address
28340 + (unsigned long) fixP
->fx_where
) & ~3)
28341 + (unsigned long) value
);
28343 if (value
& ~0x3fc)
28344 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28345 _("invalid offset, value too big (0x%08lX)"),
28348 newval
|= value
>> 2;
28351 case 9: /* SP load/store. */
28352 if (value
& ~0x3fc)
28353 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28354 _("invalid offset, value too big (0x%08lX)"),
28356 newval
|= value
>> 2;
28359 case 6: /* Word load/store. */
28361 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28362 _("invalid offset, value too big (0x%08lX)"),
28364 newval
|= value
<< 4; /* 6 - 2. */
28367 case 7: /* Byte load/store. */
28369 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28370 _("invalid offset, value too big (0x%08lX)"),
28372 newval
|= value
<< 6;
28375 case 8: /* Halfword load/store. */
28377 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28378 _("invalid offset, value too big (0x%08lX)"),
28380 newval
|= value
<< 5; /* 6 - 1. */
28384 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28385 "Unable to process relocation for thumb opcode: %lx",
28386 (unsigned long) newval
);
28389 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28392 case BFD_RELOC_ARM_THUMB_ADD
:
28393 /* This is a complicated relocation, since we use it for all of
28394 the following immediate relocations:
28398 9bit ADD/SUB SP word-aligned
28399 10bit ADD PC/SP word-aligned
28401 The type of instruction being processed is encoded in the
28408 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28410 int rd
= (newval
>> 4) & 0xf;
28411 int rs
= newval
& 0xf;
28412 int subtract
= !!(newval
& 0x8000);
28414 /* Check for HI regs, only very restricted cases allowed:
28415 Adjusting SP, and using PC or SP to get an address. */
28416 if ((rd
> 7 && (rd
!= REG_SP
|| rs
!= REG_SP
))
28417 || (rs
> 7 && rs
!= REG_SP
&& rs
!= REG_PC
))
28418 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28419 _("invalid Hi register with immediate"));
28421 /* If value is negative, choose the opposite instruction. */
28425 subtract
= !subtract
;
28427 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28428 _("immediate value out of range"));
28433 if (value
& ~0x1fc)
28434 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28435 _("invalid immediate for stack address calculation"));
28436 newval
= subtract
? T_OPCODE_SUB_ST
: T_OPCODE_ADD_ST
;
28437 newval
|= value
>> 2;
28439 else if (rs
== REG_PC
|| rs
== REG_SP
)
28441 /* PR gas/18541. If the addition is for a defined symbol
28442 within range of an ADR instruction then accept it. */
28445 && fixP
->fx_addsy
!= NULL
)
28449 if (! S_IS_DEFINED (fixP
->fx_addsy
)
28450 || S_GET_SEGMENT (fixP
->fx_addsy
) != seg
28451 || S_IS_WEAK (fixP
->fx_addsy
))
28453 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28454 _("address calculation needs a strongly defined nearby symbol"));
28458 offsetT v
= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
28460 /* Round up to the next 4-byte boundary. */
28465 v
= S_GET_VALUE (fixP
->fx_addsy
) - v
;
28469 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28470 _("symbol too far away"));
28480 if (subtract
|| value
& ~0x3fc)
28481 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28482 _("invalid immediate for address calculation (value = 0x%08lX)"),
28483 (unsigned long) (subtract
? - value
: value
));
28484 newval
= (rs
== REG_PC
? T_OPCODE_ADD_PC
: T_OPCODE_ADD_SP
);
28486 newval
|= value
>> 2;
28491 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28492 _("immediate value out of range"));
28493 newval
= subtract
? T_OPCODE_SUB_I8
: T_OPCODE_ADD_I8
;
28494 newval
|= (rd
<< 8) | value
;
28499 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28500 _("immediate value out of range"));
28501 newval
= subtract
? T_OPCODE_SUB_I3
: T_OPCODE_ADD_I3
;
28502 newval
|= rd
| (rs
<< 3) | (value
<< 6);
28505 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28508 case BFD_RELOC_ARM_THUMB_IMM
:
28509 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28510 if (value
< 0 || value
> 255)
28511 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28512 _("invalid immediate: %ld is out of range"),
28515 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28518 case BFD_RELOC_ARM_THUMB_SHIFT
:
28519 /* 5bit shift value (0..32). LSL cannot take 32. */
28520 newval
= md_chars_to_number (buf
, THUMB_SIZE
) & 0xf83f;
28521 temp
= newval
& 0xf800;
28522 if (value
< 0 || value
> 32 || (value
== 32 && temp
== T_OPCODE_LSL_I
))
28523 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28524 _("invalid shift value: %ld"), (long) value
);
28525 /* Shifts of zero must be encoded as LSL. */
28527 newval
= (newval
& 0x003f) | T_OPCODE_LSL_I
;
28528 /* Shifts of 32 are encoded as zero. */
28529 else if (value
== 32)
28531 newval
|= value
<< 6;
28532 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28535 case BFD_RELOC_VTABLE_INHERIT
:
28536 case BFD_RELOC_VTABLE_ENTRY
:
28540 case BFD_RELOC_ARM_MOVW
:
28541 case BFD_RELOC_ARM_MOVT
:
28542 case BFD_RELOC_ARM_THUMB_MOVW
:
28543 case BFD_RELOC_ARM_THUMB_MOVT
:
28544 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28546 /* REL format relocations are limited to a 16-bit addend. */
28547 if (!fixP
->fx_done
)
28549 if (value
< -0x8000 || value
> 0x7fff)
28550 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28551 _("offset out of range"));
28553 else if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
28554 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28559 if (fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
28560 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
)
28562 newval
= get_thumb32_insn (buf
);
28563 newval
&= 0xfbf08f00;
28564 newval
|= (value
& 0xf000) << 4;
28565 newval
|= (value
& 0x0800) << 15;
28566 newval
|= (value
& 0x0700) << 4;
28567 newval
|= (value
& 0x00ff);
28568 put_thumb32_insn (buf
, newval
);
28572 newval
= md_chars_to_number (buf
, 4);
28573 newval
&= 0xfff0f000;
28574 newval
|= value
& 0x0fff;
28575 newval
|= (value
& 0xf000) << 4;
28576 md_number_to_chars (buf
, newval
, 4);
28581 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
28582 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
28583 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
28584 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
28585 gas_assert (!fixP
->fx_done
);
28588 bfd_boolean is_mov
;
28589 bfd_vma encoded_addend
= value
;
28591 /* Check that addend can be encoded in instruction. */
28592 if (!seg
->use_rela_p
&& (value
< 0 || value
> 255))
28593 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28594 _("the offset 0x%08lX is not representable"),
28595 (unsigned long) encoded_addend
);
28597 /* Extract the instruction. */
28598 insn
= md_chars_to_number (buf
, THUMB_SIZE
);
28599 is_mov
= (insn
& 0xf800) == 0x2000;
28604 if (!seg
->use_rela_p
)
28605 insn
|= encoded_addend
;
28611 /* Extract the instruction. */
28612 /* Encoding is the following
28617 /* The following conditions must be true :
28622 rd
= (insn
>> 4) & 0xf;
28624 if ((insn
& 0x8000) || (rd
!= rs
) || rd
> 7)
28625 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28626 _("Unable to process relocation for thumb opcode: %lx"),
28627 (unsigned long) insn
);
28629 /* Encode as ADD immediate8 thumb 1 code. */
28630 insn
= 0x3000 | (rd
<< 8);
28632 /* Place the encoded addend into the first 8 bits of the
28634 if (!seg
->use_rela_p
)
28635 insn
|= encoded_addend
;
28638 /* Update the instruction. */
28639 md_number_to_chars (buf
, insn
, THUMB_SIZE
);
28643 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
28644 case BFD_RELOC_ARM_ALU_PC_G0
:
28645 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
28646 case BFD_RELOC_ARM_ALU_PC_G1
:
28647 case BFD_RELOC_ARM_ALU_PC_G2
:
28648 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
28649 case BFD_RELOC_ARM_ALU_SB_G0
:
28650 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
28651 case BFD_RELOC_ARM_ALU_SB_G1
:
28652 case BFD_RELOC_ARM_ALU_SB_G2
:
28653 gas_assert (!fixP
->fx_done
);
28654 if (!seg
->use_rela_p
)
28657 bfd_vma encoded_addend
;
28658 bfd_vma addend_abs
= llabs (value
);
28660 /* Check that the absolute value of the addend can be
28661 expressed as an 8-bit constant plus a rotation. */
28662 encoded_addend
= encode_arm_immediate (addend_abs
);
28663 if (encoded_addend
== (unsigned int) FAIL
)
28664 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28665 _("the offset 0x%08lX is not representable"),
28666 (unsigned long) addend_abs
);
28668 /* Extract the instruction. */
28669 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28671 /* If the addend is positive, use an ADD instruction.
28672 Otherwise use a SUB. Take care not to destroy the S bit. */
28673 insn
&= 0xff1fffff;
28679 /* Place the encoded addend into the first 12 bits of the
28681 insn
&= 0xfffff000;
28682 insn
|= encoded_addend
;
28684 /* Update the instruction. */
28685 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28689 case BFD_RELOC_ARM_LDR_PC_G0
:
28690 case BFD_RELOC_ARM_LDR_PC_G1
:
28691 case BFD_RELOC_ARM_LDR_PC_G2
:
28692 case BFD_RELOC_ARM_LDR_SB_G0
:
28693 case BFD_RELOC_ARM_LDR_SB_G1
:
28694 case BFD_RELOC_ARM_LDR_SB_G2
:
28695 gas_assert (!fixP
->fx_done
);
28696 if (!seg
->use_rela_p
)
28699 bfd_vma addend_abs
= llabs (value
);
28701 /* Check that the absolute value of the addend can be
28702 encoded in 12 bits. */
28703 if (addend_abs
>= 0x1000)
28704 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28705 _("bad offset 0x%08lX (only 12 bits available for the magnitude)"),
28706 (unsigned long) addend_abs
);
28708 /* Extract the instruction. */
28709 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28711 /* If the addend is negative, clear bit 23 of the instruction.
28712 Otherwise set it. */
28714 insn
&= ~(1 << 23);
28718 /* Place the absolute value of the addend into the first 12 bits
28719 of the instruction. */
28720 insn
&= 0xfffff000;
28721 insn
|= addend_abs
;
28723 /* Update the instruction. */
28724 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28728 case BFD_RELOC_ARM_LDRS_PC_G0
:
28729 case BFD_RELOC_ARM_LDRS_PC_G1
:
28730 case BFD_RELOC_ARM_LDRS_PC_G2
:
28731 case BFD_RELOC_ARM_LDRS_SB_G0
:
28732 case BFD_RELOC_ARM_LDRS_SB_G1
:
28733 case BFD_RELOC_ARM_LDRS_SB_G2
:
28734 gas_assert (!fixP
->fx_done
);
28735 if (!seg
->use_rela_p
)
28738 bfd_vma addend_abs
= llabs (value
);
28740 /* Check that the absolute value of the addend can be
28741 encoded in 8 bits. */
28742 if (addend_abs
>= 0x100)
28743 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28744 _("bad offset 0x%08lX (only 8 bits available for the magnitude)"),
28745 (unsigned long) addend_abs
);
28747 /* Extract the instruction. */
28748 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28750 /* If the addend is negative, clear bit 23 of the instruction.
28751 Otherwise set it. */
28753 insn
&= ~(1 << 23);
28757 /* Place the first four bits of the absolute value of the addend
28758 into the first 4 bits of the instruction, and the remaining
28759 four into bits 8 .. 11. */
28760 insn
&= 0xfffff0f0;
28761 insn
|= (addend_abs
& 0xf) | ((addend_abs
& 0xf0) << 4);
28763 /* Update the instruction. */
28764 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28768 case BFD_RELOC_ARM_LDC_PC_G0
:
28769 case BFD_RELOC_ARM_LDC_PC_G1
:
28770 case BFD_RELOC_ARM_LDC_PC_G2
:
28771 case BFD_RELOC_ARM_LDC_SB_G0
:
28772 case BFD_RELOC_ARM_LDC_SB_G1
:
28773 case BFD_RELOC_ARM_LDC_SB_G2
:
28774 gas_assert (!fixP
->fx_done
);
28775 if (!seg
->use_rela_p
)
28778 bfd_vma addend_abs
= llabs (value
);
28780 /* Check that the absolute value of the addend is a multiple of
28781 four and, when divided by four, fits in 8 bits. */
28782 if (addend_abs
& 0x3)
28783 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28784 _("bad offset 0x%08lX (must be word-aligned)"),
28785 (unsigned long) addend_abs
);
28787 if ((addend_abs
>> 2) > 0xff)
28788 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28789 _("bad offset 0x%08lX (must be an 8-bit number of words)"),
28790 (unsigned long) addend_abs
);
28792 /* Extract the instruction. */
28793 insn
= md_chars_to_number (buf
, INSN_SIZE
);
28795 /* If the addend is negative, clear bit 23 of the instruction.
28796 Otherwise set it. */
28798 insn
&= ~(1 << 23);
28802 /* Place the addend (divided by four) into the first eight
28803 bits of the instruction. */
28804 insn
&= 0xfffffff0;
28805 insn
|= addend_abs
>> 2;
28807 /* Update the instruction. */
28808 md_number_to_chars (buf
, insn
, INSN_SIZE
);
28812 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
28814 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28815 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28816 && ARM_IS_FUNC (fixP
->fx_addsy
)
28817 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28819 /* Force a relocation for a branch 5 bits wide. */
28822 if (v8_1_branch_value_check (value
, 5, FALSE
) == FAIL
)
28823 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28826 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28828 addressT boff
= value
>> 1;
28830 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28831 newval
|= (boff
<< 7);
28832 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28836 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
28838 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28839 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28840 && ARM_IS_FUNC (fixP
->fx_addsy
)
28841 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28845 if ((value
& ~0x7f) && ((value
& ~0x3f) != ~0x3f))
28846 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28847 _("branch out of range"));
28849 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28851 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28853 addressT boff
= ((newval
& 0x0780) >> 7) << 1;
28854 addressT diff
= value
- boff
;
28858 newval
|= 1 << 1; /* T bit. */
28860 else if (diff
!= 2)
28862 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28863 _("out of range label-relative fixup value"));
28865 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28869 case BFD_RELOC_ARM_THUMB_BF17
:
28871 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28872 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28873 && ARM_IS_FUNC (fixP
->fx_addsy
)
28874 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28876 /* Force a relocation for a branch 17 bits wide. */
28880 if (v8_1_branch_value_check (value
, 17, TRUE
) == FAIL
)
28881 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28884 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28887 addressT immA
, immB
, immC
;
28889 immA
= (value
& 0x0001f000) >> 12;
28890 immB
= (value
& 0x00000ffc) >> 2;
28891 immC
= (value
& 0x00000002) >> 1;
28893 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28894 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28896 newval2
|= (immC
<< 11) | (immB
<< 1);
28897 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28898 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28902 case BFD_RELOC_ARM_THUMB_BF19
:
28904 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28905 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28906 && ARM_IS_FUNC (fixP
->fx_addsy
)
28907 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28909 /* Force a relocation for a branch 19 bits wide. */
28913 if (v8_1_branch_value_check (value
, 19, TRUE
) == FAIL
)
28914 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28917 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28920 addressT immA
, immB
, immC
;
28922 immA
= (value
& 0x0007f000) >> 12;
28923 immB
= (value
& 0x00000ffc) >> 2;
28924 immC
= (value
& 0x00000002) >> 1;
28926 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28927 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28929 newval2
|= (immC
<< 11) | (immB
<< 1);
28930 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28931 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28935 case BFD_RELOC_ARM_THUMB_BF13
:
28937 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28938 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28939 && ARM_IS_FUNC (fixP
->fx_addsy
)
28940 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28942 /* Force a relocation for a branch 13 bits wide. */
28946 if (v8_1_branch_value_check (value
, 13, TRUE
) == FAIL
)
28947 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28950 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28953 addressT immA
, immB
, immC
;
28955 immA
= (value
& 0x00001000) >> 12;
28956 immB
= (value
& 0x00000ffc) >> 2;
28957 immC
= (value
& 0x00000002) >> 1;
28959 newval
= md_chars_to_number (buf
, THUMB_SIZE
);
28960 newval2
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28962 newval2
|= (immC
<< 11) | (immB
<< 1);
28963 md_number_to_chars (buf
, newval
, THUMB_SIZE
);
28964 md_number_to_chars (buf
+ THUMB_SIZE
, newval2
, THUMB_SIZE
);
28968 case BFD_RELOC_ARM_THUMB_LOOP12
:
28970 && (S_GET_SEGMENT (fixP
->fx_addsy
) == seg
)
28971 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
)
28972 && ARM_IS_FUNC (fixP
->fx_addsy
)
28973 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v8_1m_main
))
28975 /* Force a relocation for a branch 12 bits wide. */
28979 bfd_vma insn
= get_thumb32_insn (buf
);
28980 /* le lr, <label>, le <label> or letp lr, <label> */
28981 if (((insn
& 0xffffffff) == 0xf00fc001)
28982 || ((insn
& 0xffffffff) == 0xf02fc001)
28983 || ((insn
& 0xffffffff) == 0xf01fc001))
28986 if (v8_1_branch_value_check (value
, 12, FALSE
) == FAIL
)
28987 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
28989 if (fixP
->fx_done
|| !seg
->use_rela_p
)
28991 addressT imml
, immh
;
28993 immh
= (value
& 0x00000ffc) >> 2;
28994 imml
= (value
& 0x00000002) >> 1;
28996 newval
= md_chars_to_number (buf
+ THUMB_SIZE
, THUMB_SIZE
);
28997 newval
|= (imml
<< 11) | (immh
<< 1);
28998 md_number_to_chars (buf
+ THUMB_SIZE
, newval
, THUMB_SIZE
);
29002 case BFD_RELOC_ARM_V4BX
:
29003 /* This will need to go in the object file. */
29007 case BFD_RELOC_UNUSED
:
29009 as_bad_where (fixP
->fx_file
, fixP
->fx_line
,
29010 _("bad relocation fixup type (%d)"), fixP
->fx_r_type
);
29014 /* Translate internal representation of relocation info to BFD target
29018 tc_gen_reloc (asection
*section
, fixS
*fixp
)
29021 bfd_reloc_code_real_type code
;
29023 reloc
= XNEW (arelent
);
29025 reloc
->sym_ptr_ptr
= XNEW (asymbol
*);
29026 *reloc
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
29027 reloc
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
29029 if (fixp
->fx_pcrel
)
29031 if (section
->use_rela_p
)
29032 fixp
->fx_offset
-= md_pcrel_from_section (fixp
, section
);
29034 fixp
->fx_offset
= reloc
->address
;
29036 reloc
->addend
= fixp
->fx_offset
;
29038 switch (fixp
->fx_r_type
)
29041 if (fixp
->fx_pcrel
)
29043 code
= BFD_RELOC_8_PCREL
;
29046 /* Fall through. */
29049 if (fixp
->fx_pcrel
)
29051 code
= BFD_RELOC_16_PCREL
;
29054 /* Fall through. */
29057 if (fixp
->fx_pcrel
)
29059 code
= BFD_RELOC_32_PCREL
;
29062 /* Fall through. */
29064 case BFD_RELOC_ARM_MOVW
:
29065 if (fixp
->fx_pcrel
)
29067 code
= BFD_RELOC_ARM_MOVW_PCREL
;
29070 /* Fall through. */
29072 case BFD_RELOC_ARM_MOVT
:
29073 if (fixp
->fx_pcrel
)
29075 code
= BFD_RELOC_ARM_MOVT_PCREL
;
29078 /* Fall through. */
29080 case BFD_RELOC_ARM_THUMB_MOVW
:
29081 if (fixp
->fx_pcrel
)
29083 code
= BFD_RELOC_ARM_THUMB_MOVW_PCREL
;
29086 /* Fall through. */
29088 case BFD_RELOC_ARM_THUMB_MOVT
:
29089 if (fixp
->fx_pcrel
)
29091 code
= BFD_RELOC_ARM_THUMB_MOVT_PCREL
;
29094 /* Fall through. */
29096 case BFD_RELOC_NONE
:
29097 case BFD_RELOC_ARM_PCREL_BRANCH
:
29098 case BFD_RELOC_ARM_PCREL_BLX
:
29099 case BFD_RELOC_RVA
:
29100 case BFD_RELOC_THUMB_PCREL_BRANCH7
:
29101 case BFD_RELOC_THUMB_PCREL_BRANCH9
:
29102 case BFD_RELOC_THUMB_PCREL_BRANCH12
:
29103 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29104 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29105 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29106 case BFD_RELOC_VTABLE_ENTRY
:
29107 case BFD_RELOC_VTABLE_INHERIT
:
29109 case BFD_RELOC_32_SECREL
:
29111 code
= fixp
->fx_r_type
;
29114 case BFD_RELOC_THUMB_PCREL_BLX
:
29116 if (EF_ARM_EABI_VERSION (meabi_flags
) >= EF_ARM_EABI_VER4
)
29117 code
= BFD_RELOC_THUMB_PCREL_BRANCH23
;
29120 code
= BFD_RELOC_THUMB_PCREL_BLX
;
29123 case BFD_RELOC_ARM_LITERAL
:
29124 case BFD_RELOC_ARM_HWLITERAL
:
29125 /* If this is called then the a literal has
29126 been referenced across a section boundary. */
29127 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29128 _("literal referenced across section boundary"));
29132 case BFD_RELOC_ARM_TLS_CALL
:
29133 case BFD_RELOC_ARM_THM_TLS_CALL
:
29134 case BFD_RELOC_ARM_TLS_DESCSEQ
:
29135 case BFD_RELOC_ARM_THM_TLS_DESCSEQ
:
29136 case BFD_RELOC_ARM_GOT32
:
29137 case BFD_RELOC_ARM_GOTOFF
:
29138 case BFD_RELOC_ARM_GOT_PREL
:
29139 case BFD_RELOC_ARM_PLT32
:
29140 case BFD_RELOC_ARM_TARGET1
:
29141 case BFD_RELOC_ARM_ROSEGREL32
:
29142 case BFD_RELOC_ARM_SBREL32
:
29143 case BFD_RELOC_ARM_PREL31
:
29144 case BFD_RELOC_ARM_TARGET2
:
29145 case BFD_RELOC_ARM_TLS_LDO32
:
29146 case BFD_RELOC_ARM_PCREL_CALL
:
29147 case BFD_RELOC_ARM_PCREL_JUMP
:
29148 case BFD_RELOC_ARM_ALU_PC_G0_NC
:
29149 case BFD_RELOC_ARM_ALU_PC_G0
:
29150 case BFD_RELOC_ARM_ALU_PC_G1_NC
:
29151 case BFD_RELOC_ARM_ALU_PC_G1
:
29152 case BFD_RELOC_ARM_ALU_PC_G2
:
29153 case BFD_RELOC_ARM_LDR_PC_G0
:
29154 case BFD_RELOC_ARM_LDR_PC_G1
:
29155 case BFD_RELOC_ARM_LDR_PC_G2
:
29156 case BFD_RELOC_ARM_LDRS_PC_G0
:
29157 case BFD_RELOC_ARM_LDRS_PC_G1
:
29158 case BFD_RELOC_ARM_LDRS_PC_G2
:
29159 case BFD_RELOC_ARM_LDC_PC_G0
:
29160 case BFD_RELOC_ARM_LDC_PC_G1
:
29161 case BFD_RELOC_ARM_LDC_PC_G2
:
29162 case BFD_RELOC_ARM_ALU_SB_G0_NC
:
29163 case BFD_RELOC_ARM_ALU_SB_G0
:
29164 case BFD_RELOC_ARM_ALU_SB_G1_NC
:
29165 case BFD_RELOC_ARM_ALU_SB_G1
:
29166 case BFD_RELOC_ARM_ALU_SB_G2
:
29167 case BFD_RELOC_ARM_LDR_SB_G0
:
29168 case BFD_RELOC_ARM_LDR_SB_G1
:
29169 case BFD_RELOC_ARM_LDR_SB_G2
:
29170 case BFD_RELOC_ARM_LDRS_SB_G0
:
29171 case BFD_RELOC_ARM_LDRS_SB_G1
:
29172 case BFD_RELOC_ARM_LDRS_SB_G2
:
29173 case BFD_RELOC_ARM_LDC_SB_G0
:
29174 case BFD_RELOC_ARM_LDC_SB_G1
:
29175 case BFD_RELOC_ARM_LDC_SB_G2
:
29176 case BFD_RELOC_ARM_V4BX
:
29177 case BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
:
29178 case BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
:
29179 case BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
:
29180 case BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
:
29181 case BFD_RELOC_ARM_GOTFUNCDESC
:
29182 case BFD_RELOC_ARM_GOTOFFFUNCDESC
:
29183 case BFD_RELOC_ARM_FUNCDESC
:
29184 case BFD_RELOC_ARM_THUMB_BF17
:
29185 case BFD_RELOC_ARM_THUMB_BF19
:
29186 case BFD_RELOC_ARM_THUMB_BF13
:
29187 code
= fixp
->fx_r_type
;
29190 case BFD_RELOC_ARM_TLS_GOTDESC
:
29191 case BFD_RELOC_ARM_TLS_GD32
:
29192 case BFD_RELOC_ARM_TLS_GD32_FDPIC
:
29193 case BFD_RELOC_ARM_TLS_LE32
:
29194 case BFD_RELOC_ARM_TLS_IE32
:
29195 case BFD_RELOC_ARM_TLS_IE32_FDPIC
:
29196 case BFD_RELOC_ARM_TLS_LDM32
:
29197 case BFD_RELOC_ARM_TLS_LDM32_FDPIC
:
29198 /* BFD will include the symbol's address in the addend.
29199 But we don't want that, so subtract it out again here. */
29200 if (!S_IS_COMMON (fixp
->fx_addsy
))
29201 reloc
->addend
-= (*reloc
->sym_ptr_ptr
)->value
;
29202 code
= fixp
->fx_r_type
;
29206 case BFD_RELOC_ARM_IMMEDIATE
:
29207 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29208 _("internal relocation (type: IMMEDIATE) not fixed up"));
29211 case BFD_RELOC_ARM_ADRL_IMMEDIATE
:
29212 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29213 _("ADRL used for a symbol not defined in the same file"));
29216 case BFD_RELOC_THUMB_PCREL_BRANCH5
:
29217 case BFD_RELOC_THUMB_PCREL_BFCSEL
:
29218 case BFD_RELOC_ARM_THUMB_LOOP12
:
29219 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29220 _("%s used for a symbol not defined in the same file"),
29221 bfd_get_reloc_code_name (fixp
->fx_r_type
));
29224 case BFD_RELOC_ARM_OFFSET_IMM
:
29225 if (section
->use_rela_p
)
29227 code
= fixp
->fx_r_type
;
29231 if (fixp
->fx_addsy
!= NULL
29232 && !S_IS_DEFINED (fixp
->fx_addsy
)
29233 && S_IS_LOCAL (fixp
->fx_addsy
))
29235 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29236 _("undefined local label `%s'"),
29237 S_GET_NAME (fixp
->fx_addsy
));
29241 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29242 _("internal_relocation (type: OFFSET_IMM) not fixed up"));
29249 switch (fixp
->fx_r_type
)
29251 case BFD_RELOC_NONE
: type
= "NONE"; break;
29252 case BFD_RELOC_ARM_OFFSET_IMM8
: type
= "OFFSET_IMM8"; break;
29253 case BFD_RELOC_ARM_SHIFT_IMM
: type
= "SHIFT_IMM"; break;
29254 case BFD_RELOC_ARM_SMC
: type
= "SMC"; break;
29255 case BFD_RELOC_ARM_SWI
: type
= "SWI"; break;
29256 case BFD_RELOC_ARM_MULTI
: type
= "MULTI"; break;
29257 case BFD_RELOC_ARM_CP_OFF_IMM
: type
= "CP_OFF_IMM"; break;
29258 case BFD_RELOC_ARM_T32_OFFSET_IMM
: type
= "T32_OFFSET_IMM"; break;
29259 case BFD_RELOC_ARM_T32_CP_OFF_IMM
: type
= "T32_CP_OFF_IMM"; break;
29260 case BFD_RELOC_ARM_THUMB_ADD
: type
= "THUMB_ADD"; break;
29261 case BFD_RELOC_ARM_THUMB_SHIFT
: type
= "THUMB_SHIFT"; break;
29262 case BFD_RELOC_ARM_THUMB_IMM
: type
= "THUMB_IMM"; break;
29263 case BFD_RELOC_ARM_THUMB_OFFSET
: type
= "THUMB_OFFSET"; break;
29264 default: type
= _("<unknown>"); break;
29266 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29267 _("cannot represent %s relocation in this object file format"),
29274 if ((code
== BFD_RELOC_32_PCREL
|| code
== BFD_RELOC_32
)
29276 && fixp
->fx_addsy
== GOT_symbol
)
29278 code
= BFD_RELOC_ARM_GOTPC
;
29279 reloc
->addend
= fixp
->fx_offset
= reloc
->address
;
29283 reloc
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
29285 if (reloc
->howto
== NULL
)
29287 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
29288 _("cannot represent %s relocation in this object file format"),
29289 bfd_get_reloc_code_name (code
));
29293 /* HACK: Since arm ELF uses Rel instead of Rela, encode the
29294 vtable entry to be used in the relocation's section offset. */
29295 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29296 reloc
->address
= fixp
->fx_offset
;
29301 /* This fix_new is called by cons via TC_CONS_FIX_NEW. */
29304 cons_fix_new_arm (fragS
* frag
,
29308 bfd_reloc_code_real_type reloc
)
29313 FIXME: @@ Should look at CPU word size. */
29317 reloc
= BFD_RELOC_8
;
29320 reloc
= BFD_RELOC_16
;
29324 reloc
= BFD_RELOC_32
;
29327 reloc
= BFD_RELOC_64
;
29332 if (exp
->X_op
== O_secrel
)
29334 exp
->X_op
= O_symbol
;
29335 reloc
= BFD_RELOC_32_SECREL
;
29339 fix_new_exp (frag
, where
, size
, exp
, pcrel
, reloc
);
29342 #if defined (OBJ_COFF)
29344 arm_validate_fix (fixS
* fixP
)
29346 /* If the destination of the branch is a defined symbol which does not have
29347 the THUMB_FUNC attribute, then we must be calling a function which has
29348 the (interfacearm) attribute. We look for the Thumb entry point to that
29349 function and change the branch to refer to that function instead. */
29350 if (fixP
->fx_r_type
== BFD_RELOC_THUMB_PCREL_BRANCH23
29351 && fixP
->fx_addsy
!= NULL
29352 && S_IS_DEFINED (fixP
->fx_addsy
)
29353 && ! THUMB_IS_FUNC (fixP
->fx_addsy
))
29355 fixP
->fx_addsy
= find_real_start (fixP
->fx_addsy
);
29362 arm_force_relocation (struct fix
* fixp
)
29364 #if defined (OBJ_COFF) && defined (TE_PE)
29365 if (fixp
->fx_r_type
== BFD_RELOC_RVA
)
29369 /* In case we have a call or a branch to a function in ARM ISA mode from
29370 a thumb function or vice-versa force the relocation. These relocations
29371 are cleared off for some cores that might have blx and simple transformations
29375 switch (fixp
->fx_r_type
)
29377 case BFD_RELOC_ARM_PCREL_JUMP
:
29378 case BFD_RELOC_ARM_PCREL_CALL
:
29379 case BFD_RELOC_THUMB_PCREL_BLX
:
29380 if (THUMB_IS_FUNC (fixp
->fx_addsy
))
29384 case BFD_RELOC_ARM_PCREL_BLX
:
29385 case BFD_RELOC_THUMB_PCREL_BRANCH25
:
29386 case BFD_RELOC_THUMB_PCREL_BRANCH20
:
29387 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
29388 if (ARM_IS_FUNC (fixp
->fx_addsy
))
29397 /* Resolve these relocations even if the symbol is extern or weak.
29398 Technically this is probably wrong due to symbol preemption.
29399 In practice these relocations do not have enough range to be useful
29400 at dynamic link time, and some code (e.g. in the Linux kernel)
29401 expects these references to be resolved. */
29402 if (fixp
->fx_r_type
== BFD_RELOC_ARM_IMMEDIATE
29403 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM
29404 || fixp
->fx_r_type
== BFD_RELOC_ARM_OFFSET_IMM8
29405 || fixp
->fx_r_type
== BFD_RELOC_ARM_ADRL_IMMEDIATE
29406 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM
29407 || fixp
->fx_r_type
== BFD_RELOC_ARM_CP_OFF_IMM_S2
29408 || fixp
->fx_r_type
== BFD_RELOC_ARM_THUMB_OFFSET
29409 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_IMM
29410 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMMEDIATE
29411 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_IMM12
29412 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_OFFSET_IMM
29413 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_ADD_PC12
29414 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM
29415 || fixp
->fx_r_type
== BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
)
29418 /* Always leave these relocations for the linker. */
29419 if ((fixp
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29420 && fixp
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29421 || fixp
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29424 /* Always generate relocations against function symbols. */
29425 if (fixp
->fx_r_type
== BFD_RELOC_32
29427 && (symbol_get_bfdsym (fixp
->fx_addsy
)->flags
& BSF_FUNCTION
))
29430 return generic_force_reloc (fixp
);
29433 #if defined (OBJ_ELF) || defined (OBJ_COFF)
29434 /* Relocations against function names must be left unadjusted,
29435 so that the linker can use this information to generate interworking
29436 stubs. The MIPS version of this function
29437 also prevents relocations that are mips-16 specific, but I do not
29438 know why it does this.
29441 There is one other problem that ought to be addressed here, but
29442 which currently is not: Taking the address of a label (rather
29443 than a function) and then later jumping to that address. Such
29444 addresses also ought to have their bottom bit set (assuming that
29445 they reside in Thumb code), but at the moment they will not. */
29448 arm_fix_adjustable (fixS
* fixP
)
29450 if (fixP
->fx_addsy
== NULL
)
29453 /* Preserve relocations against symbols with function type. */
29454 if (symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_FUNCTION
)
29457 if (THUMB_IS_FUNC (fixP
->fx_addsy
)
29458 && fixP
->fx_subsy
== NULL
)
29461 /* We need the symbol name for the VTABLE entries. */
29462 if ( fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
29463 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
29466 /* Don't allow symbols to be discarded on GOT related relocs. */
29467 if (fixP
->fx_r_type
== BFD_RELOC_ARM_PLT32
29468 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOT32
29469 || fixP
->fx_r_type
== BFD_RELOC_ARM_GOTOFF
29470 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32
29471 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GD32_FDPIC
29472 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LE32
29473 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32
29474 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_IE32_FDPIC
29475 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32
29476 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDM32_FDPIC
29477 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_LDO32
29478 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_GOTDESC
29479 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_CALL
29480 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_CALL
29481 || fixP
->fx_r_type
== BFD_RELOC_ARM_TLS_DESCSEQ
29482 || fixP
->fx_r_type
== BFD_RELOC_ARM_THM_TLS_DESCSEQ
29483 || fixP
->fx_r_type
== BFD_RELOC_ARM_TARGET2
)
29486 /* Similarly for group relocations. */
29487 if ((fixP
->fx_r_type
>= BFD_RELOC_ARM_ALU_PC_G0_NC
29488 && fixP
->fx_r_type
<= BFD_RELOC_ARM_LDC_SB_G2
)
29489 || fixP
->fx_r_type
== BFD_RELOC_ARM_LDR_PC_G0
)
29492 /* MOVW/MOVT REL relocations have limited offsets, so keep the symbols. */
29493 if (fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW
29494 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT
29495 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVW_PCREL
29496 || fixP
->fx_r_type
== BFD_RELOC_ARM_MOVT_PCREL
29497 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW
29498 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT
29499 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVW_PCREL
29500 || fixP
->fx_r_type
== BFD_RELOC_ARM_THUMB_MOVT_PCREL
)
29503 /* BFD_RELOC_ARM_THUMB_ALU_ABS_Gx_NC relocations have VERY limited
29504 offsets, so keep these symbols. */
29505 if (fixP
->fx_r_type
>= BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
29506 && fixP
->fx_r_type
<= BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
)
29511 #endif /* defined (OBJ_ELF) || defined (OBJ_COFF) */
29515 elf32_arm_target_format (void)
29518 return (target_big_endian
29519 ? "elf32-bigarm-symbian"
29520 : "elf32-littlearm-symbian");
29521 #elif defined (TE_VXWORKS)
29522 return (target_big_endian
29523 ? "elf32-bigarm-vxworks"
29524 : "elf32-littlearm-vxworks");
29525 #elif defined (TE_NACL)
29526 return (target_big_endian
29527 ? "elf32-bigarm-nacl"
29528 : "elf32-littlearm-nacl");
29532 if (target_big_endian
)
29533 return "elf32-bigarm-fdpic";
29535 return "elf32-littlearm-fdpic";
29539 if (target_big_endian
)
29540 return "elf32-bigarm";
29542 return "elf32-littlearm";
29548 armelf_frob_symbol (symbolS
* symp
,
29551 elf_frob_symbol (symp
, puntp
);
29555 /* MD interface: Finalization. */
29560 literal_pool
* pool
;
29562 /* Ensure that all the predication blocks are properly closed. */
29563 check_pred_blocks_finished ();
29565 for (pool
= list_of_pools
; pool
; pool
= pool
->next
)
29567 /* Put it at the end of the relevant section. */
29568 subseg_set (pool
->section
, pool
->sub_section
);
29570 arm_elf_change_section ();
29577 /* Remove any excess mapping symbols generated for alignment frags in
29578 SEC. We may have created a mapping symbol before a zero byte
29579 alignment; remove it if there's a mapping symbol after the
29582 check_mapping_symbols (bfd
*abfd ATTRIBUTE_UNUSED
, asection
*sec
,
29583 void *dummy ATTRIBUTE_UNUSED
)
29585 segment_info_type
*seginfo
= seg_info (sec
);
29588 if (seginfo
== NULL
|| seginfo
->frchainP
== NULL
)
29591 for (fragp
= seginfo
->frchainP
->frch_root
;
29593 fragp
= fragp
->fr_next
)
29595 symbolS
*sym
= fragp
->tc_frag_data
.last_map
;
29596 fragS
*next
= fragp
->fr_next
;
29598 /* Variable-sized frags have been converted to fixed size by
29599 this point. But if this was variable-sized to start with,
29600 there will be a fixed-size frag after it. So don't handle
29602 if (sym
== NULL
|| next
== NULL
)
29605 if (S_GET_VALUE (sym
) < next
->fr_address
)
29606 /* Not at the end of this frag. */
29608 know (S_GET_VALUE (sym
) == next
->fr_address
);
29612 if (next
->tc_frag_data
.first_map
!= NULL
)
29614 /* Next frag starts with a mapping symbol. Discard this
29616 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29620 if (next
->fr_next
== NULL
)
29622 /* This mapping symbol is at the end of the section. Discard
29624 know (next
->fr_fix
== 0 && next
->fr_var
== 0);
29625 symbol_remove (sym
, &symbol_rootP
, &symbol_lastP
);
29629 /* As long as we have empty frags without any mapping symbols,
29631 /* If the next frag is non-empty and does not start with a
29632 mapping symbol, then this mapping symbol is required. */
29633 if (next
->fr_address
!= next
->fr_next
->fr_address
)
29636 next
= next
->fr_next
;
29638 while (next
!= NULL
);
29643 /* Adjust the symbol table. This marks Thumb symbols as distinct from
29647 arm_adjust_symtab (void)
29652 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29654 if (ARM_IS_THUMB (sym
))
29656 if (THUMB_IS_FUNC (sym
))
29658 /* Mark the symbol as a Thumb function. */
29659 if ( S_GET_STORAGE_CLASS (sym
) == C_STAT
29660 || S_GET_STORAGE_CLASS (sym
) == C_LABEL
) /* This can happen! */
29661 S_SET_STORAGE_CLASS (sym
, C_THUMBSTATFUNC
);
29663 else if (S_GET_STORAGE_CLASS (sym
) == C_EXT
)
29664 S_SET_STORAGE_CLASS (sym
, C_THUMBEXTFUNC
);
29666 as_bad (_("%s: unexpected function type: %d"),
29667 S_GET_NAME (sym
), S_GET_STORAGE_CLASS (sym
));
29669 else switch (S_GET_STORAGE_CLASS (sym
))
29672 S_SET_STORAGE_CLASS (sym
, C_THUMBEXT
);
29675 S_SET_STORAGE_CLASS (sym
, C_THUMBSTAT
);
29678 S_SET_STORAGE_CLASS (sym
, C_THUMBLABEL
);
29686 if (ARM_IS_INTERWORK (sym
))
29687 coffsymbol (symbol_get_bfdsym (sym
))->native
->u
.syment
.n_flags
= 0xFF;
29694 for (sym
= symbol_rootP
; sym
!= NULL
; sym
= symbol_next (sym
))
29696 if (ARM_IS_THUMB (sym
))
29698 elf_symbol_type
* elf_sym
;
29700 elf_sym
= elf_symbol (symbol_get_bfdsym (sym
));
29701 bind
= ELF_ST_BIND (elf_sym
->internal_elf_sym
.st_info
);
29703 if (! bfd_is_arm_special_symbol_name (elf_sym
->symbol
.name
,
29704 BFD_ARM_SPECIAL_SYM_TYPE_ANY
))
29706 /* If it's a .thumb_func, declare it as so,
29707 otherwise tag label as .code 16. */
29708 if (THUMB_IS_FUNC (sym
))
29709 ARM_SET_SYM_BRANCH_TYPE (elf_sym
->internal_elf_sym
.st_target_internal
,
29710 ST_BRANCH_TO_THUMB
);
29711 else if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
29712 elf_sym
->internal_elf_sym
.st_info
=
29713 ELF_ST_INFO (bind
, STT_ARM_16BIT
);
29718 /* Remove any overlapping mapping symbols generated by alignment frags. */
29719 bfd_map_over_sections (stdoutput
, check_mapping_symbols
, (char *) 0);
29720 /* Now do generic ELF adjustments. */
29721 elf_adjust_symtab ();
29725 /* MD interface: Initialization. */
29728 set_constant_flonums (void)
29732 for (i
= 0; i
< NUM_FLOAT_VALS
; i
++)
29733 if (atof_ieee ((char *) fp_const
[i
], 'x', fp_values
[i
]) == NULL
)
29737 /* Auto-select Thumb mode if it's the only available instruction set for the
29738 given architecture. */
29741 autoselect_thumb_from_cpu_variant (void)
29743 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v1
))
29744 opcode_select (16);
29753 if ( (arm_ops_hsh
= hash_new ()) == NULL
29754 || (arm_cond_hsh
= hash_new ()) == NULL
29755 || (arm_vcond_hsh
= hash_new ()) == NULL
29756 || (arm_shift_hsh
= hash_new ()) == NULL
29757 || (arm_psr_hsh
= hash_new ()) == NULL
29758 || (arm_v7m_psr_hsh
= hash_new ()) == NULL
29759 || (arm_reg_hsh
= hash_new ()) == NULL
29760 || (arm_reloc_hsh
= hash_new ()) == NULL
29761 || (arm_barrier_opt_hsh
= hash_new ()) == NULL
)
29762 as_fatal (_("virtual memory exhausted"));
29764 for (i
= 0; i
< sizeof (insns
) / sizeof (struct asm_opcode
); i
++)
29765 hash_insert (arm_ops_hsh
, insns
[i
].template_name
, (void *) (insns
+ i
));
29766 for (i
= 0; i
< sizeof (conds
) / sizeof (struct asm_cond
); i
++)
29767 hash_insert (arm_cond_hsh
, conds
[i
].template_name
, (void *) (conds
+ i
));
29768 for (i
= 0; i
< sizeof (vconds
) / sizeof (struct asm_cond
); i
++)
29769 hash_insert (arm_vcond_hsh
, vconds
[i
].template_name
, (void *) (vconds
+ i
));
29770 for (i
= 0; i
< sizeof (shift_names
) / sizeof (struct asm_shift_name
); i
++)
29771 hash_insert (arm_shift_hsh
, shift_names
[i
].name
, (void *) (shift_names
+ i
));
29772 for (i
= 0; i
< sizeof (psrs
) / sizeof (struct asm_psr
); i
++)
29773 hash_insert (arm_psr_hsh
, psrs
[i
].template_name
, (void *) (psrs
+ i
));
29774 for (i
= 0; i
< sizeof (v7m_psrs
) / sizeof (struct asm_psr
); i
++)
29775 hash_insert (arm_v7m_psr_hsh
, v7m_psrs
[i
].template_name
,
29776 (void *) (v7m_psrs
+ i
));
29777 for (i
= 0; i
< sizeof (reg_names
) / sizeof (struct reg_entry
); i
++)
29778 hash_insert (arm_reg_hsh
, reg_names
[i
].name
, (void *) (reg_names
+ i
));
29780 i
< sizeof (barrier_opt_names
) / sizeof (struct asm_barrier_opt
);
29782 hash_insert (arm_barrier_opt_hsh
, barrier_opt_names
[i
].template_name
,
29783 (void *) (barrier_opt_names
+ i
));
29785 for (i
= 0; i
< ARRAY_SIZE (reloc_names
); i
++)
29787 struct reloc_entry
* entry
= reloc_names
+ i
;
29789 if (arm_is_eabi() && entry
->reloc
== BFD_RELOC_ARM_PLT32
)
29790 /* This makes encode_branch() use the EABI versions of this relocation. */
29791 entry
->reloc
= BFD_RELOC_UNUSED
;
29793 hash_insert (arm_reloc_hsh
, entry
->name
, (void *) entry
);
29797 set_constant_flonums ();
29799 /* Set the cpu variant based on the command-line options. We prefer
29800 -mcpu= over -march= if both are set (as for GCC); and we prefer
29801 -mfpu= over any other way of setting the floating point unit.
29802 Use of legacy options with new options are faulted. */
29805 if (mcpu_cpu_opt
|| march_cpu_opt
)
29806 as_bad (_("use of old and new-style options to set CPU type"));
29808 selected_arch
= *legacy_cpu
;
29810 else if (mcpu_cpu_opt
)
29812 selected_arch
= *mcpu_cpu_opt
;
29813 selected_ext
= *mcpu_ext_opt
;
29815 else if (march_cpu_opt
)
29817 selected_arch
= *march_cpu_opt
;
29818 selected_ext
= *march_ext_opt
;
29820 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
29825 as_bad (_("use of old and new-style options to set FPU type"));
29827 selected_fpu
= *legacy_fpu
;
29830 selected_fpu
= *mfpu_opt
;
29833 #if !(defined (EABI_DEFAULT) || defined (TE_LINUX) \
29834 || defined (TE_NetBSD) || defined (TE_VXWORKS))
29835 /* Some environments specify a default FPU. If they don't, infer it
29836 from the processor. */
29838 selected_fpu
= *mcpu_fpu_opt
;
29839 else if (march_fpu_opt
)
29840 selected_fpu
= *march_fpu_opt
;
29842 selected_fpu
= fpu_default
;
29846 if (ARM_FEATURE_ZERO (selected_fpu
))
29848 if (!no_cpu_selected ())
29849 selected_fpu
= fpu_default
;
29851 selected_fpu
= fpu_arch_fpa
;
29855 if (ARM_FEATURE_ZERO (selected_arch
))
29857 selected_arch
= cpu_default
;
29858 selected_cpu
= selected_arch
;
29860 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29862 /* Autodection of feature mode: allow all features in cpu_variant but leave
29863 selected_cpu unset. It will be set in aeabi_set_public_attributes ()
29864 after all instruction have been processed and we can decide what CPU
29865 should be selected. */
29866 if (ARM_FEATURE_ZERO (selected_arch
))
29867 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
29869 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
29872 autoselect_thumb_from_cpu_variant ();
29874 arm_arch_used
= thumb_arch_used
= arm_arch_none
;
29876 #if defined OBJ_COFF || defined OBJ_ELF
29878 unsigned int flags
= 0;
29880 #if defined OBJ_ELF
29881 flags
= meabi_flags
;
29883 switch (meabi_flags
)
29885 case EF_ARM_EABI_UNKNOWN
:
29887 /* Set the flags in the private structure. */
29888 if (uses_apcs_26
) flags
|= F_APCS26
;
29889 if (support_interwork
) flags
|= F_INTERWORK
;
29890 if (uses_apcs_float
) flags
|= F_APCS_FLOAT
;
29891 if (pic_code
) flags
|= F_PIC
;
29892 if (!ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_any_hard
))
29893 flags
|= F_SOFT_FLOAT
;
29895 switch (mfloat_abi_opt
)
29897 case ARM_FLOAT_ABI_SOFT
:
29898 case ARM_FLOAT_ABI_SOFTFP
:
29899 flags
|= F_SOFT_FLOAT
;
29902 case ARM_FLOAT_ABI_HARD
:
29903 if (flags
& F_SOFT_FLOAT
)
29904 as_bad (_("hard-float conflicts with specified fpu"));
29908 /* Using pure-endian doubles (even if soft-float). */
29909 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_endian_pure
))
29910 flags
|= F_VFP_FLOAT
;
29912 #if defined OBJ_ELF
29913 if (ARM_CPU_HAS_FEATURE (cpu_variant
, fpu_arch_maverick
))
29914 flags
|= EF_ARM_MAVERICK_FLOAT
;
29917 case EF_ARM_EABI_VER4
:
29918 case EF_ARM_EABI_VER5
:
29919 /* No additional flags to set. */
29926 bfd_set_private_flags (stdoutput
, flags
);
29928 /* We have run out flags in the COFF header to encode the
29929 status of ATPCS support, so instead we create a dummy,
29930 empty, debug section called .arm.atpcs. */
29935 sec
= bfd_make_section (stdoutput
, ".arm.atpcs");
29939 bfd_set_section_flags
29940 (stdoutput
, sec
, SEC_READONLY
| SEC_DEBUGGING
/* | SEC_HAS_CONTENTS */);
29941 bfd_set_section_size (stdoutput
, sec
, 0);
29942 bfd_set_section_contents (stdoutput
, sec
, NULL
, 0, 0);
29948 /* Record the CPU type as well. */
29949 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt2
))
29950 mach
= bfd_mach_arm_iWMMXt2
;
29951 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_iwmmxt
))
29952 mach
= bfd_mach_arm_iWMMXt
;
29953 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_xscale
))
29954 mach
= bfd_mach_arm_XScale
;
29955 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_cext_maverick
))
29956 mach
= bfd_mach_arm_ep9312
;
29957 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5e
))
29958 mach
= bfd_mach_arm_5TE
;
29959 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v5
))
29961 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29962 mach
= bfd_mach_arm_5T
;
29964 mach
= bfd_mach_arm_5
;
29966 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4
))
29968 if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v4t
))
29969 mach
= bfd_mach_arm_4T
;
29971 mach
= bfd_mach_arm_4
;
29973 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3m
))
29974 mach
= bfd_mach_arm_3M
;
29975 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v3
))
29976 mach
= bfd_mach_arm_3
;
29977 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2s
))
29978 mach
= bfd_mach_arm_2a
;
29979 else if (ARM_CPU_HAS_FEATURE (cpu_variant
, arm_ext_v2
))
29980 mach
= bfd_mach_arm_2
;
29982 mach
= bfd_mach_arm_unknown
;
29984 bfd_set_arch_mach (stdoutput
, TARGET_ARCH
, mach
);
29987 /* Command line processing. */
29990 Invocation line includes a switch not recognized by the base assembler.
29991 See if it's a processor-specific option.
29993 This routine is somewhat complicated by the need for backwards
29994 compatibility (since older releases of gcc can't be changed).
29995 The new options try to make the interface as compatible as
29998 New options (supported) are:
30000 -mcpu=<cpu name> Assemble for selected processor
30001 -march=<architecture name> Assemble for selected architecture
30002 -mfpu=<fpu architecture> Assemble for selected FPU.
30003 -EB/-mbig-endian Big-endian
30004 -EL/-mlittle-endian Little-endian
30005 -k Generate PIC code
30006 -mthumb Start in Thumb mode
30007 -mthumb-interwork Code supports ARM/Thumb interworking
30009 -m[no-]warn-deprecated Warn about deprecated features
30010 -m[no-]warn-syms Warn when symbols match instructions
30012 For now we will also provide support for:
30014 -mapcs-32 32-bit Program counter
30015 -mapcs-26 26-bit Program counter
30016 -macps-float Floats passed in FP registers
30017 -mapcs-reentrant Reentrant code
30019 (sometime these will probably be replaced with -mapcs=<list of options>
30020 and -matpcs=<list of options>)
30022 The remaining options are only supported for back-wards compatibility.
30023 Cpu variants, the arm part is optional:
30024 -m[arm]1 Currently not supported.
30025 -m[arm]2, -m[arm]250 Arm 2 and Arm 250 processor
30026 -m[arm]3 Arm 3 processor
30027 -m[arm]6[xx], Arm 6 processors
30028 -m[arm]7[xx][t][[d]m] Arm 7 processors
30029 -m[arm]8[10] Arm 8 processors
30030 -m[arm]9[20][tdmi] Arm 9 processors
30031 -mstrongarm[110[0]] StrongARM processors
30032 -mxscale XScale processors
30033 -m[arm]v[2345[t[e]]] Arm architectures
30034 -mall All (except the ARM1)
30036 -mfpa10, -mfpa11 FPA10 and 11 co-processor instructions
30037 -mfpe-old (No float load/store multiples)
30038 -mvfpxd VFP Single precision
30040 -mno-fpu Disable all floating point instructions
30042 The following CPU names are recognized:
30043 arm1, arm2, arm250, arm3, arm6, arm600, arm610, arm620,
30044 arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700,
30045 arm700i, arm710 arm710t, arm720, arm720t, arm740t, arm710c,
30046 arm7100, arm7500, arm7500fe, arm7tdmi, arm8, arm810, arm9,
30047 arm920, arm920t, arm940t, arm946, arm966, arm9tdmi, arm9e,
30048 arm10t arm10e, arm1020t, arm1020e, arm10200e,
30049 strongarm, strongarm110, strongarm1100, strongarm1110, xscale.
30053 const char * md_shortopts
= "m:k";
30055 #ifdef ARM_BI_ENDIAN
30056 #define OPTION_EB (OPTION_MD_BASE + 0)
30057 #define OPTION_EL (OPTION_MD_BASE + 1)
30059 #if TARGET_BYTES_BIG_ENDIAN
30060 #define OPTION_EB (OPTION_MD_BASE + 0)
30062 #define OPTION_EL (OPTION_MD_BASE + 1)
30065 #define OPTION_FIX_V4BX (OPTION_MD_BASE + 2)
30066 #define OPTION_FDPIC (OPTION_MD_BASE + 3)
30068 struct option md_longopts
[] =
30071 {"EB", no_argument
, NULL
, OPTION_EB
},
30074 {"EL", no_argument
, NULL
, OPTION_EL
},
30076 {"fix-v4bx", no_argument
, NULL
, OPTION_FIX_V4BX
},
30078 {"fdpic", no_argument
, NULL
, OPTION_FDPIC
},
30080 {NULL
, no_argument
, NULL
, 0}
30083 size_t md_longopts_size
= sizeof (md_longopts
);
30085 struct arm_option_table
30087 const char * option
; /* Option name to match. */
30088 const char * help
; /* Help information. */
30089 int * var
; /* Variable to change. */
30090 int value
; /* What to change it to. */
30091 const char * deprecated
; /* If non-null, print this message. */
30094 struct arm_option_table arm_opts
[] =
30096 {"k", N_("generate PIC code"), &pic_code
, 1, NULL
},
30097 {"mthumb", N_("assemble Thumb code"), &thumb_mode
, 1, NULL
},
30098 {"mthumb-interwork", N_("support ARM/Thumb interworking"),
30099 &support_interwork
, 1, NULL
},
30100 {"mapcs-32", N_("code uses 32-bit program counter"), &uses_apcs_26
, 0, NULL
},
30101 {"mapcs-26", N_("code uses 26-bit program counter"), &uses_apcs_26
, 1, NULL
},
30102 {"mapcs-float", N_("floating point args are in fp regs"), &uses_apcs_float
,
30104 {"mapcs-reentrant", N_("re-entrant code"), &pic_code
, 1, NULL
},
30105 {"matpcs", N_("code is ATPCS conformant"), &atpcs
, 1, NULL
},
30106 {"mbig-endian", N_("assemble for big-endian"), &target_big_endian
, 1, NULL
},
30107 {"mlittle-endian", N_("assemble for little-endian"), &target_big_endian
, 0,
30110 /* These are recognized by the assembler, but have no affect on code. */
30111 {"mapcs-frame", N_("use frame pointer"), NULL
, 0, NULL
},
30112 {"mapcs-stack-check", N_("use stack size checking"), NULL
, 0, NULL
},
30114 {"mwarn-deprecated", NULL
, &warn_on_deprecated
, 1, NULL
},
30115 {"mno-warn-deprecated", N_("do not warn on use of deprecated feature"),
30116 &warn_on_deprecated
, 0, NULL
},
30117 {"mwarn-syms", N_("warn about symbols that match instruction names [default]"), (int *) (& flag_warn_syms
), TRUE
, NULL
},
30118 {"mno-warn-syms", N_("disable warnings about symobls that match instructions"), (int *) (& flag_warn_syms
), FALSE
, NULL
},
30119 {NULL
, NULL
, NULL
, 0, NULL
}
30122 struct arm_legacy_option_table
30124 const char * option
; /* Option name to match. */
30125 const arm_feature_set
** var
; /* Variable to change. */
30126 const arm_feature_set value
; /* What to change it to. */
30127 const char * deprecated
; /* If non-null, print this message. */
30130 const struct arm_legacy_option_table arm_legacy_opts
[] =
30132 /* DON'T add any new processors to this list -- we want the whole list
30133 to go away... Add them to the processors table instead. */
30134 {"marm1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30135 {"m1", &legacy_cpu
, ARM_ARCH_V1
, N_("use -mcpu=arm1")},
30136 {"marm2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30137 {"m2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -mcpu=arm2")},
30138 {"marm250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30139 {"m250", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm250")},
30140 {"marm3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30141 {"m3", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -mcpu=arm3")},
30142 {"marm6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30143 {"m6", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm6")},
30144 {"marm600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30145 {"m600", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm600")},
30146 {"marm610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30147 {"m610", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm610")},
30148 {"marm620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30149 {"m620", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm620")},
30150 {"marm7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30151 {"m7", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7")},
30152 {"marm70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30153 {"m70", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm70")},
30154 {"marm700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30155 {"m700", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700")},
30156 {"marm700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30157 {"m700i", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm700i")},
30158 {"marm710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30159 {"m710", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710")},
30160 {"marm710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30161 {"m710c", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm710c")},
30162 {"marm720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30163 {"m720", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm720")},
30164 {"marm7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30165 {"m7d", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7d")},
30166 {"marm7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30167 {"m7di", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7di")},
30168 {"marm7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30169 {"m7m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7m")},
30170 {"marm7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30171 {"m7dm", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dm")},
30172 {"marm7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30173 {"m7dmi", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -mcpu=arm7dmi")},
30174 {"marm7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30175 {"m7100", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7100")},
30176 {"marm7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30177 {"m7500", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500")},
30178 {"marm7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30179 {"m7500fe", &legacy_cpu
, ARM_ARCH_V3
, N_("use -mcpu=arm7500fe")},
30180 {"marm7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30181 {"m7t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30182 {"marm7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30183 {"m7tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm7tdmi")},
30184 {"marm710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30185 {"m710t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm710t")},
30186 {"marm720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30187 {"m720t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm720t")},
30188 {"marm740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30189 {"m740t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm740t")},
30190 {"marm8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30191 {"m8", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm8")},
30192 {"marm810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30193 {"m810", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=arm810")},
30194 {"marm9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30195 {"m9", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9")},
30196 {"marm9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30197 {"m9tdmi", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm9tdmi")},
30198 {"marm920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30199 {"m920", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm920")},
30200 {"marm940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30201 {"m940", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -mcpu=arm940")},
30202 {"mstrongarm", &legacy_cpu
, ARM_ARCH_V4
, N_("use -mcpu=strongarm")},
30203 {"mstrongarm110", &legacy_cpu
, ARM_ARCH_V4
,
30204 N_("use -mcpu=strongarm110")},
30205 {"mstrongarm1100", &legacy_cpu
, ARM_ARCH_V4
,
30206 N_("use -mcpu=strongarm1100")},
30207 {"mstrongarm1110", &legacy_cpu
, ARM_ARCH_V4
,
30208 N_("use -mcpu=strongarm1110")},
30209 {"mxscale", &legacy_cpu
, ARM_ARCH_XSCALE
, N_("use -mcpu=xscale")},
30210 {"miwmmxt", &legacy_cpu
, ARM_ARCH_IWMMXT
, N_("use -mcpu=iwmmxt")},
30211 {"mall", &legacy_cpu
, ARM_ANY
, N_("use -mcpu=all")},
30213 /* Architecture variants -- don't add any more to this list either. */
30214 {"mv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30215 {"marmv2", &legacy_cpu
, ARM_ARCH_V2
, N_("use -march=armv2")},
30216 {"mv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30217 {"marmv2a", &legacy_cpu
, ARM_ARCH_V2S
, N_("use -march=armv2a")},
30218 {"mv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30219 {"marmv3", &legacy_cpu
, ARM_ARCH_V3
, N_("use -march=armv3")},
30220 {"mv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30221 {"marmv3m", &legacy_cpu
, ARM_ARCH_V3M
, N_("use -march=armv3m")},
30222 {"mv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30223 {"marmv4", &legacy_cpu
, ARM_ARCH_V4
, N_("use -march=armv4")},
30224 {"mv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30225 {"marmv4t", &legacy_cpu
, ARM_ARCH_V4T
, N_("use -march=armv4t")},
30226 {"mv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30227 {"marmv5", &legacy_cpu
, ARM_ARCH_V5
, N_("use -march=armv5")},
30228 {"mv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30229 {"marmv5t", &legacy_cpu
, ARM_ARCH_V5T
, N_("use -march=armv5t")},
30230 {"mv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30231 {"marmv5e", &legacy_cpu
, ARM_ARCH_V5TE
, N_("use -march=armv5te")},
30233 /* Floating point variants -- don't add any more to this list either. */
30234 {"mfpe-old", &legacy_fpu
, FPU_ARCH_FPE
, N_("use -mfpu=fpe")},
30235 {"mfpa10", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa10")},
30236 {"mfpa11", &legacy_fpu
, FPU_ARCH_FPA
, N_("use -mfpu=fpa11")},
30237 {"mno-fpu", &legacy_fpu
, ARM_ARCH_NONE
,
30238 N_("use either -mfpu=softfpa or -mfpu=softvfp")},
30240 {NULL
, NULL
, ARM_ARCH_NONE
, NULL
}
30243 struct arm_cpu_option_table
30247 const arm_feature_set value
;
30248 const arm_feature_set ext
;
30249 /* For some CPUs we assume an FPU unless the user explicitly sets
30251 const arm_feature_set default_fpu
;
30252 /* The canonical name of the CPU, or NULL to use NAME converted to upper
30254 const char * canonical_name
;
30257 /* This list should, at a minimum, contain all the cpu names
30258 recognized by GCC. */
30259 #define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
30261 static const struct arm_cpu_option_table arm_cpus
[] =
30263 ARM_CPU_OPT ("all", NULL
, ARM_ANY
,
30266 ARM_CPU_OPT ("arm1", NULL
, ARM_ARCH_V1
,
30269 ARM_CPU_OPT ("arm2", NULL
, ARM_ARCH_V2
,
30272 ARM_CPU_OPT ("arm250", NULL
, ARM_ARCH_V2S
,
30275 ARM_CPU_OPT ("arm3", NULL
, ARM_ARCH_V2S
,
30278 ARM_CPU_OPT ("arm6", NULL
, ARM_ARCH_V3
,
30281 ARM_CPU_OPT ("arm60", NULL
, ARM_ARCH_V3
,
30284 ARM_CPU_OPT ("arm600", NULL
, ARM_ARCH_V3
,
30287 ARM_CPU_OPT ("arm610", NULL
, ARM_ARCH_V3
,
30290 ARM_CPU_OPT ("arm620", NULL
, ARM_ARCH_V3
,
30293 ARM_CPU_OPT ("arm7", NULL
, ARM_ARCH_V3
,
30296 ARM_CPU_OPT ("arm7m", NULL
, ARM_ARCH_V3M
,
30299 ARM_CPU_OPT ("arm7d", NULL
, ARM_ARCH_V3
,
30302 ARM_CPU_OPT ("arm7dm", NULL
, ARM_ARCH_V3M
,
30305 ARM_CPU_OPT ("arm7di", NULL
, ARM_ARCH_V3
,
30308 ARM_CPU_OPT ("arm7dmi", NULL
, ARM_ARCH_V3M
,
30311 ARM_CPU_OPT ("arm70", NULL
, ARM_ARCH_V3
,
30314 ARM_CPU_OPT ("arm700", NULL
, ARM_ARCH_V3
,
30317 ARM_CPU_OPT ("arm700i", NULL
, ARM_ARCH_V3
,
30320 ARM_CPU_OPT ("arm710", NULL
, ARM_ARCH_V3
,
30323 ARM_CPU_OPT ("arm710t", NULL
, ARM_ARCH_V4T
,
30326 ARM_CPU_OPT ("arm720", NULL
, ARM_ARCH_V3
,
30329 ARM_CPU_OPT ("arm720t", NULL
, ARM_ARCH_V4T
,
30332 ARM_CPU_OPT ("arm740t", NULL
, ARM_ARCH_V4T
,
30335 ARM_CPU_OPT ("arm710c", NULL
, ARM_ARCH_V3
,
30338 ARM_CPU_OPT ("arm7100", NULL
, ARM_ARCH_V3
,
30341 ARM_CPU_OPT ("arm7500", NULL
, ARM_ARCH_V3
,
30344 ARM_CPU_OPT ("arm7500fe", NULL
, ARM_ARCH_V3
,
30347 ARM_CPU_OPT ("arm7t", NULL
, ARM_ARCH_V4T
,
30350 ARM_CPU_OPT ("arm7tdmi", NULL
, ARM_ARCH_V4T
,
30353 ARM_CPU_OPT ("arm7tdmi-s", NULL
, ARM_ARCH_V4T
,
30356 ARM_CPU_OPT ("arm8", NULL
, ARM_ARCH_V4
,
30359 ARM_CPU_OPT ("arm810", NULL
, ARM_ARCH_V4
,
30362 ARM_CPU_OPT ("strongarm", NULL
, ARM_ARCH_V4
,
30365 ARM_CPU_OPT ("strongarm1", NULL
, ARM_ARCH_V4
,
30368 ARM_CPU_OPT ("strongarm110", NULL
, ARM_ARCH_V4
,
30371 ARM_CPU_OPT ("strongarm1100", NULL
, ARM_ARCH_V4
,
30374 ARM_CPU_OPT ("strongarm1110", NULL
, ARM_ARCH_V4
,
30377 ARM_CPU_OPT ("arm9", NULL
, ARM_ARCH_V4T
,
30380 ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T
,
30383 ARM_CPU_OPT ("arm920t", NULL
, ARM_ARCH_V4T
,
30386 ARM_CPU_OPT ("arm922t", NULL
, ARM_ARCH_V4T
,
30389 ARM_CPU_OPT ("arm940t", NULL
, ARM_ARCH_V4T
,
30392 ARM_CPU_OPT ("arm9tdmi", NULL
, ARM_ARCH_V4T
,
30395 ARM_CPU_OPT ("fa526", NULL
, ARM_ARCH_V4
,
30398 ARM_CPU_OPT ("fa626", NULL
, ARM_ARCH_V4
,
30402 /* For V5 or later processors we default to using VFP; but the user
30403 should really set the FPU type explicitly. */
30404 ARM_CPU_OPT ("arm9e-r0", NULL
, ARM_ARCH_V5TExP
,
30407 ARM_CPU_OPT ("arm9e", NULL
, ARM_ARCH_V5TE
,
30410 ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30413 ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ
,
30416 ARM_CPU_OPT ("arm926ej-s", NULL
, ARM_ARCH_V5TEJ
,
30419 ARM_CPU_OPT ("arm946e-r0", NULL
, ARM_ARCH_V5TExP
,
30422 ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE
,
30425 ARM_CPU_OPT ("arm946e-s", NULL
, ARM_ARCH_V5TE
,
30428 ARM_CPU_OPT ("arm966e-r0", NULL
, ARM_ARCH_V5TExP
,
30431 ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE
,
30434 ARM_CPU_OPT ("arm966e-s", NULL
, ARM_ARCH_V5TE
,
30437 ARM_CPU_OPT ("arm968e-s", NULL
, ARM_ARCH_V5TE
,
30440 ARM_CPU_OPT ("arm10t", NULL
, ARM_ARCH_V5T
,
30443 ARM_CPU_OPT ("arm10tdmi", NULL
, ARM_ARCH_V5T
,
30446 ARM_CPU_OPT ("arm10e", NULL
, ARM_ARCH_V5TE
,
30449 ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE
,
30452 ARM_CPU_OPT ("arm1020t", NULL
, ARM_ARCH_V5T
,
30455 ARM_CPU_OPT ("arm1020e", NULL
, ARM_ARCH_V5TE
,
30458 ARM_CPU_OPT ("arm1022e", NULL
, ARM_ARCH_V5TE
,
30461 ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ
,
30464 ARM_CPU_OPT ("arm1026ej-s", NULL
, ARM_ARCH_V5TEJ
,
30467 ARM_CPU_OPT ("fa606te", NULL
, ARM_ARCH_V5TE
,
30470 ARM_CPU_OPT ("fa616te", NULL
, ARM_ARCH_V5TE
,
30473 ARM_CPU_OPT ("fa626te", NULL
, ARM_ARCH_V5TE
,
30476 ARM_CPU_OPT ("fmp626", NULL
, ARM_ARCH_V5TE
,
30479 ARM_CPU_OPT ("fa726te", NULL
, ARM_ARCH_V5TE
,
30482 ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6
,
30485 ARM_CPU_OPT ("arm1136j-s", NULL
, ARM_ARCH_V6
,
30488 ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6
,
30491 ARM_CPU_OPT ("arm1136jf-s", NULL
, ARM_ARCH_V6
,
30494 ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K
,
30497 ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K
,
30500 ARM_CPU_OPT ("arm1156t2-s", NULL
, ARM_ARCH_V6T2
,
30503 ARM_CPU_OPT ("arm1156t2f-s", NULL
, ARM_ARCH_V6T2
,
30506 ARM_CPU_OPT ("arm1176jz-s", NULL
, ARM_ARCH_V6KZ
,
30509 ARM_CPU_OPT ("arm1176jzf-s", NULL
, ARM_ARCH_V6KZ
,
30512 ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A
,
30513 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30515 ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE
,
30517 FPU_ARCH_NEON_VFP_V4
),
30518 ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A
,
30519 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
30520 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30521 ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A
,
30522 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30523 ARM_FEATURE_COPROC (FPU_VFP_V3
| FPU_NEON_EXT_V1
)),
30524 ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE
,
30526 FPU_ARCH_NEON_VFP_V4
),
30527 ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE
,
30529 FPU_ARCH_NEON_VFP_V4
),
30530 ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE
,
30532 FPU_ARCH_NEON_VFP_V4
),
30533 ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A
,
30534 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30535 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30536 ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A
,
30537 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30538 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30539 ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A
,
30540 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30541 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30542 ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A
,
30543 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30544 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30545 ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A
,
30546 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30547 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30548 ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A
,
30549 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30550 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30551 ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A
,
30552 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30553 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30554 ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A
,
30555 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30556 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30557 ARM_CPU_OPT ("cortex-a76", "Cortex-A76", ARM_ARCH_V8_2A
,
30558 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30559 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30560 ARM_CPU_OPT ("ares", "Ares", ARM_ARCH_V8_2A
,
30561 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30562 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30563 ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R
,
30566 ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R
,
30568 FPU_ARCH_VFP_V3D16
),
30569 ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R
,
30570 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30572 ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R
,
30573 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30574 FPU_ARCH_VFP_V3D16
),
30575 ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R
,
30576 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
),
30577 FPU_ARCH_VFP_V3D16
),
30578 ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R
,
30579 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30580 FPU_ARCH_NEON_VFP_ARMV8
),
30581 ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN
,
30582 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30584 ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE
,
30587 ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM
,
30590 ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM
,
30593 ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M
,
30596 ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM
,
30599 ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM
,
30602 ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM
,
30605 ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A
,
30606 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30607 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30608 ARM_CPU_OPT ("neoverse-n1", "Neoverse N1", ARM_ARCH_V8_2A
,
30609 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30610 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_DOTPROD
),
30611 /* ??? XSCALE is really an architecture. */
30612 ARM_CPU_OPT ("xscale", NULL
, ARM_ARCH_XSCALE
,
30616 /* ??? iwmmxt is not a processor. */
30617 ARM_CPU_OPT ("iwmmxt", NULL
, ARM_ARCH_IWMMXT
,
30620 ARM_CPU_OPT ("iwmmxt2", NULL
, ARM_ARCH_IWMMXT2
,
30623 ARM_CPU_OPT ("i80200", NULL
, ARM_ARCH_XSCALE
,
30628 ARM_CPU_OPT ("ep9312", "ARM920T",
30629 ARM_FEATURE_LOW (ARM_AEXT_V4T
, ARM_CEXT_MAVERICK
),
30630 ARM_ARCH_NONE
, FPU_ARCH_MAVERICK
),
30632 /* Marvell processors. */
30633 ARM_CPU_OPT ("marvell-pj4", NULL
, ARM_ARCH_V7A
,
30634 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30635 FPU_ARCH_VFP_V3D16
),
30636 ARM_CPU_OPT ("marvell-whitney", NULL
, ARM_ARCH_V7A
,
30637 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
| ARM_EXT_SEC
),
30638 FPU_ARCH_NEON_VFP_V4
),
30640 /* APM X-Gene family. */
30641 ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A
,
30643 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30644 ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A
,
30645 ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30646 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
),
30648 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30652 struct arm_ext_table
30656 const arm_feature_set merge
;
30657 const arm_feature_set clear
;
30660 struct arm_arch_option_table
30664 const arm_feature_set value
;
30665 const arm_feature_set default_fpu
;
30666 const struct arm_ext_table
* ext_table
;
30669 /* Used to add support for +E and +noE extension. */
30670 #define ARM_EXT(E, M, C) { E, sizeof (E) - 1, M, C }
30671 /* Used to add support for a +E extension. */
30672 #define ARM_ADD(E, M) { E, sizeof(E) - 1, M, ARM_ARCH_NONE }
30673 /* Used to add support for a +noE extension. */
30674 #define ARM_REMOVE(E, C) { E, sizeof(E) -1, ARM_ARCH_NONE, C }
30676 #define ALL_FP ARM_FEATURE (0, ARM_EXT2_FP16_INST | ARM_EXT2_FP16_FML, \
30677 ~0 & ~FPU_ENDIAN_PURE)
30679 static const struct arm_ext_table armv5te_ext_table
[] =
30681 ARM_EXT ("fp", FPU_ARCH_VFP_V2
, ALL_FP
),
30682 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30685 static const struct arm_ext_table armv7_ext_table
[] =
30687 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30688 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30691 static const struct arm_ext_table armv7ve_ext_table
[] =
30693 ARM_EXT ("fp", FPU_ARCH_VFP_V4D16
, ALL_FP
),
30694 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
),
30695 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30696 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30697 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30698 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
), /* Alias for +fp. */
30699 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30701 ARM_EXT ("simd", FPU_ARCH_NEON_VFP_V4
,
30702 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30704 /* Aliases for +simd. */
30705 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30707 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30708 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30709 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30711 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30714 static const struct arm_ext_table armv7a_ext_table
[] =
30716 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30717 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30718 ARM_ADD ("vfpv3", FPU_ARCH_VFP_V3
),
30719 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30720 ARM_ADD ("vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
),
30721 ARM_ADD ("vfpv4-d16", FPU_ARCH_VFP_V4D16
),
30722 ARM_ADD ("vfpv4", FPU_ARCH_VFP_V4
),
30724 ARM_EXT ("simd", FPU_ARCH_VFP_V3_PLUS_NEON_V1
,
30725 ARM_FEATURE_COPROC (FPU_NEON_EXT_V1
| FPU_NEON_EXT_FMA
)),
30727 /* Aliases for +simd. */
30728 ARM_ADD ("neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30729 ARM_ADD ("neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
),
30731 ARM_ADD ("neon-fp16", FPU_ARCH_NEON_FP16
),
30732 ARM_ADD ("neon-vfpv4", FPU_ARCH_NEON_VFP_V4
),
30734 ARM_ADD ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
)),
30735 ARM_ADD ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
)),
30736 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30739 static const struct arm_ext_table armv7r_ext_table
[] =
30741 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V3xD
),
30742 ARM_ADD ("vfpv3xd", FPU_ARCH_VFP_V3xD
), /* Alias for +fp.sp. */
30743 ARM_EXT ("fp", FPU_ARCH_VFP_V3D16
, ALL_FP
),
30744 ARM_ADD ("vfpv3-d16", FPU_ARCH_VFP_V3D16
), /* Alias for +fp. */
30745 ARM_ADD ("vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
),
30746 ARM_ADD ("vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
),
30747 ARM_EXT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30748 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
)),
30749 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30752 static const struct arm_ext_table armv7em_ext_table
[] =
30754 ARM_EXT ("fp", FPU_ARCH_VFP_V4_SP_D16
, ALL_FP
),
30755 /* Alias for +fp, used to be known as fpv4-sp-d16. */
30756 ARM_ADD ("vfpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
),
30757 ARM_ADD ("fpv5", FPU_ARCH_VFP_V5_SP_D16
),
30758 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30759 ARM_ADD ("fpv5-d16", FPU_ARCH_VFP_V5D16
),
30760 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30763 static const struct arm_ext_table armv8a_ext_table
[] =
30765 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30766 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30767 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30768 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30770 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30771 should use the +simd option to turn on FP. */
30772 ARM_REMOVE ("fp", ALL_FP
),
30773 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30774 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30775 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30779 static const struct arm_ext_table armv81a_ext_table
[] =
30781 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30782 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30783 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30785 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30786 should use the +simd option to turn on FP. */
30787 ARM_REMOVE ("fp", ALL_FP
),
30788 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30789 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30790 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30793 static const struct arm_ext_table armv82a_ext_table
[] =
30795 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8_1
),
30796 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_2_FP16
),
30797 ARM_ADD ("fp16fml", FPU_ARCH_NEON_VFP_ARMV8_2_FP16FML
),
30798 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
,
30799 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30800 ARM_ADD ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30802 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30803 should use the +simd option to turn on FP. */
30804 ARM_REMOVE ("fp", ALL_FP
),
30805 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30806 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30807 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30810 static const struct arm_ext_table armv84a_ext_table
[] =
30812 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30813 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30814 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30815 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30817 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30818 should use the +simd option to turn on FP. */
30819 ARM_REMOVE ("fp", ALL_FP
),
30820 ARM_ADD ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
)),
30821 ARM_ADD ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
)),
30822 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30825 static const struct arm_ext_table armv85a_ext_table
[] =
30827 ARM_ADD ("simd", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
),
30828 ARM_ADD ("fp16", FPU_ARCH_NEON_VFP_ARMV8_4_FP16FML
),
30829 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_4
,
30830 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30832 /* Armv8-a does not allow an FP implementation without SIMD, so the user
30833 should use the +simd option to turn on FP. */
30834 ARM_REMOVE ("fp", ALL_FP
),
30835 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30838 static const struct arm_ext_table armv8m_main_ext_table
[] =
30840 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30841 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30842 ARM_EXT ("fp", FPU_ARCH_VFP_V5_SP_D16
, ALL_FP
),
30843 ARM_ADD ("fp.dp", FPU_ARCH_VFP_V5D16
),
30844 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30847 static const struct arm_ext_table armv8_1m_main_ext_table
[] =
30849 ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30850 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
)),
30852 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30853 FPU_VFP_V5_SP_D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
),
30856 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30857 FPU_VFP_V5D16
| FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30858 ARM_EXT ("mve", ARM_FEATURE_COPROC (FPU_MVE
),
30859 ARM_FEATURE_COPROC (FPU_MVE
| FPU_MVE_FP
)),
30861 ARM_FEATURE (0, ARM_EXT2_FP16_INST
,
30862 FPU_MVE
| FPU_MVE_FP
| FPU_VFP_V5_SP_D16
|
30863 FPU_VFP_EXT_FP16
| FPU_VFP_EXT_FMA
)),
30864 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30867 static const struct arm_ext_table armv8r_ext_table
[] =
30869 ARM_ADD ("crc", ARCH_CRC_ARMV8
),
30870 ARM_ADD ("simd", FPU_ARCH_NEON_VFP_ARMV8
),
30871 ARM_EXT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30872 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
)),
30873 ARM_REMOVE ("fp", ALL_FP
),
30874 ARM_ADD ("fp.sp", FPU_ARCH_VFP_V5_SP_D16
),
30875 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
}
30878 /* This list should, at a minimum, contain all the architecture names
30879 recognized by GCC. */
30880 #define ARM_ARCH_OPT(N, V, DF) { N, sizeof (N) - 1, V, DF, NULL }
30881 #define ARM_ARCH_OPT2(N, V, DF, ext) \
30882 { N, sizeof (N) - 1, V, DF, ext##_ext_table }
30884 static const struct arm_arch_option_table arm_archs
[] =
30886 ARM_ARCH_OPT ("all", ARM_ANY
, FPU_ARCH_FPA
),
30887 ARM_ARCH_OPT ("armv1", ARM_ARCH_V1
, FPU_ARCH_FPA
),
30888 ARM_ARCH_OPT ("armv2", ARM_ARCH_V2
, FPU_ARCH_FPA
),
30889 ARM_ARCH_OPT ("armv2a", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30890 ARM_ARCH_OPT ("armv2s", ARM_ARCH_V2S
, FPU_ARCH_FPA
),
30891 ARM_ARCH_OPT ("armv3", ARM_ARCH_V3
, FPU_ARCH_FPA
),
30892 ARM_ARCH_OPT ("armv3m", ARM_ARCH_V3M
, FPU_ARCH_FPA
),
30893 ARM_ARCH_OPT ("armv4", ARM_ARCH_V4
, FPU_ARCH_FPA
),
30894 ARM_ARCH_OPT ("armv4xm", ARM_ARCH_V4xM
, FPU_ARCH_FPA
),
30895 ARM_ARCH_OPT ("armv4t", ARM_ARCH_V4T
, FPU_ARCH_FPA
),
30896 ARM_ARCH_OPT ("armv4txm", ARM_ARCH_V4TxM
, FPU_ARCH_FPA
),
30897 ARM_ARCH_OPT ("armv5", ARM_ARCH_V5
, FPU_ARCH_VFP
),
30898 ARM_ARCH_OPT ("armv5t", ARM_ARCH_V5T
, FPU_ARCH_VFP
),
30899 ARM_ARCH_OPT ("armv5txm", ARM_ARCH_V5TxM
, FPU_ARCH_VFP
),
30900 ARM_ARCH_OPT2 ("armv5te", ARM_ARCH_V5TE
, FPU_ARCH_VFP
, armv5te
),
30901 ARM_ARCH_OPT2 ("armv5texp", ARM_ARCH_V5TExP
, FPU_ARCH_VFP
, armv5te
),
30902 ARM_ARCH_OPT2 ("armv5tej", ARM_ARCH_V5TEJ
, FPU_ARCH_VFP
, armv5te
),
30903 ARM_ARCH_OPT2 ("armv6", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30904 ARM_ARCH_OPT2 ("armv6j", ARM_ARCH_V6
, FPU_ARCH_VFP
, armv5te
),
30905 ARM_ARCH_OPT2 ("armv6k", ARM_ARCH_V6K
, FPU_ARCH_VFP
, armv5te
),
30906 ARM_ARCH_OPT2 ("armv6z", ARM_ARCH_V6Z
, FPU_ARCH_VFP
, armv5te
),
30907 /* The official spelling of this variant is ARMv6KZ, the name "armv6zk" is
30908 kept to preserve existing behaviour. */
30909 ARM_ARCH_OPT2 ("armv6kz", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30910 ARM_ARCH_OPT2 ("armv6zk", ARM_ARCH_V6KZ
, FPU_ARCH_VFP
, armv5te
),
30911 ARM_ARCH_OPT2 ("armv6t2", ARM_ARCH_V6T2
, FPU_ARCH_VFP
, armv5te
),
30912 ARM_ARCH_OPT2 ("armv6kt2", ARM_ARCH_V6KT2
, FPU_ARCH_VFP
, armv5te
),
30913 ARM_ARCH_OPT2 ("armv6zt2", ARM_ARCH_V6ZT2
, FPU_ARCH_VFP
, armv5te
),
30914 /* The official spelling of this variant is ARMv6KZ, the name "armv6zkt2" is
30915 kept to preserve existing behaviour. */
30916 ARM_ARCH_OPT2 ("armv6kzt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30917 ARM_ARCH_OPT2 ("armv6zkt2", ARM_ARCH_V6KZT2
, FPU_ARCH_VFP
, armv5te
),
30918 ARM_ARCH_OPT ("armv6-m", ARM_ARCH_V6M
, FPU_ARCH_VFP
),
30919 ARM_ARCH_OPT ("armv6s-m", ARM_ARCH_V6SM
, FPU_ARCH_VFP
),
30920 ARM_ARCH_OPT2 ("armv7", ARM_ARCH_V7
, FPU_ARCH_VFP
, armv7
),
30921 /* The official spelling of the ARMv7 profile variants is the dashed form.
30922 Accept the non-dashed form for compatibility with old toolchains. */
30923 ARM_ARCH_OPT2 ("armv7a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30924 ARM_ARCH_OPT2 ("armv7ve", ARM_ARCH_V7VE
, FPU_ARCH_VFP
, armv7ve
),
30925 ARM_ARCH_OPT2 ("armv7r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30926 ARM_ARCH_OPT ("armv7m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30927 ARM_ARCH_OPT2 ("armv7-a", ARM_ARCH_V7A
, FPU_ARCH_VFP
, armv7a
),
30928 ARM_ARCH_OPT2 ("armv7-r", ARM_ARCH_V7R
, FPU_ARCH_VFP
, armv7r
),
30929 ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M
, FPU_ARCH_VFP
),
30930 ARM_ARCH_OPT2 ("armv7e-m", ARM_ARCH_V7EM
, FPU_ARCH_VFP
, armv7em
),
30931 ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE
, FPU_ARCH_VFP
),
30932 ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN
, FPU_ARCH_VFP
,
30934 ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN
, FPU_ARCH_VFP
,
30936 ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A
, FPU_ARCH_VFP
, armv8a
),
30937 ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A
, FPU_ARCH_VFP
, armv81a
),
30938 ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A
, FPU_ARCH_VFP
, armv82a
),
30939 ARM_ARCH_OPT2 ("armv8.3-a", ARM_ARCH_V8_3A
, FPU_ARCH_VFP
, armv82a
),
30940 ARM_ARCH_OPT2 ("armv8-r", ARM_ARCH_V8R
, FPU_ARCH_VFP
, armv8r
),
30941 ARM_ARCH_OPT2 ("armv8.4-a", ARM_ARCH_V8_4A
, FPU_ARCH_VFP
, armv84a
),
30942 ARM_ARCH_OPT2 ("armv8.5-a", ARM_ARCH_V8_5A
, FPU_ARCH_VFP
, armv85a
),
30943 ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE
, FPU_ARCH_VFP
),
30944 ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT
, FPU_ARCH_VFP
),
30945 ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2
, FPU_ARCH_VFP
),
30946 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, NULL
}
30948 #undef ARM_ARCH_OPT
30950 /* ISA extensions in the co-processor and main instruction set space. */
30952 struct arm_option_extension_value_table
30956 const arm_feature_set merge_value
;
30957 const arm_feature_set clear_value
;
30958 /* List of architectures for which an extension is available. ARM_ARCH_NONE
30959 indicates that an extension is available for all architectures while
30960 ARM_ANY marks an empty entry. */
30961 const arm_feature_set allowed_archs
[2];
30964 /* The following table must be in alphabetical order with a NULL last entry. */
30966 #define ARM_EXT_OPT(N, M, C, AA) { N, sizeof (N) - 1, M, C, { AA, ARM_ANY } }
30967 #define ARM_EXT_OPT2(N, M, C, AA1, AA2) { N, sizeof (N) - 1, M, C, {AA1, AA2} }
30969 /* DEPRECATED: Refrain from using this table to add any new extensions, instead
30970 use the context sensitive approach using arm_ext_table's. */
30971 static const struct arm_option_extension_value_table arm_extensions
[] =
30973 ARM_EXT_OPT ("crc", ARCH_CRC_ARMV8
, ARM_FEATURE_COPROC (CRC_EXT_ARMV8
),
30974 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30975 ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
,
30976 ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8
),
30977 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30978 ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8
,
30979 ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD
),
30981 ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30982 ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP
| ARM_EXT_V6_DSP
),
30983 ARM_FEATURE_CORE (ARM_EXT_V7M
, ARM_EXT2_V8M
)),
30984 ARM_EXT_OPT ("fp", FPU_ARCH_VFP_ARMV8
, ARM_FEATURE_COPROC (FPU_VFP_ARMV8
),
30985 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
30986 ARM_EXT_OPT ("fp16", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30987 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
),
30989 ARM_EXT_OPT ("fp16fml", ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30990 | ARM_EXT2_FP16_FML
),
30991 ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST
30992 | ARM_EXT2_FP16_FML
),
30994 ARM_EXT_OPT2 ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30995 ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV
| ARM_EXT_DIV
),
30996 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
30997 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
30998 /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
30999 Thumb divide instruction. Due to this having the same name as the
31000 previous entry, this will be ignored when doing command-line parsing and
31001 only considered by build attribute selection code. */
31002 ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31003 ARM_FEATURE_CORE_LOW (ARM_EXT_DIV
),
31004 ARM_FEATURE_CORE_LOW (ARM_EXT_V7
)),
31005 ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
),
31006 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT
), ARM_ARCH_NONE
),
31007 ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
),
31008 ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2
), ARM_ARCH_NONE
),
31009 ARM_EXT_OPT ("maverick", ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
),
31010 ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK
), ARM_ARCH_NONE
),
31011 ARM_EXT_OPT2 ("mp", ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31012 ARM_FEATURE_CORE_LOW (ARM_EXT_MP
),
31013 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
),
31014 ARM_FEATURE_CORE_LOW (ARM_EXT_V7R
)),
31015 ARM_EXT_OPT ("os", ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31016 ARM_FEATURE_CORE_LOW (ARM_EXT_OS
),
31017 ARM_FEATURE_CORE_LOW (ARM_EXT_V6M
)),
31018 ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN
),
31019 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_PAN
, 0),
31020 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31021 ARM_EXT_OPT ("predres", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31022 ARM_FEATURE_CORE_HIGH (ARM_EXT2_PREDRES
),
31024 ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS
),
31025 ARM_FEATURE (ARM_EXT_V8
, ARM_EXT2_RAS
, 0),
31026 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31027 ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1
,
31028 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
| FPU_NEON_EXT_RDMA
),
31029 ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A
)),
31030 ARM_EXT_OPT ("sb", ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31031 ARM_FEATURE_CORE_HIGH (ARM_EXT2_SB
),
31033 ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31034 ARM_FEATURE_CORE_LOW (ARM_EXT_SEC
),
31035 ARM_FEATURE_CORE_LOW (ARM_EXT_V6K
),
31036 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31037 ARM_EXT_OPT ("simd", FPU_ARCH_NEON_VFP_ARMV8
,
31038 ARM_FEATURE_COPROC (FPU_NEON_ARMV8
),
31039 ARM_FEATURE_CORE_LOW (ARM_EXT_V8
)),
31040 ARM_EXT_OPT ("virt", ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
| ARM_EXT_ADIV
31042 ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT
),
31043 ARM_FEATURE_CORE_LOW (ARM_EXT_V7A
)),
31044 ARM_EXT_OPT ("xscale",ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
),
31045 ARM_FEATURE_COPROC (ARM_CEXT_XSCALE
), ARM_ARCH_NONE
),
31046 { NULL
, 0, ARM_ARCH_NONE
, ARM_ARCH_NONE
, { ARM_ARCH_NONE
, ARM_ARCH_NONE
} }
31050 /* ISA floating-point and Advanced SIMD extensions. */
31051 struct arm_option_fpu_value_table
31054 const arm_feature_set value
;
31057 /* This list should, at a minimum, contain all the fpu names
31058 recognized by GCC. */
31059 static const struct arm_option_fpu_value_table arm_fpus
[] =
31061 {"softfpa", FPU_NONE
},
31062 {"fpe", FPU_ARCH_FPE
},
31063 {"fpe2", FPU_ARCH_FPE
},
31064 {"fpe3", FPU_ARCH_FPA
}, /* Third release supports LFM/SFM. */
31065 {"fpa", FPU_ARCH_FPA
},
31066 {"fpa10", FPU_ARCH_FPA
},
31067 {"fpa11", FPU_ARCH_FPA
},
31068 {"arm7500fe", FPU_ARCH_FPA
},
31069 {"softvfp", FPU_ARCH_VFP
},
31070 {"softvfp+vfp", FPU_ARCH_VFP_V2
},
31071 {"vfp", FPU_ARCH_VFP_V2
},
31072 {"vfp9", FPU_ARCH_VFP_V2
},
31073 {"vfp3", FPU_ARCH_VFP_V3
}, /* Undocumented, use vfpv3. */
31074 {"vfp10", FPU_ARCH_VFP_V2
},
31075 {"vfp10-r0", FPU_ARCH_VFP_V1
},
31076 {"vfpxd", FPU_ARCH_VFP_V1xD
},
31077 {"vfpv2", FPU_ARCH_VFP_V2
},
31078 {"vfpv3", FPU_ARCH_VFP_V3
},
31079 {"vfpv3-fp16", FPU_ARCH_VFP_V3_FP16
},
31080 {"vfpv3-d16", FPU_ARCH_VFP_V3D16
},
31081 {"vfpv3-d16-fp16", FPU_ARCH_VFP_V3D16_FP16
},
31082 {"vfpv3xd", FPU_ARCH_VFP_V3xD
},
31083 {"vfpv3xd-fp16", FPU_ARCH_VFP_V3xD_FP16
},
31084 {"arm1020t", FPU_ARCH_VFP_V1
},
31085 {"arm1020e", FPU_ARCH_VFP_V2
},
31086 {"arm1136jfs", FPU_ARCH_VFP_V2
}, /* Undocumented, use arm1136jf-s. */
31087 {"arm1136jf-s", FPU_ARCH_VFP_V2
},
31088 {"maverick", FPU_ARCH_MAVERICK
},
31089 {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31090 {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1
},
31091 {"neon-fp16", FPU_ARCH_NEON_FP16
},
31092 {"vfpv4", FPU_ARCH_VFP_V4
},
31093 {"vfpv4-d16", FPU_ARCH_VFP_V4D16
},
31094 {"fpv4-sp-d16", FPU_ARCH_VFP_V4_SP_D16
},
31095 {"fpv5-d16", FPU_ARCH_VFP_V5D16
},
31096 {"fpv5-sp-d16", FPU_ARCH_VFP_V5_SP_D16
},
31097 {"neon-vfpv4", FPU_ARCH_NEON_VFP_V4
},
31098 {"fp-armv8", FPU_ARCH_VFP_ARMV8
},
31099 {"neon-fp-armv8", FPU_ARCH_NEON_VFP_ARMV8
},
31100 {"crypto-neon-fp-armv8",
31101 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8
},
31102 {"neon-fp-armv8.1", FPU_ARCH_NEON_VFP_ARMV8_1
},
31103 {"crypto-neon-fp-armv8.1",
31104 FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1
},
31105 {NULL
, ARM_ARCH_NONE
}
31108 struct arm_option_value_table
31114 static const struct arm_option_value_table arm_float_abis
[] =
31116 {"hard", ARM_FLOAT_ABI_HARD
},
31117 {"softfp", ARM_FLOAT_ABI_SOFTFP
},
31118 {"soft", ARM_FLOAT_ABI_SOFT
},
31123 /* We only know how to output GNU and ver 4/5 (AAELF) formats. */
31124 static const struct arm_option_value_table arm_eabis
[] =
31126 {"gnu", EF_ARM_EABI_UNKNOWN
},
31127 {"4", EF_ARM_EABI_VER4
},
31128 {"5", EF_ARM_EABI_VER5
},
31133 struct arm_long_option_table
31135 const char * option
; /* Substring to match. */
31136 const char * help
; /* Help information. */
31137 int (* func
) (const char * subopt
); /* Function to decode sub-option. */
31138 const char * deprecated
; /* If non-null, print this message. */
31142 arm_parse_extension (const char *str
, const arm_feature_set
*opt_set
,
31143 arm_feature_set
*ext_set
,
31144 const struct arm_ext_table
*ext_table
)
31146 /* We insist on extensions being specified in alphabetical order, and with
31147 extensions being added before being removed. We achieve this by having
31148 the global ARM_EXTENSIONS table in alphabetical order, and using the
31149 ADDING_VALUE variable to indicate whether we are adding an extension (1)
31150 or removing it (0) and only allowing it to change in the order
31152 const struct arm_option_extension_value_table
* opt
= NULL
;
31153 const arm_feature_set arm_any
= ARM_ANY
;
31154 int adding_value
= -1;
31156 while (str
!= NULL
&& *str
!= 0)
31163 as_bad (_("invalid architectural extension"));
31168 ext
= strchr (str
, '+');
31173 len
= strlen (str
);
31175 if (len
>= 2 && strncmp (str
, "no", 2) == 0)
31177 if (adding_value
!= 0)
31180 opt
= arm_extensions
;
31188 if (adding_value
== -1)
31191 opt
= arm_extensions
;
31193 else if (adding_value
!= 1)
31195 as_bad (_("must specify extensions to add before specifying "
31196 "those to remove"));
31203 as_bad (_("missing architectural extension"));
31207 gas_assert (adding_value
!= -1);
31208 gas_assert (opt
!= NULL
);
31210 if (ext_table
!= NULL
)
31212 const struct arm_ext_table
* ext_opt
= ext_table
;
31213 bfd_boolean found
= FALSE
;
31214 for (; ext_opt
->name
!= NULL
; ext_opt
++)
31215 if (ext_opt
->name_len
== len
31216 && strncmp (ext_opt
->name
, str
, len
) == 0)
31220 if (ARM_FEATURE_ZERO (ext_opt
->merge
))
31221 /* TODO: Option not supported. When we remove the
31222 legacy table this case should error out. */
31225 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, ext_opt
->merge
);
31229 if (ARM_FEATURE_ZERO (ext_opt
->clear
))
31230 /* TODO: Option not supported. When we remove the
31231 legacy table this case should error out. */
31233 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, ext_opt
->clear
);
31245 /* Scan over the options table trying to find an exact match. */
31246 for (; opt
->name
!= NULL
; opt
++)
31247 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31249 int i
, nb_allowed_archs
=
31250 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31251 /* Check we can apply the extension to this architecture. */
31252 for (i
= 0; i
< nb_allowed_archs
; i
++)
31255 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_any
))
31257 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *opt_set
))
31260 if (i
== nb_allowed_archs
)
31262 as_bad (_("extension does not apply to the base architecture"));
31266 /* Add or remove the extension. */
31268 ARM_MERGE_FEATURE_SETS (*ext_set
, *ext_set
, opt
->merge_value
);
31270 ARM_CLEAR_FEATURE (*ext_set
, *ext_set
, opt
->clear_value
);
31272 /* Allowing Thumb division instructions for ARMv7 in autodetection
31273 rely on this break so that duplicate extensions (extensions
31274 with the same name as a previous extension in the list) are not
31275 considered for command-line parsing. */
31279 if (opt
->name
== NULL
)
31281 /* Did we fail to find an extension because it wasn't specified in
31282 alphabetical order, or because it does not exist? */
31284 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31285 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31288 if (opt
->name
== NULL
)
31289 as_bad (_("unknown architectural extension `%s'"), str
);
31291 as_bad (_("architectural extensions must be specified in "
31292 "alphabetical order"));
31298 /* We should skip the extension we've just matched the next time
31310 arm_parse_fp16_opt (const char *str
)
31312 if (strcasecmp (str
, "ieee") == 0)
31313 fp16_format
= ARM_FP16_FORMAT_IEEE
;
31314 else if (strcasecmp (str
, "alternative") == 0)
31315 fp16_format
= ARM_FP16_FORMAT_ALTERNATIVE
;
31318 as_bad (_("unrecognised float16 format \"%s\""), str
);
31326 arm_parse_cpu (const char *str
)
31328 const struct arm_cpu_option_table
*opt
;
31329 const char *ext
= strchr (str
, '+');
31335 len
= strlen (str
);
31339 as_bad (_("missing cpu name `%s'"), str
);
31343 for (opt
= arm_cpus
; opt
->name
!= NULL
; opt
++)
31344 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31346 mcpu_cpu_opt
= &opt
->value
;
31347 if (mcpu_ext_opt
== NULL
)
31348 mcpu_ext_opt
= XNEW (arm_feature_set
);
31349 *mcpu_ext_opt
= opt
->ext
;
31350 mcpu_fpu_opt
= &opt
->default_fpu
;
31351 if (opt
->canonical_name
)
31353 gas_assert (sizeof selected_cpu_name
> strlen (opt
->canonical_name
));
31354 strcpy (selected_cpu_name
, opt
->canonical_name
);
31360 if (len
>= sizeof selected_cpu_name
)
31361 len
= (sizeof selected_cpu_name
) - 1;
31363 for (i
= 0; i
< len
; i
++)
31364 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
31365 selected_cpu_name
[i
] = 0;
31369 return arm_parse_extension (ext
, mcpu_cpu_opt
, mcpu_ext_opt
, NULL
);
31374 as_bad (_("unknown cpu `%s'"), str
);
31379 arm_parse_arch (const char *str
)
31381 const struct arm_arch_option_table
*opt
;
31382 const char *ext
= strchr (str
, '+');
31388 len
= strlen (str
);
31392 as_bad (_("missing architecture name `%s'"), str
);
31396 for (opt
= arm_archs
; opt
->name
!= NULL
; opt
++)
31397 if (opt
->name_len
== len
&& strncmp (opt
->name
, str
, len
) == 0)
31399 march_cpu_opt
= &opt
->value
;
31400 if (march_ext_opt
== NULL
)
31401 march_ext_opt
= XNEW (arm_feature_set
);
31402 *march_ext_opt
= arm_arch_none
;
31403 march_fpu_opt
= &opt
->default_fpu
;
31404 strcpy (selected_cpu_name
, opt
->name
);
31407 return arm_parse_extension (ext
, march_cpu_opt
, march_ext_opt
,
31413 as_bad (_("unknown architecture `%s'\n"), str
);
31418 arm_parse_fpu (const char * str
)
31420 const struct arm_option_fpu_value_table
* opt
;
31422 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
31423 if (streq (opt
->name
, str
))
31425 mfpu_opt
= &opt
->value
;
31429 as_bad (_("unknown floating point format `%s'\n"), str
);
31434 arm_parse_float_abi (const char * str
)
31436 const struct arm_option_value_table
* opt
;
31438 for (opt
= arm_float_abis
; opt
->name
!= NULL
; opt
++)
31439 if (streq (opt
->name
, str
))
31441 mfloat_abi_opt
= opt
->value
;
31445 as_bad (_("unknown floating point abi `%s'\n"), str
);
31451 arm_parse_eabi (const char * str
)
31453 const struct arm_option_value_table
*opt
;
31455 for (opt
= arm_eabis
; opt
->name
!= NULL
; opt
++)
31456 if (streq (opt
->name
, str
))
31458 meabi_flags
= opt
->value
;
31461 as_bad (_("unknown EABI `%s'\n"), str
);
31467 arm_parse_it_mode (const char * str
)
31469 bfd_boolean ret
= TRUE
;
31471 if (streq ("arm", str
))
31472 implicit_it_mode
= IMPLICIT_IT_MODE_ARM
;
31473 else if (streq ("thumb", str
))
31474 implicit_it_mode
= IMPLICIT_IT_MODE_THUMB
;
31475 else if (streq ("always", str
))
31476 implicit_it_mode
= IMPLICIT_IT_MODE_ALWAYS
;
31477 else if (streq ("never", str
))
31478 implicit_it_mode
= IMPLICIT_IT_MODE_NEVER
;
31481 as_bad (_("unknown implicit IT mode `%s', should be "\
31482 "arm, thumb, always, or never."), str
);
31490 arm_ccs_mode (const char * unused ATTRIBUTE_UNUSED
)
31492 codecomposer_syntax
= TRUE
;
31493 arm_comment_chars
[0] = ';';
31494 arm_line_separator_chars
[0] = 0;
31498 struct arm_long_option_table arm_long_opts
[] =
31500 {"mcpu=", N_("<cpu name>\t assemble for CPU <cpu name>"),
31501 arm_parse_cpu
, NULL
},
31502 {"march=", N_("<arch name>\t assemble for architecture <arch name>"),
31503 arm_parse_arch
, NULL
},
31504 {"mfpu=", N_("<fpu name>\t assemble for FPU architecture <fpu name>"),
31505 arm_parse_fpu
, NULL
},
31506 {"mfloat-abi=", N_("<abi>\t assemble for floating point ABI <abi>"),
31507 arm_parse_float_abi
, NULL
},
31509 {"meabi=", N_("<ver>\t\t assemble for eabi version <ver>"),
31510 arm_parse_eabi
, NULL
},
31512 {"mimplicit-it=", N_("<mode>\t controls implicit insertion of IT instructions"),
31513 arm_parse_it_mode
, NULL
},
31514 {"mccs", N_("\t\t\t TI CodeComposer Studio syntax compatibility mode"),
31515 arm_ccs_mode
, NULL
},
31517 N_("[ieee|alternative]\n\
31518 set the encoding for half precision floating point "
31519 "numbers to IEEE\n\
31520 or Arm alternative format."),
31521 arm_parse_fp16_opt
, NULL
},
31522 {NULL
, NULL
, 0, NULL
}
31526 md_parse_option (int c
, const char * arg
)
31528 struct arm_option_table
*opt
;
31529 const struct arm_legacy_option_table
*fopt
;
31530 struct arm_long_option_table
*lopt
;
31536 target_big_endian
= 1;
31542 target_big_endian
= 0;
31546 case OPTION_FIX_V4BX
:
31554 #endif /* OBJ_ELF */
31557 /* Listing option. Just ignore these, we don't support additional
31562 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31564 if (c
== opt
->option
[0]
31565 && ((arg
== NULL
&& opt
->option
[1] == 0)
31566 || streq (arg
, opt
->option
+ 1)))
31568 /* If the option is deprecated, tell the user. */
31569 if (warn_on_deprecated
&& opt
->deprecated
!= NULL
)
31570 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31571 arg
? arg
: "", _(opt
->deprecated
));
31573 if (opt
->var
!= NULL
)
31574 *opt
->var
= opt
->value
;
31580 for (fopt
= arm_legacy_opts
; fopt
->option
!= NULL
; fopt
++)
31582 if (c
== fopt
->option
[0]
31583 && ((arg
== NULL
&& fopt
->option
[1] == 0)
31584 || streq (arg
, fopt
->option
+ 1)))
31586 /* If the option is deprecated, tell the user. */
31587 if (warn_on_deprecated
&& fopt
->deprecated
!= NULL
)
31588 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
,
31589 arg
? arg
: "", _(fopt
->deprecated
));
31591 if (fopt
->var
!= NULL
)
31592 *fopt
->var
= &fopt
->value
;
31598 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31600 /* These options are expected to have an argument. */
31601 if (c
== lopt
->option
[0]
31603 && strncmp (arg
, lopt
->option
+ 1,
31604 strlen (lopt
->option
+ 1)) == 0)
31606 /* If the option is deprecated, tell the user. */
31607 if (warn_on_deprecated
&& lopt
->deprecated
!= NULL
)
31608 as_tsktsk (_("option `-%c%s' is deprecated: %s"), c
, arg
,
31609 _(lopt
->deprecated
));
31611 /* Call the sup-option parser. */
31612 return lopt
->func (arg
+ strlen (lopt
->option
) - 1);
31623 md_show_usage (FILE * fp
)
31625 struct arm_option_table
*opt
;
31626 struct arm_long_option_table
*lopt
;
31628 fprintf (fp
, _(" ARM-specific assembler options:\n"));
31630 for (opt
= arm_opts
; opt
->option
!= NULL
; opt
++)
31631 if (opt
->help
!= NULL
)
31632 fprintf (fp
, " -%-23s%s\n", opt
->option
, _(opt
->help
));
31634 for (lopt
= arm_long_opts
; lopt
->option
!= NULL
; lopt
++)
31635 if (lopt
->help
!= NULL
)
31636 fprintf (fp
, " -%s%s\n", lopt
->option
, _(lopt
->help
));
31640 -EB assemble code for a big-endian cpu\n"));
31645 -EL assemble code for a little-endian cpu\n"));
31649 --fix-v4bx Allow BX in ARMv4 code\n"));
31653 --fdpic generate an FDPIC object file\n"));
31654 #endif /* OBJ_ELF */
31662 arm_feature_set flags
;
31663 } cpu_arch_ver_table
;
31665 /* Mapping from CPU features to EABI CPU arch values. Table must be sorted
31666 chronologically for architectures, with an exception for ARMv6-M and
31667 ARMv6S-M due to legacy reasons. No new architecture should have a
31668 special case. This allows for build attribute selection results to be
31669 stable when new architectures are added. */
31670 static const cpu_arch_ver_table cpu_arch_ver
[] =
31672 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V1
},
31673 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2
},
31674 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V2S
},
31675 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3
},
31676 {TAG_CPU_ARCH_PRE_V4
, ARM_ARCH_V3M
},
31677 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4xM
},
31678 {TAG_CPU_ARCH_V4
, ARM_ARCH_V4
},
31679 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4TxM
},
31680 {TAG_CPU_ARCH_V4T
, ARM_ARCH_V4T
},
31681 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5xM
},
31682 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5
},
31683 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5TxM
},
31684 {TAG_CPU_ARCH_V5T
, ARM_ARCH_V5T
},
31685 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TExP
},
31686 {TAG_CPU_ARCH_V5TE
, ARM_ARCH_V5TE
},
31687 {TAG_CPU_ARCH_V5TEJ
, ARM_ARCH_V5TEJ
},
31688 {TAG_CPU_ARCH_V6
, ARM_ARCH_V6
},
31689 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6Z
},
31690 {TAG_CPU_ARCH_V6KZ
, ARM_ARCH_V6KZ
},
31691 {TAG_CPU_ARCH_V6K
, ARM_ARCH_V6K
},
31692 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6T2
},
31693 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KT2
},
31694 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6ZT2
},
31695 {TAG_CPU_ARCH_V6T2
, ARM_ARCH_V6KZT2
},
31697 /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
31698 always selected build attributes to match those of ARMv6-M
31699 (resp. ARMv6S-M). However, due to these architectures being a strict
31700 subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
31701 would be selected when fully respecting chronology of architectures.
31702 It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
31703 move them before ARMv7 architectures. */
31704 {TAG_CPU_ARCH_V6_M
, ARM_ARCH_V6M
},
31705 {TAG_CPU_ARCH_V6S_M
, ARM_ARCH_V6SM
},
31707 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7
},
31708 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7A
},
31709 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7R
},
31710 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7M
},
31711 {TAG_CPU_ARCH_V7
, ARM_ARCH_V7VE
},
31712 {TAG_CPU_ARCH_V7E_M
, ARM_ARCH_V7EM
},
31713 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8A
},
31714 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_1A
},
31715 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_2A
},
31716 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_3A
},
31717 {TAG_CPU_ARCH_V8M_BASE
, ARM_ARCH_V8M_BASE
},
31718 {TAG_CPU_ARCH_V8M_MAIN
, ARM_ARCH_V8M_MAIN
},
31719 {TAG_CPU_ARCH_V8R
, ARM_ARCH_V8R
},
31720 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_4A
},
31721 {TAG_CPU_ARCH_V8
, ARM_ARCH_V8_5A
},
31722 {TAG_CPU_ARCH_V8_1M_MAIN
, ARM_ARCH_V8_1M_MAIN
},
31723 {-1, ARM_ARCH_NONE
}
31726 /* Set an attribute if it has not already been set by the user. */
31729 aeabi_set_attribute_int (int tag
, int value
)
31732 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31733 || !attributes_set_explicitly
[tag
])
31734 bfd_elf_add_proc_attr_int (stdoutput
, tag
, value
);
31738 aeabi_set_attribute_string (int tag
, const char *value
)
31741 || tag
>= NUM_KNOWN_OBJ_ATTRIBUTES
31742 || !attributes_set_explicitly
[tag
])
31743 bfd_elf_add_proc_attr_string (stdoutput
, tag
, value
);
31746 /* Return whether features in the *NEEDED feature set are available via
31747 extensions for the architecture whose feature set is *ARCH_FSET. */
31750 have_ext_for_needed_feat_p (const arm_feature_set
*arch_fset
,
31751 const arm_feature_set
*needed
)
31753 int i
, nb_allowed_archs
;
31754 arm_feature_set ext_fset
;
31755 const struct arm_option_extension_value_table
*opt
;
31757 ext_fset
= arm_arch_none
;
31758 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
31760 /* Extension does not provide any feature we need. */
31761 if (!ARM_CPU_HAS_FEATURE (*needed
, opt
->merge_value
))
31765 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[0]);
31766 for (i
= 0; i
< nb_allowed_archs
; i
++)
31769 if (ARM_FEATURE_EQUAL (opt
->allowed_archs
[i
], arm_arch_any
))
31772 /* Extension is available, add it. */
31773 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], *arch_fset
))
31774 ARM_MERGE_FEATURE_SETS (ext_fset
, ext_fset
, opt
->merge_value
);
31778 /* Can we enable all features in *needed? */
31779 return ARM_FSET_CPU_SUBSET (*needed
, ext_fset
);
31782 /* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
31783 a given architecture feature set *ARCH_EXT_FSET including extension feature
31784 set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
31785 - if true, check for an exact match of the architecture modulo extensions;
31786 - otherwise, select build attribute value of the first superset
31787 architecture released so that results remains stable when new architectures
31789 For -march/-mcpu=all the build attribute value of the most featureful
31790 architecture is returned. Tag_CPU_arch_profile result is returned in
31794 get_aeabi_cpu_arch_from_fset (const arm_feature_set
*arch_ext_fset
,
31795 const arm_feature_set
*ext_fset
,
31796 char *profile
, int exact_match
)
31798 arm_feature_set arch_fset
;
31799 const cpu_arch_ver_table
*p_ver
, *p_ver_ret
= NULL
;
31801 /* Select most featureful architecture with all its extensions if building
31802 for -march=all as the feature sets used to set build attributes. */
31803 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, arm_arch_any
))
31805 /* Force revisiting of decision for each new architecture. */
31806 gas_assert (MAX_TAG_CPU_ARCH
<= TAG_CPU_ARCH_V8_1M_MAIN
);
31808 return TAG_CPU_ARCH_V8
;
31811 ARM_CLEAR_FEATURE (arch_fset
, *arch_ext_fset
, *ext_fset
);
31813 for (p_ver
= cpu_arch_ver
; p_ver
->val
!= -1; p_ver
++)
31815 arm_feature_set known_arch_fset
;
31817 ARM_CLEAR_FEATURE (known_arch_fset
, p_ver
->flags
, fpu_any
);
31820 /* Base architecture match user-specified architecture and
31821 extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
31822 if (ARM_FEATURE_EQUAL (*arch_ext_fset
, known_arch_fset
))
31827 /* Base architecture match user-specified architecture only
31828 (eg. ARMv6-M in the same case as above). Record it in case we
31829 find a match with above condition. */
31830 else if (p_ver_ret
== NULL
31831 && ARM_FEATURE_EQUAL (arch_fset
, known_arch_fset
))
31837 /* Architecture has all features wanted. */
31838 if (ARM_FSET_CPU_SUBSET (arch_fset
, known_arch_fset
))
31840 arm_feature_set added_fset
;
31842 /* Compute features added by this architecture over the one
31843 recorded in p_ver_ret. */
31844 if (p_ver_ret
!= NULL
)
31845 ARM_CLEAR_FEATURE (added_fset
, known_arch_fset
,
31847 /* First architecture that match incl. with extensions, or the
31848 only difference in features over the recorded match is
31849 features that were optional and are now mandatory. */
31850 if (p_ver_ret
== NULL
31851 || ARM_FSET_CPU_SUBSET (added_fset
, arch_fset
))
31857 else if (p_ver_ret
== NULL
)
31859 arm_feature_set needed_ext_fset
;
31861 ARM_CLEAR_FEATURE (needed_ext_fset
, arch_fset
, known_arch_fset
);
31863 /* Architecture has all features needed when using some
31864 extensions. Record it and continue searching in case there
31865 exist an architecture providing all needed features without
31866 the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
31868 if (have_ext_for_needed_feat_p (&known_arch_fset
,
31875 if (p_ver_ret
== NULL
)
31879 /* Tag_CPU_arch_profile. */
31880 if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7a
)
31881 || ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8
)
31882 || (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_atomics
)
31883 && !ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v8m_m_only
)))
31885 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_v7r
))
31887 else if (ARM_CPU_HAS_FEATURE (p_ver_ret
->flags
, arm_ext_m
))
31891 return p_ver_ret
->val
;
31894 /* Set the public EABI object attributes. */
31897 aeabi_set_public_attributes (void)
31899 char profile
= '\0';
31902 int fp16_optional
= 0;
31903 int skip_exact_match
= 0;
31904 arm_feature_set flags
, flags_arch
, flags_ext
;
31906 /* Autodetection mode, choose the architecture based the instructions
31908 if (no_cpu_selected ())
31910 ARM_MERGE_FEATURE_SETS (flags
, arm_arch_used
, thumb_arch_used
);
31912 if (ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
))
31913 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v1
);
31915 if (ARM_CPU_HAS_FEATURE (thumb_arch_used
, arm_arch_any
))
31916 ARM_MERGE_FEATURE_SETS (flags
, flags
, arm_ext_v4t
);
31918 /* Code run during relaxation relies on selected_cpu being set. */
31919 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31920 flags_ext
= arm_arch_none
;
31921 ARM_CLEAR_FEATURE (selected_arch
, flags_arch
, flags_ext
);
31922 selected_ext
= flags_ext
;
31923 selected_cpu
= flags
;
31925 /* Otherwise, choose the architecture based on the capabilities of the
31929 ARM_MERGE_FEATURE_SETS (flags_arch
, selected_arch
, selected_ext
);
31930 ARM_CLEAR_FEATURE (flags_arch
, flags_arch
, fpu_any
);
31931 flags_ext
= selected_ext
;
31932 flags
= selected_cpu
;
31934 ARM_MERGE_FEATURE_SETS (flags
, flags
, selected_fpu
);
31936 /* Allow the user to override the reported architecture. */
31937 if (!ARM_FEATURE_ZERO (selected_object_arch
))
31939 ARM_CLEAR_FEATURE (flags_arch
, selected_object_arch
, fpu_any
);
31940 flags_ext
= arm_arch_none
;
31943 skip_exact_match
= ARM_FEATURE_EQUAL (selected_cpu
, arm_arch_any
);
31945 /* When this function is run again after relaxation has happened there is no
31946 way to determine whether an architecture or CPU was specified by the user:
31947 - selected_cpu is set above for relaxation to work;
31948 - march_cpu_opt is not set if only -mcpu or .cpu is used;
31949 - mcpu_cpu_opt is set to arm_arch_any for autodetection.
31950 Therefore, if not in -march=all case we first try an exact match and fall
31951 back to autodetection. */
31952 if (!skip_exact_match
)
31953 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 1);
31955 arch
= get_aeabi_cpu_arch_from_fset (&flags_arch
, &flags_ext
, &profile
, 0);
31957 as_bad (_("no architecture contains all the instructions used\n"));
31959 /* Tag_CPU_name. */
31960 if (selected_cpu_name
[0])
31964 q
= selected_cpu_name
;
31965 if (strncmp (q
, "armv", 4) == 0)
31970 for (i
= 0; q
[i
]; i
++)
31971 q
[i
] = TOUPPER (q
[i
]);
31973 aeabi_set_attribute_string (Tag_CPU_name
, q
);
31976 /* Tag_CPU_arch. */
31977 aeabi_set_attribute_int (Tag_CPU_arch
, arch
);
31979 /* Tag_CPU_arch_profile. */
31980 if (profile
!= '\0')
31981 aeabi_set_attribute_int (Tag_CPU_arch_profile
, profile
);
31983 /* Tag_DSP_extension. */
31984 if (ARM_CPU_HAS_FEATURE (selected_ext
, arm_ext_dsp
))
31985 aeabi_set_attribute_int (Tag_DSP_extension
, 1);
31987 ARM_CLEAR_FEATURE (flags_arch
, flags
, fpu_any
);
31988 /* Tag_ARM_ISA_use. */
31989 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v1
)
31990 || ARM_FEATURE_ZERO (flags_arch
))
31991 aeabi_set_attribute_int (Tag_ARM_ISA_use
, 1);
31993 /* Tag_THUMB_ISA_use. */
31994 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v4t
)
31995 || ARM_FEATURE_ZERO (flags_arch
))
31999 if (!ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32000 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m_m_only
))
32002 else if (ARM_CPU_HAS_FEATURE (flags
, arm_arch_t2
))
32006 aeabi_set_attribute_int (Tag_THUMB_ISA_use
, thumb_isa_use
);
32009 /* Tag_VFP_arch. */
32010 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_armv8xd
))
32011 aeabi_set_attribute_int (Tag_VFP_arch
,
32012 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32014 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_fma
))
32015 aeabi_set_attribute_int (Tag_VFP_arch
,
32016 ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
)
32018 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_d32
))
32021 aeabi_set_attribute_int (Tag_VFP_arch
, 3);
32023 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v3xd
))
32025 aeabi_set_attribute_int (Tag_VFP_arch
, 4);
32028 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v2
))
32029 aeabi_set_attribute_int (Tag_VFP_arch
, 2);
32030 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
)
32031 || ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
))
32032 aeabi_set_attribute_int (Tag_VFP_arch
, 1);
32034 /* Tag_ABI_HardFP_use. */
32035 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1xd
)
32036 && !ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_ext_v1
))
32037 aeabi_set_attribute_int (Tag_ABI_HardFP_use
, 1);
32039 /* Tag_WMMX_arch. */
32040 if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt2
))
32041 aeabi_set_attribute_int (Tag_WMMX_arch
, 2);
32042 else if (ARM_CPU_HAS_FEATURE (flags
, arm_cext_iwmmxt
))
32043 aeabi_set_attribute_int (Tag_WMMX_arch
, 1);
32045 /* Tag_Advanced_SIMD_arch (formerly Tag_NEON_arch). */
32046 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v8_1
))
32047 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 4);
32048 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_armv8
))
32049 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 3);
32050 else if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_v1
))
32052 if (ARM_CPU_HAS_FEATURE (flags
, fpu_neon_ext_fma
))
32054 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 2);
32058 aeabi_set_attribute_int (Tag_Advanced_SIMD_arch
, 1);
32063 if (ARM_CPU_HAS_FEATURE (flags
, mve_fp_ext
))
32064 aeabi_set_attribute_int (Tag_MVE_arch
, 2);
32065 else if (ARM_CPU_HAS_FEATURE (flags
, mve_ext
))
32066 aeabi_set_attribute_int (Tag_MVE_arch
, 1);
32068 /* Tag_VFP_HP_extension (formerly Tag_NEON_FP16_arch). */
32069 if (ARM_CPU_HAS_FEATURE (flags
, fpu_vfp_fp16
) && fp16_optional
)
32070 aeabi_set_attribute_int (Tag_VFP_HP_extension
, 1);
32074 We set Tag_DIV_use to two when integer divide instructions have been used
32075 in ARM state, or when Thumb integer divide instructions have been used,
32076 but we have no architecture profile set, nor have we any ARM instructions.
32078 For ARMv8-A and ARMv8-M we set the tag to 0 as integer divide is implied
32079 by the base architecture.
32081 For new architectures we will have to check these tests. */
32082 gas_assert (arch
<= TAG_CPU_ARCH_V8_1M_MAIN
);
32083 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8
)
32084 || ARM_CPU_HAS_FEATURE (flags
, arm_ext_v8m
))
32085 aeabi_set_attribute_int (Tag_DIV_use
, 0);
32086 else if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_adiv
)
32087 || (profile
== '\0'
32088 && ARM_CPU_HAS_FEATURE (flags
, arm_ext_div
)
32089 && !ARM_CPU_HAS_FEATURE (arm_arch_used
, arm_arch_any
)))
32090 aeabi_set_attribute_int (Tag_DIV_use
, 2);
32092 /* Tag_MP_extension_use. */
32093 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_mp
))
32094 aeabi_set_attribute_int (Tag_MPextension_use
, 1);
32096 /* Tag Virtualization_use. */
32097 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_sec
))
32099 if (ARM_CPU_HAS_FEATURE (flags
, arm_ext_virt
))
32102 aeabi_set_attribute_int (Tag_Virtualization_use
, virt_sec
);
32104 if (fp16_format
!= ARM_FP16_FORMAT_DEFAULT
)
32105 aeabi_set_attribute_int (Tag_ABI_FP_16bit_format
, fp16_format
);
32108 /* Post relaxation hook. Recompute ARM attributes now that relaxation is
32109 finished and free extension feature bits which will not be used anymore. */
32112 arm_md_post_relax (void)
32114 aeabi_set_public_attributes ();
32115 XDELETE (mcpu_ext_opt
);
32116 mcpu_ext_opt
= NULL
;
32117 XDELETE (march_ext_opt
);
32118 march_ext_opt
= NULL
;
32121 /* Add the default contents for the .ARM.attributes section. */
32126 if (EF_ARM_EABI_VERSION (meabi_flags
) < EF_ARM_EABI_VER4
)
32129 aeabi_set_public_attributes ();
32131 #endif /* OBJ_ELF */
32133 /* Parse a .cpu directive. */
32136 s_arm_cpu (int ignored ATTRIBUTE_UNUSED
)
32138 const struct arm_cpu_option_table
*opt
;
32142 name
= input_line_pointer
;
32143 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32144 input_line_pointer
++;
32145 saved_char
= *input_line_pointer
;
32146 *input_line_pointer
= 0;
32148 /* Skip the first "all" entry. */
32149 for (opt
= arm_cpus
+ 1; opt
->name
!= NULL
; opt
++)
32150 if (streq (opt
->name
, name
))
32152 selected_arch
= opt
->value
;
32153 selected_ext
= opt
->ext
;
32154 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32155 if (opt
->canonical_name
)
32156 strcpy (selected_cpu_name
, opt
->canonical_name
);
32160 for (i
= 0; opt
->name
[i
]; i
++)
32161 selected_cpu_name
[i
] = TOUPPER (opt
->name
[i
]);
32163 selected_cpu_name
[i
] = 0;
32165 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32167 *input_line_pointer
= saved_char
;
32168 demand_empty_rest_of_line ();
32171 as_bad (_("unknown cpu `%s'"), name
);
32172 *input_line_pointer
= saved_char
;
32173 ignore_rest_of_line ();
32176 /* Parse a .arch directive. */
32179 s_arm_arch (int ignored ATTRIBUTE_UNUSED
)
32181 const struct arm_arch_option_table
*opt
;
32185 name
= input_line_pointer
;
32186 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32187 input_line_pointer
++;
32188 saved_char
= *input_line_pointer
;
32189 *input_line_pointer
= 0;
32191 /* Skip the first "all" entry. */
32192 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32193 if (streq (opt
->name
, name
))
32195 selected_arch
= opt
->value
;
32196 selected_ext
= arm_arch_none
;
32197 selected_cpu
= selected_arch
;
32198 strcpy (selected_cpu_name
, opt
->name
);
32199 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32200 *input_line_pointer
= saved_char
;
32201 demand_empty_rest_of_line ();
32205 as_bad (_("unknown architecture `%s'\n"), name
);
32206 *input_line_pointer
= saved_char
;
32207 ignore_rest_of_line ();
32210 /* Parse a .object_arch directive. */
32213 s_arm_object_arch (int ignored ATTRIBUTE_UNUSED
)
32215 const struct arm_arch_option_table
*opt
;
32219 name
= input_line_pointer
;
32220 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32221 input_line_pointer
++;
32222 saved_char
= *input_line_pointer
;
32223 *input_line_pointer
= 0;
32225 /* Skip the first "all" entry. */
32226 for (opt
= arm_archs
+ 1; opt
->name
!= NULL
; opt
++)
32227 if (streq (opt
->name
, name
))
32229 selected_object_arch
= opt
->value
;
32230 *input_line_pointer
= saved_char
;
32231 demand_empty_rest_of_line ();
32235 as_bad (_("unknown architecture `%s'\n"), name
);
32236 *input_line_pointer
= saved_char
;
32237 ignore_rest_of_line ();
32240 /* Parse a .arch_extension directive. */
32243 s_arm_arch_extension (int ignored ATTRIBUTE_UNUSED
)
32245 const struct arm_option_extension_value_table
*opt
;
32248 int adding_value
= 1;
32250 name
= input_line_pointer
;
32251 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32252 input_line_pointer
++;
32253 saved_char
= *input_line_pointer
;
32254 *input_line_pointer
= 0;
32256 if (strlen (name
) >= 2
32257 && strncmp (name
, "no", 2) == 0)
32263 for (opt
= arm_extensions
; opt
->name
!= NULL
; opt
++)
32264 if (streq (opt
->name
, name
))
32266 int i
, nb_allowed_archs
=
32267 sizeof (opt
->allowed_archs
) / sizeof (opt
->allowed_archs
[i
]);
32268 for (i
= 0; i
< nb_allowed_archs
; i
++)
32271 if (ARM_CPU_IS_ANY (opt
->allowed_archs
[i
]))
32273 if (ARM_FSET_CPU_SUBSET (opt
->allowed_archs
[i
], selected_arch
))
32277 if (i
== nb_allowed_archs
)
32279 as_bad (_("architectural extension `%s' is not allowed for the "
32280 "current base architecture"), name
);
32285 ARM_MERGE_FEATURE_SETS (selected_ext
, selected_ext
,
32288 ARM_CLEAR_FEATURE (selected_ext
, selected_ext
, opt
->clear_value
);
32290 ARM_MERGE_FEATURE_SETS (selected_cpu
, selected_arch
, selected_ext
);
32291 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32292 *input_line_pointer
= saved_char
;
32293 demand_empty_rest_of_line ();
32294 /* Allowing Thumb division instructions for ARMv7 in autodetection rely
32295 on this return so that duplicate extensions (extensions with the
32296 same name as a previous extension in the list) are not considered
32297 for command-line parsing. */
32301 if (opt
->name
== NULL
)
32302 as_bad (_("unknown architecture extension `%s'\n"), name
);
32304 *input_line_pointer
= saved_char
;
32305 ignore_rest_of_line ();
32308 /* Parse a .fpu directive. */
32311 s_arm_fpu (int ignored ATTRIBUTE_UNUSED
)
32313 const struct arm_option_fpu_value_table
*opt
;
32317 name
= input_line_pointer
;
32318 while (*input_line_pointer
&& !ISSPACE (*input_line_pointer
))
32319 input_line_pointer
++;
32320 saved_char
= *input_line_pointer
;
32321 *input_line_pointer
= 0;
32323 for (opt
= arm_fpus
; opt
->name
!= NULL
; opt
++)
32324 if (streq (opt
->name
, name
))
32326 selected_fpu
= opt
->value
;
32327 #ifndef CPU_DEFAULT
32328 if (no_cpu_selected ())
32329 ARM_MERGE_FEATURE_SETS (cpu_variant
, arm_arch_any
, selected_fpu
);
32332 ARM_MERGE_FEATURE_SETS (cpu_variant
, selected_cpu
, selected_fpu
);
32333 *input_line_pointer
= saved_char
;
32334 demand_empty_rest_of_line ();
32338 as_bad (_("unknown floating point format `%s'\n"), name
);
32339 *input_line_pointer
= saved_char
;
32340 ignore_rest_of_line ();
32343 /* Copy symbol information. */
32346 arm_copy_symbol_attributes (symbolS
*dest
, symbolS
*src
)
32348 ARM_GET_FLAG (dest
) = ARM_GET_FLAG (src
);
32352 /* Given a symbolic attribute NAME, return the proper integer value.
32353 Returns -1 if the attribute is not known. */
32356 arm_convert_symbolic_attribute (const char *name
)
32358 static const struct
32363 attribute_table
[] =
32365 /* When you modify this table you should
32366 also modify the list in doc/c-arm.texi. */
32367 #define T(tag) {#tag, tag}
32368 T (Tag_CPU_raw_name
),
32371 T (Tag_CPU_arch_profile
),
32372 T (Tag_ARM_ISA_use
),
32373 T (Tag_THUMB_ISA_use
),
32377 T (Tag_Advanced_SIMD_arch
),
32378 T (Tag_PCS_config
),
32379 T (Tag_ABI_PCS_R9_use
),
32380 T (Tag_ABI_PCS_RW_data
),
32381 T (Tag_ABI_PCS_RO_data
),
32382 T (Tag_ABI_PCS_GOT_use
),
32383 T (Tag_ABI_PCS_wchar_t
),
32384 T (Tag_ABI_FP_rounding
),
32385 T (Tag_ABI_FP_denormal
),
32386 T (Tag_ABI_FP_exceptions
),
32387 T (Tag_ABI_FP_user_exceptions
),
32388 T (Tag_ABI_FP_number_model
),
32389 T (Tag_ABI_align_needed
),
32390 T (Tag_ABI_align8_needed
),
32391 T (Tag_ABI_align_preserved
),
32392 T (Tag_ABI_align8_preserved
),
32393 T (Tag_ABI_enum_size
),
32394 T (Tag_ABI_HardFP_use
),
32395 T (Tag_ABI_VFP_args
),
32396 T (Tag_ABI_WMMX_args
),
32397 T (Tag_ABI_optimization_goals
),
32398 T (Tag_ABI_FP_optimization_goals
),
32399 T (Tag_compatibility
),
32400 T (Tag_CPU_unaligned_access
),
32401 T (Tag_FP_HP_extension
),
32402 T (Tag_VFP_HP_extension
),
32403 T (Tag_ABI_FP_16bit_format
),
32404 T (Tag_MPextension_use
),
32406 T (Tag_nodefaults
),
32407 T (Tag_also_compatible_with
),
32408 T (Tag_conformance
),
32410 T (Tag_Virtualization_use
),
32411 T (Tag_DSP_extension
),
32413 /* We deliberately do not include Tag_MPextension_use_legacy. */
32421 for (i
= 0; i
< ARRAY_SIZE (attribute_table
); i
++)
32422 if (streq (name
, attribute_table
[i
].name
))
32423 return attribute_table
[i
].tag
;
32428 /* Apply sym value for relocations only in the case that they are for
32429 local symbols in the same segment as the fixup and you have the
32430 respective architectural feature for blx and simple switches. */
32433 arm_apply_sym_value (struct fix
* fixP
, segT this_seg
)
32436 && ARM_CPU_HAS_FEATURE (selected_cpu
, arm_ext_v5t
)
32437 /* PR 17444: If the local symbol is in a different section then a reloc
32438 will always be generated for it, so applying the symbol value now
32439 will result in a double offset being stored in the relocation. */
32440 && (S_GET_SEGMENT (fixP
->fx_addsy
) == this_seg
)
32441 && !S_FORCE_RELOC (fixP
->fx_addsy
, TRUE
))
32443 switch (fixP
->fx_r_type
)
32445 case BFD_RELOC_ARM_PCREL_BLX
:
32446 case BFD_RELOC_THUMB_PCREL_BRANCH23
:
32447 if (ARM_IS_FUNC (fixP
->fx_addsy
))
32451 case BFD_RELOC_ARM_PCREL_CALL
:
32452 case BFD_RELOC_THUMB_PCREL_BLX
:
32453 if (THUMB_IS_FUNC (fixP
->fx_addsy
))
32464 #endif /* OBJ_ELF */